[coreboot] HELP: Porting i830 RAM init to 440BX, now it won't compile

Keith Hui buurin at gmail.com
Tue Mar 2 06:39:12 CET 2010

Hi, I need help getting this "patch" to compile.

This is my attempt at porting Joseph Smith's i830 RAM init code to 440BX.
Apply this patch and you have my 440BX part of the code. Which is where all
the trouble is. I changed motherboard target to P2B-F, P3B-F (both of which
which I haven't touched), and my under-development P2B-LS targets and they
all fail.

I need to figure out why romcc won't compile this. I wrote some stubs that I
use to test this code under userspace with dummy SPD dumps from a dozen of
my DIMM modules. I define TESTJIG when I'm compiling raminit.c to use these
stubs for my own userspace testing. gcc is used to compile both my stubs and
raminit.c for those tests and they all compile and seems to run fine. Now I
need to boot test it.

This code needs some expansion for i440bx because it supports a number of
features not present in i830.

Below are output of make when I tried to compile:

ramtest.c:6.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
ramtest.c:56.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
raminit.c:605.46: raminit.c:789.32: romstage.c:96.32:
0xd28680 or         Internal compiler error: non dominated rhs use point
make: *** [/usr/src/coreboot/build/mainboard/asus/p2b-ls/romstage.inc]

The part of raminit.c that croaks is:

            if (value == SPD_MEMORY_TYPE_EDO) {
                edosd |= 0x02;
            } else if (value == SPD_MEMORY_TYPE_SDRAM) {
                edosd |= 0x04;  // <<< ABORT!
                PRINT_DEBUG("SDRAM");   // <<< ABORT!

Let me add another few questions here. I want to add code to have coreboot
talk to the clock chip to find out its FSB in order to select the fastest
memory timing from SPD data. 440BX only has official support for 100MHz, but
they often are taken to 133MHz and beyond - my two boards are tested stable
to 140MHz. I know the clock chip sits on SMBus, and have a fixed address at
0x69. That's with the clock chip my board uses. Where should this code be

The vendor BIOS placed the PIIX4E power management device base port at
0xE400, and its SMBus base port at 0xE800. Coreboot has its SMBus base port
at 0x0F00. If I want to change the base port to match vendor BIOS, where
should it be made?

Any help appreciated.

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20100302/f3dff894/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: bxram.patch
Type: application/octet-stream
Size: 22304 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20100302/f3dff894/attachment.obj>

More information about the coreboot mailing list