[coreboot] [PATCH] ASUS P2B-LS support, RAM detection for 440BX, add Slot 1 CPU, Microcode for Intel Tualatin CPUs
joe at settoplinux.org
Fri Mar 5 13:02:53 CET 2010
On 03/05/2010 12:53 AM, Keith Hui wrote:
> On Thu, Mar 4, 2010 at 8:26 AM, Joseph Smith <joe at settoplinux.org
> <mailto:joe at settoplinux.org>> wrote:
> I would not worry about the microcode updates right now. CAR for
> Intel 6bx is coming real soon and the microcode updates will be
> included :-)
> CAN'T WAIT! :D Then I can say goodbye to the messiness that is romcc, lol.
> **********You are setting alot more than just dra here, I would
> rename this function something like sdram_setup_registers().
> Good point. Eventually I wanted to name it sdram_initalize() just like
> i830, but there are a couple other references to the current names
> elsewhere. One step at a time I guess.
> ************I also noticed you did not use the memory initialize
> each row/side code from the i830. That code is extremely important
> for multiple memory sticks. Besides that everything else looks
> really good, great work!
> There were some code that send RAM commands to the modules in the BX
> code. I just kept them around, thinking that this code in i830 may be
> specific to i830.
The only code that may be specific to the i830 is the DRC regs. Also you
may have to tweek:
dimm_end = pci_read_config8(NORTHBRIDGE, DRB + row);
for the 440bx. This basicly reading the sdram size to set as the start
of the next row.
The rest of the routine (and I have researched it extensively) is pretty
much the standard for sdram initialization.
> Mark, the problem you saw might be MBFS and MBSC not being set properly.
> I have reversed how the factory BIOS programmed them and have the code
> in my working copy. I'll see if that makes a difference. We are still
> hardcoded to CAS3 latency. One step at a time again I guess.
> On another front, with the board running factory BIOS, I dumped the BX's
> config space (lspci -s 0:0:0.0 -xxx) with various DIMM configurations,
> especially with two sticks in DIMM0&1, DIMM2&3, and 3 sticks. These
> three scenarios are where most of the logics are. I can post them if
> anyone wants to look at them. All my RAMs are double sided, one 128MB
> and the others are 256MB.
> To figure out how this gets coded for the 3-slot P2B, Someone would need
> to reverse the vendor bios for that board or do same as above.
FYI, serialice is awesome at dumping raminit routines :-)
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