[coreboot] Supermicro H8QME-2+ mct_d fatal exit.

Knut Kujat knuku at gap.upv.es
Fri Mar 5 17:23:00 CET 2010

Rudolf Marek escribió:
> Hi,
> This is pointing to something which is powered from 5VSB voltage. It
> could be some GPIO settings which sets voltage for ram through some
> other chip. It could be some powersequencing pin connected as GPIO
> too, it could be a i2c bus multiplexer operated by some GPIO pin too ;)
> I would suggest to dump the superio chip with "isadump" (all logical
> devices) and all registers powered from the 5VSB well if known. Check
> for changes on GPIO pins or SuperIO global config.
> Check if the fail is caused by missing SPD EPROMS (error SMBus reads)
> or just by ram itself.
> It could be also something from the SB itself, but try with superio
> first.
> Then compare the dumps with that you obtained from coreboot (you will
> need to program that) You can check from linux with legacy bios, then
> boot with coreboot and then boot with power unplugged.
> Good luck,
> Rudolf

I did a output on status form status = mctRead_SPD(smbaddr, Index); in
mct_d.c and it only spits -1 out while on the working coreboot machine
it gives me several numbers until index = 64 on those dimms where ram is
installed. Is this a possible SPD EPROMS missing error you pointed out?
What would be my next steps if so?

Thanks for your effort,
Knut Kujat.

More information about the coreboot mailing list