[coreboot] [PATCH] ASUS P2B-LS support, RAM detection for 440BX, add Slot 1 CPU, Microcode for Intel Tualatin CPUs

Uwe Hermann uwe at hermann-uwe.de
Sat Mar 6 19:28:25 CET 2010


I think I reviewed and committed most of the stuff now, except for the
microcode updates, IIRC there will be some bigger patch handling those
in the near future anyway.

See some more notes below.

On Tue, Mar 02, 2010 at 11:19:24PM -0500, Keith Hui wrote:
> - Adds Asus P2B-LS mainboard

Merged with some small cosmetic changes, thanks.

> - Adds RAM detection for i440bx (based on i82830 code). We're no longer hard
> coded for 64MB on one row!

Very nice! I did various smaller changes here, should be functionally
equivalent mostly though, except for these:

 - In i440bx.h: I dropped the generic PCI register definitions, those
   are not 440BX specific and already defined in pci_def.h.

 - Dropped MLT / PCI_LATENCY_TIMER for now, should not be needed, and
   raminit.c is probably the wrong place for this stuff anyway, I guess.

 - Not sure about this change, omitted it for now (need to re-check

  static const uint32_t refresh_rate_map[] = {
  -       1, 5, 5, 2, 3, 4
  +       1, 1, 1, 2, 3, 4

Probably also some more stuff I forgot about. One thing I'd like to do
next is to factor out some stuff from set_dram_row_attributes(), that's
way too long and too nested for my taste.

> - Adds a proper Slot 1 cpu under src/cpu/intel/slot_1. It's a stub copied
> from slot_2 but addresses a few FIXMEs. My P2B-LS code refers to this.

Yep, thanks! I'll fixup the other slot 1 boards in a few minutes or so.

> - Adds microcode for Intel Tualatin CPUs, cpuid 6B1 and 6B4.* Actually
> loading them is pending.

Postponed for now, see above.

Will test the code on a few 440BX boards soonish, and fix the 3 vs. 4
DIMM slots issue.

Thanks, Uwe.
http://www.hermann-uwe.de  | http://www.randomprojects.org
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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