[coreboot] Fwd: Getting started with Coreboot on Intel Core
kh.nirschl at googlemail.com
Mon Mar 8 21:47:16 CET 2010
forward this to coreboot list too.
---------- Forwarded message ----------
From: Karl-Heinz Nirschl <kh.nirschl at googlemail.com>
Subject: Re: [coreboot] Getting started with Coreboot on Intel Core
To: Stefan Reinauer <stepan at coresystems.de>
thanks for your reply. i thought
src/northbridge/intel/i945/early_init.c is executed after stage1_main
somewhere in real main. i've put a lot of postcodes bevor that
- one in front of stage1_main and and one in real_main. shouldn't i see these?
in my understanding execution takes the following way:
1 some generic x86 startup assembler
3 cache_as_ram_disable.inc (stage1_main)
4 romstage.c (real_main) in mainboard dir
isn't that right? it looks like i hang between 2 und 3.
i'll go and check the toolschain in utils.
2010/3/8 Stefan Reinauer <stepan at coresystems.de>:
> On 3/8/10 6:36 PM, Karl-Heinz Nirschl wrote:
>> i should append:
>> this is using a spi flash with 2 Megs and todays svn version.
>> i also tried with a 1 meg fhw with a somewhat earlier version of
>> coreboot. same problem.
>> 2010/3/8 Karl-Heinz Nirschl <kh.nirschl at googlemail.com>:
>>> Hi there,
>>> i'm new to coreboot and trying to port coreboot to a intel core based
>>> board. it's a u2500 with a ich7m and 945gm.
>>> i started with kontron 986lcd-m which should be quite similar but
>>> didn't have much success so far.
> Did you adapt the code for your SuperIO chip? Do you get any messages on
> the serial port?
>>> the board hangs with post code 0x23 (pci post card) which is bevor
>>> "call stage1_main" in model_6ex/cache_as_ram.inc.
>>> as this is very early and the cpu never seem to come to stage1_main
>>> (in cache_as_ram_disable.c) i assume i have a problem with my
> Try this one:
> Index: src/northbridge/intel/i945/early_init.c
> --- src/northbridge/intel/i945/early_init.c (revision 5196)
> +++ src/northbridge/intel/i945/early_init.c (working copy)
> @@ -867,7 +867,7 @@
> /* Change port80 to LPC */
> - RCBA32(GCS) &= (~0x04);
> + //RCBA32(GCS) &= (~0x04);
> /* Just do it that way */
> RCBA32(0x2010) |= (1 << 10);
> Then post codes keep going to PCI instead of LPC and you should see
> where it's going.
>>> I build on ubuntu 8.04 (Hardy Heron) with nothing special.
>>> Any hints for a coreboot newbie? Which additional information could i
>>> provide to find the problem?
> You should use the reference toolchain in util/crossgcc
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