[coreboot] src/lib/ramtest.c

Myles Watson mylesgw at gmail.com
Mon Mar 15 23:31:23 CET 2010

> >>> On my target gcc complains about undefined CONFIG_SSE2 macro and
> defaults
> >>> it to 0, maybe attached patch should quiet gcc a bit?
> >>>
> >> I think the preferred way to quiet this warning would be to define SSE2
> >> correctly in src/cpu/VENDOR/CPU/Kconfig.  The next best would be to set
> SSE2
> >> to default to n in src/cpu/Kconfig.
> >
> > I have such warning for P2, i checked and no my p2 cpus have SSE2, but i
> am not going to patch
> > src/cpu/ just because i don't understand what impact it might have.
Then silencing the warning is probably not a good idea :)  You can grep for
CONFIG_SSE2 to see where the variable is checked.  The idea is that you can
speed up execution if you have SSE2 instructions available, but we don't
want to break things for those that don't have them.  The warning is there
to suggest that you put in the correct value.

> > I understand that this patch should not be needed, but then, maybe add
> before #define in patch
> > to #warning "cpu don't define CONFIG_SSE2, fix it if you can" or
> something similar?
> >
> Yes I agree p2's do not support SSE2, so one would think you would not
> even get this warning.....
You get the warning because no one has told Coreboot that p2s don't have
SSE2.  That should be done in the Kconfig file for the processor.


More information about the coreboot mailing list