From marcj303 at gmail.com Sat May 1 00:15:56 2010 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 30 Apr 2010 16:15:56 -0600 Subject: [coreboot] run away pci scan Message-ID: I'm working with amd/mahogany_fam10 mainboard and having problems in ramstage. It is going through pci device scanning when it starts finding the same devices again and malloc memory until it dies. It also looks like it never goes down a bridge, always staying on bus0. The problem starts at CPU: APIC: 03, it starts scanning bus0 again. Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources ... normal device init happens..... CPU: APIC: 00 enabled malloc Enter, size 1092, free_mem_ptr 00270000 malloc 00270000 CPU: APIC: 01 enabled malloc Enter, size 1092, free_mem_ptr 00270444 malloc 00270444 CPU: APIC: 02 enabled malloc Enter, size 1092, free_mem_ptr 00270888 malloc 00270888 CPU: APIC: 03 enabled PCI_DOMAIN: 0000 scanning... Anyone have thoughts on what is happening here? Attached complete serial log. Thanks! Marc -- http://se-eng.com From mylesgw at gmail.com Sat May 1 00:21:52 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 30 Apr 2010 16:21:52 -0600 Subject: [coreboot] run away pci scan In-Reply-To: References: Message-ID: > I'm working with amd/mahogany_fam10 mainboard and having problems in > ramstage. It is going through pci device scanning when it starts > finding the same devices again and malloc memory until it dies. It > also looks like it never goes down a bridge, always staying on bus0. > The problem starts at CPU: APIC: 03, it starts scanning bus0 again. > > Anyone have thoughts on what is happening here? Have you tried increasing the stack size? That's been a problem in the past with this type of failure. > Attached complete serial > log. I didn't get it. Thanks, Myles From njacobs8 at hetnet.nl Sat May 1 01:34:50 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sat, 1 May 2010 01:34:50 +0200 Subject: [coreboot] Warnings Message-ID: <201005010134.50557.njacobs8@hetnet.nl> Hi Stefan, First of all thanks for the great improvements in Geode (GX2). On 4/30/10 7:50 PM, Stefan Reinauer wrote: > src/northbridge/amd/gx2/chipsetinit.c:271: warning: suggest > parentheses around '-' inside '<<' > This would need help from someone with a GX2 (or willing to check out the data sheets ;-) I would be happy if i could be of any help with this, I have a GX2 board i can test on. I saw your discussion about the warning before and it inspired me to dedicate my spare free time to again update my working rev5446 patches to current trunk. But unfortunately i can`t get it to work anymore on rev5120 and some other rev`s i tried. (Linux errors out with: "hda: lost interrupt") I will send the details in a separate mail. Thanks,Nils From joe at settoplinux.org Sat May 1 02:04:12 2010 From: joe at settoplinux.org (Joseph Smith) Date: Fri, 30 Apr 2010 20:04:12 -0400 Subject: [coreboot] Warnings In-Reply-To: <201005010134.50557.njacobs8@hetnet.nl> References: <201005010134.50557.njacobs8@hetnet.nl> Message-ID: <4BDB6FFC.4040307@settoplinux.org> On 04/30/2010 07:34 PM, Nils wrote: > Hi Stefan, > First of all thanks for the great improvements in Geode (GX2). > > On 4/30/10 7:50 PM, Stefan Reinauer wrote: >> src/northbridge/amd/gx2/chipsetinit.c:271: warning: suggest >> parentheses around '-' inside '<<' >> > This would need help from someone with a GX2 (or willing to check out > the data sheets ;-) > > I would be happy if i could be of any help with this, I have a GX2 board i can > test on. > > I saw your discussion about the warning before and it inspired me to dedicate > my spare free time to again update my working rev5446 patches to current > trunk. > But unfortunately i can`t get it to work anymore on rev5120 and some other > rev`s i tried. > (Linux errors out with: "hda: lost interrupt") > I will send the details in a separate mail. > > Thanks,Nils > I have a GX2 also (AMD PIC) that is not supported by coreboot yet, but could test if needed. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From marcj303 at gmail.com Sat May 1 02:13:23 2010 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 30 Apr 2010 18:13:23 -0600 Subject: [coreboot] run away pci scan In-Reply-To: References: Message-ID: On Fri, Apr 30, 2010 at 4:21 PM, Myles Watson wrote: >> Anyone have ?thoughts on what is happening here? > Have you tried increasing the stack size? ?That's been a problem in the past > with this type of failure. Thanks, I tried increasing the stack size from 0x8000 to 0x10000, but that didn't seem to help. -- http://se-eng.com From njacobs8 at hetnet.nl Sat May 1 01:58:33 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sat, 1 May 2010 01:58:33 +0200 Subject: [coreboot] GX2 problems Message-ID: <201005010158.34049.njacobs8@hetnet.nl> Hi all, Attached patches add the Wyse S50 thin client to Coreboot. I have rev5446 and some older rev`s working here with different hacks but rev5484 and 5520 (and some i tested in between) are not working anymore. Linux gives the following error: "hda: lost interrupt" . Attached also the bootlogs from rev5446 and rev5520. Could somebody give me a hint (or even better a patch) i can try? Although the patches are probably not ready for inclusion: Signed-off-by: Nils Jacobs Thanks,Nils. -------------- next part -------------- A non-text attachment was scrubbed... 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Name: coreboot133.log Type: text/x-log Size: 36743 bytes Desc: not available URL: From eswierk at aristanetworks.com Sat May 1 01:46:01 2010 From: eswierk at aristanetworks.com (Ed Swierk) Date: Fri, 30 Apr 2010 16:46:01 -0700 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> Message-ID: On Wed, Apr 28, 2010 at 6:26 AM, Myles Watson wrote: > Have you tried changing it to pci_locate_device_on_bus()? ?That will > constrain the search to a single bus. That doesn't help; config space accesses to the PCIe bridge devices themselves are hanging. I worked around the problem by replacing pci_locate_device() with hardcoded PCI_DEV values, which should be okay for this chipset as long as the northbridge and southbridge are always at the normal addresses. I managed to set up SerialICE on my board and get a few thousand lines of tracing from the factory BIOS. I notice that it doesn't touch those PCIe bridge devices at all early on. Is it possible that some HyperTransport magic needs to happen to get them to behave? > I think there must be some MTRR setup problem. ?Maybe you could print out > the MTRRs just before the slow parts? Here's a dump of various MSRs right after the call to raminit_amdmct() in romstage.c: /* variable MTRRs */ msr 00000200=0000000000000000 msr 00000201=0000000000000000 msr 00000202=00000000fff00006 msr 00000203=0000fffffff80800 msr 00000204=0000000000000006 msr 00000205=0000ffff80000800 msr 00000206=0000000080000006 msr 00000207=0000ffffc0000800 msr 00000208=00000000c0000006 msr 00000209=0000ffffe0000800 msr 0000020a=0000000000000000 msr 0000020b=0000000000000000 msr 0000020c=0000000000000000 msr 0000020d=0000000000000000 msr 0000020e=0000000000000000 msr 0000020f=0000000000000000 /* fixed MTRRs */ msr 00000250=1e1e1e1e1e1e1e1e msr 00000258=1e1e1e1e1e1e1e1e msr 00000259=0000000000000000 msr 00000268=1e1e1e1e00000000 msr 00000269=1e1e1e1e1e1e1e1e msr 0000026a=0000000000000000 msr 0000026b=0000000000000000 msr 0000026c=0404040404040404 msr 0000026d=0404040404040404 msr 0000026e=0404040404040404 msr 0000026f=0404040404040404 /* variable & fixed MTRRs enabled */ msr 000002ff=0000000000000c00 /* IORRs */ msr c0010016=0000000080210000 msr c0010017=0000000000000000 msr c0010018=0000000000000000 msr c0010019=0000000000000000 /* top of memory registers */ msr c001001a=00000000e0000000 msr c001001d=0000000120000000 Another experiment I tried was to replace memset() with the original assembler version of clear_memory(). With this change, the "Clearing initial memory region:" step takes a fraction of a second vs. minutes with memset(). Then things grind to a halt after "Stage: loading fallback/coreboot_ram @ ...". --Ed From buurin at gmail.com Sat May 1 04:07:11 2010 From: buurin at gmail.com (Keith Hui) Date: Fri, 30 Apr 2010 22:07:11 -0400 Subject: [coreboot] r5511 broke my compile Message-ID: > On 4/30/10 6:25 AM, Keith Hui wrote: >> $ ?make >> ? ? GEN ? ? ? ?build.h >> ? ? ROMCC ? ? ?romstage.inc >> ? ? GEN ? ? ? ?crt0.S >> ? ? CC ? ? ? ? mainboard/asus/p2b-ls/crt0.s >> ? ? CC ? ? ? ? mainboard/asus/p2b-ls/crt0.initobj.o >> ? ? LINK ? ? ? coreboot >> ? ? OBJCOPY ? ?coreboot.bootblock >> make: *** No rule to make target `src/arch/i386/include/arch/asm.h', >> needed by `build/arch/i386/lib/c_start.o'. ?Stop. >> >> > > The define ASSEMBLY is now passed by the Makefile for assembler files. > > Hence the asm.h construct is no longer needed. > > Just drop asm.h includes from your code. If you use the post_code() > macro, you can now #include instead. I solved the issue by a 'make clean'. Thanks. From mylesgw at gmail.com Sat May 1 05:49:06 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 30 Apr 2010 21:49:06 -0600 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> Message-ID: <69AAB0E5F104464AB8263E823BC37789@chimp> > On Wed, Apr 28, 2010 at 6:26 AM, Myles Watson wrote: > > Have you tried changing it to pci_locate_device_on_bus()? ?That will > > constrain the search to a single bus. > > That doesn't help; config space accesses to the PCIe bridge devices > themselves are hanging. > > I worked around the problem by replacing pci_locate_device() with > hardcoded PCI_DEV values, which should be okay for this chipset as > long as the northbridge and southbridge are always at the normal > addresses. > > I managed to set up SerialICE on my board and get a few thousand lines > of tracing from the factory BIOS. I notice that it doesn't touch those > PCIe bridge devices at all early on. Is it possible that some > HyperTransport magic needs to happen to get them to behave? I don't know. It's surprising to hang. > > I think there must be some MTRR setup problem. ?Maybe you could print > out > > the MTRRs just before the slow parts? > > Here's a dump of various MSRs right after the call to raminit_amdmct() > in romstage.c: > > /* variable MTRRs */ > msr 00000200=0000000000000000 > msr 00000201=0000000000000000 > msr 00000202=00000000fff00006 > msr 00000203=0000fffffff80800 This looks wrong to me. I'm not an expert, but Since 202 is the base, and 203 is the mask, It looks like the area from 0xfff00000 - 0xfff7ffff is cached. I would think the correct setting would be: > msr 00000202=00000000fff00006 > msr 00000203=0000fffffff00800 To cache the last MB of mem. > msr 00000204=0000000000000006 > msr 00000205=0000ffff80000800 Then this one caches 0 - 2GB > msr 00000206=0000000080000006 > msr 00000207=0000ffffc0000800 This one caches 2GB-3GB > msr 00000208=00000000c0000006 > msr 00000209=0000ffffe0000800 This one caches 3GB-3.5GB Something to keep in mind is that caching should be disabled then enabled when setting the var MTRRs. Since you don't want to disable caches when you're using cache-as-RAM, I think it's best to make sure that the MTRRs are set correctly from the beginning and not touch them again until you've copied the RAM stage to the RAM and moved your stack. > msr 0000020a=0000000000000000 > msr 0000020b=0000000000000000 > msr 0000020c=0000000000000000 > msr 0000020d=0000000000000000 > msr 0000020e=0000000000000000 > msr 0000020f=0000000000000000 > > /* fixed MTRRs */ > msr 00000250=1e1e1e1e1e1e1e1e > msr 00000258=1e1e1e1e1e1e1e1e > msr 00000259=0000000000000000 > msr 00000268=1e1e1e1e00000000 > msr 00000269=1e1e1e1e1e1e1e1e > msr 0000026a=0000000000000000 > msr 0000026b=0000000000000000 > msr 0000026c=0404040404040404 > msr 0000026d=0404040404040404 > msr 0000026e=0404040404040404 > msr 0000026f=0404040404040404 > > /* variable & fixed MTRRs enabled */ > msr 000002ff=0000000000000c00 > > /* IORRs */ > msr c0010016=0000000080210000 > msr c0010017=0000000000000000 > msr c0010018=0000000000000000 > msr c0010019=0000000000000000 > > /* top of memory registers */ > msr c001001a=00000000e0000000 > msr c001001d=0000000120000000 > > Another experiment I tried was to replace memset() with the original > assembler version of clear_memory(). With this change, the "Clearing > initial memory region:" step takes a fraction of a second vs. minutes > with memset(). Then things grind to a halt after "Stage: loading > fallback/coreboot_ram @ ...". My theory is that since clear_memory was a single rep instruction, the fact that it wasn't being cached wasn't a big deal. With the caches set correctly, memset was faster on my board. Good luck, Myles From joe at settoplinux.org Sat May 1 07:26:55 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 01 May 2010 01:26:55 -0400 Subject: [coreboot] computers with Coreboot BIOS In-Reply-To: <645097.46582.qm@web36804.mail.mud.yahoo.com> References: <645097.46582.qm@web36804.mail.mud.yahoo.com> Message-ID: <5db6c6ba597665d05b723677abbed203@imap.1and1.com> On Fri, 30 Apr 2010 04:36:36 -0700 (PDT), Peter Link wrote: > Recently I inquired with Inatux Computers, which sells pre-installed > systems that include gNewSense and Trisquel, among others, about plans for > offering > coreboot BIOS as an option. > > After a few emails back and forth, they quickly added some information on > their website on the following page: http://inatux.com/?gnu > > (text is below) > <<<< > Free BIOS (Coreboot, etc.): > --------------------------- > Our > computers are not yet available with a Free BIOS, but we are very > interested in offering that option in the future. We can build systems > with Coreboot as the BIOS, but there will be some limitations as to > certain video cards (ATI for 3D), processors, motherboards, memory, > WiFi, and other areas as well. Please write us if you are interested. Yes that is good news Pete. I don't really get the part about "limitations" though, why would those items have "limitations"? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From patrick at georgi-clan.de Sat May 1 08:09:41 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 01 May 2010 08:09:41 +0200 Subject: [coreboot] run away pci scan In-Reply-To: References: Message-ID: <1272694181.1491.2.camel@tetris> Am Freitag, den 30.04.2010, 16:15 -0600 schrieb Marc Jones: > I'm working with amd/mahogany_fam10 mainboard and having problems in > ramstage. It is going through pci device scanning when it starts > finding the same devices again and malloc memory until it dies. It > also looks like it never goes down a bridge, always staying on bus0. > The problem starts at CPU: APIC: 03, it starts scanning bus0 again. We had that case happen when a bridge had a secondary bus ID of 0. coreboot then enters the bridge, and starts again with the root bus. This could also happen with other bus ids, but I guess 0 is the most obvious contender for misbehaviour. Patrick From bari at onelabs.com Sat May 1 16:12:44 2010 From: bari at onelabs.com (bari) Date: Sat, 01 May 2010 09:12:44 -0500 Subject: [coreboot] computers with Coreboot BIOS In-Reply-To: <5db6c6ba597665d05b723677abbed203@imap.1and1.com> References: <645097.46582.qm@web36804.mail.mud.yahoo.com> <5db6c6ba597665d05b723677abbed203@imap.1and1.com> Message-ID: <4BDC36DC.1070700@onelabs.com> Joseph Smith wrote: >> <<<< >> Free BIOS (Coreboot, etc.): >> --------------------------- >> Our >> computers are not yet available with a Free BIOS, but we are very >> interested in offering that option in the future. We can build systems >> with Coreboot as the BIOS, but there will be some limitations as to >> certain video cards (ATI for 3D), processors, motherboards, memory, >> WiFi, and other areas as well. Please write us if you are interested. > > Yes that is good news Pete. > I don't really get the part about "limitations" though, why would those > items have "limitations"? > They probably meant that since there are no modern Intel chipsets or CPU's currently supported by coreboot that this will be limited to AMD only. Plus AMD DDR3 support is only ~1 week old. -Bari From rminnich at gmail.com Sat May 1 17:51:35 2010 From: rminnich at gmail.com (ron minnich) Date: Sat, 1 May 2010 15:51:35 +0000 Subject: [coreboot] run away pci scan In-Reply-To: <1272694181.1491.2.camel@tetris> References: <1272694181.1491.2.camel@tetris> Message-ID: On Sat, May 1, 2010 at 6:09 AM, Patrick Georgi wrote: > We had that case happen when a bridge had a secondary bus ID of 0. > coreboot then enters the bridge, and starts again with the root bus. > > This could also happen with other bus ids, but I guess 0 is the most > obvious contender for misbehaviour. I saw that too once but can not remember the fix save printing "this bridge is broken" and refusing to proceed. ron From anders at jenbo.dk Sat May 1 17:57:28 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Sat, 01 May 2010 17:57:28 +0200 Subject: [coreboot] =?utf-8?q?Indtast_Bcc__computers_with_Coreboot_BIOS?= Message-ID: What about the video card limits? Mvh Anders ----- Reply message ----- Fra: "bari" Dato: l?r., maj 1, 2010 16:12 Emne: [coreboot] computers with Coreboot BIOS Til: "Joseph Smith" Cc: , "Peter Link" Joseph Smith wrote: >> <<<< >> Free BIOS (Coreboot, etc.): >> --------------------------- >> Our >> computers are not yet available with a Free BIOS, but we are very >> interested in offering that option in the future. We can build systems >> with Coreboot as the BIOS, but there will be some limitations as to >> certain video cards (ATI for 3D), processors, motherboards, memory, >> WiFi, and other areas as well. Please write us if you are interested. > > Yes that is good news Pete. > I don't really get the part about "limitations" though, why would those > items have "limitations"? > They probably meant that since there are no modern Intel chipsets or CPU's currently supported by coreboot that this will be limited to AMD only. Plus AMD DDR3 support is only ~1 week old. -Bari -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From rminnich at gmail.com Sat May 1 18:05:41 2010 From: rminnich at gmail.com (ron minnich) Date: Sat, 1 May 2010 16:05:41 +0000 Subject: [coreboot] Indtast Bcc computers with Coreboot BIOS In-Reply-To: <4bdc4f7d.0837560a.4886.ffffc293SMTPIN_ADDED@mx.google.com> References: <4bdc4f7d.0837560a.4886.ffffc293SMTPIN_ADDED@mx.google.com> Message-ID: For really practical use of coreboot the mainboards need to come loaded and supported from the vendor. That's what I've been pushing on for the last few years. And vendors are starting to listen -- not because of me, I suspect, but because of their other customers. There are Tier 1 vendors out there talking and others are now telling me they can give me systems with coreboot already on them and that they have coreboot capable people on staff. This is a huge change. None too soon: ARMs are becoming a key part of the server systems available this year and they already have a free bios -- U-boot -- which is one important advantage over x86 systems for many customers. At some point the x86 universe will wake up and realize it has a new competitor, one that is just a bit more open in many ways. Not surprisingly the "EFI for ARM" concept has not gotten very far; I think people want to know what's running on their machines. ron From kevin at koconnor.net Sat May 1 19:23:22 2010 From: kevin at koconnor.net (Kevin O'Connor) Date: Sat, 1 May 2010 13:23:22 -0400 Subject: [coreboot] Linux booting hangs when booted by FILO In-Reply-To: References: Message-ID: <20100501172322.GA9900@morn.localdomain> On Fri, Apr 30, 2010 at 03:34:43AM +0100, limp wrote: > I have loaded coreboot with FILO on a Kontron 986LCD-M board and when I am > trying to boot Linux from FILO, it freezes at the "Jumping to entry > point..." bit. Out of curiosity, does SeaBIOS work? -Kevin From joe at settoplinux.org Sat May 1 20:58:57 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 01 May 2010 14:58:57 -0400 Subject: [coreboot] computers with Coreboot BIOS In-Reply-To: <4BDC36DC.1070700@onelabs.com> References: <645097.46582.qm@web36804.mail.mud.yahoo.com> <5db6c6ba597665d05b723677abbed203@imap.1and1.com> <4BDC36DC.1070700@onelabs.com> Message-ID: <4BDC79F1.4040705@settoplinux.org> On 05/01/2010 10:12 AM, bari wrote: > Joseph Smith wrote: > >>> <<<< >>> Free BIOS (Coreboot, etc.): --------------------------- >>> Our >>> computers are not yet available with a Free BIOS, but we are very >>> interested in offering that option in the future. We can build systems >>> with Coreboot as the BIOS, but there will be some limitations as to >>> certain video cards (ATI for 3D), processors, motherboards, memory, >>> WiFi, and other areas as well. Please write us if you are interested. >> >> Yes that is good news Pete. I don't really get the part about >> "limitations" though, why would those >> items have "limitations"? >> > They probably meant that since there are no modern Intel chipsets or > CPU's currently supported by coreboot that this will be limited to AMD > only. Plus AMD DDR3 support is only ~1 week old. > Yeah, your probably right. But the way it is worded implies major limitations. I would think if a vendor was going to offer coreboot as an alternative solution, they would spend some time developing coreboot to work 100% on their product. Anyways it is a good start to see coreboot offered as an alternative. Maybe other PC vendors will catch on :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From joe at settoplinux.org Sat May 1 21:34:19 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 01 May 2010 15:34:19 -0400 Subject: [coreboot] GX2 problems In-Reply-To: <201005010158.34049.njacobs8@hetnet.nl> References: <201005010158.34049.njacobs8@hetnet.nl> Message-ID: <4BDC823B.3090703@settoplinux.org> On 04/30/2010 07:58 PM, Nils wrote: > Hi all, > Attached patches add the Wyse S50 thin client to Coreboot. > I have rev5446 and some older rev`s working here with different hacks but > rev5484 and 5520 (and some i tested in between) are not working anymore. > > Linux gives the following error: "hda: lost interrupt" . > Attached also the bootlogs from rev5446 and rev5520. > > Could somebody give me a hint (or even better a patch) i can try? > > Although the patches are probably not ready for inclusion: > > Signed-off-by: Nils Jacobs > Hey Nils, I just acquired as S30, which is the same as the S50 but less onboard flash/memory :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From anders at jenbo.dk Sat May 1 21:36:12 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sat, 01 May 2010 21:36:12 +0200 Subject: [coreboot] computers with Coreboot BIOS In-Reply-To: <4BDC79F1.4040705@settoplinux.org> References: <645097.46582.qm@web36804.mail.mud.yahoo.com> <5db6c6ba597665d05b723677abbed203@imap.1and1.com> <4BDC36DC.1070700@onelabs.com> <4BDC79F1.4040705@settoplinux.org> Message-ID: <1272742572.2089.1.camel@anders-laptop> I think that it sounds more like that they are offering it early at request untill thy (or otheres) gets it to work 100% and at that point they will just ship with it. -Anders l?r, 01 05 2010 kl. 14:58 -0400, skrev Joseph Smith: > On 05/01/2010 10:12 AM, bari wrote: > > Joseph Smith wrote: > > > >>> <<<< > >>> Free BIOS (Coreboot, etc.): --------------------------- > >>> Our > >>> computers are not yet available with a Free BIOS, but we are very > >>> interested in offering that option in the future. We can build systems > >>> with Coreboot as the BIOS, but there will be some limitations as to > >>> certain video cards (ATI for 3D), processors, motherboards, memory, > >>> WiFi, and other areas as well. Please write us if you are interested. > >> > >> Yes that is good news Pete. I don't really get the part about > >> "limitations" though, why would those > >> items have "limitations"? > >> > > They probably meant that since there are no modern Intel chipsets or > > CPU's currently supported by coreboot that this will be limited to AMD > > only. Plus AMD DDR3 support is only ~1 week old. > > > Yeah, your probably right. But the way it is worded implies major > limitations. I would think if a vendor was going to offer coreboot as an > alternative solution, they would spend some time developing coreboot to > work 100% on their product. > > Anyways it is a good start to see coreboot offered as an alternative. > Maybe other PC vendors will catch on :-) > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > From njacobs8 at hetnet.nl Sat May 1 22:18:41 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sat, 1 May 2010 22:18:41 +0200 Subject: [coreboot] GX2 problems In-Reply-To: <4BDC823B.3090703@settoplinux.org> References: <201005010158.34049.njacobs8@hetnet.nl> <4BDC823B.3090703@settoplinux.org> Message-ID: <201005012218.41994.njacobs8@hetnet.nl> Hi Joseph, Op zaterdag 1 mei 2010 21:34:19 schreef u: > Hey Nils, > I just acquired as S30, which is the same as the S50 but less onboard > flash/memory :-) Very nice! The more people working on it the better. I hope the GX2 tree is working again soon. P.s. i forgot to mention there is another problem that i always had: Stage:loading fallback/coreboot_ram takes very long to load .(~35seconds) Thanks,Nils. From joe at settoplinux.org Sat May 1 23:49:12 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 01 May 2010 17:49:12 -0400 Subject: [coreboot] GX2 problems In-Reply-To: <201005012218.41994.njacobs8@hetnet.nl> References: <201005010158.34049.njacobs8@hetnet.nl> <4BDC823B.3090703@settoplinux.org> <201005012218.41994.njacobs8@hetnet.nl> Message-ID: <4BDCA1D8.4040106@settoplinux.org> On 05/01/2010 04:18 PM, Nils wrote: > Hi Joseph, > > Op zaterdag 1 mei 2010 21:34:19 schreef u: >> Hey Nils, >> I just acquired as S30, which is the same as the S50 but less onboard >> flash/memory :-) > > Very nice! > The more people working on it the better. > I hope the GX2 tree is working again soon. > > P.s. i forgot to mention there is another problem that i always had: > Stage:loading fallback/coreboot_ram takes very long to load .(~35seconds) > > Thanks,Nils. > Quick question, is the onboard flash detected as IDE device or as MTD device? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From njacobs8 at hetnet.nl Sun May 2 00:30:56 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sun, 2 May 2010 00:30:56 +0200 Subject: [coreboot] GX2 problems In-Reply-To: <4BDCA1D8.4040106@settoplinux.org> References: <201005010158.34049.njacobs8@hetnet.nl> <201005012218.41994.njacobs8@hetnet.nl> <4BDCA1D8.4040106@settoplinux.org> Message-ID: <201005020030.56903.njacobs8@hetnet.nl> Hi Joseph, Op zaterdag 1 mei 2010 23:49:12 schreef u: > Quick question, is the onboard flash detected as IDE device or as MTD > device? > The standard BIOS is configured for Flash not IDE. I didn`t use the flash yet. I have a 2,5` laptop hdd attached to it on the intern power supply and that works ok. After long experimenting i found a kernel config that seems to work only on kernel 2.6.24 and enables the hdd on the flash interface. Probably a bug in 2.6.24. I use that kernel for flashing. If you need that give me a pm. Greetings,Nils. From phcoder at gmail.com Sun May 2 15:39:55 2010 From: phcoder at gmail.com (=?UTF-8?B?VmxhZGltaXIgJ8+GLWNvZGVyL3BoY29kZXInIFNlcmJpbmVua28=?=) Date: Sun, 02 May 2010 15:39:55 +0200 Subject: [coreboot] FreeBSD Coreboot support Message-ID: <4BDD80AB.1020105@gmail.com> Hello, I was playing with loading FreeBSD using grub2 as bootloader and have met following problems: 1) FreeBSD-i386 makes BIOS calls. On coreboot they cause a crash. I propose to restructure machdep.c to call int12 only if no smap is supplied. Patch attached. Abandon keyboard rate retrieving from BIOS in sys/dev/atkbdc/atkbd.c. Or move this code to bootloader and pass the rate in environment. I'll do the patch when we decide on approach to use. sys/i386/cpufreq/smist.c is unusable and would cause panic. sys/i386/isa/vesa.c usability depends on VGA BIOS. For the last 2 cases and the future I propose to have a flag like hw.no_bios=1 and hw.no_video_bios=1 which would make vm86_intcall and vm86_datacall return an error on intnum!=0x10 / intnum=0x10. Alternatively it's possible to catch the exception in vm8086 mode and return an error instead of panic. 2) The range 0-0x1000 isn't usable on coreboot since it contains coreboot tables which according to an IRC chat I had with devs shouldn't be overwritten. It causes an early hang on i386 or a following panic on amd64: if (basemem == 0) panic("BIOS smap did not include a basemem segment!"); Can FreeBSD avoid using these memory chunks if they are not available? 3) On amd64 if no ACPI tables are present and using serial console userspace is able to write only 16 bytes to console. Kernel messages have no such problem. I'm confused -- Regards Vladimir '?-coder/phcoder' Serbinenko -------------- next part -------------- A non-text attachment was scrubbed... Name: machdep.diff Type: text/x-diff Size: 5912 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 293 bytes Desc: OpenPGP digital signature URL: From phcoder at gmail.com Sun May 2 17:00:29 2010 From: phcoder at gmail.com (=?UTF-8?B?VmxhZGltaXIgJ8+GLWNvZGVyL3BoY29kZXInIFNlcmJpbmVua28=?=) Date: Sun, 02 May 2010 17:00:29 +0200 Subject: [coreboot] [PATCH] Fix coreboot qemu RAM size detection Message-ID: <4BDD938D.6020105@gmail.com> Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM. Fix attached. Tested from 16 MiB to 2047 MiB -- Regards Vladimir '?-coder/phcoder' Serbinenko -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot_qemu_ram.diff Type: text/x-diff Size: 2044 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 293 bytes Desc: OpenPGP digital signature URL: From stepan at coresystems.de Sun May 2 17:51:46 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 02 May 2010 17:51:46 +0200 Subject: [coreboot] [PATCH] Fix coreboot qemu RAM size detection In-Reply-To: <4BDD938D.6020105@gmail.com> References: <4BDD938D.6020105@gmail.com> Message-ID: <4BDD9F92.1050201@coresystems.de> On 5/2/10 5:00 PM, Vladimir '?-coder/phcoder' Serbinenko wrote: > Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM. > Fix attached. Tested from 16 MiB to 2047 MiB > > Hi Vladimir, please sign off your patch so we can commit it: http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure Thanks, Stefan -------------- next part -------------- An HTML attachment was scrubbed... URL: From phcoder at gmail.com Sun May 2 18:23:17 2010 From: phcoder at gmail.com (=?UTF-8?B?VmxhZGltaXIgJ8+GLWNvZGVyL3BoY29kZXInIFNlcmJpbmVua28=?=) Date: Sun, 02 May 2010 18:23:17 +0200 Subject: [coreboot] [PATCH] Fix coreboot qemu RAM size detection In-Reply-To: <4BDD9F92.1050201@coresystems.de> References: <4BDD938D.6020105@gmail.com> <4BDD9F92.1050201@coresystems.de> Message-ID: <4BDDA6F5.8010307@gmail.com> Stefan Reinauer wrote: > On 5/2/10 5:00 PM, Vladimir '?-coder/phcoder' Serbinenko wrote: >> Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM. >> Fix attached. Tested from 16 MiB to 2047 MiB >> >> > Hi Vladimir, > > please sign off your patch so we can commit it: > > http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure > This patch is done by me based on info retrieved from grub-as-qemu-firmware. The chunk which contained the needed info was 4 lines long. So it's not copyright-significant. Since this patch is small I hereby give up my copyright on it and release it to public domain. Signed-off-by: Valdimir '?-coder' Serbinenko > > Thanks, > Stefan -- Regards Vladimir '?-coder/phcoder' Serbinenko -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 293 bytes Desc: OpenPGP digital signature URL: From r.marek at assembler.cz Mon May 3 00:45:51 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Mon, 03 May 2010 00:45:51 +0200 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: <4BD8861F.5050004@assembler.cz> References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> <4BD8861F.5050004@assembler.cz> Message-ID: <4BDE009F.9000802@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Rudolf Marek wrote: > I found that in k8 CAR set_var_mtrr is set as it the arguments would be an > adresses, but in fact they HAVE TO be in kilobytes. Hi again, I re-checked and it was OK, we do have an early function with same name which takes bytes parameters (mtrr-early.c). So this is not the case. I investigated MTRRs bit more. The RAM init on AMD does not use the varmtrr0 and varmtrr1 the reason is that it thinks the first is used for 0-RAMBASE second for ROM caching. I also changed the XIP MTRR setup to cache whole ROM with the MTRR. I think it is OK to do it this way... After the code goes to the post_cache_as_ram.c it sets up an mtrr for the coreboot_ram as 0-RAMTOP. Maybe we can go with a big mtrr 0-TOM and create UCs for VGA.... Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkveAJ8ACgkQ3J9wPJqZRNVDnwCZAariG5FhnCoDs9Nx2H7JAJeq 1rAAnRMKFMYD+EwhlOfotaufe/s2kOIU =GILC -----END PGP SIGNATURE----- From r.marek at assembler.cz Mon May 3 00:59:43 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Mon, 03 May 2010 00:59:43 +0200 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: <4BDB04B2.6020707@gap.upv.es> References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> Message-ID: <4BDE03DF.8080507@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, There is a plenty of bugs as in all modern CPUs ;) http://support.amd.com/us/Processor_TechDocs/41322.pdf Quick look to coreboot shows they are not handled? Some are easy to fix just to set some MSR, some are microcode fixes. Thanks Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkveA98ACgkQ3J9wPJqZRNUdLgCfccGDWGCy2LwChVO8f3W8m/aO DYwAn1NaRs7lm26RDHvGI5bBxilCEoZd =0bW1 -----END PGP SIGNATURE----- From marcj303 at gmail.com Mon May 3 05:42:34 2010 From: marcj303 at gmail.com (Marc Jones) Date: Sun, 2 May 2010 21:42:34 -0600 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: <69AAB0E5F104464AB8263E823BC37789@chimp> References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> <69AAB0E5F104464AB8263E823BC37789@chimp> Message-ID: On Fri, Apr 30, 2010 at 9:49 PM, Myles Watson wrote: > >> /* variable MTRRs */ >> msr 00000200=0000000000000000 >> msr 00000201=0000000000000000 >> msr 00000202=00000000fff00006 >> msr 00000203=0000fffffff80800 > This looks wrong to me. ?I'm not an expert, but Since 202 is the base, and > 203 is the mask, It looks like the area from 0xfff00000 - 0xfff7ffff is > cached. ?I would think the correct setting would be: >> msr 00000202=00000000fff00006 >> msr 00000203=0000fffffff00800 > I agree, this is only 512KB not 1MB as I would expect. Check $REAL_XIP_ROM_BASE and CONFIG_XIP_ROM_SIZE which get used in cpu/amd/car/cache_as_ram.inc. Marc -- http://se-eng.com From marcj303 at gmail.com Mon May 3 05:52:54 2010 From: marcj303 at gmail.com (Marc Jones) Date: Sun, 2 May 2010 21:52:54 -0600 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: <4BDE03DF.8080507@assembler.cz> References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz> Message-ID: On Sun, May 2, 2010 at 4:59 PM, Rudolf Marek wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > There is a plenty of bugs as in all modern CPUs ;) > > http://support.amd.com/us/Processor_TechDocs/41322.pdf > > Quick look to coreboot shows they are not handled? > > Some are easy to fix just to set some MSR, some are microcode fixes. > That Fam10 bugs should be handled in cpuSetAMDMSR as well as the microcode. If it is a race condition, it should pass CONFIG_LOGICAL_CPUS = 0. Marc -- http://se-eng.com From eswierk at aristanetworks.com Mon May 3 05:24:24 2010 From: eswierk at aristanetworks.com (Ed Swierk) Date: Sun, 2 May 2010 20:24:24 -0700 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: <4BDE009F.9000802@assembler.cz> References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> <4BD8861F.5050004@assembler.cz> <4BDE009F.9000802@assembler.cz> Message-ID: On Sun, May 2, 2010 at 3:45 PM, Rudolf Marek wrote: > I re-checked and it was OK, we do have an early function with same name which > takes bytes parameters (mtrr-early.c). So this is not the case. I investigated > MTRRs bit more. I noticed that too. Perhaps we should rename the early version to something like early_set_var_mtrr() to avoid confusion? > The RAM init on AMD does not use the varmtrr0 and varmtrr1 the reason is that it > thinks the first is used for 0-RAMBASE second for ROM caching. > > I also changed the XIP MTRR setup to cache whole ROM with the MTRR. I think it > is OK to do it this way... > > After the code goes to the post_cache_as_ram.c it sets up an mtrr for the > coreboot_ram as 0-RAMTOP. Maybe we can go with a big mtrr 0-TOM and create UCs > for VGA.... Would we also need to carve out an uncached space for any MMIO BARs that are used during early setup? --Ed From marcj303 at gmail.com Mon May 3 06:01:26 2010 From: marcj303 at gmail.com (Marc Jones) Date: Sun, 2 May 2010 22:01:26 -0600 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> <4BD8861F.5050004@assembler.cz> <4BDE009F.9000802@assembler.cz> Message-ID: On Sun, May 2, 2010 at 9:24 PM, Ed Swierk wrote: > On Sun, May 2, 2010 at 3:45 PM, Rudolf Marek wrote: >> I re-checked and it was OK, we do have an early function with same name which >> takes bytes parameters (mtrr-early.c). So this is not the case. I investigated >> MTRRs bit more. > > I noticed that too. Perhaps we should rename the early version to > something like early_set_var_mtrr() to avoid confusion? > That would be good. >> The RAM init on AMD does not use the varmtrr0 and varmtrr1 the reason is that it >> thinks the first is used for 0-RAMBASE second for ROM caching. >> >> I also changed the XIP MTRR setup to cache whole ROM with the MTRR. I think it >> is OK to do it this way... >> >> After the code goes to the post_cache_as_ram.c it sets up an mtrr for the >> coreboot_ram as 0-RAMTOP. Maybe we can go with a big mtrr 0-TOM and create UCs >> for VGA.... > > Would we also need to carve out an uncached space for any MMIO BARs > that are used during early setup? > TOM will have the hole already handled and additional memory would be hoisted. Marc -- http://se-eng.com From marcj303 at gmail.com Mon May 3 05:47:31 2010 From: marcj303 at gmail.com (Marc Jones) Date: Sun, 2 May 2010 21:47:31 -0600 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: <4BDE009F.9000802@assembler.cz> References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> <4BD8861F.5050004@assembler.cz> <4BDE009F.9000802@assembler.cz> Message-ID: On Sun, May 2, 2010 at 4:45 PM, Rudolf Marek wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Rudolf Marek wrote: >> I found that in k8 CAR set_var_mtrr is set as it the arguments would be an >> adresses, but in fact they HAVE TO be in kilobytes. > > Hi again, > > I re-checked and it was OK, we do have an early function with same name which > takes bytes parameters (mtrr-early.c). So this is not the case. I investigated > MTRRs bit more. > > The RAM init on AMD does not use the varmtrr0 and varmtrr1 the reason is that it > thinks the first is used for 0-RAMBASE second for ROM caching. > > I also changed the XIP MTRR setup to cache whole ROM with the MTRR. I think it > is OK to do it this way... > > After the code goes to the post_cache_as_ram.c it sets up an mtrr for the > coreboot_ram as 0-RAMTOP. Maybe we can go with a big mtrr 0-TOM and create UCs > for VGA.... > > Thanks, > Rudolf Hi Rudolf, I was just looking at the same thing. I don't like the MTRR manipulation that is happening in post_cache_as_ram.c. Doing 0-TOM is a little tricky if the dimms are different sizes. It is easier to let that get setup in the RAM stage. Getting the XIP setup correctly for the lzma decompress seems to be an issue. I am not certain what is happening and if we are crossing some boundaries that are causing flushes. In addition to fixing the cache, Arne's patch to put the lzma into memory may be the way to go. Marc -- http://se-eng.com From patrick at georgi-clan.de Mon May 3 08:12:06 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 03 May 2010 08:12:06 +0200 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> <4BD8861F.5050004@assembler.cz> <4BDE009F.9000802@assembler.cz> Message-ID: <1272867126.9413.27.camel@tetris> Am Sonntag, den 02.05.2010, 21:47 -0600 schrieb Marc Jones: > I was just looking at the same thing. I don't like the MTRR > manipulation that is happening in post_cache_as_ram.c. Doing 0-TOM is > a little tricky if the dimms are different sizes. It is easier to let It's one MTRR per DIMM, where identically sized DIMMs can be merged (in pairs of two, until merging is done). Actually, as long as there are only power-of-two DIMMs around, it's a matter of knowing the total memory size (in addition to usable memory due to UMA and the like), and counting bits. Then another MTRR for shared video memory (if configured, and if it's power-of-two sized) and another for 0xa0000-0xc0000. For 512 + 512 + 128 + 128MB DIMMs and 8MB UMA this gives: 0-1024MB: cached 1024-(1024+256): cached (1024+256-8) - (1024+256): uncached 0xa0000-0xc0000: uncached 0xfff00000-0x10000000: ROM: cached Contrast this to the current setup: 0x00000-0x80000 cached 0x80000-0xa0000 cached 0xa0000-0xc0000 uncached 0xe0000-0x100000 cached 0x100000-whereever cached (hopefully covering all of RAMBASE..RAMTOP) subset of 0xfff00000-0x10000000 (XIP_ROM): ROM: cached The latter takes more MTRRs, and we still have to hope that the >1MB MTRR actually covers the whole RAMBASE..RAMTOP area. And we can't simply use RAMBASE and RAMTOP to determine the MTRR, as MTRRs have these nice requirements about power-of-two sizes and being aligned to their size. > that get setup in the RAM stage. Getting the XIP setup correctly for > the lzma decompress seems to be an issue. I am not certain what is > happening and if we are crossing some boundaries that are causing > flushes. That would most likely mean that the XIP_ROM_SIZE is too small (so XIP_ROM + CAR isn't larger than the available cache). Curiously, the romstage doesn't run slow, only the memcpy/ulzma part. But it's not that bad: When we decompress, RAM is around, so CAR should already be disabled, and we can cache the entire ROM area and all of RAM. > In addition to fixing the cache, Arne's patch to put the lzma > into memory may be the way to go. I'm not sure we can trust the compiler to always build the code in a way that we can copy it, so I'd prefer that solution to be a work-around until the real issue is solved and then to never reappear. Patrick From stepan at coresystems.de Mon May 3 08:20:50 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Mon, 03 May 2010 08:20:50 +0200 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: <4BDE03DF.8080507@assembler.cz> References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz> Message-ID: <4BDE6B42.4000701@coresystems.de> On 5/3/10 12:59 AM, Rudolf Marek wrote: > Hi, > > There is a plenty of bugs as in all modern CPUs ;) > > http://support.amd.com/us/Processor_TechDocs/41322.pdf > > Quick look to coreboot shows they are not handled? > > Some are easy to fix just to set some MSR, some are microcode fixes. > > Thanks > Rudolf I thin we should look into this during the Fam10/RS780 porting GSoC, too. Stefan From knuku at gap.upv.es Mon May 3 09:08:59 2010 From: knuku at gap.upv.es (Knut Kujat) Date: Mon, 03 May 2010 09:08:59 +0200 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz> Message-ID: <4BDE768B.3000801@gap.upv.es> Marc Jones escribi?: > On Sun, May 2, 2010 at 4:59 PM, Rudolf Marek wrote: > >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> Hi, >> >> There is a plenty of bugs as in all modern CPUs ;) >> >> http://support.amd.com/us/Processor_TechDocs/41322.pdf >> >> Quick look to coreboot shows they are not handled? >> >> Some are easy to fix just to set some MSR, some are microcode fixes. >> >> > > That Fam10 bugs should be handled in cpuSetAMDMSR as well as the microcode. > > If it is a race condition, it should pass CONFIG_LOGICAL_CPUS = 0. > > Marc > > Hi, thx for your comments. I already set Config_Logical_CPUS = 0 and set physical and logical CPUs to 1. This gets me a little further but still hangs before warm reset. As I already set I have the exact same problem as Ward reported some time ago. Thanks, Knut Kujat. From sunlee999 at hotmail.com Mon May 3 13:50:38 2010 From: sunlee999 at hotmail.com (Li scott) Date: Mon, 3 May 2010 19:50:38 +0800 Subject: [coreboot] coreboot for ASUS A8N-E support "AMD Athlon(tm) 64 X2 Dual Core Processor 3800+" Message-ID: Hi, I have a ASUS A8N-E M/B, and found this board is on the supported list, but after flash the BIOS (build from the 5511 revision), there is no any output on the console; is it support for my hardware or there is any thing I need to modify? My hardware:M/B: ASUS A8N-E rev:2.00CPU: AMD Athlon 64 X2 3800+RAM: DDR400 512MB on channel _________________________________________________________________ Hotmail ???????????? https://signup.live.com/signup.aspx?id=60969 -------------- next part -------------- An HTML attachment was scrubbed... URL: From paulepanter at users.sourceforge.net Mon May 3 14:11:45 2010 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Mon, 03 May 2010 14:11:45 +0200 Subject: [coreboot] coreboot for ASUS A8N-E support "AMD Athlon(tm) 64 X2 Dual Core Processor 3800+" In-Reply-To: References: Message-ID: <1272888705.5936.2.camel@mattotaupa> Dear Li, Am Montag, den 03.05.2010, 19:50 +0800 schrieb Li scott: > I have a ASUS A8N-E M/B, and found this board is on the supported > list, but after flash the BIOS (build from the 5511 revision), there > is no any output on the console; do you mean the serial console? Did you test that the serial console is working fine in a different setup? > is it support for my hardware or there is any thing I need to modify? How did you build it? I do not know more. Sorry. Hopefully others will be able to help you. If it is urgent you could also join the IRC channel. [?] Thanks, Paul PS: Please just send plain text messages and no HTML ones. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: Dies ist ein digital signierter Nachrichtenteil URL: From svn at coreboot.org Mon May 3 16:00:02 2010 From: svn at coreboot.org (coreboot tracker) Date: Mon, 03 May 2010 16:00:02 +0200 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From svn at coreboot.org Mon May 3 16:16:42 2010 From: svn at coreboot.org (coreboot) Date: Mon, 03 May 2010 14:16:42 -0000 Subject: [coreboot] #142: remove #warnings in the code In-Reply-To: <041.8458c7b2040ffbac121d1b9d0c10867d@coreboot.org> References: <041.8458c7b2040ffbac121d1b9d0c10867d@coreboot.org> Message-ID: <050.bb397324a69c88de359610694b689ec2@coreboot.org> #142: remove #warnings in the code ---------------------------------+------------------------------------------ Reporter: myles | Owner: somebody Type: defect | Status: closed Priority: major | Milestone: Component: coreboot | Resolution: fixed Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Changes (by stepan): * status: new => closed * resolution: => fixed -- Ticket URL: coreboot From svn at coreboot.org Mon May 3 16:44:59 2010 From: svn at coreboot.org (coreboot) Date: Mon, 03 May 2010 14:44:59 -0000 Subject: [coreboot] #77: hang on the "Jumping to coreboot" step on via epia-m with 4-chip 128Mbyte DDR module In-Reply-To: <049.493e5c7405fef1092da8b31caf55c48b@coreboot.org> References: <049.493e5c7405fef1092da8b31caf55c48b@coreboot.org> Message-ID: <058.c77ed7cec72f2ceff548e39f712feccc@coreboot.org> #77: hang on the "Jumping to coreboot" step on via epia-m with 4-chip 128Mbyte DDR module ------------------------------+--------------------------------------------- Reporter: bam80@? | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: via epia-m ram init jumping to linuxbios hang Dependencies: | Patchstatus: there is no patch ------------------------------+--------------------------------------------- Comment(by stepan): The problem is documented on the VIA Epia-M Wiki page. Only 256MB modules are supported unless someone is willing to fix the code. (It reads like v1 did a better job) -- Ticket URL: coreboot From svn at coreboot.org Mon May 3 16:58:09 2010 From: svn at coreboot.org (coreboot) Date: Mon, 03 May 2010 14:58:09 -0000 Subject: [coreboot] #153: resume from suspend on epia-m In-Reply-To: <059.b5ee81b605ceb1fe86976c98b9b6d5b4@coreboot.org> References: <059.b5ee81b605ceb1fe86976c98b9b6d5b4@coreboot.org> Message-ID: <068.2f2c56da70d70e87a362635402b8018f@coreboot.org> #153: resume from suspend on epia-m ---------------------------------------+------------------------------------ Reporter: bam | Owner: stepan Type: defect | Status: closed Priority: major | Milestone: Component: coreboot | Resolution: wontfix Keywords: s3 suspend epia | Dependencies: Patchstatus: there is no patch | ---------------------------------------+------------------------------------ Changes (by stepan): * status: new => closed * resolution: => wontfix Comment: When using the vendor supplied ACPI (which we do not support, sorry) you have to delete the line {{{ Name (\_S3, Package () { .... }) }}} from your DSDT. -- Ticket URL: coreboot From svn at coreboot.org Mon May 3 18:21:53 2010 From: svn at coreboot.org (repository service) Date: Mon, 03 May 2010 18:21:53 +0200 Subject: [coreboot] [commit] r5521 - trunk/src/mainboard/emulation/qemu-x86 Message-ID: Author: stepan Date: Mon May 3 18:21:52 2010 New Revision: 5521 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5521 Log: Qemu, despite "emulating" an intel chipset, uses the CMOS to tell the BIOS how much RAM the virtual machine has available. This patch fixes the detection. Signed-off-by: Valdimir Serbinenko Acked-by: Stefan Reinauer Modified: trunk/src/mainboard/emulation/qemu-x86/northbridge.c Modified: trunk/src/mainboard/emulation/qemu-x86/northbridge.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/northbridge.c Fri Apr 30 22:44:30 2010 (r5520) +++ trunk/src/mainboard/emulation/qemu-x86/northbridge.c Mon May 3 18:21:52 2010 (r5521) @@ -53,60 +53,44 @@ extern uint64_t high_tables_base, high_tables_size; #endif +#define CMOS_ADDR_PORT 0x70 +#define CMOS_DATA_PORT 0x71 +#define HIGH_RAM_ADDR 0x35 +#define LOW_RAM_ADDR 0x34 + static void cpu_pci_domain_set_resources(device_t dev) { - static const uint8_t ramregs[] = { - 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 - }; - device_t mc_dev; - uint32_t pci_tolm; - - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; - if (mc_dev) { - unsigned long tomk, tolmk; - unsigned char rambits; - int i, idx; - - for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { - unsigned char reg; - reg = pci_read_config8(mc_dev, ramregs[i]); - /* these are ENDING addresses, not sizes. - * if there is memory in this slot, then reg will be > rambits. - * So we just take the max, that gives us total. - * We take the highest one to cover for once and future coreboot - * bugs. We warn about bugs. - */ - if (reg > rambits) - rambits = reg; - if (reg < rambits) - printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", - ramregs[i]); - } - if (rambits == 0) { - printk(BIOS_ERR, "RAM size config registers are empty; defaulting to 64 MBytes\n"); - rambits = 8; - } - printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); - tomk = rambits*8*1024; - /* Compute the top of Low memory */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does not overlap the memory. */ - tolmk = tomk; - } - - /* Report the memory regions. */ - idx = 10; - ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tolmk - 768); + u32 pci_tolm = find_pci_tolm(&dev->link[0]); + unsigned long tomk = 0, tolmk; + int idx; + + outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT); + tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14; + outb (LOW_RAM_ADDR, CMOS_ADDR_PORT); + tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; + tomk += 16 * 1024; + + printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n", + tomk, tomk / 1024); + + /* Compute the top of Low memory */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does not overlap the memory. */ + tolmk = tomk; + } + + /* Report the memory regions. */ + idx = 10; + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, tolmk - 768); #if CONFIG_WRITE_HIGH_TABLES==1 - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; #endif - } + assign_resources(&dev->link[0]); } From stepan at coresystems.de Mon May 3 18:24:26 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Mon, 03 May 2010 18:24:26 +0200 Subject: [coreboot] [PATCH] Fix coreboot qemu RAM size detection In-Reply-To: <4BDDA6F5.8010307@gmail.com> References: <4BDD938D.6020105@gmail.com> <4BDD9F92.1050201@coresystems.de> <4BDDA6F5.8010307@gmail.com> Message-ID: <4BDEF8BA.7080007@coresystems.de> On 5/2/10 6:23 PM, Vladimir '?-coder/phcoder' Serbinenko wrote: >> On 5/2/10 5:00 PM, Vladimir '?-coder/phcoder' Serbinenko wrote: >> >>> Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM. >>> Fix attached. Tested from 16 MiB to 2047 MiB >>> >>> > Signed-off-by: Valdimir '?-coder' Serbinenko > Thanks. Slightly simplified and committed as r5521 Stefan From joop_boonen at web.de Tue May 4 00:42:35 2010 From: joop_boonen at web.de (Joop Boonen) Date: Tue, 4 May 2010 00:42:35 +0200 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard Message-ID: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> All,' I cant create a bug ticket in: http://tracker.coreboot.org/trac/coreboot/newticket I've build Coreboot for this main board with LIFO with and without VGA ROM. But it doesn't get trough the boot process. I've attached some logging files and hwinfo as openSuSE shows it. Can someone help me? How can I create a bugzilla ticket, do I need a username/password? Regards, Joop. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: hwinfo_20100503.txt URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: log_coreboot1.txt URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: sessionvga.log Type: text/x-log Size: 33020 bytes Desc: not available URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: session_20100503.txt URL: From mylesgw at gmail.com Tue May 4 01:02:33 2010 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 3 May 2010 17:02:33 -0600 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> Message-ID: <6E38F8796C8343438E450CF5883EB548@chimp> > I've build Coreboot for this main board with LIFO with and without VGA > ROM. But it doesn't get trough the boot process. It quits really early in device enumeration. You could put some debugging statements (printk) in amdk8_scan_chains and friends to see why it quits. > Can someone help me? It worked around rev 4920. Have you tried multiple revisions? It's not getting close to starting FILO or initializing the VGA. Thanks, Myles From sunlee999 at hotmail.com Tue May 4 03:24:35 2010 From: sunlee999 at hotmail.com (Li scott) Date: Tue, 4 May 2010 09:24:35 +0800 Subject: [coreboot] coreboot for ASUS A8N-E support "AMD Athlon(tm) 64 X2 Dual Core Processor 3800+" In-Reply-To: <1272888705.5936.2.camel@mattotaupa> References: , <1272888705.5936.2.camel@mattotaupa> Message-ID: > From: paulepanter at users.sourceforge.net > To: coreboot at coreboot.org > Date: Mon, 3 May 2010 14:11:45 +0200 > Subject: Re: [coreboot] coreboot for ASUS A8N-E support "AMD Athlon(tm) 64 X2 Dual Core Processor 3800+" > > Dear Li, > > > Am Montag, den 03.05.2010, 19:50 +0800 schrieb Li scott: > > I have a ASUS A8N-E M/B, and found this board is on the supported > > list, but after flash the BIOS (build from the 5511 revision), there > > is no any output on the console; > > do you mean the serial console? Did you test that the serial console is > working fine in a different setup? yes, it is serial console, and I'm sure it is work. > > > is it support for my hardware or there is any thing I need to modify? > > How did you build it? I build it from Cent OS 5.4 x86 platform. > > I do not know more. Sorry. Hopefully others will be able to help you. If > it is urgent you could also join the IRC channel. Thank you very much, I will continue to look up what's wrong on it... > > [?] > > > Thanks, > > Paul > > > PS: Please just send plain text messages and no HTML ones. _________________________________________________________________ Hotmail ???????????? https://signup.live.com/signup.aspx?id=60969 -------------- next part -------------- An HTML attachment was scrubbed... URL: From joop_boonen at web.de Tue May 4 07:18:27 2010 From: joop_boonen at web.de (Joop Boonen) Date: Tue, 04 May 2010 07:18:27 +0200 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> Message-ID: <4BDFAE23.4040301@web.de> On 05/04/2010 12:42 AM, Joop Boonen wrote: > All, > > I cant create a bug ticket in: > http://tracker.coreboot.org/trac/coreboot/newticket > > I've build Coreboot for this main board with LIFO with and without VGA > ROM. But it doesn't get trough the boot process. > > I've attached some logging files and hwinfo as openSuSE shows it. > I've attached the .config to this email. > Can someone help me? > > How can I create a bugzilla ticket, do I need a username/password? > > Regards, > > Joop. -------------- next part -------------- A non-text attachment was scrubbed... Name: .config Type: application/x-config Size: 7882 bytes Desc: not available URL: From nathan at traverse.com.au Tue May 4 10:07:08 2010 From: nathan at traverse.com.au (Nathan Williams) Date: Tue, 04 May 2010 18:07:08 +1000 Subject: [coreboot] [PATCH] Add AES to devicetree.cb for AMD LX boards Message-ID: <4BDFD5AC.4020706@traverse.com.au> Signed-off-by: Nathan Williams -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: AES.diff URL: From joop_boonen at web.de Tue May 4 11:14:07 2010 From: joop_boonen at web.de (Joop Boonen) Date: Tue, 4 May 2010 11:14:07 +0200 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: <6E38F8796C8343438E450CF5883EB548@chimp> References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> Message-ID: <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> On Tue, May 4, 2010 1:02 am, Myles Watson wrote: >> I've build Coreboot for this main board with FILO with and without VGA >> ROM. But it doesn't get trough the boot process. > It quits really early in device enumeration. You could put some debugging > statements (printk) in amdk8_scan_chains and friends to see why it quits. > I will, try this after I try rev 4920. >> Can someone help me? > It worked around rev 4920. Have you tried multiple revisions? It's not > getting close to starting FILO or initializing the VGA. I will try this first (rev 4920). I'll let you know the outcome as soon as I've tested it. > > Thanks, > Myles > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From rminnich at gmail.com Tue May 4 16:01:02 2010 From: rminnich at gmail.com (ron minnich) Date: Tue, 4 May 2010 07:01:02 -0700 Subject: [coreboot] [PATCH] Add AES to devicetree.cb for AMD LX boards In-Reply-To: <4BDFD5AC.4020706@traverse.com.au> References: <4BDFD5AC.4020706@traverse.com.au> Message-ID: Acked-by: Ronald G. Minnich From mark at tvk.rwth-aachen.de Tue May 4 14:39:44 2010 From: mark at tvk.rwth-aachen.de (mark) Date: Tue, 04 May 2010 14:39:44 +0200 Subject: [coreboot] Hardware damaged? Message-ID: <201005041439.45120.mark@tvk.rwth-aachen.de> Hi, I wanted to flash coreboot onto my VIE Epia-M; this is what I did: 1) bought an identical Bios chip to have a working copy of the old bios 2) checked out coreboot, filo, flashrom 3) dumped the bios with flashrom into a file and wrote that file onto the new chip with flashrom, after hotswapping the chip. I verified each step with flashrom, no problems here. Now the board booted with both chips, everything was fine. Then I dumped the video-bios, compiled filo and compiled coreboot after configuring it. It compiled successfully and I wrote the rom-file onto the new chip and rebooted. The computer started and printed some random, weird, colorful blocks all around the screen, nothing else happened. So I removed the new chip and inserted the old chip, which still contained the working, official bios. But after starting up the computer, the screen remained black and nothing happend, except that the harddrive spinned up; no beep, nothing. Changed back to the new, not working chip (which at least showed some color), but same effect here. Did I brick the board somehow, or is it possible that coreboot bricked it somehow? I don't understand, what part of the board could have been damaged here. Short circuit? Greetings, Mark From stepan at coresystems.de Tue May 4 16:15:00 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 04 May 2010 16:15:00 +0200 Subject: [coreboot] [PATCH] Add AES to devicetree.cb for AMD LX boards In-Reply-To: <4BDFD5AC.4020706@traverse.com.au> References: <4BDFD5AC.4020706@traverse.com.au> Message-ID: <4BE02BE4.6080209@coresystems.de> On 5/4/10 10:07 AM, Nathan Williams wrote: > Signed-off-by: Nathan Williams > > - device pci 1.0 on end > - device pci 1.1 on end > + device pci 1.0 on end # Northbridge > + device pci 1.1 on end # Graphics > + device pci 1.2 on end # AES What's the impact of that change? Stefan -------------- next part -------------- An HTML attachment was scrubbed... URL: From r.marek at assembler.cz Tue May 4 16:16:33 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 04 May 2010 16:16:33 +0200 Subject: [coreboot] Hardware damaged? In-Reply-To: <201005041439.45120.mark@tvk.rwth-aachen.de> References: <201005041439.45120.mark@tvk.rwth-aachen.de> Message-ID: <4BE02C41.2080307@assembler.cz> Hi, Please try to unplug the board completely from the power outlet and retry. Also dont forget to clear the CMOS. Then re-try with orig bios. Rudolf From mylesgw at gmail.com Tue May 4 16:53:43 2010 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 4 May 2010 08:53:43 -0600 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> Message-ID: >> I think there must be some MTRR setup problem. ?Maybe you could print out >> the MTRRs just before the slow parts? > > Here's a dump of various MSRs right after the call to raminit_amdmct() > in romstage.c: > /* fixed MTRRs */ > msr 00000250=1e1e1e1e1e1e1e1e > msr 00000258=1e1e1e1e1e1e1e1e > msr 00000259=0000000000000000 > msr 00000268=1e1e1e1e00000000 > msr 00000269=1e1e1e1e1e1e1e1e > msr 0000026a=0000000000000000 > msr 0000026b=0000000000000000 > msr 0000026c=0404040404040404 > msr 0000026d=0404040404040404 > msr 0000026e=0404040404040404 > msr 0000026f=0404040404040404 I don't understand these values. I would have expected msr 00000268=1e1e1e1e1e1e1e1e (0xc0000-c7fff) (only if CAR size = 64K) msr 00000269=1e1e1e1e1e1e1e1e (0xc8000-cffff) Why are we setting anything in the 0-0x80000 range ( msr 0x250) or the 0x80000-0x9ffff range (msr 0x258)? Same question for 0xe0000-0xfffff (0x26d-26f). Thanks, Myles From mark at tvk.rwth-aachen.de Tue May 4 16:49:22 2010 From: mark at tvk.rwth-aachen.de (mark) Date: Tue, 04 May 2010 16:49:22 +0200 Subject: [coreboot] Hardware damaged? In-Reply-To: <4BE02C41.2080307@assembler.cz> References: <201005041439.45120.mark@tvk.rwth-aachen.de> <4BE02C41.2080307@assembler.cz> Message-ID: <201005041649.23437.mark@tvk.rwth-aachen.de> Hi, > Please try to unplug the board completely from the power outlet and retry. > Also dont forget to clear the CMOS. Then re-try with orig bios. I unplugged the power, set the clear cmos jumper, waited some time and even removed the battery, but this doesn't help, still the same symptoms after powering on again. Mark -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part. URL: From r.marek at assembler.cz Tue May 4 17:20:39 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 04 May 2010 17:20:39 +0200 Subject: [coreboot] Hardware damaged? In-Reply-To: <201005041649.23437.mark@tvk.rwth-aachen.de> References: <201005041439.45120.mark@tvk.rwth-aachen.de> <4BE02C41.2080307@assembler.cz> <201005041649.23437.mark@tvk.rwth-aachen.de> Message-ID: <4BE03B47.2040507@assembler.cz> Hi, Hm no idea what went wrong. Do you see something on serial with the coreboot? Most likely 115200 bauds... Rudolf From mylesgw at gmail.com Tue May 4 17:22:21 2010 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 4 May 2010 09:22:21 -0600 Subject: [coreboot] Hardware damaged? In-Reply-To: <201005041649.23437.mark@tvk.rwth-aachen.de> References: <201005041439.45120.mark@tvk.rwth-aachen.de> <4BE02C41.2080307@assembler.cz> <201005041649.23437.mark@tvk.rwth-aachen.de> Message-ID: On Tue, May 4, 2010 at 8:49 AM, mark wrote: > Hi, > >> Please try to unplug the board completely from the power outlet and retry. >> Also dont forget to clear the CMOS. Then re-try with orig bios. > > I unplugged the power, set the clear cmos jumper, waited some time and even > removed the battery, but this doesn't help, still the same symptoms after > powering on again. Is there any output on the serial console with Coreboot? There should have been a lot of it the first time when you got to VGA init. Thanks, Myles From Frieder.Ferlemann at gmx.de Tue May 4 18:14:58 2010 From: Frieder.Ferlemann at gmx.de (Frieder Ferlemann) Date: Tue, 04 May 2010 18:14:58 +0200 Subject: [coreboot] Hardware damaged? In-Reply-To: <201005041649.23437.mark@tvk.rwth-aachen.de> References: <201005041439.45120.mark@tvk.rwth-aachen.de> <4BE02C41.2080307@assembler.cz> <201005041649.23437.mark@tvk.rwth-aachen.de> Message-ID: <4BE04802.80407@gmx.de> Am 04.05.2010 16:49, schrieb mark: > I unplugged the power, set the clear cmos jumper, waited some time and even > removed the battery, but this doesn't help, still the same symptoms after > powering on again. has a pin of the socket or the flash been bent? Greetings, Frieder From joop_boonen at web.de Tue May 4 19:39:37 2010 From: joop_boonen at web.de (Joop Boonen) Date: Tue, 04 May 2010 19:39:37 +0200 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> Message-ID: <4BE05BD9.7050302@web.de> On 05/04/2010 11:14 AM, Joop Boonen wrote: > On Tue, May 4, 2010 1:02 am, Myles Watson wrote: > >>> I've build Coreboot for this main board with FILO with and without VGA >>> ROM. But it doesn't get trough the boot process. >>> >> It quits really early in device enumeration. You could put some debugging >> statements (printk) in amdk8_scan_chains and friends to see why it quits. >> >> > I will, try this after I try rev 4920. > rev 4920 works without a problem, also with the extracted VGA. I get the FILO screen. > >>> Can someone help me? >>> >> It worked around rev 4920. Have you tried multiple revisions? It's not >> getting close to starting FILO or initializing the VGA. >> > I will try this first (rev 4920). I'll let you know the outcome as soon as > I've tested it. > >> Thanks, >> Myles >> >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> >> > > > From mylesgw at gmail.com Tue May 4 19:54:29 2010 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 4 May 2010 11:54:29 -0600 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: <4BE05BD9.7050302@web.de> References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> <4BE05BD9.7050302@web.de> Message-ID: <2779711E82D84A8EBC18050C95858E3A@chimp> > rev 4920 works without a problem, also with the extracted VGA. I get the > FILO screen. Great. You could check the values from Kconfig (build/config.h) and compare them to the values from 4920. That would be the easiest thing to fix. Thanks, Myles From mylesgw at gmail.com Tue May 4 20:16:16 2010 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 4 May 2010 12:16:16 -0600 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: <2779711E82D84A8EBC18050C95858E3A@chimp> References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> <4BE05BD9.7050302@web.de> <2779711E82D84A8EBC18050C95858E3A@chimp> Message-ID: On Tue, May 4, 2010 at 11:54 AM, Myles Watson wrote: > >> rev 4920 works without a problem, also with the extracted VGA. I get the >> FILO screen. > > Great. ?You could check the values from Kconfig (build/config.h) and compare > them to the values from 4920. ?That would be the easiest thing to fix. I think the most likely culprit is SB_HT_CHAIN_ON_BUS0. Could you change it to 1 in src/mainboard/arima/hdama/Kconfig, make oldconfig, and test? Thanks, Myles From r.marek at assembler.cz Tue May 4 22:50:42 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 04 May 2010 22:50:42 +0200 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> Message-ID: <4BE088A2.3090100@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 > Why are we setting anything in the 0-0x80000 range ( msr 0x250) or the > 0x80000-0x9ffff range (msr 0x258)? addr = 0x250; <------>lo = 0x1E1E1E1E; <------>hi = lo; <------>_WRMSR(addr, lo, hi);<-><------>/* 0 - 512K = WB Mem */ <------>addr = 0x258; <------>_WRMSR(addr, lo, hi);<-><------>/* 512K - 640K = WB Mem */ In mctmtr_d.c Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvgiKIACgkQ3J9wPJqZRNUingCdGXpLI64NIXQoyAPLYYIussJr yjEAni1NY76Xn+IzFR5bFKU7pnVnL/BK =IuTW -----END PGP SIGNATURE----- From peter at stuge.se Tue May 4 23:26:42 2010 From: peter at stuge.se (Peter Stuge) Date: Tue, 4 May 2010 23:26:42 +0200 Subject: [coreboot] Hardware damaged? In-Reply-To: <201005041439.45120.mark@tvk.rwth-aachen.de> References: <201005041439.45120.mark@tvk.rwth-aachen.de> Message-ID: <20100504212642.18349.qmail@stuge.se> mark wrote: > Did I brick the board somehow, or is it possible that coreboot > bricked it somehow? I don't understand, what part of the board > could have been damaged here. Short circuit? There could have been a short when you inserted the new flash chip with coreboot, but then you would not have gotten the one start with the colorful display. You could check the capacitors on the board for leaks - several on my EPIA-M board have leaked and the board doesn't start, but that's not likely because of coreboot, rather because of bad capacitors. //Peter From joop_boonen at web.de Tue May 4 23:59:26 2010 From: joop_boonen at web.de (Joop Boonen) Date: Tue, 4 May 2010 23:59:26 +0200 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> <4BE05BD9.7050302@web.de> <2779711E82D84A8EBC18050C95858E3A@chimp> Message-ID: On Tue, May 4, 2010 8:16 pm, Myles Watson wrote: > On Tue, May 4, 2010 at 11:54 AM, Myles Watson wrote: >> >>> rev 4920 works without a problem, also with the extracted VGA. I get >>> the >>> FILO screen. >> >> Great. ?You could check the values from Kconfig (build/config.h) and >> compare >> them to the values from 4920. ?That would be the easiest thing to fix. > I think the most likely culprit is SB_HT_CHAIN_ON_BUS0. Could you > change it to 1 in src/mainboard/arima/hdama/Kconfig, make oldconfig, > and test? I've tested it. I get the filo screen now. When I do a probe I don't see any IDE device yet. Neither IDE nor SATA SIL3114 drive. This also didn't work for version 4920. > > Thanks, > Myles > -------------- next part -------------- A non-text attachment was scrubbed... Name: session_filo_20100504.log Type: text/x-log Size: 98720 bytes Desc: not available URL: From svn at coreboot.org Wed May 5 00:30:34 2010 From: svn at coreboot.org (repository service) Date: Wed, 05 May 2010 00:30:34 +0200 Subject: [coreboot] [commit] r5522 - trunk/src/mainboard/arima/hdama Message-ID: Author: myles Date: Wed May 5 00:30:33 2010 New Revision: 5522 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5522 Log: Fix arima/hdama. It was changed to match newconfig, which was broken. Signed-off-by: Myles Watson Acked-by: Myles Watson Modified: trunk/src/mainboard/arima/hdama/Kconfig Modified: trunk/src/mainboard/arima/hdama/Kconfig ============================================================================== --- trunk/src/mainboard/arima/hdama/Kconfig Mon May 3 18:21:52 2010 (r5521) +++ trunk/src/mainboard/arima/hdama/Kconfig Wed May 5 00:30:33 2010 (r5522) @@ -62,7 +62,7 @@ config SB_HT_CHAIN_ON_BUS0 int - default 0 + default 1 depends on BOARD_ARIMA_HDAMA config HT_CHAIN_END_UNITID_BASE From mylesgw at gmail.com Wed May 5 00:35:05 2010 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 4 May 2010 16:35:05 -0600 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> <4BE05BD9.7050302@web.de> <2779711E82D84A8EBC18050C95858E3A@chimp> Message-ID: >> I think the most likely culprit is SB_HT_CHAIN_ON_BUS0. ?Could you >> change it to 1 in src/mainboard/arima/hdama/Kconfig, make oldconfig, >> and test? > > I've tested it. I get the filo screen now. Great. I checked that in Rev 5522. > When I do a probe I don't see any IDE device yet. Neither IDE nor SATA > SIL3114 drive. This also didn't work for version 4920. Have you tried SeaBIOS? I haven't used FILO much. In your log it looks like FILO is expecting to find something in your CMOS that it doesn't find. ERROR: No such CMOS option (boot_devices) menu: hda3:/boot/filo/menu.lst You could look into that. Thanks, Myles From nathan at traverse.com.au Wed May 5 01:40:01 2010 From: nathan at traverse.com.au (Nathan Williams) Date: Wed, 05 May 2010 09:40:01 +1000 Subject: [coreboot] [PATCH] Add AES to devicetree.cb for AMD LX boards In-Reply-To: <4BE02BE4.6080209@coresystems.de> References: <4BDFD5AC.4020706@traverse.com.au> <4BE02BE4.6080209@coresystems.de> Message-ID: <4BE0B051.20905@traverse.com.au> On 5/05/2010 12:15 AM, Stefan Reinauer wrote: > On 5/4/10 10:07 AM, Nathan Williams wrote: >> Signed-off-by: Nathan Williams >> >> - device pci 1.0 on end >> - device pci 1.1 on end >> + device pci 1.0 on end # Northbridge >> + device pci 1.1 on end # Graphics >> + device pci 1.2 on end # AES > What's the impact of that change? > > Stefan > I don't think it makes any difference. I just added it for completeness/documentation. Nathan From ward at gnu.org Wed May 5 02:03:51 2010 From: ward at gnu.org (Ward Vandewege) Date: Tue, 4 May 2010 20:03:51 -0400 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> <4BE05BD9.7050302@web.de> <2779711E82D84A8EBC18050C95858E3A@chimp> Message-ID: <20100505000351.GA21290@countzero.vandewege.net> On Tue, May 04, 2010 at 11:59:26PM +0200, Joop Boonen wrote: > On Tue, May 4, 2010 8:16 pm, Myles Watson wrote: > > On Tue, May 4, 2010 at 11:54 AM, Myles Watson wrote: > >> > >>> rev 4920 works without a problem, also with the extracted VGA. I get > >>> the > >>> FILO screen. > >> > >> Great. ?You could check the values from Kconfig (build/config.h) and > >> compare > >> them to the values from 4920. ?That would be the easiest thing to fix. > > I think the most likely culprit is SB_HT_CHAIN_ON_BUS0. Could you > > change it to 1 in src/mainboard/arima/hdama/Kconfig, make oldconfig, > > and test? > > I've tested it. I get the filo screen now. > > When I do a probe I don't see any IDE device yet. Neither IDE nor SATA > SIL3114 drive. This also didn't work for version 4920. Yeah, the Sil3114 needs special handling for its SATA ports. The Tyan S2881 board has the same problem. I'm not sure about the IDE ports. In the past I've used a linux kernel payload to get around that. Rudolf has had success with SeaBIOS (and the SiL3114 option rom, I believe) http://www.coreboot.org/pipermail/coreboot/2009-February/044781.htm but I have not been able to replicate that yet on my Tyan s2881. I wonder if we could make Coreboot do the necessary to initialize that controller, so that we don't need that binary blob or a full blown linux kernel anymore. There appear to be public datasheets for Sil3114, referenced here https://ata.wiki.kernel.org/index.php/Sata_sil And the kernel driver also knows how to bring it up, since using a linux kernel as a payload has worked for me in the past. Thanks, Ward. -- Ward Vandewege From mylesgw at gmail.com Wed May 5 00:28:25 2010 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 4 May 2010 16:28:25 -0600 Subject: [coreboot] Selfboot error checking fix Message-ID: Check the return value of ulzma, and quit instead of loading the next segment if there's an error. Size pointers 8 characters instead of 16 to beautify the common case where selfboot is loading something into memory below 4GB. Signed-off-by: Myles Watson Thanks, Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: selfboot.diff Type: text/x-patch Size: 709 bytes Desc: not available URL: From mark at tvk.rwth-aachen.de Wed May 5 09:02:59 2010 From: mark at tvk.rwth-aachen.de (mark) Date: Wed, 05 May 2010 09:02:59 +0200 Subject: [coreboot] Hardware damaged? In-Reply-To: References: <201005041439.45120.mark@tvk.rwth-aachen.de> <201005041649.23437.mark@tvk.rwth-aachen.de> Message-ID: <201005050902.59750.mark@tvk.rwth-aachen.de> > Is there any output on the serial console with Coreboot? There should > have been a lot of it the first time when you got to VGA init. The problem is, not even the monitor turns on, which indicates that there is no VGA init or VGA signal, using both chips. I'll check with a multimeter if there is any current on the pins. > has a pin of the socket or the flash been bent? some pins of the original chip have been slightly bent, but I fixed them with a pliers before inserting. Unfortunately my plcc32 extractor is too big for that board, so the first time I used a screwdriver to extract the chip and after that I used some filament underneath the chip to plug it out. I did not check the serial output yet; the only lifesign is the onboard network chip which establishes a link to my switch. But my guess is, that board is beyond repair, as the original bios doesn't work anymore, there is no beep signal, and no VGA signal. If there is anything new, I'll let you know. Thanks for your help so far. Mark -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part. URL: From peter at stuge.se Wed May 5 09:07:12 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 5 May 2010 09:07:12 +0200 Subject: [coreboot] Hardware damaged? In-Reply-To: <201005050902.59750.mark@tvk.rwth-aachen.de> References: <201005041439.45120.mark@tvk.rwth-aachen.de> <201005041649.23437.mark@tvk.rwth-aachen.de> <201005050902.59750.mark@tvk.rwth-aachen.de> Message-ID: <20100505070712.30149.qmail@stuge.se> mark wrote: > the first time I used a screwdriver to extract the chip and after > that I used some filament underneath the chip to plug it out. How thick? Are you 100% sure that the chip actually has good contact in the socket? Maybe try the factory BIOS without that filament once. > the only lifesign is the onboard network chip which establishes a > link to my switch. That's completely independent of coreboot or BIOS. //Peter -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: not available URL: From knuku at gap.upv.es Wed May 5 09:39:35 2010 From: knuku at gap.upv.es (Knut Kujat) Date: Wed, 05 May 2010 09:39:35 +0200 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: <4BDE768B.3000801@gap.upv.es> References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz> <4BDE768B.3000801@gap.upv.es> Message-ID: <4BE120B7.4070401@gap.upv.es> Hi, I finally got it working, but I don't like my solution! I noticed that after setup_mb_resource_map(); the board hang at outb and inl instructions. So I commented it out to see how far this will bring me. For my surprise the board booted right into Linux without further problems. Now my questions are: - I now know that my resource map must be some kind of faulty. But why does it work on one CPU and doesn't on another, complete identical, one? - How do i manage to correct my resource map? Or how do I create a good resource map? - Since it seems to boot fine without resource map. Do I really need one? - And the last one, If I don't setup the res. map, who does it? Thanks and sorry for the whole bunch of questions, Knut Kujat. Knut Kujat escribi?: > Marc Jones escribi?: > >> On Sun, May 2, 2010 at 4:59 PM, Rudolf Marek wrote: >> >> >>> -----BEGIN PGP SIGNED MESSAGE----- >>> Hash: SHA1 >>> >>> Hi, >>> >>> There is a plenty of bugs as in all modern CPUs ;) >>> >>> http://support.amd.com/us/Processor_TechDocs/41322.pdf >>> >>> Quick look to coreboot shows they are not handled? >>> >>> Some are easy to fix just to set some MSR, some are microcode fixes. >>> >>> >>> >> That Fam10 bugs should be handled in cpuSetAMDMSR as well as the microcode. >> >> If it is a race condition, it should pass CONFIG_LOGICAL_CPUS = 0. >> >> Marc >> >> >> > Hi, > > thx for your comments. > > I already set Config_Logical_CPUS = 0 and set physical and logical CPUs > to 1. This gets me a little further but still hangs before warm reset. > As I already set I have the exact same problem as Ward reported some > time ago. > > Thanks, > Knut Kujat. > > From joop_boonen at web.de Wed May 5 10:30:54 2010 From: joop_boonen at web.de (Joop Boonen) Date: Wed, 5 May 2010 10:30:54 +0200 Subject: [coreboot] Filo and ext4 Message-ID: All, I have a question. Will FILO support ext4 in the future? Regards, Joop. From svn at coreboot.org Wed May 5 13:09:26 2010 From: svn at coreboot.org (coreboot) Date: Wed, 05 May 2010 11:09:26 -0000 Subject: [coreboot] #160: Build system: There's no convincing CFLAGS management for util/* Message-ID: <043.a60468f3bc32c2ab0ddf75523cbeacef@coreboot.org> #160: Build system: There's no convincing CFLAGS management for util/* -------------------------+-------------------------------------------------- Reporter: oxygene | Owner: oxygene Type: task | Status: new Priority: major | Milestone: Component: coreboot | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Right now, all utils build with -Iutil/kconfig. We're only lucky that there's no file name overlap. This should be cleaned up. -- Ticket URL: coreboot From patrick at georgi-clan.de Wed May 5 13:14:17 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 05 May 2010 13:14:17 +0200 Subject: [coreboot] [PATCH]Refactor sconfig Message-ID: <4BE15309.4020309@georgi-clan.de> Hi, attached patch moves all the device tree processing out of the parser into a dedicated C source file. It should help understanding what the parser is doing and thus help with further sconfig development. Unfortunately the patch isn't very readable, due to autogenerated code (in the _shipped files), and because I svn-copied sconfig.y to the new files: - sconfig.h (shared data structures) - main.c (device tree handling, main()) The change also requires some modifications to the build. The more general issue of cleaning up this area of the build system is registered as ticket #160 (assigned to me). I tested the patch by doing two full abuild runs (slightly modified to only emit static.c), with and without the patch. All mainboards' static.c were identical with or without the patch. Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20100505-1-sconfig-refactoring URL: From peter at stuge.se Wed May 5 13:17:58 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 5 May 2010 13:17:58 +0200 Subject: [coreboot] [PATCH]Refactor sconfig In-Reply-To: <4BE15309.4020309@georgi-clan.de> References: <4BE15309.4020309@georgi-clan.de> Message-ID: <20100505111758.6186.qmail@stuge.se> Patrick Georgi wrote: > Signed-off-by: Patrick Georgi Acked-by: Peter Stuge From svn at coreboot.org Wed May 5 13:19:50 2010 From: svn at coreboot.org (repository service) Date: Wed, 05 May 2010 13:19:50 +0200 Subject: [coreboot] [commit] r5523 - in trunk: . util/sconfig Message-ID: Author: oxygene Date: Wed May 5 13:19:50 2010 New Revision: 5523 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5523 Log: Split C code in sconfig's parser into a separate file. Update generated parser files. Add proper include path for utils. Signed-off-by: Patrick Georgi Acked-by: Peter Stuge Added: trunk/util/sconfig/main.c - copied, changed from r5522, trunk/util/sconfig/sconfig.y trunk/util/sconfig/sconfig.h - copied, changed from r5522, trunk/util/sconfig/sconfig.y Modified: trunk/Makefile trunk/util/sconfig/Makefile.inc trunk/util/sconfig/sconfig.tab.c_shipped trunk/util/sconfig/sconfig.tab.h_shipped trunk/util/sconfig/sconfig.y Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed May 5 00:30:33 2010 (r5522) +++ trunk/Makefile Wed May 5 13:19:50 2010 (r5523) @@ -170,7 +170,7 @@ $(objutil)/%.o: $(objutil)/%.c @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" - $(HOSTCC) -MMD $(HOSTCFLAGS) -c -o $@ $< + $(HOSTCC) -MMD -I$(subst $(objutil)/,util/,$(dir $<)) -I$(dir $<) $(HOSTCFLAGS) -c -o $@ $< $(obj)/%.o: $(obj)/%.c $(obj)/config.h @printf " CC $(subst $(obj)/,,$(@))\n" Modified: trunk/util/sconfig/Makefile.inc ============================================================================== --- trunk/util/sconfig/Makefile.inc Wed May 5 00:30:33 2010 (r5522) +++ trunk/util/sconfig/Makefile.inc Wed May 5 13:19:50 2010 (r5523) @@ -1,10 +1,17 @@ sconfigobj := sconfigobj += lex.yy.o sconfigobj += sconfig.tab.o +sconfigobj += main.o + +SCONFIGFLAGS += -I$(top)/util/sconfig -I$(objutil)/sconfig $(objutil)/sconfig: mkdir -p $@ +$(objutil)/sconfig/%.o: util/sconfig/%.c + printf " HOSTCC $(subst $(obj)/,,$(@))\n" + $(HOSTCC) $(SCONFIGFLAGS) $(HOSTCFLAGS) -c -o $@ $< + $(objutil)/sconfig/%.o: $(objutil)/sconfig/%.c printf " HOSTCC $(subst $(obj)/,,$(@))\n" $(HOSTCC) $(SCONFIGFLAGS) $(HOSTCFLAGS) -c -o $@ $< Copied and modified: trunk/util/sconfig/main.c (from r5522, trunk/util/sconfig/sconfig.y) ============================================================================== --- trunk/util/sconfig/sconfig.y Wed May 5 00:30:33 2010 (r5522, copy source) +++ trunk/util/sconfig/main.c Wed May 5 13:19:50 2010 (r5523) @@ -1,4 +1,3 @@ -%{ /* * sconfig, coreboot device tree compiler * @@ -19,71 +18,40 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ -#include -#include -#include -#include -#include -#include -#include - -enum devtype { chip, device }; - -struct resource; -struct resource { - int type; - int index; - int base; - struct resource *next; -}; +#include "sconfig.h" +#include "sconfig.tab.h" -struct reg; -struct reg { - char *key; - char *value; - struct reg *next; -}; +struct device *head, *lastdev; -struct device; -struct device { - int id; - int enabled; - int used; - int multidev; - int link; - int rescnt; - int chiph_exists; - char *ops; - char *name; - char *aliased_name; - char *name_underscore; - char *path; - int path_a; - int path_b; - int bustype; - enum devtype type; - struct device *parent; - struct device *bus; - struct device *next; - struct device *nextdev; - struct device *children; - struct device *latestchild; - struct device *next_sibling; - struct device *sibling; - struct device *chip; - struct resource *res; - struct reg *reg; -} *head, *lastdev, *cur_parent, *cur_bus, root; - -struct header; -struct header { - char *name; - struct header *next; -} headers; +struct header headers; -int devcount = 0; +static int devcount = 0; -struct device *new_dev() { +static struct device root; +static struct device mainboard = { + .name = "mainboard", + .name_underscore = "mainboard", + .id = 0, + .chip = &mainboard, + .type = chip, + .chiph_exists = 1, + .children = &root +}; + +static struct device root = { + .name = "dev_root", + .name_underscore = "dev_root", + .id = 0, + .chip = &mainboard, + .type = device, + .path = " .type = DEVICE_PATH_ROOT ", + .ops = "&default_dev_ops_root", + .parent = &root, + .bus = &root, + .enabled = 1 +}; + +static struct device *new_dev() { struct device *dev = malloc(sizeof(struct device)); memset(dev, 0, sizeof(struct device)); dev->id = ++devcount; @@ -94,7 +62,7 @@ return dev; } -int device_match(struct device *a, struct device *b) { +static int device_match(struct device *a, struct device *b) { if ((a->bustype == b->bustype) && (a->bus == b->bus) && (a->path_a == b->path_a) && (a->path_b == b->path_b)) return 1; return 0; @@ -121,15 +89,8 @@ { fprintf (stderr, "%s\n", str); } -%} -%union { - struct device *device; - char *string; - int number; -} -%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER -%% -devtree: devchip { + +void postprocess_devtree(void) { root.next_sibling = root.children; root.next_sibling->next_sibling = root.next_sibling->children; @@ -147,53 +108,43 @@ while (dev->nextdev && dev->nextdev->used) dev->nextdev = dev->nextdev->nextdev; dev = dev->next_sibling; } - }; - -devchip: chip | device ; - -devices: devices devchip | devices registers | ; - -devicesorresources: devicesorresources devchip | devicesorresources resource | ; +} -chip: CHIP STRING /* == path */ { - $$ = new_dev(); - $$->chiph_exists = 1; - $$->name = $2; - $$->name_underscore = strdup($$->name); +struct device *new_chip(char *path) { + struct device *new_chip = new_dev(); + new_chip->chiph_exists = 1; + new_chip->name = path; + new_chip->name_underscore = strdup(new_chip->name); char *c; - for (c = $$->name_underscore; *c; c++) { + for (c = new_chip->name_underscore; *c; c++) { if (*c == '/') *c = '_'; if (*c == '-') *c = '_'; } - $$->type = chip; - $$->chip = $$; + new_chip->type = chip; + new_chip->chip = new_chip; struct stat st; - char *chip_h = malloc(strlen($2)+12); - sprintf(chip_h, "src/%s/chip.h", $2); + char *chip_h = malloc(strlen(path)+12); + sprintf(chip_h, "src/%s/chip.h", path); if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) - $$->chiph_exists = 0; + new_chip->chiph_exists = 0; if (cur_parent->latestchild) { - cur_parent->latestchild->next_sibling = $$; - cur_parent->latestchild->sibling = $$; + cur_parent->latestchild->next_sibling = new_chip; + cur_parent->latestchild->sibling = new_chip; } - cur_parent->latestchild = $$; + cur_parent->latestchild = new_chip; if (!cur_parent->children) - cur_parent->children = $$; - - cur_parent = $$; + cur_parent->children = new_chip; + return new_chip; } - devices END { - cur_parent = $3->parent; - fold_in($3); - - if ($3->chiph_exists) { +void add_header(struct device *dev) { + if (dev->chiph_exists) { int include_exists = 0; struct header *h = &headers; while (h->next) { - int result = strcmp($3->name, h->next->name); + int result = strcmp(dev->name, h->next->name); if (result == 0) { include_exists = 1; break; @@ -205,70 +156,63 @@ struct header *tmp = h->next; h->next = malloc(sizeof(struct header)); memset(h->next, 0, sizeof(struct header)); - h->next->name = $3->name; + h->next->name = dev->name; h->next->next = tmp; - break; } } -}; +} -device: DEVICE BUS NUMBER /* == devnum */ BOOL { - $$ = new_dev(); - $$->bustype = $2; +struct device *new_device(const int bus, const char *devnum, int enabled) { + struct device *new_d = new_dev(); + new_d->bustype = bus; char *tmp; - $$->path_a = strtol(strdup($3), &tmp, 16); + new_d->path_a = strtol(strdup(devnum), &tmp, 16); if (*tmp == '.') { tmp++; - $$->path_b = strtol(tmp, NULL, 16); + new_d->path_b = strtol(tmp, NULL, 16); } char *name = malloc(10); - sprintf(name, "_dev%d", $$->id); - $$->name = name; - $$->name_underscore = name; // shouldn't be necessary, but avoid 0-ptr - $$->type = device; - $$->enabled = $4; - $$->chip = $$->parent->chip; + sprintf(name, "_dev%d", new_d->id); + new_d->name = name; + new_d->name_underscore = name; // shouldn't be necessary, but avoid 0-ptr + new_d->type = device; + new_d->enabled = enabled; + new_d->chip = new_d->parent->chip; if (cur_parent->latestchild) { - cur_parent->latestchild->next_sibling = $$; - cur_parent->latestchild->sibling = $$; + cur_parent->latestchild->next_sibling = new_d; + cur_parent->latestchild->sibling = new_d; } - cur_parent->latestchild = $$; + cur_parent->latestchild = new_d; if (!cur_parent->children) - cur_parent->children = $$; + cur_parent->children = new_d; - lastdev->nextdev = $$; - lastdev = $$; - if ($2 == PCI) { - $$->path = ".type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%x,%d)}}"; + lastdev->nextdev = new_d; + lastdev = new_d; + if (bus == PCI) { + new_d->path = ".type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%x,%d)}}"; } - if ($2 == PNP) { - $$->path = ".type=DEVICE_PATH_PNP,{.pnp={ .port = 0x%x, .device = 0x%x }}"; + if (bus == PNP) { + new_d->path = ".type=DEVICE_PATH_PNP,{.pnp={ .port = 0x%x, .device = 0x%x }}"; } - if ($2 == I2C) { - $$->path = ".type=DEVICE_PATH_I2C,{.i2c={ .device = 0x%x }}"; + if (bus == I2C) { + new_d->path = ".type=DEVICE_PATH_I2C,{.i2c={ .device = 0x%x }}"; } - if ($2 == APIC) { - $$->path = ".type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x%x }}"; + if (bus == APIC) { + new_d->path = ".type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x%x }}"; } - if ($2 == APIC_CLUSTER) { - $$->path = ".type=DEVICE_PATH_APIC_CLUSTER,{.apic_cluster={ .cluster = 0x%x }}"; + if (bus == APIC_CLUSTER) { + new_d->path = ".type=DEVICE_PATH_APIC_CLUSTER,{.apic_cluster={ .cluster = 0x%x }}"; } - if ($2 == PCI_DOMAIN) { - $$->path = ".type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%x }}"; + if (bus == PCI_DOMAIN) { + new_d->path = ".type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%x }}"; } - cur_parent = $$; - cur_bus = $$; + return new_d; } - devicesorresources END { - cur_parent = $5->parent; - cur_bus = $5->bus; - - fold_in($5); - struct device *d = $5->children; +void alias_siblings(struct device *d) { while (d) { int link = 0; struct device *cmp = d->next_sibling; @@ -289,63 +233,58 @@ } d = d->next_sibling; } -}; +} -resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */ - { - struct resource *r = malloc(sizeof(struct resource)); - memset (r, 0, sizeof(struct resource)); - r->type = $1; - r->index = strtol($2, NULL, 0); - r->base = strtol($4, NULL, 0); - if (cur_parent->res) { - struct resource *head = cur_parent->res; - while (head->next) head = head->next; - head->next = r; - } else { - cur_parent->res = r; +void add_resource(int type, int index, int base) { + struct resource *r = malloc(sizeof(struct resource)); + memset (r, 0, sizeof(struct resource)); + r->type = type; + r->index = index; + r->base = base; + if (cur_parent->res) { + struct resource *head = cur_parent->res; + while (head->next) head = head->next; + head->next = r; + } else { + cur_parent->res = r; + } + cur_parent->rescnt++; +} + +void add_register(char *name, char *val) { + struct reg *r = malloc(sizeof(struct reg)); + memset (r, 0, sizeof(struct reg)); + r->key = name; + r->value = val; + if (cur_parent->reg) { + struct reg *head = cur_parent->reg; + // sorting to be equal to sconfig's behaviour + int sort = strcmp(r->key, head->key); + if (sort == 0) { + printf("ERROR: duplicate 'register' key.\n"); + exit(1); } - cur_parent->rescnt++; - } - ; - -registers: REGISTER STRING /* == regname */ EQUALS STRING /* == regval */ - { - struct reg *r = malloc(sizeof(struct reg)); - memset (r, 0, sizeof(struct reg)); - r->key = $2; - r->value = $4; - if (cur_parent->reg) { - struct reg *head = cur_parent->reg; - // sorting to be equal to sconfig's behaviour - int sort = strcmp(r->key, head->key); - if (sort == 0) { - printf("ERROR: duplicate 'register' key.\n"); - exit(1); - } - if (sort<0) { - r->next = head; - cur_parent->reg = r; - } else { - while ((head->next) && (strcmp(head->next->key, r->key)<0)) head = head->next; - r->next = head->next; - head->next = r; - } - } else { + if (sort<0) { + r->next = head; cur_parent->reg = r; + } else { + while ((head->next) && (strcmp(head->next->key, r->key)<0)) head = head->next; + r->next = head->next; + head->next = r; } + } else { + cur_parent->reg = r; } - ; +} -%% -void pass0(FILE *fil, struct device *ptr) { +static void pass0(FILE *fil, struct device *ptr) { if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) fprintf(fil, "struct device %s;\n", ptr->name); if ((ptr->type == device) && (ptr->id != 0) && ptr->used) fprintf(fil, "struct device %s;\n", ptr->aliased_name); } -void pass1(FILE *fil, struct device *ptr) { +static void pass1(FILE *fil, struct device *ptr) { if (!ptr->used && (ptr->type == device)) { fprintf(fil, "struct device %s = {\n", ptr->name); fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); @@ -422,36 +361,13 @@ } } -void walk_device_tree(FILE *fil, struct device *ptr, void (*func)(FILE *, struct device*), struct device *chips) { +static void walk_device_tree(FILE *fil, struct device *ptr, void (*func)(FILE *, struct device*), struct device *chips) { do { func(fil, ptr); ptr = ptr->next_sibling; } while (ptr); } -struct device mainboard = { - .name = "mainboard", - .name_underscore = "mainboard", - .id = 0, - .chip = &mainboard, - .type = chip, - .chiph_exists = 1, - .children = &root -}; - -struct device root = { - .name = "dev_root", - .name_underscore = "dev_root", - .id = 0, - .chip = &mainboard, - .type = device, - .path = " .type = DEVICE_PATH_ROOT ", - .ops = "&default_dev_ops_root", - .parent = &root, - .bus = &root, - .enabled = 1 -}; - int main(int argc, char** argv) { if (argc != 3) { printf("usage: sconfig vendor/mainboard outputdir\n"); Copied and modified: trunk/util/sconfig/sconfig.h (from r5522, trunk/util/sconfig/sconfig.y) ============================================================================== --- trunk/util/sconfig/sconfig.y Wed May 5 00:30:33 2010 (r5522, copy source) +++ trunk/util/sconfig/sconfig.h Wed May 5 13:19:50 2010 (r5523) @@ -1,4 +1,3 @@ -%{ /* * sconfig, coreboot device tree compiler * @@ -73,429 +72,22 @@ struct device *chip; struct resource *res; struct reg *reg; -} *head, *lastdev, *cur_parent, *cur_bus, root; +}; + +extern struct device *cur_parent, *cur_bus; struct header; struct header { char *name; struct header *next; -} headers; - -int devcount = 0; - -struct device *new_dev() { - struct device *dev = malloc(sizeof(struct device)); - memset(dev, 0, sizeof(struct device)); - dev->id = ++devcount; - dev->parent = cur_parent; - dev->bus = cur_bus; - head->next = dev; - head = dev; - return dev; -} - -int device_match(struct device *a, struct device *b) { - if ((a->bustype == b->bustype) && (a->bus == b->bus) && (a->path_a == b->path_a) && (a->path_b == b->path_b)) - return 1; - return 0; -} - -void fold_in(struct device *parent) { - struct device *child = parent->children; - struct device *latest = 0; - while (child != latest) { - if (child->children) { - if (!latest) latest = child->children; - parent->latestchild->next_sibling = child->children; - parent->latestchild = child->latestchild; - } - child = child->next_sibling; - } -} - -int yywrap(void) { - return 1; -} - -void yyerror (char const *str) -{ - fprintf (stderr, "%s\n", str); -} -%} -%union { - struct device *device; - char *string; - int number; -} -%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER -%% -devtree: devchip { - root.next_sibling = root.children; - root.next_sibling->next_sibling = root.next_sibling->children; - - struct device *dev = &root; - while (dev) { - /* skip "chip" elements in children chain */ - while (dev->children && (dev->children->type == chip)) dev->children = dev->children->children; - /* skip "chip" elements and functions of the same device in sibling chain */ - while (dev->sibling && dev->sibling->used) dev->sibling = dev->sibling->sibling; - /* If end of chain, and parent is a chip, move on */ - if (!dev->sibling && (dev->parent->type == chip)) dev->sibling = dev->parent->sibling; - /* skip chips */ - while (dev->sibling && dev->sibling->type == chip) dev->sibling = dev->sibling->children; - /* skip duplicate function elements in nextdev chain */ - while (dev->nextdev && dev->nextdev->used) dev->nextdev = dev->nextdev->nextdev; - dev = dev->next_sibling; - } - }; - -devchip: chip | device ; - -devices: devices devchip | devices registers | ; - -devicesorresources: devicesorresources devchip | devicesorresources resource | ; - -chip: CHIP STRING /* == path */ { - $$ = new_dev(); - $$->chiph_exists = 1; - $$->name = $2; - $$->name_underscore = strdup($$->name); - char *c; - for (c = $$->name_underscore; *c; c++) { - if (*c == '/') *c = '_'; - if (*c == '-') *c = '_'; - } - $$->type = chip; - $$->chip = $$; - - struct stat st; - char *chip_h = malloc(strlen($2)+12); - sprintf(chip_h, "src/%s/chip.h", $2); - if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) - $$->chiph_exists = 0; - - if (cur_parent->latestchild) { - cur_parent->latestchild->next_sibling = $$; - cur_parent->latestchild->sibling = $$; - } - cur_parent->latestchild = $$; - if (!cur_parent->children) - cur_parent->children = $$; - - cur_parent = $$; -} - devices END { - cur_parent = $3->parent; - - fold_in($3); - - if ($3->chiph_exists) { - int include_exists = 0; - struct header *h = &headers; - while (h->next) { - int result = strcmp($3->name, h->next->name); - if (result == 0) { - include_exists = 1; - break; - } - if (result < 0) break; - h = h->next; - } - if (!include_exists) { - struct header *tmp = h->next; - h->next = malloc(sizeof(struct header)); - memset(h->next, 0, sizeof(struct header)); - h->next->name = $3->name; - h->next->next = tmp; - break; - } - } -}; - -device: DEVICE BUS NUMBER /* == devnum */ BOOL { - $$ = new_dev(); - $$->bustype = $2; - - char *tmp; - $$->path_a = strtol(strdup($3), &tmp, 16); - if (*tmp == '.') { - tmp++; - $$->path_b = strtol(tmp, NULL, 16); - } - - char *name = malloc(10); - sprintf(name, "_dev%d", $$->id); - $$->name = name; - $$->name_underscore = name; // shouldn't be necessary, but avoid 0-ptr - $$->type = device; - $$->enabled = $4; - $$->chip = $$->parent->chip; - - if (cur_parent->latestchild) { - cur_parent->latestchild->next_sibling = $$; - cur_parent->latestchild->sibling = $$; - } - cur_parent->latestchild = $$; - if (!cur_parent->children) - cur_parent->children = $$; - - lastdev->nextdev = $$; - lastdev = $$; - if ($2 == PCI) { - $$->path = ".type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%x,%d)}}"; - } - if ($2 == PNP) { - $$->path = ".type=DEVICE_PATH_PNP,{.pnp={ .port = 0x%x, .device = 0x%x }}"; - } - if ($2 == I2C) { - $$->path = ".type=DEVICE_PATH_I2C,{.i2c={ .device = 0x%x }}"; - } - if ($2 == APIC) { - $$->path = ".type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x%x }}"; - } - if ($2 == APIC_CLUSTER) { - $$->path = ".type=DEVICE_PATH_APIC_CLUSTER,{.apic_cluster={ .cluster = 0x%x }}"; - } - if ($2 == PCI_DOMAIN) { - $$->path = ".type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%x }}"; - } - cur_parent = $$; - cur_bus = $$; -} - devicesorresources END { - cur_parent = $5->parent; - cur_bus = $5->bus; - - fold_in($5); - - struct device *d = $5->children; - while (d) { - int link = 0; - struct device *cmp = d->next_sibling; - while (cmp && (cmp->bus == d->bus) && (cmp->path_a == d->path_a) && (cmp->path_b == d->path_b)) { - if (cmp->type==device && !cmp->used) { - if (device_match(d, cmp)) { - d->multidev = 1; - - cmp->aliased_name = malloc(12); - sprintf(cmp->aliased_name, "_dev%d", cmp->id); - cmp->id = d->id; - cmp->name = d->name; - cmp->used = 1; - cmp->link = ++link; - } - } - cmp = cmp->next_sibling; - } - d = d->next_sibling; - } }; -resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */ - { - struct resource *r = malloc(sizeof(struct resource)); - memset (r, 0, sizeof(struct resource)); - r->type = $1; - r->index = strtol($2, NULL, 0); - r->base = strtol($4, NULL, 0); - if (cur_parent->res) { - struct resource *head = cur_parent->res; - while (head->next) head = head->next; - head->next = r; - } else { - cur_parent->res = r; - } - cur_parent->rescnt++; - } - ; - -registers: REGISTER STRING /* == regname */ EQUALS STRING /* == regval */ - { - struct reg *r = malloc(sizeof(struct reg)); - memset (r, 0, sizeof(struct reg)); - r->key = $2; - r->value = $4; - if (cur_parent->reg) { - struct reg *head = cur_parent->reg; - // sorting to be equal to sconfig's behaviour - int sort = strcmp(r->key, head->key); - if (sort == 0) { - printf("ERROR: duplicate 'register' key.\n"); - exit(1); - } - if (sort<0) { - r->next = head; - cur_parent->reg = r; - } else { - while ((head->next) && (strcmp(head->next->key, r->key)<0)) head = head->next; - r->next = head->next; - head->next = r; - } - } else { - cur_parent->reg = r; - } - } - ; - -%% -void pass0(FILE *fil, struct device *ptr) { - if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) - fprintf(fil, "struct device %s;\n", ptr->name); - if ((ptr->type == device) && (ptr->id != 0) && ptr->used) - fprintf(fil, "struct device %s;\n", ptr->aliased_name); -} - -void pass1(FILE *fil, struct device *ptr) { - if (!ptr->used && (ptr->type == device)) { - fprintf(fil, "struct device %s = {\n", ptr->name); - fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); - fprintf(fil, "\t.bus = &%s.link[%d],\n", ptr->bus->name, ptr->bus->link); - fprintf(fil, "\t.path = {"); - fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); - fprintf(fil, "},\n"); - fprintf(fil, "\t.enabled = %d,\n", ptr->enabled); - fprintf(fil, "\t.on_mainboard = 1,\n"); - if (ptr->rescnt > 0) { - fprintf(fil, "\t.resources = %d,\n", ptr->rescnt); - fprintf(fil, "\t.resource = {\n"); - struct resource *r = ptr->res; - while (r) { - fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_"); - if (r->type == IRQ) fprintf(fil, "IRQ"); - if (r->type == DRQ) fprintf(fil, "DRQ"); - if (r->type == IO) fprintf(fil, "IO"); - fprintf(fil, ", .index=0x%x, .base=0x%x},\n", r->index, r->base); - r = r->next; - } - fprintf(fil, "\t },\n"); - } - int link = 0; - fprintf(fil, "\t.link = {\n"); - if (ptr->multidev) { - struct device *d = ptr; - while (d) { - if (device_match(d, ptr)) { - fprintf(fil, "\t\t[%d] = {\n", d->link); - fprintf(fil, "\t\t\t.link = %d,\n", d->link); - fprintf(fil, "\t\t\t.dev = &%s,\n", d->name); - if (d->children) - fprintf(fil, "\t\t\t.children = &%s,\n", d->children->name); - fprintf(fil, "\t\t},\n"); - link++; - } - d = d->next_sibling; - } - } else { - if (ptr->children) { - fprintf(fil, "\t\t[0] = {\n"); - fprintf(fil, "\t\t\t.link = 0,\n"); - fprintf(fil, "\t\t\t.dev = &%s,\n", ptr->name); - fprintf(fil, "\t\t\t.children = &%s,\n", ptr->children->name); - fprintf(fil, "\t\t},\n"); - link++; - } - } - fprintf(fil, "\t},\n"); - fprintf(fil, "\t.links = %d,\n", link); - if (ptr->sibling) - fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); - if (ptr->chip->chiph_exists) { - fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); - fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); - } - if (ptr->nextdev) - fprintf(fil, "\t.next=&%s\n", ptr->nextdev->name); - fprintf(fil, "};\n"); - } - if ((ptr->type == chip) && (ptr->chiph_exists)) { - if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", ptr->name_underscore, ptr->name_underscore, ptr->id); - struct reg *r = ptr->reg; - while (r) { - fprintf(fil, "\t.%s = %s,\n", r->key, r->value); - r = r->next; - } - fprintf(fil, "};\n\n"); - } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", ptr->name_underscore, ptr->name_underscore, ptr->id); - } - } -} - -void walk_device_tree(FILE *fil, struct device *ptr, void (*func)(FILE *, struct device*), struct device *chips) { - do { - func(fil, ptr); - ptr = ptr->next_sibling; - } while (ptr); -} - -struct device mainboard = { - .name = "mainboard", - .name_underscore = "mainboard", - .id = 0, - .chip = &mainboard, - .type = chip, - .chiph_exists = 1, - .children = &root -}; - -struct device root = { - .name = "dev_root", - .name_underscore = "dev_root", - .id = 0, - .chip = &mainboard, - .type = device, - .path = " .type = DEVICE_PATH_ROOT ", - .ops = "&default_dev_ops_root", - .parent = &root, - .bus = &root, - .enabled = 1 -}; - -int main(int argc, char** argv) { - if (argc != 3) { - printf("usage: sconfig vendor/mainboard outputdir\n"); - return 1; - } - char *mainboard=argv[1]; - char *outputdir=argv[2]; - char *devtree=malloc(strlen(mainboard)+30); - char *outputc=malloc(strlen(outputdir)+10); - sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard); - sprintf(outputc, "%s/static.c", outputdir); - - headers.next = malloc(sizeof(struct header)); - headers.next->name = malloc(strlen(mainboard)+12); - headers.next->next = 0; - sprintf(headers.next->name, "mainboard/%s", mainboard); - - FILE *filec = fopen(devtree, "r"); - yyrestart(filec); - - FILE *staticc = fopen(outputc, "w"); - - cur_bus = cur_parent = lastdev = head = &root; - yyparse(); - fclose(filec); - - if ((head->type == chip) && (!head->chiph_exists)) { - struct device *tmp = head; - head = &root; - while (head->next != tmp) head = head->next; - } - - fprintf(staticc, "#include \n"); - fprintf(staticc, "#include \n"); - struct header *h = &headers; - while (h->next) { - h = h->next; - fprintf(staticc, "#include \"%s/chip.h\"\n", h->name); - } - fprintf(staticc, "\n/* pass 0 */\n"); - walk_device_tree(staticc, &root, pass0, NULL); - fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device **last_dev_p = &%s.next;\n", lastdev->name); - walk_device_tree(staticc, &root, pass1, NULL); +void fold_in(struct device *parent); - fclose(staticc); - return 0; -} +void postprocess_devtree(void); +struct device *new_chip(char *path); +void add_header(struct device *dev); +struct device *new_device(const int bus, const char *devnum, int enabled); +void alias_siblings(struct device *d); +void add_resource(int type, int index, int base); +void add_register(char *name, char *val); Modified: trunk/util/sconfig/sconfig.tab.c_shipped ============================================================================== --- trunk/util/sconfig/sconfig.tab.c_shipped Wed May 5 00:30:33 2010 (r5522) +++ trunk/util/sconfig/sconfig.tab.c_shipped Wed May 5 13:19:50 2010 (r5523) @@ -2,20 +2,20 @@ /* A Bison parser, made by GNU Bison 2.4.1. */ /* Skeleton implementation for Bison's Yacc-like parsers in C - + Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. - + This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program. If not, see . */ @@ -28,7 +28,7 @@ special exception, which will cause the skeleton and the resulting Bison output files to be licensed under the GNU General Public License without this special exception. - + This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ @@ -88,108 +88,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ -#include -#include -#include -#include -#include -#include -#include - -enum devtype { chip, device }; - -struct resource; -struct resource { - int type; - int index; - int base; - struct resource *next; -}; - -struct reg; -struct reg { - char *key; - char *value; - struct reg *next; -}; - -struct device; -struct device { - int id; - int enabled; - int used; - int multidev; - int link; - int rescnt; - int chiph_exists; - char *ops; - char *name; - char *aliased_name; - char *name_underscore; - char *path; - int path_a; - int path_b; - int bustype; - enum devtype type; - struct device *parent; - struct device *bus; - struct device *next; - struct device *nextdev; - struct device *children; - struct device *latestchild; - struct device *next_sibling; - struct device *sibling; - struct device *chip; - struct resource *res; - struct reg *reg; -} *head, *lastdev, *cur_parent, *cur_bus, root; - -struct header; -struct header { - char *name; - struct header *next; -} headers; - -int devcount = 0; - -struct device *new_dev() { - struct device *dev = malloc(sizeof(struct device)); - memset(dev, 0, sizeof(struct device)); - dev->id = ++devcount; - dev->parent = cur_parent; - dev->bus = cur_bus; - head->next = dev; - head = dev; - return dev; -} +#include "sconfig.h" -int device_match(struct device *a, struct device *b) { - if ((a->bustype == b->bustype) && (a->bus == b->bus) && (a->path_a == b->path_a) && (a->path_b == b->path_b)) - return 1; - return 0; -} +struct device *cur_parent, *cur_bus; -void fold_in(struct device *parent) { - struct device *child = parent->children; - struct device *latest = 0; - while (child != latest) { - if (child->children) { - if (!latest) latest = child->children; - parent->latestchild->next_sibling = child->children; - parent->latestchild = child->latestchild; - } - child = child->next_sibling; - } -} - -int yywrap(void) { - return 1; -} - -void yyerror (char const *str) -{ - fprintf (stderr, "%s\n", str); -} @@ -549,10 +451,10 @@ }; /* YYRLINE[YYN] -- source line where rule number YYN was defined. */ -static const yytype_uint16 yyrline[] = +static const yytype_uint8 yyrline[] = { - 0, 132, 132, 152, 152, 154, 154, 154, 156, 156, - 156, 158, 158, 215, 215, 294, 312 + 0, 34, 34, 36, 36, 38, 38, 38, 40, 40, + 40, 42, 42, 52, 52, 64, 67 }; #endif @@ -1466,56 +1368,13 @@ { case 2: - { - root.next_sibling = root.children; - root.next_sibling->next_sibling = root.next_sibling->children; - - struct device *dev = &root; - while (dev) { - /* skip "chip" elements in children chain */ - while (dev->children && (dev->children->type == chip)) dev->children = dev->children->children; - /* skip "chip" elements and functions of the same device in sibling chain */ - while (dev->sibling && dev->sibling->used) dev->sibling = dev->sibling->sibling; - /* If end of chain, and parent is a chip, move on */ - if (!dev->sibling && (dev->parent->type == chip)) dev->sibling = dev->parent->sibling; - /* skip chips */ - while (dev->sibling && dev->sibling->type == chip) dev->sibling = dev->sibling->children; - /* skip duplicate function elements in nextdev chain */ - while (dev->nextdev && dev->nextdev->used) dev->nextdev = dev->nextdev->nextdev; - dev = dev->next_sibling; - } - ;} + { postprocess_devtree(); ;} break; case 11: { - (yyval.device) = new_dev(); - (yyval.device)->chiph_exists = 1; - (yyval.device)->name = (yyvsp[(2) - (2)].string); - (yyval.device)->name_underscore = strdup((yyval.device)->name); - char *c; - for (c = (yyval.device)->name_underscore; *c; c++) { - if (*c == '/') *c = '_'; - if (*c == '-') *c = '_'; - } - (yyval.device)->type = chip; - (yyval.device)->chip = (yyval.device); - - struct stat st; - char *chip_h = malloc(strlen((yyvsp[(2) - (2)].string))+12); - sprintf(chip_h, "src/%s/chip.h", (yyvsp[(2) - (2)].string)); - if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) - (yyval.device)->chiph_exists = 0; - - if (cur_parent->latestchild) { - cur_parent->latestchild->next_sibling = (yyval.device); - cur_parent->latestchild->sibling = (yyval.device); - } - cur_parent->latestchild = (yyval.device); - if (!cur_parent->children) - cur_parent->children = (yyval.device); - + (yyval.device) = new_chip((yyvsp[(2) - (2)].string)); cur_parent = (yyval.device); ;} break; @@ -1524,82 +1383,15 @@ { cur_parent = (yyvsp[(3) - (5)].device)->parent; - fold_in((yyvsp[(3) - (5)].device)); - - if ((yyvsp[(3) - (5)].device)->chiph_exists) { - int include_exists = 0; - struct header *h = &headers; - while (h->next) { - int result = strcmp((yyvsp[(3) - (5)].device)->name, h->next->name); - if (result == 0) { - include_exists = 1; - break; - } - if (result < 0) break; - h = h->next; - } - if (!include_exists) { - struct header *tmp = h->next; - h->next = malloc(sizeof(struct header)); - memset(h->next, 0, sizeof(struct header)); - h->next->name = (yyvsp[(3) - (5)].device)->name; - h->next->next = tmp; - break; - } - } + add_header((yyvsp[(3) - (5)].device)); ;} break; case 13: { - (yyval.device) = new_dev(); - (yyval.device)->bustype = (yyvsp[(2) - (4)].number); - - char *tmp; - (yyval.device)->path_a = strtol(strdup((yyvsp[(3) - (4)].string)), &tmp, 16); - if (*tmp == '.') { - tmp++; - (yyval.device)->path_b = strtol(tmp, NULL, 16); - } - - char *name = malloc(10); - sprintf(name, "_dev%d", (yyval.device)->id); - (yyval.device)->name = name; - (yyval.device)->name_underscore = name; // shouldn't be necessary, but avoid 0-ptr - (yyval.device)->type = device; - (yyval.device)->enabled = (yyvsp[(4) - (4)].number); - (yyval.device)->chip = (yyval.device)->parent->chip; - - if (cur_parent->latestchild) { - cur_parent->latestchild->next_sibling = (yyval.device); - cur_parent->latestchild->sibling = (yyval.device); - } - cur_parent->latestchild = (yyval.device); - if (!cur_parent->children) - cur_parent->children = (yyval.device); - - lastdev->nextdev = (yyval.device); - lastdev = (yyval.device); - if ((yyvsp[(2) - (4)].number) == PCI) { - (yyval.device)->path = ".type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%x,%d)}}"; - } - if ((yyvsp[(2) - (4)].number) == PNP) { - (yyval.device)->path = ".type=DEVICE_PATH_PNP,{.pnp={ .port = 0x%x, .device = 0x%x }}"; - } - if ((yyvsp[(2) - (4)].number) == I2C) { - (yyval.device)->path = ".type=DEVICE_PATH_I2C,{.i2c={ .device = 0x%x }}"; - } - if ((yyvsp[(2) - (4)].number) == APIC) { - (yyval.device)->path = ".type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x%x }}"; - } - if ((yyvsp[(2) - (4)].number) == APIC_CLUSTER) { - (yyval.device)->path = ".type=DEVICE_PATH_APIC_CLUSTER,{.apic_cluster={ .cluster = 0x%x }}"; - } - if ((yyvsp[(2) - (4)].number) == PCI_DOMAIN) { - (yyval.device)->path = ".type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%x }}"; - } + (yyval.device) = new_device((yyvsp[(2) - (4)].number), (yyvsp[(3) - (4)].string), (yyvsp[(4) - (4)].number)); cur_parent = (yyval.device); cur_bus = (yyval.device); ;} @@ -1610,79 +1402,19 @@ { cur_parent = (yyvsp[(5) - (7)].device)->parent; cur_bus = (yyvsp[(5) - (7)].device)->bus; - fold_in((yyvsp[(5) - (7)].device)); - - struct device *d = (yyvsp[(5) - (7)].device)->children; - while (d) { - int link = 0; - struct device *cmp = d->next_sibling; - while (cmp && (cmp->bus == d->bus) && (cmp->path_a == d->path_a) && (cmp->path_b == d->path_b)) { - if (cmp->type==device && !cmp->used) { - if (device_match(d, cmp)) { - d->multidev = 1; - - cmp->aliased_name = malloc(12); - sprintf(cmp->aliased_name, "_dev%d", cmp->id); - cmp->id = d->id; - cmp->name = d->name; - cmp->used = 1; - cmp->link = ++link; - } - } - cmp = cmp->next_sibling; - } - d = d->next_sibling; - } + alias_siblings((yyvsp[(5) - (7)].device)->children); ;} break; case 15: - { - struct resource *r = malloc(sizeof(struct resource)); - memset (r, 0, sizeof(struct resource)); - r->type = (yyvsp[(1) - (4)].number); - r->index = strtol((yyvsp[(2) - (4)].string), NULL, 0); - r->base = strtol((yyvsp[(4) - (4)].string), NULL, 0); - if (cur_parent->res) { - struct resource *head = cur_parent->res; - while (head->next) head = head->next; - head->next = r; - } else { - cur_parent->res = r; - } - cur_parent->rescnt++; - ;} + { add_resource((yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); ;} break; case 16: - { - struct reg *r = malloc(sizeof(struct reg)); - memset (r, 0, sizeof(struct reg)); - r->key = (yyvsp[(2) - (4)].string); - r->value = (yyvsp[(4) - (4)].string); - if (cur_parent->reg) { - struct reg *head = cur_parent->reg; - // sorting to be equal to sconfig's behaviour - int sort = strcmp(r->key, head->key); - if (sort == 0) { - printf("ERROR: duplicate 'register' key.\n"); - exit(1); - } - if (sort<0) { - r->next = head; - cur_parent->reg = r; - } else { - while ((head->next) && (strcmp(head->next->key, r->key)<0)) head = head->next; - r->next = head->next; - head->next = r; - } - } else { - cur_parent->reg = r; - } - ;} + { add_register((yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); ;} break; @@ -1898,165 +1630,4 @@ -void pass0(FILE *fil, struct device *ptr) { - if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) - fprintf(fil, "struct device %s;\n", ptr->name); - if ((ptr->type == device) && (ptr->id != 0) && ptr->used) - fprintf(fil, "struct device %s;\n", ptr->aliased_name); -} - -void pass1(FILE *fil, struct device *ptr) { - if (!ptr->used && (ptr->type == device)) { - fprintf(fil, "struct device %s = {\n", ptr->name); - fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); - fprintf(fil, "\t.bus = &%s.link[%d],\n", ptr->bus->name, ptr->bus->link); - fprintf(fil, "\t.path = {"); - fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); - fprintf(fil, "},\n"); - fprintf(fil, "\t.enabled = %d,\n", ptr->enabled); - fprintf(fil, "\t.on_mainboard = 1,\n"); - if (ptr->rescnt > 0) { - fprintf(fil, "\t.resources = %d,\n", ptr->rescnt); - fprintf(fil, "\t.resource = {\n"); - struct resource *r = ptr->res; - while (r) { - fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_"); - if (r->type == IRQ) fprintf(fil, "IRQ"); - if (r->type == DRQ) fprintf(fil, "DRQ"); - if (r->type == IO) fprintf(fil, "IO"); - fprintf(fil, ", .index=0x%x, .base=0x%x},\n", r->index, r->base); - r = r->next; - } - fprintf(fil, "\t },\n"); - } - int link = 0; - fprintf(fil, "\t.link = {\n"); - if (ptr->multidev) { - struct device *d = ptr; - while (d) { - if (device_match(d, ptr)) { - fprintf(fil, "\t\t[%d] = {\n", d->link); - fprintf(fil, "\t\t\t.link = %d,\n", d->link); - fprintf(fil, "\t\t\t.dev = &%s,\n", d->name); - if (d->children) - fprintf(fil, "\t\t\t.children = &%s,\n", d->children->name); - fprintf(fil, "\t\t},\n"); - link++; - } - d = d->next_sibling; - } - } else { - if (ptr->children) { - fprintf(fil, "\t\t[0] = {\n"); - fprintf(fil, "\t\t\t.link = 0,\n"); - fprintf(fil, "\t\t\t.dev = &%s,\n", ptr->name); - fprintf(fil, "\t\t\t.children = &%s,\n", ptr->children->name); - fprintf(fil, "\t\t},\n"); - link++; - } - } - fprintf(fil, "\t},\n"); - fprintf(fil, "\t.links = %d,\n", link); - if (ptr->sibling) - fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); - if (ptr->chip->chiph_exists) { - fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); - fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); - } - if (ptr->nextdev) - fprintf(fil, "\t.next=&%s\n", ptr->nextdev->name); - fprintf(fil, "};\n"); - } - if ((ptr->type == chip) && (ptr->chiph_exists)) { - if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", ptr->name_underscore, ptr->name_underscore, ptr->id); - struct reg *r = ptr->reg; - while (r) { - fprintf(fil, "\t.%s = %s,\n", r->key, r->value); - r = r->next; - } - fprintf(fil, "};\n\n"); - } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", ptr->name_underscore, ptr->name_underscore, ptr->id); - } - } -} - -void walk_device_tree(FILE *fil, struct device *ptr, void (*func)(FILE *, struct device*), struct device *chips) { - do { - func(fil, ptr); - ptr = ptr->next_sibling; - } while (ptr); -} - -struct device mainboard = { - .name = "mainboard", - .name_underscore = "mainboard", - .id = 0, - .chip = &mainboard, - .type = chip, - .chiph_exists = 1, - .children = &root -}; - -struct device root = { - .name = "dev_root", - .name_underscore = "dev_root", - .id = 0, - .chip = &mainboard, - .type = device, - .path = " .type = DEVICE_PATH_ROOT ", - .ops = "&default_dev_ops_root", - .parent = &root, - .bus = &root, - .enabled = 1 -}; - -int main(int argc, char** argv) { - if (argc != 3) { - printf("usage: sconfig vendor/mainboard outputdir\n"); - return 1; - } - char *mainboard=argv[1]; - char *outputdir=argv[2]; - char *devtree=malloc(strlen(mainboard)+30); - char *outputc=malloc(strlen(outputdir)+10); - sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard); - sprintf(outputc, "%s/static.c", outputdir); - - headers.next = malloc(sizeof(struct header)); - headers.next->name = malloc(strlen(mainboard)+12); - headers.next->next = 0; - sprintf(headers.next->name, "mainboard/%s", mainboard); - - FILE *filec = fopen(devtree, "r"); - yyrestart(filec); - - FILE *staticc = fopen(outputc, "w"); - - cur_bus = cur_parent = lastdev = head = &root; - yyparse(); - fclose(filec); - - if ((head->type == chip) && (!head->chiph_exists)) { - struct device *tmp = head; - head = &root; - while (head->next != tmp) head = head->next; - } - - fprintf(staticc, "#include \n"); - fprintf(staticc, "#include \n"); - struct header *h = &headers; - while (h->next) { - h = h->next; - fprintf(staticc, "#include \"%s/chip.h\"\n", h->name); - } - fprintf(staticc, "\n/* pass 0 */\n"); - walk_device_tree(staticc, &root, pass0, NULL); - fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device **last_dev_p = &%s.next;\n", lastdev->name); - walk_device_tree(staticc, &root, pass1, NULL); - - fclose(staticc); - return 0; -} Modified: trunk/util/sconfig/sconfig.tab.h_shipped ============================================================================== --- trunk/util/sconfig/sconfig.tab.h_shipped Wed May 5 00:30:33 2010 (r5522) +++ trunk/util/sconfig/sconfig.tab.h_shipped Wed May 5 13:19:50 2010 (r5523) @@ -2,20 +2,20 @@ /* A Bison parser, made by GNU Bison 2.4.1. */ /* Skeleton interface for Bison's Yacc-like parsers in C - + Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. - + This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program. If not, see . */ @@ -28,7 +28,7 @@ special exception, which will cause the skeleton and the resulting Bison output files to be licensed under the GNU General Public License without this special exception. - + This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ Modified: trunk/util/sconfig/sconfig.y ============================================================================== --- trunk/util/sconfig/sconfig.y Wed May 5 00:30:33 2010 (r5522) +++ trunk/util/sconfig/sconfig.y Wed May 5 13:19:50 2010 (r5523) @@ -19,108 +19,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ -#include -#include -#include -#include -#include -#include -#include - -enum devtype { chip, device }; - -struct resource; -struct resource { - int type; - int index; - int base; - struct resource *next; -}; - -struct reg; -struct reg { - char *key; - char *value; - struct reg *next; -}; - -struct device; -struct device { - int id; - int enabled; - int used; - int multidev; - int link; - int rescnt; - int chiph_exists; - char *ops; - char *name; - char *aliased_name; - char *name_underscore; - char *path; - int path_a; - int path_b; - int bustype; - enum devtype type; - struct device *parent; - struct device *bus; - struct device *next; - struct device *nextdev; - struct device *children; - struct device *latestchild; - struct device *next_sibling; - struct device *sibling; - struct device *chip; - struct resource *res; - struct reg *reg; -} *head, *lastdev, *cur_parent, *cur_bus, root; - -struct header; -struct header { - char *name; - struct header *next; -} headers; - -int devcount = 0; - -struct device *new_dev() { - struct device *dev = malloc(sizeof(struct device)); - memset(dev, 0, sizeof(struct device)); - dev->id = ++devcount; - dev->parent = cur_parent; - dev->bus = cur_bus; - head->next = dev; - head = dev; - return dev; -} - -int device_match(struct device *a, struct device *b) { - if ((a->bustype == b->bustype) && (a->bus == b->bus) && (a->path_a == b->path_a) && (a->path_b == b->path_b)) - return 1; - return 0; -} +#include "sconfig.h" -void fold_in(struct device *parent) { - struct device *child = parent->children; - struct device *latest = 0; - while (child != latest) { - if (child->children) { - if (!latest) latest = child->children; - parent->latestchild->next_sibling = child->children; - parent->latestchild = child->latestchild; - } - child = child->next_sibling; - } -} +struct device *cur_parent, *cur_bus; -int yywrap(void) { - return 1; -} - -void yyerror (char const *str) -{ - fprintf (stderr, "%s\n", str); -} %} %union { struct device *device; @@ -129,25 +31,7 @@ } %token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER %% -devtree: devchip { - root.next_sibling = root.children; - root.next_sibling->next_sibling = root.next_sibling->children; - - struct device *dev = &root; - while (dev) { - /* skip "chip" elements in children chain */ - while (dev->children && (dev->children->type == chip)) dev->children = dev->children->children; - /* skip "chip" elements and functions of the same device in sibling chain */ - while (dev->sibling && dev->sibling->used) dev->sibling = dev->sibling->sibling; - /* If end of chain, and parent is a chip, move on */ - if (!dev->sibling && (dev->parent->type == chip)) dev->sibling = dev->parent->sibling; - /* skip chips */ - while (dev->sibling && dev->sibling->type == chip) dev->sibling = dev->sibling->children; - /* skip duplicate function elements in nextdev chain */ - while (dev->nextdev && dev->nextdev->used) dev->nextdev = dev->nextdev->nextdev; - dev = dev->next_sibling; - } - }; +devtree: devchip { postprocess_devtree(); } ; devchip: chip | device ; @@ -156,346 +40,31 @@ devicesorresources: devicesorresources devchip | devicesorresources resource | ; chip: CHIP STRING /* == path */ { - $$ = new_dev(); - $$->chiph_exists = 1; - $$->name = $2; - $$->name_underscore = strdup($$->name); - char *c; - for (c = $$->name_underscore; *c; c++) { - if (*c == '/') *c = '_'; - if (*c == '-') *c = '_'; - } - $$->type = chip; - $$->chip = $$; - - struct stat st; - char *chip_h = malloc(strlen($2)+12); - sprintf(chip_h, "src/%s/chip.h", $2); - if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) - $$->chiph_exists = 0; - - if (cur_parent->latestchild) { - cur_parent->latestchild->next_sibling = $$; - cur_parent->latestchild->sibling = $$; - } - cur_parent->latestchild = $$; - if (!cur_parent->children) - cur_parent->children = $$; - + $$ = new_chip($2); cur_parent = $$; } devices END { cur_parent = $3->parent; - fold_in($3); - - if ($3->chiph_exists) { - int include_exists = 0; - struct header *h = &headers; - while (h->next) { - int result = strcmp($3->name, h->next->name); - if (result == 0) { - include_exists = 1; - break; - } - if (result < 0) break; - h = h->next; - } - if (!include_exists) { - struct header *tmp = h->next; - h->next = malloc(sizeof(struct header)); - memset(h->next, 0, sizeof(struct header)); - h->next->name = $3->name; - h->next->next = tmp; - break; - } - } + add_header($3); }; device: DEVICE BUS NUMBER /* == devnum */ BOOL { - $$ = new_dev(); - $$->bustype = $2; - - char *tmp; - $$->path_a = strtol(strdup($3), &tmp, 16); - if (*tmp == '.') { - tmp++; - $$->path_b = strtol(tmp, NULL, 16); - } - - char *name = malloc(10); - sprintf(name, "_dev%d", $$->id); - $$->name = name; - $$->name_underscore = name; // shouldn't be necessary, but avoid 0-ptr - $$->type = device; - $$->enabled = $4; - $$->chip = $$->parent->chip; - - if (cur_parent->latestchild) { - cur_parent->latestchild->next_sibling = $$; - cur_parent->latestchild->sibling = $$; - } - cur_parent->latestchild = $$; - if (!cur_parent->children) - cur_parent->children = $$; - - lastdev->nextdev = $$; - lastdev = $$; - if ($2 == PCI) { - $$->path = ".type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%x,%d)}}"; - } - if ($2 == PNP) { - $$->path = ".type=DEVICE_PATH_PNP,{.pnp={ .port = 0x%x, .device = 0x%x }}"; - } - if ($2 == I2C) { - $$->path = ".type=DEVICE_PATH_I2C,{.i2c={ .device = 0x%x }}"; - } - if ($2 == APIC) { - $$->path = ".type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x%x }}"; - } - if ($2 == APIC_CLUSTER) { - $$->path = ".type=DEVICE_PATH_APIC_CLUSTER,{.apic_cluster={ .cluster = 0x%x }}"; - } - if ($2 == PCI_DOMAIN) { - $$->path = ".type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%x }}"; - } + $$ = new_device($2, $3, $4); cur_parent = $$; cur_bus = $$; } devicesorresources END { cur_parent = $5->parent; cur_bus = $5->bus; - fold_in($5); - - struct device *d = $5->children; - while (d) { - int link = 0; - struct device *cmp = d->next_sibling; - while (cmp && (cmp->bus == d->bus) && (cmp->path_a == d->path_a) && (cmp->path_b == d->path_b)) { - if (cmp->type==device && !cmp->used) { - if (device_match(d, cmp)) { - d->multidev = 1; - - cmp->aliased_name = malloc(12); - sprintf(cmp->aliased_name, "_dev%d", cmp->id); - cmp->id = d->id; - cmp->name = d->name; - cmp->used = 1; - cmp->link = ++link; - } - } - cmp = cmp->next_sibling; - } - d = d->next_sibling; - } + alias_siblings($5->children); }; resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */ - { - struct resource *r = malloc(sizeof(struct resource)); - memset (r, 0, sizeof(struct resource)); - r->type = $1; - r->index = strtol($2, NULL, 0); - r->base = strtol($4, NULL, 0); - if (cur_parent->res) { - struct resource *head = cur_parent->res; - while (head->next) head = head->next; - head->next = r; - } else { - cur_parent->res = r; - } - cur_parent->rescnt++; - } - ; + { add_resource($1, strtol($2, NULL, 0), strtol($4, NULL, 0)); } ; registers: REGISTER STRING /* == regname */ EQUALS STRING /* == regval */ - { - struct reg *r = malloc(sizeof(struct reg)); - memset (r, 0, sizeof(struct reg)); - r->key = $2; - r->value = $4; - if (cur_parent->reg) { - struct reg *head = cur_parent->reg; - // sorting to be equal to sconfig's behaviour - int sort = strcmp(r->key, head->key); - if (sort == 0) { - printf("ERROR: duplicate 'register' key.\n"); - exit(1); - } - if (sort<0) { - r->next = head; - cur_parent->reg = r; - } else { - while ((head->next) && (strcmp(head->next->key, r->key)<0)) head = head->next; - r->next = head->next; - head->next = r; - } - } else { - cur_parent->reg = r; - } - } - ; + { add_register($2, $4); } ; %% -void pass0(FILE *fil, struct device *ptr) { - if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) - fprintf(fil, "struct device %s;\n", ptr->name); - if ((ptr->type == device) && (ptr->id != 0) && ptr->used) - fprintf(fil, "struct device %s;\n", ptr->aliased_name); -} - -void pass1(FILE *fil, struct device *ptr) { - if (!ptr->used && (ptr->type == device)) { - fprintf(fil, "struct device %s = {\n", ptr->name); - fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); - fprintf(fil, "\t.bus = &%s.link[%d],\n", ptr->bus->name, ptr->bus->link); - fprintf(fil, "\t.path = {"); - fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); - fprintf(fil, "},\n"); - fprintf(fil, "\t.enabled = %d,\n", ptr->enabled); - fprintf(fil, "\t.on_mainboard = 1,\n"); - if (ptr->rescnt > 0) { - fprintf(fil, "\t.resources = %d,\n", ptr->rescnt); - fprintf(fil, "\t.resource = {\n"); - struct resource *r = ptr->res; - while (r) { - fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_"); - if (r->type == IRQ) fprintf(fil, "IRQ"); - if (r->type == DRQ) fprintf(fil, "DRQ"); - if (r->type == IO) fprintf(fil, "IO"); - fprintf(fil, ", .index=0x%x, .base=0x%x},\n", r->index, r->base); - r = r->next; - } - fprintf(fil, "\t },\n"); - } - int link = 0; - fprintf(fil, "\t.link = {\n"); - if (ptr->multidev) { - struct device *d = ptr; - while (d) { - if (device_match(d, ptr)) { - fprintf(fil, "\t\t[%d] = {\n", d->link); - fprintf(fil, "\t\t\t.link = %d,\n", d->link); - fprintf(fil, "\t\t\t.dev = &%s,\n", d->name); - if (d->children) - fprintf(fil, "\t\t\t.children = &%s,\n", d->children->name); - fprintf(fil, "\t\t},\n"); - link++; - } - d = d->next_sibling; - } - } else { - if (ptr->children) { - fprintf(fil, "\t\t[0] = {\n"); - fprintf(fil, "\t\t\t.link = 0,\n"); - fprintf(fil, "\t\t\t.dev = &%s,\n", ptr->name); - fprintf(fil, "\t\t\t.children = &%s,\n", ptr->children->name); - fprintf(fil, "\t\t},\n"); - link++; - } - } - fprintf(fil, "\t},\n"); - fprintf(fil, "\t.links = %d,\n", link); - if (ptr->sibling) - fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); - if (ptr->chip->chiph_exists) { - fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); - fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); - } - if (ptr->nextdev) - fprintf(fil, "\t.next=&%s\n", ptr->nextdev->name); - fprintf(fil, "};\n"); - } - if ((ptr->type == chip) && (ptr->chiph_exists)) { - if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", ptr->name_underscore, ptr->name_underscore, ptr->id); - struct reg *r = ptr->reg; - while (r) { - fprintf(fil, "\t.%s = %s,\n", r->key, r->value); - r = r->next; - } - fprintf(fil, "};\n\n"); - } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", ptr->name_underscore, ptr->name_underscore, ptr->id); - } - } -} - -void walk_device_tree(FILE *fil, struct device *ptr, void (*func)(FILE *, struct device*), struct device *chips) { - do { - func(fil, ptr); - ptr = ptr->next_sibling; - } while (ptr); -} - -struct device mainboard = { - .name = "mainboard", - .name_underscore = "mainboard", - .id = 0, - .chip = &mainboard, - .type = chip, - .chiph_exists = 1, - .children = &root -}; - -struct device root = { - .name = "dev_root", - .name_underscore = "dev_root", - .id = 0, - .chip = &mainboard, - .type = device, - .path = " .type = DEVICE_PATH_ROOT ", - .ops = "&default_dev_ops_root", - .parent = &root, - .bus = &root, - .enabled = 1 -}; - -int main(int argc, char** argv) { - if (argc != 3) { - printf("usage: sconfig vendor/mainboard outputdir\n"); - return 1; - } - char *mainboard=argv[1]; - char *outputdir=argv[2]; - char *devtree=malloc(strlen(mainboard)+30); - char *outputc=malloc(strlen(outputdir)+10); - sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard); - sprintf(outputc, "%s/static.c", outputdir); - - headers.next = malloc(sizeof(struct header)); - headers.next->name = malloc(strlen(mainboard)+12); - headers.next->next = 0; - sprintf(headers.next->name, "mainboard/%s", mainboard); - - FILE *filec = fopen(devtree, "r"); - yyrestart(filec); - - FILE *staticc = fopen(outputc, "w"); - - cur_bus = cur_parent = lastdev = head = &root; - yyparse(); - fclose(filec); - - if ((head->type == chip) && (!head->chiph_exists)) { - struct device *tmp = head; - head = &root; - while (head->next != tmp) head = head->next; - } - - fprintf(staticc, "#include \n"); - fprintf(staticc, "#include \n"); - struct header *h = &headers; - while (h->next) { - h = h->next; - fprintf(staticc, "#include \"%s/chip.h\"\n", h->name); - } - fprintf(staticc, "\n/* pass 0 */\n"); - walk_device_tree(staticc, &root, pass0, NULL); - fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device **last_dev_p = &%s.next;\n", lastdev->name); - walk_device_tree(staticc, &root, pass1, NULL); - - fclose(staticc); - return 0; -} From patrick at georgi-clan.de Wed May 5 13:40:14 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 05 May 2010 13:40:14 +0200 Subject: [coreboot] [PATCH]Make parser state local to parser Message-ID: <4BE1591E.2020607@georgi-clan.de> Hi, attached patch makes cur_parent and cur_bus, two variables that track internal parser state, local to the parser. Before, the device tree handling had to use them, too - their values are now passed as arguments instead. Tested to give identical results for all boards. Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20100505-2-sconfig-isolate-global-state URL: From stepan at coresystems.de Wed May 5 14:03:13 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Wed, 05 May 2010 14:03:13 +0200 Subject: [coreboot] [PATCH]Make parser state local to parser In-Reply-To: <4BE1591E.2020607@georgi-clan.de> References: <4BE1591E.2020607@georgi-clan.de> Message-ID: <4BE15E81.4030707@coresystems.de> On 5/5/10 1:40 PM, Patrick Georgi wrote: > Hi, > > attached patch makes cur_parent and cur_bus, two variables that track > internal parser state, local to the parser. Before, the device tree > handling had to use them, too - their values are now passed as arguments > instead. > > Tested to give identical results for all boards. > > Signed-off-by: Patrick Georgi > Acked-by: Stefan Reinauer From svn at coreboot.org Wed May 5 14:05:26 2010 From: svn at coreboot.org (repository service) Date: Wed, 05 May 2010 14:05:26 +0200 Subject: [coreboot] [commit] r5524 - trunk/util/sconfig Message-ID: Author: oxygene Date: Wed May 5 14:05:25 2010 New Revision: 5524 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5524 Log: sconfig: Make cur_bus and cur_parent local to the parser. Instead of accessing them globally, pass them as arguments where necessary. Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Modified: trunk/util/sconfig/main.c trunk/util/sconfig/sconfig.h trunk/util/sconfig/sconfig.tab.c_shipped trunk/util/sconfig/sconfig.y Modified: trunk/util/sconfig/main.c ============================================================================== --- trunk/util/sconfig/main.c Wed May 5 13:19:50 2010 (r5523) +++ trunk/util/sconfig/main.c Wed May 5 14:05:25 2010 (r5524) @@ -51,12 +51,12 @@ .enabled = 1 }; -static struct device *new_dev() { +static struct device *new_dev(struct device *parent, struct device *bus) { struct device *dev = malloc(sizeof(struct device)); memset(dev, 0, sizeof(struct device)); dev->id = ++devcount; - dev->parent = cur_parent; - dev->bus = cur_bus; + dev->parent = parent; + dev->bus = bus; head->next = dev; head = dev; return dev; @@ -110,8 +110,8 @@ } } -struct device *new_chip(char *path) { - struct device *new_chip = new_dev(); +struct device *new_chip(struct device *parent, struct device *bus, char *path) { + struct device *new_chip = new_dev(parent, bus); new_chip->chiph_exists = 1; new_chip->name = path; new_chip->name_underscore = strdup(new_chip->name); @@ -129,13 +129,13 @@ if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) new_chip->chiph_exists = 0; - if (cur_parent->latestchild) { - cur_parent->latestchild->next_sibling = new_chip; - cur_parent->latestchild->sibling = new_chip; - } - cur_parent->latestchild = new_chip; - if (!cur_parent->children) - cur_parent->children = new_chip; + if (parent->latestchild) { + parent->latestchild->next_sibling = new_chip; + parent->latestchild->sibling = new_chip; + } + parent->latestchild = new_chip; + if (!parent->children) + parent->children = new_chip; return new_chip; } @@ -162,8 +162,8 @@ } } -struct device *new_device(const int bus, const char *devnum, int enabled) { - struct device *new_d = new_dev(); +struct device *new_device(struct device *parent, struct device *busdev, const int bus, const char *devnum, int enabled) { + struct device *new_d = new_dev(parent, busdev); new_d->bustype = bus; char *tmp; @@ -181,13 +181,13 @@ new_d->enabled = enabled; new_d->chip = new_d->parent->chip; - if (cur_parent->latestchild) { - cur_parent->latestchild->next_sibling = new_d; - cur_parent->latestchild->sibling = new_d; - } - cur_parent->latestchild = new_d; - if (!cur_parent->children) - cur_parent->children = new_d; + if (parent->latestchild) { + parent->latestchild->next_sibling = new_d; + parent->latestchild->sibling = new_d; + } + parent->latestchild = new_d; + if (!parent->children) + parent->children = new_d; lastdev->nextdev = new_d; lastdev = new_d; @@ -235,29 +235,29 @@ } } -void add_resource(int type, int index, int base) { +void add_resource(struct device *dev, int type, int index, int base) { struct resource *r = malloc(sizeof(struct resource)); memset (r, 0, sizeof(struct resource)); r->type = type; r->index = index; r->base = base; - if (cur_parent->res) { - struct resource *head = cur_parent->res; + if (dev->res) { + struct resource *head = dev->res; while (head->next) head = head->next; head->next = r; } else { - cur_parent->res = r; + dev->res = r; } - cur_parent->rescnt++; + dev->rescnt++; } -void add_register(char *name, char *val) { +void add_register(struct device *dev, char *name, char *val) { struct reg *r = malloc(sizeof(struct reg)); memset (r, 0, sizeof(struct reg)); r->key = name; r->value = val; - if (cur_parent->reg) { - struct reg *head = cur_parent->reg; + if (dev->reg) { + struct reg *head = dev->reg; // sorting to be equal to sconfig's behaviour int sort = strcmp(r->key, head->key); if (sort == 0) { @@ -266,14 +266,14 @@ } if (sort<0) { r->next = head; - cur_parent->reg = r; + dev->reg = r; } else { while ((head->next) && (strcmp(head->next->key, r->key)<0)) head = head->next; r->next = head->next; head->next = r; } } else { - cur_parent->reg = r; + dev->reg = r; } } @@ -390,7 +390,7 @@ FILE *staticc = fopen(outputc, "w"); - cur_bus = cur_parent = lastdev = head = &root; + lastdev = head = &root; yyparse(); fclose(filec); Modified: trunk/util/sconfig/sconfig.h ============================================================================== --- trunk/util/sconfig/sconfig.h Wed May 5 13:19:50 2010 (r5523) +++ trunk/util/sconfig/sconfig.h Wed May 5 14:05:25 2010 (r5524) @@ -74,7 +74,7 @@ struct reg *reg; }; -extern struct device *cur_parent, *cur_bus; +struct device *head; struct header; struct header { @@ -85,9 +85,9 @@ void fold_in(struct device *parent); void postprocess_devtree(void); -struct device *new_chip(char *path); +struct device *new_chip(struct device *parent, struct device *bus, char *path); void add_header(struct device *dev); -struct device *new_device(const int bus, const char *devnum, int enabled); +struct device *new_device(struct device *parent, struct device *busdev, const int bus, const char *devnum, int enabled); void alias_siblings(struct device *d); -void add_resource(int type, int index, int base); -void add_register(char *name, char *val); +void add_resource(struct device *dev, int type, int index, int base); +void add_register(struct device *dev, char *name, char *val); Modified: trunk/util/sconfig/sconfig.tab.c_shipped ============================================================================== --- trunk/util/sconfig/sconfig.tab.c_shipped Wed May 5 13:19:50 2010 (r5523) +++ trunk/util/sconfig/sconfig.tab.c_shipped Wed May 5 14:05:25 2010 (r5524) @@ -90,7 +90,7 @@ #include "sconfig.h" -struct device *cur_parent, *cur_bus; +static struct device *cur_parent, *cur_bus; @@ -378,18 +378,18 @@ #endif /* YYFINAL -- State number of the termination state. */ -#define YYFINAL 9 +#define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 23 +#define YYLAST 22 /* YYNTOKENS -- Number of terminals. */ #define YYNTOKENS 23 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 11 +#define YYNNTS 12 /* YYNRULES -- Number of rules. */ -#define YYNRULES 16 +#define YYNRULES 17 /* YYNRULES -- Number of states. */ -#define YYNSTATES 30 +#define YYNSTATES 31 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ #define YYUNDEFTOK 2 @@ -436,25 +436,26 @@ YYRHS. */ static const yytype_uint8 yyprhs[] = { - 0, 0, 3, 5, 7, 9, 12, 15, 16, 19, - 22, 23, 24, 30, 31, 39, 44 + 0, 0, 3, 4, 7, 9, 11, 14, 17, 18, + 21, 24, 25, 26, 32, 33, 41, 46 }; /* YYRHS -- A `-1'-separated list of the rules' RHS. */ static const yytype_int8 yyrhs[] = { - 24, 0, -1, 25, -1, 28, -1, 30, -1, 26, - 25, -1, 26, 33, -1, -1, 27, 25, -1, 27, - 32, -1, -1, -1, 3, 12, 29, 26, 9, -1, - -1, 4, 7, 22, 6, 31, 27, 9, -1, 8, - 22, 10, 22, -1, 5, 12, 10, 12, -1 + 24, 0, -1, -1, 25, 26, -1, 29, -1, 31, + -1, 27, 26, -1, 27, 34, -1, -1, 28, 26, + -1, 28, 33, -1, -1, -1, 3, 12, 30, 27, + 9, -1, -1, 4, 7, 22, 6, 32, 28, 9, + -1, 8, 22, 10, 22, -1, 5, 12, 10, 12, + -1 }; /* YYRLINE[YYN] -- source line where rule number YYN was defined. */ static const yytype_uint8 yyrline[] = { - 0, 34, 34, 36, 36, 38, 38, 38, 40, 40, - 40, 42, 42, 52, 52, 64, 67 + 0, 34, 34, 34, 36, 36, 38, 38, 38, 40, + 40, 40, 42, 42, 52, 52, 64, 67 }; #endif @@ -466,8 +467,8 @@ "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C", "APIC", "APIC_CLUSTER", "PCI_DOMAIN", "IRQ", "DRQ", "IO", "NUMBER", - "$accept", "devtree", "devchip", "devices", "devicesorresources", "chip", - "@1", "device", "@2", "resource", "registers", 0 + "$accept", "devtree", "$@1", "devchip", "devices", "devicesorresources", + "chip", "@2", "device", "@3", "resource", "registers", 0 }; #endif @@ -485,15 +486,15 @@ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 23, 24, 25, 25, 26, 26, 26, 27, 27, - 27, 29, 28, 31, 30, 32, 33 + 0, 23, 25, 24, 26, 26, 27, 27, 27, 28, + 28, 28, 30, 29, 32, 31, 33, 34 }; /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ static const yytype_uint8 yyr2[] = { - 0, 2, 1, 1, 1, 2, 2, 0, 2, 2, - 0, 0, 5, 0, 7, 4, 4 + 0, 2, 0, 2, 1, 1, 2, 2, 0, 2, + 2, 0, 0, 5, 0, 7, 4, 4 }; /* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state @@ -501,33 +502,35 @@ means the default is an error. */ static const yytype_uint8 yydefact[] = { - 0, 0, 0, 0, 2, 3, 4, 11, 0, 1, - 7, 0, 0, 13, 0, 12, 5, 6, 10, 0, - 0, 0, 0, 14, 8, 9, 16, 0, 0, 15 + 2, 0, 0, 1, 0, 0, 3, 4, 5, 12, + 0, 8, 0, 0, 14, 0, 13, 6, 7, 11, + 0, 0, 0, 0, 15, 9, 10, 17, 0, 0, + 16 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { - -1, 3, 4, 12, 20, 5, 10, 6, 18, 25, - 17 + -1, 1, 2, 6, 13, 21, 7, 11, 8, 19, + 26, 18 }; /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing STATE-NUM. */ -#define YYPACT_NINF -13 +#define YYPACT_NINF -14 static const yytype_int8 yypact[] = { - 8, -6, 6, 14, -13, -13, -13, -13, -7, -13, - -13, 10, -2, -13, 5, -13, -13, -13, -13, 9, - 1, 11, -4, -13, -13, -13, -13, 12, -1, -13 + -14, 6, 8, -14, 2, 9, -14, -14, -14, -14, + -9, -14, 11, -2, -14, 3, -14, -14, -14, -14, + 10, 1, 7, -4, -14, -14, -14, -14, 12, -1, + -14 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -13, -13, -12, -13, -13, -13, -13, -13, -13, -13, - -13 + -14, -14, -14, -13, -14, -14, -14, -14, -14, -14, + -14, -14 }; /* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If @@ -537,25 +540,26 @@ #define YYTABLE_NINF -1 static const yytype_uint8 yytable[] = { - 16, 1, 2, 14, 1, 2, 7, 15, 24, 22, - 23, 1, 2, 8, 9, 11, 13, 19, 27, 21, - 0, 29, 28, 26 + 17, 4, 5, 15, 4, 5, 3, 16, 25, 23, + 24, 4, 5, 12, 9, 20, 10, 14, 28, 27, + 22, 30, 29 }; -static const yytype_int8 yycheck[] = +static const yytype_uint8 yycheck[] = { - 12, 3, 4, 5, 3, 4, 12, 9, 20, 8, - 9, 3, 4, 7, 0, 22, 6, 12, 22, 10, - -1, 22, 10, 12 + 13, 3, 4, 5, 3, 4, 0, 9, 21, 8, + 9, 3, 4, 22, 12, 12, 7, 6, 22, 12, + 10, 22, 10 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 3, 4, 24, 25, 28, 30, 12, 7, 0, - 29, 22, 26, 6, 5, 9, 25, 33, 31, 12, - 27, 10, 8, 9, 25, 32, 12, 22, 10, 22 + 0, 24, 25, 0, 3, 4, 26, 29, 31, 12, + 7, 30, 22, 27, 6, 5, 9, 26, 34, 32, + 12, 28, 10, 8, 9, 26, 33, 12, 22, 10, + 22 }; #define yyerrok (yyerrstatus = 0) @@ -1368,18 +1372,23 @@ { case 2: + { cur_parent = cur_bus = head; ;} + break; + + case 3: + { postprocess_devtree(); ;} break; - case 11: + case 12: { - (yyval.device) = new_chip((yyvsp[(2) - (2)].string)); + (yyval.device) = new_chip(cur_parent, cur_bus, (yyvsp[(2) - (2)].string)); cur_parent = (yyval.device); ;} break; - case 12: + case 13: { cur_parent = (yyvsp[(3) - (5)].device)->parent; @@ -1388,16 +1397,16 @@ ;} break; - case 13: + case 14: { - (yyval.device) = new_device((yyvsp[(2) - (4)].number), (yyvsp[(3) - (4)].string), (yyvsp[(4) - (4)].number)); + (yyval.device) = new_device(cur_parent, cur_bus, (yyvsp[(2) - (4)].number), (yyvsp[(3) - (4)].string), (yyvsp[(4) - (4)].number)); cur_parent = (yyval.device); cur_bus = (yyval.device); ;} break; - case 14: + case 15: { cur_parent = (yyvsp[(5) - (7)].device)->parent; @@ -1407,14 +1416,14 @@ ;} break; - case 15: + case 16: - { add_resource((yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); ;} + { add_resource(cur_parent, (yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); ;} break; - case 16: + case 17: - { add_register((yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); ;} + { add_register(cur_parent, (yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); ;} break; Modified: trunk/util/sconfig/sconfig.y ============================================================================== --- trunk/util/sconfig/sconfig.y Wed May 5 13:19:50 2010 (r5523) +++ trunk/util/sconfig/sconfig.y Wed May 5 14:05:25 2010 (r5524) @@ -21,7 +21,7 @@ #include "sconfig.h" -struct device *cur_parent, *cur_bus; +static struct device *cur_parent, *cur_bus; %} %union { @@ -31,7 +31,7 @@ } %token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER %% -devtree: devchip { postprocess_devtree(); } ; +devtree: { cur_parent = cur_bus = head; } devchip { postprocess_devtree(); } ; devchip: chip | device ; @@ -40,7 +40,7 @@ devicesorresources: devicesorresources devchip | devicesorresources resource | ; chip: CHIP STRING /* == path */ { - $$ = new_chip($2); + $$ = new_chip(cur_parent, cur_bus, $2); cur_parent = $$; } devices END { @@ -50,7 +50,7 @@ }; device: DEVICE BUS NUMBER /* == devnum */ BOOL { - $$ = new_device($2, $3, $4); + $$ = new_device(cur_parent, cur_bus, $2, $3, $4); cur_parent = $$; cur_bus = $$; } @@ -62,9 +62,9 @@ }; resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */ - { add_resource($1, strtol($2, NULL, 0), strtol($4, NULL, 0)); } ; + { add_resource(cur_parent, $1, strtol($2, NULL, 0), strtol($4, NULL, 0)); } ; registers: REGISTER STRING /* == regname */ EQUALS STRING /* == regval */ - { add_register($2, $4); } ; + { add_register(cur_parent, $2, $4); } ; %% From svn at coreboot.org Wed May 5 14:24:11 2010 From: svn at coreboot.org (coreboot) Date: Wed, 05 May 2010 12:24:11 -0000 Subject: [coreboot] #18: autoprobe apic cluster and application processors on K8 systems In-Reply-To: <042.3b6a74bac1755b1786072950302df3e4@coreboot.org> References: <042.3b6a74bac1755b1786072950302df3e4@coreboot.org> Message-ID: <051.8c5727e416fbd4fd7703162c9abaf660@coreboot.org> #18: autoprobe apic cluster and application processors on K8 systems -------------------------+-------------------------------------------------- Reporter: stepan | Owner: oxygene Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: K8, cleanup Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by oxygene): * owner: somebody => oxygene * patchstatus: => there is no patch -- Ticket URL: coreboot From patrick at georgi-clan.de Wed May 5 14:28:39 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 05 May 2010 14:28:39 +0200 Subject: [coreboot] [PATCH]Improve sconfig parser Message-ID: <4BE16477.4080707@georgi-clan.de> Hi, attached patch improves the sconfig parser: - The device tree must start with a chip (not a device) - It's more clearly visible at which places chip, device, register and resource can be used. Again, this gives byte-identical results to older sconfig. Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20100505-3-sconfig-stricter-parser URL: From patrick at georgi-clan.de Wed May 5 14:50:57 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 05 May 2010 14:50:57 +0200 Subject: [coreboot] [PATCH]rename apic to lapic in device trees Message-ID: <4BE169B1.9080604@georgi-clan.de> Hi, attached patch renames "apic" and "apic_cluster" to "lapic" and "lapic_cluster". This is in preparation of adding ioapics to device trees, and it also makes clearer what is covered by those devices. Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20100505-4-sconfig-rename-apic-to-lapic URL: From stepan at coresystems.de Wed May 5 15:02:47 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Wed, 05 May 2010 15:02:47 +0200 Subject: [coreboot] [PATCH]Improve sconfig parser In-Reply-To: <4BE16477.4080707@georgi-clan.de> References: <4BE16477.4080707@georgi-clan.de> Message-ID: <4BE16C77.40609@coresystems.de> On 5/5/10 2:28 PM, Patrick Georgi wrote: > Hi, > > attached patch improves the sconfig parser: > - The device tree must start with a chip (not a device) > - It's more clearly visible at which places chip, device, register and > resource can be used. > > Again, this gives byte-identical results to older sconfig. > > Signed-off-by: Patrick Georgi > Acked-by: Stefan Reinauer From stepan at coresystems.de Wed May 5 15:03:07 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Wed, 05 May 2010 15:03:07 +0200 Subject: [coreboot] [PATCH]rename apic to lapic in device trees In-Reply-To: <4BE169B1.9080604@georgi-clan.de> References: <4BE169B1.9080604@georgi-clan.de> Message-ID: <4BE16C8B.6080004@coresystems.de> On 5/5/10 2:50 PM, Patrick Georgi wrote: > Hi, > > attached patch renames "apic" and "apic_cluster" to "lapic" and > "lapic_cluster". This is in preparation of adding ioapics to device > trees, and it also makes clearer what is covered by those devices. > > > Signed-off-by: Patrick Georgi > Acked-by: Stefan Reinauer From peter at stuge.se Wed May 5 15:08:05 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 5 May 2010 15:08:05 +0200 Subject: [coreboot] [PATCH]Improve sconfig parser In-Reply-To: <4BE16477.4080707@georgi-clan.de> References: <4BE16477.4080707@georgi-clan.de> Message-ID: <20100505130805.22701.qmail@stuge.se> Patrick Georgi wrote: > Again, this gives byte-identical results to older sconfig. > > Signed-off-by: Patrick Georgi Acked-by: Peter Stuge From peter at stuge.se Wed May 5 15:08:34 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 5 May 2010 15:08:34 +0200 Subject: [coreboot] [PATCH]rename apic to lapic in device trees In-Reply-To: <4BE169B1.9080604@georgi-clan.de> References: <4BE169B1.9080604@georgi-clan.de> Message-ID: <20100505130834.22816.qmail@stuge.se> Patrick Georgi wrote: > attached patch renames "apic" and "apic_cluster" to "lapic" and > "lapic_cluster". This is in preparation of adding ioapics to device > trees, and it also makes clearer what is covered by those devices. Nice! > Signed-off-by: Patrick Georgi Acked-by: Peter Stuge From svn at coreboot.org Wed May 5 15:12:42 2010 From: svn at coreboot.org (repository service) Date: Wed, 05 May 2010 15:12:42 +0200 Subject: [coreboot] [commit] r5525 - in trunk: src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/amd/db800 src/mainboard/amd/dbm690t src/mainboard/amd/mahogany ... Message-ID: Author: oxygene Date: Wed May 5 15:12:42 2010 New Revision: 5525 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5525 Log: Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster" in device trees. Adapt sconfig as necessary. Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Acked-by: Peter Stuge Modified: trunk/src/mainboard/a-trend/atc-6220/devicetree.cb trunk/src/mainboard/a-trend/atc-6240/devicetree.cb trunk/src/mainboard/abit/be6-ii_v2_0/devicetree.cb trunk/src/mainboard/amd/db800/devicetree.cb trunk/src/mainboard/amd/dbm690t/devicetree.cb trunk/src/mainboard/amd/mahogany/devicetree.cb trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb trunk/src/mainboard/amd/norwich/devicetree.cb trunk/src/mainboard/amd/pistachio/devicetree.cb trunk/src/mainboard/amd/rumba/devicetree.cb trunk/src/mainboard/amd/serengeti_cheetah/devicetree.cb trunk/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb trunk/src/mainboard/arima/hdama/devicetree.cb trunk/src/mainboard/artecgroup/dbe61/devicetree.cb trunk/src/mainboard/asrock/939a785gmh/devicetree.cb trunk/src/mainboard/asus/a8n_e/devicetree.cb trunk/src/mainboard/asus/a8v-e_se/devicetree.cb trunk/src/mainboard/asus/m2v-mx_se/devicetree.cb trunk/src/mainboard/asus/mew-am/devicetree.cb trunk/src/mainboard/asus/p2b-d/devicetree.cb trunk/src/mainboard/asus/p2b-ds/devicetree.cb trunk/src/mainboard/asus/p2b-f/devicetree.cb trunk/src/mainboard/asus/p2b-ls/devicetree.cb trunk/src/mainboard/asus/p2b/devicetree.cb trunk/src/mainboard/asus/p3b-f/devicetree.cb trunk/src/mainboard/azza/pt-6ibd/devicetree.cb trunk/src/mainboard/bcom/winnetp680/devicetree.cb trunk/src/mainboard/biostar/m6tba/devicetree.cb trunk/src/mainboard/broadcom/blast/devicetree.cb trunk/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb trunk/src/mainboard/dell/s1850/devicetree.cb trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb trunk/src/mainboard/digitallogic/msm800sev/devicetree.cb trunk/src/mainboard/gigabyte/ga-6bxc/devicetree.cb trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb trunk/src/mainboard/gigabyte/m57sli/devicetree.cb trunk/src/mainboard/hp/dl145_g3/devicetree.cb trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb trunk/src/mainboard/ibm/e325/devicetree.cb trunk/src/mainboard/ibm/e326/devicetree.cb trunk/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb trunk/src/mainboard/intel/d945gclf/devicetree.cb trunk/src/mainboard/intel/eagleheights/devicetree.cb trunk/src/mainboard/intel/jarrell/devicetree.cb trunk/src/mainboard/intel/mtarvon/devicetree.cb trunk/src/mainboard/intel/truxton/devicetree.cb trunk/src/mainboard/intel/xe7501devkit/devicetree.cb trunk/src/mainboard/iwill/dk8_htx/devicetree.cb trunk/src/mainboard/iwill/dk8s2/devicetree.cb trunk/src/mainboard/iwill/dk8x/devicetree.cb trunk/src/mainboard/jetway/j7f24/devicetree.cb trunk/src/mainboard/kontron/986lcd-m/devicetree.cb trunk/src/mainboard/kontron/kt690/devicetree.cb trunk/src/mainboard/lippert/roadrunner-lx/devicetree.cb trunk/src/mainboard/lippert/spacerunner-lx/devicetree.cb trunk/src/mainboard/mitac/6513wu/devicetree.cb trunk/src/mainboard/msi/ms6119/devicetree.cb trunk/src/mainboard/msi/ms6147/devicetree.cb trunk/src/mainboard/msi/ms6156/devicetree.cb trunk/src/mainboard/msi/ms6178/devicetree.cb trunk/src/mainboard/msi/ms7135/devicetree.cb trunk/src/mainboard/msi/ms7260/devicetree.cb trunk/src/mainboard/msi/ms9185/devicetree.cb trunk/src/mainboard/msi/ms9282/devicetree.cb trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb trunk/src/mainboard/nec/powermate2000/devicetree.cb trunk/src/mainboard/newisys/khepri/devicetree.cb trunk/src/mainboard/nokia/ip530/devicetree.cb trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb trunk/src/mainboard/olpc/btest/devicetree.cb trunk/src/mainboard/olpc/rev_a/devicetree.cb trunk/src/mainboard/pcengines/alix1c/devicetree.cb trunk/src/mainboard/rca/rm4100/devicetree.cb trunk/src/mainboard/roda/rk886ex/devicetree.cb trunk/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb trunk/src/mainboard/sunw/ultra40/devicetree.cb trunk/src/mainboard/supermicro/h8dme/devicetree.cb trunk/src/mainboard/supermicro/h8dmr/devicetree.cb trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb trunk/src/mainboard/supermicro/x6dai_g/devicetree.cb trunk/src/mainboard/supermicro/x6dhe_g/devicetree.cb trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb trunk/src/mainboard/technexion/tim5690/devicetree.cb trunk/src/mainboard/technexion/tim8690/devicetree.cb trunk/src/mainboard/thomson/ip1000/devicetree.cb trunk/src/mainboard/tyan/s1846/devicetree.cb trunk/src/mainboard/tyan/s2735/devicetree.cb trunk/src/mainboard/tyan/s2850/devicetree.cb trunk/src/mainboard/tyan/s2875/devicetree.cb trunk/src/mainboard/tyan/s2880/devicetree.cb trunk/src/mainboard/tyan/s2881/devicetree.cb trunk/src/mainboard/tyan/s2882/devicetree.cb trunk/src/mainboard/tyan/s2885/devicetree.cb trunk/src/mainboard/tyan/s2891/devicetree.cb trunk/src/mainboard/tyan/s2892/devicetree.cb trunk/src/mainboard/tyan/s2895/devicetree.cb trunk/src/mainboard/tyan/s2912/devicetree.cb trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb trunk/src/mainboard/tyan/s4880/devicetree.cb trunk/src/mainboard/tyan/s4882/devicetree.cb trunk/src/mainboard/via/epia-cn/devicetree.cb trunk/src/mainboard/via/epia-m/devicetree.cb trunk/src/mainboard/via/epia-m700/devicetree.cb trunk/src/mainboard/via/epia-n/devicetree.cb trunk/src/mainboard/via/epia/devicetree.cb trunk/src/mainboard/via/pc2500e/devicetree.cb trunk/src/mainboard/via/vt8454c/devicetree.cb trunk/src/mainboard/winent/pl6064/devicetree.cb trunk/util/sconfig/lex.yy.c_shipped trunk/util/sconfig/sconfig.l Modified: trunk/src/mainboard/a-trend/atc-6220/devicetree.cb ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/a-trend/atc-6220/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/a-trend/atc-6240/devicetree.cb ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/a-trend/atc-6240/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/abit/be6-ii_v2_0/devicetree.cb ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/abit/be6-ii_v2_0/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/amd/db800/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/db800/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/amd/db800/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -59,9 +59,9 @@ end end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/dbm690t/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/amd/dbm690t/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -9,9 +9,9 @@ #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_S1G1 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/amd/mahogany/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/mahogany/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/amd/mahogany/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -9,9 +9,9 @@ #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_AM2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,8 +1,8 @@ # sample config for amd/mahogany_fam10 chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_AM2r2 #L1 and DDR2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/amd/norwich/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/norwich/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/amd/norwich/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -32,9 +32,9 @@ end end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/pistachio/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/amd/pistachio/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -9,9 +9,9 @@ #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_AM2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/amd/rumba/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/rumba/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/amd/rumba/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,9 +1,9 @@ chip northbridge/amd/gx2 register "setupflash" = "0" #register "irqmap" = "0xaa5b" - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_gx2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/amd/serengeti_cheetah/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/amd/serengeti_cheetah/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F_1207 #L1 and DDR2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,8 +1,8 @@ # sample config for amd/tilapia_fam10 chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_AM3 #L1 and DDR3 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/arima/hdama/devicetree.cb ============================================================================== --- trunk/src/mainboard/arima/hdama/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/arima/hdama/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/artecgroup/dbe61/devicetree.cb ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/artecgroup/dbe61/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -32,9 +32,9 @@ end end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/asrock/939a785gmh/devicetree.cb ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asrock/939a785gmh/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -9,9 +9,9 @@ #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_939 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/asus/a8n_e/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/a8n_e/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asus/a8n_e/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/amd/socket_939 # Socket 939 CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end Modified: trunk/src/mainboard/asus/a8v-e_se/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asus/a8v-e_se/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/amd/socket_939 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/asus/m2v-mx_se/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asus/m2v-mx_se/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/amd/socket_AM2 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/asus/mew-am/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/mew-am/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asus/mew-am/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/asus/p2b-d/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b-d/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asus/p2b-d/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,10 +1,10 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end chip cpu/intel/slot_1 # CPU - device apic 1 on end # APIC + device lapic 1 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/asus/p2b-ds/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asus/p2b-ds/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,10 +1,10 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end chip cpu/intel/slot_1 # CPU - device apic 1 on end # APIC + device lapic 1 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/asus/p2b-f/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b-f/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asus/p2b-f/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/asus/p2b-ls/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asus/p2b-ls/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/asus/p2b/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asus/p2b/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/asus/p3b-f/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p3b-f/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/asus/p3b-f/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/azza/pt-6ibd/devicetree.cb ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/azza/pt-6ibd/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/bcom/winnetp680/devicetree.cb ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/bcom/winnetp680/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -56,9 +56,9 @@ device pci 12.0 on end # Ethernet end end - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/via/model_c7 # VIA C7 - device apic 0 on end # APIC + device lapic 0 on end # APIC end end end Modified: trunk/src/mainboard/biostar/m6tba/devicetree.cb ============================================================================== --- trunk/src/mainboard/biostar/m6tba/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/biostar/m6tba/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/broadcom/blast/devicetree.cb ============================================================================== --- trunk/src/mainboard/broadcom/blast/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/broadcom/blast/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/dell/s1850/devicetree.cb ============================================================================== --- trunk/src/mainboard/dell/s1850/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/dell/s1850/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -58,12 +58,12 @@ device pci 04.0 on end device pci 06.0 on end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 # cpu 0 - device apic 0 on end + device lapic 0 on end end chip cpu/intel/socket_mPGA604 # cpu 1 - device apic 6 on end + device lapic 6 on end end end register "intrline" = "0x00070100" Modified: trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -51,9 +51,9 @@ end end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA479M - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/src/mainboard/digitallogic/msm800sev/devicetree.cb ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/digitallogic/msm800sev/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -76,9 +76,9 @@ end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/gigabyte/ga-6bxc/devicetree.cb ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/gigabyte/ga-6bxc/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_AM2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/gigabyte/m57sli/devicetree.cb ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/gigabyte/m57sli/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_AM2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/hp/dl145_g3/devicetree.cb ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/hp/dl145_g3/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,8 +1,8 @@ # TODO: i810E actually! chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on Modified: trunk/src/mainboard/ibm/e325/devicetree.cb ============================================================================== --- trunk/src/mainboard/ibm/e325/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/ibm/e325/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -69,12 +69,12 @@ device pci 19.3 on end end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end chip cpu/amd/socket_940 - device apic 1 on end + device lapic 1 on end end end end Modified: trunk/src/mainboard/ibm/e326/devicetree.cb ============================================================================== --- trunk/src/mainboard/ibm/e326/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/ibm/e326/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -67,9 +67,9 @@ end end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/src/mainboard/intel/d945gclf/devicetree.cb ============================================================================== --- trunk/src/mainboard/intel/d945gclf/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/intel/d945gclf/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -19,9 +19,9 @@ chip northbridge/intel/i945 - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_441 - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/intel/eagleheights/devicetree.cb ============================================================================== --- trunk/src/mainboard/intel/eagleheights/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/intel/eagleheights/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -64,9 +64,9 @@ device pci 1f.4 on end # Performance counters end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/bga956 - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/src/mainboard/intel/jarrell/devicetree.cb ============================================================================== --- trunk/src/mainboard/intel/jarrell/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/intel/jarrell/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -68,12 +68,12 @@ register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT" end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 # cpu 0 - device apic 0 on end + device lapic 0 on end end chip cpu/intel/socket_mPGA604 # cpu 1 - device apic 6 on end + device lapic 6 on end end end end Modified: trunk/src/mainboard/intel/mtarvon/devicetree.cb ============================================================================== --- trunk/src/mainboard/intel/mtarvon/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/intel/mtarvon/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -36,9 +36,9 @@ device pci 1f.3 on end # SMBus end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA479M - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/src/mainboard/intel/truxton/devicetree.cb ============================================================================== --- trunk/src/mainboard/intel/truxton/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/intel/truxton/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -46,9 +46,9 @@ device pci 1f.4 on end # ? end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/ep80579 - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/src/mainboard/intel/xe7501devkit/devicetree.cb ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/intel/xe7501devkit/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -61,12 +61,12 @@ device pci 1f.6 off end # AC97 Modem end # SB end # PCI_DOMAIN - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 - device apic 0 on end + device lapic 0 on end end chip cpu/intel/socket_mPGA604 - device apic 6 on end + device lapic 6 on end end end end Modified: trunk/src/mainboard/iwill/dk8_htx/devicetree.cb ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/iwill/dk8_htx/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/iwill/dk8s2/devicetree.cb ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/iwill/dk8s2/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -77,12 +77,12 @@ device pci 19.3 on end end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end chip cpu/amd/socket_940 - device apic 1 on end + device lapic 1 on end end end end Modified: trunk/src/mainboard/iwill/dk8x/devicetree.cb ============================================================================== --- trunk/src/mainboard/iwill/dk8x/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/iwill/dk8x/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -56,12 +56,12 @@ device pci 19.3 on end end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end chip cpu/amd/socket_940 - device apic 1 on end + device lapic 1 on end end end end Modified: trunk/src/mainboard/jetway/j7f24/devicetree.cb ============================================================================== --- trunk/src/mainboard/jetway/j7f24/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/jetway/j7f24/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -54,9 +54,9 @@ device pci 12.0 on end # Ethernet end end - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/via/model_c7 # VIA C7 - device apic 0 on end # APIC + device lapic 0 on end # APIC end end end Modified: trunk/src/mainboard/kontron/986lcd-m/devicetree.cb ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/kontron/986lcd-m/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,8 +1,8 @@ chip northbridge/intel/i945 - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mFCPGA478 - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb ============================================================================== --- trunk/src/mainboard/kontron/kt690/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/kontron/kt690/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -9,9 +9,9 @@ #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_S1G1 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/lippert/roadrunner-lx/devicetree.cb ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/lippert/roadrunner-lx/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -81,9 +81,9 @@ end end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/src/mainboard/lippert/spacerunner-lx/devicetree.cb ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/lippert/spacerunner-lx/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -82,9 +82,9 @@ end end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/src/mainboard/mitac/6513wu/devicetree.cb ============================================================================== --- trunk/src/mainboard/mitac/6513wu/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/mitac/6513wu/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -19,9 +19,9 @@ ## chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/msi/ms6119/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms6119/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/msi/ms6119/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/msi/ms6147/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms6147/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/msi/ms6147/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/msi/ms6156/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms6156/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/msi/ms6156/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -19,9 +19,9 @@ ## chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/msi/ms6178/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms6178/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/msi/ms6178/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -19,9 +19,9 @@ ## chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on Modified: trunk/src/mainboard/msi/ms7135/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms7135/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/msi/ms7135/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/amd/socket_754 # Socket 754 CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end Modified: trunk/src/mainboard/msi/ms7260/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms7260/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/msi/ms7260/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/amd/socket_AM2 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/msi/ms9185/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms9185/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/msi/ms9185/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms9282/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/msi/ms9282/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -22,9 +22,9 @@ ## chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F_1207 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/nec/powermate2000/devicetree.cb ============================================================================== --- trunk/src/mainboard/nec/powermate2000/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/nec/powermate2000/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on Modified: trunk/src/mainboard/newisys/khepri/devicetree.cb ============================================================================== --- trunk/src/mainboard/newisys/khepri/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/newisys/khepri/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,10 +1,10 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end chip cpu/amd/socket_940 - device apic 1 on end + device lapic 1 on end end end Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb ============================================================================== --- trunk/src/mainboard/nokia/ip530/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/nokia/ip530/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -19,9 +19,9 @@ ## chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/olpc/btest/devicetree.cb ============================================================================== --- trunk/src/mainboard/olpc/btest/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/olpc/btest/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,9 +1,9 @@ chip northbridge/amd/gx2 register "irqmap" = "0xaa5b" register "setupflash" = "0" - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_gx2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/olpc/rev_a/devicetree.cb ============================================================================== --- trunk/src/mainboard/olpc/rev_a/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/olpc/rev_a/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,9 +1,9 @@ chip northbridge/amd/gx2 register "irqmap" = "0xaa5b" register "setupflash" = "0" - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_gx2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/pcengines/alix1c/devicetree.cb ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/pcengines/alix1c/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -76,9 +76,9 @@ end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb ============================================================================== --- trunk/src/mainboard/rca/rm4100/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/rca/rm4100/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i82830 # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/socket_mFCBGA479 # Mobile Celeron Micro-FCBGA Socket 479 - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/roda/rk886ex/devicetree.cb ============================================================================== --- trunk/src/mainboard/roda/rk886ex/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/roda/rk886ex/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -21,9 +21,9 @@ chip northbridge/intel/i945 - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mFCPGA478 - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -19,9 +19,9 @@ ## chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/sunw/ultra40/devicetree.cb ============================================================================== --- trunk/src/mainboard/sunw/ultra40/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/sunw/ultra40/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F_1207 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F_1207 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/supermicro/x6dai_g/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/supermicro/x6dai_g/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -52,12 +52,12 @@ device pci 04.0 on end device pci 08.0 on end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 # cpu0 - device apic 0 on end + device lapic 0 on end end chip cpu/intel/socket_mPGA604 # cpu1 - device apic 6 on end + device lapic 6 on end end end end Modified: trunk/src/mainboard/supermicro/x6dhe_g/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/supermicro/x6dhe_g/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -75,12 +75,12 @@ device pci 06.0 on end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 # CPU 0 - device apic 0 on end + device lapic 0 on end end chip cpu/intel/socket_mPGA604 # CPU 1 - device apic 6 on end + device lapic 6 on end end end end Modified: trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -75,12 +75,12 @@ device pci 06.0 on end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 # CPU 0 - device apic 0 on end + device lapic 0 on end end chip cpu/intel/socket_mPGA604 # CPU 1 - device apic 6 on end + device lapic 6 on end end end end Modified: trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -71,12 +71,12 @@ end device pci 06.0 on end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 # cpu 0 - device apic 0 on end + device lapic 0 on end end chip cpu/intel/socket_mPGA604 # cpu 1 - device apic 6 on end + device lapic 6 on end end end register "intrline" = "0x00070105" Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -62,12 +62,12 @@ device pci 04.0 on end device pci 06.0 on end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 # cpu 0 - device apic 0 on end + device lapic 0 on end end chip cpu/intel/socket_mPGA604 # cpu 1 - device apic 6 on end + device lapic 6 on end end end register "intrline" = "0x00070105" Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb ============================================================================== --- trunk/src/mainboard/technexion/tim5690/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/technexion/tim5690/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -9,9 +9,9 @@ #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_S1G1 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb ============================================================================== --- trunk/src/mainboard/technexion/tim8690/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/technexion/tim8690/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -9,9 +9,9 @@ #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_S1G1 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb ============================================================================== --- trunk/src/mainboard/thomson/ip1000/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/thomson/ip1000/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i82830 # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/socket_mFCBGA479 # Low Voltage PIII Micro-FCBGA Socket 479 - device apic 0 on end # APIC + device lapic 0 on end # APIC end end Modified: trunk/src/mainboard/tyan/s1846/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s1846/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s1846/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/intel/slot_1 # CPU - device apic 0 on end # APIC + device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/tyan/s2735/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2735/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2735/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -73,12 +73,12 @@ device pci 1f.6 off end end # SB end # PCI_DOMAIN - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 - device apic 0 on end + device lapic 0 on end end chip cpu/intel/socket_mPGA604 - device apic 6 on end + device lapic 6 on end end end end Modified: trunk/src/mainboard/tyan/s2850/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2850/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2850/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/tyan/s2875/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2875/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2875/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/tyan/s2880/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2880/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2880/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/tyan/s2881/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2881/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2881/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/tyan/s2882/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2882/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2882/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/tyan/s2885/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2885/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2885/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/tyan/s2891/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2891/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2891/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/tyan/s2892/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2892/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2892/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/tyan/s2895/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2895/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2895/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/tyan/s2912/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2912/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2912/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F_1207 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/tyan/s4880/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s4880/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s4880/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/tyan/s4882/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s4882/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/tyan/s4882/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_940 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/via/epia-cn/devicetree.cb ============================================================================== --- trunk/src/mainboard/via/epia-cn/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/via/epia-cn/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -53,9 +53,9 @@ device pci 12.0 on end # Ethernet end end - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/via/model_c7 # VIA C7 - device apic 0 on end # APIC + device lapic 0 on end # APIC end end end Modified: trunk/src/mainboard/via/epia-m/devicetree.cb ============================================================================== --- trunk/src/mainboard/via/epia-m/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/via/epia-m/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,8 +1,8 @@ chip northbridge/via/vt8623 - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/via/model_c3 - device apic 0 on end + device lapic 0 on end end end Modified: trunk/src/mainboard/via/epia-m700/devicetree.cb ============================================================================== --- trunk/src/mainboard/via/epia-m700/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/via/epia-m700/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -16,9 +16,9 @@ # device pci 11.0 on # Southbridge LPC # end end - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/via/model_c7 # VIA C7 - device apic 0 on end # APIC + device lapic 0 on end # APIC end end end Modified: trunk/src/mainboard/via/epia-n/devicetree.cb ============================================================================== --- trunk/src/mainboard/via/epia-n/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/via/epia-n/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -21,9 +21,9 @@ chip northbridge/via/cn400 # Northbridge - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/via/model_c3 # VIA C3 - device apic 0 on end # APIC + device lapic 0 on end # APIC end end Modified: trunk/src/mainboard/via/epia/devicetree.cb ============================================================================== --- trunk/src/mainboard/via/epia/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/via/epia/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -54,9 +54,9 @@ end end - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/via/model_c3 - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/src/mainboard/via/pc2500e/devicetree.cb ============================================================================== --- trunk/src/mainboard/via/pc2500e/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/via/pc2500e/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -80,9 +80,9 @@ device pci 12.0 on end # Ethernet end end - device apic_cluster 0 on # APIC cluster + device lapic_cluster 0 on # APIC cluster chip cpu/via/model_c7 # VIA C7 - device apic 0 on end # APIC + device lapic 0 on end # APIC end end end Modified: trunk/src/mainboard/via/vt8454c/devicetree.cb ============================================================================== --- trunk/src/mainboard/via/vt8454c/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/via/vt8454c/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -1,7 +1,7 @@ chip northbridge/via/cx700 - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/via/model_c7 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on Modified: trunk/src/mainboard/winent/pl6064/devicetree.cb ============================================================================== --- trunk/src/mainboard/winent/pl6064/devicetree.cb Wed May 5 14:05:25 2010 (r5524) +++ trunk/src/mainboard/winent/pl6064/devicetree.cb Wed May 5 15:12:42 2010 (r5525) @@ -72,9 +72,9 @@ end end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end end Modified: trunk/util/sconfig/lex.yy.c_shipped ============================================================================== --- trunk/util/sconfig/lex.yy.c_shipped Wed May 5 14:05:25 2010 (r5524) +++ trunk/util/sconfig/lex.yy.c_shipped Wed May 5 15:12:42 2010 (r5525) @@ -33,7 +33,7 @@ #if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L /* C99 says to define __STDC_LIMIT_MACROS before including stdint.h, - * if you want the limit (max/min) macros for int types. + * if you want the limit (max/min) macros for int types. */ #ifndef __STDC_LIMIT_MACROS #define __STDC_LIMIT_MACROS 1 @@ -50,10 +50,9 @@ typedef signed char flex_int8_t; typedef short int flex_int16_t; typedef int flex_int32_t; -typedef unsigned char flex_uint8_t; +typedef unsigned char flex_uint8_t; typedef unsigned short int flex_uint16_t; typedef unsigned int flex_uint32_t; -#endif /* ! C99 */ /* Limits of integral types. */ #ifndef INT8_MIN @@ -84,6 +83,8 @@ #define UINT32_MAX (4294967295U) #endif +#endif /* ! C99 */ + #endif /* ! FLEXINT_H */ #ifdef __cplusplus @@ -140,7 +141,15 @@ /* Size of default input buffer. */ #ifndef YY_BUF_SIZE +#ifdef __ia64__ +/* On IA-64, the buffer size is 16k, not 8k. + * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case. + * Ditto for the __ia64__ case accordingly. + */ +#define YY_BUF_SIZE 32768 +#else #define YY_BUF_SIZE 16384 +#endif /* __ia64__ */ #endif /* The state buf must be large enough to hold one state per character in the main buffer. @@ -161,7 +170,7 @@ #define EOB_ACT_LAST_MATCH 2 #define YY_LESS_LINENO(n) - + /* Return all but the first "n" matched characters back to the input stream. */ #define yyless(n) \ do \ @@ -223,7 +232,7 @@ int yy_bs_lineno; /**< The line count. */ int yy_bs_column; /**< The column count. */ - + /* Whether to try to fill the input buffer when we reach the * end of it. */ @@ -368,17 +377,17 @@ flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static yyconst flex_int16_t yy_accept[86] = +static yyconst flex_int16_t yy_accept[87] = { 0, 0, 0, 26, 24, 1, 3, 24, 24, 24, 21, - 21, 19, 22, 22, 22, 22, 22, 24, 24, 24, + 21, 19, 22, 22, 22, 22, 24, 24, 24, 24, 24, 24, 1, 3, 24, 0, 24, 0, 2, 21, - 22, 24, 24, 24, 22, 24, 24, 24, 17, 24, + 22, 24, 24, 22, 24, 24, 24, 17, 24, 24, 24, 7, 24, 24, 24, 23, 23, 20, 24, 24, - 24, 16, 18, 11, 15, 8, 9, 10, 24, 12, - 4, 24, 24, 24, 24, 24, 24, 24, 24, 5, + 16, 18, 11, 15, 24, 8, 9, 10, 24, 4, + 24, 24, 24, 24, 24, 12, 24, 24, 5, 24, 24, 24, 24, 24, 24, 24, 24, 6, 24, 24, - 24, 14, 24, 13, 0 + 24, 14, 24, 24, 13, 0 } ; static yyconst flex_int32_t yy_ec[256] = @@ -421,76 +430,80 @@ 1, 1 } ; -static yyconst flex_int16_t yy_base[91] = +static yyconst flex_int16_t yy_base[92] = { 0, - 0, 0, 146, 0, 143, 147, 141, 31, 35, 32, - 111, 0, 43, 46, 49, 65, 52, 53, 46, 21, - 126, 0, 139, 147, 62, 135, 76, 136, 147, 0, - 75, 86, 118, 117, 78, 110, 120, 120, 0, 107, - 115, 0, 111, 105, 111, 0, 147, 0, 114, 102, - 106, 0, 0, 0, 0, 0, 113, 0, 104, 111, - 0, 108, 106, 92, 105, 102, 84, 78, 85, 0, - 83, 88, 68, 83, 64, 62, 69, 0, 59, 53, - 54, 0, 39, 0, 147, 41, 109, 111, 113, 115 + 0, 0, 144, 0, 141, 145, 139, 31, 35, 32, + 109, 0, 43, 46, 59, 49, 35, 127, 46, 47, + 123, 0, 136, 145, 71, 132, 75, 133, 145, 0, + 72, 80, 115, 75, 108, 118, 118, 0, 105, 105, + 112, 0, 108, 102, 108, 0, 145, 0, 100, 104, + 0, 0, 0, 0, 103, 0, 110, 0, 101, 0, + 106, 105, 103, 89, 100, 103, 81, 75, 0, 89, + 80, 85, 79, 86, 71, 62, 70, 0, 57, 48, + 35, 0, 44, 15, 0, 145, 34, 106, 108, 110, + 112 + } ; -static yyconst flex_int16_t yy_def[91] = +static yyconst flex_int16_t yy_def[92] = { 0, - 85, 1, 85, 86, 85, 85, 86, 87, 88, 86, - 10, 86, 10, 10, 10, 10, 10, 86, 86, 86, - 86, 86, 85, 85, 87, 89, 88, 90, 85, 10, - 10, 10, 86, 86, 10, 86, 86, 86, 86, 86, - 86, 86, 86, 86, 86, 86, 85, 32, 86, 86, - 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, - 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, - 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, - 86, 86, 86, 86, 0, 85, 85, 85, 85, 85 + 86, 1, 86, 87, 86, 86, 87, 88, 89, 87, + 10, 87, 10, 10, 10, 10, 87, 87, 87, 87, + 87, 87, 86, 86, 88, 90, 89, 91, 86, 10, + 10, 10, 87, 10, 87, 87, 87, 87, 87, 87, + 87, 87, 87, 87, 87, 87, 86, 32, 87, 87, + 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, + 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, + 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, + 87, 87, 87, 87, 87, 0, 86, 86, 86, 86, + 86 + } ; -static yyconst flex_int16_t yy_nxt[180] = +static yyconst flex_int16_t yy_nxt[178] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, - 13, 4, 14, 15, 16, 17, 13, 4, 4, 18, - 4, 4, 4, 19, 20, 4, 21, 4, 4, 4, - 4, 4, 26, 26, 43, 22, 28, 29, 30, 30, - 30, 22, 31, 44, 31, 31, 31, 31, 31, 31, - 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, - 31, 38, 41, 26, 26, 84, 46, 34, 42, 83, - 33, 31, 31, 31, 37, 82, 39, 28, 29, 40, - 35, 31, 31, 31, 31, 31, 31, 81, 80, 79, - 78, 36, 48, 48, 48, 77, 48, 76, 48, 48, - - 48, 48, 48, 75, 74, 73, 72, 71, 51, 25, - 25, 27, 27, 26, 26, 28, 28, 70, 69, 68, - 67, 66, 65, 64, 63, 62, 61, 60, 59, 58, - 57, 56, 55, 54, 53, 52, 50, 49, 29, 47, - 23, 45, 32, 24, 23, 85, 3, 85, 85, 85, - 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, - 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, - 85, 85, 85, 85, 85, 85, 85, 85, 85 + 13, 4, 13, 14, 15, 16, 13, 4, 4, 17, + 18, 4, 4, 19, 20, 4, 21, 4, 4, 4, + 4, 4, 26, 26, 22, 22, 28, 29, 30, 30, + 30, 85, 31, 37, 31, 31, 31, 31, 31, 31, + 31, 31, 31, 31, 31, 31, 31, 31, 38, 84, + 43, 39, 41, 83, 33, 31, 31, 31, 42, 44, + 82, 36, 26, 26, 34, 46, 28, 29, 31, 31, + 31, 31, 31, 31, 81, 35, 48, 48, 48, 80, + 48, 79, 48, 48, 48, 48, 48, 78, 77, 76, + + 75, 74, 73, 72, 71, 50, 25, 25, 27, 27, + 26, 26, 28, 28, 70, 69, 68, 67, 66, 65, + 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, + 54, 53, 52, 51, 49, 29, 47, 23, 45, 40, + 32, 24, 23, 86, 3, 86, 86, 86, 86, 86, + 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, + 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, + 86, 86, 86, 86, 86, 86, 86 } ; -static yyconst flex_int16_t yy_chk[180] = +static yyconst flex_int16_t yy_chk[178] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 8, 8, 20, 8, 9, 9, 10, 10, - 10, 86, 10, 20, 10, 10, 10, 10, 10, 13, - 13, 13, 14, 14, 14, 15, 15, 15, 17, 17, - 17, 18, 19, 25, 25, 83, 25, 15, 19, 81, - 14, 16, 16, 16, 17, 80, 18, 27, 27, 18, - 16, 31, 31, 31, 35, 35, 35, 79, 77, 76, - 75, 16, 32, 32, 32, 74, 32, 73, 32, 32, - - 32, 32, 32, 72, 71, 69, 68, 67, 35, 87, - 87, 88, 88, 89, 89, 90, 90, 66, 65, 64, - 63, 62, 60, 59, 57, 51, 50, 49, 45, 44, - 43, 41, 40, 38, 37, 36, 34, 33, 28, 26, - 23, 21, 11, 7, 5, 3, 85, 85, 85, 85, - 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, - 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, - 85, 85, 85, 85, 85, 85, 85, 85, 85 + 1, 1, 8, 8, 87, 8, 9, 9, 10, 10, + 10, 84, 10, 17, 10, 10, 10, 10, 10, 13, + 13, 13, 14, 14, 14, 16, 16, 16, 17, 83, + 20, 17, 19, 81, 14, 15, 15, 15, 19, 20, + 80, 16, 25, 25, 15, 25, 27, 27, 31, 31, + 31, 34, 34, 34, 79, 15, 32, 32, 32, 77, + 32, 76, 32, 32, 32, 32, 32, 75, 74, 73, + + 72, 71, 70, 68, 67, 34, 88, 88, 89, 89, + 90, 90, 91, 91, 66, 65, 64, 63, 62, 61, + 59, 57, 55, 50, 49, 45, 44, 43, 41, 40, + 39, 37, 36, 35, 33, 28, 26, 23, 21, 18, + 11, 7, 5, 3, 86, 86, 86, 86, 86, 86, + 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, + 86, 86, 86, 86, 86, 86, 86, 86, 86, 86, + 86, 86, 86, 86, 86, 86, 86 } ; static yy_state_type yy_last_accepting_state; @@ -589,7 +602,7 @@ #endif static void yyunput (int c,char *buf_ptr ); - + #ifndef yytext_ptr static void yy_flex_strncpy (char *,yyconst char *,int ); #endif @@ -610,7 +623,12 @@ /* Amount of stuff to slurp up with each read. */ #ifndef YY_READ_BUF_SIZE +#ifdef __ia64__ +/* On IA-64, the buffer size is 16k, not 8k */ +#define YY_READ_BUF_SIZE 16384 +#else #define YY_READ_BUF_SIZE 8192 +#endif /* __ia64__ */ #endif /* Copy whatever the last rule matched to the standard output. */ @@ -618,7 +636,7 @@ /* This used to be an fputs(), but since the string might contain NUL's, * we now use fwrite(). */ -#define ECHO fwrite( yytext, yyleng, 1, yyout ) +#define ECHO do { if (fwrite( yytext, yyleng, 1, yyout )) {} } while (0) #endif /* Gets input and stuffs it into "buf". number of characters read, or YY_NULL, @@ -629,7 +647,7 @@ if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ { \ int c = '*'; \ - int n; \ + size_t n; \ for ( n = 0; n < max_size && \ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ buf[n] = (char) c; \ @@ -710,7 +728,7 @@ register yy_state_type yy_current_state; register char *yy_cp, *yy_bp; register int yy_act; - + if ( !(yy_init) ) { (yy_init) = 1; @@ -762,13 +780,13 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 86 ) + if ( yy_current_state >= 87 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 147 ); + while ( yy_base[yy_current_state] != 145 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -1172,7 +1190,7 @@ { register yy_state_type yy_current_state; register char *yy_cp; - + yy_current_state = (yy_start); for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp ) @@ -1186,7 +1204,7 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 86 ) + if ( yy_current_state >= 87 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; @@ -1214,11 +1232,11 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 86 ) + if ( yy_current_state >= 87 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; - yy_is_jam = (yy_current_state == 85); + yy_is_jam = (yy_current_state == 86); return yy_is_jam ? 0 : yy_current_state; } @@ -1226,7 +1244,7 @@ static void yyunput (int c, register char * yy_bp ) { register char *yy_cp; - + yy_cp = (yy_c_buf_p); /* undo effects of setting up yytext */ @@ -1269,7 +1287,7 @@ { int c; - + *(yy_c_buf_p) = (yy_hold_char); if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR ) @@ -1336,12 +1354,12 @@ /** Immediately switch to a different input stream. * @param input_file A readable stream. - * + * * @note This function does not reset the start condition to @c INITIAL . */ void yyrestart (FILE * input_file ) { - + if ( ! YY_CURRENT_BUFFER ){ yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = @@ -1354,11 +1372,11 @@ /** Switch to a different input buffer. * @param new_buffer The new input buffer. - * + * */ void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer ) { - + /* TODO. We should be able to replace this entire function body * with * yypop_buffer_state(); @@ -1398,13 +1416,13 @@ /** Allocate and initialize an input buffer state. * @param file A readable stream. * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE. - * + * * @return the allocated buffer state. */ YY_BUFFER_STATE yy_create_buffer (FILE * file, int size ) { YY_BUFFER_STATE b; - + b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); @@ -1427,11 +1445,11 @@ /** Destroy the buffer. * @param b a buffer created with yy_create_buffer() - * + * */ void yy_delete_buffer (YY_BUFFER_STATE b ) { - + if ( ! b ) return; @@ -1447,7 +1465,7 @@ #ifndef __cplusplus extern int isatty (int ); #endif /* __cplusplus */ - + /* Initializes or reinitializes a buffer. * This function is sometimes called more than once on the same buffer, * such as during a yyrestart() or at EOF. @@ -1456,7 +1474,7 @@ { int oerrno = errno; - + yy_flush_buffer(b ); b->yy_input_file = file; @@ -1472,13 +1490,13 @@ } b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0; - + errno = oerrno; } /** Discard all buffered characters. On the next scan, YY_INPUT will be called. * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER. - * + * */ void yy_flush_buffer (YY_BUFFER_STATE b ) { @@ -1507,7 +1525,7 @@ * the current state. This function will allocate the stack * if necessary. * @param new_buffer The new state. - * + * */ void yypush_buffer_state (YY_BUFFER_STATE new_buffer ) { @@ -1537,7 +1555,7 @@ /** Removes and deletes the top of the stack, if present. * The next element becomes the new top. - * + * */ void yypop_buffer_state (void) { @@ -1561,7 +1579,7 @@ static void yyensure_buffer_stack (void) { int num_to_alloc; - + if (!(yy_buffer_stack)) { /* First allocation is just for 2 elements, since we don't know if this @@ -1574,9 +1592,9 @@ ); if ( ! (yy_buffer_stack) ) YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" ); - + memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*)); - + (yy_buffer_stack_max) = num_to_alloc; (yy_buffer_stack_top) = 0; return; @@ -1604,13 +1622,13 @@ /** Setup the input buffer state to scan directly from a user-specified character buffer. * @param base the character buffer * @param size the size in bytes of the character buffer - * - * @return the newly allocated buffer state object. + * + * @return the newly allocated buffer state object. */ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) { YY_BUFFER_STATE b; - + if ( size < 2 || base[size-2] != YY_END_OF_BUFFER_CHAR || base[size-1] != YY_END_OF_BUFFER_CHAR ) @@ -1639,22 +1657,22 @@ /** Setup the input buffer state to scan a string. The next call to yylex() will * scan from a @e copy of @a str. * @param yystr a NUL-terminated string to scan - * + * * @return the newly allocated buffer state object. * @note If you want to scan bytes that may contain NUL values, then use * yy_scan_bytes() instead. */ YY_BUFFER_STATE yy_scan_string (yyconst char * yystr ) { - + return yy_scan_bytes(yystr,strlen(yystr) ); } /** Setup the input buffer state to scan the given bytes. The next call to yylex() will * scan from a @e copy of @a bytes. - * @param bytes the byte buffer to scan - * @param len the number of bytes in the buffer pointed to by @a bytes. - * + * @param yybytes the byte buffer to scan + * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes. + * * @return the newly allocated buffer state object. */ YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, int _yybytes_len ) @@ -1663,7 +1681,7 @@ char *buf; yy_size_t n; int i; - + /* Get memory for full buffer, including space for trailing EOB's. */ n = _yybytes_len + 2; buf = (char *) yyalloc(n ); @@ -1717,16 +1735,16 @@ /* Accessor methods (get/set functions) to struct members. */ /** Get the current line number. - * + * */ int yyget_lineno (void) { - + return yylineno; } /** Get the input stream. - * + * */ FILE *yyget_in (void) { @@ -1734,7 +1752,7 @@ } /** Get the output stream. - * + * */ FILE *yyget_out (void) { @@ -1742,7 +1760,7 @@ } /** Get the length of the current token. - * + * */ int yyget_leng (void) { @@ -1750,7 +1768,7 @@ } /** Get the current token. - * + * */ char *yyget_text (void) @@ -1760,18 +1778,18 @@ /** Set the current line number. * @param line_number - * + * */ void yyset_lineno (int line_number ) { - + yylineno = line_number; } /** Set the input stream. This does not discard the current * input buffer. * @param in_str A readable stream. - * + * * @see yy_switch_to_buffer */ void yyset_in (FILE * in_str ) @@ -1825,7 +1843,7 @@ /* yylex_destroy is for both reentrant and non-reentrant scanners. */ int yylex_destroy (void) { - + /* Pop the buffer stack, destroying each element. */ while(YY_CURRENT_BUFFER){ yy_delete_buffer(YY_CURRENT_BUFFER ); Modified: trunk/util/sconfig/sconfig.l ============================================================================== --- trunk/util/sconfig/sconfig.l Wed May 5 14:05:25 2010 (r5524) +++ trunk/util/sconfig/sconfig.l Wed May 5 15:12:42 2010 (r5525) @@ -36,8 +36,8 @@ pci {yylval.number=PCI; return(BUS);} pnp {yylval.number=PNP; return(BUS);} i2c {yylval.number=I2C; return(BUS);} -apic {yylval.number=APIC; return(BUS);} -apic_cluster {yylval.number=APIC_CLUSTER; return(BUS);} +lapic {yylval.number=APIC; return(BUS);} +lapic_cluster {yylval.number=APIC_CLUSTER; return(BUS);} pci_domain {yylval.number=PCI_DOMAIN; return(BUS);} irq {yylval.number=IRQ; return(RESOURCE);} drq {yylval.number=DRQ; return(RESOURCE);} From svn at coreboot.org Wed May 5 15:13:48 2010 From: svn at coreboot.org (repository service) Date: Wed, 05 May 2010 15:13:48 +0200 Subject: [coreboot] [commit] r5526 - trunk/util/sconfig Message-ID: Author: oxygene Date: Wed May 5 15:13:47 2010 New Revision: 5526 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5526 Log: Improve the sconfig parser: - The device tree must start with a chip (not a device) - It's more clearly visible at which places chip, device, register and resource can be used. Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Acked-by: Peter Stuge Modified: trunk/util/sconfig/sconfig.tab.c_shipped trunk/util/sconfig/sconfig.y Modified: trunk/util/sconfig/sconfig.tab.c_shipped ============================================================================== --- trunk/util/sconfig/sconfig.tab.c_shipped Wed May 5 15:12:42 2010 (r5525) +++ trunk/util/sconfig/sconfig.tab.c_shipped Wed May 5 15:13:47 2010 (r5526) @@ -380,12 +380,12 @@ /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 22 +#define YYLAST 24 /* YYNTOKENS -- Number of terminals. */ #define YYNTOKENS 23 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 12 +#define YYNNTS 11 /* YYNRULES -- Number of rules. */ #define YYNRULES 17 /* YYNRULES -- Number of states. */ @@ -436,26 +436,26 @@ YYRHS. */ static const yytype_uint8 yyprhs[] = { - 0, 0, 3, 4, 7, 9, 11, 14, 17, 18, - 21, 24, 25, 26, 32, 33, 41, 46 + 0, 0, 3, 4, 7, 10, 13, 16, 17, 20, + 23, 26, 27, 28, 34, 35, 43, 48 }; /* YYRHS -- A `-1'-separated list of the rules' RHS. */ static const yytype_int8 yyrhs[] = { - 24, 0, -1, -1, 25, 26, -1, 29, -1, 31, - -1, 27, 26, -1, 27, 34, -1, -1, 28, 26, - -1, 28, 33, -1, -1, -1, 3, 12, 30, 27, - 9, -1, -1, 4, 7, 22, 6, 32, 28, 9, - -1, 8, 22, 10, 22, -1, 5, 12, 10, 12, - -1 + 24, 0, -1, -1, 25, 28, -1, 26, 30, -1, + 26, 28, -1, 26, 33, -1, -1, 27, 30, -1, + 27, 28, -1, 27, 32, -1, -1, -1, 3, 12, + 29, 26, 9, -1, -1, 4, 7, 22, 6, 31, + 27, 9, -1, 8, 22, 10, 22, -1, 5, 12, + 10, 12, -1 }; /* YYRLINE[YYN] -- source line where rule number YYN was defined. */ static const yytype_uint8 yyrline[] = { - 0, 34, 34, 34, 36, 36, 38, 38, 38, 40, - 40, 40, 42, 42, 52, 52, 64, 67 + 0, 34, 34, 34, 36, 36, 36, 36, 38, 38, + 38, 38, 40, 40, 50, 50, 62, 65 }; #endif @@ -467,8 +467,8 @@ "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C", "APIC", "APIC_CLUSTER", "PCI_DOMAIN", "IRQ", "DRQ", "IO", "NUMBER", - "$accept", "devtree", "$@1", "devchip", "devices", "devicesorresources", - "chip", "@2", "device", "@3", "resource", "registers", 0 + "$accept", "devtree", "$@1", "chipchildren", "devicechildren", "chip", + "@2", "device", "@3", "resource", "registers", 0 }; #endif @@ -486,14 +486,14 @@ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 23, 25, 24, 26, 26, 27, 27, 27, 28, - 28, 28, 30, 29, 32, 31, 33, 34 + 0, 23, 25, 24, 26, 26, 26, 26, 27, 27, + 27, 27, 29, 28, 31, 30, 32, 33 }; /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ static const yytype_uint8 yyr2[] = { - 0, 2, 0, 2, 1, 1, 2, 2, 0, 2, + 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, 2, 0, 0, 5, 0, 7, 4, 4 }; @@ -502,35 +502,35 @@ means the default is an error. */ static const yytype_uint8 yydefact[] = { - 2, 0, 0, 1, 0, 0, 3, 4, 5, 12, - 0, 8, 0, 0, 14, 0, 13, 6, 7, 11, - 0, 0, 0, 0, 15, 9, 10, 17, 0, 0, + 2, 0, 0, 1, 0, 3, 12, 7, 0, 0, + 0, 13, 5, 4, 6, 0, 0, 0, 0, 14, + 17, 11, 0, 0, 15, 9, 8, 10, 0, 0, 16 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { - -1, 1, 2, 6, 13, 21, 7, 11, 8, 19, - 26, 18 + -1, 1, 2, 8, 22, 5, 7, 13, 21, 27, + 14 }; /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing STATE-NUM. */ -#define YYPACT_NINF -14 +#define YYPACT_NINF -10 static const yytype_int8 yypact[] = { - -14, 6, 8, -14, 2, 9, -14, -14, -14, -14, - -9, -14, 11, -2, -14, 3, -14, -14, -14, -14, - 10, 1, 7, -4, -14, -14, -14, -14, 12, -1, - -14 + -10, 6, 5, -10, -1, -10, -10, -10, -2, 8, + 0, -10, -10, -10, -10, -9, 7, 10, 9, -10, + -10, -10, 1, -4, -10, -10, -10, -10, 12, -3, + -10 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -14, -14, -14, -13, -14, -14, -14, -14, -14, -14, - -14, -14 + -10, -10, -10, -10, -10, -8, -10, 2, -10, -10, + -10 }; /* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If @@ -540,25 +540,25 @@ #define YYTABLE_NINF -1 static const yytype_uint8 yytable[] = { - 17, 4, 5, 15, 4, 5, 3, 16, 25, 23, - 24, 4, 5, 12, 9, 20, 10, 14, 28, 27, - 22, 30, 29 + 12, 4, 9, 10, 4, 9, 3, 11, 4, 23, + 24, 6, 16, 17, 25, 15, 19, 18, 28, 30, + 0, 20, 29, 0, 26 }; -static const yytype_uint8 yycheck[] = +static const yytype_int8 yycheck[] = { - 13, 3, 4, 5, 3, 4, 0, 9, 21, 8, - 9, 3, 4, 22, 12, 12, 7, 6, 22, 12, - 10, 22, 10 + 8, 3, 4, 5, 3, 4, 0, 9, 3, 8, + 9, 12, 12, 22, 22, 7, 6, 10, 22, 22, + -1, 12, 10, -1, 22 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 24, 25, 0, 3, 4, 26, 29, 31, 12, - 7, 30, 22, 27, 6, 5, 9, 26, 34, 32, - 12, 28, 10, 8, 9, 26, 33, 12, 22, 10, + 0, 24, 25, 0, 3, 28, 12, 29, 26, 4, + 5, 9, 28, 30, 33, 7, 12, 22, 10, 6, + 12, 31, 27, 8, 9, 28, 30, 32, 22, 10, 22 }; Modified: trunk/util/sconfig/sconfig.y ============================================================================== --- trunk/util/sconfig/sconfig.y Wed May 5 15:12:42 2010 (r5525) +++ trunk/util/sconfig/sconfig.y Wed May 5 15:13:47 2010 (r5526) @@ -31,19 +31,17 @@ } %token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER %% -devtree: { cur_parent = cur_bus = head; } devchip { postprocess_devtree(); } ; +devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ; -devchip: chip | device ; +chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; -devices: devices devchip | devices registers | ; - -devicesorresources: devicesorresources devchip | devicesorresources resource | ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | /* empty */ ; chip: CHIP STRING /* == path */ { $$ = new_chip(cur_parent, cur_bus, $2); cur_parent = $$; } - devices END { + chipchildren END { cur_parent = $3->parent; fold_in($3); add_header($3); @@ -54,7 +52,7 @@ cur_parent = $$; cur_bus = $$; } - devicesorresources END { + devicechildren END { cur_parent = $5->parent; cur_bus = $5->bus; fold_in($5); From svn at coreboot.org Wed May 5 15:53:46 2010 From: svn at coreboot.org (coreboot) Date: Wed, 05 May 2010 13:53:46 -0000 Subject: [coreboot] #146: memalign requests huge amounts of memory for large alignments (was: memalign faild with 4k boundary) In-Reply-To: <057.f47ec0d42244277ad07d82e5f91f0d2c@coreboot.org> References: <057.f47ec0d42244277ad07d82e5f91f0d2c@coreboot.org> Message-ID: <066.4cd116b75fc2531eaa06ec83df22bfae@coreboot.org> #146: memalign requests huge amounts of memory for large alignments -------------------------------------+-------------------------------------- Reporter: wangqingpei@? | Owner: oxygene Type: defect | Status: closed Priority: blocker | Milestone: Component: libpayload | Resolution: fixed Keywords: | Dependencies: Patchstatus: there is no patch | -------------------------------------+-------------------------------------- Changes (by oxygene): * keywords: memalign crashed => * status: assigned => closed * resolution: => fixed Comment: Fixed in r5298, which included the attached patch. memalign doesn't try to allocate at least 100 units of memory (which meant 400kb for 4kb of 4kb-aligned memory. It only allocates at least a kilobyte of data, which should match most use cases: For more common 16byte requests, 1kb is allocated and pooled for 16byte requests, for relatively rare 4kb requests, 4kb is allocated (as it's already >1kb) -- Ticket URL: coreboot From mylesgw at gmail.com Wed May 5 16:09:27 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 5 May 2010 08:09:27 -0600 Subject: [coreboot] Porting to RS780/SB700 board In-Reply-To: <4BE088A2.3090100@assembler.cz> References: <7A8F712D13B74FA5A5E2230AEE5E4B52@chimp> <4BE088A2.3090100@assembler.cz> Message-ID: > > Why are we setting anything in the 0-0x80000 range ( msr 0x250) or the > > 0x80000-0x9ffff range (msr 0x258)? > > addr = 0x250; > <------>lo = 0x1E1E1E1E; > <------>hi = lo; > <------>_WRMSR(addr, lo, hi);<-><------>/* 0 - 512K = WB Mem */ > <------>addr = 0x258; > <------>_WRMSR(addr, lo, hi);<-><------>/* 512K - 640K = WB Mem */ > > In mctmtr_d.c Thanks for pointing out where it's done. I'm surprised that fam10 sets this up so early. K8 doesn't set any of that up until much later. Thanks, Myles From mylesgw at gmail.com Wed May 5 16:22:32 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 5 May 2010 08:22:32 -0600 Subject: [coreboot] Hardware damaged? In-Reply-To: <201005050902.59750.mark@tvk.rwth-aachen.de> References: <201005041439.45120.mark@tvk.rwth-aachen.de> <201005041649.23437.mark@tvk.rwth-aachen.de> <201005050902.59750.mark@tvk.rwth-aachen.de> Message-ID: On Wed, May 5, 2010 at 1:02 AM, mark wrote: >> Is there any output on the serial console with Coreboot? ?There should >> have been a lot of it the first time when you got to VGA init. > > The problem is, not even the monitor turns on, which indicates that there is > no VGA init or VGA signal, using both chips. That's not surprising. VGA init is pretty late in the process. > I'll check with a multimeter if there is any current on the pins. > >> has a pin of the socket or the flash been bent? > > some pins of the original chip have been slightly bent, but I fixed them with a > pliers before inserting. Unfortunately my plcc32 extractor is too big for that > board, so the first time I used a screwdriver to extract the chip and after > that I used some filament underneath the chip to plug it out. I like the pushpin method. Cheap, easy, reversible. http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools Thanks, Myles From rminnich at gmail.com Wed May 5 16:27:58 2010 From: rminnich at gmail.com (ron minnich) Date: Wed, 5 May 2010 07:27:58 -0700 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: <4BE120B7.4070401@gap.upv.es> References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz> <4BDE768B.3000801@gap.upv.es> <4BE120B7.4070401@gap.upv.es> Message-ID: On Wed, May 5, 2010 at 12:39 AM, Knut Kujat wrote: > - I now know that my resource map must be some kind of faulty. But why > does it work on one CPU and doesn't on another, complete identical, one? It's not about the CPU, it is more about how the mainboard is wired up. And, it is not surprising that it might be wired differently on two mainboards with identical part #s. Supermicro does this type of change frequently. You would really need to boot the factory bios and dump the config registers on all cpus to see if they mainboard has changed somehow. > - How do i manage to correct my resource map? Or how do I create a good > resource map? dump the factory bios. > - Since it seems to boot fine without resource map. Do I really need one? you really need one. > - And the last one, If I don't setup the res. map, who does it? nobody. ron From mylesgw at gmail.com Wed May 5 16:44:13 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 5 May 2010 08:44:13 -0600 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es><20100430154443.GA15966@countzero.vandewege.net><4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz><4BDE768B.3000801@gap.upv.es> <4BE120B7.4070401@gap.upv.es> Message-ID: I've had questions about resource maps too. > > - I now know that my resource map must be some kind of faulty. But why > > does it work on one CPU and doesn't on another, complete identical, one? > > It's not about the CPU, it is more about how the mainboard is wired > up. And, it is not surprising that it might be wired differently > on two mainboards with identical part #s. Supermicro does this type of > change frequently. You would really need to boot the factory > bios and dump the config registers on all cpus to see if they > mainboard has changed somehow. The reason he got to that conclusion was that the same motherboard boots differently with a different CPU and the identical BIOS. I don't understand how it could be a wiring issue. If the failure is consistent, can you use showallroutes(BIOS_INFO, PCI_DEV(0, 0x18, 1)); right before your resource map gets set. I think that might help us figure it out. > > - How do i manage to correct my resource map? Or how do I create a good > > resource map? > > dump the factory bios. I think this can be problematic, since by the time you can dump the factory BIOS resource allocation has already occurred. The resource map is only good for early initialization, before resource allocation, right? > > - Since it seems to boot fine without resource map. Do I really need > one? I think the problem comes if values happen to be left over from a previous boot. I guess it could happen with different "default" values for different processors, too. Then devices that should be reachable won't respond. > you really need one. > > > - And the last one, If I don't setup the res. map, who does it? > > nobody. At least until resource allocation. Thanks, Myles From rminnich at gmail.com Wed May 5 16:58:45 2010 From: rminnich at gmail.com (ron minnich) Date: Wed, 5 May 2010 07:58:45 -0700 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz> <4BDE768B.3000801@gap.upv.es> <4BE120B7.4070401@gap.upv.es> Message-ID: On Wed, May 5, 2010 at 7:44 AM, Myles Watson wrote: > The reason he got to that conclusion was that the same motherboard boots > differently with a different CPU and the identical BIOS. ?I don't understand > how it could be a wiring issue. I went back and managed to misunderstand the post, I thought it was same motherboard type but two different boards. Sorry. > I think this can be problematic, since by the time you can dump the factory > BIOS resource allocation has already occurred. ?The resource map is only > good for early initialization, before resource allocation, right? hmm. I had always used the bios map as a starting point and it had worked well for me. But maybe things are much harder now. It is true that you need to do a bit of interpretation of the map once the factory BIOS has set it up. Does resource allocation get all the bits, even legacy ones? Are there not some resource map values that a resource allocator can not figure out? ron From mylesgw at gmail.com Wed May 5 17:17:32 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 5 May 2010 09:17:32 -0600 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz> <4BDE768B.3000801@gap.upv.es> <4BE120B7.4070401@gap.upv.es> Message-ID: <3E82FA80444D43E0B48A8585DB6D1815@chimp> > > I think this can be problematic, since by the time you can dump the > factory > > BIOS resource allocation has already occurred. ?The resource map is only > > good for early initialization, before resource allocation, right? > > hmm. I had always used the bios map as a starting point and it had > worked well for me. I think most of the time it should work fine, but we have some hard-coded addresses where the chipset is expected to live in early setup routines, and they might break. My resource map sets: DRAM mappings for each node MMIO mappings for each HT chain PCI IO mappings for each HT chain PCI Bus numbers for each HT chain I think they should only be needed for things like ck804_early_setup_car.c, where I/O is being used and set up. If the mappings aren't configured the reads and writes don't reach the chipset. > But maybe things are much harder now. It is true that you need to do a bit > of > interpretation of the map once the factory BIOS has set it up. > > Does resource allocation get all the bits, even legacy ones? Are there > not some resource map values that > a resource allocator can not figure out? I don't know. Once resource allocation is done you should know where your VGA card is, and where your Southbridge is. I'm probably missing something, but I think once resource allocation is done all of the registers that are touched in the resource map have been rewritten. Thanks, Myles From svn at coreboot.org Wed May 5 18:25:17 2010 From: svn at coreboot.org (coreboot) Date: Wed, 05 May 2010 16:25:17 -0000 Subject: [coreboot] #18: autoprobe apic cluster and application processors on K8 systems In-Reply-To: <042.3b6a74bac1755b1786072950302df3e4@coreboot.org> References: <042.3b6a74bac1755b1786072950302df3e4@coreboot.org> Message-ID: <051.96e6667ebe774827ce1b569cba262a59@coreboot.org> #18: autoprobe apic cluster and application processors on K8 systems -------------------------+-------------------------------------------------- Reporter: stepan | Owner: oxygene Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: K8, cleanup Dependencies: | Patchstatus: patch needs review -------------------------+-------------------------------------------------- Changes (by stepan): * patchstatus: there is no patch => patch needs review -- Ticket URL: coreboot From mylesgw at gmail.com Wed May 5 18:35:41 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 5 May 2010 10:35:41 -0600 Subject: [coreboot] [PATCH] Add AES to devicetree.cb for AMD LX boards In-Reply-To: <4BE0B051.20905@traverse.com.au> References: <4BDFD5AC.4020706@traverse.com.au> <4BE02BE4.6080209@coresystems.de> <4BE0B051.20905@traverse.com.au> Message-ID: On Tue, May 4, 2010 at 5:40 PM, Nathan Williams wrote: > On 5/05/2010 12:15 AM, Stefan Reinauer wrote: >> On 5/4/10 10:07 AM, Nathan Williams wrote: >>> Signed-off-by: Nathan Williams >>> >>> - ? ? ? ? ? ? ? ? ? ?device pci 1.0 on end >>> - ? ? ? ? ? ?device pci 1.1 on end >>> + ? ? ? ? ? ? ? ? ? ?device pci 1.0 on end # Northbridge >>> + ? ? ? ? ? ?device pci 1.1 on end # Graphics >>> + ? ? ? ? ? ?device pci 1.2 on end # AES >> What's the impact of that change? >> >> Stefan >> > > I don't think it makes any difference. ?I just added it for completeness/documentation. In general we try to only specify the devices that must be specified because they have special driver needs. It keeps the device trees cleaner. Things that can be probed for and initialized by the generic code are better left alone. Maybe a comment in the lx code would be a good way to document other functions. Thanks, Myles From joop_boonen at web.de Wed May 5 21:21:54 2010 From: joop_boonen at web.de (Joop Boonen) Date: Wed, 5 May 2010 21:21:54 +0200 Subject: [coreboot] FILO issue? Message-ID: <813549e1d4a99e1405f7db53f2c9a06c.squirrel@www.boonen.name> All, I have an issue that might be related to FILO. I don't seem to be able to read the filesystem. I've attached the serial session log. I've compiled filo with all debug flags. Regards, Joop. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: session_debug_filo_20100505.txt URL: From joe.korty at ccur.com Wed May 5 22:06:08 2010 From: joe.korty at ccur.com (Joe Korty) Date: Wed, 5 May 2010 16:06:08 -0400 Subject: [coreboot] H8DME-2 woes, hints? Message-ID: <20100505200608.GA15441@tsunami.ccur.com> As a first time coreboot user, I thought that I should first try it out on a supported board. That way I would learn the ropes a bit before even thinking about doing something more challenging. Naturally I am having troubles. I suspect that as a newbie I am probably doing something stupid. But then I've heard that mb manufacturers like to change things around without notice, so maybe I'm doing things right and what was once a supported mb, no longer is. The hardware: SuperMicro H8DME-2. Four 1Gbyte DDR2-667/533/400 Registered ECC SDRAM sticks from Crucial. Two Quad-Core AMD 2378 2.4 GHz Processors. Onboard video. One SATA disk. One PATA DVD-ROM reader. NULL modem serial cable from COM1 to COM1 on another PC. The details: When booting coreboot, nothing happens for about 45 seconds. Then the fans speed up to high and some messages start appearing on the serial line. These messages print rather slowly (maybe 1 second/message). They are: coreboot-4.0-r5521M Wed May 5 10:53:42 EDT 2010 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=00 Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=00 At this point coreboot ceases to make forward progress. The fans remain spinning at their highest settings. The VGA screen is blank throughout. I put some printk's in setup_smb2, the crashing routine. They show that setup_temp_row is called by setup_smb2 but never returns. Anyways, I've attached the entire build procedure I used to achieve these results. Perhaps there is something in this sequence that I am doing wrong??? And, what kind of luck have others had with recent H8DME-2 boards? Regards, Joe # install RHEL5 32-bit on H8DME-2 test stand # log in as myself # --- make flashrom(1) tool cd svn co svn://coreboot.org/flashrom/trunk flashrom cd flashrom make sudo make install # --- get latest coreboot sources cd .. svn co svn://coreboot.org/coreboot/trunk coreboot cd coreboot # --- get pre-built SeaBIOS coreboot payload wget -O payload.elf http://linuxtogo.org/~kevin/SeaBIOS/bios.bin.elf-0.6.0 # --- extract H8DME-2's onboard Video ROM fgrep 'Video ROM' /proc/iomem # displays "000c0000-000cafff : Video ROM" sudo dd if=/dev/mem of=/tmp/vgabios.bin bs=4k skip=$((0xc0)) count=$((0xb)) # --- figure out the Video ROM's PCI Vendor,Device ID # --- I _think_ the numbers I want are the second set shown, ie "15d9:1611". lspci -v | fgrep VGA # displays "01:05.0 VGA compatible controller: ATI Technologies Inc ES1000 ..." lspci -vn | fgrep -A1 01:05.0 # displays "01:05.0 0300: 1002:515e (rev 02) Subsystem: 15d9:1611" # --- build-n-burn coreboot make menuconfig # select Mainboard -> SuperMicro -> H8DME-2 # select Payload -> Add A Payload -> ELF # select VGA Bios -> Add A VGA BIOS -> VGA Device PCI IDS -> "15d9,1611" make /usr/local/sbin/flashrom -w build/coreboot.rom From r.marek at assembler.cz Wed May 5 22:08:57 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Wed, 05 May 2010 22:08:57 +0200 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: <20100505000351.GA21290@countzero.vandewege.net> References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> <4BE05BD9.7050302@web.de> <2779711E82D84A8EBC18050C95858E3A@chimp> <20100505000351.GA21290@countzero.vandewege.net> Message-ID: <4BE1D059.3010403@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, I used the Sillicon Image PCI card with onboard BIOS. It works well in SeaBIOS. I would say here would be enough to extract the optionrom from orig BIOS. And SeaBIOS will assign/use it. By the bizarre coincidence I had this board @home and booting from IDE worked well (under SeaBIOS). Attached patch enables bios_extract to extract the BIOS ;) oprom_4.rom is for SATA oprom_3.rom is FastTRAK I think you can http://www.coreboot.org/SeaBIOS go same as for Adding the VGA rom here. As a side note one could program an GPL rombios for this controller - any takers? Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvh0FgACgkQ3J9wPJqZRNWS9ACfX/zKWvtO+WV/wwHkDxPdq6P9 qZgAoIrO8y4BaYJBV2e/Lx//gsbpy6I/ =vBZM -----END PGP SIGNATURE----- -------------- next part -------------- A non-text attachment was scrubbed... Name: add_ServerBIOS3.patch Type: text/x-diff Size: 535 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: add_ServerBIOS3.patch.sig Type: application/octet-stream Size: 72 bytes Desc: not available URL: From mylesgw at gmail.com Wed May 5 22:26:15 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 5 May 2010 14:26:15 -0600 Subject: [coreboot] H8DME-2 woes, hints? In-Reply-To: <20100505200608.GA15441@tsunami.ccur.com> References: <20100505200608.GA15441@tsunami.ccur.com> Message-ID: On Wed, May 5, 2010 at 2:06 PM, Joe Korty wrote: > As a first time coreboot user, I thought that I should first try it out > on a supported board. ?That way I would learn the ropes a bit before even > thinking about doing something more challenging. > > Naturally I am having troubles. ?I suspect that as a newbie I am probably > doing something stupid. ?But then I've heard that mb manufacturers like > to change things around without notice, so maybe I'm doing things right > and what was once a supported mb, no longer is. It looks like you're doing things right. It's dying really early, though. > The details: > ? When booting coreboot, nothing happens for about 45 seconds. > ? Then the fans speed up to high and some messages start appearing > ? on the serial line. ?These messages print rather slowly (maybe > ? 1 second/message). ?They are: > > ? ? ? ?coreboot-4.0-r5521M Wed May ?5 10:53:42 EDT 2010 starting... > ? ? ? ?*sysinfo range: [000cf000,000cf730] > ? ? ? ?bsp_apicid=00 > ? ? ? ?Enabling routing table for node 00 done. > ? ? ? ?Enabling SMP settings > ? ? ? ?(0,1) link=00 You could try an earlier revision. I can't think of what would slow it down that much. > ? At this point coreboot ceases to make forward progress. ?The > ? fans remain spinning at their highest settings. ?The VGA screen > ? is blank throughout. > > ? I put some printk's in setup_smb2, the crashing routine. ?They show > ? that setup_temp_row is called by setup_smb2 but never returns. Since it takes so long to get there, I think you'll have better luck trying to figure out what's wrong before that. > ? # --- extract H8DME-2's onboard Video ROM > > ? fgrep 'Video ROM' /proc/iomem > ? # displays "000c0000-000cafff : Video ROM" > ? sudo dd if=/dev/mem of=/tmp/vgabios.bin bs=4k skip=$((0xc0)) count=$((0xb)) > > ? # --- figure out the Video ROM's PCI Vendor,Device ID > ? # --- I _think_ the numbers I want are the second set shown, ie "15d9:1611". You want the first set. The second set is Supermicro's board ID. > ? lspci -v | fgrep VGA > ? # displays "01:05.0 VGA compatible controller: ATI Technologies Inc ES1000 ..." > > ? lspci -vn | fgrep -A1 01:05.0 > ? # displays "01:05.0 0300: 1002:515e (rev 02) > ? ? ? ? ? ? ? Subsystem: 15d9:1611" > Good luck, Myles From joop_boonen at web.de Wed May 5 23:42:23 2010 From: joop_boonen at web.de (Joop Boonen) Date: Wed, 5 May 2010 23:42:23 +0200 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> <4BE05BD9.7050302@web.de> <2779711E82D84A8EBC18050C95858E3A@chimp> Message-ID: On Wed, May 5, 2010 12:35 am, Myles Watson wrote: >>> I think the most likely culprit is SB_HT_CHAIN_ON_BUS0. ?Could you >>> change it to 1 in src/mainboard/arima/hdama/Kconfig, make oldconfig, >>> and test? >> >> I've tested it. I get the filo screen now. > Great. I checked that in Rev 5522. > >> When I do a probe I don't see any IDE device yet. Neither IDE nor SATA >> SIL3114 drive. This also didn't work for version 4920. > > Have you tried SeaBIOS? I haven't used FILO much. In your log it > looks like FILO is expecting to find something in your CMOS that it > doesn't find. > > ERROR: No such CMOS option (boot_devices) > menu: hda3:/boot/filo/menu.lst I've just used SeaBIOS. With SeaBIOS LInux boots without a problem (except for ACPI, I understood this is not (fully) supported yet. I have a feeling that FILO has an issue? > > You could look into that. > > Thanks, > Myles > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From joop_boonen at web.de Wed May 5 23:43:41 2010 From: joop_boonen at web.de (Joop Boonen) Date: Wed, 5 May 2010 23:43:41 +0200 Subject: [coreboot] FILO issue? In-Reply-To: <813549e1d4a99e1405f7db53f2c9a06c.squirrel@www.boonen.name> References: <813549e1d4a99e1405f7db53f2c9a06c.squirrel@www.boonen.name> Message-ID: On Wed, May 5, 2010 9:21 pm, Joop Boonen wrote: > All, > > I have an issue that might be related to FILO. I don't seem to be able to > read the filesystem. > > I've attached the serial session log. > I've compiled filo with all debug flags. > I've just used SeaBIOS. With SeaBIOS LInux boots without a problem (except for ACPI, I understood this is not (fully) supported yet. I have a feeling that FILO has an issue? I booted off an ATA disk. > Regards, > > Joop.-- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From joop_boonen at web.de Wed May 5 23:44:23 2010 From: joop_boonen at web.de (Joop Boonen) Date: Wed, 5 May 2010 23:44:23 +0200 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> <4BE05BD9.7050302@web.de> <2779711E82D84A8EBC18050C95858E3A@chimp> Message-ID: <49a3d329eb3851fc34780542dd2a3365.squirrel@www.boonen.name> On Wed, May 5, 2010 12:35 am, Myles Watson wrote: >>> I think the most likely culprit is SB_HT_CHAIN_ON_BUS0. ?Could you >>> change it to 1 in src/mainboard/arima/hdama/Kconfig, make oldconfig, >>> and test? >> >> I've tested it. I get the filo screen now. > Great. I checked that in Rev 5522. > >> When I do a probe I don't see any IDE device yet. Neither IDE nor SATA >> SIL3114 drive. This also didn't work for version 4920. > > Have you tried SeaBIOS? I haven't used FILO much. In your log it > looks like FILO is expecting to find something in your CMOS that it > doesn't find. > > ERROR: No such CMOS option (boot_devices) > menu: hda3:/boot/filo/menu.lst I've just used SeaBIOS. With SeaBIOS LInux boots without a problem (except for ACPI, I understood this is not (fully) supported yet. I have a feeling that FILO has an issue? I booted off an ATA disk. > > You could look into that. > > Thanks, > Myles > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From r.marek at assembler.cz Wed May 5 23:52:52 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Wed, 05 May 2010 23:52:52 +0200 Subject: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard In-Reply-To: <49a3d329eb3851fc34780542dd2a3365.squirrel@www.boonen.name> References: <63aa5a50178e770268ff8d393d66db99.squirrel@www.boonen.name> <6E38F8796C8343438E450CF5883EB548@chimp> <548738bbc3df124ed25be921f4dcf128.squirrel@www.boonen.name> <4BE05BD9.7050302@web.de> <2779711E82D84A8EBC18050C95858E3A@chimp> <49a3d329eb3851fc34780542dd2a3365.squirrel@www.boonen.name> Message-ID: <4BE1E8B4.5000206@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I think we miss ACPI support for this board and PowerNow. The documentation is available and I think it could be added easily. I'm willing to help give/hints if somebody takes that. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvh6LQACgkQ3J9wPJqZRNWCmQCdGESsx0CQN5ynhzSMyKcGsuwQ tPkAn0xt4wTbmcKDka03rciPSSAv4vzf =+yhi -----END PGP SIGNATURE----- From anders at jenbo.dk Thu May 6 00:07:54 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Thu, 06 May 2010 00:07:54 +0200 Subject: [coreboot] [CoreBoot][Patch] Support for Gigabyte GA-6BXE Message-ID: <1273097274.22903.5.camel@anders-laptop> Adds initial support for Gigabyte GA-6BXE. Known issues: The serial port runs at 2x the baud. Signed-off-by: Anders Jenbo --- Anders Jenbo -------------- next part -------------- A non-text attachment was scrubbed... Name: ga-6bxe.patch Type: text/x-patch Size: 12457 bytes Desc: not available URL: From knuku at gap.upv.es Thu May 6 09:17:01 2010 From: knuku at gap.upv.es (Knut Kujat) Date: Thu, 06 May 2010 09:17:01 +0200 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: <3E82FA80444D43E0B48A8585DB6D1815@chimp> References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz> <4BDE768B.3000801@gap.upv.es> <4BE120B7.4070401@gap.upv.es> <3E82FA80444D43E0B48A8585DB6D1815@chimp> Message-ID: <4BE26CED.2090501@gap.upv.es> Myles Watson escribi?: > > >>> I think this can be problematic, since by the time you can dump the >>> >> factory >> >>> BIOS resource allocation has already occurred. The resource map is only >>> good for early initialization, before resource allocation, right? >>> >> hmm. I had always used the bios map as a starting point and it had >> worked well for me. >> > > I think most of the time it should work fine, but we have some hard-coded > addresses where the chipset is expected to live in early setup routines, and > they might break. > > My resource map sets: > DRAM mappings for each node > MMIO mappings for each HT chain > PCI IO mappings for each HT chain > PCI Bus numbers for each HT chain > > I think they should only be needed for things like ck804_early_setup_car.c, > where I/O is being used and set up. If the mappings aren't configured the > reads and writes don't reach the chipset. > > >> But maybe things are much harder now. It is true that you need to do a bit >> of >> interpretation of the map once the factory BIOS has set it up. >> >> Does resource allocation get all the bits, even legacy ones? Are there >> not some resource map values that >> a resource allocator can not figure out? >> > > I don't know. Once resource allocation is done you should know where your > VGA card is, and where your Southbridge is. I'm probably missing something, > but I think once resource allocation is done all of the registers that are > touched in the resource map have been rewritten. > > Thanks, > Myles > > > Hi, and thx for your replies so far. For what I understand now is that the resource map is needed for early initialization work and if I'm booting my boards without one it is just luck when they work?! Furthermore I understand that I can't use setpci to dump the vendor BIOS registers once booted into Linux. Then, unfortunately, my question still remains about how to set up a correct resource map for my board? Could anyone who has done one explain how he/she did it? In the meantime I tried a different resource map from a fam10 board and it seems to work, but just because sun were shinning ?? Thanks and again sorry for all the question marks, Knut Kujat. From knuku at gap.upv.es Thu May 6 10:19:42 2010 From: knuku at gap.upv.es (Knut Kujat) Date: Thu, 06 May 2010 10:19:42 +0200 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: <3E82FA80444D43E0B48A8585DB6D1815@chimp> References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz> <4BDE768B.3000801@gap.upv.es> <4BE120B7.4070401@gap.upv.es> <3E82FA80444D43E0B48A8585DB6D1815@chimp> Message-ID: <4BE27B9E.9010406@gap.upv.es> Myles Watson escribi?: > > >>> I think this can be problematic, since by the time you can dump the >>> >> factory >> >>> BIOS resource allocation has already occurred. The resource map is only >>> good for early initialization, before resource allocation, right? >>> >> hmm. I had always used the bios map as a starting point and it had >> worked well for me. >> > > I think most of the time it should work fine, but we have some hard-coded > addresses where the chipset is expected to live in early setup routines, and > they might break. > > My resource map sets: > DRAM mappings for each node > MMIO mappings for each HT chain > PCI IO mappings for each HT chain > PCI Bus numbers for each HT chain > > I think they should only be needed for things like ck804_early_setup_car.c, > where I/O is being used and set up. If the mappings aren't configured the > reads and writes don't reach the chipset. > > >> But maybe things are much harder now. It is true that you need to do a bit >> of >> interpretation of the map once the factory BIOS has set it up. >> >> Does resource allocation get all the bits, even legacy ones? Are there >> not some resource map values that >> a resource allocator can not figure out? >> > > I don't know. Once resource allocation is done you should know where your > VGA card is, and where your Southbridge is. I'm probably missing something, > but I think once resource allocation is done all of the registers that are > touched in the resource map have been rewritten. > > Thanks, > Myles > > > Sorry I forgot to add the showroutes output: For the good working CPU and the resource map adopted from H8DMR it this: After finalize_node_setup DRAM(40)0000000000-0000ffffff, ->(0), R, W, No interleave, 0 MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(98)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(b8)0000000000-033e26ffff, ->(5,1), , , CPU disable 0, Lock 0, Non posted 1 PCIIO(c0)0000000-1ffffff, ->(0,2), , ,VGA 0 ISA 0 PCIIO(c8)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0 PCIIO(d0)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0 CONFIG(e0)00-05 ->(0,2),R W (bus numbers) AFTER setup_mb_resource DRAM(40)0000000000-0000ffffff, ->(0), R, W, No interleave, 0 MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(98)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(b8)0000000000-033e26ffff, ->(5,1), , , CPU disable 0, Lock 0, Non posted 1 PCIIO(c0)0000000-1ffffff, ->(0,2), R, W,VGA 1 ISA 1 PCIIO(c8)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0 PCIIO(d0)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0 CONFIG(e0)00-3f ->(0,2),R W (bus numbers) And for the Not so good working CPU: After finalize_node_setup DRAM(40)0000000000-0000ffffff, ->(0), R, W, No interleave, 0 DRAM(48)0000000000-f800ffffff, ->(2), , , No interleave, 0 DRAM(50)0000000000-26acffffff, ->(0), , , No interleave, 0 DRAM(58)0000000000-a725ffffff, ->(4), , , No interleave, 0 DRAM(60)0000000000-c520ffffff, ->(0), , , No interleave, 1 DRAM(68)0000000000-7861ffffff, ->(3), , , No interleave, 3 DRAM(70)0000000000-0c84ffffff, ->(1), , , No interleave, 2 DRAM(78)0000000000-4992ffffff, ->(3), , , No interleave, 1 MMIO(80)0000000000-0bf611ffff, ->(6,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(88)0000000000-05d30cffff, ->(7,1), , , CPU disable 0, Lock 0, Non posted 1 MMIO(90)0000000000-1100b9ffff, ->(5,2), , , CPU disable 0, Lock 0, Non posted 1 MMIO(98)0000000000-a0d18effff, ->(1,1), , , CPU disable 0, Lock 0, Non posted 0 MMIO(a0)0000000000-584dd4ffff, ->(2,0), , , CPU disable 0, Lock 0, Non posted 1 MMIO(a8)0000000000-3a9903ffff, ->(3,3), , , CPU disable 0, Lock 0, Non posted 1 MMIO(b0)0000000000-1f36f0ffff, ->(5,1), , , CPU disable 0, Lock 0, Non posted 0 MMIO(b8)0000000000-9686b0ffff, ->(1,0), , , CPU disable 0, Lock 0, Non posted 1 PCIIO(c0)0000000-0e20fff, ->(6,0), , ,VGA 0 ISA 0 PCIIO(c8)0000000-1e65fff, ->(2,2), , ,VGA 0 ISA 0 PCIIO(d0)0000000-0782fff, ->(4,3), , ,VGA 0 ISA 0 PCIIO(d8)0000000-0819fff, ->(1,1), , ,VGA 0 ISA 0 CONFIG(e0)00-05 ->(0,2),R W (bus numbers) AFTER setup_mb_resource DRAM(40)0000000000-0000ffffff, ->(0), R, W, No interleave, 0 MMIO(80)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(98)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(a0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(b0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(b8)0000000000-9686b0ffff, ->(1,0), , , CPU disable 0, Lock 0, Non posted 1 PCIIO(c0)0000000-1ffffff, ->(0,2), R, W,VGA 1 ISA 1 CONFIG(e0)00-3f ->(0,2),R W (bus numbers) Notice that I haven't switched CPU but used 2 different boards for this capture. thanks and bye, Knut Kujat. From joop_boonen at web.de Thu May 6 11:35:44 2010 From: joop_boonen at web.de (Joop Boonen) Date: Thu, 6 May 2010 11:35:44 +0200 Subject: [coreboot] FILO bug disk not seen at ata-0 Message-ID: <9fcf30ec4fe94654bd26b1ac9822bf75.squirrel@www.boonen.name> All, I have an issue with FILO the disk at ata-0 isn't seen. When is use SEABIOS it's detected properly. I've attached session log with all debugging for FILO enabled. Regards, Joop. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: session_debug_filo_20100505.txt URL: From joop_boonen at web.de Thu May 6 11:56:43 2010 From: joop_boonen at web.de (Joop Boonen) Date: Thu, 6 May 2010 11:56:43 +0200 Subject: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114) In-Reply-To: <9fcf30ec4fe94654bd26b1ac9822bf75.squirrel@www.boonen.name> References: <9fcf30ec4fe94654bd26b1ac9822bf75.squirrel@www.boonen.name> Message-ID: <074aeb78763ef5fb4e896f43a334b2f4.squirrel@www.boonen.name> On Thu, May 6, 2010 11:35 am, Joop Boonen wrote: > All, > > I have an issue with FILO the disk at ata-0 isn't seen. I saw that it only tries to find disk connected at the SIL3114 controller (1095:3114 pci_1095_3114 SiI 3114 [SATALink/SATARaid] Serial ATA Controller) not the pata in the chipset (pci_1022_7469 AMD-8111 IDE). I've attached the session log also to this ticket including the hwinfo as presented by openSuSE. > > When is use SEABIOS it's detected properly. > > I've attached session log with all debugging for FILO enabled. > > Regards, > > Joop.-- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: session_debug_filo_20100505.txt URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: hwinfo_20100503.txt URL: From mylesgw at gmail.com Thu May 6 12:56:20 2010 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 6 May 2010 04:56:20 -0600 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: <4BE26CED.2090501@gap.upv.es> References: <4BD81C75.6010408@gap.upv.es><4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es><4BDE03DF.8080507@assembler.cz> <4BDE768B.3000801@gap.upv.es><4BE120B7.4070401@gap.upv.es> <3E82FA80444D43E0B48A8585DB6D1815@chimp> <4BE26CED.2090501@gap.upv.es> Message-ID: <2DE9556A93D5485BB829A25150196250@chimp> > > My resource map sets: > > DRAM mappings for each node > > MMIO mappings for each HT chain > > PCI IO mappings for each HT chain > > PCI Bus numbers for each HT chain Since all of your devices are on the same HT chain in your devicetree.cb, a resourcemap should be pretty easy to do. DRAM - All 0, but make sure to include the correct node numbers. MMIO - All (0xc0000000-0xffffffff) down link 2 of node 0. PCI-IO - All (0x0000-0xffff) on link 2 of node 0 PCI Bus numbers - All on link 2 of node 0 > Hi, > and thx for your replies so far. For what I understand now is that the > resource map is needed for early initialization work and if I'm booting > my boards without one it is just luck when they work?! > Furthermore I understand that I can't use setpci to dump the vendor BIOS > registers once booted into Linux. In your case you can get most of it from Linux, just enable the whole ranges, and don't touch the DRAM registers unless you know how they interact with CAR. > Then, unfortunately, my question still > remains about how to set up a correct resource map for my board? > Could anyone who has done one explain how he/she did it? I think the process should be: 1. Look at the register values from Linux 2. Set up the registers so that there is some MMIO, PCI I/O, bus resources for each link you want to touch before device enumeration (anything named early, especially). For ck804_early... It assumes that you allocate PCI I/O resources to each link in 16K blocks. Again, since you only have one non-coherent HT link, allocating the whole range there should work fine. > In the meantime I tried a different resource map from a fam10 board and > it seems to work, but just because sun were shinning ?? Have you done showallroutes() before and after setting up your resource map? It will make it obvious why you need it on cold boot, and it could help you figure out what's missing. Try it on a working board and one that doesn't. I'd like to see the differences. It would also help to know what address range is failing on inb and outb. That would tell you which register you need to play with. Thanks, Myles From mylesgw at gmail.com Thu May 6 13:14:38 2010 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 6 May 2010 05:14:38 -0600 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: <4BE27B9E.9010406@gap.upv.es> References: <4BD81C75.6010408@gap.upv.es> <4BDA9507.40306@gap.upv.es> <20100430154443.GA15966@countzero.vandewege.net> <4BDB04B2.6020707@gap.upv.es> <4BDE03DF.8080507@assembler.cz> <4BDE768B.3000801@gap.upv.es> <4BE120B7.4070401@gap.upv.es> <3E82FA80444D43E0B48A8585DB6D1815@chimp> <4BE27B9E.9010406@gap.upv.es> Message-ID: <276B064EA5A24477A8C4BF4D6A0B5DAB@chimp> > -----Original Message----- > From: Knut Kujat [mailto:knuku at gap.upv.es] > Sent: Thursday, May 06, 2010 2:20 AM > To: Myles Watson > Cc: 'ron minnich'; 'coreboot' > Subject: Re: [coreboot] H8QME-2+ boot problems on different machines. > > Myles Watson escribi?: > > > > > >>> I think this can be problematic, since by the time you can dump the > >>> > >> factory > >> > >>> BIOS resource allocation has already occurred. The resource map is > only > >>> good for early initialization, before resource allocation, right? > >>> > >> hmm. I had always used the bios map as a starting point and it had > >> worked well for me. > >> > > > > I think most of the time it should work fine, but we have some hard- > coded > > addresses where the chipset is expected to live in early setup routines, > and > > they might break. > > > > My resource map sets: > > DRAM mappings for each node > > MMIO mappings for each HT chain > > PCI IO mappings for each HT chain > > PCI Bus numbers for each HT chain > > > > I think they should only be needed for things like > ck804_early_setup_car.c, > > where I/O is being used and set up. If the mappings aren't configured > the > > reads and writes don't reach the chipset. > > > > > >> But maybe things are much harder now. It is true that you need to do a > bit > >> of > >> interpretation of the map once the factory BIOS has set it up. > >> > >> Does resource allocation get all the bits, even legacy ones? Are there > >> not some resource map values that > >> a resource allocator can not figure out? > >> > > > > I don't know. Once resource allocation is done you should know where > your > > VGA card is, and where your Southbridge is. I'm probably missing > something, > > but I think once resource allocation is done all of the registers that > are > > touched in the resource map have been rewritten. > > > > Thanks, > > Myles > > > > > > > Sorry I forgot to add the showroutes output: Thanks for sending it. > For the good working CPU and the resource map adopted from H8DMR it this: > AFTER setup_mb_resource > DRAM(40)0000000000-0000ffffff, ->(0), R, W, No interleave, 0 > MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 > MMIO(98)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 > MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 > MMIO(b8)0000000000-033e26ffff, ->(5,1), , , CPU disable 0, Lock 0, Non > posted 1 > PCIIO(c0)0000000-1ffffff, ->(0,2), R, W,VGA 1 ISA 1 > PCIIO(c8)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0 > PCIIO(d0)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0 > CONFIG(e0)00-3f ->(0,2),R W (bus numbers) > > And for the Not so good working CPU: > AFTER setup_mb_resource > DRAM(40)0000000000-0000ffffff, ->(0), R, W, No interleave, 0 > MMIO(80)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 > MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 > MMIO(98)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 > MMIO(a0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 > MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 > MMIO(b0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 I wonder why all those registers show up. They shouldn't print if they're zeroed. Maybe you could print the raw register values, too. The docs are available, and most of the meanings are copied into resourcemap.c. > MMIO(b8)0000000000-9686b0ffff, ->(1,0), , , CPU disable 0, Lock 0, Non > posted 1 > PCIIO(c0)0000000-1ffffff, ->(0,2), R, W,VGA 1 ISA 1 > CONFIG(e0)00-3f ->(0,2),R W (bus numbers) > > Notice that I haven't switched CPU but used 2 different boards for this > capture. Were these both for a cold boot? The first one looks like a lot fewer registers changed. You could compare what happens with the other resource map that works for you. Good luck, Myles From joe.korty at ccur.com Thu May 6 16:32:00 2010 From: joe.korty at ccur.com (Joe Korty) Date: Thu, 6 May 2010 10:32:00 -0400 Subject: [coreboot] H8DME-2 woes, hints? In-Reply-To: References: <20100505200608.GA15441@tsunami.ccur.com> Message-ID: <20100506143200.GA24873@tsunami.ccur.com> On Wed, May 05, 2010 at 04:26:15PM -0400, Myles Watson wrote: > On Wed, May 5, 2010 at 2:06 PM, Joe Korty wrote: >> Naturally I am having troubles. I suspect that as a newbie I am probably >> doing something stupid. But then I've heard that mb manufacturers like >> to change things around without notice, so maybe I'm doing things right >> and what was once a supported mb, no longer is. > It looks like you're doing things right. It's dying really early, though. >> When booting coreboot, nothing happens for about 45 seconds. >> Then the fans speed up to high and some messages start appearing >> on the serial line. These messages print rather slowly (maybe >> 1 second/message). They are: >> >> coreboot-4.0-r5521M Wed May 5 10:53:42 EDT 2010 starting... >> *sysinfo range: [000cf000,000cf730] >> bsp_apicid=00 >> Enabling routing table for node 00 done. >> Enabling SMP settings >> (0,1) link=00 > You could try an earlier revision. I can't think of what would slow > it down that much. >> I put some printk's in setup_smb2, the crashing routine. They show >> that setup_temp_row is called by setup_smb2 but never returns. > Since it takes so long to get there, I think you'll have better luck > trying to figure out what's wrong before that. >> fgrep 'Video ROM' /proc/iomem >> # displays "000c0000-000cafff : Video ROM" >> sudo dd if=/dev/mem of=/tmp/vgabios.bin bs=4k skip=$((0xc0)) count=$((0xb)) >> >> # --- figure out the Video ROM's PCI Vendor,Device ID >> # --- I _think_ the numbers I want are the second set shown, ie "15d9:1611". > > You want the first set. The second set is Supermicro's board ID. Hi Myles, Thanks for the pointers. I'm going to try some earlier releases of coreboot and if I can find one that lacks the slowdown. If that fails I am going to have to figure out how to debug the earliest stages of coreboot, when nothing is visible and little can be saved. Joe From coop.rocks.123e at gmail.com Thu May 6 14:04:32 2010 From: coop.rocks.123e at gmail.com (Cooper Harrison) Date: Thu, 6 May 2010 08:04:32 -0400 Subject: [coreboot] Dell Optiplex GX1 support Message-ID: By looking at all the supported hardware, it looks like it should work at a minimum amount. It has an Intel 440BX, an Intel PIIX4e and a NSC (formerly National) PC87309. Will I be able to boot Debian and if not, how soon until whoever is working on it estimates they will have it at a working status? I am just wondering as I think it would be cool to have it on my computer. -- Cooper -------------- next part -------------- An HTML attachment was scrubbed... URL: From anders at jenbo.dk Thu May 6 17:24:50 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Thu, 06 May 2010 17:24:50 +0200 Subject: [coreboot] =?utf-8?q?Indtast_Bcc__Dell_Optiplex_GX1_support?= Message-ID: Hi As you are the only one who has this board you will have to do a bit of the work your self. But I would be glad to help you, I recently ported coreboot to a 440bx board, Ubuntu boots on it so Debians should work fine. There is still a few limitations in the support for this chip. No L2 cache no ecc memory, only sdram and no ACPI. Also it looks like you won't have support for any legacy I/O (ps2 keyboard pc speaker) You could of ofcourse fix all this by reading the docs an coding a bit of C :) -Anders ----- Reply message ----- Fra: "Cooper Harrison" Dato: tor., maj 6, 2010 14:04 Emne: [coreboot] Dell Optiplex GX1 support Til: -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Thu May 6 21:32:12 2010 From: svn at coreboot.org (repository service) Date: Thu, 06 May 2010 21:32:12 +0200 Subject: [coreboot] [commit] r5527 - trunk/src/mainboard/tyan/s2912_fam10 Message-ID: Author: oxygene Date: Thu May 6 21:32:12 2010 New Revision: 5527 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5527 Log: Remove duplicate Kconfig entry. Trivial. Signed-off-by: Patrick Georgi Acked-by: Patrick Georgi Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Wed May 5 15:13:47 2010 (r5526) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Thu May 6 21:32:12 2010 (r5527) @@ -112,11 +112,6 @@ default "mc_patch_01000095.h" depends on BOARD_TYAN_S2912_FAM10 -config SERIAL_CPU_INIT - bool - default n - depends on BOARD_TYAN_S2912_FAM10 - config RAMBASE hex default 0x200000 From mylesgw at gmail.com Thu May 6 21:15:28 2010 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 6 May 2010 13:15:28 -0600 Subject: [coreboot] H8QME-2+ boot problems on different machines. In-Reply-To: <276B064EA5A24477A8C4BF4D6A0B5DAB@chimp> References: <4BD81C75.6010408@gap.upv.es> <4BDE768B.3000801@gap.upv.es> <4BE120B7.4070401@gap.upv.es> <3E82FA80444D43E0B48A8585DB6D1815@chimp> <4BE27B9E.9010406@gap.upv.es> <276B064EA5A24477A8C4BF4D6A0B5DAB@chimp> Message-ID: >> And for the Not so good working CPU: >> AFTER ?setup_mb_resource >> DRAM(40)0000000000-0000ffffff, ->(0), R, W, No interleave, 0 >> MMIO(80)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non >> posted 0 >> MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non >> posted 0 >> MMIO(98)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non >> posted 0 >> MMIO(a0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non >> posted 0 >> MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non >> posted 0 >> MMIO(b0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non >> posted 0 > I wonder why all those registers show up. ?They shouldn't print if they're > zeroed. ?Maybe you could print the raw register values, too. ?The docs are > available, and most of the meanings are copied into resourcemap.c. It looks like your resourcemap.c is for k8, not fam10. There's an extra bit in fam10 that controls ganged links. Since it's listed as reserved in your resource map, it should never get cleared, which could cause you problems, but only sporadically (depending on how that bit floats). That's probably the reason all the 0 registers show up. Thanks, Myles From buurin at gmail.com Fri May 7 05:31:49 2010 From: buurin at gmail.com (Keith Hui) Date: Thu, 6 May 2010 23:31:49 -0400 Subject: [coreboot] PATCH: model_6bx CPUs can go in a lot of places Message-ID: Hi all, Intel model 6bx CPUs (specifically 6B1 and 6B4) can end up in a lot of places, specifically Slot 1 and Socket 370. Ever since references to them were removed from cpu/intel/model_6xx my coreboot would die when initializing CPU with a "Unknown cpu" error. This patch fixes it by adding references to model_6bx to cpu/intel/slot_1 and cpu/intel/socket_PGA370. Also included are before and after boot logs with relevant sections highlighted. Before boot log: http://coreboot.pastebin.com/CGWgihaG After boot log: http://coreboot.pastebin.com/GLgnpZT6 Signed-off-by: Keith Hui ----- Begin patch ----- Index: src/cpu/intel/slot_1/Makefile.inc =================================================================== --- src/cpu/intel/slot_1/Makefile.inc (revision 5527) +++ src/cpu/intel/slot_1/Makefile.inc (working copy) @@ -20,6 +20,7 @@ obj-y += slot_1.o subdirs-y += ../model_6xx +subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic Index: src/cpu/intel/socket_PGA370/Makefile.inc =================================================================== --- src/cpu/intel/socket_PGA370/Makefile.inc (revision 5527) +++ src/cpu/intel/socket_PGA370/Makefile.inc (working copy) @@ -20,6 +20,7 @@ obj-y += socket_PGA370.o subdirs-y += ../model_6xx +subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic ----- End patch ----- From arne.gleditsch at numascale.com Fri May 7 12:30:54 2010 From: arne.gleditsch at numascale.com (Arne Georg Gleditsch) Date: Fri, 07 May 2010 12:30:54 +0200 Subject: [coreboot] H8DME-2 woes, hints? In-Reply-To: <20100505200608.GA15441@tsunami.ccur.com> (Joe Korty's message of "Wed, 5 May 2010 16:06:08 -0400") References: <20100505200608.GA15441@tsunami.ccur.com> Message-ID: <871vdongv5.fsf@taniquetil.gledits.ch> Joe Korty writes: > As a first time coreboot user, I thought that I should first try it out > on a supported board. That way I would learn the ropes a bit before even > thinking about doing something more challenging. > > Naturally I am having troubles. I suspect that as a newbie I am probably > doing something stupid. But then I've heard that mb manufacturers like > to change things around without notice, so maybe I'm doing things right > and what was once a supported mb, no longer is. > > The hardware: > SuperMicro H8DME-2. > Four 1Gbyte DDR2-667/533/400 Registered ECC SDRAM sticks from Crucial. > Two Quad-Core AMD 2378 2.4 GHz Processors. > Onboard video. > One SATA disk. > One PATA DVD-ROM reader. > NULL modem serial cable from COM1 to COM1 on another PC. > > The details: > When booting coreboot, nothing happens for about 45 seconds. > Then the fans speed up to high and some messages start appearing > on the serial line. These messages print rather slowly (maybe > 1 second/message). They are: > > coreboot-4.0-r5521M Wed May 5 10:53:42 EDT 2010 starting... > *sysinfo range: [000cf000,000cf730] > bsp_apicid=00 > Enabling routing table for node 00 done. > Enabling SMP settings > (0,1) link=00 This looks like the bootup code for gen f Opterons. It doesn't look like the h8dme has a fam10 variant yet, which is what you need for the 2378 CPUs. -- Arne. From joe.korty at ccur.com Fri May 7 14:51:09 2010 From: joe.korty at ccur.com (Joe Korty) Date: Fri, 7 May 2010 08:51:09 -0400 Subject: [coreboot] H8DME-2 woes, hints? In-Reply-To: <876330nieo.fsf@taniquetil.gledits.ch> References: <20100505200608.GA15441@tsunami.ccur.com> <876330nieo.fsf@taniquetil.gledits.ch> Message-ID: <20100507125109.GC17836@tsunami.ccur.com> On Fri, May 07, 2010 at 05:57:35AM -0400, Arne Georg Gleditsch wrote: > Joe Korty writes: > > As a first time coreboot user, I thought that I should first try it out > > on a supported board. That way I would learn the ropes a bit before even > > thinking about doing something more challenging. > > > > Naturally I am having troubles. I suspect that as a newbie I am probably > > doing something stupid. But then I've heard that mb manufacturers like > > to change things around without notice, so maybe I'm doing things right > > and what was once a supported mb, no longer is. > > > > The hardware: > > SuperMicro H8DME-2. > > Four 1Gbyte DDR2-667/533/400 Registered ECC SDRAM sticks from Crucial. > > Two Quad-Core AMD 2378 2.4 GHz Processors. > > Onboard video. > > One SATA disk. > > One PATA DVD-ROM reader. > > NULL modem serial cable from COM1 to COM1 on another PC. > > > > The details: > > When booting coreboot, nothing happens for about 45 seconds. > > Then the fans speed up to high and some messages start appearing > > on the serial line. These messages print rather slowly (maybe > > 1 second/message). They are: > > > > coreboot-4.0-r5521M Wed May 5 10:53:42 EDT 2010 starting... > > *sysinfo range: [000cf000,000cf730] > > bsp_apicid=00 > > Enabling routing table for node 00 done. > > Enabling SMP settings > > (0,1) link=00 > > This looks like the bootup code for gen f Opterons. It doesn't look > like the h8dme has a fam10 variant yet, which is what you need for the > 2378 CPUs. Thanks Arne! I'll have to figure out how to proceed from here. On a side note, it _looks_ like the slowdown might be due to the udelay unification. Still bisecting. Joe From mylesgw at gmail.com Fri May 7 15:30:08 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 7 May 2010 07:30:08 -0600 Subject: [coreboot] H8DME-2 woes, hints? In-Reply-To: <20100507125109.GC17836@tsunami.ccur.com> References: <20100505200608.GA15441@tsunami.ccur.com><876330nieo.fsf@taniquetil.gledits.ch> <20100507125109.GC17836@tsunami.ccur.com> Message-ID: <7779FEEFBA9D41BC9AB89D6B9C455CC9@chimp> > > > The hardware: > > > SuperMicro H8DME-2. > > > Four 1Gbyte DDR2-667/533/400 Registered ECC SDRAM sticks from > Crucial. > > > Two Quad-Core AMD 2378 2.4 GHz Processors. > > > Onboard video. > > > One SATA disk. > > > One PATA DVD-ROM reader. > > > NULL modem serial cable from COM1 to COM1 on another PC. > > > > > > The details: > > > When booting coreboot, nothing happens for about 45 seconds. > > > Then the fans speed up to high and some messages start appearing > > > on the serial line. These messages print rather slowly (maybe > > > 1 second/message). They are: > > > > > > coreboot-4.0-r5521M Wed May 5 10:53:42 EDT 2010 starting... > > > *sysinfo range: [000cf000,000cf730] > > > bsp_apicid=00 > > > Enabling routing table for node 00 done. > > > Enabling SMP settings > > > (0,1) link=00 > > > > This looks like the bootup code for gen f Opterons. It doesn't look > > like the h8dme has a fam10 variant yet, which is what you need for the > > 2378 CPUs. > > Thanks Arne! > I'll have to figure out how to proceed from here. > > On a side note, it _looks_ like the slowdown might be due to the udelay > unification. Still bisecting. I'm surprised you found a revision that works, since it has never supported fam10. I think it would be more fruitful for you to look at one of the boards that has both fam10 and k8 support, and try to put together an h8dme_fam10 port. Thanks, Myles From ward at gnu.org Fri May 7 15:37:54 2010 From: ward at gnu.org (Ward Vandewege) Date: Fri, 7 May 2010 09:37:54 -0400 Subject: [coreboot] H8DME-2 woes, hints? In-Reply-To: <7779FEEFBA9D41BC9AB89D6B9C455CC9@chimp> References: <20100507125109.GC17836@tsunami.ccur.com> <7779FEEFBA9D41BC9AB89D6B9C455CC9@chimp> Message-ID: <20100507133754.GA27742@countzero.vandewege.net> On Fri, May 07, 2010 at 07:30:08AM -0600, Myles Watson wrote: > > > This looks like the bootup code for gen f Opterons. It doesn't look > > > like the h8dme has a fam10 variant yet, which is what you need for the > > > 2378 CPUs. > > > > Thanks Arne! > > I'll have to figure out how to proceed from here. > > > > On a side note, it _looks_ like the slowdown might be due to the udelay > > unification. Still bisecting. > > I'm surprised you found a revision that works, since it has never supported > fam10. I think it would be more fruitful for you to look at one of the > boards that has both fam10 and k8 support, and try to put together an > h8dme_fam10 port. For the record, I've been trying to get that going for a while, but have not had much success - very early hangs in the fam10 code on this board. Cf. the problems Knut is having, I think... Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator From joe at settoplinux.org Fri May 7 15:39:02 2010 From: joe at settoplinux.org (Joseph Smith) Date: Fri, 07 May 2010 09:39:02 -0400 Subject: [coreboot] =?utf-8?q?PATCH=3A_model=5F6bx_CPUs_can_go_in_a_lot_of?= =?utf-8?q?_places?= In-Reply-To: References: Message-ID: <45617214e36fd8c64a14ac127ff710e8@imap.1and1.com> On Thu, 6 May 2010 23:31:49 -0400, Keith Hui wrote: > Hi all, > > Intel model 6bx CPUs (specifically 6B1 and 6B4) can end up in a lot of > places, specifically Slot 1 and Socket 370. Ever since references to > them were removed from cpu/intel/model_6xx my coreboot would die when > initializing CPU with a "Unknown cpu" error. This patch fixes it by > adding references to model_6bx to cpu/intel/slot_1 and > cpu/intel/socket_PGA370. Also included are before and after boot logs > with relevant sections highlighted. > > Before boot log: http://coreboot.pastebin.com/CGWgihaG > After boot log: http://coreboot.pastebin.com/GLgnpZT6 > > Signed-off-by: Keith Hui > > ----- Begin patch ----- > Index: src/cpu/intel/slot_1/Makefile.inc > =================================================================== > --- src/cpu/intel/slot_1/Makefile.inc (revision 5527) > +++ src/cpu/intel/slot_1/Makefile.inc (working copy) > @@ -20,6 +20,7 @@ > > obj-y += slot_1.o > subdirs-y += ../model_6xx > +subdirs-y += ../model_6bx > subdirs-y += ../../x86/tsc > subdirs-y += ../../x86/mtrr > subdirs-y += ../../x86/lapic > Index: src/cpu/intel/socket_PGA370/Makefile.inc > =================================================================== > --- src/cpu/intel/socket_PGA370/Makefile.inc (revision 5527) > +++ src/cpu/intel/socket_PGA370/Makefile.inc (working copy) > @@ -20,6 +20,7 @@ > > obj-y += socket_PGA370.o > subdirs-y += ../model_6xx > +subdirs-y += ../model_6bx > subdirs-y += ../../x86/tsc > subdirs-y += ../../x86/mtrr > subdirs-y += ../../x86/lapic > > ----- End patch ----- > Hello Keith, I kind of saw this coming. That is why I left the 6bx's in model_6xx. The new model_6bx is intended for CAR, so I don't know how well it will work with romcc. My advice is to either get CAR running on your board, or we put back the 6bx's in model_6xx for the interim. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From patrick at georgi-clan.de Fri May 7 16:17:38 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Fri, 07 May 2010 16:17:38 +0200 Subject: [coreboot] [PATCH]Support tinybootblock on broadcom/bcm5785 Message-ID: <4BE42102.9080209@georgi-clan.de> Hi, attached patch adds the rom-enable function on bcm5785 to a tinybootblock build, allowing for 4MB ROMs (instead of the default configuration which seems to be 1MB). Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20100507-1-bcm5785-tinybootblock.diff URL: From anton.kochkov at gmail.com Fri May 7 13:27:58 2010 From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=) Date: Fri, 7 May 2010 15:27:58 +0400 Subject: [coreboot] inteltool patch: Added support to ICH9 chipset family Message-ID: Added support to ICH9 chipset family Signed-off-by: Anton Kochkov --- -------------- next part -------------- A non-text attachment was scrubbed... Name: ich9.patch Type: text/x-diff Size: 14359 bytes Desc: not available URL: From johnkyr83 at hotmail.com Fri May 7 13:41:03 2010 From: johnkyr83 at hotmail.com (limp) Date: Fri, 7 May 2010 12:41:03 +0100 Subject: [coreboot] Linux booting hangs when booted by FILO In-Reply-To: <20100501172322.GA9900@morn.localdomain> References: <20100501172322.GA9900@morn.localdomain> Message-ID: Hi, Yes, SeaBIOS works (well, with some minor issues). After putting a VGA bios into coreboot, the following are also displayed after the "Jumping to entry point..." message, but the system still freezes: Jumping to entry point... out of memory while allocating output buffer -- System halted Does anyone have any idea regarding the cause of the "out of memory while allocating output buffer" error? Thank you in advance. -John -----Original Message----- From: Kevin O'Connor [mailto:kevin at koconnor.net] Sent: Saturday, May 01, 2010 6:23 PM To: limp Cc: coreboot at coreboot.org Subject: Re: [coreboot] Linux booting hangs when booted by FILO On Fri, Apr 30, 2010 at 03:34:43AM +0100, limp wrote: > I have loaded coreboot with FILO on a Kontron 986LCD-M board and when I am > trying to boot Linux from FILO, it freezes at the "Jumping to entry > point..." bit. Out of curiosity, does SeaBIOS work? -Kevin From mylesgw at gmail.com Fri May 7 17:08:39 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 7 May 2010 09:08:39 -0600 Subject: [coreboot] H8DME-2 woes, hints? In-Reply-To: <20100507133754.GA27742@countzero.vandewege.net> References: <20100507125109.GC17836@tsunami.ccur.com> <7779FEEFBA9D41BC9AB89D6B9C455CC9@chimp> <20100507133754.GA27742@countzero.vandewege.net> Message-ID: > On Fri, May 07, 2010 at 07:30:08AM -0600, Myles Watson wrote: > > > > This looks like the bootup code for gen f Opterons. It doesn't look > > > > like the h8dme has a fam10 variant yet, which is what you need for > the > > > > 2378 CPUs. > > > > > > Thanks Arne! > > > I'll have to figure out how to proceed from here. > > > > > > On a side note, it _looks_ like the slowdown might be due to the > udelay > > > unification. Still bisecting. > > > > I'm surprised you found a revision that works, since it has never > supported > > fam10. I think it would be more fruitful for you to look at one of the > > boards that has both fam10 and k8 support, and try to put together an > > h8dme_fam10 port. > > For the record, I've been trying to get that going for a while, but have > not > had much success - very early hangs in the fam10 code on this board. Cf. > the > problems Knut is having, I think... Sorry I forgot that. The Supermicro names all blend together for me. Have you tried adding the extra bits to the masks in resourcemap.c? Thanks, Myles From anton.kochkov at gmail.com Fri May 7 18:10:53 2010 From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=) Date: Fri, 7 May 2010 20:10:53 +0400 Subject: [coreboot] inteltool patch: Added support to ICH9 chipset family In-Reply-To: References: Message-ID: Added support to ICH9 chipset family Signed-off-by: Anton Kochkov --- -------------- next part -------------- A non-text attachment was scrubbed... Name: ich9.patch Type: text/x-diff Size: 11715 bytes Desc: not available URL: From svn at coreboot.org Fri May 7 18:11:20 2010 From: svn at coreboot.org (coreboot) Date: Fri, 07 May 2010 16:11:20 -0000 Subject: [coreboot] #161: Improve USB debug port configuration Message-ID: <043.ecfee9842e1558ff96781bc6015a2861@coreboot.org> #161: Improve USB debug port configuration ----------------------------+----------------------------------------------- Reporter: oxygene | Owner: stepan@? Type: enhancement | Status: new Priority: trivial | Milestone: Component: coreboot | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Right now, the right port number is configured in DBGP_DEFAULT without much documentation anywhere. It's even defined in boards that don't use the value at all. Maybe move it to Kconfig? Document it? Just clean up the copy&pasted useless values? -- Ticket URL: coreboot From svn at coreboot.org Fri May 7 18:24:02 2010 From: svn at coreboot.org (coreboot) Date: Fri, 07 May 2010 16:24:02 -0000 Subject: [coreboot] #161: Improve USB debug port configuration In-Reply-To: <043.ecfee9842e1558ff96781bc6015a2861@coreboot.org> References: <043.ecfee9842e1558ff96781bc6015a2861@coreboot.org> Message-ID: <052.636563995b4a653f2be3d40e5ccbf003@coreboot.org> #161: Improve USB debug port configuration ----------------------------+----------------------------------------------- Reporter: oxygene | Owner: stepan@? Type: enhancement | Status: new Priority: trivial | Milestone: Component: coreboot | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Comment(by stuge): Definately mainboard Kconfig! -- Ticket URL: coreboot From buurin at gmail.com Fri May 7 19:00:37 2010 From: buurin at gmail.com (Keith Hui) Date: Fri, 7 May 2010 13:00:37 -0400 Subject: [coreboot] PATCH: model_6bx CPUs can go in a lot of places In-Reply-To: <45617214e36fd8c64a14ac127ff710e8@imap.1and1.com> References: <45617214e36fd8c64a14ac127ff710e8@imap.1and1.com> Message-ID: I think I should get CAR running. But CAR is not quite developed for the rest of the 6xx family. If you look at the boot log you'll see that it got through to SeaBIOS just fine. My coreboot is still on romcc. What are the steps needed to enable CAR on a board? Thanks Keith On 5/7/10, Joseph Smith wrote: > > > > On Thu, 6 May 2010 23:31:49 -0400, Keith Hui wrote: >> Hi all, >> >> Intel model 6bx CPUs (specifically 6B1 and 6B4) can end up in a lot of >> places, specifically Slot 1 and Socket 370. Ever since references to >> them were removed from cpu/intel/model_6xx my coreboot would die when >> initializing CPU with a "Unknown cpu" error. This patch fixes it by >> adding references to model_6bx to cpu/intel/slot_1 and >> cpu/intel/socket_PGA370. Also included are before and after boot logs >> with relevant sections highlighted. >> >> Before boot log: http://coreboot.pastebin.com/CGWgihaG >> After boot log: http://coreboot.pastebin.com/GLgnpZT6 >> >> Signed-off-by: Keith Hui >> >> ----- Begin patch ----- >> Index: src/cpu/intel/slot_1/Makefile.inc >> =================================================================== >> --- src/cpu/intel/slot_1/Makefile.inc (revision 5527) >> +++ src/cpu/intel/slot_1/Makefile.inc (working copy) >> @@ -20,6 +20,7 @@ >> >> obj-y += slot_1.o >> subdirs-y += ../model_6xx >> +subdirs-y += ../model_6bx >> subdirs-y += ../../x86/tsc >> subdirs-y += ../../x86/mtrr >> subdirs-y += ../../x86/lapic >> Index: src/cpu/intel/socket_PGA370/Makefile.inc >> =================================================================== >> --- src/cpu/intel/socket_PGA370/Makefile.inc (revision 5527) >> +++ src/cpu/intel/socket_PGA370/Makefile.inc (working copy) >> @@ -20,6 +20,7 @@ >> >> obj-y += socket_PGA370.o >> subdirs-y += ../model_6xx >> +subdirs-y += ../model_6bx >> subdirs-y += ../../x86/tsc >> subdirs-y += ../../x86/mtrr >> subdirs-y += ../../x86/lapic >> >> ----- End patch ----- >> > Hello Keith, > I kind of saw this coming. That is why I left the 6bx's in model_6xx. The > new model_6bx is intended for CAR, so I don't know how well it will work > with romcc. My advice is to either get CAR running on your board, or we put > back the 6bx's in model_6xx for the interim. > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > > From joe at settoplinux.org Fri May 7 19:28:41 2010 From: joe at settoplinux.org (Joseph Smith) Date: Fri, 07 May 2010 13:28:41 -0400 Subject: [coreboot] =?utf-8?q?PATCH=3A_model=5F6bx_CPUs_can_go_in_a_lot_of?= =?utf-8?q?_places?= In-Reply-To: References: <45617214e36fd8c64a14ac127ff710e8@imap.1and1.com> Message-ID: <591873b1eecc97a2de5690c7139afe94@imap.1and1.com> On Fri, 7 May 2010 13:00:37 -0400, Keith Hui wrote: > I think I should get CAR running. But CAR is not quite developed for > the rest of the 6xx family. > Correct, and it will never get done if we don't step forward. > If you look at the boot log you'll see that it got through to SeaBIOS > just fine. My coreboot is still on romcc. > > What are the steps needed to enable CAR on a board? > Take a look at Thomson IP1000. Hope that helps. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From joe.korty at ccur.com Fri May 7 19:59:12 2010 From: joe.korty at ccur.com (Joe Korty) Date: Fri, 7 May 2010 13:59:12 -0400 Subject: [coreboot] Query, known-good CPUs to use in a H8DME-2 mb? In-Reply-To: <20100507133754.GA27742@countzero.vandewege.net> References: <20100507125109.GC17836@tsunami.ccur.com> <7779FEEFBA9D41BC9AB89D6B9C455CC9@chimp> <20100507133754.GA27742@countzero.vandewege.net> Message-ID: <20100507175912.GA13258@tsunami.ccur.com> On Fri, May 07, 2010 at 09:37:54AM -0400, Ward Vandewege wrote: > On Fri, May 07, 2010 at 07:30:08AM -0600, Myles Watson wrote: >> This looks like the bootup code for gen f Opterons. >> It doesn't look like the h8dme has a fam10 variant yet, >> which is what you need for the 2378 CPUs. >> >> I'm surprised you found a revision that works, since >> it has never supported fam10. I think it would be more >> fruitful for you to look at one of the boards that has >> both fam10 and k8 support, and try to put together an >> h8dme_fam10 port. > > For the record, I've been trying to get that going for a > while, but have not had much success - very early hangs > in the fam10 code on this board. Cf. the problems Knut > is having, I think... What AMD Processor model numbers have you folks been using on the SuperMicro H8DME-2 mainboards? I'd like to buy a pair of known-working CPUs. I currently have a pair of AMD model #2378 Processors, which are of the fam10 line, with a pair of model #2222 CPUs, which are of the K8 line. Thoughts? Regards, Joe From ward at gnu.org Fri May 7 20:02:19 2010 From: ward at gnu.org (Ward Vandewege) Date: Fri, 7 May 2010 14:02:19 -0400 Subject: [coreboot] Query, known-good CPUs to use in a H8DME-2 mb? In-Reply-To: <20100507175912.GA13258@tsunami.ccur.com> References: <20100507125109.GC17836@tsunami.ccur.com> <7779FEEFBA9D41BC9AB89D6B9C455CC9@chimp> <20100507133754.GA27742@countzero.vandewege.net> <20100507175912.GA13258@tsunami.ccur.com> Message-ID: <20100507180219.GA5195@countzero.vandewege.net> On Fri, May 07, 2010 at 01:59:12PM -0400, Joe Korty wrote: > What AMD Processor model numbers have you folks been using > on the SuperMicro H8DME-2 mainboards? I'd like to buy a > pair of known-working CPUs. > > I currently have a pair of AMD model #2378 Processors, > which are of the fam10 line, with a pair of model #2222 > CPUs, which are of the K8 line. The port for that board was done on a pair of 2216 HE CPUs. You may be hard pressed to find those for sale these days... Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator From r.marek at assembler.cz Fri May 7 20:10:53 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 07 May 2010 20:10:53 +0200 Subject: [coreboot] AMD CAR II Message-ID: <4BE457AD.5050007@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, I examined a bit how does it works. Maybe if one can read this http://en.wikipedia.org/wiki/CPU_cache and then continue here :) I was particularly curious because we do writeback - writeback copy of data from CAR to ram (to copy stack and sysinfo, which must cause L1 evictions), and also we do DQS memory training (which writes to RAM during CAR) and we use cache to cache ROM too. This means not only L1 is used but we must be using L2 too. Here are some notes why I think it works :) Here is what I found: AMD L2 cache is exclusive, it means it only contains data evicted from L1 caches. In other words there is never same data in both caches. I could not find any info if it is valid for the Icache too. If the icache gets moved to L2 or not. It should but it does not seem to happen during CAR. L1 Data cache: Size: 64Kb 2-way associative. lines per tag=1 line size=64 bytes. L1 Instruction cache: Size: 64Kb 2-way associative. lines per tag=1 line size=64 bytes. 512KB/core L2 cache: Size: 1024Kb 16-way associative. lines per tag=1 line size=64 bytes. Here is basic math how to calculate cache organization: line size => tells how many bytes are stored in one cache line (exploits the spatial locality of data). Here it is 64 bytes so bits of address 5:0 are used. Index: it tells how many cache lines do we have. The level of associativity tells how many addresses which compete for same index can be stored in cache simultaneously. For L1 we have: 64*1024 / 64 / 2 = 512 is the number of cache lines. We have 2 (assoc is 2) "arrays" each has 64 bytes/per line and total size is 64KB. The index is therefore on addresses 14:6. The rest of address is used as tag (tag identifies the actual location of data in memory together with the cache line index) One can say each 14:0 bit of address compete for same index. We have asoc level of 2 so each 16 bits of addr will fill whole cache. For L2 here it is 512KB assoc is 16. We have 32KB / 64 indexes = 512 (lines) so addresses 14:6 build up the index. Rest is tag. The CAR idea on AMD is just to use it and never cause an eviction from L2 cache to main memory (which is not functioning). Step 0) enable cache and WB mtrrs for any ranges 1) all lines are invalid, validate them by dummy read exactly as big as max L1 cache. For instruction cache enough is a instr fetch. 2) The dummy read region can be now used to store data - it is simply an arbitrary address range 0-64KB max. 3) caching of ROM works too because: a) MTRR for rom is set (currently only for part of it) it could be WP type but we use WB, no harm here because we do not modify any code ;) b) L1 instruction cache is filled from flash chip directly (remember L2 is exclusive cache on AMD) c) if L1 instr cache is not evicted into L2 then on cache miss it L1 line is simply invalidated and refilled from flash rom. I tried to check this using performance counters but there is not a counter for this. This is uninteresting case because it does not complicate anything. c) if L1 instr cache gets evicted into L2, (which I dont know if is true), then we can run into following I) no L1 data cache lines was evicted into L2 - again not interesting case because nothing gets wrong. II) we have some L1 data cache evicted into L2. This really happens in our CAR! print_debug("Copying data from cache to RAM -- switching to use RAM as stack..."); memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); It happens here because we do copy from CAR region to RAM while CAR is still running. Both regions are WB so we must evict some L1 cache lines for sure, and performance counters confirm this. You may say this is not an issue because RAM is running normally, but for example while we resume from S3 we cannot overwrite random memory with out CAR... I think this evictions so far happens only here and still things works nice here is why: We have at most 64KB or dirty data, we can spread it into L2 nicely and still have a lot of free space even on systems where we have 128KB L2. In this case no evictions into system because we can have the data still in L2. Now lets go back, what if CPU instruction cache gets evicted into L2? Here it would cause problems because in L2 would be L1 data cache data and random L1 instr cache code competing for the space. I think here it works because dirty data is evicted with lowest priority. I think if all lanes of cache are full, the lane with "clean" data is invalidated first. This saves the day for us because it guarantees that our L1 data will not fall off the cache never ever - only if we exceed the L2 cache size with dirty data. We examined so far the ROM caching and oversized L1 handling. But the memory training uses writes to not yet initialized RAM. How it works here? I checked and the memory write uses the instruction which bypasses caches. The read uses cache, but it invalidates the cache line afterwards. Again because we have at most L1size of dirty data and L2 is big enough it does not spoil the party and no stuff gets evicted back to non functioning memory. Last thing which worries me are speculated fills which can be do by CPU. I think they are disabled because the bit for proble FILLs is 0. The fam11 which has better documented L2 for general storage needs to have some other bits toggled not to do some extra speculations. Fam 10h describes only L1 car and older fams also the L1 only CAR. In our code we practically use L2 in all cases. What we could do is to program a performance counter for L2 writebacks to system at the beginning of CAR and in CAR disable check if it is still zero. This will tell if we did something nasty. We could also avoid the WB-WB copy of the CAR area. I tried with WB-UC copy and we have then 0 evictions from L1 which is fine (i did some experiments in January see AMD CAR questions email). Uhh its long email took like hour to write, please tell if you think that it works really this way. Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvkV60ACgkQ3J9wPJqZRNXaYgCglBFGuv2PtaR7yI/xxpVgvFBu vjwAn1ZPp1AArEih9CyO1T44tz/o97LR =ce4w -----END PGP SIGNATURE----- From mylesgw at gmail.com Fri May 7 22:04:58 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 7 May 2010 14:04:58 -0600 Subject: [coreboot] AMD CAR II In-Reply-To: <4BE457AD.5050007@assembler.cz> References: <4BE457AD.5050007@assembler.cz> Message-ID: > II) we have some L1 data cache evicted into L2. This really happens in our CAR! > print_debug("Copying data from cache to RAM -- switching to use RAM as stack..."); > memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void > *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); > > It happens here because we do copy from CAR region to RAM while CAR is still > running. Both regions are WB so we must evict some L1 cache lines for sure, and > performance counters confirm this. You may say this is not an issue because RAM > is running normally, but for example while we resume from S3 we cannot overwrite > random memory with out CAR... I think this evictions so far happens only here > and still things works nice here is why: Are you sure they're both WB? Since CAR is running, we don't disable the cache and enable it again, which is recommended when setting an MTRR. I commented out the line that sets that MTRR and can't tell a difference. I like the rest of analysis. Thanks, Myles From marcj303 at gmail.com Fri May 7 21:54:20 2010 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 7 May 2010 13:54:20 -0600 Subject: [coreboot] AMD CAR II In-Reply-To: <4BE457AD.5050007@assembler.cz> References: <4BE457AD.5050007@assembler.cz> Message-ID: Hi Rudolf, Good detailed email. Yes, this is how I think it works, and as far as I know, the L1 instruction cache also writes to the L2. The L2 is the main reason that CAR works. I have never been happy with the post_car code. Something about it doesn't seem right, but I have never found it. I do think that more care needs to happen with cache en/disable and the MTRR settings. Marc On Fri, May 7, 2010 at 12:10 PM, Rudolf Marek wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi all, > > I examined a bit how does it works. Maybe if one can read this > http://en.wikipedia.org/wiki/CPU_cache and then continue here :) > > > I was particularly curious because we do writeback - writeback copy of data from > CAR to ram (to copy stack and sysinfo, which must cause L1 evictions), and also > we do DQS memory training (which writes to RAM during CAR) and we use cache to > cache ROM too. > > This means not only L1 is used but we must be using L2 too. Here are some notes > why I think it works :) > > Here is what I found: > > AMD L2 cache is exclusive, it means it only contains data evicted from L1 > caches. In other words there is never same data in both caches. I could not find > any info if it is valid for the Icache too. If the icache gets moved to L2 or > not. It should but it does not seem to happen during CAR. > > L1 Data cache: > ? ? ? ?Size: 64Kb ? ? ?2-way associative. > ? ? ? ?lines per tag=1 line size=64 bytes. > L1 Instruction cache: > ? ? ? ?Size: 64Kb ? ? ?2-way associative. > ? ? ? ?lines per tag=1 line size=64 bytes. > > 512KB/core > > L2 cache: > ? ? ? ?Size: 1024Kb ? ?16-way associative. > ? ? ? ?lines per tag=1 line size=64 bytes. > > Here is basic math how to calculate cache organization: > > line size => tells how many bytes are stored in one cache line (exploits the > spatial locality of data). Here it is 64 bytes so bits of address 5:0 are used. > > Index: it tells how many cache lines do we have. > > The level of associativity tells how many addresses which compete for same index > can be stored in cache simultaneously. > > For L1 we have: 64*1024 / 64 / 2 = 512 is the number of cache lines. We have 2 > (assoc is 2) "arrays" each has 64 bytes/per line and total size is 64KB. The > index is therefore on addresses 14:6. The rest of address is used as tag (tag > identifies the actual location of data in memory together with the cache line > index) One can say each 14:0 bit of address compete for same index. We have asoc > level of 2 so each 16 bits of addr will fill whole cache. > > For L2 here it is 512KB assoc is 16. We have 32KB / 64 indexes = 512 (lines) > so addresses 14:6 build up the index. Rest is tag. > > The CAR idea on AMD is just to use it and never cause an eviction from L2 cache > to main memory (which is not functioning). > > Step 0) enable cache and WB mtrrs for any ranges > 1) all lines are invalid, validate them by dummy read exactly as big as max L1 > cache. For instruction cache enough is a instr fetch. > 2) The dummy read region can be now used to store data - it is simply an > arbitrary address range 0-64KB max. > > 3) caching of ROM works too because: > > a) MTRR for rom is set (currently only for part of it) it could be WP type but > we use WB, no harm here because we do not modify any code ;) > b) L1 instruction cache is filled from flash chip directly (remember L2 is > exclusive cache on AMD) > c) if L1 instr cache is not evicted into L2 then on cache miss it L1 line is > simply invalidated and refilled from flash rom. I tried to check this using > performance counters but there is not a counter for this. This is uninteresting > case because it does not complicate anything. > > c) if L1 instr cache gets evicted into L2, (which I dont know if is true), > > then we can run into following > > I) no L1 data cache lines was evicted into L2 - again not interesting case > because nothing gets wrong. > > II) we have some L1 data cache evicted into L2. This really happens in our CAR! > print_debug("Copying data from cache to RAM -- switching to use RAM as stack..."); > memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void > *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); > > It happens here because we do copy from CAR region to RAM while CAR is still > running. Both regions are WB so we must evict some L1 cache lines for sure, and > performance counters confirm this. You may say this is not an issue because RAM > is running normally, but for example while we resume from S3 we cannot overwrite > random memory with out CAR... I think this evictions so far happens only here > and still things works nice here is why: > > We have at most 64KB or dirty data, we can spread it into L2 nicely and still > have a lot of free space even on systems where we have 128KB L2. In this case no > evictions into system ?because we can have the data still in L2. > > Now lets go back, what if CPU instruction cache gets evicted into L2? Here it > would cause problems because in L2 would be L1 data cache data and random L1 > instr cache code competing for the space. > > I think here it works because dirty data is evicted with lowest priority. I > think if all lanes of cache are full, the lane with "clean" data is invalidated > ?first. This saves the day for us because it guarantees that our L1 data will > not fall off the cache never ever - only if we exceed the L2 cache size with > dirty data. > > We examined so far the ROM caching and oversized L1 handling. But the memory > training uses writes to not yet initialized RAM. How it works here? > > I checked and the memory write uses the instruction which bypasses caches. The > read uses cache, but it invalidates the cache line afterwards. Again because we > have at most L1size of dirty data and L2 is big enough it does not spoil the > party and no stuff gets evicted back to non functioning memory. > > Last thing which worries me are speculated fills which can be do by CPU. I think > they are disabled because the bit for proble FILLs is 0. The fam11 which has > better documented L2 for general storage needs to have some other bits toggled > not to do some extra speculations. Fam 10h describes only L1 car and older fams > also the L1 only CAR. In our code we practically use L2 in all cases. > > What we could do is to program a performance counter for L2 writebacks to system > at the beginning of CAR and in CAR disable check if it is still zero. This will > tell if we did something nasty. > > We could also avoid the WB-WB copy of the CAR area. I tried with WB-UC copy and > we have then 0 evictions from L1 which is fine (i did some experiments in > January see AMD CAR questions email). > > Uhh its long email took like hour to write, please tell if you think that it > works really this way. > > Thanks, > Rudolf > > > > > > > > > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.10 (GNU/Linux) > Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org > > iEYEARECAAYFAkvkV60ACgkQ3J9wPJqZRNXaYgCglBFGuv2PtaR7yI/xxpVgvFBu > vjwAn1ZPp1AArEih9CyO1T44tz/o97LR > =ce4w > -----END PGP SIGNATURE----- > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- http://se-eng.com From joop_boonen at web.de Fri May 7 22:37:43 2010 From: joop_boonen at web.de (Joop Boonen) Date: Fri, 7 May 2010 22:37:43 +0200 Subject: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114) In-Reply-To: <074aeb78763ef5fb4e896f43a334b2f4.squirrel@www.boonen.name> References: <9fcf30ec4fe94654bd26b1ac9822bf75.squirrel@www.boonen.name> <074aeb78763ef5fb4e896f43a334b2f4.squirrel@www.boonen.name> Message-ID: <665f02730557c26a7d0472538ec8d828.squirrel@www.boonen.name> On Thu, May 6, 2010 11:56 am, Joop Boonen wrote: > On Thu, May 6, 2010 11:35 am, Joop Boonen wrote: >> All, >> >> I have an issue with FILO the disk at ata-0 isn't seen. > I've been trying some more. I've used the old IDE in FILO. It now recognises the drive connected to the SIL3114. But still not the ATA drive. > I saw that it only tries to find disk connected at the SIL3114 controller > (1095:3114 pci_1095_3114 SiI 3114 [SATALink/SATARaid] Serial ATA > Controller) not the pata in the chipset (pci_1022_7469 AMD-8111 IDE). > I've attached the session log also to this ticket including the hwinfo as > presented by openSuSE. > >> >> When is use SEABIOS it's detected properly. >> >> I've attached session log with all debugging for FILO enabled. >> >> Regards, >> >> Joop.-- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From peter at stuge.se Fri May 7 23:11:47 2010 From: peter at stuge.se (Peter Stuge) Date: Fri, 7 May 2010 23:11:47 +0200 Subject: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114) In-Reply-To: <665f02730557c26a7d0472538ec8d828.squirrel@www.boonen.name> References: <9fcf30ec4fe94654bd26b1ac9822bf75.squirrel@www.boonen.name> <074aeb78763ef5fb4e896f43a334b2f4.squirrel@www.boonen.name> <665f02730557c26a7d0472538ec8d828.squirrel@www.boonen.name> Message-ID: <20100507211147.29282.qmail@stuge.se> Joop Boonen wrote: > >> I have an issue with FILO the disk at ata-0 isn't seen. > > I've been trying some more. I've used the old IDE in FILO. It now > recognises the drive connected to the SIL3114. But still not the > ATA drive. Curious. Maybe I can ask you to try even older code? I did a bunch of work on the IDE driver in FILO 0.5 but haven't kept up with current code. If you'd like to try the latest 0.5: svn co svn://coreboot.org/filo/branches/filo-0.5 Please disable the GRUB junk (comment out USE_GRUB), enable filesystems you need, and enable DEBUG_BLOCKDEV, DEBUG_PCI, and DEBUG_IDE. Thanks. //Peter From patrick at georgi-clan.de Sat May 8 00:13:19 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 08 May 2010 00:13:19 +0200 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 1/many Message-ID: <4BE4907F.5030202@georgi-clan.de> Hi, attached patch drops console/console.c and pc80/serial.c from the mainboards' romstage.c. console/console.h is included instead. On CAR builds, console/console.c is built separately and linked to the romstage, on romcc builds, this includes console/console.c from within console/console.h. The romcc variant helps with uniformity. In the same way, pc80/serial.c is eliminated from romstage.c. The necessary prototypes were already included via some other paths. Both files needs to include arch/io.h for separate compilation, so it finds outb, so it's moved outside the #ifndef __PRE_RAM__ in console.c and added in serial.c The patch also removes two superfluous ARRAY_SIZE definitions (in amd/db800 and winent/pl6064) It's abuild tested and Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20100507-2-reduce-c-in-c-includes.diff URL: From buurin at gmail.com Sat May 8 01:38:32 2010 From: buurin at gmail.com (Keith Hui) Date: Fri, 7 May 2010 19:38:32 -0400 Subject: [coreboot] PATCH: model_6bx CPUs can go in a lot of places In-Reply-To: References: <45617214e36fd8c64a14ac127ff710e8@imap.1and1.com> Message-ID: On Fri, May 7, 2010 at 7:01 PM, Idwer Vollering wrote: > > > 2010/5/7 Keith Hui >> >> I think I should get CAR running. But CAR is not quite developed for >> the rest of the 6xx family. >> >> If you look at the boot log you'll see that it got through to SeaBIOS >> just fine. My coreboot is still on romcc. >> >> What are the steps needed to enable CAR on a board? > > Example: see attached patch (as an example/reference only because > USE_PRINTK_IN_CAR, in src/mainboard/asus/p2b/Kconfig, somehow breaks > booting/serial output.. waiting for my pci post card to arrive). >> All that I can find with importance is two Kconfig options... Booting failed with POST code 0x10. Digging into code now. From vidwer at gmail.com Sat May 8 01:01:23 2010 From: vidwer at gmail.com (Idwer Vollering) Date: Sat, 8 May 2010 01:01:23 +0200 Subject: [coreboot] PATCH: model_6bx CPUs can go in a lot of places In-Reply-To: References: <45617214e36fd8c64a14ac127ff710e8@imap.1and1.com> Message-ID: 2010/5/7 Keith Hui > I think I should get CAR running. But CAR is not quite developed for > the rest of the 6xx family. > > If you look at the boot log you'll see that it got through to SeaBIOS > just fine. My coreboot is still on romcc. > > What are the steps needed to enable CAR on a board? > Example: see attached patch (as an example/reference only because USE_PRINTK_IN_CAR, in src/mainboard/asus/p2b/Kconfig, somehow breaks booting/serial output.. waiting for my pci post card to arrive). > > Thanks > Keith > > On 5/7/10, Joseph Smith wrote: > > > > > > > > On Thu, 6 May 2010 23:31:49 -0400, Keith Hui wrote: > >> Hi all, > >> > >> Intel model 6bx CPUs (specifically 6B1 and 6B4) can end up in a lot of > >> places, specifically Slot 1 and Socket 370. Ever since references to > >> them were removed from cpu/intel/model_6xx my coreboot would die when > >> initializing CPU with a "Unknown cpu" error. This patch fixes it by > >> adding references to model_6bx to cpu/intel/slot_1 and > >> cpu/intel/socket_PGA370. Also included are before and after boot logs > >> with relevant sections highlighted. > >> > >> Before boot log: http://coreboot.pastebin.com/CGWgihaG > >> After boot log: http://coreboot.pastebin.com/GLgnpZT6 > >> > >> Signed-off-by: Keith Hui > >> > >> ----- Begin patch ----- > >> Index: src/cpu/intel/slot_1/Makefile.inc > >> =================================================================== > >> --- src/cpu/intel/slot_1/Makefile.inc (revision 5527) > >> +++ src/cpu/intel/slot_1/Makefile.inc (working copy) > >> @@ -20,6 +20,7 @@ > >> > >> obj-y += slot_1.o > >> subdirs-y += ../model_6xx > >> +subdirs-y += ../model_6bx > >> subdirs-y += ../../x86/tsc > >> subdirs-y += ../../x86/mtrr > >> subdirs-y += ../../x86/lapic > >> Index: src/cpu/intel/socket_PGA370/Makefile.inc > >> =================================================================== > >> --- src/cpu/intel/socket_PGA370/Makefile.inc (revision 5527) > >> +++ src/cpu/intel/socket_PGA370/Makefile.inc (working copy) > >> @@ -20,6 +20,7 @@ > >> > >> obj-y += socket_PGA370.o > >> subdirs-y += ../model_6xx > >> +subdirs-y += ../model_6bx > >> subdirs-y += ../../x86/tsc > >> subdirs-y += ../../x86/mtrr > >> subdirs-y += ../../x86/lapic > >> > >> ----- End patch ----- > >> > > Hello Keith, > > I kind of saw this coming. That is why I left the 6bx's in model_6xx. The > > new model_6bx is intended for CAR, so I don't know how well it will work > > with romcc. My advice is to either get CAR running on your board, or we > put > > back the 6bx's in model_6xx for the interim. > > > > -- > > Thanks, > > Joseph Smith > > Set-Top-Linux > > www.settoplinux.org > > > > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot_r5527_asus_p2b_ram+car+printk.patch Type: text/x-diff Size: 49564 bytes Desc: not available URL: From stepan at coresystems.de Sat May 8 10:14:43 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 08 May 2010 10:14:43 +0200 Subject: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114) In-Reply-To: <665f02730557c26a7d0472538ec8d828.squirrel@www.boonen.name> References: <9fcf30ec4fe94654bd26b1ac9822bf75.squirrel@www.boonen.name> <074aeb78763ef5fb4e896f43a334b2f4.squirrel@www.boonen.name> <665f02730557c26a7d0472538ec8d828.squirrel@www.boonen.name> Message-ID: <4BE51D73.6030203@coresystems.de> On 5/7/10 10:37 PM, Joop Boonen wrote: > On Thu, May 6, 2010 11:56 am, Joop Boonen wrote: > >> On Thu, May 6, 2010 11:35 am, Joop Boonen wrote: >> >>> All, >>> >>> I have an issue with FILO the disk at ata-0 isn't seen. >>> >> > I've been trying some more. I've used the old IDE in FILO. It now > recognises the drive connected to the SIL3114. But still not the ATA > drive. > Under PCI support, try enabling [ ] Scan all PCI busses From stepan at coresystems.de Sat May 8 10:25:57 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 08 May 2010 10:25:57 +0200 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 1/many In-Reply-To: <4BE4907F.5030202@georgi-clan.de> References: <4BE4907F.5030202@georgi-clan.de> Message-ID: <4BE52015.7070906@coresystems.de> On 5/8/10 12:13 AM, Patrick Georgi wrote: > -#initobj-y += serial.o > +initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o > subdirs-y += vga > > Awesome... the less .c file includes we have in romstage.c the better.. This way works in the case of converting code that was previously always compiled in. But how should we handle things in case of other conditions? Acked-by: Stefan Reinauer Stefan From patrick at georgi-clan.de Sat May 8 10:34:23 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 08 May 2010 10:34:23 +0200 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 1/many In-Reply-To: <4BE52015.7070906@coresystems.de> References: <4BE4907F.5030202@georgi-clan.de> <4BE52015.7070906@coresystems.de> Message-ID: <1273307663.1518.3.camel@tetris> Am Samstag, den 08.05.2010, 10:25 +0200 schrieb Stefan Reinauer: > On 5/8/10 12:13 AM, Patrick Georgi wrote: > > -#initobj-y += serial.o > > +initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o > > subdirs-y += vga > > > > > Awesome... the less .c file includes we have in romstage.c the better.. > > This way works in the case of converting code that was previously always > compiled in. > > But how should we handle things in case of other conditions? We could stuff all of the initobjs into an initobj.a, and use that for linking. ld will only pick up the object files that are actually needed then. This means we probably compile a serial port thingy too many, but they're rather small. For chipset specific stuff (once we get there), it can be initobj-$(CONFIG_SOUTHBRIDGE_X_Y) += ... Patrick From svn at coreboot.org Sat May 8 11:14:52 2010 From: svn at coreboot.org (repository service) Date: Sat, 08 May 2010 11:14:52 +0200 Subject: [coreboot] [commit] r5528 - in trunk/src: console include/console mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit/be6-ii_v2_0 mainboard/advantech/pcm-5820 mainboard/amd/db800 mainboard/am... Message-ID: Author: oxygene Date: Sat May 8 11:14:51 2010 New Revision: 5528 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5528 Log: Drop console/console.c and pc80/serial.c from mainboards' romstage.c. Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Modified: trunk/src/console/Makefile.inc trunk/src/console/console.c trunk/src/include/console/console.h trunk/src/mainboard/a-trend/atc-6220/romstage.c trunk/src/mainboard/a-trend/atc-6240/romstage.c trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c trunk/src/mainboard/advantech/pcm-5820/romstage.c trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/asi/mb_5blgp/romstage.c trunk/src/mainboard/asi/mb_5blmp/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/asus/mew-am/romstage.c trunk/src/mainboard/asus/mew-vm/romstage.c trunk/src/mainboard/asus/p2b-d/romstage.c trunk/src/mainboard/asus/p2b-ds/romstage.c trunk/src/mainboard/asus/p2b-f/romstage.c trunk/src/mainboard/asus/p2b-ls/romstage.c trunk/src/mainboard/asus/p2b/romstage.c trunk/src/mainboard/asus/p3b-f/romstage.c trunk/src/mainboard/axus/tc320/romstage.c trunk/src/mainboard/azza/pt-6ibd/romstage.c trunk/src/mainboard/bcom/winnet100/romstage.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/biostar/m6tba/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/digitallogic/msm586seg/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/eaglelion/5bcm/romstage.c trunk/src/mainboard/emulation/qemu-x86/romstage.c trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iei/juki-511p/romstage.c trunk/src/mainboard/iei/nova4899r/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/mitac/6513wu/romstage.c trunk/src/mainboard/msi/ms6119/romstage.c trunk/src/mainboard/msi/ms6147/romstage.c trunk/src/mainboard/msi/ms6156/romstage.c trunk/src/mainboard/msi/ms6178/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nec/powermate2000/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nokia/ip530/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/olpc/btest/romstage.c trunk/src/mainboard/olpc/rev_a/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/technologic/ts5300/romstage.c trunk/src/mainboard/televideo/tc7020/romstage.c trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/mainboard/tyan/s1846/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-m/romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/epia-n/romstage.c trunk/src/mainboard/via/epia/romstage.c trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/via/vt8454c/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/pc80/Makefile.inc trunk/src/pc80/serial.c Modified: trunk/src/console/Makefile.inc ============================================================================== --- trunk/src/console/Makefile.inc Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/console/Makefile.inc Sat May 8 11:14:51 2010 (r5528) @@ -7,6 +7,7 @@ smmobj-y += vtxprintf.o initobj-y += vtxprintf.o +initobj-$(CONFIG_USE_DCACHE_RAM) += console.o driver-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.o driver-$(CONFIG_USBDEBUG_DIRECT) += usbdebug_direct_console.o Modified: trunk/src/console/console.c ============================================================================== --- trunk/src/console/console.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/console/console.c Sat May 8 11:14:51 2010 (r5528) @@ -5,9 +5,9 @@ #include #include #include +#include #ifndef __PRE_RAM__ -#include #include #include Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/include/console/console.h Sat May 8 11:14:51 2010 (r5528) @@ -307,4 +307,9 @@ #endif +#ifdef __ROMCC__ +/* if included by romcc, include the sources, too. romcc can't use prototypes */ +#include +#endif + #endif /* CONSOLE_CONSOLE_H_ */ Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/a-trend/atc-6220/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/a-trend/atc-6240/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/a-trend/atc-6240/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/advantech/pcm-5820/romstage.c ============================================================================== --- trunk/src/mainboard/advantech/pcm-5820/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/advantech/pcm-5820/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -24,7 +24,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/amd/db800/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -19,13 +19,12 @@ */ #include +#include #include #include #include #include -#include "pc80/serial.c" #include -#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" @@ -33,7 +32,6 @@ #include #include "southbridge/amd/cs5536/cs5536.h" -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -42,8 +42,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/amd/mahogany/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -42,8 +42,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -47,8 +47,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "console/console.c" -#include "pc80/serial.c" +#include #include "lib/ramtest.c" #include #include "northbridge/amd/amdfam10/raminit.h" Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/amd/norwich/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -23,8 +23,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/amd/pistachio/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -36,8 +36,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/amd/rumba/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -5,7 +5,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -29,8 +29,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -47,8 +47,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "console/console.c" -#include "pc80/serial.c" +#include #include "lib/ramtest.c" #include #include "southbridge/amd/amd8111/amd8111_early_smbus.c" Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -47,8 +47,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "console/console.c" -#include "pc80/serial.c" +#include #include "lib/ramtest.c" #include #include "northbridge/amd/amdfam10/raminit.h" Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/arima/hdama/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -7,8 +7,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -25,8 +25,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/asi/mb_5blgp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blgp/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asi/mb_5blgp/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -24,7 +24,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/asi/mb_5blmp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blmp/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asi/mb_5blmp/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -25,7 +25,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc87351/pc87351_early_serial.c" Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -43,8 +43,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -48,8 +48,7 @@ #define CK804_NUM 1 #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -46,8 +46,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -51,8 +51,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/asus/mew-am/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-am/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/mew-am/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" Modified: trunk/src/mainboard/asus/mew-vm/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-vm/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/mew-vm/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" #include "northbridge/intel/i82810/raminit.h" Modified: trunk/src/mainboard/asus/p2b-d/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/p2b-d/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -27,7 +27,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/p2b-ds/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -27,7 +27,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/asus/p2b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-f/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/p2b-f/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/asus/p2b/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/p2b/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/asus/p3b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p3b-f/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/asus/p3b-f/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/axus/tc320/romstage.c ============================================================================== --- trunk/src/mainboard/axus/tc320/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/axus/tc320/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -25,7 +25,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" Modified: trunk/src/mainboard/azza/pt-6ibd/romstage.c ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/azza/pt-6ibd/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/bcom/winnet100/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnet100/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/bcom/winnet100/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -25,7 +25,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,8 +26,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/biostar/m6tba/romstage.c ============================================================================== --- trunk/src/mainboard/biostar/m6tba/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/biostar/m6tba/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/broadcom/blast/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -13,8 +13,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/dell/s1850/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,8 +8,7 @@ #include #include "pc80/udelay_io.c" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -6,7 +6,7 @@ #include #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "cpu/x86/bist.h" //#include "lib/delay.c" Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -4,8 +4,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c ============================================================================== --- trunk/src/mainboard/eaglelion/5bcm/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/eaglelion/5bcm/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -6,7 +6,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" //#include "southbridge/intel/i440bx/i440bx_early_smbus.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" Modified: trunk/src/mainboard/emulation/qemu-x86/romstage.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/emulation/qemu-x86/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" Modified: trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -53,8 +53,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #if CONFIG_USBDEBUG_DIRECT #include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -51,8 +51,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -57,8 +57,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" /* TODO: It's a PC87364 actually! */ #include "superio/nsc/pc87360/pc87360_early_serial.c" Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/ibm/e325/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -9,8 +9,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/ibm/e326/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -9,8 +9,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/iei/juki-511p/romstage.c ============================================================================== --- trunk/src/mainboard/iei/juki-511p/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/iei/juki-511p/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -25,7 +25,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/winbond/w83977f/w83977f_early_serial.c" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" Modified: trunk/src/mainboard/iei/nova4899r/romstage.c ============================================================================== --- trunk/src/mainboard/iei/nova4899r/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/iei/nova4899r/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -25,7 +25,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -23,8 +23,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -37,8 +37,6 @@ #include "pc80/mc146818rtc_early.c" #include -#include "pc80/serial.c" -#include "console/console.c" #include #if CONFIG_USBDEBUG_DIRECT Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -32,8 +32,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/intel/jarrell/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -28,7 +28,7 @@ #include #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/intel/truxton/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -29,7 +29,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "pc80/udelay_io.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -9,7 +9,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -29,8 +29,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -29,8 +29,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -29,8 +29,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,8 +26,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -46,8 +46,6 @@ #include "pc80/mc146818rtc_early.c" #include -#include "pc80/serial.c" -#include "console/console.c" #include #if CONFIG_USBDEBUG_DIRECT Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/kontron/kt690/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -43,8 +43,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -5,7 +5,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -27,8 +27,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -28,8 +28,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/mitac/6513wu/romstage.c ============================================================================== --- trunk/src/mainboard/mitac/6513wu/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/mitac/6513wu/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" Modified: trunk/src/mainboard/msi/ms6119/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6119/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/msi/ms6119/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/msi/ms6147/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6147/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/msi/ms6147/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/msi/ms6156/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6156/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/msi/ms6156/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/msi/ms6178/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/msi/ms6178/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/i82810/raminit.h" Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/msi/ms7135/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -50,8 +50,7 @@ #define CK804_USE_ACI 1 #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/msi/ms7260/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -55,8 +55,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/msi/ms9185/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -49,8 +49,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/msi/ms9282/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -44,8 +44,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -45,8 +45,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/nec/powermate2000/romstage.c ============================================================================== --- trunk/src/mainboard/nec/powermate2000/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/nec/powermate2000/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82810/raminit.h" Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/newisys/khepri/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -14,8 +14,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/nokia/ip530/romstage.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/nokia/ip530/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -51,8 +51,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/olpc/btest/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/btest/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/olpc/btest/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -5,7 +5,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/olpc/rev_a/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/olpc/rev_a/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -5,7 +5,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -24,8 +24,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/rca/rm4100/romstage.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/rca/rm4100/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -25,9 +25,8 @@ #include #include #include -#include "pc80/serial.c" #include "pc80/udelay_io.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -39,8 +39,6 @@ #include "pc80/mc146818rtc_early.c" #include -#include "pc80/serial.c" -#include "console/console.c" #include #if CONFIG_USBDEBUG_DIRECT Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -16,8 +16,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -46,8 +46,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -49,8 +49,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -44,8 +44,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -44,8 +44,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "pc80/udelay_io.c" #include "lib/delay.c" Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "pc80/udelay_io.c" #include "lib/delay.c" Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -42,8 +42,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -42,8 +42,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/technologic/ts5300/romstage.c ============================================================================== --- trunk/src/mainboard/technologic/ts5300/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/technologic/ts5300/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -12,7 +12,7 @@ #include #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/televideo/tc7020/romstage.c ============================================================================== --- trunk/src/mainboard/televideo/tc7020/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/televideo/tc7020/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -25,7 +25,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,9 +26,8 @@ #include #include #include -#include "pc80/serial.c" #include "pc80/udelay_io.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" Modified: trunk/src/mainboard/tyan/s1846/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s1846/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s1846/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,7 +26,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2735/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,8 +8,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2850/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -9,8 +9,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2875/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -9,8 +9,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2880/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -9,8 +9,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2881/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -13,8 +13,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2882/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -9,8 +9,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2885/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,8 +8,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2891/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -14,8 +14,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2892/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -14,8 +14,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2895/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -15,8 +15,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2912/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -51,8 +51,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -45,8 +45,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s4880/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -9,8 +9,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/tyan/s4882/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -8,8 +8,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/via/epia-cn/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,8 +26,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/epia-m/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/via/epia-m/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -7,7 +7,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/via/vt8623/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/via/epia-m700/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -33,8 +33,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/via/vx800/vx800.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/via/epia-n/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -27,7 +27,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/via/cn400/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/epia/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/via/epia/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -6,7 +6,7 @@ #include #include #include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/via/vt8601/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/via/pc2500e/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -27,8 +27,7 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/vt8454c/romstage.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/via/vt8454c/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -26,8 +26,7 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "northbridge/via/cx700/raminit.h" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/mainboard/winent/pl6064/romstage.c Sat May 8 11:14:51 2010 (r5528) @@ -20,12 +20,12 @@ */ #include +#include #include #include #include #include -#include "pc80/serial.c" -#include "console/console.c" +#include #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" @@ -33,7 +33,6 @@ #include #include "southbridge/amd/cs5536/cs5536.h" -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" Modified: trunk/src/pc80/Makefile.inc ============================================================================== --- trunk/src/pc80/Makefile.inc Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/pc80/Makefile.inc Sat May 8 11:14:51 2010 (r5528) @@ -4,7 +4,7 @@ obj-$(CONFIG_UDELAY_IO) += udelay_io.o obj-y += keyboard.o -#initobj-y += serial.o +initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o subdirs-y += vga $(obj)/pc80/mc146818rtc.o : $(OPTION_TABLE_H) Modified: trunk/src/pc80/serial.c ============================================================================== --- trunk/src/pc80/serial.c Thu May 6 21:32:12 2010 (r5527) +++ trunk/src/pc80/serial.c Sat May 8 11:14:51 2010 (r5528) @@ -1,4 +1,5 @@ #include /* Prototypes */ +#include /* Base Address */ #ifndef CONFIG_TTYS0_BASE From info at coresystems.de Sat May 8 11:27:11 2010 From: info at coresystems.de (coreboot information) Date: Sat, 08 May 2010 11:27:11 +0200 Subject: [coreboot] build service results for r5528 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5528 to the coreboot repository. This caused the following changes: Change Log: Drop console/console.c and pc80/serial.c from mainboards' romstage.c. Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Build Log: Compilation of amd:norwich has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=norwich&vendor=amd&num=2 Compilation of amd:serengeti_cheetah has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=serengeti_cheetah&vendor=amd&num=2 Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=a8n_e&vendor=asus&num=2 Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=adl855pc&vendor=digitallogic&num=2 Compilation of iei:pcisa-lx-800-r10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=pcisa-lx-800-r10&vendor=iei&num=2 Compilation of iwill:dk8_htx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=dk8_htx&vendor=iwill&num=2 Compilation of iwill:dk8x has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=dk8x&vendor=iwill&num=2 Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=986lcd-m&vendor=kontron&num=2 Compilation of msi:ms9652_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=ms9652_fam10&vendor=msi&num=2 Compilation of sunw:ultra40 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=ultra40&vendor=sunw&num=2 Compilation of supermicro:h8dme has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=h8dme&vendor=supermicro&num=2 Compilation of thomson:ip1000 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=ip1000&vendor=thomson&num=2 Compilation of tyan:s4882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5528&device=s4882&vendor=tyan&num=2 If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Sat May 8 13:17:24 2010 From: svn at coreboot.org (repository service) Date: Sat, 08 May 2010 13:17:24 +0200 Subject: [coreboot] [commit] r5529 - trunk/src/console Message-ID: Author: stepan Date: Sat May 8 13:17:24 2010 New Revision: 5529 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5529 Log: We didn't have console.initobj.o before, but the same hard coded build rule is needed as for console.o Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/console/Makefile.inc Modified: trunk/src/console/Makefile.inc ============================================================================== --- trunk/src/console/Makefile.inc Sat May 8 11:14:51 2010 (r5528) +++ trunk/src/console/Makefile.inc Sat May 8 13:17:24 2010 (r5529) @@ -17,3 +17,4 @@ driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.o $(obj)/console/console.o : $(obj)/build.h +$(obj)/console/console.initobj.o : $(obj)/build.h From info at coresystems.de Sat May 8 13:30:31 2010 From: info at coresystems.de (coreboot information) Date: Sat, 08 May 2010 13:30:31 +0200 Subject: [coreboot] build service results for r5529 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5529 to the coreboot repository. This caused the following changes: Change Log: We didn't have console.initobj.o before, but the same hard coded build rule is needed as for console.o Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:norwich has been fixed Compilation of amd:serengeti_cheetah has been fixed Compilation of asus:a8n_e has been fixed Compilation of digitallogic:adl855pc has been fixed Compilation of iei:pcisa-lx-800-r10 has been fixed Compilation of iwill:dk8_htx has been fixed Compilation of iwill:dk8x has been fixed Compilation of kontron:986lcd-m has been fixed Compilation of msi:ms9652_fam10 has been fixed Compilation of sunw:ultra40 has been fixed Compilation of supermicro:h8dme has been fixed Compilation of thomson:ip1000 has been fixed Compilation of tyan:s4882 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Sat May 8 17:50:44 2010 From: svn at coreboot.org (repository service) Date: Sat, 08 May 2010 17:50:44 +0200 Subject: [coreboot] [commit] r5530 - trunk Message-ID: Author: oxygene Date: Sat May 8 17:50:44 2010 New Revision: 5530 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5530 Log: Slightly improve detecting Windows. Trivial Signed-off-by: Patrick Georgi Acked-by: Patrick Georgi Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat May 8 13:17:24 2010 (r5529) +++ trunk/Makefile Sat May 8 17:50:44 2010 (r5530) @@ -368,12 +368,12 @@ $(obj)/ldoptions: $(obj)/config.h awk '/^#define ([^"])* ([^"])*$$/ {gsub("\\r","",$$3); print $$2 " = " $$3 ";";}' $< > $@ -_OS=$(shell uname -s |cut -c-7) +_OS=$(shell uname -o) STACK= -ifeq ($(_OS),MINGW32) +ifeq ($(_OS),Msys) STACK=-Wl,--stack,16384000 endif -ifeq ($(_OS),CYGWIN_) +ifeq ($(_OS),Cygwin) STACK=-Wl,--stack,16384000 endif $(objutil)/romcc/romcc: $(top)/util/romcc/romcc.c From kevin at koconnor.net Sat May 8 17:56:46 2010 From: kevin at koconnor.net (Kevin O'Connor) Date: Sat, 8 May 2010 11:56:46 -0400 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 1/many In-Reply-To: <1273307663.1518.3.camel@tetris> References: <4BE4907F.5030202@georgi-clan.de> <4BE52015.7070906@coresystems.de> <1273307663.1518.3.camel@tetris> Message-ID: <20100508155646.GA3688@morn.localdomain> On Sat, May 08, 2010 at 10:34:23AM +0200, Patrick Georgi wrote: > Am Samstag, den 08.05.2010, 10:25 +0200 schrieb Stefan Reinauer: > > On 5/8/10 12:13 AM, Patrick Georgi wrote: > > > -#initobj-y += serial.o > > > +initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o > > > subdirs-y += vga > > Awesome... the less .c file includes we have in romstage.c the better.. > > > > This way works in the case of converting code that was previously always > > compiled in. > > > > But how should we handle things in case of other conditions? > We could stuff all of the initobjs into an initobj.a, and use that for > linking. ld will only pick up the object files that are actually needed > then. This means we probably compile a serial port thingy too many, but > they're rather small. I think coreboot should try to avoid using .a files. The latest version of gcc (v4.5) contains the -flto feature. This can provide significant benefits to coreboot code generation because it allows the entire romstage (and ramstage) to be analyzed as a whole. The resulting binaries are significantly smaller because unused code can be eliminated and more functions can be inlined. Unfortunately, the standard linker can't handle -flto with .a files. -Kevin From patrick at georgi-clan.de Sat May 8 17:59:19 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 08 May 2010 17:59:19 +0200 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 1/many In-Reply-To: <20100508155646.GA3688@morn.localdomain> References: <4BE4907F.5030202@georgi-clan.de> <4BE52015.7070906@coresystems.de> <1273307663.1518.3.camel@tetris> <20100508155646.GA3688@morn.localdomain> Message-ID: <4BE58A57.8020908@georgi-clan.de> Am 08.05.2010 17:56, schrieb Kevin O'Connor: > I think coreboot should try to avoid using .a files. > > The latest version of gcc (v4.5) contains the -flto feature. This can > provide significant benefits to coreboot code generation because it > allows the entire romstage (and ramstage) to be analyzed as a whole. > The resulting binaries are significantly smaller because unused code > can be eliminated and more functions can be inlined. Unfortunately, > the standard linker can't handle -flto with .a files. Our build system is advanced enough that this can be an option based on compiler version. Thanks for the notice, but I guess we should support non-lto builds until gcc4.5 is the lowest common denominator, or even better the next version, so we can assume that bugs are fixed. Patrick From stepan at coresystems.de Sat May 8 18:21:03 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 08 May 2010 18:21:03 +0200 Subject: [coreboot] [commit] r5530 - trunk In-Reply-To: References: Message-ID: <4BE58F6F.1030602@coresystems.de> On 5/8/10 5:50 PM, repository service wrote: > Modified: trunk/Makefile > ============================================================================== > --- trunk/Makefile Sat May 8 13:17:24 2010 (r5529) > +++ trunk/Makefile Sat May 8 17:50:44 2010 (r5530) > @@ -368,12 +368,12 @@ > $(obj)/ldoptions: $(obj)/config.h > awk '/^#define ([^"])* ([^"])*$$/ {gsub("\\r","",$$3); print $$2 " = " $$3 ";";}' $< > $@ > > -_OS=$(shell uname -s |cut -c-7) > +_OS=$(shell uname -o) GNUism warning macpro:coreboot stepan$ uname -s Darwin macpro:coreboot stepan$ uname -o uname: illegal option -- o usage: uname [-amnprsv] From stepan at coresystems.de Sat May 8 18:22:54 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 08 May 2010 18:22:54 +0200 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 1/many In-Reply-To: <20100508155646.GA3688@morn.localdomain> References: <4BE4907F.5030202@georgi-clan.de> <4BE52015.7070906@coresystems.de> <1273307663.1518.3.camel@tetris> <20100508155646.GA3688@morn.localdomain> Message-ID: <4BE58FDE.1040104@coresystems.de> On 5/8/10 5:56 PM, Kevin O'Connor wrote: > I think coreboot should try to avoid using .a files. > > The latest version of gcc (v4.5) contains the -flto feature. This can > provide significant benefits to coreboot code generation because it > allows the entire romstage (and ramstage) to be analyzed as a whole. > The resulting binaries are significantly smaller because unused code > can be eliminated and more functions can be inlined. Unfortunately, > the standard linker can't handle -flto with .a files. > The reason we used .a files to begin with was because the linker can smartly drop unused objects files "linked" into a static library, significantly decreasing code size. Going to -flto introduces one code size reduction mechanism by rendering another one unusable. That's only half-baked, especially since many optimizations making -flto useful are still known broken in gcc 4.5. We should keep this in mind. Last time I checked -flto on a coreboot image it would not gain more than 1-2kb on a 1MB image. Didn't benchmark the 4.5 release yet though. Being curious: Will gold cope with .a files and flto? From patrick at georgi-clan.de Sat May 8 18:24:06 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 08 May 2010 18:24:06 +0200 Subject: [coreboot] [commit] r5530 - trunk In-Reply-To: <4BE58F6F.1030602@coresystems.de> References: <4BE58F6F.1030602@coresystems.de> Message-ID: <4BE59026.2070601@georgi-clan.de> Am 08.05.2010 18:21, schrieb Stefan Reinauer: >> -_OS=$(shell uname -s |cut -c-7) >> +_OS=$(shell uname -o) > GNUism warning Platform warning. Given that this is exclusively used for checking for mingw and cygwin (both support this), at most this requires routing the error message to /dev/null. And rename the variable so it's not used for any non-windows purpose. Patrick From kevin at koconnor.net Sat May 8 18:40:27 2010 From: kevin at koconnor.net (Kevin O'Connor) Date: Sat, 8 May 2010 12:40:27 -0400 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 1/many In-Reply-To: <4BE58FDE.1040104@coresystems.de> References: <4BE4907F.5030202@georgi-clan.de> <4BE52015.7070906@coresystems.de> <1273307663.1518.3.camel@tetris> <20100508155646.GA3688@morn.localdomain> <4BE58FDE.1040104@coresystems.de> Message-ID: <20100508164027.GA6574@morn.localdomain> On Sat, May 08, 2010 at 06:22:54PM +0200, Stefan Reinauer wrote: > On 5/8/10 5:56 PM, Kevin O'Connor wrote: > > I think coreboot should try to avoid using .a files. > > > > The latest version of gcc (v4.5) contains the -flto feature. This can > > provide significant benefits to coreboot code generation because it > > allows the entire romstage (and ramstage) to be analyzed as a whole. > > The resulting binaries are significantly smaller because unused code > > can be eliminated and more functions can be inlined. Unfortunately, > > the standard linker can't handle -flto with .a files. > > > The reason we used .a files to begin with was because the linker can > smartly drop unused objects files "linked" into a static library, > significantly decreasing code size. Yeah, but I've not had much luck with that optimization because it's too easy to inadvertently pull in .o files. I've had more success with enabling -ffunction-sections / -fdata-sections and giving ld the --gc-sections option. > Going to -flto introduces one code size reduction mechanism by rendering > another one unusable. That's only half-baked, especially since many > optimizations making -flto useful are still known broken in gcc 4.5. We > should keep this in mind. Last time I checked -flto on a coreboot image > it would not gain more than 1-2kb on a 1MB image. Didn't benchmark the > 4.5 release yet though. I use -fwhole-program in seabios and find it quite useful. I haven't done much with -flto, but it is supposed to allow -fwhole-program without having to completely restructure the build process. It's more than just a size optimization, though I suspect that's the biggest impact coreboot would see. > Being curious: Will gold cope with .a files and flto? Yes (according to the gcc documentation). See the -flto description at: http://gcc.gnu.org/onlinedocs/gcc-4.5.0/gcc/Optimize-Options.html#Optimize-Options -Kevin From svn at coreboot.org Sat May 8 19:15:36 2010 From: svn at coreboot.org (repository service) Date: Sat, 08 May 2010 19:15:36 +0200 Subject: [coreboot] [commit] r5531 - trunk Message-ID: Author: stepan Date: Sat May 8 19:15:36 2010 New Revision: 5531 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5531 Log: Patrick Georgi wrote: Given that this is exclusively used for checking for mingw and cygwin (both support this), at most this requires routing the error message to /dev/null. And rename the variable so it's not used for any non-windows purpose. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat May 8 17:50:44 2010 (r5530) +++ trunk/Makefile Sat May 8 19:15:36 2010 (r5531) @@ -368,14 +368,15 @@ $(obj)/ldoptions: $(obj)/config.h awk '/^#define ([^"])* ([^"])*$$/ {gsub("\\r","",$$3); print $$2 " = " $$3 ";";}' $< > $@ -_OS=$(shell uname -o) +_WINCHECK=$(shell uname -o 2> /dev/null) STACK= -ifeq ($(_OS),Msys) +ifeq ($(_WINCHECK),Msys) STACK=-Wl,--stack,16384000 endif -ifeq ($(_OS),Cygwin) +ifeq ($(_WINCHECK),Cygwin) STACK=-Wl,--stack,16384000 endif + $(objutil)/romcc/romcc: $(top)/util/romcc/romcc.c @printf " HOSTCC $(subst $(obj)/,,$(@)) (this may take a while)\n" @# Note: Adding -O2 here might cause problems. For details see: From svn at coreboot.org Sat May 8 20:14:50 2010 From: svn at coreboot.org (repository service) Date: Sat, 08 May 2010 20:14:50 +0200 Subject: [coreboot] [commit] r5532 - trunk/src/arch/i386/include/arch Message-ID: Author: stepan Date: Sat May 8 20:14:50 2010 New Revision: 5532 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5532 Log: wipe some old unused code, this has been cleaned up now. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/arch/i386/include/arch/io.h trunk/src/arch/i386/include/arch/romcc_io.h Modified: trunk/src/arch/i386/include/arch/io.h ============================================================================== --- trunk/src/arch/i386/include/arch/io.h Sat May 8 19:15:36 2010 (r5531) +++ trunk/src/arch/i386/include/arch/io.h Sat May 8 20:14:50 2010 (r5532) @@ -134,47 +134,6 @@ ); } -#if 0 -/* XXX XXX XXX This is a story from the evil API from hell XXX XXX XXX - * We have different functions for memory access in pre-ram stage and ram - * stage. Those in pre-ram stage are called write32 and expect the address - * first and the address as a pointer type. Those in ram stage are called - * writel and expect the datum first and the address as an integer type. - * Until all code is checked and fixed, I'll add both versions here now. - */ - -static inline void writeb(uint8_t b, volatile void *addr) -{ - *(volatile uint8_t *) addr = b; -} - -static inline void writew(uint16_t b, volatile void *addr) -{ - *(volatile uint16_t *) addr = b; -} - -static inline void writel(uint32_t b, volatile void *addr) -{ - *(volatile uint32_t *) addr = b; -} - -static inline uint8_t readb(const volatile void *addr) -{ - return *(volatile uint8_t *) addr; -} - -static inline uint16_t readw(const volatile void *addr) -{ - return *(volatile uint16_t *) addr; -} - -static inline uint32_t readl(const volatile void *addr) -{ - return *(volatile uint32_t *) addr; -} -#endif - -#if !defined(__PRE_RAM__) static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr) { return *((volatile uint8_t *)(addr)); @@ -204,7 +163,6 @@ { *((volatile uint32_t *)(addr)) = value; } -#endif #endif Modified: trunk/src/arch/i386/include/arch/romcc_io.h ============================================================================== --- trunk/src/arch/i386/include/arch/romcc_io.h Sat May 8 19:15:36 2010 (r5531) +++ trunk/src/arch/i386/include/arch/romcc_io.h Sat May 8 20:14:50 2010 (r5532) @@ -3,37 +3,9 @@ #include -#ifdef __PRE_RAM__ -static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr) -{ - return *((volatile uint8_t *)(addr)); -} - -static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr) -{ - return *((volatile uint16_t *)(addr)); -} - -static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr) -{ - return *((volatile uint32_t *)(addr)); -} - -static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value) -{ - *((volatile uint8_t *)(addr)) = value; -} - -static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value) -{ - *((volatile uint16_t *)(addr)) = value; -} - -static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value) -{ - *((volatile uint32_t *)(addr)) = value; -} -#endif +// arch/io.h is pulled in in many places but it could +// also be pulled in here for all romcc/romstage code. +// #include #if CONFIG_MMCONF_SUPPORT From stepan at coresystems.de Sat May 8 20:43:58 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 08 May 2010 20:43:58 +0200 Subject: [coreboot] [PATCH] improve realmode api Message-ID: <4BE5B0EE.2040503@coresystems.de> See patch -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: oprom.diff URL: From patrick at georgi-clan.de Sat May 8 22:59:42 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 08 May 2010 22:59:42 +0200 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 2/many Message-ID: <4BE5D0BE.7070006@georgi-clan.de> Hi, attached patch completes the changes from the first part, by eliminating the direct inclusion of pc80/serial.c in all romstage.c files. So far, they were still around in ROMCC builds. I moved the include to console/console.h, guarded so it's only included for ROMCC, as this file is a direct consumer of the functions in pc80/serial.c It's abuild tested and Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20100508-2-remove-serial.c-includes.diff URL: From njacobs8 at hetnet.nl Sat May 8 23:15:54 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sat, 8 May 2010 23:15:54 +0200 Subject: [coreboot] [PATCH] improve realmode api Message-ID: <201005082315.54795.njacobs8@hetnet.nl> Hi Stefan, I tested your patch in the hope that my Geode GX2 board started to work again. Unfortunatly it doesn`t. My board stopped working after your vsm loading patches in rev5471. The error after rev5471 was "hda: lost interrupt" . Now after rev5532 with your improve realmode api patch the board oopses. I will not ack nor nack because i know to little about programming. Thanks,Nils. Last part of rev5532 + improve realmode api patch: sizeram: sizem 0x200 setup_gx2_cache: enable for 524288 KB msr 0x00001808 will be set to 25fff002:11ffe000 MSR 0x10000026 is now 0x2dfbe040:0x400fffe0 Preparing for VSA... VSA: Real mode stub @00000600: 628 bytes Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + 79ab + align -> fff07a00 Check fallback/payload CBFS: follow chain: fff07a00 + 38 + 11038 + align -> fff18a80 Check vsa Stage: loading vsa @ 0x60000 (57868 bytes), entry @ 0x60020 Stage: done loading. VSA: Buffer @00060000 *[0k]=ba VSA: Signature *[0x20-0x23] is b0:10:e6:80 Calling VSA module... oprom: INT# 0xd oprom: eax: 11ffe000 ebx: 80007800 ecx: 00001012 edx: 25fff002 oprom: ebp: 00000ff4 esp: 00000fec edi: 0000102d esi: 00000028 oprom: ip: 0647 cs: 6000 flags: 00000013 Oops, exception 13 while executing option rom Unexpected Exception: 13 @ 6000:00000647 - Halting Code: 0 eflags: 00000013 eax: 11ffe000 ebx: 80007800 ecx: 00001012 edx: 25fff002 edi: 0000102d esi: 00000028 ebp: 00000ff4 esp: 00000fec From stepan at coresystems.de Sat May 8 23:40:32 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 08 May 2010 23:40:32 +0200 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 2/many In-Reply-To: <4BE5D0BE.7070006@georgi-clan.de> References: <4BE5D0BE.7070006@georgi-clan.de> Message-ID: <4BE5DA50.4080401@coresystems.de> On 5/8/10 10:59 PM, Patrick Georgi wrote: > Index: src/include/lib.h > =================================================================== > --- src/include/lib.h (Revision 5532) > +++ src/include/lib.h (Arbeitskopie) > @@ -49,5 +49,7 @@ > void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); > #endif > > +#else /* __ROMCC__ */ > +#include "pc80/serial.c" > #endif /* __ROMCC__ */ > #endif /* __LIB_H__ */ > It looks like only console/console.h is actually using these functions, so I think it should rather be included in console/console.h than in lib.h? Stefan -------------- next part -------------- An HTML attachment was scrubbed... URL: From stepan at coresystems.de Sat May 8 23:41:47 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 08 May 2010 23:41:47 +0200 Subject: [coreboot] [PATCH] improve realmode api In-Reply-To: <201005082315.54795.njacobs8@hetnet.nl> References: <201005082315.54795.njacobs8@hetnet.nl> Message-ID: <4BE5DA9B.1060003@coresystems.de> Hey Nils, can you confirm r5470 works with your board? If so, could you send me a complete boot log with that revision, please? Which board was that again? Which VSM module are you using? Stefan On 5/8/10 11:15 PM, Nils wrote: > Hi Stefan, > I tested your patch in the hope that my Geode GX2 board started to work again. > Unfortunatly it doesn`t. > My board stopped working after your vsm loading patches in rev5471. > The error after rev5471 was "hda: lost interrupt" . > Now after rev5532 with your improve realmode api patch the board oopses. > > I will not ack nor nack because i know to little about programming. > > Thanks,Nils. > > Last part of rev5532 + improve realmode api patch: > > sizeram: sizem 0x200 > setup_gx2_cache: enable for 524288 KB > msr 0x00001808 will be set to 25fff002:11ffe000 > MSR 0x10000026 is now 0x2dfbe040:0x400fffe0 > Preparing for VSA... > VSA: Real mode stub @00000600: 628 bytes > Check CBFS header at fffeffe0 > magic is 4f524243 > Found CBFS header at fffeffe0 > Check fallback/coreboot_ram > CBFS: follow chain: fff00000 + 38 + 79ab + align -> fff07a00 > Check fallback/payload > CBFS: follow chain: fff07a00 + 38 + 11038 + align -> fff18a80 > Check vsa > Stage: loading vsa @ 0x60000 (57868 bytes), entry @ 0x60020 > Stage: done loading. > VSA: Buffer @00060000 *[0k]=ba > VSA: Signature *[0x20-0x23] is b0:10:e6:80 > Calling VSA module... > oprom: INT# 0xd > oprom: eax: 11ffe000 ebx: 80007800 ecx: 00001012 edx: 25fff002 > oprom: ebp: 00000ff4 esp: 00000fec edi: 0000102d esi: 00000028 > oprom: ip: 0647 cs: 6000 flags: 00000013 > Oops, exception 13 while executing option rom > Unexpected Exception: 13 @ 6000:00000647 - Halting > Code: 0 eflags: 00000013 > eax: 11ffe000 ebx: 80007800 ecx: 00001012 edx: 25fff002 > edi: 0000102d esi: 00000028 ebp: 00000ff4 esp: 00000fec > > From njacobs8 at hetnet.nl Sat May 8 23:44:17 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sat, 8 May 2010 23:44:17 +0200 Subject: [coreboot] [PATCH] improve realmode api Message-ID: <201005082344.17572.njacobs8@hetnet.nl> Hi, During my investigations i found this Geode GX2 hardware bug discription, could that have anything to do with my problems? Thanks,Nils. AMD Geode? GX Processors Silicon Revision 2.1 Specification Update: 1.15 Limit fault during exception in SMM with unreal code segment Description: When an exception or other interseg- ment change of flow (COF) occurs inside an SMI handler and the target offset is higher than the SMI handler's code segment (CS) limit, a spurious general protection fault for a segment limit violation may occur. The CS limit, normally FFFFh in real mode, can be set to a smaller value inside SMM with RSM or with an MSR write. When fetching the first instruction of an exception handler, or the target of a far jump, the CPU mistakenly uses that shortened CS limit instead of the implicit limit of FFFFh that would normally apply to a real mode code segment. This leads to an erroneous general protection excep- tion. Implications: Exceptions may generate a limit fault when a COF occurs while in SMM. Resolution: Leave the SMM's code segment limit at FFFFh, or put any SMM exception handlers and intersegment COF targets lower in their segment, at offsets that are less than the SMM CS limit. From patrick at georgi-clan.de Sat May 8 23:48:30 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 08 May 2010 23:48:30 +0200 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 2/many In-Reply-To: <4BE5DA50.4080401@coresystems.de> References: <4BE5D0BE.7070006@georgi-clan.de> <4BE5DA50.4080401@coresystems.de> Message-ID: <4BE5DC2E.7080109@georgi-clan.de> Am 08.05.2010 23:40, schrieb Stefan Reinauer: > On 5/8/10 10:59 PM, Patrick Georgi wrote: >> Index: src/include/lib.h >> =================================================================== >> --- src/include/lib.h (Revision 5532) >> +++ src/include/lib.h (Arbeitskopie) >> @@ -49,5 +49,7 @@ >> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); >> #endif >> >> +#else /* __ROMCC__ */ >> +#include "pc80/serial.c" >> #endif /* __ROMCC__ */ >> #endif /* __LIB_H__ */ >> > It looks like only console/console.h is actually using these functions, > so I think it should rather be included in console/console.h than in lib.h? Oops, that was the older version of the patch (this won't even compile on all boards) See attached patch instead Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20100508-2-remove-serial.c-includes.diff URL: From svn at coreboot.org Sat May 8 23:50:32 2010 From: svn at coreboot.org (repository service) Date: Sat, 08 May 2010 23:50:32 +0200 Subject: [coreboot] [commit] r5533 - in trunk/src/mainboard: . wyse wyse/s50 Message-ID: Author: stepan Date: Sat May 8 23:50:31 2010 New Revision: 5533 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5533 Log: Add the Wyse S50 thin client to Coreboot. Signed-off-by: Nils Jacobs Acked-by: Stefan Reinauer Added: trunk/src/mainboard/wyse/ trunk/src/mainboard/wyse/Kconfig trunk/src/mainboard/wyse/s50/ trunk/src/mainboard/wyse/s50/Kconfig trunk/src/mainboard/wyse/s50/chip.h trunk/src/mainboard/wyse/s50/cmos.layout trunk/src/mainboard/wyse/s50/devicetree.cb trunk/src/mainboard/wyse/s50/irq_tables.c trunk/src/mainboard/wyse/s50/mainboard.c trunk/src/mainboard/wyse/s50/romstage.c Modified: trunk/src/mainboard/Kconfig Modified: trunk/src/mainboard/Kconfig ============================================================================== --- trunk/src/mainboard/Kconfig Sat May 8 20:14:50 2010 (r5532) +++ trunk/src/mainboard/Kconfig Sat May 8 23:50:31 2010 (r5533) @@ -100,6 +100,8 @@ bool "VIA" config VENDOR_WINENT bool "Win Enterprises" +config VENDOR_WYSE + bool "Wyse" endchoice @@ -373,6 +375,16 @@ default "Win Enterprise" depends on VENDOR_WINENT +config MAINBOARD_VENDOR + string + default "Wyse" + depends on VENDOR_WYSE + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x102d + depends on VENDOR_WYSE + source "src/mainboard/a-trend/Kconfig" source "src/mainboard/abit/Kconfig" source "src/mainboard/advantech/Kconfig" @@ -421,6 +433,7 @@ source "src/mainboard/tyan/Kconfig" source "src/mainboard/via/Kconfig" source "src/mainboard/winent/Kconfig" +source "src/mainboard/wyse/Kconfig" config BOARD_ROMSIZE_KB_128 bool Added: trunk/src/mainboard/wyse/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/Kconfig Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,8 @@ +choice + prompt "Mainboard model" + depends on VENDOR_WYSE + +source "src/mainboard/wyse/s50/Kconfig" + +endchoice + Added: trunk/src/mainboard/wyse/s50/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/Kconfig Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,51 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_WYSE_S50 + bool "S50" + select ARCH_X86 + select CPU_AMD_GX2 + select NORTHBRIDGE_AMD_GX2 + select SOUTHBRIDGE_AMD_CS5536 + select ROMCC + select UDELAY_TSC + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_256 + +config MAINBOARD_DIR + string + default wyse/s50 + depends on BOARD_WYSE_S50 + +config MAINBOARD_PART_NUMBER + string + default "s50" + depends on BOARD_WYSE_S50 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_WYSE_S50 + +config IRQ_SLOT_COUNT + int + default 3 + depends on BOARD_WYSE_S50 Added: trunk/src/mainboard/wyse/s50/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/chip.h Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,5 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config { + int nicirq; +}; Added: trunk/src/mainboard/wyse/s50/cmos.layout ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/cmos.layout Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/src/mainboard/wyse/s50/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/devicetree.cb Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,32 @@ +chip northbridge/amd/gx2 + register "irqmap" = "0xaa5b" + register "setupflash" = "0" + device lapic_cluster 0 on + chip cpu/amd/model_gx2 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 1.0 on end + device pci 1.1 on end + chip southbridge/amd/cs5536 + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" #0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "1" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + device pci e.0 on end # Realtek 8139 LAN + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end +end + Added: trunk/src/mainboard/wyse/s50/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/irq_tables.c Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 200x TODO + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x0f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x100b, /* Vendor */ + 0x2b, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xdc, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x0f << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x5, 0x0}, + {0x00, (0x0d << 3) | 0x0, {{0x04, 0x0400}, {0x03, 0x0400}, {0x02, 0x0020}, {0x01, 0x0800}}, 0x1, 0x0}, + {0x00, (0x0e << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x2, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/src/mainboard/wyse/s50/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/mainboard.c Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,12 @@ +#include +#include +#include +#include +#include +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("WYSE S50 Mainboard") +}; + Added: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/romstage.c Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,167 @@ +#include +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include +#include "lib/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/gx2/raminit.h" + +static inline unsigned int ctz(unsigned int n) +{ + int zeros; + + n = (n ^ (n - 1)) >> 1; + for (zeros = 0; n; zeros++) + { + n >>= 1; + } + return zeros; +} + +static void sdram_set_spd_registers(const struct mem_controller *ctrl) +{ + /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * + * component Banks (byte 17) * module banks, side (byte 5) * + * width in bits (byte 6,7) + * = Density per side (byte 31) * number of sides (byte 5) */ + /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */ + msr_t msr; + unsigned char module_banks, val; + uint16_t dimm_size; + + msr = rdmsr(MC_CF07_DATA); + + /* get module banks (sides) per dimm, SPD byte 5 */ + module_banks = spd_read_byte(0xA0, 5); + if (module_banks < 1 || module_banks > 2) + print_err("Module banks per dimm\n"); + module_banks >>= 1; + msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); + msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); + + /* get component banks per module bank, SPD byte 17 */ + val = spd_read_byte(0xA0, 17); + if (val < 2 || val > 4) + print_err("Component banks per module bank\n"); + val >>= 2; + msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); + msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); + + dimm_size = spd_read_byte(0xA0, 31); + dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */ + dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */ + /* Module Density * Module Banks */ + dimm_size <<= (0 >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ + if (dimm_size != 0) { + dimm_size = ctz(dimm_size); + } + if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */ + print_err("Only support up to 512MB \n"); + hlt(); + } + msr.hi |= dimm_size << CF07_UPPER_D0_SZ_SHIFT; + + /* page size = 2^col address */ + val = spd_read_byte(0xA0, 4); + val -= 7; + msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT); + msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT); + + print_debug("computed msr.hi "); + print_debug_hex32(msr.hi); + print_debug("\n"); + + msr.lo = 0x00003400; + wrmsr(MC_CF07_DATA, msr); + + msr = rdmsr(MC_CF8F_DATA); + msr.hi = 0x18000008; + msr.lo = 0x296332a3; + wrmsr(MC_CF8F_DATA, msr); + +} + +#include "northbridge/amd/gx2/raminit.c" +#include "lib/generic_sdram.c" + +#include "northbridge/amd/gx2/pll_reset.c" +#include "cpu/amd/model_gx2/cpureginit.c" +#include "cpu/amd/model_gx2/syspreinit.c" + +static void msr_init(void) +{ + /* total physical memory */ + __builtin_wrmsr(0x1808, 0x11f6bf00, 0x21c00002); + + /* traditional memory 0kB-512kB, 512kB-1MB */ + __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); + __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); + __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2dfbc040); + __builtin_wrmsr(0x10000028, 0x6bf00100, 0x2000001f); + __builtin_wrmsr(0x1000002c, 0xffff0003, 0x2000ffff); + + __builtin_wrmsr(0x10000080, 0x3, 0x0); + + __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); + __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); + __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040); + __builtin_wrmsr(0x40000029, 0x6bf00100, 0x2000001f); + __builtin_wrmsr(0x4000002d, 0xffff0003, 0x2000ffff); + + __builtin_wrmsr(0x40000080, 0x1, 0x0); + + __builtin_wrmsr(0x50002001, 0x27, 0x0); + __builtin_wrmsr(0x4c002001, 0x1, 0x0); + + /* put code in northbridge[init].c here */ +} + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl [] = { + {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* disable the power button */ + outl(0x00, PMS_IO_BASE + 0x40); + + cs5536_setup_onchipuart(1); + + uart_init(); + console_init(); + + pll_reset(); + + cpuRegInit(); + print_err("done cpuRegInit\n"); + + sdram_initialize(1, memctrl); + print_err("ram setup done\n"); + + /* Check all of memory */ + /*ram_check(0x00000000, 640*1024);*/ + print_err("ram check done\n"); +} + From joe at settoplinux.org Sat May 8 23:57:16 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 08 May 2010 17:57:16 -0400 Subject: [coreboot] [commit] r5533 - in trunk/src/mainboard: . wyse wyse/s50 In-Reply-To: References: Message-ID: <4BE5DE3C.8040909@settoplinux.org> On 05/08/2010 05:50 PM, repository service wrote: > Author: stepan > Date: Sat May 8 23:50:31 2010 > New Revision: 5533 > URL: https://tracker.coreboot.org/trac/coreboot/changeset/5533 > > Log: > Add the Wyse S50 thin client to Coreboot. > Signed-off-by: Nils Jacobs > Acked-by: Stefan Reinauer > Sweet! Wyse S30 will be coming soon too! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From stepan at coresystems.de Sun May 9 00:00:22 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 09 May 2010 00:00:22 +0200 Subject: [coreboot] GX2 problems In-Reply-To: <201005010158.34049.njacobs8@hetnet.nl> References: <201005010158.34049.njacobs8@hetnet.nl> Message-ID: <4BE5DEF6.6030701@coresystems.de> On 5/1/10 1:58 AM, Nils wrote: > Index: src/northbridge/amd/gx2/northbridgeinit.c > =================================================================== > --- src/northbridge/amd/gx2/northbridgeinit.c (revision 5520) > +++ src/northbridge/amd/gx2/northbridgeinit.c (working copy) > @@ -672,7 +672,7 @@ > { > uint64_t shadowSettings = getShadow(); > shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes > - shadowSettings |= (uint64_t) 0x00000000F0000000ULL; // Enable reads for F0000-FFFFF > + shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable reads for C0000-FFFFF > setShadow(shadowSettings); > } > > What's this doing? Is it potentially dangerous for other systems? -------------- next part -------------- An HTML attachment was scrubbed... URL: From joe at settoplinux.org Sun May 9 00:01:37 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 08 May 2010 18:01:37 -0400 Subject: [coreboot] [commit] r5533 - in trunk/src/mainboard: . wyse wyse/s50 In-Reply-To: <4BE5DE3C.8040909@settoplinux.org> References: <4BE5DE3C.8040909@settoplinux.org> Message-ID: <4BE5DF41.3070806@settoplinux.org> On 05/08/2010 05:57 PM, Joseph Smith wrote: > On 05/08/2010 05:50 PM, repository service wrote: >> Author: stepan >> Date: Sat May 8 23:50:31 2010 >> New Revision: 5533 >> URL: https://tracker.coreboot.org/trac/coreboot/changeset/5533 >> >> Log: >> Add the Wyse S50 thin client to Coreboot. >> Signed-off-by: Nils Jacobs >> Acked-by: Stefan Reinauer >> > Sweet! Wyse S30 will be coming soon too! > Is the: The error after rev5471 was "hda: lost interrupt" fixed? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From svn at coreboot.org Sun May 9 00:02:55 2010 From: svn at coreboot.org (repository service) Date: Sun, 09 May 2010 00:02:55 +0200 Subject: [coreboot] [commit] r5534 - in trunk/src/mainboard: arima/hdama ibm/e325 iwill/dk8s2 iwill/dk8x newisys/khepri Message-ID: Author: stepan Date: Sun May 9 00:02:54 2010 New Revision: 5534 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5534 Log: autoprobe apic cluster and application processors on K8 systems (fixes #18) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/mainboard/arima/hdama/devicetree.cb trunk/src/mainboard/ibm/e325/devicetree.cb trunk/src/mainboard/iwill/dk8s2/devicetree.cb trunk/src/mainboard/iwill/dk8x/devicetree.cb trunk/src/mainboard/newisys/khepri/devicetree.cb Modified: trunk/src/mainboard/arima/hdama/devicetree.cb ============================================================================== --- trunk/src/mainboard/arima/hdama/devicetree.cb Sat May 8 23:50:31 2010 (r5533) +++ trunk/src/mainboard/arima/hdama/devicetree.cb Sun May 9 00:02:54 2010 (r5534) @@ -180,14 +180,6 @@ device pci 18.2 on end device pci 18.3 on end end # chip northbridge/amd/amdk8 - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end end end Modified: trunk/src/mainboard/ibm/e325/devicetree.cb ============================================================================== --- trunk/src/mainboard/ibm/e325/devicetree.cb Sat May 8 23:50:31 2010 (r5533) +++ trunk/src/mainboard/ibm/e325/devicetree.cb Sun May 9 00:02:54 2010 (r5534) @@ -1,4 +1,9 @@ chip northbridge/amd/amdk8/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on end # LDT 0 @@ -60,22 +65,6 @@ device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - chip cpu/amd/socket_940 - device lapic 1 on end - end end end Modified: trunk/src/mainboard/iwill/dk8s2/devicetree.cb ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/devicetree.cb Sat May 8 23:50:31 2010 (r5533) +++ trunk/src/mainboard/iwill/dk8s2/devicetree.cb Sun May 9 00:02:54 2010 (r5534) @@ -1,4 +1,9 @@ chip northbridge/amd/amdk8/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # LDT 0 @@ -68,22 +73,6 @@ device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - chip cpu/amd/socket_940 - device lapic 1 on end - end end end Modified: trunk/src/mainboard/iwill/dk8x/devicetree.cb ============================================================================== --- trunk/src/mainboard/iwill/dk8x/devicetree.cb Sat May 8 23:50:31 2010 (r5533) +++ trunk/src/mainboard/iwill/dk8x/devicetree.cb Sun May 9 00:02:54 2010 (r5534) @@ -1,4 +1,9 @@ chip northbridge/amd/amdk8/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge @@ -47,22 +52,6 @@ device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - chip cpu/amd/socket_940 - device lapic 1 on end - end end end Modified: trunk/src/mainboard/newisys/khepri/devicetree.cb ============================================================================== --- trunk/src/mainboard/newisys/khepri/devicetree.cb Sat May 8 23:50:31 2010 (r5533) +++ trunk/src/mainboard/newisys/khepri/devicetree.cb Sun May 9 00:02:54 2010 (r5534) @@ -3,9 +3,6 @@ chip cpu/amd/socket_940 device lapic 0 on end end - chip cpu/amd/socket_940 - device lapic 1 on end - end end device pci_domain 0 on @@ -79,14 +76,6 @@ device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end end end From njacobs8 at hetnet.nl Sat May 8 23:59:52 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sat, 8 May 2010 23:59:52 +0200 Subject: [coreboot] [PATCH] improve realmode api Message-ID: <201005082359.52850.njacobs8@hetnet.nl> Hi Stefan, After trying all VSA`s i could find on the net back in last December, no one was working. So i hacked up my own. Attached a log from rev5470. Thanks,Nils. -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot142.log Type: text/x-log Size: 42478 bytes Desc: not available URL: From svn at coreboot.org Sun May 9 00:12:43 2010 From: svn at coreboot.org (coreboot) Date: Sat, 08 May 2010 22:12:43 -0000 Subject: [coreboot] #18: autoprobe apic cluster and application processors on K8 systems In-Reply-To: <042.3b6a74bac1755b1786072950302df3e4@coreboot.org> References: <042.3b6a74bac1755b1786072950302df3e4@coreboot.org> Message-ID: <051.e22727a2f06ee9ccbaccab53ac74d3dd@coreboot.org> #18: autoprobe apic cluster and application processors on K8 systems -------------------------+-------------------------------------------------- Reporter: stepan | Owner: oxygene Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: K8, cleanup Dependencies: | Patchstatus: patch needs review -------------------------+-------------------------------------------------- Comment(by stepan): cleanup-lapics.diff applied as r5534. -- Ticket URL: coreboot From njacobs8 at hetnet.nl Sun May 9 00:11:56 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sun, 9 May 2010 00:11:56 +0200 Subject: [coreboot] GX2 problems Message-ID: <201005090011.56345.njacobs8@hetnet.nl> Op zondag 9 mei 2010 00:00:22 schreef u: x0000FFFFFFFF0000ULL; // Enable reads for C0000-FFFFF > > setShadow(shadowSettings); > > } > > What's this doing? > > Is it potentially dangerous for other systems? > I was strugling with memory regions and saw this in the LX code. From njacobs8 at hetnet.nl Sun May 9 00:24:51 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sun, 9 May 2010 00:24:51 +0200 Subject: [coreboot] [commit] r5533 - in trunk/src/mainboard: . wyse wyse/s50 Message-ID: <201005090024.51546.njacobs8@hetnet.nl> >Author: stepan >Date: Sat May 8 23:50:31 2010 >New Revision: 5533 >URL: https://tracker.coreboot.org/trac/coreboot/changeset/5533 >Log: >Add the Wyse S50 thin client to Coreboot. Thanks for committing my board. Now i don`t have to hand adjust my patches for every revision. Since this patchset i have changed the memmory region setup to match the LX boards. I wil send a patch for that later. Thanks,Nils. From anders at jenbo.dk Sun May 9 00:27:03 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sun, 09 May 2010 00:27:03 +0200 Subject: [coreboot] PATCH: superiotool dump it8671f Message-ID: <1273357623.3508.2.camel@anders-laptop> Add registers for the it8671f chip. Signed-off-by: Anders Jenbo --- Anders Jenbo -------------- next part -------------- A non-text attachment was scrubbed... Name: superiotool-it8671f-dump.patch Type: text/x-patch Size: 1849 bytes Desc: not available URL: From stepan at coresystems.de Sun May 9 00:31:49 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 09 May 2010 00:31:49 +0200 Subject: [coreboot] [PATCH] improve realmode api In-Reply-To: <201005082359.52850.njacobs8@hetnet.nl> References: <201005082359.52850.njacobs8@hetnet.nl> Message-ID: <4BE5E655.8010902@coresystems.de> On 5/8/10 11:59 PM, Nils wrote: > Hi Stefan, > After trying all VSA`s i could find on the net back in > last December, no one was working. > So i hacked up my own. > How? From r.marek at assembler.cz Sun May 9 00:33:50 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Sun, 09 May 2010 00:33:50 +0200 Subject: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114) In-Reply-To: <665f02730557c26a7d0472538ec8d828.squirrel@www.boonen.name> References: <9fcf30ec4fe94654bd26b1ac9822bf75.squirrel@www.boonen.name> <074aeb78763ef5fb4e896f43a334b2f4.squirrel@www.boonen.name> <665f02730557c26a7d0472538ec8d828.squirrel@www.boonen.name> Message-ID: <4BE5E6CE.6040600@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, The sil3114 chip has a class code set to something else then IDE by strap resistor. It took me long time to figure out that this chip is otherwise IDE compatible ;) Try attached patch for coreboot which reprograms it back to IDE mode ;) It should start to work - booting from FILO and from Seabios. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvl5s0ACgkQ3J9wPJqZRNU8fwCg0ImG+JeZyuIpAjBB0OQBxu32 OP0AnjzRNyz6DRdLHLnyfAS+wseQn6a3 =Mc1w -----END PGP SIGNATURE----- -------------- next part -------------- A non-text attachment was scrubbed... Name: fix_sil.patch Type: text/x-diff Size: 1571 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: fix_sil.patch.sig Type: application/octet-stream Size: 72 bytes Desc: not available URL: From joe at settoplinux.org Sun May 9 00:34:07 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 08 May 2010 18:34:07 -0400 Subject: [coreboot] PATCH: superiotool dump it8671f In-Reply-To: <1273357623.3508.2.camel@anders-laptop> References: <1273357623.3508.2.camel@anders-laptop> Message-ID: <4BE5E6DF.2010800@settoplinux.org> On 05/08/2010 06:27 PM, Anders Jenbo wrote: > Add registers for the it8671f chip. > > Signed-off-by: Anders Jenbo Acked-by: Joseph Smith -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From anders at jenbo.dk Sun May 9 00:41:57 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sun, 09 May 2010 00:41:57 +0200 Subject: [coreboot] PATCH: IT8671F Select CLKIN Message-ID: <1273358517.3508.5.camel@anders-laptop> Split up the function to allow selecting the CLKIN speed, and possibly other individual configurations in the future. Signed-off-by: Anders Jenbo --- Anders Jenbo -------------- next part -------------- A non-text attachment was scrubbed... Name: it8671f-select-mhz.patch Type: text/x-patch Size: 2850 bytes Desc: not available URL: From r.marek at assembler.cz Sun May 9 00:48:20 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Sun, 09 May 2010 00:48:20 +0200 Subject: [coreboot] PATCH: IT8671F Select CLKIN In-Reply-To: <1273358517.3508.5.camel@anders-laptop> References: <1273358517.3508.5.camel@anders-laptop> Message-ID: <4BE5EA34.6000301@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, Couple of issues to fix: > Index: src/superio/ite/it8671f/it8671f_early_serial.c > =================================================================== > --- src/superio/ite/it8671f/it8671f_early_serial.c (revision 5531) > +++ src/superio/ite/it8671f/it8671f_early_serial.c (working copy) > @@ -53,12 +53,11 @@ > outb(value, SIO_DATA); > } > > -/* Enable the peripheral devices on the IT8671F Super I/O chip. */ > -static void it8671f_enable_serial(device_t dev, unsigned iobase) > +static void it8671f_enter_conf(void) > { > uint8_t i; > > - /* (1) Enter the configuration state (MB PnP mode). */ > + /* Enter the configuration state (MB PnP mode). */ > > /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ > /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ > @@ -74,20 +73,27 @@ > outb(init_values[i], SIO_BASE); > } > > - /* (2) Modify the data of configuration registers. */ > - > /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), > PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */ ^^^ this is not stuff for enable function. move it to enable serial where it was please. > it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); > +} > > +static void it8671f_exit_conf(void) > +{ > + /* Exit the configuration state (MB PnP mode). */ > + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); > +} > + > +void it8671f_48mhz_clkin(void) > +{ > + /* Select 48MHz CLKIN (24MHz default)*/ > + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x40); > +} > + > +/* Enable the peripheral devices on the IT8671F Super I/O chip. */ > +static void it8671f_enable_serial(device_t dev, unsigned iobase) > +{ you need to do call the it8671f_enter_conf(); here > /* Enable serial port(s). */ > it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */ > it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */ > - > - /* Select 24MHz CLKIN (clear bit 6) and clear software suspend > - mode (clear bit 0). */ > - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00); > - > - /* (3) Exit the configuration state (MB PnP mode). */ > - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); You need to call the it8671f_exit_conf(); here > } > Index: src/mainboard/soyo/sy-6ba-plus-iii/romstage.c > =================================================================== > --- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c (revision 5531) > +++ src/mainboard/soyo/sy-6ba-plus-iii/romstage.c (working copy) > @@ -53,7 +53,9 @@ > if (bist == 0) > early_mtrr_init(); > > + it8671f_enter_conf(); > it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); > + it8671f_exit_conf(); and not here > uart_init(); > console_init(); > report_bist_failure(bist); > Index: src/mainboard/gigabyte/ga-6bxc/romstage.c > =================================================================== > --- src/mainboard/gigabyte/ga-6bxc/romstage.c (revision 5531) > +++ src/mainboard/gigabyte/ga-6bxc/romstage.c (working copy) > @@ -53,7 +53,9 @@ > if (bist == 0) > early_mtrr_init(); > > + it8671f_enter_conf(); > it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); > + it8671f_exit_conf(); same here > uart_init(); > console_init(); > report_bist_failure(bist); > > Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvl6jQACgkQ3J9wPJqZRNWD+QCgqH8tzFQZMvsAc/iUUf65hqwk OG8An28IYhB72RaMTtQ2tMCFqsaMmHki =x2EW -----END PGP SIGNATURE----- From njacobs8 at hetnet.nl Sun May 9 00:52:40 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sun, 9 May 2010 00:52:40 +0200 Subject: [coreboot] Warnings In-Reply-To: <4BE5E781.1060402@coresystems.de> References: <201005010134.50557.njacobs8@hetnet.nl> <4BE5E781.1060402@coresystems.de> Message-ID: <201005090052.40942.njacobs8@hetnet.nl> Op zondag 9 mei 2010 00:36:49 schreef u: > On 5/1/10 1:34 AM, Nils wrote: > > Hi Stefan, > > First of all thanks for the great improvements in Geode (GX2). > > > > On 4/30/10 7:50 PM, Stefan Reinauer wrote: > >> src/northbridge/amd/gx2/chipsetinit.c:271: warning: suggest > >> parentheses around '-' inside '<<' > > > > This would need help from someone with a GX2 (or willing to check out > > the data sheets ;-) > > > > I would be happy if i could be of any help with this, I have a GX2 board > > i can test on. > > Can you test the following two patches: > > Index: northbridge/amd/gx2/chipsetinit.c > =================================================================== > --- northbridge/amd/gx2/chipsetinit.c (revision 5532) > +++ northbridge/amd/gx2/chipsetinit.c (working copy) > @@ -268,7 +268,7 @@ > if ((msr.lo&0xff) == 0x11) > return; > > - totalmem = sizeram() << 20 - 1; > + totalmem = (sizeram() << 20) - 1; > totalmem >>= 12; > totalmem = ~totalmem; > totalmem &= 0xfffff; > > > and this one > > Index: northbridge/amd/gx2/chipsetinit.c > =================================================================== > --- northbridge/amd/gx2/chipsetinit.c (revision 5532) > +++ northbridge/amd/gx2/chipsetinit.c (working copy) > @@ -268,7 +268,7 @@ > if ((msr.lo&0xff) == 0x11) > return; > > - totalmem = sizeram() << 20 - 1; > + totalmem = sizeram() << (20 - 1); > totalmem >>= 12; > totalmem = ~totalmem; > totalmem &= 0xfffff; > > > and see if any of them causes a failure? > > It would seem the first patch is correct and the second is not, but i am > not sure. > > > I saw your discussion about the warning before and it inspired me to > > dedicate my spare free time to again update my working rev5446 patches to > > current trunk. > > But unfortunately i can`t get it to work anymore on rev5120 and some > > other rev`s i tried. > > (Linux errors out with: "hda: lost interrupt") > > I will send the details in a separate mail. > > We do need to make sure we know the exact revision that broke this. > > Stefan > Yes, i wil test that next time i find some time for hobby, now i`m of to bed. On what revision would you like me to test? Nils. From stepan at coresystems.de Sun May 9 00:53:32 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 09 May 2010 00:53:32 +0200 Subject: [coreboot] [PATCH] improve realmode api In-Reply-To: <201005090046.34912.njacobs8@hetnet.nl> References: <201005090046.34912.njacobs8@hetnet.nl> Message-ID: <4BE5EB6C.40408@coresystems.de> On 5/9/10 12:46 AM, Nils wrote: > I brought back the GX2 code in to the code at: > svn://coreboot.org/vsa/trunk/gplvsa2 > The biggest chunk of code doesn`t affect the LX code. > The resulting LX image is binary compatible with the old one. > But a few lines have to be selected for GX2 only. > I wanted to invetigate how to do that and send a patch, > but i haven`t had time. > I am focusing on the board till now. > > Thanks,Nils. > > Jordan, do you happen to know where we can find a known good vsa image for GX2? -------------- next part -------------- An HTML attachment was scrubbed... URL: From stepan at coresystems.de Sun May 9 00:54:36 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 09 May 2010 00:54:36 +0200 Subject: [coreboot] Warnings In-Reply-To: <201005090052.40942.njacobs8@hetnet.nl> References: <201005010134.50557.njacobs8@hetnet.nl> <4BE5E781.1060402@coresystems.de> <201005090052.40942.njacobs8@hetnet.nl> Message-ID: <4BE5EBAC.4090506@coresystems.de> On 5/9/10 12:52 AM, Nils wrote: > Op zondag 9 mei 2010 00:36:49 schreef u: > >> On 5/1/10 1:34 AM, Nils wrote: >> >>> Hi Stefan, >>> First of all thanks for the great improvements in Geode (GX2). >>> >>> On 4/30/10 7:50 PM, Stefan Reinauer wrote: >>> >>>> src/northbridge/amd/gx2/chipsetinit.c:271: warning: suggest >>>> parentheses around '-' inside '<<' >>>> >>> This would need help from someone with a GX2 (or willing to check out >>> the data sheets ;-) >>> >>> I would be happy if i could be of any help with this, I have a GX2 board >>> i can test on. >>> >> Can you test the following two patches: >> >> Index: northbridge/amd/gx2/chipsetinit.c >> =================================================================== >> --- northbridge/amd/gx2/chipsetinit.c (revision 5532) >> +++ northbridge/amd/gx2/chipsetinit.c (working copy) >> @@ -268,7 +268,7 @@ >> if ((msr.lo&0xff) == 0x11) >> return; >> >> - totalmem = sizeram() << 20 - 1; >> + totalmem = (sizeram() << 20) - 1; >> totalmem >>= 12; >> totalmem = ~totalmem; >> totalmem &= 0xfffff; >> >> >> and this one >> >> Index: northbridge/amd/gx2/chipsetinit.c >> =================================================================== >> --- northbridge/amd/gx2/chipsetinit.c (revision 5532) >> +++ northbridge/amd/gx2/chipsetinit.c (working copy) >> @@ -268,7 +268,7 @@ >> if ((msr.lo&0xff) == 0x11) >> return; >> >> - totalmem = sizeram() << 20 - 1; >> + totalmem = sizeram() << (20 - 1); >> totalmem >>= 12; >> totalmem = ~totalmem; >> totalmem &= 0xfffff; >> >> >> and see if any of them causes a failure? >> >> It would seem the first patch is correct and the second is not, but i am >> not sure. >> >> >>> I saw your discussion about the warning before and it inspired me to >>> dedicate my spare free time to again update my working rev5446 patches to >>> current trunk. >>> But unfortunately i can`t get it to work anymore on rev5120 and some >>> other rev`s i tried. >>> (Linux errors out with: "hda: lost interrupt") >>> I will send the details in a separate mail. >>> >> We do need to make sure we know the exact revision that broke this. >> >> Stefan >> >> > Yes, i wil test that next time i find some time for hobby, > now i`m of to bed. > On what revision would you like me to test? > Possibly a working one. 5470 or so. From njacobs8 at hetnet.nl Sun May 9 00:46:34 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sun, 9 May 2010 00:46:34 +0200 Subject: [coreboot] [PATCH] improve realmode api Message-ID: <201005090046.34912.njacobs8@hetnet.nl> I brought back the GX2 code in to the code at: svn://coreboot.org/vsa/trunk/gplvsa2 The biggest chunk of code doesn`t affect the LX code. The resulting LX image is binary compatible with the old one. But a few lines have to be selected for GX2 only. I wanted to invetigate how to do that and send a patch, but i haven`t had time. I am focusing on the board till now. Thanks,Nils. From njacobs8 at hetnet.nl Sun May 9 00:57:55 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sun, 9 May 2010 00:57:55 +0200 Subject: [coreboot] [PATCH] improve realmode api Message-ID: <201005090057.55451.njacobs8@hetnet.nl> Op zondag 9 mei 2010 00:41:06 schreef u: > > Attached a log from rev5470. > > cool thanks... > could you send one for 5471 too, please? > Here you go, attached. Nils. -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot145.log Type: text/x-log Size: 39468 bytes Desc: not available URL: From anders at jenbo.dk Sun May 9 01:24:11 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sun, 09 May 2010 01:24:11 +0200 Subject: [coreboot] PATCH: superiotool dump it8671f In-Reply-To: <4BE5E6DF.2010800@settoplinux.org> References: <1273357623.3508.2.camel@anders-laptop> <4BE5E6DF.2010800@settoplinux.org> Message-ID: <1273361051.3508.6.camel@anders-laptop> Heres a sample of it's output -Anders l?r, 08 05 2010 kl. 18:34 -0400, skrev Joseph Smith: > On 05/08/2010 06:27 PM, Anders Jenbo wrote: > > Add registers for the it8671f chip. > > > > Signed-off-by: Anders Jenbo > Acked-by: Joseph Smith > -------------- next part -------------- superiotool r5507 Found ITE IT8671F/IT8687R (id=0x8681, rev=0x1) at 0x370 Register dump: idx 00 01 02 03 04 05 06 07 20 21 22 23 24 25 26 2e 2f val 00 00 00 00 ff 01 01 02 86 81 01 6f 00 00 00 00 00 def NA NA NA NA NA NA 00 NA 86 81 00 00 00 00 00 00 00 LDN 0x00 (Floppy disk controller) idx 30 31 60 61 70 71 74 f0 val 00 00 03 f0 06 02 02 00 def 00 00 03 f0 06 02 02 00 LDN 0x01 (COM1) idx 30 31 60 61 70 71 f0 val 01 00 03 f8 04 02 00 def 00 00 03 f8 04 02 00 LDN 0x02 (COM2) idx 30 31 60 61 62 63 70 71 72 73 74 75 f0 f1 val 01 00 02 f8 00 00 03 02 00 00 04 04 00 00 def 00 00 02 f8 03 00 03 02 0a 02 00 01 00 00 LDN 0x03 (Parallel port) idx 30 31 60 61 62 63 70 71 74 f0 val 00 00 03 78 07 78 07 02 04 03 def 00 00 01 78 07 78 07 02 03 03 LDN 0x04 (APC) idx 30 f0 f1 f2 f4 f5 f6 val 00 d1 01 10 20 00 00 def 00 00 00 00 00 00 NA LDN 0x05 (Keyboard) idx 30 31 60 61 62 63 70 71 f0 val 01 00 00 60 00 64 01 02 00 def 01 00 00 60 00 64 01 02 00 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO and Alternative function) idx 60 61 62 63 64 65 66 67 68 69 70 71 72 73 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff e0 e1 e2 e3 e4 val 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 def 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From svn at coreboot.org Sun May 9 01:28:33 2010 From: svn at coreboot.org (repository service) Date: Sun, 09 May 2010 01:28:33 +0200 Subject: [coreboot] [commit] r5535 - trunk/util/superiotool Message-ID: Author: linux_junkie Date: Sun May 9 01:28:33 2010 New Revision: 5535 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5535 Log: Add registers for the it8671f chip. Signed-off-by: Anders Jenbo Acked-by: Joseph Smith Modified: trunk/util/superiotool/ite.c Modified: trunk/util/superiotool/ite.c ============================================================================== --- trunk/util/superiotool/ite.c Sun May 9 00:02:54 2010 (r5534) +++ trunk/util/superiotool/ite.c Sun May 9 01:28:33 2010 (r5535) @@ -69,6 +69,33 @@ {0x8673, "IT8673F", { {EOT}}}, {0x8681, "IT8671F/IT8687R", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x2E,0x2F,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,0x00,NANA,0x86,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x0, "Floppy disk controller", + {0x30,0x31,0x60,0x61,0x70,0x71,0x74,0xF0,EOT}, + {0x00,0x00,0x03,0xF0,0x06,0x02,0x02,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x31,0x60,0x61,0x70,0x71,0xF0,EOT}, + {0x00,0x00,0x03,0xF8,0x04,0x02,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0x72,0x73,0x74,0x75,0xF0,0xF1,EOT}, + {0x00,0x00,0x02,0xF8,0x03,0x00,0x03,0x02,0x0A,0x02,0x00,0x01,0x00,0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0xF0,EOT}, + {0x00,0x00,0x01,0x78,0x07,0x78,0x07,0x02,0x03,0x03,EOT}}, + {0x4, "APC", + {0x30,0xF0,0xF1,0xF2,0xF4,0xF5,0xF6,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,NANA,EOT}}, + {0x5, "Keyboard", + {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0xF0,EOT}, + {0x01,0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x00,EOT}}, + {0x6, "Mouse", + {0x30,0x70,0x71,0xF0,EOT}, + {0x00,0x0C,0x02,0x00,EOT}}, + {0x7, "GPIO and Alternative function", + {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x70,0x71,0x72,0x73,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF,0xE0,0xE1,0xE2,0xE3,0xE4,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {EOT}}}, {0x8701, "IT8703F", { {NOLDN, NULL, From joe at settoplinux.org Sun May 9 01:30:24 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 08 May 2010 19:30:24 -0400 Subject: [coreboot] PATCH: superiotool dump it8671f In-Reply-To: <1273361051.3508.6.camel@anders-laptop> References: <1273357623.3508.2.camel@anders-laptop> <4BE5E6DF.2010800@settoplinux.org> <1273361051.3508.6.camel@anders-laptop> Message-ID: <4BE5F410.6020603@settoplinux.org> On 05/08/2010 07:24 PM, Anders Jenbo wrote: > Heres a sample of it's output > > -Anders > > l?r, 08 05 2010 kl. 18:34 -0400, skrev Joseph Smith: >> On 05/08/2010 06:27 PM, Anders Jenbo wrote: >>> Add registers for the it8671f chip. >>> >>> Signed-off-by: Anders Jenbo >> Acked-by: Joseph Smith >> > r5535, please add to wiki: http://www.coreboot.org/Superiotool -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From stepan at coresystems.de Sun May 9 01:46:37 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 09 May 2010 01:46:37 +0200 Subject: [coreboot] [PATCH] improve realmode api In-Reply-To: <201005090057.55451.njacobs8@hetnet.nl> References: <201005090057.55451.njacobs8@hetnet.nl> Message-ID: <4BE5F7DD.1050603@coresystems.de> On 5/9/10 12:57 AM, Nils wrote: > Op zondag 9 mei 2010 00:41:06 schreef u: > >>> Attached a log from rev5470. >>> >> cool thanks... >> could you send one for 5471 too, please? >> >> Due to a bug in the code there were two functions called chipsetinit() and coreboot was using the wrong one but should be using the right one now. However, the "new" one is broken... src/northbridge/amd/gx2/chipsetinit.c (broken) vs src/southbridge/amd/cs5536/cs5536.c (apparently working) From anders at jenbo.dk Sun May 9 01:49:21 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sun, 09 May 2010 01:49:21 +0200 Subject: [coreboot] PATCH: IT8671F Select CLKIN In-Reply-To: <4BE5EA34.6000301@assembler.cz> References: <1273358517.3508.5.camel@anders-laptop> <4BE5EA34.6000301@assembler.cz> Message-ID: <1273362561.3508.7.camel@anders-laptop> Ok done. -Anders s?n, 09 05 2010 kl. 00:48 +0200, skrev Rudolf Marek: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > Couple of issues to fix: > > > > Index: src/superio/ite/it8671f/it8671f_early_serial.c > > =================================================================== > > --- src/superio/ite/it8671f/it8671f_early_serial.c (revision 5531) > > +++ src/superio/ite/it8671f/it8671f_early_serial.c (working copy) > > @@ -53,12 +53,11 @@ > > outb(value, SIO_DATA); > > } > > > > -/* Enable the peripheral devices on the IT8671F Super I/O chip. */ > > -static void it8671f_enable_serial(device_t dev, unsigned iobase) > > +static void it8671f_enter_conf(void) > > { > > uint8_t i; > > > > - /* (1) Enter the configuration state (MB PnP mode). */ > > + /* Enter the configuration state (MB PnP mode). */ > > > > /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ > > /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ > > @@ -74,20 +73,27 @@ > > outb(init_values[i], SIO_BASE); > > } > > > > - /* (2) Modify the data of configuration registers. */ > > - > > /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), > > PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */ > > > ^^^ this is not stuff for enable function. move it to enable serial where it was > please. > > > it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); > > +} > > > > +static void it8671f_exit_conf(void) > > +{ > > + /* Exit the configuration state (MB PnP mode). */ > > + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); > > +} > > + > > +void it8671f_48mhz_clkin(void) > > +{ > > + /* Select 48MHz CLKIN (24MHz default)*/ > > + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x40); > > +} > > + > > +/* Enable the peripheral devices on the IT8671F Super I/O chip. */ > > +static void it8671f_enable_serial(device_t dev, unsigned iobase) > > +{ > > you need to do call the it8671f_enter_conf(); here > > /* Enable serial port(s). */ > > it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */ > > it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */ > > - > > - /* Select 24MHz CLKIN (clear bit 6) and clear software suspend > > - mode (clear bit 0). */ > > - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00); > > - > > - /* (3) Exit the configuration state (MB PnP mode). */ > > - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); > > You need to call the it8671f_exit_conf(); here > > > } > > Index: src/mainboard/soyo/sy-6ba-plus-iii/romstage.c > > =================================================================== > > --- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c (revision 5531) > > +++ src/mainboard/soyo/sy-6ba-plus-iii/romstage.c (working copy) > > @@ -53,7 +53,9 @@ > > if (bist == 0) > > early_mtrr_init(); > > > > + it8671f_enter_conf(); > > it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); > > + it8671f_exit_conf(); > and not here > > uart_init(); > > console_init(); > > report_bist_failure(bist); > > Index: src/mainboard/gigabyte/ga-6bxc/romstage.c > > =================================================================== > > --- src/mainboard/gigabyte/ga-6bxc/romstage.c (revision 5531) > > +++ src/mainboard/gigabyte/ga-6bxc/romstage.c (working copy) > > @@ -53,7 +53,9 @@ > > if (bist == 0) > > early_mtrr_init(); > > > > + it8671f_enter_conf(); > > it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); > > + it8671f_exit_conf(); > > same here > > > uart_init(); > > console_init(); > > report_bist_failure(bist); > > > > > > Thanks, > Rudolf > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.10 (GNU/Linux) > Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org > > iEYEARECAAYFAkvl6jQACgkQ3J9wPJqZRNWD+QCgqH8tzFQZMvsAc/iUUf65hqwk > OG8An28IYhB72RaMTtQ2tMCFqsaMmHki > =x2EW > -----END PGP SIGNATURE----- -------------- next part -------------- A non-text attachment was scrubbed... Name: it8671f-select-mhz2.patch Type: text/x-patch Size: 2023 bytes Desc: not available URL: From anders at jenbo.dk Sun May 9 01:51:27 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sun, 09 May 2010 01:51:27 +0200 Subject: [coreboot] PATCH: superiotool dump it8671f In-Reply-To: <4BE5F410.6020603@settoplinux.org> References: <1273357623.3508.2.camel@anders-laptop> <4BE5E6DF.2010800@settoplinux.org> <1273361051.3508.6.camel@anders-laptop> <4BE5F410.6020603@settoplinux.org> Message-ID: <1273362687.3508.8.camel@anders-laptop> Done, thanks for the link. -Anders l?r, 08 05 2010 kl. 19:30 -0400, skrev Joseph Smith: > On 05/08/2010 07:24 PM, Anders Jenbo wrote: > > Heres a sample of it's output > > > > -Anders > > > > l?r, 08 05 2010 kl. 18:34 -0400, skrev Joseph Smith: > >> On 05/08/2010 06:27 PM, Anders Jenbo wrote: > >>> Add registers for the it8671f chip. > >>> > >>> Signed-off-by: Anders Jenbo > >> Acked-by: Joseph Smith > >> > > > > r5535, please add to wiki: > > http://www.coreboot.org/Superiotool > From anders at jenbo.dk Sun May 9 01:55:39 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sun, 09 May 2010 01:55:39 +0200 Subject: [coreboot] [CoreBoot] PATCH: Support for Gigabyte GA-6BXE Message-ID: <1273362939.3508.10.camel@anders-laptop> Adds support for Gigabyte GA-6BXE. Signed-off-by: Anders Jenbo --- Anders Jenbo -------------- next part -------------- A non-text attachment was scrubbed... Name: ga-6bxe.patch Type: text/x-patch Size: 11959 bytes Desc: not available URL: From anders at jenbo.dk Sun May 9 02:40:40 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sun, 09 May 2010 02:40:40 +0200 Subject: [coreboot] [CoreBoot] PATCH: Support for Gigabyte GA-6BXE In-Reply-To: <1273362939.3508.10.camel@anders-laptop> References: <1273362939.3508.10.camel@anders-laptop> Message-ID: <1273365640.13598.0.camel@anders-laptop> Quick update to add my name to the headers -------------- next part -------------- A non-text attachment was scrubbed... Name: ga-6bxe.patch Type: text/x-patch Size: 11951 bytes Desc: not available URL: From buurin at gmail.com Sun May 9 07:33:02 2010 From: buurin at gmail.com (Keith Hui) Date: Sun, 9 May 2010 01:33:02 -0400 Subject: [coreboot] [RFC] Getting CAR to work on P6 family; Port SECC P6 L2 cache initialization code to where? Message-ID: Hi all, this is a RFC. While Joseph, Idwer and myself convened on IRC for the past two days trying to get CAR working on the P6 family of CPUs, we found that - The Intel CAR code works as is on Tualatin cores, L2 cache fully enabled The same code works for me on a Katmai, but only L1 cache is enabled This code does not boot at all for Idwer who also has a Katmai, and has stumped everyone We need to port a piece of long code from coreboot v1 that initializes the off-chip L2 cache found on Klamath/Deschutes/Katmai CPUs. They are respectively models 63x,65x and 67x. 16k of L1 is enough. We're only using 4k for CAR on Intel. It was written in C. I looked at the OEM BIOS for P2B-LS and L2 is initialized from the "inner BIOS", like the RAM stage of coreboot, when RAM is fully up and running. This means this can go into model_6xx_init(), which is prefereable as I just need to make enough adjustments to make it work again. Joseph OTOH suggests that I should port this code into cache_as_ram.inc which is much earlier, actually before motherboard romstage. This code is assembly, meaning I'll need to port this thing back to assembly. Question is: Where should I port this code to? CPU driver, or cache_as_ram.inc? A patch to separate model 67x from model 6xx will soon come, either from me or Joseph. A similar one could be done for 65x and 63x. I do not have 66x Celerons to test so I cannot ascertain if this special attention will be needed for them. Thanks Keith From joe at settoplinux.org Sun May 9 07:45:24 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sun, 09 May 2010 01:45:24 -0400 Subject: [coreboot] [RFC] Getting CAR to work on P6 family; Port SECC P6 L2 cache initialization code to where? In-Reply-To: References: Message-ID: <4BE64BF4.1070102@settoplinux.org> On 05/09/2010 01:33 AM, Keith Hui wrote: > Hi all, this is a RFC. > > While Joseph, Idwer and myself convened on IRC for the past two days > trying to get CAR working on the P6 family of CPUs, we found that - > > The Intel CAR code works as is on Tualatin cores, L2 cache fully enabled > The same code works for me on a Katmai, but only L1 cache is enabled > This code does not boot at all for Idwer who also has a Katmai, and > has stumped everyone > We need to port a piece of long code from coreboot v1 that initializes > the off-chip L2 cache found on Klamath/Deschutes/Katmai CPUs. > They are respectively models 63x,65x and 67x. > 16k of L1 is enough. We're only using 4k for CAR on Intel. > > It was written in C. I looked at the OEM BIOS for P2B-LS and L2 is > initialized from the "inner BIOS", like the RAM stage of coreboot, > when RAM is fully up and running. This means this can go into > model_6xx_init(), which is prefereable as I just need to make enough > adjustments to make it work again. > > Joseph OTOH suggests that I should port this code into > cache_as_ram.inc which is much earlier, actually before motherboard > romstage. This code is assembly, meaning I'll need to port this thing > back to assembly. > > Question is: Where should I port this code to? CPU driver, or cache_as_ram.inc? > Hmm, I guess it does not really need to be done in cache_as_ram if the 16k is large enough to get things going. So if it would be easier I would suggest early in model_6*x_init(). Especially if the vendor bios enables it post raminit. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From anders at jenbo.dk Sun May 9 09:19:23 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Sun, 09 May 2010 09:19:23 +0200 Subject: [coreboot] =?utf-8?q?_=5BRFC=5D_Getting_CAR_to_work_on_P6_family?= =?utf-8?q?=3B_Port_SECC_P6_L2_cache_=09initialization_code_to_wher?= =?utf-8?q?e=3F?= Message-ID: I have two Deschutes and a 1ghz PIII that I would happily test your code on. Mvh Anders ----- Reply message ----- Fra: "Joseph Smith" Dato: s?n., maj 9, 2010 07:45 Emne: [coreboot] [RFC] Getting CAR to work on P6 family; Port SECC P6 L2 cache initialization code to where? Til: "Keith Hui" Cc: On 05/09/2010 01:33 AM, Keith Hui wrote: > Hi all, this is a RFC. > > While Joseph, Idwer and myself convened on IRC for the past two days > trying to get CAR working on the P6 family of CPUs, we found that - > > The Intel CAR code works as is on Tualatin cores, L2 cache fully enabled > The same code works for me on a Katmai, but only L1 cache is enabled > This code does not boot at all for Idwer who also has a Katmai, and > has stumped everyone > We need to port a piece of long code from coreboot v1 that initializes > the off-chip L2 cache found on Klamath/Deschutes/Katmai CPUs. > They are respectively models 63x,65x and 67x. > 16k of L1 is enough. We're only using 4k for CAR on Intel. > > It was written in C. I looked at the OEM BIOS for P2B-LS and L2 is > initialized from the "inner BIOS", like the RAM stage of coreboot, > when RAM is fully up and running. This means this can go into > model_6xx_init(), which is prefereable as I just need to make enough > adjustments to make it work again. > > Joseph OTOH suggests that I should port this code into > cache_as_ram.inc which is much earlier, actually before motherboard > romstage. This code is assembly, meaning I'll need to port this thing > back to assembly. > > Question is: Where should I port this code to? CPU driver, or cache_as_ram.inc? > Hmm, I guess it does not really need to be done in cache_as_ram if the 16k is large enough to get things going. So if it would be easier I would suggest early in model_6*x_init(). Especially if the vendor bios enables it post raminit. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From r.marek at assembler.cz Sun May 9 11:14:37 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Sun, 09 May 2010 11:14:37 +0200 Subject: [coreboot] PATCH: IT8671F Select CLKIN In-Reply-To: <1273362561.3508.7.camel@anders-laptop> References: <1273358517.3508.5.camel@anders-laptop> <4BE5EA34.6000301@assembler.cz> <1273362561.3508.7.camel@anders-laptop> Message-ID: <4BE67CFD.7090901@assembler.cz> Hi almost OK, You deleted it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00); I would not trust the documentation if this is really a default value. Please return it back. Otherwise if this is fixed: Acked-by: Rudolf Marek Thanks, Rudolf Dne 9.5.2010 01:49, Anders Jenbo napsal(a): > Ok done. > > -Anders > > s?n, 09 05 2010 kl. 00:48 +0200, skrev Rudolf Marek: >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> Hi, >> >> Couple of issues to fix: >> >> >>> Index: src/superio/ite/it8671f/it8671f_early_serial.c >>> =================================================================== >>> --- src/superio/ite/it8671f/it8671f_early_serial.c (revision 5531) >>> +++ src/superio/ite/it8671f/it8671f_early_serial.c (working copy) >>> @@ -53,12 +53,11 @@ >>> outb(value, SIO_DATA); >>> } >>> >>> -/* Enable the peripheral devices on the IT8671F Super I/O chip. */ >>> -static void it8671f_enable_serial(device_t dev, unsigned iobase) >>> +static void it8671f_enter_conf(void) >>> { >>> uint8_t i; >>> >>> - /* (1) Enter the configuration state (MB PnP mode). */ >>> + /* Enter the configuration state (MB PnP mode). */ >>> >>> /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ >>> /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ >>> @@ -74,20 +73,27 @@ >>> outb(init_values[i], SIO_BASE); >>> } >>> >>> - /* (2) Modify the data of configuration registers. */ >>> - >>> /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), >>> PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */ >> >> >> ^^^ this is not stuff for enable function. move it to enable serial where it was >> please. >> >>> it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); >>> +} >>> >>> +static void it8671f_exit_conf(void) >>> +{ >>> + /* Exit the configuration state (MB PnP mode). */ >>> + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); >>> +} >>> + >>> +void it8671f_48mhz_clkin(void) >>> +{ >>> + /* Select 48MHz CLKIN (24MHz default)*/ >>> + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x40); >>> +} >>> + >>> +/* Enable the peripheral devices on the IT8671F Super I/O chip. */ >>> +static void it8671f_enable_serial(device_t dev, unsigned iobase) >>> +{ >> >> you need to do call the it8671f_enter_conf(); here >>> /* Enable serial port(s). */ >>> it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */ >>> it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */ >>> - >>> - /* Select 24MHz CLKIN (clear bit 6) and clear software suspend >>> - mode (clear bit 0). */ >>> - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00); >>> - >>> - /* (3) Exit the configuration state (MB PnP mode). */ >>> - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); >> >> You need to call the it8671f_exit_conf(); here >> >>> } >>> Index: src/mainboard/soyo/sy-6ba-plus-iii/romstage.c >>> =================================================================== >>> --- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c (revision 5531) >>> +++ src/mainboard/soyo/sy-6ba-plus-iii/romstage.c (working copy) >>> @@ -53,7 +53,9 @@ >>> if (bist == 0) >>> early_mtrr_init(); >>> >>> + it8671f_enter_conf(); >>> it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); >>> + it8671f_exit_conf(); >> and not here >>> uart_init(); >>> console_init(); >>> report_bist_failure(bist); >>> Index: src/mainboard/gigabyte/ga-6bxc/romstage.c >>> =================================================================== >>> --- src/mainboard/gigabyte/ga-6bxc/romstage.c (revision 5531) >>> +++ src/mainboard/gigabyte/ga-6bxc/romstage.c (working copy) >>> @@ -53,7 +53,9 @@ >>> if (bist == 0) >>> early_mtrr_init(); >>> >>> + it8671f_enter_conf(); >>> it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); >>> + it8671f_exit_conf(); >> >> same here >> >>> uart_init(); >>> console_init(); >>> report_bist_failure(bist); >>> >>> >> >> Thanks, >> Rudolf >> -----BEGIN PGP SIGNATURE----- >> Version: GnuPG v1.4.10 (GNU/Linux) >> Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org >> >> iEYEARECAAYFAkvl6jQACgkQ3J9wPJqZRNWD+QCgqH8tzFQZMvsAc/iUUf65hqwk >> OG8An28IYhB72RaMTtQ2tMCFqsaMmHki >> =x2EW >> -----END PGP SIGNATURE----- > From stepan at coresystems.de Sun May 9 12:58:16 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 09 May 2010 12:58:16 +0200 Subject: [coreboot] [RFC] Getting CAR to work on P6 family; Port SECC P6 L2 cache initialization code to where? In-Reply-To: References: Message-ID: <4BE69548.1030009@coresystems.de> On 5/9/10 7:33 AM, Keith Hui wrote: > Joseph OTOH suggests that I should port this code into > cache_as_ram.inc which is much earlier, actually before motherboard > romstage. This code is assembly, meaning I'll need to port this thing > back to assembly. > > Question is: Where should I port this code to? CPU driver, or cache_as_ram.inc? > > If there are no penalties for putting it in the CPU driver, put it there. If you run without cache until the CPU driver is executed otherwise (and that makes a measurable difference of several ms) you might want to do this earlier Stefan From stepan at coresystems.de Sun May 9 14:56:17 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 09 May 2010 14:56:17 +0200 Subject: [coreboot] PATCH: IT8671F Select CLKIN In-Reply-To: <1273362561.3508.7.camel@anders-laptop> References: <1273358517.3508.5.camel@anders-laptop> <4BE5EA34.6000301@assembler.cz> <1273362561.3508.7.camel@anders-laptop> Message-ID: <4BE6B0F1.5040507@coresystems.de> On 5/9/10 1:49 AM, Anders Jenbo wrote: > Ok done. > > -Anders > Please send a Signed-off-by: so we can commit this.... http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure -------------- next part -------------- An HTML attachment was scrubbed... URL: From patrick at georgi-clan.de Sun May 9 15:47:05 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sun, 09 May 2010 15:47:05 +0200 Subject: [coreboot] [CoreBoot] PATCH: Support for Gigabyte GA-6BXE In-Reply-To: <1273365640.13598.0.camel@anders-laptop> References: <1273362939.3508.10.camel@anders-laptop> <1273365640.13598.0.camel@anders-laptop> Message-ID: <4BE6BCD9.40702@georgi-clan.de> Am 09.05.2010 02:40, schrieb Anders Jenbo: > Quick update to add my name to the headers How much of Uwe's code (which you seemed to have based the board on) is left? Patrick From anders at jenbo.dk Sun May 9 16:01:26 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Sun, 09 May 2010 16:01:26 +0200 Subject: [coreboot] =?utf-8?q?Indtast_Bcc__PATCH=3A_IT8671F_Select_CLKIN?= Message-ID: Signed-off-by: Anders Jenbo Mvh Anders ----- Reply message ----- Fra: "Stefan Reinauer" Dato: s?n., maj 9, 2010 14:56 Emne: [coreboot] PATCH: IT8671F Select CLKIN Til: "Anders Jenbo" Cc: "Rudolf Marek" , -------------- next part -------------- An HTML attachment was scrubbed... URL: From anders at jenbo.dk Sun May 9 16:07:45 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Sun, 09 May 2010 16:07:45 +0200 Subject: [coreboot] =?utf-8?q?Indtast_Bcc__=5BCoreBoot=5D_PATCH=3A_Support?= =?utf-8?q?_for_Gigabyte_GA-6BXE?= Message-ID: Most of it. IRQ tables is just me, tree is mostly me, the rest is mostly his. People keept telling me to put my name there so I did. Mvh Anders ----- Reply message ----- Fra: "Patrick Georgi" Dato: s?n., maj 9, 2010 15:47 Emne: [coreboot] [CoreBoot] PATCH: Support for Gigabyte GA-6BXE Til: Am 09.05.2010 02:40, schrieb Anders Jenbo: > Quick update to add my name to the headers How much of Uwe's code (which you seemed to have based the board on) is left? Patrick -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From anton.kochkov at gmail.com Sun May 9 16:14:54 2010 From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=) Date: Sun, 9 May 2010 18:14:54 +0400 Subject: [coreboot] superiotool: Begin implementation support to IT8512/IT8513 In-Reply-To: References: Message-ID: Begin implementation support to IT8512/IT8513 Signed-off-by: Anton Kochkov --- -------------- next part -------------- A non-text attachment was scrubbed... Name: it8512.diff Type: text/x-diff Size: 529 bytes Desc: not available URL: From svn at coreboot.org Sun May 9 17:15:09 2010 From: svn at coreboot.org (repository service) Date: Sun, 09 May 2010 17:15:09 +0200 Subject: [coreboot] [commit] r5536 - trunk/src/northbridge/intel/i82830 Message-ID: Author: stepan Date: Sun May 9 17:15:08 2010 New Revision: 5536 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5536 Log: i82830: fix debugging output and clarify bracketing Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/northbridge/intel/i82830/i82830_smihandler.c Modified: trunk/src/northbridge/intel/i82830/i82830_smihandler.c ============================================================================== --- trunk/src/northbridge/intel/i82830/i82830_smihandler.c Sun May 9 01:28:33 2010 (r5535) +++ trunk/src/northbridge/intel/i82830/i82830_smihandler.c Sun May 9 17:15:08 2010 (r5536) @@ -258,11 +258,11 @@ if (getobj->objnum == count) { printk(BIOS_DEBUG, "| |- len = %x\n", len); memcpy((void *)(getobj->buffer + OBJ_OFFSET), - ((char *)mbi_header) + 0x20 , (len > getobj->buflen ? getobj->buflen : len)); + ((char *)mbi_header) + 0x20 , (len > getobj->buflen) ? getobj->buflen : len); getobj->banner.retsts = MSH_OK; #ifdef DEBUG_SMI_I82830 - dump(banner_id, sizeof(getobj)); + dump(banner_id, sizeof(*getobj)); dump(getobj->buffer + OBJ_OFFSET, len); #endif break; From svn at coreboot.org Sun May 9 17:30:46 2010 From: svn at coreboot.org (repository service) Date: Sun, 09 May 2010 17:30:46 +0200 Subject: [coreboot] [commit] r5537 - trunk/util/superiotool Message-ID: Author: stepan Date: Sun May 9 17:30:45 2010 New Revision: 5537 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5537 Log: Begin implementation support to IT8512/IT8513 Signed-off-by: Anton Kochkov Acked-by: Stefan Reinauer Modified: trunk/util/superiotool/ite.c Modified: trunk/util/superiotool/ite.c ============================================================================== --- trunk/util/superiotool/ite.c Sun May 9 17:15:08 2010 (r5536) +++ trunk/util/superiotool/ite.c Sun May 9 17:30:45 2010 (r5537) @@ -33,6 +33,10 @@ {EOT}}}, {0x8511, "IT8511E/TE/G", { {EOT}}}, + {0x8512, "IT8512E/F/G", { + {EOT}}}, + {0x8513, "IT8513E/F/G", { + {EOT}}}, {0x8661, "IT8661F/IT8770F", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x20,0x21,0x22, From anders at jenbo.dk Sun May 9 21:33:36 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sun, 9 May 2010 21:33:36 +0200 Subject: [coreboot] Indtast Bcc Dell Optiplex GX1 support Message-ID: <9DACE9BF-521B-4ECF-A6D5-2C214315CA72@jenbo.dk> Serial Cable is only for debug output. USB should work fine. Start by downloding the source. $ svn co svn://coreboot.org/coreboot/trunk coreboot go to the src/mainboard/tyan folder and copy the folder for the s1846, it has all the same chips as your board so we will use it to base your board of. You should call yor dolder src/mainboard/dell/optiplex_gx1. Edit src/ mainboard/dell/Kconfig, add 'source "src/mainboard/delloptiplex_gx1/ Kconfig"' abouve the existing source line. Open the Kconfig in yor board folder and change all the references to your board. Run lspci -tvnn and make sure that your devicetree.cb seams to match it's output. Open mainboard.c and correct the board name. Go back to the coreboot folder type make menuconfig, select your board and make any other adjustments that you think is needed or would like. Exit and save, run make. Hopfully it will compile a 256kb rom image. We also need to know somthing about your rom chip so run flashrom and post the out put her. Next I'll try to help you saifly flash your board and posibly improve the support for your board. Mvh Anders Den 09/05/2010 kl. 18.27 skrev Cooper Harrison : > Who cares about ACPI! :D I don't have ECC memory either. Can I use > an USB keyboard as input or do I have to get a serial cable? > > On Thu, May 6, 2010 at 11:24 AM, anders at jenbo.dk > wrote: > Hi > > As you are the only one who has this board you will have to do a bit > of the work your self. But I would be glad to help you, I recently > ported coreboot to a 440bx board, Ubuntu boots on it so Debians > should work fine. > There is still a few limitations in the support for this chip. No L2 > cache no ecc memory, only sdram and no ACPI. > > Also it looks like you won't have support for any legacy I/O (ps2 > keyboard pc speaker) > > You could of ofcourse fix all this by reading the docs an coding a > bit of C :) > > -Anders > > ----- Reply message ----- > Fra: "Cooper Harrison" > Dato: tor., maj 6, 2010 14:04 > Emne: [coreboot] Dell Optiplex GX1 support > Til: > > By looking at all the supported hardware, it looks like it should > work at a minimum amount. It has an Intel 440BX, an Intel PIIX4e and > a NSC (formerly National) PC87309. Will I be able to boot Debian and > if not, how soon until whoever is working on it estimates they will > have it at a working status? I am just wondering as I think it would > be cool to have it on my computer. > -- > Cooper > > > > -- > Cooper -------------- next part -------------- An HTML attachment was scrubbed... URL: From njacobs8 at hetnet.nl Sun May 9 22:10:27 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sun, 9 May 2010 22:10:27 +0200 Subject: [coreboot] Warnings Message-ID: <201005092210.27469.njacobs8@hetnet.nl> Op zondag 9 mei 2010 00:36:49 schreef u: > On 5/1/10 1:34 AM, Nils wrote: > > Hi Stefan, > > First of all thanks for the great improvements in Geode (GX2). > > > > On 4/30/10 7:50 PM, Stefan Reinauer wrote: > >> src/northbridge/amd/gx2/chipsetinit.c:271: warning: suggest > >> parentheses around '-' inside '<<' > > > > This would need help from someone with a GX2 (or willing to check out > > the data sheets ;-) > > > > I would be happy if i could be of any help with this, I have a GX2 board > > i can test on. > > Can you test the following two patches: > > Index: northbridge/amd/gx2/chipsetinit.c > =================================================================== > --- northbridge/amd/gx2/chipsetinit.c (revision 5532) > +++ northbridge/amd/gx2/chipsetinit.c (working copy) > @@ -268,7 +268,7 @@ > if ((msr.lo&0xff) == 0x11) > return; > > - totalmem = sizeram() << 20 - 1; > + totalmem = (sizeram() << 20) - 1; > totalmem >>= 12; > totalmem = ~totalmem; > totalmem &= 0xfffff; > > > and this one > > Index: northbridge/amd/gx2/chipsetinit.c > =================================================================== > --- northbridge/amd/gx2/chipsetinit.c (revision 5532) > +++ northbridge/amd/gx2/chipsetinit.c (working copy) > @@ -268,7 +268,7 @@ > if ((msr.lo&0xff) == 0x11) > return; > > - totalmem = sizeram() << 20 - 1; > + totalmem = sizeram() << (20 - 1); > totalmem >>= 12; > totalmem = ~totalmem; > totalmem &= 0xfffff; > > > and see if any of them causes a failure? > > It would seem the first patch is correct and the second is not, but i am > not sure. I tested both patches on rev 5470 and didn`t see a difference, both seem to work fine. See attached patches. > > > I saw your discussion about the warning before and it inspired me to > > dedicate my spare free time to again update my working rev5446 patches to > > current trunk. > > But unfortunately i can`t get it to work anymore on rev5120 and some > > other rev`s i tried. > > (Linux errors out with: "hda: lost interrupt") > > I will send the details in a separate mail. > > We do need to make sure we know the exact revision that broke this. > > Stefan > The exact revision that broke vsa was 5471. Thanks,Nils. -------------- next part -------------- A non-text attachment was scrubbed... Name: (sizeram() << 20) - 1.log Type: text/x-log Size: 42395 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: sizeram() << (20 - 1).log Type: text/x-log Size: 42478 bytes Desc: not available URL: From patrick at georgi-clan.de Sun May 9 22:47:15 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sun, 09 May 2010 22:47:15 +0200 Subject: [coreboot] [PATCH]Move includes to files that actually use them Message-ID: <4BE71F53.8030104@georgi-clan.de> Hi, as part of the ongoing quest to clean up the code to make it easier to use and adapt, I added a couple of #include statements to AMD code, so it gains some self-sufficiency. These includes are necessary because those files use their definitions. It only works so far because the romstage carefully includes files in the right order so everything is included before it's needed by another file. This change, and similar ones that will come after it, allow us to simplify the romstage.c of boards that use these chipsets (ie. Fam10 for this patch), making it easier to support new boards. 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Name: 20100509-2-amd-includes URL: From stepan at coresystems.de Sun May 9 23:04:44 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 09 May 2010 23:04:44 +0200 Subject: [coreboot] [PATCH]Move includes to files that actually use them In-Reply-To: <4BE71F53.8030104@georgi-clan.de> References: <4BE71F53.8030104@georgi-clan.de> Message-ID: <4BE7236C.9000906@coresystems.de> On 5/9/10 10:47 PM, Patrick Georgi wrote: > Hi, > > as part of the ongoing quest to clean up the code to make it easier to > use and adapt, I added a couple of #include statements to AMD code, so > it gains some self-sufficiency. > > These includes are necessary because those files use their definitions. > It only works so far because the romstage carefully includes files in > the right order so everything is included before it's needed by another > file. > > This change, and similar ones that will come after it, allow us to > simplify the romstage.c of boards that use these chipsets (ie. Fam10 for > this patch), making it easier to support new boards. > > Signed-off-by: Patrick Georgi > Acked-by: Stefan Reinauer From stefan.reinauer at coresystems.de Sun May 9 23:08:14 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Sun, 09 May 2010 23:08:14 +0200 Subject: [coreboot] [PATCH]Include headers instead of sources in romstage, part 2/many In-Reply-To: <4BE5DC2E.7080109@georgi-clan.de> References: <4BE5D0BE.7070006@georgi-clan.de> <4BE5DA50.4080401@coresystems.de> <4BE5DC2E.7080109@georgi-clan.de> Message-ID: <4BE7243E.2080901@coresystems.de> On 5/8/10 11:48 PM, Patrick Georgi wrote: > Am 08.05.2010 23:40, schrieb Stefan Reinauer: > >> On 5/8/10 10:59 PM, Patrick Georgi wrote: >> >>> Index: src/include/lib.h >>> =================================================================== >>> --- src/include/lib.h (Revision 5532) >>> +++ src/include/lib.h (Arbeitskopie) >>> @@ -49,5 +49,7 @@ >>> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); >>> #endif >>> >>> +#else /* __ROMCC__ */ >>> +#include "pc80/serial.c" >>> #endif /* __ROMCC__ */ >>> #endif /* __LIB_H__ */ >>> >>> >> It looks like only console/console.h is actually using these functions, >> so I think it should rather be included in console/console.h than in lib.h? >> > Oops, that was the older version of the patch (this won't even compile > on all boards) > > See attached patch instead > > Signed-off-by: Patrick Georgi > Acked-by: Stefan Reinauer -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From svn at coreboot.org Sun May 9 23:09:58 2010 From: svn at coreboot.org (repository service) Date: Sun, 09 May 2010 23:09:58 +0200 Subject: [coreboot] [commit] r5538 - in trunk/src: include/console mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit/be6-ii_v2_0 mainboard/advantech/pcm-5820 mainboard/amd/rumba mainboard/asi/mb_5bl... Message-ID: Author: oxygene Date: Sun May 9 23:09:58 2010 New Revision: 5538 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5538 Log: Remove pc80/serial.c includes in ROMCC boards and include it centrally in console/console.h instead. Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Modified: trunk/src/include/console/console.h trunk/src/mainboard/a-trend/atc-6220/romstage.c trunk/src/mainboard/a-trend/atc-6240/romstage.c trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c trunk/src/mainboard/advantech/pcm-5820/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/asi/mb_5blgp/romstage.c trunk/src/mainboard/asi/mb_5blmp/romstage.c trunk/src/mainboard/asus/mew-am/romstage.c trunk/src/mainboard/asus/mew-vm/romstage.c trunk/src/mainboard/asus/p2b-d/romstage.c trunk/src/mainboard/asus/p2b-ds/romstage.c trunk/src/mainboard/asus/p2b-f/romstage.c trunk/src/mainboard/asus/p2b-ls/romstage.c trunk/src/mainboard/asus/p2b/romstage.c trunk/src/mainboard/asus/p3b-f/romstage.c trunk/src/mainboard/axus/tc320/romstage.c trunk/src/mainboard/azza/pt-6ibd/romstage.c trunk/src/mainboard/bcom/winnet100/romstage.c trunk/src/mainboard/biostar/m6tba/romstage.c trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/digitallogic/msm586seg/romstage.c trunk/src/mainboard/eaglelion/5bcm/romstage.c trunk/src/mainboard/emulation/qemu-x86/romstage.c trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c trunk/src/mainboard/iei/juki-511p/romstage.c trunk/src/mainboard/iei/nova4899r/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/mitac/6513wu/romstage.c trunk/src/mainboard/msi/ms6119/romstage.c trunk/src/mainboard/msi/ms6147/romstage.c trunk/src/mainboard/msi/ms6156/romstage.c trunk/src/mainboard/msi/ms6178/romstage.c trunk/src/mainboard/nec/powermate2000/romstage.c trunk/src/mainboard/nokia/ip530/romstage.c trunk/src/mainboard/olpc/btest/romstage.c trunk/src/mainboard/olpc/rev_a/romstage.c trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/technologic/ts5300/romstage.c trunk/src/mainboard/televideo/tc7020/romstage.c trunk/src/mainboard/tyan/s1846/romstage.c trunk/src/mainboard/via/epia-m/romstage.c trunk/src/mainboard/via/epia-n/romstage.c trunk/src/mainboard/via/epia/romstage.c trunk/src/mainboard/wyse/s50/romstage.c Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/include/console/console.h Sun May 9 23:09:58 2010 (r5538) @@ -129,6 +129,7 @@ #define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) #else +#include /* __ROMCC__ */ static void __console_tx_byte(unsigned char byte) Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/a-trend/atc-6220/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/a-trend/atc-6240/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/a-trend/atc-6240/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/advantech/pcm-5820/romstage.c ============================================================================== --- trunk/src/mainboard/advantech/pcm-5820/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/advantech/pcm-5820/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -23,7 +23,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/amd/rumba/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -4,7 +4,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/asi/mb_5blgp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blgp/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asi/mb_5blgp/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -23,7 +23,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/asi/mb_5blmp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blmp/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asi/mb_5blmp/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/asus/mew-am/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-am/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/mew-am/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" Modified: trunk/src/mainboard/asus/mew-vm/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-vm/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/mew-vm/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" Modified: trunk/src/mainboard/asus/p2b-d/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p2b-d/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -26,7 +26,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p2b-ds/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -26,7 +26,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/asus/p2b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-f/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p2b-f/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/asus/p2b/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p2b/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/asus/p3b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p3b-f/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p3b-f/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/axus/tc320/romstage.c ============================================================================== --- trunk/src/mainboard/axus/tc320/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/axus/tc320/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/azza/pt-6ibd/romstage.c ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/azza/pt-6ibd/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/bcom/winnet100/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnet100/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/bcom/winnet100/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/biostar/m6tba/romstage.c ============================================================================== --- trunk/src/mainboard/biostar/m6tba/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/biostar/m6tba/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/dell/s1850/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -5,7 +5,6 @@ #include #include #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c ============================================================================== --- trunk/src/mainboard/eaglelion/5bcm/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/eaglelion/5bcm/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -5,7 +5,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" //#include "southbridge/intel/i440bx/i440bx_early_smbus.c" Modified: trunk/src/mainboard/emulation/qemu-x86/romstage.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/emulation/qemu-x86/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "pc80/udelay_io.c" #include "lib/delay.c" Modified: trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" /* TODO: It's a PC87364 actually! */ Modified: trunk/src/mainboard/iei/juki-511p/romstage.c ============================================================================== --- trunk/src/mainboard/iei/juki-511p/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/iei/juki-511p/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "superio/winbond/w83977f/w83977f_early_serial.c" Modified: trunk/src/mainboard/iei/nova4899r/romstage.c ============================================================================== --- trunk/src/mainboard/iei/nova4899r/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/iei/nova4899r/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/intel/jarrell/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -27,7 +27,6 @@ #include #include #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/intel/truxton/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -27,7 +27,6 @@ #include #include #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include "pc80/udelay_io.c" #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -8,7 +8,6 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -4,7 +4,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/mitac/6513wu/romstage.c ============================================================================== --- trunk/src/mainboard/mitac/6513wu/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/mitac/6513wu/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" Modified: trunk/src/mainboard/msi/ms6119/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6119/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/msi/ms6119/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/msi/ms6147/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6147/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/msi/ms6147/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/msi/ms6156/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6156/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/msi/ms6156/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/msi/ms6178/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/msi/ms6178/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/nec/powermate2000/romstage.c ============================================================================== --- trunk/src/mainboard/nec/powermate2000/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/nec/powermate2000/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" Modified: trunk/src/mainboard/nokia/ip530/romstage.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/nokia/ip530/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/olpc/btest/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/btest/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/olpc/btest/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -4,7 +4,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/olpc/rev_a/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/olpc/rev_a/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -4,7 +4,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/technologic/ts5300/romstage.c ============================================================================== --- trunk/src/mainboard/technologic/ts5300/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/technologic/ts5300/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -11,7 +11,6 @@ #include #include #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/televideo/tc7020/romstage.c ============================================================================== --- trunk/src/mainboard/televideo/tc7020/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/televideo/tc7020/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/tyan/s1846/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s1846/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/tyan/s1846/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/via/epia-m/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/via/epia-m/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -6,7 +6,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "northbridge/via/vt8623/raminit.h" Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/via/epia-n/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -26,7 +26,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "northbridge/via/cn400/raminit.h" Modified: trunk/src/mainboard/via/epia/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/via/epia/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -5,7 +5,6 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "northbridge/via/vt8601/raminit.h" Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/wyse/s50/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -4,15 +4,12 @@ #include #include #include -#include "pc80/serial.c" #include #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) - #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" From svn at coreboot.org Sun May 9 23:15:15 2010 From: svn at coreboot.org (repository service) Date: Sun, 09 May 2010 23:15:15 +0200 Subject: [coreboot] [commit] r5539 - in trunk/src: arch/i386/include cpu/amd/car cpu/amd/model_10xxx cpu/amd/quadcore include/cpu/amd northbridge/amd/amdht northbridge/amd/amdmct/mct superio/smsc/smscsuperio Message-ID: Author: oxygene Date: Sun May 9 23:15:13 2010 New Revision: 5539 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5539 Log: Move includes to where they are needed. This allows to simplify romstage.c files in mainboards. Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Modified: trunk/src/arch/i386/include/stddef.h trunk/src/cpu/amd/car/post_cache_as_ram.c trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/include/cpu/amd/model_10xxx_msr.h trunk/src/northbridge/amd/amdht/ht_wrapper.c trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Modified: trunk/src/arch/i386/include/stddef.h ============================================================================== --- trunk/src/arch/i386/include/stddef.h Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/arch/i386/include/stddef.h Sun May 9 23:15:13 2010 (r5539) @@ -8,7 +8,9 @@ typedef int wchar_t; typedef unsigned int wint_t; +#ifndef NULL #define NULL ((void *)0) +#endif #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c ============================================================================== --- trunk/src/cpu/amd/car/post_cache_as_ram.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/car/post_cache_as_ram.c Sun May 9 23:15:13 2010 (r5539) @@ -1,6 +1,7 @@ /* 2005.6 by yhlu * 2006.3 yhlu add copy data from CAR to ram */ +#include #include #include "cpu/amd/car/disable_cache_as_ram.c" Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Sun May 9 23:15:13 2010 (r5539) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include +#include /* * Default MSR and errata settings. Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Sun May 9 23:15:13 2010 (r5539) @@ -18,6 +18,12 @@ */ #include "defaults.h" +#include +#include +#include +#include +#include +#include //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef SET_FIDVID Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/quadcore/quadcore.c Sun May 9 23:15:13 2010 (r5539) @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #ifndef SET_NB_CFG_54 #define SET_NB_CFG_54 1 Modified: trunk/src/include/cpu/amd/model_10xxx_msr.h ============================================================================== --- trunk/src/include/cpu/amd/model_10xxx_msr.h Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/include/cpu/amd/model_10xxx_msr.h Sun May 9 23:15:13 2010 (r5539) @@ -20,6 +20,8 @@ #ifndef CPU_AMD_MODEL_10XXX_MSR_H #define CPU_AMD_MODEL_10XXX_MSR_H +#include + #define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f #define LS_CFG_MSR 0xC0011020 Modified: trunk/src/northbridge/amd/amdht/ht_wrapper.c ============================================================================== --- trunk/src/northbridge/amd/amdht/ht_wrapper.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/northbridge/amd/amdht/ht_wrapper.c Sun May 9 23:15:13 2010 (r5539) @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include +#include +#include /*---------------------------------------------------------------------------- * TYPEDEFS, DEFINITIONS AND MACROS Modified: trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c Sun May 9 23:15:13 2010 (r5539) @@ -19,6 +19,7 @@ #include "mct_d.h" +#include static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr); static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType); Modified: trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c ============================================================================== --- trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Sun May 9 23:15:13 2010 (r5539) @@ -19,6 +19,7 @@ */ #include +#include /* All known/supported SMSC Super I/Os have the same logical device IDs * for the serial ports (COM1, COM2). From joop_boonen at web.de Sun May 9 23:08:45 2010 From: joop_boonen at web.de (Joop Boonen) Date: Sun, 9 May 2010 23:08:45 +0200 Subject: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114) In-Reply-To: <4BE51D73.6030203@coresystems.de> References: <9fcf30ec4fe94654bd26b1ac9822bf75.squirrel@www.boonen.name> <074aeb78763ef5fb4e896f43a334b2f4.squirrel@www.boonen.name> <665f02730557c26a7d0472538ec8d828.squirrel@www.boonen.name> <4BE51D73.6030203@coresystems.de> Message-ID: On Sat, May 8, 2010 10:14 am, Stefan Reinauer wrote: > On 5/7/10 10:37 PM, Joop Boonen wrote: >> On Thu, May 6, 2010 11:56 am, Joop Boonen wrote: >> >>> On Thu, May 6, 2010 11:35 am, Joop Boonen wrote: >>> >>>> All, >>>> >>>> I have an issue with FILO the disk at ata-0 isn't seen. >>>> >>> >> I've been trying some more. I've used the old IDE in FILO. It now >> recognises the drive connected to the SIL3114. But still not the ATA >> drive. >> > Under PCI support, try enabling > [ ] Scan all PCI busses I've tried this already. Attached the session and the .config file. I still need to test with filo 0.5 > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- A non-text attachment was scrubbed... Name: session_20100509.log Type: text/x-log Size: 64987 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: .config Type: application/x-config Size: 1452 bytes Desc: not available URL: From svn at coreboot.org Sun May 9 23:44:53 2010 From: svn at coreboot.org (repository service) Date: Sun, 09 May 2010 23:44:53 +0200 Subject: [coreboot] [commit] r5540 - in trunk/src: arch/i386/include northbridge/amd/amdht Message-ID: Author: oxygene Date: Sun May 9 23:44:52 2010 New Revision: 5540 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5540 Log: Remove extra NULL #define in amdht code. The common one is enough. Trivial Signed-off-by: Patrick Georgi Acked-by: Patrick Georgi Modified: trunk/src/arch/i386/include/stddef.h trunk/src/northbridge/amd/amdht/porting.h Modified: trunk/src/arch/i386/include/stddef.h ============================================================================== --- trunk/src/arch/i386/include/stddef.h Sun May 9 23:15:13 2010 (r5539) +++ trunk/src/arch/i386/include/stddef.h Sun May 9 23:44:52 2010 (r5540) @@ -8,9 +8,7 @@ typedef int wchar_t; typedef unsigned int wint_t; -#ifndef NULL #define NULL ((void *)0) -#endif #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) Modified: trunk/src/northbridge/amd/amdht/porting.h ============================================================================== --- trunk/src/northbridge/amd/amdht/porting.h Sun May 9 23:15:13 2010 (r5539) +++ trunk/src/northbridge/amd/amdht/porting.h Sun May 9 23:44:52 2010 (r5540) @@ -77,10 +77,6 @@ void CALLCONV AmdCPUIDRead(uint32 Address, uint32 Regs[4]); void CALLCONV ErrorStop(uint32 Value); -#ifndef NULL -#define NULL ((void *) 0) -#endif - #define BYTESIZE 1 #define WORDSIZE 2 #define DWORDSIZE 4 From svn at coreboot.org Mon May 10 00:29:51 2010 From: svn at coreboot.org (coreboot) Date: Sun, 09 May 2010 22:29:51 -0000 Subject: [coreboot] #162: Move SYSTEM_TYPE to Kconfig Message-ID: <043.597d39f9c64761f08194d46ef312edec@coreboot.org> #162: Move SYSTEM_TYPE to Kconfig ----------------------------+----------------------------------------------- Reporter: oxygene | Owner: oxygene Type: enhancement | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- SYSTEM_TYPE is used to tell coreboot if the board is "server", "desktop" or "laptop". It's only used for AMD for now, but could also be used elsewhere to tweak configuration (and there's a flag in some table, maybe ACPI, that tells the OS about the system type, too). It's defined for some boards, there's a default defined somewhere in the code, that looks a lot like a good match for Kconfig. -- Ticket URL: coreboot From coop.rocks.123e at gmail.com Mon May 10 03:55:40 2010 From: coop.rocks.123e at gmail.com (Cooper Harrison) Date: Sun, 9 May 2010 21:55:40 -0400 Subject: [coreboot] Indtast Bcc Dell Optiplex GX1 support In-Reply-To: References: <9DACE9BF-521B-4ECF-A6D5-2C214315CA72@jenbo.dk> Message-ID: if I had access to the source code on this machine, I would. But, I forgot to save my modifications onto usb. lspci -tvnn: -[0000:00]-+-00.0 Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge [8086:7190] +-01.0-[0000:01]----00.0 ATI Technologies Inc 3D Rage Pro AGP 1X/2X [1002:4742] +-07.0 Intel Corporation 82371AB/EB/MB PIIX4 ISA [8086:7110] +-07.1 Intel Corporation 82371AB/EB/MB PIIX4 IDE [8086:7111] +-07.2 Intel Corporation 82371AB/EB/MB PIIX4 USB [8086:7112] +-07.3 Intel Corporation 82371AB/EB/MB PIIX4 ACPI [8086:7113] +-0d.0 Conexant HSF 56k HSFi Modem [14f1:2f00] \-11.0 3Com Corporation 3c905B 100BaseTX [Cyclone] [10b7:9055] lspci -vnn: 00:00.0 Host bridge [0600]: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge [8086:7190] (rev 03) Flags: bus master, medium devsel, latency 64 Memory at f4000000 (32-bit, prefetchable) [size=64M] Capabilities: [a0] AGP version 1.0 Kernel driver in use: agpgart-intel Kernel modules: intel-agp 00:01.0 PCI bridge [0604]: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge [8086:7191] (rev 03) (prog-if 00 [Normal decode]) Flags: bus master, 66MHz, medium devsel, latency 64 Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fc000000-feffffff Prefetchable memory behind bridge: f9000000-f9ffffff Kernel modules: shpchp 00:07.0 ISA bridge [0601]: Intel Corporation 82371AB/EB/MB PIIX4 ISA [8086:7110] (rev 02) Flags: bus master, medium devsel, latency 0 00:07.1 IDE interface [0101]: Intel Corporation 82371AB/EB/MB PIIX4 IDE [8086:7111] (rev 01) (prog-if 80 [Master]) Flags: bus master, medium devsel, latency 32 [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] I/O ports at ffa0 [size=16] Kernel driver in use: PIIX_IDE Kernel modules: piix 00:07.2 USB Controller [0c03]: Intel Corporation 82371AB/EB/MB PIIX4 USB [8086:7112] (rev 01) (prog-if 00 [UHCI]) Flags: bus master, medium devsel, latency 64, IRQ 11 I/O ports at dce0 [size=32] Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00:07.3 Bridge [0680]: Intel Corporation 82371AB/EB/MB PIIX4 ACPI [8086:7113] (rev 02) Flags: medium devsel, IRQ 9 Kernel modules: i2c-piix4 00:0d.0 Communication controller [0780]: Conexant HSF 56k HSFi Modem [14f1:2f00] (rev 01) Subsystem: Conexant Dynalink 56PMi [14f1:2004] Flags: bus master, medium devsel, latency 64, IRQ 10 Memory at ff000000 (32-bit, non-prefetchable) [size=64K] I/O ports at dcd8 [size=8] Capabilities: [40] Power Management version 2 00:11.0 Ethernet controller [0200]: 3Com Corporation 3c905B 100BaseTX [Cyclone] [10b7:9055] (rev 24) Subsystem: Dell 3C905B Fast Etherlink XL 10/100 [1028:0082] Flags: bus master, medium devsel, latency 64, IRQ 11 I/O ports at dc00 [size=128] Memory at ff010000 (32-bit, non-prefetchable) [size=128] Expansion ROM at fb000000 [disabled] [size=128K] Capabilities: [dc] Power Management version 1 Kernel driver in use: 3c59x Kernel modules: 3c59x 01:00.0 VGA compatible controller [0300]: ATI Technologies Inc 3D Rage Pro AGP 1X/2X [1002:4742] (rev 5c) (prog-if 00 [VGA controller]) Subsystem: Dell Optiplex GX1 Onboard Display Adapter [1028:4082] Flags: bus master, stepping, medium devsel, latency 64, IRQ 10 Memory at fd000000 (32-bit, non-prefetchable) [size=16M] I/O ports at ec00 [size=256] Memory at fcfff000 (32-bit, non-prefetchable) [size=4K] [virtual] Expansion ROM at f9000000 [disabled] [size=128K] Capabilities: [50] AGP version 1.0 Once again, thanks for helping me. On Sun, May 9, 2010 at 8:23 PM, Cooper Harrison wrote: > Is this good for the board Kconfig? > > config BOARD_DELL_OPTIPLEX_GX1 > bool "S1846 (Tsunami ATX)" > select ARCH_X86 > select CPU_INTEL_SLOT_1 > select NORTHBRIDGE_INTEL_I440BX > select SOUTHBRIDGE_INTEL_I82371EB > select SUPERIO_NSC_PC87309 > select ROMCC > select UDELAY_TSC > select BOARD_ROMSIZE_MB_2 > > config MAINBOARD_DIR > string > default dell/optiplex_gx1 > depends on BOARD_DELL_OPTIPLEX_GX1 > > config MAINBOARD_PART_NUMBER > string > default "DELLOPTGX1" > depends on BOARD_DELL_OPTIPLEX_GX1 > > config HAVE_OPTION_TABLE > bool > default n > depends on BOARD_DELL_OPTIPLEX_GX1 > > The board has a 2 mb rom, is that a problem? > > tree= > . > |-- Kconfig > |-- optiplex_gx1 > |-- Kconfig > |-- chip.h > |-- devicetree.cb > |-- mainboard.c > `-- romstage.c > > Will send the lspci -tvnn as soon as i have access to the machine. > > On Sun, May 9, 2010 at 3:33 PM, Anders Jenbo wrote: > >> Serial Cable is only for debug output. USB should work fine. >> >> Start by downloding the source. >> >> >> $ svn co svn://coreboot.org/coreboot/trunk coreboot >> >> go to the src/mainboard/tyan folder and copy the folder for the s1846, it >> has all the same chips as your board so we will use it to base your board >> of. >> You should call yor dolder src/mainboard/dell/optiplex_gx1. Edit src/mainboard/dell/Kconfig, >> add 'source "src/mainboard/delloptiplex_gx1/Kconfig"' abouve the existing >> source line. >> Open the Kconfig in yor board folder and change all the references to your >> board. >> Run lspci -tvnn and make sure that your devicetree.cb seams to match it's >> output. >> Open mainboard.c and correct the board name. >> >> Go back to the coreboot folder type make menuconfig, select your board and >> make any other adjustments that you think is needed or would like. >> Exit and save, run make. Hopfully it will compile a 256kb rom image. >> >> We also need to know somthing about your rom chip so run flashrom and post >> the out put her. >> >> Next I'll try to help you saifly flash your board and posibly improve the >> support for your board. >> >> Mvh Anders >> >> Den 09/05/2010 kl. 18.27 skrev Cooper Harrison < >> coop.rocks.123e at gmail.com>: >> >> Who cares about ACPI! :D I don't have ECC memory either. Can I use an USB >> keyboard as input or do I have to get a serial cable? >> >> On Thu, May 6, 2010 at 11:24 AM, >> anders at jenbo.dk < anders at jenbo.dk>wrote: >> >>> Hi >>> >>> As you are the only one who has this board you will have to do a bit of >>> the work your self. But I would be glad to help you, I recently ported >>> coreboot to a 440bx board, Ubuntu boots on it so Debians should work fine. >>> There is still a few limitations in the support for this chip. No L2 >>> cache no ecc memory, only sdram and no ACPI. >>> >>> Also it looks like you won't have support for any legacy I/O (ps2 >>> keyboard pc speaker) >>> >>> You could of ofcourse fix all this by reading the docs an coding a bit of >>> C :) >>> >>> -Anders >>> >>> ----- Reply message ----- >>> Fra: "Cooper Harrison" < >>> coop.rocks.123e at gmail.com> >>> Dato: tor., maj 6, 2010 14:04 >>> Emne: [coreboot] Dell Optiplex GX1 support >>> Til: < >>> coreboot at coreboot.org> >>> >>> By looking at all the supported hardware, it looks like it should work at >>> a minimum amount. It has an Intel 440BX, an Intel PIIX4e and a NSC (formerly >>> National) PC87309. Will I be able to boot Debian and if not, how soon until >>> whoever is working on it estimates they will have it at a working status? I >>> am just wondering as I think it would be cool to have it on my computer. >>> -- >>> Cooper >>> >> >> >> >> -- >> Cooper >> >> > > > -- > Cooper > -- Cooper -------------- next part -------------- An HTML attachment was scrubbed... URL: From coop.rocks.123e at gmail.com Mon May 10 02:23:28 2010 From: coop.rocks.123e at gmail.com (Cooper Harrison) Date: Sun, 9 May 2010 20:23:28 -0400 Subject: [coreboot] Indtast Bcc Dell Optiplex GX1 support In-Reply-To: <9DACE9BF-521B-4ECF-A6D5-2C214315CA72@jenbo.dk> References: <9DACE9BF-521B-4ECF-A6D5-2C214315CA72@jenbo.dk> Message-ID: Is this good for the board Kconfig? config BOARD_DELL_OPTIPLEX_GX1 bool "S1846 (Tsunami ATX)" select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_NSC_PC87309 select ROMCC select UDELAY_TSC select BOARD_ROMSIZE_MB_2 config MAINBOARD_DIR string default dell/optiplex_gx1 depends on BOARD_DELL_OPTIPLEX_GX1 config MAINBOARD_PART_NUMBER string default "DELLOPTGX1" depends on BOARD_DELL_OPTIPLEX_GX1 config HAVE_OPTION_TABLE bool default n depends on BOARD_DELL_OPTIPLEX_GX1 The board has a 2 mb rom, is that a problem? tree= . |-- Kconfig |-- optiplex_gx1 |-- Kconfig |-- chip.h |-- devicetree.cb |-- mainboard.c `-- romstage.c Will send the lspci -tvnn as soon as i have access to the machine. On Sun, May 9, 2010 at 3:33 PM, Anders Jenbo wrote: > Serial Cable is only for debug output. USB should work fine. > > Start by downloding the source. > > > $ svn co svn://coreboot.org/coreboot/trunk coreboot > > go to the src/mainboard/tyan folder and copy the folder for the s1846, it > has all the same chips as your board so we will use it to base your board > of. > You should call yor dolder src/mainboard/dell/optiplex_gx1. Edit src/mainboard/dell/Kconfig, > add 'source "src/mainboard/delloptiplex_gx1/Kconfig"' abouve the existing > source line. > Open the Kconfig in yor board folder and change all the references to your > board. > Run lspci -tvnn and make sure that your devicetree.cb seams to match it's > output. > Open mainboard.c and correct the board name. > > Go back to the coreboot folder type make menuconfig, select your board and > make any other adjustments that you think is needed or would like. > Exit and save, run make. Hopfully it will compile a 256kb rom image. > > We also need to know somthing about your rom chip so run flashrom and post > the out put her. > > Next I'll try to help you saifly flash your board and posibly improve the > support for your board. > > Mvh Anders > > Den 09/05/2010 kl. 18.27 skrev Cooper Harrison < > coop.rocks.123e at gmail.com>: > > Who cares about ACPI! :D I don't have ECC memory either. Can I use an USB > keyboard as input or do I have to get a serial cable? > > On Thu, May 6, 2010 at 11:24 AM, > anders at jenbo.dk < anders at jenbo.dk>wrote: > >> Hi >> >> As you are the only one who has this board you will have to do a bit of >> the work your self. But I would be glad to help you, I recently ported >> coreboot to a 440bx board, Ubuntu boots on it so Debians should work fine. >> There is still a few limitations in the support for this chip. No L2 cache >> no ecc memory, only sdram and no ACPI. >> >> Also it looks like you won't have support for any legacy I/O (ps2 keyboard >> pc speaker) >> >> You could of ofcourse fix all this by reading the docs an coding a bit of >> C :) >> >> -Anders >> >> ----- Reply message ----- >> Fra: "Cooper Harrison" < >> coop.rocks.123e at gmail.com> >> Dato: tor., maj 6, 2010 14:04 >> Emne: [coreboot] Dell Optiplex GX1 support >> Til: < >> coreboot at coreboot.org> >> >> By looking at all the supported hardware, it looks like it should work at >> a minimum amount. It has an Intel 440BX, an Intel PIIX4e and a NSC (formerly >> National) PC87309. Will I be able to boot Debian and if not, how soon until >> whoever is working on it estimates they will have it at a working status? I >> am just wondering as I think it would be cool to have it on my computer. >> -- >> Cooper >> > > > > -- > Cooper > > -- Cooper -------------- next part -------------- An HTML attachment was scrubbed... URL: From jordan at cosmicpenguin.net Mon May 10 05:06:30 2010 From: jordan at cosmicpenguin.net (Jordan Crouse) Date: Sun, 9 May 2010 21:06:30 -0600 Subject: [coreboot] [PATCH] improve realmode api In-Reply-To: <4BE5EB6C.40408@coresystems.de> References: <201005090046.34912.njacobs8@hetnet.nl> <4BE5EB6C.40408@coresystems.de> Message-ID: On Sat, May 8, 2010 at 4:53 PM, Stefan Reinauer wrote: > On 5/9/10 12:46 AM, Nils wrote: > > I brought back the GX2 code in to the code at: > svn://coreboot.org/vsa/trunk/gplvsa2 > The biggest chunk of code doesn`t affect the LX code. > The resulting LX image is binary compatible with the old one. > But a few lines have to be selected for GX2 only. > I wanted to invetigate how to do that and send a patch, > but i haven`t had time. > I am focusing on the board till now. > > Thanks,Nils. > > > > Jordan, > > do you happen to know where we can find a known good vsa image for GX2? I'm not even sure if one ever got released. Marc would know. Jordan From anders at jenbo.dk Mon May 10 10:23:12 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Mon, 10 May 2010 10:23:12 +0200 Subject: [coreboot] =?utf-8?q?Re__Dell_Optiplex_GX1_support?= Message-ID: You forgot to change bool "S1846 (Tsunami ATX)". 2 MB is not a problem but you should run flashrom to make sure. Mvh Anders ----- Reply message ----- Fra: "Cooper Harrison" Dato: man., maj 10, 2010 02:23 Emne: Indtast Bcc [coreboot] Dell Optiplex GX1 support Til: "Anders Jenbo" Cc: -------------- next part -------------- An HTML attachment was scrubbed... URL: From anders at jenbo.dk Mon May 10 17:07:10 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Mon, 10 May 2010 17:07:10 +0200 Subject: [coreboot] Indtast Bcc Dell Optiplex GX1 support In-Reply-To: References: <9DACE9BF-521B-4ECF-A6D5-2C214315CA72@jenbo.dk> Message-ID: <1273504030.12757.44.camel@anders-laptop> Your devicetree.cb seams fine, but i will need the output from superiotool to see if you have set it to the correct address. the output from $ cat /proc/tty/driver/serial would also be help full in identifying the serial port. the output form flashrom should solve the mystery about the size of you rom. both flashrom and superiotool should be avalible from the devian repository. -Anders s?n, 09 05 2010 kl. 21:55 -0400, skrev Cooper Harrison: > > -[0000:00]-+-00.0 Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host > bridge [8086:7190] > +-01.0-[0000:01]----00.0 ATI Technologies Inc 3D Rage Pro > AGP 1X/2X [1002:4742] > +-07.0 Intel Corporation 82371AB/EB/MB PIIX4 ISA > [8086:7110] > +-07.1 Intel Corporation 82371AB/EB/MB PIIX4 IDE > [8086:7111] > +-07.2 Intel Corporation 82371AB/EB/MB PIIX4 USB > [8086:7112] > +-07.3 Intel Corporation 82371AB/EB/MB PIIX4 ACPI > [8086:7113] > +-0d.0 Conexant HSF 56k HSFi Modem [14f1:2f00] > \-11.0 3Com Corporation 3c905B 100BaseTX [Cyclone] > [10b7:9055] > From anders at jenbo.dk Mon May 10 18:31:54 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Mon, 10 May 2010 18:31:54 +0200 Subject: [coreboot] Re Dell Optiplex GX1 support In-Reply-To: References: <4be7c277.041bdf0a.77fe.ffffccc4SMTPIN_ADDED@mx.google.com> Message-ID: <1273509114.12757.59.camel@anders-laptop> To improve the support a bit navigate to coreboot/util/getpir/ and run make, then run ./getpir (on the GX1), this will generate a irq_tables.c file. Copy it to your folder, and add the following to the first section of your Kconfig. select HAVE_PIRQ_TABLE Once you have done this you should be ready to compile CoreBoot and flash it on to your board. If the flashing fails or the compiled ROM doesn't work for your board could be unable to boot, so it is strongly recommended that you find or buy a similar ROM chip so that you have a working backup in case something goes wrong. -Anders From anders at jenbo.dk Mon May 10 16:44:05 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Mon, 10 May 2010 16:44:05 +0200 Subject: [coreboot] Re Dell Optiplex GX1 support In-Reply-To: References: <4be7c277.041bdf0a.77fe.ffffccc4SMTPIN_ADDED@mx.google.com> Message-ID: <1273502645.12757.25.camel@anders-laptop> Remember to reply to all so that the mail also ends up on the mailing list. I think it should be: bool "Optplex GX1" Also select BOARD_ROMSIZE_MB_2 should be select BOARD_ROMSIZE_KB_2048 Be aware that ROMs are often specified in bit's and not bytes, so if you have a 2Mb (mega bits) is is actually 256KB (kilo bytes), if that is the case it should be: select BOARD_ROMSIZE_KB_256 Witch is what all other 440BX boards seams to have. -Anders man, 10 05 2010 kl. 07:56 -0400, skrev Cooper Harrison: > > bool "Dell Optplex GX1 Mainboard" From mylesgw at gmail.com Mon May 10 21:24:43 2010 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 10 May 2010 13:24:43 -0600 Subject: [coreboot] [PATCH] resource maps Message-ID: I think there's too much duplication in the resource map code. resourcemaps.diff tries to address it by: Creating clear_resource_map() for k8 and fam10. This sets all the routing registers to a known state. Calling clear_resource_map() and then only setting the specific registers that are non-zero in board-specific code. Adding util.c for fam10, so that it can be customized for fam10. I didn't update all of the resourcemap.c files, yet. I wanted to see what the reaction would be. sublinks.diff marks that bit as not reserved for all fam10 boards, so that it can be cleared. Signed-off-by: Myles Watson Thanks, Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: resourcemaps.diff Type: text/x-patch Size: 55694 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: sublinks.diff Type: text/x-patch Size: 25071 bytes Desc: not available URL: From svn at coreboot.org Mon May 10 21:38:59 2010 From: svn at coreboot.org (repository service) Date: Mon, 10 May 2010 21:38:59 +0200 Subject: [coreboot] [commit] r5541 - in trunk/src/northbridge/amd: amdfam10 amdk8 Message-ID: Author: myles Date: Mon May 10 21:38:59 2010 New Revision: 5541 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5541 Log: High tables don't have to be on node 0 on K8. Make it less restrictive. Signed-off-by: Myles Watson Acked-by: Myles Watson Added: trunk/src/northbridge/amd/amdfam10/util.c (props changed) - copied unchanged from r5527, trunk/src/northbridge/amd/amdk8/util.c Modified: trunk/src/northbridge/amd/amdk8/northbridge.c Copied: trunk/src/northbridge/amd/amdfam10/util.c (from r5527, trunk/src/northbridge/amd/amdk8/util.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/northbridge/amd/amdfam10/util.c Mon May 10 21:38:59 2010 (r5541, copy of r5527, trunk/src/northbridge/amd/amdk8/util.c) @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Vincent Legoll + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +/* + * K8 northbridge utilities (dump routing registers). + * Designed to be called at any time. + * It can be called before RAM is set up by including this file. + * It can be called after RAM is set up by including amdk8.h and enabling the + * compilation of this file in src/northbridge/amd/amdk8/Makefile.inc. + */ +#ifndef __PRE_RAM__ +#include +#include +#include +#endif +#include "amdk8.h" + +/* Function 1 */ +/* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at + * 0x78, 0xb8, and 0xd8 + */ +#define DRAM_ROUTE_START 0x40 +#define DRAM_ROUTE_END 0x78 +#define MMIO_ROUTE_START 0x80 +#define MMIO_ROUTE_END 0xb8 +#define PCIIO_ROUTE_START 0xc0 +#define PCIIO_ROUTE_END 0xd8 +#define CONFIG_ROUTE_START 0xe0 +#define CONFIG_ROUTE_END 0xec + +#define PCI_IO_BASE0 0xc0 +#define PCI_IO_BASE1 0xc8 +#define PCI_IO_BASE2 0xd0 +#define PCI_IO_BASE3 0xd8 +#define PCI_IO_BASE_VGA_EN (1 << 4) +#define PCI_IO_BASE_NO_ISA (1 << 5) + +#define BITS(r, shift, mask) (((r>>shift)&mask)) + +/** + * Return "R" if the register has read-enable bit set. + */ +static const char *re(u32 i) +{ + return ((i & 1) ? "R" : ""); +} + +/** + * Return "W" if the register has write-enable bit set. + */ +static const char *we(u32 i) +{ + return ((i & 1) ? "W" : ""); +} + +/** + * Return a string containing the interleave settings. + */ +static const char *ileave(u32 base) +{ + switch ((base >> 8) & 7) { + case 0: + return "No interleave"; + case 1: + return "2 nodes"; + case 3: + return "4 nodes"; + case 7: + return "8 nodes"; + default: + return "Reserved"; + } +} + +/** + * Return the node number. + * For one case (config registers) these are not the right bit fields. + */ +static int r_node(u32 reg) +{ + return BITS(reg, 0, 0x7); +} + +/** + * Return the link number. + * For one case (config registers) these are not the right bit fields. + */ +static int r_link(u32 reg) +{ + return BITS(reg, 4, 0x3); +} + +/** + * Print the DRAM routing info for one base/limit pair. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and interleave information. + * + * @param level Printing level + * @param which Register number + * @param base Base register + * @param lim Limit register + */ +static void showdram(int level, u8 which, u32 base, u32 lim) +{ + printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n", + which, (((u64) base & 0xffff0000) << 8), + (((u64) lim & 0xffff0000) << 8) + 0xffffff, + r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); +} + +/** + * Print the config routing info for a config register. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and device number compare enable + * + * @param level Printing level + * @param which Register number + * @param reg Config register + */ +static void showconfig(int level, u8 which, u32 reg) +{ + /* Don't use r_node() and r_link() here. */ + printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", + which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), + BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), + re(reg), we(reg), + BITS(reg, 2, 0x1)?"dev":"bus"); +} + +/** + * Print the PCIIO routing info for one base/limit pair. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and VGA and ISA Enable. + * + * @param level Printing level + * @param which Register number + * @param base Base register + * @param lim Limit register + */ +static void showpciio(int level, u8 which, u32 base, u32 lim) +{ + printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n", + which, BITS(base, 12, 0x3fff) << 12, + (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim), + re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1)); +} + +/** + * Print the MMIO routing info for one base/limit pair. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and CPU Disable, Lock, and Non-posted. + * + * @param level Printing level + * @param which Register number + * @param base Base register + * @param lim Limit register + */ +static void showmmio(int level, u8 which, u32 base, u32 lim) +{ + printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, " + "CPU disable %d, Lock %d, Non posted %d\n", + which, ((u64) BITS(base, 0, 0xffffff00)) << 8, + (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim), + r_link(lim), re(base), we(base), BITS(base, 4, 0x1), + BITS(base, 7, 0x1), BITS(lim, 7, 0x1)); +} + +/** + * Show all DRAM routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showalldram(int level, device_t dev) +{ + u8 reg; + for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev, reg + 4); + if (base || lim!=(reg-DRAM_ROUTE_START)/8) + showdram(level, reg, base, lim); + } +} + +/** + * Show all MMIO routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showallmmio(int level, device_t dev) +{ + u8 reg; + for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev, reg + 4); + if (base || lim) + showmmio(level, reg, base, lim); + } +} + +/** + * Show all PCIIO routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showallpciio(int level, device_t dev) +{ + u8 reg; + for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev, reg + 4); + if (base || lim) + showpciio(level, reg, base, lim); + } +} + +/** + * Show all config routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showallconfig(int level, device_t dev) +{ + u8 reg; + for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) { + u32 val = pci_read_config32(dev, reg); + if (val) + showconfig(level, reg, val); + } +} + +/** + * Show all routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +void showallroutes(int level, device_t dev) +{ + showalldram(level, dev); + showallmmio(level, dev); + showallpciio(level, dev); + showallconfig(level, dev); +} Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Sun May 9 23:44:52 2010 (r5540) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Mon May 10 21:38:59 2010 (r5541) @@ -1021,7 +1021,7 @@ idx += 0x10; sizek -= pre_sizek; #if CONFIG_WRITE_HIGH_TABLES==1 - if (i==0 && high_tables_base==0) { + if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); @@ -1061,7 +1061,7 @@ #if CONFIG_WRITE_HIGH_TABLES==1 printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); - if (i==0 && high_tables_base==0) { + if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); From svn at coreboot.org Mon May 10 21:45:46 2010 From: svn at coreboot.org (repository service) Date: Mon, 10 May 2010 21:45:46 +0200 Subject: [coreboot] [commit] r5542 - trunk/src/northbridge/amd/amdfam10 Message-ID: Author: myles Date: Mon May 10 21:45:45 2010 New Revision: 5542 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5542 Log: Make show_all_routes work for fam10. Signed-off-by: Myles Watson Acked-by: Myles Watson Modified: trunk/src/northbridge/amd/amdfam10/Makefile.inc trunk/src/northbridge/amd/amdfam10/amdfam10.h trunk/src/northbridge/amd/amdfam10/util.c Modified: trunk/src/northbridge/amd/amdfam10/Makefile.inc ============================================================================== --- trunk/src/northbridge/amd/amdfam10/Makefile.inc Mon May 10 21:38:59 2010 (r5541) +++ trunk/src/northbridge/amd/amdfam10/Makefile.inc Mon May 10 21:45:45 2010 (r5542) @@ -10,3 +10,7 @@ obj-$(CONFIG_GENERATE_ACPI_TABLES) += sspr5.o obj-y += get_pci1234.o + +# Enable this if you want to check the values of the PCI routing registers. +# Call show_all_routes() anywhere amdfam10.h is included. +#obj-y += util.o Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10.h Mon May 10 21:38:59 2010 (r5541) +++ trunk/src/northbridge/amd/amdfam10/amdfam10.h Mon May 10 21:45:45 2010 (r5542) @@ -1169,4 +1169,8 @@ #endif +#ifndef __ROMCC__ +void showallroutes(int level, device_t dev); +#endif + #endif /* AMDFAM10_H */ Modified: trunk/src/northbridge/amd/amdfam10/util.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/util.c Mon May 10 21:38:59 2010 (r5541) +++ trunk/src/northbridge/amd/amdfam10/util.c Mon May 10 21:45:45 2010 (r5542) @@ -19,18 +19,18 @@ */ /* - * K8 northbridge utilities (dump routing registers). + * fam10 northbridge utilities (dump routing registers). * Designed to be called at any time. * It can be called before RAM is set up by including this file. - * It can be called after RAM is set up by including amdk8.h and enabling the - * compilation of this file in src/northbridge/amd/amdk8/Makefile.inc. + * It can be called after RAM is set up by including amdfam10.h and enabling the + * compilation of this file in src/northbridge/amd/amdfam10/Makefile.inc. */ #ifndef __PRE_RAM__ #include #include #include #endif -#include "amdk8.h" +#include "amdfam10.h" /* Function 1 */ /* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at From coop.rocks.123e at gmail.com Mon May 10 22:41:36 2010 From: coop.rocks.123e at gmail.com (Cooper Harrison) Date: Mon, 10 May 2010 16:41:36 -0400 Subject: [coreboot] Re Dell Optiplex GX1 support In-Reply-To: <1273509114.12757.59.camel@anders-laptop> References: <4be7c277.041bdf0a.77fe.ffffccc4SMTPIN_ADDED@mx.google.com> <1273509114.12757.59.camel@anders-laptop> Message-ID: the bios chip is built into the board, but would the bios bootblock not work? is there any way to check for a bootblock? this is a good computer and I do not want to kill it. On Mon, May 10, 2010 at 12:31 PM, Anders Jenbo wrote: > To improve the support a bit navigate to coreboot/util/getpir/ and run > make, then run ./getpir (on the GX1), this will generate a irq_tables.c > file. Copy it to your folder, and add the following to the first section > of your Kconfig. > > select HAVE_PIRQ_TABLE > > Once you have done this you should be ready to compile CoreBoot and > flash it on to your board. > If the flashing fails or the compiled ROM doesn't work for your board > could be unable to boot, so it is strongly recommended that you find or > buy a similar ROM chip so that you have a working backup in case > something goes wrong. > > -Anders > > -- Cooper -------------- next part -------------- An HTML attachment was scrubbed... URL: From peter at stuge.se Mon May 10 23:49:24 2010 From: peter at stuge.se (Peter Stuge) Date: Mon, 10 May 2010 23:49:24 +0200 Subject: [coreboot] Re Dell Optiplex GX1 support In-Reply-To: References: <4be7c277.041bdf0a.77fe.ffffccc4SMTPIN_ADDED@mx.google.com> <1273509114.12757.59.camel@anders-laptop> Message-ID: <20100510214924.22806.qmail@stuge.se> Cooper Harrison wrote: > the bios chip is built into the board, Soldered on? Does flashrom find the flash chip? > but would the bios bootblock not work? No. You will replace the complete factory BIOS if you try coreboot. > is there any way to check for a bootblock? > this is a good computer and I do not want to kill it. Which is why you need a way to recover from when the first version of coreboot that you try does not work. It most likely will not work without tuning, so please prepare for this. //Peter From anders at jenbo.dk Tue May 11 00:12:54 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Tue, 11 May 2010 00:12:54 +0200 Subject: [coreboot] =?utf-8?q?Indtast_Bcc_Re__Dell_Optiplex_GX1_support?= Message-ID: It is strongly advanced that you find a way to recover the BIOS. Mvh Anders ----- Reply message ----- Fra: "Cooper Harrison" Dato: man., maj 10, 2010 22:41 Emne: Re [coreboot] Dell Optiplex GX1 support Til: "Anders Jenbo" Cc: -------------- next part -------------- An HTML attachment was scrubbed... URL: From njacobs8 at hetnet.nl Tue May 11 01:30:31 2010 From: njacobs8 at hetnet.nl (Nils) Date: Tue, 11 May 2010 01:30:31 +0200 Subject: [coreboot] wyse s50 In-Reply-To: <4BE6ADCE.2060905@coresystems.de> References: <4BE6ADCE.2060905@coresystems.de> Message-ID: <201005110130.31227.njacobs8@hetnet.nl> Op zondag 9 mei 2010 14:42:54 schreef u: > hi Nils, > > could you please make a patch for your wyse s50 target that adds > - GPLv2 headers to all files > - adds your copyright to the files you created or changed (like > irq_tables.c) > > Sorry to ask for this late.. I guess I could add it, too, but it would > be nice if you'd find the time to create a patch as it's "your target" > now ;-) > > Anyways, thanks a lot for all your testing and work on coreboot. > > Stefan > Hi, As soon as i have some spare time i wil send a patch. I feel responsabel for "my target" ;-). Nils. From marcj303 at gmail.com Tue May 11 05:58:53 2010 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 10 May 2010 21:58:53 -0600 Subject: [coreboot] [PATCH] improve realmode api In-Reply-To: References: <201005090046.34912.njacobs8@hetnet.nl> <4BE5EB6C.40408@coresystems.de> Message-ID: On Sun, May 9, 2010 at 9:06 PM, Jordan Crouse wrote: > On Sat, May 8, 2010 at 4:53 PM, Stefan Reinauer wrote: >> On 5/9/10 12:46 AM, Nils wrote: >> >> I brought back the GX2 code in to the code at: >> svn://coreboot.org/vsa/trunk/gplvsa2 >> The biggest chunk of code doesn`t affect the LX code. >> The resulting LX image is binary compatible with the old one. >> But a few lines have to be selected for GX2 only. >> I wanted to invetigate how to do that and send a patch, >> but i haven`t had time. >> I am focusing on the board till now. >> >> Thanks,Nils. >> >> >> >> Jordan, >> >> do you happen to know where we can find a known good vsa image for GX2? > > I'm not even sure if one ever got released. ?Marc would know. That would be the OLPC VSA. Sorry, i don't have it, but OLPC should. Marc -- http://se-eng.com From svn at coreboot.org Tue May 11 17:39:20 2010 From: svn at coreboot.org (repository service) Date: Tue, 11 May 2010 17:39:20 +0200 Subject: [coreboot] [commit] r5543 - in trunk/src: devices/oprom northbridge/via/cx700 northbridge/via/vt8623 northbridge/via/vx800 Message-ID: Author: stepan Date: Tue May 11 17:39:20 2010 New Revision: 5543 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5543 Log: Change real mode API to allow passing intXX number or entry point and some register values from C. This theoretically fixes non-vga option roms, but it also allows to use the same assembler code for option roms and vsm. It will also make using the bootsplash without yabel a lot easier. Factor out and improve BDA setup, do some rom segment setup for those option roms that need it. Don't call the coreboot exception handler if an exception occurs in real mode. It's only partly usable, but mainly the Kontron 986LCD-M (and other i945GM boards) choke on an exception #6 (invalid opcode). This particular issue is not introduced by the changes in this patch but has been around for quite a while at least. Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi Modified: trunk/src/devices/oprom/x86.c trunk/src/devices/oprom/x86_asm.S trunk/src/northbridge/via/cx700/cx700_vga.c trunk/src/northbridge/via/cx700/northbridge.h trunk/src/northbridge/via/vt8623/northbridge.h trunk/src/northbridge/via/vt8623/vga.c trunk/src/northbridge/via/vx800/northbridge.h trunk/src/northbridge/via/vx800/vga.c Modified: trunk/src/devices/oprom/x86.c ============================================================================== --- trunk/src/devices/oprom/x86.c Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/devices/oprom/x86.c Tue May 11 17:39:20 2010 (r5543) @@ -34,12 +34,45 @@ void x86_exception(struct eregs *info); +/* From x86_asm.S */ extern unsigned char __idt_handler, __idt_handler_size; extern unsigned char __realmode_code, __realmode_code_size; -extern unsigned char __run_optionrom, __run_interrupt; +extern unsigned char __realmode_call, __realmode_interrupt; -void (*run_optionrom)(u32 devfn) __attribute__((regparm(0))) = (void *)&__run_optionrom; -void (*vga_enable_console)(void) __attribute__((regparm(0))) = (void *)&__run_interrupt; +void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_call; + +void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_interrupt; + +#define FAKE_MEMORY_SIZE (1024*1024) // only 1MB +#define INITIAL_EBDA_SEGMENT 0xF600 +#define INITIAL_EBDA_SIZE 0x400 + +static void setup_bda(void) +{ + /* clear BIOS DATA AREA */ + memset((void *)0x400, 0, 0x200); + + write16(0x413, FAKE_MEMORY_SIZE / 1024); + write16(0x40e, INITIAL_EBDA_SEGMENT); + + /* Set up EBDA */ + memset((void *)(INITIAL_EBDA_SEGMENT << 4), 0, INITIAL_EBDA_SIZE); + write16((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024); +} + +static void setup_rombios(void) +{ + const char date[] = "06/11/99"; + memcpy((void *)0xffff5, &date, 8); + + const char ident[] = "PCI_ISA"; + memcpy((void *)0xfffd9, &ident, 7); + + /* system model: IBM-AT */ + write8(0xffffe, 0xfc); +} int (*intXX_handler[256])(struct eregs *regs) = { NULL }; @@ -47,7 +80,12 @@ { printk(BIOS_INFO, "Oops, exception %d while executing option rom\n", regs->vector); +#if 0 + // Odd: The i945GM VGA oprom chokes on a pushl %eax and will + // die with an exception #6 if we run the coreboot exception + // handler. Just continue, as it executes fine. x86_exception(regs); // Call coreboot exception handler +#endif return 0; // Never returns? } @@ -138,20 +176,38 @@ /* int42 is the relocated int10 */ write_idt_stub((void *)0xff065, 0x42); - - /* VIA's VBIOS calls f000:f859 instead of int15 */ + /* BIOS Int 11 Handler F000:F84D */ + write_idt_stub((void *)0xff84d, 0x11); + /* BIOS Int 12 Handler F000:F841 */ + write_idt_stub((void *)0xff841, 0x12); + /* BIOS Int 13 Handler F000:EC59 */ + write_idt_stub((void *)0xfec59, 0x13); + /* BIOS Int 14 Handler F000:E739 */ + write_idt_stub((void *)0xfe739, 0x14); + /* BIOS Int 15 Handler F000:F859 */ write_idt_stub((void *)0xff859, 0x15); + /* BIOS Int 16 Handler F000:E82E */ + write_idt_stub((void *)0xfe82e, 0x16); + /* BIOS Int 17 Handler F000:EFD2 */ + write_idt_stub((void *)0xfefd2, 0x17); + /* ROM BIOS Int 1A Handler F000:FE6E */ + write_idt_stub((void *)0xffe6e, 0x1a); } void run_bios(struct device *dev, unsigned long addr) { - /* clear vga bios data area */ - memset((void *)0x400, 0, 0x200); + u32 num_dev = (dev->bus->secondary << 8) | dev->path.pci.devfn; + + /* Set up BIOS Data Area */ + setup_bda(); + + /* Set up some legacy information in the F segment */ + setup_rombios(); /* Set up C interrupt handlers */ setup_interrupt_handlers(); - /* Setting up realmode IDT */ + /* Set up real-mode IDT */ setup_realmode_idt(); memcpy(REALMODE_BASE, &__realmode_code, (size_t)&__realmode_code_size); @@ -159,7 +215,9 @@ (u32)&__realmode_code_size); printk(BIOS_DEBUG, "Calling Option ROM...\n"); - run_optionrom((dev->bus->secondary << 8) | dev->path.pci.devfn); + /* TODO ES:DI Pointer to System BIOS PnP Installation Check Structure */ + /* Option ROM entry point is at OPROM start + 3 */ + realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0); printk(BIOS_DEBUG, "... Option ROM returned.\n"); } @@ -168,9 +226,6 @@ #include #include -extern unsigned char __run_vsa; -void (*run_vsa)(u32 smm, u32 sysmem) __attribute__((regparm(0))) = (void *)&__run_vsa; - #define VSA2_BUFFER 0x60000 #define VSA2_ENTRY_POINT 0x60020 @@ -198,9 +253,6 @@ { printk(BIOS_DEBUG, "Preparing for VSA...\n"); - /* clear bios data area */ - memset((void *)0x400, 0, 0x200); - /* Set up C interrupt handlers */ setup_interrupt_handlers(); @@ -229,8 +281,11 @@ } printk(BIOS_DEBUG, "Calling VSA module...\n"); + /* ECX gets SMM, EDX gets SYSMEM */ - run_vsa(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM); + realmode_call(VSA2_ENTRY_POINT, 0x0, 0x0, MSR_GLIU0_SMM, + MSR_GLIU0_SYSMEM, 0x0, 0x0); + printk(BIOS_DEBUG, "... VSA module returned.\n"); /* Restart timer 1 */ Modified: trunk/src/devices/oprom/x86_asm.S ============================================================================== --- trunk/src/devices/oprom/x86_asm.S Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/devices/oprom/x86_asm.S Tue May 11 17:39:20 2010 (r5543) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2009-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,21 +57,49 @@ __stack = RELOCATED(.) .long 0 +/* Register store for realmode_call and realmode_interrupt */ +__registers = RELOCATED(.) + .long 0 /* 0x00 - EAX */ + .long 0 /* 0x04 - EBX */ + .long 0 /* 0x08 - ECX */ + .long 0 /* 0x0c - EDX */ + .long 0 /* 0x10 - EDI */ + .long 0 /* 0x14 - ESI */ + .code32 - .globl __run_optionrom -__run_optionrom = RELOCATED(.) + .globl __realmode_call +__realmode_call = RELOCATED(.) /* save all registers to the stack */ pushal /* Move the protected mode stack to a safe place */ - mov %esp, __stack - - /* Get devfn into %ecx */ + movl %esp, __stack movl %esp, %ebp + /* This function is called with regparm=0 and we have - * to skip the 32 byte from pushal: + * to skip the 32 byte from pushal. Hence start at 36. */ - movl 36(%ebp), %ecx + + /* entry point */ + movl 36(%ebp), %eax + movw %ax, __lcall_instr + 1 + andl $0xffff0000, %eax + shrl $4, %eax + movw %ax, __lcall_instr + 3 + + /* initial register values */ + movl 40(%ebp), %eax + movl %eax, __registers + 0x00 /* eax */ + movl 44(%ebp), %eax + movl %eax, __registers + 0x04 /* ebx */ + movl 48(%ebp), %eax + movl %eax, __registers + 0x08 /* ecx */ + movl 52(%ebp), %eax + movl %eax, __registers + 0x0c /* edx */ + movl 56(%ebp), %eax + movl %eax, __registers + 0x10 /* esi */ + movl 60(%ebp), %eax + movl %eax, __registers + 0x14 /* esi */ /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f) @@ -120,11 +148,18 @@ mov $0x40, %ax mov %ax, %ds + /* initialize registers for option rom lcall */ + movl __registers + 0, %eax + movl __registers + 4, %ebx + movl __registers + 8, %ecx + movl __registers + 12, %edx + movl __registers + 16, %esi + movl __registers + 20, %edi + /* ************************************ */ - mov %cx, %ax // restore ax - // TODO this will not work for non-VGA option ROMs - /* run VGA BIOS at 0xc000:0003 */ - lcall $0xc000, $0x0003 +__lcall_instr = RELOCATED(.) + .byte 0x9a + .word 0x0000, 0x0000 /* ************************************ */ /* If we got here, just about done. @@ -151,126 +186,47 @@ lidt idtarg /* and exit */ - mov __stack, %esp + movl __stack, %esp popal - ret -#if defined(CONFIG_GEODE_VSA) && CONFIG_GEODE_VSA -#define VSA2_ENTRY_POINT 0x60020 + // TODO return AX from OPROM call + ret - .globl __run_vsa -__run_vsa = RELOCATED(.) + .globl __realmode_interrupt +__realmode_interrupt = RELOCATED(.) /* save all registers to the stack */ pushal - - /* Move the protected mode stack to a safe place */ - mov %esp, __stack - + /* save the stack */ + movl %esp, __stack movl %esp, %ebp - /* This function is called with regparm=0 and we have - * to skip the 32 byte from pushal: - */ - movl 36(%ebp), %ecx - movl 40(%ebp), %edx - - /* Activate the right segment descriptor real mode. */ - ljmp $0x28, $RELOCATED(1f) -1: -.code16 - /* 16 bit code from here on... */ - - /* Load the segment registers w/ properly configured - * segment descriptors. They will retain these - * configurations (limits, writability, etc.) once - * protected mode is turned off. - */ - mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss - - /* Turn off protection */ - movl %cr0, %eax - andl $~PE, %eax - movl %eax, %cr0 - - /* Now really going into real mode */ - ljmp $0, $RELOCATED(1f) -1: - /* Setup a stack: Put the stack at the end of page zero. - * That way we can easily share it between real and - * protected, since the 16 bit ESP at segment 0 will - * work for any case. */ - mov $0x0, %ax - mov %ax, %ss - movl $0x1000, %eax - movl %eax, %esp - /* Load our 16 bit idt */ - xor %ax, %ax - mov %ax, %ds - lidt __realmode_idt - - /* Set all segments to 0x0000, ds to 0x0040 */ - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov $0x40, %ax - mov %ax, %ds - mov %cx, %ax // restore ax - - /* ************************************ */ - lcall $((VSA2_ENTRY_POINT & 0xffff0000) >> 4), $(VSA2_ENTRY_POINT & 0xffff) - /* ************************************ */ - - /* If we got here, just about done. - * Need to get back to protected mode + /* This function is called with regparm=0 and we have + * to skip the 32 byte from pushal. Hence start at 36. */ - movl %cr0, %eax - orl $PE, %eax - movl %eax, %cr0 - - /* Now that we are in protected mode - * jump to a 32 bit code segment. - */ - data32 ljmp $0x10, $RELOCATED(1f) -1: - .code32 - movw $0x18, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss - - /* restore proper idt */ - lidt idtarg - - /* and exit */ - mov __stack, %esp - popal - ret -#endif - - .globl __run_interrupt -__run_interrupt = RELOCATED(.) - - pushal - /* save the stack */ - mov %esp, __stack + /* prepare interrupt calling code */ + movl 36(%ebp), %eax + movb %al, __intXX_instr + 1 /* intno */ + + /* initial register values */ + movl 40(%ebp), %eax + movl %eax, __registers + 0x00 /* eax */ + movl 44(%ebp), %eax + movl %eax, __registers + 0x04 /* ebx */ + movl 48(%ebp), %eax + movl %eax, __registers + 0x08 /* ecx */ + movl 52(%ebp), %eax + movl %eax, __registers + 0x0c /* edx */ + movl 56(%ebp), %eax + movl %eax, __registers + 0x10 /* esi */ + movl 60(%ebp), %eax + movl %eax, __registers + 0x14 /* esi */ /* This configures CS properly for real mode. */ ljmp $0x28, $RELOCATED(1f) 1: .code16 /* 16 bit code from here on... */ - // DEBUG - movb $0xec, %al - outb %al, $0x80 - /* Load the segment registers w/ properly configured segment * descriptors. They will retain these configurations (limits, * writability, etc.) once protected mode is turned off. @@ -291,9 +247,9 @@ data32 ljmp $0, $RELOCATED(1f) 1: - /* put the stack at the end of page zero. - * that way we can easily share it between real and protected, - * since the 16-bit ESP at segment 0 will work for any case. + /* put the stack at the end of page zero. That way we can easily + * share it between real mode and protected mode, because %esp and + * %ss:%sp point to the same memory. */ /* setup a stack */ mov $0x0, %ax @@ -312,18 +268,16 @@ mov %ax, %fs mov %ax, %gs - /* Call VGA BIOS int10 function 0x4f14 to enable main console - * Epia-M does not always autosence the main console so forcing - * it on is good. - */ + /* initialize registers for intXX call */ + movl __registers + 0, %eax + movl __registers + 4, %ebx + movl __registers + 8, %ecx + movl __registers + 12, %edx + movl __registers + 16, %esi + movl __registers + 20, %edi - /* Ask VGA option rom to enable main console */ - movw $0x4f14,%ax - movw $0x8003,%bx - movw $1, %cx - movw $0, %dx - movw $0, %di - int $0x10 +__intXX_instr = RELOCATED(.) + .byte 0xcd, 0x00 /* This becomes intXX */ /* Ok, the job is done, now go back to protected mode coreboot */ movl %cr0, %eax @@ -345,13 +299,15 @@ lidt idtarg /* Exit */ - mov __stack, %esp + movl __stack, %esp popal ret /* This is the 16-bit interrupt entry point called by the IDT stub code. + * * Before this code code is called, %eax is pushed to the stack, and the - * interrupt number is loaded into %al + * interrupt number is loaded into %al. On return this function cleans up + * for its caller. */ .code16 __interrupt_handler_16bit = RELOCATED(.) Modified: trunk/src/northbridge/via/cx700/cx700_vga.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/cx700/cx700_vga.c Tue May 11 17:39:20 2010 (r5543) @@ -144,6 +144,17 @@ } #endif +static void vga_enable_console(void) +{ + /* Call VGA BIOS int10 function 0x4f14 to enable main console + * Epia-M does not always autosense the main console so forcing + * it on is good. + */ + + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + realmode_interrupt(0x10, 0x4f1f, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); +} + static void vga_init(device_t dev) { u8 reg8; @@ -166,9 +177,6 @@ if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return; printk(BIOS_DEBUG, "Enable VGA console\n"); - // this is how it should look: - // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); - // this is how it looks: vga_enable_console(); /* It's not clear if these need to be programmed before or after Modified: trunk/src/northbridge/via/cx700/northbridge.h ============================================================================== --- trunk/src/northbridge/via/cx700/northbridge.h Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/cx700/northbridge.h Tue May 11 17:39:20 2010 (r5543) @@ -21,6 +21,6 @@ #define NORTHBRIDGE_VIA_CX700_H extern unsigned int cx700_scan_root_bus(device_t root, unsigned int max); -extern void (*vga_enable_console)(void) __attribute__((regparm(0))); - +extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))); #endif /* NORTHBRIDGE_VIA_CX700_H */ Modified: trunk/src/northbridge/via/vt8623/northbridge.h ============================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.h Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/vt8623/northbridge.h Tue May 11 17:39:20 2010 (r5543) @@ -2,7 +2,7 @@ #define NORTHBRIDGE_VIA_VT8623_H unsigned int vt8623_scan_root_bus(device_t root, unsigned int max); -extern void (*vga_enable_console)(void) __attribute__((regparm(0))); -void write_protect_vgabios(void); +extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))); #endif /* NORTHBRIDGE_VIA_VT8623_H */ Modified: trunk/src/northbridge/via/vt8623/vga.c ============================================================================== --- trunk/src/northbridge/via/vt8623/vga.c Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/vt8623/vga.c Tue May 11 17:39:20 2010 (r5543) @@ -72,7 +72,8 @@ return res; } -void write_protect_vgabios(void) +#ifdef UNUSED_CODE +static void write_protect_vgabios(void) { device_t dev; @@ -86,6 +87,7 @@ if (dev) pci_write_config8(dev, 0x61, 0xaa); } +#endif static void vga_random_fixup(device_t dev) { @@ -96,6 +98,17 @@ pci_write_config32(dev,0x14,0xdc000000); } +static void vga_enable_console(void) +{ + /* Call VGA BIOS int10 function 0x4f14 to enable main console + * Epia-M does not always autosense the main console so forcing + * it on is good. + */ + + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + realmode_interrupt(0x10, 0x4f1f, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); +} + static void vga_init(device_t dev) { vga_random_fixup(dev); @@ -118,9 +131,6 @@ pci_dev_init(dev); printk(BIOS_DEBUG, "Enable VGA console\n"); - // this is how it should look: - // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); - // this is how it looks: vga_enable_console(); #ifdef MEASURE_VGA_INIT_TIME Modified: trunk/src/northbridge/via/vx800/northbridge.h ============================================================================== --- trunk/src/northbridge/via/vx800/northbridge.h Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/vx800/northbridge.h Tue May 11 17:39:20 2010 (r5543) @@ -21,6 +21,7 @@ #define NORTHBRIDGE_VIA_VX800_H extern unsigned int vx800_scan_root_bus(device_t root, unsigned int max); -extern void (*vga_enable_console)(void) __attribute__((regparm(0))); +extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))); #endif /* NORTHBRIDGE_VIA_VX800_H */ Modified: trunk/src/northbridge/via/vx800/vga.c ============================================================================== --- trunk/src/northbridge/via/vx800/vga.c Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/vx800/vga.c Tue May 11 17:39:20 2010 (r5543) @@ -127,7 +127,7 @@ } #ifdef UNUSED_CODE -void write_protect_vgabios(void) +static void write_protect_vgabios(void) { device_t dev; @@ -144,6 +144,17 @@ } #endif +static void vga_enable_console(void) +{ + /* Call VGA BIOS int10 function 0x4f14 to enable main console + * Epia-M does not always autosense the main console so forcing + * it on is good. + */ + + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + realmode_interrupt(0x10, 0x4f1f, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); +} + extern u8 acpi_sleep_type; static void vga_init(device_t dev) { @@ -170,9 +181,6 @@ pci_dev_init(dev); printk(BIOS_DEBUG, "Enable VGA console\n"); - // this is how it should look: - // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); - // this is how it looks: vga_enable_console(); if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) { From joe.korty at ccur.com Tue May 11 21:56:20 2010 From: joe.korty at ccur.com (Joe Korty) Date: Tue, 11 May 2010 15:56:20 -0400 Subject: [coreboot] H8DME-2 woes,continued... In-Reply-To: <20100505200608.GA15441@tsunami.ccur.com> References: <20100505200608.GA15441@tsunami.ccur.com> Message-ID: <20100511195620.GA3442@tsunami.ccur.com> Hi Everyone, Well, I've replaced the AMD 2378 CPUs on my SuperMicro H8DME-2 mb with a pair of AMD 2212 CPUs, and I get much much further along in the boot. But it still locks up. The starting and ending messages on the serial console are: <30 second wait before first message, here> oreboot-4.0-r5543 Tue May 11 09:42:01 EDT 2010 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=00 Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=00 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done core0 started: 01 started ap apicid: * AP 01started * AP 03started <10 second wait, here> SBLink=02 NC node|link=02 begin msr fid, vid 31081212080c0202 Current fid_cur: 0x2, fid_max: 0xc Requested fid_new: 0xc FidVid table step fidvid: 0xc Current fid_cur: 0x2, fid_max: 0xc Requested fid_new: 0xc FidVid table step fidvid: 0xc end msr fid, vid 31081208080c020c entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0xca, unfiltered freq_cap=0x8075 pos=0xca, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 ... IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 set power on after power fail RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum enabling HPET @0xfed00000 PNP: 002e.2 init PNP: 002e.5 init Keyboard init... Keyboard controller output buffer result timeout PNP: 002e.b init PCI: 00:01.1 init PCI: 00:02.1 init PCI: 00:04.0 init IDE0 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b018 + align -> fff0b080 Check fallback/payload CBFS: follow chain: fff0b080 + 38 + 9dfb + align -> fff14ec0 Check pci10de,0363.rom CBFS: follow chain: fff14ec0 + 38 + b000 + align -> fff1ff00 Check CBFS: follow chain: fff1ff00 + 28 + d00b8 + align -> ffff0000 CBFS: Could not find file pci10de,036e.rom PCI: 00:05.0 init SATA S SATA P PCI: 00:05.1 init SATA S SATA P PCI: 00:05.2 init SATA S SATA P PCI: 00:06.0 init PCI DOMAIN mem base = 0x00f0000000 [0x50] <-- 0xf0000000 PCI: 00:06.1 init base = 0xfc140000 codec_mask = 01 That 'CBFS: Could not find file pci10d3,036e.rom' really bothers me. AFAICS, 10d3,036e is a IDE controller on the MCP55 southbridge; the VGA is at 1002,515e. Am I reading everything wrong? My lspci -vn is: 00:00.0 0500: 10de:0369 (rev a2) Subsystem: 15d9:1611 Flags: bus master, 66MHz, fast devsel, latency 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Capabilities: [dc] HyperTransport: MSI Mapping 00:01.0 0601: 10de:0364 (rev a3) Subsystem: 15d9:1611 Flags: bus master, 66MHz, fast devsel, latency 0 00:01.1 0c05: 10de:0368 (rev a3) Subsystem: 15d9:1611 Flags: 66MHz, fast devsel, IRQ 11 I/O ports at dc00 [size=64] I/O ports at 2d00 [size=64] I/O ports at 2e00 [size=64] Capabilities: [44] Power Management version 2 00:02.0 0c03: 10de:036c (rev a1) (prog-if 10) Subsystem: 15d9:1611 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 22 Memory at feabf000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 00:02.1 0c03: 10de:036d (rev a2) (prog-if 20) Subsystem: 15d9:1611 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 23 Memory at feabec00 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port Capabilities: [80] Power Management version 2 00:04.0 0101: 10de:036e (rev a1) (prog-if 8a) Subsystem: 15d9:1611 Flags: bus master, 66MHz, fast devsel, latency 0 [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] I/O ports at ffa0 [size=16] Capabilities: [44] Power Management version 2 00:05.0 0101: 10de:037f (rev a3) (prog-if 85) Subsystem: 15d9:1611 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 23 I/O ports at d480 [size=8] I/O ports at d400 [size=4] I/O ports at d080 [size=8] I/O ports at d000 [size=4] I/O ports at cc00 [size=16] Memory at feabd000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Capabilities: [cc] HyperTransport: MSI Mapping 00:05.1 0101: 10de:037f (rev a3) (prog-if 85) Subsystem: 15d9:1611 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 22 I/O ports at c880 [size=8] I/O ports at c800 [size=4] I/O ports at c480 [size=8] I/O ports at c400 [size=4] I/O ports at c080 [size=16] Memory at feabc000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Capabilities: [cc] HyperTransport: MSI Mapping 00:05.2 0101: 10de:037f (rev a3) (prog-if 85) Subsystem: 15d9:1611 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 21 I/O ports at c000 [size=8] I/O ports at bc00 [size=4] I/O ports at b880 [size=8] I/O ports at b800 [size=4] I/O ports at b480 [size=16] Memory at feabb000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Capabilities: [cc] HyperTransport: MSI Mapping 00:06.0 0604: 10de:0370 (rev a2) (prog-if 01) Flags: bus master, 66MHz, fast devsel, latency 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 0000e000-0000efff Memory behind bridge: feb00000-febfffff Prefetchable memory behind bridge: f0000000-f7ffffff Capabilities: [b8] #0d [0000] Capabilities: [8c] HyperTransport: MSI Mapping 00:08.0 0680: 10de:0373 (rev a3) Subsystem: 15d9:1611 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 29 Memory at feaba000 (32-bit, non-prefetchable) [size=4K] I/O ports at b400 [size=8] Memory at feabe800 (32-bit, non-prefetchable) [size=256] Memory at feabe400 (32-bit, non-prefetchable) [size=16] Capabilities: [44] Power Management version 2 Capabilities: [70] MSI-X: Enable- Mask- TabSize=8 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable+ Capabilities: [6c] HyperTransport: MSI Mapping 00:09.0 0680: 10de:0373 (rev a3) Subsystem: 15d9:1611 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 28 Memory at feab9000 (32-bit, non-prefetchable) [size=4K] I/O ports at b080 [size=8] Memory at feabe000 (32-bit, non-prefetchable) [size=256] Memory at feab8c00 (32-bit, non-prefetchable) [size=16] Capabilities: [44] Power Management version 2 Capabilities: [70] MSI-X: Enable- Mask- TabSize=8 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable+ Capabilities: [6c] HyperTransport: MSI Mapping 00:0a.0 0604: 10de:0376 (rev a3) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=02, subordinate=04, sec-latency=0 Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [160] Advanced Error Reporting 00:0d.0 0604: 10de:0378 (rev a3) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [160] Advanced Error Reporting 00:0e.0 0604: 10de:0375 (rev a3) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [160] Advanced Error Reporting 00:0f.0 0604: 10de:0377 (rev a3) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=07, subordinate=07, sec-latency=0 Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [160] Advanced Error Reporting 00:18.0 0600: 1022:1100 Flags: fast devsel Capabilities: [80] HyperTransport: Host or Secondary Interface Capabilities: [a0] HyperTransport: Host or Secondary Interface Capabilities: [c0] HyperTransport: Host or Secondary Interface 00:18.1 0600: 1022:1101 Flags: fast devsel 00:18.2 0600: 1022:1102 Flags: fast devsel 00:18.3 0600: 1022:1103 Flags: fast devsel Capabilities: [f0] #0f [0010] 00:19.0 0600: 1022:1100 Flags: fast devsel Capabilities: [80] HyperTransport: Host or Secondary Interface Capabilities: [a0] HyperTransport: Host or Secondary Interface Capabilities: [c0] HyperTransport: Host or Secondary Interface 00:19.1 0600: 1022:1101 Flags: fast devsel 00:19.2 0600: 1022:1102 Flags: fast devsel 00:19.3 0600: 1022:1103 Flags: fast devsel Capabilities: [f0] #0f [0010] 01:05.0 0300: 1002:515e (rev 02) Subsystem: 15d9:1611 Flags: bus master, stepping, medium devsel, latency 64, IRQ 10 Memory at f0000000 (32-bit, prefetchable) [size=128M] I/O ports at e000 [size=256] Memory at febf0000 (32-bit, non-prefetchable) [size=64K] Expansion ROM at feb00000 [disabled] [size=128K] Capabilities: [50] Power Management version 2 02:00.0 0604: 1033:0125 (rev 08) Flags: bus master, fast devsel, latency 0 Bus: primary=02, secondary=03, subordinate=03, sec-latency=64 Capabilities: [40] Express PCI/PCI-X Bridge IRQ 0 Capabilities: [54] PCI-X bridge device Capabilities: [64] Power Management version 2 Capabilities: [100] Advanced Error Reporting 02:00.1 0604: 1033:0125 (rev 08) Flags: bus master, fast devsel, latency 0 Bus: primary=02, secondary=04, subordinate=04, sec-latency=64 Capabilities: [40] Express PCI/PCI-X Bridge IRQ 0 Capabilities: [54] PCI-X bridge device Capabilities: [64] Power Management version 2 Capabilities: [100] Advanced Error Reporting Any advice on what I am doing wrong here, or what I need to do right or what I need to do to find out how to get further along, would be appreciated. Regards, Joe From joe.korty at ccur.com Tue May 11 23:10:37 2010 From: joe.korty at ccur.com (Joe Korty) Date: Tue, 11 May 2010 17:10:37 -0400 Subject: [coreboot] [PATCH] h8dme-2: fix most remaining compile-time warnings Message-ID: <20100511211037.GA8824@tsunami.ccur.com> Clean up some h8dme-2 warnings. Eliminate those warnings in the supermicro h8dme-2 build that are due to the header file w83627hf.h being included multiple times. Signed-off-by: Joe Korty Index: trunk/src/superio/winbond/w83627hf/w83627hf.h =================================================================== --- trunk.orig/src/superio/winbond/w83627hf/w83627hf.h 2010-05-11 07:00:24.000000000 -0400 +++ trunk/src/superio/winbond/w83627hf/w83627hf.h 2010-05-11 13:06:19.000000000 -0400 @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __W83627HF_H +#define __W83627HF_H + #define W83627HF_FDC 0 /* Floppy */ #define W83627HF_PP 1 /* Parallel Port */ #define W83627HF_SP1 2 /* Com1 */ @@ -117,3 +120,4 @@ void w83627hf_set_clksel_48(device_t dev); #endif +#endif /* __W83627HF_H */ From joe.korty at ccur.com Tue May 11 23:54:29 2010 From: joe.korty at ccur.com (Joe Korty) Date: Tue, 11 May 2010 17:54:29 -0400 Subject: [coreboot] it boots! [was: re: H8DME-2 woes, continued....] In-Reply-To: <20100511195620.GA3442@tsunami.ccur.com> References: <20100505200608.GA15441@tsunami.ccur.com> <20100511195620.GA3442@tsunami.ccur.com> Message-ID: <20100511215429.GA5588@tsunami.ccur.com> On Tue, May 11, 2010 at 03:56:20PM -0400, Joe Korty wrote: > Hi Everyone, > Well, I've replaced the AMD 2378 CPUs on my SuperMicro H8DME-2 mb with > a pair of AMD 2212 CPUs, and I get much much further along in the boot. > But it still locks up. The starting and ending messages on the serial > console are: > > [0x50] <-- 0xf0000000 > PCI: 00:06.1 init > base = 0xfc140000 > codec_mask = 01 It boots!!!!! I applied the below patch to skip 'codec' initialization (whatever that is) and I was able to boot up to linux. Can anyone explain what the codec is; perhaps we can turn this 'feature' off permanently? (or make it a .config option). Joe Index: trunk/src/southbridge/nvidia/mcp55/mcp55_aza.c =================================================================== --- trunk.orig/src/southbridge/nvidia/mcp55/mcp55_aza.c 2010-05-06 10:54:13.000000000 -0400 +++ trunk/src/southbridge/nvidia/mcp55/mcp55_aza.c 2010-05-11 13:57:59.000000000 -0400 @@ -237,7 +237,7 @@ if(codec_mask) { printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); - codecs_init(base, codec_mask); + // codecs_init(base, codec_mask); } } From njacobs8 at hetnet.nl Wed May 12 00:47:48 2010 From: njacobs8 at hetnet.nl (Nils) Date: Wed, 12 May 2010 00:47:48 +0200 Subject: [coreboot] [PATCH] Wyse S50 cleanup Message-ID: <201005120047.49057.njacobs8@hetnet.nl> This patch cleanes up the Wyse S50 port and unifies the memmory regions with Geode LX , adds gpl2 headers plus some white space fixes. This is build and boot tested.(of course vsa loading is stil not fixed,it now runs forever with :"Oops, exception 13 while executing option rom") Signed-off-by: Nils Jacobs Hi Stefan, I hope this is what you had in mind regarding the GPLv2 headers? Thanks,Nils. -------------- next part -------------- A non-text attachment was scrubbed... Name: 5543_s50_cleanup.patch Type: text/x-patch Size: 11258 bytes Desc: not available URL: From njacobs8 at hetnet.nl Wed May 12 01:03:29 2010 From: njacobs8 at hetnet.nl (Nils) Date: Wed, 12 May 2010 01:03:29 +0200 Subject: [coreboot] GX2 problems In-Reply-To: <4BE5DEF6.6030701@coresystems.de> References: <201005010158.34049.njacobs8@hetnet.nl> <4BE5DEF6.6030701@coresystems.de> Message-ID: <201005120103.29494.njacobs8@hetnet.nl> Op zondag 9 mei 2010 00:00:22 schreef u: > On 5/1/10 1:58 AM, Nils wrote: > > Index: src/northbridge/amd/gx2/northbridgeinit.c > > =================================================================== > > --- src/northbridge/amd/gx2/northbridgeinit.c (revision 5520) > > +++ src/northbridge/amd/gx2/northbridgeinit.c (working copy) > > @@ -672,7 +672,7 @@ > > { > > uint64_t shadowSettings = getShadow(); > > shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & > > writes - shadowSettings |= (uint64_t) 0x00000000F0000000ULL; // Enable > > reads for F0000-FFFFF + shadowSettings |= (uint64_t) > > 0x0000FFFFFFFF0000ULL; // Enable reads for C0000-FFFFF > > setShadow(shadowSettings); > > } > > What's this doing? > > Is it potentially dangerous for other systems? > Hi Stefan, I specifically tested this again on my patched rev5470 (the last working version here) and it is needed there. Without it Seabios refuses to work and coreboot reboots. I don`t know what it does on current trunk because it never gets til Seabios. I don`t think it is dangrous to other systems because the GX2 tree is broken for more than a year and probably never worked with Seabios. It would be nice if you could commit it. Thanks,Nils. From peter at stuge.se Wed May 12 02:01:28 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 12 May 2010 02:01:28 +0200 Subject: [coreboot] it boots! [was: re: H8DME-2 woes, continued....] In-Reply-To: <20100511215429.GA5588@tsunami.ccur.com> References: <20100505200608.GA15441@tsunami.ccur.com> <20100511195620.GA3442@tsunami.ccur.com> <20100511215429.GA5588@tsunami.ccur.com> Message-ID: <20100512000128.8767.qmail@stuge.se> Joe Korty wrote: > I applied the below patch to skip 'codec' initialization (whatever > that is) and I was able to boot up to linux. Where did you find the suggestion to do it? > Can anyone explain what the codec is; perhaps we can turn this > 'feature' off permanently? (or make it a .config option). The codec in this case is the chip that converts digital signals into audible sound. It's part of the integrated soundcard in the chipset. It should certainly not cause a hang.. The bad part is that we have no docs for MCP55. In any case, there is code like this in southbridge/nvidia/mcp55/mcp55_aza.c: do { dword = read32(base + 0x68); } while (dword & 1); And that's bad. We shouldn't have code like this anywhere in coreboot. It should get a timeout of some sort, so that it doesn't hang forever. A simple counter would be a great start, but it would of course be best to understand why the code doesn't work on your system.. Can you check which codec you have please? Linux reports this. From my laptop: [ 3.509587] ALSA device list: [ 3.509593] #0: Intel 82801DB-ICH4 with AD1981B at irq 17 AD1981B is the codec. //Peter From marcj303 at gmail.com Wed May 12 03:42:55 2010 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 11 May 2010 19:42:55 -0600 Subject: [coreboot] H8DME-2 woes,continued... In-Reply-To: <20100511195620.GA3442@tsunami.ccur.com> References: <20100505200608.GA15441@tsunami.ccur.com> <20100511195620.GA3442@tsunami.ccur.com> Message-ID: Hi Joe, I'm not much help, but I made a couple comments below. On Tue, May 11, 2010 at 1:56 PM, Joe Korty wrote: > Hi Everyone, > Well, I've replaced the AMD 2378 CPUs on my SuperMicro H8DME-2 mb with > a pair of AMD 2212 CPUs, and I get much much further along in the boot. > But it still locks up. ?The starting and ending messages on the serial > console are: > > <30 second wait before first message, here> This wait is bad. I guess it is off spinning in CAR somewhere. You might try using a port80 card to get more debug information. > ? ? ? ?CBFS: follow chain: fff1ff00 + 28 + d00b8 + align -> ffff0000 > ? ? ? ?CBFS: ?Could not find file pci10de,036e.rom > That 'CBFS: Could not find file pci10d3,036e.rom' really bothers me. ?AFAICS, > 10d3,036e is a IDE controller on the MCP55 southbridge; the VGA is at 1002,515e. > Am I reading everything wrong? ?My lspci -vn is: > This is ok. It is a normal part of the scan for some devices to not have a PCI ROM in coreboot. Filo, SeaBIOS, and/or Linux should handle the IDE for you. Marc -- http://se-eng.com From buurin at gmail.com Wed May 12 03:53:29 2010 From: buurin at gmail.com (Keith Hui) Date: Tue, 11 May 2010 21:53:29 -0400 Subject: [coreboot] Preview: SECC Pentium 2/3 users are gonna love this Message-ID: See this boot log: http://coreboot.pastebin.com/rdmwwvha I have done the 72oz steak ;-P that is porting the L2 enabling code from coreboot v1 to current trunk, made much slimmer by being able to put it post-raminit. The CPU in question is a Pentium III 600MHz, Katmai core, 512KB cache. Tell me if I am headed the right direction. Patch to come soonish. Enjoy Keith PS. Oh by the way... [root at ojisan ~]# cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 7 model name : Pentium III (Katmai) stepping : 3 cpu MHz : 601.352 cache size : 512 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 2 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pse36 mmx fxsr sse up bogomips : 1202.70 clflush size : 32 power management: [root at ojisan ~]# From joe.korty at ccur.com Wed May 12 05:25:07 2010 From: joe.korty at ccur.com (Joe Korty) Date: Tue, 11 May 2010 23:25:07 -0400 Subject: [coreboot] H8DME-2 woes,continued... In-Reply-To: References: <20100505200608.GA15441@tsunami.ccur.com> <20100511195620.GA3442@tsunami.ccur.com> Message-ID: <20100512032507.GA30112@tsunami.ccur.com> On Tue, May 11, 2010 at 09:42:55PM -0400, Marc Jones wrote: > Hi Joe, > I'm not much help, but I made a couple comments below. > > On Tue, May 11, 2010 at 1:56 PM, Joe Korty wrote: > > Hi Everyone, > > Well, I've replaced the AMD 2378 CPUs on my SuperMicro H8DME-2 mb with > > a pair of AMD 2212 CPUs, and I get much much further along in the boot. > > But it still locks up. ?The starting and ending messages on the serial > > console are: > > > > <30 second wait before first message, here> > > This wait is bad. I guess it is off spinning in CAR somewhere. You > might try using a port80 card to get more debug information. Thanks, Marc. I'll try pinning this down again tommorrow morning. My first attempts to do so (bisection) have been inconclusive. Regards, Joe From joe.korty at ccur.com Wed May 12 05:54:18 2010 From: joe.korty at ccur.com (Joe Korty) Date: Tue, 11 May 2010 23:54:18 -0400 Subject: [coreboot] it boots! [was: re: H8DME-2 woes, continued....] In-Reply-To: <20100512000128.8767.qmail@stuge.se> References: <20100505200608.GA15441@tsunami.ccur.com> <20100511195620.GA3442@tsunami.ccur.com> <20100511215429.GA5588@tsunami.ccur.com> <20100512000128.8767.qmail@stuge.se> Message-ID: <20100512035418.GA32033@tsunami.ccur.com> On Tue, May 11, 2010 at 08:01:28PM -0400, Peter Stuge wrote: > Joe Korty wrote: > > I applied the below patch to skip 'codec' initialization (whatever > > that is) and I was able to boot up to linux. > > Where did you find the suggestion to do it? I merely looked at the code around the last message to be printed. There was another printk a few lines down that wasn't being reached. As the 'codec' feature sounded worthless (at least at boot time), I decided to comment it out and see how much further in the boot I proceeded. > > Can anyone explain what the codec is; perhaps we can turn this > > 'feature' off permanently? (or make it a .config option). > > The codec in this case is the chip that converts digital signals into > audible sound. It's part of the integrated soundcard in the chipset. > It should certainly not cause a hang.. Thanks! Now I as least know what it is. > The bad part is that we have no docs for MCP55. > > In any case, there is code like this in > southbridge/nvidia/mcp55/mcp55_aza.c: > > do { > dword = read32(base + 0x68); > } while (dword & 1); > > And that's bad. We shouldn't have code like this anywhere in > coreboot. It should get a timeout of some sort, so that it doesn't > hang forever. I'll write up a patch to do that, if no one else beats me to it first. Regards, Joe From peter at stuge.se Wed May 12 06:28:10 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 12 May 2010 06:28:10 +0200 Subject: [coreboot] it boots! [was: re: H8DME-2 woes, continued....] In-Reply-To: <20100512035418.GA32033@tsunami.ccur.com> References: <20100505200608.GA15441@tsunami.ccur.com> <20100511195620.GA3442@tsunami.ccur.com> <20100511215429.GA5588@tsunami.ccur.com> <20100512000128.8767.qmail@stuge.se> <20100512035418.GA32033@tsunami.ccur.com> Message-ID: <20100512042810.11335.qmail@stuge.se> Joe Korty wrote: > > do { > > dword = read32(base + 0x68); > > } while (dword & 1); > > > > And that's bad. We shouldn't have code like this anywhere in > > coreboot. It should get a timeout of some sort, so that it doesn't > > hang forever. > > I'll write up a patch to do that, if no one else beats me to it > first. Awesome! Go for it! (Btw what codec is on your board?) //Peter From c-d.hailfinger.devel.2006 at gmx.net Wed May 12 07:16:25 2010 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 12 May 2010 07:16:25 +0200 Subject: [coreboot] flashrom command line syntax change Message-ID: <4BEA39A9.7040403@gmx.net> Hi, [please followup to flashrom at flashrom.org] since I didn't get any answers except "hmm..." on IRC, I hope that list feedback will be more verbose. In the past, flashrom served one purpose (developers writing LinuxBIOS images or parts thereof to onboard flash), but nowadays it can handle external programmers, graphics/network/storage cards and other hardware as well. Given that the flashrom user base is growing rapidly especially among less technically inclined people, we changed the flashrom command line interface in various ways to eliminate nasty surprises. The flashrom 0.9.2 release is impending (only one small bugfix and one big frontend/documentation patch left), and this is why I'd like comments about the following change: -r and -w and -v currently take a filename argument, but that filename can be anywhere on the command line. Examples: flashrom -p dummy backup.rom -r flashrom -rp dummy backup.rom flashrom -rV backup.rom flashrom -p dummy -r backup.rom This flashrom behaviour is confusing and contradicts the man page which says that -r/-w/-v are followed by a filename. Besides that, all other options with arguments want their arguments directly after the option. I posted a patch which will make the accepted command line syntax conform to the man page, but I'd like to hear about any problems this change may cause. The patch is at http://patchwork.coreboot.org/patch/1298/ (click on "patch" to download it in raw form) and applies cleanly against latest flashrom from svn. Tests of current svn flashrom with the patch applied are really appreciated, and feedback about the interface change will be taken seriously. Regards, Carl-Daniel -- http://www.hailfinger.org/ From anders at jenbo.dk Wed May 12 12:17:39 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Wed, 12 May 2010 12:17:39 +0200 Subject: [coreboot] =?utf-8?q?Indtast_Bcc__Preview=3A_SECC_Pentium_2/3_use?= =?utf-8?q?rs_are_gonna_love_this?= Message-ID: Yay this is just what I have been hoping for. Mvh Anders ----- Reply message ----- Fra: "Keith Hui" Dato: ons., maj 12, 2010 03:53 Emne: [coreboot] Preview: SECC Pentium 2/3 users are gonna love this Til: See this boot log: http://coreboot.pastebin.com/rdmwwvha I have done the 72oz steak ;-P that is porting the L2 enabling code from coreboot v1 to current trunk, made much slimmer by being able to put it post-raminit. The CPU in question is a Pentium III 600MHz, Katmai core, 512KB cache. Tell me if I am headed the right direction. Patch to come soonish. Enjoy Keith PS. Oh by the way... [root at ojisan ~]# cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 7 model name : Pentium III (Katmai) stepping : 3 cpu MHz : 601.352 cache size : 512 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 2 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pse36 mmx fxsr sse up bogomips : 1202.70 clflush size : 32 power management: [root at ojisan ~]# -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From patrick.georgi at coresystems.de Wed May 12 12:49:47 2010 From: patrick.georgi at coresystems.de (Patrick Georgi) Date: Wed, 12 May 2010 12:49:47 +0200 Subject: [coreboot] [PATCH] Wyse S50 cleanup In-Reply-To: <201005120047.49057.njacobs8@hetnet.nl> References: <201005120047.49057.njacobs8@hetnet.nl> Message-ID: <4BEA87CB.9080407@coresystems.de> Am 12.05.2010 00:47, schrieb Nils: > This patch cleanes up the Wyse S50 port and unifies the memmory regions > with Geode LX , adds gpl2 headers plus some white space fixes. > > This is build and boot tested.(of course vsa loading is stil not fixed,it now > runs forever with :"Oops, exception 13 while executing option rom") > > Signed-off-by: Nils Jacobs > > Hi Stefan, > I hope this is what you had in mind regarding the GPLv2 headers? > > Thanks,Nils. > In Kconfig: +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. We usually use exactly version 2, not 2 plus whatever the FSF might come up with in future. The other files already use the "version 2 only" verbage. +config RAMBASE + hex + default 0x4000 + depends on BOARD_WYSE_S50 Is that necessary? If so, we should fix the reason. RAMBASE below 1MB is going to go away as soon as the remaining issues are fixed. Everything else is Acked-by: Patrick Georgi From knuku at gap.upv.es Wed May 12 13:04:31 2010 From: knuku at gap.upv.es (Knut Kujat) Date: Wed, 12 May 2010 13:04:31 +0200 Subject: [coreboot] H8QME 128GB RAM not Booting Message-ID: <4BEA8B3F.7080501@gap.upv.es> Hi, I have a board here with 128GB Ram (16*8GB) and it won't boot. It hangs at "Copying data from cache to RAM -- switching to use RAM as stack...". So at least ram initialization is done, but why does it stop booting? Some values I have to increment in order to use more RAM? Thanks, Knut Kujat. From joe at settoplinux.org Wed May 12 13:18:11 2010 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 12 May 2010 07:18:11 -0400 Subject: [coreboot] Preview: SECC Pentium 2/3 users are gonna love this In-Reply-To: References: Message-ID: <5cca3cc6efeb25b2c7507370a545fa4b@imap.1and1.com> On Tue, 11 May 2010 21:53:29 -0400, Keith Hui wrote: > See this boot log: http://coreboot.pastebin.com/rdmwwvha > > I have done the 72oz steak ;-P that is porting the L2 enabling code > from coreboot v1 to current trunk, made much slimmer by being able to > put it post-raminit. > > The CPU in question is a Pentium III 600MHz, Katmai core, 512KB cache. > Tell me if I am headed the right direction. > > Patch to come soonish. > > Enjoy > Keith > > PS. Oh by the way... > > [root at ojisan ~]# cat /proc/cpuinfo > processor : 0 > vendor_id : GenuineIntel > cpu family : 6 > model : 7 > model name : Pentium III (Katmai) > stepping : 3 > cpu MHz : 601.352 > cache size : 512 KB > fdiv_bug : no > hlt_bug : no > f00f_bug : no > coma_bug : no > fpu : yes > fpu_exception : yes > cpuid level : 2 > wp : yes > flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca > cmov pse36 mmx fxsr sse up > bogomips : 1202.70 > clflush size : 32 > power management: > > [root at ojisan ~]# > Congrats! :-) One question, your bootlog says the cache is only 128k ? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From mylesgw at gmail.com Wed May 12 13:43:22 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 12 May 2010 05:43:22 -0600 Subject: [coreboot] H8QME 128GB RAM not Booting In-Reply-To: <4BEA8B3F.7080501@gap.upv.es> References: <4BEA8B3F.7080501@gap.upv.es> Message-ID: <80BDD8AE9779451BACFD2F54F4D26C8D@chimp> > I have a board here with 128GB Ram (16*8GB) and it won't boot. It hangs > at "Copying data from cache to RAM -- switching to use RAM as stack...". > So at least ram initialization is done, but why does it stop booting? > Some values I have to increment in order to use more RAM? Most likely RAM init didn't work. You could run showallroutes() right before that message and do some basic RAM tests to see. Thanks, Myles From joe.korty at ccur.com Wed May 12 17:12:45 2010 From: joe.korty at ccur.com (Joe Korty) Date: Wed, 12 May 2010 11:12:45 -0400 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops Message-ID: <20100512151245.GA14873@tsunami.ccur.com> Put a 1 msec watchdog on the mcp55's codec status-wait loops. This 'fixes' a coreboot lockup I saw on my SuperMicro H8DME-2 with AMD 2222 Processors installed. For some reason the codec is being found but the subsequent initialization sequence is not able to initialize the device. Hopefully a 1 msec watchdog is long enough for a found codec. If not it can be made longer but hopefully it can be kept much shorter than 1 second as excessively long timeouts make it difficult to use coreboot as a 'quick boot' mechanism. Index: trunk/src/southbridge/nvidia/mcp55/mcp55_aza.c =================================================================== --- trunk.orig/src/southbridge/nvidia/mcp55/mcp55_aza.c 2010-05-12 06:33:16.000000000 -0400 +++ trunk/src/southbridge/nvidia/mcp55/mcp55_aza.c 2010-05-12 07:05:51.000000000 -0400 @@ -173,16 +173,28 @@ int i; /* 1 */ + i = 100; /* 1 msec watchdog */ do { + udelay(10); dword = read32(base + 0x68); - } while (dword & 1); + } while ((dword & 1) && --i); + if (!i) { + printk(BIOS_WARNING, "1: codec(%08x,%d) timed out. Not set up.\n", base, addr); + return; + } dword = (addr<<28) | 0x000f0000; write32(base + 0x60, dword); + i = 100; /* 1 msec watchdog */ do { + udelay(10); dword = read32(base + 0x68); - } while ((dword & 3)!=2); + } while (((dword & 3) != 2) && --i); + if (!i) { + printk(BIOS_WARNING, "2: codec(%08x,%d) timed out. Not set up.\n", base, addr); + return; + } dword = read32(base + 0x64); From buurin at gmail.com Wed May 12 17:48:57 2010 From: buurin at gmail.com (Keith Hui) Date: Wed, 12 May 2010 11:48:57 -0400 Subject: [coreboot] Preview: SECC Pentium 2/3 users are gonna love this In-Reply-To: <5cca3cc6efeb25b2c7507370a545fa4b@imap.1and1.com> References: <5cca3cc6efeb25b2c7507370a545fa4b@imap.1and1.com> Message-ID: Yes, the debug output from the L2 init code does say 128K, but /proc/cpuinfo reports 512K. This is where I'd like some expert opinions. Thanks Keith On Wed, May 12, 2010 at 7:18 AM, Joseph Smith wrote: > > > > On Tue, 11 May 2010 21:53:29 -0400, Keith Hui wrote: >> See this boot log: http://coreboot.pastebin.com/rdmwwvha >> >> I have done the 72oz steak ;-P that is porting the L2 enabling code >> from coreboot v1 to current trunk, made much slimmer by being able to >> put it post-raminit. >> >> The CPU in question is a Pentium III 600MHz, Katmai core, 512KB cache. >> Tell me if I am headed the right direction. >> >> Patch to come soonish. >> >> Enjoy >> Keith >> >> PS. Oh by the way... >> >> [root at ojisan ~]# cat /proc/cpuinfo >> processor ? ? ? : 0 >> vendor_id ? ? ? : GenuineIntel >> cpu family ? ? ?: 6 >> model ? ? ? ? ? : 7 >> model name ? ? ?: Pentium III (Katmai) >> stepping ? ? ? ?: 3 >> cpu MHz ? ? ? ? : 601.352 >> cache size ? ? ?: 512 KB >> fdiv_bug ? ? ? ?: no >> hlt_bug ? ? ? ? : no >> f00f_bug ? ? ? ?: no >> coma_bug ? ? ? ?: no >> fpu ? ? ? ? ? ? : yes >> fpu_exception ? : yes >> cpuid level ? ? : 2 >> wp ? ? ? ? ? ? ?: yes >> flags ? ? ? ? ? : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca >> cmov pse36 mmx fxsr sse up >> bogomips ? ? ? ?: 1202.70 >> clflush size ? ?: 32 >> power management: >> >> [root at ojisan ~]# >> > Congrats! :-) > > One question, your bootlog says the cache is only 128k ? > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > > From joe.korty at ccur.com Wed May 12 17:59:10 2010 From: joe.korty at ccur.com (Joe Korty) Date: Wed, 12 May 2010 11:59:10 -0400 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: References: <20100512151245.GA14873@tsunami.ccur.com> Message-ID: <20100512155910.GA18804@tsunami.ccur.com> On Wed, May 12, 2010 at 11:54:23AM -0400, Myles Watson wrote: > > > > Put a 1 msec watchdog on the mcp55's codec status-wait > > loops. > > For some reason the codec is being found but the > > subsequent initialization sequence is not able to > > initialize the device. > > I wonder if the address is somehow wrong, or not routed correctly. > > > + if (!i) { > > + printk(BIOS_WARNING, "2: codec(%08x,%d) timed out. Not set > > up.\n", base, addr); > > + return; > > + } > > What's the output when it fails? It's ..... PCI: 00:06.1 init base = 0xfc140000 codec_mask = 01 2: codec(fc140000,0) timed out. Not set up. PCI: 00:08.0 init Regards, Joe From mylesgw at gmail.com Wed May 12 17:54:23 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 12 May 2010 09:54:23 -0600 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <20100512151245.GA14873@tsunami.ccur.com> References: <20100512151245.GA14873@tsunami.ccur.com> Message-ID: > Put a 1 msec watchdog on the mcp55's codec status-wait > loops. > For some reason the codec is being found but the > subsequent initialization sequence is not able to > initialize the device. I wonder if the address is somehow wrong, or not routed correctly. > + if (!i) { > + printk(BIOS_WARNING, "2: codec(%08x,%d) timed out. Not set > up.\n", base, addr); > + return; > + } What's the output when it fails? Thanks, Myles From joe at settoplinux.org Wed May 12 18:16:28 2010 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 12 May 2010 12:16:28 -0400 Subject: [coreboot] Preview: SECC Pentium 2/3 users are gonna love this In-Reply-To: References: <5cca3cc6efeb25b2c7507370a545fa4b@imap.1and1.com> Message-ID: <3c91e2bebf4b91e038d760c20f10ec7b@imap.1and1.com> On Wed, 12 May 2010 11:48:57 -0400, Keith Hui wrote: > Yes, the debug output from the L2 init code does say 128K, but > /proc/cpuinfo reports 512K. This is where I'd like some expert > opinions. > Sure, but we need to see the code to give an opinion :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From mylesgw at gmail.com Wed May 12 18:19:52 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 12 May 2010 10:19:52 -0600 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <20100512155910.GA18804@tsunami.ccur.com> References: <20100512151245.GA14873@tsunami.ccur.com> <20100512155910.GA18804@tsunami.ccur.com> Message-ID: <027CB1C8431F43639C99E565A17A9861@chimp> > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of Joe Korty > Sent: Wednesday, May 12, 2010 9:59 AM > To: Myles Watson > Cc: coreboot at coreboot.org > Subject: Re: [coreboot] [PATCH] watchdog mcp55's codec initialization > loops > > On Wed, May 12, 2010 at 11:54:23AM -0400, Myles Watson wrote: > > > > > > > Put a 1 msec watchdog on the mcp55's codec status-wait > > > loops. > > > For some reason the codec is being found but the > > > subsequent initialization sequence is not able to > > > initialize the device. > > > > I wonder if the address is somehow wrong, or not routed correctly. > > > > > + if (!i) { > > > + printk(BIOS_WARNING, "2: codec(%08x,%d) timed out. Not set > > > up.\n", base, addr); > > > + return; > > > + } > > > > What's the output when it fails? > > > It's ..... > > PCI: 00:06.1 init > base = 0xfc140000 > codec_mask = 01 > 2: codec(fc140000,0) timed out. Not set up. > PCI: 00:08.0 init I'd try to figure out if the read is failing. If you print out dword (the read value), is it 0xffffffff (probably not responding to the read)? Earlier in the boot log does it look like fc14 is the correct address for one of the resources for PCI 6.1? Does it get enabled before this in the log? Thanks, Myles From patrick at georgi-clan.de Wed May 12 20:23:21 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 12 May 2010 20:23:21 +0200 Subject: [coreboot] [PATCH]Some more removal of c-includes in AMD code Message-ID: <4BEAF219.90200@georgi-clan.de> Hi, attached patch removes another set of includes from Fam10 romstages: northbridge/amd/amdht/ht_wrapper.c northbridge/amd/amdfam10/raminit_amdmct.c cpu/amd/model_10xxx/fidvid.c pc80/mc146818rtc_early.c are included from within other AMD files now (where they are references). They can later be replaced with header file includes and initobj-linking. Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20100511-amdfam10-cleanup-pt2 URL: From njacobs8 at hetnet.nl Wed May 12 21:44:13 2010 From: njacobs8 at hetnet.nl (Nils) Date: Wed, 12 May 2010 21:44:13 +0200 Subject: [coreboot] [PATCH] Wyse S50 cleanup Message-ID: <201005122144.13218.njacobs8@hetnet.nl> This patch cleanes up the Wyse S50 port and unifies the memmory regions with Geode LX , adds gpl2 headers plus some white space fixes. This is build and boot tested.(of course vsa loading is stil not fixed,it now runs forever with :"Oops, exception 13 while executing option rom") Signed-off-by: Nils Jacobs Hi Patrick, Thanks for the review! Op woensdag 12 mei 2010 12:49:47 schreef u: >In Kconfig: > >+## the Free Software Foundation; either version 2 of the License, or >+## (at your option) any later version. > >We usually use exactly version 2, not 2 plus whatever the FSF might come >up with in future. The other files already use the "version 2 only" verbage. I am sorry about that mistake, i copied it from AMD Rumba. Attached you find a corrected v2 version of the patch. I looked a little at the current trunk and found a "few" other kconfig`s that had the "wrong" GPLv2 header. I hope everybody knows this new rule because the last wrong one is committed two weeks ago! I think often new patches are copied out of trunk. To stop the chance of copying the wrong version, i prepared a little patch for you.(see attachment 2) > > >+config RAMBASE >+ hex >+ default 0x4000 >+ depends on BOARD_WYSE_S50 > >Is that necessary? If so, we should fix the reason. RAMBASE below 1MB is >going to go away as soon as the remaining issues are fixed. This is necessary in rev5542, otherwise the board hangs after ramtest. See attached log.I didn`t test it with rev5543(the new revisions come faster than i can test). :) So i think this is one of the remaining issues. > > >Everything else is >Acked-by: Patrick Georgi Thanks,Nils -------------- next part -------------- A non-text attachment was scrubbed... Name: 5543_s50_cleanup2.patch Type: text/x-patch Size: 11519 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 5543_kconfig_gplv2.patch Type: text/x-patch Size: 47800 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot157.log Type: text/x-log Size: 298 bytes Desc: not available URL: From joe.korty at ccur.com Wed May 12 22:23:39 2010 From: joe.korty at ccur.com (Joe Korty) Date: Wed, 12 May 2010 16:23:39 -0400 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <027CB1C8431F43639C99E565A17A9861@chimp> References: <20100512151245.GA14873@tsunami.ccur.com> <20100512155910.GA18804@tsunami.ccur.com> <027CB1C8431F43639C99E565A17A9861@chimp> Message-ID: <20100512202339.GA31004@tsunami.ccur.com> On Wed, May 12, 2010 at 12:19:52PM -0400, Myles Watson wrote: > I'd try to figure out if the read is failing. If you print out dword (the > read value), is it 0xffffffff (probably not responding to the read)? > Earlier in the boot log does it look like fc14 is the correct address for > one of the resources for PCI 6.1? Does it get enabled before this in the > log? The dword at point the '2: codec(f9f40000,0) timed out' message is 0. The mapped device address (different this time as my PCI card mix has changed) appears to be consistant with the built-in audio device. Raw data: lspci -v: 00:06.1 Audio device: nVidia Corporation MCP55 High Definition Audio (rev a2) Subsystem: Super Micro Computer Inc Unknown device 1511 Flags: 66MHz, fast devsel, IRQ 23 Memory at f9f40000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable - Capabilities: [6c] HyperTransport: MSI Mapping coreboot ttyS0 log: PCI: 00:0f.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:f8000000 size:2000000 align:23 gran:20 limit:febfffff Assigned: PCI: 00:0e.0 20 * [0xf8000000 - 0xf9dfffff] mem Assigned: PCI: 00:06.0 20 * [0xf9e00000 - 0xf9efffff] mem Assigned: PCI: 00:01.3 10 * [0xf9f00000 - 0xf9f3ffff] mem Assigned: PCI: 00:06.1 10 * [0xf9f40000 - 0xf9f43fff] mem Assigned: PCI: 00:01.0 14 * [0xf9f44000 - 0xf9f44fff] mem Assigned: PCI: 00:02.0 10 * [0xf9f45000 - 0xf9f45fff] mem Assigned: PCI: 00:05.0 24 * [0xf9f46000 - 0xf9f46fff] mem Assigned: PCI: 00:05.1 24 * [0xf9f47000 - 0xf9f47fff] mem ... PCI: 00:06.0 assign_resources, bus 1 link: 0 PCI: 00:06.1 10 <- [0x00f9f40000 - 0x00f9f43fff] size 0x00004000 gran 0x0e mem PCI: 00:08.0 10 <- [0x00f9f49000 - 0x00f9f49fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 14 <- [0x000000b030 - 0x000000b037] size 0x00000008 gran 0x03 io PCI: 00:08.0 18 <- [0x00f9f4b100 - 0x00f9f4b1ff] size 0x00000100 gran 0x08 mem ... PCI: 01:05.0 resource base f9e00000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30 PCI: 01:06.0 links 0 child on link 0 NULL PCI: 00:06.1 links 0 child on link 0 NULL PCI: 00:06.1 resource base f9f40000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 10 PCI: 00:08.0 links 0 child on link 0 NULL PCI: 00:08.0 resource base f9f49000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:08.0 resource base b030 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 ... SATA S SATA P PCI: 00:05.2 init SATA S SATA P PCI: 00:06.0 init PCI DOMAIN mem base = 0x00e8000000 [0x50] <-- 0xe8000000 PCI: 00:06.1 init base = 0xf9f40000 codec_mask = 01 2: codec(f9f40000,0) timed out. Not set up. dword = 00000000 PCI: 00:08.0 init MCP55 MAC PHY ID 0x01410c00 PHY ADDR 2 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram From mylesgw at gmail.com Wed May 12 22:38:47 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 12 May 2010 14:38:47 -0600 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <20100512202339.GA31004@tsunami.ccur.com> References: <20100512151245.GA14873@tsunami.ccur.com><20100512155910.GA18804@tsunami.ccur.com><027CB1C8431F43639C99E565A17A9861@chimp> <20100512202339.GA31004@tsunami.ccur.com> Message-ID: > On Wed, May 12, 2010 at 12:19:52PM -0400, Myles Watson wrote: > > I'd try to figure out if the read is failing. If you print out dword > (the > > read value), is it 0xffffffff (probably not responding to the read)? > > Earlier in the boot log does it look like fc14 is the correct address > for > > one of the resources for PCI 6.1? Does it get enabled before this in > the > > log? > > The dword at point the '2: codec(f9f40000,0) timed out' message is 0. > The mapped device address (different this time as my PCI card mix has > changed) appears to be consistant with the built-in audio device. Raw > data: Unfortunately, I don't see an obvious problem. Everything looks good until the failure. Good luck, Myles From oregon.mick at gmail.com Thu May 13 02:17:29 2010 From: oregon.mick at gmail.com (Mick Reed) Date: Wed, 12 May 2010 17:17:29 -0700 Subject: [coreboot] Preview: SECC Pentium 2/3 users are gonna love this In-Reply-To: References: <5cca3cc6efeb25b2c7507370a545fa4b@imap.1and1.com> <3c91e2bebf4b91e038d760c20f10ec7b@imap.1and1.com> Message-ID: I'd like to see your work as well, I have a PII SECC board here with a 440BX. From rminnich at gmail.com Thu May 13 03:32:20 2010 From: rminnich at gmail.com (ron minnich) Date: Wed, 12 May 2010 18:32:20 -0700 Subject: [coreboot] Preview: SECC Pentium 2/3 users are gonna love this In-Reply-To: References: <5cca3cc6efeb25b2c7507370a545fa4b@imap.1and1.com> <3c91e2bebf4b91e038d760c20f10ec7b@imap.1and1.com> Message-ID: When we were debugging this 10 (!) years ago, we used the lmbench memory test tool to really make sure that the cache was what we thought it was. That tool will really show you very nice performance information and you can really see the delta in memory time when you fall out of the cache. In fact it's how I first figured out that L2 was not enabled at all ... ron From peter at stuge.se Thu May 13 05:06:35 2010 From: peter at stuge.se (Peter Stuge) Date: Thu, 13 May 2010 05:06:35 +0200 Subject: [coreboot] [PATCH]Some more removal of c-includes in AMD code In-Reply-To: <4BEAF219.90200@georgi-clan.de> References: <4BEAF219.90200@georgi-clan.de> Message-ID: <20100513030635.15555.qmail@stuge.se> Patrick Georgi wrote: > attached patch removes another set of includes from Fam10 romstages: > > northbridge/amd/amdht/ht_wrapper.c > northbridge/amd/amdfam10/raminit_amdmct.c > cpu/amd/model_10xxx/fidvid.c > pc80/mc146818rtc_early.c > > are included from within other AMD files now (where they are > references). They can later be replaced with header file includes and > initobj-linking. > > > Signed-off-by: Patrick Georgi Acked-by: Peter Stuge From joop_boonen at web.de Thu May 13 12:31:34 2010 From: joop_boonen at web.de (Joop Boonen) Date: Thu, 13 May 2010 12:31:34 +0200 Subject: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114) In-Reply-To: <20100507211147.29282.qmail@stuge.se> References: <9fcf30ec4fe94654bd26b1ac9822bf75.squirrel@www.boonen.name> <074aeb78763ef5fb4e896f43a334b2f4.squirrel@www.boonen.name> <665f02730557c26a7d0472538ec8d828.squirrel@www.boonen.name> <20100507211147.29282.qmail@stuge.se> Message-ID: On Fri, May 7, 2010 11:11 pm, Peter Stuge wrote: > Joop Boonen wrote: >> >> I have an issue with FILO the disk at ata-0 isn't seen. >> >> I've been trying some more. I've used the old IDE in FILO. It now >> recognises the drive connected to the SIL3114. But still not the >> ATA drive. > > Curious. Maybe I can ask you to try even older code? I did a bunch of > work on the IDE driver in FILO 0.5 but haven't kept up with current > code. If you'd like to try the latest 0.5: > > svn co svn://coreboot.org/filo/branches/filo-0.5 > > Please disable the GRUB junk (comment out USE_GRUB), enable > filesystems you need, and enable DEBUG_BLOCKDEV, DEBUG_PCI, and > DEBUG_IDE. > I've just tested with filo-0.50. The IDE drives aren't seen. I've attached the log. > > Thanks. > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- A non-text attachment was scrubbed... Name: session_20100513.log Type: text/x-log Size: 66515 bytes Desc: not available URL: From joop_boonen at web.de Thu May 13 12:33:40 2010 From: joop_boonen at web.de (Joop Boonen) Date: Thu, 13 May 2010 12:33:40 +0200 Subject: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114) Message-ID: On Fri, May 7, 2010 11:11 pm, Peter Stuge wrote: > Joop Boonen wrote: >> >> I have an issue with FILO the disk at ata-0 isn't seen. >> >> I've been trying some more. I've used the old IDE in FILO. It now recognises the drive connected to the SIL3114. But still not the ATA drive. > > Curious. Maybe I can ask you to try even older code? I did a bunch of work on the IDE driver in FILO 0.5 but haven't kept up with current code. If you'd like to try the latest 0.5: > > svn co svn://coreboot.org/filo/branches/filo-0.5 > > Please disable the GRUB junk (comment out USE_GRUB), enable > filesystems you need, and enable DEBUG_BLOCKDEV, DEBUG_PCI, and > DEBUG_IDE. > I've just tested with filo-0.50. The IDE drives aren't seen. I've attached the log. > > Thanks. > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- A non-text attachment was scrubbed... Name: session_20100513.log Type: text/x-log Size: 66515 bytes Desc: not available URL: From stefan.reinauer at coresystems.de Thu May 13 16:42:40 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Thu, 13 May 2010 16:42:40 +0200 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <20100512151245.GA14873@tsunami.ccur.com> References: <20100512151245.GA14873@tsunami.ccur.com> Message-ID: <4BEC0FE0.8080409@coresystems.de> On 5/12/10 5:12 PM, Joe Korty wrote: > Put a 1 msec watchdog on the mcp55's codec status-wait > loops. > > This 'fixes' a coreboot lockup I saw on my SuperMicro > H8DME-2 with AMD 2222 Processors installed. > > For some reason the codec is being found but the > subsequent initialization sequence is not able to > initialize the device. > > Hopefully a 1 msec watchdog is long enough for a found > codec. If not it can be made longer but hopefully it > can be kept much shorter than 1 second as excessively > long timeouts make it difficult to use coreboot as a > 'quick boot' mechanism. Hi Joe, the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a while ago and now I ported my version of the Azalia code to MCP55 / H8DME (assuming that's the board target you use for the H8DME-2) Can you please see if this is any better than before? It's likely that the verb table won't match the codec used on that board, but there only was a single codec in the mcp55 driver and the used codec is usually mainboard dependent, not chipset dependent. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: mcp55_azalia_fix.diff URL: From joe.korty at ccur.com Thu May 13 17:08:22 2010 From: joe.korty at ccur.com (Joe Korty) Date: Thu, 13 May 2010 11:08:22 -0400 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <4BEC0FE0.8080409@coresystems.de> References: <20100512151245.GA14873@tsunami.ccur.com> <4BEC0FE0.8080409@coresystems.de> Message-ID: <20100513150822.GA16268@tsunami.ccur.com> On Thu, May 13, 2010 at 10:42:40AM -0400, Stefan Reinauer wrote: > the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a > while ago and now I ported my version of the Azalia code to MCP55 / > H8DME (assuming that's the board target you use for the H8DME-2) > Can you please see if this is any better than before? It's likely that > the verb table won't match the codec used on that board, but there only > was a single codec in the mcp55 driver and the used codec is usually > mainboard dependent, not chipset dependent. It works!!! But I didn't hear a beep during coreboot. Was I supposed to? Regards, and thanks, Joe From stefan.reinauer at coresystems.de Thu May 13 17:40:36 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Thu, 13 May 2010 17:40:36 +0200 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <20100513150822.GA16268@tsunami.ccur.com> References: <20100512151245.GA14873@tsunami.ccur.com> <4BEC0FE0.8080409@coresystems.de> <20100513150822.GA16268@tsunami.ccur.com> Message-ID: <4BEC1D74.50302@coresystems.de> On 5/13/10 5:08 PM, Joe Korty wrote: > On Thu, May 13, 2010 at 10:42:40AM -0400, Stefan Reinauer wrote: > >> the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a >> while ago and now I ported my version of the Azalia code to MCP55 / >> H8DME (assuming that's the board target you use for the H8DME-2) >> Can you please see if this is any better than before? It's likely that >> the verb table won't match the codec used on that board, but there only >> was a single codec in the mcp55 driver and the used codec is usually >> mainboard dependent, not chipset dependent. >> > > It works!!! > But I didn't hear a beep during coreboot. Was I supposed to? > No, no beeps... The driver just initializes the codec. If someone had a nice piece of code to output a sample on azalia devices, I think we should make it an option. I looked at alsa some time ago but found it less than trivial to extract the info useful for us. Could you please send a log file containing the output of the new azalia driver? Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From nowens2 at illinois.edu Thu May 13 16:01:13 2010 From: nowens2 at illinois.edu (Nathan Owens) Date: Thu, 13 May 2010 09:01:13 -0500 Subject: [coreboot] problem compiling Coreboot+SeaBIOS+VGA BIOS Message-ID: <4BEC0629.8040102@illinois.edu> I'm having a bit of a problem compiling Coreboot+SeaBIOS+VGA BIOS Here's my output. Any ideas? GEN build.h CC romstage.inc src/northbridge/amd/amdk8/early_ht.c:5: warning: ?enumerate_ht_chain? defined but not used src/northbridge/amd/amdk8/setup_resource_map.c:3: warning: ?setup_resource_map_offset? defined but not used src/northbridge/amd/amdk8/setup_resource_map.c:39: warning: ?setup_resource_map_x_offset? defined but not used src/northbridge/amd/amdk8/coherent_ht.c:208: warning: ?fill_row? defined but not used src/northbridge/amd/amdk8/raminit_f_dqs.c:1720: warning: ?set_top_mem_ap? defined but not used src/northbridge/amd/amdk8/raminit_f_dqs.c:1813: warning: ?wait_till_sysinfo_in_ram? defined but not used src/cpu/amd/model_fxx/init_cpus.c:182: warning: ?wait_all_aps_started? defined but not used POST romstage.inc GEN romstage/crt0.S CC mainboard/asus/m2v-mx_se/crt0.s CC mainboard/asus/m2v-mx_se/crt0.initobj.o CC console/console.initobj.o LINK coreboot.romstage HOSTCC util/sconfig/sconfig (link) SCONFIG mainboard/asus/m2v-mx_se/devicetree.cb CC mainboard/asus/m2v-mx_se/static.o CC lib/version.o CC console/console.o AR coreboot.a CC coreboot_ram.o CC coreboot_ram build/coreboot_ram.o: In function `__wrap___umoddi3': (.text+0x12583): undefined reference to `__umoddi3' build/coreboot_ram.o: In function `__wrap___moddi3': (.text+0x1258e): undefined reference to `__moddi3' build/coreboot_ram.o: In function `__wrap___udivdi3': (.text+0x12599): undefined reference to `__udivdi3' build/coreboot_ram.o: In function `__wrap___divdi3': (.text+0x125a4): undefined reference to `__divdi3' collect2: ld returned 1 exit status make: *** [build/coreboot_ram] Error 1 From stefan.reinauer at coresystems.de Thu May 13 17:45:04 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Thu, 13 May 2010 17:45:04 +0200 Subject: [coreboot] problem compiling Coreboot+SeaBIOS+VGA BIOS In-Reply-To: <4BEC0629.8040102@illinois.edu> References: <4BEC0629.8040102@illinois.edu> Message-ID: <4BEC1E80.9070808@coresystems.de> On 5/13/10 4:01 PM, Nathan Owens wrote: > I'm having a bit of a problem compiling Coreboot+SeaBIOS+VGA BIOS > > Here's my output. Any ideas? > > GEN build.h > CC romstage.inc > src/northbridge/amd/amdk8/early_ht.c:5: warning: ?enumerate_ht_chain? > defined but not used > src/northbridge/amd/amdk8/setup_resource_map.c:3: warning: > ?setup_resource_map_offset? defined but not used > src/northbridge/amd/amdk8/setup_resource_map.c:39: warning: > ?setup_resource_map_x_offset? defined but not used > src/northbridge/amd/amdk8/coherent_ht.c:208: warning: ?fill_row? > defined but not used > src/northbridge/amd/amdk8/raminit_f_dqs.c:1720: warning: > ?set_top_mem_ap? defined but not used > src/northbridge/amd/amdk8/raminit_f_dqs.c:1813: warning: > ?wait_till_sysinfo_in_ram? defined but not used > src/cpu/amd/model_fxx/init_cpus.c:182: warning: ?wait_all_aps_started? > defined but not used > POST romstage.inc > GEN romstage/crt0.S > CC mainboard/asus/m2v-mx_se/crt0.s > CC mainboard/asus/m2v-mx_se/crt0.initobj.o > CC console/console.initobj.o > LINK coreboot.romstage > HOSTCC util/sconfig/sconfig (link) > SCONFIG mainboard/asus/m2v-mx_se/devicetree.cb > CC mainboard/asus/m2v-mx_se/static.o > CC lib/version.o > CC console/console.o > AR coreboot.a > CC coreboot_ram.o > CC coreboot_ram > build/coreboot_ram.o: In function `__wrap___umoddi3': > (.text+0x12583): undefined reference to `__umoddi3' > build/coreboot_ram.o: In function `__wrap___moddi3': > (.text+0x1258e): undefined reference to `__moddi3' > build/coreboot_ram.o: In function `__wrap___udivdi3': > (.text+0x12599): undefined reference to `__udivdi3' > build/coreboot_ram.o: In function `__wrap___divdi3': > (.text+0x125a4): undefined reference to `__divdi3' > collect2: ld returned 1 exit status > make: *** [build/coreboot_ram] Error 1 Seems like your compiler is broken and can't find libgcc. Use the one built by the toolchain in coreboot/util/crossgcc. $ i386-elf-gcc --print-libgcc /opt/cross/lib/gcc/i386-elf/4.4.2/libgcc.a If it just prints libgcc.a you are missing libgcc.a Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From joe.korty at ccur.com Thu May 13 18:56:27 2010 From: joe.korty at ccur.com (Joe Korty) Date: Thu, 13 May 2010 12:56:27 -0400 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <4BEC1D74.50302@coresystems.de> References: <20100512151245.GA14873@tsunami.ccur.com> <4BEC0FE0.8080409@coresystems.de> <20100513150822.GA16268@tsunami.ccur.com> <4BEC1D74.50302@coresystems.de> Message-ID: <20100513165627.GA24079@tsunami.ccur.com> On Thu, May 13, 2010 at 11:40:36AM -0400, Stefan Reinauer wrote: >On 5/13/10 5:08 PM, Joe Korty wrote: >> On Thu, May 13, 2010 at 10:42:40AM -0400, Stefan Reinauer wrote: >> >>> the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a >>> while ago and now I ported my version of the Azalia code to MCP55 / >>> H8DME (assuming that's the board target you use for the H8DME-2) >>> Can you please see if this is any better than before? It's likely that >>> the verb table won't match the codec used on that board, but there only >>> was a single codec in the mcp55 driver and the used codec is usually >>> mainboard dependent, not chipset dependent. >> >> It works!!! >> But I didn't hear a beep during coreboot. Was I supposed to? > > No, no beeps... The driver just initializes the codec. > > If someone had a nice piece of code to output a sample on azalia > devices, I think we should make it an option. I looked at alsa some time > ago but found it less than trivial to extract the info useful for us. > > Could you please send a log file containing the output of the new azalia > driver? Sure. Here it is.... Regards, Joe -------------------------------------------------------------------- INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... coreboot-4.0-r5543M Thu May 13 08:55:53 EDT 2010 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=00 Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=00 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done core0 started: 01 started ap apicid: * AP 01started * AP 03started SBLink=02 NC node|link=02 begin msr fid, vid 31081208080c020c end msr fid, vid 31081208080c020c entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0xca, unfiltered freq_cap=0x8075 pos=0xca, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num:01 SMBus controller enabled Ram1.00 setting up CPU 00 northbridge registers done. Ram1.01 setting up CPU 01 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cee34 Enabling dual channel memory Registered 333MHz 333MHz RAM end at 0x00200000 kB Ram2.01 sdram_set_spd_registers: paramx :000cee34 Enabling dual channel memory Registered 333MHz 333MHz RAM end at 0x00400000 kB Ram3 ECC enabled ECC enabled Initializing memory: done Initializing memory: done RAM end at 0x00500000 kB set DQS timing:RcvrEn:Pass1: 00 done set DQS timing:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce9a0 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 TrainDQSPos: MutualCSPassW[48] :000ce874 done set DQS timing:RcvrEn:Pass2: 00 done Total DQS Training : tsc [00]=0000001bc57f58f7 Total DQS Training : tsc [01]=0000001bc6b671be Total DQS Training : tsc [02]=0000001c0b0d9cce Total DQS Training : tsc [03]=0000001c0c187dce Ram4 v_esp=000ceea8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done oading stage CiOmDaEg eI.N eROChMe cAkN DC BRFUSN hOeNa dNeOrD Ea:t fffe0f1f 0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram mtaTgrea:i nlDoQaSdRidnWgr Pfoasl:l bbaucfk_/ac:or0e0b0ocoet9_br0a @ T0rxa1i0n0D0Q0S0P o(s4:0 9M6u0t0u ablyCtSePsa)s,s We[n4t8r]y :@0 000xc1e0800040 TrainDQSPos: MutualCSPassW[48] :000ce884 TrainDQSPos: MutualCSPassW[48] :000ce884 utage: Tdroanien DlQoSaPdoisn:g .M 0tJuuamlpCiSnPga stsoW [i4m8a]g e:.0 o0ccoer8e8b4o t-4.0-r5543M Thu May 13 08:55:53 EDT 2010 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources :NP: T0r0a2ien.D1Q:S Peonsa:b lMeudt u0a,l C2S PraesssoWu[r4c8e]s e0P0N0Pc:e 808042 .2: enabled 1, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources I2C: 00:48: enabled 0, 0 resources l2C: 00:49: enablTerda i0n,D Q0S Proess:o uMructeusa ,CIS2PCa:s s0W0[:4581]: :e0n0a0bclee8d8 41 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:02.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:05.1: enabled 1, 0 resources PCI: 00:05.2: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:06.1: enabled 1, 0 resources PCI: 00:08.0: enabled 1, 0 resources aCI: 00:09.0: enableTdr a1i,n D0Q SrPeosso:u rMcuetsu 1lPCCSIP:a s0s0W:[04a8.]0 :: 0e0n0acbel8e8d4 , 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:04.1: enabled 1, 0 resources PCI: 00:0b.0: enabled 1, 0 resources PCI: 00:0c.0: enabled 1, 0 resources PCI: 00:0d.0: enabled 1, 0 resources PCI: 00:0e.0: enabled 1, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources lCI: 00:18.2: enablTerda i1n,D Q0S Proess:o uMructeusa CPSCPIa:s s0W0[:4188]. 3::0 0e0ncaeb8l8e4d 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources ] PNP: 00T2rea.i2n:D QeSnPaobsl:e dM u1t,u a2l CrSePsaosusrWc[e4s8 0 : 0 0 0PcNeP8:8 40 2e.3: enabled 0, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources I2C: 00:48: enabled 0, 0 resources I2C: 00:49: enabled 0, 0 resources I2C: 00:51: enabled 1, 0 resources T r a iPnCDIQ:S P0o0s::0 2M.u0t:u aelnCaSbPlaesds W1[,4 80] r:e0s0o0ucrec8e8s4 PCI: 00:02.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:05.1: enabled 1, 0 resources PCI: 00:05.2: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:06.1: enabled 1, 0 resources PCI: 00:08.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources u PCI: 00:00.0: enabled 1T,r a0i nrDeQsSoPuorsc:e sM t u a l CPSCPIa:s s0W0[:4080]. 1::0 0e0ncaeb8l8e4d 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:04.1: enabled 1, 0 resources PCI: 00:0b.0: enabled 1, 0 resources PCI: 00:0c.0: enabled 1, 0 resources PCI: 00:0d.0: enabled 1, 0 resources PCI: 00:0e.0: enabled 1, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources Scan_static_Tbruasi nfDoQrS PRooso:t MDuetvuiacleC bPAaPsIsCW_[C4L8U]S T:E0R0:0 c0e 8e8n4a led PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled malloc Enter, size 1092, free_mem_ptr 00160000 malloc 00160000 CPU: APIC: 01 enabled malloc Enter, size 1092, free_mem_ptr 00160444 malloc 00160444 PCI: 00:19.0 [1022/1100] bus ops PCI: 00:19.0 [1022/1100] enabled malloc Enter, size 1092, free_mem_ptr 00160888 malloc 00160888 PCI: 00:19.1 [1022/1101] enabled malloc TErnatienrD,Q SsPiozse: 1M0u9t2u,a lfCrSePea_smseWm[_4p8t]r :0000106c0ec8c8c4 malloc 00160ccc PCI: 00:19.2 [1022/1102] enabled malloc Enter, size 1092, free_mem_ptr 00161110 malloc 00161110 PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled PCI: 00:19.3 siblings=1 malloc Enter, size 1092, free_mem_ptr 00161554 malloc 00161554 CPU: APIC: 02 enabled malloc Enter, size 1092, free_mem_ptr 00161998 malloc 00161998 CPU: APIC: 03 enabled PCI_DOMAIN: 0000 scanning... sCI: pTcria_isncDaQnS_Pbouss: fMourt ubaulsC S0P0a 2sPWC[I4:8 ]0 0::01080.c0e 8[8140 2/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled PCI: Using configuration type 1 PCI: 00:00.0 [10de/0369] ops CI: 00:00.0 [10de/03T6r9a]i neDnQaSbPloesd: 4MCuatpuaabliClSiPtays:s Wt[y4p8e] 0:x00080 c at e 808x44 flags: 0x01e0 PCI: 00:00.0 count: 000f static_count: 0010 PCI: 00:00.0 [10de/0369] enabled next_unitid: 0010 PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [10de/0369] enabled PCI: 00:01.0 [10de/0364] bus ops PCI: 00:01.0 [10de/0364] enabled PCI: 00:01.1 [10de/0368] bus ops PCI: 00:01.1 [10de/0368] enabled malloc Enter, size 1092, free_mem_ptr 00161ddc malloc 00161ddc PCI: 00:01.2 [10de/036a] enabled malTlroaci nEDnQtSePro,s :s iMzuet u1a0l9C2S,P afsrseWe[_4m8e]m _:p0t0r0 c0e0818242 20 malloc 00162220 PCI: 00:01.3 [10de/036b] enabled PCI: 00:02.0 [10de/036c] ops PCI: 00:02.0 [10de/036c] enabled PCI: 00:02.1 [10de/036d] ops PCI: 00:02.1 [10de/036d] enabled PCI: 00:04.0 [10de/036e] ops PCI: 00:04.0 [10de/036e] enabled PCI: 00:05.0 [10de/037f] ops PCI: 00:05.0 [10de/037f] enabled PCI: 00:05.1 [10de/037f] ops PCI: 00:05.1 [10de/037f] enabled PCI: 00:05.2 [10de/037f] ops sCI: 00:05T.r2a i[n1D0QdSeP/o0s3:7 fM]u teunaalbClSePda dsWPC[I4:8 ]0 0::00060.c0e 8[8140 e/0370] bus ops PCI: 00:06.0 [10de/0370] enabled PCI: 00:06.1 [10de/0371] ops PCI: 00:06.1 [10de/0371] enabled PCI: 00:08.0 [10de/0373] ops PCI: 00:08.0 [10de/0373] enabled PCI: 00:09.0 [10de/0373] ops PCI: 00:09.0 [10de/0373] enabled PCI: 00:0a.0 [10de/0376] bus ops PCI: 00:0a.0 [10de/0376] enabled PCI: 00:0b.0 [10de/0374] bus ops PCI: 00:0b.0 [10de/0374] enabled PCI: 00:0c.0 [10de/0374] bus ops :CTIr:a i0n0D:Q0ScP.o0s :[ 1M0udteu/a0l3C7S4P]a sesnWa[b4l8e]d 000PC0Ic:e 80804: d.0 [10de/0378] bus ops PCI: 00:0d.0 [10de/0378] enabled PCI: 00:0e.0 [10de/0375] bus ops PCI: 00:0e.0 [10de/0375] enabled PCI: 00:0f.0 [10de/0377] bus ops PCI: 00:0f.0 [10de/0377] enabled scan_static_bus for PCI: 00:01.0 PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.1 smbus: PCI: 00:01.1[0]->I2C: 01:48 disabled smbus: PCI: 00:01.1[0]->I2C: 01:49 disabled smbus: PCI: 00:01.1[1]->I2C: 02:51 enabled scan_static_bus for PCI: 00:01.1 done do_pci_scan_bridge for PCI: 00:06.0 PCI: pci_scan_bus for bus 01 malloc Enter, size 1092, free_mem_ptr 00162664 malloc 00162664 PCI: 01:05.0 [1002/515e] enabled PCI: Static device PCI: 01:06.0 not found, disabling it. PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:0a.0 PCI: pci_scan_bus for bus 02 Capability: type 0x10 @ 0x40 Capability: type 0x07 @ 0x54 PCI: 02:00.0 subordinate bus PCI-X PCI: 02:00.0 [1033/0125] enabled Capability: type 0x10 @ 0x40 Capability: type 0x07 @ 0x54 PCI: 02:00.1 subordinate bus PCI-X PCI: 02:00.1 [1033/0125] enabled Capability: type 0x10 @ 0x40 Capability: type 0x07 @ 0x54 do_pci_scan_bridge for PCI: 02:00.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 PCI: 03: 133MHz PCI-X Capability: type 0x10 @ 0x40 Capability: type 0x07 @ 0x54 do_pci_scan_bridge for PCI: 02:00.1 PCI: pci_scan_bus for bus 04 PCI: Static device PCI: 04:04.0 not found, disabling it. PCI: Static device PCI: 04:04.1 not found, disabling it. PCI: pci_scan_bus returning with max=004 Capability: type 0xff @ 0xfc Capability: type 0xff @ 0xfc do_pci_scan_bridge returns max 4 PCI: 04: 133MHz PCI-X PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:0b.0 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 do_pci_scan_bridge for PCI: 00:0c.0 PCI: pci_scan_bus for bus 06 PCI: pci_scan_bus returning with max=006 do_pci_scan_bridge returns max 6 do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 07 PCI: pci_scan_bus returning with max=007 do_pci_scan_bridge returns max 7 do_pci_scan_bridge for PCI: 00:0e.0 PCI: pci_scan_bus for bus 08 PCI: pci_scan_bus returning with max=008 do_pci_scan_bridge returns max 8 do_pci_scan_bridge for PCI: 00:0f.0 PCI: pci_scan_bus for bus 09 PCI: pci_scan_bus returning with max=009 do_pci_scan_bridge returns max 9 PCI: pci_scan_bus returning with max=009 PCI: pci_scan_bus returning with max=009 PCI_DOMAIN: 0000 passpw: enabled PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Setting up VGA for PCI: 01:05.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:06.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC: 02 missing read_resources APIC: 03 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 2 has VGA device PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:01.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 done PCI: 00:01.1 read_resources bus 1 link: 0 PCI: 00:01.1 read_resources bus 1 link: 0 done PCI: 00:01.1 read_resources bus 2 link: 1 I2C: 02:51 missing read_resources PCI: 00:01.1 read_resources bus 2 link: 1 done PCI: 00:06.0 read_resources bus 1 link: 0 PCI: 00:06.0 read_resources bus 1 link: 0 done PCI: 00:0a.0 read_resources bus 2 link: 0 PCI: 02:00.0 read_resources bus 3 link: 0 PCI: 02:00.0 read_resources bus 3 link: 0 done PCI: 02:00.1 read_resources bus 4 link: 0 PCI: 02:00.1 read_resources bus 4 link: 0 done PCI: 00:0a.0 read_resources bus 2 link: 0 done PCI: 00:0b.0 read_resources bus 5 link: 0 PCI: 00:0b.0 read_resources bus 5 link: 0 done PCI: 00:0c.0 read_resources bus 6 link: 0 PCI: 00:0c.0 read_resources bus 6 link: 0 done PCI: 00:0d.0 read_resources bus 7 link: 0 PCI: 00:0d.0 read_resources bus 7 link: 0 done PCI: 00:0e.0 read_resources bus 8 link: 0 PCI: 00:0e.0 read_resources bus 8 link: 0 done PCI: 00:0f.0 read_resources bus 9 link: 0 PCI: 00:0f.0 read_resources bus 9 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:19.0 read_resources bus 0 link: 0 PCI: 00:19.0 read_resources bus 0 link: 0 done PCI: 00:19.0 read_resources bus 0 link: 1 PCI: 00:19.0 read_resources bus 0 link: 1 done PCI: 00:19.0 read_resources bus 0 link: 2 PCI: 00:19.0 read_resources bus 0 link: 2 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device links 1 child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00 APIC: 00 links 0 child on link 0 NULL APIC: 01 links 0 child on link 0 NULL APIC: 02 links 0 child on link 0 NULL APIC: 03 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:18.0 links 3 child on link 0 NULL PCI: 00:18.0 resource base 33 size 0 align 0 gran 0 limit 3020 flags 1 index 201c0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 20000 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 20002 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 20001 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 20004 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:01.0 links 1 child on link 0 PNP: 002e.0 PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 links 0 child on link 0 NULL PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 links 0 child on link 0 NULL PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 links 0 child on link 0 NULL PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 links 0 child on link 0 NULL PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 links 0 child on link 0 NULL PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 links 0 child on link 0 NULL PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 links 0 child on link 0 NULL PNP: 002e.7 resource base 220 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.7 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62 PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 links 0 child on link 0 NULL PNP: 002e.9 links 0 child on link 0 NULL PNP: 002e.a links 0 child on link 0 NULL PNP: 002e.b links 0 child on link 0 NULL PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:01.1 links 2 child on link 0 I2C: 01:48 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 10 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 64 PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 68 I2C: 01:48 links 0 child on link 0 NULL I2C: 01:49 links 0 child on link 0 NULL I2C: 02:51 links 0 child on link 0 NULL PCI: 00:01.2 links 0 child on link 0 NULL PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:01.3 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 10 PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:02.1 links 0 child on link 0 NULL PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:04.0 links 0 child on link 0 NULL PCI: 00:04.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:05.0 links 0 child on link 0 NULL PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:05.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:05.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 PCI: 00:05.1 links 0 child on link 0 NULL PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:05.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:05.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 PCI: 00:05.2 links 0 child on link 0 NULL PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:05.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:05.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 PCI: 00:06.0 links 1 child on link 0 PCI: 01:05.0 PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:05.0 links 0 child on link 0 NULL PCI: 01:05.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffff flags 1200 index 10 PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18 PCI: 01:05.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 01:06.0 links 0 child on link 0 NULL PCI: 00:06.1 links 0 child on link 0 NULL PCI: 00:06.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:08.0 links 0 child on link 0 NULL PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 PCI: 00:08.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffffffff flags 200 index 1c PCI: 00:09.0 links 0 child on link 0 NULL PCI: 00:09.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:09.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 18 PCI: 00:09.0 resource base 0 size 10 align 4 gran 4 limit ffffffff flags 200 index 1c PCI: 00:0a.0 links 1 child on link 0 PCI: 02:00.0 PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 links 1 child on link 0 NULL PCI: 02:00.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 02:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 02:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.1 links 1 child on link 0 PCI: 04:04.0 PCI: 02:00.1 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 02:00.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 02:00.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:04.0 links 0 child on link 0 NULL PCI: 04:04.1 links 0 child on link 0 NULL PCI: 00:0b.0 links 1 child on link 0 NULL PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0c.0 links 1 child on link 0 NULL PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0d.0 links 1 child on link 0 NULL PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0e.0 links 1 child on link 0 NULL PCI: 00:0e.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0f.0 links 1 child on link 0 NULL PCI: 00:0f.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:18.1 links 0 child on link 0 NULL PCI: 00:18.2 links 0 child on link 0 NULL PCI: 00:18.3 links 0 child on link 0 NULL PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:19.0 links 3 child on link 0 NULL PCI: 00:19.1 links 0 child on link 0 NULL PCI: 00:19.2 links 0 child on link 0 NULL PCI: 00:19.3 links 0 child on link 0 NULL PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:06.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 01:05.0 14 * [0x0 - 0xff] io PCI: 00:06.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 02:00.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 02:00.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 02:00.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 02:00.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0b.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0b.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0f.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0f.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:06.0 1c * [0x0 - 0xfff] io PCI: 00:01.1 60 * [0x1000 - 0x10ff] io PCI: 00:01.1 64 * [0x1400 - 0x14ff] io PCI: 00:01.1 68 * [0x1800 - 0x18ff] io PCI: 00:01.1 10 * [0x1c00 - 0x1c3f] io PCI: 00:01.1 20 * [0x1c40 - 0x1c7f] io PCI: 00:01.1 24 * [0x1c80 - 0x1cbf] io PCI: 00:04.0 20 * [0x1cc0 - 0x1ccf] io PCI: 00:05.0 20 * [0x1cd0 - 0x1cdf] io PCI: 00:05.1 20 * [0x1ce0 - 0x1cef] io PCI: 00:05.2 20 * [0x1cf0 - 0x1cff] io PCI: 00:05.0 10 * [0x2000 - 0x2007] io PCI: 00:05.0 18 * [0x2008 - 0x200f] io PCI: 00:05.1 10 * [0x2010 - 0x2017] io PCI: 00:05.1 18 * [0x2018 - 0x201f] io PCI: 00:05.2 10 * [0x2020 - 0x2027] io PCI: 00:05.2 18 * [0x2028 - 0x202f] io PCI: 00:08.0 14 * [0x2030 - 0x2037] io PCI: 00:09.0 14 * [0x2038 - 0x203f] io PCI: 00:05.0 14 * [0x2040 - 0x2043] io PCI: 00:05.0 1c * [0x2044 - 0x2047] io PCI: 00:05.1 14 * [0x2048 - 0x204b] io PCI: 00:05.1 1c * [0x204c - 0x204f] io PCI: 00:05.2 14 * [0x2050 - 0x2053] io PCI: 00:05.2 1c * [0x2054 - 0x2057] io PCI: 00:18.0 compute_resources_io: base: 2058 size: 3000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 20000 * [0x0 - 0x2fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:06.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:05.0 10 * [0x0 - 0x7ffffff] prefmem PCI: 00:06.0 compute_resources_prefmem: base: 8000000 size: 8000000 align: 27 gran: 20 limit: ffffffff done PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 02:00.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 02:00.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 02:00.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 02:00.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0b.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0b.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0f.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0f.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:06.0 24 * [0x0 - 0x7ffffff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 8000000 size: 8000000 align: 27 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:06.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:05.0 30 * [0x0 - 0x1ffff] mem PCI: 01:05.0 18 * [0x20000 - 0x2ffff] mem PCI: 00:06.0 compute_resources_mem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 02:00.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0b.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0b.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0f.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0f.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:06.0 20 * [0x0 - 0xfffff] mem PCI: 00:01.3 10 * [0x100000 - 0x13ffff] mem PCI: 00:06.1 10 * [0x140000 - 0x143fff] mem PCI: 00:01.0 14 * [0x144000 - 0x144fff] mem PCI: 00:02.0 10 * [0x145000 - 0x145fff] mem PCI: 00:05.0 24 * [0x146000 - 0x146fff] mem PCI: 00:05.1 24 * [0x147000 - 0x147fff] mem PCI: 00:05.2 24 * [0x148000 - 0x148fff] mem PCI: 00:08.0 10 * [0x149000 - 0x149fff] mem PCI: 00:09.0 10 * [0x14a000 - 0x14afff] mem PCI: 00:02.1 10 * [0x14b000 - 0x14b0ff] mem PCI: 00:08.0 18 * [0x14b100 - 0x14b1ff] mem PCI: 00:09.0 18 * [0x14b200 - 0x14b2ff] mem PCI: 00:08.0 1c * [0x14b300 - 0x14b30f] mem PCI: 00:09.0 1c * [0x14b310 - 0x14b31f] mem PCI: 00:18.0 compute_resources_mem: base: 14b320 size: 200000 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.0 20002 * [0x0 - 0x7ffffff] prefmem PCI: 00:18.3 94 * [0x8000000 - 0xbffffff] mem PCI: 00:18.0 20001 * [0xc000000 - 0xc1fffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: c200000 size: c200000 align: 27 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.5 constrain_resources: PNP: 002e.b constrain_resources: PCI: 00:01.1 constrain_resources: I2C: 02:51 constrain_resources: PCI: 00:01.2 constrain_resources: PCI: 00:01.3 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:02.1 constrain_resources: PCI: 00:04.0 constrain_resources: PCI: 00:05.0 constrain_resources: PCI: 00:05.1 constrain_resources: PCI: 00:05.2 constrain_resources: PCI: 00:06.0 constrain_resources: PCI: 01:05.0 constrain_resources: PCI: 00:06.1 constrain_resources: PCI: 00:08.0 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0a.0 constrain_resources: PCI: 02:00.0 constrain_resources: PCI: 02:00.1 constrain_resources: PCI: 00:0b.0 constrain_resources: PCI: 00:0c.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:0e.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:19.0 constrain_resources: PCI: 00:19.1 constrain_resources: PCI: 00:19.2 constrain_resources: PCI: 00:19.3 avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff lim->base 000c0000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:3000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 20000 * [0x1000 - 0x3fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 4000 size: 3000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:1000 size:3000 align:12 gran:12 limit:ffff Assigned: PCI: 00:06.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:01.1 60 * [0x2000 - 0x20ff] io Assigned: PCI: 00:01.1 64 * [0x2400 - 0x24ff] io Assigned: PCI: 00:01.1 68 * [0x2800 - 0x28ff] io Assigned: PCI: 00:01.1 10 * [0x2c00 - 0x2c3f] io Assigned: PCI: 00:01.1 20 * [0x2c40 - 0x2c7f] io Assigned: PCI: 00:01.1 24 * [0x2c80 - 0x2cbf] io Assigned: PCI: 00:04.0 20 * [0x2cc0 - 0x2ccf] io Assigned: PCI: 00:05.0 20 * [0x2cd0 - 0x2cdf] io Assigned: PCI: 00:05.1 20 * [0x2ce0 - 0x2cef] io Assigned: PCI: 00:05.2 20 * [0x2cf0 - 0x2cff] io Assigned: PCI: 00:05.0 10 * [0x3000 - 0x3007] io Assigned: PCI: 00:05.0 18 * [0x3008 - 0x300f] io Assigned: PCI: 00:05.1 10 * [0x3010 - 0x3017] io Assigned: PCI: 00:05.1 18 * [0x3018 - 0x301f] io Assigned: PCI: 00:05.2 10 * [0x3020 - 0x3027] io Assigned: PCI: 00:05.2 18 * [0x3028 - 0x302f] io Assigned: PCI: 00:08.0 14 * [0x3030 - 0x3037] io Assigned: PCI: 00:09.0 14 * [0x3038 - 0x303f] io Assigned: PCI: 00:05.0 14 * [0x3040 - 0x3043] io Assigned: PCI: 00:05.0 1c * [0x3044 - 0x3047] io Assigned: PCI: 00:05.1 14 * [0x3048 - 0x304b] io Assigned: PCI: 00:05.1 1c * [0x304c - 0x304f] io Assigned: PCI: 00:05.2 14 * [0x3050 - 0x3053] io Assigned: PCI: 00:05.2 1c * [0x3054 - 0x3057] io PCI: 00:18.0 allocate_resources_io: next_base: 3058 size: 3000 align: 12 gran: 12 done PCI: 00:06.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 01:05.0 14 * [0x1000 - 0x10ff] io PCI: 00:06.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done PCI: 00:0a.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0a.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 02:00.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 02:00.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 02:00.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 02:00.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:0b.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0b.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:0c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:0d.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0d.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:0e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:0f.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0f.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:f0000000 size:c200000 align:27 gran:0 limit:febfffff Assigned: PCI: 00:18.0 20002 * [0xf0000000 - 0xf7ffffff] prefmem Assigned: PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem Assigned: PCI: 00:18.0 20001 * [0xfc000000 - 0xfc1fffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fc200000 size: c200000 align: 27 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:f0000000 size:8000000 align:27 gran:20 limit:febfffff Assigned: PCI: 00:06.0 24 * [0xf0000000 - 0xf7ffffff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: f8000000 size: 8000000 align: 27 gran: 20 done PCI: 00:06.0 allocate_resources_prefmem: base:f0000000 size:8000000 align:27 gran:20 limit:febfffff Assigned: PCI: 01:05.0 10 * [0xf0000000 - 0xf7ffffff] prefmem PCI: 00:06.0 allocate_resources_prefmem: next_base: f8000000 size: 8000000 align: 27 gran: 20 done PCI: 00:0a.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0a.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 02:00.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 02:00.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 02:00.1 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 02:00.1 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0b.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0b.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0c.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0d.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0e.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0e.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0f.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0f.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:fc000000 size:200000 align:20 gran:20 limit:febfffff Assigned: PCI: 00:06.0 20 * [0xfc000000 - 0xfc0fffff] mem Assigned: PCI: 00:01.3 10 * [0xfc100000 - 0xfc13ffff] mem Assigned: PCI: 00:06.1 10 * [0xfc140000 - 0xfc143fff] mem Assigned: PCI: 00:01.0 14 * [0xfc144000 - 0xfc144fff] mem Assigned: PCI: 00:02.0 10 * [0xfc145000 - 0xfc145fff] mem Assigned: PCI: 00:05.0 24 * [0xfc146000 - 0xfc146fff] mem Assigned: PCI: 00:05.1 24 * [0xfc147000 - 0xfc147fff] mem Assigned: PCI: 00:05.2 24 * [0xfc148000 - 0xfc148fff] mem Assigned: PCI: 00:08.0 10 * [0xfc149000 - 0xfc149fff] mem Assigned: PCI: 00:09.0 10 * [0xfc14a000 - 0xfc14afff] mem Assigned: PCI: 00:02.1 10 * [0xfc14b000 - 0xfc14b0ff] mem Assigned: PCI: 00:08.0 18 * [0xfc14b100 - 0xfc14b1ff] mem Assigned: PCI: 00:09.0 18 * [0xfc14b200 - 0xfc14b2ff] mem Assigned: PCI: 00:08.0 1c * [0xfc14b300 - 0xfc14b30f] mem Assigned: PCI: 00:09.0 1c * [0xfc14b310 - 0xfc14b31f] mem PCI: 00:18.0 allocate_resources_mem: next_base: fc14b320 size: 200000 align: 20 gran: 20 done PCI: 00:06.0 allocate_resources_mem: base:fc000000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 01:05.0 30 * [0xfc000000 - 0xfc01ffff] mem Assigned: PCI: 01:05.0 18 * [0xfc020000 - 0xfc02ffff] mem PCI: 00:06.0 allocate_resources_mem: next_base: fc030000 size: 100000 align: 20 gran: 20 done PCI: 00:0a.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0a.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 02:00.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 02:00.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 02:00.1 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 02:00.1 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0b.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0b.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0c.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0d.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0e.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0e.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0f.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0f.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 0: mmio_basek=00300000, basek=00000300, limitk=00200000 1: mmio_basek=00300000, basek=00400000, limitk=00500000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x2 PCI: 00:18.0 201c0 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io PCI: 00:18.0 201b8 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 prefmem PCI: 00:18.0 201b0 <- [0x00fc000000 - 0x00fc1fffff] size 0x00200000 gran 0x14 mem PCI: 00:18.0 201a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem PCI: 00:18.0 assign_resources, bus 0 link: 2 PCI: 00:01.0 14 <- [0x00fc144000 - 0x00fc144fff] size 0x00001000 gran 0x0c mem PCI: 00:01.0 assign_resources, bus 0 link: 0 PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq PCI: 00:01.0 assign_resources, bus 0 link: 0 PCI: 00:01.1 10 <- [0x0000002c00 - 0x0000002c3f] size 0x00000040 gran 0x06 io PCI: 00:01.1 20 <- [0x0000002c40 - 0x0000002c7f] size 0x00000040 gran 0x06 io PCI: 00:01.1 24 <- [0x0000002c80 - 0x0000002cbf] size 0x00000040 gran 0x06 io PCI: 00:01.1 60 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 64 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 68 <- [0x0000002800 - 0x00000028ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 assign_resources, bus 1 link: 0 PCI: 00:01.1 assign_resources, bus 1 link: 0 PCI: 00:01.1 assign_resources, bus 2 link: 1 PCI: 00:01.1 assign_resources, bus 2 link: 1 PCI: 00:01.3 10 <- [0x00fc100000 - 0x00fc13ffff] size 0x00040000 gran 0x12 mem PCI: 00:02.0 10 <- [0x00fc145000 - 0x00fc145fff] size 0x00001000 gran 0x0c mem PCI: 00:02.1 10 <- [0x00fc14b000 - 0x00fc14b0ff] size 0x00000100 gran 0x08 mem PCI: 00:04.0 20 <- [0x0000002cc0 - 0x0000002ccf] size 0x00000010 gran 0x04 io PCI: 00:05.0 10 <- [0x0000003000 - 0x0000003007] size 0x00000008 gran 0x03 io PCI: 00:05.0 14 <- [0x0000003040 - 0x0000003043] size 0x00000004 gran 0x02 io PCI: 00:05.0 18 <- [0x0000003008 - 0x000000300f] size 0x00000008 gran 0x03 io PCI: 00:05.0 1c <- [0x0000003044 - 0x0000003047] size 0x00000004 gran 0x02 io PCI: 00:05.0 20 <- [0x0000002cd0 - 0x0000002cdf] size 0x00000010 gran 0x04 io PCI: 00:05.0 24 <- [0x00fc146000 - 0x00fc146fff] size 0x00001000 gran 0x0c mem PCI: 00:05.1 10 <- [0x0000003010 - 0x0000003017] size 0x00000008 gran 0x03 io PCI: 00:05.1 14 <- [0x0000003048 - 0x000000304b] size 0x00000004 gran 0x02 io PCI: 00:05.1 18 <- [0x0000003018 - 0x000000301f] size 0x00000008 gran 0x03 io PCI: 00:05.1 1c <- [0x000000304c - 0x000000304f] size 0x00000004 gran 0x02 io PCI: 00:05.1 20 <- [0x0000002ce0 - 0x0000002cef] size 0x00000010 gran 0x04 io PCI: 00:05.1 24 <- [0x00fc147000 - 0x00fc147fff] size 0x00001000 gran 0x0c mem PCI: 00:05.2 10 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran 0x03 io PCI: 00:05.2 14 <- [0x0000003050 - 0x0000003053] size 0x00000004 gran 0x02 io PCI: 00:05.2 18 <- [0x0000003028 - 0x000000302f] size 0x00000008 gran 0x03 io PCI: 00:05.2 1c <- [0x0000003054 - 0x0000003057] size 0x00000004 gran 0x02 io PCI: 00:05.2 20 <- [0x0000002cf0 - 0x0000002cff] size 0x00000010 gran 0x04 io PCI: 00:05.2 24 <- [0x00fc148000 - 0x00fc148fff] size 0x00001000 gran 0x0c mem PCI: 00:06.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:06.0 24 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 bus 01 prefmem PCI: 00:06.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 00:06.0 assign_resources, bus 1 link: 0 PCI: 01:05.0 10 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem PCI: 01:05.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 01:05.0 18 <- [0x00fc020000 - 0x00fc02ffff] size 0x00010000 gran 0x10 mem PCI: 01:05.0 30 <- [0x00fc000000 - 0x00fc01ffff] size 0x00020000 gran 0x11 romem PCI: 00:06.0 assign_resources, bus 1 link: 0 PCI: 00:06.1 10 <- [0x00fc140000 - 0x00fc143fff] size 0x00004000 gran 0x0e mem PCI: 00:08.0 10 <- [0x00fc149000 - 0x00fc149fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 14 <- [0x0000003030 - 0x0000003037] size 0x00000008 gran 0x03 io PCI: 00:08.0 18 <- [0x00fc14b100 - 0x00fc14b1ff] size 0x00000100 gran 0x08 mem PCI: 00:08.0 1c <- [0x00fc14b300 - 0x00fc14b30f] size 0x00000010 gran 0x04 mem PCI: 00:09.0 10 <- [0x00fc14a000 - 0x00fc14afff] size 0x00001000 gran 0x0c mem PCI: 00:09.0 14 <- [0x0000003038 - 0x000000303f] size 0x00000008 gran 0x03 io PCI: 00:09.0 18 <- [0x00fc14b200 - 0x00fc14b2ff] size 0x00000100 gran 0x08 mem PCI: 00:09.0 1c <- [0x00fc14b310 - 0x00fc14b31f] size 0x00000010 gran 0x04 mem PCI: 00:0a.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:0a.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:0a.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:0a.0 assign_resources, bus 2 link: 0 PCI: 02:00.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io PCI: 02:00.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 02:00.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 mem PCI: 02:00.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 02:00.1 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 02:00.1 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 mem PCI: 02:00.1 assign_resources, bus 4 link: 0 PCI: 02:00.1 assign_resources, bus 4 link: 0 PCI: 00:0a.0 assign_resources, bus 2 link: 0 PCI: 00:0b.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:0b.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:0b.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:0c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 06 io PCI: 00:0c.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 06 prefmem PCI: 00:0c.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 06 mem PCI: 00:0d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 07 io PCI: 00:0d.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 07 prefmem PCI: 00:0d.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 07 mem PCI: 00:0e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 08 io PCI: 00:0e.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 08 prefmem PCI: 00:0e.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 08 mem PCI: 00:0f.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 09 io PCI: 00:0f.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 09 prefmem PCI: 00:0f.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 09 mem PCI: 00:18.0 assign_resources, bus 0 link: 2 PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device links 1 child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00 APIC: 00 links 0 child on link 0 NULL APIC: 01 links 0 child on link 0 NULL APIC: 02 links 0 child on link 0 NULL APIC: 03 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base f0000000 size c200000 align 27 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size 7ff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 31 PCI_DOMAIN: 0000 resource base 100000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 41 PCI: 00:18.0 links 3 child on link 0 NULL PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit ffff flags 60080100 index 201c0 PCI: 00:18.0 resource base f0000000 size 8000000 align 27 gran 20 limit febfffff flags 60081200 index 201b8 PCI: 00:18.0 resource base fc000000 size 200000 align 20 gran 20 limit febfffff flags 60080200 index 201b0 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 201a8 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:01.0 links 1 child on link 0 PNP: 002e.0 PCI: 00:01.0 resource base fc144000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 links 0 child on link 0 NULL PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 links 0 child on link 0 NULL PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 links 0 child on link 0 NULL PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 links 0 child on link 0 NULL PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 links 0 child on link 0 NULL PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 002e.6 links 0 child on link 0 NULL PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 links 0 child on link 0 NULL PNP: 002e.7 resource base 220 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.7 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62 PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 links 0 child on link 0 NULL PNP: 002e.9 links 0 child on link 0 NULL PNP: 002e.a links 0 child on link 0 NULL PNP: 002e.b links 0 child on link 0 NULL PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PCI: 00:01.1 links 2 child on link 0 I2C: 01:48 PCI: 00:01.1 resource base 2c00 size 40 align 6 gran 6 limit ffff flags 60000100 index 10 PCI: 00:01.1 resource base 2c40 size 40 align 6 gran 6 limit ffff flags 60000100 index 20 PCI: 00:01.1 resource base 2c80 size 40 align 6 gran 6 limit ffff flags 60000100 index 24 PCI: 00:01.1 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 60 PCI: 00:01.1 resource base 2400 size 100 align 8 gran 8 limit ffff flags 60000100 index 64 PCI: 00:01.1 resource base 2800 size 100 align 8 gran 8 limit ffff flags 60000100 index 68 I2C: 01:48 links 0 child on link 0 NULL I2C: 01:49 links 0 child on link 0 NULL I2C: 02:51 links 0 child on link 0 NULL PCI: 00:01.2 links 0 child on link 0 NULL PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:01.3 resource base fc100000 size 40000 align 18 gran 18 limit febfffff flags 60000200 index 10 PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base fc145000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:02.1 links 0 child on link 0 NULL PCI: 00:02.1 resource base fc14b000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10 PCI: 00:04.0 links 0 child on link 0 NULL PCI: 00:04.0 resource base 2cc0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:05.0 links 0 child on link 0 NULL PCI: 00:05.0 resource base 3000 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:05.0 resource base 3040 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:05.0 resource base 3008 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:05.0 resource base 3044 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:05.0 resource base 2cd0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:05.0 resource base fc146000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 24 PCI: 00:05.1 links 0 child on link 0 NULL PCI: 00:05.1 resource base 3010 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:05.1 resource base 3048 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:05.1 resource base 3018 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:05.1 resource base 304c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:05.1 resource base 2ce0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:05.1 resource base fc147000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 24 PCI: 00:05.2 links 0 child on link 0 NULL PCI: 00:05.2 resource base 3020 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:05.2 resource base 3050 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:05.2 resource base 3028 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:05.2 resource base 3054 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:05.2 resource base 2cf0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:05.2 resource base fc148000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 24 PCI: 00:06.0 links 1 child on link 0 PCI: 01:05.0 PCI: 00:06.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:06.0 resource base f0000000 size 8000000 align 27 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:06.0 resource base fc000000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 01:05.0 links 0 child on link 0 NULL PCI: 01:05.0 resource base f0000000 size 8000000 align 27 gran 27 limit febfffff flags 60001200 index 10 PCI: 01:05.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14 PCI: 01:05.0 resource base fc020000 size 10000 align 16 gran 16 limit febfffff flags 60000200 index 18 PCI: 01:05.0 resource base fc000000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30 PCI: 01:06.0 links 0 child on link 0 NULL PCI: 00:06.1 links 0 child on link 0 NULL PCI: 00:06.1 resource base fc140000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 10 PCI: 00:08.0 links 0 child on link 0 NULL PCI: 00:08.0 resource base fc149000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:08.0 resource base 3030 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 PCI: 00:08.0 resource base fc14b100 size 100 align 8 gran 8 limit febfffff flags 60000200 index 18 PCI: 00:08.0 resource base fc14b300 size 10 align 4 gran 4 limit febfffff flags 60000200 index 1c PCI: 00:09.0 links 0 child on link 0 NULL PCI: 00:09.0 resource base fc14a000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:09.0 resource base 3038 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 PCI: 00:09.0 resource base fc14b200 size 100 align 8 gran 8 limit febfffff flags 60000200 index 18 PCI: 00:09.0 resource base fc14b310 size 10 align 4 gran 4 limit febfffff flags 60000200 index 1c PCI: 00:0a.0 links 1 child on link 0 PCI: 02:00.0 PCI: 00:0a.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:0a.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:0a.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 02:00.0 links 1 child on link 0 NULL PCI: 02:00.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 02:00.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 02:00.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 02:00.1 links 1 child on link 0 PCI: 04:04.0 PCI: 02:00.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 02:00.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 02:00.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 04:04.0 links 0 child on link 0 NULL PCI: 04:04.1 links 0 child on link 0 NULL PCI: 00:0b.0 links 1 child on link 0 NULL PCI: 00:0b.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:0b.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:0b.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:0c.0 links 1 child on link 0 NULL PCI: 00:0c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:0c.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:0c.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:0d.0 links 1 child on link 0 NULL PCI: 00:0d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:0d.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:0d.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:0e.0 links 1 child on link 0 NULL PCI: 00:0e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:0e.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:0e.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:0f.0 links 1 child on link 0 NULL PCI: 00:0f.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:0f.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:0f.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:18.1 links 0 child on link 0 NULL PCI: 00:18.2 links 0 child on link 0 NULL PCI: 00:18.3 links 0 child on link 0 NULL PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit febfffff flags 60000200 index 94 PCI: 00:19.0 links 3 child on link 0 NULL PCI: 00:19.1 links 0 child on link 0 NULL PCI: 00:19.2 links 0 child on link 0 NULL PCI: 00:19.3 links 0 child on link 0 NULL Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:00.0 subsystem <- 15d9/1511 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 subsystem <- 15d9/1511 PCI: 00:01.0 cmd <- 0f mcp55 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff mcp55 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 mcp55 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 w83627hf hwm smbus enabled mcp55 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000297 PCI: 00:01.1 subsystem <- 15d9/1511 PCI: 00:01.1 cmd <- 01 PCI: 00:01.2 cmd <- 400 PCI: 00:01.3 cmd <- 02 PCI: 00:02.0 subsystem <- 15d9/1511 PCI: 00:02.0 cmd <- 02 PCI: 00:02.1 subsystem <- 15d9/1511 PCI: 00:02.1 cmd <- 02 PCI: 00:04.0 subsystem <- 15d9/1511 PCI: 00:04.0 cmd <- 01 PCI: 00:05.0 subsystem <- 15d9/1511 PCI: 00:05.0 cmd <- 03 PCI: 00:05.1 subsystem <- 15d9/1511 PCI: 00:05.1 cmd <- 03 PCI: 00:05.2 subsystem <- 15d9/1511 PCI: 00:05.2 cmd <- 03 PCI: 00:06.0 bridge ctrl <- 0a0b PCI: 00:06.0 cmd <- 107 PCI: 01:05.0 cmd <- 83 PCI: 00:06.1 subsystem <- 15d9/1511 PCI: 00:06.1 cmd <- 02 PCI: 00:08.0 subsystem <- 15d9/1511 PCI: 00:08.0 cmd <- 03 PCI: 00:09.0 subsystem <- 15d9/1511 PCI: 00:09.0 cmd <- 03 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 00 PCI: 02:00.0 bridge ctrl <- 0003 PCI: 02:00.0 cmd <- 00 PCI: 02:00.1 bridge ctrl <- 0003 PCI: 02:00.1 cmd <- 00 PCI: 00:0b.0 bridge ctrl <- 0003 PCI: 00:0b.0 cmd <- 00 PCI: 00:0c.0 bridge ctrl <- 0003 PCI: 00:0c.0 cmd <- 00 PCI: 00:0d.0 bridge ctrl <- 0003 PCI: 00:0d.0 cmd <- 00 PCI: 00:0e.0 bridge ctrl <- 0003 PCI: 00:0e.0 cmd <- 00 PCI: 00:0f.0 bridge ctrl <- 0003 PCI: 00:0f.0 cmd <- 00 PCI: 00:18.1 subsystem <- 15d9/1511 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 15d9/1511 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x0000c000, offset=0x00100000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 40f12 CPU: family 0f, model 41, stepping 02 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 1, base: 4096MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model Dual-Core AMD Opteron(tm) Processor 2212 Setting up local apic... apic_id: 0x00 done. Clearing memory 2048K - 2097152K: ------------------------------- done CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +Sending STARTUP #2 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 CPU: vendor AMD device 40f12 CPU: family 0f, model 41, stepping 02 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 1, base: 4096MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model Dual-Core AMD Opteron(tm) Processor 2212 Setting up local apic... apic_id: 0x01 done. CPU #1 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 2. After apic_write. Startup point 1. Waiting for send to finish... +Sending STARTUP #2 to 2. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #2 CPU: vendor AMD device 40f12 CPU: family 0f, model 41, stepping 02 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 1, base: 4096MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model Dual-Core AMD Opteron(tm) Processor 2212 Setting up local apic... apic_id: 0x02 done. Clearing memory 2097152K - 5242880K: ----------------++++++++++++++++ done CPU #2 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 3. After apic_write. Startup point 1. Waiting for send to finish... +Sending STARTUP #2 to 3. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #3 Waiting for 1 CPUS to stop CPU: vendor AMD device 40f12 CPU: family 0f, model 41, stepping 02 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 1, base: 4096MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model Dual-Core AMD Opteron(tm) Processor 2212 Setting up local apic... apic_id: 0x03 done. CPU #3 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:01.0 init IOAPIC: Initializing IOAPIC at 0xfc144000 IOAPIC: Bootstrap Processor Local APIC = 00 IOAPIC: 23 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 set power on after power fail RTC Init Invalid CMOS LB checksum enabling HPET @0xfed00000 PNP: 002e.2 init PNP: 002e.5 init Keyboard init... Keyboard controller output buffer result timeout PNP: 002e.b init PCI: 00:01.1 init PCI: 00:02.1 init PCI: 00:04.0 init IDE0 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0 Check pci1002,515e.rom CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000 Check CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000 CBFS: Could not find file pci10de,036e.rom PCI: 00:05.0 init SATA S SATA P PCI: 00:05.1 init SATA S SATA P PCI: 00:05.2 init SATA S SATA P PCI: 00:06.0 init PCI DOMAIN mem base = 0x00f0000000 [0x50] <-- 0xf0000000 PCI: 00:06.1 init Azalia: codec type: Azalia Azalia: base = fc140000 Azalia: codec_mask = 01 Azalia: Initializing codec #0 PCI: 00:08.0 init MCP55 MAC PHY ID 0x01410c00 PHY ADDR 2 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0 Check pci1002,515e.rom CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000 Check CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000 CBFS: Could not find file pci10de,0373.rom PCI: 00:09.0 init MCP55 MAC PHY ID 0x01410c00 PHY ADDR 3 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0 Check pci1002,515e.rom CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000 Check CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000 CBFS: Could not find file pci10de,0373.rom PCI: 00:0a.0 init PCI: 00:0b.0 init PCI: 00:0c.0 init PCI: 00:0d.0 init PCI: 00:0e.0 init PCI: 00:0f.0 init PCI: 00:18.1 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0 Check pci1002,515e.rom CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000 Check CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000 CBFS: Could not find file pci1022,1101.rom PCI: 00:18.2 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0 Check pci1002,515e.rom CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000 Check CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000 CBFS: Could not find file pci1022,1102.rom PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.0 init PCI: 00:19.1 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0 Check pci1002,515e.rom CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000 Check CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000 CBFS: Could not find file pci1022,1101.rom PCI: 00:19.2 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0 Check pci1002,515e.rom CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000 Check CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000 CBFS: Could not find file pci1022,1102.rom PCI: 00:19.3 init NB: Function 3 Misc Control.. done. PCI: 00:01.2 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0 Check pci1002,515e.rom CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000 Check CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000 CBFS: Could not find file pci10de,036a.rom PCI: 00:01.3 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0 Check pci1002,515e.rom CBFS: follow chain: fff14fc0 + 38 + b000 + align -> fff20000 Check CBFS: follow chain: fff20000 + 28 + cffb8 + align -> ffff0000 CBFS: Could not find file pci10de,036b.rom PCI: 01:05.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload CBFS: follow chain: fff0b180 + 38 + 9dfb + align -> fff14fc0 Check pci1002,515e.rom In cbfs, rom address for PCI: 01:05.0 = fff14ff8 PCI Expansion ROM, signature 0xaa55, INIT size 0xb000, data ptr 0x0158 PCI ROM Image, Vendor 1002, Device 515e, PCI ROM Image, Class Code 030000, Code Type 00 copying VGA ROM Image from fff14ff8 to 0xc0000, 0xb000 bytes Real mode stub @00000600: 609 bytes Calling Option ROM... oprom: INT# 0x10 oprom: eax: 00000007 ebx: 00000200 ecx: 00000000 edx: 000003c2 oprom: ebp: 0015ff10 esp: 00000fca edi: 00000000 esi: 0000597b oprom: ip: 481c cs: c000 flags: 00000006 Unsupported software interrupt #0x10 int10 call returned error. ... Option ROM returned. Devices initialized Show all devs...After init. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 6 resources PCI: 00:18.0: enabled 1, 4 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 4 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 3 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 3 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 6 resources I2C: 01:48: enabled 0, 0 resources I2C: 01:49: enabled 0, 0 resources I2C: 02:51: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 1 resources PCI: 00:02.1: enabled 1, 1 resources PCI: 00:04.0: enabled 1, 1 resources PCI: 00:05.0: enabled 1, 6 resources PCI: 00:05.1: enabled 1, 6 resources PCI: 00:05.2: enabled 1, 6 resources PCI: 00:06.0: enabled 1, 3 resources PCI: 01:06.0: enabled 0, 0 resources PCI: 00:06.1: enabled 1, 1 resources PCI: 00:08.0: enabled 1, 4 resources PCI: 00:09.0: enabled 1, 4 resources PCI: 00:0a.0: enabled 1, 3 resources PCI: 02:00.0: enabled 1, 3 resources PCI: 02:00.1: enabled 1, 3 resources PCI: 04:04.0: enabled 0, 0 resources PCI: 04:04.1: enabled 0, 0 resources PCI: 00:0b.0: enabled 1, 3 resources PCI: 00:0c.0: enabled 1, 3 resources PCI: 00:0d.0: enabled 1, 3 resources PCI: 00:0e.0: enabled 1, 3 resources PCI: 00:0f.0: enabled 1, 3 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 1 resources APIC: 01: enabled 1, 0 resources PCI: 00:19.0: enabled 1, 0 resources PCI: 00:19.1: enabled 1, 0 resources PCI: 00:19.2: enabled 1, 0 resources PCI: 00:19.3: enabled 1, 0 resources APIC: 02: enabled 1, 0 resources APIC: 03: enabled 1, 0 resources PCI: 00:01.2: enabled 1, 0 resources PCI: 00:01.3: enabled 1, 1 resources PCI: 01:05.0: enabled 1, 4 resources Initializing CBMEM area to 0x7fff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 7fff0200...ok High Tables Base is 7fff0000. Writing IRQ routing tables to 0xf0000...done. Adding CBMEM entry as no. 2 Writing IRQ routing tables to 0x7fff0400...done. PIRQ table: 48 bytes. Wrote the mp table end at: 000f0410 - 000f06b4 Adding CBMEM entry as no. 3 Wrote the mp table end at: 7fff1410 - 7fff16b4 MP table: 692 bytes. Multiboot Information structure has been written. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 5bdf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x7fff2400 rom_table_end = 0x7fff2400 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x7fff2400 to 0x80000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000007ffeffff: RAM 3. 000000007fff0000-000000007fffffff: CONFIGURATION TABLES 4. 0000000080000000-00000000bfffffff: RAM 5. 0000000100000000-000000013fffffff: RAM Wrote coreboot table at: 7fff2400 - 7fff2cd0 checksum 8b9a coreboot table: 2256 bytes. 0. FREE SPACE 7fff4400 0000bc00 1. GDT 7fff0200 00000200 2. IRQ TABLE 7fff0400 00001000 3. SMP TABLE 7fff1400 00001000 4. COREBOOT 7fff2400 00002000 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + b139 + align -> fff0b180 Check fallback/payload Got a payload Loading segment from rom address 0xfff0b1b8 data (compression=1) malloc Enter, size 36, free_mem_ptr 00162aa8 malloc 00162aa8 New segment dstaddr 0xec400 memsize 0x13c00 srcaddr 0xfff0b1f0 filesize 0x9dc3 (cleaned up) New segment addr 0xec400 size 0x13c00 offset 0xfff0b1f0 filesize 0x9dc3 Loading segment from rom address 0xfff0b1d4 Entry Point 0x000fdf82 Loading Segment: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 filesz: 0x0000000000009dc3 lb: [0x0000000000100000, 0x0000000000164000) Post relocation: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 filesz: 0x0000000000009dc3 using LZMA [ 0x00000000000ec400, 0000000000100000, 0x0000000000100000) <- 00000000fff0b1f0 dest 000ec400, end 00100000, bouncebuffer bff38000 Loaded segments Jumping to boot code at fdf82 entry = 0x000fdf82 lb_start = 0x00100000 lb_size = 0x00064000 adjust = 0xbfe9c000 buffer = 0xbff38000 elf_boot_notes = 0x001154a0 adjusted_boot_notes = 0xbffb14a0 Start bios (version 0.6.0-20100326_214650-morn.localdomain) Found mainboard Supermicro H8DME-2 Found CBFS header at 0xfffeffe0 Ram Size=0xc0000000 (0x0000000040000000 high) CPU Mhz=2000 Found 4 cpu(s) max supported 4 cpu(s) Copying PIR from 0x7fff0400 to 0x000f7b80 Copying MPTABLE from 0x7fff1400/7fff1410 to 0x000f78c0 SMBIOS ptr=0x000f78a0 table=0xbffffe70 Scan for VGA option rom Running option rom at c000:0003 Turning on vga console Starting SeaBIOS (version 0.6.0-20100326_214650-morn.localdomain) EHCI init on dev 00:02.1 (regs=0xfc14b020) Found 0 lpt ports Found 1 serial ports ATA controller 0 at 1f0/3f4/0 (irq 14 dev 20) ATA controller 1 at 170/374/0 (irq 15 dev 20) ATA controller 2 at 3000/3040/0 (irq 0 dev 28) ata0-0: SONY DVD RW DRU-840A ATAPI-7 CD-Rom/DVD-Rom ATA controller 3 at 3008/3044/0 (irq 0 dev 28) ATA controller 4 at 3010/3048/0 (irq 0 dev 29) ATA controller 5 at 3018/304c/0 (irq 0 dev 29) ATA controller 6 at 3020/3050/0 (irq 0 dev 2a) ATA controller 7 at 3028/3054/0 (irq 0 dev 2a) ata2-0: WDC WD1601ABYS-01C0A0 ATA-8 Hard-Disk (153 GiBytes) drive 0x000f7790: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=321672960 PS2 keyboard initialized Scan for option roms Press F12 for boot menu. Returned 61440 bytes of ZoneHigh e820 map has 8 items: 0: 0000000000000000 - 000000000009f400 = 1 1: 000000000009f400 - 00000000000a0000 = 2 2: 00000000000f0000 - 0000000000100000 = 2 3: 0000000000100000 - 000000007fff0000 = 1 4: 000000007fff0000 - 0000000080000000 = 2 5: 0000000080000000 - 00000000bffff000 = 1 6: 00000000bffff000 - 00000000c0000000 = 2 7: 0000000100000000 - 0000000140000000 = 1 enter handle_19: NULL Booting from Floppy... Boot failed: could not read the boot disk enter handle_18: NULL Booting from CD-Rom... Device reports MEDIUM NOT PRESENT atapi_is_ready returned -1 Boot failed: Could not read from CDROM (code 0003) enter handle_18: NULL Booting from Hard Disk... Booting from 0000:7c00 From joe.korty at ccur.com Thu May 13 19:12:22 2010 From: joe.korty at ccur.com (Joe Korty) Date: Thu, 13 May 2010 13:12:22 -0400 Subject: [coreboot] it boots! [was: re: H8DME-2 woes, continued....] In-Reply-To: <20100512000128.8767.qmail@stuge.se> References: <20100505200608.GA15441@tsunami.ccur.com> <20100511195620.GA3442@tsunami.ccur.com> <20100511215429.GA5588@tsunami.ccur.com> <20100512000128.8767.qmail@stuge.se> Message-ID: <20100513171222.GA24306@tsunami.ccur.com> On Tue, May 11, 2010 at 08:01:28PM -0400, Peter Stuge wrote: > Can you check which codec you have please? Linux reports this. From > my laptop: > > [ 3.509587] ALSA device list: > [ 3.509593] #0: Intel 82801DB-ICH4 with AD1981B at irq 17 > > AD1981B is the codec. Hi Peter, Sorry, I didn't see your request in this, your earlier email. I don't have an 'ALSA' labeled line in either dmesg or in /var/log/messages. I've grepped for other strings that might indicate the sound card used (eg, sound, audio, nvidia, mcp55, ICH) but nothing has come up yet. lspci says: 00:06.1 Audio device: nVidia Corporation MCP55 High Definition Audio (rev a2) Joe From peter at stuge.se Thu May 13 19:17:23 2010 From: peter at stuge.se (Peter Stuge) Date: Thu, 13 May 2010 19:17:23 +0200 Subject: [coreboot] it boots! [was: re: H8DME-2 woes, continued....] In-Reply-To: <20100513171222.GA24306@tsunami.ccur.com> References: <20100505200608.GA15441@tsunami.ccur.com> <20100511195620.GA3442@tsunami.ccur.com> <20100511215429.GA5588@tsunami.ccur.com> <20100512000128.8767.qmail@stuge.se> <20100513171222.GA24306@tsunami.ccur.com> Message-ID: <20100513171723.18008.qmail@stuge.se> Hi Joe, Joe Korty wrote: > > Can you check which codec you have please? Linux reports this. From > > my laptop: > > > > [ 3.509587] ALSA device list: > > [ 3.509593] #0: Intel 82801DB-ICH4 with AD1981B at irq 17 > > > > AD1981B is the codec. > > Hi Peter, > Sorry, I didn't see your request in this, your earlier email. No problem - thanks for checking this! > I don't have an 'ALSA' labeled line in either dmesg or in > /var/log/messages. Ahh - then the sound drivers simply aren't loaded. There's noone else in the system that would care about the codec so then the info isn't to be found. Unfortunately they manual doesn't mention audio hardware at all. :\ Thanks! //Peter From dhendrix at google.com Thu May 13 22:26:04 2010 From: dhendrix at google.com (David Hendricks) Date: Thu, 13 May 2010 13:26:04 -0700 Subject: [coreboot] flashrom command line syntax change In-Reply-To: <4BEA39A9.7040403@gmx.net> References: <4BEA39A9.7040403@gmx.net> Message-ID: On Tue, May 11, 2010 at 10:16 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006 at gmx.net> wrote: > Hi, > > [please followup to flashrom at flashrom.org] > > since I didn't get any answers except "hmm..." on IRC, I hope that list > feedback will be more verbose. > > In the past, flashrom served one purpose (developers writing LinuxBIOS > images or parts thereof to onboard flash), but nowadays it can handle > external programmers, graphics/network/storage cards and other hardware > as well. Given that the flashrom user base is growing rapidly especially > among less technically inclined people, we changed the flashrom command > line interface in various ways to eliminate nasty surprises. > > The flashrom 0.9.2 release is impending (only one small bugfix and one > big frontend/documentation patch left), and this is why I'd like > comments about the following change: > > -r and -w and -v currently take a filename argument, but that filename > can be anywhere on the command line. Examples: > > flashrom -p dummy backup.rom -r > flashrom -rp dummy backup.rom > flashrom -rV backup.rom > flashrom -p dummy -r backup.rom > > This flashrom behaviour is confusing and contradicts the man page which > says that -r/-w/-v are followed by a filename. Besides that, all other > options with arguments want their arguments directly after the option. > > I posted a patch which will make the accepted command line syntax > conform to the man page, but I'd like to hear about any problems this > change may cause. > The patch is at http://patchwork.coreboot.org/patch/1298/ (click on > "patch" to download it in raw form) and applies cleanly against latest > flashrom from svn. > > Tests of current svn flashrom with the patch applied are really > appreciated, and feedback about the interface change will be taken > seriously. I like the suggestion. There are lots of programs out there which presume that the first string encountered that does not have a flag assigned to it, e.g. -p or -c or whatever, is the filename to operate on. That behavior is nice when the program does not require arguments to behave in a sane manner, e.g. *mplayer foo.ogg*. This usage model doesn't make sense for Flashrom, so it makes sense to treat the filename as any other argument and require that it has a flag preceding it to define the behavior. /my $0.02 -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -------------- next part -------------- An HTML attachment was scrubbed... URL: From buurin at gmail.com Fri May 14 04:03:34 2010 From: buurin at gmail.com (Keith Hui) Date: Thu, 13 May 2010 22:03:34 -0400 Subject: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this Message-ID: Hi all, This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other related changes (below), so it is gzipped. I may have committed a few "crimes" here, but anyway... First, I found out why the debug output isn't correct - A typo caused the cache size to got lost amid the shuffle. It has been fixed in this version. This patch: 1. Brings back L2 initialization from coreboot v1 for family 63x,65x and 67x CPUs. Need someone with a Mendocino Celeron to see if the entire 128k of L2 is still enabled. 2. Split model_67x/65x and model_63x from model_6xx. model_67x also serves model 65x because they share too much code. Also included are Intel microcode for all CPUs in these families. There's just one file for all microcodes in one family. 3. In Slot 1 Makefile.inc, conditionally bring in sources in models 63x/67x/6bx only when the proper config has been selected in Kconfig. Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has been selected. 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above. 5. Blocked out some apparently unused #includes from model_6xx_init.c. Once we're sure nothing really are using it, then remove them. Bootlog with a PIII 600MHz can be found here: http://coreboot.pastebin.com/PNUzJXZT Have fun, bon appetit and cheers. Signed-off-by: Keith Hui On Wed, May 12, 2010 at 12:16 PM, Joseph Smith wrote: > > > > On Wed, 12 May 2010 11:48:57 -0400, Keith Hui wrote: >> Yes, the debug output from the L2 init code does say 128K, but >> /proc/cpuinfo reports 512K. This is where I'd like some expert >> opinions. >> > Sure, but we need to see the code to give an opinion :-) > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > > -------------- next part -------------- A non-text attachment was scrubbed... Name: p6l2cache.patch.gz Type: application/x-gzip Size: 47499 bytes Desc: not available URL: From joe at settoplinux.org Fri May 14 04:28:57 2010 From: joe at settoplinux.org (Joseph Smith) Date: Thu, 13 May 2010 22:28:57 -0400 Subject: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this In-Reply-To: References: Message-ID: <4BECB569.5070700@settoplinux.org> On 05/13/2010 10:03 PM, Keith Hui wrote: > Hi all, > > This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other > related changes (below), so it is gzipped. I may have committed a few > "crimes" here, but anyway... > > First, I found out why the debug output isn't correct - A typo caused > the cache size to got lost amid the shuffle. It has been fixed in this > version. > > This patch: > 1. Brings back L2 initialization from coreboot v1 for family 63x,65x > and 67x CPUs. Need someone with a Mendocino Celeron to see if the > entire 128k of L2 is still enabled. > 2. Split model_67x/65x and model_63x from model_6xx. model_67x also > serves model 65x because they share too much code. Also included are > Intel microcode for all CPUs in these families. There's just one file > for all microcodes in one family. > 3. In Slot 1 Makefile.inc, conditionally bring in sources in models > 63x/67x/6bx only when the proper config has been selected in Kconfig. > Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has > been selected. > 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the > mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above. > 5. Blocked out some apparently unused #includes from model_6xx_init.c. > Once we're sure nothing really are using it, then remove them. > > Bootlog with a PIII 600MHz can be found here: > http://coreboot.pastebin.com/PNUzJXZT > > Have fun, bon appetit and cheers. > > Signed-off-by: Keith Hui This looks awesome Keith! Great Work :-) I can only see one thing that needs fixing and it is cosmetic: Lines 394-395 of bootlog look good: CPU: vendor Intel device 673 CPU: family 06, model 07, stepping 03 But, Line 411 of bootlog: CPU: . + /* Print processor name */ + fill_processor_name(processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); Is the %s not working? Otherwise, Acked-by: Joseph Smith -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From buurin at gmail.com Fri May 14 05:20:14 2010 From: buurin at gmail.com (Keith Hui) Date: Thu, 13 May 2010 23:20:14 -0400 Subject: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this In-Reply-To: References: Message-ID: The original patch was unclean as pork (didn't apply cleanly). Please use this one instead. Thanks Joseph. And edit your board's romstage similar to patch below: Index: src/mainboard/asus/p2b-ls/romstage.c =================================================================== --- src/mainboard/asus/p2b-ls/romstage.c (revision 5543) +++ src/mainboard/asus/p2b-ls/romstage.c (working copy) @@ -33,7 +33,9 @@ #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" +#if CONFIG_ROMCC==1 #include "cpu/x86/mtrr/earlymtrr.c" +#endif #include "cpu/x86/bist.h" /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" @@ -46,12 +48,20 @@ } #include "northbridge/intel/i440bx/raminit.c" +#if CONFIG_DEBUG_RAM_SETUP #include "northbridge/intel/i440bx/debug.c" +#endif -static void main(unsigned long bist) +#if CONFIG_ROMCC +static /* This is part of main() declaration below for romcc only. */ +#endif + +void main(unsigned long bist) { +#if CONFIG_ROMCC if (bist == 0) early_mtrr_init(); +#endif /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -63,10 +73,14 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */ enable_smbus(); - /* dump_spd_registers(); */ +#if CONFIG_DEBUG_RAM_SETUP + dump_spd_registers(); +#endif sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ +#if CONFIG_DEBUG_RAM_SETUP + ram_check(0, 640 * 1024); +#endif } > > This patch: > 1. Brings back L2 initialization from coreboot v1 for family 63x,65x > and 67x CPUs. Need someone with a Mendocino Celeron to see if the > entire 128k of L2 is still enabled. > 2. Split model_67x/65x and model_63x from model_6xx. model_67x also > serves model 65x because they share too much code. Also included are > Intel microcode for all CPUs in these families. There's just one file > for all microcodes in one family. > 3. In Slot 1 Makefile.inc, conditionally bring in sources in models > 63x/67x/6bx only when the proper config has been selected in Kconfig. > Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has > been selected. > 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the > mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above. > 5. Blocked out some apparently unused #includes from model_6xx_init.c. > Once we're sure nothing really are using it, then remove them. > > Bootlog with a PIII 600MHz can be found here: > http://coreboot.pastebin.com/PNUzJXZT > > Have fun, bon appetit and cheers. > Signed-off-by: Keith Hui -------------- next part -------------- A non-text attachment was scrubbed... Name: p6l2cache.patch.gz Type: application/x-gzip Size: 48674 bytes Desc: not available URL: From buurin at gmail.com Fri May 14 05:30:02 2010 From: buurin at gmail.com (Keith Hui) Date: Thu, 13 May 2010 23:30:02 -0400 Subject: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this In-Reply-To: <4BECB569.5070700@settoplinux.org> References: <4BECB569.5070700@settoplinux.org> Message-ID: On Thu, May 13, 2010 at 10:28 PM, Joseph Smith wrote: > On 05/13/2010 10:03 PM, Keith Hui wrote: >> >> Hi all, >> >> This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other >> related changes (below), so it is gzipped. I may have committed a few >> "crimes" here, but anyway... >> >> First, I found out why the debug output isn't correct - A typo caused >> the cache size to got lost amid the shuffle. It has been fixed in this >> version. >> >> This patch: >> 1. Brings back L2 initialization from coreboot v1 for family 63x,65x >> and 67x CPUs. Need someone with a Mendocino Celeron to see if the >> entire 128k of L2 is still enabled. >> 2. Split model_67x/65x and model_63x from model_6xx. model_67x also >> serves model 65x because they share too much code. Also included are >> Intel microcode for all CPUs in these families. There's just one file >> for all microcodes in one family. >> 3. In Slot 1 Makefile.inc, conditionally bring in sources in models >> 63x/67x/6bx only when the proper config has been selected in Kconfig. >> Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has >> been selected. >> 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the >> mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above. >> 5. Blocked out some apparently unused #includes from model_6xx_init.c. >> Once we're sure nothing really are using it, then remove them. >> >> Bootlog with a PIII 600MHz can be found here: >> http://coreboot.pastebin.com/PNUzJXZT >> >> Have fun, bon appetit and cheers. >> >> Signed-off-by: Keith Hui > > This looks awesome Keith! Great Work :-) > I can only see one thing that needs fixing and it is cosmetic: > > Lines 394-395 of bootlog look good: > > CPU: vendor Intel device 673 > CPU: family 06, model 07, stepping 03 > > > But, Line 411 of bootlog: ?CPU: . > > + ? ? ? /* Print processor name */ > + ? ? ? fill_processor_name(processor_name); > + ? ? ? printk(BIOS_INFO, "CPU: %s.\n", processor_name); > > Is the %s not working? > I think that's because Katmai doesn't support processor brand string through CPUID. See page 3-197, volume 2A, Intel Software Developer's Manual It's cosmetic. This code can be removed from model 63x and 67x in the next patch. Thanks Keith From knuku at gap.upv.es Fri May 14 10:21:35 2010 From: knuku at gap.upv.es (Knut Kujat) Date: Fri, 14 May 2010 10:21:35 +0200 Subject: [coreboot] H8QME 128GB RAM not Booting In-Reply-To: <80BDD8AE9779451BACFD2F54F4D26C8D@chimp> References: <4BEA8B3F.7080501@gap.upv.es> <80BDD8AE9779451BACFD2F54F4D26C8D@chimp> Message-ID: <4BED080F.6010107@gap.upv.es> Myles Watson escribi?: >> I have a board here with 128GB Ram (16*8GB) and it won't boot. It hangs >> at "Copying data from cache to RAM -- switching to use RAM as stack...". >> So at least ram initialization is done, but why does it stop booting? >> Some values I have to increment in order to use more RAM? >> > > Most likely RAM init didn't work. You could run showallroutes() right > before that message and do some basic RAM tests to see. > > Thanks, > Myles > > > Hi, like always, thanks for your help Myles! I steal one of the 8GB dimms and put it on one of my test machines I configured coreboot to only initialize one CPU/CORE and therefore only the 8GB. Booting with this configuration leads to the same result as on the 128GB machine it hangs at the first memcopy it finds so the problem seem to be the dimm itself but it is still DDR 2. I attached the showroutes and dumpmem outputs. raminit_amdmct() DRAM(40)0000000000-0000ffffff, ->(0), R, W, No interleave, 0 MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(b8)00fc000000-00ffffffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 PCIIO(c0)0000000-1ffffff, ->(0,2), , ,VGA 0 ISA 0 PCIIO(c8)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0 PCIIO(d0)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0 CONFIG(e0)00-ff ->(0,2),R W (bus numbers) raminit_amdmct begin: DCTInit_D: mct_DIMMPresence Done DCTInit_D: mct_SPDCalcWidth Done DCTInit_D: mct_DIMMPresence Done DCTInit_D: mct_SPDCalcWidth Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D Node: 00 base: 00 limit: 7fffff BottomIO: e00000 raminit_amdmct end: *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf18 testx = 5a5a5a5a dump_mem: 000c8000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c80a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c80b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c80c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c80d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c80e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c80f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c81a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c81b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c81c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c81d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c81e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c81f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8270: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8290: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c82a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c82b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c82c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c82d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c82e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c82f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8310: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8330: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8370: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8380: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c8390: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c83a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c83b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c83c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c83d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c83e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000c83f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Copying data from cache to RAM -- switching to use RAM as stack... Thanks, Knut Kujat. From svn at coreboot.org Fri May 14 11:45:30 2010 From: svn at coreboot.org (repository service) Date: Fri, 14 May 2010 11:45:30 +0200 Subject: [coreboot] [commit] r5544 - in trunk/src/mainboard/wyse: . s50 Message-ID: Author: stepan Date: Fri May 14 11:45:29 2010 New Revision: 5544 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5544 Log: This patch cleanes up the Wyse S50 port and unifies the memmory regions with Geode LX , adds gpl2 headers plus some white space fixes. This is build and boot tested.(of course vsa loading is stil not fixed,it now runs forever with :"Oops, exception 13 while executing option rom") Signed-off-by: Nils Jacobs Acked-by: Stefan Reinauer Modified: trunk/src/mainboard/wyse/Kconfig trunk/src/mainboard/wyse/s50/Kconfig trunk/src/mainboard/wyse/s50/chip.h trunk/src/mainboard/wyse/s50/cmos.layout trunk/src/mainboard/wyse/s50/devicetree.cb trunk/src/mainboard/wyse/s50/irq_tables.c trunk/src/mainboard/wyse/s50/mainboard.c trunk/src/mainboard/wyse/s50/romstage.c Modified: trunk/src/mainboard/wyse/Kconfig ============================================================================== --- trunk/src/mainboard/wyse/Kconfig Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/Kconfig Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Nils Jacobs +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + choice prompt "Mainboard model" depends on VENDOR_WYSE Modified: trunk/src/mainboard/wyse/s50/Kconfig ============================================================================== --- trunk/src/mainboard/wyse/s50/Kconfig Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/Kconfig Fri May 14 11:45:29 2010 (r5544) @@ -1,12 +1,11 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann +## Copyright (C) 2010 Nils Jacobs ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -49,3 +48,8 @@ int default 3 depends on BOARD_WYSE_S50 + +config RAMBASE + hex + default 0x4000 + depends on BOARD_WYSE_S50 Modified: trunk/src/mainboard/wyse/s50/chip.h ============================================================================== --- trunk/src/mainboard/wyse/s50/chip.h Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/chip.h Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + extern struct chip_operations mainboard_ops; struct mainboard_config { Modified: trunk/src/mainboard/wyse/s50/cmos.layout ============================================================================== --- trunk/src/mainboard/wyse/s50/cmos.layout Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/cmos.layout Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,26 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Nils Jacobs +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- + entries #start-bit length config config-ID name Modified: trunk/src/mainboard/wyse/s50/devicetree.cb ============================================================================== --- trunk/src/mainboard/wyse/s50/devicetree.cb Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/devicetree.cb Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Nils Jacobs +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + chip northbridge/amd/gx2 register "irqmap" = "0xaa5b" register "setupflash" = "0" Modified: trunk/src/mainboard/wyse/s50/irq_tables.c ============================================================================== --- trunk/src/mainboard/wyse/s50/irq_tables.c Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/irq_tables.c Fri May 14 11:45:29 2010 (r5544) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 200x TODO + * Copyright (C) 2010 Nils Jacobs * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: trunk/src/mainboard/wyse/s50/mainboard.c ============================================================================== --- trunk/src/mainboard/wyse/s50/mainboard.c Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/mainboard.c Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + #include #include #include Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/romstage.c Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + #include #include #include @@ -20,16 +41,17 @@ #include "northbridge/amd/gx2/raminit.h" + /* This is needed because ROMCC doesn`t now the ctz bitop */ static inline unsigned int ctz(unsigned int n) { - int zeros; + int zeros; - n = (n ^ (n - 1)) >> 1; + n = (n ^ (n - 1)) >> 1; for (zeros = 0; n; zeros++) { n >>= 1; } - return zeros; + return zeros; } static void sdram_set_spd_registers(const struct mem_controller *ctrl) @@ -42,7 +64,7 @@ msr_t msr; unsigned char module_banks, val; uint16_t dimm_size; - + msr = rdmsr(MC_CF07_DATA); /* get module banks (sides) per dimm, SPD byte 5 */ @@ -97,35 +119,30 @@ #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" - #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" static void msr_init(void) { - /* total physical memory */ - __builtin_wrmsr(0x1808, 0x11f6bf00, 0x21c00002); - - /* traditional memory 0kB-512kB, 512kB-1MB */ - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); - __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2dfbc040); - __builtin_wrmsr(0x10000028, 0x6bf00100, 0x2000001f); - __builtin_wrmsr(0x1000002c, 0xffff0003, 0x2000ffff); - - __builtin_wrmsr(0x10000080, 0x3, 0x0); - - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); - __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040); - __builtin_wrmsr(0x40000029, 0x6bf00100, 0x2000001f); - __builtin_wrmsr(0x4000002d, 0xffff0003, 0x2000ffff); - - __builtin_wrmsr(0x40000080, 0x1, 0x0); - - __builtin_wrmsr(0x50002001, 0x27, 0x0); - __builtin_wrmsr(0x4c002001, 0x1, 0x0); + /* Setup access to cache under 1MB. + __builtin_wrmsr(CPU_RCONF_DEFAULT, 0x1000a000, 0x24fffc02); /* Rom Properties: Write Serialize, WriteProtect. + * RomBase: 0xFFFC0 + * SysTop to RomBase Properties: Write Serialize, Cache Disable. + * SysTop: 0x000A0 + * System Memory Properties: (Write Back) */ + + __builtin_wrmsr(CPU_RCONF_A0_BF, 0x00000000, 0x00000000); /* 0xA0000-0xBFFFF : (Write Back) */ + __builtin_wrmsr(CPU_RCONF_C0_DF, 0x00000000, 0x00000000); /* 0xC0000-0xDFFFF : (Write Back) */ + __builtin_wrmsr(CPU_RCONF_E0_FF, 0x00000000, 0x00000000); /* 0xE0000-0xFFFFF : (Write Back) */ + + /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ + __builtin_wrmsr(MSR_GLIU0_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */ + __builtin_wrmsr(MSR_GLIU0_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */ + __builtin_wrmsr(MSR_GLIU0_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */ + __builtin_wrmsr(MSR_GLIU1_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */ + __builtin_wrmsr(MSR_GLIU1_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */ + __builtin_wrmsr(MSR_GLIU1_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */ /* put code in northbridge[init].c here */ } @@ -137,13 +154,13 @@ }; SystemPreInit(); - msr_init(); cs5536_early_setup(); - + /* disable the power button */ outl(0x00, PMS_IO_BASE + 0x40); + /* cs5536_disable_internal_uart disable them. Set them up now... */ cs5536_setup_onchipuart(1); uart_init(); @@ -157,6 +174,8 @@ sdram_initialize(1, memctrl); print_err("ram setup done\n"); + msr_init(); + /* Check all of memory */ /*ram_check(0x00000000, 640*1024);*/ print_err("ram check done\n"); From svn at coreboot.org Fri May 14 11:48:07 2010 From: svn at coreboot.org (repository service) Date: Fri, 14 May 2010 11:48:07 +0200 Subject: [coreboot] [commit] r5545 - in trunk/src: cpu/amd/model_gx1 cpu/intel/slot_1 cpu/intel/slot_2 cpu/intel/socket_PGA370 mainboard/a-trend mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit mai... Message-ID: Author: stepan Date: Fri May 14 11:48:05 2010 New Revision: 5545 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5545 Log: license header fixes Signed-off-by: Nils Jacobs Acked-by: Stefan Reinauer Modified: trunk/src/cpu/amd/model_gx1/Kconfig trunk/src/cpu/intel/slot_1/Kconfig trunk/src/cpu/intel/slot_2/Kconfig trunk/src/cpu/intel/socket_PGA370/Kconfig trunk/src/mainboard/a-trend/Kconfig trunk/src/mainboard/a-trend/atc-6220/Kconfig trunk/src/mainboard/a-trend/atc-6240/Kconfig trunk/src/mainboard/abit/Kconfig trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig trunk/src/mainboard/advantech/Kconfig trunk/src/mainboard/advantech/pcm-5820/Kconfig trunk/src/mainboard/amd/rumba/Kconfig trunk/src/mainboard/asi/Kconfig trunk/src/mainboard/asi/mb_5blgp/Kconfig trunk/src/mainboard/asi/mb_5blmp/Kconfig trunk/src/mainboard/asrock/Kconfig trunk/src/mainboard/asus/Kconfig trunk/src/mainboard/asus/m2v-mx_se/Kconfig trunk/src/mainboard/asus/mew-am/Kconfig trunk/src/mainboard/asus/mew-vm/Kconfig trunk/src/mainboard/asus/p2b-d/Kconfig trunk/src/mainboard/asus/p2b-ds/Kconfig trunk/src/mainboard/asus/p2b-f/Kconfig trunk/src/mainboard/asus/p2b-ls/Kconfig trunk/src/mainboard/asus/p2b/Kconfig trunk/src/mainboard/asus/p3b-f/Kconfig trunk/src/mainboard/axus/Kconfig trunk/src/mainboard/axus/tc320/Kconfig trunk/src/mainboard/azza/Kconfig trunk/src/mainboard/azza/pt-6ibd/Kconfig trunk/src/mainboard/bcom/Kconfig trunk/src/mainboard/bcom/winnet100/Kconfig trunk/src/mainboard/biostar/Kconfig trunk/src/mainboard/biostar/m6tba/Kconfig trunk/src/mainboard/compaq/Kconfig trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig trunk/src/mainboard/eaglelion/5bcm/Kconfig trunk/src/mainboard/eaglelion/Kconfig trunk/src/mainboard/gigabyte/Kconfig trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig trunk/src/mainboard/iei/Kconfig trunk/src/mainboard/iei/juki-511p/Kconfig trunk/src/mainboard/iei/nova4899r/Kconfig trunk/src/mainboard/mitac/6513wu/Kconfig trunk/src/mainboard/mitac/Kconfig trunk/src/mainboard/msi/Kconfig trunk/src/mainboard/msi/ms6119/Kconfig trunk/src/mainboard/msi/ms6147/Kconfig trunk/src/mainboard/msi/ms6156/Kconfig trunk/src/mainboard/msi/ms6178/Kconfig trunk/src/mainboard/nec/Kconfig trunk/src/mainboard/nec/powermate2000/Kconfig trunk/src/mainboard/nokia/Kconfig trunk/src/mainboard/nokia/ip530/Kconfig trunk/src/mainboard/soyo/Kconfig trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig trunk/src/mainboard/televideo/Kconfig trunk/src/mainboard/televideo/tc7020/Kconfig trunk/src/mainboard/tyan/Kconfig trunk/src/mainboard/tyan/s1846/Kconfig trunk/src/mainboard/winent/Kconfig trunk/src/northbridge/amd/gx1/Kconfig trunk/src/northbridge/intel/i440bx/Kconfig trunk/src/northbridge/intel/i440lx/Kconfig trunk/src/northbridge/intel/i82810/Kconfig trunk/src/southbridge/amd/cs5530/Kconfig trunk/src/southbridge/intel/i82801ax/Kconfig trunk/src/southbridge/intel/i82801bx/Kconfig Modified: trunk/src/cpu/amd/model_gx1/Kconfig ============================================================================== --- trunk/src/cpu/amd/model_gx1/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/cpu/amd/model_gx1/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/cpu/intel/slot_1/Kconfig ============================================================================== --- trunk/src/cpu/intel/slot_1/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/cpu/intel/slot_1/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/cpu/intel/slot_2/Kconfig ============================================================================== --- trunk/src/cpu/intel/slot_2/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/cpu/intel/slot_2/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/cpu/intel/socket_PGA370/Kconfig ============================================================================== --- trunk/src/cpu/intel/socket_PGA370/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/cpu/intel/socket_PGA370/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/a-trend/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/a-trend/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/a-trend/atc-6220/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/a-trend/atc-6220/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/a-trend/atc-6240/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/a-trend/atc-6240/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/abit/Kconfig ============================================================================== --- trunk/src/mainboard/abit/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/abit/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/advantech/Kconfig ============================================================================== --- trunk/src/mainboard/advantech/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/advantech/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/advantech/pcm-5820/Kconfig ============================================================================== --- trunk/src/mainboard/advantech/pcm-5820/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/advantech/pcm-5820/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/amd/rumba/Kconfig ============================================================================== --- trunk/src/mainboard/amd/rumba/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/amd/rumba/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asi/Kconfig ============================================================================== --- trunk/src/mainboard/asi/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asi/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asi/mb_5blgp/Kconfig ============================================================================== --- trunk/src/mainboard/asi/mb_5blgp/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asi/mb_5blgp/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asi/mb_5blmp/Kconfig ============================================================================== --- trunk/src/mainboard/asi/mb_5blmp/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asi/mb_5blmp/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asrock/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asrock/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asus/Kconfig ============================================================================== --- trunk/src/mainboard/asus/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asus/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,12 +5,11 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License Modified: trunk/src/mainboard/asus/mew-am/Kconfig ============================================================================== --- trunk/src/mainboard/asus/mew-am/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asus/mew-am/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asus/mew-vm/Kconfig ============================================================================== --- trunk/src/mainboard/asus/mew-vm/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asus/mew-vm/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asus/p2b-d/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-d/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asus/p2b-d/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asus/p2b-ds/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asus/p2b-ds/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asus/p2b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-f/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asus/p2b-f/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asus/p2b-ls/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asus/p2b-ls/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asus/p2b/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asus/p2b/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/asus/p3b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p3b-f/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/asus/p3b-f/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/axus/Kconfig ============================================================================== --- trunk/src/mainboard/axus/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/axus/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/axus/tc320/Kconfig ============================================================================== --- trunk/src/mainboard/axus/tc320/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/axus/tc320/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/azza/Kconfig ============================================================================== --- trunk/src/mainboard/azza/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/azza/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/azza/pt-6ibd/Kconfig ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/azza/pt-6ibd/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/bcom/Kconfig ============================================================================== --- trunk/src/mainboard/bcom/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/bcom/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/bcom/winnet100/Kconfig ============================================================================== --- trunk/src/mainboard/bcom/winnet100/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/bcom/winnet100/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/biostar/Kconfig ============================================================================== --- trunk/src/mainboard/biostar/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/biostar/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/biostar/m6tba/Kconfig ============================================================================== --- trunk/src/mainboard/biostar/m6tba/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/biostar/m6tba/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/compaq/Kconfig ============================================================================== --- trunk/src/mainboard/compaq/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/compaq/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/eaglelion/5bcm/Kconfig ============================================================================== --- trunk/src/mainboard/eaglelion/5bcm/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/eaglelion/5bcm/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/eaglelion/Kconfig ============================================================================== --- trunk/src/mainboard/eaglelion/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/eaglelion/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/gigabyte/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/gigabyte/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/iei/Kconfig ============================================================================== --- trunk/src/mainboard/iei/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/iei/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/iei/juki-511p/Kconfig ============================================================================== --- trunk/src/mainboard/iei/juki-511p/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/iei/juki-511p/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/iei/nova4899r/Kconfig ============================================================================== --- trunk/src/mainboard/iei/nova4899r/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/iei/nova4899r/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/mitac/6513wu/Kconfig ============================================================================== --- trunk/src/mainboard/mitac/6513wu/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/mitac/6513wu/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/mitac/Kconfig ============================================================================== --- trunk/src/mainboard/mitac/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/mitac/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/msi/Kconfig ============================================================================== --- trunk/src/mainboard/msi/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/msi/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/msi/ms6119/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6119/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/msi/ms6119/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/msi/ms6147/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6147/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/msi/ms6147/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/msi/ms6156/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6156/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/msi/ms6156/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/msi/ms6178/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6178/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/msi/ms6178/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/nec/Kconfig ============================================================================== --- trunk/src/mainboard/nec/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/nec/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/nec/powermate2000/Kconfig ============================================================================== --- trunk/src/mainboard/nec/powermate2000/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/nec/powermate2000/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/nokia/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/nokia/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/ip530/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/nokia/ip530/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/soyo/Kconfig ============================================================================== --- trunk/src/mainboard/soyo/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/soyo/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/televideo/Kconfig ============================================================================== --- trunk/src/mainboard/televideo/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/televideo/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/televideo/tc7020/Kconfig ============================================================================== --- trunk/src/mainboard/televideo/tc7020/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/televideo/tc7020/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/tyan/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/tyan/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/tyan/s1846/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s1846/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/tyan/s1846/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/winent/Kconfig ============================================================================== --- trunk/src/mainboard/winent/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/mainboard/winent/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/northbridge/amd/gx1/Kconfig ============================================================================== --- trunk/src/northbridge/amd/gx1/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/northbridge/amd/gx1/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/northbridge/intel/i440bx/Kconfig ============================================================================== --- trunk/src/northbridge/intel/i440bx/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/northbridge/intel/i440bx/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/northbridge/intel/i440lx/Kconfig ============================================================================== --- trunk/src/northbridge/intel/i440lx/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/northbridge/intel/i440lx/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/northbridge/intel/i82810/Kconfig ============================================================================== --- trunk/src/northbridge/intel/i82810/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/northbridge/intel/i82810/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/southbridge/amd/cs5530/Kconfig ============================================================================== --- trunk/src/southbridge/amd/cs5530/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/southbridge/amd/cs5530/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/southbridge/intel/i82801ax/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801ax/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/southbridge/intel/i82801ax/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/southbridge/intel/i82801bx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801bx/Kconfig Fri May 14 11:45:29 2010 (r5544) +++ trunk/src/southbridge/intel/i82801bx/Kconfig Fri May 14 11:48:05 2010 (r5545) @@ -5,8 +5,7 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of From svn at coreboot.org Fri May 14 11:56:47 2010 From: svn at coreboot.org (repository service) Date: Fri, 14 May 2010 11:56:47 +0200 Subject: [coreboot] [commit] r5546 - trunk/src/northbridge/amd/gx2 Message-ID: Author: stepan Date: Fri May 14 11:56:46 2010 New Revision: 5546 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5546 Log: Fix warning. Hardware tested and didn't change behavior. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/northbridge/amd/gx2/chipsetinit.c Modified: trunk/src/northbridge/amd/gx2/chipsetinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/chipsetinit.c Fri May 14 11:48:05 2010 (r5545) +++ trunk/src/northbridge/amd/gx2/chipsetinit.c Fri May 14 11:56:46 2010 (r5546) @@ -268,7 +268,7 @@ if ((msr.lo&0xff) == 0x11) return; - totalmem = sizeram() << 20 - 1; + totalmem = (sizeram() << 20) - 1; // highest address totalmem >>= 12; totalmem = ~totalmem; totalmem &= 0xfffff; From svn at coreboot.org Fri May 14 12:00:00 2010 From: svn at coreboot.org (repository service) Date: Fri, 14 May 2010 12:00:00 +0200 Subject: [coreboot] [commit] r5547 - trunk/src/northbridge/amd/gx2 Message-ID: Author: stepan Date: Fri May 14 11:59:59 2010 New Revision: 5547 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5547 Log: fix SeaBIOS loading on GX2. Signed-off-by: Nils Jacobs Acked-by: Stefan Reinauer Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridgeinit.c Fri May 14 11:56:46 2010 (r5546) +++ trunk/src/northbridge/amd/gx2/northbridgeinit.c Fri May 14 11:59:59 2010 (r5547) @@ -672,7 +672,7 @@ { uint64_t shadowSettings = getShadow(); shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes - shadowSettings |= (uint64_t) 0x00000000F0000000ULL; // Enable reads for F0000-FFFFF + shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable reads for C0000-FFFFF setShadow(shadowSettings); } From svn at coreboot.org Fri May 14 13:02:56 2010 From: svn at coreboot.org (repository service) Date: Fri, 14 May 2010 13:02:56 +0200 Subject: [coreboot] [commit] r5548 - in trunk/src: cpu/amd/car cpu/amd/model_10xxx cpu/amd/quadcore mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah_fam10 mainboard/amd/tilapia_fam10 mainboard/msi/ms9652_f... Message-ID: Author: oxygene Date: Fri May 14 13:02:56 2010 New Revision: 5548 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5548 Log: Remove another set of includes from Fam10 romstages: northbridge/amd/amdht/ht_wrapper.c northbridge/amd/amdfam10/raminit_amdmct.c cpu/amd/model_10xxx/fidvid.c pc80/mc146818rtc_early.c They are now included by the fam10 chipset code that requires them. Signed-off-by: Patrick Georgi Acked-by: Peter Stuge Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c trunk/src/northbridge/amd/amdht/h3gtopo.h Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c ============================================================================== --- trunk/src/cpu/amd/car/post_cache_as_ram.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/cpu/amd/car/post_cache_as_ram.c Fri May 14 13:02:56 2010 (r5548) @@ -3,7 +3,9 @@ */ #include #include +#include #include "cpu/amd/car/disable_cache_as_ram.c" +#include "cpu/x86/mtrr/earlymtrr.c" static inline void print_debug_pcar(const char *strval, uint32_t val) { Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Fri May 14 13:02:56 2010 (r5548) @@ -18,7 +18,7 @@ */ #if SET_FIDVID == 1 -#include "../../../northbridge/amd/amdht/AsPsDefs.h" +#include #define SET_FIDVID_DEBUG 1 Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Fri May 14 13:02:56 2010 (r5548) @@ -25,6 +25,9 @@ #include #include +#include +#include + //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef SET_FIDVID #define SET_FIDVID 1 @@ -976,3 +979,5 @@ } #endif } + +#include "fidvid.c" Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/cpu/amd/quadcore/quadcore.c Fri May 14 13:02:56 2010 (r5548) @@ -18,6 +18,8 @@ */ #include +#include +#include #ifndef SET_NB_CFG_54 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -46,7 +46,6 @@ #include #include #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include #include "lib/ramtest.c" #include @@ -82,10 +81,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -95,7 +92,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -46,7 +46,6 @@ #include #include #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include #include "lib/ramtest.c" #include @@ -104,10 +103,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -117,7 +114,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -46,7 +46,6 @@ #include #include #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include #include "lib/ramtest.c" #include @@ -82,10 +81,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -95,7 +92,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -44,7 +44,6 @@ #include #include #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" @@ -88,10 +87,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -123,7 +120,6 @@ #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -42,7 +42,6 @@ #include #include #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include #include "lib/ramtest.c" @@ -83,10 +82,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -108,7 +105,6 @@ #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -42,7 +42,6 @@ #include #include #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include #include "lib/ramtest.c" @@ -86,10 +85,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -113,7 +110,6 @@ #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -44,7 +44,6 @@ #include #include #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" @@ -88,10 +87,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -120,7 +117,6 @@ #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" Modified: trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Fri May 14 13:02:56 2010 (r5548) @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include static void set_htic_bit(u8 i, u32 val, u8 bit) { Modified: trunk/src/northbridge/amd/amdht/h3gtopo.h ============================================================================== --- trunk/src/northbridge/amd/amdht/h3gtopo.h Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/northbridge/amd/amdht/h3gtopo.h Fri May 14 13:02:56 2010 (r5548) @@ -20,6 +20,8 @@ #ifndef HTTOPO_H #define HTTOPO_H +#include + /*---------------------------------------------------------------------------- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) * From stepan at coresystems.de Fri May 14 13:13:39 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 14 May 2010 13:13:39 +0200 Subject: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code Message-ID: <4BED3063.7050300@coresystems.de> This patch should fix the hda interrupt lost problem on the Wyse S50 -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: cs5536_setup_fix.diff URL: From stefan.reinauer at coresystems.de Fri May 14 13:17:11 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Fri, 14 May 2010 13:17:11 +0200 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <20100513165627.GA24079@tsunami.ccur.com> References: <20100512151245.GA14873@tsunami.ccur.com> <4BEC0FE0.8080409@coresystems.de> <20100513150822.GA16268@tsunami.ccur.com> <4BEC1D74.50302@coresystems.de> <20100513165627.GA24079@tsunami.ccur.com> Message-ID: <4BED3137.8070603@coresystems.de> On 5/13/10 6:56 PM, Joe Korty wrote: > On Thu, May 13, 2010 at 11:40:36AM -0400, Stefan Reinauer wrote: > >> On 5/13/10 5:08 PM, Joe Korty wrote: >> >>> On Thu, May 13, 2010 at 10:42:40AM -0400, Stefan Reinauer wrote: >>> >>> >>>> the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a >>>> while ago and now I ported my version of the Azalia code to MCP55 / >>>> H8DME (assuming that's the board target you use for the H8DME-2) >>>> Can you please see if this is any better than before? It's likely that >>>> the verb table won't match the codec used on that board, but there only >>>> was a single codec in the mcp55 driver and the used codec is usually >>>> mainboard dependent, not chipset dependent. >>>> >>> >>> It works!!! >>> But I didn't hear a beep during coreboot. Was I supposed to? >>> >> No, no beeps... The driver just initializes the codec. >> >> If someone had a nice piece of code to output a sample on azalia >> devices, I think we should make it an option. I looked at alsa some time >> ago but found it less than trivial to extract the info useful for us. >> >> Could you please send a log file containing the output of the new azalia >> driver? >> > Sure. Here it is.... > Regards, > Joe > > PCI: 00:06.1 init > Azalia: codec type: Azalia > Azalia: base = fc140000 > Azalia: codec_mask = 01 > Azalia: Initializing codec #0 > PCI: 00:08.0 init > It's still timing out though, despite the fact that it knows there is a codec. Does sound work? -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From svn at coreboot.org Fri May 14 13:17:41 2010 From: svn at coreboot.org (coreboot) Date: Fri, 14 May 2010 11:17:41 -0000 Subject: [coreboot] #163: Board still requires RAMBASE <1MB Message-ID: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org> #163: Board still requires RAMBASE <1MB -------------------------+-------------------------------------------------- Reporter: oxygene | Owner: stepan@? Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Some boards have RAMBASE at 0x4000. For some, it's probably a left-over from old times, but others actually require it. Update the former, and fix the latter. Wyse/s50 requires 0x4000, see http://www.coreboot.org/pipermail/coreboot/2010-May/058080.html (and the log file therein) -- Ticket URL: coreboot From muellinger_hn at yahoo.de Fri May 14 13:02:54 2010 From: muellinger_hn at yahoo.de (=?iso-8859-1?Q?Carsten_M=FCller?=) Date: Fri, 14 May 2010 11:02:54 +0000 (GMT) Subject: [coreboot] How is the Status for 845 Chipset (Akimbo 1150 / Thomson IP1101) ? Message-ID: <29807.76380.qm@web26207.mail.ukl.yahoo.com> Hi, i know that someone is trying to get coreboot to run on the Akimbo 1150 STB with Intel 845 Chipset. I have a Thomson IP1101 which has the same board in it and i'd like to know if there is any news about runnin coreboot on this platform. Thanks! Carsten From joe at settoplinux.org Fri May 14 14:27:51 2010 From: joe at settoplinux.org (Joseph Smith) Date: Fri, 14 May 2010 08:27:51 -0400 Subject: [coreboot] =?utf-8?q?How_is_the_Status_for_854_Chipset_=28Akimbo_?= =?utf-8?q?1150_/_Thomson_IP1101=29_=3F?= In-Reply-To: <29807.76380.qm@web26207.mail.ukl.yahoo.com> References: <29807.76380.qm@web26207.mail.ukl.yahoo.com> Message-ID: On Fri, 14 May 2010 11:02:54 +0000 (GMT), Carsten M?ller wrote: > Hi, > i know that someone is trying to get coreboot to run on the Akimbo 1150 STB > with Intel 845 Chipset. I have a Thomson IP1101 which has the same board in > it and i'd like to know if there is any news about runnin coreboot on this > platform. > Greetings, I think you meant the i854 (different beast). It is coming? I seem to be getting more and more requests for the i854 lately. I am just trying to work out some issues on the i830 TV-out code that will be transferable to the i854. As soon as that is done I will be starting on i854 (this includes Thomson IP1101, Akimbo 1150, and Tatung 5000). I actually am supposed to be receiving a package from Germany sometime soon (hint, hint) with a couple of IP1101?s to develop on :-) So stay tuned.... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From muellinger_hn at yahoo.de Fri May 14 14:40:47 2010 From: muellinger_hn at yahoo.de (=?utf-8?B?Q2Fyc3RlbiBNw7xsbGVy?=) Date: Fri, 14 May 2010 12:40:47 +0000 (GMT) Subject: [coreboot] How is the Status for 854 Chipset (Akimbo 1150 / Thomson IP1101) ? In-Reply-To: Message-ID: <725672.74567.qm@web26204.mail.ukl.yahoo.com> Hi Joseph, thanks four your reply. It is really interesting and i'll "stay tuned"! :-) I have some problems getting linux the mambux way that blocks my plan making a linux based NAS with the IP1101. Until theres anything new from your site i'll keep using it wathing some IPTV :-) You rock! best regards and have a nice weekend. Carsten --- Joseph Smith schrieb am Fr, 14.5.2010: > Von: Joseph Smith > Betreff: Re: [coreboot] How is the Status for 854 Chipset (Akimbo 1150 / Thomson IP1101) ? > An: "Carsten M?ller" > CC: coreboot at coreboot.org > Datum: Freitag, 14. Mai, 2010 14:27 Uhr > > > > On Fri, 14 May 2010 11:02:54 +0000 (GMT), Carsten M?ller > > wrote: > > Hi, > > i know that someone is trying to get coreboot to run > on the Akimbo 1150 > STB > > with Intel 845 Chipset. I have a Thomson IP1101 which > has the same board > in > > it and i'd like to know if there is any news about > runnin coreboot on > this > > platform. > > > Greetings, > I think you meant the i854 (different beast). It is > coming? > I seem to be getting more and more requests for the i854 > lately. I am just > trying to work out some issues on the i830 TV-out code that > will be > transferable to the i854. As soon as that is done I will be > starting on > i854 (this includes Thomson IP1101, Akimbo 1150, and Tatung > 5000). > > I actually am supposed to be receiving a package from > Germany sometime soon > (hint, hint) with a couple of IP1101?s to develop on :-) > > So stay tuned.... > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > > From joe.korty at ccur.com Fri May 14 16:29:28 2010 From: joe.korty at ccur.com (Joe Korty) Date: Fri, 14 May 2010 10:29:28 -0400 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <4BED3137.8070603@coresystems.de> References: <20100512151245.GA14873@tsunami.ccur.com> <4BEC0FE0.8080409@coresystems.de> <20100513150822.GA16268@tsunami.ccur.com> <4BEC1D74.50302@coresystems.de> <20100513165627.GA24079@tsunami.ccur.com> <4BED3137.8070603@coresystems.de> Message-ID: <20100514142928.GA12805@tsunami.ccur.com> On Fri, May 14, 2010 at 07:17:11AM -0400, Stefan Reinauer wrote: > >> Could you please send a log file containing the output of the new azalia > >> driver? > > > > PCI: 00:06.1 init > > Azalia: codec type: Azalia > > Azalia: base = fc140000 > > Azalia: codec_mask = 01 > > Azalia: Initializing codec #0 > > PCI: 00:08.0 init > > > It's still timing out though, despite the fact that it knows there is a > codec. > > Does sound work? Hi Stefan, Believe it or not, I see no audio-out port on the back of the motherboard. The H8DME-2's manual does not show one on its schematic, and a grep of the text shows no mention of audio output capabilities. I never noticed this until now, since I have no interest in audio in any of my projects. Joe PS: I'm curious, why does coreboot need to initialize the audio? It has no need of audio itself, and AFAIK, no payload which follows coreboot needs audio either. I believe that if coreboot restricted itself to initializing only that which was absolutely essential, it would become intrinsically more stable. From mylesgw at gmail.com Fri May 14 16:30:02 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 14 May 2010 08:30:02 -0600 Subject: [coreboot] H8QME 128GB RAM not Booting In-Reply-To: <4BED080F.6010107@gap.upv.es> References: <4BEA8B3F.7080501@gap.upv.es> <80BDD8AE9779451BACFD2F54F4D26C8D@chimp> <4BED080F.6010107@gap.upv.es> Message-ID: <9820C255EB4E474E955BE647812A3A74@chimp> > I steal one of the 8GB dimms and put it on one of my test machines I > configured coreboot to only initialize one CPU/CORE and therefore only > the 8GB. Booting with this configuration leads to the same result as on > the 128GB machine it hangs at the first memcopy it finds so the problem > seem to be the dimm itself but it is still DDR 2. I'm glad you could narrow it down. I would expect that no one had tested the code with 8GB dimms, so maybe you should be looking for a math/logic error (or just missing code) in the sizing or initialization? > > I attached the showroutes and dumpmem outputs. > > raminit_amdmct() > DRAM(40)0000000000-0000ffffff, ->(0), R, W, No interleave, 0 > MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 > MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 > MMIO(b8)00fc000000-00ffffffff, ->(0,0), , , CPU disable 0, Lock 0, Non > posted 0 This is wrong, but shouldn't affect this problem. Your buses and I/O are on node 0 link 2, but your MMIO is on node 0 link 0. > PCIIO(c0)0000000-1ffffff, ->(0,2), , ,VGA 0 ISA 0 > PCIIO(c8)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0 > PCIIO(d0)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0 > CONFIG(e0)00-ff ->(0,2),R W (bus numbers) > raminit_amdmct begin: > DCTInit_D: mct_DIMMPresence Done > DCTInit_D: mct_SPDCalcWidth Done > DCTInit_D: mct_DIMMPresence Done > DCTInit_D: mct_SPDCalcWidth Done > DCTInit_D: AutoCycTiming_D Done > DCTInit_D: AutoConfig_D Done > DCTInit_D: PlatformSpec_D Done > DCTInit_D: StartupDCT_D > Node: 00 base: 00 limit: 7fffff BottomIO: e00000 limit 7fffff = 2 GB of RAM. > raminit_amdmct end: > > *** Yes, the copy/decompress is taking a while, FIXME! > v_esp=000cbf18 > testx = 5a5a5a5a > dump_mem: > 000c8000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 I think the other end of the stack would be more interesting. Something like 0xcbf00-0xcc000 (CAR). Then you could dump the RAM for the stack too. I guess since you know it's not working, seeing the values wouldn't really help. I'd try looking at the values you see in raminit, and why the dimm isn't getting initialized correctly. Thanks, Myles From vidwer at gmail.com Fri May 14 16:10:02 2010 From: vidwer at gmail.com (Idwer Vollering) Date: Fri, 14 May 2010 16:10:02 +0200 Subject: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this In-Reply-To: References: Message-ID: 2010/5/14 Keith Hui > The original patch was unclean as pork (didn't apply cleanly). Please > use this one instead. > > Thanks Joseph. > > And edit your board's romstage similar to patch below: > > Index: src/mainboard/asus/p2b-ls/romstage.c > =================================================================== > --- src/mainboard/asus/p2b-ls/romstage.c (revision 5543) > +++ src/mainboard/asus/p2b-ls/romstage.c (working copy) > @@ -33,7 +33,9 @@ > #include "lib/debug.c" > #include "pc80/udelay_io.c" > #include "lib/delay.c" > +#if CONFIG_ROMCC==1 > #include "cpu/x86/mtrr/earlymtrr.c" > +#endif > #include "cpu/x86/bist.h" > /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ > #include "superio/winbond/w83977tf/w83977tf_early_serial.c" > @@ -46,12 +48,20 @@ > } > > #include "northbridge/intel/i440bx/raminit.c" > +#if CONFIG_DEBUG_RAM_SETUP > #include "northbridge/intel/i440bx/debug.c" > +#endif > > -static void main(unsigned long bist) > +#if CONFIG_ROMCC > +static /* This is part of main() declaration below for romcc only. */ > +#endif > + > +void main(unsigned long bist) > { > +#if CONFIG_ROMCC > if (bist == 0) > early_mtrr_init(); > +#endif > > /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ > w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); > @@ -63,10 +73,14 @@ > i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */ > > enable_smbus(); > - /* dump_spd_registers(); */ > +#if CONFIG_DEBUG_RAM_SETUP > + dump_spd_registers(); > +#endif > sdram_set_registers(); > sdram_set_spd_registers(); > sdram_enable(); > - /* ram_check(0, 640 * 1024); */ > +#if CONFIG_DEBUG_RAM_SETUP > + ram_check(0, 640 * 1024); > +#endif > } > > The only additional adjustment I had to make was in raminit.c: Index: src/northbridge/intel/i440bx/raminit.c =================================================================== --- src/northbridge/intel/i440bx/raminit.c (revision 5543) +++ src/northbridge/intel/i440bx/raminit.c (working copy) @@ -947,7 +947,7 @@ set_dram_row_attributes(); /* TODO: Set SDRAMC. */ - pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config */ + pci_write_config16(NB, SDRAMC, 0x0000); /* SDRAMPWR=0: 3 DIMM config */ /* TODO */ set_dram_buffer_strength(); > > > > This patch: > > 1. Brings back L2 initialization from coreboot v1 for family 63x,65x > > and 67x CPUs. Need someone with a Mendocino Celeron to see if the > > entire 128k of L2 is still enabled. > > 2. Split model_67x/65x and model_63x from model_6xx. model_67x also > > serves model 65x because they share too much code. Also included are > > Intel microcode for all CPUs in these families. There's just one file > > for all microcodes in one family. > > 3. In Slot 1 Makefile.inc, conditionally bring in sources in models > > 63x/67x/6bx only when the proper config has been selected in Kconfig. > > Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has > > been selected. > > 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the > > mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above. > > 5. Blocked out some apparently unused #includes from model_6xx_init.c. > > Once we're sure nothing really are using it, then remove them. > > > > Bootlog with a PIII 600MHz can be found here: > > http://coreboot.pastebin.com/PNUzJXZT > Bootlog with a 450MHz P3: http://coreboot.pastebin.com/DAqztY9H [ 0.005829] CPU: L1 I cache: 16K, L1 D cache: 16K [ 0.005952] CPU: L2 cache: 512K > > > > Have fun, bon appetit and cheers. > > > > Signed-off-by: Keith Hui > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.reinauer at coresystems.de Fri May 14 16:45:54 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Fri, 14 May 2010 16:45:54 +0200 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <20100514142928.GA12805@tsunami.ccur.com> References: <20100512151245.GA14873@tsunami.ccur.com> <4BEC0FE0.8080409@coresystems.de> <20100513150822.GA16268@tsunami.ccur.com> <4BEC1D74.50302@coresystems.de> <20100513165627.GA24079@tsunami.ccur.com> <4BED3137.8070603@coresystems.de> <20100514142928.GA12805@tsunami.ccur.com> Message-ID: <4BED6222.4000802@coresystems.de> On 5/14/10 4:29 PM, Joe Korty wrote: > PS: I'm curious, why does coreboot need to initialize > the audio? It has no need of audio itself, and AFAIK, > no payload which follows coreboot needs audio either. > The wiring of the codec is mainboard specific and all Windows and Linux drivers expect the BIOS to set up the Azalia codecs, or sound will not work correctly. This is not something that could be probed by the OS otherwise. > I believe that if coreboot restricted itself to > initializing only that which was absolutely essential, > it would become intrinsically more stable. > Oh, that is absolutely what we do. If the mainboard porters care to do their job right. However many people assume that they don't have to worry since they don't use a certain feature for their project and just leave it as it is. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From buurin at gmail.com Fri May 14 17:05:11 2010 From: buurin at gmail.com (Keith Hui) Date: Fri, 14 May 2010 11:05:11 -0400 Subject: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this In-Reply-To: References: Message-ID: On Fri, May 14, 2010 at 10:10 AM, Idwer Vollering wrote: > 2010/5/14 Keith Hui >> >> The original patch was unclean as pork (didn't apply cleanly). Please >> use this one instead. >> >> Thanks Joseph. >> >> And edit your board's romstage similar to patch below: > > The only additional adjustment I had to make was in raminit.c: > > Index: src/northbridge/intel/i440bx/raminit.c > =================================================================== > --- src/northbridge/intel/i440bx/raminit.c????? (revision 5543) > +++ src/northbridge/intel/i440bx/raminit.c????? (working copy) > @@ -947,7 +947,7 @@ > ??????? set_dram_row_attributes(); > > ??????? /* TODO: Set SDRAMC. */ > -?????? pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config > */ > +?????? pci_write_config16(NB, SDRAMC, 0x0000); /* SDRAMPWR=0: 3 DIMM config > */ > > ??????? /* TODO */ > ??????? set_dram_buffer_strength(); > So the reason you were having your problems seems to be your CPUID isn't included in the family_67x whitelist of CPUIDs. No compiled in CPU driver claims your cpuid, then it just dies. Hmm... You have the same cpuid as mine. Interesting. Anyway, That line you edited should have been removed altogether as that register was already set elsewhere. I submitted a cleanup patch for this and don't know how it end up. BTW enable CAR and try again. We want to officially migrate the ASUS P2B family to CAR. Cheers Keith From joe.korty at ccur.com Fri May 14 17:38:18 2010 From: joe.korty at ccur.com (Joe Korty) Date: Fri, 14 May 2010 11:38:18 -0400 Subject: [coreboot] it boots! [was: re: H8DME-2 woes, continued....] In-Reply-To: <20100513171723.18008.qmail@stuge.se> References: <20100505200608.GA15441@tsunami.ccur.com> <20100511195620.GA3442@tsunami.ccur.com> <20100511215429.GA5588@tsunami.ccur.com> <20100512000128.8767.qmail@stuge.se> <20100513171222.GA24306@tsunami.ccur.com> <20100513171723.18008.qmail@stuge.se> Message-ID: <20100514153818.GA19617@tsunami.ccur.com> On Thu, May 13, 2010 at 01:17:23PM -0400, Peter Stuge wrote: > Can you check which codec you have please? Linux reports this. From > my laptop: > > [ 3.509587] ALSA device list: > [ 3.509593] #0: Intel 82801DB-ICH4 with AD1981B at irq 17 > > Joe Korty wrote: >> I don't have an 'ALSA' labeled line in either dmesg or in >> /var/log/messages. > > Ahh - then the sound drivers simply aren't loaded. There's noone else > in the system that would care about the codec so then the info isn't > to be found. > > Unfortunately they manual doesn't mention audio hardware at all. :\ Hi Peter, I just booted with the original flash rather than with coreboot. This is to get the audio properly initialized by BIOS as Sefan mentions is required. Although I don't have the ALSA line (still), I do have these lines in /var/log/messages from the Linux azalia driver: mount used greatest stack depth: 5960 bytes left HDA Intel 0000:00:06.1: PCI->APIC IRQ transform: INT B -> IRQ 23 input: PC Speaker as /class/input/input2 eth1: no link during initialization. hda-intel: azx_get_response timeout, switching to polling mode: last cmd=0x000f0000 hda-intel: Codec #0 probe error; disabling it... hda_intel: azx_get_response timeout, switching to single_cmd mode: last cmd=0x000f0000 hda-intel: no codecs initialized Also, my mainboard has no audio-out jack.... Regards, Joe From anders at jenbo.dk Fri May 14 17:38:24 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Fri, 14 May 2010 17:38:24 +0200 Subject: [coreboot] =?utf-8?q?Re__=5BPATCH=5D_SECC_Pentium_2/3_users_are_g?= =?utf-8?q?onna_love_this?= Message-ID: Just fund a Celeron coppermine (686), The chipset of the mainboard seams to be mostly supported so shouldn't take to long to port and test. L2 is 128kb. Mvh Anders ----- Reply message ----- Fra: "Keith Hui" Dato: fre., maj 14, 2010 05:30 Emne: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this Til: "Joseph Smith" Cc: On Thu, May 13, 2010 at 10:28 PM, Joseph Smith wrote: > On 05/13/2010 10:03 PM, Keith Hui wrote: >> >> Hi all, >> >> This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other >> related changes (below), so it is gzipped. I may have committed a few >> "crimes" here, but anyway... >> >> First, I found out why the debug output isn't correct - A typo caused >> the cache size to got lost amid the shuffle. It has been fixed in this >> version. >> >> This patch: >> 1. Brings back L2 initialization from coreboot v1 for family 63x,65x >> and 67x CPUs. Need someone with a Mendocino Celeron to see if the >> entire 128k of L2 is still enabled. >> 2. Split model_67x/65x and model_63x from model_6xx. model_67x also >> serves model 65x because they share too much code. Also included are >> Intel microcode for all CPUs in these families. There's just one file >> for all microcodes in one family. >> 3. In Slot 1 Makefile.inc, conditionally bring in sources in models >> 63x/67x/6bx only when the proper config has been selected in Kconfig. >> Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has >> been selected. >> 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the >> mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above. >> 5. Blocked out some apparently unused #includes from model_6xx_init.c. >> Once we're sure nothing really are using it, then remove them. >> >> Bootlog with a PIII 600MHz can be found here: >> http://coreboot.pastebin.com/PNUzJXZT >> >> Have fun, bon appetit and cheers. >> >> Signed-off-by: Keith Hui > > This looks awesome Keith! Great Work :-) > I can only see one thing that needs fixing and it is cosmetic: > > Lines 394-395 of bootlog look good: > > CPU: vendor Intel device 673 > CPU: family 06, model 07, stepping 03 > > > But, Line 411 of bootlog: ?CPU: . > > + ? ? ? /* Print processor name */ > + ? ? ? fill_processor_name(processor_name); > + ? ? ? printk(BIOS_INFO, "CPU: %s.\n", processor_name); > > Is the %s not working? > I think that's because Katmai doesn't support processor brand string through CPUID. See page 3-197, volume 2A, Intel Software Developer's Manual It's cosmetic. This code can be removed from model 63x and 67x in the next patch. Thanks Keith -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Fri May 14 18:40:55 2010 From: svn at coreboot.org (repository service) Date: Fri, 14 May 2010 18:40:55 +0200 Subject: [coreboot] [commit] r5549 - trunk/util/superiotool Message-ID: Author: uwe Date: Fri May 14 18:40:55 2010 New Revision: 5549 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5549 Log: Various superiotool fixes. - IT8671F/IT8687R: - Fix typo: Parallel port register 0x60 value is 0x03 (not 0x01). - Fix typo: APC register 0xf6 is 0x00. - Drop register 0x07 (LDN 0 / none), that's not useful and not listed in any of the other Super I/Os either, it always contains the LDN number selected "last time", which is useless. - Fix indentation and other cosmetics. - Cosmetics, and consistency fixes in LDN names of various Super I/Os. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/util/superiotool/fintek.c trunk/util/superiotool/ite.c trunk/util/superiotool/winbond.c Modified: trunk/util/superiotool/fintek.c ============================================================================== --- trunk/util/superiotool/fintek.c Fri May 14 13:02:56 2010 (r5548) +++ trunk/util/superiotool/fintek.c Fri May 14 18:40:55 2010 (r5549) @@ -37,13 +37,13 @@ 0x2b,0x2c,0x2d,EOT}, {0x06,0x01,0x19,0x34,0x00,0x00,MISC,0x00,0x00,0x00, 0x00,0x00,0x08,EOT}}, - {0x0, "FDC", + {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, - {0x1, "UART1", + {0x1, "COM1", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x01,0x03,0xf8,0x04,0x00,EOT}}, - {0x2, "UART2", + {0x2, "COM2", {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, {0x3, "Parallel port", Modified: trunk/util/superiotool/ite.c ============================================================================== --- trunk/util/superiotool/ite.c Fri May 14 13:02:56 2010 (r5548) +++ trunk/util/superiotool/ite.c Fri May 14 18:40:55 2010 (r5549) @@ -74,74 +74,86 @@ {EOT}}}, {0x8681, "IT8671F/IT8687R", { {NOLDN, NULL, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x2E,0x2F,EOT}, - {NANA,NANA,NANA,NANA,NANA,NANA,0x00,NANA,0x86,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, - {0x0, "Floppy disk controller", - {0x30,0x31,0x60,0x61,0x70,0x71,0x74,0xF0,EOT}, - {0x00,0x00,0x03,0xF0,0x06,0x02,0x02,0x00,EOT}}, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x20,0x21,0x22, + 0x23,0x24,0x25,0x26,0x2e,0x2f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x86,0x81,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x31,0x60,0x61,0x70,0x71,0x74,0xf0,EOT}, + {0x00,0x00,0x03,0xf0,0x06,0x02,0x02,0x00,EOT}}, {0x1, "COM1", - {0x30,0x31,0x60,0x61,0x70,0x71,0xF0,EOT}, - {0x00,0x00,0x03,0xF8,0x04,0x02,0x00,EOT}}, + {0x30,0x31,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x03,0xf8,0x04,0x02,0x00,EOT}}, {0x2, "COM2", - {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0x72,0x73,0x74,0x75,0xF0,0xF1,EOT}, - {0x00,0x00,0x02,0xF8,0x03,0x00,0x03,0x02,0x0A,0x02,0x00,0x01,0x00,0x00,EOT}}, + {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0x72,0x73, + 0x74,0x75,0xf0,0xf1,EOT}, + {0x00,0x00,0x02,0xf8,0x03,0x00,0x03,0x02,0x0a,0x02, + 0x00,0x01,0x00,0x00,EOT}}, {0x3, "Parallel port", - {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0xF0,EOT}, - {0x00,0x00,0x01,0x78,0x07,0x78,0x07,0x02,0x03,0x03,EOT}}, + {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0x74, + 0xf0,EOT}, + {0x00,0x00,0x03,0x78,0x07,0x78,0x07,0x02,0x03, + 0x03,EOT}}, {0x4, "APC", - {0x30,0xF0,0xF1,0xF2,0xF4,0xF5,0xF6,EOT}, - {0x00,0x00,0x00,0x00,0x00,0x00,NANA,EOT}}, + {0x30,0xf0,0xf1,0xf2,0xf4,0xf5,0xf6,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {0x5, "Keyboard", - {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0xF0,EOT}, - {0x01,0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x00,EOT}}, + {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {MISC,0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x00,EOT}}, {0x6, "Mouse", - {0x30,0x70,0x71,0xF0,EOT}, - {0x00,0x0C,0x02,0x00,EOT}}, - {0x7, "GPIO and Alternative function", - {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x70,0x71,0x72,0x73,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF,0xE0,0xE1,0xE2,0xE3,0xE4,EOT}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x30,0x70,0x71,0xf0,EOT}, + {0x00,0x0c,0x02,0x00,EOT}}, + {0x7, "GPIO", + {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69, + 0x70,0x71,0x72,0x73,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, + 0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff, + 0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,EOT}}, {EOT}}}, {0x8701, "IT8703F", { {NOLDN, NULL, - {0x20,0x21,0x23,0x24,0x26,0x29,0x2A,0x2B,EOT}, - {0x87,0x00,0x00,0x80,0x00,0x00,0x7C,0xC0,EOT}}, - {0x0, "Floppy disk controller", - {0x30,0x60,0x61,0x70,0x74,0xF0,0xF1,0xF2,0xF3,0xF4, - 0xF5,EOT}, - {0x00,0x03,0xf0,0x06,0x02,0x0E,0x00,0xFF,0x00,0x00, + {0x20,0x21,0x23,0x24,0x26,0x29,0x2a,0x2b,EOT}, + {0x87,0x00,0x00,0x80,0x00,0x00,0x7c,0xc0,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf3,0xf4, + 0xf5,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00,0x00, 0x00,EOT}}, {0x1, "Parallel port", {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT}, {0x00,0x03,0x78,0x00,0x80,0x07,0x03,0x03,EOT}}, - {0x2, "Serial port 1", + {0x2, "COM1", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0xf8,0x04,0x00,EOT}}, - {0x3, "Serial port 2", + {0x3, "COM2", {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, {0x00,0x02,0xf8,0x03,0x00,0x00,0x00,0x7f,EOT}}, - {0x5, "Keyboard controller", + {0x5, "Keyboard", {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, - {0x01,0x00,0x60,0x00,0x64,0x01,0x0C,0x80,EOT}}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x80,EOT}}, {0x6, "Consumer IR", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x00,0x00,0x00,EOT}}, {0x7, "Game port, MIDI, GPIO set 1", - {0x30,0x60,0x61,0x62,0x63,0x70,0xF0,0xF1,0xF2,EOT}, - {0x00,0x02,0x01,0x03,0x30,0x00,0xFF,0x00,0x00,EOT}}, + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,EOT}, + {0x00,0x02,0x01,0x03,0x30,0x00,0xff,0x00,0x00,EOT}}, {0x8, "GPIO set 2", - {0x30,0xF0,0xF1,0xF2,0xF3,0xF5,EOT}, - {0x00,0xFF,0x00,0x00,0x00,0x00,EOT}}, + {0x30,0xf0,0xf1,0xf2,0xf3,0xf5,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, {0x9, "GPIO set 3 and 4", - {0x30,0x60,0x61,0xF0,0xF1,0xF2,0xF3,0xF4,EOT}, - {0x00,0x02,0x90,0xFF,0x00,0x00,0x00,0x00,EOT}}, - {0xA, "ACPI", - {0x30,0x70,0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7, - 0xF3,0xF4,0xF6,0xF7,0xF9,EOT}, + {0x30,0x60,0x61,0xf0,0xf1,0xf2,0xf3,0xf4,EOT}, + {0x00,0x02,0x90,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "ACPI", + {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xf3,0xf4,0xf6,0xf7,0xf9,EOT}, {0x00,0x00,0x00,0x00,NANA,NANA,0x00,0x00,0x00,0x00, NANA,NANA,0x00,0x00,0x00,EOT}}, - {0xC, "GPIO set 5, 6 and 7", - {0x30,0x60,0x61,0xF0,0xF3,0xF6,EOT}, - {0x00,0x03,0x70,0x00,0xFF,0xFF,EOT}}, + {0xc, "GPIO set 5, 6 and 7", + {0x30,0x60,0x61,0xf0,0xf3,0xf6,EOT}, + {0x00,0x03,0x70,0x00,0xff,0xff,EOT}}, {EOT}}}, {0x8702, "IT8702F", { {EOT}}}, Modified: trunk/util/superiotool/winbond.c ============================================================================== --- trunk/util/superiotool/winbond.c Fri May 14 13:02:56 2010 (r5548) +++ trunk/util/superiotool/winbond.c Fri May 14 18:40:55 2010 (r5549) @@ -243,7 +243,8 @@ {0x9771, "W83977F-A/G-A/AF-A/AG-A", { {EOT}}}, {0x9777, "W83977AF", { - /* W83977AF as found on the Advantech PCM-5820. We weren't able + /* + * W83977AF as found on the Advantech PCM-5820. We weren't able * to find a datasheet (so far) which lists the 0x77 revision, * but the hardware is there in the wild, so detect it... */ From svn at coreboot.org Fri May 14 18:44:46 2010 From: svn at coreboot.org (repository service) Date: Fri, 14 May 2010 18:44:46 +0200 Subject: [coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi Message-ID: Author: stepan Date: Fri May 14 18:44:45 2010 New Revision: 5550 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5550 Log: Fix i945 ACPI for ASL Optimizing Compiler version 20100428. The values are overwritten on the fly but without the patch iasl will refuse to compile the code. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/northbridge/intel/i945/acpi/i945_hostbridge.asl Modified: trunk/src/northbridge/intel/i945/acpi/i945_hostbridge.asl ============================================================================== --- trunk/src/northbridge/intel/i945/acpi/i945_hostbridge.asl Fri May 14 18:40:55 2010 (r5549) +++ trunk/src/northbridge/intel/i945/acpi/i945_hostbridge.asl Fri May 14 18:44:45 2010 (r5550) @@ -207,17 +207,17 @@ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-0xfebfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0x00000000,,, PM01) + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + 0xfec00000,,, PM01) - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00000000,,, TPMR) + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) }) // Find PCI resource area in MCRS From joe.korty at ccur.com Fri May 14 18:45:27 2010 From: joe.korty at ccur.com (Joe Korty) Date: Fri, 14 May 2010 12:45:27 -0400 Subject: [coreboot] [PATCH] fix hd8me early-boot 50 sec stallout Message-ID: <20100514164527.GA24346@tsunami.ccur.com> Fix the SuperMicro H8DME-2 early-boot 50 sec stall. Somewhere between r5491 and r5496, a change occured which added some 30-50 seconds to the boot time of a Supermicro H8DME-2. This rises by an additional 30-50 seconds if the boot sequence decides it needs to reset-restart. The problem was traced to a printk which was enabled somewhere between those two svn revisions. Apparently this printk appears too early in the boot sequence to function correctly. This patch again comments out the printk, but this time around, adds an explanation, to encourage future maintainers to keep it commented out. Please apply. Joe Signed-off-by: Joe Korty Index: trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c =================================================================== --- trunk.orig/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c 2010-05-14 08:37:35.000000000 -0400 +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c 2010-05-14 08:39:06.000000000 -0400 @@ -32,11 +32,14 @@ device_t dev; dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0); +#if 0 + /* for the h8dme, at least, this is too early for a printk */ if (dev == PCI_DEV_INVALID) { printk(BIOS_WARNING, "SMBUS controller not found\n"); } else { printk(BIOS_DEBUG, "SMBus controller enabled\n"); } +#endif /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1); From vidwer at gmail.com Fri May 14 18:51:17 2010 From: vidwer at gmail.com (Idwer Vollering) Date: Fri, 14 May 2010 18:51:17 +0200 Subject: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this In-Reply-To: References: Message-ID: 2010/5/14 Keith Hui BTW enable CAR and try again. Like this (note that it doesn't boot my asus p2b, rev 1.04): svn diff src/mainboard/asus/p2b/Kconfig Index: src/mainboard/asus/p2b/Kconfig =================================================================== --- src/mainboard/asus/p2b/Kconfig (revision 5543) +++ src/mainboard/asus/p2b/Kconfig (working copy) @@ -25,7 +25,9 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC +# select ROMCC + select USE_PRINTK_IN_CAR + select CONFIG_USE_DCACHE_RAM select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 @@ -50,3 +52,13 @@ default 6 depends on BOARD_ASUS_P2B +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_ASUS_P2B + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_ASUS_P2B + -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Fri May 14 19:16:00 2010 From: svn at coreboot.org (repository service) Date: Fri, 14 May 2010 19:16:00 +0200 Subject: [coreboot] [commit] r5551 - in trunk/src/northbridge/amd: amdfam10 amdk8 Message-ID: Author: stepan Date: Fri May 14 19:15:57 2010 New Revision: 5551 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5551 Log: more acpica fixes... The tricky part is the stuff in the AMD mainboard directories. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_util.asl trunk/src/northbridge/amd/amdk8/amdk8_util.asl Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_util.asl ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10_util.asl Fri May 14 18:44:45 2010 (r5550) +++ trunk/src/northbridge/amd/amdfam10/amdfam10_util.asl Fri May 14 19:15:57 2010 (r5551) @@ -131,7 +131,7 @@ 0x0000, // Address Range Minimum 0x0000, // Address Range Maximum 0x0000, // Address Translation Offset - 0x0000,,,) + 0x0001,,,) }) CreateWordField (BUF0, 0x08, BMIN) CreateWordField (BUF0, 0x0A, BMAX) @@ -170,7 +170,7 @@ 0x00000000, // Address Range Minimum 0x00000000, // Address Range Maximum 0x00000000, // Address Translation Offset - 0x00000000,,, + 0x00000001,,, , AddressRangeMemory, TypeStatic) }) CreateDWordField (BUF0, 0x0A, MMIN) @@ -231,7 +231,7 @@ 0x00000000, // Address Range Minimum 0x00000000, // Address Range Maximum 0x00000000, // Address Translation Offset - 0x00000000,,, + 0x00000001,,, , TypeStatic) }) CreateDWordField (BUF0, 0x0A, PMIN) Modified: trunk/src/northbridge/amd/amdk8/amdk8_util.asl ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_util.asl Fri May 14 18:44:45 2010 (r5550) +++ trunk/src/northbridge/amd/amdk8/amdk8_util.asl Fri May 14 19:15:57 2010 (r5551) @@ -116,7 +116,7 @@ 0x0000, // Address Range Minimum 0x0000, // Address Range Maximum 0x0000, // Address Translation Offset - 0x0000,,,) + 0x0001,,,) }) CreateWordField (BUF0, 0x08, BMIN) CreateWordField (BUF0, 0x0A, BMAX) @@ -155,7 +155,7 @@ 0x00000000, // Address Range Minimum 0x00000000, // Address Range Maximum 0x00000000, // Address Translation Offset - 0x00000000,,, + 0x00000001,,, , AddressRangeMemory, TypeStatic) }) CreateDWordField (BUF0, 0x0A, MMIN) @@ -216,7 +216,7 @@ 0x00000000, // Address Range Minimum 0x00000000, // Address Range Maximum 0x00000000, // Address Translation Offset - 0x00000000,,, + 0x00000001,,, , TypeStatic) }) CreateDWordField (BUF0, 0x0A, PMIN) From uwe at hermann-uwe.de Fri May 14 19:17:46 2010 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 14 May 2010 19:17:46 +0200 Subject: [coreboot] License changes In-Reply-To: References: Message-ID: <20100514171746.GA6202@greenwood> On Fri, May 14, 2010 at 11:48:07AM +0200, repository service wrote: > Author: stepan > Date: Fri May 14 11:48:05 2010 > New Revision: 5545 > URL: https://tracker.coreboot.org/trac/coreboot/changeset/5545 > > Log: > license header fixes Please don't do this kind of change to any code other than trivial stuff like one-liner Kconfig files. I for one license all my code intentionally under "GPLv2-or-later" and I don't want that changed to "GPLv2-only". > Modified: trunk/src/mainboard/a-trend/atc-6220/Kconfig > ============================================================================== > --- trunk/src/mainboard/a-trend/atc-6220/Kconfig Fri May 14 11:45:29 2010 (r5544) > +++ trunk/src/mainboard/a-trend/atc-6220/Kconfig Fri May 14 11:48:05 2010 (r5545) > @@ -5,8 +5,7 @@ > ## > ## This program is free software; you can redistribute it and/or modify > ## it under the terms of the GNU General Public License as published by > -## the Free Software Foundation; either version 2 of the License, or > -## (at your option) any later version. > +## the Free Software Foundation; version 2 of the License. > ## > ## This program is distributed in the hope that it will be useful, > ## but WITHOUT ANY WARRANTY; without even the implied warranty of Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org From stefan.reinauer at coresystems.de Fri May 14 19:19:37 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Fri, 14 May 2010 19:19:37 +0200 Subject: [coreboot] [PATCH] update reference tool chain Message-ID: <4BED8629.4090003@coresystems.de> See patch -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: crossgcc-update.diff URL: From stefan.reinauer at coresystems.de Fri May 14 19:25:51 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Fri, 14 May 2010 19:25:51 +0200 Subject: [coreboot] License changes In-Reply-To: <20100514171746.GA6202@greenwood> References: <20100514171746.GA6202@greenwood> Message-ID: <4BED879F.7040708@coresystems.de> On 5/14/10 7:17 PM, Uwe Hermann wrote: > On Fri, May 14, 2010 at 11:48:07AM +0200, repository service wrote: > >> Author: stepan >> Date: Fri May 14 11:48:05 2010 >> New Revision: 5545 >> URL: https://tracker.coreboot.org/trac/coreboot/changeset/5545 >> >> Log: >> license header fixes >> > Please don't do this kind of change to any code other than trivial stuff > like one-liner Kconfig files. I for one license all my code > intentionally under "GPLv2-or-later" and I don't want that changed to > "GPLv2-only". > Oh, it said that the license choice was at my option. Sorry for that. Maybe the header should clarify whose option is meant, then. I think we should make clear which license we assign to the code. Having code in our tree which is licensed by anyone else's choice (i.e. not the authors of coreboot) is a legal concern. Since the complete project is v2 only, the headers should reflect this. That does of course not take your freedom to release the code under v2 or later, should anyone ask you or grab your patches from the list. Besides, most Kconfig scripts (which we are talking about here) are trivial few-liners indeed. Stefan From njacobs8 at hetnet.nl Fri May 14 19:57:22 2010 From: njacobs8 at hetnet.nl (Nils) Date: Fri, 14 May 2010 19:57:22 +0200 Subject: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code In-Reply-To: <4BED3063.7050300@coresystems.de> References: <4BED3063.7050300@coresystems.de> Message-ID: <201005141957.23113.njacobs8@hetnet.nl> Op vrijdag 14 mei 2010 13:13:39 schreef u: > This patch should fix the hda interrupt lost problem on the Wyse S50 > Hi Stefan, Thanks for making this patch. :) Unfortunately i have no time today to test it, maybe tomorrow evening. I quickly browsed the code, am i correct that you disabled the CS5536 code for GX2 ? You are aware of the fact that the wyse s50 has a CS5536? (i think the Rumba and olpc`s also) Thanks,Nils. From uwe at hermann-uwe.de Fri May 14 20:01:10 2010 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 14 May 2010 20:01:10 +0200 Subject: [coreboot] License changes In-Reply-To: <4BED879F.7040708@coresystems.de> References: <20100514171746.GA6202@greenwood> <4BED879F.7040708@coresystems.de> Message-ID: <20100514180110.GB6202@greenwood> On Fri, May 14, 2010 at 07:25:51PM +0200, Stefan Reinauer wrote: > Oh, it said that the license choice was at my option. Sorry for that. > Maybe the header should clarify whose option is meant, then. > > I think we should make clear which license we assign to the code. Having Sure, we already do that (well, in those files which _do_ have license headers, there are still quite a few which have none). Some coreboot files are GPL2, some or GPL2-or-later, some are BSD, some may be other GPL-compatible licenses. The coreboot code as a whole is GPL2-only as a result, but everyone is free to take out individual GPL2-or-later files and re-use them in GPL3 projects (which is one of the reasons I use GPL2-or-later). Or take out a BSD-licensed file and use it in BSD licensed projects etc. That does not change the fact that coreboot as a whole is GPL2-only. > code in our tree which is licensed by anyone else's choice (i.e. not the > authors of coreboot) is a legal concern. Since the complete project is > v2 only, the headers should reflect this. They already do, no reason for changes here. In addition, the README also states the coreboot license pretty clearly IMHO. > Besides, most Kconfig scripts (which we are talking about here) are > trivial few-liners indeed. Sure, not an issue in this case. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org From joe at settoplinux.org Fri May 14 20:03:25 2010 From: joe at settoplinux.org (Joseph Smith) Date: Fri, 14 May 2010 14:03:25 -0400 Subject: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code In-Reply-To: <201005141957.23113.njacobs8@hetnet.nl> References: <4BED3063.7050300@coresystems.de> <201005141957.23113.njacobs8@hetnet.nl> Message-ID: On Fri, 14 May 2010 19:57:22 +0200, Nils wrote: > Op vrijdag 14 mei 2010 13:13:39 schreef u: >> This patch should fix the hda interrupt lost problem on the Wyse S50 >> > Hi Stefan, > Thanks for making this patch. :) > Unfortunately i have no time today to test it, maybe tomorrow evening. > I quickly browsed the code, am i correct that you disabled the CS5536 > code for GX2 ? > You are aware of the fact that the wyse s50 has a CS5536? (i think the > Rumba > and olpc`s also) > Really? The Wyse S30 has GX2 and CS5535 -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From njacobs8 at hetnet.nl Fri May 14 20:04:06 2010 From: njacobs8 at hetnet.nl (Nils) Date: Fri, 14 May 2010 20:04:06 +0200 Subject: [coreboot] [commit] r5544 - in trunk/src/mainboard/wyse: . s50 Message-ID: <201005142004.06478.njacobs8@hetnet.nl> Hi Stefan, You wrote: >Author: stepan >Date: Fri May 14 11:45:29 2010 >New Revision: 5544 >URL: https://tracker.coreboot.org/trac/coreboot/changeset/5544 Thanks for committing! Regards,Nils. From peter at stuge.se Fri May 14 20:05:16 2010 From: peter at stuge.se (Peter Stuge) Date: Fri, 14 May 2010 20:05:16 +0200 Subject: [coreboot] [PATCH] watchdog mcp55's codec initialization loops In-Reply-To: <20100514142928.GA12805@tsunami.ccur.com> References: <20100512151245.GA14873@tsunami.ccur.com> <4BEC0FE0.8080409@coresystems.de> <20100513150822.GA16268@tsunami.ccur.com> <4BEC1D74.50302@coresystems.de> <20100513165627.GA24079@tsunami.ccur.com> <4BED3137.8070603@coresystems.de> <20100514142928.GA12805@tsunami.ccur.com> Message-ID: <20100514180516.27674.qmail@stuge.se> Joe Korty wrote: > > Does sound work? > > Hi Stefan, > Believe it or not, I see no audio-out port on the back of > the motherboard. The H8DME-2's manual does not show one > on its schematic, and a grep of the text shows no mention > of audio output capabilities. > > I never noticed this until now, since I have no interest > in audio in any of my projects. In order to help improve coreboot, could you try to load the right audio drivers for azalia and see what ends up in the kernel log? //Peter From peter at stuge.se Fri May 14 20:09:05 2010 From: peter at stuge.se (Peter Stuge) Date: Fri, 14 May 2010 20:09:05 +0200 Subject: [coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi In-Reply-To: References: Message-ID: <20100514180905.28227.qmail@stuge.se> repository service wrote: > Fix i945 ACPI for ASL Optimizing Compiler version 20100428. The whitespace changes in this commit made it difficult to see what was actually changed. :\ //Peter From njacobs8 at hetnet.nl Fri May 14 20:17:08 2010 From: njacobs8 at hetnet.nl (Nils) Date: Fri, 14 May 2010 20:17:08 +0200 Subject: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code In-Reply-To: References: <4BED3063.7050300@coresystems.de> <201005141957.23113.njacobs8@hetnet.nl> Message-ID: <201005142017.08342.njacobs8@hetnet.nl> Op vrijdag 14 mei 2010 20:03:25 schreef u: > On Fri, 14 May 2010 19:57:22 +0200, Nils wrote: > > Op vrijdag 14 mei 2010 13:13:39 schreef u: > >> This patch should fix the hda interrupt lost problem on the Wyse S50 > > > > Hi Stefan, > > Thanks for making this patch. :) > > Unfortunately i have no time today to test it, maybe tomorrow evening. > > I quickly browsed the code, am i correct that you disabled the CS5536 > > code for GX2 ? > > You are aware of the fact that the wyse s50 has a CS5536? (i think the > > Rumba > > and olpc`s also) > > Really? The Wyse S30 has GX2 and CS5535 > Hi Joseph, Really! See the attached lspci. Then your s30 has unfortunately slow usb ports. Thanks,Nils. -------------- next part -------------- -[0000:00]-+-01.0 National Semiconductor Corporation Geode GX2 Host Bridge [100b:0028] +-01.1 National Semiconductor Corporation Geode GX2 Graphics Processor [100b:0030] +-0e.0 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] +-0f.0 Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] +-0f.2 Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] +-0f.3 Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio [1022:2093] +-0f.4 Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] \-0f.5 Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] From buurin at gmail.com Fri May 14 20:25:07 2010 From: buurin at gmail.com (Keith Hui) Date: Fri, 14 May 2010 14:25:07 -0400 Subject: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this In-Reply-To: References: Message-ID: Limit your DCACHE_RAM_SIZE to 0x1000 (4k). The L2 init is done post-raminit so it's not available for CAR. Your CPU only has 16k of L1 cache available for CAR. HTH Keith On Fri, May 14, 2010 at 12:51 PM, Idwer Vollering wrote: > 2010/5/14 Keith Hui > >> BTW enable CAR and try again. > > Like this (note that it doesn't boot my asus p2b, rev 1.04): > > ?svn diff src/mainboard/asus/p2b/Kconfig > Index: src/mainboard/asus/p2b/Kconfig > =================================================================== > --- src/mainboard/asus/p2b/Kconfig????? (revision 5543) > +++ src/mainboard/asus/p2b/Kconfig????? (working copy) > @@ -25,7 +25,9 @@ > ??????? select NORTHBRIDGE_INTEL_I440BX > ??????? select SOUTHBRIDGE_INTEL_I82371EB > ??????? select SUPERIO_WINBOND_W83977TF > -?????? select ROMCC > +#????? select ROMCC > +?????? select USE_PRINTK_IN_CAR > +?????? select CONFIG_USE_DCACHE_RAM > ??????? select HAVE_PIRQ_TABLE > ??????? select UDELAY_TSC > ??????? select BOARD_ROMSIZE_KB_256 > @@ -50,3 +52,13 @@ > ??????? default 6 > ??????? depends on BOARD_ASUS_P2B > > +config DCACHE_RAM_BASE > +?????? hex > +?????? default 0xffdf8000 > +?????? depends on BOARD_ASUS_P2B > + > +config DCACHE_RAM_SIZE > +?????? hex > +?????? default 0x8000 > +?????? depends on BOARD_ASUS_P2B > + > > From stepan at coresystems.de Fri May 14 20:37:49 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 14 May 2010 20:37:49 +0200 Subject: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code In-Reply-To: <201005141957.23113.njacobs8@hetnet.nl> References: <4BED3063.7050300@coresystems.de> <201005141957.23113.njacobs8@hetnet.nl> Message-ID: <4BED987D.5060905@coresystems.de> On 5/14/10 7:57 PM, Nils wrote: > Op vrijdag 14 mei 2010 13:13:39 schreef u: > >> This patch should fix the hda interrupt lost problem on the Wyse S50 >> >> > Hi Stefan, > Thanks for making this patch. :) > Unfortunately i have no time today to test it, maybe tomorrow evening. > I quickly browsed the code, am i correct that you disabled the CS5536 > code for GX2 ? > You are aware of the fact that the wyse s50 has a CS5536? (i think the Rumba > and olpc`s also) > Hi Nils, until a while back the GX2 code contained code to set up the CS5535 and the CS5536. The CS5536 code under src/southbridge contained a different version of that code. But gcc chose to use the code under src/southbridge. Because that choice was rather arbitrary we cleaned up the GX2 code a while back to not call the src/southbridge init code but the version in src/northbridge, so it would work with the same code path of CS5535 and CS5536. However, the CS5536 code in src/northbridge is no good and so moved all CS5535/CS5536 code out of the GX2. The CS5535 code was moved to src/southbridge/CS5535, while the CS5536 code already contains a (working) version of that code that was previously living in the GX2 component. So, what I did is move CS5535 code to the CS5535 directory and make sure there is no southbridge code in the northbridge directory because it really does not belong there. Stefan From joe at settoplinux.org Fri May 14 20:41:01 2010 From: joe at settoplinux.org (Joseph Smith) Date: Fri, 14 May 2010 14:41:01 -0400 Subject: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code In-Reply-To: <201005142017.08342.njacobs8@hetnet.nl> References: <4BED3063.7050300@coresystems.de> <201005141957.23113.njacobs8@hetnet.nl> <201005142017.08342.njacobs8@hetnet.nl> Message-ID: <785770ddee356ad1f0f4feb0b9f728d9@imap.1and1.com> On Fri, 14 May 2010 20:17:08 +0200, Nils wrote: > Op vrijdag 14 mei 2010 20:03:25 schreef u: >> On Fri, 14 May 2010 19:57:22 +0200, Nils wrote: >> > Op vrijdag 14 mei 2010 13:13:39 schreef u: >> >> This patch should fix the hda interrupt lost problem on the Wyse S50 >> > >> > Hi Stefan, >> > Thanks for making this patch. :) >> > Unfortunately i have no time today to test it, maybe tomorrow evening. >> > I quickly browsed the code, am i correct that you disabled the CS5536 >> > code for GX2 ? >> > You are aware of the fact that the wyse s50 has a CS5536? (i think the >> > Rumba >> > and olpc`s also) >> >> Really? The Wyse S30 has GX2 and CS5535 >> > Hi Joseph, > Really! > See the attached lspci. > Then your s30 has unfortunately slow usb ports. > No it has a VIA USB 2.0 chip onboard. Kind of a funny combo AMD and VIA chips on the same board :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From stefan.reinauer at coresystems.de Fri May 14 20:50:49 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Fri, 14 May 2010 20:50:49 +0200 Subject: [coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi In-Reply-To: <20100514180905.28227.qmail@stuge.se> References: <20100514180905.28227.qmail@stuge.se> Message-ID: <4BED9B89.8060006@coresystems.de> On 5/14/10 8:09 PM, Peter Stuge wrote: > repository service wrote: > >> Fix i945 ACPI for ASL Optimizing Compiler version 20100428. >> > The whitespace changes in this commit made it difficult to see what > was actually changed. :\ > Check out the link that comes with the mails: https://tracker.coreboot.org/trac/coreboot/changeset/5550 It makes it really easy to understand the patch. From mylesgw at gmail.com Fri May 14 20:54:22 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 14 May 2010 12:54:22 -0600 Subject: [coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi In-Reply-To: <4BED9B89.8060006@coresystems.de> References: <20100514180905.28227.qmail@stuge.se> <4BED9B89.8060006@coresystems.de> Message-ID: > Check out the link that comes with the mails: > > https://tracker.coreboot.org/trac/coreboot/changeset/5550 I do like seeing it side by side. Would it be an easy fix to change the emailed links to http instead of https? Manually editing the link to http already works. Thanks, Myles From peter at stuge.se Fri May 14 20:57:22 2010 From: peter at stuge.se (Peter Stuge) Date: Fri, 14 May 2010 20:57:22 +0200 Subject: [coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi In-Reply-To: <4BED9B89.8060006@coresystems.de> References: <20100514180905.28227.qmail@stuge.se> <4BED9B89.8060006@coresystems.de> Message-ID: <20100514185722.3227.qmail@stuge.se> Stefan Reinauer wrote: > > The whitespace changes in this commit made it difficult to see what > > was actually changed. :\ > > Check out the link that comes with the mails: > > https://tracker.coreboot.org/trac/coreboot/changeset/5550 > > It makes it really easy to understand the patch. I agree - very nice! Unfortunately it's also more complicated than simply reading the patch in the email, so I don't think it will be very common. :\ //Peter From vidwer at gmail.com Fri May 14 21:07:38 2010 From: vidwer at gmail.com (Idwer Vollering) Date: Fri, 14 May 2010 21:07:38 +0200 Subject: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this In-Reply-To: References: Message-ID: 2010/5/14 Keith Hui > Limit your DCACHE_RAM_SIZE to 0x1000 (4k). The L2 init is done > post-raminit so it's not available for CAR. Your CPU only has 16k of > L1 cache available for CAR. > Bootlog+dmesg :) coreboot-4.0-r5543M Fri May 14 20:31:05 CEST 2010 starting... SMBus controller enabled dimm: 00.0: 50 00: 80 08 04 0c 0a 01 40 00 01 80 60 00 80 08 00 01 10: 8f 04 06 01 01 00 0e a0 60 00 00 14 14 14 32 20 20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 f6 40: 7f da 00 00 00 00 00 00 53 44 50 31 30 30 2d 30 50: 36 34 31 36 32 45 00 00 00 00 00 00 00 01 45 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 af 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff dimm: 01.0: 51 00: 80 08 04 0c 09 01 40 00 01 80 60 00 80 08 00 01 10: 8f 04 06 01 01 00 0e 0c 60 00 00 14 10 14 30 10 20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 ff 40: da 43 4d 45 4d 4f 52 59 53 50 44 50 31 30 30 2d 50: 30 36 34 30 38 33 41 55 00 00 00 00 00 98 50 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ad 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff dimm: 02.0: 52 00: 80 08 04 0c 09 01 40 00 01 75 54 00 80 08 00 01 10: 8f 04 06 01 01 00 0f a0 60 00 00 14 0f 14 2d 10 20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 8f 40: 7f 94 ff ff ff ff ff ff 04 47 4d 4d 32 36 34 39 50: 32 33 33 45 54 47 2d 37 35 20 20 00 ff 22 64 88 60: f2 d0 2d 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ad 80: 43 50 51 31 15 38 30 34 38 46 52 34 5a 30 42 50 90: 37 20 01 14 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dimm: 03.0: 53 00: bad device Northbridge prior to SDRAM init: Found DIMM in slot 00 Found DIMM in slot 01 Found DIMM in slot 02 PGPOL[BPR] has been set to 0x15 RPS has been set to 0x0112 NBXECC[31:24] has been set to 0xff DRAMC has been set to 0x08 RAM Enable 1: Apply NOP RAM Enable 2: Precharge all RAM Enable 3: CBR RAM Enable 4: Mode register set RAM Enable 5: Normal operation RAM Enable 6: Enable refresh Enabling refresh (DRAMC = 0x09) for DIMM 00 Enabling refresh (DRAMC = 0x09) for DIMM 01 Enabling refresh (DRAMC = 0x09) for DIMM 02 Northbridge following SDRAM init: Testing DRAM : 00000000 - 000a0000 DRAM fill: 0x00000000-0x000a0000 000a0000 DRAM filled DRAM verify: 0x00000000-0x000a0000 000a0000 DRAM range verified. Done. Loading stage image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (212992 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-r5543M Fri May 14 20:31:05 CEST 2010 booting... POST: 0x40 Calibrating delay loop... end 922a0e65, start 5f8a0bcf 32-bit delta 810 calibrate_tsc 32-bit result is 810 clocks_per_usec: 810 Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PNP: 03f0.0: enabled 1, 3 resources PNP: 03f0.1: enabled 1, 2 resources PNP: 03f0.2: enabled 1, 2 resources PNP: 03f0.3: enabled 1, 2 resources PNP: 03f0.5: enabled 1, 4 resources PNP: 03f0.7: enabled 1, 0 resources PNP: 03f0.8: enabled 1, 0 resources PNP: 03f0.9: enabled 1, 0 resources PNP: 03f0.a: enabled 1, 0 resources PCI: 00:04.1: enabled 1, 0 resources PCI: 00:04.2: enabled 1, 0 resources PCI: 00:04.3: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PNP: 03f0.0: enabled 1, 3 resources PNP: 03f0.1: enabled 1, 2 resources PNP: 03f0.2: enabled 1, 2 resources PNP: 03f0.3: enabled 1, 2 resources PNP: 03f0.5: enabled 1, 4 resources PNP: 03f0.7: enabled 1, 0 resources PNP: 03f0.8: enabled 1, 0 resources PNP: 03f0.9: enabled 1, 0 resources PNP: 03f0.a: enabled 1, 0 resources PCI: 00:04.1: enabled 1, 0 resources PCI: 00:04.2: enabled 1, 0 resources PCI: 00:04.3: enabled 1, 0 resources scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 POST: 0x5f PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:00.0 [8086/7190] ops PCI: 00:00.0 [8086/7190] enabled PCI: 00:01.0 [8086/7191] enabled PCI: 00:04.0 [8086/7110] bus ops PCI: 00:04.0 [8086/7110] enabled PCI: 00:04.1 [8086/7111] ops PCI: 00:04.1 [8086/7111] enabled PCI: 00:04.2 [8086/7112] ops PCI: 00:04.2 [8086/7112] enabled PCI: 00:04.3 [8086/7113] bus ops PCI: 00:04.3 [8086/7113] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:04.0 malloc Enter, size 1092, free_mem_ptr 00130000 malloc 00130000 PNP: 03f0.0 enabled PNP: 03f0.1 enabled PNP: 03f0.2 enabled PNP: 03f0.3 enabled PNP: 03f0.5 enabled PNP: 03f0.7 enabled PNP: 03f0.8 enabled PNP: 03f0.9 enabled PNP: 03f0.a enabled PNP: 03f0.6 enabled scan_static_bus for PCI: 00:04.0 done scan_static_bus for PCI: 00:04.3 scan_static_bus for PCI: 00:04.3 done PCI: pci_scan_bus returning with max=001 POST: 0x55 scan_static_bus for Root Device done done POST: 0x66 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:04.0 read_resources bus 0 link: 0 PNP: 03f0.8 missing read_resources PNP: 03f0.9 missing read_resources PCI: 00:04.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device links 1 child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00 APIC: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:01.0 links 1 child on link 0 NULL PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:04.0 links 1 child on link 0 PNP: 03f0.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0000200 index 2 PCI: 00:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 03f0.0 links 0 child on link 0 NULL PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 03f0.1 links 0 child on link 0 NULL PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 links 0 child on link 0 NULL PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.3 links 0 child on link 0 NULL PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.5 links 0 child on link 0 NULL PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 03f0.7 links 0 child on link 0 NULL PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.8 links 0 child on link 0 NULL PNP: 03f0.9 links 0 child on link 0 NULL PNP: 03f0.a links 0 child on link 0 NULL PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.6 links 0 child on link 0 NULL PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 links 0 child on link 0 NULL PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:04.2 links 0 child on link 0 NULL PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:04.3 links 0 child on link 0 NULL PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:04.2 20 * [0x0 - 0x1f] io PCI: 00:04.1 20 * [0x20 - 0x2f] io PCI_DOMAIN: 0000 compute_resources_io: base: 30 size: 30 align: 5 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI_DOMAIN: 0000 compute_resources_mem: base: 10000000 size: 10000000 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:04.0 constrain_resources: PNP: 03f0.0 constrain_resources: PNP: 03f0.1 constrain_resources: PNP: 03f0.2 constrain_resources: PNP: 03f0.3 constrain_resources: PNP: 03f0.5 constrain_resources: PNP: 03f0.7 constrain_resources: PNP: 03f0.8 constrain_resources: PNP: 03f0.9 constrain_resources: PNP: 03f0.a constrain_resources: PNP: 03f0.6 constrain_resources: PCI: 00:04.1 constrain_resources: PCI: 00:04.2 constrain_resources: PCI: 00:04.3 avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:30 align:5 gran:0 limit:ffff Assigned: PCI: 00:04.2 20 * [0x1000 - 0x101f] io Assigned: PCI: 00:04.1 20 * [0x1020 - 0x102f] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1030 size: 30 align: 5 gran: 0 done PCI: 00:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10000000 align:28 gran:0 limit:febfffff Assigned: PCI: 00:00.0 10 * [0xe0000000 - 0xefffffff] prefmem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0000000 size: 10000000 align: 28 gran: 0 done PCI: 00:01.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:01.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:01.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 Setting RAM size to 256 MB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:04.0 assign_resources, bus 0 link: 0 PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.1 74 drq size: 0x0000000001 not assigned PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.7 60 io size: 0x0000000001 not assigned ERROR: PNP: 03f0.7 62 io size: 0x0000000002 not assigned ERROR: PNP: 03f0.7 70 irq size: 0x0000000001 not assigned ERROR: PNP: 03f0.a 70 irq size: 0x0000000001 not assigned ERROR: PNP: 03f0.6 60 io size: 0x0000000008 not assigned ERROR: PNP: 03f0.6 70 irq size: 0x0000000001 not assigned PCI: 00:04.0 assign_resources, bus 0 link: 0 PCI: 00:04.1 20 <- [0x0000001020 - 0x000000102f] size 0x00000010 gran 0x04 io PCI: 00:04.2 20 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device links 1 child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00 APIC: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 30 align 5 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 28 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size ff40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10 PCI: 00:01.0 links 1 child on link 0 NULL PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:01.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:04.0 links 1 child on link 0 PNP: 03f0.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0000200 index 2 PCI: 00:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 03f0.0 links 0 child on link 0 NULL PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 03f0.1 links 0 child on link 0 NULL PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 links 0 child on link 0 NULL PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.3 links 0 child on link 0 NULL PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.5 links 0 child on link 0 NULL PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 03f0.7 links 0 child on link 0 NULL PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.8 links 0 child on link 0 NULL PNP: 03f0.9 links 0 child on link 0 NULL PNP: 03f0.a links 0 child on link 0 NULL PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.6 links 0 child on link 0 NULL PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 links 0 child on link 0 NULL PCI: 00:04.1 resource base 1020 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:04.2 links 0 child on link 0 NULL PCI: 00:04.2 resource base 1000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:04.3 links 0 child on link 0 NULL Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 0083 PCI: 00:01.0 cmd <- 00 PCI: 00:04.0 cmd <- 07 PCI: 00:04.1 cmd <- 01 PCI: 00:04.2 cmd <- 01 PCI: 00:04.3 cmd <- 01 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00009000, offset=0x00100000, code_size=0x0000005b Initializing CPU #0 CPU: vendor Intel device 673 CPU: family 06, model 07, stepping 03 microcode_info: sig = 0x00000673 pf=0x00000001 rev = 0x00000000 microcode updated to revision: 0000000e from revision 00000000 Configuring L2 cache... rdmsr(IA32_PLATFORM_ID) = 0, 11010000 L2 Cache latency is 8 Sending 0 to set_l2_register4 L2 ECC Checking is enabled L2 Physical Address Range is 4096M Maximum cache mask is 20000 L2 Cache Mask is 4000 read_l2(2) = 8 write_l2(2) = 8 L2 Cache size is 512K L2 Cache lines initialized done. POST: 0x60 Enabling cache CPU: . Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU #0 initialized All AP CPUs stopped PCI: 00:00.0 init Northbridge Init PCI: 00:04.0 init RTC Init PNP: 03f0.0 init PNP: 03f0.1 init PNP: 03f0.2 init PNP: 03f0.3 init PNP: 03f0.5 init Keyboard init... No PS/2 keyboard detected. PNP: 03f0.7 init PNP: 03f0.a init PCI: 00:04.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: on IDE: Primary IDE interface, drive 0: UDMA/33: off IDE: Primary IDE interface, drive 1: UDMA/33: off IDE: Secondary IDE interface, drive 0: UDMA/33: off IDE: Secondary IDE interface, drive 1: UDMA/33: off PCI: 00:04.2 init PNP: 03f0.6 init Devices initialized Show all devs...After init. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 4 resources PCI: 00:00.0: enabled 1, 1 resources PCI: 00:01.0: enabled 1, 3 resources PCI: 00:04.0: enabled 1, 3 resources PNP: 03f0.0: enabled 1, 3 resources PNP: 03f0.1: enabled 1, 3 resources PNP: 03f0.2: enabled 1, 2 resources PNP: 03f0.3: enabled 1, 2 resources PNP: 03f0.5: enabled 1, 4 resources PNP: 03f0.7: enabled 1, 3 resources PNP: 03f0.8: enabled 1, 0 resources PNP: 03f0.9: enabled 1, 0 resources PNP: 03f0.a: enabled 1, 1 resources PCI: 00:04.1: enabled 1, 1 resources PCI: 00:04.2: enabled 1, 1 resources PCI: 00:04.3: enabled 1, 0 resources PNP: 03f0.6: enabled 1, 2 resources POST: 0x89 Initializing CBMEM area to 0xfff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 0fff0200...ok High Tables Base is fff0000. POST: 0x9a Copying