[coreboot] Porting to RS780/SB700 board

[Marc Jones]

On Fri, Apr 30, 2010 at 9:49 PM, Myles Watson <mylesgw at gmail.com> wrote:
>

>> /* variable MTRRs */
>> msr 00000200=0000000000000000
>> msr 00000201=0000000000000000
>> msr 00000202=00000000fff00006
>> msr 00000203=0000fffffff80800
> This looks wrong to me.  I'm not an expert, but Since 202 is the base, and
> 203 is the mask, It looks like the area from 0xfff00000 - 0xfff7ffff is
> cached.  I would think the correct setting would be:
>> msr 00000202=00000000fff00006
>> msr 00000203=0000fffffff00800
>

I agree, this is only 512KB not 1MB as I would expect.
Check $REAL_XIP_ROM_BASE and CONFIG_XIP_ROM_SIZE which get used in
cpu/amd/car/cache_as_ram.inc.

Marc

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