From scott at notabs.org  Mon Nov  1 00:17:00 2010
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 31 Oct 2010 18:17:00 -0500
Subject: [coreboot] [PATCH 0/7] ASUS M2V support (v2)
In-Reply-To: <20101031221046.GU31684@yumi.tdiedrich.de>
References: <20101029115628.GH31684@yumi.tdiedrich.de><3B1E6CBE68214C2C8C7DD7FE4BAD4FAC@m3a78><20101031212946.GT31684@yumi.tdiedrich.de>
	<20101031221046.GU31684@yumi.tdiedrich.de>
Message-ID: <26B5616D96014B26A8EF646E9526B388@m3a78>

]Tobias Diedrich wrote:
]> Scott Duplichan wrote:
]> > The stop A5 can be easy to debug if you go through the pain of
]> > setting up a checked build with windbg. For me the first thing
]> > it reported was e820 ranges overlapping with other (ACPI) ranges.
]> > I found Windows wants no range reserved in e820 unless it is
]> > truly off limits to the OS ands its drivers. The exception is
]> > mmconf, which is often reserved in e820. An annoyance with checked
]> > build (at least win7) is the e820 range error message prints
]> > garbage. The reason is that the DbgPrint format string and arg list
]> > do not match. One is 32-bit and the other 64-bit. It will work if
]> > patched in memory before executing. Another problem is that Windows
]> > wants ACPI to report the address space available to the PCI bus.
]> > Here is how mine looks. It is hard-coded for 2MB TOM at the moment:
]> 
]> Finally have a win install on my notebook set up. I didn't have any
]> disk space left on the hard disk and had to patch the xp install cd
]> so I could install it on an external USB hard drive...
]> Hmm, according to windbg the error is 'failed to load DDB', and the
]> third arg points to the generated SSDT for my Processor. I'll have a
]> look...
]
]Disabling the SSDT for now there was indeed an E820 conflict with the
]DSDT PCI0 _CRS resources. Looks like the dsdt I copied it from was a
]bad example. :)
]I got my first successful ACPI boot of XP now.

That is great news, congratulations. 
Thanks,
Scott

]-- 
]Tobias						PGP: http://8ef7ddba.uguu.de




From svn at coreboot.org  Mon Nov  1 00:24:19 2010
From: svn at coreboot.org (repository service)
Date: Mon, 01 Nov 2010 00:24:19 +0100
Subject: [coreboot] [commit] r6007 - in trunk/src/mainboard:
	amd/mahogany_fam10 amd/tilapia_fam10 asus/m4a785-m
	gigabyte/ma785gmt gigabyte/ma78gm iei/kino-780am2-fam10
	jetway/pa78vm5
Message-ID: <E1PChG7-0008Qu-35@ra.coresystems.de>

Author: uwe
Date: Mon Nov  1 00:24:18 2010
New Revision: 6007
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6007

Log:
Remove definitions of ACPI_SSDTX_NUM to 0, that's the default anyway.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/mainboard/amd/mahogany_fam10/Kconfig
   trunk/src/mainboard/amd/tilapia_fam10/Kconfig
   trunk/src/mainboard/asus/m4a785-m/Kconfig
   trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
   trunk/src/mainboard/gigabyte/ma78gm/Kconfig
   trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig
   trunk/src/mainboard/jetway/pa78vm5/Kconfig

Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Sun Oct 31 20:37:50 2010	(r6006)
+++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Mon Nov  1 00:24:18 2010	(r6007)
@@ -81,10 +81,6 @@
 	hex
 	default 0xc0000
 
-config ACPI_SSDTX_NUM
-	int
-	default 0
-
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
 	default 0x3060

Modified: trunk/src/mainboard/amd/tilapia_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/Kconfig	Sun Oct 31 20:37:50 2010	(r6006)
+++ trunk/src/mainboard/amd/tilapia_fam10/Kconfig	Mon Nov  1 00:24:18 2010	(r6007)
@@ -81,10 +81,6 @@
 	hex
 	default 0xc0000
 
-config ACPI_SSDTX_NUM
-	int
-	default 0
-
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
 	default 0x3060

Modified: trunk/src/mainboard/asus/m4a785-m/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/Kconfig	Sun Oct 31 20:37:50 2010	(r6006)
+++ trunk/src/mainboard/asus/m4a785-m/Kconfig	Mon Nov  1 00:24:18 2010	(r6007)
@@ -80,10 +80,6 @@
 	hex
 	default 0xc0000
 
-config ACPI_SSDTX_NUM
-	int
-	default 0
-
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
 	default 0x83a2

Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Sun Oct 31 20:37:50 2010	(r6006)
+++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Mon Nov  1 00:24:18 2010	(r6007)
@@ -81,10 +81,6 @@
 	hex
 	default 0xc0000
 
-config ACPI_SSDTX_NUM
-	int
-	default 0
-
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
 	default 0x3060

Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Sun Oct 31 20:37:50 2010	(r6006)
+++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Mon Nov  1 00:24:18 2010	(r6007)
@@ -81,10 +81,6 @@
 	hex
 	default 0xc0000
 
-config ACPI_SSDTX_NUM
-	int
-	default 0
-
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
 	default 0x3060

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig	Sun Oct 31 20:37:50 2010	(r6006)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig	Mon Nov  1 00:24:18 2010	(r6007)
@@ -81,10 +81,6 @@
 	hex
 	default 0xc0000
 
-config ACPI_SSDTX_NUM
-	int
-	default 0
-
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
 	default 0x0000

Modified: trunk/src/mainboard/jetway/pa78vm5/Kconfig
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/Kconfig	Sun Oct 31 20:37:50 2010	(r6006)
+++ trunk/src/mainboard/jetway/pa78vm5/Kconfig	Mon Nov  1 00:24:18 2010	(r6007)
@@ -81,10 +81,6 @@
 	hex
 	default 0xc0000
 
-config ACPI_SSDTX_NUM
-	int
-	default 0
-
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
 	default 0x3060



From svn at coreboot.org  Mon Nov  1 15:18:12 2010
From: svn at coreboot.org (repository service)
Date: Mon, 01 Nov 2010 15:18:12 +0100
Subject: [coreboot] [commit] r6008 - trunk/src/northbridge/amd/gx2
Message-ID: <E1PCvDA-0007R7-DQ@ra.coresystems.de>

Author: uwe
Date: Mon Nov  1 15:18:11 2010
New Revision: 6008
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6008

Log:
GX2: Change MSR register numbers into more descriptive names.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/northbridge/amd/gx2/raminit.c

Modified: trunk/src/northbridge/amd/gx2/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/raminit.c	Mon Nov  1 00:24:18 2010	(r6007)
+++ trunk/src/northbridge/amd/gx2/raminit.c	Mon Nov  1 15:18:11 2010	(r6008)
@@ -12,31 +12,31 @@
 	msr_t msr;
 
 	/* 2. clock gating for PMode */
-	msr = rdmsr(0x20002004);
+	msr = rdmsr(MC_GLD_MSR_PM);
 	msr.lo &= ~0x04;
 	msr.lo |=  0x01;
-	wrmsr(0x20002004, msr);
+	wrmsr(MC_GLD_MSR_PM, msr);
 	/* undocmented bits in GX, in LX there are
 	 * 8 bits in PM1_UP_DLY */
-	msr = rdmsr(0x2000001a);
+	msr = rdmsr(MC_CF1017_DATA);
 	msr.lo = 0x0101;
-	wrmsr(0x2000001a, msr);
+	wrmsr(MC_CF1017_DATA, msr);
 	//print_debug("sdram_enable step 2\n");
 
 	/* 3. release CKE mask to enable CKE */
-	msr = rdmsr(0x2000001d);
+	msr = rdmsr(MC_CFCLK_DBUG);
 	msr.lo &= ~(0x03 << 8);
-	wrmsr(0x2000201d, msr);
+	wrmsr(MC_CFCLK_DBUG, msr);
 	//print_debug("sdram_enable step 3\n");
 
 	/* 4. set and clear REF_TST 16 times, more shouldn't hurt
 	 * why this is before EMRS and MRS ? */
 	for (i = 0; i < 19; i++) {
-		msr = rdmsr(0x20000018);
+		msr = rdmsr(MC_CF07_DATA);
 		msr.lo |=  (0x01 << 3);
-		wrmsr(0x20000018, msr);
+		wrmsr(MC_CF07_DATA, msr);
 		msr.lo &= ~(0x01 << 3);
-		wrmsr(0x20000018, msr);
+		wrmsr(MC_CF07_DATA, msr);
 	}
 	//print_debug("sdram_enable step 4\n");
 
@@ -53,29 +53,29 @@
 	//print_debug("sdram_enable step 5\n");
 
 	/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
-	msr = rdmsr(0x20000018);
+	msr = rdmsr(MC_CF07_DATA);
 	msr.lo |=  ((0x01 << 28) | 0x01);
-	wrmsr(0x20000018, msr);
+	wrmsr(MC_CF07_DATA, msr);
 	msr.lo &= ~((0x01 << 28) | 0x01);
-	wrmsr(0x20000018, msr);
+	wrmsr(MC_CF07_DATA, msr);
 	//print_debug("sdram_enable step 6\n");
 
 	/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
 	 * it is documented in LX datasheet  */
 	/* load Mode Register by set and clear PROG_DRAM */
-	msr = rdmsr(0x20000018);
+	msr = rdmsr(MC_CF07_DATA);
 	msr.lo |=  ((0x01 << 27) | 0x01);
-	wrmsr(0x20000018, msr);
+	wrmsr(MC_CF07_DATA, msr);
 	msr.lo &= ~((0x01 << 27) | 0x01);
-	wrmsr(0x20000018, msr);
+	wrmsr(MC_CF07_DATA, msr);
 	//print_debug("sdram_enable step 7\n");
 
 	/* 8. load Mode Register by set and clear PROG_DRAM */
-	msr = rdmsr(0x20000018);
+	msr = rdmsr(MC_CF07_DATA);
 	msr.lo |=  0x01;
-	wrmsr(0x20000018, msr);
+	wrmsr(MC_CF07_DATA, msr);
 	msr.lo &= ~0x01;
-	wrmsr(0x20000018, msr);
+	wrmsr(MC_CF07_DATA, msr);
 	//print_debug("sdram_enable step 8\n");
 
 	/* wait 200 SDCLKs */
@@ -83,7 +83,7 @@
 		outb(0xaa, 0x80);
 
 	/* load RDSYNC */
-	msr = rdmsr(0x2000001f);
+	msr = rdmsr(MC_CF_RDSYNC);
 	msr.hi = 0x000ff310;
 	/* the above setting is supposed to be good for "slow" ram. We have found that for
 	 * some dram, at some clock rates, e.g. hynix at 366/244, this will actually
@@ -94,13 +94,13 @@
 	 */
 	msr.hi = 0x00000310;
 	msr.lo = 0x00000000;
-	wrmsr(0x2000001f, msr);
+	wrmsr(MC_CF_RDSYNC, msr);
 
 	/* set delay control */
-	msr = rdmsr(0x4c00000f);
+	msr = rdmsr(GLCP_DELAY_CONTROLS);
 	msr.hi = 0x830d415a;
 	msr.lo = 0x8ea0ad6a;
-	wrmsr(0x4c00000f, msr);
+	wrmsr(GLCP_DELAY_CONTROLS, msr);
 
 	/* The RAM dll needs a write to lock on so generate a few dummy writes */
 	/* Note: The descriptor needs to be enabled to point at memory */



From svn at coreboot.org  Mon Nov  1 15:36:56 2010
From: svn at coreboot.org (repository service)
Date: Mon, 01 Nov 2010 15:36:56 +0100
Subject: [coreboot] [commit] r6009 - in trunk/src: include/cpu/amd
	northbridge/amd/gx2
Message-ID: <E1PCvVI-0007x5-O2@ra.coresystems.de>

Author: uwe
Date: Mon Nov  1 15:36:54 2010
New Revision: 6009
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6009

Log:
GX2: Clean up some white space and comments.

Also, add a copyright header to pll_reset.c.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/include/cpu/amd/gx2def.h
   trunk/src/northbridge/amd/gx2/pll_reset.c

Modified: trunk/src/include/cpu/amd/gx2def.h
==============================================================================
--- trunk/src/include/cpu/amd/gx2def.h	Mon Nov  1 15:18:11 2010	(r6008)
+++ trunk/src/include/cpu/amd/gx2def.h	Mon Nov  1 15:36:54 2010	(r6009)
@@ -1,5 +1,6 @@
 #ifndef CPU_AMD_GX2DEF_H
 #define CPU_AMD_GX2DEF_H
+
 #define	CPU_ID_1_X							0x540		/* Stepping ID 1.x*/
 #define	CPU_ID_2_0							0x551		/* Stepping ID 2.0*/
 #define	CPU_ID_2_1							0x552		/* Stepping ID 2.1*/
@@ -13,6 +14,7 @@
 #define	CPU_REV_2_1							0x021
 #define	CPU_REV_2_2							0x022
 #define	CPU_REV_3_0							0x030
+
 /* GeodeLink Control Processor Registers, GLIU1, Port 3 */
 #define	GLCP_CLK_DIS_DELAY	0x4c000008
 #define	GLCP_PMCLKDISABLE	0x4c000009
@@ -37,28 +39,27 @@
 #define	GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE  8
 #define	GLCP_SYS_RSTPLL_CHIP_RESET	    0
 
-/* MSR routing as follows*/
-/* MSB = 1 means not for CPU*/
-/* next 3 bits 1st port*/
-/* next3 bits next port if through an GLIU*/
-/* etc...*/
+/* MSR routing as follows */
+/* MSB = 1 means not for CPU */
+/* next 3 bits 1st port */
+/* next3 bits next port if through an GLIU */
+/* etc... */
 
-/*Redcloud as follows.*/
+/* Redcloud as follows. */
 /* GLIU0*/
-/*	port0 - GLIU0*/
-/*	port1 - MC*/
-/*	port2 - GLIU1*/
-/*	port3 - CPU*/
-/*	port4 - VG*/
-/*	port5 - GP*/
-/*	port6 - DF*/
+/*	port0 - GLIU0 */
+/*	port1 - MC */
+/*	port2 - GLIU1 */
+/*	port3 - CPU */
+/*	port4 - VG */
+/*	port5 - GP */
+/*	port6 - DF */
 
 /* GLIU1*/
-/*	port1 - GLIU0*/
-/*	port3 - GLCP*/
-/*	port4 - PCI*/
-/*	port5 - FG*/
-
+/*	port1 - GLIU0 */
+/*	port3 - GLCP */
+/*	port4 - PCI */
+/*	port5 - FG */
 
 #define	GL0_GLIU0			0
 #define	GL0_MC				1
@@ -78,7 +79,7 @@
 #define	MSR_GLIU0			(GL0_GLIU0 << 29) + (1 << 28)	/* 1000xxxx - To get on GeodeLink one bit has to be set */
 #define	MSR_MC				(GL0_MC		<< 29)	/* 2000xxxx */
 #define	MSR_GLIU1			(GL0_GLIU1	<< 29)	/* 4000xxxx */
-#define	MSR_CPU				(GL0_CPU	<< 29)	/* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed*/
+#define	MSR_CPU				(GL0_CPU	<< 29)	/* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */
 #define	MSR_VG				(GL0_VG		<< 29)	/* 8000xxxx */
 #define	MSR_GP				(GL0_GP		<< 29)	/* A000xxxx */
 #define	MSR_DF				(GL0_DF		<< 29)	/* C000xxxx */
@@ -88,14 +89,11 @@
 #define	MSR_FG				(GL1_FG << 26) + MSR_GLIU1	/* 5400xxxx */
 #define MSR_VIP				((GL1_VIP << 26) + MSR_GLIU1)	/* 5400xxxx */
 #define MSR_AES				((GL1_AES << 26) + MSR_GLIU1)	/* 5800xxxx */
-/* South Bridge*/
-#define SB_PORT	2			/* port of the SouthBridge */
-
 
-/**/
-/*GeodeLink Interface Unit 0 (GLIU0) port0*/
-/**/
+/* South Bridge */
+#define SB_PORT	2			/* port of the SouthBridge */
 
+/* GeodeLink Interface Unit 0 (GLIU0) port0 */
 #define	GLIU0_GLD_MSR_CAP			(MSR_GLIU0 + 0x2000)
 #define	GLIU0_GLD_MSR_PM			(MSR_GLIU0 + 0x2004)
 
@@ -103,10 +101,7 @@
 #define	GLIU0_CAP					(MSR_GLIU0 + 0x86)
 #define	GLIU0_GLD_MSR_COH			(MSR_GLIU0 + 0x80)
 
-
-/**/
-/* Memory Controller GLIU0 port 1*/
-/**/
+/* Memory Controller GLIU0 port 1 */
 #define	MC_GLD_MSR_CAP			(MSR_MC + 0x2000)
 #define	MC_GLD_MSR_PM			(MSR_MC + 0x2004)
 
@@ -129,7 +124,6 @@
 #define		CF07_LOWER_REF_TEST_SET				(1 << 3)
 #define		CF07_LOWER_PROG_DRAM_SET			(1 << 0)
 
-
 #define	MC_CF8F_DATA			(MSR_MC + 0x19)
 
 #define		CF8F_UPPER_XOR_BS_SHIFT				19
@@ -164,19 +158,13 @@
 
 #define	MC_CF_RDSYNC			(MSR_MC	+ 0x1F)
 
-
-/**/
-/* GLIU1 GLIU0 port2*/
-/**/
+/* GLIU1 GLIU0 port2 */
 #define	GLIU1_GLD_MSR_CAP			(MSR_GLIU1 + 0x2000)
 #define	GLIU1_GLD_MSR_PM			(MSR_GLIU1 + 0x2004)
 
 #define	GLIU1_GLD_MSR_COH			(MSR_GLIU1 + 0x80)
 
-
-/**/
-/* CPU	; does not need routing instructions since we are executing there.*/
-/**/
+/* CPU	; does not need routing instructions since we are executing there. */
 #define	CPU_GLD_MSR_CAP						0x2000
 #define	CPU_GLD_MSR_CONFIG					0x2001
 #define	CPU_GLD_MSR_PM						0x2004
@@ -200,7 +188,7 @@
 #define	CPU_AC_MSR							0x1301
 #define	CPU_EX_BIST							0x1428
 
-/*IM*/
+/* IM */
 #define	CPU_IM_CONFIG							0x1700
 #define		IM_CONFIG_LOWER_ICD_SET					(1 << 8)
 #define		IM_CONFIG_LOWER_QWT_SET					(1 << 20)
@@ -215,13 +203,13 @@
 #define	CPU_IM_BIST_TAG							0x1730
 #define	CPU_IM_BIST_DATA						0x1731
 
-
 /* various CPU MSRs */
 #define CPU_DM_CONFIG0 0x1800
 #define	DM_CONFIG0_UPPER_WSREQ_SHIFT  12
 #define	DM_CONFIG0_LOWER_DCDIS_SET		(1<<8)
 #define	DM_CONFIG0_LOWER_WBINVD_SET	(1<<5)
 #define	DM_CONFIG0_LOWER_MISSER_SET		(1<<1)
+
 /* configuration MSRs */
 #define	CPU_RCONF_DEFAULT						0x1808
 #define		RCONF_DEFAULT_UPPER_ROMRC_SHIFT				24
@@ -276,7 +264,7 @@
 #define	CPU_L2TB_ENTRY						0x189E
 #define	CPU_L2TB_ENTRY_I					0x189F
 #define	CPU_DM_BIST							0x18C0
-		/* SMM*/
+		/* SMM */
 #define	CPU_AC_SMM_CTL						0x1301
 #define		SMM_NMI_EN_SET					(1<<0)
 #define		SMM_SUSP_EN_SET					(1<<1)
@@ -294,10 +282,7 @@
 #define		TSC_SUSP_SET				 (1<<5)
 #define		SUSP_EN_SET				 (1<<12)
 
-	/**/
-	/*	VG GLIU0 port4*/
-	/**/
-
+/* VG GLIU0 port4 */
 #define	VG_GLD_MSR_CAP				(MSR_VG + 0x2000)
 #define	VG_GLD_MSR_CONFIG			(MSR_VG + 0x2001)
 #define	VG_GLD_MSR_PM				(MSR_VG + 0x2004)
@@ -306,29 +291,20 @@
 #define	GP_GLD_MSR_CONFIG			(MSR_GP + 0x2001)
 #define	GP_GLD_MSR_PM				(MSR_GP + 0x2004)
 
-
-
-/**/
-/*	DF GLIU0 port6*/
-/**/
-
+/* DF GLIU0 port6 */
 #define	DF_GLD_MSR_CAP					(MSR_DF + 0x2000)
 #define	DF_GLD_MSR_MASTER_CONF			(MSR_DF + 0x2001)
 #define		DF_LOWER_LCD_SHIFT				6
 #define	DF_GLD_MSR_PM					(MSR_DF + 0x2004)
 
-
-
-/**/
-/* GeodeLink Control Processor GLIU1 port3*/
-/**/
+/* GeodeLink Control Processor GLIU1 port3 */
 #define	GLCP_GLD_MSR_CAP			(MSR_GLCP + 0x2000)
 #define	GLCP_GLD_MSR_CONF			(MSR_GLCP + 0x2001)
 #define	GLCP_GLD_MSR_PM				(MSR_GLCP + 0x2004)
 
 #define	GLCP_DELAY_CONTROLS			(MSR_GLCP + 0x0F)
 
-#define	GLCP_SYS_RSTPLL				(MSR_GLCP +0x14	/* R/W*/)
+#define	GLCP_SYS_RSTPLL				(MSR_GLCP +0x14	/* R/W */)
 #define		RSTPLL_UPPER_MDIV_SHIFT				9
 #define		RSTPLL_UPPER_VDIV_SHIFT				6
 #define		RSTPLL_UPPER_FBDIV_SHIFT			0
@@ -352,13 +328,10 @@
 #define		RSTPPL_LOWER_PCI_SEMI_SYNC_SET		 (1<<8)
 #define		RSTPPL_LOWER_CHIP_RESET_SET		 (1<<0)
 
-#define	GLCP_DOTPLL				(MSR_GLCP + 0x15	/* R/W*/)
+#define	GLCP_DOTPLL				(MSR_GLCP + 0x15	/* R/W */)
 #define		DOTPPL_LOWER_PD_SET				 (1<<14)
 
-
-/**/
-/*  GLIU1 port 4*/
-/**/
+/* GLIU1 port 4 */
 #define	GLPCI_GLD_MSR_CAP			(MSR_PCI + 0x2000)
 #define	GLPCI_GLD_MSR_CONFIG			(MSR_PCI + 0x2001)
 #define	GLPCI_GLD_MSR_PM				(MSR_PCI + 0x2004)
@@ -423,64 +396,60 @@
 #define		GLPCI_SPARE_LOWER_NSE_SET					(1<<1)
 #define		GLPCI_SPARE_LOWER_SUPO_SET					(1<<0)
 
-
-/**/
-/* FooGlue GLIU1 port 5*/
-/**/
+/* FooGlue GLIU1 port 5 */
 #define	FG_GLD_MSR_CAP			(MSR_FG + 0x2000)
 #define	FG_GLD_MSR_PM			(MSR_FG + 0x2004)
 
-/*  VIP GLIU1 port 5*/
-/* */
+/* VIP GLIU1 port 5 */
 #define VIP_GLD_MSR_CAP		(MSR_VIP + 0x2000)
 #define VIP_GLD_MSR_CONFIG	(MSR_VIP + 0x2001)
 #define VIP_GLD_MSR_PM		(MSR_VIP + 0x2004)
 #define VIP_BIST		(MSR_VIP + 0x2005)
 #define VIP_GIO_MSR_SEL		(MSR_VIP + 0x2010)
-/* */
-/*  AES GLIU1 port 6*/
-/* */
+
+/* AES GLIU1 port 6 */
 #define AES_GLD_MSR_CAP		(MSR_AES + 0x2000)
 #define AES_GLD_MSR_CONFIG	(MSR_AES + 0x2001)
 #define AES_GLD_MSR_PM		(MSR_AES + 0x2004)
 #define AES_CONTROL		(MSR_AES + 0x2006)
+
 /* more fun stuff */
-#define BM			1	/*  Base Mask - map power of 2 size aligned region*/
-#define BMO			2	/*  BM with an offset*/
-#define R				3	/*  Range - 4k range minimum*/
-#define RO			4	/*  R with offset*/
-#define SC			5	/*  Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/
-#define BMIO			6	/*  Base Mask IO*/
-#define SCIO			7	/*  Swiss 0xCeese IO*/
-#define SC_SHADOW	8	/*  Special marker for Shadow SC descriptors so setShadow proc is independant of CPU*/
-#define R_SYSMEM		9	/*  Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU*/
-#define BMO_SMM		10	/*  Specail marker for SMM*/
-#define BM_SMM		11	/*  Specail marker for SMM*/
-#define BMO_DMM		12	/*  Specail marker for DMM*/
-#define BM_DMM		13	/*  Specail marker for DMM*/
-#define RO_FB			14	/*  special for Frame buffer.*/
-#define R_FB			15	/*  special for FB.*/
-#define OTHER			0x0FE /*  Special marker for other*/
-#define GL_END		 0x0FF	/*  end*/
+#define BM			1	/* Base Mask - map power of 2 size aligned region */
+#define BMO			2	/* BM with an offset */
+#define R				3	/* Range - 4k range minimum */
+#define RO			4	/* R with offset */
+#define SC			5	/* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
+#define BMIO			6	/* Base Mask IO */
+#define SCIO			7	/* Swiss 0xCeese IO */
+#define SC_SHADOW	8	/* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */
+#define R_SYSMEM		9	/* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */
+#define BMO_SMM		10	/* Specail marker for SMM */
+#define BM_SMM		11	/* Specail marker for SMM */
+#define BMO_DMM		12	/* Specail marker for DMM */
+#define BM_DMM		13	/* Specail marker for DMM */
+#define RO_FB			14	/* special for Frame buffer. */
+#define R_FB			15	/* special for FB. */
+#define OTHER			0x0FE /* Special marker for other */
+#define GL_END		 0x0FF	/* end */
 
 #define MSR_GL0	(GL1_GLIU0 << 29)
 
-/*  Set up desc addresses from 20 - 3f*/
-/*  This is chip specific!*/
-#define MSR_GLIU0_BASE1			(MSR_GLIU0 + 0x20)		/*  BM*/
-#define MSR_GLIU0_BASE2			(MSR_GLIU0 + 0x21)		/*  BM*/
-#define MSR_GLIU0_SHADOW			(MSR_GLIU0 + 0x2C)		/*  SCO should only be SC*/
-#define MSR_GLIU0_SYSMEM			(MSR_GLIU0 + 0x28)		/*  RO should only be R*/
-#define MSR_GLIU0_SMM			(MSR_GLIU0 + 0x26)		/*  BMO*/
-#define MSR_GLIU0_DMM			(MSR_GLIU0 + 0x27)		/*  BMO*/
-
-#define MSR_GLIU1_BASE1			(MSR_GLIU1 + 0x20)		/*  BM*/
-#define MSR_GLIU1_BASE2			(MSR_GLIU1 + 0x21)		/*  BM*/
-#define MSR_GLIU1_SHADOW			(MSR_GLIU1 + 0x2D)		/*  SCO should only be SC*/
-#define MSR_GLIU1_SYSMEM			(MSR_GLIU1 + 0x29)		/*  RO should only be R*/
-#define MSR_GLIU1_SMM			(MSR_GLIU1 + 0x23)		/*  BM*/
-#define MSR_GLIU1_DMM			(MSR_GLIU1 + 0x24)		/*  BM*/
-#define MSR_GLIU1_FPU_TRAP		(MSR_GLIU1 + 0x0E3)	/*  FooGlue F0 for FPU*/
+/* Set up desc addresses from 20 - 3f */
+/* This is chip specific! */
+#define MSR_GLIU0_BASE1			(MSR_GLIU0 + 0x20)		/* BM */
+#define MSR_GLIU0_BASE2			(MSR_GLIU0 + 0x21)		/* BM */
+#define MSR_GLIU0_SHADOW			(MSR_GLIU0 + 0x2C)		/* SCO should only be SC */
+#define MSR_GLIU0_SYSMEM			(MSR_GLIU0 + 0x28)		/* RO should only be R */
+#define MSR_GLIU0_SMM			(MSR_GLIU0 + 0x26)		/* BMO */
+#define MSR_GLIU0_DMM			(MSR_GLIU0 + 0x27)		/* BMO */
+
+#define MSR_GLIU1_BASE1			(MSR_GLIU1 + 0x20)		/* BM */
+#define MSR_GLIU1_BASE2			(MSR_GLIU1 + 0x21)		/* BM */
+#define MSR_GLIU1_SHADOW			(MSR_GLIU1 + 0x2D)		/* SCO should only be SC */
+#define MSR_GLIU1_SYSMEM			(MSR_GLIU1 + 0x29)		/* RO should only be R */
+#define MSR_GLIU1_SMM			(MSR_GLIU1 + 0x23)		/* BM */
+#define MSR_GLIU1_DMM			(MSR_GLIU1 + 0x24)		/* BM */
+#define MSR_GLIU1_FPU_TRAP		(MSR_GLIU1 + 0x0E3)	/* FooGlue F0 for FPU */
 
 /* definitions that are "once you are mostly up, start VSA" type things */
 #define SMM_OFFSET	0x40400000
@@ -503,9 +472,7 @@
 #define CHIPSET_DEV_NUM	15
 #define IDSEL_BASE	11			 // bit 11 = device 1
 
-/* */
-/* SB LBAR IO + MEMORY MAP*/
-/* */
+/* SB LBAR IO + MEMORY MAP */
 #define SMBUS_BASE		 (		0x6000)
 #define GPIO_BASE		 (		0x6100)
 #define MFGPT_BASE		 (		0x6200)

Modified: trunk/src/northbridge/amd/gx2/pll_reset.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/pll_reset.c	Mon Nov  1 15:18:11 2010	(r6008)
+++ trunk/src/northbridge/amd/gx2/pll_reset.c	Mon Nov  1 15:36:54 2010	(r6009)
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #include <cpu/x86/tsc.h>
 
 #define CLOCK_TICK_RATE	1193180U /* Underlying HZ */
@@ -69,7 +89,7 @@
 
 /* spll_raw_clk = SYSREF * FbDIV,
  * GLIU Clock   = spll_raw_clk / MDIV
- * CPU Clock    = sppl_raw_clk / VDIV
+ * CPU Clock    = spll_raw_clk / VDIV
  */
 
 /* table for Feedback divisor to FbDiv register value */
@@ -99,6 +119,15 @@
              26,    2,    3             // 433/289
 };
 
+/*	FbDIV	VDIV	MDIV	CPU/GeodeLink */
+/*	12	2	3	200/133 */
+/*	16	2	3	266/177 */
+/*	18	2	3	300/200 */
+/*	20	2	3	333/222 */
+/*	22	2	3	366/244 */
+/*	24	2	3	400/266 */
+/*	26	2	3	433/289 */
+
 #if 0
 static unsigned int get_memory_speed(void)
 {
@@ -118,12 +147,12 @@
 ///////////////////////////////////////////////////////////////////////////////
 // Goodrich Version of pll_reset
 
-// PLLCHECK_COMPLETED is the "we've already done this" flag
+/* PLLCHECK_COMPLETED is the "we've already done this" flag */
 #define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
 
 #ifndef RSTPPL_LOWER_BYPASS_SET
 #define RSTPPL_LOWER_BYPASS_SET (1 << GLCP_SYS_RSTPLL_BYPASS)
-#endif // RSTPPL_LOWER_BYPASS_SET
+#endif /* RSTPPL_LOWER_BYPASS_SET */
 
 #define DEFAULT_MDIV	3
 #define DEFAULT_VDIV	2
@@ -133,84 +162,84 @@
 {
 	msr_t msrGlcpSysRstpll;
 	unsigned MDIV_VDIV_FBDIV;
-	unsigned SyncBits;			// store the sync bits in up ebx
+	unsigned SyncBits;			/* store the sync bits in up ebx */
 
-	// clear the Bypass bit
+	/* clear the Bypass bit */
 
-	// If the straps say we are in bypass and the syspll is not AND there are no software
-	// bits set then FS2 or something set up the PLL and we should not change it.
+	/* If the straps say we are in bypass and the syspll is not AND there are no software */
+	/* bits set then FS2 or something set up the PLL and we should not change it. */
 
 	msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
 	msrGlcpSysRstpll.lo &= ~RSTPPL_LOWER_BYPASS_SET;
 	wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
-	// If the "we've already been here" flag is set, don't reconfigure the pll
+	/* If the "we've already been here" flag is set, don't reconfigure the pll */
 	if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) )
-	{ // we haven't configured the PLL; do it now
+	{ /* we haven't configured the PLL; do it now */
 
-		// Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the
-		// correct Strap Table.
+		/* Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the */
+		/* correct Strap Table. */
 		post_code(POST_PLL_INIT);
 
-		// configure for DDR
+		/* configure for DDR */
 		msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
-		// Use Manual settings
-		//	UseManual:
+		/* Use Manual settings */
+		/*	UseManual: */
 		post_code(POST_PLL_MANUAL);
 
-		// DIV settings manually entered.
-		// ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
-		// use gs and fs since we don't need them.
-
-		//	ProgramClocks:
-		// ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
-		// move everything into ebx
-		// VDIV
+		/* DIV settings manually entered. */
+		/* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */
+		/* use gs and fs since we don't need them. */
+
+		/*	ProgramClocks: */
+		/* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */
+		/* move everything into ebx */
+		/* VDIV */
 		MDIV_VDIV_FBDIV = ((DEFAULT_VDIV - 2) << RSTPLL_UPPER_VDIV_SHIFT);
 
-		// MDIV
+		/* MDIV */
 		MDIV_VDIV_FBDIV |= ((DEFAULT_MDIV - 2) << RSTPLL_UPPER_MDIV_SHIFT);
 
-		// FbDIV
+		/* FbDIV */
 		MDIV_VDIV_FBDIV |= (plldiv2fbdiv[DEFAULT_FBDIV] << RSTPLL_UPPER_FBDIV_SHIFT);
 
-		// write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values
+		/* write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values */
 		msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
 		msrGlcpSysRstpll.hi = MDIV_VDIV_FBDIV;
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
-		// Set Reset, LockWait, and SW flag
-		//	DoReset:
+		/* Set Reset, LockWait, and SW flag */
+		/*	DoReset: */
 
-		// CheckSemiSync proc
-		// Check for Semi-Sync in GeodeLink and CPU.
-		// We need to do this here since the strap settings don't account for these bits.
+		/* CheckSemiSync proc */
+		/* Check for Semi-Sync in GeodeLink and CPU. */
+		/* We need to do this here since the strap settings don't account for these bits. */
 		SyncBits = 0;			// store the sync bits in up ebx
 
-		// Check for Bypass mode.
+		/* Check for Bypass mode. */
 		if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET)
 		{
-			// If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will.
+			/* If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. */
 			SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET;
 		}
 		else
 		{
-			//	CheckPCIsync:
-			// If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater
-			// look up the real divider... if we get a 0 we have serious problems
+			/*	CheckPCIsync: */
+			/* If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater */
+			/* look up the real divider... if we get a 0 we have serious problems */
 			if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %
 				(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) )
 			{
 				SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET;
 			}
 
-			//	CheckCPUSync:
-			// If Vdiv/Mdiv is evenly divisible then set the CPU semi-sync.
-			// CPU is always greater or equal.
+			/*	CheckCPUSync: */
+			/* If Vdiv/Mdiv is evenly divisible then set the CPU semi-sync. */
+			/* CPU is always greater or equal. */
 			if (!((((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x07) + 2) %
 				(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_VDIV_SHIFT) & 0x0F) + 2)))
 			{
@@ -219,29 +248,29 @@
 		}
 
 
-		//	SetSync:
+		/*	SetSync: */
 		msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_PCI_SEMI_SYNC_SET | RSTPPL_LOWER_CPU_SEMI_SYNC_SET);
 		msrGlcpSysRstpll.lo |= SyncBits;
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
-		// CheckSemiSync endp
+		/* CheckSemiSync endp */
 
-		// now we do the reset
-		// Set hold count to 99 (063h)
+		/* now we do the reset */
+		/* Set hold count to 99 (063h) */
 		msrGlcpSysRstpll.lo &= ~(0x0FF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
 		msrGlcpSysRstpll.lo |=  (0x0DE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
 		msrGlcpSysRstpll.lo |=  PLLCHECK_COMPLETED;		// Say we are done
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
-		// Don't want to use LOCKWAIT
+		/* Don't want to use LOCKWAIT */
 		msrGlcpSysRstpll.lo |= (RSTPPL_LOWER_PLL_RESET_SET + RSTPPL_LOWER_PD_SET);
 		msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
-		// You should never get here..... The chip has reset.
+		/* You should never get here..... The chip has reset. */
 		post_code(POST_PLL_RESET_FAIL);
 		while (1);
 
-	} // we haven't configured the PLL; do it now
+	} /* we haven't configured the PLL; do it now */
 
 }
 // End of Goodrich version of pll_reset



From uwe at hermann-uwe.de  Mon Nov  1 15:37:34 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 1 Nov 2010 15:37:34 +0100
Subject: [coreboot] [PATCH 2/4] Geode GX2 auto DRAM detect patch V2
In-Reply-To: <201010312257.58221.njacobs8@hetnet.nl>
References: <201010312257.58221.njacobs8@hetnet.nl>
Message-ID: <20101101143733.GI3256@greenwood>

On Sun, Oct 31, 2010 at 10:57:58PM +0100, Nils wrote:
> This patch cleans up some white space and comments.
> It also adds a copyright header to pll_reset.c  .
> 
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

Thanks, r6009. I took the freedom to do a few more whitespace cleanups.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Mon Nov  1 15:39:50 2010
From: svn at coreboot.org (repository service)
Date: Mon, 01 Nov 2010 15:39:50 +0100
Subject: [coreboot] [commit] r6010 - trunk/src/northbridge/amd/gx2
Message-ID: <E1PCvY6-0002hI-Ed@ra.coresystems.de>

Author: uwe
Date: Mon Nov  1 15:39:49 2010
New Revision: 6010
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6010

Log:
Remove some unused code.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/northbridge/amd/gx2/pll_reset.c

Modified: trunk/src/northbridge/amd/gx2/pll_reset.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/pll_reset.c	Mon Nov  1 15:36:54 2010	(r6009)
+++ trunk/src/northbridge/amd/gx2/pll_reset.c	Mon Nov  1 15:39:49 2010	(r6010)
@@ -24,69 +24,6 @@
 #define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
 #define CALIBRATE_DIVISOR  (20*1000) /* 20ms / 20000 == 1usec */
 
-#if 0
-static unsigned int calibrate_tsc(void)
-{
-	/* Set the Gate high, disable speaker */
-	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
-
-	/*
-	 * Now let's take care of CTC channel 2
-	 *
-	 * Set the Gate high, program CTC channel 2 for mode 0,
-	 * (interrupt on terminal count mode), binary count,
-	 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
-	 */
-	outb(0xb0, 0x43);			/* binary, mode 0, LSB/MSB, Ch 2 */
-	outb(CALIBRATE_INTERVAL	& 0xff, 0x42);	/* LSB of count */
-	outb(CALIBRATE_INTERVAL	>> 8, 0x42);	/* MSB of count */
-
-	{
-		tsc_t start;
-		tsc_t end;
-		unsigned long count;
-
-		start = rdtsc();
-		count = 0;
-		do {
-			count++;
-		} while ((inb(0x61) & 0x20) == 0);
-		end = rdtsc();
-
-		/* Error: ECTCNEVERSET */
-		if (count <= 1)
-			goto bad_ctc;
-
-		/* 64-bit subtract - gcc just messes up with long longs */
-		__asm__("subl %2,%0\n\t"
-			"sbbl %3,%1"
-			:"=a" (end.lo), "=d" (end.hi)
-			:"g" (start.lo), "g" (start.hi),
-			 "0" (end.lo), "1" (end.hi));
-
-		/* Error: ECPUTOOFAST */
-		if (end.hi)
-			goto bad_ctc;
-
-
-		/* Error: ECPUTOOSLOW */
-		if (end.lo <= CALIBRATE_DIVISOR)
-			goto bad_ctc;
-
-		return (end.lo + CALIBRATE_DIVISOR -1)/CALIBRATE_DIVISOR;
-	}
-
-	/*
-	 * The CTC wasn't reliable: we got a hit on the very first read,
-	 * or the CPU was so fast/slow that the quotient wouldn't fit in
-	 * 32 bits..
-	 */
-bad_ctc:
-	print_err("bad_ctc\n");
-	return 0;
-}
-#endif
-
 /* spll_raw_clk = SYSREF * FbDIV,
  * GLIU Clock   = spll_raw_clk / MDIV
  * CPU Clock    = spll_raw_clk / VDIV
@@ -108,17 +45,6 @@
 	49, 40, 19, 59, 32, 54, 35,  0, 41, 60, 55,  0, 61,  0,  0,  0
 };
 
-static const unsigned char pci33_ddr_crt [] = {
-	/* FbDIV, VDIV, MDIV		   CPU/GeodeLink */
-	     12,    2,    3,		// 200/133
-	     16,    2,    3,		// 266/177
-             18,    2,    3,		// 300/200
-             20,    2,    3,		// 333/222
-             22,    2,    3,		// 366/244
-             24,    2,    3,		// 400/266
-             26,    2,    3             // 433/289
-};
-
 /*	FbDIV	VDIV	MDIV	CPU/GeodeLink */
 /*	12	2	3	200/133 */
 /*	16	2	3	266/177 */
@@ -128,31 +54,12 @@
 /*	24	2	3	400/266 */
 /*	26	2	3	433/289 */
 
-#if 0
-static unsigned int get_memory_speed(void)
-{
-	unsigned char val, hi, lo;
-
-	val = spd_read_byte(0xA0, 9);
-	hi = (val >> 4) & 0x0f;
-	lo = val & 0x0f;
-
-	return 20000/(hi*10 + lo);
-}
-#endif
-
-#define USE_GOODRICH_VERSION 1
-
-#if USE_GOODRICH_VERSION
-///////////////////////////////////////////////////////////////////////////////
-// Goodrich Version of pll_reset
-
 /* PLLCHECK_COMPLETED is the "we've already done this" flag */
 #define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
 
 #ifndef RSTPPL_LOWER_BYPASS_SET
 #define RSTPPL_LOWER_BYPASS_SET (1 << GLCP_SYS_RSTPLL_BYPASS)
-#endif /* RSTPPL_LOWER_BYPASS_SET */
+#endif // RSTPPL_LOWER_BYPASS_SET
 
 #define DEFAULT_MDIV	3
 #define DEFAULT_VDIV	2
@@ -218,7 +125,7 @@
 		/* CheckSemiSync proc */
 		/* Check for Semi-Sync in GeodeLink and CPU. */
 		/* We need to do this here since the strap settings don't account for these bits. */
-		SyncBits = 0;			// store the sync bits in up ebx
+		SyncBits = 0;			/* store the sync bits in up ebx */
 
 		/* Check for Bypass mode. */
 		if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET)
@@ -247,7 +154,6 @@
 			}
 		}
 
-
 		/*	SetSync: */
 		msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_PCI_SEMI_SYNC_SET | RSTPPL_LOWER_CPU_SEMI_SYNC_SET);
 		msrGlcpSysRstpll.lo |= SyncBits;
@@ -273,78 +179,3 @@
 	} /* we haven't configured the PLL; do it now */
 
 }
-// End of Goodrich version of pll_reset
-///////////////////////////////////////////////////////////////////////////////
-
-#else // #if USE_GOODRICH_VERSION
-
-static void pll_reset(void)
-{
-	msr_t msr;
-	unsigned int sysref, spll_raw, cpu_core, gliu;
-	unsigned mdiv, vdiv, fbdiv;
-
-	/* get CPU core clock in MHZ */
-	cpu_core = calibrate_tsc();
-	print_debug("Cpu core is ");
-	print_debug_hex32(cpu_core);
-	print_debug("\n");
-
-	msr = rdmsr(GLCP_SYS_RSTPLL);
-	if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
-#if 0
-		print_debug("MSR ");
-		print_debug_hex32(GLCP_SYS_RSTPLL);
-		print_debug("is ");
-		print_debug_hex32(msr.hi);
-		print_debug(":");
-		print_debug_hex32(msr.lo);
-
-		msr.hi = PLLMSRhi;
-		msr.lo = PLLMSRlo;
-		wrmsr(GLCP_SYS_RSTPLL, msr);
-		msr.lo |= PLLMSRlo1;
-		wrmsr(GLCP_SYS_RSTPLL, msr);
-
-		print_debug("Reset PLL\n");
-
-		msr.lo |= PLLMSRlo2;
-		wrmsr(GLCP_SYS_RSTPLL,msr);
-		print_debug("should not be here\n");
-#endif
-		print_err("shit");
-		while (1)
-			;
-	}
-
-	if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) {
-		/* PLL is already set and we are reboot from PLL reset */
-		print_debug("reboot from BIOS reset\n");
-		return;
-	}
-
-	/* get the sysref clock rate */
-	vdiv  = (msr.hi >> GLCP_SYS_RSTPLL_VDIV_SHIFT) & 0x07;
-	vdiv += 2;
-	fbdiv = (msr.hi >> GLCP_SYS_RSTPLL_FBDIV_SHIFT) & 0x3f;
-	fbdiv = fbdiv2plldiv[fbdiv];
-	spll_raw = cpu_core * vdiv;
-	sysref   = spll_raw / fbdiv;
-
-	/* get target memory rate by SPD */
-	//gliu = get_memory_speed();
-
-	msr.hi = 0x00000019;
-	msr.lo = 0x06de0378;
-	wrmsr(0x4c000014, msr);
-	msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
-	wrmsr(0x4c000014, msr);
-
-	print_debug("Reset PLL\n");
-
-	msr.lo |= ((1<<14) |(1<<13) | (1<<0));
-	wrmsr(0x4c000014,msr);
-
-	print_debug("should not be here\n");
-}
-#endif // #if USE_GOODRICH_VERSION



From uwe at hermann-uwe.de  Mon Nov  1 15:41:32 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 1 Nov 2010 15:41:32 +0100
Subject: [coreboot] [PATCH 3/4] Geode GX2 auto DRAM detect patch V2
In-Reply-To: <201010312258.06918.njacobs8@hetnet.nl>
References: <201010312258.06918.njacobs8@hetnet.nl>
Message-ID: <20101101144132.GJ3256@greenwood>

On Sun, Oct 31, 2010 at 10:58:06PM +0100, Nils wrote:
> This patch removes some unused code.
> 
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

Thanks, r6010.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From uwe at hermann-uwe.de  Mon Nov  1 15:19:46 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 1 Nov 2010 15:19:46 +0100
Subject: [coreboot] [PATCH 1/4] Geode GX2 auto DRAM detect patch V2
In-Reply-To: <201010312257.51890.njacobs8@hetnet.nl>
References: <201010312257.51890.njacobs8@hetnet.nl>
Message-ID: <20101101141946.GH3256@greenwood>

On Sun, Oct 31, 2010 at 10:57:51PM +0100, Nils wrote:
> This patch changes the MSR register numbers in to more descriptive names.
> 
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

Thanks, r6008.

I cross-checked against the datasheet and gx2def.h.


>  	/* 3. release CKE mask to enable CKE */
> -	msr = rdmsr(0x2000001d);
> +	msr = rdmsr(MC_CFCLK_DBUG);
>  	msr.lo &= ~(0x03 << 8);
> -	wrmsr(0x2000201d, msr);
> +	wrmsr(MC_CFCLK_DBUG, msr);

Heh, fun. This was a bug anyway (0x2000001d vs. 0x2000201d).


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Mon Nov  1 16:00:02 2010
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 01 Nov 2010 16:00:02 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1PCvre-0007oI-KP@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20101101/dc12c78c/attachment.html>

From svn at coreboot.org  Mon Nov  1 16:20:29 2010
From: svn at coreboot.org (repository service)
Date: Mon, 01 Nov 2010 16:20:29 +0100
Subject: [coreboot] [commit] r6011 - in trunk/src: include/cpu/amd
	mainboard/amd/rumba mainboard/lippert/frontrunner
	mainboard/wyse/s50 northbridge/amd/gx2
Message-ID: <E1PCwBR-0004UA-7p@ra.coresystems.de>

Author: uwe
Date: Mon Nov  1 16:20:27 2010
New Revision: 6011
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6011

Log:
Change Geode GX2 to use the auto DRAM detect code from Geode LX.

Also, change the GX2 boards to use it.

Add a processor speed setting function in human readable MHz and remove
the useless and broken PLLMSR settings (the processor speed was hardcoded
to 366MHz in pll_reset.c).

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/include/cpu/amd/gx2def.h
   trunk/src/mainboard/amd/rumba/romstage.c
   trunk/src/mainboard/lippert/frontrunner/Kconfig
   trunk/src/mainboard/lippert/frontrunner/romstage.c
   trunk/src/mainboard/wyse/s50/romstage.c
   trunk/src/northbridge/amd/gx2/Kconfig
   trunk/src/northbridge/amd/gx2/pll_reset.c
   trunk/src/northbridge/amd/gx2/raminit.c

Modified: trunk/src/include/cpu/amd/gx2def.h
==============================================================================
--- trunk/src/include/cpu/amd/gx2def.h	Mon Nov  1 15:39:49 2010	(r6010)
+++ trunk/src/include/cpu/amd/gx2def.h	Mon Nov  1 16:20:27 2010	(r6011)
@@ -413,6 +413,13 @@
 #define AES_GLD_MSR_PM		(MSR_AES + 0x2004)
 #define AES_CONTROL		(MSR_AES + 0x2006)
 
+/* from MC spec */
+#define MIN_MOD_BANKS		1
+#define MAX_MOD_BANKS		2
+#define MIN_DEV_BANKS		2
+#define MAX_DEV_BANKS		4
+#define MAX_COL_ADDR		17
+
 /* more fun stuff */
 #define BM			1	/* Base Mask - map power of 2 size aligned region */
 #define BMO			2	/* BM with an offset */

Modified: trunk/src/mainboard/amd/rumba/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/rumba/romstage.c	Mon Nov  1 15:39:49 2010	(r6010)
+++ trunk/src/mainboard/amd/rumba/romstage.c	Mon Nov  1 16:20:27 2010	(r6011)
@@ -15,87 +15,21 @@
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-        return smbus_read_byte(device, address);
-}
+#define DIMM0 0xA0
+#define DIMM1 0xA2
 
-#include "northbridge/amd/gx2/raminit.h"
-
-static inline unsigned int fls(unsigned int x)
-{
-        int r;
-
-        __asm__("bsfl %1,%0\n\t"
-                "jnz 1f\n\t"
-                "movl $32,%0\n"
-                "1:" : "=r" (r) : "g" (x));
-        return r;
-}
-
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+static inline int spd_read_byte(unsigned device, unsigned address)
 {
-	/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
-	 *                      component Banks (byte 17) * module banks, side (byte 5) *
-	 *                      width in bits (byte 6,7)
-	 *                    = Density per side (byte 31) * number of sides (byte 5) */
-	/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
-	msr_t msr;
-	unsigned char module_banks, val;
-
-	msr = rdmsr(MC_CF07_DATA);
-
-	/* get module banks (sides) per dimm, SPD byte 5 */
-	module_banks = spd_read_byte(0xA0, 5);
-	if (module_banks < 1 || module_banks > 2)
-		print_err("Module banks per dimm\n");
-	module_banks >>= 1;
-	msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
-	msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
-
-	/* get component banks per module bank, SPD byte 17 */
-	val = spd_read_byte(0xA0, 17);
-	if (val < 2 || val > 4)
-		print_err("Component banks per module bank\n");
-	val >>= 2;
-	msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
-	msr.hi |=  (val << CF07_UPPER_D0_CB_SHIFT);
-
-	/* get the module bank density, SPD byte 31  */
-	val = spd_read_byte(0xA0, 31);
-	val = fls(val);
-	val <<= module_banks;
-	msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
-	msr.hi |=  (val << CF07_UPPER_D0_SZ_SHIFT);
-
-	/* page size = 2^col address */
-	val = spd_read_byte(0xA0, 4);
-	val -= 7;
-	msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
-	msr.hi |=  (val << CF07_UPPER_D0_PSZ_SHIFT);
-
-	print_debug("computed msr.hi ");
-	print_debug_hex32(msr.hi);
-	print_debug("\n");
-
-	msr.lo = 0x00003000;
-	wrmsr(MC_CF07_DATA, msr);
-
-	msr = rdmsr(0x20000019);
-	msr.hi = 0x18000108;
-	msr.lo = 0x696332a3;
-	wrmsr(0x20000019, msr);
+ 	if (device != DIMM0)
+		return 0xFF;	/* No DIMM1, don't even try. */
 
+	return smbus_read_byte(device, address);
 }
 
+#include "northbridge/amd/gx2/raminit.h"
+#include "northbridge/amd/gx2/pll_reset.c"
 #include "northbridge/amd/gx2/raminit.c"
 #include "lib/generic_sdram.c"
-
-#define PLLMSRhi 0x00001490
-#define PLLMSRlo 0x02000030
-#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
-#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
-#include "northbridge/amd/gx2/pll_reset.c"
 #include "cpu/amd/model_gx2/cpureginit.c"
 #include "cpu/amd/model_gx2/syspreinit.c"
 #include "cpu/amd/model_lx/msrinit.c"

Modified: trunk/src/mainboard/lippert/frontrunner/Kconfig
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/Kconfig	Mon Nov  1 15:39:49 2010	(r6010)
+++ trunk/src/mainboard/lippert/frontrunner/Kconfig	Mon Nov  1 16:20:27 2010	(r6011)
@@ -6,6 +6,7 @@
 	select CPU_AMD_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5535
+	select HAVE_DEBUG_SMBUS
 	select UDELAY_TSC
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256

Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/romstage.c	Mon Nov  1 15:39:49 2010	(r6010)
+++ trunk/src/mainboard/lippert/frontrunner/romstage.c	Mon Nov  1 16:20:27 2010	(r6011)
@@ -1,4 +1,5 @@
 #include <stdint.h>
+#include <spd.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
@@ -15,35 +16,61 @@
 
 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
-#include "northbridge/amd/gx2/raminit.h"
 
-/* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+#define DIMM0 0xA0
+#define DIMM1 0xA2
+
+static const unsigned char spdbytes[] = {	/* 4x Qimonda HYB25DC512160CF-6 */
+	0xFF, 0xFF,				/* only values used by raminit.c are set */
+	[SPD_MEMORY_TYPE]		= SPD_MEMORY_TYPE_SDRAM_DDR,	/* (Fundamental) memory type */
+	[SPD_NUM_ROWS]			= 0x0D,	/* Number of row address bits [13] */
+	[SPD_NUM_COLUMNS]		= 0x0A,	/* Number of column address bits [10] */
+	[SPD_NUM_DIMM_BANKS]		= 1,	/* Number of module rows (banks) */
+	0xFF, 0xFF, 0xFF,
+	[SPD_MIN_CYCLE_TIME_AT_CAS_MAX]	= 0x60,	/* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [6.0 ns in BCD] */
+	0xFF, 0xFF,
+	[SPD_REFRESH]			= 0x82,	/* Refresh rate/type [Self Refresh, 7.8 us] */
+	[SPD_PRIMARY_SDRAM_WIDTH]	= 64,	/* SDRAM width (primary SDRAM) [64 bits] */
+	0xFF, 0xFF, 0xFF,
+	[SPD_NUM_BANKS_PER_SDRAM]	= 4,	/* SDRAM device attributes, number of banks on SDRAM device */
+	[SPD_ACCEPTABLE_CAS_LATENCIES]	= 0x1C,	/* SDRAM device attributes, CAS latency [3, 2.5, 2] */
+	0xFF, 0xFF,
+	[SPD_MODULE_ATTRIBUTES]		= 0x20,	/* SDRAM module attributes [differential clk] */
+	[SPD_DEVICE_ATTRIBUTES_GENERAL]	= 0x40,	/* SDRAM device attributes, general [Concurrent AP] */
+	[SPD_SDRAM_CYCLE_TIME_2ND]	= 0x60,	/* SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] */
+	0xFF,
+	[SPD_SDRAM_CYCLE_TIME_3RD]	= 0x75,	/* SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] */
+	0xFF,
+	[SPD_tRP]			= 72,	/* Min. row precharge time [18 ns in units of 0.25 ns] */
+	[SPD_tRRD]			= 48,	/* Min. row active to row active [12 ns in units of 0.25 ns] */
+	[SPD_tRCD]			= 72,	/* Min. RAS to CAS delay [18 ns in units of 0.25 ns] */
+	[SPD_tRAS]			= 42,	/* Min. RAS pulse width = active to precharge delay [42 ns] */
+	[SPD_BANK_DENSITY]		= 0x40,	/* Density of each row on module [256 MB] */
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	[SPD_tRFC]			= 72	/* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [72 ns] */
+};
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
-	msr_t msr;
-	/* 1. Initialize GLMC registers base on SPD values,
-	 * Hard coded as XpressROM for now */
-	//print_debug("sdram_enable step 1\n");
-	msr = rdmsr(0x20000018);
-	msr.hi = 0x10076013;
-	msr.lo = 0x3400;
-	wrmsr(0x20000018, msr);
-
-	msr = rdmsr(0x20000019);
-	msr.hi = 0x18000008;
-	msr.lo = 0x696332a3;
-	wrmsr(0x20000019, msr);
+	if (device != DIMM0)
+		return 0xFF;	/* No DIMM1, don't even try. */
+
+#if CONFIG_DEBUG_SMBUS
+	if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
+		print_err("ERROR: spd_read_byte(DIMM0, 0x");
+		print_err_hex8(address);
+		print_err(") returns 0xff\n");
+	}
+#endif
 
+	/* Fake SPD ROM value */
+	return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
 }
 
+#include "northbridge/amd/gx2/raminit.h"
+#include "northbridge/amd/gx2/pll_reset.c"
 #include "northbridge/amd/gx2/raminit.c"
 #include "lib/generic_sdram.c"
-
-#define PLLMSRhi 0x00000226
-#define PLLMSRlo 0x00000008
-#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
-#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
-#include "northbridge/amd/gx2/pll_reset.c"
 #include "cpu/amd/model_gx2/cpureginit.c"
 #include "cpu/amd/model_gx2/syspreinit.c"
 #include "cpu/amd/model_lx/msrinit.c"

Modified: trunk/src/mainboard/wyse/s50/romstage.c
==============================================================================
--- trunk/src/mainboard/wyse/s50/romstage.c	Mon Nov  1 15:39:49 2010	(r6010)
+++ trunk/src/mainboard/wyse/s50/romstage.c	Mon Nov  1 16:20:27 2010	(r6011)
@@ -34,92 +34,21 @@
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-        return smbus_read_byte(device, address);
-}
+#define DIMM0 0xA0
+#define DIMM1 0xA2
 
-#include "northbridge/amd/gx2/raminit.h"
-
-	/* This is needed because ROMCC doesn`t now the ctz bitop */
-static inline unsigned int ctz(unsigned int n)
+static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
-	int zeros;
-
-	n = (n ^ (n - 1)) >> 1;
-	for (zeros = 0; n; zeros++)
-	{
-	  n >>= 1;
-	}
-	return zeros;
-}
-
-static void sdram_set_spd_registers(const struct mem_controller *ctrl) 
-{
-	/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
-	 *                      component Banks (byte 17) * module banks, side (byte 5) *
-	 *                      width in bits (byte 6,7)
-	 *                    = Density per side (byte 31) * number of sides (byte 5) */
-	/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
-	msr_t msr;
-	unsigned char module_banks, val;
-	uint16_t dimm_size;
-
-	msr = rdmsr(MC_CF07_DATA);
-
-	/* get module banks (sides) per dimm, SPD byte 5 */
-	module_banks = spd_read_byte(0xA0, 5);
-	if (module_banks < 1 || module_banks > 2)
-		print_err("Module banks per dimm\n");
-	module_banks >>= 1;
-	msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
-	msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
-
-	/* get component banks per module bank, SPD byte 17 */
-	val = spd_read_byte(0xA0, 17);
-	if (val < 2 || val > 4)
-		print_err("Component banks per module bank\n");
-	val >>= 2;
-	msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
-	msr.hi |=  (val << CF07_UPPER_D0_CB_SHIFT);
-
-	dimm_size = spd_read_byte(0xA0, 31);
-	dimm_size |= (dimm_size << 8);	/* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
-	dimm_size &= 0x01FC;	/* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
-	/*       Module Density * Module Banks */
-	dimm_size <<= (0 >> CF07_UPPER_D0_MB_SHIFT) & 1;	/* shift to multiply by # DIMM banks */
-	if (dimm_size != 0) {
-	dimm_size = ctz(dimm_size);
-	}
-	if (dimm_size > 7) {	/* 7 is 512MB only support 512MB per DIMM */
-		print_err("Only support up to 512MB \n");
-		hlt();
-	}
-	msr.hi |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
-
-	/* page size = 2^col address */
-	val = spd_read_byte(0xA0, 4);
-	val -= 7;
-	msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
-	msr.hi |=  (val << CF07_UPPER_D0_PSZ_SHIFT);
-
-	print_debug("computed msr.hi ");
-	print_debug_hex32(msr.hi);
-	print_debug("\n");
-
-	msr.lo = 0x00003400;
-	wrmsr(MC_CF07_DATA, msr);
-
-	msr = rdmsr(MC_CF8F_DATA);
-	msr.hi = 0x18000008;
-	msr.lo = 0x296332a3;
-	wrmsr(MC_CF8F_DATA, msr);		
+	if (device != DIMM0)
+		return 0xFF;	/* No DIMM1, don't even try. */
 
+	return smbus_read_byte(device, address);
 }
 
+#include "northbridge/amd/gx2/raminit.h"
+#include "northbridge/amd/gx2/pll_reset.c"
 #include "northbridge/amd/gx2/raminit.c"
 #include "lib/generic_sdram.c"
-#include "northbridge/amd/gx2/pll_reset.c"
 #include "cpu/amd/model_gx2/cpureginit.c"
 #include "cpu/amd/model_gx2/syspreinit.c"
 #include "cpu/amd/model_lx/msrinit.c"

Modified: trunk/src/northbridge/amd/gx2/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/gx2/Kconfig	Mon Nov  1 15:39:49 2010	(r6010)
+++ trunk/src/northbridge/amd/gx2/Kconfig	Mon Nov  1 16:20:27 2010	(r6011)
@@ -21,3 +21,9 @@
 	bool
 	select GEODE_VSA
 
+# Valid PROCESSOR_MHZ options: 300/366/400 MHz.
+config PROCESSOR_MHZ
+	int
+	default 366
+	depends on NORTHBRIDGE_AMD_GX2
+

Modified: trunk/src/northbridge/amd/gx2/pll_reset.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/pll_reset.c	Mon Nov  1 15:39:49 2010	(r6010)
+++ trunk/src/northbridge/amd/gx2/pll_reset.c	Mon Nov  1 16:20:27 2010	(r6011)
@@ -63,13 +63,25 @@
 
 #define DEFAULT_MDIV	3
 #define DEFAULT_VDIV	2
-#define DEFAULT_FBDIV	22	// 366/244 ; 24 400/266 018 ;300/200
 
 static void pll_reset(void)
 {
 	msr_t msrGlcpSysRstpll;
 	unsigned MDIV_VDIV_FBDIV;
 	unsigned SyncBits;			/* store the sync bits in up ebx */
+	unsigned DEFAULT_FBDIV;
+
+	if (CONFIG_PROCESSOR_MHZ == 400) {
+		DEFAULT_FBDIV = 24;
+	} else if (CONFIG_PROCESSOR_MHZ == 366) {
+		DEFAULT_FBDIV = 22;
+	} else if (CONFIG_PROCESSOR_MHZ == 300) {
+		DEFAULT_FBDIV = 18;
+	} else {
+		printk(BIOS_ERR, "Unsupported PROCESSOR_MHZ setting!\n");
+		post_code(POST_PLL_CPU_VER_FAIL);
+		__asm__ __volatile__("hlt\n");
+	}
 
 	/* clear the Bypass bit */
 
@@ -179,3 +191,10 @@
 	} /* we haven't configured the PLL; do it now */
 
 }
+
+static unsigned int GeodeLinkSpeed(void)
+{
+	unsigned geodelinkspeed;
+	geodelinkspeed = ((CONFIG_PROCESSOR_MHZ * DEFAULT_VDIV) / DEFAULT_MDIV);
+	return (geodelinkspeed);
+}

Modified: trunk/src/northbridge/amd/gx2/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/raminit.c	Mon Nov  1 15:39:49 2010	(r6010)
+++ trunk/src/northbridge/amd/gx2/raminit.c	Mon Nov  1 16:20:27 2010	(r6011)
@@ -1,7 +1,521 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #include <cpu/amd/gx2def.h>
+#include <spd.h>
+
+static const unsigned char NumColAddr[] = {
+	0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
+	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
+};
+
+static void banner(const char *s)
+{
+	printk(BIOS_DEBUG, " * %s\n", s);
+}
+
+static void hcf(void)
+{
+	print_emerg("DIE\n");
+	/* this guarantees we flush the UART fifos (if any) and also
+	 * ensures that things, in general, keep going so no debug output
+	 * is lost
+	 */
+	while (1)
+		print_emerg_char(0);
+}
+
+static void auto_size_dimm(unsigned int dimm)
+{
+	uint32_t dimm_setting;
+	uint16_t dimm_size;
+	uint8_t spd_byte;
+	msr_t msr;
+
+	dimm_setting = 0;
+
+	banner("Check present");
+	/* Check that we have a dimm */
+	if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
+		return;
+	}
+
+	banner("MODBANKS");
+	/* Field: Module Banks per DIMM */
+	/* EEPROM byte usage: (5) Number of DIMM Banks */
+	spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
+	if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
+		print_emerg("Number of module banks not compatible\n");
+		post_code(ERROR_BANK_SET);
+		hcf();
+	}
+	dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
+	banner("FIELDBANKS");
+
+	/* Field: Banks per SDRAM device */
+	/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
+	spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
+	if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
+		print_emerg("Number of device banks not compatible\n");
+		post_code(ERROR_BANK_SET);
+		hcf();
+	}
+	dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
+	banner("SPDNUMROWS");
+
+	/*; Field: DIMM size
+	 *; EEPROM byte usage: (3)  Number of Row Addresses
+	 *;                                       (4)  Number of Column Addresses
+	 *;                                       (5)  Number of DIMM Banks
+	 *;                                       (31) Module Bank Density
+	 *; Size = Module Density * Module Banks
+	 */
+	if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
+	    || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
+		print_emerg("Assymetirc DIMM not compatible\n");
+		post_code(ERROR_UNSUPPORTED_DIMM);
+		hcf();
+	}
+	banner("SPDBANKDENSITY");
+
+	dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
+	banner("DIMMSIZE");
+	dimm_size |= (dimm_size << 8);	/* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
+	dimm_size &= 0x01FC;	/* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
+
+	/*       Module Density * Module Banks */
+	dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;	/* shift to multiply by # DIMM banks */
+	banner("BEFORT CTZ");
+	dimm_size = __builtin_ctz(dimm_size);
+	banner("TEST DIMM SIZE>7");
+	if (dimm_size > 7) {	/* 7 is 512MB only support 512MB per DIMM */
+		print_emerg("Only support up to 512MB per DIMM\n");
+		post_code(ERROR_DENSITY_DIMM);
+		hcf();
+	}
+	dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
+	banner("PAGESIZE");
+
+/*; Field: PAGE size
+*; EEPROM byte usage: (4)  Number of Column Addresses
+*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
+*
+*; But this really works by magic.
+*; If ma[11:0] is the memory address pins, and pa[13:0] is the physical column address
+*; that MC generates, here is how the MC assigns the pa onto the ma pins:
+*
+*;ma	11	10	09	08	07	06	05	04	03	02	01	00
+*;--------------------------------------------------------------------------------------------------------------------------------------
+*;pa						09	08	07	06	05	04	03	(7 col addr bits = 1K page size)
+*;pa					10	09	08	07	06	05	04	03	(8 col addr bits = 2K page size)
+*;pa				11	10	09	08	07	06	05	04	03	(9 col addr bits = 4K page size)
+*;pa			12	11	10	09	08	07	06	05	04	03	(10 col addr bits = 8K page size)
+*;pa	13	AP	12	11	10	09	08	07	06	05	04	03	(11 col addr bits = 16K page size)
+*; *AP=autoprecharge bit
+*
+*; Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
+*; so lower 3 address bits are dont_cares.So from the table above,
+*; it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
+*; it adds 3 to get 10, then does 2^10=1K.  Get it?*/
+
+	spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
+	banner("MAXCOLADDR");
+	if (spd_byte > MAX_COL_ADDR) {
+		print_emerg("DIMM page size not compatible\n");
+		post_code(ERROR_SET_PAGE);
+		hcf();
+	}
+	banner(">11address test");
+	spd_byte -= 7;
+	if (spd_byte > 4) {	/* if the value is above 4 it means >11 col address lines */
+		spd_byte = 7;	/* which means >16k so set to disabled */
+	}
+	dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT;	/* 0=1k,1=2k,2=4k,etc */
+
+	banner("RDMSR CF07");
+	msr = rdmsr(MC_CF07_DATA);
+	banner("WRMSR CF07");
+	if (dimm == DIMM0) {
+		msr.hi &= 0xFFFF0000;
+		msr.hi |= dimm_setting;
+	} else {
+		msr.hi &= 0x0000FFFF;
+		msr.hi |= dimm_setting << 16;
+	}
+	wrmsr(MC_CF07_DATA, msr);
+	banner("ALL DONE");
+}
+
+static void checkDDRMax(void)
+{
+	uint8_t spd_byte0, spd_byte1;
+	uint16_t speed;
+
+	/* PC133 identifier */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+	if (spd_byte0 == 0xFF) {
+		spd_byte0 = 0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+	if (spd_byte1 == 0xFF) {
+		spd_byte1 = 0;
+	}
+
+	/* Use the slowest DIMM */
+	if (spd_byte0 < spd_byte1) {
+		spd_byte0 = spd_byte1;
+	}
+
+	/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+	speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
+
+	/* current speed > max speed? */
+	if (GeodeLinkSpeed() > speed) {
+		print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
+		post_code(POST_PLL_MEM_FAIL);
+		hcf();
+	}
+}
+
+const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 };	/* ns */
+
+static void set_refresh_rate(void)
+{
+	uint8_t spd_byte0, spd_byte1;
+	uint16_t rate0, rate1;
+	msr_t msr;
+
+	spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
+	spd_byte0 &= 0xF;
+	if (spd_byte0 > 5) {
+		spd_byte0 = 5;
+	}
+	rate0 = REF_RATE[spd_byte0];
+
+	spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
+	spd_byte1 &= 0xF;
+	if (spd_byte1 > 5) {
+		spd_byte1 = 5;
+	}
+	rate1 = REF_RATE[spd_byte1];
+
+	/* Use the faster rate (lowest number) */
+	if (rate0 > rate1) {
+		rate0 = rate1;
+	}
+
+	msr = rdmsr(MC_CF07_DATA);
+	msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
+			<< CF07_LOWER_REF_INT_SHIFT;
+	wrmsr(MC_CF07_DATA, msr);
+}
+
+const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 };	/* 1(1.5), 1.5, 2, 2.5, 0 */
+
+static u8 getcasmap(u32 dimm, u16 glspeed)
+{
+	u16 dimm_speed;
+	u8 spd_byte, casmap, casmap_shift=0;
+
+	/**************************	 DIMM0	**********************************/
+	casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
+	if (casmap != 0xFF) {
+		/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
+		spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
+		if (spd_byte != 0) {
+			/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+			dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
+			if (dimm_speed >= glspeed) {
+				casmap_shift = 1; /* -.5 is a shift of 1 */
+				/* IF -1 timing is supported, check -1 timing > GeodeLink */
+				spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
+				if (spd_byte != 0) {
+					/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+					dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
+					if (dimm_speed >= glspeed) {
+						casmap_shift = 2; /* -1 is a shift of 2 */
+					}
+				}	/* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
+			} else {
+				casmap_shift = 0;
+			}
+		}	/* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
+		/* set the casmap based on the shift to limit possible CAS settings */
+		spd_byte = 31 - __builtin_clz((uint32_t) casmap);
+		/* just want bits in the lower byte since we have to cast to a 32 */
+		casmap &= 0xFF << (spd_byte - casmap_shift);
+	} else {		/* No DIMM */
+		casmap = 0;
+	}
+	return casmap;
+}
+
+static void setCAS(void)
+{
+/*;*****************************************************************************
+;*
+;*	setCAS
+;*	EEPROM byte usage: (18) SDRAM device attributes - CAS latency
+;*	EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
+;*	EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
+;*
+;*	The CAS setting is based on the information provided in each DIMMs SPD.
+;*	 The speed at which a DIMM can run is described relative to the slowest
+;*	 CAS the DIMM supports. Each speed for the relative CAS settings is
+;*	 checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
+;*	 speed, the CAS setting	 is removed from the list of good settings for
+;*	 the DIMM. This is done for both DIMMs and the lists are compared to
+;*	 find the lowest common CAS latency setting. If there are no CAS settings
+;*	 in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
+;*
+;*	Entry:
+;*	Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
+;*	Destroys: We really use everything !
+;*****************************************************************************/
+	uint16_t glspeed;
+	uint8_t spd_byte, casmap0, casmap1;
+	msr_t msr;
+
+	glspeed = GeodeLinkSpeed();
+
+	casmap0 = getcasmap(DIMM0, glspeed);
+	casmap1 = getcasmap(DIMM1, glspeed);
+
+	/*********************	CAS_LAT MAP COMPARE	***************************/
+	if (casmap0 == 0) {
+		spd_byte = CASDDR[__builtin_ctz(casmap1)];
+	} else if (casmap1 == 0) {
+		spd_byte = CASDDR[__builtin_ctz(casmap0)];
+	} else if ((casmap0 &= casmap1)) {
+		spd_byte = CASDDR[__builtin_ctz(casmap0)];
+	} else {
+		print_emerg("DIMM CAS Latencies not compatible\n");
+		post_code(ERROR_DIFF_DIMMS);
+		hcf();
+	}
+
+	msr = rdmsr(MC_CF8F_DATA);
+	msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
+	msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
+	wrmsr(MC_CF8F_DATA, msr);
+}
+
+static void set_latencies(void)
+{
+	uint32_t memspeed, dimm_setting;
+	uint8_t spd_byte0, spd_byte1;
+	msr_t msr;
+
+	memspeed = GeodeLinkSpeed() / 2;
+	dimm_setting = 0;
+
+	/* MC_CF8F setup */
+	/* tRAS */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
+	if (spd_byte0 == 0xFF) {
+		spd_byte0 = 0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
+	if (spd_byte1 == 0xFF) {
+		spd_byte1 = 0;
+	}
+	if (spd_byte0 < spd_byte1) {
+		spd_byte0 = spd_byte1;
+	}
+	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	spd_byte1 = (spd_byte0 * memspeed) / 1000;
+	if (((spd_byte0 * memspeed) % 1000)) {
+		++spd_byte1;
+	}
+	if (spd_byte1 > 6) {
+		--spd_byte1;
+	}
+	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
+
+	/* tRP */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
+	if (spd_byte0 == 0xFF) {
+		spd_byte0 = 0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
+	if (spd_byte1 == 0xFF) {
+		spd_byte1 = 0;
+	}
+	if (spd_byte0 < spd_byte1) {
+		spd_byte0 = spd_byte1;
+	}
+	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
+	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
+		++spd_byte1;
+	}
+	dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
+
+	/* tRCD */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
+	if (spd_byte0 == 0xFF) {
+		spd_byte0 = 0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
+	if (spd_byte1 == 0xFF) {
+		spd_byte1 = 0;
+	}
+	if (spd_byte0 < spd_byte1) {
+		spd_byte0 = spd_byte1;
+	}
+	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
+	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
+		++spd_byte1;
+	}
+	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
+
+	/* tRRD */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
+	if (spd_byte0 == 0xFF) {
+		spd_byte0 = 0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
+	if (spd_byte1 == 0xFF) {
+		spd_byte1 = 0;
+	}
+	if (spd_byte0 < spd_byte1) {
+		spd_byte0 = spd_byte1;
+	}
+	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
+	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
+		++spd_byte1;
+	}
+	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
+
+	/* tRC = tRP + tRAS */
+	dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
+	     		((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
+	    			<< CF8F_LOWER_REF2ACT_SHIFT;
+
+	msr = rdmsr(MC_CF8F_DATA);
+	msr.lo &= 0xF00000FF;
+	msr.lo |= dimm_setting;
+	msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
+	wrmsr(MC_CF8F_DATA, msr);
+	printk(BIOS_DEBUG, "MSR MC_CF8F_DATA (%08x) value is %08x:%08x\n",
+	MC_CF8F_DATA, msr.hi, msr.lo);
+}
+
+static void set_extended_mode_registers(void)
+{
+	uint8_t spd_byte0, spd_byte1;
+	msr_t msr;
+	spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
+	if (spd_byte0 == 0xFF) {
+		spd_byte0 = 0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
+	if (spd_byte1 == 0xFF) {
+		spd_byte1 = 0;
+	}
+	spd_byte1 &= spd_byte0;
+
+	msr = rdmsr(MC_CF07_DATA);
+	if (spd_byte1 & 1) {	/* Drive Strength Control */
+		msr.lo |= CF07_LOWER_EMR_DRV_SET;
+	}
+	if (spd_byte1 & 2) {	/* FET Control */
+		msr.lo |= CF07_LOWER_EMR_QFC_SET;
+	}
+	wrmsr(MC_CF07_DATA, msr);
+}
 
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
+	msr_t msr;
+	uint32_t msrnum;
+
+	/* Set Refresh Staggering */
+	msrnum = MC_CF07_DATA;
+	msr = rdmsr(msrnum);
+	msr.lo &= ~0xC0;
+	msr.lo |= 0x0;		/* set refresh to 4SDRAM clocks */
+	wrmsr(msrnum, msr);
+
+	/* Memory Interleave: Set HOI here otherwise default is LOI */
+	/* msrnum = MC_CF8F_DATA;
+	   msr = rdmsr(msrnum);
+	   msr.hi |= CF8F_UPPER_HOI_LOI_SET;
+	   wrmsr(msrnum, msr); */
+}
+
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+{
+	uint8_t spd_byte;
+
+	banner("sdram_set_spd_register");
+	post_code(POST_MEM_SETUP);	// post_70h
+
+	spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
+	banner("Check DIMM 0");
+	/* Check DIMM is not Register and not Buffered DIMMs. */
+	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
+		print_emerg("DIMM0 NOT COMPATIBLE\n");
+		post_code(ERROR_UNSUPPORTED_DIMM);
+		hcf();
+	}
+	banner("Check DIMM 1");
+	spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
+	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
+		print_emerg("DIMM1 NOT COMPATIBLE\n");
+		post_code(ERROR_UNSUPPORTED_DIMM);
+		hcf();
+	}
+
+	post_code(POST_MEM_SETUP2);	// post_72h
+	banner("Check DDR MAX");
+
+	/* Check that the memory is not overclocked. */
+	checkDDRMax();
+
+	/* Size the DIMMS */
+	post_code(POST_MEM_SETUP3);	// post_73h
+	banner("AUTOSIZE DIMM 0");
+	auto_size_dimm(DIMM0);
+	post_code(POST_MEM_SETUP4);	// post_74h
+	banner("AUTOSIZE DIMM 1");
+	auto_size_dimm(DIMM1);
+
+	/* Set CAS latency */
+	banner("set cas latency");
+	post_code(POST_MEM_SETUP5);	// post_75h
+	setCAS();
+
+	/* Set all the other latencies here (tRAS, tRP....) */
+	banner("set all latency");
+	set_latencies();
+
+	/* Set Extended Mode Registers */
+	banner("set emrs");
+	set_extended_mode_registers();
+
+	banner("set ref rate");
+	/* Set Memory Refresh Rate */
+	set_refresh_rate();
 }
 
 /* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
@@ -40,18 +554,6 @@
 	}
 	//print_debug("sdram_enable step 4\n");
 
-	/* 5. set refresh interval */
-	msr = rdmsr(0x20000018);
-	msr.lo &= ~(0xffff << 8);
-	msr.lo |=  (0x34 << 8);
-	wrmsr(0x20000018, msr);
-	/* set refresh staggering to 4 SDRAM clocks */
-	msr = rdmsr(0x20000018);
-	msr.lo &= ~(0x03 << 6);
-	msr.lo |=  (0x00 << 6);
-	wrmsr(0x20000018, msr);
-	//print_debug("sdram_enable step 5\n");
-
 	/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(MC_CF07_DATA);
 	msr.lo |=  ((0x01 << 28) | 0x01);



From uwe at hermann-uwe.de  Mon Nov  1 16:21:36 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 1 Nov 2010 16:21:36 +0100
Subject: [coreboot] [PATCH 4/4] Geode GX2 auto DRAM detect patch V2
In-Reply-To: <201010312258.28195.njacobs8@hetnet.nl>
References: <201010312258.28195.njacobs8@hetnet.nl>
Message-ID: <20101101152136.GK3256@greenwood>

On Sun, Oct 31, 2010 at 10:58:28PM +0100, Nils wrote:
> This patch changes Geode GX2 to use the auto DRAM detect code
> from Geode LX and changes the boards to use it.
> It also  adds a processor speed setting function in human 
> readable Mhz and removes the useless and broken PLLMSR settings.
> (the processor speed was hardcoded to 366Mhz in pll_reset.c)
> 
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

Thanks, r6011 with some small whitespace changes and s/Mhz/MHz/.


> Index: src/northbridge/amd/gx2/Kconfig
> ===================================================================
> --- src/northbridge/amd/gx2/Kconfig	(revision 6006)
> +++ src/northbridge/amd/gx2/Kconfig	(working copy)
> @@ -21,3 +21,9 @@
>  	bool
>  	select GEODE_VSA
>  
> +# Valid PROCESSOR_MHZ options: 300 ; 366 ; 400 Mhz
> +config PROCESSOR_MHZ
> +	int
> +	default 366
> +	depends on NORTHBRIDGE_AMD_GX2

Maybe we could make a GX2_PROCESSOR_MHZ_300, GX2_PROCESSOR_MHZ_366 etc.
here, and let each board "select" the correct one in its Kconfig file?


> +static void banner(const char *s)
> +{
> +	printk(BIOS_DEBUG, " * %s\n", s);
> +}

I'd personally drop this (also in the LX code), let's just use printk(),
there's no reason to add such a mini-wrapper.


> +	if (CONFIG_PROCESSOR_MHZ == 400){
> +		DEFAULT_FBDIV = 24;
> +	}
> +	else if (CONFIG_PROCESSOR_MHZ == 366){
> +		DEFAULT_FBDIV = 22;
> +	}
> +	else if (CONFIG_PROCESSOR_MHZ == 300){
> +		DEFAULT_FBDIV = 18;
> +	} else {
> +		printk(BIOS_ERR, "Unsupported PROCESSOR_MHZ setting !\n");
> +		post_code(POST_PLL_CPU_VER_FAIL);
> +		__asm__ __volatile__("hlt\n");

Shouldn't there be a "while (1)" around the hlt instruction?


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From ward at gnu.org  Mon Nov  1 17:03:38 2010
From: ward at gnu.org (Ward Vandewege)
Date: Mon, 1 Nov 2010 12:03:38 -0400
Subject: [coreboot] [PATCH] don't print too early on mcp55-based boards
Message-ID: <20101101160338.GA28294@countzero.vandewege.net>

See attached. Perhaps we should also print a post code if the SMBus
controller can't be found - suggestions for a value?

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator
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From njacobs8 at hetnet.nl  Mon Nov  1 20:28:27 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Mon, 1 Nov 2010 20:28:27 +0100
Subject: [coreboot] [PATCH 0/4] Geode GX2 auto DRAM detect patch V2
Message-ID: <201011012028.27545.njacobs8@hetnet.nl>

Hi Uwe,
Thanks for the fast review and commit!

>Heh, fun. This was a bug anyway (0x2000001d vs. 0x2000201d).
Yes.

>Thanks, r6009. I took the freedom to do a few more whitespace cleanups.
Thanks, i must have overlooked them.

>Thanks, r6011 with some small whitespace changes and s/Mhz/MHz/.
OK thanks.

>Maybe we could make a GX2_PROCESSOR_MHZ_300, GX2_PROCESSOR_MHZ_366 etc.
>here, and let each board "select" the correct one in its Kconfig file?
This sounds good, i actually thought about something like that but i didn?t 
quite know how.
And because at the moment there are only boards with 366 Mhz so i skipped it.
I will study it some more and try to make a patch for it.

>I'd personally drop this (also in the LX code), let's just use printk(),
>there's no reason to add such a mini-wrapper.
I copied it from LX.
I will make a patch for that when i find some time.

>Shouldn't there be a "while (1)" around the hlt instruction?
?? i don't know should it?
The code seems to work, but if it is preferred/needed i will add it.
Can you point me to some example code or could you supply some code snipped i 
can test?

Thanks, Nils.



From scott at notabs.org  Mon Nov  1 20:34:30 2010
From: scott at notabs.org (Scott Duplichan)
Date: Mon, 1 Nov 2010 14:34:30 -0500
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7
Message-ID: <2924E87E845A4B3F98F6D270D6196482@m3a78>

This patch solves crashes and BSODs that occur when booting Win7 with
AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB
by running dxdiag and Windows media player at 1600x1200 true color.
Additional changes needed to boot Win7 on Mahogany_fam10 will follow.

-- Leave graphics debug bar enabled because the ATI driver uses it.
-- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
-- Make strap programming more closely follow the reference BIOS.
-- Disable PCIe bar 3 after using it.
-- UMA size is no longer hardcoded.
-- Disable write combining for all steppings to eliminate stability problem.
-- Correct task file data.
-- Improve the accuracy of the Atom table that passes information to the driver.

Signed-off-by: Scott Duplichan <scott at notabs.org>

Index: src/southbridge/amd/rs780/rs780.c
===================================================================
--- src/southbridge/amd/rs780/rs780.c	(revision 6011)
+++ src/southbridge/amd/rs780/rs780.c	(working copy)
@@ -133,11 +133,6 @@
 	temp32 = pci_read_config32(nb_dev, 0x4c);
 	printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32);
 
-	/* disable GFX debug. */
-	temp8 = pci_read_config8(nb_dev, 0x8d);
-	temp8 &= ~(1<<1);
-	pci_write_config8(nb_dev, 0x8d, temp8);
-
 	/* set temporary NB TOM to 0x40000000. */
 	rs780_set_tom(nb_dev);
 
@@ -194,15 +189,27 @@
 static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 {
 	/* NB_InitGFXStraps */
-	u32 MMIOBase, apc04, apc18, apc24;
+	u32 MMIOBase, apc04, apc18, apc24, romstrap2;
+	msr_t pcie_mmio_save;
 	volatile u32 * strap;
 
+	// disable processor pcie mmio, if enabled
+	if (is_family10h()) {
+		msr_t temp;
+		pcie_mmio_save = temp = rdmsr (0xc0010058);
+		temp.lo &= ~1;
+		wrmsr (0xc0010058, temp);
+	}
+
 	/* Get PCIe configuration space. */
 	MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0;
 	/* Temporarily disable PCIe configuration space. */
+
 	set_htiu_enable_bits(nb_dev, 0x32, 1<<28, 0);
 
+	// 1E: NB_BIF_SPARE
 	set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7);
+
 	/* Set a temporary Bus number. */
 	apc18 = pci_read_config32(dev, 0x18);
 	pci_write_config32(dev, 0x18, 0x010100);
@@ -214,18 +221,27 @@
 	pci_write_config8(dev, 0x04, 0x02);
 
 	/* Program Straps. */
-	strap = (volatile u32 *)(MMIOBase + 0x15020);
+	romstrap2 = 1 << 26; // enables audio function
 #if (CONFIG_GFXUMA == 1)
-	*strap = 1<<7; /* the format of BIF_MEM_AP_SIZE. 001->256MB? */
-#else
-	*strap = 0; /* 128M SP memory, 000 -> 128MB */
+	extern uint64_t uma_memory_size;
+	// bits 7-9: aperture size
+	// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g 
+	if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;
+	if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7;
+	if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7;
+	if (uma_memory_size == 0x10000000) romstrap2 |= 1 << 7;
+	if (uma_memory_size == 0x20000000) romstrap2 |= 4 << 7;
+	if (uma_memory_size == 0x40000000) romstrap2 |= 5 << 7;
+	if (uma_memory_size == 0x80000000) romstrap2 |= 6 << 7;
 #endif
+	strap = (volatile u32 *)(MMIOBase + 0x15020);
+	*strap = romstrap2;
 	strap = (volatile u32 *)(MMIOBase + 0x15000);
 	*strap = 0x2c006300;
 	strap = (volatile u32 *)(MMIOBase + 0x15010);
 	*strap = 0x03015330;
-	//strap = (volatile u32 *)(MMIOBase + 0x15020);
-	//*strap |= 0x00000040; /* Disable HDA device. */
+	strap = (volatile u32 *)(MMIOBase + 0x15020);
+	*strap = romstrap2 | 0x00000040;
 	strap = (volatile u32 *)(MMIOBase + 0x15030);
 	*strap = 0x00001002;
 	strap = (volatile u32 *)(MMIOBase + 0x15040);
@@ -240,8 +256,9 @@
 	/* BIF switches into normal functional mode. */
 	set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<4 | 1<<5, 1<<5);
 
-	/* NB Revision is A12. */
-	set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9);
+	/* NB Revision is A12 or newer */
+	if (get_nb_rev(nb_dev) >= REV_RS780_A12)
+		set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9);
 
 	/* Restore APC04, APC18, APC24. */
 	pci_write_config32(dev, 0x04, apc04);
@@ -250,6 +267,11 @@
 
 	/* Enable PCIe configuration space. */
 	set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28);
+
+	// restore processor pcie mmio
+	if (is_family10h())
+		wrmsr (0xc0010058, pcie_mmio_save);
+
 	printk(BIOS_INFO, "GC is accessible from now on.\n");
 }
 
@@ -332,18 +354,16 @@
 				       (dev->enabled ? 1 : 0) << 6);
 		if (dev->enabled)
 			rs780_gpp_sb_init(nb_dev, dev, dev_ind);
-		disable_pcie_bar3(nb_dev);
 		break;
 	case 9:		/* bus 0, dev 9,10, GPP */
 	case 10:
 		printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n",
 			    dev->enabled);
-		enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
 				       (dev->enabled ? 0 : 1) << (7 + dev_ind));
 		if (dev->enabled)
 			rs780_gpp_sb_init(nb_dev, dev, dev_ind);
-		/* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */
+		if (dev_ind == 10) disable_pcie_bar3(nb_dev);
 		break;
 	default:
 		printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
Index: src/southbridge/amd/rs780/rs780.h
===================================================================
--- src/southbridge/amd/rs780/rs780.h	(revision 6011)
+++ src/southbridge/amd/rs780/rs780.h	(working copy)
@@ -208,4 +208,9 @@
 void config_gpp_core(device_t nb_dev, device_t sb_dev);
 void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
 u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
+u32 extractbit(u32 data, int bit_number);
+u32 extractbits(u32 source, int lsb, int msb);
+int cpuidFamily(void);
+int is_family0Fh(void);
+int is_family10h(void);
 #endif				/* RS780_H */
Index: src/southbridge/amd/rs780/rs780_cmn.c
===================================================================
--- src/southbridge/amd/rs780/rs780_cmn.c	(revision 6011)
+++ src/southbridge/amd/rs780/rs780_cmn.c	(working copy)
@@ -29,6 +29,7 @@
 #include <cpu/amd/mtrr.h>
 #include <boot/coreboot_tables.h>
 #include <delay.h>
+#include <cpu/cpu.h>
 #include "rs780.h"
 
 static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
@@ -223,7 +224,7 @@
 		pci_write_config32(k8_f1, 0xbc, 0);
 		pci_write_config32(k8_f1, 0xb0, 0);
 		pci_write_config32(k8_f1, 0xb4, 0);
-	}
+	}
 }
 
 void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
@@ -361,3 +362,42 @@
 	pci_write_config32(nb_dev, 0x90, uma_memory_base);
 	//nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
 }
+
+// extract single bit
+u32 extractbit(u32 data, int bit_number)
+{
+	return (data >> bit_number) & 1;
+}
+
+// extract bit field
+u32 extractbits(u32 source, int lsb, int msb)
+{
+	int field_width = msb - lsb + 1;
+	u32 mask = 0xFFFFFFFF >> (32 - field_width);
+	return (source >> lsb) & mask;
+}
+
+// return AMD cpuid family
+int cpuidFamily(void)
+{
+	u32 baseFamily, extendedFamily, fms;
+	
+	fms = cpuid_eax (1);
+	baseFamily = extractbits (fms, 8, 11);
+	extendedFamily = extractbits (fms, 20, 27);
+	return baseFamily + extendedFamily;
+}
+
+
+// return non-zero for AMD family 0Fh processor found
+int is_family0Fh(void)
+{
+	return cpuidFamily() == 0x0F;
+}
+
+
+// return non-zero for AMD family 10h processor found
+int is_family10h(void)
+{
+	return cpuidFamily() == 0x10;
+}
Index: src/southbridge/amd/rs780/rs780_early_setup.c
===================================================================
--- src/southbridge/amd/rs780/rs780_early_setup.c	(revision 6011)
+++ src/southbridge/amd/rs780/rs780_early_setup.c	(working copy)
@@ -485,7 +485,7 @@
 
 	/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
 	 * force this BAR as mem type in rs780_gfx.c */
-	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
+	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x06);
 }
 
 static void rs780_por_mc_index_init(device_t nb_dev)
Index: src/southbridge/amd/rs780/rs780_gfx.c
===================================================================
--- src/southbridge/amd/rs780/rs780_gfx.c	(revision 6011)
+++ src/southbridge/amd/rs780/rs780_gfx.c	(working copy)
@@ -39,6 +39,8 @@
 void set_pcie_reset(void);
 void set_pcie_dereset(void);
 
+extern uint64_t uma_memory_base, uma_memory_size;
+
 /* Trust the original resource allocation. Don't do it again. */
 #undef DONT_TRUST_RESOURCE_ALLOCATION
 //#define DONT_TRUST_RESOURCE_ALLOCATION
@@ -304,11 +306,15 @@
 	volatile u32 * pointer;
 	int i;
 	u16 command;
-	u32 value, sblk;
+	u32 value;
 	u16 deviceid, vendorid;
 	device_t nb_dev = dev_find_slot(0, 0);
 	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
 	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	static u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32};
+	static u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0};
+	static u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200};
+	static u16 memclk_lookup_fam10 [] = {200, 266, 333, 400, 533, 667, 800, 800};
 
 	/* We definetely will use this in future. Just leave it here. */
 	/*struct southbridge_amd_rs780_config *cfg =
@@ -339,6 +345,8 @@
 	*(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8);
 	*(GpuF0MMReg + 0x2c04/4) = ((value&0xff00)<<8);
 	*(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16);
+	*(GpuF0MMReg + 0xF774/4) = 0xffffffff;
+	*(GpuF0MMReg + 0xF770/4) = 0x00000001;
 	*(GpuF0MMReg + 0x2000/4) = 0x00000011;
 	*(GpuF0MMReg + 0x200c/4) = 0x00000020;
 	*(GpuF0MMReg + 0x2010/4) = 0x10204810;
@@ -352,21 +360,26 @@
 	*(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4);
 	/* Force allow LDT_STOP Cool'n'Quiet workaround. */
 	*(GpuF0MMReg + 0x655c/4) |= 1<<4;
+
+	// disable write combining, needed for stability
+	*(GpuF0MMReg + 0x2000/4) = 0x00000010;
+	*(GpuF0MMReg + 0x2408/4) = 1 << 9;
+	*(GpuF0MMReg + 0x2000/4) = 0x00000011;
+
 	/* GFX_InitFBAccess finished. */
 
+#if (CONFIG_GFXUMA == 1) /* for UMA mode. */
 	/* GFX_StartMC. */
-#if (CONFIG_GFXUMA == 1) /* for UMA mode. */
-	/* MC_INIT_COMPLETE. */
-	set_nbmc_enable_bits(nb_dev, 0x2, 0, 1<<31);
-	/* MC_STARTUP, MC_POWERED_UP and MC_VMODE.*/
-	set_nbmc_enable_bits(nb_dev, 0x1, 1<<18, 1|1<<2);
-
-	set_nbmc_enable_bits(nb_dev, 0xb1, 0, 1<<6);
-	set_nbmc_enable_bits(nb_dev, 0xc3, 0, 1);
-	nbmc_write_index(nb_dev, 0x07, 0x18);
-	nbmc_write_index(nb_dev, 0x06, 0x00000102);
-	nbmc_write_index(nb_dev, 0x09, 0x40000008);
-	set_nbmc_enable_bits(nb_dev, 0x6, 0, 1<<31);
+	set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000004);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00040000, 0x00000000);
+	set_nbmc_enable_bits(nb_dev, 0xB1, 0xFFFF0000, 0x00000040);
+	set_nbmc_enable_bits(nb_dev, 0xC3, 0x00000000, 0x00000001);
+	set_nbmc_enable_bits(nb_dev, 0x07, 0xFFFFFFFF, 0x00000018);
+	set_nbmc_enable_bits(nb_dev, 0x06, 0xFFFFFFFF, 0x00000102);
+	set_nbmc_enable_bits(nb_dev, 0x09, 0xFFFFFFFF, 0x40000008);
+	set_nbmc_enable_bits(nb_dev, 0x06, 0x00000000, 0x80000000);
 	/* GFX_StartMC finished. */
 #else
 	/* for SP mode. */
@@ -418,77 +431,110 @@
 	vgainfo.sHeader.ucTableContentRevision = 2;
 
 #if (CONFIG_GFXUMA == 0) /* SP mode. */
+	// Side port support is incomplete, do not use it
+	// These parameters must match the motherboard
 	vgainfo.ulBootUpSidePortClock = 667*100;
-	vgainfo.ucMemoryType = 3;
+	vgainfo.ucMemoryType = 3;  // 3=ddr3 sp mem, 2=ddr2 sp mem
 	vgainfo.ulMinSidePortClock = 333*100;
 #endif
 
-	vgainfo.ulBootUpEngineClock = 500 * 100; /* set boot up GFX engine clock. */
-	vgainfo.ulReserved1[0] = 0;	vgainfo.ulReserved1[1] = 0;
-	value = pci_read_config32(k8_f2, 0x94);
-	printk(BIOS_DEBUG, "MEMCLK = %x\n", value&0x7);
-	vgainfo.ulBootUpUMAClock = 333 * 100; /* set boot up UMA memory clock. */
-	vgainfo.ulBootUpSidePortClock = 0; /* disable SP. */
-	vgainfo.ulMinSidePortClock = 0; /* disable SP. */
-	for(i=0; i<6; i++)
-		vgainfo.ulReserved2[i] = 0;
-	vgainfo.ulSystemConfig = 0;
-	//vgainfo.ulSystemConfig |= 1<<1 | 1<<3 | 1<<4 | 1<<5 | 1<<6 | 1<<7 | 1;
-	vgainfo.ulBootUpReqDisplayVector = 0; //?
-	vgainfo.ulOtherDisplayMisc = 0; //?
-	vgainfo.ulDDISlot1Config = 0x000c0011; //0; //VGA
-	//vgainfo.ulDDISlot1Config = 0x000c00FF; //0; //HDMI
-	vgainfo.ulDDISlot2Config = 0x00130022; //0; //?
-	vgainfo.ucMemoryType = 2;
-	/* UMA Channel Number: 1 or 2. */
-	vgainfo.ucUMAChannelNumber = 2;
-	vgainfo.ucDockingPinBit = 0; //?
-	vgainfo.ucDockingPinPolarity = 0; //?
-	vgainfo.ulDockingPinCFGInfo = 0; //?
-	vgainfo.ulCPUCapInfo = 3; /* K8. */
+	vgainfo.ulBootUpEngineClock = 500 * 100;	       	// setup option on reference BIOS, 500 is default
 
-	/* page 5-19 on BDG. */
-	vgainfo.usNumberOfCyclesInPeriod = 0x8019;
-	vgainfo.usMaxNBVoltage = 0x1a;
-	vgainfo.usMinNBVoltage = 0;
-	vgainfo.usBootUpNBVoltage = 0x1a;
+	// find the DDR memory frequency
+	if (is_family10h()) {
+		value = pci_read_config32(k8_f2, 0x94);		// read channel 0 DRAM Configuration High Register
+		if (extractbit(value, 14))			// if channel 0 disabled, channel 1 must have memory
+			value = pci_read_config32(k8_f2, 0x194);// read channel 1 DRAM Configuration High Register
+		vgainfo.ulBootUpUMAClock = memclk_lookup_fam10 [extractbits (value, 0, 2)] * 100;
+	}
+	if (is_family0Fh()) {
+		value = pci_read_config32(k8_f2, 0x94);
+		vgainfo.ulBootUpUMAClock = memclk_lookup_fam0F [extractbits (value, 20, 22)] * 100;
+	}
 
-	/* Get SBLink value (HyperTransport I/O Hub Link ID). */
-	value = pci_read_config32(k8_f0, 0x64);
-	sblk = (value >> 8) & 0x3;
-	printk(BIOS_DEBUG, "SBLINK = %d.\n", sblk);
+	/* UMA Channel Number: 1 or 2. */
+	vgainfo.ucUMAChannelNumber = 1;
+	if (is_family0Fh()) {
+		value = pci_read_config32(k8_f2, 0x90);
+	if (extractbit(value, 11))  // 128-bit mode
+		vgainfo.ucUMAChannelNumber = 2;
+	}
+	if (is_family10h()) {
+		u32 dch0 = pci_read_config32(k8_f2, 0x94);
+		u32 dch1 = pci_read_config32(k8_f2, 0x194);
+		if (extractbit(dch0, 14) == 0 && extractbit(dch1, 14) == 0) { // both channels enabled
+			value = pci_read_config32(k8_f2, 0x110);
+			if (extractbit(value, 4))  // ganged mode
+			vgainfo.ucUMAChannelNumber = 2;
+		}
+	}
+      
+	// processor type
+	if (is_family0Fh())
+		vgainfo.ulCPUCapInfo = 3;
+	if (is_family10h())
+		vgainfo.ulCPUCapInfo = 2;
 
 	/* HT speed */
-	value = pci_read_config32(nb_dev, 0xd0);
-	printk(BIOS_DEBUG, "NB HT speed = %x.\n", value);
-	value = pci_read_config32(k8_f0, 0x88 + (sblk * 0x20));
-	printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value);
-	vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */
+	value = pci_read_config8(nb_dev, 0xd1);
+	value = ht_freq_lookup [value] * 100;  // HT link frequency in MHz
+	vgainfo.ulHTLinkFreq = value * 100;    // HT frequency in units of 100 MHz
+	vgainfo.ulHighVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
+	vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
 
+	if (value <= 1800)
+		vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
+	else {
+		int sblink, cpuLnkFreqCap, nbLnkFreqCap;
+		value = pci_read_config32(k8_f0, 0x64);
+		sblink = extractbits(value, 8, 10);
+		cpuLnkFreqCap = pci_read_config16(k8_f0, 0x8a + sblink * 0x20);
+		nbLnkFreqCap = pci_read_config16(nb_dev, 0xd2);
+		if (cpuLnkFreqCap & nbLnkFreqCap & (1 << 10)) // if both 1800 MHz capable
+		vgainfo.ulLowVoltageHTLinkFreq = 1800*100;
+	}
+
 	/* HT width. */
-	value = pci_read_config32(nb_dev, 0xc8);
-	printk(BIOS_DEBUG, "HT width = %x.\n", value);
-	vgainfo.usMinHTLinkWidth = 16;
-	vgainfo.usMaxHTLinkWidth = 16;
-	vgainfo.usUMASyncStartDelay = 322;
-	vgainfo.usUMADataReturnTime = 86;
-	vgainfo.usLinkStatusZeroTime = 0x00c8; //0; //?
-	vgainfo.usReserved = 0;
-	vgainfo.ulHighVoltageHTLinkFreq = 100 * 100;
-	vgainfo.ulLowVoltageHTLinkFreq = 100 * 100;
-	vgainfo.usMaxUpStreamHTLinkWidth = 16;
-	vgainfo.usMaxDownStreamHTLinkWidth = 16;
-	vgainfo.usMinUpStreamHTLinkWidth = 16;
-	vgainfo.usMinDownStreamHTLinkWidth = 16;
-	for(i=0; i<97; i++)
-		vgainfo.ulReserved3[i] = 0;
+	value = pci_read_config8(nb_dev, 0xcb);
+	vgainfo.usMinDownStreamHTLinkWidth = 
+	vgainfo.usMaxDownStreamHTLinkWidth = 
+	vgainfo.usMinUpStreamHTLinkWidth = 
+	vgainfo.usMaxUpStreamHTLinkWidth =
+	vgainfo.usMinHTLinkWidth =
+	vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)];
 
+	if (is_family0Fh()) {
+		vgainfo.usUMASyncStartDelay = 322;
+		vgainfo.usUMADataReturnTime = 286;
+	}
+
+	if (is_family10h()) {
+		static u16 t0mult_lookup [] = {10, 50, 200, 2000};
+		int t0time, t0scale;
+		value = pci_read_config32(k8_f0, 0x16c);
+		t0time = extractbits(value, 0, 3);
+		t0scale = extractbits(value, 4, 5);
+		vgainfo.usLinkStatusZeroTime = t0mult_lookup [t0scale] * t0time;
+		vgainfo.usUMASyncStartDelay = 100;
+		if (vgainfo.ulHTLinkFreq < 1000 * 100) { // less than 1000 MHz
+			vgainfo.usUMADataReturnTime = 300;
+			vgainfo.usLinkStatusZeroTime = 6 * 100;   // 6us for GH in HT1 mode
+		}
+		else {
+			int lssel;
+			value = pci_read_config32(nb_dev, 0xac);
+			lssel = extractbits (value, 7, 8);
+			vgainfo.usUMADataReturnTime = 1300;
+			if (lssel == 0) vgainfo.usUMADataReturnTime = 150;
+		}
+	}
+
 	/* Transfer the Table to VBIOS. */
 	pointer = (u32 *)&vgainfo;
 	for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
 	{
 #if (CONFIG_GFXUMA == 1)
-		*GpuF0MMReg = 0x80000000 + 0x10000000 - 512 + i;
+		*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
 #else
 		*GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
 #endif
@@ -584,7 +630,6 @@
 * Set registers in RS780 and CPU to enable the internal GFX.
 * Please refer to CIM source code and BKDG.
 */
-extern uint64_t uma_memory_base, uma_memory_size;
 
 static void rs780_internal_gfx_enable(device_t dev)
 {
@@ -637,7 +682,9 @@
 #if (CONFIG_GFXUMA == 1)
 	/* GFX_InitUMA. */
 	/* Copy CPU DDR Controller to NB MC. */
+	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
 	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
 	for (i = 0; i < 12; i++)
 	{
 		l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
@@ -646,24 +693,40 @@
 
 	l_dword = pci_read_config32(k8_f2, 0x80);
 	nbmc_write_index(nb_dev, 0x3c, l_dword);
-
 	l_dword = pci_read_config32(k8_f2, 0x94);
-	if(l_dword & (1<<22))
-		set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<16);
-	else
-		set_nbmc_enable_bits(nb_dev, 0x3c, 1<<16, 0);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<22))<<16);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
+	l_dword = pci_read_config32(k8_f2, 0x90);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
+   if (is_family10h())
+   {
+	   for (i = 0; i < 12; i++)
+	   {
+		   l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
+		   nbmc_write_index(nb_dev, 0x3d + i, l_dword);
+	   }
 
-	if(l_dword & (1<<8))
-		set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<17);
-	else
-		set_nbmc_enable_bits(nb_dev, 0x3c, 1<<17, 0);
+	   l_dword = pci_read_config32(k8_f2, 0x180);
+	   nbmc_write_index(nb_dev, 0x49, l_dword);
+	   l_dword = pci_read_config32(k8_f2, 0x194);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<22))<<16);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<< 8))<<17);
+	   l_dword = pci_read_config32(k8_f2, 0x190);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<10))<<18);
 
-	l_dword = pci_read_config32(k8_f2, 0x90);
-	if(l_dword & (1<<10))
-		set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<18);
-	else
-		set_nbmc_enable_bits(nb_dev, 0x3c, 1<<18, 0);
+	   l_dword = pci_read_config32(k8_f2, 0x110);
+	   nbmc_write_index(nb_dev, 0x4a, l_dword);
+	   l_dword = pci_read_config32(k8_f2, 0x114);
+	   nbmc_write_index(nb_dev, 0x4b, l_dword);
+	   l_dword = pci_read_config32(k8_f4, 0x44);
+	   set_nbmc_enable_bits(nb_dev, 0x4a, 0, !!(l_dword & (1<<22))<<24);
+	   l_dword = pci_read_config32(k8_f1, 0x40);
+	   nbmc_write_index(nb_dev, 0x4c, l_dword);
+	   l_dword = pci_read_config32(k8_f1, 0xf0);
+	   nbmc_write_index(nb_dev, 0x4d, l_dword);
+   }
 
+
 	/* Set UMA in the 780 side. */
 	/* UMA start address, size. */
 	/* The UMA starts at 0xC0000000 of internal RS780 address space
@@ -672,7 +735,7 @@
 	nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000);
 	nbmc_write_index(nb_dev, 0x11, uma_memory_base);
 	nbmc_write_index(nb_dev, 0x12, 0);
-	nbmc_write_index(nb_dev, 0xf0, 256);
+	nbmc_write_index(nb_dev, 0xf0, uma_memory_size >> 20);
 	/* GFX_InitUMA finished. */
 #else
 	/* GFX_InitSP. */
@@ -1016,7 +1079,7 @@
 	/* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX
 	 * REFCLK PAD can be driven by an external source. */
 	/* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */
-	set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 0 << 29 | 1 << 28);
+	set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28 | 1 << 26, 1 << 28);
 
 	/* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
 	/* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
Index: src/southbridge/amd/rs780/rs780_pcie.c
===================================================================
--- src/southbridge/amd/rs780/rs780_pcie.c	(revision 6011)
+++ src/southbridge/amd/rs780/rs780_pcie.c	(working copy)
@@ -221,6 +221,7 @@
 	printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
 	pci_write_config32(nb_dev, 0x1C, 0);	/* clear BAR3 address */
 	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3. */
+	set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 0);	/* disable bar3 decode */
 	ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
 }

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From njacobs8 at hetnet.nl  Mon Nov  1 20:44:25 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Mon, 1 Nov 2010 20:44:25 +0100
Subject: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch
In-Reply-To: <20101015165953.GG3256@greenwood>
References: <201010132251.42246.njacobs8@hetnet.nl>
	<201010151610.27048.njacobs8@hetnet.nl>
	<20101015165953.GG3256@greenwood>
Message-ID: <201011012044.26096.njacobs8@hetnet.nl>

Hi Uwe,
It seems i forgot to answer this question from you:
> Can you update any wiki instructions wrt to VSA which may be out of
> date, and or shall we upload a known-good blob to the wiki?
I think the wiki only mentions the LX vsa witch is not usable for GX2 boards.
I rather not distribute my vsa at the moment because i don't know yet if it is 
completely working.
I used softvga in my vsa but it seems not to work yet.
If i don't get it working i might remove it again and i think it is not good 
to have different expirimental/broken vsa blobs on the internet floating around.

When i finish my GX2 updating i will send a patch to update gplvsa to make both 
LX and GX2 blobs and supply the working result blob.

Thanks, Nils.



From dhendrix at google.com  Mon Nov  1 21:02:53 2010
From: dhendrix at google.com (David Hendricks)
Date: Mon, 1 Nov 2010 13:02:53 -0700
Subject: [coreboot] [superiotool] patch for fintek f71889fg
Message-ID: <AANLkTi=KZohJ9RPtm8D7hFNfJ7BiVwEGO0t=POKjcF4M@mail.gmail.com>

The patch (attached) was tested by a user on IRC who had the F71889FG. I
wrote it using documentation from Fintek's website available here:
http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf

This patch also seems to work for the F71889ED, which uses 0x09 and 0x09 for
chip ID bytes 1 & 2. However, I have not been able to find documentation to
verify that the two chips are identical from superiotool's perspective.

The F71889 seems popular on current generation platforms with AMD chipsets,
in case there are folks looking to try it on a presently unsupported
board...

Signed-off-by: David Hendricks <dhendrix at google.com>

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From neotheuser at ymail.com  Mon Nov  1 22:05:26 2010
From: neotheuser at ymail.com (Neo The User)
Date: Mon, 1 Nov 2010 14:05:26 -0700 (PDT)
Subject: [coreboot] Fw: Re: [superiotool] patch for fintek f71889fg
Message-ID: <38062.13913.qm@web114110.mail.gq1.yahoo.com>


--- On Mon, 11/1/10, Neo The User <neotheuser at ymail.com> wrote:

From: Neo The User <neotheuser at ymail.com>
Subject: Re: [superiotool] patch for fintek f71889fg
To: "David Hendricks" <dhendrix at google.com>
Date: Monday, November 1, 2010, 9:04 PM

Works and tested on f71889fg super IO (motherboard MS785GT-E63)

-Alec Ari


--- On Mon, 11/1/10, David Hendricks <dhendrix at google.com> wrote:

From: David Hendricks <dhendrix at google.com>
Subject: [superiotool] patch for fintek f71889fg
To: "Coreboot" <coreboot at coreboot.org>
Cc: neotheuser at ymail.com
Date: Monday, November 1, 2010, 8:02 PM

The patch (attached) was tested by a user on IRC who had the F71889FG. I wrote it using documentation from Fintek's website available here:?http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf


This patch also seems to work for the F71889ED, which uses 0x09 and 0x09 for chip ID bytes 1 & 2. However, I have not been able to find documentation to verify that the two chips are identical from superiotool's perspective.



The F71889 seems popular on current generation platforms with AMD chipsets, in case there are folks looking to try it on a presently unsupported board...
Signed-off-by: David Hendricks <dhendrix at google.com>


-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.





      


      
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From peter at stuge.se  Mon Nov  1 23:01:41 2010
From: peter at stuge.se (Peter Stuge)
Date: Mon, 1 Nov 2010 23:01:41 +0100
Subject: [coreboot] [PATCH] don't print too early on mcp55-based boards
In-Reply-To: <20101101160338.GA28294@countzero.vandewege.net>
References: <20101101160338.GA28294@countzero.vandewege.net>
Message-ID: <20101101220141.592.qmail@stuge.se>

Ward Vandewege wrote:
> See attached. Perhaps we should also print a post code if the SMBus
> controller can't be found - suggestions for a value?

0x5B ?


> We can't print this early.
> 
> This patch fixes a hang on 
> 
>   supermicro/h8dme
>   supermicro/h8dmr
>   supermicro/h8dmr_fam10
> 
> and possibly on other mcp55-based boards.
> 
> Signed-off-by: Ward Vandewege <ward at gnu.org>

Acked-by: Peter Stuge <peter at stuge.se>



From dustin.harrison at sutus.com  Tue Nov  2 02:17:11 2010
From: dustin.harrison at sutus.com (Dustin Harrison)
Date: Mon, 01 Nov 2010 18:17:11 -0700
Subject: [coreboot] Trouble converting Truxton to CAR
Message-ID: <4CCF6697.6040305@sutus.com>

Hello,

After all the excitement of converting the i810 boards to CAR, I've been 
looking at converting the Truxton board to cache-as-RAM.  However, I'm 
not sure how to validate that the cpu/intel/car/cache_as_ram.inc code is 
valid for an Intel EP80579.  Is there a way I can validate that this CPU 
will work with the existing CAR code?

I've gone so far as doing a code-n-pray conversion, but my linux boot 
hangs at "Jumping to Entry" and running memtest causes it to bork on 
Test #2 with an unhandled interrupt.

Cheers
Dustin



From patrick at georgi-clan.de  Tue Nov  2 08:43:50 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 02 Nov 2010 08:43:50 +0100
Subject: [coreboot] Trouble converting Truxton to CAR
In-Reply-To: <4CCF6697.6040305@sutus.com>
References: <4CCF6697.6040305@sutus.com>
Message-ID: <4CCFC136.3020509@georgi-clan.de>

Am 02.11.2010 02:17, schrieb Dustin Harrison:
> valid for an Intel EP80579.  Is there a way I can validate that this CPU
> will work with the existing CAR code?
> 
> I've gone so far as doing a code-n-pray conversion, but my linux boot
> hangs at "Jumping to Entry" and running memtest causes it to bork on
> Test #2 with an unhandled interrupt.
That's already _very_ far as much as CAR is concerned. Usually, if CAR
fails, you either see nothing but a couple of post codes, or have the
system fail when decompressing ramstage at the latest (because RAM init
failed for some reason).


Patrick



From joe at settoplinux.org  Tue Nov  2 17:54:23 2010
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 02 Nov 2010 12:54:23 -0400
Subject: [coreboot] Trouble converting Truxton to CAR
In-Reply-To: <4CCFC136.3020509@georgi-clan.de>
References: <4CCF6697.6040305@sutus.com> <4CCFC136.3020509@georgi-clan.de>
Message-ID: <a6c38b270e623262bae3c567ae0964ea@imap.1and1.com>



On Tue, 02 Nov 2010 08:43:50 +0100, Patrick Georgi <patrick at georgi-clan.de>
wrote:
> Am 02.11.2010 02:17, schrieb Dustin Harrison:
>> valid for an Intel EP80579.  Is there a way I can validate that this CPU
>> will work with the existing CAR code?
>>
>> I've gone so far as doing a code-n-pray conversion, but my linux boot
>> hangs at "Jumping to Entry" and running memtest causes it to bork on
>> Test #2 with an unhandled interrupt.
> That's already _very_ far as much as CAR is concerned. Usually, if CAR
> fails, you either see nothing but a couple of post codes, or have the
> system fail when decompressing ramstage at the latest (because RAM init
> failed for some reason).
> 
> 
Yes, sounds to me more like a raminit issue more than a CAR issue.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From dustin.harrison at sutus.com  Tue Nov  2 18:43:08 2010
From: dustin.harrison at sutus.com (Dustin Harrison)
Date: Tue, 02 Nov 2010 10:43:08 -0700
Subject: [coreboot] Trouble converting Truxton to CAR
In-Reply-To: <a6c38b270e623262bae3c567ae0964ea@imap.1and1.com>
References: <4CCF6697.6040305@sutus.com> <4CCFC136.3020509@georgi-clan.de>
	<a6c38b270e623262bae3c567ae0964ea@imap.1and1.com>
Message-ID: <4CD04DAC.6000003@sutus.com>



On 02/11/2010 9:54 AM, Joseph Smith wrote:
>
> On Tue, 02 Nov 2010 08:43:50 +0100, Patrick Georgi<patrick at georgi-clan.de>
> wrote:
>> Am 02.11.2010 02:17, schrieb Dustin Harrison:
>>> valid for an Intel EP80579.  Is there a way I can validate that this CPU
>>> will work with the existing CAR code?
>>>
>>> I've gone so far as doing a code-n-pray conversion, but my linux boot
>>> hangs at "Jumping to Entry" and running memtest causes it to bork on
>>> Test #2 with an unhandled interrupt.
>> That's already _very_ far as much as CAR is concerned. Usually, if CAR
>> fails, you either see nothing but a couple of post codes, or have the
>> system fail when decompressing ramstage at the latest (because RAM init
>> failed for some reason).
>>
>>
> Yes, sounds to me more like a raminit issue more than a CAR issue.
>
Indeed, I enabled the ramtest and see failures starting at 0xCFE14 which 
is inside the CAR space (DCACHE_RAM_SIZE is 0x8000 in my case which 
should make the CAR range 0xC8000-0xCFFFF).  My (naive) ideas are that 
either writes are getting sent to the SDRAM which prevents the raminit 
code from working or that CAR is not being (successfully) disabled after 
raminit due to some unique feature of this CPU.  The reason I was asking 
about a method for validating the CAR code for this CPU is because this 
CPU supports a feature to share memory (for DMA purposes) with an 
accelerated services unit (ASU).  Thus I jumped to the conclusion that 
this may affect the CAR routines.



From uwe at hermann-uwe.de  Tue Nov  2 20:45:53 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 2 Nov 2010 20:45:53 +0100
Subject: [coreboot] [superiotool] patch for fintek f71889fg
In-Reply-To: <AANLkTi=KZohJ9RPtm8D7hFNfJ7BiVwEGO0t=POKjcF4M@mail.gmail.com>
References: <AANLkTi=KZohJ9RPtm8D7hFNfJ7BiVwEGO0t=POKjcF4M@mail.gmail.com>
Message-ID: <20101102194552.GL3256@greenwood>

Hi,

On Mon, Nov 01, 2010 at 01:02:53PM -0700, David Hendricks wrote:
> The patch (attached) was tested by a user on IRC who had the F71889FG. I
> wrote it using documentation from Fintek's website available here:
> http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf
> 
> This patch also seems to work for the F71889ED, which uses 0x09 and 0x09 for

Both times 0x09? Or is this a typo?


> chip ID bytes 1 & 2. However, I have not been able to find documentation to
> verify that the two chips are identical from superiotool's perspective.
> 
> The F71889 seems popular on current generation platforms with AMD chipsets,
> in case there are folks looking to try it on a presently unsupported
> board...
> 
> Signed-off-by: David Hendricks <dhendrix at google.com>

Are you sure this is the correct patch? It doesn't seem to match the
datasheet in a number of places, e.g. 0x20 and 0x21 (IDs) are incorrect
in NOLDN (as well as most other values in NOLDN), some registers are missing
completely, some LDNs are missing completely etc.

Is this for another Super I/O, or remainders of copying another table?


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Tue Nov  2 21:54:38 2010
From: svn at coreboot.org (repository service)
Date: Tue, 02 Nov 2010 21:54:38 +0100
Subject: [coreboot] [commit] r6012 - in trunk/src: include/device
	southbridge/via/k8t890 southbridge/via/vt8237r
Message-ID: <E1PDNsM-0005HY-Fh@ra.coresystems.de>

Author: ruik
Date: Tue Nov  2 21:54:37 2010
New Revision: 6012
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6012

Log:
This adds pci device ids and pci_driver structs for the K8T890 CF
variant. It also adds additional dev_find_device calls in k8t890_ctrl.c for
subfunctions 3 and 7.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Modified:
   trunk/src/include/device/pci_ids.h
   trunk/src/southbridge/via/k8t890/k8t890_ctrl.c
   trunk/src/southbridge/via/k8t890/k8t890_dram.c
   trunk/src/southbridge/via/k8t890/k8t890_error.c
   trunk/src/southbridge/via/k8t890/k8t890_host.c
   trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
   trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c

Modified: trunk/src/include/device/pci_ids.h
==============================================================================
--- trunk/src/include/device/pci_ids.h	Mon Nov  1 16:20:27 2010	(r6011)
+++ trunk/src/include/device/pci_ids.h	Tue Nov  2 21:54:37 2010	(r6012)
@@ -1204,6 +1204,13 @@
 #define PCI_DEVICE_ID_VIA_K8T890CE_4	0x4238
 #define PCI_DEVICE_ID_VIA_K8T890CE_5	0x5238
 #define PCI_DEVICE_ID_VIA_K8T890CE_7	0x7238
+#define PCI_DEVICE_ID_VIA_K8T890CF_0	0x0351
+#define PCI_DEVICE_ID_VIA_K8T890CF_1	0x1351
+#define PCI_DEVICE_ID_VIA_K8T890CF_2	0x2351
+#define PCI_DEVICE_ID_VIA_K8T890CF_3	0x3351
+#define PCI_DEVICE_ID_VIA_K8T890CF_4	0x4351
+#define PCI_DEVICE_ID_VIA_K8T890CF_5	0x5351
+#define PCI_DEVICE_ID_VIA_K8T890CF_7	0x7351
 #define PCI_DEVICE_ID_VIA_K8M890CE_0	0x0336
 #define PCI_DEVICE_ID_VIA_K8M890CE_1	0x1336
 #define PCI_DEVICE_ID_VIA_K8M890CE_2	0x2336

Modified: trunk/src/southbridge/via/k8t890/k8t890_ctrl.c
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890_ctrl.c	Mon Nov  1 16:20:27 2010	(r6011)
+++ trunk/src/southbridge/via/k8t890/k8t890_ctrl.c	Tue Nov  2 21:54:37 2010	(r6012)
@@ -36,8 +36,12 @@
 	devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
 					   PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
 
-		if (!devfun3)
-			devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+	if (!devfun3)
+		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+					   PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
+
+	if (!devfun3)
+		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
 					   PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
 
 	pci_write_config8(dev, 0x70, 0xc2);
@@ -175,6 +179,12 @@
 	.device	= PCI_DEVICE_ID_VIA_K8T890CE_7,
 };
 
+static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+	.ops	= &ctrl_ops,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_K8T890CF_7,
+};
+
 static const struct pci_driver northbridge_driver_m __pci_driver = {
 	.ops	= &ctrl_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,

Modified: trunk/src/southbridge/via/k8t890/k8t890_dram.c
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890_dram.c	Mon Nov  1 16:20:27 2010	(r6011)
+++ trunk/src/southbridge/via/k8t890/k8t890_dram.c	Tue Nov  2 21:54:37 2010	(r6012)
@@ -170,6 +170,12 @@
 	.device	= PCI_DEVICE_ID_VIA_K8T890CE_3,
 };
 
+static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+	.ops	= &dram_ops_t,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_K8T890CF_3,
+};
+
 static const struct pci_driver northbridge_driver_m __pci_driver = {
 	.ops	= &dram_ops_m,
 	.vendor	= PCI_VENDOR_ID_VIA,

Modified: trunk/src/southbridge/via/k8t890/k8t890_error.c
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890_error.c	Mon Nov  1 16:20:27 2010	(r6011)
+++ trunk/src/southbridge/via/k8t890/k8t890_error.c	Tue Nov  2 21:54:37 2010	(r6012)
@@ -48,6 +48,12 @@
 	.device	= PCI_DEVICE_ID_VIA_K8T890CE_1,
 };
 
+static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+	.ops	= &error_ops,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_K8T890CF_1,
+};
+
 static const struct pci_driver northbridge_driver_m __pci_driver = {
 	.ops	= &error_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,

Modified: trunk/src/southbridge/via/k8t890/k8t890_host.c
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890_host.c	Mon Nov  1 16:20:27 2010	(r6011)
+++ trunk/src/southbridge/via/k8t890/k8t890_host.c	Tue Nov  2 21:54:37 2010	(r6012)
@@ -76,6 +76,12 @@
 	.device	= PCI_DEVICE_ID_VIA_K8T890CE_0,
 };
 
+static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+	.ops	= &host_ops_t,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_K8T890CF_0,
+};
+
 static const struct pci_driver northbridge_driver_m __pci_driver = {
 	.ops	= &host_ops_m,
 	.vendor	= PCI_VENDOR_ID_VIA,

Modified: trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c	Mon Nov  1 16:20:27 2010	(r6011)
+++ trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c	Tue Nov  2 21:54:37 2010	(r6012)
@@ -144,6 +144,12 @@
 	.device	= PCI_DEVICE_ID_VIA_K8T890CE_5,
 };
 
+static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+	.ops	= &traf_ctrl_ops_t,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_K8T890CF_5,
+};
+
 static const struct pci_driver northbridge_driver_m __pci_driver = {
 	.ops	= &traf_ctrl_ops_m,
 	.vendor	= PCI_VENDOR_ID_VIA,

Modified: trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c	Mon Nov  1 16:20:27 2010	(r6011)
+++ trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c	Tue Nov  2 21:54:37 2010	(r6012)
@@ -37,6 +37,9 @@
 		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
 					  PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
 	if (!devfun3)
+		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
+	if (!devfun3)
 		die("Unknown NB");
 
 	/* CPU to PCI Flow Control 1 & 2, just fill in recommended. */
@@ -109,6 +112,9 @@
 	if (!devfun7)
 		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
 					  PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
 	/* No pairing NB was found. */
 	if (!devfun7)
 		return;



From r.marek at assembler.cz  Tue Nov  2 21:55:01 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Nov 2010 21:55:01 +0100
Subject: [coreboot] [PATCH 1/7] ASUS M2V support (v2): K8T890CF device
 ids	(unchanged)
In-Reply-To: <20101029115745.GI31684@yumi.tdiedrich.de>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029115745.GI31684@yumi.tdiedrich.de>
Message-ID: <4CD07AA5.5000605@assembler.cz>

Hi,

Acked-by: Rudolf Marek <r.marek at assembler.cz>

Committed revision 6012.

Thanks,
Rudolf


> ===================================================================
> --- src/southbridge/via/k8t890/k8t890_ctrl.c.orig	2010-10-27 11:34:19.000000000 +0200
> +++ src/southbridge/via/k8t890/k8t890_ctrl.c	2010-10-27 11:42:58.000000000 +0200
> @@ -36,8 +36,12 @@
>   	devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
>   					   PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
>
> -		if (!devfun3)
> -			devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
> +	if (!devfun3)
> +		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
> +					   PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
> +
> +	if (!devfun3)
> +		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
>   					   PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
>
>   	pci_write_config8(dev, 0x70, 0xc2);
> @@ -175,6 +179,12 @@
>   	.device	= PCI_DEVICE_ID_VIA_K8T890CE_7,
>   };
>
> +static const struct pci_driver northbridge_driver_tcf __pci_driver = {
> +	.ops	=&ctrl_ops,
> +	.vendor	= PCI_VENDOR_ID_VIA,
> +	.device	= PCI_DEVICE_ID_VIA_K8T890CF_7,
> +};
> +
>   static const struct pci_driver northbridge_driver_m __pci_driver = {
>   	.ops	=&ctrl_ops,
>   	.vendor	= PCI_VENDOR_ID_VIA,
> Index: src/southbridge/via/vt8237r/vt8237_ctrl.c
> ===================================================================
> --- src/southbridge/via/vt8237r/vt8237_ctrl.c.orig	2010-10-27 11:34:19.000000000 +0200
> +++ src/southbridge/via/vt8237r/vt8237_ctrl.c	2010-10-27 11:48:47.000000000 +0200
> @@ -37,6 +37,9 @@
>   		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
>   					  PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
>   	if (!devfun3)
> +		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
> +					  PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
> +	if (!devfun3)
>   		die("Unknown NB");
>
>   	/* CPU to PCI Flow Control 1&  2, just fill in recommended. */
> @@ -109,6 +112,9 @@
>   	if (!devfun7)
>   		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
>   					  PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
> +	if (!devfun7)
> +		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
> +					  PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
>   	/* No pairing NB was found. */
>   	if (!devfun7)
>   		return;
> Index: src/include/device/pci_ids.h
> ===================================================================
> --- src/include/device/pci_ids.h.orig	2010-10-27 11:34:19.000000000 +0200
> +++ src/include/device/pci_ids.h	2010-10-27 11:40:16.000000000 +0200
> @@ -1204,6 +1204,13 @@
>   #define PCI_DEVICE_ID_VIA_K8T890CE_4	0x4238
>   #define PCI_DEVICE_ID_VIA_K8T890CE_5	0x5238
>   #define PCI_DEVICE_ID_VIA_K8T890CE_7	0x7238
> +#define PCI_DEVICE_ID_VIA_K8T890CF_0	0x0351
> +#define PCI_DEVICE_ID_VIA_K8T890CF_1	0x1351
> +#define PCI_DEVICE_ID_VIA_K8T890CF_2	0x2351
> +#define PCI_DEVICE_ID_VIA_K8T890CF_3	0x3351
> +#define PCI_DEVICE_ID_VIA_K8T890CF_4	0x4351
> +#define PCI_DEVICE_ID_VIA_K8T890CF_5	0x5351
> +#define PCI_DEVICE_ID_VIA_K8T890CF_7	0x7351
>   #define PCI_DEVICE_ID_VIA_K8M890CE_0	0x0336
>   #define PCI_DEVICE_ID_VIA_K8M890CE_1	0x1336
>   #define PCI_DEVICE_ID_VIA_K8M890CE_2	0x2336
>



From r.marek at assembler.cz  Tue Nov  2 22:04:58 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Nov 2010 22:04:58 +0100
Subject: [coreboot] [PATCH 2/7] ASUS M2V support (v2): VT8237A
 LPC	device id	(unchanged)
In-Reply-To: <20101029115838.GJ31684@yumi.tdiedrich.de>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029115838.GJ31684@yumi.tdiedrich.de>
Message-ID: <4CD07CFA.8040500@assembler.cz>

Hi,

I think following is not true. The VT8237A has something else at 0x50, so 
vt8237_sb_enable_fid_vid should not be neccessary to call. Do you call it or 
not? If not then we either need to fix it for the "old" location 0x11 iirc or 
not to put there any test for A version.
>
> +static const struct device_operations vt8237r_lpc_ops_a = {
> +	.read_resources		= vt8237r_read_resources,
> +	.set_resources		= pci_dev_set_resources,
> +	.enable_resources	= pci_dev_enable_resources,
> +	.init			= vt8237r_init,
> +	.scan_bus		= scan_static_bus,
> +};
> +


I think you dont need this for now, if you use "r" init version you can cange it 
directly:


> +static const struct pci_driver lpc_driver_a __pci_driver = {
> +	.ops	=&vt8237r_lpc_ops_a,

_r here.

Thanks,
Rudolf



From r.marek at assembler.cz  Tue Nov  2 22:10:12 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Nov 2010 22:10:12 +0100
Subject: [coreboot] [PATCH 3/7] ASUS M2V support
 (v2):	simplify	vt8237r_early_smbus.c (unchanged)
In-Reply-To: <20101029115945.GK31684@yumi.tdiedrich.de>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029115945.GK31684@yumi.tdiedrich.de>
Message-ID: <4CD07E34.7040002@assembler.cz>

On 29.10.2010 13:59, Tobias Diedrich wrote:
> Instead of duplicating the pci_locate_device calls multiple times,
> add a get_vt8237_lpc() function.

Yeah nice idea! Can I get separate patch for that? In the meanwhile do we need 
to call the enablefidvid for "A" ? I think we dont scritly need that. Maybe we 
can make it part of 2/7 and leave this just for the grand get_vt8237_lpc() 
function? (and I can apply that before 2/7 so you don't need to re-do the stuff)

Thanks,
Rudolf



From r.marek at assembler.cz  Tue Nov  2 22:16:23 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Nov 2010 22:16:23 +0100
Subject: [coreboot] [PATCH 4/7] ASUS M2V support (v2): VT8237A	specific
 initialization
In-Reply-To: <20101029121533.GP31684@yumi.tdiedrich.de>
References: <20101029115628.GH31684@yumi.tdiedrich.de>	<20101029120051.GL31684@yumi.tdiedrich.de>
	<20101029121533.GP31684@yumi.tdiedrich.de>
Message-ID: <4CD07FA7.80306@assembler.cz>

On 29.10.2010 14:15, Tobias Diedrich wrote:
> Hmpf, forgot to compiletest this one and missed the unused pdev,
> fixed.
>
> This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.c
> and vt8237r_lpc.c
>
> Signed-off-by: Tobias Diedrich<ranma+coreboot at tdiedrich.de>
>
> ---
>
> Index: src/southbridge/via/vt8237r/vt8237_ctrl.c
> ===================================================================
> --- src/southbridge/via/vt8237r/vt8237_ctrl.c.orig	2010-10-29 14:05:23.000000000 +0200
> +++ src/southbridge/via/vt8237r/vt8237_ctrl.c	2010-10-29 14:06:09.000000000 +0200
> @@ -168,6 +168,69 @@
>
>   }
>
> +static void vt8237a_vlink_init(struct device *dev)
> +{
> +	u8 reg;
> +	device_t devfun7;
> +
> +	devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
> +				  PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
> +	if (!devfun7)
> +		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
> +					  PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
> +	if (!devfun7)
> +		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
> +					  PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
> +	/* No pairing NB was found. */
> +	if (!devfun7)
> +		return;
> +
> +	/*
> +	 * This init code is valid only for the VT8237A! For different
> +	 * sounthbridges (e.g. VT8237S, VT8237R (without plus R)

typo :) maybe was just copied? Did you get the values from orig bios? Or just 
copied? For what vlink mode it is 8x? I got some VIA recommended values but they 
are bit different 0xb5 is 0x88.

> ===================================================================
> --- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig	2010-10-29 14:05:39.000000000 +0200
> +++ src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-10-29 14:06:27.000000000 +0200
> @@ -319,6 +319,49 @@
>   	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
>   }
>
> +static void vt8237a_init(struct device *dev)

Aha now I see why you need the own struct.


> +{
> +	u32 tmp;
> +
> +	/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
> +	tmp = pci_read_config8(dev, 0x4f);
> +	tmp |= 0x08;
> +	pci_write_config8(dev, 0x4f, tmp);
> +
> +	/*
> +	 * bit2: REQ5 as PCI request input - should be together with INTE-INTH.
> +	 * bit5: usb power control lines as gpio
> +	 */
> +	pci_write_config8(dev, 0xe4, 0x24);
> +	/*
> +	 * Enable APIC wakeup from INTH
> +	 * Enable SATA LED, disable special CPU Frequency Change -
> +	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
> +	 */
> +	pci_write_config8(dev, 0xe5, 0x69);
> +
> +	/* Reduce further the STPCLK/LDTSTP signal to 5us. */
> +	pci_write_config8(dev, 0xec, 0x4);
> +
> +	/* Host Bus Power Management Control, maybe not needed */
> +	pci_write_config8(dev, 0x8c, 0x5);
> +
> +	/* Enable HPET at VT8237R_HPET_ADDR. */
> +	pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
> +
> +	southbridge_init_common(dev);
> +
> +	/* FIXME: Intel needs more bit set for C2/C3. */
> +
> +	/*
> +	 * Allow SLP# signal to assert LDTSTOP_L.
> +	 * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2.

What is fixme fixme pre revA2?

> +	 */
> +	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
> +
> +	dump_south(dev);
> +}
> +
>   static void vt8237s_init(struct device *dev)
>   {
>   	u32 tmp;
> @@ -541,7 +584,7 @@
>   	.read_resources		= vt8237r_read_resources,
>   	.set_resources		= pci_dev_set_resources,
>   	.enable_resources	= pci_dev_enable_resources,
> -	.init			= vt8237r_init,
> +	.init			= vt8237a_init,
>   	.scan_bus		= scan_static_bus,
>   };
>

Otherwise fine.

Thanks,
Rudolf




From svn at coreboot.org  Tue Nov  2 22:24:29 2010
From: svn at coreboot.org (repository service)
Date: Tue, 02 Nov 2010 22:24:29 +0100
Subject: [coreboot] [commit] r6013 - trunk/src/southbridge/via/k8t890
Message-ID: <E1PDOLF-0005QM-Kb@ra.coresystems.de>

Author: ruik
Date: Tue Nov  2 22:24:29 2010
New Revision: 6013
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6013

Log:
Need to clear downstream read cycle retry bit, or the bus scan will
hang.  Also need to set lane config to 0x00 for autonegotiation.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Modified:
   trunk/src/southbridge/via/k8t890/k8t890_pcie.c

Modified: trunk/src/southbridge/via/k8t890/k8t890_pcie.c
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890_pcie.c	Tue Nov  2 21:54:37 2010	(r6012)
+++ trunk/src/southbridge/via/k8t890/k8t890_pcie.c	Tue Nov  2 22:24:29 2010	(r6013)
@@ -35,7 +35,23 @@
 	reg = pci_read_config8(dev, 0x50);
 	pci_write_config8(dev, 0x50, reg | 0x10);
 
-	/* Award has 0xb, VIA recomends 0x4. */
+	/* Disable downstream read cycle retry,
+	 * otherwise the bus scan will hang if no device is plugged in. */
+	reg = pci_read_config8(dev, 0xa3);
+	pci_write_config8(dev, 0xa3, reg & ~0x01);
+
+	/* Use PHY negotiation for lane config */
+	reg = pci_read_config8(dev, 0xc1);
+	pci_write_config8(dev, 0xc1, reg & ~0x1f);
+
+	/* Award has 0xb, VIA recommends 0xd, default 0x8.
+	 * bit4: receive polarity change control
+	 * bits3:2: squelch window select 64~175mv
+	 * bit1: Number of non-idle bits detected before exiting idle state
+	 *       0: 10 bits, 1: 2 bits
+	 * bit0: Number of idle bits detected before entering idle state
+	 *       0: 10 bits, 1: 2 bits
+	 */
 	pci_write_config8(dev, 0xe1, 0xb);
 
 	/*
@@ -75,8 +91,25 @@
 	reg = pci_read_config8(dev, 0x50);
 	pci_write_config8(dev, 0x50, reg | 0x10);
 
-	/* Award has 0xb, VIA recommends 0x4. */
+	/* Disable downstream read cycle retry,
+	 * otherwise the bus scan will hang if no device is plugged in. */
+	reg = pci_read_config8(dev, 0xa3);
+	pci_write_config8(dev, 0xa3, reg & ~0x01);
+
+	/* Use PHY negotiation for lane config */
+	reg = pci_read_config8(dev, 0xc1);
+	pci_write_config8(dev, 0xc1, reg & ~0x1f);
+
+	/* Award has 0xb, VIA recommends 0xd, default 0x8.
+	 * bit4: receive polarity change control
+	 * bits3:2: squelch window select 64~175mv
+	 * bit1: Number of non-idle bits detected before exiting idle state
+	 *       0: 10 bits, 1: 2 bits
+	 * bit0: Number of idle bits detected before entering idle state
+	 *       0: 10 bits, 1: 2 bits
+	 */
 	pci_write_config8(dev, 0xe1, 0xb);
+
 	/* Set replay timer limit. */
 	pci_write_config8(dev, 0xb1, 0xf0);
 



From r.marek at assembler.cz  Tue Nov  2 22:25:45 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Nov 2010 22:25:45 +0100
Subject: [coreboot] [PATCH 5/7] ASUS M2V support (v2): K8T890 PCIe bugfix
In-Reply-To: <20101029120149.GM31684@yumi.tdiedrich.de>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029120149.GM31684@yumi.tdiedrich.de>
Message-ID: <4CD081D9.6070004@assembler.cz>

OK hope it fixes your PCIe issues. The "M" and CE variant has default 0s.

Acked-by: Rudolf Marek <r.marek at assembler.cz>

Committed revision 6013.


Thanks,
Rudolf



From dustin.harrison at sutus.com  Tue Nov  2 22:28:36 2010
From: dustin.harrison at sutus.com (Dustin Harrison)
Date: Tue, 02 Nov 2010 14:28:36 -0700
Subject: [coreboot] Trouble converting Truxton to CAR
In-Reply-To: <4CD04DAC.6000003@sutus.com>
References: <4CCF6697.6040305@sutus.com>
	<4CCFC136.3020509@georgi-clan.de>	<a6c38b270e623262bae3c567ae0964ea@imap.1and1.com>
	<4CD04DAC.6000003@sutus.com>
Message-ID: <4CD08284.7080103@sutus.com>

On 02/11/2010 10:43 AM, Dustin Harrison wrote:
> On 02/11/2010 9:54 AM, Joseph Smith wrote:
>> Yes, sounds to me more like a raminit issue more than a CAR issue.
> Indeed, I enabled the ramtest and see failures starting at 0xCFE14 
> which is inside the CAR space (DCACHE_RAM_SIZE is 0x8000 in my case 
> which should make the CAR range 0xC8000-0xCFFFF).  My (naive) ideas 
> are that either writes are getting sent to the SDRAM which prevents 
> the raminit code from working or that CAR is not being (successfully) 
> disabled after raminit due to some unique feature of this CPU.  The 
> reason I was asking about a method for validating the CAR code for 
> this CPU is because this CPU supports a feature to share memory (for 
> DMA purposes) with an accelerated services unit (ASU).  Thus I jumped 
> to the conclusion that this may affect the CAR routines.
Ok, I didn't think that last test through: Of course I fail the ramtest 
when I run it inside romstage.c:main() because I'm writing to memory 
that is in use.  Adjusting the test (hopefully this is valid!), I moved 
the ram_check into hardwaremain.c.  The result is that when I check 
0xc0000 to 0xd0000 everything passes except the CAR area.  The result of 
reads from the CAR area are always zero, up to the 128 failures that 
ram_verify shows before stopping.  I adjusted the CAR size to be 0x1000 
instead of 0x8000 and the read failures indeed moved to 0xcf000 instead 
of 0xc8000.

I also realized I missed one difference which is that 
cache_lbmem(MTRR_TYPE_WRBACK) line should be skipped if 
CONFIG_CACHE_AS_RAM is enabled, but that didn't solve the issue.

What would make the CAR area always return 0x0 as a value?



From r.marek at assembler.cz  Tue Nov  2 22:30:15 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Nov 2010 22:30:15 +0100
Subject: [coreboot] [PATCH 6/7] ASUS M2V support (v2):
	Comments	(unchanged)
In-Reply-To: <20101029120234.GN31684@yumi.tdiedrich.de>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029120234.GN31684@yumi.tdiedrich.de>
Message-ID: <4CD082E7.3010600@assembler.cz>

> -	/* ROM memory cycles go to LPC. */
> +	/* Only ROM memory cycles go to LPC. */

I think it should be,

 > +	/* Only memory ROM cycles go to LPC.  */

Because this bit is telling if all memory cycles should go to LPC or just those 
from ROM range. Please try to rephase that.

Thanks,
Rudolf



From njacobs8 at hetnet.nl  Tue Nov  2 22:32:39 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Tue, 2 Nov 2010 22:32:39 +0100
Subject: [coreboot]  [PATCH] Geode GX2 comment cleanup 1
Message-ID: <201011022232.39478.njacobs8@hetnet.nl>

This patch cleans up some comments and white space in gx2/northbridgeinit.c 
and gx2/raminit.c.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

This is Abuild and boot tested.

Thanks, Nils.
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From njacobs8 at hetnet.nl  Tue Nov  2 22:32:59 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Tue, 2 Nov 2010 22:32:59 +0100
Subject: [coreboot]  [PATCH] Geode GX2 comment cleanup 2
Message-ID: <201011022232.59237.njacobs8@hetnet.nl>

This patch  cleans up some more comments and white space in 
model_gx2/cpureginit.c .

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

This is Abuild and boot tested.

Thanks, Nils.
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From njacobs8 at hetnet.nl  Tue Nov  2 22:33:22 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Tue, 2 Nov 2010 22:33:22 +0100
Subject: [coreboot] [PATCH] Define unused DIMM1 to 0xFF on Geode GX2 boards
Message-ID: <201011022233.22980.njacobs8@hetnet.nl>

This patch defines the unused DIMM1 to 0xFF to make it obvious it is a bogus 
value.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

This was requested by Myles.
This is Abuild and boot tested.

Thanks, Nils.
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From njacobs8 at hetnet.nl  Tue Nov  2 22:33:53 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Tue, 2 Nov 2010 22:33:53 +0100
Subject: [coreboot]  [PATCH] Remove unused code from Geode GX2
Message-ID: <201011022233.53488.njacobs8@hetnet.nl>

This patch removes some unused code from gx2/raminit.c .

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

This is Abuild and boot tested.

Thanks, Nils.
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From njacobs8 at hetnet.nl  Tue Nov  2 22:33:44 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Tue, 2 Nov 2010 22:33:44 +0100
Subject: [coreboot]  [PATCH] Add cpu speed selection to Geode GX2 boards
Message-ID: <201011022233.44143.njacobs8@hetnet.nl>

This patch adds Kconfig cpu speed selection to Geode GX2 boards as requested by 
Uwe.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

This is Abuild and boot tested.

Thanks, Nils.
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From r.marek at assembler.cz  Tue Nov  2 22:57:41 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Nov 2010 22:57:41 +0100
Subject: [coreboot] [PATCH 7/7] ASUS M2V support (v2): Add m2v mainboard
 directory	and files
In-Reply-To: <20101029121423.GO31684@yumi.tdiedrich.de>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029121423.GO31684@yumi.tdiedrich.de>
Message-ID: <4CD08955.2020709@assembler.cz>

Hi,


On 29.10.2010 14:14, Tobias Diedrich wrote:
> This adds the m2v directory to src/mainboards/asus and adjusts the Kconfig.
> Note:
>
> I added pci irq routing setup based on pirq tables:
> pci_fixup_irqs() in irq_tables.c
>
> I didn't see any existing functionality that will just take the pirq
> information and use that to setup pci interrupts.
> For example, in src/southbridge/via/vt8237r/vt8237r_lpc.c there is
> some epia specific setup, which may really belong into the
> corresponding mainboard directory...

Hmm the legacy PIC routing may not work. In linux it could. I never tested that.

> +	/* Write SB IOAPIC. */
> +	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
> +				VT8237R_APIC_ID, IO_APIC_ADDR, 0);
> +
> +	/* Write NB IOAPIC. */
> +	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
> +				K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);

I never used the VIA system on multicore CPU, dunno what to do if we have in 
fact more cpus... The IDs should be shifted then.


> +++ src/mainboard/asus/m2v/dsdt.asl	2010-10-29 14:07:37.000000000 +0200
> @@ -0,0 +1,967 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2004 Nick Barker<Nick.Barker9 at btinternet.com>
> + * Copyright (C) 2007 Rudolf Marek<r.marek at assembler.cz>
> + * Copyright (C) 2010 Tobias Diedrich<ranma+coreboot at tdiedrich.de>

Where you have taken parts of it? Some parts feel like AMD 7xx code? Maybe we 
miss copyright here?

> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +/*
> + * ISA portions taken from QEMU acpi-dsdt.dsl.
> + */
> +
> +DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
> +{
> +	/* Data to be patched by the BIOS during POST */
> +	/* FIXME the patching is not done yet! */
> +	/* Memory related values */
> +	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
> +	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr>>  16) */
> +	Name(PBLN, 0x0)	/* Length of BIOS area */

We dont do patching we do apcigen stuff instead into SSDT.

> +
> +	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */

This cannot be hardcoded.


> +	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
> +
> +	/* global variables */
> +	Name(APIC, 0)		// 0=>8259, 1=>IOAPIC
> +	Name(LINX, 0)
> +	Name(OSYS, 0x0000)
> +
> +	/* very generic stuff */
> +
> +	/* Port 80 POST */

> +
> +	OperationRegion (POST, SystemIO, 0x80, 1)
> +	Field (POST, ByteAcc, Lock, Preserve)
> +	{
> +		DBG0, 8
> +	}
> +
> +	Method (DEBG, 1, NotSerialized)
> +	{
> +		Store (Arg0, DBG0)
> +	}
> +

I dont think you need this. My philosophy for ACPI code is: Put there only what 
is needed even no extra bit more.


> +	Method (MIN, 2, NotSerialized)
> +	{
> +		If (LLess (Arg0, Arg1)) {
> +			Return (Arg0)
> +		}
> +		Return (Arg1)
> +	}
> +
> +	/* generic acpi */
> +
> +	/* The _PIC method is called by the OS to choose between interrupt
> +	 * routing via the i8259 interrupt controller or the APIC.
> +	 *
> +	 * _PIC is called with a parameter of 0 for i8259 configuration and
> +	 * with a parameter of 1 for Local Apic/IOAPIC configuration.
> +	 */
> +
> +	Method(_PIC, 1)
> +	{
> +		// Remember the OS' IRQ routing choice.
> +		Store(Arg0, APIC)
> +	}
> +
> +	Scope(\_SB)
> +	{
> +		/* This method is placed on the top level, so we can make sure it's the
> +		 * first executed _INI method.
> +		 */
> +		Method(_INI, 0)
> +		{
> +			/* Determine the Operating System and save the value in OSYS.
> +			 * We have to do this in order to be able to work around
> +			 * certain windows bugs.
> +			 *
> +			 *    OSYS value | Operating System
> +			 *    -----------+------------------
> +			 *       2000    | Windows 2000
> +			 *       2001    | Windows XP(+SP1)
> +			 *       2002    | Windows XP SP2
> +			 *       2006    | Windows Vista
> +			 *       ????    | Windows 7
> +			 */
> +
> +			/* Let's assume we're running at least Windows 2000 */
> +			Store (2000, OSYS)
> +
> +			If (CondRefOf(_OSI, Local0)) {
> +				/* Linux answers _OSI with "True" for a couple of
> +				 * Windows version queries. But unlike Windows it
> +				 * needs a Video repost, so let's determine whether
> +				 * we're running Linux.
> +				 */
> +
> +				If (_OSI("Linux")) {
> +					Store (1, LINX)
> +				}
> +
> +				If (_OSI("Windows 2001")) {
> +					Store (2001, OSYS)
> +				}
> +
> +				If (_OSI("Windows 2001 SP1")) {
> +					Store (2001, OSYS)
> +				}
> +
> +				If (_OSI("Windows 2001 SP2")) {
> +					Store (2002, OSYS)
> +				}
> +
> +				If (_OSI("Windows 2006")) {
> +					Store (2006, OSYS)
> +				}
> +			}
> +		}
> +	}
> +

You dont need this.

> +	/* _PR CPU0 is dynamically supplied by SSDT */
> +
> +	/* For now only define 2 power states:
> +	 *  - S0 which is fully on
> +	 *  - S5 which is soft off
> +	 * Any others would involve declaring the wake up methods.
> +	 *
> +	 * Package contents:
> +	 * ofs len desc
> +	 * 0   1   Value for PM1a_CNT.SLP_TYP register to enter this system state.
> +	 * 1   1   Value for PM1b_CNT.SLP_TYP register to enter this system state. To enter any
> +	 *         given state, OSPM must write the PM1a_CNT.SLP_TYP register before the
> +	 *         PM1b_CNT.SLP_TYP register.
> +	 * 2   2   Reserved
> +	 */
> +	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
> +	Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
> +
> +	/*
> +	 * Prepare to sleep
> +	 *
> +	 * Arg0 ? An Integer containing the value of the sleeping state (1 for S1, 2 for S2, etc.)
> +	 * Return Value: None
> +	 */
> +	Method (_PTS, 1, NotSerialized)
> +	{
> +		// FIXME: Not implemented
> +	}
> +
> +	/*
> +	 * Transition to state
> +	 *
> +	 * Arg0 ? An Integer containing the value of the sleeping state (1 for S1, 2 for S2, etc.)
> +	 * Return Value: None
> +	 */
> +	Method (_TTS, 1, NotSerialized)
> +	{
> +		// FIXME: Not implemented
> +	}
> +

get rif of those please

> +	/*
> +	 * System wake
> +	 *
> +	 * Arg0 ? An Integer containing the value of the sleeping state (1 for S1, 2 for S2, etc.)
> +	 * Return Value: A Package containing two Integers containing status and the power supply S-state
> +	 *
> +	 * Element 0 ? An Integer containing a bitfield that represents conditions that occurred during sleep.
> +	 *    0x00000000 ? Wake was signaled and was successful
> +	 *    0x00000001 ? Wake was signaled but failed due to lack of power
> +	 *    0x00000002 ? Wake was signaled but failed due to thermal condition
> +	 *    Other values ? Reserved
> +	 * Element 1 ? An Integer containing the power supply S-state.
> +	 *    If non-zero, this is the effective S-state the power supply that was actually entered. This value is used
> +	 *    to detect when the targeted S-state was not entered because of too much current being drawn from the
> +	 *    power supply. For example, this might occur when some active device?s current consumption pushes
> +	 *    the system?s power requirements over the low power supply mark, thus preventing the lower power
> +	 *    mode from being entered as desired.
> +	 */
> +	Method (_WAK, 1, NotSerialized)
> +	{
> +		// FIXME: Not implemented
> +		Return ( Package () {0x00, 0x00} ) /* successful, S0 */
> +	}
> +

same here

> +/*
> +OSPM will invoke _GTS, _PTS, _TTS, _WAK, and _BFS in the following order:
> +   1. OSPM decides (through a policy scheme) to place the system into a sleeping state
> +   2. _TTS(Sx) is run, where Sx is the desired sleep state to enter
> +   3. OSPM notifies all native device drivers of the sleep state transition
> +   4. _PTS is run
> +   5. OSPM readies system for the sleep state transition
> +   6. _GTS is run
> +   7. OSPM writes the sleep vector and the system enters the specified Sx sleep state
> +   8. System Wakes up
> +   9. _BFS is run
> +   10. OSPM readies system for the return from the sleep state transition
> +   11. _WAK is run
> +   12. OSPM notifies all native device drivers of the return from the sleep state transition
> +   13. _TTS(0) is run to indicate the return to the S0 state
> +*/
> +


and here


> +	/* Root of the bus hierarchy */
> +	Scope (\_SB)
> +	{
> +		/* Top PCI device */
> +		Device (PCI0)
> +		{
> +			Name (_HID, EisaId ("PNP0A03"))
> +			Name (_ADR, 0x00180000)
> +			Name (_BBN, 0x00)
> +
> +			Name (APRT, Package() {
> +				/* AGP? */
> +				Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
> +				Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
> +				Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 },
> +				Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 },
> +				/* PCIe graphics bridge */
> +				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B },
> +				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
> +				Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
> +				Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
> +				/* PCIe bridge */
> +				Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },
> +				Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 },
> +				Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 },
> +				Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B },
> +				/* SATA */
> +				Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 },
> +				/* IDE */
> +				Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x15 },
> +				/* USB */
> +				Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 },
> +				Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
> +				Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
> +				Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
> +				/* PCI bridge */
> +				Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 },
> +				Package (0x04) { 0x0013FFFF, 0x01, 0x00, 0x14 },
> +				Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x14 },
> +				Package (0x04) { 0x0013FFFF, 0x03, 0x00, 0x14 },
> +			})
> +			Name (PPRT, Package() {
> +				/* ?? */
> +				Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 },
> +				Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 },
> +				Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 },
> +				Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 },
> +				/* PCIe graphics bridge */
> +				Package (0x04) { 0x0002FFFF, 0x00, LNKH, 0x00 },
> +				Package (0x04) { 0x0002FFFF, 0x01, LNKH, 0x00 },
> +				Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 },
> +				Package (0x04) { 0x0002FFFF, 0x03, LNKH, 0x00 },
> +				/* PCIe bridge */
> +				Package (0x04) { 0x0003FFFF, 0x00, LNKH, 0x00 },
> +				Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 },
> +				Package (0x04) { 0x0003FFFF, 0x02, LNKH, 0x00 },
> +				Package (0x04) { 0x0003FFFF, 0x03, LNKH, 0x00 },
> +				/* SATA */
> +				Package (0x04) { 0x000FFFFF, 0x01, LNKB, 0x00 },
> +				/* USB */
> +				Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 },
> +				Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 },
> +				Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 },
> +				Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 },
> +				/* PCI bridge */
> +				Package (0x04) { 0x0013FFFF, 0x00, LNKD, 0x00 },
> +				Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
> +				Package (0x04) { 0x0013FFFF, 0x02, LNKD, 0x00 },
> +				Package (0x04) { 0x0013FFFF, 0x03, LNKD, 0x00 },
> +			})
> +
> +			/* PCI Routing Table */
> +			Method (_PRT, 0, NotSerialized)
> +			{
> +				If (APIC)
> +				{
> +					Return (APRT)
> +				}
> +				Return (PPRT)
> +			}
> +
> +			Device (K8T0) { Name (_ADR, 0x00000000) }
> +			Device (K8T1) { Name (_ADR, 0x00000001) }
> +			Device (K8T2) { Name (_ADR, 0x00000002) }
> +			Device (K8T3) { Name (_ADR, 0x00000003) }
> +			Device (K8T4) { Name (_ADR, 0x00000004) }
> +			Device (K8T5) { Name (_ADR, 0x00000005) }
> +			Device (K8T7) { Name (_ADR, 0x00000007) }

no need

> +
> +			Device (PCI1) { Name (_ADR, 0x00010000) }
> +
> +			Device (PEGG)
> +			{
> +				Name (_ADR, 0x00020000)
> +				Name (APRT, Package () {
> +					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
> +					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
> +					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
> +					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
> +				})
> +				Name (PPRT, Package () {
> +					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
> +				})
> +				Method (_PRT, 0, NotSerialized)
> +				{
> +					If (APIC)
> +					{
> +						Return (APRT)
> +					}
> +					Return (PPRT)
> +				}
> +			}
> +
> +			Device (PEX0)
> +			{
> +				Name (_ADR, 0x00030000)
> +				Name (APRT, Package () {
> +					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
> +					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
> +					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
> +					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
> +				})
> +				Name (PPRT, Package () {
> +					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
> +				})
> +				Method (_PRT, 0, NotSerialized)
> +				{
> +					If (APIC)
> +					{
> +						Return (APRT)
> +					}
> +					Return (PPRT)
> +				}
> +			}
> +
> +			Device (PEX1)
> +			{
> +				Name (_ADR, 0x00030001)
> +				Name (APRT, Package () {
> +					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
> +					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
> +					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
> +					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
> +				})
> +				Name (PPRT, Package () {
> +					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
> +				})
> +				Method (_PRT, 0, NotSerialized)
> +				{
> +					If (APIC)
> +					{
> +						Return (APRT)
> +					}
> +					Return (PPRT)
> +				}
> +			}
> +
> +			Device (PEX2)
> +			{
> +				Name (_ADR, 0x00030002)
> +				Name (APRT, Package () {
> +					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
> +					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
> +					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
> +					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
> +				})
> +				Name (PPRT, Package () {
> +					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
> +					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
> +				})
> +				Method (_PRT, 0, NotSerialized)
> +				{
> +					If (APIC)
> +					{
> +						Return (APRT)
> +					}
> +					Return (PPRT)
> +				}
> +			}
> +
> +			Device (SATA) { Name (_ADR, 0x000f0000) }
> +			Device (PATA) { Name (_ADR, 0x000f0001) }
> +
> +			Device (PCI6)
> +			{
> +				Name (_ADR, 0x00130000)
> +				Name (APRT, Package () {
> +					Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* IRQ17 */
> +				})
> +				Name (PPRT, Package () {
> +					Package (0x04) { 0x0001FFFF, 0x00, LNKB, 0x00 },
> +				})
> +				Method (_PRT, 0, NotSerialized)
> +				{
> +					If (APIC)
> +					{
> +						Return (APRT)
> +					}
> +					Return (PPRT)
> +				}
> +			}
> +
> +			Device (PCI7)
> +			{
> +				Name (_ADR, 0x00130001)
> +				Name (APR8, Package () {
> +					/* PCI slot 1 */
> +					Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 },
> +					Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
> +					Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
> +					Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
> +
> +					/* PCI slot 2 */
> +					Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 },
> +					Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
> +					Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
> +					Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
> +
> +					/* PCI slot 3 */
> +					Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 },
> +					Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x13 },
> +					Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x10 },
> +					Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x11 },
> +
> +					/* PCI slot 4 */
> +					Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x13 },
> +					Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x10 },
> +					Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x11 },
> +					Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x12 },
> +				})
> +				Name (PPR8, Package () {
> +					/* PCI slot 1 */
> +					Package (0x04) { 0x0006FFFF, 0x00, LNKA, 0x00 },
> +					Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 },
> +					Package (0x04) { 0x0006FFFF, 0x02, LNKC, 0x00 },
> +					Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 },
> +
> +					/* PCI slot 2 */
> +					Package (0x04) { 0x0007FFFF, 0x00, LNKB, 0x00 },
> +					Package (0x04) { 0x0007FFFF, 0x01, LNKC, 0x00 },
> +					Package (0x04) { 0x0007FFFF, 0x02, LNKD, 0x00 },
> +					Package (0x04) { 0x0007FFFF, 0x03, LNKA, 0x00 },
> +
> +					/* PCI slot 3 */
> +					Package (0x04) { 0x0008FFFF, 0x00, LNKC, 0x00 },
> +					Package (0x04) { 0x0008FFFF, 0x01, LNKD, 0x00 },
> +					Package (0x04) { 0x0008FFFF, 0x02, LNKA, 0x00 },
> +					Package (0x04) { 0x0008FFFF, 0x03, LNKB, 0x00 },
> +
> +					/* PCI slot 4 */
> +					Package (0x04) { 0x0009FFFF, 0x00, LNKD, 0x00 },
> +					Package (0x04) { 0x0009FFFF, 0x01, LNKA, 0x00 },
> +					Package (0x04) { 0x0009FFFF, 0x02, LNKB, 0x00 },
> +					Package (0x04) { 0x0009FFFF, 0x03, LNKC, 0x00 },
> +				})
> +
> +				Method (_PRT, 0, NotSerialized)
> +				{
> +					If (APIC)
> +					{
> +						Return (APR8)
> +					}
> +					Return (PPR8)
> +				}
> +			}
> +
> +			Device (PCIE)
> +			{
> +				Name (_HID, EisaId ("PNP0C02"))
> +				Method (_CRS, 0, NotSerialized)
> +				{
> +					Name (TMP, ResourceTemplate () {
> +						Memory32Fixed(ReadOnly,
> +							0xE0000000,

Sorry this cannot be hardcoded. I dont think you need this at all.



> +							0x10000000,
> +						)
> +					})
> +					Return (TMP)
> +				}
> +			}
> +
> +			Device (SBRG) { /* southbridge */
> +				Name (_ADR, 0x00110000)
> +				Device (HPET) {
> +					Name (_HID, EisaId ("PNP0103"))
> +					Method (_STA, 0, NotSerialized)
> +					{
> +						Return (0x0F)
> +					}
> +					Method (_CRS, 0, NotSerialized)
> +					{
> +						Name (TMP, ResourceTemplate () {
> +							Memory32Fixed(ReadOnly,
> +								0xFED00000,
> +								0x00000400,
> +							)
> +							IRQNoFlags () {0}
> +							IRQNoFlags () {8}
> +						})
> +						Return (TMP)
> +					}
> +				}
> +
> +				/* PS/2 keyboard (seems to be important for WinXP install) */
> +				Device (KBD)
> +				{
> +					Name (_HID, EisaId ("PNP0303"))
> +					Method (_STA, 0, NotSerialized)
> +					{
> +						Return (0x0f)
> +					}
> +					Method (_CRS, 0, NotSerialized)
> +					{
> +						Name (TMP, ResourceTemplate () {
> +							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
> +							IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
> +							IRQNoFlags () {1}
> +						})
> +						Return (TMP)
> +					}
> +				}
> +
> +				/* PS/2 mouse */
> +				Device (MOU)
> +				{
> +					Name (_HID, EisaId ("PNP0F13"))
> +					Method (_STA, 0, NotSerialized)
> +					{
> +						Return (0x0f)
> +					}
> +					Method (_CRS, 0, NotSerialized)
> +					{
> +						Name (TMP, ResourceTemplate () {
> +						     IRQNoFlags () {12}
> +						})
> +						Return (TMP)
> +					}
> +				}
> +
> +				/* Parallel port */
> +				Device (LPT0)
> +				{
> +					Name (_HID, EisaId ("PNP0401"))
> +					Method (_STA, 0, NotSerialized)
> +					{
> +						Return (0x0f)
> +					}
> +					Method (_CRS, 0, NotSerialized)
> +					{
> +						Name (TMP, ResourceTemplate () {
> +							IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
> +							IO (Decode16, 0x0778, 0x0778, 0x01, 0x08)
> +							IRQNoFlags () {7}
> +							DMA (Compatibility, NotBusMaster, Transfer8) {3}
> +						})
> +						Return (TMP)
> +					}
> +				}
> +			}
> +
> +			Name(CRES, ResourceTemplate() {
> +				WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
> +					0x0000,             // Granularity
> +					0x0000,             // Range Minimum
> +					0x00FF,             // Range Maximum
> +					0x0000,             // Translation Offset
> +					0x0100,             // Length
> +					,,
> +				)
> +				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
> +
> +				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
> +					0x0000,			/* address granularity */
> +					0x0000,			/* range minimum */
> +					0x0CF7,			/* range maximum */
> +					0x0000,			/* translation */
> +					0x0CF8			/* length */
> +				)
> +
> +				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
> +					0x0000,			/* address granularity */
> +					0x0D00,			/* range minimum */
> +					0xFFFF,			/* range maximum */
> +					0x0000,			/* translation */
> +					0xF300			/* length */
> +				)
> +
> +				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
> +				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
> +				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
> +				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
> +				/* DRAM Memory from 1MB to TopMem */
> +				Memory32Fixed(READWRITE, 0x00100000, 0x00000000, DMLO)  /* 1MB to TopMem */
> +				Memory32Fixed(ReadOnly, 0xE0000000, 0x10000000, MCFG)   /* MMCONFIG area */
> +				Memory32Fixed(READONLY, 0xF0000000, 0x10000000, MMIO)   /* PCI mapping space */
> +
> +#if 0
> +				/* BIOS space just below 4GB */
> +				DWORDMemory(
> +					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> +					0x00,			/* Granularity */
> +					0x00000000,		/* Min */
> +					0x00000000,		/* Max */
> +					0x00000000,		/* Translation */
> +					0x00000001,		/* Max-Min, RLEN */
> +					,,
> +					PCBM
> +				)
> +
> +				/* BIOS space just below 16EB */
> +				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> +					0x00000000,		/* Granularity */
> +					0x00000000,		/* Min */
> +					0x00000000,		/* Max */
> +					0x00000000,		/* Translation */
> +					0x00000001,		/* Max-Min, RLEN */
> +					,,
> +					PEBM
> +				)
> +#endif
> +
> +				/* DRAM memory from 4GB to TopMem2 */
> +				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> +					0x00000000,		/* Granularity */
> +					0x00000000,		/* Min */
> +					0x00000000,		/* Max */
> +					0x00000000,		/* Translation */
> +					0x00000001,		/* Max-Min, RLEN */
> +					,,
> +					DMHI
> +				)
> +
> +			}) /* End Name(_SB.PCI0.CRES) */
> +
> +			External(TOM1) /* 32bit top of memory from SSDT */
> +			External(TOM2) /* 64bit top of memory from SSDT */


Maybe windows will accept only IO resorce without any memory resource. It is 
PITA. Please try to investigate what we should relly tell here:

Name(CRES, ResourceTemplate() {
                 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)

                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, 
EntireRange,
                     0x0000,         /* address granularity */
                     0x0000,         /* range minimum */
                     0x0CF7,         /* range maximum */
                     0x0000,         /* translation */
                     0x0CF8          /* length */
                 )

                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, 
EntireRange,
                     0x0000,         /* address granularity */
                     0x0D00,         /* range minimum */
                     0xFFFF,         /* range maximum */
                     0x0000,         /* translation */
                     0xF300          /* length */
                      )
             }) /* End Name(_SB.PCI0.CRES) */

             Method(_CRS, 0) {
                 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
                 Return(CRES) /* note to change the Name buffer */
             }  /* end of Method(_SB.PCI0._CRS) */
         } /* End Device(PCI0)  */


If this works for XP it would be nice...

> +	Scope (\_SB)
> +	{
> +		OperationRegion (PCI0.SBRG.PIX0, PCI_Config, 0x55, 0x04)
> +		OperationRegion (PCI0.SBRG.PIX1, PCI_Config, 0x50, 0x02)
> +		OperationRegion (PCI0.SBRG.PIX2, PCI_Config, 0x44, 0x02)
> +		OperationRegion (PCI0.SBRG.PIX3, PCI_Config, 0x67, 0x03)
> +		OperationRegion (PCI0.SBRG.PIX4, PCI_Config, 0x6C, 0x04)
> +		OperationRegion (PCI0.SBRG.PIEF, PCI_Config, 0x46, 0x01)

This code comes from where? You wrote it?

> +		Field (PCI0.SBRG.PIX0, ByteAcc, NoLock, Preserve)
> +		{
> +			    , 4,
> +			PIRA, 4,
> +			PIRB, 4,
> +			PIRC, 4,
> +			    , 4,
> +			PIRD, 4,
> +			    , 4
> +		}
> +		Field (PCI0.SBRG.PIX1, ByteAcc, NoLock, Preserve)
> +		{
> +			    , 1,
> +			EP3C, 1,
> +			EN3C, 1,
> +			    , 6,
> +			KBFG, 1
> +		}
> +		Field (PCI0.SBRG.PIX2, ByteAcc, NoLock, Preserve)
> +		{
> +			PIRE, 4,
> +			PIRF, 4,
> +			PIRG, 4,
> +			PIRH, 4,
> +		}
> +		Field (PCI0.SBRG.PIX3, ByteAcc, NoLock, Preserve)
> +		{
> +			ENIR, 1,
> +			IRSD, 1,
> +			Offset (0x02),
> +			IRBA, 8
> +		}
> +		Field (PCI0.SBRG.PIX4, ByteAcc, NoLock, Preserve)
> +		{
> +			PS0E, 1,
> +			PS1E, 1,
> +			ROME, 1,
> +			APCE, 1,
> +			LPMS, 2,
> +			MSEN, 1,
> +			IXEN, 1,
> +			LPMD, 2,
> +			MDEN, 1,
> +			GMEN, 1,
> +			LPLP, 2,
> +			LPEN, 1,
> +			FDEN, 1,
> +			LPCA, 3,
> +			CAEN, 1,
> +			LPCB, 3,
> +			CBEN, 1,
> +			LPSB, 2,
> +			SBEN, 1,
> +			FDSE, 1,
> +			Offset (0x04)

This looks suspicius. We cannot copy anything from orig bios. I think you dont 
need legacy IRQ anyway windows should work with APIC only. Please try to keep 
the ACPI stuff as simple as possible.
> +/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
> +   LDN the register belongs to, before you can access the register. */
> +static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
> +{
> +	outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
> +	outb(ldn, SIO_DATA);
> +	outb(index, SIO_BASE);
> +	outb(value, SIO_DATA);
> +}


I think we have some generic function like pnp_enter_ext_func_mode
etc please check it.


> +	/*
> +	 * it8712f gpio config
> +	 *
> +	 * Most importantly this switches pin 91 from
> +	 * PCIRSTIN# to VIN7.
> +	 * Note that only PCIRST3# and PCIRST5# are affected
> +	 * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always
> +	 * direct buffers of #LRESET (low pin count bus reset).
> +	 * If this is not done All PCIRST are in reset state and the
> +	 * pcie slots don't initialize.
> +	 *
> +	 * pci reset handling:
> +	 * pin 91: VIN7 (alternate PCIRSTIN#)
> +	 * pin 48: PCIRST5# / gpio port 5 bit 0
> +	 * pin 84: PCIRST4# / gpio port 1 bit 0
> +	 * pin 31: PCIRST1# / gpio port 1 bit 4
> +	 * pin 33: PCIRST2# / gpio port 1 bit 2
> +	 * pin 34: PCIRST3# / gpio port 1 bit 1
> +	 *
> +	 * PCIRST[0-5]# are connected as follows:
> +	 * pcirst1# ->  pci bus
> +	 * pcirst2# ->  ide bus
> +	 * pcirst3# ->  pcie devices
> +	 * pcirst4# ->  pcie graphics
> +	 * pcirst5# ->  maybe n/c (untested)

nice how did you found out?

Btw we usually have sio setup in romstage.c But maybe it makes more sense here 
if it is not critical.

Maybe resets and voltage setup should be really in romstage.c (so it is called 
before memory etc is setup).




> +
> +static void m2v_bus_init(void)
> +{
> +	u8 tmp;
> +
> +	pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0, 0), K8T890_MULTIPLE_FN_EN, 0x01);
> +	/*
> +	 * Northbridge pcie bridge 3.3 is not connected to anything, hide it.
> +	 */
> +	tmp = pci_cf8_conf1.read8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0);
> +	tmp&= ~0x10; /* hide pcie bridge 0:3.3 */
> +	tmp&= ~0x40; /* hide scratch register function 0:0.6 */
> +	pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0, tmp);
> +	/* Enable southbridge bridges 13.0 and 13.1 */
> +	pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0x11, 7), 0X4F, 0x43);


Hmm this most likely shoudl be done with the help of devicetree.cb

> +	/*
> +	 * Mark APIC memory as reserved to get closer to ASUS E820 map
> +	 */
> +	lb_add_memory_range(mem, LB_MEM_RESERVED, IO_APIC_ADDR,     0x1000);
> +	lb_add_memory_range(mem, LB_MEM_RESERVED, K8T890_APIC_BASE, 0x1000);

Dont think this is neccessary.


> +	/*
> +	 * Mark BIOS ROM space as reserved
> +	 */
> +	lb_add_memory_range(mem, LB_MEM_RESERVED, 0xffc00000, 0x400000);

Dont think this is neccessary.

> +	return 0;
> +}
> +
> +struct chip_operations mainboard_ops = {
> +	CHIP_NAME("ASUS M2V")
> +	.enable_dev = m2v_enable,
> +};
> Index: src/mainboard/asus/m2v/mptable.c
> ===================================================================
> --- /dev/null	1970-01-01 00:00:00.000000000 +0000
> +++ src/mainboard/asus/m2v/mptable.c	2010-10-29 14:07:37.000000000 +0200

THis was recently fixed are you using fixed version?
> +#define SB_VFSMAF 0

I think for you would work normal way (without this ldstop_sb. I had troubles 
with integrated VGA on K8M890.


Otherwise well done! Please try to address the remaining issues.

Thanks,
Rudolf




From uwe at hermann-uwe.de  Tue Nov  2 23:03:23 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 2 Nov 2010 23:03:23 +0100
Subject: [coreboot] Trouble converting Truxton to CAR
In-Reply-To: <4CD04DAC.6000003@sutus.com>
References: <4CCF6697.6040305@sutus.com> <4CCFC136.3020509@georgi-clan.de>
	<a6c38b270e623262bae3c567ae0964ea@imap.1and1.com>
	<4CD04DAC.6000003@sutus.com>
Message-ID: <20101102220323.GM3256@greenwood>

On Tue, Nov 02, 2010 at 10:43:08AM -0700, Dustin Harrison wrote:
> Indeed, I enabled the ramtest and see failures starting at 0xCFE14
> which is inside the CAR space (DCACHE_RAM_SIZE is 0x8000 in my case
> which should make the CAR range 0xC8000-0xCFFFF).  My (naive) ideas
> are that either writes are getting sent to the SDRAM which prevents
> the raminit code from working or that CAR is not being
> (successfully) disabled after raminit due to some unique feature of
> this CPU.  The reason I was asking about a method for validating the
> CAR code for this CPU is because this CPU supports a feature to
> share memory (for DMA purposes) with an accelerated services unit
> (ASU).  Thus I jumped to the conclusion that this may affect the CAR
> routines.

Maybe. Can you post your patch for review and if possible the URL for
the CPU datasheet?


Thanks, Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From r.marek at assembler.cz  Tue Nov  2 23:03:12 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Nov 2010 23:03:12 +0100
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7
In-Reply-To: <2924E87E845A4B3F98F6D270D6196482@m3a78>
References: <2924E87E845A4B3F98F6D270D6196482@m3a78>
Message-ID: <4CD08AA0.5020009@assembler.cz>

Hi Scott!

Thank you very much working on this! I wanted to try out but Igot hang in early 
init (car stage). Most likely because of this:

> ===================================================================
> --- src/southbridge/amd/rs780/rs780_early_setup.c	(revision 6011)
> +++ src/southbridge/amd/rs780/rs780_early_setup.c	(working copy)
> @@ -485,7 +485,7 @@
>
>   	/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
>   	 * force this BAR as mem type in rs780_gfx.c */
> -	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
> +	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x06);
>   }
>
>   static void rs780_por_mc_index_init(device_t nb_dev)
> Index: src/southbridge/amd/rs780/rs780_gfx.c

Can you please tell what it does?

Thanks,
Rudolf



From uwe at hermann-uwe.de  Tue Nov  2 23:20:43 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 2 Nov 2010 23:20:43 +0100
Subject: [coreboot] [PATCH] don't print too early on mcp55-based boards
In-Reply-To: <20101101220141.592.qmail@stuge.se>
References: <20101101160338.GA28294@countzero.vandewege.net>
	<20101101220141.592.qmail@stuge.se>
Message-ID: <20101102222043.GN3256@greenwood>

On Mon, Nov 01, 2010 at 11:01:41PM +0100, Peter Stuge wrote:
> Ward Vandewege wrote:
> > See attached. Perhaps we should also print a post code if the SMBus
> > controller can't be found - suggestions for a value?
> 
> 0x5B ?
> 
> 
> > We can't print this early.
> > 
> > This patch fixes a hang on 
> > 
> >   supermicro/h8dme
> >   supermicro/h8dmr
> >   supermicro/h8dmr_fam10
> > 
> > and possibly on other mcp55-based boards.
> > 
> > Signed-off-by: Ward Vandewege <ward at gnu.org>
> 
> Acked-by: Peter Stuge <peter at stuge.se>

I don't object to the patch, and we should probably fix this in all
other southbridges, I think the same problem applies there.

But: the die() call itself also does a printk(), so that'll still hang
if the error path is chosen (at that point it probably doesn't matter
much, though, as we die anyway).

I also agree that die() should have a POST code, preferrably something
easy to remember. It already has a commented-out "//post_code(0xff);".
Not sure why it's disabled, but I think it should be something other
than 0xff, that's a bit too "special" for my taste.

We have "0xee: Not supposed to get here" as per documentation/POSTCODES,
so maybe we can use 0xdd ("d" as in die), if that's not already used elsewhere.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From njacobs8 at hetnet.nl  Wed Nov  3 00:03:18 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Wed, 3 Nov 2010 00:03:18 +0100
Subject: [coreboot]  print(k) question
Message-ID: <201011030003.18131.njacobs8@hetnet.nl>

Hi all,
Could someone explain the difference between printk(BIOS_EMERG, "message\n") 
and print_emerg("message\n") and witch one is preferred?

Thanks, Nils



From wangqingpei at gmail.com  Wed Nov  3 03:05:02 2010
From: wangqingpei at gmail.com (Qing Pei Wang)
Date: Wed, 3 Nov 2010 10:05:02 +0800
Subject: [coreboot] print(k) question
In-Reply-To: <201011030003.18131.njacobs8@hetnet.nl>
References: <201011030003.18131.njacobs8@hetnet.nl>
Message-ID: <AANLkTikmQzm0+CKL-UraprPgDHDeD0ntMrUOkbjtaS2k@mail.gmail.com>

actually, there is no difference.
You can check the marco definition under
coreboot/src/include/console/console.h line 103(maybe)

Best wishes
Wang Qing Pei
Phone: 86+18930528086


On Wed, Nov 3, 2010 at 7:03 AM, Nils <njacobs8 at hetnet.nl> wrote:

> Hi all,
> Could someone explain the difference between printk(BIOS_EMERG,
> "message\n")
> and print_emerg("message\n") and witch one is preferred?
>
> Thanks, Nils
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From dustin.harrison at sutus.com  Wed Nov  3 03:18:01 2010
From: dustin.harrison at sutus.com (Dustin Harrison)
Date: Tue, 02 Nov 2010 19:18:01 -0700
Subject: [coreboot] Trouble converting Truxton to CAR
In-Reply-To: <20101102220323.GM3256@greenwood>
References: <4CCF6697.6040305@sutus.com> <4CCFC136.3020509@georgi-clan.de>
	<a6c38b270e623262bae3c567ae0964ea@imap.1and1.com>
	<4CD04DAC.6000003@sutus.com> <20101102220323.GM3256@greenwood>
Message-ID: <4CD0C659.7060308@sutus.com>

On 02/11/2010 3:03 PM, Uwe Hermann wrote:
> On Tue, Nov 02, 2010 at 10:43:08AM -0700, Dustin Harrison wrote:
>> Indeed, I enabled the ramtest and see failures starting at 0xCFE14
>> which is inside the CAR space (DCACHE_RAM_SIZE is 0x8000 in my case
>> which should make the CAR range 0xC8000-0xCFFFF).  My (naive) ideas
>> are that either writes are getting sent to the SDRAM which prevents
>> the raminit code from working or that CAR is not being
>> (successfully) disabled after raminit due to some unique feature of
>> this CPU.  The reason I was asking about a method for validating the
>> CAR code for this CPU is because this CPU supports a feature to
>> share memory (for DMA purposes) with an accelerated services unit
>> (ASU).  Thus I jumped to the conclusion that this may affect the CAR
>> routines.
> Maybe. Can you post your patch for review and if possible the URL for
> the CPU datasheet?
>
I'll see what I can do for a patch, but it will be a couple of days 
while I wait for my RDIMM to show up so I can resurrect the Truxton dev 
board.

In the meantime here is the link to the datasheet:
http://download.intel.com/design/intarch/ep80579/320066.pdf



From scott at notabs.org  Wed Nov  3 05:04:45 2010
From: scott at notabs.org (Scott Duplichan)
Date: Tue, 2 Nov 2010 23:04:45 -0500
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7
In-Reply-To: <4CD08AA0.5020009@assembler.cz>
References: <2924E87E845A4B3F98F6D270D6196482@m3a78>
	<4CD08AA0.5020009@assembler.cz>
Message-ID: <2F4E22AFAEED4EA993B55E8D9D9160C8@m3a78>

-----Original Message-----
From: coreboot-bounces+scott=notabs.org at coreboot.org [mailto:coreboot-bounces+scott=notabs.org at coreboot.org] On Behalf Of Rudolf
Marek
Sent: Tuesday, November 02, 2010 05:03 PM
To: coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7

]Hi Scott!
]
]Thank you very much working on this! I wanted to try out but Igot hang in early 
]init (car stage). Most likely because of this:
]
]> ===================================================================
]> --- src/southbridge/amd/rs780/rs780_early_setup.c	(revision 6011)
]> +++ src/southbridge/amd/rs780/rs780_early_setup.c	(working copy)
]> @@ -485,7 +485,7 @@
]>
]>   	/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
]>   	 * force this BAR as mem type in rs780_gfx.c */
]> -	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
]> +	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x06);
]>   }
]>
]>   static void rs780_por_mc_index_init(device_t nb_dev)
]> Index: src/southbridge/amd/rs780/rs780_gfx.c
]
]Can you please tell what it does?

Hello Rudolf,

Thanks for taking time to test this patch. I assume you tested with
a family 0Fh processor. The mistake I made was testing only with
family 10h, which is how this problem slipped through. Here are the
bit definitions:

F2_MULTI_FUNC_ENABLE     8
GFX_DEBUG_BAR_ENABLE     9
GFX_DEBUG_DECODE_ENABLE 10

The original code was incorrect to set bit 8 because the reference BIOS
does not set it. But that may be insignificant. I believe the real
problem is this. The following sequence is needed needed to reliably
enable the gfx debug bar (bar 6 of bus 1, device 5, function 0):

1) Set bit 9 so that the bar is writable and can be programmed.
2) Allow the resource allocation code assign a range to the debug bar.
3) Set bit 10 to let the debug start decoding its range.

The debug bar is a back door into the pci config space of the RS780.
If it is not setup and working, the ATI graphics driver will not work.

I will re-sumbit the patch with this change. I still have to port some
ACPI changes from mahogany_fam10 to mahogany before I can test Win7
the family 0Fh processor.

Thanks,
Scott


]Thanks,
]Rudolf





From scott at notabs.org  Wed Nov  3 05:29:10 2010
From: scott at notabs.org (Scott Duplichan)
Date: Tue, 2 Nov 2010 23:29:10 -0500
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7
	(revised)
Message-ID: <C030A2F7944A40AE9FC019041544BB6A@m3a78>

(Re-submitting with correction to GFX debug bar setup procedure needed
for use with AMD family 0Fh processor).

This patch solves crashes and BSODs that occur when booting Win7 with
AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB
by running dxdiag and Windows media player at 1600x1200 true color.
Additional changes needed to boot Win7 on Mahogany_fam10 will follow.

-- Enable and program the debug bar as required by the ATI graphics driver.
   First, make the debug bar writable and allow resource allocation code
   to program it. Once programmed, enable its operation.
-- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
-- Make strap programming more closely follow the reference BIOS.
-- Disable PCIe bar 3 after using it.
-- UMA size is no longer hardcoded.
-- Disable write combining for all steppings to eliminate stability problem.
-- Correct task file data.
-- Improve the accuracy of the Atom table that passes information to the driver.

Signed-off-by: Scott Duplichan <scott at notabs.org>

Index: src/southbridge/amd/rs780/rs780.c
===================================================================
--- src/southbridge/amd/rs780/rs780.c	(revision 6011)
+++ src/southbridge/amd/rs780/rs780.c	(working copy)
@@ -133,11 +133,6 @@
 	temp32 = pci_read_config32(nb_dev, 0x4c);
 	printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32);
 
-	/* disable GFX debug. */
-	temp8 = pci_read_config8(nb_dev, 0x8d);
-	temp8 &= ~(1<<1);
-	pci_write_config8(nb_dev, 0x8d, temp8);
-
 	/* set temporary NB TOM to 0x40000000. */
 	rs780_set_tom(nb_dev);
 
@@ -194,14 +189,24 @@
 static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 {
 	/* NB_InitGFXStraps */
-	u32 MMIOBase, apc04, apc18, apc24;
+	u32 MMIOBase, apc04, apc18, apc24, romstrap2;
+	msr_t pcie_mmio_save;
 	volatile u32 * strap;
 
+	// disable processor pcie mmio, if enabled
+	if (is_family10h()) {
+		msr_t temp;
+		pcie_mmio_save = temp = rdmsr (0xc0010058);
+		temp.lo &= ~1;
+		wrmsr (0xc0010058, temp);
+	}
+
 	/* Get PCIe configuration space. */
 	MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0;
 	/* Temporarily disable PCIe configuration space. */
 	set_htiu_enable_bits(nb_dev, 0x32, 1<<28, 0);
 
+	// 1E: NB_BIF_SPARE
 	set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7);
 	/* Set a temporary Bus number. */
 	apc18 = pci_read_config32(dev, 0x18);
@@ -214,18 +219,27 @@
 	pci_write_config8(dev, 0x04, 0x02);
 
 	/* Program Straps. */
-	strap = (volatile u32 *)(MMIOBase + 0x15020);
+	romstrap2 = 1 << 26; // enables audio function
 #if (CONFIG_GFXUMA == 1)
-	*strap = 1<<7; /* the format of BIF_MEM_AP_SIZE. 001->256MB? */
-#else
-	*strap = 0; /* 128M SP memory, 000 -> 128MB */
+	extern uint64_t uma_memory_size;
+	// bits 7-9: aperture size
+	// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g 
+	if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;
+	if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7;
+	if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7;
+	if (uma_memory_size == 0x10000000) romstrap2 |= 1 << 7;
+	if (uma_memory_size == 0x20000000) romstrap2 |= 4 << 7;
+	if (uma_memory_size == 0x40000000) romstrap2 |= 5 << 7;
+	if (uma_memory_size == 0x80000000) romstrap2 |= 6 << 7;
 #endif
+	strap = (volatile u32 *)(MMIOBase + 0x15020);
+	*strap = romstrap2;
 	strap = (volatile u32 *)(MMIOBase + 0x15000);
 	*strap = 0x2c006300;
 	strap = (volatile u32 *)(MMIOBase + 0x15010);
 	*strap = 0x03015330;
-	//strap = (volatile u32 *)(MMIOBase + 0x15020);
-	//*strap |= 0x00000040; /* Disable HDA device. */
+	strap = (volatile u32 *)(MMIOBase + 0x15020);
+	*strap = romstrap2 | 0x00000040;
 	strap = (volatile u32 *)(MMIOBase + 0x15030);
 	*strap = 0x00001002;
 	strap = (volatile u32 *)(MMIOBase + 0x15040);
@@ -240,8 +254,9 @@
 	/* BIF switches into normal functional mode. */
 	set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<4 | 1<<5, 1<<5);
 
-	/* NB Revision is A12. */
-	set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9);
+	/* NB Revision is A12 or newer */
+	if (get_nb_rev(nb_dev) >= REV_RS780_A12)
+		set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9);
 
 	/* Restore APC04, APC18, APC24. */
 	pci_write_config32(dev, 0x04, apc04);
@@ -250,6 +265,11 @@
 
 	/* Enable PCIe configuration space. */
 	set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28);
+
+	// restore processor pcie mmio
+	if (is_family10h())
+		wrmsr (0xc0010058, pcie_mmio_save);
+
 	printk(BIOS_INFO, "GC is accessible from now on.\n");
 }
 
@@ -332,18 +352,17 @@
 				       (dev->enabled ? 1 : 0) << 6);
 		if (dev->enabled)
 			rs780_gpp_sb_init(nb_dev, dev, dev_ind);
-		disable_pcie_bar3(nb_dev);
 		break;
 	case 9:		/* bus 0, dev 9,10, GPP */
 	case 10:
 		printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n",
 			    dev->enabled);
-		enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
 				       (dev->enabled ? 0 : 1) << (7 + dev_ind));
 		if (dev->enabled)
 			rs780_gpp_sb_init(nb_dev, dev, dev_ind);
-		/* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */
+
+		if (dev_ind == 10) disable_pcie_bar3(nb_dev);
 		break;
 	default:
 		printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
Index: src/southbridge/amd/rs780/rs780.h
===================================================================
--- src/southbridge/amd/rs780/rs780.h	(revision 6011)
+++ src/southbridge/amd/rs780/rs780.h	(working copy)
@@ -208,4 +208,9 @@
 void config_gpp_core(device_t nb_dev, device_t sb_dev);
 void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
 u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
+u32 extractbit(u32 data, int bit_number);
+u32 extractbits(u32 source, int lsb, int msb);
+int cpuidFamily(void);
+int is_family0Fh(void);
+int is_family10h(void);
 #endif				/* RS780_H */
Index: src/southbridge/amd/rs780/rs780_cmn.c
===================================================================
--- src/southbridge/amd/rs780/rs780_cmn.c	(revision 6011)
+++ src/southbridge/amd/rs780/rs780_cmn.c	(working copy)
@@ -29,6 +29,7 @@
 #include <cpu/amd/mtrr.h>
 #include <boot/coreboot_tables.h>
 #include <delay.h>
+#include <cpu/cpu.h>
 #include "rs780.h"
 
 static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
@@ -223,7 +224,7 @@
 		pci_write_config32(k8_f1, 0xbc, 0);
 		pci_write_config32(k8_f1, 0xb0, 0);
 		pci_write_config32(k8_f1, 0xb4, 0);
-	}
+	}
 }
 
 void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
@@ -361,3 +362,42 @@
 	pci_write_config32(nb_dev, 0x90, uma_memory_base);
 	//nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
 }
+
+// extract single bit
+u32 extractbit(u32 data, int bit_number)
+{
+	return (data >> bit_number) & 1;
+}
+
+// extract bit field
+u32 extractbits(u32 source, int lsb, int msb)
+{
+	int field_width = msb - lsb + 1;
+	u32 mask = 0xFFFFFFFF >> (32 - field_width);
+	return (source >> lsb) & mask;
+}
+
+// return AMD cpuid family
+int cpuidFamily(void)
+{
+	u32 baseFamily, extendedFamily, fms;
+	
+	fms = cpuid_eax (1);
+	baseFamily = extractbits (fms, 8, 11);
+	extendedFamily = extractbits (fms, 20, 27);
+	return baseFamily + extendedFamily;
+}
+
+
+// return non-zero for AMD family 0Fh processor found
+int is_family0Fh(void)
+{
+	return cpuidFamily() == 0x0F;
+}
+
+
+// return non-zero for AMD family 10h processor found
+int is_family10h(void)
+{
+	return cpuidFamily() == 0x10;
+}
Index: src/southbridge/amd/rs780/rs780_early_setup.c
===================================================================
--- src/southbridge/amd/rs780/rs780_early_setup.c	(revision 6011)
+++ src/southbridge/amd/rs780/rs780_early_setup.c	(working copy)
@@ -483,9 +483,11 @@
 	/* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */
 	set_nbcfg_enable_bits_8(nb_dev, 0x97, (u8)(~0x1F), 0xE0);
 
-	/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
-	 * force this BAR as mem type in rs780_gfx.c */
-	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
+	/* Reg8Ch[9] enables Gfx Debug BAR programming
+	 * Reg8Ch[10] enables Gfx Debug BAR operation
+	 * Enable programming of the debug bar now, but enable
+	 * operation only after it has been programmed */
+	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x02);
 }
 
 static void rs780_por_mc_index_init(device_t nb_dev)
Index: src/southbridge/amd/rs780/rs780_gfx.c
===================================================================
--- src/southbridge/amd/rs780/rs780_gfx.c	(revision 6011)
+++ src/southbridge/amd/rs780/rs780_gfx.c	(working copy)
@@ -39,6 +39,8 @@
 void set_pcie_reset(void);
 void set_pcie_dereset(void);
 
+extern uint64_t uma_memory_base, uma_memory_size;
+
 /* Trust the original resource allocation. Don't do it again. */
 #undef DONT_TRUST_RESOURCE_ALLOCATION
 //#define DONT_TRUST_RESOURCE_ALLOCATION
@@ -304,11 +306,15 @@
 	volatile u32 * pointer;
 	int i;
 	u16 command;
-	u32 value, sblk;
+	u32 value;
 	u16 deviceid, vendorid;
 	device_t nb_dev = dev_find_slot(0, 0);
 	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
 	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	static u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32};
+	static u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0};
+	static u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200};
+	static u16 memclk_lookup_fam10 [] = {200, 266, 333, 400, 533, 667, 800, 800};
 
 	/* We definetely will use this in future. Just leave it here. */
 	/*struct southbridge_amd_rs780_config *cfg =
@@ -339,6 +345,8 @@
 	*(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8);
 	*(GpuF0MMReg + 0x2c04/4) = ((value&0xff00)<<8);
 	*(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16);
+	*(GpuF0MMReg + 0xF774/4) = 0xffffffff;
+	*(GpuF0MMReg + 0xF770/4) = 0x00000001;
 	*(GpuF0MMReg + 0x2000/4) = 0x00000011;
 	*(GpuF0MMReg + 0x200c/4) = 0x00000020;
 	*(GpuF0MMReg + 0x2010/4) = 0x10204810;
@@ -352,21 +360,26 @@
 	*(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4);
 	/* Force allow LDT_STOP Cool'n'Quiet workaround. */
 	*(GpuF0MMReg + 0x655c/4) |= 1<<4;
+
+	// disable write combining, needed for stability
+	*(GpuF0MMReg + 0x2000/4) = 0x00000010;
+	*(GpuF0MMReg + 0x2408/4) = 1 << 9;
+	*(GpuF0MMReg + 0x2000/4) = 0x00000011;
+
 	/* GFX_InitFBAccess finished. */
 
+#if (CONFIG_GFXUMA == 1) /* for UMA mode. */
 	/* GFX_StartMC. */
-#if (CONFIG_GFXUMA == 1) /* for UMA mode. */
-	/* MC_INIT_COMPLETE. */
-	set_nbmc_enable_bits(nb_dev, 0x2, 0, 1<<31);
-	/* MC_STARTUP, MC_POWERED_UP and MC_VMODE.*/
-	set_nbmc_enable_bits(nb_dev, 0x1, 1<<18, 1|1<<2);
-
-	set_nbmc_enable_bits(nb_dev, 0xb1, 0, 1<<6);
-	set_nbmc_enable_bits(nb_dev, 0xc3, 0, 1);
-	nbmc_write_index(nb_dev, 0x07, 0x18);
-	nbmc_write_index(nb_dev, 0x06, 0x00000102);
-	nbmc_write_index(nb_dev, 0x09, 0x40000008);
-	set_nbmc_enable_bits(nb_dev, 0x6, 0, 1<<31);
+	set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000004);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00040000, 0x00000000);
+	set_nbmc_enable_bits(nb_dev, 0xB1, 0xFFFF0000, 0x00000040);
+	set_nbmc_enable_bits(nb_dev, 0xC3, 0x00000000, 0x00000001);
+	set_nbmc_enable_bits(nb_dev, 0x07, 0xFFFFFFFF, 0x00000018);
+	set_nbmc_enable_bits(nb_dev, 0x06, 0xFFFFFFFF, 0x00000102);
+	set_nbmc_enable_bits(nb_dev, 0x09, 0xFFFFFFFF, 0x40000008);
+	set_nbmc_enable_bits(nb_dev, 0x06, 0x00000000, 0x80000000);
 	/* GFX_StartMC finished. */
 #else
 	/* for SP mode. */
@@ -418,77 +431,110 @@
 	vgainfo.sHeader.ucTableContentRevision = 2;
 
 #if (CONFIG_GFXUMA == 0) /* SP mode. */
+	// Side port support is incomplete, do not use it
+	// These parameters must match the motherboard
 	vgainfo.ulBootUpSidePortClock = 667*100;
-	vgainfo.ucMemoryType = 3;
+	vgainfo.ucMemoryType = 3;  // 3=ddr3 sp mem, 2=ddr2 sp mem
 	vgainfo.ulMinSidePortClock = 333*100;
 #endif
 
-	vgainfo.ulBootUpEngineClock = 500 * 100; /* set boot up GFX engine clock. */
-	vgainfo.ulReserved1[0] = 0;	vgainfo.ulReserved1[1] = 0;
-	value = pci_read_config32(k8_f2, 0x94);
-	printk(BIOS_DEBUG, "MEMCLK = %x\n", value&0x7);
-	vgainfo.ulBootUpUMAClock = 333 * 100; /* set boot up UMA memory clock. */
-	vgainfo.ulBootUpSidePortClock = 0; /* disable SP. */
-	vgainfo.ulMinSidePortClock = 0; /* disable SP. */
-	for(i=0; i<6; i++)
-		vgainfo.ulReserved2[i] = 0;
-	vgainfo.ulSystemConfig = 0;
-	//vgainfo.ulSystemConfig |= 1<<1 | 1<<3 | 1<<4 | 1<<5 | 1<<6 | 1<<7 | 1;
-	vgainfo.ulBootUpReqDisplayVector = 0; //?
-	vgainfo.ulOtherDisplayMisc = 0; //?
-	vgainfo.ulDDISlot1Config = 0x000c0011; //0; //VGA
-	//vgainfo.ulDDISlot1Config = 0x000c00FF; //0; //HDMI
-	vgainfo.ulDDISlot2Config = 0x00130022; //0; //?
-	vgainfo.ucMemoryType = 2;
-	/* UMA Channel Number: 1 or 2. */
-	vgainfo.ucUMAChannelNumber = 2;
-	vgainfo.ucDockingPinBit = 0; //?
-	vgainfo.ucDockingPinPolarity = 0; //?
-	vgainfo.ulDockingPinCFGInfo = 0; //?
-	vgainfo.ulCPUCapInfo = 3; /* K8. */
+	vgainfo.ulBootUpEngineClock = 500 * 100;	       	// setup option on reference BIOS, 500 is default
 
-	/* page 5-19 on BDG. */
-	vgainfo.usNumberOfCyclesInPeriod = 0x8019;
-	vgainfo.usMaxNBVoltage = 0x1a;
-	vgainfo.usMinNBVoltage = 0;
-	vgainfo.usBootUpNBVoltage = 0x1a;
+	// find the DDR memory frequency
+	if (is_family10h()) {
+		value = pci_read_config32(k8_f2, 0x94);		// read channel 0 DRAM Configuration High Register
+		if (extractbit(value, 14))			// if channel 0 disabled, channel 1 must have memory
+			value = pci_read_config32(k8_f2, 0x194);// read channel 1 DRAM Configuration High Register
+		vgainfo.ulBootUpUMAClock = memclk_lookup_fam10 [extractbits (value, 0, 2)] * 100;
+	}
+	if (is_family0Fh()) {
+		value = pci_read_config32(k8_f2, 0x94);
+		vgainfo.ulBootUpUMAClock = memclk_lookup_fam0F [extractbits (value, 20, 22)] * 100;
+	}
 
-	/* Get SBLink value (HyperTransport I/O Hub Link ID). */
-	value = pci_read_config32(k8_f0, 0x64);
-	sblk = (value >> 8) & 0x3;
-	printk(BIOS_DEBUG, "SBLINK = %d.\n", sblk);
+	/* UMA Channel Number: 1 or 2. */
+	vgainfo.ucUMAChannelNumber = 1;
+	if (is_family0Fh()) {
+		value = pci_read_config32(k8_f2, 0x90);
+	if (extractbit(value, 11))  // 128-bit mode
+		vgainfo.ucUMAChannelNumber = 2;
+	}
+	if (is_family10h()) {
+		u32 dch0 = pci_read_config32(k8_f2, 0x94);
+		u32 dch1 = pci_read_config32(k8_f2, 0x194);
+		if (extractbit(dch0, 14) == 0 && extractbit(dch1, 14) == 0) { // both channels enabled
+			value = pci_read_config32(k8_f2, 0x110);
+			if (extractbit(value, 4))  // ganged mode
+			vgainfo.ucUMAChannelNumber = 2;
+		}
+	}
+      
+	// processor type
+	if (is_family0Fh())
+		vgainfo.ulCPUCapInfo = 3;
+	if (is_family10h())
+		vgainfo.ulCPUCapInfo = 2;
 
 	/* HT speed */
-	value = pci_read_config32(nb_dev, 0xd0);
-	printk(BIOS_DEBUG, "NB HT speed = %x.\n", value);
-	value = pci_read_config32(k8_f0, 0x88 + (sblk * 0x20));
-	printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value);
-	vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */
+	value = pci_read_config8(nb_dev, 0xd1);
+	value = ht_freq_lookup [value] * 100;  // HT link frequency in MHz
+	vgainfo.ulHTLinkFreq = value * 100;    // HT frequency in units of 100 MHz
+	vgainfo.ulHighVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
+	vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
 
+	if (value <= 1800)
+		vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
+	else {
+		int sblink, cpuLnkFreqCap, nbLnkFreqCap;
+		value = pci_read_config32(k8_f0, 0x64);
+		sblink = extractbits(value, 8, 10);
+		cpuLnkFreqCap = pci_read_config16(k8_f0, 0x8a + sblink * 0x20);
+		nbLnkFreqCap = pci_read_config16(nb_dev, 0xd2);
+		if (cpuLnkFreqCap & nbLnkFreqCap & (1 << 10)) // if both 1800 MHz capable
+		vgainfo.ulLowVoltageHTLinkFreq = 1800*100;
+	}
+
 	/* HT width. */
-	value = pci_read_config32(nb_dev, 0xc8);
-	printk(BIOS_DEBUG, "HT width = %x.\n", value);
-	vgainfo.usMinHTLinkWidth = 16;
-	vgainfo.usMaxHTLinkWidth = 16;
-	vgainfo.usUMASyncStartDelay = 322;
-	vgainfo.usUMADataReturnTime = 86;
-	vgainfo.usLinkStatusZeroTime = 0x00c8; //0; //?
-	vgainfo.usReserved = 0;
-	vgainfo.ulHighVoltageHTLinkFreq = 100 * 100;
-	vgainfo.ulLowVoltageHTLinkFreq = 100 * 100;
-	vgainfo.usMaxUpStreamHTLinkWidth = 16;
-	vgainfo.usMaxDownStreamHTLinkWidth = 16;
-	vgainfo.usMinUpStreamHTLinkWidth = 16;
-	vgainfo.usMinDownStreamHTLinkWidth = 16;
-	for(i=0; i<97; i++)
-		vgainfo.ulReserved3[i] = 0;
+	value = pci_read_config8(nb_dev, 0xcb);
+	vgainfo.usMinDownStreamHTLinkWidth = 
+	vgainfo.usMaxDownStreamHTLinkWidth = 
+	vgainfo.usMinUpStreamHTLinkWidth = 
+	vgainfo.usMaxUpStreamHTLinkWidth =
+	vgainfo.usMinHTLinkWidth =
+	vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)];
 
+	if (is_family0Fh()) {
+		vgainfo.usUMASyncStartDelay = 322;
+		vgainfo.usUMADataReturnTime = 286;
+	}
+
+	if (is_family10h()) {
+		static u16 t0mult_lookup [] = {10, 50, 200, 2000};
+		int t0time, t0scale;
+		value = pci_read_config32(k8_f0, 0x16c);
+		t0time = extractbits(value, 0, 3);
+		t0scale = extractbits(value, 4, 5);
+		vgainfo.usLinkStatusZeroTime = t0mult_lookup [t0scale] * t0time;
+		vgainfo.usUMASyncStartDelay = 100;
+		if (vgainfo.ulHTLinkFreq < 1000 * 100) { // less than 1000 MHz
+			vgainfo.usUMADataReturnTime = 300;
+			vgainfo.usLinkStatusZeroTime = 6 * 100;   // 6us for GH in HT1 mode
+		}
+		else {
+			int lssel;
+			value = pci_read_config32(nb_dev, 0xac);
+			lssel = extractbits (value, 7, 8);
+			vgainfo.usUMADataReturnTime = 1300;
+			if (lssel == 0) vgainfo.usUMADataReturnTime = 150;
+		}
+	}
+
 	/* Transfer the Table to VBIOS. */
 	pointer = (u32 *)&vgainfo;
 	for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
 	{
 #if (CONFIG_GFXUMA == 1)
-		*GpuF0MMReg = 0x80000000 + 0x10000000 - 512 + i;
+		*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
 #else
 		*GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
 #endif
@@ -497,11 +543,22 @@
 
 	/* GFX_InitLate. */
 	{
-		u8 temp8;
-		temp8 = pci_read_config8(dev, 0x4);
-		//temp8 &= ~1; /* CIM clears this bit. Strangely, I can'd. */
-		temp8 |= 1<<1|1<<2;
-		pci_write_config8(dev, 0x4, temp8);
+		u32 temp;
+		temp = pci_read_config8(dev, 0x4);
+		//temp &= ~1; /* CIM clears this bit. Strangely, I can'd. */
+		temp |= 1<<1|1<<2;
+		pci_write_config8(dev, 0x4, temp);
+
+		// if the GFX debug bar is writable, then it has
+		// been programmed and can be safely enabled now
+		temp = pci_read_config32(nb_dev, 0x8c);
+
+		// if bits 1 (intgfx_enable) and 9 (gfx_debug_bar_enable)
+		// then enable gfx debug bar (set gxf_debug_decode_enable)
+		if (temp & 0x202)
+			temp |= (1 << 10);
+		pci_write_config32(nb_dev, 0x8c, temp);
+
 	}
 
 #ifdef DONT_TRUST_RESOURCE_ALLOCATION
@@ -584,7 +641,6 @@
 * Set registers in RS780 and CPU to enable the internal GFX.
 * Please refer to CIM source code and BKDG.
 */
-extern uint64_t uma_memory_base, uma_memory_size;
 
 static void rs780_internal_gfx_enable(device_t dev)
 {
@@ -637,7 +693,9 @@
 #if (CONFIG_GFXUMA == 1)
 	/* GFX_InitUMA. */
 	/* Copy CPU DDR Controller to NB MC. */
+	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
 	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
 	for (i = 0; i < 12; i++)
 	{
 		l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
@@ -646,24 +704,40 @@
 
 	l_dword = pci_read_config32(k8_f2, 0x80);
 	nbmc_write_index(nb_dev, 0x3c, l_dword);
-
 	l_dword = pci_read_config32(k8_f2, 0x94);
-	if(l_dword & (1<<22))
-		set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<16);
-	else
-		set_nbmc_enable_bits(nb_dev, 0x3c, 1<<16, 0);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<22))<<16);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
+	l_dword = pci_read_config32(k8_f2, 0x90);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
+   if (is_family10h())
+   {
+	   for (i = 0; i < 12; i++)
+	   {
+		   l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
+		   nbmc_write_index(nb_dev, 0x3d + i, l_dword);
+	   }
 
-	if(l_dword & (1<<8))
-		set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<17);
-	else
-		set_nbmc_enable_bits(nb_dev, 0x3c, 1<<17, 0);
+	   l_dword = pci_read_config32(k8_f2, 0x180);
+	   nbmc_write_index(nb_dev, 0x49, l_dword);
+	   l_dword = pci_read_config32(k8_f2, 0x194);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<22))<<16);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<< 8))<<17);
+	   l_dword = pci_read_config32(k8_f2, 0x190);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<10))<<18);
 
-	l_dword = pci_read_config32(k8_f2, 0x90);
-	if(l_dword & (1<<10))
-		set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<18);
-	else
-		set_nbmc_enable_bits(nb_dev, 0x3c, 1<<18, 0);
+	   l_dword = pci_read_config32(k8_f2, 0x110);
+	   nbmc_write_index(nb_dev, 0x4a, l_dword);
+	   l_dword = pci_read_config32(k8_f2, 0x114);
+	   nbmc_write_index(nb_dev, 0x4b, l_dword);
+	   l_dword = pci_read_config32(k8_f4, 0x44);
+	   set_nbmc_enable_bits(nb_dev, 0x4a, 0, !!(l_dword & (1<<22))<<24);
+	   l_dword = pci_read_config32(k8_f1, 0x40);
+	   nbmc_write_index(nb_dev, 0x4c, l_dword);
+	   l_dword = pci_read_config32(k8_f1, 0xf0);
+	   nbmc_write_index(nb_dev, 0x4d, l_dword);
+   }
 
+
 	/* Set UMA in the 780 side. */
 	/* UMA start address, size. */
 	/* The UMA starts at 0xC0000000 of internal RS780 address space
@@ -672,7 +746,7 @@
 	nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000);
 	nbmc_write_index(nb_dev, 0x11, uma_memory_base);
 	nbmc_write_index(nb_dev, 0x12, 0);
-	nbmc_write_index(nb_dev, 0xf0, 256);
+	nbmc_write_index(nb_dev, 0xf0, uma_memory_size >> 20);
 	/* GFX_InitUMA finished. */
 #else
 	/* GFX_InitSP. */
@@ -1016,7 +1090,7 @@
 	/* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX
 	 * REFCLK PAD can be driven by an external source. */
 	/* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */
-	set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 0 << 29 | 1 << 28);
+	set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28 | 1 << 26, 1 << 28);
 
 	/* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
 	/* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
Index: src/southbridge/amd/rs780/rs780_pcie.c
===================================================================
--- src/southbridge/amd/rs780/rs780_pcie.c	(revision 6011)
+++ src/southbridge/amd/rs780/rs780_pcie.c	(working copy)
@@ -221,6 +221,7 @@
 	printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
 	pci_write_config32(nb_dev, 0x1C, 0);	/* clear BAR3 address */
 	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3. */
+	set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 0);	/* disable bar3 decode */
 	ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
 }

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From ladeecabet at hotmail.com  Mon Nov  1 01:49:10 2010
From: ladeecabet at hotmail.com (Monte Cabet)
Date: Sun, 31 Oct 2010 17:49:10 -0700
Subject: [coreboot] Compaq Presario CQ50-115NR Notebook PC
Message-ID: <BLU0-SMTP2110D2C7853D26B7048A1AFD7480@phx.gbl>


  Product info page:
http://h10025.www1.hp.com/ewfrf/wc/document?cc=us&lc=en&docname=c01486798&product=3752693

lspci -tvnn:
$ lspci -tvnn
-[0000:00]-+-00.0  nVidia Corporation MCP78S [GeForce 8200] Memory 
Controller [10de:0754]
            +-01.0  nVidia Corporation Device [10de:075e]
            +-01.1  nVidia Corporation MCP78S [GeForce 8200] SMBus 
[10de:0752]
            +-01.3  nVidia Corporation MCP78S [GeForce 8200] 
Co-Processor [10de:0753]
            +-01.4  nVidia Corporation MCP78S [GeForce 8200] Memory 
Controller [10de:0568]
            +-02.0  nVidia Corporation MCP78S [GeForce 8200] OHCI USB 
1.1 Controller [10de:077b]
            +-02.1  nVidia Corporation MCP78S [GeForce 8200] EHCI USB 
2.0 Controller [10de:077c]
            +-04.0  nVidia Corporation MCP78S [GeForce 8200] OHCI USB 
1.1 Controller [10de:077d]
            +-04.1  nVidia Corporation MCP78S [GeForce 8200] EHCI USB 
2.0 Controller [10de:077e]
            +-06.0  nVidia Corporation MCP78S [GeForce 8200] IDE [10de:0759]
            +-07.0  nVidia Corporation MCP72XE/MCP72P/MCP78U/MCP78S High 
Definition Audio [10de:0774]
            +-08.0-[0000:01]--
            +-09.0  nVidia Corporation MCP78S [GeForce 8200] SATA 
Controller (non-AHCI mode) [10de:0ad0]
            +-0a.0  nVidia Corporation MCP77 Ethernet [10de:0760]
            +-0b.0-[0000:02]----00.0  nVidia Corporation C77 [GeForce 
8200M G] [10de:0845]
            +-14.0-[0000:07]----00.0  Atheros Communications Inc. AR5001 
Wireless Network Adapter [168c:001c]
            +-18.0  Advanced Micro Devices [AMD] Mobile K10 [Turion X2, 
Athlon X2, Sempron] HyperTransport Configuration [1022:1300]
            +-18.1  Advanced Micro Devices [AMD] Family 11h [Turion X2, 
Athlon X2, Sempron] Address Map [1022:1301]
            +-18.2  Advanced Micro Devices [AMD] Mobile K10 [Turion X2, 
Athlon X2, Sempron] DRAM Controller [1022:1302]
            +-18.3  Advanced Micro Devices [AMD] Mobile K10 [Turion X2, 
Athlon X2, Sempron] Miscellaneous Control [1022:1303]
            \-18.4  Advanced Micro Devices [AMD] Mobile K10 [Turion X2, 
Athlon X2, Sempron] Link Control [1022:1304]

superiotool -dV:
superiotool r3844
Probing for ALi Super I/O at 0x3f0...
   Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
   Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
   Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
   Failed. Returned data: vid=0x0000, id=0x11fc
Probing for ITE Super I/O (init=standard) at 0x2e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x2e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x2e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x4e...
   Failed. Returned data: id=0xfc11, rev=0x0
Probing for ITE Super I/O (init=it8761e) at 0x4e...
   Failed. Returned data: id=0xfc11, rev=0x0
Probing for ITE Super I/O (init=it8228e) at 0x4e...
   Failed. Returned data: id=0xfc11, rev=0x0
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
   Failed. Returned data: id=0xfc11, rev=0x0
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
   Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
   Failed. Returned data: sid=0xfc, srid=0xa2
Probing for NSC Super I/O at 0x15c...
   Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
   Failed. Returned data: id=0xfc, rev=0x11
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
   Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
   Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
   Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x89) at 0x4e...
   Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
   Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
   Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
No Super I/O found

flashrom -V:
flashrom v0.9.1-r946
No coreboot table found.
DMI string system-manufacturer: "Hewlett-Packard"
DMI string system-product-name: "Compaq Presario CQ50 Notebook PC"
DMI string system-version: "F.07"
DMI string baseboard-manufacturer: "Wistron"
DMI string baseboard-product-name: "360A"
DMI string baseboard-version: "08.36"
DMI string chassis-type: "Notebook"
Laptop detected via DMI
========================================================================
WARNING! You seem to be running flashrom on a laptop.
Laptops, notebooks and netbooks are difficult to support and we recommend
to use the vendor flashing utility. The embedded controller (EC) in these
machines often interacts badly with flashing.
See http://www.flashrom.org/Laptops for details.
========================================================================
This chipset supports the following protocols: Non-SPI.
WARNING: No chipset found. Flash detection will most likely fail.
Calibrating delay loop... 487M loops per second, 100 myus = 196 us. OK.
Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0x61, id2 
0x87, id1 is normal flash content, id2 is normal flash content
Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0x61, id2 
0x87, id1 is normal flash content, id2 is normal flash content
Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0x3c, id2 
0x40, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0x3c, id2 
0x40, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0xff, 
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is 
normal flash content
Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for Eon EN25B05T, 64 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for Eon EN25B10T, 128 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for Eon EN25B20T, 256 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for Eon EN25B40T, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0xff, 
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is 
normal flash content
Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0xff, 
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is 
normal flash content
Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x4e, 
id2 0x41, id1 parity violation, id1 is normal flash content, id2 is 
normal flash content
Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x4e, 
id2 0x41, id1 parity violation, id1 is normal flash content, id2 is 
normal flash content
Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50
Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50
Probing for Intel 28F001BX-B, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Intel 28F001BX-T, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Intel 28F004S5, 512 KB: probe_82802ab: id1 0x4e, id2 0x41
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x4e, id2 0x41
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x61, id2 0x87
Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type 
Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0x61, id2 0x87
Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41
Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0x3c, id2 
0x40, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0x3c, id2 
0x40, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0x61, id2 
0x87, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x07, id2 
0xbf, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x4e, id2 0x41
Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0x61, id2 
0x87, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0x61, id2 0x87
Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0x61, id2 
0x87, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip 
bus type SPI are incompatible.
Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, 
id1 parity violation, id1 is normal flash content, id2 is normal flash 
content
Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50
Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, 
id1 parity violation, id1 is normal flash content, id2 is normal flash 
content
Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, 
id1 parity violation, id1 is normal flash content, id2 is normal flash 
content
Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0x3c, id2 0x40, 
id1 parity violation, id1 is normal flash content, id2 is normal flash 
content
Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41
Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41
Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x61, id2 0x87
Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x61, id2 0x87
Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x4e, id2 0x41
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x61, id2 0x87
Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for SyncMOS S29C31004T, 512 KB: probe_jedec_common: id1 0x4e, 
id2 0x41, id1 parity violation, id1 is normal flash content, id2 is 
normal flash content
Probing for SyncMOS S29C51001T, 128 KB: probe_jedec_common: id1 0xf6, 
id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is 
normal flash content
Probing for SyncMOS S29C51002T, 256 KB: probe_jedec_common: id1 0xff, 
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is 
normal flash content
Probing for SyncMOS S29C51004T, 512 KB: probe_jedec_common: id1 0x4e, 
id2 0x41, id1 parity violation, id1 is normal flash content, id2 is 
normal flash content
Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Winbond W25x32, 4096 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Winbond W25x64, 8192 KB: skipped. Host bus type Non-SPI and 
chip bus type SPI are incompatible.
Probing for Winbond W29C011, 128 KB: probe_jedec_common: id1 0xf6, id2 
0x0d, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W29C020C, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W29C040P, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond 
W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky 
state. Use 'flashrom -c W29EE011' if you have a board with this chip.
Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x4e, id2 
0x41, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0x61, id2 
0x87, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W49F002U, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
flash content
Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jedec_common: id1 0x61, id2 
0x87, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct 
probe timing information, using default 10mS/40uS. probe_jedec_common: 
id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, 
id2 is normal flash content
Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type 
Non-SPI and chip bus type SPI are incompatible.
Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type 
Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus 
type Non-SPI and chip bus type SPI are incompatible.
Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type 
Non-SPI and chip bus type SPI are incompatible.
Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type 
Non-SPI and chip bus type SPI are incompatible.
Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI 
and chip bus type SPI are incompatible.
Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type 
Non-SPI and chip bus type SPI are incompatible.
Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus 
type Non-SPI and chip bus type SPI are incompatible.
Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus 
type Non-SPI and chip bus type SPI are incompatible.
No EEPROM/flash device found.
If you know which flash chip you have, and if this version of flashrom
supports a similar flash chip, you can try to force read your chip. Run:
flashrom -f -r -c similar_supported_flash_chip filename

Note: flashrom can never write when the flash chip isn't found 
automatically.

I posted all the info the FAQ said to post when asking of the mailing 
list; it does seem abit overkill, but I don't know what I'm looking 
at/for. I didn't see my laptop on the "Laptops" section of "Supported 
Motherboards". I did notice the top of flashrom that it said that since 
I want to flash my laptop's BIOS, I should use the factory tool (I 
cheated and used Win Vista as the OS when I'm really running Ubuntu 
10.10; 
http://h10025.www1.hp.com/ewfrf/wc/softwareDownloadIndex?softwareitem=ob-76825-1&lc=en&dlc=en&cc=us&os=2093&product=3752693). 
If there is any other information you require, please let me know as 
I'll do my best to provide it.

The question is if I can flash my BIOS and replace it with coreboot? Or 
is coreboot not mature enough to handle laptops and my mileage may vary?



From peter at stuge.se  Wed Nov  3 10:36:36 2010
From: peter at stuge.se (Peter Stuge)
Date: Wed, 3 Nov 2010 10:36:36 +0100
Subject: [coreboot] Compaq Presario CQ50-115NR Notebook PC
In-Reply-To: <BLU0-SMTP2110D2C7853D26B7048A1AFD7480@phx.gbl>
References: <BLU0-SMTP2110D2C7853D26B7048A1AFD7480@phx.gbl>
Message-ID: <20101103093636.3590.qmail@stuge.se>

Monte Cabet wrote:
> -[0000:00]-+-00.0  nVidia Corporation MCP78S [GeForce 8200] Memory Controller [10de:0754]
..
> The question is if I can flash my BIOS and replace it with
> coreboot? Or is coreboot not mature enough to handle laptops and
> my mileage may vary?

coreboot currently supports a few laptops based on the i945 chipset,
but unfortunately not yours.

NVIDIA chipsets are the least likely to ever be supported by coreboot
because NVIDIA doesn't release the required documentation.

flashrom may still work on your laptop, independently of coreboot.


//Peter



From svn at coreboot.org  Wed Nov  3 14:19:51 2010
From: svn at coreboot.org (repository service)
Date: Wed, 03 Nov 2010 14:19:51 +0100
Subject: [coreboot] [commit] r6014 - trunk/src/northbridge/amd/gx2
Message-ID: <E1PDdFn-00086D-5a@ra.coresystems.de>

Author: uwe
Date: Wed Nov  3 14:19:50 2010
New Revision: 6014
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6014

Log:
Clean up some comments and white space in gx2/northbridgeinit.c
and gx2/raminit.c.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/northbridge/amd/gx2/northbridgeinit.c
   trunk/src/northbridge/amd/gx2/raminit.c

Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/northbridgeinit.c	Tue Nov  2 22:24:29 2010	(r6013)
+++ trunk/src/northbridge/amd/gx2/northbridgeinit.c	Wed Nov  3 14:19:50 2010	(r6014)
@@ -22,26 +22,25 @@
 };
 
 struct gliutable gliu0table[] = {
-	{.desc_name=MSR_GLIU0_BASE1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=  0x0FFF80},		/*  0-7FFFF to MC*/
-	{.desc_name=MSR_GLIU0_BASE2,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},		/*  80000-9ffff to Mc*/
-	{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=  0x03},	/*  C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
-	{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi=  MSR_MC,.lo=  0x0},		/*  Catch and fix dynamicly.*/
-	{.desc_name=MSR_GLIU0_DMM,    .desc_type= BMO_DMM,.hi=  MSR_MC,.lo=  0x0},		/*  Catch and fix dynamicly.*/
-	{.desc_name=MSR_GLIU0_SMM,    .desc_type= BMO_SMM,.hi=  MSR_MC,.lo=  0x0},		/*  Catch and fix dynamicly.*/
+	{.desc_name=MSR_GLIU0_BASE1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=  0x0FFF80},		/* 0-7FFFF to MC */
+	{.desc_name=MSR_GLIU0_BASE2,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},	/* 80000-9ffff to Mc */
+	{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=  0x03},	/* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
+	{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi=  MSR_MC,.lo=  0x0},		/* Catch and fix dynamicly. */
+	{.desc_name=MSR_GLIU0_DMM,    .desc_type= BMO_DMM,.hi=  MSR_MC,.lo=  0x0},		/* Catch and fix dynamicly. */
+	{.desc_name=MSR_GLIU0_SMM,    .desc_type= BMO_SMM,.hi=  MSR_MC,.lo=  0x0},		/* Catch and fix dynamicly. */
 	{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
 	{.desc_name=GL_END,           .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };
 
-
 struct gliutable gliu1table[] = {
-	{.desc_name=MSR_GLIU1_BASE1,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},	/*  0-7FFFF to MC*/
-	{.desc_name=MSR_GLIU1_BASE2,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},	/*  80000-9ffff to Mc*/
-	{.desc_name=MSR_GLIU1_SHADOW,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03}, /*  C0000-Fffff split to MC and PCI (sub decode)*/
-	{.desc_name=MSR_GLIU1_SYSMEM,.desc_type=  R_SYSMEM,.hi=  MSR_GL0,.lo=  0x0},		/*  Catch and fix dynamicly.*/
-	{.desc_name=MSR_GLIU1_DMM,.desc_type=  BM_DMM,.hi=  MSR_GL0,.lo=  0x0},			/*  Catch and fix dynamicly.*/
-	{.desc_name=MSR_GLIU1_SMM,.desc_type=  BM_SMM,.hi=  MSR_GL0,.lo=  0x0},			/*  Catch and fix dynamicly.*/
+	{.desc_name=MSR_GLIU1_BASE1,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},	/* 0-7FFFF to MC */
+	{.desc_name=MSR_GLIU1_BASE2,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},	/* 80000-9ffff to Mc */
+	{.desc_name=MSR_GLIU1_SHADOW,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03},	/* C0000-Fffff split to MC and PCI (sub decode) */
+	{.desc_name=MSR_GLIU1_SYSMEM,.desc_type=  R_SYSMEM,.hi=  MSR_GL0,.lo=  0x0},		/* Catch and fix dynamicly. */
+	{.desc_name=MSR_GLIU1_DMM,.desc_type=  BM_DMM,.hi=  MSR_GL0,.lo=  0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=MSR_GLIU1_SMM,.desc_type=  BM_SMM,.hi=  MSR_GL0,.lo=  0x0},			/* Catch and fix dynamicly. */
 	{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
-	{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type=  SCIO,.hi=  (GL1_GLCP << 29) + 0x0,.lo=  0x033000F0},	/*  FooGlue FPU 0xF0*/
+	{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type=  SCIO,.hi=  (GL1_GLCP << 29) + 0x0,.lo=  0x033000F0},	/* FooGlue FPU 0xF0 */
 	{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };
 
@@ -54,18 +53,18 @@
 
 struct msrinit ClockGatingDefault [] = {
 	{GLIU0_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
-			/*  MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142*/
+	/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */
 	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},
 	{GLIU1_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
-	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},			/*  lotus #77.163*/
+	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},		/* lotus #77.163 */
 	{GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x0001}},
 	{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0155}},
 	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
 	{GLPCI_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
-	{FG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},			/* Always on*/
+	{FG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},		/* Always on */
 	{0xffffffff, 				{0xffffffff, 0xffffffff}},
 };
-	/*  All On*/
+	/*  All On */
 struct msrinit ClockGatingAllOn[] = {
 	{GLIU0_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
 	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0FFFFFFFF}},
@@ -79,7 +78,7 @@
  	{0xffffffff, 				{0xffffffff, 0xffffffff}},
 };
 
-	/*  Performance*/
+	/* Performance */
 struct msrinit ClockGatingPerformance[] = {
 	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},		/*  lotus #77.163*/
 	{GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x0001}},
@@ -87,19 +86,18 @@
 	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
 	{0xffffffff, 				{0xffffffff, 0xffffffff}},
 };
-/* */
-/*  SET GeodeLink PRIORITY*/
-/* */
+
+	/* SET GeodeLink PRIORITY */
 struct msrinit GeodeLinkPriorityTable [] = {
-	{CPU_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0220}},	/*  CPU Priority.*/
-	{DF_GLD_MSR_MASTER_CONF,	{.hi=0x00,.lo=0x0000}},	/*  DF Priority.*/
-	{VG_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0720}},	/*  VG Primary and Secondary Priority.*/
-	{GP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0010}},	/*  Graphics Priority.*/
-	{GLPCI_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0027}},	/*  GLPCI Priority + PID*/
-	{GLCP_GLD_MSR_CONF,		{.hi=0x00,.lo=0x0001}},	/*  GLCP Priority + PID*/
-	{VIP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0622}},	/*  VIP PID*/
-	{AES_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0013}},	/*  AES PID*/
-	{0x0FFFFFFFF, 			{0x0FFFFFFFF, 0x0FFFFFFFF}},	/*  END*/
+	{CPU_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0220}},		/* CPU Priority. */
+	{DF_GLD_MSR_MASTER_CONF,	{.hi=0x00,.lo=0x0000}},		/* DF Priority. */
+	{VG_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0720}},		/* VG Primary and Secondary Priority. */
+	{GP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0010}},		/* Graphics Priority. */
+	{GLPCI_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0027}},		/* GLPCI Priority + PID */
+	{GLCP_GLD_MSR_CONF,		{.hi=0x00,.lo=0x0001}},		/* GLCP Priority + PID */
+	{VIP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0622}},		/* VIP PID */
+	{AES_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0013}},		/* AES PID */
+	{0x0FFFFFFFF, 			{0x0FFFFFFFF, 0x0FFFFFFFF}},	/* END */
 };
 
 /* do we have dmi or not? assume NO per AMD */
@@ -111,7 +109,7 @@
 
 	msr.lo = gl->lo;
 	msr.hi = gl->hi;
-	wrmsr(gl->desc_name, msr);	// MSR - see table above
+	wrmsr(gl->desc_name, msr);	/* MSR - see table above */
 	printk(BIOS_DEBUG, "%s: write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 	/* they do this, so we do this */
 	msr = rdmsr(gl->desc_name);
@@ -131,10 +129,9 @@
 }
 
 /* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here.
-  * CLEAN ME UP
-   */
-/* yes, this duplicates later code, but it seems that is how they want it done.
-  */
+ * CLEAN ME UP
+ */
+/* yes, this duplicates later code, but it seems that is how they want it done. */
 static void
 SysmemInit(struct gliutable *gl)
 {
@@ -161,12 +158,12 @@
 	sizebytes &= 0xfff00000;
 	sizebytes |= 0x100;
 	msr.lo = sizebytes;
-	wrmsr(gl->desc_name, msr);	// MSR - see table above
+	wrmsr(gl->desc_name, msr);	/* MSR - see table above */
 	msr = rdmsr(gl->desc_name);
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 				gl->desc_name, msr.hi, msr.lo);
-
 }
+
 static void
 DMMGL0Init(struct gliutable *gl) {
 	msr_t msr;
@@ -189,11 +186,11 @@
 	msr.lo = DMM_OFFSET << 8;
 	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
 
-	wrmsr(gl->desc_name, msr);	// MSR - See table above
+	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
 	msr = rdmsr(gl->desc_name);
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
-
 }
+
 static void
 DMMGL1Init(struct gliutable *gl) {
 	msr_t msr;
@@ -212,10 +209,11 @@
 	printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
 	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
 
-	wrmsr(gl->desc_name, msr);	// MSR - See table above
+	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
 	msr = rdmsr(gl->desc_name);
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
+
 static void
 SMMGL0Init(struct gliutable *gl) {
 	msr_t msr;
@@ -239,10 +237,11 @@
 	msr.lo = SMM_OFFSET << 8;
 	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
 
-	wrmsr(gl->desc_name, msr);	// MSR - See table above
+	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
 	msr = rdmsr(gl->desc_name);
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
+
 static void
 SMMGL1Init(struct gliutable *gl) {
 	msr_t msr;
@@ -255,7 +254,7 @@
 	msr.lo = SMM_OFFSET << 8;
 	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
 
-	wrmsr(gl->desc_name, msr);	// MSR - See table above
+	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
 	msr = rdmsr(gl->desc_name);
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
@@ -268,69 +267,58 @@
 		default:
 			/* For Unknown types: Write then read MSR */
 			writeglmsr(gl);
-		case SC_SHADOW: /*  Check for a Shadow entry*/
+		case SC_SHADOW: /* Check for a Shadow entry */
 			ShadowInit(gl);
 			break;
 
-		case R_SYSMEM: /*  check for a SYSMEM entry*/
+		case R_SYSMEM: /* check for a SYSMEM entry */
 			SysmemInit(gl);
 			break;
 
-		case BMO_DMM: /*  check for a DMM entry*/
+		case BMO_DMM: /* check for a DMM entry */
 			DMMGL0Init(gl);
 			break;
 
-		case BM_DMM	: /*  check for a DMM entry*/
+		case BM_DMM	: /* check for a DMM entry */
 			DMMGL1Init(gl);
 			break;
 
-		case BMO_SMM	: /*  check for a SMM entry*/
+		case BMO_SMM	: /* check for a SMM entry */
 			SMMGL0Init(gl);
 			break;
 
-		case BM_SMM	: /*  check for a SMM entry*/
+		case BM_SMM	: /* check for a SMM entry */
 			SMMGL1Init(gl);
 			break;
 		}
 		gl++;
 	}
-
 }
-	/* ***************************************************************************/
-	/* **/
-	/* *	GLPCIInit*/
-	/* **/
-	/* *	Set up GLPCI settings for reads/write into memory*/
-	/* *	R0:  0-640KB,*/
-	/* *	R1:  1MB - Top of System Memory*/
-	/* *	R2: SMM Memory*/
-	/* *	R3: Framebuffer? - not set up yet*/
-	/* *	R4: ??*/
-	/* **/
-	/* *	Entry:*/
-	/* *	Exit:*/
-	/* *	Modified:*/
-	/* **/
-	/* ***************************************************************************/
+
+/*
+ * Set up GLPCI settings for reads/write into memory.
+ *
+ * R0:  0-640KB,
+ * R1:  1MB - Top of System Memory
+ * R2: SMM Memory
+ * R3: Framebuffer? - not set up yet
+ * R4: ??
+ */
 static void GLPCIInit(void){
 	struct gliutable *gl = 0;
 	int i;
 	msr_t msr;
 	int msrnum;
 
-	/* */
-	/*  R0 - GLPCI settings for Conventional Memory space.*/
-	/* */
-	msr.hi =  (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT		/*  640*/;
-	msr.lo =  0							/*  0*/;
+	/* R0 - GLPCI settings for Conventional Memory space. */
+	msr.hi =  (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;	/* 640 */
+	msr.lo =  0;						/* 0 */
 	msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
 	msrnum = GLPCI_RC0;
 	wrmsr(msrnum, msr);
 
-	/* */
-	/*  R1 - GLPCI settings for SysMem space.*/
-	/* */
-	/*  Get systop from GLIU0 SYSTOP Descriptor*/
+	/* R1 - GLPCI settings for SysMem space. */
+	/* Get systop from GLIU0 SYSTOP Descriptor */
 	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
 		if (gliu0table[i].desc_type == R_SYSMEM) {
 			gl = &gliu0table[i];
@@ -345,8 +333,8 @@
                  * translates to a base of 0x00100000 and top of 0xffbf0000
                  * base of 1M and top of around 256M
 		 */
-		/* we have to create a page-aligned (4KB page) address for base and top */
-		/* So we need a high page aligned addresss (pah) and low page aligned address (pal)
+		/* we have to create a page-aligned (4KB page) address for base and top
+		 * So we need a high page aligned addresss (pah) and low page aligned address (pal)
 		 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
 		 */
 		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
@@ -363,9 +351,7 @@
 		wrmsr(msrnum, msr);
 	}
 
-	/* */
-	/*  R2 - GLPCI settings for SMM space.*/
-	/* */
+	/* R2 - GLPCI settings for SMM space. */
 	msr.hi =  ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
 	msr.lo =  (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
 	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
@@ -373,9 +359,9 @@
 	wrmsr(msrnum, msr);
 
 	/* this is done elsewhere already, but it does no harm to do it more than once */
-	/*  write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
-	msr.lo =  0x021212121								/*  cache disabled and write serialized*/;
-	msr.hi =  0x021212121								/*  cache disabled and write serialized*/;
+	/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */
+	msr.lo =  0x021212121;		/* cache disabled and write serialized */
+	msr.hi =  0x021212121;		/* cache disabled and write serialized */
 
 	msrnum = CPU_RCONF_A0_BF;
 	wrmsr(msrnum, msr);
@@ -386,7 +372,7 @@
 	msrnum = CPU_RCONF_E0_FF;
 	wrmsr(msrnum, msr);
 
-	/*  Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup.*/
+	/* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */
 	msrnum = GLPCI_A0_BF;
 	msr.hi =  0x35353535;
 	msr.lo =  0x35353535;
@@ -402,29 +388,26 @@
 	msr.lo =  0x35353535;
 	wrmsr(msrnum, msr);
 
-	/*  Set WSREQ*/
+	/* Set WSREQ */
 	msrnum = CPU_DM_CONFIG0;
 	msr = rdmsr(msrnum);
 	msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
-	msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT	;	/*  reduce to 1 for safe mode.*/
+	msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT	;	/* reduce to 1 for safe mode. */
 	wrmsr(msrnum, msr);
 
 	/* we are ignoring the 5530 case for now, and perhaps forever. */
 
-	/* */
-	/* 5535 NB Init*/
-	/* */
+	/* 5535 NB Init */
 	msrnum = GLPCI_ARB;
 	msr = rdmsr(msrnum);
 	msr.hi |=  GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
 	msr.lo |=  GLPCI_ARB_LOWER_IIE_SET;
 	wrmsr(msrnum, msr);
 
-
 	msrnum = GLPCI_CTRL;
 	msr = rdmsr(msrnum);
 
-	msr.lo |=  GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; 	/*   (Out will be disabled in CPUBUG649 for < 2.0 parts .)*/
+	msr.lo |=  GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; 	/* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
 	msr.lo |=  GLPCI_CTRL_LOWER_LDE_SET;
 
 	msr.lo &=  ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
@@ -449,37 +432,23 @@
 	msr.hi |=  0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
 	wrmsr(msrnum, msr);
 
-
-	/*  Set GLPCI Latency Timer.*/
+	/* Set GLPCI Latency Timer. */
 	msrnum = GLPCI_CTRL;
 	msr = rdmsr(msrnum);
-	msr.hi |=  0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; 	/*  Change once 1.x is gone.*/
+	msr.hi |=  0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; 	/* Change once 1.x is gone. */
 	wrmsr(msrnum, msr);
 
-	/*  GLPCI_SPARE*/
+	/* GLPCI_SPARE */
 	msrnum = GLPCI_SPARE;
 	msr = rdmsr(msrnum);
 	msr.lo &=  ~ 0x7;
 	msr.lo |=  GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
 	wrmsr(msrnum, msr);
-
 }
 
-
-
-	/* ***************************************************************************/
-	/* **/
-	/* *	ClockGatingInit*/
-	/* **/
-	/* *	Enable Clock Gating.*/
-	/* **/
-	/* *	Entry:*/
-	/* *	Exit:*/
-	/* *	Modified:*/
-	/* **/
-	/* ***************************************************************************/
-static void
-ClockGatingInit (void){
+/* Enable Clock Gating. */
+static void ClockGatingInit (void)
+{
 	msr_t msr;
 	struct msrinit *gating = ClockGatingDefault;
 	int i;
@@ -511,14 +480,13 @@
 		msr.lo |= gating->msr.lo;
 		printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to  0x%08x:0x%08x\n", __func__,
 			gating->msrnum, msr.hi, msr.lo);
-		wrmsr(gating->msrnum, msr);	// MSR - See the table above
+		wrmsr(gating->msrnum, msr);	/* MSR - See the table above */
 		gating +=1;
 	}
-
 }
 
-static void
-GeodeLinkPriority(void){
+static void GeodeLinkPriority(void)
+{
 	msr_t msr;
 	struct msrinit *prio = GeodeLinkPriorityTable;
 	int i;
@@ -531,17 +499,16 @@
 		msr.lo |= prio->msr.lo;
 		printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
 			prio->msrnum, msr.hi, msr.lo);
-		wrmsr(prio->msrnum, msr);	// MSR - See the table above
+		wrmsr(prio->msrnum, msr);	/* MSR - See the table above */
 		prio +=1;
 	}
 }
 
-
-
 /*
- *	Get the GLIU0 shadow register settings
- *	If the setShadow function is used then all shadow descriptors
- *	  will stay sync'ed.
+ * Get the GLIU0 shadow register settings.
+ *
+ * If the setShadow function is used then all shadow descriptors
+ * will stay sync'ed.
  */
 static uint64_t getShadow(void)
 {
@@ -550,83 +517,81 @@
 	return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
 }
 
-
 /*
- *	Set the cache RConf registers for the memory hole.
- *	Keeps all cache shadow descriptors sync'ed.
- *	This is part of the PCI lockup solution
- *	Entry: EDX:EAX is the shadow settings
+ * Set the cache RConf registers for the memory hole.
+ *
+ * Keeps all cache shadow descriptors sync'ed.
+ * This is part of the PCI lockup solution.
+ *
+ * Entry: EDX:EAX is the shadow settings.
  */
 static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
 {
-	// ok this is whacky bit translation time.
+	/* ok this is whacky bit translation time. */
 	int bit;
 	uint8_t shadowByte;
 	msr_t msr;
 	shadowByte = (uint8_t) (shadowLo >> 16);
 
-	// load up D000 settings in edx.
+	/* load up D000 settings in edx. */
 	for (bit = 8; (bit > 4); bit--) {
 		msr.hi <<= 8;
-		msr.hi |= 1;						// cache disable PCI/Shadow memory
+		msr.hi |= 1;				/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
-			msr.hi |= 0x20;					// write serialize PCI memory
+			msr.hi |= 0x20;			/* write serialize PCI memory */
 	}
 
-	// load up C000 settings in eax.
+	/* load up C000 settings in eax. */
 	for ( ; bit; bit--) {
 		msr.lo <<= 8;
-		msr.lo |= 1;						// cache disable PCI/Shadow memory
+		msr.lo |= 1;				/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
-			msr.lo |= 0x20;					// write serialize PCI memory
+			msr.lo |= 0x20;			/* write serialize PCI memory */
 	}
 
 	wrmsr(CPU_RCONF_C0_DF, msr);
 
 	shadowByte = (uint8_t) (shadowLo >> 24);
 
-	// load up F000 settings in edx.
+	/* load up F000 settings in edx. */
 	for (bit = 8; (bit > 4); bit--) {
 		msr.hi <<= 8;
-		msr.hi |= 1;						// cache disable PCI/Shadow memory
+		msr.hi |= 1;				/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
-			msr.hi |= 0x20;					// write serialize PCI memory
+			msr.hi |= 0x20;			/* write serialize PCI memory */
 	}
 
-	// load up E000 settings in eax.
+	/* load up E000 settings in eax. */
 	for ( ; bit; bit--) {
 		msr.lo <<= 8;
-		msr.lo |= 1;						// cache disable PCI/Shadow memory
+		msr.lo |= 1;				/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
-			msr.lo |= 0x20;					// write serialize PCI memory
+			msr.lo |= 0x20;			/* write serialize PCI memory */
 	}
 
 	wrmsr(CPU_RCONF_E0_FF, msr);
 }
 
-
 /*
- *	Set the GLPCI registers for the memory hole.
- *	Keeps all cache shadow descriptors sync'ed.
- *	Entry: EDX:EAX is the shadow settings
+ * Set the GLPCI registers for the memory hole.
+ * Keeps all cache shadow descriptors sync'ed.
+ * Entry: EDX:EAX is the shadow settings
  */
 static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
 {
 	msr_t msr;
 
-// Set the Enable Register.
-
+	/* Set the Enable Register. */
 	msr = rdmsr(GLPCI_REN);
 	msr.lo &= 0xFFFF00FF;
 	msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8);
 	wrmsr(GLPCI_REN, msr);
 }
 
-
 /*
- *	Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
- *	Keeps all shadow descriptors sync'ed.
- *	Entry: EDX:EAX is the shadow settings
+ * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
+ * Keeps all shadow descriptors sync'ed.
+ * Entry: EDX:EAX is the shadow settings
  */
 static void setShadow(uint64_t shadowSettings)
 {
@@ -647,50 +612,34 @@
 
 				msr = rdmsr(pTable->desc_name);
 				msr.lo = (uint32_t) shadowSettings;
-				msr.hi &= 0xFFFF0000;		// maintain PDID in upper EDX
+				msr.hi &= 0xFFFF0000;		/* maintain PDID in upper EDX */
 				msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF;
-				wrmsr(pTable->desc_name, msr);	// MSR - See the table above
+				wrmsr(pTable->desc_name, msr);	/* MSR - See the table above */
 
 			}
 		}
 	}
 }
 
-/**************************************************************************
- *
- *	shadowRom
- *
- *	Set up a stack for ease of further testing
- *
- *	Entry:
- *	Exit:
- *	Destroys:
- *
- **************************************************************************/
-static void
-shadowRom(void)
+/* Set up a stack for ease of further testing. */
+static void shadowRom(void)
 {
 	uint64_t shadowSettings = getShadow();
-	shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL;	// Disable read & writes
-	shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL;	// Enable reads for C0000-FFFFF
+	shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL;	/* Disable read & writes */
+	shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL;	/* Enable reads for C0000-FFFFF */
 	setShadow(shadowSettings);
 }
 
-
-
-/***************************************************************************
- *
- * RCONFInit
- *	  Set up RCONF_DEFAULT and any other RCONF registers needed
- *
- *  DEVRC_RCONF_DEFAULT:
- *  ROMRC(63:56) = 04h	 ; write protect ROMBASE
- *  ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
- *  DEVRC(35:28) =  39h	 ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
- *  SYSTOP(27:8) = top of system memory
- *  SYSRC(7:0) = 00h 		 ; writeback, can set to 08h to make writethrough
+/*
+ * Set up RCONF_DEFAULT and any other RCONF registers needed.
  *
- ***************************************************************************/
+ * DEVRC_RCONF_DEFAULT:
+ * ROMRC(63:56) = 04h	 ; write protect ROMBASE
+ * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
+ * DEVRC(35:28) =  39h	 ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
+ * SYSTOP(27:8) = top of system memory
+ * SYSRC(7:0) = 00h 		 ; writeback, can set to 08h to make writethrough
+ */
 #define SYSMEM_RCONF_WRITETHROUGH 8
 #define DEVRC_RCONF_DEFAULT 0x21
 #define ROMBASE_RCONF_DEFAULT 0xFFFC0000
@@ -712,11 +661,11 @@
 		}
 	}
 	if (gl == 0) {
-		post_code(0xCE);		/* POST_RCONFInitError */
+		post_code(0xCE);	/* POST_RCONFInitError */
 		while (1);
 	}
 
-// sysdescfound:
+/* sysdescfound: */
 	/* found the descriptor... get its contents */
 	msr = rdmsr(gl->desc_name);
 
@@ -725,26 +674,26 @@
 	 */
 	msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);
 	msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
-	msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT;	// 8
+	msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT;	/* 8 */
 
-	// Set Default SYSMEM region properties
-	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	// 8 (or ~8)
+	/* Set Default SYSMEM region properties */
+	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	/* 8 (or ~8) */
 
-	// Set PCI space cache properties
-	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);	// only need the bottom bits and lets clean the rest of edx
+	/* Set PCI space cache properties */
+	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);	/* only need the bottom bits and lets clean the rest of edx */
 	msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
 
-	// Set the ROMBASE. This is usually FFFC0000h
+	/* Set the ROMBASE. This is usually FFFC0000h */
 	msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
 
-	// Set ROMBASE cache properties.
+	/* Set ROMBASE cache properties. */
 	msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
 
-	// now program RCONF_DEFAULT
+	/* now program RCONF_DEFAULT */
 	wrmsr(CPU_RCONF_DEFAULT, msr);
 
-	// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
-	// Set to match system memory cache properties.
+	/* RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. */
+	/* Set to match system memory cache properties. */
 	msr = rdmsr(CPU_RCONF_DEFAULT);
 	SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
 	msr = rdmsr(CPU_RCONF_BYPASS);
@@ -752,21 +701,8 @@
 	wrmsr(CPU_RCONF_BYPASS, msr);
 }
 
-
-/* ***************************************************************************/
-/* **/
-/* *	northBridgeInit*/
-/* **/
-/* *	Core Logic initialization:  Host bridge*/
-/* **/
-/* *	Entry:*/
-/* *	Exit:*/
-/* *	Modified:*/
-/* **/
-/* ***************************************************************************/
-
-void
-northbridgeinit(void)
+/* Core Logic initialization: Host bridge. */
+void northbridgeinit(void)
 {
 	msr_t msr;
 	int i;
@@ -779,22 +715,23 @@
 
 	shadowRom();
 
-	// GeodeROM ensures that the BIOS waits the required 1 second before
-	// allowing anything to access PCI
+	/* GeodeROM ensures that the BIOS waits the required 1 second before */
+	/* allowing anything to access PCI */
 	// PCIDelay();
 
 	RCONFInit();
 
-	// The cacheInit function in GeodeROM tests cache and, among other things,
-	// makes sure all INVD instructions are treated as WBINVD.  We do this
-	// because we've found some programs which require this behavior.
-	// That subset of cacheInit() is implemented here:
+	/* The cacheInit function in GeodeROM tests cache and, among other things,
+	 * makes sure all INVD instructions are treated as WBINVD.  We do this
+	 * because we've found some programs which require this behavior.
+	 * That subset of cacheInit() is implemented here:
+	 */
 	msr = rdmsr(CPU_DM_CONFIG0);
 	msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
 	wrmsr(CPU_DM_CONFIG0, msr);
 
-	/*  Now that the descriptor to memory is set up.*/
-	/*  The memory controller needs one read to synch its lines before it can be used.*/
+	/* Now that the descriptor to memory is set up. */
+	/* The memory controller needs one read to synch its lines before it can be used. */
 	i = *(int *) 0;
 
 	GLPCIInit();

Modified: trunk/src/northbridge/amd/gx2/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/raminit.c	Tue Nov  2 22:24:29 2010	(r6013)
+++ trunk/src/northbridge/amd/gx2/raminit.c	Wed Nov  3 14:19:50 2010	(r6014)
@@ -80,12 +80,13 @@
 	dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
 	banner("SPDNUMROWS");
 
-	/*; Field: DIMM size
-	 *; EEPROM byte usage: (3)  Number of Row Addresses
-	 *;                                       (4)  Number of Column Addresses
-	 *;                                       (5)  Number of DIMM Banks
-	 *;                                       (31) Module Bank Density
-	 *; Size = Module Density * Module Banks
+	/* Field: DIMM size
+	 * EEPROM byte usage:
+	 *   (3)  Number of Row Addresses
+	 *   (4)  Number of Column Addresses
+	 *   (5)  Number of DIMM Banks
+	 *   (31) Module Bank Density
+	 * Size = Module Density * Module Banks
 	 */
 	if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
 	    || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
@@ -100,7 +101,7 @@
 	dimm_size |= (dimm_size << 8);	/* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
 	dimm_size &= 0x01FC;	/* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
 
-	/*       Module Density * Module Banks */
+	/* Module Density * Module Banks */
 	dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;	/* shift to multiply by # DIMM banks */
 	banner("BEFORT CTZ");
 	dimm_size = __builtin_ctz(dimm_size);
@@ -113,27 +114,32 @@
 	dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
 	banner("PAGESIZE");
 
-/*; Field: PAGE size
-*; EEPROM byte usage: (4)  Number of Column Addresses
-*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
-*
-*; But this really works by magic.
-*; If ma[11:0] is the memory address pins, and pa[13:0] is the physical column address
-*; that MC generates, here is how the MC assigns the pa onto the ma pins:
-*
-*;ma	11	10	09	08	07	06	05	04	03	02	01	00
-*;--------------------------------------------------------------------------------------------------------------------------------------
-*;pa						09	08	07	06	05	04	03	(7 col addr bits = 1K page size)
-*;pa					10	09	08	07	06	05	04	03	(8 col addr bits = 2K page size)
-*;pa				11	10	09	08	07	06	05	04	03	(9 col addr bits = 4K page size)
-*;pa			12	11	10	09	08	07	06	05	04	03	(10 col addr bits = 8K page size)
-*;pa	13	AP	12	11	10	09	08	07	06	05	04	03	(11 col addr bits = 16K page size)
-*; *AP=autoprecharge bit
-*
-*; Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
-*; so lower 3 address bits are dont_cares.So from the table above,
-*; it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
-*; it adds 3 to get 10, then does 2^10=1K.  Get it?*/
+/*
+ * Field: PAGE size
+ * EEPROM byte usage: (4)  Number of Column Addresses
+ * PageSize = 2^# Column Addresses * Data width in bytes
+ *                                   (should be 8bytes for a normal DIMM)
+ *
+ * But this really works by magic.
+ * If ma[11:0] is the memory address pins, and pa[13:0] is the physical column
+ * address that MC generates, here is how the MC assigns the pa onto the
+ * ma pins:
+ *
+ * ma  11 10 09 08 07 06 05 04 03 02 01 00
+ * ---------------------------------------
+ * pa                 09 08 07 06 05 04 03  (7 col addr bits = 1K page size)
+ * pa              10 09 08 07 06 05 04 03  (8 col addr bits = 2K page size)
+ * pa           11 10 09 08 07 06 05 04 03  (9 col addr bits = 4K page size)
+ * pa        12 11 10 09 08 07 06 05 04 03  (10 col addr bits = 8K page size)
+ * pa  13 AP 12 11 10 09 08 07 06 05 04 03  (11 col addr bits = 16K page size)
+ *
+ * (AP = autoprecharge bit)
+ *
+ * Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
+ * so lower 3 address bits are dont_cares. So from the table above,
+ * it's easier to see what the old code is doing: if for example,
+ * #col_addr_bits=7(06h), it adds 3 to get 10, then does 2^10=1K.
+ */
 
 	spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
 	banner("MAXCOLADDR");
@@ -269,26 +275,25 @@
 
 static void setCAS(void)
 {
-/*;*****************************************************************************
-;*
-;*	setCAS
-;*	EEPROM byte usage: (18) SDRAM device attributes - CAS latency
-;*	EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
-;*	EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
-;*
-;*	The CAS setting is based on the information provided in each DIMMs SPD.
-;*	 The speed at which a DIMM can run is described relative to the slowest
-;*	 CAS the DIMM supports. Each speed for the relative CAS settings is
-;*	 checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
-;*	 speed, the CAS setting	 is removed from the list of good settings for
-;*	 the DIMM. This is done for both DIMMs and the lists are compared to
-;*	 find the lowest common CAS latency setting. If there are no CAS settings
-;*	 in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
-;*
-;*	Entry:
-;*	Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
-;*	Destroys: We really use everything !
-;*****************************************************************************/
+/*
+ *	setCAS
+ *	EEPROM byte usage: (18) SDRAM device attributes - CAS latency
+ *	EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
+ *	EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
+ *
+ *	The CAS setting is based on the information provided in each DIMMs SPD.
+ *	 The speed at which a DIMM can run is described relative to the slowest
+ *	 CAS the DIMM supports. Each speed for the relative CAS settings is
+ *	 checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
+ *	 speed, the CAS setting	 is removed from the list of good settings for
+ *	 the DIMM. This is done for both DIMMs and the lists are compared to
+ *	 find the lowest common CAS latency setting. If there are no CAS settings
+ *	 in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
+ *
+ *	Entry:
+ *	Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
+ *	Destroys: We really use everything !
+ */
 	uint16_t glspeed;
 	uint8_t spd_byte, casmap0, casmap1;
 	msr_t msr;
@@ -298,7 +303,7 @@
 	casmap0 = getcasmap(DIMM0, glspeed);
 	casmap1 = getcasmap(DIMM1, glspeed);
 
-	/*********************	CAS_LAT MAP COMPARE	***************************/
+	/* CAS_LAT MAP COMPARE */
 	if (casmap0 == 0) {
 		spd_byte = CASDDR[__builtin_ctz(casmap1)];
 	} else if (casmap1 == 0) {
@@ -468,7 +473,7 @@
 	uint8_t spd_byte;
 
 	banner("sdram_set_spd_register");
-	post_code(POST_MEM_SETUP);	// post_70h
+	post_code(POST_MEM_SETUP);	/* post_70h */
 
 	spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
 	banner("Check DIMM 0");
@@ -486,23 +491,23 @@
 		hcf();
 	}
 
-	post_code(POST_MEM_SETUP2);	// post_72h
+	post_code(POST_MEM_SETUP2);	/* post_72h */
 	banner("Check DDR MAX");
 
 	/* Check that the memory is not overclocked. */
 	checkDDRMax();
 
 	/* Size the DIMMS */
-	post_code(POST_MEM_SETUP3);	// post_73h
+	post_code(POST_MEM_SETUP3);	/* post_73h */
 	banner("AUTOSIZE DIMM 0");
 	auto_size_dimm(DIMM0);
-	post_code(POST_MEM_SETUP4);	// post_74h
+	post_code(POST_MEM_SETUP4);	/* post_74h */
 	banner("AUTOSIZE DIMM 1");
 	auto_size_dimm(DIMM1);
 
 	/* Set CAS latency */
 	banner("set cas latency");
-	post_code(POST_MEM_SETUP5);	// post_75h
+	post_code(POST_MEM_SETUP5);	/* post_75h */
 	setCAS();
 
 	/* Set all the other latencies here (tRAS, tRP....) */
@@ -563,7 +568,7 @@
 	//print_debug("sdram_enable step 6\n");
 
 	/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
-	 * it is documented in LX datasheet  */
+	 * it is documented in LX datasheet */
 	/* load Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(MC_CF07_DATA);
 	msr.lo |=  ((0x01 << 27) | 0x01);



From uwe at hermann-uwe.de  Wed Nov  3 14:20:31 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 3 Nov 2010 14:20:31 +0100
Subject: [coreboot] [PATCH] Geode GX2 comment cleanup 1
In-Reply-To: <201011022232.39478.njacobs8@hetnet.nl>
References: <201011022232.39478.njacobs8@hetnet.nl>
Message-ID: <20101103132031.GO3256@greenwood>

On Tue, Nov 02, 2010 at 10:32:39PM +0100, Nils wrote:
> This patch cleans up some comments and white space in gx2/northbridgeinit.c 
> and gx2/raminit.c.
> 
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

Thanks, r6014 with some further cosmetic fixes I noticed.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Wed Nov  3 14:21:45 2010
From: svn at coreboot.org (repository service)
Date: Wed, 03 Nov 2010 14:21:45 +0100
Subject: [coreboot] [commit] r6015 - trunk/src/cpu/amd/model_gx2
Message-ID: <E1PDdHd-0001yA-LA@ra.coresystems.de>

Author: uwe
Date: Wed Nov  3 14:21:41 2010
New Revision: 6015
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6015

Log:
Clean up some more comments and white space in model_gx2/cpureginit.c.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/cpu/amd/model_gx2/cpureginit.c

Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c
==============================================================================
--- trunk/src/cpu/amd/model_gx2/cpureginit.c	Wed Nov  3 14:19:50 2010	(r6014)
+++ trunk/src/cpu/amd/model_gx2/cpureginit.c	Wed Nov  3 14:21:41 2010	(r6015)
@@ -1,134 +1,120 @@
 
-/* ***************************************************************************/
-/* *	cpuRegInit*/
-/* ***************************************************************************/
+/* cpuRegInit */
 void cpuRegInit (void)
 {
 	int msrnum;
 	msr_t msr;
-	/*  Turn on BTM for early debug based on setup. */
-	/*if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {*/
-	/*
-	 * The following is only for diagnostics mode; do not use for OLPC
-	 */
+	/* Turn on BTM for early debug based on setup. */
+	/* if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) { */
+	/* The following is only for diagnostics mode; do not use for OLPC */
 	if (0) {
-		/*  Set Diagnostic Mode */
+		/* Set Diagnostic Mode */
 		msrnum = CPU_GLD_MSR_DIAG;
 		msr.hi =  0;
 		msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
 		wrmsr(msrnum, msr);
 
-		/*  Set up GLCP to grab BTM data.*/
-		msrnum = 0x04C00000C;		/*  GLCP_DBGOUT MSR*/
+		/* Set up GLCP to grab BTM data. */
+		msrnum = 0x04C00000C;		/* GLCP_DBGOUT MSR */
 		msr.hi =  0x0;
-		msr.lo =  0x08;			/*  reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
-		wrmsr(msrnum, msr);		/*  exchange it to anything else to prevent this*/
+		msr.lo =  0x08;			/* reset value (SCOPE_SEL = 0) causes FIFO toshift out, */
+		wrmsr(msrnum, msr);		/* exchange it to anything else to prevent this */
 
-		/* ;Turn off debug clock*/
+		/* Turn off debug clock */
 		msrnum = 0x04C000016;		/* DBG_CLK_CTL*/
 		msr.lo =  0x00;			/* No clock*/
 		msr.hi =  0x00;
 		wrmsr(msrnum, msr);
 
-		/* ;Set debug clock to CPU*/
-		msrnum = 0x04C000016;		/* DBG_CLK_CTL*/
-		msr.lo =  0x01;			/* CPU CLOCK*/
+		/* Set debug clock to CPU */
+		msrnum = 0x04C000016;		/* DBG_CLK_CTL */
+		msr.lo =  0x01;			/* CPU CLOCK */
 		msr.hi =  0x00;
 		wrmsr(msrnum, msr);
 
-		/* ;Set fifo ctl to BTM bits wide*/
-		msrnum = 0x04C00005E;		/*  FIFO_CTL*/
-		msr.lo =  0x003880000;		/*  Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
-		wrmsr(msrnum, msr);	/*  Bit [23:21] are position (100 = CPU downto0)*/
-							/*  Bit [19] sets it up in slow data mode.*/
-
-		/* ;enable fifo loading - BTM sizing will constrain*/
-		/* ; only valid BTM packets to load - this action should always be on*/
-
-		msrnum = 0x04C00006F;		/*  GLCP ACTION7 - load fifo*/
-		msr.lo =  0x00000F000;		/*    Any nibble all 1's will always trigger*/
-		msr.hi =  0x000000000;		/* */
-		wrmsr(msrnum, msr);
-
-		/* ;start storing diag data in the fifo*/
-		msrnum = 0x04C00005F;		/* DIAG CTL*/
-		msr.lo =  0x080000000;		/*  enable actions*/
+		/* Set fifo ctl to BTM bits wide */
+		msrnum = 0x04C00005E;		/* FIFO_CTL */
+		msr.lo =  0x003880000;		/* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit) */
+		wrmsr(msrnum, msr);		/* Bit [23:21] are position (100 = CPU downto0) */
+						/* Bit [19] sets it up in slow data mode. */
+
+		/* enable fifo loading - BTM sizing will constrain */
+		/* only valid BTM packets to load - this action should always be on */
+		msrnum = 0x04C00006F;		/* GLCP ACTION7 - load fifo */
+		msr.lo =  0x00000F000;		/* Any nibble all 1's will always trigger */
 		msr.hi =  0x000000000;
 		wrmsr(msrnum, msr);
 
-		/*  Set up delay on data lines, so that the hold time*/
-		/*  is 1 ns.*/
-		msrnum = 0x04C00000D ;	/*  GLCP IO DELAY CONTROLS*/
+		/* start storing diag data in the fifo */
+		msrnum = 0x04C00005F;		/* DIAG CTL */
+		msr.lo =  0x080000000;		/* enable actions */
+		msr.hi =  0x000000000;
+		wrmsr(msrnum, msr);
+
+		/* Set up delay on data lines, so that the hold time */
+		/* is 1 ns. */
+		msrnum = 0x04C00000D ;		/* GLCP IO DELAY CONTROLS */
 		msr.lo =  0x082b5ad68;
-		msr.hi =  0x080ad6b57;	/*  RGB delay = 0x07*/
+		msr.hi =  0x080ad6b57;		/* RGB delay = 0x07 */
 		wrmsr(msrnum, msr);
 
-		/*  Set up DF to output diag information on DF pins.*/
+		/* Set up DF to output diag information on DF pins. */
 		msrnum = DF_GLD_MSR_MASTER_CONF;
 		msr.lo =  0x0220;
 		msr.hi = 0;
 		wrmsr(msrnum, msr);
 
-		msrnum = 0x04C00000C ;	/*  GLCP_DBGOUT MSR*/
+		msrnum = 0x04C00000C ;	/* GLCP_DBGOUT MSR */
 		msr.hi =  0x0;
-		msr.lo =  0x0;				/*  reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
+		msr.lo =  0x0;			/* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */
 		wrmsr(msrnum, msr);
 		/* end of code for BTM */
 	}
 
-	/*  Enable Suspend on Halt*/
+	/* Enable Suspend on Halt */
 	msrnum = CPU_XC_CONFIG;
 	msr = rdmsr(msrnum);
 	msr.lo |=  XC_CONFIG_SUSP_ON_HLT;
 	wrmsr(msrnum, msr);
 
-	/*  ENable SUSP and allow TSC to run in Suspend */
-	/*  to keep speed detection happy*/
+	/* ENable SUSP and allow TSC to run in Suspend */
+	/* to keep speed detection happy */
 	msrnum = CPU_BC_CONF_0;
 	msr = rdmsr(msrnum);
 	msr.lo |=  TSC_SUSP_SET | SUSP_EN_SET;
 	wrmsr(msrnum, msr);
 
-	/*  Setup throttling to proper mode if it is ever enabled.*/
+	/* Setup throttling to proper mode if it is ever enabled. */
 	msrnum = 0x04C00001E;
 	msr.hi =  0x000000000;
 	msr.lo =  0x00000603C;
 	wrmsr(msrnum, msr);
 
-
-/*  Only do this if we are building for 5535*/
-/* */
-/*  FooGlue Setup*/
-/* */
+/* Only do this if we are building for 5535 */
+/* FooGlue Setup */
 #if 1
-	/*  Enable CIS mode B in FooGlue*/
+	/* Enable CIS mode B in FooGlue */
 	msrnum = MSR_FG + 0x10;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~3;
-	msr.lo |= 2;			/*  ModeB*/
+	msr.lo |= 2;			/* ModeB */
 	wrmsr(msrnum, msr);
 #endif
 
-/* */
-/*  Disable DOT PLL. Graphics init will enable it if needed.*/
-/* */
+/* Disable DOT PLL. Graphics init will enable it if needed. */
 	msrnum = GLCP_DOTPLL;
 	msr = rdmsr(msrnum);
 	msr.lo |= DOTPPL_LOWER_PD_SET;
 	wrmsr(msrnum, msr);
 
-/* */
-/*  Enable RSDC*/
-/* */
+/* Enable RSDC */
 	msrnum = 0x1301 ;
 	msr = rdmsr(msrnum);
 	msr.lo |=  0x08;
 	wrmsr(msrnum, msr);
 
-/* */
-/*  Enable BTB*/
-/* */
-	/*  I hate to put this check here but it doesn't really work in cpubug.asm*/
+/* Enable BTB */
+	/* I hate to put this check here but it doesn't really work in cpubug.asm */
 	msrnum = MSR_GLCP+0x17;
 	msr = rdmsr(msrnum);
 	if (msr.lo >= CPU_REV_2_1){
@@ -138,10 +124,8 @@
 		wrmsr(msrnum, msr);
 	}
 
-/* */
-/*  FPU impercise exceptions bit*/
-/* */
-	/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
+/* FPU impercise exceptions bit */
+	/* if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) { */
 	{
 		msrnum = CPU_FPU_MSR_MODE;
 		msr = rdmsr(msrnum);
@@ -150,16 +134,13 @@
 	}
 
 #if 0
-	/* */
-	/*  Cache Overides*/
-	/* */
+	/* Cache Overides */
 	/* This code disables the data cache.  Don't execute this
 	 * unless you're testing something.
 	 */
-	/*  Allow NVRam to override DM Setup*/
-	/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
+	/* Allow NVRam to override DM Setup */
+	/* if (getnvram( TOKEN_CACHE_DM_MODE) != 1) { */
 	{
-
 		msrnum = CPU_DM_CONFIG0;
 		msr = rdmsr(msrnum);
 		msr.lo |=  DM_CONFIG0_LOWER_DCDIS_SET;
@@ -168,8 +149,8 @@
 	/* This code disables the instruction cache.  Don't execute
 	 * this unless you're testing something.
 	*/
-	/*  Allow NVRam to override IM Setup*/
-	/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
+	/* Allow NVRam to override IM Setup */
+	/* if (getnvram( TOKEN_CACHE_IM_MODE) ==1) { */
 	{
 		msrnum = CPU_IM_CONFIG;
 		msr = rdmsr(msrnum);



From uwe at hermann-uwe.de  Wed Nov  3 14:23:36 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 3 Nov 2010 14:23:36 +0100
Subject: [coreboot] [PATCH] Geode GX2 comment cleanup 2
In-Reply-To: <201011022232.59237.njacobs8@hetnet.nl>
References: <201011022232.59237.njacobs8@hetnet.nl>
Message-ID: <20101103132336.GP3256@greenwood>

On Tue, Nov 02, 2010 at 10:32:59PM +0100, Nils wrote:
> This patch  cleans up some more comments and white space in 
> model_gx2/cpureginit.c .
> 
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

Thanks, r6015. Minor request, please drop the "This patch ..." from the
patch descriptions, just say directly what it does (as we usually use
the description as commit message).

"Clean up stuff" looks better than "This patch cleans up stuff" in svn logs.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Wed Nov  3 14:24:30 2010
From: svn at coreboot.org (repository service)
Date: Wed, 03 Nov 2010 14:24:30 +0100
Subject: [coreboot] [commit] r6016 - trunk/src/northbridge/amd/gx2
Message-ID: <E1PDdKI-0005xK-Sa@ra.coresystems.de>

Author: uwe
Date: Wed Nov  3 14:24:29 2010
New Revision: 6016
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6016

Log:
Remove some unused code from gx2/raminit.c.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/northbridge/amd/gx2/raminit.c

Modified: trunk/src/northbridge/amd/gx2/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/raminit.c	Wed Nov  3 14:21:41 2010	(r6015)
+++ trunk/src/northbridge/amd/gx2/raminit.c	Wed Nov  3 14:24:29 2010	(r6016)
@@ -460,12 +460,6 @@
 	msr.lo &= ~0xC0;
 	msr.lo |= 0x0;		/* set refresh to 4SDRAM clocks */
 	wrmsr(msrnum, msr);
-
-	/* Memory Interleave: Set HOI here otherwise default is LOI */
-	/* msrnum = MC_CF8F_DATA;
-	   msr = rdmsr(msrnum);
-	   msr.hi |= CF8F_UPPER_HOI_LOI_SET;
-	   wrmsr(msrnum, msr); */
 }
 
 static void sdram_set_spd_registers(const struct mem_controller *ctrl)



From uwe at hermann-uwe.de  Wed Nov  3 14:24:47 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 3 Nov 2010 14:24:47 +0100
Subject: [coreboot] [PATCH] Remove unused code from Geode GX2
In-Reply-To: <201011022233.53488.njacobs8@hetnet.nl>
References: <201011022233.53488.njacobs8@hetnet.nl>
Message-ID: <20101103132447.GQ3256@greenwood>

On Tue, Nov 02, 2010 at 10:33:53PM +0100, Nils wrote:
> This patch removes some unused code from gx2/raminit.c .
> 
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

Thanks, r6016.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From ranma+coreboot at tdiedrich.de  Wed Nov  3 15:13:52 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 3 Nov 2010 15:13:52 +0100
Subject: [coreboot] [PATCH] simplify vt8237r_early_smbus.c (was: Re: [PATCH
	3/7] ASUS	M2V support (v2): simplify vt8237r_early_smbus.c
	(unchanged))
In-Reply-To: <4CD07E34.7040002@assembler.cz>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029115945.GK31684@yumi.tdiedrich.de>
	<4CD07E34.7040002@assembler.cz>
Message-ID: <20101103141352.GA31684@yumi.tdiedrich.de>

Rudolf Marek wrote:
> On 29.10.2010 13:59, Tobias Diedrich wrote:
>> Instead of duplicating the pci_locate_device calls multiple times,
>> add a get_vt8237_lpc() function.
>
> Yeah nice idea! Can I get separate patch for that? In the meanwhile do we 
> need to call the enablefidvid for "A" ? I think we dont scritly need 
> that. Maybe we can make it part of 2/7 and leave this just for the grand 
> get_vt8237_lpc() function? (and I can apply that before 2/7 so you don't 
> need to re-do the stuff)

Here you go:

Instead of duplicating the pci_locate_device calls multiple times,
add a get_vt8237_lpc() function.

The devid variable introduced to vt8237_sb_enable_fid_vid() in hunk 3
will come in handy in the patch adding vt8237a support.
I think it also makes the logic a bit more clear.
The other option would be to not use get_vt8237_lpc() in
vt8237_sb_enable_fid_vid() and leave that bit to the vt8237a support
patch.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>

---

Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c.orig	2010-11-03 14:54:54.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2010-11-03 15:00:34.000000000 +0100
@@ -134,6 +134,21 @@
 
 #define PSONREADY_TIMEOUT 0x7fffffff
 
+static device_t get_vt8237_lpc(void)
+{
+	device_t dev;
+
+	/* Power management controller */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+	if (dev != PCI_DEV_INVALID)
+		return dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+	return dev;
+}
+
 /**
  * Enable the SMBus on VT8237R-based systems.
  */
@@ -143,15 +158,9 @@
 	int loops;
 
 	/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			die("Power management controller not found\n");
-	}
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		die("Power management controller not found\n");
 
 	/* Make sure the RTC power well is up before touching smbus. */
 	loops = 0;
@@ -235,17 +244,15 @@
 void vt8237_sb_enable_fid_vid(void)
 {
 	device_t dev, devctl;
+	u16 devid;
 
 	/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			return;
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		return;
 
+	devid = pci_read_config16(dev, PCI_DEVICE_ID);
+	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) {
 		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 					   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
 
@@ -292,15 +292,9 @@
 	device_t dev;
 
 	/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			return;
-	}
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		return;
 
 	/* ROM decode last 1MB FFC00000 - FFFFFFFF. */
 	pci_write_config8(dev, 0x41, 0x7f);
@@ -316,15 +310,9 @@
 	print_debug("IN TEST WAKEUP\n");
 
 	/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			die("Power management controller not found\n");
-	}
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		die("Power management controller not found\n");
 
 	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
 	pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);




From ward at gnu.org  Wed Nov  3 17:56:04 2010
From: ward at gnu.org (Ward Vandewege)
Date: Wed, 3 Nov 2010 12:56:04 -0400
Subject: [coreboot] [PATCH] don't print too early on mcp55-based boards
In-Reply-To: <20101102222043.GN3256@greenwood>
References: <20101101160338.GA28294@countzero.vandewege.net>
	<20101101220141.592.qmail@stuge.se>
	<20101102222043.GN3256@greenwood>
Message-ID: <20101103165604.GA5218@countzero.vandewege.net>

On Tue, Nov 02, 2010 at 11:20:43PM +0100, Uwe Hermann wrote:
> I don't object to the patch, and we should probably fix this in all
> other southbridges, I think the same problem applies there.
> 
> But: the die() call itself also does a printk(), so that'll still hang
> if the error path is chosen (at that point it probably doesn't matter
> much, though, as we die anyway).

Right, I think it does not matter. If the die happens when printk is already
functional, great, if not it will hang there which is fine.

> I also agree that die() should have a POST code, preferrably something
> easy to remember. It already has a commented-out "//post_code(0xff);".
> Not sure why it's disabled, but I think it should be something other
> than 0xff, that's a bit too "special" for my taste.
> 
> We have "0xee: Not supposed to get here" as per documentation/POSTCODES,
> so maybe we can use 0xdd ("d" as in die), if that's not already used elsewhere.

So, thinking about this a little more, I'm not sure adding a post code to
'die' is a good idea. The problem with doing that is that it would clobber
any previous post codes, which might be a better indicator for what's going
wrong.

Perhaps a good way to deal with fatal runtime error conditions would be

  a) set a unique post code
  b) call die

in the assumption that die does not clobber the post code.

What do you think?

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From ranma+coreboot at tdiedrich.de  Wed Nov  3 18:03:44 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 3 Nov 2010 18:03:44 +0100
Subject: [coreboot] [PATCH 7/7] ASUS M2V support (v2): Add m2v mainboard
	directory	and files
In-Reply-To: <4CD08955.2020709@assembler.cz>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029121423.GO31684@yumi.tdiedrich.de>
	<4CD08955.2020709@assembler.cz>
Message-ID: <20101103170344.GC31684@yumi.tdiedrich.de>

Rudolf Marek wrote:
> On 29.10.2010 14:14, Tobias Diedrich wrote:
>> This adds the m2v directory to src/mainboards/asus and adjusts the Kconfig.
>> Note:
>>
>> I added pci irq routing setup based on pirq tables:
>> pci_fixup_irqs() in irq_tables.c
>>
>> I didn't see any existing functionality that will just take the pirq
>> information and use that to setup pci interrupts.
>> For example, in src/southbridge/via/vt8237r/vt8237r_lpc.c there is
>> some epia specific setup, which may really belong into the
>> corresponding mainboard directory...
>
> Hmm the legacy PIC routing may not work. In linux it could. I never tested that.

I currently working on cleaning up the mainboard part, but I tested
legacy pic routing (which is why I added this function), acpi w/o
apic, acpi with apic and mptables with apic, each in both XP and Linux.

>> +	/* Write SB IOAPIC. */
>> +	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
>> +				VT8237R_APIC_ID, IO_APIC_ADDR, 0);
>> +
>> +	/* Write NB IOAPIC. */
>> +	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
>> +				K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
>
> I never used the VIA system on multicore CPU, dunno what to do if we have 
> in fact more cpus... The IDs should be shifted then.

The IDs are currently hardcoded:

src/southbridge/via/k8t890/k8t890.h:
#define K8T890_APIC_ID          0x3
#define K8T890_APIC_BASE        0xfecc0000

src/southbridge/via/vt8237r/vt8237r.h
#define VT8237R_APIC_ID                  0x2

Which is good for up to dual-core, should be shifted up for
quad-core... Maybe we should change this to 0x10 and 0x11? (up to 16 cores)
Not sure how many bits are available for the ID by default, but I
saw that there is an enable bit for extended ID numbers somewhere.

>> +++ src/mainboard/asus/m2v/dsdt.asl	2010-10-29 14:07:37.000000000 +0200
>> @@ -0,0 +1,967 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2004 Nick Barker<Nick.Barker9 at btinternet.com>
>> + * Copyright (C) 2007 Rudolf Marek<r.marek at assembler.cz>
>> + * Copyright (C) 2010 Tobias Diedrich<ranma+coreboot at tdiedrich.de>
>
> Where you have taken parts of it? Some parts feel like AMD 7xx code? 
> Maybe we miss copyright here?

Portions (e.g. "Remember the OS' IRQ routing choice" are from
src/mainboard/ibase/mb899/acpi/), I'll add "Copyright (C) 2007-2009
coresystems GmbH"

>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; version 2 of the License.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> + */
>> +
>> +/*
>> + * ISA portions taken from QEMU acpi-dsdt.dsl.
>> + */
>> +
>> +DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
>> +{
>> +	/* Data to be patched by the BIOS during POST */
>> +	/* FIXME the patching is not done yet! */
>> +	/* Memory related values */
>> +	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
>> +	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr>>  16) */
>> +	Name(PBLN, 0x0)	/* Length of BIOS area */
>
> We dont do patching we do apcigen stuff instead into SSDT.

That's copied from gigabyte/ma78gm/dsdt.asl, I'll remove it, it
isn't used anyway.  As I already said elsewhere, I haven't cleaned
up the mainboard bits yet, especially the acpi stuff.

>> +
>> +	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
>
> This cannot be hardcoded.

Ok, then I'll add it to the SSDT generation code and use an
external.

>
>> +	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
>> +
>> +	/* global variables */
>> +	Name(APIC, 0)		// 0=>8259, 1=>IOAPIC
>> +	Name(LINX, 0)
>> +	Name(OSYS, 0x0000)
>> +
>> +	/* very generic stuff */
>> +
>> +	/* Port 80 POST */
>
>> +
>> +	OperationRegion (POST, SystemIO, 0x80, 1)
>> +	Field (POST, ByteAcc, Lock, Preserve)
>> +	{
>> +		DBG0, 8
>> +	}
>> +
>> +	Method (DEBG, 1, NotSerialized)
>> +	{
>> +		Store (Arg0, DBG0)
>> +	}
>> +
>
> I dont think you need this. My philosophy for ACPI code is: Put there 
> only what is needed even no extra bit more.

I thought the POST port might come in handy for debugging, but haven't used it
so far.

>> +	/* _PR CPU0 is dynamically supplied by SSDT */
>> +
>> +	/* For now only define 2 power states:
>> +	 *  - S0 which is fully on
>> +	 *  - S5 which is soft off
>> +	 * Any others would involve declaring the wake up methods.
>> +	 *
>> +	 * Package contents:
>> +	 * ofs len desc
>> +	 * 0   1   Value for PM1a_CNT.SLP_TYP register to enter this system state.
>> +	 * 1   1   Value for PM1b_CNT.SLP_TYP register to enter this system state. To enter any
>> +	 *         given state, OSPM must write the PM1a_CNT.SLP_TYP register before the
>> +	 *         PM1b_CNT.SLP_TYP register.
>> +	 * 2   2   Reserved
>> +	 */
>> +	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
>> +	Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
>> +
>> +	/*
>> +	 * Prepare to sleep
>> +	 *
>> +	 * Arg0 ? An Integer containing the value of the sleeping state (1 for S1, 2 for S2, etc.)
>> +	 * Return Value: None
>> +	 */
>> +	Method (_PTS, 1, NotSerialized)
>> +	{
>> +		// FIXME: Not implemented
>> +	}
>> +
>> +	/*
>> +	 * Transition to state
>> +	 *
>> +	 * Arg0 ? An Integer containing the value of the sleeping state (1 for S1, 2 for S2, etc.)
>> +	 * Return Value: None
>> +	 */
>> +	Method (_TTS, 1, NotSerialized)
>> +	{
>> +		// FIXME: Not implemented
>> +	}
>> +
>
> get rif of those please

I thought they were required methods, and put them in when I was
trying to get XP to boot with ACPI on. I'll remove them if they are
unneeded.

I probably will have to add them back when I look at suspend to ram support
though...

>> +			Device (PCIE)
>> +			{
>> +				Name (_HID, EisaId ("PNP0C02"))
>> +				Method (_CRS, 0, NotSerialized)
>> +				{
>> +					Name (TMP, ResourceTemplate () {
>> +						Memory32Fixed(ReadOnly,
>> +							0xE0000000,
>
> Sorry this cannot be hardcoded. I dont think you need this at all.

Win Vista/7 might need it for MMCONF.  I'll remove the hardcoding.
Linux is contempt with 0xe0000000-0xefffffff resered in either e820
or acpi, but one must be there for MMCONF / pcie extended config
space.

>> +			Name(CRES, ResourceTemplate() {
>> +				WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
>> +					0x0000,             // Granularity
>> +					0x0000,             // Range Minimum
>> +					0x00FF,             // Range Maximum
>> +					0x0000,             // Translation Offset
>> +					0x0100,             // Length
>> +					,,
>> +				)
>> +				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
>> +
>> +				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
>> +					0x0000,			/* address granularity */
>> +					0x0000,			/* range minimum */
>> +					0x0CF7,			/* range maximum */
>> +					0x0000,			/* translation */
>> +					0x0CF8			/* length */
>> +				)
>> +
>> +				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
>> +					0x0000,			/* address granularity */
>> +					0x0D00,			/* range minimum */
>> +					0xFFFF,			/* range maximum */
>> +					0x0000,			/* translation */
>> +					0xF300			/* length */
>> +				)
>> +
>> +				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
>> +				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
>> +				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
>> +				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
>> +				/* DRAM Memory from 1MB to TopMem */
>> +				Memory32Fixed(READWRITE, 0x00100000, 0x00000000, DMLO)  /* 1MB to TopMem */
>> +				Memory32Fixed(ReadOnly, 0xE0000000, 0x10000000, MCFG)   /* MMCONFIG area */
>> +				Memory32Fixed(READONLY, 0xF0000000, 0x10000000, MMIO)   /* PCI mapping space */
>> +
>> +#if 0
>> +				/* BIOS space just below 4GB */
>> +				DWORDMemory(
>> +					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
>> +					0x00,			/* Granularity */
>> +					0x00000000,		/* Min */
>> +					0x00000000,		/* Max */
>> +					0x00000000,		/* Translation */
>> +					0x00000001,		/* Max-Min, RLEN */
>> +					,,
>> +					PCBM
>> +				)
>> +
>> +				/* BIOS space just below 16EB */
>> +				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
>> +					0x00000000,		/* Granularity */
>> +					0x00000000,		/* Min */
>> +					0x00000000,		/* Max */
>> +					0x00000000,		/* Translation */
>> +					0x00000001,		/* Max-Min, RLEN */
>> +					,,
>> +					PEBM
>> +				)
>> +#endif
>> +
>> +				/* DRAM memory from 4GB to TopMem2 */
>> +				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
>> +					0x00000000,		/* Granularity */
>> +					0x00000000,		/* Min */
>> +					0x00000000,		/* Max */
>> +					0x00000000,		/* Translation */
>> +					0x00000001,		/* Max-Min, RLEN */
>> +					,,
>> +					DMHI
>> +				)
>> +
>> +			}) /* End Name(_SB.PCI0.CRES) */
>> +
>> +			External(TOM1) /* 32bit top of memory from SSDT */
>> +			External(TOM2) /* 64bit top of memory from SSDT */
>
>
> Maybe windows will accept only IO resorce without any memory resource. It 
> is PITA. Please try to investigate what we should relly tell here:

Declaring main memory there turned out to be a problem actually.
AFAICS the asus dsdt doesn't declare main memory in ACPI, E820 or
the efi equivalent is used for main memory map according to the ACPI standard
if I read it right.

What needs to be there:
Unused IO port and memory ranges which can be assigned to PCI/PCIE
devices.

If we don't want to declare all legacy ports, using IO 0x400-0xcf8
and 0xd00-0xffff, as well as memory TOM-0xdfffffff and
0xf0000000-first apic? should be ok.

> Name(CRES, ResourceTemplate() {
>                 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
>
>                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode,  
> EntireRange,
>                     0x0000,         /* address granularity */
>                     0x0000,         /* range minimum */
>                     0x0CF7,         /* range maximum */
>                     0x0000,         /* translation */
>                     0x0CF8          /* length */
>                 )
>
>                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode,  
> EntireRange,
>                     0x0000,         /* address granularity */
>                     0x0D00,         /* range minimum */
>                     0xFFFF,         /* range maximum */
>                     0x0000,         /* translation */
>                     0xF300          /* length */
>                      )
>             }) /* End Name(_SB.PCI0.CRES) */
>
>             Method(_CRS, 0) {
>                 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
>                 Return(CRES) /* note to change the Name buffer */
>             }  /* end of Method(_SB.PCI0._CRS) */
>         } /* End Device(PCI0)  */
>
>
> If this works for XP it would be nice...

Memory resources are needed too for PCI BARs.

>> +	Scope (\_SB)
>> +	{
>> +		OperationRegion (PCI0.SBRG.PIX0, PCI_Config, 0x55, 0x04)
>> +		OperationRegion (PCI0.SBRG.PIX1, PCI_Config, 0x50, 0x02)
>> +		OperationRegion (PCI0.SBRG.PIX2, PCI_Config, 0x44, 0x02)
>> +		OperationRegion (PCI0.SBRG.PIX3, PCI_Config, 0x67, 0x03)
>> +		OperationRegion (PCI0.SBRG.PIX4, PCI_Config, 0x6C, 0x04)
>> +		OperationRegion (PCI0.SBRG.PIEF, PCI_Config, 0x46, 0x01)
>> +		Field (PCI0.SBRG.PIX0, ByteAcc, NoLock, Preserve)
>> +		{
>> +			    , 4,
>> +			PIRA, 4,
>> +			PIRB, 4,
>> +			PIRC, 4,
>> +			    , 4,
>> +			PIRD, 4,
>> +			    , 4
>> +		}
>> +		Field (PCI0.SBRG.PIX1, ByteAcc, NoLock, Preserve)
>> +		{
>> +			    , 1,
>> +			EP3C, 1,
>> +			EN3C, 1,
>> +			    , 6,
>> +			KBFG, 1
>> +		}
>> +		Field (PCI0.SBRG.PIX2, ByteAcc, NoLock, Preserve)
>> +		{
>> +			PIRE, 4,
>> +			PIRF, 4,
>> +			PIRG, 4,
>> +			PIRH, 4,
>> +		}
>> +		Field (PCI0.SBRG.PIX3, ByteAcc, NoLock, Preserve)
>> +		{
>> +			ENIR, 1,
>> +			IRSD, 1,
>> +			Offset (0x02),
>> +			IRBA, 8
>> +		}
>> +		Field (PCI0.SBRG.PIX4, ByteAcc, NoLock, Preserve)
>> +		{
>> +			PS0E, 1,
>> +			PS1E, 1,
>> +			ROME, 1,
>> +			APCE, 1,
>> +			LPMS, 2,
>> +			MSEN, 1,
>> +			IXEN, 1,
>> +			LPMD, 2,
>> +			MDEN, 1,
>> +			GMEN, 1,
>> +			LPLP, 2,
>> +			LPEN, 1,
>> +			FDEN, 1,
>> +			LPCA, 3,
>> +			CAEN, 1,
>> +			LPCB, 3,
>> +			CBEN, 1,
>> +			LPSB, 2,
>> +			SBEN, 1,
>> +			FDSE, 1,
>> +			Offset (0x04)
>
>
> This code comes from where? You wrote it?
> This looks suspicius. We cannot copy anything from orig bios. I think you 
> dont need legacy IRQ anyway windows should work with APIC only. Please 
> try to keep the ACPI stuff as simple as possible.

That was copied from asus dsdt, good catch. I'll rewrite it from
scratch. (Even though it an barely be called code, it's mostly IO
space defines).

I'd like to have legacy IRQ as well as APIC working.
I think working legacy support is required for ACPI compliance.

>> +/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
>> +   LDN the register belongs to, before you can access the register. */
>> +static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
>> +{
>> +	outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
>> +	outb(ldn, SIO_DATA);
>> +	outb(index, SIO_BASE);
>> +	outb(value, SIO_DATA);
>> +}
>
>
> I think we have some generic function like pnp_enter_ext_func_mode
> etc please check it.

Ok, I'll have a look.

>> +	/*
>> +	 * it8712f gpio config
>> +	 *
>> +	 * Most importantly this switches pin 91 from
>> +	 * PCIRSTIN# to VIN7.
>> +	 * Note that only PCIRST3# and PCIRST5# are affected
>> +	 * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always
>> +	 * direct buffers of #LRESET (low pin count bus reset).
>> +	 * If this is not done All PCIRST are in reset state and the
>> +	 * pcie slots don't initialize.
>> +	 *
>> +	 * pci reset handling:
>> +	 * pin 91: VIN7 (alternate PCIRSTIN#)
>> +	 * pin 48: PCIRST5# / gpio port 5 bit 0
>> +	 * pin 84: PCIRST4# / gpio port 1 bit 0
>> +	 * pin 31: PCIRST1# / gpio port 1 bit 4
>> +	 * pin 33: PCIRST2# / gpio port 1 bit 2
>> +	 * pin 34: PCIRST3# / gpio port 1 bit 1
>> +	 *
>> +	 * PCIRST[0-5]# are connected as follows:
>> +	 * pcirst1# ->  pci bus
>> +	 * pcirst2# ->  ide bus
>> +	 * pcirst3# ->  pcie devices
>> +	 * pcirst4# ->  pcie graphics
>> +	 * pcirst5# ->  maybe n/c (untested)
>
> nice how did you found out?

I configured it for software control, wiggled the bits and saw what
happened. :)

> Btw we usually have sio setup in romstage.c But maybe it makes more sense 
> here if it is not critical.
>
> Maybe resets and voltage setup should be really in romstage.c (so it is 
> called before memory etc is setup).

The pcie resets are not critical, so I'm thinking romstage should
only contain what's strictly necessary at that point.
I tried finding the memory slot voltage setting, but I didn't find
any noticable gpio differences. :/
TODO: Measure the memory slot voltage.

>> +
>> +static void m2v_bus_init(void)
>> +{
>> +	u8 tmp;
>> +
>> +	pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0, 0), K8T890_MULTIPLE_FN_EN, 0x01);
>> +	/*
>> +	 * Northbridge pcie bridge 3.3 is not connected to anything, hide it.
>> +	 */
>> +	tmp = pci_cf8_conf1.read8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0);
>> +	tmp&= ~0x10; /* hide pcie bridge 0:3.3 */
>> +	tmp&= ~0x40; /* hide scratch register function 0:0.6 */
>> +	pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0, tmp);
>> +	/* Enable southbridge bridges 13.0 and 13.1 */
>> +	pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0x11, 7), 0X4F, 0x43);
>
>
> Hmm this most likely shoudl be done with the help of devicetree.cb

I don't see how this can be done with devicetree.cb.

>> +	/*
>> +	 * Mark APIC memory as reserved to get closer to ASUS E820 map
>> +	 */
>> +	lb_add_memory_range(mem, LB_MEM_RESERVED, IO_APIC_ADDR,     0x1000);
>> +	lb_add_memory_range(mem, LB_MEM_RESERVED, K8T890_APIC_BASE, 0x1000);
>> +	/*
>> +	 * Mark BIOS ROM space as reserved
>> +	 */
>> +	lb_add_memory_range(mem, LB_MEM_RESERVED, 0xffc00000, 0x400000);
>
> Dont think this is neccessary.

I think all ranges that have mapped devices and are unavailable for
PCI bars should be marked as reserved in E820 for correctness.
Should probably be done in the chipset code and not in the mainboard
code though.

>> +	return 0;
>> +}
>> +
>> +struct chip_operations mainboard_ops = {
>> +	CHIP_NAME("ASUS M2V")
>> +	.enable_dev = m2v_enable,
>> +};
>> Index: src/mainboard/asus/m2v/mptable.c
>> ===================================================================
>> --- /dev/null	1970-01-01 00:00:00.000000000 +0000
>> +++ src/mainboard/asus/m2v/mptable.c	2010-10-29 14:07:37.000000000 +0200
>
> THis was recently fixed are you using fixed version?

Well, I was the one who fixed it. ;)

>> +#define SB_VFSMAF 0
>
> I think for you would work normal way (without this ldstop_sb. I had 
> troubles with integrated VGA on K8M890.

It's there because I started with a copy of m2v-mx_se/romstage.c.
I'll remove it.

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From neotheuser at ymail.com  Wed Nov  3 18:55:40 2010
From: neotheuser at ymail.com (Neo The User)
Date: Wed, 3 Nov 2010 10:55:40 -0700 (PDT)
Subject: [coreboot] F71889 Super I/O patch
Message-ID: <445475.1685.qm@web114114.mail.gq1.yahoo.com>

Hello, I looked over the F71889 Fintek datasheet, and its very similar to the F71863FG I noticed. I used sed to replace some of the names around and such. I haven't tested it, nor will I, since I have little to no experience with flashing devices, and have no back-up (can't recover) and I do have a stub (that most likely wont work) for the MSI MS785GT-E63 board, and it compiled fine and all, using the F71889 code, I mainly just changed the romstage.c file around to make it fit, while still basing the code off the other 785 boards. If anybody wants to test the F71889 patch, feel free.

Also I wasn't sure to keep the same name in the other Fintek chips or not, so I changed the name to mine, and the year. I apologize if that was incorrect, and will be more than willing to keep the original GNU header.

Some indentation was changed when using svn diff to generate the patch.

-Alec Ari <neotheuser at ymail.com>


      
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From c-d.hailfinger.devel.2006 at gmx.net  Wed Nov  3 19:14:09 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 03 Nov 2010 19:14:09 +0100
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in
 Win7 (revised)
In-Reply-To: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
Message-ID: <4CD1A671.2070304@gmx.net>

Hi Scott,

I am not totally convinced that all changes are a net win.

On 03.11.2010 05:29, Scott Duplichan wrote:
> (Re-submitting with correction to GFX debug bar setup procedure needed
> for use with AMD family 0Fh processor).
>
> This patch solves crashes and BSODs that occur when booting Win7 with
> AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB
> by running dxdiag and Windows media player at 1600x1200 true color.
> Additional changes needed to boot Win7 on Mahogany_fam10 will follow.
>
> -- Enable and program the debug bar as required by the ATI graphics driver.
>    First, make the debug bar writable and allow resource allocation code
>    to program it. Once programmed, enable its operation.
>   

Good.


> -- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
>   

I thought the family 10h processors need their own MMCONF for some
configuration accesses. If this disable happens after all such config
writes are done, I'm OK with it.


> -- Make strap programming more closely follow the reference BIOS.
>   

Good.


> -- Disable PCIe bar 3 after using it.
>   

This one is something I have reservations about. Isn't PCIe BAR 3 the
one via which MMCONF accesses are done? How is MMCONF going to work
after that?


> -- UMA size is no longer hardcoded.
>   

Nice.


> -- Disable write combining for all steppings to eliminate stability problem.
>   

This may have a performance impact, right? Do you know if any steppings
with stable write combining exist?


> -- Correct task file data.
> -- Improve the accuracy of the Atom table that passes information to the driver.
>   

Yes, that's definitely needed.


> Signed-off-by: Scott Duplichan <scott at notabs.org>
>   

I think the patch looks good, but I'd like a few answers before I ack it.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From ranma+coreboot at tdiedrich.de  Wed Nov  3 19:21:01 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 3 Nov 2010 19:21:01 +0100
Subject: [coreboot] [PATCH 2/7] ASUS M2V support (v2): VT8237A LPC
	device id	(unchanged)
In-Reply-To: <4CD07CFA.8040500@assembler.cz>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029115838.GJ31684@yumi.tdiedrich.de>
	<4CD07CFA.8040500@assembler.cz>
Message-ID: <20101103182101.GA21368@yumi.tdiedrich.de>

Rudolf Marek wrote:
> Hi,
>
> I think following is not true. The VT8237A has something else at 0x50, so 
> vt8237_sb_enable_fid_vid should not be neccessary to call. Do you call it 
> or not? If not then we either need to fix it for the "old" location 0x11 
> iirc or not to put there any test for A version.
>>
>> +static const struct device_operations vt8237r_lpc_ops_a = {
>> +	.read_resources		= vt8237r_read_resources,
>> +	.set_resources		= pci_dev_set_resources,
>> +	.enable_resources	= pci_dev_enable_resources,
>> +	.init			= vt8237r_init,
>> +	.scan_bus		= scan_static_bus,
>> +};
>> +
>
>
> I think you dont need this for now, if you use "r" init version you can 
> cange it directly:
>
>
>> +static const struct pci_driver lpc_driver_a __pci_driver = {
>> +	.ops	=&vt8237r_lpc_ops_a,

Updated patch:

This adds the VT8237A LPC device id and corresponding pci_locate_device
calls in vt8237r_early_smbus.c plus the pci_driver struct in
vt8237r_lpc.c

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>

---

Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c.orig	2010-11-03 15:15:02.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2010-11-03 15:15:25.000000000 +0100
@@ -146,6 +146,11 @@
 
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 				PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+	if (dev != PCI_DEV_INVALID)
+		return dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);
 	return dev;
 }
 
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig	2010-11-03 14:54:54.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-11-03 15:16:35.000000000 +0100
@@ -543,6 +543,12 @@
 	.device	= PCI_DEVICE_ID_VIA_VT8237R_LPC,
 };
 
+static const struct pci_driver lpc_driver_a __pci_driver = {
+	.ops	= &vt8237r_lpc_ops_r,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_VT8237A_LPC,
+};
+
 static const struct pci_driver lpc_driver_s __pci_driver = {
 	.ops	= &vt8237r_lpc_ops_s,
 	.vendor	= PCI_VENDOR_ID_VIA,
Index: src/include/device/pci_ids.h
===================================================================
--- src/include/device/pci_ids.h.orig	2010-11-03 14:54:54.000000000 +0100
+++ src/include/device/pci_ids.h	2010-11-03 15:14:49.000000000 +0100
@@ -1226,6 +1226,7 @@
 #define PCI_DEVICE_ID_VIA_K8T890CE_BR	0xb188
 #define PCI_DEVICE_ID_VIA_VT6420_SATA	0x3149
 #define PCI_DEVICE_ID_VIA_VT8237R_LPC	0x3227
+#define PCI_DEVICE_ID_VIA_VT8237A_LPC	0x3337
 #define PCI_DEVICE_ID_VIA_VT8237S_LPC	0x3372
 #define PCI_DEVICE_ID_VIA_VT8237_SATA	0x5372
 #define PCI_DEVICE_ID_VIA_VT8237_VLINK	0x287e




From ranma+coreboot at tdiedrich.de  Wed Nov  3 19:24:54 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 3 Nov 2010 19:24:54 +0100
Subject: [coreboot] [PATCH 4/7] ASUS M2V support (v2): VT8237A
	specific	initialization
In-Reply-To: <4CD07FA7.80306@assembler.cz>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029120051.GL31684@yumi.tdiedrich.de>
	<20101029121533.GP31684@yumi.tdiedrich.de>
	<4CD07FA7.80306@assembler.cz>
Message-ID: <20101103182454.GB21368@yumi.tdiedrich.de>

Rudolf Marek wrote:
>> +	if (!devfun7)
>> +		return;
>> +
>> +	/*
>> +	 * This init code is valid only for the VT8237A! For different
>> +	 * sounthbridges (e.g. VT8237S, VT8237R (without plus R)
>
> typo :) maybe was just copied? Did you get the values from orig bios? Or 
> just copied? For what vlink mode it is 8x? I got some VIA recommended 
> values but they are bit different 0xb5 is 0x88.
>
>> +	/* FIXME: Intel needs more bit set for C2/C3. */
>> +
>> +	/*
>> +	 * Allow SLP# signal to assert LDTSTOP_L.
>> +	 * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2.
>
> What is fixme fixme pre revA2?
>
>> +	 */
>> +	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
>> +
>> +	dump_south(dev);
>> +}
>> +
>>   static void vt8237s_init(struct device *dev)
>>   {
>>   	u32 tmp;
>> @@ -541,7 +584,7 @@
>>   	.read_resources		= vt8237r_read_resources,
>>   	.set_resources		= pci_dev_set_resources,
>>   	.enable_resources	= pci_dev_enable_resources,
>> -	.init			= vt8237r_init,
>> +	.init			= vt8237a_init,
>>   	.scan_bus		= scan_static_bus,
>>   };
>>
>
> Otherwise fine.

Updated patch:

This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.c,
vt8237r_lpc.c and vt8237r_early_smbus.c
I ran some tests and apparently both the

|			/* So the chip knows we are on AMD. */
|			pci_write_config8(devctl, 0x7c, 0x7f);

and

|	/*
|	 * Allow SLP# signal to assert LDTSTOP_L.
|	 * Will work for C3 and for FID/VID change.
|	 */
|	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);

in vt8237r_early_smbus.c are needed on VT8237A, otherwise I get a (non-fatal)
fid/vid change error on boot.

While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>

---

Index: src/southbridge/via/vt8237r/vt8237_ctrl.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237_ctrl.c.orig	2010-11-03 15:23:19.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237_ctrl.c	2010-11-03 15:37:25.000000000 +0100
@@ -168,6 +168,75 @@
 
 }
 
+static void vt8237a_vlink_init(struct device *dev)
+{
+	u8 reg;
+	device_t devfun7;
+
+	devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+				  PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
+	/* No pairing NB was found. */
+	if (!devfun7)
+		return;
+
+	/*
+	 * This init code is valid only for the VT8237A! For different
+	 * sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different
+	 * init code is required.
+	 *
+	 * FIXME: This is based on vt8237r_vlink_init() in
+	 *        k8t890/k8t890_ctrl.c and modified to fit what the AMI
+	 *        BIOS on my M2V wrote to these registers (by looking
+	 *        at lspci -nxxx output).
+	 *        Works for me.
+	 */
+
+	/* disable auto disconnect */
+	reg = pci_read_config8(devfun7, 0x42);
+	reg &= ~0x4;
+	pci_write_config8(devfun7, 0x42, reg);
+
+	/* NB part setup */
+	pci_write_config8(devfun7, 0xb5, 0x88);
+	pci_write_config8(devfun7, 0xb6, 0x88);
+	pci_write_config8(devfun7, 0xb7, 0x61);
+
+	reg = pci_read_config8(devfun7, 0xb4);
+	reg |= 0x11;
+	pci_write_config8(devfun7, 0xb4, reg);
+
+	pci_write_config8(devfun7, 0xb0, 0x6);
+	pci_write_config8(devfun7, 0xb1, 0x1);
+
+	/* SB part setup */
+	pci_write_config8(dev, 0xb7, 0x50);
+	pci_write_config8(dev, 0xb9, 0x88);
+	pci_write_config8(dev, 0xba, 0x8a);
+	pci_write_config8(dev, 0xbb, 0x88);
+
+	reg = pci_read_config8(dev, 0xbd);
+	reg |= 0x3;
+	reg &= ~0x4;
+	pci_write_config8(dev, 0xbd, reg);
+
+	reg = pci_read_config8(dev, 0xbc);
+	reg &= ~0x7;
+	pci_write_config8(dev, 0xbc, reg);
+
+	pci_write_config8(dev, 0x48, 0x23);
+
+	/* enable auto disconnect, for STPGNT and HALT */
+	reg = pci_read_config8(devfun7, 0x42);
+	reg |= 0x7;
+	pci_write_config8(devfun7, 0x42, reg);
+}
+
 static void ctrl_enable(struct device *dev)
 {
 	/* Enable the 0:13 and 0:13.1. */
@@ -193,6 +262,12 @@
 		vt8237s_vlink_init(dev);
 	}
 
+	devsb = dev_find_device(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
+	if (devsb) {
+		vt8237a_vlink_init(dev);
+	}
+
 	/* Configure PCI1 and copy mirror registers from D0F3. */
 	vt8237_cfg(dev);
 	dump_south(dev);
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig	2010-11-03 15:23:19.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-11-03 15:50:51.000000000 +0100
@@ -319,6 +319,55 @@
 	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 }
 
+static void vt8237a_init(struct device *dev)
+{
+	/*
+	 * FIXME: This is based on vt8237s_init() and the values the AMI
+	 *        BIOS on my M2V wrote to these registers (by loking
+	 *        at lspci -nxxx output).
+	 *        Works for me.
+	 */
+	u32 tmp;
+
+	/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
+	tmp = pci_read_config8(dev, 0x4f);
+	tmp |= 0x08;
+	pci_write_config8(dev, 0x4f, tmp);
+
+	/*
+	 * bit2: REQ5 as PCI request input - should be together with INTE-INTH.
+	 * bit5: usb power control lines as gpio
+	 */
+	pci_write_config8(dev, 0xe4, 0x24);
+	/*
+	 * Enable APIC wakeup from INTH
+	 * Enable SATA LED, disable special CPU Frequency Change -
+	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+	 */
+	pci_write_config8(dev, 0xe5, 0x69);
+
+	/* Reduce further the STPCLK/LDTSTP signal to 5us. */
+	pci_write_config8(dev, 0xec, 0x4);
+
+	/* Host Bus Power Management Control, maybe not needed */
+	pci_write_config8(dev, 0x8c, 0x5);
+
+	/* Enable HPET at VT8237R_HPET_ADDR. */
+	pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+
+	southbridge_init_common(dev);
+
+	/* FIXME: Intel needs more bit set for C2/C3. */
+
+	/*
+	 * Allow SLP# signal to assert LDTSTOP_L.
+	 * Will work for C3 and for FID/VID change.
+	 */
+	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+
+	dump_south(dev);
+}
+
 static void vt8237s_init(struct device *dev)
 {
 	u32 tmp;
@@ -537,6 +586,14 @@
 	.scan_bus		= scan_static_bus,
 };
 
+static const struct device_operations vt8237r_lpc_ops_a = {
+	.read_resources		= vt8237r_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= vt8237a_init,
+	.scan_bus		= scan_static_bus,
+};
+
 static const struct pci_driver lpc_driver_r __pci_driver = {
 	.ops	= &vt8237r_lpc_ops_r,
 	.vendor	= PCI_VENDOR_ID_VIA,
@@ -544,7 +601,7 @@
 };
 
 static const struct pci_driver lpc_driver_a __pci_driver = {
-	.ops	= &vt8237r_lpc_ops_r,
+	.ops	= &vt8237r_lpc_ops_a,
 	.vendor	= PCI_VENDOR_ID_VIA,
 	.device	= PCI_DEVICE_ID_VIA_VT8237A_LPC,
 };
Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c.orig	2010-11-03 15:23:19.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2010-11-03 15:23:22.000000000 +0100
@@ -257,19 +257,30 @@
 		return;
 
 	devid = pci_read_config16(dev, PCI_DEVICE_ID);
-	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) {
-		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
 
-		if (devctl == PCI_DEV_INVALID)
-			return;
+	/* generic setup */
+
+	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
+	pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
+
+	/* Enable ACPI accessm RTC signal gated with PSON. */
+	pci_write_config8(dev, 0x81, 0x84);
+
+	/* chipset-specific parts */
 
-		/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
-		pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
+	/* VLINK: FIXME: can we drop the devid check and just look for the VLINK device? */
+	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC ||
+	    devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) {
+		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+					   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
 
-		/* Enable ACPI accessm RTC signal gated with PSON. */
-		pci_write_config8(dev, 0x81, 0x84);
+		if (devctl != PCI_DEV_INVALID) {
+			/* So the chip knows we are on AMD. */
+			pci_write_config8(devctl, 0x7c, 0x7f);
+		}
+	}
 
+	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) {
 		/*
 		 * Allow SLP# signal to assert LDTSTOP_L.
 		 * Will work for C3 and for FID/VID change.
@@ -280,17 +291,10 @@
 		/* Reduce further the STPCLK/LDTSTP signal to 5us. */
 		pci_write_config8(dev, 0xec, 0x4);
 
-		/* So the chip knows we are on AMD. */
-		pci_write_config8(devctl, 0x7c, 0x7f);
-
 		return;
 	}
 
-	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
-	pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
-
-	/* Enable ACPI accessm RTC signal gated with PSON. */
-	pci_write_config8(dev, 0x81, 0x84);
+	/* VT8237R and VT8237A */
 
 	/*
 	 * Allow SLP# signal to assert LDTSTOP_L.




From ranma+coreboot at tdiedrich.de  Wed Nov  3 19:26:44 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 3 Nov 2010 19:26:44 +0100
Subject: [coreboot] [PATCH 6/7] ASUS M2V support (v2): Comments
	(unchanged)
In-Reply-To: <4CD082E7.3010600@assembler.cz>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029120234.GN31684@yumi.tdiedrich.de>
	<4CD082E7.3010600@assembler.cz>
Message-ID: <20101103182644.GC21368@yumi.tdiedrich.de>

Rudolf Marek wrote:
>> -	/* ROM memory cycles go to LPC. */
>> +	/* Only ROM memory cycles go to LPC. */
>
> I think it should be,
>
> > +	/* Only memory ROM cycles go to LPC.  */
>
> Because this bit is telling if all memory cycles should go to LPC or just 
> those from ROM range. Please try to rephase that.

Updated patch:

Comment changes, add pointer to PCIe bridge documentation.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>

---

Index: src/southbridge/via/k8t890/k8t890_ctrl.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_ctrl.c.orig	2010-11-03 14:53:07.000000000 +0100
+++ src/southbridge/via/k8t890/k8t890_ctrl.c	2010-11-03 15:51:23.000000000 +0100
@@ -154,7 +154,11 @@
 
 	pci_write_config8(dev, 0x47, 0x30);
 
-	/* VT8237R specific configuration  other SB are done in their own directories */
+	/*
+	 * VT8237R specific configuration,
+	 * other SB are done in their own directories:
+	 * VT8237A and VT8237S are handled in vt8237_ctrl.c
+	 */
 
 	device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
 					 PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig	2010-11-03 15:50:51.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-11-03 16:02:37.000000000 +0100
@@ -457,7 +457,18 @@
 	/* I/O recovery time, default IDE routing */
 	pci_write_config8(dev, 0x4c, 0x04);
 
-	/* ROM memory cycles go to LPC. */
+	/*
+	 * Bit | Meaning
+	 *   7 | 1: Only ROM memory cycles go to LPC instead of all memory
+	 *     |    cycles.
+	 *   6 | 0: Internal ISA cycles do not arbitrate with secondary IDE
+	 *   5 | 0: Disable LPC RTC
+	 *   4 | 0: Disable LPC Keyboard
+	 *   3 | 0: Disable Port 0x62/0x66 to LPC
+	 *   2 | 0: Disable Port 0x62/0x66 MCCS# chipselect decoding
+	 *   1 | 0: Disable A20M# signal (signal not asserted)
+	 *   0 | 0: Disable NMI on PCI parity error
+	 */
 	pci_write_config8(dev, 0x59, 0x80);
 
 	/*
@@ -479,7 +490,18 @@
 	/* I/O recovery time, default IDE routing */
 	pci_write_config8(dev, 0x4c, 0x44);
 
-	/* ROM memory cycles go to LPC. */
+	/*
+	 * Bit | Meaning
+	 *   7 | 1: Only ROM memory cycles go to LPC instead of all memory
+	 *     |    cycles.
+	 *   6 | 0: Internal ISA cycles do not arbitrate with secondary IDE
+	 *   5 | 0: Disable LPC RTC
+	 *   4 | 0: Disable LPC Keyboard
+	 *   3 | 0: Disable Port 0x62/0x66 to LPC
+	 *   2 | 0: Disable Port 0x62/0x66 MCCS# chipselect decoding
+	 *   1 | 0: Disable A20M# signal (signal not asserted)
+	 *   0 | 0: Disable NMI on PCI parity error
+	 */
 	pci_write_config8(dev, 0x59, 0x80);
 
 	/*
Index: src/southbridge/via/k8t890/k8t890_pcie.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_pcie.c.orig	2010-11-03 14:53:07.000000000 +0100
+++ src/southbridge/via/k8t890/k8t890_pcie.c	2010-11-03 15:51:23.000000000 +0100
@@ -24,6 +24,12 @@
 #include <device/pci_ids.h>
 #include "k8t890.h"
 
+/*
+ * Note:
+ * The pcie bridges are similar to the VX800 ones documented at
+ * http://linux.via.com.tw/
+ */
+
 static void peg_init(struct device *dev)
 {
 	u8 reg;




From peter at stuge.se  Wed Nov  3 20:13:23 2010
From: peter at stuge.se (Peter Stuge)
Date: Wed, 3 Nov 2010 20:13:23 +0100
Subject: [coreboot] [PATCH 7/7] ASUS M2V support (v2): Add m2v	mainboard
	directory and files
In-Reply-To: <20101103170344.GC31684@yumi.tdiedrich.de>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029121423.GO31684@yumi.tdiedrich.de>
	<4CD08955.2020709@assembler.cz>
	<20101103170344.GC31684@yumi.tdiedrich.de>
Message-ID: <20101103191323.1880.qmail@stuge.se>

Tobias Diedrich wrote:
> >> +	/*
> >> +	 * Northbridge pcie bridge 3.3 is not connected to anything, hide it.
> >> +	 */
> >> +	tmp = pci_cf8_conf1.read8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0);
> >> +	tmp&= ~0x10; /* hide pcie bridge 0:3.3 */
> >> +	tmp&= ~0x40; /* hide scratch register function 0:0.6 */
> >> +	pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0, tmp);
> >> +	/* Enable southbridge bridges 13.0 and 13.1 */
> >> +	pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0x11, 7), 0X4F, 0x43);
> >
> >
> > Hmm this most likely shoudl be done with the help of devicetree.cb
> 
> I don't see how this can be done with devicetree.cb.

device pci 3.3 off end


> I think all ranges that have mapped devices and are unavailable for
> PCI bars should be marked as reserved in E820 for correctness.
> Should probably be done in the chipset code and not in the
> mainboard code though.

I agree - and that would be wonderful!


//Peter



From neotheuser at ymail.com  Wed Nov  3 20:18:56 2010
From: neotheuser at ymail.com (Neo The User)
Date: Wed, 3 Nov 2010 12:18:56 -0700 (PDT)
Subject: [coreboot] F71889 Super I/O patch
Message-ID: <980104.54562.qm@web114105.mail.gq1.yahoo.com>

Signed-off-by: Alec Ari <neotheuser at ymail.com>


--- On Wed, 11/3/10, Neo The User <neotheuser at ymail.com> wrote:

> From: Neo The User <neotheuser at ymail.com>
> Subject: F71889 Super I/O patch
> To: coreboot at coreboot.org
> Date: Wednesday, November 3, 2010, 5:55 PM
> Hello, I looked over the F71889
> Fintek datasheet, and its very similar to the F71863FG I
> noticed. I used sed to replace some of the names around and
> such. I haven't tested it, nor will I, since I have little
> to no experience with flashing devices, and have no back-up
> (can't recover) and I do have a stub (that most likely wont
> work) for the MSI MS785GT-E63 board, and it compiled fine
> and all, using the F71889 code, I mainly just changed the
> romstage.c file around to make it fit, while still basing
> the code off the other 785 boards. If anybody wants to test
> the F71889 patch, feel free.
> 
> Also I wasn't sure to keep the same name in the other
> Fintek chips or not, so I changed the name to mine, and the
> year. I apologize if that was incorrect, and will be more
> than willing to keep the original GNU header.
> 
> Some indentation was changed when using svn diff to
> generate the patch.
> 
> -Alec Ari <neotheuser at ymail.com>
> 
> 
> ? ? ? 


      



From ranma+coreboot at tdiedrich.de  Wed Nov  3 21:00:17 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 3 Nov 2010 21:00:17 +0100
Subject: [coreboot] [PATCH 7/7] ASUS M2V support (v2): Add m2v mainboard
	directory	and files
In-Reply-To: <20101103191323.1880.qmail@stuge.se>
References: <20101029115628.GH31684@yumi.tdiedrich.de>
	<20101029121423.GO31684@yumi.tdiedrich.de>
	<4CD08955.2020709@assembler.cz>
	<20101103170344.GC31684@yumi.tdiedrich.de>
	<20101103191323.1880.qmail@stuge.se>
Message-ID: <20101103200017.GD21368@yumi.tdiedrich.de>

Peter Stuge wrote:
> Tobias Diedrich wrote:
> > >> +	/*
> > >> +	 * Northbridge pcie bridge 3.3 is not connected to anything, hide it.
> > >> +	 */
> > >> +	tmp = pci_cf8_conf1.read8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0);
> > >> +	tmp&= ~0x10; /* hide pcie bridge 0:3.3 */
> > >> +	tmp&= ~0x40; /* hide scratch register function 0:0.6 */
> > >> +	pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0, tmp);
> > >> +	/* Enable southbridge bridges 13.0 and 13.1 */
> > >> +	pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0x11, 7), 0X4F, 0x43);
> > >
> > >
> > > Hmm this most likely shoudl be done with the help of devicetree.cb
> > 
> > I don't see how this can be done with devicetree.cb.
> 
> device pci 3.3 off end

That does something different though I think.
I.e. the bridge is still visible as a device, even if we leave it
unconfigured.
The code above completely removes the device so it is no longer
visible at all.
Since we don't use the scratch register function 0:0.6 and the 4th
pcie bridge 0:3.3 is not physically wired to anything I thought it
would be neat to just disable those two completely.

> > I think all ranges that have mapped devices and are unavailable for
> > PCI bars should be marked as reserved in E820 for correctness.
> > Should probably be done in the chipset code and not in the
> > mainboard code though.
> 
> I agree - and that would be wonderful!

I'll look into it.

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From njacobs8 at hetnet.nl  Wed Nov  3 21:51:37 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Wed, 3 Nov 2010 21:51:37 +0100
Subject: [coreboot] [PATCH] Geode GX2 comment cleanup 1
In-Reply-To: <20101103132031.GO3256@greenwood>
References: <201011022232.39478.njacobs8@hetnet.nl>
	<20101103132031.GO3256@greenwood>
Message-ID: <201011032151.37916.njacobs8@hetnet.nl>

Op woensdag 3 november 2010 14:20:31 schreef u:
> Thanks, r6014 with some further cosmetic fixes I noticed.
> 
> 
> Uwe.
Thanks for the fast review and commit.

Nils.



From qcuiag at arvutipartnerid.ee  Wed Nov  3 20:56:45 2010
From: qcuiag at arvutipartnerid.ee (QCUIAG QCUIAG)
Date: Wed, 3 Nov 2010 21:56:45 +0200
Subject: [coreboot] EPIA halting after vt8601 init
Message-ID: <AANLkTinaN=tJw7or6v8hUR+EJcQS+TEvUfkatrpX2h_V@mail.gmail.com>

Hello,

 please advise on EPIA 800 board hanging after northbridge initialisation. I
checked against chipset datasheet and working AWARD dump - the northbridge
SDRAM configuration registers are correctly set. There are no errors in
memory test, I can induce errors in memory test for example with wrongly
configured paging registers. I have tested with five different memory
modules (single/double sided, differing speeds, latencys).

I did found an old thread (by Al Hooton) with similar problem, that was
resolved with correct CAS latency setting, does not help in this case.

Outcome does not differ with/without payload(s) and the hardware passes all
tests with AWARD I can throw at it.

Is this rom structure reasonable (missing fallback/romstage?):

    CBFSPRINT  coreboot.rom

coreboot.rom: 256 kB, bootblocksize 65536, romsize 262144, offset 0x0
Alignment: 64 bytes

Name                                 Offset       Type           Size
fallback/coreboot_ram          0x0          stage          47306
fallback/payload                  0xb940     payload       17021
pci1023,8500.rom                0xfc00      optionrom    49152
(empty)                              0x1bc40    null             82808

What I get out from console with SPEW:

coreboot-4.0-r6016M Wed Nov  3 21:17:24 EET 2010 starting...
87 is the comm register
SMBus controller enabled
vt8601 init starting
00000000 is the north
1106 0601
0120d4 is the computed timing
NOP
PRECHARGE
DUMMY READS
CBR
MRS
NORMAL
set ref. rate
enable multi-page open
Slot 00 is SDRAM 20000000 bytes
000e is the MA type
Slot 01 is empty
Slot 02 is empty
Slot 03 is empty
vt8601 done
<northbridge dump>
00:06 11 01 06 06 00 90 22 05 00 00 06 00 00 00 00
10:08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50:ac 08 80 00 00 00 40 40 e0 00 40 40 40 40 40 40
60:3f 00 00 31 e6 95 95 00 52 3c 86 0d 08 7f 00 00
70:00 00 00 00 00 00 00 00 01 f0 00 00 00 00 00 00
80:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0:02 00 20 00 03 02 00 07 00 00 00 00 08 02 00 00
b0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0:00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 00
<memory tests>
Testing DRAM : 00000000-000a0000
DRAM fill: 00000000-000a0000
000a0000
DRAM filled
DRAM verify: 00000000-000a0000
000a0000
DRAM range verified.
Done.
Testing DRAM : 00100000-01000000
DRAM fill: 00100000-01000000
01000000
DRAM filled
DRAM verify: 00100000-01000000
01000000
DRAM range verified.
Done.
Loading stage image.
Check CBFS header at <hangs here>


With lower loglevel:

coreboot-4.0-r6016M Wed Nov  3 21:30:53 EET 2010 starting...
vt8601 init starting
Slot 00 is SDRAM 20000000 bytes
Slot 01 is empty
Slot 02 is empty
Slot 03 is empty
vt8601 done
Stage: loading fallback/coreboot_ram @ 0x <hangs here>


Regards,
Toomas Pruuden
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From njacobs8 at hetnet.nl  Wed Nov  3 21:56:06 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Wed, 3 Nov 2010 21:56:06 +0100
Subject: [coreboot] [PATCH] Geode GX2 comment cleanup 2
In-Reply-To: <20101103132336.GP3256@greenwood>
References: <201011022232.59237.njacobs8@hetnet.nl>
	<20101103132336.GP3256@greenwood>
Message-ID: <201011032156.06352.njacobs8@hetnet.nl>

Hi Uwe,
Op woensdag 3 november 2010 14:23:36 schreef u:
>Thanks, r6015
Thanks for the fast review and commit.

> "Clean up stuff" looks better than "This patch cleans up stuff" in svn
> logs.
OK will do better next time.

Thanks, Nils.



From mylesgw at gmail.com  Wed Nov  3 22:00:54 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 3 Nov 2010 15:00:54 -0600
Subject: [coreboot] EPIA halting after vt8601 init
In-Reply-To: <AANLkTinaN=tJw7or6v8hUR+EJcQS+TEvUfkatrpX2h_V@mail.gmail.com>
References: <AANLkTinaN=tJw7or6v8hUR+EJcQS+TEvUfkatrpX2h_V@mail.gmail.com>
Message-ID: <AANLkTimZWMT5LeeEK1Bkx_iDP16TbQqUn_WLfzvdYOYJ@mail.gmail.com>

> Is this rom structure reasonable (missing fallback/romstage?):
It's fine.  The romstage (boot block) isn't part of CBFS.


> Loading stage image.
> Check CBFS header at <hangs here>
Normally a hang here means that the whole ROM isn't mapped, so trying
to read from the top of the ROM hangs, even though the bootblock
accesses work fine.

Thanks,
Myles



From njacobs8 at hetnet.nl  Wed Nov  3 21:59:52 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Wed, 3 Nov 2010 21:59:52 +0100
Subject: [coreboot] [PATCH] Remove unused code from Geode GX2
In-Reply-To: <20101103132447.GQ3256@greenwood>
References: <201011022233.53488.njacobs8@hetnet.nl>
	<20101103132447.GQ3256@greenwood>
Message-ID: <201011032159.52428.njacobs8@hetnet.nl>

Uwe wrote,
Op woensdag 3 november 2010 14:24:47 schreef u:
> Thanks, r6016.

Thanks for the fast review and commit.

Nils.



From ranma+coreboot at tdiedrich.de  Wed Nov  3 22:12:45 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 3 Nov 2010 22:12:45 +0100
Subject: [coreboot] [PATCH] via k8t890/vt8237: mark mmconf,
	apic and bios resources as	reserved
Message-ID: <20101103211245.GE21368@yumi.tdiedrich.de>

Ranges unavailable for PCI BARs should be marked as reserved in the E820
memory map, in case the OS wants to change the BARs.
This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
resource flags to do this.
I also added a new resource for the mapped bios rom area just below 4GB.
I'm not sure if the choice for the index parameter of new_resource()
is correct though.
Note that the bios rom decode is enabled in
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
for the whole 4MB area (even though the comment says 1MB).

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>

---

Index: coreboot-svn-m2v-splitpatches/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
===================================================================
--- coreboot-svn-m2v-splitpatches.orig/src/southbridge/via/k8t890/k8t890_traf_ctrl.c	2010-11-03 21:38:32.000000000 +0100
+++ coreboot-svn-m2v-splitpatches/src/southbridge/via/k8t890/k8t890_traf_ctrl.c	2010-11-03 21:45:21.000000000 +0100
@@ -58,7 +58,7 @@
 	res->limit = res->base + res->size - 1;
 	res->align = 8;
 	res->gran = 8;
-	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
 		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 
 	/* Add an MMCONFIG resource. */
@@ -67,7 +67,7 @@
 	res->align = log2(res->size);
 	res->gran = log2(res->size);
 	res->limit = 0xffffffff;	/* 4G */
-	res->flags = IORESOURCE_MEM;
+	res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;
 }
 
 static void traf_ctrl_enable_generic(struct device *dev)
Index: coreboot-svn-m2v-splitpatches/src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- coreboot-svn-m2v-splitpatches.orig/src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-11-03 21:50:45.000000000 +0100
+++ coreboot-svn-m2v-splitpatches/src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-11-03 21:58:52.000000000 +0100
@@ -566,7 +566,15 @@
 	res->limit = 0xffffffffUL;
 	res->align = 8;
 	res->gran = 8;
-	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
+		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	/* Fixed flashrom resource */
+	res = new_resource(dev, 4);
+	res->base = 0xffc00000UL;
+	res->size = 0x00400000UL; /* 4MB */
+	res->limit = 0xffffffffUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
 		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 
 	res = new_resource(dev, 1);




From scott at notabs.org  Wed Nov  3 22:17:35 2010
From: scott at notabs.org (Scott Duplichan)
Date: Wed, 3 Nov 2010 16:17:35 -0500
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in
	Win7 (revised)
In-Reply-To: <4CD1A671.2070304@gmx.net>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78> <4CD1A671.2070304@gmx.net>
Message-ID: <0262D18532FD466FABE0B2E0DCECDE61@m3a78>

-----Original Message-----
From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] 
Sent: Wednesday, November 03, 2010 01:14 PM
To: Scott Duplichan
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7 (revised)

]Hi Scott,
]
]I am not totally convinced that all changes are a net win.

Hello Carl-Daniel,

Thanks for looking at it. The strategy I used is to try to make the code
match the current AMD CIMx code as closely as possible. The existing RS780
code is based on an older CIMx version that does not support the family 10h
processor. I actually did many experiments with a reference BIOS as a way
to find what parts of the code are essential for getting Win7 booted. It is
interesting to know that much of the code is not needed for Win7 boot or
even for video playback using windows media player. An example is the code
that copies some of the processor memory controller settings to the RS780.
What is this code for then? Possibly it becomes important for some directX
or 3D operation that I did not exercise. I did not test any 3D application.

]On 03.11.2010 05:29, Scott Duplichan wrote:
]> (Re-submitting with correction to GFX debug bar setup procedure needed
]> for use with AMD family 0Fh processor).
]>
]> This patch solves crashes and BSODs that occur when booting Win7 with
]> AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB
]> by running dxdiag and Windows media player at 1600x1200 true color.
]> Additional changes needed to boot Win7 on Mahogany_fam10 will follow.
]>
]> -- Enable and program the debug bar as required by the ATI graphics driver.
]>    First, make the debug bar writable and allow resource allocation code
]>    to program it. Once programmed, enable its operation.
]>   
]
]Good.
]
]
]> -- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
]>   
]
]I thought the family 10h processors need their own MMCONF for some
]configuration accesses. If this disable happens after all such config
]writes are done, I'm OK with it.

The family 10h mmconf is disabled only temporarily, then restored to its
previous state. I added this code because that is how the current CIMx
code does it.

]> -- Make strap programming more closely follow the reference BIOS.
]>   
]
]Good.
]
]
]> -- Disable PCIe bar 3 after using it.
]>   
]
]This one is something I have reservations about. Isn't PCIe BAR 3 the
]one via which MMCONF accesses are done? How is MMCONF going to work
]after that?

Of the two reference BIOS binaries I can boot, neither appears to leave
PCIe bar 3 enabled. I see zeros there after booting, although I am not
100% sure this means zero is its real value. Yet on the two reference BIOS
images, along with the patched coreboot, I can still see the RS780 at
mmconf+0. I assume the family 10h processor sends mmconf requests to
the HT link if the address is not that of an internal device. I don't
know how it works for family 0Fh processors. 

The original coreboot RS780 code intended to disable BAR 3 after using
it. The code comment reads, "We should disable bar3 when we want to exit
rs780_enable, because bar3 will be remapped in set_resource later".
However, the call to the disable function was removed and replaced by
this comment: "Don't call disable_pcie_bar3(nb_dev) here, otherwise the
screen will crash". I debugged this problem and found the disable function
set the bar to zero, but did not disable it. So legacy video MMIO writes
were being claimed by bar 3 and not reaching the video function. The patch
corrects this problem and adds back the function call to disable bar 3 after
PCIe training is complete. The reason I even looked at this code in the
first place is this. With the unpatched code, the PCI resource allocation
code finds bar 3 writable and assigns it a base address. In my case it
assigned C0000000. This C000000 range is unusable because it is not the
range set aside for mmconf. I have mmconf at F8000000.

In addition, I noticed the mahogany_fam10 and mahogany projects have no
MCFG table, so Windows will never use mmconf for PCI config access. This
is an area I would like to study more, but any improvement should probably
be done in a separate patch. It is interesting to know that Microsoft
planned for mmconf and the ACPI MCFG table to be required for Windows Vista.
The early beta editions required it. But it proved too much trouble and
the requirement was removed. The requirement was not added back for Win7.
I don't know if it is planned for Win8.

]> -- UMA size is no longer hardcoded.
]>   
]
]Nice.
]
]
]> -- Disable write combining for all steppings to eliminate stability problem.
]>   
]
]This may have a performance impact, right? Do you know if any steppings
]with stable write combining exist?

Write combining should only be disabled for the early steppings. Why
I have to disable it for A13 is an unsolved problem. Yes, I would assume
there is a performance impact. On the otherhand, using the ATI driver with
write combining disabled still gives a big performance boost when compared
to the generic vga driver. I would like to solve this problem, but have run
out of time for the moment.


]> -- Correct task file data.
]> -- Improve the accuracy of the Atom table that passes information to the driver.
]>   
]
]Yes, that's definitely needed.
]
]
]> Signed-off-by: Scott Duplichan <scott at notabs.org>
]>   
]
]I think the patch looks good, but I'd like a few answers before I ack it.
]
]Regards,
]Carl-Daniel




From r.marek at assembler.cz  Wed Nov  3 22:34:29 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 03 Nov 2010 22:34:29 +0100
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in
 Win7 (revised)
In-Reply-To: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
Message-ID: <4CD1D565.4070608@assembler.cz>

Hi Scott,

I tried to boot with that on famF CPU and it went well.
ruiktest:~#
ruiktest:~# lspci -vvv -s 01:05.0

01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4200] 
(prog-if 00 [VGA controller])
	Subsystem: ATI Technologies Inc Device 0000
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- 
SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 18
	Region 0: Memory at e8000000 (32-bit, prefetchable) [size=128M]
	Region 1: I/O ports at 1000 [size=256]
	Region 2: Memory at f8100000 (32-bit, non-prefetchable) [size=64K]
	Region 5: Memory at f8000000 (32-bit, non-prefetchable) [size=1M]
	Expansion ROM at <unassigned> [disabled]
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
		Address: 0000000000000000  Data: 0000
	Kernel driver in use: radeon

The BAR seems to be enabled. Btw I tried to boot Win7 but still got only logo 
animation forever. Not sure what it could be.

I agree that this patch is big improvement. We can fix the MMCONF later.

Thanks,
Rudolf



From svn at coreboot.org  Wed Nov  3 22:46:42 2010
From: svn at coreboot.org (repository service)
Date: Wed, 03 Nov 2010 22:46:42 +0100
Subject: [coreboot] [commit] r6017 - in trunk/src/superio/fintek: . f71889
Message-ID: <E1PDlAI-0000E2-4v@ra.coresystems.de>

Author: uwe
Date: Wed Nov  3 22:46:41 2010
New Revision: 6017
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6017

Log:
Add Fintek F71889 Super I/O support.

Untested, but should work mostly (even though some TODOs remain).

Signed-off-by: Alec Ari <neotheuser at ymail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Added:
   trunk/src/superio/fintek/f71889/
   trunk/src/superio/fintek/f71889/Makefile.inc
   trunk/src/superio/fintek/f71889/chip.h
   trunk/src/superio/fintek/f71889/f71889.h
   trunk/src/superio/fintek/f71889/f71889_early_serial.c
   trunk/src/superio/fintek/f71889/superio.c
Modified:
   trunk/src/superio/fintek/Kconfig
   trunk/src/superio/fintek/Makefile.inc

Modified: trunk/src/superio/fintek/Kconfig
==============================================================================
--- trunk/src/superio/fintek/Kconfig	Wed Nov  3 14:24:29 2010	(r6016)
+++ trunk/src/superio/fintek/Kconfig	Wed Nov  3 22:46:41 2010	(r6017)
@@ -4,3 +4,5 @@
 	bool
 config SUPERIO_FINTEK_F71859
 	bool
+config SUPERIO_FINTEK_F71889
+	bool

Modified: trunk/src/superio/fintek/Makefile.inc
==============================================================================
--- trunk/src/superio/fintek/Makefile.inc	Wed Nov  3 14:24:29 2010	(r6016)
+++ trunk/src/superio/fintek/Makefile.inc	Wed Nov  3 22:46:41 2010	(r6017)
@@ -1,3 +1,4 @@
 subdirs-y += f71805f
 subdirs-y += f71863fg
 subdirs-y += f71859
+subdirs-y += f71889

Added: trunk/src/superio/fintek/f71889/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/fintek/f71889/Makefile.inc	Wed Nov  3 22:46:41 2010	(r6017)
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Alec Ari <neotheuser at ymail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_FINTEK_F71889) += superio.c
+

Added: trunk/src/superio/fintek/f71889/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/fintek/f71889/chip.h	Wed Nov  3 22:46:41 2010	(r6017)
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Alec Ari <neotheuser at ymail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <pc80/keyboard.h>
+#include <device/device.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_fintek_f71889_ops;
+
+struct superio_fintek_f71889_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};

Added: trunk/src/superio/fintek/f71889/f71889.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/fintek/f71889/f71889.h	Wed Nov  3 22:46:41 2010	(r6017)
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Alec Ari <neotheuser at ymail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Logical Device Numbers (LDN). */
+#define F71889_FDC	0x00	/* Floppy */
+#define F71889_SP1	0x01	/* UART1 */
+#define F71889_SP2	0x02	/* UART2 */
+#define F71889_PP	0x03	/* Parallel port */
+#define F71889_HWM	0x04	/* Hardware monitor */
+#define F71889_KBC	0x05	/* Keyboard and mouse */
+#define F71889_GPIO	0x06	/* General Purpose I/O (GPIO) */
+#define F71889_VID	0x07	/* VID */
+#define F71889_SPI	0x08	/* SPI */
+#define F71889_PME	0x0a	/* Power Management Events (PME) and ACPI */
+#define F71889_VREF	0x0b	/* Vref */

Added: trunk/src/superio/fintek/f71889/f71889_early_serial.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/fintek/f71889/f71889_early_serial.c	Wed Nov  3 22:46:41 2010	(r6017)
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Alec Ari <neotheuser at ymail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/romcc_io.h>
+#include "f71889.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0xaa, port);
+}
+
+static void f71889_enable_serial(device_t dev, u16 iobase)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}

Added: trunk/src/superio/fintek/f71889/superio.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/fintek/f71889/superio.c	Wed Nov  3 22:46:41 2010	(r6017)
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Alec Ari <neotheuser at ymail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <stdlib.h>
+#include <uart8250.h>
+#include "chip.h"
+#include "f71889.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+	outb(0x87, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	outb(0xaa, dev->path.pnp.port);
+}
+
+static void f71889_init(device_t dev)
+{
+	struct superio_fintek_f71889_config *conf = dev->chip_info;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled)
+		return;
+
+	switch (dev->path.pnp.device) {
+	/* TODO: Might potentially need code for HWM or FDC etc. */
+	case F71889_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case F71889_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case F71889_KBC:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		pc_keyboard_init(&conf->keyboard);
+		break;
+	}
+}
+
+static void f71889_pnp_set_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void f71889_pnp_enable_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_enable_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void f71889_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	(dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+	pnp_exit_conf_state(dev);
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = f71889_pnp_set_resources,
+	.enable_resources = f71889_pnp_enable_resources,
+	.enable           = f71889_pnp_enable,
+	.init             = f71889_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	/* TODO: Some of the 0x7f8 etc. values may not be correct. */
+	{ &ops, F71889_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, F71889_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, F71889_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, F71889_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, F71889_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
+	{ &ops, F71889_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+	{ &ops, F71889_GPIO, },
+	{ &ops, F71889_VID,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0}, },
+	{ &ops, F71889_SPI, },
+	{ &ops, F71889_PME, },
+	{ &ops, F71889_VREF, },
+};
+
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_fintek_f71889_ops = {
+	CHIP_NAME("Fintek F71889 Super I/O")
+	.enable_dev = enable_dev
+};



From uwe at hermann-uwe.de  Wed Nov  3 22:52:50 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 3 Nov 2010 22:52:50 +0100
Subject: [coreboot] F71889 Super I/O patch
In-Reply-To: <980104.54562.qm@web114105.mail.gq1.yahoo.com>
References: <980104.54562.qm@web114105.mail.gq1.yahoo.com>
Message-ID: <20101103215250.GR3256@greenwood>

On Wed, Nov 03, 2010 at 12:18:56PM -0700, Neo The User wrote:
> Signed-off-by: Alec Ari <neotheuser at ymail.com>

Thanks, committed in r6017 with a few changes:

 - Changed unsigned int etc. to u8/u16 etc. everywhere.

 - Add the missing LDNs as per datasheet to f71889.h and added superio.c
   code to handle the devices (at least partially).

 - Add KBC stuff, this Super I/O _does_ have a keyboard LDN.

 - Fixed up pnp_dev_info as good as possible, but it seems the datasheet
   is missing some info needed to asses where to use 0x7f8 or 0xff8 etc.


> > the code off the other 785 boards. If anybody wants to test
> > the F71889 patch, feel free.

Yup, but testing is not strictly required, I'm relatively sure the
code as committed should work (though there are some TODOs).


> > Also I wasn't sure to keep the same name in the other
> > Fintek chips or not, so I changed the name to mine, and the

Yep, that's fine for such simple pieces of code which cannot be written
much differently anyways. But please do keep the (C) lines intact
when deriving/copying larger and more complex pieces of code.


> > year. I apologize if that was incorrect, and will be more
> > than willing to keep the original GNU header.

There's no such thing as a "GNU header" btw. Every file has one or
more "(C) Copyright" line(s) which list the copyright holder(s) and
the resp. years, and a text-blob which describes the license that
applies to that file (in this case it happens to be the GNU GPL).


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From ranma+coreboot at tdiedrich.de  Wed Nov  3 23:29:14 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 3 Nov 2010 23:29:14 +0100
Subject: [coreboot] [PATCH] ACPI: XP doesn't like qwords...
Message-ID: <20101103222914.GF21368@yumi.tdiedrich.de>

Since XP only implements parts of ACPI 2.0, it chokes on the TOM2 qword in the
SSDT, which is present if a board uses k8acpi_write_vars.

With the acpigen_write_name_qword("TOM2"... in place I get a
Stop A5 (0x11, 0x8, <virtual address of SSDT>, <somevalue>)
bluescreen on boot.

This patch replaces the qword with a dword, which contains (TOM2 >> 20),
giving us 1MB granularity and a limit of almost 4Exabyte of memory.
I added corresponding ShiftLeft calls in the commented out dsdt
sections that would use TOM2 if they were not commented out.

This problem was introduced with
http://tracker.coreboot.org/trac/coreboot/changeset/3953

Note that all corresponding DSDTs currently only ever check TOM2 against 0.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>

---

Index: src/northbridge/amd/amdk8/amdk8_acpi.c
===================================================================
--- src/northbridge/amd/amdk8/amdk8_acpi.c.orig	2010-11-03 23:19:03.000000000 +0100
+++ src/northbridge/amd/amdk8/amdk8_acpi.c	2010-11-03 23:19:37.000000000 +0100
@@ -270,7 +270,15 @@
 	msr = rdmsr(TOP_MEM);
 	lens += acpigen_write_name_dword("TOM1", msr.lo);
 	msr = rdmsr(TOP_MEM2);
-	lens += acpigen_write_name_qword("TOM2", (((uint64_t) msr.hi) << 32) | msr.lo);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
 
 	lens += k8acpi_write_HT();
 	//minus opcode
Index: src/mainboard/gigabyte/ma78gm/dsdt.asl
===================================================================
--- src/mainboard/gigabyte/ma78gm/dsdt.asl.orig	2010-11-03 23:19:03.000000000 +0100
+++ src/mainboard/gigabyte/ma78gm/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/asrock/939a785gmh/dsdt.asl
===================================================================
--- src/mainboard/asrock/939a785gmh/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/asrock/939a785gmh/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1122,7 +1122,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1530,7 +1530,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/kontron/kt690/dsdt.asl
===================================================================
--- src/mainboard/kontron/kt690/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/kontron/kt690/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1129,7 +1129,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1557,7 +1557,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/gigabyte/ma785gmt/dsdt.asl
===================================================================
--- src/mainboard/gigabyte/ma785gmt/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/gigabyte/ma785gmt/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/amd/mahogany/dsdt.asl
===================================================================
--- src/mainboard/amd/mahogany/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/amd/mahogany/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1126,7 +1126,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1572,7 +1572,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/amd/pistachio/dsdt.asl
===================================================================
--- src/mainboard/amd/pistachio/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/amd/pistachio/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1128,7 +1128,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1480,7 +1480,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/amd/dbm690t/dsdt.asl
===================================================================
--- src/mainboard/amd/dbm690t/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/amd/dbm690t/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1129,7 +1129,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1557,7 +1557,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/amd/mahogany_fam10/dsdt.asl
===================================================================
--- src/mainboard/amd/mahogany_fam10/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/amd/mahogany_fam10/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/amd/tilapia_fam10/dsdt.asl
===================================================================
--- src/mainboard/amd/tilapia_fam10/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/amd/tilapia_fam10/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/iei/kino-780am2-fam10/dsdt.asl
===================================================================
--- src/mainboard/iei/kino-780am2-fam10/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/iei/kino-780am2-fam10/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/jetway/pa78vm5/dsdt.asl
===================================================================
--- src/mainboard/jetway/pa78vm5/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/jetway/pa78vm5/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/technexion/tim8690/dsdt.asl
===================================================================
--- src/mainboard/technexion/tim8690/dsdt.asl.orig	2010-11-03 23:19:28.000000000 +0100
+++ src/mainboard/technexion/tim8690/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1129,7 +1129,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1557,7 +1557,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/technexion/tim5690/dsdt.asl
===================================================================
--- src/mainboard/technexion/tim5690/dsdt.asl.orig	2010-11-03 23:19:29.000000000 +0100
+++ src/mainboard/technexion/tim5690/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1129,7 +1129,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1557,7 +1557,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 
Index: src/mainboard/asus/m4a785-m/dsdt.asl
===================================================================
--- src/mainboard/asus/m4a785-m/dsdt.asl.orig	2010-11-03 23:19:29.000000000 +0100
+++ src/mainboard/asus/m4a785-m/dsdt.asl	2010-11-03 23:19:37.000000000 +0100
@@ -1168,7 +1168,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
-			External (TOM2)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
 				/*
 				* If(LNotEqual(TOM2, 0x00000000)){
 				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
 				* }
 				*/
 




From r.marek at assembler.cz  Thu Nov  4 00:07:15 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 04 Nov 2010 00:07:15 +0100
Subject: [coreboot] [patch] fix unexpacted MTRR setup for UMA memory
In-Reply-To: <924C2396-43F5-4B88-B8D0-B3162E264E46@coresystems.de>
References: <C6A6796319634D409459A0710CC85FB1@m3a78>
	<4CC0F38C.50806@gmx.net>	<0C5CDCBCD5F74440BB7BE8B8AC46DFB3@m3a78>
	<924C2396-43F5-4B88-B8D0-B3162E264E46@coresystems.de>
Message-ID: <4CD1EB23.7000303@assembler.cz>

Hi,

I just want to tell "me too", so question is we go to direction of claiming less 
ram_resource as intel do or others.

Is the AMD uma limited to < 4GB?

Thanks,
Rudolf



From njacobs8 at hetnet.nl  Thu Nov  4 00:38:43 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Thu, 4 Nov 2010 00:38:43 +0100
Subject: [coreboot]  [PATCH] Geode GX2 print(k)
Message-ID: <201011040038.43417.njacobs8@hetnet.nl>

Remove banner wrapper function and unify print(k).

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

The banner part was requested by Uwe.
This is Abuild and boot tested.

Thanks, Nils.

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From marcj303 at gmail.com  Thu Nov  4 00:52:42 2010
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 3 Nov 2010 17:52:42 -0600
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in
	Win7 (revised)
In-Reply-To: <4CD1D565.4070608@assembler.cz>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
	<4CD1D565.4070608@assembler.cz>
Message-ID: <AANLkTinQcz_egBosmUZC=wsbKRWj9ftfrABYZnj0Pv62@mail.gmail.com>

On Wed, Nov 3, 2010 at 3:34 PM, Rudolf Marek <r.marek at assembler.cz> wrote:
> Hi Scott,
>
> I tried to boot with that on famF CPU and it went well.
> ruiktest:~#
> ruiktest:~# lspci -vvv -s 01:05.0
>
> 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD
> 4200] (prog-if 00 [VGA controller])
> ? ? ? ?Subsystem: ATI Technologies Inc Device 0000
> ? ? ? ?Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B- DisINTx-
> ? ? ? ?Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
> ? ? ? ?Latency: 0, Cache Line Size: 64 bytes
> ? ? ? ?Interrupt: pin A routed to IRQ 18
> ? ? ? ?Region 0: Memory at e8000000 (32-bit, prefetchable) [size=128M]
> ? ? ? ?Region 1: I/O ports at 1000 [size=256]
> ? ? ? ?Region 2: Memory at f8100000 (32-bit, non-prefetchable) [size=64K]
> ? ? ? ?Region 5: Memory at f8000000 (32-bit, non-prefetchable) [size=1M]
> ? ? ? ?Expansion ROM at <unassigned> [disabled]
> ? ? ? ?Capabilities: [50] Power Management version 3
> ? ? ? ? ? ? ? ?Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
> PME(D0-,D1-,D2-,D3hot-,D3cold-)
> ? ? ? ? ? ? ? ?Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
> ? ? ? ?Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
> ? ? ? ? ? ? ? ?Address: 0000000000000000 ?Data: 0000
> ? ? ? ?Kernel driver in use: radeon
>
> The BAR seems to be enabled. Btw I tried to boot Win7 but still got only
> logo animation forever. Not sure what it could be.
>
> I agree that this patch is big improvement. We can fix the MMCONF later.

Was that an ack?

Maybe I misunderstand, but I don't think that there is an MMCONF
issue. The bar disable prevents the 780 MMCONF from being moved,
right?

Just curious, have you test this with Linux? I tried to load win7, but
got a ACPI stop 0xA5. I suspect that my tables are not working at all.
This is on iei kino. I will investigate more tomorrow.

Marc

-- 
http://se-eng.com



From vidwer at gmail.com  Thu Nov  4 00:51:35 2010
From: vidwer at gmail.com (Idwer Vollering)
Date: Thu, 4 Nov 2010 00:51:35 +0100
Subject: [coreboot] [PATCH] Geode GX2 print(k)
In-Reply-To: <201011040038.43417.njacobs8@hetnet.nl>
References: <201011040038.43417.njacobs8@hetnet.nl>
Message-ID: <AANLkTiknVzE7F+5kb0AtDwMJF23x5y7oz8dC8FkQT2N3@mail.gmail.com>

2010/11/4 Nils <njacobs8 at hetnet.nl>

> Remove banner wrapper function and unify print(k).
>

Index: src/northbridge/amd/gx2/raminit.c
> ===================================================================
> --- src/northbridge/amd/gx2/raminit.c    (revision 6017)
> +++ src/northbridge/amd/gx2/raminit.c    (working copy)
> @@ -26,20 +26,15 @@
>      0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
>  };
>
> -static void banner(const char *s)
> -{
> -    printk(BIOS_DEBUG, " * %s\n", s);
> -}
> -
>  static void hcf(void)
>  {
> -    print_emerg("DIE\n");
> +    printk(BIOS_EMERG, "DIE\n");
>      /* this guarantees we flush the UART fifos (if any) and also
>       * ensures that things, in general, keep going so no debug output
>       * is lost
>       */
>      while (1)
> -        print_emerg_char(0);
> +        printk(BIOS_EMERG, (0));
>  }
>
>  static void auto_size_dimm(unsigned int dimm)
> @@ -51,35 +46,35 @@
>
>      dimm_setting = 0;
>
> -    banner("Check present");
> +    printk(BIOS_DEBUG, "Check present\n");
>      /* Check that we have a dimm */
>      if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
>          return;
>      }
>
> -    banner("MODBANKS");
> +    printk(BIOS_DEBUG, "MODBANKS\n");
>      /* Field: Module Banks per DIMM */
>      /* EEPROM byte usage: (5) Number of DIMM Banks */
>      spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
>      if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
> -        print_emerg("Number of module banks not compatible\n");
> +        printk(BIOS_EMERG, "Number of module banks not compatible\n");
>          post_code(ERROR_BANK_SET);
>          hcf();
>      }
>      dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
> -    banner("FIELDBANKS");
>
> +    printk(BIOS_DEBUG, "FIELDBANKS\n");
>      /* Field: Banks per SDRAM device */
>      /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
>      spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
>      if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
> -        print_emerg("Number of device banks not compatible\n");
> +        printk(BIOS_EMERG, "Number of device banks not compatible\n");
>          post_code(ERROR_BANK_SET);
>          hcf();
>      }
>      dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
> -    banner("SPDNUMROWS");
>
> +    printk(BIOS_DEBUG, "SPDNUMROWS\n");
>      /* Field: DIMM size
>       * EEPROM byte usage:
>       *   (3)  Number of Row Addresses
> @@ -90,29 +85,29 @@
>       */
>      if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
>          || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
> -        print_emerg("Assymetirc DIMM not compatible\n");
> +        printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n");
>

"Asymmetric"


>          post_code(ERROR_UNSUPPORTED_DIMM);
>          hcf();
>      }
> -    banner("SPDBANKDENSITY");
>
> +    printk(BIOS_DEBUG, "SPDBANKDENSITY\n");
>      dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
> -    banner("DIMMSIZE");
> +    printk(BIOS_DEBUG, "DIMMSIZE\n");
>      dimm_size |= (dimm_size << 8);    /* align so 1GB(bit0) is bit 8, this
> is a little weird to get gcc to not optimize this out */
>      dimm_size &= 0x01FC;    /* and off 2GB DIMM size : not supported and
> the 1GB size we just moved up to bit 8 as well as all the extra on top */
>
>      /* Module Density * Module Banks */
>      dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;    /*
> shift to multiply by # DIMM banks */
> -    banner("BEFORT CTZ");
> +    printk(BIOS_DEBUG, "BEFORT CTZ\n");
>      dimm_size = __builtin_ctz(dimm_size);
> -    banner("TEST DIMM SIZE>7");
> +    printk(BIOS_DEBUG, "TEST DIMM SIZE>7\n");
>      if (dimm_size > 7) {    /* 7 is 512MB only support 512MB per DIMM */
> -        print_emerg("Only support up to 512MB per DIMM\n");
> +        printk(BIOS_EMERG, "Only support up to 512MB per DIMM\n");
>          post_code(ERROR_DENSITY_DIMM);
>          hcf();
>      }
>      dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
> -    banner("PAGESIZE");
> +    printk(BIOS_DEBUG, "PAGESIZE\n");
>
>  /*
>   * Field: PAGE size
> @@ -142,22 +137,22 @@
>   */
>
>      spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
> -    banner("MAXCOLADDR");
> +    printk(BIOS_DEBUG, "MAXCOLADDR\n");
>      if (spd_byte > MAX_COL_ADDR) {
> -        print_emerg("DIMM page size not compatible\n");
> +        printk(BIOS_EMERG, "DIMM page size not compatible\n");
>          post_code(ERROR_SET_PAGE);
>          hcf();
>      }
> -    banner(">11address test");
> +    printk(BIOS_DEBUG, ">11address test\n");
>      spd_byte -= 7;
>      if (spd_byte > 4) {    /* if the value is above 4 it means >11 col
> address lines */
>          spd_byte = 7;    /* which means >16k so set to disabled */
>      }
>      dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT;    /*
> 0=1k,1=2k,2=4k,etc */
>
> -    banner("RDMSR CF07");
> +    printk(BIOS_DEBUG, "RDMSR CF07\n");
>      msr = rdmsr(MC_CF07_DATA);
> -    banner("WRMSR CF07");
> +    printk(BIOS_DEBUG, "WRMSR CF07\n");
>      if (dimm == DIMM0) {
>          msr.hi &= 0xFFFF0000;
>          msr.hi |= dimm_setting;
> @@ -166,7 +161,7 @@
>          msr.hi |= dimm_setting << 16;
>      }
>      wrmsr(MC_CF07_DATA, msr);
> -    banner("ALL DONE");
> +    printk(BIOS_DEBUG, "ALL DONE\n");
>  }
>
>  static void checkDDRMax(void)
> @@ -194,7 +189,7 @@
>
>      /* current speed > max speed? */
>      if (GeodeLinkSpeed() > speed) {
> -        print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
> +        printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
>          post_code(POST_PLL_MEM_FAIL);
>          hcf();
>      }
> @@ -311,7 +306,7 @@
>      } else if ((casmap0 &= casmap1)) {
>          spd_byte = CASDDR[__builtin_ctz(casmap0)];
>      } else {
> -        print_emerg("DIMM CAS Latencies not compatible\n");
> +        printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
>          post_code(ERROR_DIFF_DIMMS);
>          hcf();
>      }
> @@ -466,53 +461,53 @@
>  {
>      uint8_t spd_byte;
>
> -    banner("sdram_set_spd_register");
> +    printk(BIOS_DEBUG, "sdram_set_spd_register\n");
>      post_code(POST_MEM_SETUP);    /* post_70h */
>
>      spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
> -    banner("Check DIMM 0");
> +    printk(BIOS_DEBUG, "Check DIMM 0\n");
>      /* Check DIMM is not Register and not Buffered DIMMs. */
>      if ((spd_byte != 0xFF) && (spd_byte & 3)) {
> -        print_emerg("DIMM0 NOT COMPATIBLE\n");
> +        printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");
>          post_code(ERROR_UNSUPPORTED_DIMM);
>          hcf();
>      }
> -    banner("Check DIMM 1");
> +    printk(BIOS_DEBUG, "Check DIMM 1\n");
>      spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
>      if ((spd_byte != 0xFF) && (spd_byte & 3)) {
> -        print_emerg("DIMM1 NOT COMPATIBLE\n");
> +        printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");
>          post_code(ERROR_UNSUPPORTED_DIMM);
>          hcf();
>      }
>
>      post_code(POST_MEM_SETUP2);    /* post_72h */
> -    banner("Check DDR MAX");
> +    printk(BIOS_DEBUG, "Check DDR MAX\n");
>
>      /* Check that the memory is not overclocked. */
>      checkDDRMax();
>
>      /* Size the DIMMS */
>      post_code(POST_MEM_SETUP3);    /* post_73h */
> -    banner("AUTOSIZE DIMM 0");
> +    printk(BIOS_DEBUG, "AUTOSIZE DIMM 0\n");
>      auto_size_dimm(DIMM0);
>      post_code(POST_MEM_SETUP4);    /* post_74h */
> -    banner("AUTOSIZE DIMM 1");
> +    printk(BIOS_DEBUG, "AUTOSIZE DIMM 1\n");
>      auto_size_dimm(DIMM1);
>
>      /* Set CAS latency */
> -    banner("set cas latency");
> +    printk(BIOS_DEBUG, "set cas latency\n");
>      post_code(POST_MEM_SETUP5);    /* post_75h */
>      setCAS();
>
>      /* Set all the other latencies here (tRAS, tRP....) */
> -    banner("set all latency");
> +    printk(BIOS_DEBUG, "set all latency\n");
>      set_latencies();
>
>      /* Set Extended Mode Registers */
> -    banner("set emrs");
> +    printk(BIOS_DEBUG, "set emrs\n");
>      set_extended_mode_registers();
>
> -    banner("set ref rate");
> +    printk(BIOS_DEBUG, "set ref rate\n");
>      /* Set Memory Refresh Rate */
>      set_refresh_rate();
>  }
> @@ -534,13 +529,13 @@
>      msr = rdmsr(MC_CF1017_DATA);
>      msr.lo = 0x0101;
>      wrmsr(MC_CF1017_DATA, msr);
> -    //print_debug("sdram_enable step 2\n");
> +    printk(BIOS_DEBUG, "sdram_enable step 2\n");
>
>      /* 3. release CKE mask to enable CKE */
>      msr = rdmsr(MC_CFCLK_DBUG);
>      msr.lo &= ~(0x03 << 8);
>      wrmsr(MC_CFCLK_DBUG, msr);
> -    //print_debug("sdram_enable step 3\n");
> +    printk(BIOS_DEBUG, "sdram_enable step 3\n");
>
>      /* 4. set and clear REF_TST 16 times, more shouldn't hurt
>       * why this is before EMRS and MRS ? */
> @@ -551,7 +546,7 @@
>          msr.lo &= ~(0x01 << 3);
>          wrmsr(MC_CF07_DATA, msr);
>      }
> -    //print_debug("sdram_enable step 4\n");
> +    printk(BIOS_DEBUG, "sdram_enable step 4\n");
>
>      /* 6. enable DLL, load Extended Mode Register by set and clear
> PROG_DRAM */
>      msr = rdmsr(MC_CF07_DATA);
> @@ -559,7 +554,7 @@
>      wrmsr(MC_CF07_DATA, msr);
>      msr.lo &= ~((0x01 << 28) | 0x01);
>      wrmsr(MC_CF07_DATA, msr);
> -    //print_debug("sdram_enable step 6\n");
> +    printk(BIOS_DEBUG, "sdram_enable step 6\n");
>
>      /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
>       * it is documented in LX datasheet */
> @@ -569,7 +564,7 @@
>      wrmsr(MC_CF07_DATA, msr);
>      msr.lo &= ~((0x01 << 27) | 0x01);
>      wrmsr(MC_CF07_DATA, msr);
> -    //print_debug("sdram_enable step 7\n");
> +    printk(BIOS_DEBUG, "sdram_enable step 7\n");
>
>      /* 8. load Mode Register by set and clear PROG_DRAM */
>      msr = rdmsr(MC_CF07_DATA);
> @@ -577,7 +572,7 @@
>      wrmsr(MC_CF07_DATA, msr);
>      msr.lo &= ~0x01;
>      wrmsr(MC_CF07_DATA, msr);
> -    //print_debug("sdram_enable step 8\n");
> +    printk(BIOS_DEBUG, "sdram_enable step 8\n");
>
>      /* wait 200 SDCLKs */
>      for (i = 0; i < 200; i++)
>


>
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
>
> The banner part was requested by Uwe.
> This is Abuild and boot tested.
>
> Thanks, Nils.
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From uwe at hermann-uwe.de  Thu Nov  4 01:16:47 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 4 Nov 2010 01:16:47 +0100
Subject: [coreboot] EPIA halting after vt8601 init
In-Reply-To: <AANLkTimZWMT5LeeEK1Bkx_iDP16TbQqUn_WLfzvdYOYJ@mail.gmail.com>
References: <AANLkTinaN=tJw7or6v8hUR+EJcQS+TEvUfkatrpX2h_V@mail.gmail.com>
	<AANLkTimZWMT5LeeEK1Bkx_iDP16TbQqUn_WLfzvdYOYJ@mail.gmail.com>
Message-ID: <20101104001646.GS3256@greenwood>

On Wed, Nov 03, 2010 at 03:00:54PM -0600, Myles Watson wrote:
> > Is this rom structure reasonable (missing fallback/romstage?):
> It's fine.  The romstage (boot block) isn't part of CBFS.
> 
> 
> > Loading stage image.
> > Check CBFS header at <hangs here>
> Normally a hang here means that the whole ROM isn't mapped, so trying
> to read from the top of the ROM hangs, even though the bootblock
> accesses work fine.

Yup, sounds like that's the problem. Here's a quick patch to fix it
by adding a rom_enable() function (and converting VT8231 to
TINYBOOTBLOCK) while I'm at it. The only problem: It won't compile ;)

    ROMCC      romstage.inc
mtrr.h:73.42: 
non const static variables not supported
make: *** [build/mainboard/via/epia/romstage.inc] Error 1

No time to investigate right now, if someone else sees the problem,
please feel free to fix and commit. Probably just some missing
"#if defined(ROMCC)" or the like.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
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From stefan.reinauer at coresystems.de  Wed Nov  3 20:48:54 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Wed, 3 Nov 2010 12:48:54 -0700
Subject: [coreboot] [PATCH] don't print too early on mcp55-based boards
In-Reply-To: <20101103165604.GA5218@countzero.vandewege.net>
References: <20101101160338.GA28294@countzero.vandewege.net>
	<20101101220141.592.qmail@stuge.se>
	<20101102222043.GN3256@greenwood>
	<20101103165604.GA5218@countzero.vandewege.net>
Message-ID: <03062997-06A1-43EF-9D53-2DF079031E0E@coresystems.de>



Sent from my mobile phone

On 03.11.2010, at 09:56, Ward Vandewege <ward at gnu.org> wrote:

> On Tue, Nov 02, 2010 at 11:20:43PM +0100, Uwe Hermann wrote:
>> I don't object to the patch, and we should probably fix this in all
>> other southbridges, I think the same problem applies there.
>> 
>> But: the die() call itself also does a printk(), so that'll still hang
>> if the error path is chosen (at that point it probably doesn't matter
>> much, though, as we die anyway).
> 
> Right, I think it does not matter. If the die happens when printk is already
> functional, great, if not it will hang there which is fine.
> 
>> I also agree that die() should have a POST code, preferrably something
>> easy to remember. It already has a commented-out "//post_code(0xff);".
>> Not sure why it's disabled, but I think it should be something other
>> than 0xff, that's a bit too "special" for my taste.
>> 
>> We have "0xee: Not supposed to get here" as per documentation/POSTCODES,
>> so maybe we can use 0xdd ("d" as in die), if that's not already used elsewhere.
> 
> So, thinking about this a little more, I'm not sure adding a post code to
> 'die' is a good idea. The problem with doing that is that it would clobber
> any previous post codes, which might be a better indicator for what's going
> wrong.
> 
> Perhaps a good way to deal with fatal runtime error conditions would be
> 
>  a) set a unique post code
>  b) call die
> 
> in the assumption that die does not clobber the post code.
> 

We could add a post code to the parameters of the die() function.

> What do you think?
> 
> Thanks,
> Ward.
> 
> -- 
> Ward Vandewege <ward at fsf.org>
> Free Software Foundation - Senior Systems Administrator
> 
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 



From scott at notabs.org  Thu Nov  4 03:45:35 2010
From: scott at notabs.org (Scott Duplichan)
Date: Wed, 3 Nov 2010 21:45:35 -0500
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
	(revised)
In-Reply-To: <AANLkTinQcz_egBosmUZC=wsbKRWj9ftfrABYZnj0Pv62@mail.gmail.com>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78><4CD1D565.4070608@assembler.cz>
	<AANLkTinQcz_egBosmUZC=wsbKRWj9ftfrABYZnj0Pv62@mail.gmail.com>
Message-ID: <3951883AA62145329EB5709F26EA2B73@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Marc Jones
Sent: Wednesday, November 03, 2010 06:53 PM
To: Rudolf Marek
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7 (revised)

]On Wed, Nov 3, 2010 at 3:34 PM, Rudolf Marek <r.marek at assembler.cz> wrote:
]> Hi Scott,
]>
]> I tried to boot with that on famF CPU and it went well.
]> ruiktest:~#
]> ruiktest:~# lspci -vvv -s 01:05.0
]>
]> 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD
]> 4200] (prog-if 00 [VGA controller])
]> ? ? ? ?Subsystem: ATI Technologies Inc Device 0000
]> ? ? ? ?Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
]> Stepping- SERR- FastB2B- DisINTx-
]> ? ? ? ?Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
]> <TAbort- <MAbort- >SERR- <PERR- INTx-
]> ? ? ? ?Latency: 0, Cache Line Size: 64 bytes
]> ? ? ? ?Interrupt: pin A routed to IRQ 18
]> ? ? ? ?Region 0: Memory at e8000000 (32-bit, prefetchable) [size=128M]
]> ? ? ? ?Region 1: I/O ports at 1000 [size=256]
]> ? ? ? ?Region 2: Memory at f8100000 (32-bit, non-prefetchable) [size=64K]
]> ? ? ? ?Region 5: Memory at f8000000 (32-bit, non-prefetchable) [size=1M]
]> ? ? ? ?Expansion ROM at <unassigned> [disabled]
]> ? ? ? ?Capabilities: [50] Power Management version 3
]> ? ? ? ? ? ? ? ?Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
]> PME(D0-,D1-,D2-,D3hot-,D3cold-)
]> ? ? ? ? ? ? ? ?Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
]> ? ? ? ?Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
]> ? ? ? ? ? ? ? ?Address: 0000000000000000 ?Data: 0000
]> ? ? ? ?Kernel driver in use: radeon
]>
]> The BAR seems to be enabled. Btw I tried to boot Win7 but still got only
]> logo animation forever. Not sure what it could be.
]>
]> I agree that this patch is big improvement. We can fix the MMCONF later.
]
]Was that an ack?
]
]Maybe I misunderstand, but I don't think that there is an MMCONF
]issue. The bar disable prevents the 780 MMCONF from being moved,
]right?
]
]Just curious, have you test this with Linux?

Slax 6.12 live CD - Good. Using I/O APIC interrupts.

Linuxmint 9 live CD - Good. Using I/O APIC interrupts.

DSL linux live CD - Flood of "APIC error on CPU0: 40(40)"
    I believe if SB700 ioxapic mode is not enabled everything is good.

WinXP x64 SP2 setup CD - An unexpected error (805246152) occurred at line
                         1831 in d:\nt\base\boot\setup\arcdisp.c

WinXP x86 SP3 setup CD - An unexpected error (805246152) occurred at line
                         1831 in d:\nt\base\boot\setup\arcdisp.c

Win7 x64 Ultimate setup DVD - setup completed quickly with zero problems.

All testing is with UMA graphics. I build the mahogany_fam10 project and
run it on an ECS A780GM-M3 board.

]I tried to load win7, but
]got a ACPI stop 0xA5. I suspect that my tables are not working at all.
]This is on iei kino. I will investigate more tomorrow.

The attached patch contains work in progress changes outside of the
previously RS780 patch. Apply it to the latest trunk code along with
the RS780 patch. This patch is good only for mahogany_fam10, not for
mahogany (family 0Fh). The ACPI changes need to be ported from family
10h to family 0Fh. Based on what Rudolf said recently, the family 0Fh
project method of passing TOM1 etc to ACPI is the preferred way, not
the family 10h method.

Use 1 or 2 GB of memory. Three should also work, although I am not sure
the memory init code can handle 3GB. As I recall memory above 4GB is 
not yet handled correctly for booting Win7.

Hopefully you can just build a mahogany_fam10 binary and run it on Kino.
Probably any RS780 video option rom will get the job done.

Thanks,
Scott

]Marc
]
]-- 
]http://se-eng.com
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From peter at stuge.se  Thu Nov  4 08:33:37 2010
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Nov 2010 08:33:37 +0100
Subject: [coreboot] [PATCH] ACPI: XP doesn't like qwords...
In-Reply-To: <20101103222914.GF21368@yumi.tdiedrich.de>
References: <20101103222914.GF21368@yumi.tdiedrich.de>
Message-ID: <20101104073337.15462.qmail@stuge.se>

Tobias Diedrich wrote:
> This patch replaces the qword with a dword, which contains (TOM2 >> 20),

Could the name be changed to reflect this?


//Peter



From peter at stuge.se  Thu Nov  4 08:46:31 2010
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Nov 2010 08:46:31 +0100
Subject: [coreboot] [PATCH] don't print too early on mcp55-based boards
In-Reply-To: <03062997-06A1-43EF-9D53-2DF079031E0E@coresystems.de>
	<20101103165604.GA5218@countzero.vandewege.net>
References: <20101101160338.GA28294@countzero.vandewege.net>
	<20101101220141.592.qmail@stuge.se>
	<20101102222043.GN3256@greenwood>
	<20101103165604.GA5218@countzero.vandewege.net>
	<03062997-06A1-43EF-9D53-2DF079031E0E@coresystems.de>
	<20101101160338.GA28294@countzero.vandewege.net>
	<20101101220141.592.qmail@stuge.se>
	<20101102222043.GN3256@greenwood>
	<20101103165604.GA5218@countzero.vandewege.net>
Message-ID: <20101104074631.16921.qmail@stuge.se>

Ward Vandewege wrote:
> I'm not sure adding a post code to 'die' is a good idea. The
> problem with doing that is that it would clobber any previous post
> codes, which might be a better indicator for what's going wrong.

I think it is important to have a special POST code for use in die()
to positively identify that that is really where the code has hung.


Stefan Reinauer wrote:
> We could add a post code to the parameters of the die() function.

I think this is a good idea, and I would like to suggest that die()
does the following:

void die(u8 post) {
  while(1) {
    post_code(0xdd);
    mdelay(700);
    post_code(post);
    mdelay(700);
  }
}

There is no printk() which is sad. I think it's better to only use
POST codes if that is the only reliable output method, but I think
it's a lot better if the print functions can just be made to not
hang if called before they can actually output something. That would
need a bit more work though, so for now I'd like to suggest the
above.


//Peter



From Zheng.Bao at amd.com  Thu Nov  4 08:55:01 2010
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Thu, 4 Nov 2010 15:55:01 +0800
Subject: [coreboot] [PATCH][superiotool]: Add an entry of fintek f81865
Message-ID: <DD1CC71B621B004FA76856E5129D6B1704411793@sbjgexmb1.amd.com>

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From ranma+coreboot at tdiedrich.de  Thu Nov  4 10:22:53 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Thu, 4 Nov 2010 10:22:53 +0100
Subject: [coreboot] [PATCH] ACPI: XP doesn't like qwords...
In-Reply-To: <20101104073337.15462.qmail@stuge.se>
References: <20101103222914.GF21368@yumi.tdiedrich.de>
	<20101104073337.15462.qmail@stuge.se>
Message-ID: <20101104092253.GH21368@yumi.tdiedrich.de>

Peter Stuge wrote:
> Tobias Diedrich wrote:
> > This patch replaces the qword with a dword, which contains (TOM2 >> 20),
> 
> Could the name be changed to reflect this?

Any suggestions?
Being limited to 4 characters there is not much you can do to convey this...

TM2S? (Top of memory 2 shifted)

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From peter at stuge.se  Thu Nov  4 10:24:13 2010
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Nov 2010 10:24:13 +0100
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems
	in	Win7 (revised)
In-Reply-To: <0262D18532FD466FABE0B2E0DCECDE61@m3a78>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78> <4CD1A671.2070304@gmx.net>
	<0262D18532FD466FABE0B2E0DCECDE61@m3a78>
Message-ID: <20101104092413.28084.qmail@stuge.se>

Scott Duplichan wrote:
> With the unpatched code, the PCI resource allocation code finds bar
> 3 writable and assigns it a base address. In my case it assigned
> C0000000. This C000000 range is unusable because it is not the
> range set aside for mmconf. I have mmconf at F8000000.

Do we need a parameter for the resource allocator to know if a
resource should go within or outside mmconf?


//Peter



From arne.gleditsch at numascale.com  Thu Nov  4 10:37:36 2010
From: arne.gleditsch at numascale.com (Arne Georg Gleditsch)
Date: Thu, 04 Nov 2010 10:37:36 +0100
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in
	Win7 (revised)
In-Reply-To: <C030A2F7944A40AE9FC019041544BB6A@m3a78> (Scott Duplichan's
	message of "Tue, 2 Nov 2010 23:29:10 -0500")
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
Message-ID: <kjmbp65sa3j.fsf@pelargir.numascale.com>

"Scott Duplichan" <scott at notabs.org> writes:
> -- Disable the family 10h processor mmconf while the RS780 mmconf is in use.

I'm not sure I understand how this is supposed to work.  Shouldn't we
just make sure the two mmconf regions don't overlap?  (Or is the overlap
intended?)  To be frank, I'm not sure what the RS780 mmconf offers over
the Fam10 mmconf at all.  For Fam0f, I assume it is useful in order to
reach extended config space, but as far as I know that should be covered
by the Fam10 mmconf already.

> +	// disable processor pcie mmio, if enabled
> +	if (is_family10h()) {
> +		msr_t temp;
> +		pcie_mmio_save = temp = rdmsr (0xc0010058);
> +		temp.lo &= ~1;
> +		wrmsr (0xc0010058, temp);
> +	}
> +
>  	/* Get PCIe configuration space. */
>  	MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0;

This pci_read_config32 is targeting the Fam10 mmconf area, which is now
disabled.  Are we relying on the rs780 mmconf to back this address
region at this point?  If so, we probably should take care to make sure
the address assignments match (or rather, document that they need to
match).  If we need to do this at all, that is.

>  	/* Temporarily disable PCIe configuration space. */
>  	set_htiu_enable_bits(nb_dev, 0x32, 1<<28, 0);

But here we disable the rs780 mmconf, no?  Who's backing the mmconf
address region now:

> +	// 1E: NB_BIF_SPARE
>  	set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7);
>  	/* Set a temporary Bus number. */
>  	apc18 = pci_read_config32(dev, 0x18);

?

Apologies if I have misunderstood something, I haven't quite kept up
with the discussion.  I'm just a bit concerned about these changes.

-- 
								Arne.



From neotheuser at ymail.com  Thu Nov  4 16:17:40 2010
From: neotheuser at ymail.com (Neo The User)
Date: Thu, 4 Nov 2010 08:17:40 -0700 (PDT)
Subject: [coreboot] [superiotool] Fix VID / SPI registers for F71889
Message-ID: <596879.86361.qm@web114117.mail.gq1.yahoo.com>

Hi, The SPI should be on 0x8, not 0x7, as that is the VID. I double checked the datasheet and came across this while working on the coreboot port for my board. This is a follow-up for the initial F71889 support for superiotool.


      
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From neotheuser at ymail.com  Thu Nov  4 16:19:49 2010
From: neotheuser at ymail.com (Neo The User)
Date: Thu, 4 Nov 2010 08:19:49 -0700 (PDT)
Subject: [coreboot] [superiotool] Fix VID / SPI registers for F71889
Message-ID: <426206.54275.qm@web114109.mail.gq1.yahoo.com>

Sorry, I forgot to sign-off.

Signed-off-by: Alec Ari <neotheuser at ymail.com>

--- On Thu, 11/4/10, Neo The User <neotheuser at ymail.com> wrote:

> From: Neo The User <neotheuser at ymail.com>
> Subject: [superiotool] Fix VID / SPI registers for F71889
> To: coreboot at coreboot.org
> Date: Thursday, November 4, 2010, 3:17 PM
> Hi, The SPI should be on 0x8, not
> 0x7, as that is the VID. I double checked the datasheet and
> came across this while working on the coreboot port for my
> board. This is a follow-up for the initial F71889 support
> for superiotool.
> 
> 
> ? ? ? 


      



From scott at notabs.org  Thu Nov  4 17:03:20 2010
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 4 Nov 2010 11:03:20 -0500
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
	(revised)
In-Reply-To: <kjmbp65sa3j.fsf@pelargir.numascale.com>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
	<kjmbp65sa3j.fsf@pelargir.numascale.com>
Message-ID: <764D695859364DBF9D1D1AB7AB036A93@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Arne Georg Gleditsch
Sent: Thursday, November 04, 2010 04:38 AM
To: Scott Duplichan
Cc: 'Peter Stuge'; 'Carl-Daniel Hailfinger'; coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7 (revised)

"Scott Duplichan" <scott at notabs.org> writes:
> -- Disable the family 10h processor mmconf while the RS780 mmconf is in use.

]I'm not sure I understand how this is supposed to work.  Shouldn't we
]just make sure the two mmconf regions don't overlap?  (Or is the overlap
]intended?)  To be frank, I'm not sure what the RS780 mmconf offers over
]the Fam10 mmconf at all.  For Fam0f, I assume it is useful in order to
]reach extended config space, but as far as I know that should be covered
]by the Fam10 mmconf already.

No doubt there different, and possibly simpler, ways to make this work.
The patch I submitted attempts to follow the method used by the AMD CIMx
reference code. 

]> +	// disable processor pcie mmio, if enabled
]> +	if (is_family10h()) {
]> +		msr_t temp;
]> +		pcie_mmio_save = temp = rdmsr (0xc0010058);
]> +		temp.lo &= ~1;
]> +		wrmsr (0xc0010058, temp);
]> +	}
]> +
]>  	/* Get PCIe configuration space. */
]>  	MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0;
]
]This pci_read_config32 is targeting the Fam10 mmconf area, which is now
]disabled.  Are we relying on the rs780 mmconf to back this address
]region at this point?

When I step through this pci_read_config32 call (on simnow) I see it using
the cf8/cfc method for config access, not the mmio method.

]If so, we probably should take care to make sure
]the address assignments match (or rather, document that they need to
]match).  If we need to do this at all, that is.
]
]>  	/* Temporarily disable PCIe configuration space. */
]>  	set_htiu_enable_bits(nb_dev, 0x32, 1<<28, 0);
]
]But here we disable the rs780 mmconf, no?  Who's backing the mmconf
]address region now:

Again it looks like all config space access is done with cf8/cfc for
these calls.

]
]> +	// 1E: NB_BIF_SPARE
]>  	set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7);
]>  	/* Set a temporary Bus number. */
]>  	apc18 = pci_read_config32(dev, 0x18);
]
]?
]
]Apologies if I have misunderstood something, I haven't quite kept up
]with the discussion.  I'm just a bit concerned about these changes.
]-- 
]								Arne.





From mylesgw at gmail.com  Thu Nov  4 17:09:14 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 4 Nov 2010 10:09:14 -0600
Subject: [coreboot] EPIA halting after vt8601 init
In-Reply-To: <20101104001646.GS3256@greenwood>
References: <AANLkTinaN=tJw7or6v8hUR+EJcQS+TEvUfkatrpX2h_V@mail.gmail.com>
	<AANLkTimZWMT5LeeEK1Bkx_iDP16TbQqUn_WLfzvdYOYJ@mail.gmail.com>
	<20101104001646.GS3256@greenwood>
Message-ID: <AANLkTin4tMRFdj9PkjShFRrod4cNE2dPA4e0qXa5Fs9s@mail.gmail.com>

>> > Loading stage image.
>> > Check CBFS header at <hangs here>
>> Normally a hang here means that the whole ROM isn't mapped, so trying
>> to read from the top of the ROM hangs, even though the bootblock
>> accesses work fine.
>
> Yup, sounds like that's the problem. Here's a quick patch to fix it
> by adding a rom_enable() function (and converting VT8231 to
> TINYBOOTBLOCK) while I'm at it. The only problem: It won't compile ;)
>
> No time to investigate right now, if someone else sees the problem,
> please feel free to fix and commit. Probably just some missing
> "#if defined(ROMCC)" or the like.
I just simplified the patch.  TINYBOOTBLOCK can come later.

It compiles.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From arne.gleditsch at numascale.com  Thu Nov  4 18:16:25 2010
From: arne.gleditsch at numascale.com (Arne Georg Gleditsch)
Date: Thu, 04 Nov 2010 18:16:25 +0100
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
	(revised)
In-Reply-To: <764D695859364DBF9D1D1AB7AB036A93@m3a78> (Scott Duplichan's
	message of "Thu, 4 Nov 2010 11:03:20 -0500")
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
	<kjmbp65sa3j.fsf@pelargir.numascale.com>
	<764D695859364DBF9D1D1AB7AB036A93@m3a78>
Message-ID: <87eib1ggba.fsf@taniquetil.gledits.ch>

"Scott Duplichan" <scott at notabs.org> writes:
> When I step through this pci_read_config32 call (on simnow) I see it using
> the cf8/cfc method for config access, not the mmio method.

Ok, that sounds like CONFIG_MMCONF_SUPPORT_DEFAULT is not set, is that
right?  Presuming that's so, I'm worried that this code will break for
boards where MMCONFIG is enabled per default.

-- 
							Arne.



From harald.gutmann at gmx.net  Thu Nov  4 18:55:28 2010
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 4 Nov 2010 18:55:28 +0100
Subject: [coreboot] MCP55 Mac Address copying/change
Message-ID: <201011041855.28624.harald.gutmann@gmx.net>

Hello!

Yesterday I tried coreboot again, and it worked fine so far.

But I faced a nasty problem, like the last time I tried it with the MAC 
address on MCP55. This is nothing serious as you can change it by editing the 
romcache.inc from the southbridge, but it's nasty.

I was thinking about fixing this in a decent way. I'd love to see a KConfig 
value to enter in the configure process to get this done, or even to copy the 
mac address of the board.

As of now the MAC is stored in the romcache.inc file of the southbridge, and as 
far as I guess, this value is read in the mcp55_nic.c and used. There is as of 
now in the bugtracker a script to apply the new mac after compiling the image, 
but I think this is not a really good solution.

If my guess is right, readout from romcache.inc and usage in mcp55_nic.c it 
should be possible to solve this via  KConfig, and not read the value from the 
romcache.inc, but store it a config value and take this value. Possibly with a 
fallback on the romcache.inc value.

My questions on this suggestion are:
Would there be any good reason not to do it that way?
Is my guess right?  (Until now I didn't look that careful into the code of 
mcp55_nic.c.)

If my guess is right, and there is no problem to do as suggested, I'd prepare 
a patch for it.
Any comments are welcome.


Kind regards,
Harald



From harald.gutmann at gmx.net  Thu Nov  4 18:46:07 2010
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 4 Nov 2010 18:46:07 +0100
Subject: [coreboot] Gigabyte M57SLI - some troubles with recent coreboot
	version
Message-ID: <201011041846.08467.harald.gutmann@gmx.net>

Hello readers,

after some while I tried to use coreboot again on my well supported Gigabyte 
M57SLI and I was really happy, that the first built image booted the machine.

Last time I tried this, I stumbled across an error with the RAM, and had no 
time to investigate this further.

With the recent version of coreboot (r6013) I get some errors which I'd like 
to fix. I don't know if some changes to coreboot happened in the meanwhile or, 
if the kernel got changed so that this errors appear. My kernel version 
running is from debian sid with the version number 2.6.32-27 for AMD64.

The problems I get are the following:
[    0.000000] mtrr: your BIOS has set up an incorrect mask, fixing it up.
[    0.000000] Modules linked in:
[    0.000000] Pid: 0, comm: swapper Not tainted 2.6.32-5-amd64 #1
[    0.000000] Call Trace:
[    0.000000]  [<ffffffff8102189f>] ? generic_get_mtrr+0xbf/0xf9
[    0.000000]  [<ffffffff8102189f>] ? generic_get_mtrr+0xbf/0xf9                                                                                                                                                                            
[    0.000000]  [<ffffffff8104dd8c>] ? warn_slowpath_common+0x77/0xa3                                                                                                                                                                        
[    0.000000]  [<ffffffff8104de14>] ? warn_slowpath_fmt+0x51/0x59                                                                                                                                                                           
[    0.000000]  [<ffffffff810219ab>] ? mtrr_wrmsr+0x1c/0x49                                                                                                                                                                                  
[    0.000000]  [<ffffffff81021bb0>] ? get_fixed_ranges+0x71/0x98                                                                                                                                                                            
[    0.000000]  [<ffffffff810219ab>] ? mtrr_wrmsr+0x1c/0x49                                                                                                                                                                                  
[    0.000000]  [<ffffffff81021a6f>] ? prepare_set+0x97/0x9d                                                                                                                                                                                 
[    0.000000]  [<ffffffff81021ac8>] ? post_set+0x53/0x60                                                                                                                                                                                    
[    0.000000]  [<ffffffff814fb0d6>] ? get_mtrr_state+0x2eb/0x2f6                                                                                                                                                                            
[    0.000000]  [<ffffffff8102189f>] ? generic_get_mtrr+0xbf/0xf9                                                                                                                                                                            
[    0.000000]  [<ffffffff812f96e3>] ? printk+0x4e/0x5b                                                                                                                                                                                      
[    0.000000]  [<ffffffff814fbcad>] ? mtrr_trim_uncached_memory+0x91/0x311                                                                                                                                                                  
[    0.000000]  [<ffffffff814fac46>] ? mtrr_bp_init+0x1b1/0x1d4
[    0.000000]  [<ffffffff8123a7b7>] ? dmi_name_in_serial+0x1d/0x28
[    0.000000]  [<ffffffff81504f2b>] ? early_gart_iommu_check+0x9b/0x287
[    0.000000]  [<ffffffff814f7141>] ? setup_arch+0x43f/0x9cb
[    0.000000]  [<ffffffff811f6a9f>] ? extract_entropy+0x6a/0x125
[    0.000000]  [<ffffffff814f3140>] ? early_idt_handler+0x0/0x71
[    0.000000]  [<ffffffff814f39d0>] ? start_kernel+0xdb/0x3e8
[    0.000000]  [<ffffffff814f33b7>] ? x86_64_start_kernel+0xf9/0x106
[    0.000000] ---[ end trace a7919e7f17c0a725 ]---
[    0.000000] initial memory mapped : 0 - 20000000
[    0.000000] init_memory_mapping: 0000000000000000-000000007ffef000
[    0.000000]  0000000000 - 007fe00000 page 2M
[    0.000000]  007fe00000 - 007ffef000 page 4k
[    0.000000] kernel direct mapping tables up to 7ffef000 @ 8000-c000
[    0.000000] RAMDISK: 37753000 - 37fefe82

According to /proc/mtrr it looks like something failed on the MTRR setup:
reg00: base=0x000000000 (    0MB), size= 2048MB, count=1: write-back

I don't really know how this table looked like the last time I had coreboot 
running without troubles (it was around my last commit about rev. 4362), but 
it definitely had no MTRR error and the table contained more lines with 
different values. Rudolf Marek told me yesterday on the IRC that there are some 
MTRR problems with different boards, but not the same type of problem.


The second one, which is delaying the boot process form the kernel is 
something regarding the USB controller on the board.
Here are the messages from the dmesg, but right now I didn't look that up in 
detail until now:
[    1.038117] hub 2-0:1.0: USB hub found
[    1.396015] usb 1-10: new high speed USB device using ehci_hcd and address 
4
[   11.528167] usb 1-10: device descriptor read/all, error -110
[   11.640020] usb 1-10: new high speed USB device using ehci_hcd and address 
5
[   21.772039] usb 1-10: device descriptor read/all, error -110
[   21.884014] usb 1-10: new high speed USB device using ehci_hcd and address 
6
[   26.904039] usb 1-10: device descriptor read/8, error -110
Oh, I just saw that this could be related to a new USB device which doesn't 
give a proper name via USB identification. - Need to try booting without device 
or booting on the proprietary bios.


On the last point I'm not really sure if I should call it problem, or if this 
is just warnings/errors from kernel changes:[    5.400416] k8temp 
0000:00:18.3: Temperature readouts might be wrong - check erratum #141
[    5.670067] EDAC MC: Ver: 2.1.0 Oct 30 2010
[    5.671976] EDAC amd64_edac:  Ver: 3.2.0 Oct 30 2010
[    5.672079] EDAC amd64: This node reports that Memory ECC is currently 
disabled, set F3x44[22] (0000:00:18.3).
[    5.672087] EDAC amd64: ECC disabled in the BIOS or no ECC capability, 
module will not load.
[    5.672088]  Either enable ECC checking or force module loading by setting 
'ecc_enable_override'.
[    5.672089]  (Note that use of the override may cause unknown side effects.)
[    5.672113] amd64_edac: probe of 0000:00:18.2 failed with error -22


About the temperature readouts I'm not sure if this is only a warning, because 
I know that there was some discussion about this erratum from AMD on the list.
Does anyone know something about this one?

The ECC check might also only be a warning, as the mainboard (afaik) does not 
support ECC ram. Hints on that one?



For everyone who read until here, thank you for your time reading the mail.


Kind regards,
Harald Gutmann





From uwe at hermann-uwe.de  Thu Nov  4 19:25:16 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 4 Nov 2010 19:25:16 +0100
Subject: [coreboot] EPIA halting after vt8601 init
In-Reply-To: <AANLkTin4tMRFdj9PkjShFRrod4cNE2dPA4e0qXa5Fs9s@mail.gmail.com>
References: <AANLkTinaN=tJw7or6v8hUR+EJcQS+TEvUfkatrpX2h_V@mail.gmail.com>
	<AANLkTimZWMT5LeeEK1Bkx_iDP16TbQqUn_WLfzvdYOYJ@mail.gmail.com>
	<20101104001646.GS3256@greenwood>
	<AANLkTin4tMRFdj9PkjShFRrod4cNE2dPA4e0qXa5Fs9s@mail.gmail.com>
Message-ID: <20101104182515.GJ6119@greenwood>

On Thu, Nov 04, 2010 at 10:09:14AM -0600, Myles Watson wrote:
> I just simplified the patch.  TINYBOOTBLOCK can come later.
> 
> It compiles.
> 
> Signed-off-by: Myles Watson <mylesgw at gmail.com>

True, go ahead.

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

 
Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From scott at notabs.org  Thu Nov  4 19:28:39 2010
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 4 Nov 2010 13:28:39 -0500
Subject: [coreboot] Gigabyte M57SLI - some troubles with recent
	corebootversion
In-Reply-To: <201011041846.08467.harald.gutmann@gmx.net>
References: <201011041846.08467.harald.gutmann@gmx.net>
Message-ID: <5D2EC50731B44DBE9055F98F97C7F6CA@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Harald Gutmann
Sent: Thursday, November 04, 2010 12:46 PM
To: coreboot at coreboot.org
Subject: [coreboot] Gigabyte M57SLI - some troubles with recent corebootversion

]Hello readers,
]
]after some while I tried to use coreboot again on my well supported Gigabyte 
]M57SLI and I was really happy, that the first built image booted the machine.
]
]Last time I tried this, I stumbled across an error with the RAM, and had no 
]time to investigate this further.
]
]With the recent version of coreboot (r6013) I get some errors which I'd like 
]to fix. I don't know if some changes to coreboot happened in the meanwhile or, 
]if the kernel got changed so that this errors appear. My kernel version 
]running is from debian sid with the version number 2.6.32-27 for AMD64.
]
]The problems I get are the following:
][    0.000000] mtrr: your BIOS has set up an incorrect mask, fixing it up.

It looks like your project uses an AMD family 0Fh processor. Windows 7 
checked build makes a blue screen due to the variable MTRR mask. It defaults
to 36, which is incorrect for his processor. 40 is needed:

Index: src/cpu/amd/model_fxx/Kconfig
===================================================================
--- src/cpu/amd/model_fxx/Kconfig	(revision 6017)
+++ src/cpu/amd/model_fxx/Kconfig	(working copy)
@@ -4,6 +4,11 @@
 	select SSE
 	select SSE2
 
+config CPU_ADDR_BITS
+	int
+	default 40
+	depends on CPU_AMD_MODEL_FXX
+
 config UDELAY_IO
 	bool
 	default n


]Kind regards,
]Harald Gutmann




From svn at coreboot.org  Thu Nov  4 19:33:42 2010
From: svn at coreboot.org (repository service)
Date: Thu, 04 Nov 2010 19:33:42 +0100
Subject: [coreboot] [commit] r6018 - in trunk/src: mainboard/via/epia
	southbridge/via/vt8231
Message-ID: <E1PE4d4-0007gD-Tm@ra.coresystems.de>

Author: myles
Date: Thu Nov  4 19:33:42 2010
New Revision: 6018
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6018

Log:
Add a rom_enable() function to via/vt8231 and call it from via/epia/romstage.c

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Added:
   trunk/src/southbridge/via/vt8231/vt8231_enable_rom.c
Modified:
   trunk/src/mainboard/via/epia/romstage.c
   trunk/src/southbridge/via/vt8231/vt8231_lpc.c

Modified: trunk/src/mainboard/via/epia/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia/romstage.c	Wed Nov  3 22:46:41 2010	(r6017)
+++ trunk/src/mainboard/via/epia/romstage.c	Thu Nov  4 19:33:42 2010	(r6018)
@@ -15,6 +15,7 @@
 #include "lib/debug.c"
 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
 #include "southbridge/via/vt8231/vt8231_early_serial.c"
+#include "southbridge/via/vt8231/vt8231_enable_rom.c"
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
@@ -86,6 +87,7 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
+	vt8231_enable_rom();
 	enable_mainboard_devices();
 	enable_smbus();
 	enable_shadow_ram();

Added: trunk/src/southbridge/via/vt8231/vt8231_enable_rom.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/via/vt8231/vt8231_enable_rom.c	Thu Nov  4 19:33:42 2010	(r6018)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+static void vt8231_enable_rom(void)
+{
+	device_t dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+	                               PCI_DEVICE_ID_VIA_8231), 0);
+
+	/*
+	 * ROM decode control register (0x43):
+	 *
+	 * Bit  Decode range
+	 * -----------------
+	 * 7	0xFFFE0000-0xFFFEFFFF
+	 * 6	0xFFF80000-0xFFFDFFFF
+	 * 5	0xFFF00000-0xFFF7FFFF
+	 * 4	0x000E0000-0x000EFFFF
+	 * 3	0x000D8000-0x000DFFFF
+	 * 2	0x000D0000-0x000D7FFF
+	 * 1	0x000C8000-0x000CFFFF
+	 * 0	0x000C0000-0x000C7FFF
+	 */
+	pci_write_config8(dev, 0x43, (1 << 7) | (1 << 6) | (1 << 5));
+}

Modified: trunk/src/southbridge/via/vt8231/vt8231_lpc.c
==============================================================================
--- trunk/src/southbridge/via/vt8231/vt8231_lpc.c	Wed Nov  3 22:46:41 2010	(r6017)
+++ trunk/src/southbridge/via/vt8231/vt8231_lpc.c	Thu Nov  4 19:33:42 2010	(r6018)
@@ -61,9 +61,6 @@
 	enables |= 0x80;
 	pci_write_config8(dev, 0x6C, enables);
 
-	// Map 4MB of FLASH into the address space
-	pci_write_config8(dev, 0x41, 0x7f);
-
 	// Set bit 6 of 0x40, because Award does it (IO recovery time)
 	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
 	// interrupts can be properly marked as level triggered.



From marcj303 at gmail.com  Thu Nov  4 18:34:41 2010
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 4 Nov 2010 11:34:41 -0600
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
	(revised)
In-Reply-To: <764D695859364DBF9D1D1AB7AB036A93@m3a78>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
	<kjmbp65sa3j.fsf@pelargir.numascale.com>
	<764D695859364DBF9D1D1AB7AB036A93@m3a78>
Message-ID: <AANLkTi=t-9zUL_XTp07k7jCMKpOH+eAGMiKX+108gK=5@mail.gmail.com>

On Thu, Nov 4, 2010 at 10:03 AM, Scott Duplichan <scott at notabs.org> wrote:
> -----Original Message-----

> ]> + ? ?// disable processor pcie mmio, if enabled
> ]> + ? ?if (is_family10h()) {
> ]> + ? ? ? ? ? ?msr_t temp;
> ]> + ? ? ? ? ? ?pcie_mmio_save = temp = rdmsr (0xc0010058);
> ]> + ? ? ? ? ? ?temp.lo &= ~1;
> ]> + ? ? ? ? ? ?wrmsr (0xc0010058, temp);
> ]> + ? ?}
> ]> +
> ]> ? ? ?/* Get PCIe configuration space. */
> ]> ? ? ?MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0;
> ]
> ]This pci_read_config32 is targeting the Fam10 mmconf area, which is now
> ]disabled. ?Are we relying on the rs780 mmconf to back this address
> ]region at this point?
>
> When I step through this pci_read_config32 call (on simnow) I see it using
> the cf8/cfc method for config access, not the mmio method.


This should be MMCONF with CONFIG_MMCONF_SUPPORT=y. Is that not the
case? Did we miss something?

Marc


-- 
http://se-eng.com



From scott at notabs.org  Thu Nov  4 19:42:38 2010
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 4 Nov 2010 13:42:38 -0500
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
	(revised)
In-Reply-To: <AANLkTi=t-9zUL_XTp07k7jCMKpOH+eAGMiKX+108gK=5@mail.gmail.com>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
	<kjmbp65sa3j.fsf@pelargir.numascale.com>
	<764D695859364DBF9D1D1AB7AB036A93@m3a78>
	<AANLkTi=t-9zUL_XTp07k7jCMKpOH+eAGMiKX+108gK=5@mail.gmail.com>
Message-ID: <EDF1256CF0714CAE8ADEE086CB9D003B@m3a78>


-----Original Message-----
From: Marc Jones [mailto:marcj303 at gmail.com] 
Sent: Thursday, November 04, 2010 12:35 PM
To: Scott Duplichan
Cc: Arne Georg Gleditsch; Peter Stuge; Carl-Daniel Hailfinger; coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7 (revised)

]On Thu, Nov 4, 2010 at 10:03 AM, Scott Duplichan <scott at notabs.org> wrote:
]> -----Original Message-----
]
]> ]> + ? ?// disable processor pcie mmio, if enabled
]> ]> + ? ?if (is_family10h()) {
]> ]> + ? ? ? ? ? ?msr_t temp;
]> ]> + ? ? ? ? ? ?pcie_mmio_save = temp = rdmsr (0xc0010058);
]> ]> + ? ? ? ? ? ?temp.lo &= ~1;
]> ]> + ? ? ? ? ? ?wrmsr (0xc0010058, temp);
]> ]> + ? ?}
]> ]> +
]> ]> ? ? ?/* Get PCIe configuration space. */
]> ]> ? ? ?MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0;
]> ]
]> ]This pci_read_config32 is targeting the Fam10 mmconf area, which is now
]> ]disabled. ?Are we relying on the rs780 mmconf to back this address
]> ]region at this point?
]>
]> When I step through this pci_read_config32 call (on simnow) I see it using
]> the cf8/cfc method for config access, not the mmio method.
]
]
]This should be MMCONF with CONFIG_MMCONF_SUPPORT=y. Is that not the
]case? Did we miss something?

Yes, CONFIG_MMCONF_SUPPORT=y for my test. OK, so let's step through
pci_write_config32(). That sould be simple enough, probably 3 or 4
processor instructions? It turns out 112 instructions with the 
optimized build! Anyway, pci_read_config32() first calls get_pbus(dev).
In the context above, get_pbus(dev) returns null. It then passes this
null pointer to ops_pci_bus, which falls back to the cf8/cfc method
because that is what pci_check_direct() found to work. I believe for
whatever reasons, the fallback code is used for early execution. Once
execution reaches post code 40, the mmconf method is used.

Thanks,
Scott

]Marc
]
]
]-- 
]http://se-eng.com




From arne.gleditsch at numascale.com  Thu Nov  4 20:25:28 2010
From: arne.gleditsch at numascale.com (Arne Georg Gleditsch)
Date: Thu, 04 Nov 2010 20:25:28 +0100
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
	(revised)
In-Reply-To: <EDF1256CF0714CAE8ADEE086CB9D003B@m3a78> (Scott Duplichan's
	message of "Thu, 4 Nov 2010 13:42:38 -0500")
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
	<kjmbp65sa3j.fsf@pelargir.numascale.com>
	<764D695859364DBF9D1D1AB7AB036A93@m3a78>
	<AANLkTi=t-9zUL_XTp07k7jCMKpOH+eAGMiKX+108gK=5@mail.gmail.com>
	<EDF1256CF0714CAE8ADEE086CB9D003B@m3a78>
Message-ID: <87aalohown.fsf@taniquetil.gledits.ch>

"Scott Duplichan" <scott at notabs.org> writes:
> Yes, CONFIG_MMCONF_SUPPORT=y for my test.

This only indicates whether support for the mmconf facility should be
compiled in.  If CONFIG_MMCONF_SUPPORT_DEFAULT isn't also set, you'll
only be using the mmconf facility if you explicitly do
pci_mmconf_read_config32 or similar.

-- 
							Arne.



From dhendrix at google.com  Thu Nov  4 20:46:16 2010
From: dhendrix at google.com (David Hendricks)
Date: Thu, 4 Nov 2010 12:46:16 -0700
Subject: [coreboot] [superiotool] patch for fintek f71889fg
In-Reply-To: <20101102194552.GL3256@greenwood>
References: <AANLkTi=KZohJ9RPtm8D7hFNfJ7BiVwEGO0t=POKjcF4M@mail.gmail.com>
	<20101102194552.GL3256@greenwood>
Message-ID: <AANLkTik5BXbWE0scn98eocmBavTfMzBz3cuHVcDUCv4R@mail.gmail.com>

On Tue, Nov 2, 2010 at 12:45 PM, Uwe Hermann <uwe at hermann-uwe.de> wrote:

> Hi,
>
> On Mon, Nov 01, 2010 at 01:02:53PM -0700, David Hendricks wrote:
> > The patch (attached) was tested by a user on IRC who had the F71889FG. I
> > wrote it using documentation from Fintek's website available here:
> > http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf
> >
> > This patch also seems to work for the F71889ED, which uses 0x09 and 0x09
> for
>
> Both times 0x09? Or is this a typo?
>

FWIW, lm-sensors has these two entries:
}, {
 name => "Fintek F71889FG Super IO Sensors",
 driver => "f71882fg",
 devid => 0x0723,
 logdev => 0x04,
 features => FEAT_IN | FEAT_FAN | FEAT_TEMP,
 }, {
 name => "Fintek F71889E Super IO Sensors",
 driver => "to-be-written",
 devid => 0x0909,
 logdev => 0x04,
 features => FEAT_IN | FEAT_FAN | FEAT_TEMP,
 }, {

I am not certain what the difference is between the two chips, if any
are discernible from superiotool's perspective. The F71889FG datasheet seems
to be the public one -- the 0x23 and 0x07 chip IDs match the documented
values. However, the chip I tested with has F71889ED printed on it and has
0x09 for the two chip ID bytes.


>
> > chip ID bytes 1 & 2. However, I have not been able to find documentation
> to
> > verify that the two chips are identical from superiotool's perspective.
> >
> > The F71889 seems popular on current generation platforms with AMD
> chipsets,
> > in case there are folks looking to try it on a presently unsupported
> > board...
> >
> > Signed-off-by: David Hendricks <dhendrix at google.com>
>
> Are you sure this is the correct patch? It doesn't seem to match the
> datasheet in a number of places, e.g. 0x20 and 0x21 (IDs) are incorrect
> in NOLDN (as well as most other values in NOLDN), some registers are
> missing
> completely, some LDNs are missing completely etc.
>
> Is this for another Super I/O, or remainders of copying another table?
>

I took a glance at the patch again and agree that there are several places
where the code does not match the doc. Probably sloppy copy + paste on my
part. Let's hold off on this patch until NTU, myself, or someone has time to
check the accuracy.

If someone happens to have a F71889*ED* datasheet with the chip ID bytes
both listed as 0x09, that would help.

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
-------------- next part --------------
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From harald.gutmann at gmx.net  Thu Nov  4 20:46:44 2010
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 4 Nov 2010 20:46:44 +0100
Subject: [coreboot] Gigabyte M57SLI - some troubles with recent
	corebootversion
In-Reply-To: <5D2EC50731B44DBE9055F98F97C7F6CA@m3a78>
References: <201011041846.08467.harald.gutmann@gmx.net>
	<5D2EC50731B44DBE9055F98F97C7F6CA@m3a78>
Message-ID: <201011042046.44659.harald.gutmann@gmx.net>

Hello Scott,

thank you for your fast reply!

Your provided solution works fine to fix the MTRR problem on my board!
Just FYI, my CPU is the following:
model name      : AMD Athlon(tm) 64 X2 Dual Core Processor 6000+

I'm just thinking if your suggested place for changing the KConfig is the right 
one, as the other boards did that config in the socket directory.
And I guess that the model_fxx directory is used in several sockets. Therefor 
I think it would be better to add that config value in "cpu/amd/socket_AM2" so 
that other sockets don't get affected with this change.


Kind regards,
Harald



On Thursday 04 November 2010 19:28:39 Scott Duplichan wrote:
> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Harald Gutmann Sent: Thursday, November 04, 2010 12:46 PM
> To: coreboot at coreboot.org
> Subject: [coreboot] Gigabyte M57SLI - some troubles with recent
> corebootversion
> 
> ]Hello readers,
> ]
> ]after some while I tried to use coreboot again on my well supported
> Gigabyte ]M57SLI and I was really happy, that the first built image booted
> the machine. ]
> ]Last time I tried this, I stumbled across an error with the RAM, and had
> no ]time to investigate this further.
> ]
> ]With the recent version of coreboot (r6013) I get some errors which I'd
> like ]to fix. I don't know if some changes to coreboot happened in the
> meanwhile or, ]if the kernel got changed so that this errors appear. My
> kernel version ]running is from debian sid with the version number
> 2.6.32-27 for AMD64. ]
> ]The problems I get are the following:
> ][    0.000000] mtrr: your BIOS has set up an incorrect mask, fixing it up.
> 
> It looks like your project uses an AMD family 0Fh processor. Windows 7
> checked build makes a blue screen due to the variable MTRR mask. It
> defaults to 36, which is incorrect for his processor. 40 is needed:
> 
> Index: src/cpu/amd/model_fxx/Kconfig
> ===================================================================
> --- src/cpu/amd/model_fxx/Kconfig	(revision 6017)
> +++ src/cpu/amd/model_fxx/Kconfig	(working copy)
> @@ -4,6 +4,11 @@
>  	select SSE
>  	select SSE2
> 
> +config CPU_ADDR_BITS
> +	int
> +	default 40
> +	depends on CPU_AMD_MODEL_FXX
> +
>  config UDELAY_IO
>  	bool
>  	default n
> 
> 
> ]Kind regards,
> ]Harald Gutmann



From scott at notabs.org  Thu Nov  4 22:29:50 2010
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 4 Nov 2010 16:29:50 -0500
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
	(revised)
In-Reply-To: <87aalohown.fsf@taniquetil.gledits.ch>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78><kjmbp65sa3j.fsf@pelargir.numascale.com><764D695859364DBF9D1D1AB7AB036A93@m3a78><AANLkTi=t-9zUL_XTp07k7jCMKpOH+eAGMiKX+108gK=5@mail.gmail.com><EDF1256CF0714CAE8ADEE086CB9D003B@m3a78>
	<87aalohown.fsf@taniquetil.gledits.ch>
Message-ID: <D44376B7200A4ECC817ABA05E8319B21@m3a78>

-----Original Message-----
From: Arne Georg Gleditsch [mailto:arne at gledits.ch] On Behalf Of Arne Georg Gleditsch
Sent: Thursday, November 04, 2010 02:25 PM
To: Scott Duplichan
Cc: 'Marc Jones'; 'Peter Stuge'; 'Carl-Daniel Hailfinger'; coreboot at coreboot.org
Subject: Re: [PATCH] Fix AMD HD 3200 uma graphics problems inWin7 (revised)

"Scott Duplichan" <scott at notabs.org> writes:
> Yes, CONFIG_MMCONF_SUPPORT=y for my test.

]This only indicates whether support for the mmconf facility should be
]compiled in.  If CONFIG_MMCONF_SUPPORT_DEFAULT isn't also set, you'll
]only be using the mmconf facility if you explicitly do
]pci_mmconf_read_config32 or similar.

Hello Arne,

That is a good point. Here are the relevant items from my config.h:
#define CONFIG_MMCONF_BUS_NUMBER 16
#define CONFIG_MMCONF_SUPPORT 1
#define CONFIG_MMCONF_BASE_ADDRESS 0xf8000000
#define CONFIG_MMCONF_SUPPORT_DEFAULT 1

]-- 
							Arne.




From scott at notabs.org  Thu Nov  4 22:51:09 2010
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 4 Nov 2010 16:51:09 -0500
Subject: [coreboot] Gigabyte M57SLI - some troubles with
	recentcorebootversion
In-Reply-To: <201011042046.44659.harald.gutmann@gmx.net>
References: <201011041846.08467.harald.gutmann@gmx.net><5D2EC50731B44DBE9055F98F97C7F6CA@m3a78>
	<201011042046.44659.harald.gutmann@gmx.net>
Message-ID: <2BF06B125F9741369D7C98D0FA20008A@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Harald Gutmann
Sent: Thursday, November 04, 2010 02:47 PM
To: coreboot at coreboot.org
Subject: Re: [coreboot] Gigabyte M57SLI - some troubles with recentcorebootversion

]Hello Scott,
]
]thank you for your fast reply!
]
]Your provided solution works fine to fix the MTRR problem on my board!
]Just FYI, my CPU is the following:
]model name      : AMD Athlon(tm) 64 X2 Dual Core Processor 6000+
]
]I'm just thinking if your suggested place for changing the KConfig is the right 
]one, as the other boards did that config in the socket directory.
]And I guess that the model_fxx directory is used in several sockets. Therefor 
]I think it would be better to add that config value in "cpu/amd/socket_AM2" so 
]that other sockets don't get affected with this change.

Hello Harald,

I chose model_fxx directory because all AMD family F processors use the 40-bit
mask. But any kconfig seems like the wrong place this kind of information. There
was some recent talk about making coreboot get this info from cpuid at runtime,
which is the method that lets Windows and linux report the problem. I might
submit such a patch. It should solve this problem for years to come.

Thanks,
Scott

]Kind regards,
]Harald



On Thursday 04 November 2010 19:28:39 Scott Duplichan wrote:
> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Harald Gutmann Sent: Thursday, November 04, 2010 12:46 PM
> To: coreboot at coreboot.org
> Subject: [coreboot] Gigabyte M57SLI - some troubles with recent
> corebootversion
> 
> ]Hello readers,
> ]
> ]after some while I tried to use coreboot again on my well supported
> Gigabyte ]M57SLI and I was really happy, that the first built image booted
> the machine. ]
> ]Last time I tried this, I stumbled across an error with the RAM, and had
> no ]time to investigate this further.
> ]
> ]With the recent version of coreboot (r6013) I get some errors which I'd
> like ]to fix. I don't know if some changes to coreboot happened in the
> meanwhile or, ]if the kernel got changed so that this errors appear. My
> kernel version ]running is from debian sid with the version number
> 2.6.32-27 for AMD64. ]
> ]The problems I get are the following:
> ][    0.000000] mtrr: your BIOS has set up an incorrect mask, fixing it up.
> 
> It looks like your project uses an AMD family 0Fh processor. Windows 7
> checked build makes a blue screen due to the variable MTRR mask. It
> defaults to 36, which is incorrect for his processor. 40 is needed:
> 
> Index: src/cpu/amd/model_fxx/Kconfig
> ===================================================================
> --- src/cpu/amd/model_fxx/Kconfig	(revision 6017)
> +++ src/cpu/amd/model_fxx/Kconfig	(working copy)
> @@ -4,6 +4,11 @@
>  	select SSE
>  	select SSE2
> 
> +config CPU_ADDR_BITS
> +	int
> +	default 40
> +	depends on CPU_AMD_MODEL_FXX
> +
>  config UDELAY_IO
>  	bool
>  	default n
> 
> 
> ]Kind regards,
> ]Harald Gutmann

-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot




From arne.gleditsch at numascale.com  Thu Nov  4 23:14:33 2010
From: arne.gleditsch at numascale.com (Arne Georg Gleditsch)
Date: Thu, 04 Nov 2010 23:14:33 +0100
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
	(revised)
In-Reply-To: <D44376B7200A4ECC817ABA05E8319B21@m3a78> (Scott Duplichan's
	message of "Thu, 4 Nov 2010 16:29:50 -0500")
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
	<kjmbp65sa3j.fsf@pelargir.numascale.com>
	<764D695859364DBF9D1D1AB7AB036A93@m3a78>
	<AANLkTi=t-9zUL_XTp07k7jCMKpOH+eAGMiKX+108gK=5@mail.gmail.com>
	<EDF1256CF0714CAE8ADEE086CB9D003B@m3a78>
	<87aalohown.fsf@taniquetil.gledits.ch>
	<D44376B7200A4ECC817ABA05E8319B21@m3a78>
Message-ID: <8762wchh2u.fsf@taniquetil.gledits.ch>

"Scott Duplichan" <scott at notabs.org> writes:
> Hello Arne,
>
> That is a good point. Here are the relevant items from my config.h:
> #define CONFIG_MMCONF_BUS_NUMBER 16
> #define CONFIG_MMCONF_SUPPORT 1
> #define CONFIG_MMCONF_BASE_ADDRESS 0xf8000000
> #define CONFIG_MMCONF_SUPPORT_DEFAULT 1

My apologies, I went back and followed your email re pci_write_config32
step through properly, and of course you're right.  In this context this
doesn't really matter, since the pci_ops_mmconf selected by the fam10
northbridge are not invoked.  So provided we're not (inadvertently)
making config space accesses that do so, switching the mapping around
should be fairly safe.

(That said, if these accesses are not touching that address region, what
accesses are?  If none actually do, switching the mapping around
wouldn't really seem to accomplish much?  Anyway, it seems my
understanding of this particular code is less complete than I thought,
so I'll butt out of this discussion for now.)

-- 
							Arne.



From njacobs8 at hetnet.nl  Thu Nov  4 23:35:56 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Thu, 4 Nov 2010 23:35:56 +0100
Subject: [coreboot]  [PATCH] Geode GX2 print(k) V2
Message-ID: <201011042335.56685.njacobs8@hetnet.nl>

Remove banner wrapper function and unify print(k).

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

The banner part was requested by Uwe.
This is Abuild and boot tested.

V2:Also change Assymetirc into Asymmetric thanks to Idwer for spotting.

Thanks, Nils.
-------------- next part --------------
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From svn at coreboot.org  Fri Nov  5 00:23:48 2010
From: svn at coreboot.org (repository service)
Date: Fri, 05 Nov 2010 00:23:48 +0100
Subject: [coreboot] [commit] r6019 - in trunk/src: devices include/device
Message-ID: <E1PE99o-0008AW-9a@ra.coresystems.de>

Author: uwe
Date: Fri Nov  5 00:23:47 2010
New Revision: 6019
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6019

Log:
Various cosmetic and coding style fixes in src/devices.

Also:

 - Improve a few code comments, fix typos, etc.

 - Change a few more variable types to u8/u16/u32 etc.

 - Make some very long lines fit into 80chars/line.

 - Drop a huge duplicated comment, use "@see" to refer to the other one.

 - Reduce nesting level a bit by restructuring some code chunks.

 - s/Config.lb/devicetree.cb/ in a few places.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/devices/agp_device.c
   trunk/src/devices/cardbus_device.c
   trunk/src/devices/device.c
   trunk/src/devices/device_util.c
   trunk/src/devices/hypertransport.c
   trunk/src/devices/pci_device.c
   trunk/src/devices/pci_ops.c
   trunk/src/devices/pci_rom.c
   trunk/src/devices/pciexp_device.c
   trunk/src/devices/pcix_device.c
   trunk/src/devices/pnp_device.c
   trunk/src/devices/smbus_ops.c
   trunk/src/include/device/device.h
   trunk/src/include/device/pci.h
   trunk/src/include/device/pci_ops.h

Modified: trunk/src/devices/agp_device.c
==============================================================================
--- trunk/src/devices/agp_device.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/agp_device.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -26,27 +26,30 @@
 
 static void agp_tune_dev(device_t dev)
 {
-	unsigned cap;
+	unsigned int cap;
+
 	cap = pci_find_capability(dev, PCI_CAP_ID_AGP);
-	if (!cap) {
+	if (!cap)
 		return;
-	}
-	/* The OS is responsible for AGP tuning so do nothing here */
+
+	/* The OS is responsible for AGP tuning so do nothing here. */
 }
 
-unsigned int agp_scan_bus(struct bus *bus,
-	unsigned min_devfn, unsigned max_devfn, unsigned int max)
+unsigned int agp_scan_bus(struct bus *bus, unsigned int min_devfn,
+			  unsigned int max_devfn, unsigned int max)
 {
 	device_t child;
+
 	max = pci_scan_bus(bus, min_devfn, max_devfn, max);
-	for(child = bus->children; child; child = child->sibling) {
-		if (	(child->path.pci.devfn < min_devfn) ||
-			(child->path.pci.devfn > max_devfn))
-		{
+
+	for (child = bus->children; child; child = child->sibling) {
+		if ((child->path.pci.devfn < min_devfn) ||
+		    (child->path.pci.devfn > max_devfn)) {
 			continue;
 		}
 		agp_tune_dev(child);
 	}
+
 	return max;
 }
 
@@ -55,7 +58,7 @@
 	return do_pci_scan_bridge(dev, max, agp_scan_bus);
 }
 
-/** Default device operations for AGP bridges */
+/** Default device operations for AGP bridges. */
 static struct pci_operations agp_bus_ops_pci = {
 	.set_subsystem = 0,
 };
@@ -64,8 +67,8 @@
 	.read_resources   = pci_bus_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_bus_enable_resources,
-	.init		  = 0,
-	.scan_bus	  = agp_scan_bridge,
+	.init             = 0,
+	.scan_bus         = agp_scan_bridge,
 	.enable           = 0,
 	.reset_bus        = pci_bus_reset,
 	.ops_pci          = &agp_bus_ops_pci,

Modified: trunk/src/devices/cardbus_device.c
==============================================================================
--- trunk/src/devices/cardbus_device.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/cardbus_device.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -42,36 +42,32 @@
 		resource_t min_size, unsigned int index, unsigned long type)
 {
 	struct resource *resource;
+	unsigned long gran;
+	resource_t step;
 
 	/* Initialize the constraints on the current bus. */
 	resource = NULL;
-	if (moving) {
-		unsigned long gran;
-		resource_t step;
+	if (!moving)
+		return;
 
-		resource = new_resource(dev, index);
-		resource->size = 0;
-		gran = 0;
-		step = 1;
-		while ((moving & step) == 0) {
-			gran += 1;
-			step <<= 1;
-		}
-		resource->gran = gran;
-		resource->align = gran;
-		resource->limit = moving | (step - 1);
-		resource->flags = type;
+	resource = new_resource(dev, index);
+	resource->size = 0;
+	gran = 0;
+	step = 1;
+	while ((moving & step) == 0) {
+		gran += 1;
+		step <<= 1;
+	}
+	resource->gran = gran;
+	resource->align = gran;
+	resource->limit = moving | (step - 1);
+	resource->flags = type;
 
-		/*
-		 * Don't let the minimum size exceed what we
-		 * can put in the resource.
-		 */
-		if ((min_size - 1) > resource->limit)
-			min_size = resource->limit + 1;
+	/* Don't let the minimum size exceed what we can put in the resource. */
+	if ((min_size - 1) > resource->limit)
+		min_size = resource->limit + 1;
 
-		resource->size = min_size;
-	}
-	return;
+	resource->size = min_size;
 }
 
 static void cardbus_size_bridge_resource(device_t dev, unsigned int index)

Modified: trunk/src/devices/device.c
==============================================================================
--- trunk/src/devices/device.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/device.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -18,15 +18,18 @@
 /*
  *      (c) 1999--2000 Martin Mares <mj at suse.cz>
  */
-/* lots of mods by ron minnich (rminnich at lanl.gov), with
- * the final architecture guidance from Tom Merritt (tjm at codegen.com)
+
+/*
+ * Lots of mods by Ron Minnich <rminnich at lanl.gov>, with
+ * the final architecture guidance from Tom Merritt <tjm at codegen.com>.
+ *
  * In particular, we changed from the one-pass original version to
  * Tom's recommended multiple-pass version. I wasn't sure about doing
  * it with multiple passes, until I actually started doing it and saw
- * the wisdom of Tom's recommendations ...
+ * the wisdom of Tom's recommendations...
  *
  * Lots of cleanups by Eric Biederman to handle bridges, and to
- * handle resource allocation for non-pci devices.
+ * handle resource allocation for non-PCI devices.
  */
 
 #include <console/console.h>
@@ -67,13 +70,12 @@
 	spin_lock(&dev_lock);
 
 	/* Find the last child of our parent. */
-	for (child = parent->children; child && child->sibling; /* */ ) {
+	for (child = parent->children; child && child->sibling; /* */ )
 		child = child->sibling;
-	}
 
 	dev = malloc(sizeof(*dev));
 	if (dev == 0)
-		die("DEV: out of memory.\n");
+		die("alloc_dev(): out of memory.\n");
 
 	memset(dev, 0, sizeof(*dev));
 	memcpy(&dev->path, path, sizeof(*path));
@@ -83,11 +85,10 @@
 
 	/* Add the new device to the list of children of the bus. */
 	dev->bus = parent;
-	if (child) {
+	if (child)
 		child->sibling = dev;
-	} else {
+	else
 		parent->children = dev;
-	}
 
 	/* Append a new device to the global device list.
 	 * The list is used to find devices once everything is set up.
@@ -130,12 +131,13 @@
 	/* Walk through all devices and find which resources they need. */
 	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
 		struct bus *link;
-		if (!curdev->enabled) {
+
+		if (!curdev->enabled)
 			continue;
-		}
+
 		if (!curdev->ops || !curdev->ops->read_resources) {
 			printk(BIOS_ERR, "%s missing read_resources\n",
-				   dev_path(curdev));
+			       dev_path(curdev));
 			continue;
 		}
 		curdev->ops->read_resources(curdev);
@@ -145,7 +147,7 @@
 			read_resources(link);
 	}
 	printk(BIOS_SPEW, "%s read_resources bus %d link: %d done\n",
-		    dev_path(bus->dev), bus->secondary, bus->link_num);
+	       dev_path(bus->dev), bus->secondary, bus->link_num);
 }
 
 struct pick_largest_state {
@@ -169,7 +171,7 @@
 		return;
 	}
 	if (resource->flags & IORESOURCE_FIXED)
-		return;		// Skip it.
+		return;	/* Skip it. */
 	if (last && ((last->align < resource->align) ||
 		     ((last->align == resource->align) &&
 		      (last->size < resource->size)) ||
@@ -206,7 +208,7 @@
 }
 
 /**
- * Compute allocate resources is the guts of the resource allocator.
+ * This function is the guts of the resource allocator.
  *
  * The problem.
  *  - Allocate resource locations for every device.
@@ -239,20 +241,20 @@
  * @return TODO
  */
 static void compute_resources(struct bus *bus, struct resource *bridge,
-		       unsigned long type_mask, unsigned long type)
+			      unsigned long type_mask, unsigned long type)
 {
 	struct device *dev;
 	struct resource *resource;
 	resource_t base;
 	base = round(bridge->base, bridge->align);
 
-	printk(BIOS_SPEW,  "%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx\n",
-	       dev_path(bus->dev), __func__,
+	printk(BIOS_SPEW,  "%s %s_%s: base: %llx size: %llx align: %d gran: %d"
+	       " limit: %llx\n", dev_path(bus->dev), __func__,
 	       (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
-	       "prefmem" : "mem",
-	       base, bridge->size, bridge->align, bridge->gran, bridge->limit);
+	       "prefmem" : "mem", base, bridge->size, bridge->align,
+	       bridge->gran, bridge->limit);
 
-	/* For each child which is a bridge, compute_resource_needs. */
+	/* For each child which is a bridge, compute the resource needs. */
 	for (dev = bus->children; dev; dev = dev->sibling) {
 		struct resource *child_bridge;
 
@@ -264,24 +266,28 @@
 		     child_bridge = child_bridge->next) {
 			struct bus* link;
 
-			if (!(child_bridge->flags & IORESOURCE_BRIDGE) ||
-			    (child_bridge->flags & type_mask) != type)
+			if (!(child_bridge->flags & IORESOURCE_BRIDGE)
+			    || (child_bridge->flags & type_mask) != type)
 				continue;
 
-			/* Split prefetchable memory if combined.  Many domains
+			/*
+			 * Split prefetchable memory if combined. Many domains
 			 * use the same address space for prefetchable memory
-			 * and non-prefetchable memory.  Bridges below them
-			 * need it separated.  Add the PREFETCH flag to the
-			 * type_mask and type.
+			 * and non-prefetchable memory. Bridges below them need
+			 * it separated. Add the PREFETCH flag to the type_mask
+			 * and type.
 			 */
 			link = dev->link_list;
 			while (link && link->link_num !=
 					IOINDEX_LINK(child_bridge->index))
 				link = link->next;
-			if (link == NULL)
+
+			if (link == NULL) {
 				printk(BIOS_ERR, "link %ld not found on %s\n",
 				       IOINDEX_LINK(child_bridge->index),
 				       dev_path(dev));
+			}
+
 			compute_resources(link, child_bridge,
 					  type_mask | IORESOURCE_PREFETCH,
 					  type | (child_bridge->flags &
@@ -292,37 +298,37 @@
 	/* Remember we haven't found anything yet. */
 	resource = NULL;
 
-	/* Walk through all the resources on the current bus and compute the
-	 * amount of address space taken by them.  Take granularity and
+	/*
+	 * Walk through all the resources on the current bus and compute the
+	 * amount of address space taken by them. Take granularity and
 	 * alignment into account.
 	 */
 	while ((dev = largest_resource(bus, &resource, type_mask, type))) {
 
 		/* Size 0 resources can be skipped. */
-		if (!resource->size) {
+		if (!resource->size)
 			continue;
-		}
 
 		/* Propagate the resource alignment to the bridge resource. */
-		if (resource->align > bridge->align) {
+		if (resource->align > bridge->align)
 			bridge->align = resource->align;
-		}
 
 		/* Propagate the resource limit to the bridge register. */
-		if (bridge->limit > resource->limit) {
+		if (bridge->limit > resource->limit)
 			bridge->limit = resource->limit;
-		}
 
 		/* Warn if it looks like APICs aren't declared. */
 		if ((resource->limit == 0xffffffff) &&
 		    (resource->flags & IORESOURCE_ASSIGNED)) {
-			printk(BIOS_ERR, "Resource limit looks wrong! (no APIC?)\n");
-			printk(BIOS_ERR, "%s %02lx limit %08Lx\n", dev_path(dev),
-			           resource->index, resource->limit);
+			printk(BIOS_ERR,
+			       "Resource limit looks wrong! (no APIC?)\n");
+			printk(BIOS_ERR, "%s %02lx limit %08Lx\n",
+			       dev_path(dev), resource->index, resource->limit);
 		}
 
 		if (resource->flags & IORESOURCE_IO) {
-			/* Don't allow potential aliases over the legacy PCI
+			/*
+			 * Don't allow potential aliases over the legacy PCI
 			 * expansion card addresses. The legacy PCI decodes
 			 * only 10 bits, uses 0x100 - 0x3ff. Therefore, only
 			 * 0x00 - 0xff can be used out of each 0x400 block of
@@ -331,7 +337,8 @@
 			if ((base & 0x300) != 0) {
 				base = (base & ~0x3ff) + 0x400;
 			}
-			/* Don't allow allocations in the VGA I/O range.
+			/*
+			 * Don't allow allocations in the VGA I/O range.
 			 * PCI has special cases for that.
 			 */
 			else if ((base >= 0x3b0) && (base <= 0x3df)) {
@@ -344,73 +351,53 @@
 		base += resource->size;
 
 		printk(BIOS_SPEW, "%s %02lx *  [0x%llx - 0x%llx] %s\n",
-			    dev_path(dev), resource->index,
-			    resource->base,
-			    resource->base + resource->size - 1,
-			    (resource->flags & IORESOURCE_IO) ? "io" :
-			    (resource->flags & IORESOURCE_PREFETCH) ?
-			     "prefmem" : "mem");
-	}
-	/* A pci bridge resource does not need to be a power
-	 * of two size, but it does have a minimum granularity.
-	 * Round the size up to that minimum granularity so we
-	 * know not to place something else at an address postitively
-	 * decoded by the bridge.
+		       dev_path(dev), resource->index, resource->base,
+		       resource->base + resource->size - 1,
+		       (resource->flags & IORESOURCE_IO) ? "io" :
+		       (resource->flags & IORESOURCE_PREFETCH) ?
+		        "prefmem" : "mem");
+	}
+
+	/*
+	 * A PCI bridge resource does not need to be a power of two size, but
+	 * it does have a minimum granularity. Round the size up to that
+	 * minimum granularity so we know not to place something else at an
+	 * address postitively decoded by the bridge.
 	 */
 	bridge->size = round(base, bridge->gran) -
 		       round(bridge->base, bridge->align);
 
-	printk(BIOS_SPEW, "%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n",
-		    dev_path(bus->dev), __func__,
-		    (bridge->flags & IORESOURCE_IO) ? "io" :
-		     (bridge->flags & IORESOURCE_PREFETCH) ?  "prefmem" : "mem",
-		    base, bridge->size, bridge->align, bridge->gran, bridge->limit);
+	printk(BIOS_SPEW, "%s %s_%s: base: %llx size: %llx align: %d gran: %d"
+	       " limit: %llx done\n", dev_path(bus->dev), __func__,
+	       (bridge->flags & IORESOURCE_IO) ? "io" :
+	       (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem",
+	       base, bridge->size, bridge->align, bridge->gran, bridge->limit);
 }
 
 /**
  * This function is the second part of the resource allocator.
  *
- * The problem.
- *  - Allocate resource locations for every device.
- *  - Don't overlap, and follow the rules of bridges.
- *  - Don't overlap with resources in fixed locations.
- *  - Be efficient so we don't have ugly strategies.
- *
- * The strategy.
- * - Devices that have fixed addresses are the minority so don't
- *   worry about them too much. Instead only use part of the address
- *   space for devices with programmable addresses. This easily handles
- *   everything except bridges.
+ * See the compute_resources function for a more detailed explanation.
  *
- * - PCI devices are required to have their sizes and their alignments
- *   equal. In this case an optimal solution to the packing problem
- *   exists. Allocate all devices from highest alignment to least
- *   alignment or vice versa. Use this.
- *
- * - So we can handle more than PCI run two allocation passes on bridges. The
- *   first to see how large the resources are behind the bridge, and what
- *   their alignment requirements are. The second to assign a safe address to
- *   the devices behind the bridge. This allows us to treat a bridge as just
- *   a device with a couple of resources, and not need to special case it in
- *   the allocator. Also this allows handling of other types of bridges.
- *
- * - This function assigns the resources a value.
+ * This function assigns the resources a value.
  *
  * @param bus The bus we are traversing.
  * @param bridge The bridge resource which must contain the bus' resources.
  * @param type_mask This value gets ANDed with the resource type.
  * @param type This value must match the result of the AND.
+ *
+ * @see compute_resources
  */
 static void allocate_resources(struct bus *bus, struct resource *bridge,
-			unsigned long type_mask, unsigned long type)
+			       unsigned long type_mask, unsigned long type)
 {
 	struct device *dev;
 	struct resource *resource;
 	resource_t base;
 	base = bridge->base;
 
-	printk(BIOS_SPEW, "%s %s_%s: base:%llx size:%llx align:%d gran:%d limit:%llx\n",
-	       dev_path(bus->dev), __func__,
+	printk(BIOS_SPEW, "%s %s_%s: base:%llx size:%llx align:%d gran:%d "
+	       "limit:%llx\n", dev_path(bus->dev), __func__,
 	       (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
 	       "prefmem" : "mem",
 	       base, bridge->size, bridge->align, bridge->gran, bridge->limit);
@@ -418,15 +405,15 @@
 	/* Remember we haven't found anything yet. */
 	resource = NULL;
 
-	/* Walk through all the resources on the current bus and allocate them
+	/*
+	 * Walk through all the resources on the current bus and allocate them
 	 * address space.
 	 */
 	while ((dev = largest_resource(bus, &resource, type_mask, type))) {
 
 		/* Propagate the bridge limit to the resource register. */
-		if (resource->limit > bridge->limit) {
+		if (resource->limit > bridge->limit)
 			resource->limit = bridge->limit;
-		}
 
 		/* Size 0 resources can be skipped. */
 		if (!resource->size) {
@@ -437,7 +424,8 @@
 		}
 
 		if (resource->flags & IORESOURCE_IO) {
-			/* Don't allow potential aliases over the legacy PCI
+			/*
+			 * Don't allow potential aliases over the legacy PCI
 			 * expansion card addresses. The legacy PCI decodes
 			 * only 10 bits, uses 0x100 - 0x3ff. Therefore, only
 			 * 0x00 - 0xff can be used out of each 0x400 block of
@@ -446,7 +434,8 @@
 			if ((base & 0x300) != 0) {
 				base = (base & ~0x3ff) + 0x400;
 			}
-			/* Don't allow allocations in the VGA I/O range.
+			/*
+			 * Don't allow allocations in the VGA I/O range.
 			 * PCI has special cases for that.
 			 */
 			else if ((base >= 0x3b0) && (base <= 0x3df)) {
@@ -464,36 +453,33 @@
 			base += resource->size;
 		} else {
 			printk(BIOS_ERR, "!! Resource didn't fit !!\n");
-			printk(BIOS_ERR, "   aligned base %llx size %llx limit %llx\n",
-			       round(base, resource->align), resource->size,
-			       resource->limit);
-			printk(BIOS_ERR, "   %llx needs to be <= %llx (limit)\n",
-			       (round(base, resource->align) +
+			printk(BIOS_ERR, "   aligned base %llx size %llx "
+			       "limit %llx\n", round(base, resource->align),
+			       resource->size, resource->limit);
+			printk(BIOS_ERR, "   %llx needs to be <= %llx "
+			       "(limit)\n", (round(base, resource->align) +
 				resource->size) - 1, resource->limit);
-			printk(BIOS_ERR, "   %s%s %02lx *  [0x%llx - 0x%llx] %s\n",
-			       (resource->
-				flags & IORESOURCE_ASSIGNED) ? "Assigned: " :
-			       "", dev_path(dev), resource->index,
-			       resource->base,
+			printk(BIOS_ERR, "   %s%s %02lx *  [0x%llx - 0x%llx]"
+			       " %s\n", (resource->flags & IORESOURCE_ASSIGNED)
+			       ? "Assigned: " : "", dev_path(dev),
+			       resource->index, resource->base,
 			       resource->base + resource->size - 1,
-			       (resource->
-				flags & IORESOURCE_IO) ? "io" : (resource->
-								 flags &
-								 IORESOURCE_PREFETCH)
+			       (resource->flags & IORESOURCE_IO) ? "io"
+			       : (resource->flags & IORESOURCE_PREFETCH)
 			       ? "prefmem" : "mem");
 		}
 
 		printk(BIOS_SPEW, "%s%s %02lx *  [0x%llx - 0x%llx] %s\n",
 		       (resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: "
-		       : "",
-		       dev_path(dev), resource->index, resource->base,
+		       : "", dev_path(dev), resource->index, resource->base,
 		       resource->size ? resource->base + resource->size - 1 :
-		       resource->base,
-		       (resource->flags & IORESOURCE_IO) ? "io" :
-		       (resource->flags & IORESOURCE_PREFETCH) ? "prefmem" :
-		       "mem");
+		       resource->base, (resource->flags & IORESOURCE_IO)
+		       ? "io" : (resource->flags & IORESOURCE_PREFETCH)
+		       ? "prefmem" : "mem");
 	}
-	/* A PCI bridge resource does not need to be a power of two size, but
+
+	/*
+	 * A PCI bridge resource does not need to be a power of two size, but
 	 * it does have a minimum granularity. Round the size up to that
 	 * minimum granularity so we know not to place something else at an
 	 * address positively decoded by the bridge.
@@ -501,11 +487,11 @@
 
 	bridge->flags |= IORESOURCE_ASSIGNED;
 
-	printk(BIOS_SPEW, "%s %s_%s: next_base: %llx size: %llx align: %d gran: %d done\n",
-	       dev_path(bus->dev), __func__,
+	printk(BIOS_SPEW, "%s %s_%s: next_base: %llx size: %llx align: %d "
+	       "gran: %d done\n", dev_path(bus->dev), __func__,
 	       (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
-	       "prefmem" : "mem",
-	       base, bridge->size, bridge->align, bridge->gran);
+	       "prefmem" : "mem", base, bridge->size, bridge->align,
+	       bridge->gran);
 
 	/* For each child which is a bridge, allocate_resources. */
 	for (dev = bus->children; dev; dev = dev->sibling) {
@@ -523,11 +509,12 @@
 			    (child_bridge->flags & type_mask) != type)
 				continue;
 
-			/* Split prefetchable memory if combined.  Many domains
+			/*
+			 * Split prefetchable memory if combined. Many domains
 			 * use the same address space for prefetchable memory
-			 * and non-prefetchable memory.  Bridges below them
-			 * need it separated.  Add the PREFETCH flag to the
-			 * type_mask and type.
+			 * and non-prefetchable memory. Bridges below them need
+			 * it separated. Add the PREFETCH flag to the type_mask
+			 * and type.
 			 */
 			link = dev->link_list;
 			while (link && link->link_num !=
@@ -537,6 +524,7 @@
 				printk(BIOS_ERR, "link %ld not found on %s\n",
 				       IOINDEX_LINK(child_bridge->index),
 				       dev_path(dev));
+
 			allocate_resources(link, child_bridge,
 					   type_mask | IORESOURCE_PREFETCH,
 					   type | (child_bridge->flags &
@@ -551,10 +539,10 @@
 #define MEM_MASK (IORESOURCE_MEM)
 #endif
 
-#define IO_MASK (IORESOURCE_IO)
+#define IO_MASK   (IORESOURCE_IO)
 #define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM)
-#define MEM_TYPE (IORESOURCE_MEM)
-#define IO_TYPE (IORESOURCE_IO)
+#define MEM_TYPE  (IORESOURCE_MEM)
+#define IO_TYPE   (IORESOURCE_IO)
 
 struct constraints {
 	struct resource pref, io, mem;
@@ -575,8 +563,8 @@
 			continue;
 		if (!res->size) {
 			/* It makes no sense to have 0-sized, fixed resources.*/
-			printk(BIOS_ERR, "skipping %s@%lx fixed resource, size=0!\n",
-				   dev_path(dev), res->index);
+			printk(BIOS_ERR, "skipping %s@%lx fixed resource, "
+			       "size=0!\n", dev_path(dev), res->index);
 			continue;
 		}
 
@@ -590,29 +578,34 @@
 		else
 			continue;
 
-		/* Is it a fixed resource outside the current known region?
-		   If so, we don't have to consider it - it will be handled
-		   correctly and doesn't affect current region's limits */
-		if (((res->base + res->size -1) < lim->base) || (res->base > lim->limit))
+		/*
+		 * Is it a fixed resource outside the current known region?
+		 * If so, we don't have to consider it - it will be handled
+		 * correctly and doesn't affect current region's limits.
+		 */
+		if (((res->base + res->size -1) < lim->base)
+		    || (res->base > lim->limit))
 			continue;
 
-		/* Choose to be above or below fixed resources.  This
-		 * check is signed so that "negative" amounts of space
-		 * are handled correctly.
+		/*
+		 * Choose to be above or below fixed resources. This check is
+		 * signed so that "negative" amounts of space are handled
+		 * correctly.
 		 */
-		if ((signed long long)(lim->limit - (res->base + res->size -1)) >
-		    (signed long long)(res->base - lim->base))
+		if ((signed long long)(lim->limit - (res->base + res->size -1))
+		    > (signed long long)(res->base - lim->base))
 			lim->base = res->base + res->size;
 		else
 			lim->limit = res->base -1;
 	}
 
 	/* Descend into every enabled child and look for fixed resources. */
-	for (link = dev->link_list; link; link = link->next)
-		for (child = link->children; child;
-		     child = child->sibling)
+	for (link = dev->link_list; link; link = link->next) {
+		for (child = link->children; child; child = child->sibling) {
 			if (child->enabled)
 				constrain_resources(child, limits);
+		}
+	}
 }
 
 static void avoid_fixed_resources(struct device *dev)
@@ -621,8 +614,8 @@
 	struct resource *res;
 
 	printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev));
-	/* Initialize constraints to maximum size. */
 
+	/* Initialize constraints to maximum size. */
 	limits.pref.base = 0;
 	limits.pref.limit = 0xffffffffffffffffULL;
 	limits.io.base = 0;
@@ -635,7 +628,7 @@
 		if ((res->flags & IORESOURCE_FIXED))
 			continue;
 		printk(BIOS_SPEW, "%s:@%s %02lx limit %08Lx\n", __func__,
-			     dev_path(dev), res->index, res->limit);
+		       dev_path(dev), res->index, res->limit);
 		if ((res->flags & MEM_MASK) == PREF_TYPE &&
 		    (res->limit < limits.pref.limit))
 			limits.pref.limit = res->limit;
@@ -685,7 +678,7 @@
 static void set_vga_bridge_bits(void)
 {
 	/*
-	 * FIXME: Modify set_vga_bridge so it is less PCI centric!
+	 * FIXME: Modify set_vga_bridge() so it is less PCI centric!
 	 * This function knows too much about PCI stuff, it should be just
 	 * an iterator/visitor.
 	 */
@@ -693,28 +686,30 @@
 	/* FIXME: Handle the VGA palette snooping. */
 	struct device *dev, *vga, *vga_onboard, *vga_first, *vga_last;
 	struct bus *bus;
+
 	bus = 0;
 	vga = 0;
 	vga_onboard = 0;
 	vga_first = 0;
 	vga_last = 0;
+
 	for (dev = all_devices; dev; dev = dev->next) {
+
 		if (!dev->enabled)
 			continue;
+
 		if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
 		    ((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) {
 			if (!vga_first) {
-				if (dev->on_mainboard) {
+				if (dev->on_mainboard)
 					vga_onboard = dev;
-				} else {
+				else
 					vga_first = dev;
-				}
 			} else {
-				if (dev->on_mainboard) {
+				if (dev->on_mainboard)
 					vga_onboard = dev;
-				} else {
+				else
 					vga_last = dev;
-				}
 			}
 
 			/* It isn't safe to enable other VGA cards. */
@@ -724,30 +719,31 @@
 
 	vga = vga_last;
 
-	if (!vga) {
+	if (!vga)
 		vga = vga_first;
-	}
+
 #if CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST == 1
-	if (vga_onboard)	// Will use on board VGA as pri.
+	if (vga_onboard)	/* Will use onboard VGA as primary. */
 #else
-	if (!vga)		// Will use last add on adapter as pri.
+	if (!vga)		/* Will use last add-on adapter as primary. */
 #endif
 	{
 		vga = vga_onboard;
 	}
 
 	if (vga) {
-		/* VGA is first add on card or the only onboard VGA. */
+		/* VGA is first add-on card or the only onboard VGA. */
 		printk(BIOS_DEBUG, "Setting up VGA for %s\n", dev_path(vga));
 		/* All legacy VGA cards have MEM & I/O space registers. */
 		vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 		vga_pri = vga;
 		bus = vga->bus;
 	}
+
 	/* Now walk up the bridges setting the VGA enable. */
 	while (bus) {
 		printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
-			     dev_path(bus->dev));
+		       dev_path(bus->dev));
 		bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA;
 		bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus;
 	}
@@ -758,7 +754,7 @@
 /**
  * Assign the computed resources to the devices on the bus.
  *
- * Use the device specific set_resources method to store the computed
+ * Use the device specific set_resources() method to store the computed
  * resources to hardware. For bridge devices, the set_resources() method
  * has to recurse into every down stream buses.
  *
@@ -773,21 +769,21 @@
 	struct device *curdev;
 
 	printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n",
-		    dev_path(bus->dev), bus->secondary, bus->link_num);
+	       dev_path(bus->dev), bus->secondary, bus->link_num);
 
 	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
-		if (!curdev->enabled || !curdev->resource_list) {
+		if (!curdev->enabled || !curdev->resource_list)
 			continue;
-		}
+
 		if (!curdev->ops || !curdev->ops->set_resources) {
 			printk(BIOS_ERR, "%s missing set_resources\n",
-				   dev_path(curdev));
+			       dev_path(curdev));
 			continue;
 		}
 		curdev->ops->set_resources(curdev);
 	}
 	printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n",
-		    dev_path(bus->dev), bus->secondary, bus->link_num);
+	       dev_path(bus->dev), bus->secondary, bus->link_num);
 }
 
 /**
@@ -808,15 +804,13 @@
 	struct bus *c_link;
 
 	for (dev = link->children; dev; dev = dev->sibling) {
-		if (dev->enabled && dev->ops && dev->ops->enable_resources) {
+		if (dev->enabled && dev->ops && dev->ops->enable_resources)
 			dev->ops->enable_resources(dev);
-		}
 	}
 
 	for (dev = link->children; dev; dev = dev->sibling) {
-		for (c_link = dev->link_list; c_link; c_link = c_link->next) {
+		for (c_link = dev->link_list; c_link; c_link = c_link->next)
 			enable_resources(c_link);
-		}
 	}
 }
 
@@ -851,6 +845,7 @@
 {
 	unsigned int new_max;
 	int do_scan_bus;
+
 	if (!busdev || !busdev->enabled || !busdev->ops ||
 	    !busdev->ops->scan_bus) {
 		return max;
@@ -863,11 +858,10 @@
 		do_scan_bus = 0;
 		for (link = busdev->link_list; link; link = link->next) {
 			if (link->reset_needed) {
-				if (reset_bus(link)) {
+				if (reset_bus(link))
 					do_scan_bus = 1;
-				} else {
+				else
 					busdev->bus->reset_needed = 1;
-				}
 			}
 		}
 	}
@@ -877,19 +871,19 @@
 /**
  * Determine the existence of devices and extend the device tree.
  *
- * Most of the devices in the system are listed in the mainboard Config.lb
+ * Most of the devices in the system are listed in the mainboard devicetree.cb
  * file. The device structures for these devices are generated at compile
  * time by the config tool and are organized into the device tree. This
  * function determines if the devices created at compile time actually exist
  * in the physical system.
  *
- * For devices in the physical system but not listed in the Config.lb file,
+ * For devices in the physical system but not listed in devicetree.cb,
  * the device structures have to be created at run time and attached to the
  * device tree.
  *
- * This function starts from the root device 'dev_root', scan the buses in
- * the system recursively, modify the device tree according to the result of
- * the probe.
+ * This function starts from the root device 'dev_root', scans the buses in
+ * the system recursively, and modifies the device tree according to the
+ * result of the probe.
  *
  * This function has no idea how to scan and probe buses and devices at all.
  * It depends on the bus/device specific scan_bus() method to do it. The
@@ -899,16 +893,18 @@
 void dev_enumerate(void)
 {
 	struct device *root;
+
 	printk(BIOS_INFO, "Enumerating buses...\n");
+
 	root = &dev_root;
 
-	show_all_devs(BIOS_SPEW, "Before Device Enumeration.");
+	show_all_devs(BIOS_SPEW, "Before device enumeration.");
 	printk(BIOS_SPEW, "Compare with tree...\n");
 	show_devs_tree(root, BIOS_SPEW, 0, 0);
 
-	if (root->chip_ops && root->chip_ops->enable_dev) {
+	if (root->chip_ops && root->chip_ops->enable_dev)
 		root->chip_ops->enable_dev(root);
-	}
+
 	if (!root->ops || !root->ops->scan_bus) {
 		printk(BIOS_ERR, "dev_root missing scan_bus operation");
 		return;
@@ -944,7 +940,8 @@
 
 	root = &dev_root;
 
-	/* Each domain should create resources which contain the entire address
+	/*
+	 * Each domain should create resources which contain the entire address
 	 * space for IO, MEM, and PREFMEM resources in the domain. The
 	 * allocation of device resources will be done from this address space.
 	 */
@@ -966,17 +963,17 @@
 				continue;
 			if (res->flags & IORESOURCE_PREFETCH) {
 				compute_resources(child->link_list,
-					       res, MEM_MASK, PREF_TYPE);
+						  res, MEM_MASK, PREF_TYPE);
 				continue;
 			}
 			if (res->flags & IORESOURCE_MEM) {
 				compute_resources(child->link_list,
-					       res, MEM_MASK, MEM_TYPE);
+						  res, MEM_MASK, MEM_TYPE);
 				continue;
 			}
 			if (res->flags & IORESOURCE_IO) {
 				compute_resources(child->link_list,
-					       res, IO_MASK, IO_TYPE);
+						  res, IO_MASK, IO_TYPE);
 				continue;
 			}
 		}
@@ -987,7 +984,8 @@
 		if (child->path.type == DEVICE_PATH_PCI_DOMAIN)
 			avoid_fixed_resources(child);
 
-	/* Now we need to adjust the resources. MEM resources need to start at
+	/*
+	 * Now we need to adjust the resources. MEM resources need to start at
 	 * the highest address managable.
 	 */
 	for (child = root->link_list->children; child; child = child->sibling) {
@@ -1011,17 +1009,17 @@
 				continue;
 			if (res->flags & IORESOURCE_PREFETCH) {
 				allocate_resources(child->link_list,
-					       res, MEM_MASK, PREF_TYPE);
+						   res, MEM_MASK, PREF_TYPE);
 				continue;
 			}
 			if (res->flags & IORESOURCE_MEM) {
 				allocate_resources(child->link_list,
-					       res, MEM_MASK, MEM_TYPE);
+						   res, MEM_MASK, MEM_TYPE);
 				continue;
 			}
 			if (res->flags & IORESOURCE_IO) {
 				allocate_resources(child->link_list,
-					       res, IO_MASK, IO_TYPE);
+						   res, IO_MASK, IO_TYPE);
 				continue;
 			}
 		}
@@ -1045,7 +1043,7 @@
 
 	printk(BIOS_INFO, "Enabling resources...\n");
 
-	/* now enable everything. */
+	/* Now enable everything. */
 	for (link = dev_root.link_list; link; link = link->next)
 		enable_resources(link);
 
@@ -1055,17 +1053,16 @@
 /**
  * Initialize a specific device.
  *
- * The parent should be initialized first to avoid having an ordering
- * problem. This is done by calling the parent's init()
- * method before its childrens' init() methods.
+ * The parent should be initialized first to avoid having an ordering problem.
+ * This is done by calling the parent's init() method before its childrens'
+ * init() methods.
  *
  * @param dev The device to be initialized.
  */
 static void init_dev(struct device *dev)
 {
-	if (!dev->enabled) {
+	if (!dev->enabled)
 		return;
-	}
 
 	if (!dev->initialized && dev->ops && dev->ops->init) {
 		if (dev->path.type == DEVICE_PATH_I2C) {
@@ -1084,14 +1081,12 @@
 	struct device *dev;
 	struct bus *c_link;
 
-	for (dev = link->children; dev; dev = dev->sibling) {
+	for (dev = link->children; dev; dev = dev->sibling)
 		init_dev(dev);
-	}
 
 	for (dev = link->children; dev; dev = dev->sibling) {
-		for (c_link = dev->link_list; c_link; c_link = c_link->next) {
+		for (c_link = dev->link_list; c_link; c_link = c_link->next)
 			init_link(c_link);
-		}
 	}
 }
 
@@ -1110,7 +1105,7 @@
 	/* First call the mainboard init. */
 	init_dev(&dev_root);
 
-	/* now initialize everything. */
+	/* Now initialize everything. */
 	for (link = dev_root.link_list; link; link = link->next)
 		init_link(link);
 

Modified: trunk/src/devices/device_util.c
==============================================================================
--- trunk/src/devices/device_util.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/device_util.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -41,9 +41,8 @@
 {
 	device_t child;
 	for (child = parent->children; child; child = child->sibling) {
-		if (path_eq(path, &child->path)) {
+		if (path_eq(path, &child->path))
 			break;
-		}
 	}
 	return child;
 }
@@ -59,9 +58,8 @@
 {
 	device_t child;
 	child = find_dev_path(parent, path);
-	if (!child) {
+	if (!child)
 		child = alloc_dev(parent, path);
-	}
 	return child;
 }
 
@@ -79,8 +77,8 @@
 	result = 0;
 	for (dev = all_devices; dev; dev = dev->next) {
 		if ((dev->path.type == DEVICE_PATH_PCI) &&
-			(dev->bus->secondary == bus) &&
-			(dev->path.pci.devfn == devfn)) {
+		    (dev->bus->secondary == bus) &&
+		    (dev->path.pci.devfn == devfn)) {
 			result = dev;
 			break;
 		}
@@ -97,18 +95,18 @@
  */
 struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr)
 {
-        struct device *dev, *result;
+	struct device *dev, *result;
 
-        result = 0;
-        for (dev = all_devices; dev; dev = dev->next) {
-                if ((dev->path.type == DEVICE_PATH_I2C) &&
-                        (dev->bus->secondary == bus) &&
-                        (dev->path.i2c.device == addr)) {
-                        result = dev;
-                        break;
-                }
-        }
-        return result;
+	result = 0;
+	for (dev = all_devices; dev; dev = dev->next) {
+		if ((dev->path.type == DEVICE_PATH_I2C) &&
+		    (dev->bus->secondary == bus) &&
+		    (dev->path.i2c.device == addr)) {
+			result = dev;
+			break;
+		}
+	}
+	return result;
 }
 
 /**
@@ -116,21 +114,21 @@
  *
  * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel).
  * @param device A PCI device ID.
- * @param from Pointer to the device structure, used as a starting point
- *        in the linked list of all_devices, which can be 0 to start at the
- *        head of the list (i.e. all_devices).
+ * @param from Pointer to the device structure, used as a starting point in
+ *             the linked list of all_devices, which can be 0 to start at the
+ *             head of the list (i.e. all_devices).
  * @return Pointer to the device struct.
  */
-struct device *dev_find_device(unsigned int vendor, unsigned int device,
-			       struct device *from)
+struct device *dev_find_device(u16 vendor, u16 device, struct device *from)
 {
 	if (!from)
 		from = all_devices;
 	else
 		from = from->next;
-	while (from && (from->vendor != vendor || from->device != device)) {
+
+	while (from && (from->vendor != vendor || from->device != device))
 		from = from->next;
-	}
+
 	return from;
 }
 
@@ -138,9 +136,9 @@
  * Find a device of a given class.
  *
  * @param class Class of the device.
- * @param from Pointer to the device structure, used as a starting point
- *        in the linked list of all_devices, which can be 0 to start at the
- *        head of the list (i.e. all_devices).
+ * @param from Pointer to the device structure, used as a starting point in
+ *             the linked list of all_devices, which can be 0 to start at the
+ *             head of the list (i.e. all_devices).
  * @return Pointer to the device struct.
  */
 struct device *dev_find_class(unsigned int class, struct device *from)
@@ -149,8 +147,10 @@
 		from = all_devices;
 	else
 		from = from->next;
+
 	while (from && (from->class & 0xffffff00) != class)
 		from = from->next;
+
 	return from;
 }
 
@@ -165,8 +165,7 @@
 	buffer[0] = '\0';
 	if (!dev) {
 		memcpy(buffer, "<null>", 7);
-	}
-	else {
+	} else {
 		switch(dev->path.type) {
 		case DEVICE_PATH_ROOT:
 			memcpy(buffer, "Root Device", 12);
@@ -174,12 +173,15 @@
 		case DEVICE_PATH_PCI:
 #if CONFIG_PCI_BUS_SEGN_BITS
 			sprintf(buffer, "PCI: %04x:%02x:%02x.%01x",
-				dev->bus->secondary>>8, dev->bus->secondary & 0xff,
-				PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
+				dev->bus->secondary >> 8,
+				dev->bus->secondary & 0xff,
+				PCI_SLOT(dev->path.pci.devfn),
+				PCI_FUNC(dev->path.pci.devfn));
 #else
 			sprintf(buffer, "PCI: %02x:%02x.%01x",
 				dev->bus->secondary,
-				PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
+				PCI_SLOT(dev->path.pci.devfn),
+				PCI_FUNC(dev->path.pci.devfn));
 #endif
 			break;
 		case DEVICE_PATH_PNP:
@@ -210,7 +212,8 @@
 			sprintf(buffer, "CPU_BUS: %02x", dev->path.cpu_bus.id);
 			break;
 		default:
-			printk(BIOS_ERR, "Unknown device path type: %d\n", dev->path.type);
+			printk(BIOS_ERR, "Unknown device path type: %d\n",
+			       dev->path.type);
 			break;
 		}
 	}
@@ -227,43 +230,47 @@
 int path_eq(struct device_path *path1, struct device_path *path2)
 {
 	int equal = 0;
-	if (path1->type == path2->type) {
-		switch(path1->type) {
-		case DEVICE_PATH_NONE:
-			break;
-		case DEVICE_PATH_ROOT:
-			equal = 1;
-			break;
-		case DEVICE_PATH_PCI:
-			equal = (path1->pci.devfn == path2->pci.devfn);
-			break;
-		case DEVICE_PATH_PNP:
-			equal = (path1->pnp.port == path2->pnp.port) &&
-				(path1->pnp.device == path2->pnp.device);
-			break;
-		case DEVICE_PATH_I2C:
-			equal = (path1->i2c.device == path2->i2c.device);
-			break;
-		case DEVICE_PATH_APIC:
-			equal = (path1->apic.apic_id == path2->apic.apic_id);
-			break;
-		case DEVICE_PATH_PCI_DOMAIN:
-			equal = (path1->pci_domain.domain == path2->pci_domain.domain);
-			break;
-		case DEVICE_PATH_APIC_CLUSTER:
-			equal = (path1->apic_cluster.cluster == path2->apic_cluster.cluster);
-			break;
-		case DEVICE_PATH_CPU:
-			equal = (path1->cpu.id == path2->cpu.id);
-			break;
-		case DEVICE_PATH_CPU_BUS:
-			equal = (path1->cpu_bus.id == path2->cpu_bus.id);
-			break;
-		default:
-			printk(BIOS_ERR, "Uknown device type: %d\n", path1->type);
-			break;
-		}
+
+	if (path1->type != path2->type)
+		return 0;
+
+	switch (path1->type) {
+	case DEVICE_PATH_NONE:
+		break;
+	case DEVICE_PATH_ROOT:
+		equal = 1;
+		break;
+	case DEVICE_PATH_PCI:
+		equal = (path1->pci.devfn == path2->pci.devfn);
+		break;
+	case DEVICE_PATH_PNP:
+		equal = (path1->pnp.port == path2->pnp.port) &&
+			(path1->pnp.device == path2->pnp.device);
+		break;
+	case DEVICE_PATH_I2C:
+		equal = (path1->i2c.device == path2->i2c.device);
+		break;
+	case DEVICE_PATH_APIC:
+		equal = (path1->apic.apic_id == path2->apic.apic_id);
+		break;
+	case DEVICE_PATH_PCI_DOMAIN:
+		equal = (path1->pci_domain.domain == path2->pci_domain.domain);
+		break;
+	case DEVICE_PATH_APIC_CLUSTER:
+		equal = (path1->apic_cluster.cluster
+			 == path2->apic_cluster.cluster);
+		break;
+	case DEVICE_PATH_CPU:
+		equal = (path1->cpu.id == path2->cpu.id);
+		break;
+	case DEVICE_PATH_CPU_BUS:
+		equal = (path1->cpu_bus.id == path2->cpu_bus.id);
+		break;
+	default:
+		printk(BIOS_ERR, "Uknown device type: %d\n", path1->type);
+		break;
 	}
+
 	return equal;
 }
 
@@ -276,6 +283,7 @@
 {
 	int i;
 	struct resource *new_res_list;
+
 	new_res_list = malloc(64 * sizeof(*new_res_list));
 
 	if (new_res_list == NULL)
@@ -283,7 +291,7 @@
 
 	memset(new_res_list, 0, 64 * sizeof(*new_res_list));
 
-	for (i = 0; i < 64-1; i++)
+	for (i = 0; i < 64 - 1; i++)
 		new_res_list[i].next = &new_res_list[i+1];
 
 	free_resources = new_res_list;
@@ -305,12 +313,14 @@
 		prev->next = res->next;
 	else
 		dev->resource_list = res->next;
+
 	res->next = free_resources;
 	free_resources = res;
 }
 
 /**
  * See if we have unused but allocated resource structures.
+ *
  * If so remove the allocation.
  *
  * @param dev The device to find the resource on.
@@ -318,6 +328,7 @@
 void compact_resources(device_t dev)
 {
 	struct resource *res, *next, *prev = NULL;
+
 	/* Move all of the free resources to the end */
 	for (res = dev->resource_list; res; res = next) {
 		next = res->next;
@@ -344,6 +355,7 @@
 		if (res->index == index)
 			break;
 	}
+
 	return res;
 }
 
@@ -361,10 +373,10 @@
 {
 	struct resource *resource, *tail;
 
-	/* First move all of the free resources to the end */
+	/* First move all of the free resources to the end. */
 	compact_resources(dev);
 
-	/* See if there is a resource with the appropriate index */
+	/* See if there is a resource with the appropriate index. */
 	resource = probe_resource(dev, index);
 	if (!resource) {
 		if (free_resources == NULL && !allocate_more_resources())
@@ -378,11 +390,12 @@
 		if (tail) {
 			while (tail->next) tail = tail->next;
 			tail->next = resource;
-		}
-		else
+		} else {
 			dev->resource_list = resource;
+		}
 	}
-	/* Initialize the resource values */
+
+	/* Initialize the resource values. */
 	if (!(resource->flags & IORESOURCE_FIXED)) {
 		resource->flags = 0;
 		resource->base = 0;
@@ -407,17 +420,16 @@
 {
 	struct resource *resource;
 
-	/* See if there is a resource with the appropriate index */
+	/* See if there is a resource with the appropriate index. */
 	resource = probe_resource(dev, index);
 	if (!resource) {
 		printk(BIOS_EMERG, "%s missing resource: %02x\n",
-			dev_path(dev), index);
+		       dev_path(dev), index);
 		die("");
 	}
 	return resource;
 }
 
-
 /**
  * Round a number up to the next multiple of gran.
  *
@@ -458,16 +470,18 @@
 resource_t resource_end(struct resource *resource)
 {
 	resource_t base, end;
-	/* get the base address */
+
+	/* Get the base address. */
 	base = resource->base;
 
-	/* For a non bridge resource granularity and alignment are the same.
+	/*
+	 * For a non bridge resource granularity and alignment are the same.
 	 * For a bridge resource align is the largest needed alignment below
-	 * the bridge.  While the granularity is simply how many low bits of the
-	 * address cannot be set.
+	 * the bridge. While the granularity is simply how many low bits of
+	 * the address cannot be set.
 	 */
 
-	/* Get the end (rounded up) */
+	/* Get the end (rounded up). */
 	end = base + align_up(resource->size, resource->gran) - 1;
 
 	return end;
@@ -498,14 +512,14 @@
 {
 	static char buffer[RESOURCE_TYPE_MAX];
 	sprintf(buffer, "%s%s%s%s",
-		((resource->flags & IORESOURCE_READONLY)? "ro": ""),
-		((resource->flags & IORESOURCE_PREFETCH)? "pref":""),
-		((resource->flags == 0)? "unused":
-	 	(resource->flags & IORESOURCE_IO)? "io":
-		(resource->flags & IORESOURCE_DRQ)? "drq":
-		(resource->flags & IORESOURCE_IRQ)? "irq":
-		(resource->flags & IORESOURCE_MEM)? "mem":"??????"),
-		((resource->flags & IORESOURCE_PCI64)?"64":""));
+		((resource->flags & IORESOURCE_READONLY) ? "ro" : ""),
+		((resource->flags & IORESOURCE_PREFETCH) ? "pref" : ""),
+		((resource->flags == 0) ? "unused" :
+		(resource->flags & IORESOURCE_IO) ? "io" :
+		(resource->flags & IORESOURCE_DRQ) ? "drq" :
+		(resource->flags & IORESOURCE_IRQ) ? "irq" :
+		(resource->flags & IORESOURCE_MEM) ? "mem" : "??????"),
+		((resource->flags & IORESOURCE_PCI64) ? "64" : ""));
 	return buffer;
 }
 
@@ -519,52 +533,58 @@
 void report_resource_stored(device_t dev, struct resource *resource,
 			    const char *comment)
 {
-	if (resource->flags & IORESOURCE_STORED) {
-		char buf[10];
-		unsigned long long base, end;
-		base = resource->base;
-		end = resource_end(resource);
-		buf[0] = '\0';
-		if (resource->flags & IORESOURCE_PCI_BRIDGE) {
+	char buf[10];
+	unsigned long long base, end;
+
+	if (!(resource->flags & IORESOURCE_STORED))
+		return;
+
+	base = resource->base;
+	end = resource_end(resource);
+	buf[0] = '\0';
+
+	if (resource->flags & IORESOURCE_PCI_BRIDGE) {
 #if CONFIG_PCI_BUS_SEGN_BITS
-			sprintf(buf, "bus %04x:%02x ", dev->bus->secondary>>8, dev->link_list->secondary & 0xff);
+		sprintf(buf, "bus %04x:%02x ", dev->bus->secondary >> 8,
+			dev->link_list->secondary & 0xff);
 #else
-			sprintf(buf, "bus %02x ", dev->link_list->secondary);
+		sprintf(buf, "bus %02x ", dev->link_list->secondary);
 #endif
-		}
-		printk(BIOS_DEBUG,
-			"%s %02lx <- [0x%010Lx - 0x%010Lx] size 0x%08Lx gran 0x%02x %s%s%s\n",
-			dev_path(dev),
-			resource->index,
-			base, end,
-			resource->size, resource->gran,
-			buf,
-			resource_type(resource),
-			comment);
 	}
+	printk(BIOS_DEBUG, "%s %02lx <- [0x%010Lx - 0x%010Lx] size 0x%08Lx "
+	       "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index,
+		base, end, resource->size, resource->gran, buf,
+		resource_type(resource), comment);
 }
 
-void search_bus_resources(struct bus *bus,
-	unsigned long type_mask, unsigned long type,
-	resource_search_t search, void *gp)
+void search_bus_resources(struct bus *bus, unsigned long type_mask,
+			  unsigned long type, resource_search_t search,
+			  void *gp)
 {
 	struct device *curdev;
+
 	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
 		struct resource *res;
-		/* Ignore disabled devices */
-		if (!curdev->enabled) continue;
+
+		/* Ignore disabled devices. */
+		if (!curdev->enabled)
+			continue;
+
 		for (res = curdev->resource_list; res; res = res->next) {
-			/* If it isn't the right kind of resource ignore it */
-			if ((res->flags & type_mask) != type) {
+			/* If it isn't the right kind of resource ignore it. */
+			if ((res->flags & type_mask) != type)
 				continue;
-			}
-			/* If it is a subtractive resource recurse */
+
+			/* If it is a subtractive resource recurse. */
 			if (res->flags & IORESOURCE_SUBTRACTIVE) {
 				struct bus * subbus;
-				for (subbus = curdev->link_list; subbus; subbus = subbus->next)
-					if (subbus->link_num == IOINDEX_SUBTRACTIVE_LINK(res->index))
+				for (subbus = curdev->link_list; subbus;
+				     subbus = subbus->next)
+					if (subbus->link_num
+					== IOINDEX_SUBTRACTIVE_LINK(res->index))
 						break;
-				search_bus_resources(subbus, type_mask, type, search, gp);
+				search_bus_resources(subbus, type_mask, type,
+						     search, gp);
 				continue;
 			}
 			search(gp, curdev, res);
@@ -572,24 +592,27 @@
 	}
 }
 
-void search_global_resources(
-	unsigned long type_mask, unsigned long type,
-	resource_search_t search, void *gp)
+void search_global_resources(unsigned long type_mask, unsigned long type,
+			     resource_search_t search, void *gp)
 {
 	struct device *curdev;
+
 	for (curdev = all_devices; curdev; curdev = curdev->next) {
 		struct resource *res;
-		/* Ignore disabled devices */
-		if (!curdev->enabled) continue;
+
+		/* Ignore disabled devices. */
+		if (!curdev->enabled)
+			continue;
+
 		for (res = curdev->resource_list; res; res = res->next) {
-			/* If it isn't the right kind of resource ignore it */
-			if ((res->flags & type_mask) != type) {
+			/* If it isn't the right kind of resource ignore it. */
+			if ((res->flags & type_mask) != type)
 				continue;
-			}
-			/* If it is a subtractive resource ignore it */
-			if (res->flags & IORESOURCE_SUBTRACTIVE) {
+
+			/* If it is a subtractive resource ignore it. */
+			if (res->flags & IORESOURCE_SUBTRACTIVE)
 				continue;
-			}
+
 			search(gp, curdev, res);
 		}
 	}
@@ -597,14 +620,13 @@
 
 void dev_set_enabled(device_t dev, int enable)
 {
-	if (dev->enabled == enable) {
+	if (dev->enabled == enable)
 		return;
-	}
+
 	dev->enabled = enable;
 	if (dev->ops && dev->ops->enable) {
 		dev->ops->enable(dev);
-	}
-	else if (dev->chip_ops && dev->chip_ops->enable_dev) {
+	} else if (dev->chip_ops && dev->chip_ops->enable_dev) {
 		dev->chip_ops->enable_dev(dev);
 	}
 }
@@ -612,11 +634,11 @@
 void disable_children(struct bus *bus)
 {
 	device_t child;
+
 	for (child = bus->children; child; child = child->sibling) {
 		struct bus *link;
-		for (link = child->link_list; link; link = link->next) {
+		for (link = child->link_list; link; link = link->next)
 			disable_children(link);
-		}
 		dev_set_enabled(child, 0);
 	}
 }
@@ -640,12 +662,11 @@
  	do_printk(BIOS_DEBUG, "\n");
 
 	for (res = root->resource_list; res; res = res->next) {
-		do_printk(debug_level,
-			  "%s%s resource base %llx size %llx align %d gran %d limit %llx flags %lx index %lx\n",
-			  indent, dev_path(root), res->base,
-			  res->size, res->align,
-			  res->gran, res->limit,
-			  res->flags, res->index);
+		do_printk(debug_level, "%s%s resource base %llx size %llx "
+			  "align %d gran %d limit %llx flags %lx index %lx\n",
+			  indent, dev_path(root), res->base, res->size,
+			  res->align, res->gran, res->limit, res->flags,
+			  res->index);
 	}
 
 	for (link = root->link_list; link; link = link->next) {
@@ -654,8 +675,7 @@
 	}
 }
 
-void print_resource_tree(struct device * root, int debug_level,
-			 const char *msg)
+void print_resource_tree(struct device *root, int debug_level, const char *msg)
 {
 	/* Bail if root is null. */
 	if (!root) {
@@ -665,8 +685,9 @@
 
 	/* Bail if not printing to screen. */
 	if (!do_printk(debug_level, "Show resources in subtree (%s)...%s\n",
-		    dev_path(root), msg))
+		       dev_path(root), msg))
 		return;
+
 	resource_tree(root, debug_level, 0);
 }
 
@@ -680,8 +701,10 @@
 	for (i = 0; i < depth; i++)
 		depth_str[i] = ' ';
 	depth_str[i] = '\0';
+
 	do_printk(debug_level, "%s%s: enabled %d\n",
 		  depth_str, dev_path(dev), dev->enabled);
+
 	for (link = dev->link_list; link; link = link->next) {
 		for (sibling = link->children; sibling;
 		     sibling = sibling->sibling)
@@ -701,7 +724,7 @@
 {
 	/* Bail if not printing to screen. */
 	if (!do_printk(debug_level, "Show all devs in subtree %s...%s\n",
-		    dev_path(root), msg))
+		       dev_path(root), msg))
 		return;
 	do_printk(debug_level, "%s\n", msg);
 	show_devs_tree(root, debug_level, 0, -1);
@@ -728,6 +751,7 @@
 	base = resource->base;
 	end = resource_end(resource);
 	buf[0] = '\0';
+
 /*
 	if (resource->flags & IORESOURCE_BRIDGE) {
 #if CONFIG_PCI_BUS_SEGN_BITS
@@ -738,19 +762,18 @@
 #endif
 	}
 */
-	do_printk(debug_level, "%s %02lx <- [0x%010llx - 0x%010llx] "
-		  "size 0x%08Lx gran 0x%02x %s%s%s\n",
-		  dev_path(dev), resource->index, base, end,
-		  resource->size, resource->gran, buf,
-		  resource_type(resource), comment);
 
+	do_printk(debug_level, "%s %02lx <- [0x%010llx - 0x%010llx] "
+		  "size 0x%08Lx gran 0x%02x %s%s%s\n", dev_path(dev),
+		  resource->index, base, end, resource->size, resource->gran,
+		  buf, resource_type(resource), comment);
 }
 
 void show_all_devs_resources(int debug_level, const char* msg)
 {
 	struct device *dev;
 
-	if(!do_printk(debug_level, "Show all devs with resources...%s\n", msg))
+	if (!do_printk(debug_level, "Show all devs with resources...%s\n", msg))
 		return;
 
 	for (dev = all_devices; dev; dev = dev->next) {

Modified: trunk/src/devices/hypertransport.c
==============================================================================
--- trunk/src/devices/hypertransport.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/hypertransport.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -44,35 +44,38 @@
 static device_t ht_scan_get_devs(device_t *old_devices)
 {
 	device_t first, last;
+
 	first = *old_devices;
 	last = first;
-	/* Extract the chain of devices to (first through last)
-	 * for the next hypertransport device.
+
+	/*
+	 * Extract the chain of devices to (first through last) for the next
+	 * hypertransport device.
 	 */
-	while(last && last->sibling &&
-		(last->sibling->path.type == DEVICE_PATH_PCI) &&
-		(last->sibling->path.pci.devfn > last->path.pci.devfn))
+	while (last && last->sibling &&
+	       (last->sibling->path.type == DEVICE_PATH_PCI) &&
+	       (last->sibling->path.pci.devfn > last->path.pci.devfn))
 	{
 		last = last->sibling;
 	}
+
 	if (first) {
 		device_t child;
-		/* Unlink the chain from the list of old devices */
+
+		/* Unlink the chain from the list of old devices. */
 		*old_devices = last->sibling;
 		last->sibling = 0;
 
-		/* Now add the device to the list of devices on the bus.
-		 */
-		/* Find the last child of our parent */
-		for(child = first->bus->children; child && child->sibling; ) {
+		/* Now add the device to the list of devices on the bus. */
+		/* Find the last child of our parent. */
+		for (child = first->bus->children; child && child->sibling; )
 			child = child->sibling;
-		}
+
 		/* Place the chain on the list of children of their parent. */
-		if (child) {
+		if (child)
 			child->sibling = first;
-		} else {
+		else
 			first->bus->children = first;
-		}
 	}
 	return first;
 }
@@ -80,35 +83,39 @@
 #if OPT_HT_LINK == 1
 static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
 {
-	/* Handle bugs in valid hypertransport frequency reporting */
+	/* Handle bugs in valid hypertransport frequency reporting. */
 	unsigned freq_cap;
 
 	freq_cap = pci_read_config16(dev, pos);
-	freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
+	freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies. */
 
-	/* AMD 8131 Errata 48 */
+	/* AMD 8131 Errata 48. */
 	if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
-		(dev->device == PCI_DEVICE_ID_AMD_8131_PCIX)) {
+	    (dev->device == PCI_DEVICE_ID_AMD_8131_PCIX)) {
 		freq_cap &= ~(1 << HT_FREQ_800Mhz);
 	}
-	/* AMD 8151 Errata 23 */
+
+	/* AMD 8151 Errata 23. */
 	if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
-		(dev->device == PCI_DEVICE_ID_AMD_8151_SYSCTRL)) {
+	    (dev->device == PCI_DEVICE_ID_AMD_8151_SYSCTRL)) {
 		freq_cap &= ~(1 << HT_FREQ_800Mhz);
 	}
-	/* AMD K8 Unsupported 1Ghz? */
+
+	/* AMD K8 unsupported 1GHz? */
 	if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
 #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
-	#if CONFIG_K8_REV_F_SUPPORT == 0
-		if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT
+
+#if CONFIG_K8_REV_F_SUPPORT == 0
+		/* Only e0 later suupport 1GHz HT. */
+		if (is_cpu_pre_e0())
 			freq_cap &= ~(1 << HT_FREQ_1000Mhz);
-		}
-	#endif
+#endif
+
 #else
 		freq_cap &= ~(1 << HT_FREQ_1000Mhz);
 #endif
-
 	}
+
 	return freq_cap;
 }
 #endif
@@ -122,11 +129,11 @@
 static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
 {
 #if OPT_HT_LINK == 1
-	static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
-	static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
-	unsigned present_width_cap,    upstream_width_cap;
-	unsigned present_freq_cap,     upstream_freq_cap;
-	unsigned ln_present_width_in,  ln_upstream_width_in;
+	static const u8 link_width_to_pow2[] = { 3, 4, 0, 5, 1, 2, 0, 0 };
+	static const u8 pow2_to_link_width[] = { 7, 4, 5, 0, 1, 3 };
+	unsigned present_width_cap, upstream_width_cap;
+	unsigned present_freq_cap, upstream_freq_cap;
+	unsigned ln_present_width_in, ln_upstream_width_in;
 	unsigned ln_present_width_out, ln_upstream_width_out;
 	unsigned freq, old_freq;
 	unsigned present_width, upstream_width, old_width;
@@ -135,54 +142,60 @@
 	int reset_needed;
 	int linkb_to_host;
 
-	/* Set the hypertransport link width and frequency */
+	/* Set the hypertransport link width and frequency. */
 	reset_needed = 0;
-	/* See which side of the device our previous write to
-	 * set the unitid came from.
+	/*
+	 * See which side of the device our previous write to set the unitid
+	 * came from.
 	 */
 	cur->dev = dev;
 	cur->pos = pos;
-	linkb_to_host = (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
+	linkb_to_host =
+	  (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
+
 	if (!linkb_to_host) {
 		cur->ctrl_off     = PCI_HT_CAP_SLAVE_CTRL0;
 		cur->config_off   = PCI_HT_CAP_SLAVE_WIDTH0;
 		cur->freq_off     = PCI_HT_CAP_SLAVE_FREQ0;
 		cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
-	}
-	else {
+	} else {
 		cur->ctrl_off     = PCI_HT_CAP_SLAVE_CTRL1;
 		cur->config_off   = PCI_HT_CAP_SLAVE_WIDTH1;
 		cur->freq_off     = PCI_HT_CAP_SLAVE_FREQ1;
 		cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
 	}
+
 #if OPT_HT_LINK == 1
-	/* Read the capabilities */
-	present_freq_cap   = ht_read_freq_cap(cur->dev, cur->pos + cur->freq_cap_off);
-	upstream_freq_cap  = ht_read_freq_cap(prev->dev, prev->pos + prev->freq_cap_off);
-	present_width_cap  = pci_read_config8(cur->dev, cur->pos + cur->config_off);
-	upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off);
+	/* Read the capabilities. */
+	present_freq_cap =
+		ht_read_freq_cap(cur->dev, cur->pos + cur->freq_cap_off);
+	upstream_freq_cap =
+		ht_read_freq_cap(prev->dev, prev->pos + prev->freq_cap_off);
+	present_width_cap =
+		pci_read_config8(cur->dev, cur->pos + cur->config_off);
+	upstream_width_cap =
+		pci_read_config8(prev->dev, prev->pos + prev->config_off);
 
-	/* Calculate the highest useable frequency */
+	/* Calculate the highest useable frequency. */
 	freq = log2(present_freq_cap & upstream_freq_cap);
 
-	/* Calculate the highest width */
+	/* Calculate the highest width. */
 	ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
 	ln_present_width_out = link_width_to_pow2[(present_width_cap >> 4) & 7];
-	if (ln_upstream_width_in > ln_present_width_out) {
+	if (ln_upstream_width_in > ln_present_width_out)
 		ln_upstream_width_in = ln_present_width_out;
-	}
 	upstream_width = pow2_to_link_width[ln_upstream_width_in];
 	present_width  = pow2_to_link_width[ln_upstream_width_in] << 4;
 
-	ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
-	ln_present_width_in   = link_width_to_pow2[present_width_cap & 7];
-	if (ln_upstream_width_out > ln_present_width_in) {
+	ln_upstream_width_out =
+		link_width_to_pow2[(upstream_width_cap >> 4) & 7];
+	ln_present_width_in = link_width_to_pow2[present_width_cap & 7];
+	if (ln_upstream_width_out > ln_present_width_in)
 		ln_upstream_width_out = ln_present_width_in;
-	}
 	upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
 	present_width  |= pow2_to_link_width[ln_upstream_width_out];
 
-	/* Set the current device */
+	/* Set the current device. */
 	old_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
 	old_freq &= 0x0f;
 	if (freq != old_freq) {
@@ -193,55 +206,68 @@
 		new_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
 		new_freq &= 0x0f;
 		if (new_freq != freq) {
-			printk(BIOS_ERR, "%s Hypertransport frequency would not set wanted: %x got: %x\n",
-				dev_path(dev), freq, new_freq);
+			printk(BIOS_ERR, "%s Hypertransport frequency would "
+			       "not set. Wanted: %x, got: %x\n",
+			       dev_path(dev), freq, new_freq);
 		}
 	}
 	old_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
 	if (present_width != old_width) {
 		unsigned new_width;
 		pci_write_config8(cur->dev, cur->pos + cur->config_off + 1,
-			present_width);
+				  present_width);
 		reset_needed = 1;
-		printk(BIOS_SPEW, "HyperT widthP old %x new %x\n",old_width, present_width);
-		new_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
+		printk(BIOS_SPEW, "HyperT widthP old %x new %x\n",
+		       old_width, present_width);
+		new_width = pci_read_config8(cur->dev,
+					     cur->pos + cur->config_off + 1);
 		if (new_width != present_width) {
-			printk(BIOS_ERR, "%s Hypertransport width would not set wanted: %x got: %x\n",
-				dev_path(dev), present_width, new_width);
+			printk(BIOS_ERR, "%s Hypertransport width would not "
+			       "set. Wanted: %x, got: %x\n",
+			       dev_path(dev), present_width, new_width);
 		}
 	}
 
-	/* Set the upstream device */
+	/* Set the upstream device. */
 	old_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
 	old_freq &= 0x0f;
 	if (freq != old_freq) {
 		unsigned new_freq;
 		pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq);
 		reset_needed = 1;
-		printk(BIOS_SPEW, "HyperT freqU old %x new %x\n", old_freq, freq);
-		new_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
+		printk(BIOS_SPEW, "HyperT freqU old %x new %x\n",
+		       old_freq, freq);
+		new_freq =
+		  pci_read_config8(prev->dev, prev->pos + prev->freq_off);
 		new_freq &= 0x0f;
 		if (new_freq != freq) {
-			printk(BIOS_ERR, "%s Hypertransport frequency would not set wanted: %x got: %x\n",
-				dev_path(prev->dev), freq, new_freq);
+			printk(BIOS_ERR, "%s Hypertransport frequency would "
+			       "not set. Wanted: %x, got: %x\n",
+			       dev_path(prev->dev), freq, new_freq);
 		}
 	}
-	old_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
+	old_width =
+		pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
 	if (upstream_width != old_width) {
 		unsigned new_width;
-		pci_write_config8(prev->dev, prev->pos + prev->config_off + 1, upstream_width);
+		pci_write_config8(prev->dev, prev->pos + prev->config_off + 1,
+				  upstream_width);
 		reset_needed = 1;
-		printk(BIOS_SPEW, "HyperT widthU old %x new %x\n", old_width, upstream_width);
-		new_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
+		printk(BIOS_SPEW, "HyperT widthU old %x new %x\n", old_width,
+		       upstream_width);
+		new_width = pci_read_config8(prev->dev,
+					     prev->pos + prev->config_off + 1);
 		if (new_width != upstream_width) {
-			printk(BIOS_ERR, "%s Hypertransport width would not set wanted: %x got: %x\n",
-				dev_path(prev->dev), upstream_width, new_width);
+			printk(BIOS_ERR, "%s Hypertransport width would not "
+			       "set. Wanted: %x, got: %x\n",
+			       dev_path(prev->dev), upstream_width, new_width);
 		}
 	}
 #endif
 
-	/* Remember the current link as the previous link,
-	 * But look at the other offsets.
+	/*
+	 * Remember the current link as the previous link, but look at the
+	 * other offsets.
 	 */
 	prev->dev = cur->dev;
 	prev->pos = cur->pos;
@@ -263,29 +289,32 @@
 static unsigned ht_lookup_slave_capability(struct device *dev)
 {
 	unsigned pos;
+
 	pos = 0;
 	do {
 		pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos);
 		if (pos) {
-			unsigned flags;
+			u16 flags;
 			flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
 			printk(BIOS_SPEW, "flags: 0x%04x\n", flags);
 			if ((flags >> 13) == 0) {
-				/* Entry is a Slave secondary, success... */
+				/* Entry is a slave secondary, success... */
 				break;
 			}
 		}
-	} while(pos);
+	} while (pos);
+
 	return pos;
 }
 
-static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_unitid)
+static void ht_collapse_early_enumeration(struct bus *bus,
+					  unsigned offset_unitid)
 {
 	unsigned int devfn;
 	struct ht_link prev;
-	unsigned ctrl;
+	u16 ctrl;
 
-	/* Initialize the hypertransport enumeration state */
+	/* Initialize the hypertransport enumeration state. */
 	prev.dev = bus->dev;
 	prev.pos = bus->cap;
 	prev.ctrl_off     = PCI_HT_CAP_HOST_CTRL;
@@ -293,303 +322,328 @@
 	prev.freq_off     = PCI_HT_CAP_HOST_FREQ;
 	prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
 
-	/* Wait until the link initialization is complete */
+	/* Wait until the link initialization is complete. */
 	do {
 		ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
-		/* Is this the end of the hypertransport chain */
-		if (ctrl & (1 << 6)) {
+
+		/* Is this the end of the hypertransport chain? */
+		if (ctrl & (1 << 6))
 			return;
-		}
+
 		/* Has the link failed? */
 		if (ctrl & (1 << 4)) {
 			/*
-			 * Either the link has failed, or we have
-			 * a CRC error.
-			 * Sometimes this can happen due to link
-			 * retrain, so lets knock it down and see
-			 * if its transient
+			 * Either the link has failed, or we have a CRC error.
+			 * Sometimes this can happen due to link retrain, so
+			 * lets knock it down and see if its transient.
 			 */
-			ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
-			pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
-			ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
+			ctrl |= ((1 << 4) | (1 << 8)); /* Link fail + CRC */
+			pci_write_config16(prev.dev, prev.pos + prev.ctrl_off,
+					   ctrl);
+			ctrl = pci_read_config16(prev.dev,
+						 prev.pos + prev.ctrl_off);
 			if (ctrl & ((1 << 4) | (1 << 8))) {
-				printk(BIOS_ALERT, "Detected error on Hypertransport Link\n");
+				printk(BIOS_ALERT, "Detected error on "
+				       "Hypertransport link\n");
 				return;
 			}
 		}
-	} while((ctrl & (1 << 5)) == 0);
+	} while ((ctrl & (1 << 5)) == 0);
 
-	        //actually, only for one HT device HT chain, and unitid is 0
+	/* Actually, only for one HT device HT chain, and unitid is 0. */
 #if CONFIG_HT_CHAIN_UNITID_BASE == 0
-        if(offset_unitid) {
-                return;
-        }
-#endif
-
-        /* Check if is already collapsed */
-        if((!offset_unitid)|| (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) {
-                struct device dummy;
-                uint32_t id;
-                dummy.bus              = bus;
-                dummy.path.type        = DEVICE_PATH_PCI;
-                dummy.path.pci.devfn = PCI_DEVFN(0, 0);
-                id = pci_read_config32(&dummy, PCI_VENDOR_ID);
-                if ( ! ( (id == 0xffffffff) || (id == 0x00000000) ||
-                    (id == 0x0000ffff) || (id == 0xffff0000) ) ) {
-                             return;
-                }
-        }
+	if (offset_unitid)
+		return;
+#endif
 
-	/* Spin through the devices and collapse any early
-	 * hypertransport enumeration.
-	 */
-	for(devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) {
+	/* Check if is already collapsed. */
+	if ((!offset_unitid) || (offset_unitid
+	    && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0)
+	    && (CONFIG_HT_CHAIN_END_UNITID_BASE
+	    < CONFIG_HT_CHAIN_UNITID_BASE))))) {
+
+		struct device dummy;
+		u32 id;
+
+		dummy.bus = bus;
+		dummy.path.type = DEVICE_PATH_PCI;
+		dummy.path.pci.devfn = PCI_DEVFN(0, 0);
+
+		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
+		if (!((id == 0xffffffff) || (id == 0x00000000)
+		    || (id == 0x0000ffff) || (id == 0xffff0000))) {
+			return;
+		}
+	}
+
+	/* Spin through the devices and collapse any early HT enumeration. */
+	for (devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) {
 		struct device dummy;
-		uint32_t id;
+		u32 id;
 		unsigned pos, flags;
-		dummy.bus              = bus;
-		dummy.path.type        = DEVICE_PATH_PCI;
+
+		dummy.bus = bus;
+		dummy.path.type = DEVICE_PATH_PCI;
 		dummy.path.pci.devfn = devfn;
+
 		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
-		if (	(id == 0xffffffff) || (id == 0x00000000) ||
-			(id == 0x0000ffff) || (id == 0xffff0000)) {
+		if ((id == 0xffffffff) || (id == 0x00000000)
+		    || (id == 0x0000ffff) || (id == 0xffff0000)) {
 			continue;
 		}
+
 		dummy.vendor = id & 0xffff;
 		dummy.device = (id >> 16) & 0xffff;
 		dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
+
 		pos = ht_lookup_slave_capability(&dummy);
-		if (!pos){
+		if (!pos)
 			continue;
-		}
 
-		/* Clear the unitid */
+		/* Clear the unitid. */
 		flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
 		flags &= ~0x1f;
 		pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
 		printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n",
-			dev_path(&dummy), dummy.vendor, dummy.device);
+		       dev_path(&dummy), dummy.vendor, dummy.device);
 	}
 }
 
-unsigned int hypertransport_scan_chain(struct bus *bus,
-	unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid)
+unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn,
+				       unsigned max_devfn, unsigned int max,
+				       unsigned *ht_unitid_base,
+				       unsigned offset_unitid)
 {
-	//even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
-	unsigned next_unitid, last_unitid;
-	device_t old_devices, dev, func;
-	unsigned min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1;
+	/*
+	 * Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this
+	 * function, because of end_of_chain check. Also, we need it to
+	 * optimize link.
+	 */
+	unsigned int next_unitid, last_unitid, min_unitid, max_unitid;
+	device_t old_devices, dev, func, last_func = 0;
 	struct ht_link prev;
-	device_t last_func = 0;
 	int ht_dev_num = 0;
-	unsigned max_unitid;
+
+	min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1;
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
-        //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
-        unsigned real_last_unitid=0;
-        uint8_t real_last_pos=0;
-	device_t real_last_dev=NULL;
-	unsigned end_used = 0;
+        /*
+	 * Let's record the device of last HT device, so we can set the unitid
+	 * to CONFIG_HT_CHAIN_END_UNITID_BASE.
+	 */
+	unsigned int real_last_unitid = 0, end_used = 0;
+	u8 real_last_pos = 0;
+	device_t real_last_dev = NULL;
 #endif
 
-	/* Restore the hypertransport chain to it's unitialized state */
+	/* Restore the hypertransport chain to it's unitialized state. */
 	ht_collapse_early_enumeration(bus, offset_unitid);
 
-	/* See which static device nodes I have */
+	/* See which static device nodes I have. */
 	old_devices = bus->children;
 	bus->children = 0;
 
-	/* Initialize the hypertransport enumeration state */
+	/* Initialize the hypertransport enumeration state. */
 	prev.dev = bus->dev;
 	prev.pos = bus->cap;
+
 	prev.ctrl_off     = PCI_HT_CAP_HOST_CTRL;
 	prev.config_off   = PCI_HT_CAP_HOST_WIDTH;
 	prev.freq_off     = PCI_HT_CAP_HOST_FREQ;
 	prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
 
-	/* If present assign unitid to a hypertransport chain */
+	/* If present, assign unitid to a hypertransport chain. */
 	last_unitid = min_unitid -1;
 	max_unitid = next_unitid = min_unitid;
 	do {
-		uint8_t pos;
-		uint16_t flags;
-		unsigned count, static_count;
-		unsigned ctrl;
+		u8 pos;
+		u16 flags, ctrl;
+		unsigned int count, static_count;
 
 		last_unitid = next_unitid;
 
-		/* Wait until the link initialization is complete */
+		/* Wait until the link initialization is complete. */
 		do {
-			ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
+			ctrl = pci_read_config16(prev.dev,
+						 prev.pos + prev.ctrl_off);
 
+			/* End of chain? */
 			if (ctrl & (1 << 6))
-				goto end_of_chain;	// End of chain
+				goto end_of_chain;
 
 			if (ctrl & ((1 << 4) | (1 << 8))) {
 				/*
-				 * Either the link has failed, or we have
-				 * a CRC error.
-				 * Sometimes this can happen due to link
-				 * retrain, so lets knock it down and see
-				 * if its transient
+				 * Either the link has failed, or we have a CRC
+				 * error. Sometimes this can happen due to link
+				 * retrain, so lets knock it down and see if
+				 * it's transient.
 				 */
-				ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
-				pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
-				ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
+				ctrl |= ((1 << 4) | (1 <<8)); // Link fail + CRC
+				pci_write_config16(prev.dev,
+					prev.pos + prev.ctrl_off, ctrl);
+				ctrl = pci_read_config16(prev.dev,
+						prev.pos + prev.ctrl_off);
 				if (ctrl & ((1 << 4) | (1 << 8))) {
-					printk(BIOS_ALERT, "Detected error on Hypertransport Link\n");
+					printk(BIOS_ALERT, "Detected error on "
+					       "hypertransport link\n");
 					goto end_of_chain;
 				}
 			}
-		} while((ctrl & (1 << 5)) == 0);
+		} while ((ctrl & (1 << 5)) == 0);
 
 
-		/* Get and setup the device_structure */
+		/* Get and setup the device_structure. */
 		dev = ht_scan_get_devs(&old_devices);
 
-		/* See if a device is present and setup the
-		 * device structure.
-		 */
+		/* See if a device is present and setup the device structure. */
 		dev = pci_probe_dev(dev, bus, 0);
-		if (!dev || !dev->enabled) {
+		if (!dev || !dev->enabled)
 			break;
-		}
 
-		/* Find the hypertransport link capability */
+		/* Find the hypertransport link capability. */
 		pos = ht_lookup_slave_capability(dev);
 		if (pos == 0) {
-			printk(BIOS_ERR, "%s Hypertransport link capability not found",
-				dev_path(dev));
+			printk(BIOS_ERR, "%s Hypertransport link capability "
+			       "not found", dev_path(dev));
 			break;
 		}
 
-		/* Update the Unitid of the current device */
+		/* Update the unitid of the current device. */
 		flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
 
-		/* If the devices has a unitid set and is at devfn 0 we are done.
-		 * This can happen with shadow hypertransport devices,
-		 * or if we have reached the bottom of a
-		 * hypertransport device chain.
+		/*
+		 * If the devices has a unitid set and is at devfn 0 we are
+		 * done. This can happen with shadow hypertransport devices,
+		 * or if we have reached the bottom of a HT device chain.
 		 */
-		if (flags & 0x1f) {
+		if (flags & 0x1f)
 			break;
-		}
-		flags &= ~0x1f; /* mask out base Unit ID */
 
-		count = (flags >> 5) & 0x1f; /* get unit count */
+		flags &= ~0x1f; /* Mask out base Unit ID. */
+
+		count = (flags >> 5) & 0x1f; /* Het unit count. */
+
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
-		if(offset_unitid) {
-			if(next_unitid > (max_devfn>>3)) { // max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7
-				if(!end_used) {
-			                next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
+		if (offset_unitid) {
+			/* max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7. */
+			if (next_unitid > (max_devfn >> 3)) {
+				if (!end_used) {
+			                next_unitid =
+					  CONFIG_HT_CHAIN_END_UNITID_BASE;
 					end_used = 1;
 				} else {
 					goto end_of_chain;
 				}
 			}
-
 		}
 #endif
 
-                flags |= next_unitid & 0x1f;
-                pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
+		flags |= next_unitid & 0x1f;
+		pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
 
-		/* Update the Unitd id in the device structure */
+		/* Update the unitid in the device structure. */
 		static_count = 1;
-		for(func = dev; func; func = func->sibling) {
+		for (func = dev; func; func = func->sibling) {
 			func->path.pci.devfn += (next_unitid << 3);
 			static_count = (func->path.pci.devfn >> 3)
-				- (dev->path.pci.devfn >> 3) + 1;
+				        - (dev->path.pci.devfn >> 3) + 1;
 			last_func = func;
 		}
-		/* Compute the number of unitids consumed */
+
+		/* Compute the number of unitids consumed. */
 		printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n",
-			dev_path(dev), count, static_count);
-		if (count < static_count) {
+		       dev_path(dev), count, static_count);
+		if (count < static_count)
 			count = static_count;
-		}
 
-		/* Update the Unitid of the next device */
+		/* Update the unitid of the next device. */
 		ht_unitid_base[ht_dev_num] = next_unitid;
 		ht_dev_num++;
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 		if (offset_unitid) {
-        	        real_last_pos = pos;
+			real_last_pos = pos;
 			real_last_unitid = next_unitid;
 			real_last_dev = dev;
 		}
 #endif
-		next_unitid +=  count;
-		if (next_unitid > max_unitid) {
+		next_unitid += count;
+		if (next_unitid > max_unitid)
 			max_unitid = next_unitid;
-		}
 
-		/* Setup the hypetransport link */
+		/* Setup the hypetransport link. */
 		bus->reset_needed |= ht_setup_link(&prev, dev, pos);
 
 		printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n",
-			dev_path(dev),
-			dev->vendor, dev->device,
-			(dev->enabled? "enabled": "disabled"), next_unitid);
+		       dev_path(dev), dev->vendor, dev->device,
+		       (dev->enabled? "enabled" : "disabled"), next_unitid);
 
 	} while (last_unitid != next_unitid);
- end_of_chain:
+
+end_of_chain:
+
 #if OPT_HT_LINK == 1
-	if(bus->reset_needed) {
+	if (bus->reset_needed)
 		printk(BIOS_INFO, "HyperT reset needed\n");
-	}
-	else {
+	else
 		printk(BIOS_DEBUG, "HyperT reset not needed\n");
-	}
 #endif
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
-        if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE)  && !end_used) {
-                uint16_t flags;
-                flags = pci_read_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS);
-                flags &= ~0x1f;
-                flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
-                pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS, flags);
-
-                for(func = real_last_dev; func; func = func->sibling) {
-                        func->path.pci.devfn -= ((real_last_unitid - CONFIG_HT_CHAIN_END_UNITID_BASE) << 3);
+	if (offset_unitid && (ht_dev_num > 1)
+	    && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE)
+	    && !end_used) {
+		u16 flags;
+		flags = pci_read_config16(real_last_dev,
+					  real_last_pos + PCI_CAP_FLAGS);
+		flags &= ~0x1f;
+		flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
+		pci_write_config16(real_last_dev,
+				   real_last_pos + PCI_CAP_FLAGS, flags);
+
+		for (func = real_last_dev; func; func = func->sibling) {
+			func->path.pci.devfn -= ((real_last_unitid
+				- CONFIG_HT_CHAIN_END_UNITID_BASE) << 3);
 			last_func = func;
-                }
+		}
 
-		ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; // update last one
+		/* Update last one. */
+		ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE;
 
 		printk(BIOS_DEBUG, " unitid: %04x --> %04x\n",
-				real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE);
-
-        }
+		       real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE);
+	}
 #endif
 	next_unitid = max_unitid;
 
-	if (next_unitid > 0x20) {
+	if (next_unitid > 0x20)
 		next_unitid = 0x20;
-	}
-	if( (bus->secondary == 0) && (next_unitid > 0x18)) {
-		next_unitid = 0x18; /* avoid K8 on bus 0 */
-	}
 
-	/* Die if any leftover Static devices are are found.
-	 * There's probably a problem in the Config.lb.
+	if ((bus->secondary == 0) && (next_unitid > 0x18))
+		next_unitid = 0x18; /* Avoid K8 on bus 0. */
+
+	/*
+	 * Die if any leftover static devices are are found. There's probably
+	 * a problem in devicetree.cb.
 	 */
-	if(old_devices) {
+	if (old_devices) {
 		device_t left;
-		for(left = old_devices; left; left = left->sibling) {
+		for (left = old_devices; left; left = left->sibling)
 			printk(BIOS_DEBUG, "%s\n", dev_path(left));
-		}
-		printk(BIOS_ERR, "HT: Left over static devices.  Check your Config.lb\n");
-		if(last_func  && !last_func->sibling) // put back the left over static device, and let pci_scan_bus disable it
+
+		printk(BIOS_ERR, "HT: Leftover static devices. "
+		       "Check your devicetree.cb\n");
+
+		/*
+		 * Put back the leftover static device, and let pci_scan_bus()
+		 * disable it.
+		 */
+		if (last_func && !last_func->sibling)
 			last_func->sibling = old_devices;
 	}
 
-	/* Now that nothing is overlapping it is safe to scan the
-	 * children.
-	 */
-	max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max);
+	/* Now that nothing is overlapping it is safe to scan the children. */
+	max = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, max);
 	return max;
 }
 
@@ -608,11 +662,12 @@
  * @return The maximum bus number found, after scanning all subordinate busses.
  */
 static unsigned int hypertransport_scan_chain_x(struct bus *bus,
-        unsigned min_devfn, unsigned max_devfn, unsigned int max)
+	unsigned int min_devfn, unsigned int max_devfn, unsigned int max)
 {
-	unsigned ht_unitid_base[4];
-	unsigned offset_unitid = 1;
-	return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, ht_unitid_base, offset_unitid);
+	unsigned int ht_unitid_base[4];
+	unsigned int offset_unitid = 1;
+	return hypertransport_scan_chain(bus, min_devfn, max_devfn, max,
+					 ht_unitid_base, offset_unitid);
 }
 
 unsigned int ht_scan_bridge(struct device *dev, unsigned int max)
@@ -629,8 +684,8 @@
 	.read_resources   = pci_bus_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_bus_enable_resources,
-	.init		  = 0,
-	.scan_bus	  = ht_scan_bridge,
+	.init             = 0,
+	.scan_bus         = ht_scan_bridge,
 	.enable           = 0,
 	.reset_bus        = pci_bus_reset,
 	.ops_pci          = &ht_bus_ops_pci,

Modified: trunk/src/devices/pci_device.c
==============================================================================
--- trunk/src/devices/pci_device.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/pci_device.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -56,6 +56,7 @@
 u8 pci_moving_config8(struct device *dev, unsigned int reg)
 {
 	u8 value, ones, zeroes;
+
 	value = pci_read_config8(dev, reg);
 
 	pci_write_config8(dev, reg, 0xff);
@@ -69,9 +70,10 @@
 	return ones ^ zeroes;
 }
 
-u16 pci_moving_config16(struct device * dev, unsigned int reg)
+u16 pci_moving_config16(struct device *dev, unsigned int reg)
 {
 	u16 value, ones, zeroes;
+
 	value = pci_read_config16(dev, reg);
 
 	pci_write_config16(dev, reg, 0xffff);
@@ -85,9 +87,10 @@
 	return ones ^ zeroes;
 }
 
-u32 pci_moving_config32(struct device * dev, unsigned int reg)
+u32 pci_moving_config32(struct device *dev, unsigned int reg)
 {
 	u32 value, ones, zeroes;
+
 	value = pci_read_config32(dev, reg);
 
 	pci_write_config32(dev, reg, 0xffffffff);
@@ -114,13 +117,13 @@
 				  unsigned last)
 {
 	unsigned pos = 0;
-	unsigned status;
+	u16 status;
 	unsigned reps = 48;
 
 	status = pci_read_config16(dev, PCI_STATUS);
-	if (!(status & PCI_STATUS_CAP_LIST)) {
+	if (!(status & PCI_STATUS_CAP_LIST))
 		return 0;
-	}
+
 	switch (dev->hdr_type & 0x7f) {
 	case PCI_HEADER_TYPE_NORMAL:
 	case PCI_HEADER_TYPE_BRIDGE:
@@ -132,22 +135,24 @@
 	default:
 		return 0;
 	}
+
 	pos = pci_read_config8(dev, pos);
-	while (reps-- && (pos >= 0x40)) {	/* Loop through the linked list. */
+	while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
 		int this_cap;
+
 		pos &= ~3;
 		this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
-		printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n", this_cap,
-			    pos);
-		if (this_cap == 0xff) {
+		printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n",
+		       this_cap, pos);
+		if (this_cap == 0xff)
 			break;
-		}
-		if (!last && (this_cap == cap)) {
+
+		if (!last && (this_cap == cap))
 			return pos;
-		}
-		if (last == pos) {
+
+		if (last == pos)
 			last = 0;
-		}
+
 		pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
 	}
 	return 0;
@@ -199,6 +204,7 @@
 		moving |=
 		    ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
 	}
+
 	/* Find the resource constraints.
 	 * Start by finding the bits that move. From there:
 	 * - Size is the least significant bit of the bits that move.
@@ -217,20 +223,25 @@
 		resource->limit = limit = moving | (resource->size - 1);
 	}
 
-	/* Some broken hardware has read-only registers that do not
+	/*
+	 * Some broken hardware has read-only registers that do not
 	 * really size correctly.
-	 * Example: the Acer M7229 has BARs 1-4 normally read-only.
+	 *
+	 * Example: the Acer M7229 has BARs 1-4 normally read-only,
 	 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
-	 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
-	 * violation of the spec.
-	 * We catch this case and ignore it by observing which bits move,
-	 * This also catches the common case unimplemented registers
+	 * by writing 0xffffffff to it, it will read back as 0x1f1 -- which
+	 * is a violation of the spec.
+	 *
+	 * We catch this case and ignore it by observing which bits move.
+	 *
+	 * This also catches the common case of unimplemented registers
 	 * that always read back as 0.
 	 */
 	if (moving == 0) {
 		if (value != 0) {
-			printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n",
-			     dev_path(dev), index, value);
+			printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
+			       "read-only ignoring it\n",
+			       dev_path(dev), index, value);
 		}
 		resource->flags = 0;
 	} else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
@@ -243,9 +254,8 @@
 		/* A Memory mapped base address. */
 		attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
 		resource->flags |= IORESOURCE_MEM;
-		if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
+		if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH)
 			resource->flags |= IORESOURCE_PREFETCH;
-		}
 		attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
 		if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
 			/* 32bit limit. */
@@ -265,10 +275,10 @@
 			resource->flags = 0;
 		}
 	}
+
 	/* Don't let the limit exceed which bits can move. */
-	if (resource->limit > limit) {
+	if (resource->limit > limit)
 		resource->limit = limit;
-	}
 
 	return resource;
 }
@@ -315,8 +325,9 @@
 		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
 	} else {
 		if (value != 0) {
-			printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n",
-			     dev_path(dev), index, value);
+			printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
+			       "read-only ignoring it\n",
+			       dev_path(dev), index, value);
 		}
 		resource->flags = 0;
 	}
@@ -346,27 +357,29 @@
 static void pci_record_bridge_resource(struct device *dev, resource_t moving,
 				       unsigned index, unsigned long type)
 {
-	/* Initialize the constraints on the current bus. */
 	struct resource *resource;
+	unsigned long gran;
+	resource_t step;
+
 	resource = NULL;
-	if (moving) {
-		unsigned long gran;
-		resource_t step;
-		resource = new_resource(dev, index);
-		resource->size = 0;
-		gran = 0;
-		step = 1;
-		while ((moving & step) == 0) {
-			gran += 1;
-			step <<= 1;
-		}
-		resource->gran = gran;
-		resource->align = gran;
-		resource->limit = moving | (step - 1);
-		resource->flags = type | IORESOURCE_PCI_BRIDGE |
-				  IORESOURCE_BRIDGE;
-	}
-	return;
+
+	if (!moving)
+		return;
+
+	/* Initialize the constraints on the current bus. */
+	resource = new_resource(dev, index);
+	resource->size = 0;
+	gran = 0;
+	step = 1;
+	while ((moving & step) == 0) {
+		gran += 1;
+		step <<= 1;
+	}
+	resource->gran = gran;
+	resource->align = gran;
+	resource->limit = moving | (step - 1);
+	resource->flags = type | IORESOURCE_PCI_BRIDGE |
+			  IORESOURCE_BRIDGE;
 }
 
 static void pci_bridge_read_bases(struct device *dev)
@@ -452,26 +465,23 @@
 
 	/* Make certain the resource has actually been assigned a value. */
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
-			   dev_path(dev), resource->index,
-			   resource_type(resource), resource->size);
+		printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not "
+		       "assigned\n", dev_path(dev), resource->index,
+		       resource_type(resource), resource->size);
 		return;
 	}
 
 	/* If this resource is fixed don't worry about it. */
-	if (resource->flags & IORESOURCE_FIXED) {
+	if (resource->flags & IORESOURCE_FIXED)
 		return;
-	}
 
 	/* If I have already stored this resource don't worry about it. */
-	if (resource->flags & IORESOURCE_STORED) {
+	if (resource->flags & IORESOURCE_STORED)
 		return;
-	}
 
 	/* If the resource is subtractive don't worry about it. */
-	if (resource->flags & IORESOURCE_SUBTRACTIVE) {
+	if (resource->flags & IORESOURCE_SUBTRACTIVE)
 		return;
-	}
 
 	/* Only handle PCI memory and I/O resources for now. */
 	if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
@@ -479,16 +489,14 @@
 
 	/* Enable the resources in the command register. */
 	if (resource->size) {
-		if (resource->flags & IORESOURCE_MEM) {
+		if (resource->flags & IORESOURCE_MEM)
 			dev->command |= PCI_COMMAND_MEMORY;
-		}
-		if (resource->flags & IORESOURCE_IO) {
+		if (resource->flags & IORESOURCE_IO)
 			dev->command |= PCI_COMMAND_IO;
-		}
-		if (resource->flags & IORESOURCE_PCI_BRIDGE) {
+		if (resource->flags & IORESOURCE_PCI_BRIDGE)
 			dev->command |= PCI_COMMAND_MASTER;
-		}
 	}
+
 	/* Get the base address. */
 	base = resource->base;
 
@@ -498,8 +506,9 @@
 	/* Now store the resource. */
 	resource->flags |= IORESOURCE_STORED;
 
-	/* PCI Bridges have no enable bit.  They are disabled if the base of
-	 * the range is greater than the limit.  If the size is zero, disable
+	/*
+	 * PCI bridges have no enable bit. They are disabled if the base of
+	 * the range is greater than the limit. If the size is zero, disable
 	 * by setting the base = limit and end = limit - 2^gran.
 	 */
 	if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
@@ -510,18 +519,18 @@
 
 	if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
 		unsigned long base_lo, base_hi;
-		/* Some chipsets allow us to set/clear the I/O bit
-		 * (e.g. VIA 82c686a). So set it to be safe.
+
+		/*
+		 * Some chipsets allow us to set/clear the I/O bit
+		 * (e.g. VIA 82C686A). So set it to be safe.
 		 */
 		base_lo = base & 0xffffffff;
 		base_hi = (base >> 32) & 0xffffffff;
-		if (resource->flags & IORESOURCE_IO) {
+		if (resource->flags & IORESOURCE_IO)
 			base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
-		}
 		pci_write_config32(dev, resource->index, base_lo);
-		if (resource->flags & IORESOURCE_PCI64) {
+		if (resource->flags & IORESOURCE_PCI64)
 			pci_write_config32(dev, resource->index + 4, base_hi);
-		}
 	} else if (resource->index == PCI_IO_BASE) {
 		/* Set the I/O ranges. */
 		pci_write_config8(dev, PCI_IO_BASE, base >> 8);
@@ -542,10 +551,10 @@
 		/* Don't let me think I stored the resource. */
 		resource->flags &= ~IORESOURCE_STORED;
 		printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n",
-			   resource->index);
+		       resource->index);
 	}
+
 	report_resource_stored(dev, resource, "");
-	return;
 }
 
 void pci_dev_set_resources(struct device *dev)
@@ -554,28 +563,26 @@
 	struct bus *bus;
 	u8 line;
 
-	for (res = dev->resource_list; res; res = res->next) {
+	for (res = dev->resource_list; res; res = res->next)
 		pci_set_resource(dev, res);
-	}
+
 	for (bus = dev->link_list; bus; bus = bus->next) {
-		if (bus->children) {
+		if (bus->children)
 			assign_resources(bus);
-		}
 	}
 
 	/* Set a default latency timer. */
 	pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
 
 	/* Set a default secondary latency timer. */
-	if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
+	if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE)
 		pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
-	}
 
 	/* Zero the IRQ settings. */
 	line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
-	if (line) {
+	if (line)
 		pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
-	}
+
 	/* Set the cache line size, so far 64 bytes is good for everyone. */
 	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 }
@@ -585,22 +592,23 @@
 	const struct pci_operations *ops;
 	u16 command;
 
-	/* Set the subsystem vendor and device id for mainboard devices. */
+	/* Set the subsystem vendor and device ID for mainboard devices. */
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
-		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
-			     dev_path(dev),
-			     CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			     CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", dev_path(dev),
+		       CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+		       CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 		ops->set_subsystem(dev,
 				   CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
 				   CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 	}
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;
+
 	/* v3 has
 	 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR);	// Error check.
 	 */
+
 	printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
 	pci_write_config16(dev, PCI_COMMAND, command);
 }
@@ -609,14 +617,15 @@
 {
 	u16 ctrl;
 
-	/* Enable I/O in command register if there is VGA card
+	/*
+	 * Enable I/O in command register if there is VGA card
 	 * connected with (even it does not claim I/O resource).
 	 */
 	if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
 		dev->command |= PCI_COMMAND_IO;
 	ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 	ctrl |= dev->link_list->bridge_ctrl;
-	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR);	/* Error check. */
+	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
 	printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 
@@ -625,11 +634,13 @@
 
 void pci_bus_reset(struct bus *bus)
 {
-	unsigned ctl;
+	u16 ctl;
+
 	ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
 	ctl |= PCI_BRIDGE_CTL_BUS_RESET;
 	pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
 	mdelay(10);
+
 	ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 	pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
 	delay(1);
@@ -641,7 +652,7 @@
 			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
-/** default handler: only runs the relevant pci bios. */
+/** Default handler: only runs the relevant PCI BIOS. */
 void pci_dev_init(struct device *dev)
 {
 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
@@ -666,7 +677,7 @@
 	run_bios(dev, (unsigned long)ram);
 
 #if CONFIG_CONSOLE_VGA == 1
-	if ((dev->class>>8) == PCI_CLASS_DISPLAY_VGA)
+	if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
 		vga_console_init();
 #endif /* CONFIG_CONSOLE_VGA */
 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
@@ -678,13 +689,13 @@
 };
 
 struct device_operations default_pci_ops_dev = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init = pci_dev_init,
-	.scan_bus = 0,
-	.enable = 0,
-	.ops_pci = &pci_dev_ops_pci,
+	.init             = pci_dev_init,
+	.scan_bus         = 0,
+	.enable           = 0,
+	.ops_pci          = &pci_dev_ops_pci,
 };
 
 /** Default device operations for PCI bridges */
@@ -693,14 +704,14 @@
 };
 
 struct device_operations default_pci_ops_bus = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_bus_enable_resources,
-	.init = 0,
-	.scan_bus = pci_scan_bridge,
-	.enable = 0,
-	.reset_bus = pci_bus_reset,
-	.ops_pci = &pci_bus_ops_pci,
+	.init             = 0,
+	.scan_bus         = pci_scan_bridge,
+	.enable           = 0,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = &pci_bus_ops_pci,
 };
 
 /**
@@ -711,15 +722,15 @@
  * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
  * Hypertransport all seem to have appropriate capabilities.
  *
- * When only a PCI-Express capability is found the type
- * is examined to see which type of bridge we have.
+ * When only a PCI-Express capability is found the type is examined to see
+ * which type of bridge we have.
  *
  * @param dev Pointer to the device structure of the bridge.
  * @return Appropriate bridge operations.
  */
 static struct device_operations *get_pci_bridge_ops(device_t dev)
 {
-	unsigned pos;
+	unsigned int pos;
 
 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
 	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
@@ -729,17 +740,17 @@
 	}
 #endif
 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
-	/* How do I detect an PCI to AGP bridge? */
+	/* How do I detect a PCI to AGP bridge? */
 #endif
 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
 	pos = 0;
 	while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
-		unsigned flags;
+		u16 flags;
 		flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
 		if ((flags >> 13) == 1) {
 			/* Host or Secondary Interface */
-			printk(BIOS_DEBUG, "%s subordinate bus Hypertransport\n",
-				     dev_path(dev));
+			printk(BIOS_DEBUG, "%s subordinate bus HT\n",
+			       dev_path(dev));
 			return &default_ht_ops_bus;
 		}
 	}
@@ -747,17 +758,18 @@
 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
 	pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 	if (pos) {
-		unsigned flags;
+		u16 flags;
 		flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
 		switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
 		case PCI_EXP_TYPE_ROOT_PORT:
 		case PCI_EXP_TYPE_UPSTREAM:
 		case PCI_EXP_TYPE_DOWNSTREAM:
 			printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
-				     dev_path(dev));
+			       dev_path(dev));
 			return &default_pciexp_ops_bus;
 		case PCI_EXP_TYPE_PCI_BRIDGE:
-			printk(BIOS_DEBUG, "%s subordinate PCI\n", dev_path(dev));
+			printk(BIOS_DEBUG, "%s subordinate PCI\n",
+			       dev_path(dev));
 			return &default_pci_ops_bus;
 		default:
 			break;
@@ -779,11 +791,12 @@
 static void set_pci_ops(struct device *dev)
 {
 	struct pci_driver *driver;
-	if (dev->ops) {
+
+	if (dev->ops)
 		return;
-	}
 
-	/* Look through the list of setup drivers and find one for
+	/*
+	 * Look through the list of setup drivers and find one for
 	 * this PCI device.
 	 */
 	for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
@@ -791,16 +804,15 @@
 		    (driver->device == dev->device)) {
 			dev->ops = (struct device_operations *)driver->ops;
 			printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
-				    dev_path(dev),
-				    driver->vendor, driver->device,
-				    (driver->ops->scan_bus ? "bus " : ""));
+			       dev_path(dev), driver->vendor, driver->device,
+			       (driver->ops->scan_bus ? "bus " : ""));
 			return;
 		}
 	}
 
-	/* If I don't have a specific driver use the default operations */
-	switch (dev->hdr_type & 0x7f) {	/* header type */
-	case PCI_HEADER_TYPE_NORMAL:	/* standard header */
+	/* If I don't have a specific driver use the default operations. */
+	switch (dev->hdr_type & 0x7f) {	/* Header type */
+	case PCI_HEADER_TYPE_NORMAL:
 		if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 			goto bad;
 		dev->ops = &default_pci_ops_dev;
@@ -815,17 +827,15 @@
 		dev->ops = &default_cardbus_ops_bus;
 		break;
 #endif
-	default:
-	      bad:
+default:
+bad:
 		if (dev->enabled) {
-			printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown header "
-				   "type %02x, ignoring.\n",
-				   dev_path(dev),
-				   dev->vendor, dev->device,
-				   dev->class >> 8, dev->hdr_type);
+			printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown "
+			       "header type %02x, ignoring.\n", dev_path(dev),
+			       dev->vendor, dev->device,
+			       dev->class >> 8, dev->hdr_type);
 		}
 	}
-	return;
 }
 
 /**
@@ -843,11 +853,12 @@
 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
 {
 	struct device *dev;
+
 	dev = 0;
 	for (; *list; list = &(*list)->sibling) {
 		if ((*list)->path.type != DEVICE_PATH_PCI) {
-			printk(BIOS_ERR, "child %s not a pci device\n",
-				   dev_path(*list));
+			printk(BIOS_ERR, "child %s not a PCI device\n",
+			       dev_path(*list));
 			continue;
 		}
 		if ((*list)->path.pci.devfn == devfn) {
@@ -859,23 +870,24 @@
 		}
 	}
 
-	/* Just like alloc_dev() add the device to the list of devices on the
+	/*
+	 * Just like alloc_dev() add the device to the list of devices on the
 	 * bus. When the list of devices was formed we removed all of the
 	 * parents children, and now we are interleaving static and dynamic
 	 * devices in order on the bus.
 	 */
 	if (dev) {
 		struct device *child;
+
 		/* Find the last child of our parent. */
-		for (child = dev->bus->children; child && child->sibling;) {
+		for (child = dev->bus->children; child && child->sibling;)
 			child = child->sibling;
-		}
+
 		/* Place the device on the list of children of its parent. */
-		if (child) {
+		if (child)
 			child->sibling = dev;
-		} else {
+		else
 			dev->bus->children = dev;
-		}
 	}
 
 	return dev;
@@ -900,25 +912,29 @@
 	/* Detect if a device is present. */
 	if (!dev) {
 		struct device dummy;
+
 		dummy.bus = bus;
 		dummy.path.type = DEVICE_PATH_PCI;
 		dummy.path.pci.devfn = devfn;
+
 		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
-		/* Have we found something?
-		 * Some broken boards return 0 if a slot is empty, but
-		 * the expected answer is 0xffffffff
+		/*
+		 * Have we found something? Some broken boards return 0 if a
+		 * slot is empty, but the expected answer is 0xffffffff.
 		 */
-		if (id == 0xffffffff) {
+		if (id == 0xffffffff)
 			return NULL;
-		}
+
 		if ((id == 0x00000000) || (id == 0x0000ffff) ||
 		    (id == 0xffff0000)) {
-			printk(BIOS_SPEW, "%s, bad id 0x%x\n", dev_path(&dummy), id);
+			printk(BIOS_SPEW, "%s, bad id 0x%x\n",
+			       dev_path(&dummy), id);
 			return NULL;
 		}
 		dev = alloc_dev(bus, &dummy.path);
 	} else {
-		/* Enable/disable the device. Once we have found the device-
+		/*
+		 * Enable/disable the device. Once we have found the device-
 		 * specific operations this operations we will disable the
 		 * device with those as well.
 		 *
@@ -929,13 +945,14 @@
 		 * it may be absent and enable_dev() must cope.
 		 */
 		/* Run the magic enable sequence for the device. */
-		if (dev->chip_ops && dev->chip_ops->enable_dev) {
+		if (dev->chip_ops && dev->chip_ops->enable_dev)
 			dev->chip_ops->enable_dev(dev);
-		}
+
 		/* Now read the vendor and device ID. */
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
 
-		/* If the device does not have a PCI ID disable it. Possibly
+		/*
+		 * If the device does not have a PCI ID disable it. Possibly
 		 * this is because we have already disabled the device. But
 		 * this also handles optional devices that may not always
 		 * show up.
@@ -944,13 +961,14 @@
 		if ((id == 0xffffffff) || (id == 0x00000000) ||
 		    (id == 0x0000ffff) || (id == 0xffff0000)) {
 			if (dev->enabled) {
-				printk(BIOS_INFO, "PCI: Static device %s not found, disabling it.\n",
-					    dev_path(dev));
+				printk(BIOS_INFO, "PCI: Static device %s not "
+				       "found, disabling it.\n", dev_path(dev));
 				dev->enabled = 0;
 			}
 			return dev;
 		}
 	}
+
 	/* Read the rest of the PCI configuration information. */
 	hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
 	class = pci_read_config32(dev, PCI_CLASS_REVISION);
@@ -964,26 +982,24 @@
 	dev->class = class >> 8;
 
 	/* Architectural/System devices always need to be bus masters. */
-	if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
+	if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM)
 		dev->command |= PCI_COMMAND_MASTER;
-	}
-	/* Look at the vendor and device ID, or at least the header type and
+
+	/*
+	 * Look at the vendor and device ID, or at least the header type and
 	 * class and figure out which set of configuration methods to use.
 	 * Unless we already have some PCI ops.
 	 */
 	set_pci_ops(dev);
 
 	/* Now run the magic enable/disable sequence for the device. */
-	if (dev->ops && dev->ops->enable) {
+	if (dev->ops && dev->ops->enable)
 		dev->ops->enable(dev);
-	}
 
 	/* Display the device. */
-	printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n",
-		     dev_path(dev),
-		     dev->vendor, dev->device,
-		     dev->enabled ? "enabled" : "disabled",
-		     dev->ops ? "" : " No operations");
+	printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n", dev_path(dev),
+	       dev->vendor, dev->device, dev->enabled ? "enabled" : "disabled",
+	       dev->ops ? "" : " No operations");
 
 	return dev;
 }
@@ -1003,9 +1019,8 @@
  * @param max Current bus number.
  * @return The maximum bus number found, after scanning all subordinate busses.
  */
-unsigned int pci_scan_bus(struct bus *bus,
-			  unsigned min_devfn, unsigned max_devfn,
-			  unsigned int max)
+unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
+			  unsigned max_devfn, unsigned int max)
 {
 	unsigned int devfn;
 	struct device *old_devices;
@@ -1013,16 +1028,17 @@
 
 #if CONFIG_PCI_BUS_SEGN_BITS
 	printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n",
-		     bus->secondary >> 8, bus->secondary & 0xff);
+	       bus->secondary >> 8, bus->secondary & 0xff);
 #else
 	printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
 #endif
 
-	// Maximum sane devfn is 0xFF
+	/* Maximum sane devfn is 0xFF. */
 	if (max_devfn > 0xff) {
-		printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - devfn %x\n",
-			   min_devfn, max_devfn );
-		printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. Using 0xff.\n");
+		printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - "
+		       "devfn %x\n", min_devfn, max_devfn);
+		printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. "
+		       "Using 0xff.\n");
 		max_devfn=0xff;
 	}
 
@@ -1030,50 +1046,55 @@
 	bus->children = NULL;
 
 	post_code(0x24);
-	/* Probe all devices/functions on this bus with some optimization for
+
+	/*
+	 * Probe all devices/functions on this bus with some optimization for
 	 * non-existence and single function devices.
 	 */
 	for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
 		struct device *dev;
 
-		/* First thing setup the device structure */
+		/* First thing setup the device structure. */
 		dev = pci_scan_get_dev(&old_devices, devfn);
 
 		/* See if a device is present and setup the device structure. */
 		dev = pci_probe_dev(dev, bus, devfn);
 
-		/* If this is not a multi function device, or the device is
+		/*
+		 * If this is not a multi function device, or the device is
 		 * not present don't waste time probing another function.
 		 * Skip to next device.
 		 */
-		if ((PCI_FUNC(devfn) == 0x00) &&
-		    (!dev
+		if ((PCI_FUNC(devfn) == 0x00) && (!dev
 		     || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
 			devfn += 0x07;
 		}
 	}
+
 	post_code(0x25);
 
-	/* Warn if any leftover static devices are are found.
-	 * There's probably a problem in the Config.lb.
+	/*
+	 * Warn if any leftover static devices are are found.
+	 * There's probably a problem in devicetree.cb.
 	 */
 	if (old_devices) {
 		device_t left;
 		printk(BIOS_WARNING, "PCI: Left over static devices:\n");
-		for (left = old_devices; left; left = left->sibling) {
+		for (left = old_devices; left; left = left->sibling)
 			printk(BIOS_WARNING, "%s\n", dev_path(left));
-		}
-		printk(BIOS_WARNING, "PCI: Check your mainboard Config.lb.\n");
+
+		printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n");
 	}
 
-	/* For all children that implement scan_bus() (i.e. bridges)
+	/*
+	 * For all children that implement scan_bus() (i.e. bridges)
 	 * scan the bus behind that child.
 	 */
-	for (child = bus->children; child; child = child->sibling) {
+	for (child = bus->children; child; child = child->sibling)
 		max = scan_bus(child, max);
-	}
 
-	/* We've scanned the bus and so we know all about what's on the other
+	/*
+	 * We've scanned the bus and so we know all about what's on the other
 	 * side of any bridges that may be on this bus plus any devices.
 	 * Return how far we've got finding sub-buses.
 	 */
@@ -1119,7 +1140,8 @@
 
 	bus = dev->link_list;
 
-	/* Set up the primary, secondary and subordinate bus numbers. We have
+	/*
+	 * Set up the primary, secondary and subordinate bus numbers. We have
 	 * no idea how many buses are behind this bridge yet, so we set the
 	 * subordinate bus number to 0xff for the moment.
 	 */
@@ -1131,12 +1153,14 @@
 	pci_write_config16(dev, PCI_COMMAND, 0x0000);
 	pci_write_config16(dev, PCI_STATUS, 0xffff);
 
-	/* Read the existing primary/secondary/subordinate bus
+	/*
+	 * Read the existing primary/secondary/subordinate bus
 	 * number configuration.
 	 */
 	buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
 
-	/* Configure the bus numbers for this bridge: the configuration
+	/*
+	 * Configure the bus numbers for this bridge: the configuration
 	 * transactions will not be propagated by the bridge if it is not
 	 * correctly configured.
 	 */
@@ -1146,12 +1170,11 @@
 		  ((unsigned int)(bus->subordinate) << 16));
 	pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
 
-	/* Now we can scan all subordinate buses
-	 * i.e. the bus behind the bridge.
-	 */
+	/* Now we can scan all subordinate buses (those behind the bridge). */
 	max = do_scan_bus(bus, 0x00, 0xff, max);
 
-	/* We know the number of buses behind this bridge. Set the subordinate
+	/*
+	 * We know the number of buses behind this bridge. Set the subordinate
 	 * bus number to its real value.
 	 */
 	bus->subordinate = max;
@@ -1200,7 +1223,7 @@
  * Assign IRQ numbers.
  *
  * This function assigns IRQs for all functions contained within the indicated
- * device address.  If the device does not exist or does not require interrupts
+ * device address. If the device does not exist or does not require interrupts
  * then this function has no effect.
  *
  * This function should be called for each PCI slot in your system.
@@ -1212,14 +1235,13 @@
  *        routing inside your southbridge and on your board.
  */
 void pci_assign_irqs(unsigned bus, unsigned slot,
-	const unsigned char pIntAtoD[4])
+		     const unsigned char pIntAtoD[4])
 {
 	unsigned int funct;
 	device_t pdev;
-	u8 line;
-	u8 irq;
+	u8 line, irq;
 
-	/* Each slot may contain up to eight functions */
+	/* Each slot may contain up to eight functions. */
 	for (funct = 0; funct < 8; funct++) {
 		pdev = dev_find_slot(bus, (slot << 3) + funct);
 
@@ -1228,26 +1250,26 @@
 
 		line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
 
-		// PCI spec says all values except 1..4 are reserved.
+		/* PCI spec says all values except 1..4 are reserved. */
 		if ((line < 1) || (line > 4))
 			continue;
 
 		irq = pIntAtoD[line - 1];
 
 		printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n",
-			irq, bus, slot, funct);
+		       irq, bus, slot, funct);
 
 		pci_write_config8(pdev, PCI_INTERRUPT_LINE,
-			pIntAtoD[line - 1]);
+				  pIntAtoD[line - 1]);
 
 #ifdef PARANOID_IRQ_ASSIGNMENTS
 		irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
 		printk(BIOS_DEBUG, "  Readback = %d\n", irq);
 #endif
 
-		// Change to level triggered
-		i8259_configure_irq_trigger(pIntAtoD[line - 1], IRQ_LEVEL_TRIGGERED);
+		/* Change to level triggered. */
+		i8259_configure_irq_trigger(pIntAtoD[line - 1],
+					    IRQ_LEVEL_TRIGGERED);
 	}
 }
 #endif
-

Modified: trunk/src/devices/pci_ops.c
==============================================================================
--- trunk/src/devices/pci_ops.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/pci_ops.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -38,93 +38,112 @@
 	else
 		pbus = dev->bus;
 
-	while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
+	while (pbus && pbus->dev && !ops_pci_bus(pbus)) {
 		if (pbus == pbus->dev->bus) {
-			printk(BIOS_ALERT, "%s in endless loop looking for a parent "
-				"bus with ops_pci_bus for %s, breaking out.\n",
-				 __func__, dev_path(dev));
+			printk(BIOS_ALERT, "%s in endless loop looking for a "
+			       "parent bus with ops_pci_bus for %s, breaking "
+			       "out.\n", __func__, dev_path(dev));
 			break;
 		}
 		pbus = pbus->dev->bus;
 	}
-	if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) {
-		/* This can happen before the device tree is set up completely. */
-		//printk(BIOS_EMERG, "%s: Cannot find pci bus operations.\n", dev_path(dev));
+
+	if (!pbus || !pbus->dev || !pbus->dev->ops
+	    || !pbus->dev->ops->ops_pci_bus) {
+		/* This can happen before the device tree is fully set up. */
+
+		// printk(BIOS_EMERG, "%s: Cannot find PCI bus operations.\n",
+		// dev_path(dev));
+
 		pbus = NULL;
 	}
+
 	return pbus;
 }
 
-uint8_t pci_read_config8(device_t dev, unsigned where)
+u8 pci_read_config8(device_t dev, unsigned int where)
 {
 	struct bus *pbus = get_pbus(dev);
-	return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+	return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary,
+					dev->path.pci.devfn, where);
 }
 
-uint16_t pci_read_config16(device_t dev, unsigned where)
+u16 pci_read_config16(device_t dev, unsigned int where)
 {
 	struct bus *pbus = get_pbus(dev);
-	return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+	return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary,
+					 dev->path.pci.devfn, where);
 }
 
-uint32_t pci_read_config32(device_t dev, unsigned where)
+u32 pci_read_config32(device_t dev, unsigned int where)
 {
 	struct bus *pbus = get_pbus(dev);
-	return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+	return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary,
+					 dev->path.pci.devfn, where);
 }
 
-void pci_write_config8(device_t dev, unsigned where, uint8_t val)
+void pci_write_config8(device_t dev, unsigned int where, u8 val)
 {
 	struct bus *pbus = get_pbus(dev);
-	ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+	ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary,
+				  dev->path.pci.devfn, where, val);
 }
 
-void pci_write_config16(device_t dev, unsigned where, uint16_t val)
+void pci_write_config16(device_t dev, unsigned int where, u16 val)
 {
 	struct bus *pbus = get_pbus(dev);
-	ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+	ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary,
+				   dev->path.pci.devfn, where, val);
 }
 
-void pci_write_config32(device_t dev, unsigned where, uint32_t val)
+void pci_write_config32(device_t dev, unsigned int where, u32 val)
 {
 	struct bus *pbus = get_pbus(dev);
-	ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+	ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary,
+				   dev->path.pci.devfn, where, val);
 }
 
 #if CONFIG_MMCONF_SUPPORT
-uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
+u8 pci_mmio_read_config8(device_t dev, unsigned int where)
 {
 	struct bus *pbus = get_pbus(dev);
-	return pci_ops_mmconf.read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+	return pci_ops_mmconf.read8(pbus, dev->bus->secondary,
+				    dev->path.pci.devfn, where);
 }
 
-uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
+u16 pci_mmio_read_config16(device_t dev, unsigned int where)
 {
 	struct bus *pbus = get_pbus(dev);
-	return pci_ops_mmconf.read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+	return pci_ops_mmconf.read16(pbus, dev->bus->secondary,
+				     dev->path.pci.devfn, where);
 }
 
-uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
+u32 pci_mmio_read_config32(device_t dev, unsigned int where)
 {
 	struct bus *pbus = get_pbus(dev);
-	return pci_ops_mmconf.read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+	return pci_ops_mmconf.read32(pbus, dev->bus->secondary,
+				     dev->path.pci.devfn, where);
 }
 
-void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t val)
+void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val)
 {
 	struct bus *pbus = get_pbus(dev);
-	pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+	pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn,
+			      where, val);
 }
 
-void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t val)
+void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val)
 {
 	struct bus *pbus = get_pbus(dev);
-	pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+	pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn,
+			       where, val);
 }
 
-void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val)
+void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val)
 {
 	struct bus *pbus = get_pbus(dev);
-	pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+	pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn,
+			       where, val);
 }
+
 #endif

Modified: trunk/src/devices/pci_rom.c
==============================================================================
--- trunk/src/devices/pci_rom.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/pci_rom.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -38,59 +38,62 @@
 	rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
 
 	if (rom_header) {
-		printk(BIOS_DEBUG, "In cbfs, rom address for %s = %p\n",
-			     dev_path(dev), rom_header);
+		printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n",
+		       dev_path(dev), rom_header);
 	} else {
-		unsigned long rom_address;
+		u32 rom_address;
 
 		rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
 
 		if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
-			#if defined(CONFIG_BOARD_EMULATION_QEMU_X86) \
-				 && CONFIG_BOARD_EMULATION_QEMU_X86
+#if defined(CONFIG_BOARD_EMULATION_QEMU_X86) && CONFIG_BOARD_EMULATION_QEMU_X86
 			if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
 				rom_address = 0xc0000;
 			else
-			#endif
+#endif
 				return NULL;
 		} else {
-			/* enable expansion ROM address decoding */
+			/* Enable expansion ROM address decoding. */
 			pci_write_config32(dev, PCI_ROM_ADDRESS,
 					   rom_address|PCI_ROM_ADDRESS_ENABLE);
 		}
 
-		printk(BIOS_DEBUG, "On card, rom address for %s = %lx\n",
-				dev_path(dev), rom_address);
+		printk(BIOS_DEBUG, "On card, ROM address for %s = %lx\n",
+		       dev_path(dev), (unsigned long)rom_address);
 		rom_header = (struct rom_header *)rom_address;
 	}
 
-	printk(BIOS_SPEW, "PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n",
-		    le32_to_cpu(rom_header->signature),
-		    rom_header->size * 512, le32_to_cpu(rom_header->data));
+	printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "
+	       "INIT size 0x%04x, data ptr 0x%04x\n",
+	       le32_to_cpu(rom_header->signature),
+	       rom_header->size * 512, le32_to_cpu(rom_header->data));
+
 	if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
-		printk(BIOS_ERR, "Incorrect Expansion ROM Header Signature %04x\n",
-			   le32_to_cpu(rom_header->signature));
+		printk(BIOS_ERR, "Incorrect expansion ROM header "
+		       "signature %04x\n", le32_to_cpu(rom_header->signature));
 		return NULL;
 	}
 
 	rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data));
 
-	printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n",
-		    rom_data->vendor, rom_data->device);
-	if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
-		printk(BIOS_ERR, "ID mismatch: Vendor ID %04x, Device ID %04x\n",
-			   rom_data->vendor, rom_data->device);
+	printk(BIOS_SPEW, "PCI ROM image, vendor ID %04x, device ID %04x,\n",
+	       rom_data->vendor, rom_data->device);
+	if (dev->vendor != rom_data->vendor
+	    || dev->device != rom_data->device) {
+		printk(BIOS_ERR, "ID mismatch: vendor ID %04x, "
+		       "device ID %04x\n", rom_data->vendor, rom_data->device);
 		return NULL;
 	}
 
-	printk(BIOS_SPEW, "PCI ROM Image,  Class Code %04x%02x, Code Type %02x\n",
-		    rom_data->class_hi, rom_data->class_lo,
-		    rom_data->type);
+	printk(BIOS_SPEW, "PCI ROM image, Class Code %04x%02x, "
+	       "Code Type %02x\n", rom_data->class_hi, rom_data->class_lo,
+	       rom_data->type);
+
 	if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
 		printk(BIOS_DEBUG, "Class Code mismatch ROM %08x, dev %08x\n",
-			     (rom_data->class_hi << 8) | rom_data->class_lo,
-			     dev->class);
-		//return NULL;
+		       (rom_data->class_hi << 8) | rom_data->class_lo,
+		       dev->class);
+		// return NULL;
 	}
 
 	return rom_header;
@@ -98,41 +101,51 @@
 
 static void *pci_ram_image_start = (void *)PCI_RAM_IMAGE_START;
 
-struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header)
+struct rom_header *pci_rom_load(struct device *dev,
+				struct rom_header *rom_header)
 {
 	struct pci_data * rom_data;
 	unsigned int rom_size;
 	unsigned int image_size=0;
 
 	do {
-		rom_header = (struct rom_header *)((void *) rom_header + image_size); // get next image
-	        rom_data = (struct pci_data *)((void *) rom_header + le32_to_cpu(rom_header->data));
-        	image_size = le32_to_cpu(rom_data->ilen) * 512;
-	} while ((rom_data->type!=0) && (rom_data->indicator!=0));  // make sure we got x86 version
+		/* Get next image. */
+		rom_header = (struct rom_header *)((void *) rom_header
+							    + image_size);
+
+		rom_data = (struct pci_data *)((void *) rom_header
+				+ le32_to_cpu(rom_header->data));
+
+		image_size = le32_to_cpu(rom_data->ilen) * 512;
+	} while ((rom_data->type != 0) && (rom_data->indicator != 0)); // make sure we got x86 version
 
 	if (rom_data->type != 0)
 		return NULL;
 
 	rom_size = rom_header->size * 512;
 
-	// We check to see if the device thinks it is a VGA device not
-	// whether the ROM image is for a VGA device because some
-	// devices have a mismatch between the hardware and the ROM
+	/*
+	 * We check to see if the device thinks it is a VGA device not
+	 * whether the ROM image is for a VGA device because some
+	 * devices have a mismatch between the hardware and the ROM.
+	 */
  	if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) {
 #if CONFIG_CONSOLE_VGA == 1 && CONFIG_CONSOLE_VGA_MULTI == 0
-		extern device_t vga_pri;	// the primary vga device, defined in device.c
-		if (dev != vga_pri) return NULL; // only one VGA supported
+		extern device_t vga_pri; /* Primary VGA device (device.c). */
+		if (dev != vga_pri) return NULL; /* Only one VGA supported. */
 #endif
 		if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) {
-			printk(BIOS_DEBUG, "copying VGA ROM Image from %p to 0x%x, 0x%x bytes\n",
-			    rom_header, PCI_VGA_RAM_IMAGE_START, rom_size);
-			memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size);
+			printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to "
+			       "0x%x, 0x%x bytes\n", rom_header,
+			       PCI_VGA_RAM_IMAGE_START, rom_size);
+			memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header,
+			       rom_size);
 		}
 		return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START);
 	}
 
-	printk(BIOS_DEBUG, "copying non-VGA ROM Image from %p to %p, 0x%x bytes\n",
-		    rom_header, pci_ram_image_start, rom_size);
+	printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x "
+	       "bytes\n", rom_header, pci_ram_image_start, rom_size);
 
 	memcpy(pci_ram_image_start, rom_header, rom_size);
 	pci_ram_image_start += rom_size;

Modified: trunk/src/devices/pciexp_device.c
==============================================================================
--- trunk/src/devices/pciexp_device.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/pciexp_device.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -27,6 +27,9 @@
 static void pciexp_tune_dev(device_t dev)
 {
 	unsigned int cap;
+#ifdef CONFIG_PCIE_TUNING
+	u32 reg32;
+#endif
 
 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 	if (!cap)
@@ -35,9 +38,9 @@
 #ifdef CONFIG_PCIE_TUNING
 	printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
 
-	// TODO make this depending on ASPM
-	/* Enable ASPM Role Based Error Reporting */
-	u32 reg32;
+	// TODO make this depending on ASPM.
+
+	/* Enable ASPM role based error reporting. */
 	reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
 	reg32 |= PCI_EXP_DEVCAP_RBER;
 	pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);

Modified: trunk/src/devices/pcix_device.c
==============================================================================
--- trunk/src/devices/pcix_device.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/pcix_device.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -56,7 +56,7 @@
 	/* Don't attempt to handle PCI-X errors. */
 	cmd &= ~PCI_X_CMD_DPERR_E;
 
-	/* Enable Relaxed Ordering. */
+	/* Enable relaxed ordering. */
 	cmd |= PCI_X_CMD_ERO;
 
 	if (orig_cmd != cmd)
@@ -108,6 +108,7 @@
 		result = pcix_533mhz;
 		break;
 	}
+
 	return result;
 }
 

Modified: trunk/src/devices/pnp_device.c
==============================================================================
--- trunk/src/devices/pnp_device.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/pnp_device.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -163,7 +163,7 @@
 	.enable           = pnp_enable,
 };
 
-/* PNP chip opertations */
+/* PNP chip operations */
 
 static void pnp_get_ioresource(device_t dev, u8 index, struct io_info *info)
 {
@@ -214,18 +214,15 @@
 {
 	struct resource *resource;
 
-	if (info->flags & PNP_IO0) {
+	if (info->flags & PNP_IO0)
 		pnp_get_ioresource(dev, PNP_IDX_IO0, &info->io0);
-	}
-	if (info->flags & PNP_IO1) {
+	if (info->flags & PNP_IO1)
 		pnp_get_ioresource(dev, PNP_IDX_IO1, &info->io1);
-	}
-	if (info->flags & PNP_IO2) {
+	if (info->flags & PNP_IO2)
 		pnp_get_ioresource(dev, PNP_IDX_IO2, &info->io2);
-	}
-	if (info->flags & PNP_IO3) {
+	if (info->flags & PNP_IO3)
 		pnp_get_ioresource(dev, PNP_IDX_IO3, &info->io3);
-	}
+
 	if (info->flags & PNP_IRQ0) {
 		resource = new_resource(dev, PNP_IDX_IRQ0);
 		resource->size = 1;
@@ -236,6 +233,7 @@
 		resource->size = 1;
 		resource->flags |= IORESOURCE_IRQ;
 	}
+
 	if (info->flags & PNP_DRQ0) {
 		resource = new_resource(dev, PNP_IDX_DRQ0);
 		resource->size = 1;

Modified: trunk/src/devices/smbus_ops.c
==============================================================================
--- trunk/src/devices/smbus_ops.c	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/devices/smbus_ops.c	Fri Nov  5 00:23:47 2010	(r6019)
@@ -43,7 +43,7 @@
 }
 
 /*
- * Multi-level I2C MUX? may need to find the first i2c device and then set link
+ * Multi-level I2C MUX? May need to find the first I2C device and then set link
  * down to current dev.
  *
  * 1 store get_pbus_smbus list link

Modified: trunk/src/include/device/device.h
==============================================================================
--- trunk/src/include/device/device.h	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/include/device/device.h	Fri Nov  5 00:23:47 2010	(r6019)
@@ -120,7 +120,7 @@
 /* Helper functions */
 device_t find_dev_path(struct bus *parent, struct device_path *path);
 device_t alloc_find_dev(struct bus *parent, struct device_path *path);
-device_t dev_find_device (unsigned int vendor, unsigned int device, device_t from);
+device_t dev_find_device (u16 vendor, u16 device, device_t from);
 device_t dev_find_class (unsigned int class, device_t from);
 device_t dev_find_slot (unsigned int bus, unsigned int devfn);
 device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);

Modified: trunk/src/include/device/pci.h
==============================================================================
--- trunk/src/include/device/pci.h	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/include/device/pci.h	Fri Nov  5 00:23:47 2010	(r6019)
@@ -15,6 +15,7 @@
 #ifndef PCI_H
 #define PCI_H
 
+#include <stdint.h>
 #include <device/pci_def.h>
 #include <device/resource.h>
 #include <device/device.h>

Modified: trunk/src/include/device/pci_ops.h
==============================================================================
--- trunk/src/include/device/pci_ops.h	Thu Nov  4 19:33:42 2010	(r6018)
+++ trunk/src/include/device/pci_ops.h	Fri Nov  5 00:23:47 2010	(r6019)
@@ -5,20 +5,20 @@
 #include <device/device.h>
 #include <arch/pci_ops.h>
 
-uint8_t  pci_read_config8(device_t dev, unsigned where);
-uint16_t pci_read_config16(device_t dev, unsigned where);
-uint32_t pci_read_config32(device_t dev, unsigned where);
-void pci_write_config8(device_t dev, unsigned where, uint8_t val);
-void pci_write_config16(device_t dev, unsigned where, uint16_t val);
-void pci_write_config32(device_t dev, unsigned where, uint32_t val);
+u8 pci_read_config8(device_t dev, unsigned int where);
+u16 pci_read_config16(device_t dev, unsigned int where);
+u32 pci_read_config32(device_t dev, unsigned int where);
+void pci_write_config8(device_t dev, unsigned int where, u8 val);
+void pci_write_config16(device_t dev, unsigned int where, u16 val);
+void pci_write_config32(device_t dev, unsigned int where, u32 val);
 
 #if CONFIG_MMCONF_SUPPORT
-uint8_t  pci_mmio_read_config8(device_t dev, unsigned where);
-uint16_t pci_mmio_read_config16(device_t dev, unsigned where);
-uint32_t pci_mmio_read_config32(device_t dev, unsigned where);
-void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t val);
-void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t val);
-void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val);
+u8 pci_mmio_read_config8(device_t dev, unsigned int where);
+u16 pci_mmio_read_config16(device_t dev, unsigned int where);
+u32 pci_mmio_read_config32(device_t dev, unsigned int where);
+void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val);
+void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val);
+void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val);
 #endif
 
 /* This function lives in pci_ops_auto.c */



From rminnich at gmail.com  Fri Nov  5 00:54:14 2010
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Nov 2010 16:54:14 -0700
Subject: [coreboot] interesting request for serial console over enet
Message-ID: <AANLkTi=hwYw__ozW8AOmZ5aMsHiz_H5CX8LUX7Pb7oFx@mail.gmail.com>

someone I know from a Big telecom company just pushed an interesting
idea on me.

If coreboot+seabios would provide a bios service for serial console
over enet, it would improve their life a lot. They could stop building
cyclades boxes into their racks, and stop worrying about which
mainboards had serial ports. I know that coreboot can now do console
over enet; would be neat if seabios could provide a path for payloads
to use it.

Note they don't want vga over enet or IPMI. Just a very simple "until
we're  booted" console over enet that looks like serial port. Sort of
a bios-level version of this: http://man.cat-v.org/plan_9/8/cec

Just thought I'd mention it ...

ron



From svn at coreboot.org  Fri Nov  5 01:07:14 2010
From: svn at coreboot.org (repository service)
Date: Fri, 05 Nov 2010 01:07:14 +0100
Subject: [coreboot] [commit] r6020 - in trunk/src/superio: fintek/f71805f
	fintek/f71859 fintek/f71863fg fintek/f71889 intel/i3100
Message-ID: <E1PE9pq-0006pO-CW@ra.coresystems.de>

Author: uwe
Date: Fri Nov  5 01:07:13 2010
New Revision: 6020
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6020

Log:
Fintek and Intel i3100 Super I/O cleanups.

 - Drop commented out "config chip.h" and a duplicate link to a datasheet.

 - F71805F -> F71805F/FG, to mention all variants.
 
 - Use u8/u16/ etc. everywhere.
 
 - Add a missing (C) line.
 
 - Fix up a bunch of pnp_dev_info[] structs according to the datasheets.
 
 - Fintek F71889: Drop res1/PNP_IO1 from KBC, there's no 0x62/0x63 register
   pair on this Super I/O.
   
 - Fintek F71863FG: This Super I/O _does_ have a keyboard/mouse LDN, add the
   respective code in superio.c. Also: Add missing LDNs to f71863fg.h.
   
 - i3100: Add some more comments and datasheet infos.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/superio/fintek/f71805f/Makefile.inc
   trunk/src/superio/fintek/f71805f/f71805f.h
   trunk/src/superio/fintek/f71805f/f71805f_early_serial.c
   trunk/src/superio/fintek/f71805f/superio.c
   trunk/src/superio/fintek/f71859/Makefile.inc
   trunk/src/superio/fintek/f71859/f71859_early_serial.c
   trunk/src/superio/fintek/f71859/superio.c
   trunk/src/superio/fintek/f71863fg/chip.h
   trunk/src/superio/fintek/f71863fg/f71863fg.h
   trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c
   trunk/src/superio/fintek/f71863fg/superio.c
   trunk/src/superio/fintek/f71889/superio.c
   trunk/src/superio/intel/i3100/Makefile.inc
   trunk/src/superio/intel/i3100/i3100.h
   trunk/src/superio/intel/i3100/i3100_early_serial.c
   trunk/src/superio/intel/i3100/superio.c

Modified: trunk/src/superio/fintek/f71805f/Makefile.inc
==============================================================================
--- trunk/src/superio/fintek/f71805f/Makefile.inc	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71805f/Makefile.inc	Fri Nov  5 01:07:13 2010	(r6020)
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-#config chip.h
 ramstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.c
+

Modified: trunk/src/superio/fintek/f71805f/f71805f.h
==============================================================================
--- trunk/src/superio/fintek/f71805f/f71805f.h	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71805f/f71805f.h	Fri Nov  5 01:07:13 2010	(r6020)
@@ -30,7 +30,7 @@
 #define F71805F_FDC	0x00	/* Floppy */
 #define F71805F_SP1	0x01	/* UART1 */
 #define	F71805F_SP2	0x02	/* UART2 */
-#define F71805F_PP	0x03	/* Parallel Port */
-#define	F71805F_HWM	0x04	/* Hardware Monitor */
+#define F71805F_PP	0x03	/* Parallel port */
+#define	F71805F_HWM	0x04	/* Hardware monitor */
 #define	F71805F_GPIO	0x06	/* General Purpose I/O (GPIO) */
 #define	F71805F_PME	0x0a	/* Power Management Events (PME) */

Modified: trunk/src/superio/fintek/f71805f/f71805f_early_serial.c
==============================================================================
--- trunk/src/superio/fintek/f71805f/f71805f_early_serial.c	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71805f/f71805f_early_serial.c	Fri Nov  5 01:07:13 2010	(r6020)
@@ -23,19 +23,19 @@
 #include <arch/romcc_io.h>
 #include "f71805f.h"
 
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
 {
-	unsigned int port = dev >> 8;
+	u16 port = dev >> 8;
 	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
 {
-	unsigned int port = dev >> 8;
+	u16 port = dev >> 8;
 	outb(0xaa, port);
 }
 
-static void f71805f_enable_serial(device_t dev, unsigned int iobase)
+static void f71805f_enable_serial(device_t dev, u16 iobase)
 {
 	pnp_enter_conf_state(dev);
 	pnp_set_logical_device(dev);

Modified: trunk/src/superio/fintek/f71805f/superio.c
==============================================================================
--- trunk/src/superio/fintek/f71805f/superio.c	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71805f/superio.c	Fri Nov  5 01:07:13 2010	(r6020)
@@ -18,8 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* Datasheet: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf */
-
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pnp.h>
@@ -107,6 +105,6 @@
 }
 
 struct chip_operations superio_fintek_f71805f_ops = {
-	CHIP_NAME("Fintek F71805F Super I/O")
+	CHIP_NAME("Fintek F71805F/FG Super I/O")
 	.enable_dev = enable_dev
 };

Modified: trunk/src/superio/fintek/f71859/Makefile.inc
==============================================================================
--- trunk/src/superio/fintek/f71859/Makefile.inc	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71859/Makefile.inc	Fri Nov  5 01:07:13 2010	(r6020)
@@ -1,6 +1,8 @@
 ##
 ## This file is part of the coreboot project.
 ##
+## Copyright (C) 2010 Marc Jones <marcj303 at gmail.com>
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
@@ -16,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-#config chip.h
 ramstage-$(CONFIG_SUPERIO_FINTEK_F71859) += superio.c
+

Modified: trunk/src/superio/fintek/f71859/f71859_early_serial.c
==============================================================================
--- trunk/src/superio/fintek/f71859/f71859_early_serial.c	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71859/f71859_early_serial.c	Fri Nov  5 01:07:13 2010	(r6020)
@@ -23,19 +23,19 @@
 #include <arch/romcc_io.h>
 #include "f71859.h"
 
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
 {
-	unsigned int port = dev >> 8;
+	u16 port = dev >> 8;
 	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
 {
-	unsigned int port = dev >> 8;
+	u16 port = dev >> 8;
 	outb(0xaa, port);
 }
 
-static void f71859_enable_serial(device_t dev, unsigned int iobase)
+static void f71859_enable_serial(device_t dev, u16 iobase)
 {
 	pnp_enter_conf_state(dev);
 	pnp_set_logical_device(dev);

Modified: trunk/src/superio/fintek/f71859/superio.c
==============================================================================
--- trunk/src/superio/fintek/f71859/superio.c	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71859/superio.c	Fri Nov  5 01:07:13 2010	(r6020)
@@ -19,7 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pnp.h>

Modified: trunk/src/superio/fintek/f71863fg/chip.h
==============================================================================
--- trunk/src/superio/fintek/f71863fg/chip.h	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71863fg/chip.h	Fri Nov  5 01:07:13 2010	(r6020)
@@ -18,13 +18,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <pc80/keyboard.h>
 #include <device/device.h>
 #include <uart8250.h>
 
-/* This chip doesn't have keyboard and mouse support. */
-
 extern struct chip_operations superio_fintek_f71863fg_ops;
 
 struct superio_fintek_f71863fg_config {
 	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
 };

Modified: trunk/src/superio/fintek/f71863fg/f71863fg.h
==============================================================================
--- trunk/src/superio/fintek/f71863fg/f71863fg.h	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71863fg/f71863fg.h	Fri Nov  5 01:07:13 2010	(r6020)
@@ -22,8 +22,10 @@
 #define F71863FG_FDC	0x00	/* Floppy */
 #define F71863FG_SP1	0x01	/* UART1 */
 #define	F71863FG_SP2	0x02	/* UART2 */
-#define F71863FG_PP	0x03	/* Parallel Port */
-#define	F71863FG_HWM	0x04	/* Hardware Monitor */
-#define	F71863FG_KBC	0x05	/* KBC devices  */
+#define F71863FG_PP	0x03	/* Parallel port */
+#define	F71863FG_HWM	0x04	/* Hardware monitor */
+#define	F71863FG_KBC	0x05	/* PS/2 keyboard and mouse */
 #define	F71863FG_GPIO	0x06	/* General Purpose I/O (GPIO) */
-#define	F71863FG_PME	0x0a	/* Power Management Events (PME) */
+#define	F71863FG_VID	0x07	/* VID */
+#define	F71863FG_SPI	0x08	/* SPI */
+#define	F71863FG_PME	0x0a	/* Power Management Events (PME) and ACPI */

Modified: trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c
==============================================================================
--- trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c	Fri Nov  5 01:07:13 2010	(r6020)
@@ -23,19 +23,19 @@
 #include <arch/romcc_io.h>
 #include "f71863fg.h"
 
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
 {
-	unsigned int port = dev >> 8;
+	u16 port = dev >> 8;
 	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
 {
-	unsigned int port = dev >> 8;
+	u16 port = dev >> 8;
 	outb(0xaa, port);
 }
 
-static void f71863fg_enable_serial(device_t dev, unsigned int iobase)
+static void f71863fg_enable_serial(device_t dev, u16 iobase)
 {
 	pnp_enter_conf_state(dev);
 	pnp_set_logical_device(dev);

Modified: trunk/src/superio/fintek/f71863fg/superio.c
==============================================================================
--- trunk/src/superio/fintek/f71863fg/superio.c	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71863fg/superio.c	Fri Nov  5 01:07:13 2010	(r6020)
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pnp.h>
@@ -56,6 +55,10 @@
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		init_uart8250(res0->base, &conf->com2);
 		break;
+	case F71863FG_KBC:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		pc_keyboard_init(&conf->keyboard);
+		break;
 	}
 }
 
@@ -91,12 +94,15 @@
 
 static struct pnp_info pnp_dev_info[] = {
 	/* TODO: Some of the 0x7f8 etc. values may not be correct. */
-	{ &ops, F71863FG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, F71863FG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
 	{ &ops, F71863FG_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 	{ &ops, F71863FG_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &ops, F71863FG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-	{ &ops, F71863FG_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
-	{ &ops, F71863FG_GPIO, PNP_IRQ0, },
+	{ &ops, F71863FG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
+	{ &ops, F71863FG_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
+	{ &ops, F71863FG_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, },
+	{ &ops, F71863FG_GPIO, },
+	{ &ops, F71863FG_VID,  PNP_IO0, { 0x07f8, 0 }, },
+	{ &ops, F71863FG_SPI, },
 	{ &ops, F71863FG_PME, },
 };
 

Modified: trunk/src/superio/fintek/f71889/superio.c
==============================================================================
--- trunk/src/superio/fintek/f71889/superio.c	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/fintek/f71889/superio.c	Fri Nov  5 01:07:13 2010	(r6020)
@@ -40,7 +40,7 @@
 static void f71889_init(device_t dev)
 {
 	struct superio_fintek_f71889_config *conf = dev->chip_info;
-	struct resource *res0, *res1;
+	struct resource *res0;
 
 	if (!dev->enabled)
 		return;
@@ -57,7 +57,6 @@
 		break;
 	case F71889_KBC:
 		res0 = find_resource(dev, PNP_IDX_IO0);
-		res1 = find_resource(dev, PNP_IDX_IO1);
 		pc_keyboard_init(&conf->keyboard);
 		break;
 	}
@@ -95,14 +94,14 @@
 
 static struct pnp_info pnp_dev_info[] = {
 	/* TODO: Some of the 0x7f8 etc. values may not be correct. */
-	{ &ops, F71889_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, F71889_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
 	{ &ops, F71889_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 	{ &ops, F71889_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &ops, F71889_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-	{ &ops, F71889_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
-	{ &ops, F71889_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+	{ &ops, F71889_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
+	{ &ops, F71889_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
+	{ &ops, F71889_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, },
 	{ &ops, F71889_GPIO, },
-	{ &ops, F71889_VID,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0}, },
+	{ &ops, F71889_VID,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
 	{ &ops, F71889_SPI, },
 	{ &ops, F71889_PME, },
 	{ &ops, F71889_VREF, },

Modified: trunk/src/superio/intel/i3100/Makefile.inc
==============================================================================
--- trunk/src/superio/intel/i3100/Makefile.inc	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/intel/i3100/Makefile.inc	Fri Nov  5 01:07:13 2010	(r6020)
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-#config chip.h
 ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c
+

Modified: trunk/src/superio/intel/i3100/i3100.h
==============================================================================
--- trunk/src/superio/intel/i3100/i3100.h	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/intel/i3100/i3100.h	Fri Nov  5 01:07:13 2010	(r6020)
@@ -18,11 +18,30 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* Datasheet: http://www.intel.com/design/intarch/datashts/313458.htm */
+/*
+ * Datasheet:
+ *  - Name: Intel 3100 Chipset
+ *  - URL: http://www.intel.com/design/intarch/datashts/313458.htm
+ *  - PDF: http://download.intel.com/design/intarch/datashts/31345803.pdf
+ *  - Revision / Date: 007, October 2008
+ *  - Order number: 313458-007US
+ */
 
 #ifndef SUPERIO_INTEL_I3100_I3100_H
 #define SUPERIO_INTEL_I3100_I3100_H
 
+/*
+ * The SIW ("Serial I/O and Watchdog Timer") integrated into the i3100 is
+ * very similar to a Super I/O, both in functionality and config mechanism.
+ *
+ * The SIW contains:
+ *  - UART(s)
+ *  - Serial interrupt controller
+ *  - Watchdog timer (WDT)
+ *  - LPC interface
+ */
+
+/* Logical device numbers (LDNs). */
 #define I3100_SP1 0x04 /* Com1 */
 #define I3100_SP2 0x05 /* Com2 */
 #define I3100_WDT 0x06 /* Watchdog timer */

Modified: trunk/src/superio/intel/i3100/i3100_early_serial.c
==============================================================================
--- trunk/src/superio/intel/i3100/i3100_early_serial.c	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/intel/i3100/i3100_early_serial.c	Fri Nov  5 01:07:13 2010	(r6020)
@@ -21,8 +21,7 @@
 #include <arch/romcc_io.h>
 #include "i3100.h"
 
-static void i3100_sio_write(u8 port, u8 ldn, u8 index,
-			    u8 value)
+static void i3100_sio_write(u8 port, u8 ldn, u8 index, u8 value)
 {
 	outb(0x07, port);
 	outb(ldn, port + 1);
@@ -32,21 +31,21 @@
 
 static void i3100_enable_serial(u8 port, u8 ldn, u16 iobase)
 {
-	/* Enter configuration state */
+	/* Enter configuration state. */
 	outb(0x80, port);
 	outb(0x86, port);
 
-	/* Enable serial port */
+	/* Enable serial port. */
 	i3100_sio_write(port, ldn, 0x30, 0x01);
 
-	/* Set serial port IO region */
+	/* Set serial port I/O region. */
 	i3100_sio_write(port, ldn, 0x60, (iobase >> 8) & 0xff);
 	i3100_sio_write(port, ldn, 0x61, iobase & 0xff);
 
-	/* Enable device interrupts, set UART_CLK predivide to 26 */
+	/* Enable device interrupts, set UART_CLK predivide to 26. */
 	i3100_sio_write(port, 0x00, 0x29, 0x0b);
 
-	/* Exit configuration state */
+	/* Exit configuration state. */
 	outb(0x68, port);
 	outb(0x08, port);
 }

Modified: trunk/src/superio/intel/i3100/superio.c
==============================================================================
--- trunk/src/superio/intel/i3100/superio.c	Fri Nov  5 00:23:47 2010	(r6019)
+++ trunk/src/superio/intel/i3100/superio.c	Fri Nov  5 01:07:13 2010	(r6020)
@@ -43,9 +43,8 @@
 	struct superio_intel_i3100_config *conf;
 	struct resource *res0;
 
-	if (!dev->enabled) {
+	if (!dev->enabled)
 		return;
-	}
 
 	conf = dev->chip_info;
 



From svn at coreboot.org  Fri Nov  5 01:13:15 2010
From: svn at coreboot.org (repository service)
Date: Fri, 05 Nov 2010 01:13:15 +0100
Subject: [coreboot] [commit] r6021 - trunk/src/northbridge/amd/gx2
Message-ID: <E1PE9vf-0008Im-Dr@ra.coresystems.de>

Author: uwe
Date: Fri Nov  5 01:13:14 2010
New Revision: 6021
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6021

Log:
Remove banner wrapper function and unify print(k) usage.

 - Drop banner(), use printk()s instead.

 - Uncomment a few printk()s, if a users doesn't want to see them he/she
   can lower the debug level.

 - Replace print_emerg() with printk(BIOS_EMERG) etc.

Also change 'Assymetirc' into 'Asymmetric', thanks to Idwer for spotting.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/northbridge/amd/gx2/raminit.c

Modified: trunk/src/northbridge/amd/gx2/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/raminit.c	Fri Nov  5 01:07:13 2010	(r6020)
+++ trunk/src/northbridge/amd/gx2/raminit.c	Fri Nov  5 01:13:14 2010	(r6021)
@@ -26,20 +26,15 @@
 	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
 };
 
-static void banner(const char *s)
-{
-	printk(BIOS_DEBUG, " * %s\n", s);
-}
-
 static void hcf(void)
 {
-	print_emerg("DIE\n");
+	printk(BIOS_EMERG, "DIE\n");
 	/* this guarantees we flush the UART fifos (if any) and also
 	 * ensures that things, in general, keep going so no debug output
 	 * is lost
 	 */
 	while (1)
-		print_emerg_char(0);
+		printk(BIOS_EMERG, (0));
 }
 
 static void auto_size_dimm(unsigned int dimm)
@@ -51,35 +46,35 @@
 
 	dimm_setting = 0;
 
-	banner("Check present");
+	printk(BIOS_DEBUG, "Check present\n");
 	/* Check that we have a dimm */
 	if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
 		return;
 	}
 
-	banner("MODBANKS");
+	printk(BIOS_DEBUG, "MODBANKS\n");
 	/* Field: Module Banks per DIMM */
 	/* EEPROM byte usage: (5) Number of DIMM Banks */
 	spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
 	if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
-		print_emerg("Number of module banks not compatible\n");
+		printk(BIOS_EMERG, "Number of module banks not compatible\n");
 		post_code(ERROR_BANK_SET);
 		hcf();
 	}
 	dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
-	banner("FIELDBANKS");
 
+	printk(BIOS_DEBUG, "FIELDBANKS\n");
 	/* Field: Banks per SDRAM device */
 	/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
 	spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
 	if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
-		print_emerg("Number of device banks not compatible\n");
+		printk(BIOS_EMERG, "Number of device banks not compatible\n");
 		post_code(ERROR_BANK_SET);
 		hcf();
 	}
 	dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
-	banner("SPDNUMROWS");
 
+	printk(BIOS_DEBUG, "SPDNUMROWS\n");
 	/* Field: DIMM size
 	 * EEPROM byte usage:
 	 *   (3)  Number of Row Addresses
@@ -90,29 +85,29 @@
 	 */
 	if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
 	    || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
-		print_emerg("Assymetirc DIMM not compatible\n");
+		printk(BIOS_EMERG, "Asymmetric DIMM not compatible\n");
 		post_code(ERROR_UNSUPPORTED_DIMM);
 		hcf();
 	}
-	banner("SPDBANKDENSITY");
 
+	printk(BIOS_DEBUG, "SPDBANKDENSITY\n");
 	dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
-	banner("DIMMSIZE");
+	printk(BIOS_DEBUG, "DIMMSIZE\n");
 	dimm_size |= (dimm_size << 8);	/* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
 	dimm_size &= 0x01FC;	/* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
 
 	/* Module Density * Module Banks */
 	dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;	/* shift to multiply by # DIMM banks */
-	banner("BEFORT CTZ");
+	printk(BIOS_DEBUG, "BEFORT CTZ\n");
 	dimm_size = __builtin_ctz(dimm_size);
-	banner("TEST DIMM SIZE>7");
+	printk(BIOS_DEBUG, "TEST DIMM SIZE>7\n");
 	if (dimm_size > 7) {	/* 7 is 512MB only support 512MB per DIMM */
-		print_emerg("Only support up to 512MB per DIMM\n");
+		printk(BIOS_EMERG, "Only support up to 512MB per DIMM\n");
 		post_code(ERROR_DENSITY_DIMM);
 		hcf();
 	}
 	dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
-	banner("PAGESIZE");
+	printk(BIOS_DEBUG, "PAGESIZE\n");
 
 /*
  * Field: PAGE size
@@ -142,22 +137,22 @@
  */
 
 	spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
-	banner("MAXCOLADDR");
+	printk(BIOS_DEBUG, "MAXCOLADDR\n");
 	if (spd_byte > MAX_COL_ADDR) {
-		print_emerg("DIMM page size not compatible\n");
+		printk(BIOS_EMERG, "DIMM page size not compatible\n");
 		post_code(ERROR_SET_PAGE);
 		hcf();
 	}
-	banner(">11address test");
+	printk(BIOS_DEBUG, ">11address test\n");
 	spd_byte -= 7;
 	if (spd_byte > 4) {	/* if the value is above 4 it means >11 col address lines */
 		spd_byte = 7;	/* which means >16k so set to disabled */
 	}
 	dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT;	/* 0=1k,1=2k,2=4k,etc */
 
-	banner("RDMSR CF07");
+	printk(BIOS_DEBUG, "RDMSR CF07\n");
 	msr = rdmsr(MC_CF07_DATA);
-	banner("WRMSR CF07");
+	printk(BIOS_DEBUG, "WRMSR CF07\n");
 	if (dimm == DIMM0) {
 		msr.hi &= 0xFFFF0000;
 		msr.hi |= dimm_setting;
@@ -166,7 +161,7 @@
 		msr.hi |= dimm_setting << 16;
 	}
 	wrmsr(MC_CF07_DATA, msr);
-	banner("ALL DONE");
+	printk(BIOS_DEBUG, "ALL DONE\n");
 }
 
 static void checkDDRMax(void)
@@ -194,7 +189,7 @@
 
 	/* current speed > max speed? */
 	if (GeodeLinkSpeed() > speed) {
-		print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
+		printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
 		post_code(POST_PLL_MEM_FAIL);
 		hcf();
 	}
@@ -311,7 +306,7 @@
 	} else if ((casmap0 &= casmap1)) {
 		spd_byte = CASDDR[__builtin_ctz(casmap0)];
 	} else {
-		print_emerg("DIMM CAS Latencies not compatible\n");
+		printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
 		post_code(ERROR_DIFF_DIMMS);
 		hcf();
 	}
@@ -466,53 +461,53 @@
 {
 	uint8_t spd_byte;
 
-	banner("sdram_set_spd_register");
+	printk(BIOS_DEBUG, "sdram_set_spd_register\n");
 	post_code(POST_MEM_SETUP);	/* post_70h */
 
 	spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
-	banner("Check DIMM 0");
+	printk(BIOS_DEBUG, "Check DIMM 0\n");
 	/* Check DIMM is not Register and not Buffered DIMMs. */
 	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
-		print_emerg("DIMM0 NOT COMPATIBLE\n");
+		printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");
 		post_code(ERROR_UNSUPPORTED_DIMM);
 		hcf();
 	}
-	banner("Check DIMM 1");
+	printk(BIOS_DEBUG, "Check DIMM 1\n");
 	spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
 	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
-		print_emerg("DIMM1 NOT COMPATIBLE\n");
+		printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");
 		post_code(ERROR_UNSUPPORTED_DIMM);
 		hcf();
 	}
 
 	post_code(POST_MEM_SETUP2);	/* post_72h */
-	banner("Check DDR MAX");
+	printk(BIOS_DEBUG, "Check DDR MAX\n");
 
 	/* Check that the memory is not overclocked. */
 	checkDDRMax();
 
 	/* Size the DIMMS */
 	post_code(POST_MEM_SETUP3);	/* post_73h */
-	banner("AUTOSIZE DIMM 0");
+	printk(BIOS_DEBUG, "AUTOSIZE DIMM 0\n");
 	auto_size_dimm(DIMM0);
 	post_code(POST_MEM_SETUP4);	/* post_74h */
-	banner("AUTOSIZE DIMM 1");
+	printk(BIOS_DEBUG, "AUTOSIZE DIMM 1\n");
 	auto_size_dimm(DIMM1);
 
 	/* Set CAS latency */
-	banner("set cas latency");
+	printk(BIOS_DEBUG, "set cas latency\n");
 	post_code(POST_MEM_SETUP5);	/* post_75h */
 	setCAS();
 
 	/* Set all the other latencies here (tRAS, tRP....) */
-	banner("set all latency");
+	printk(BIOS_DEBUG, "set all latency\n");
 	set_latencies();
 
 	/* Set Extended Mode Registers */
-	banner("set emrs");
+	printk(BIOS_DEBUG, "set emrs\n");
 	set_extended_mode_registers();
 
-	banner("set ref rate");
+	printk(BIOS_DEBUG, "set ref rate\n");
 	/* Set Memory Refresh Rate */
 	set_refresh_rate();
 }
@@ -534,13 +529,13 @@
 	msr = rdmsr(MC_CF1017_DATA);
 	msr.lo = 0x0101;
 	wrmsr(MC_CF1017_DATA, msr);
-	//print_debug("sdram_enable step 2\n");
+	printk(BIOS_DEBUG, "sdram_enable step 2\n");
 
 	/* 3. release CKE mask to enable CKE */
 	msr = rdmsr(MC_CFCLK_DBUG);
 	msr.lo &= ~(0x03 << 8);
 	wrmsr(MC_CFCLK_DBUG, msr);
-	//print_debug("sdram_enable step 3\n");
+	printk(BIOS_DEBUG, "sdram_enable step 3\n");
 
 	/* 4. set and clear REF_TST 16 times, more shouldn't hurt
 	 * why this is before EMRS and MRS ? */
@@ -551,7 +546,7 @@
 		msr.lo &= ~(0x01 << 3);
 		wrmsr(MC_CF07_DATA, msr);
 	}
-	//print_debug("sdram_enable step 4\n");
+	printk(BIOS_DEBUG, "sdram_enable step 4\n");
 
 	/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(MC_CF07_DATA);
@@ -559,7 +554,7 @@
 	wrmsr(MC_CF07_DATA, msr);
 	msr.lo &= ~((0x01 << 28) | 0x01);
 	wrmsr(MC_CF07_DATA, msr);
-	//print_debug("sdram_enable step 6\n");
+	printk(BIOS_DEBUG, "sdram_enable step 6\n");
 
 	/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
 	 * it is documented in LX datasheet */
@@ -569,7 +564,7 @@
 	wrmsr(MC_CF07_DATA, msr);
 	msr.lo &= ~((0x01 << 27) | 0x01);
 	wrmsr(MC_CF07_DATA, msr);
-	//print_debug("sdram_enable step 7\n");
+	printk(BIOS_DEBUG, "sdram_enable step 7\n");
 
 	/* 8. load Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(MC_CF07_DATA);
@@ -577,7 +572,7 @@
 	wrmsr(MC_CF07_DATA, msr);
 	msr.lo &= ~0x01;
 	wrmsr(MC_CF07_DATA, msr);
-	//print_debug("sdram_enable step 8\n");
+	printk(BIOS_DEBUG, "sdram_enable step 8\n");
 
 	/* wait 200 SDCLKs */
 	for (i = 0; i < 200; i++)



From uwe at hermann-uwe.de  Fri Nov  5 01:14:03 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 5 Nov 2010 01:14:03 +0100
Subject: [coreboot] [PATCH] Geode GX2 print(k) V2
In-Reply-To: <201011042335.56685.njacobs8@hetnet.nl>
References: <201011042335.56685.njacobs8@hetnet.nl>
Message-ID: <20101105001403.GT3256@greenwood>

On Thu, Nov 04, 2010 at 11:35:56PM +0100, Nils wrote:
> Remove banner wrapper function and unify print(k).
> 
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

Thanks, 6021.

 
Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Fri Nov  5 01:19:22 2010
From: svn at coreboot.org (repository service)
Date: Fri, 05 Nov 2010 01:19:22 +0100
Subject: [coreboot] [commit] r6022 - in trunk/src/mainboard: amd/rumba
	lippert/frontrunner wyse/s50
Message-ID: <E1PEA1a-0007wR-39@ra.coresystems.de>

Author: uwe
Date: Fri Nov  5 01:19:21 2010
New Revision: 6022
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6022

Log:
GX2: Define the unused DIMM1 to 0xFF to make it obvious it is a bogus value.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/mainboard/amd/rumba/romstage.c
   trunk/src/mainboard/lippert/frontrunner/romstage.c
   trunk/src/mainboard/wyse/s50/romstage.c

Modified: trunk/src/mainboard/amd/rumba/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/rumba/romstage.c	Fri Nov  5 01:13:14 2010	(r6021)
+++ trunk/src/mainboard/amd/rumba/romstage.c	Fri Nov  5 01:19:21 2010	(r6022)
@@ -16,7 +16,7 @@
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
 #define DIMM0 0xA0
-#define DIMM1 0xA2
+#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {

Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/romstage.c	Fri Nov  5 01:13:14 2010	(r6021)
+++ trunk/src/mainboard/lippert/frontrunner/romstage.c	Fri Nov  5 01:19:21 2010	(r6022)
@@ -18,7 +18,7 @@
 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
 
 #define DIMM0 0xA0
-#define DIMM1 0xA2
+#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
 
 static const unsigned char spdbytes[] = {	/* 4x Qimonda HYB25DC512160CF-6 */
 	0xFF, 0xFF,				/* only values used by raminit.c are set */

Modified: trunk/src/mainboard/wyse/s50/romstage.c
==============================================================================
--- trunk/src/mainboard/wyse/s50/romstage.c	Fri Nov  5 01:13:14 2010	(r6021)
+++ trunk/src/mainboard/wyse/s50/romstage.c	Fri Nov  5 01:19:21 2010	(r6022)
@@ -35,7 +35,7 @@
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
 #define DIMM0 0xA0
-#define DIMM1 0xA2
+#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {



From uwe at hermann-uwe.de  Fri Nov  5 01:20:03 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 5 Nov 2010 01:20:03 +0100
Subject: [coreboot] [PATCH] Define unused DIMM1 to 0xFF on Geode GX2
 boards
In-Reply-To: <201011022233.22980.njacobs8@hetnet.nl>
References: <201011022233.22980.njacobs8@hetnet.nl>
Message-ID: <20101105002003.GU3256@greenwood>

On Tue, Nov 02, 2010 at 10:33:22PM +0100, Nils wrote:
> This patch defines the unused DIMM1 to 0xFF to make it obvious it is a bogus 
> value.
> 
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

Thanks, r6022. I added some comments too to make it clearer why it's
0xFF, I hope the comments are correct and make sense.

 
Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Fri Nov  5 01:23:20 2010
From: svn at coreboot.org (repository service)
Date: Fri, 05 Nov 2010 01:23:20 +0100
Subject: [coreboot] [commit] r6023 - in trunk/src: mainboard/amd/rumba
	mainboard/lippert/frontrunner mainboard/wyse/s50 northbridge/amd/gx2
Message-ID: <E1PEA5Q-0005Yd-Kl@ra.coresystems.de>

Author: uwe
Date: Fri Nov  5 01:23:11 2010
New Revision: 6023
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6023

Log:
Add Kconfig CPU speed selection to Geode GX2 boards.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/mainboard/amd/rumba/Kconfig
   trunk/src/mainboard/lippert/frontrunner/Kconfig
   trunk/src/mainboard/wyse/s50/Kconfig
   trunk/src/northbridge/amd/gx2/Kconfig
   trunk/src/northbridge/amd/gx2/pll_reset.c

Modified: trunk/src/mainboard/amd/rumba/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/rumba/Kconfig	Fri Nov  5 01:19:21 2010	(r6022)
+++ trunk/src/mainboard/amd/rumba/Kconfig	Fri Nov  5 01:23:11 2010	(r6023)
@@ -28,6 +28,7 @@
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
 	select POWER_BUTTON_FORCE_ENABLE
+	select GX2_PROCESSOR_MHZ_366
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/lippert/frontrunner/Kconfig
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/Kconfig	Fri Nov  5 01:19:21 2010	(r6022)
+++ trunk/src/mainboard/lippert/frontrunner/Kconfig	Fri Nov  5 01:23:11 2010	(r6023)
@@ -10,6 +10,7 @@
 	select UDELAY_TSC
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
+	select GX2_PROCESSOR_MHZ_366
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/wyse/s50/Kconfig
==============================================================================
--- trunk/src/mainboard/wyse/s50/Kconfig	Fri Nov  5 01:19:21 2010	(r6022)
+++ trunk/src/mainboard/wyse/s50/Kconfig	Fri Nov  5 01:23:11 2010	(r6023)
@@ -29,6 +29,7 @@
 	select PIRQ_ROUTE
 	select BOARD_ROMSIZE_KB_256
 	select POWER_BUTTON_FORCE_DISABLE
+	select GX2_PROCESSOR_MHZ_366
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/northbridge/amd/gx2/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/gx2/Kconfig	Fri Nov  5 01:19:21 2010	(r6022)
+++ trunk/src/northbridge/amd/gx2/Kconfig	Fri Nov  5 01:23:11 2010	(r6023)
@@ -21,9 +21,19 @@
 	bool
 	select GEODE_VSA
 
-# Valid PROCESSOR_MHZ options: 300/366/400 MHz.
-config PROCESSOR_MHZ
+# The GX2_PROCESSOR_MHZ options let you chose the correct GX2 processor
+# speed in the mainboard's Kconfig file.
+config GX2_PROCESSOR_MHZ_300
+	bool
+config GX2_PROCESSOR_MHZ_366
+	bool
+config GX2_PROCESSOR_MHZ_400
+	bool
+
+# Map the config names to an integer (MHz).
+config GX2_PROCESSOR_MHZ
 	int
-	default 366
-	depends on NORTHBRIDGE_AMD_GX2
+	default 300 if GX2_PROCESSOR_MHZ_300
+	default 366 if GX2_PROCESSOR_MHZ_366
+	default 400 if GX2_PROCESSOR_MHZ_400
 

Modified: trunk/src/northbridge/amd/gx2/pll_reset.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/pll_reset.c	Fri Nov  5 01:19:21 2010	(r6022)
+++ trunk/src/northbridge/amd/gx2/pll_reset.c	Fri Nov  5 01:23:11 2010	(r6023)
@@ -71,14 +71,14 @@
 	unsigned SyncBits;			/* store the sync bits in up ebx */
 	unsigned DEFAULT_FBDIV;
 
-	if (CONFIG_PROCESSOR_MHZ == 400) {
+	if (CONFIG_GX2_PROCESSOR_MHZ == 400) {
 		DEFAULT_FBDIV = 24;
-	} else if (CONFIG_PROCESSOR_MHZ == 366) {
+	} else if (CONFIG_GX2_PROCESSOR_MHZ == 366) {
 		DEFAULT_FBDIV = 22;
-	} else if (CONFIG_PROCESSOR_MHZ == 300) {
+	} else if (CONFIG_GX2_PROCESSOR_MHZ == 300) {
 		DEFAULT_FBDIV = 18;
 	} else {
-		printk(BIOS_ERR, "Unsupported PROCESSOR_MHZ setting!\n");
+		printk(BIOS_ERR, "Unsupported GX2_PROCESSOR_MHZ setting!\n");
 		post_code(POST_PLL_CPU_VER_FAIL);
 		__asm__ __volatile__("hlt\n");
 	}
@@ -195,6 +195,6 @@
 static unsigned int GeodeLinkSpeed(void)
 {
 	unsigned geodelinkspeed;
-	geodelinkspeed = ((CONFIG_PROCESSOR_MHZ * DEFAULT_VDIV) / DEFAULT_MDIV);
+	geodelinkspeed = ((CONFIG_GX2_PROCESSOR_MHZ * DEFAULT_VDIV) / DEFAULT_MDIV);
 	return (geodelinkspeed);
 }



From uwe at hermann-uwe.de  Fri Nov  5 01:23:48 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 5 Nov 2010 01:23:48 +0100
Subject: [coreboot] [PATCH] Add cpu speed selection to Geode GX2 boards
In-Reply-To: <201011022233.44143.njacobs8@hetnet.nl>
References: <201011022233.44143.njacobs8@hetnet.nl>
Message-ID: <20101105002348.GV3256@greenwood>

On Tue, Nov 02, 2010 at 10:33:44PM +0100, Nils wrote:
> This patch adds Kconfig cpu speed selection to Geode GX2 boards as requested by 
> Uwe.
> 
> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>

Thanks, r6023.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From uwe at hermann-uwe.de  Fri Nov  5 01:29:52 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 5 Nov 2010 01:29:52 +0100
Subject: [coreboot] [PATCH 0/4] Geode GX2 auto DRAM detect patch V2
In-Reply-To: <201011012028.27545.njacobs8@hetnet.nl>
References: <201011012028.27545.njacobs8@hetnet.nl>
Message-ID: <20101105002952.GW3256@greenwood>

On Mon, Nov 01, 2010 at 08:28:27PM +0100, Nils wrote:
> >Shouldn't there be a "while (1)" around the hlt instruction?
> ?? i don't know should it?
> The code seems to work, but if it is preferred/needed i will add it.

As far as I know the "hlt" instruction on x86 does not really terminally
"halt" the processor, it can be woken up again by certain events (NMI,
debug exceptions, whatever). So usually you only see the "hlt"
instruction in a while(1) loop if you want the code to not ever continue
execution after the "hlt" instruction. But someone please correct me
if I'm wrong.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Fri Nov  5 01:34:15 2010
From: svn at coreboot.org (repository service)
Date: Fri, 05 Nov 2010 01:34:15 +0100
Subject: [coreboot] [commit] r6024 - trunk/util/superiotool
Message-ID: <E1PEAFz-0007Ns-1G@ra.coresystems.de>

Author: uwe
Date: Fri Nov  5 01:34:12 2010
New Revision: 6024
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6024

Log:
Add detection support for the Fintek F81865/F81865-I.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/util/superiotool/fintek.c

Modified: trunk/util/superiotool/fintek.c
==============================================================================
--- trunk/util/superiotool/fintek.c	Fri Nov  5 01:23:11 2010	(r6023)
+++ trunk/util/superiotool/fintek.c	Fri Nov  5 01:34:12 2010	(r6024)
@@ -229,6 +229,8 @@
 			{0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
 			{0x00,NANA,NANA,NANA,NANA,NANA,EOT}},
 		{EOT}}},
+	{0x0407, "F81865F/F-I", {
+		{EOT}}},
 	{EOT}
 };
 



From uwe at hermann-uwe.de  Fri Nov  5 01:34:46 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 5 Nov 2010 01:34:46 +0100
Subject: [coreboot] [PATCH][superiotool]: Add an entry of fintek f81865
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1704411793@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B1704411793@sbjgexmb1.amd.com>
Message-ID: <20101105003446.GX3256@greenwood>

Thanks, r6024.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From peter at stuge.se  Fri Nov  5 01:37:47 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 5 Nov 2010 01:37:47 +0100
Subject: [coreboot] interesting request for serial console over enet
In-Reply-To: <AANLkTi=hwYw__ozW8AOmZ5aMsHiz_H5CX8LUX7Pb7oFx@mail.gmail.com>
References: <AANLkTi=hwYw__ozW8AOmZ5aMsHiz_H5CX8LUX7Pb7oFx@mail.gmail.com>
Message-ID: <20101105003748.10581.qmail@stuge.se>

ron minnich wrote:
> I know that coreboot can now do console over enet; would be neat if
> seabios could provide a path for payloads to use it.

There's a problem; not very many ethernet adapters besides the old
RealTek 8029 (NE2000 PCI clone) have on-chip SRAM reachable via PIO.
:\


//Peter



From scott at notabs.org  Fri Nov  5 03:53:59 2010
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 4 Nov 2010 21:53:59 -0500
Subject: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in
	Win7 (revised)
In-Reply-To: <4CD1D565.4070608@assembler.cz>
References: <C030A2F7944A40AE9FC019041544BB6A@m3a78>
	<4CD1D565.4070608@assembler.cz>
Message-ID: <8BC4DE0287FE4B7DBC9F0598FDB9D57A@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Rudolf Marek
Sent: Wednesday, November 03, 2010 04:34 PM
To: coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7 (revised)

]Hi Scott,
]
]I tried to boot with that on famF CPU and it went well.
]ruiktest:~#
]ruiktest:~# lspci -vvv -s 01:05.0
]
]01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4200] 
](prog-if 00 [VGA controller])
]	Subsystem: ATI Technologies Inc Device 0000
]	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- 
]SERR- FastB2B- DisINTx-
]	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
]<MAbort- >SERR- <PERR- INTx-
]	Latency: 0, Cache Line Size: 64 bytes
]	Interrupt: pin A routed to IRQ 18
]	Region 0: Memory at e8000000 (32-bit, prefetchable) [size=128M]
]	Region 1: I/O ports at 1000 [size=256]
]	Region 2: Memory at f8100000 (32-bit, non-prefetchable) [size=64K]
]	Region 5: Memory at f8000000 (32-bit, non-prefetchable) [size=1M]
]	Expansion ROM at <unassigned> [disabled]
]	Capabilities: [50] Power Management version 3
]		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
]		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
]	Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
]		Address: 0000000000000000  Data: 0000
]	Kernel driver in use: radeon
]
]The BAR seems to be enabled. Btw I tried to boot Win7 but still got only logo 
]animation forever. Not sure what it could be.

Hello Rudolf,

I was able to get the mahogany coreboot to boot Win7 on an ECS A780GM-M3 board
with a family 0Fh processor installed. Here are the steps, starting with trunk:

1) Apply the revised RS780 patch (patch-rs780-2.txt).
2) Apply the Win7 changes (win7-wip-1.txt).
3) Apply the additional attached changes for family 0Fh (win7-mahogany.txt).
4) Revert file ht_wrapper.c. That quick and dirty HT3 change is not good for family 0Fh.

Thanks,
Scott

]I agree that this patch is big improvement. We can fix the MMCONF later.
]
]Thanks,
]Rudolf

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From scott at notabs.org  Fri Nov  5 04:13:07 2010
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 4 Nov 2010 22:13:07 -0500
Subject: [coreboot] [patch] fix unexpacted MTRR setup for UMA memory
In-Reply-To: <4CD1EB23.7000303@assembler.cz>
References: <C6A6796319634D409459A0710CC85FB1@m3a78><4CC0F38C.50806@gmx.net>	<0C5CDCBCD5F74440BB7BE8B8AC46DFB3@m3a78><924C2396-43F5-4B88-B8D0-B3162E264E46@coresystems.de>
	<4CD1EB23.7000303@assembler.cz>
Message-ID: <91C95AAD449B4454A0F9240F95D2A107@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Rudolf Marek
Sent: Wednesday, November 03, 2010 06:07 PM
To: coreboot at coreboot.org
Subject: Re: [coreboot] [patch] fix unexpacted MTRR setup for UMA memory

]Hi,
]
]I just want to tell "me too", so question is we go to direction of claiming less 
]ram_resource as intel do or others.

So far there has been no comments about non-AMD UMA systems. This is one of several
items that need to be resolved before the trunk can support Win7 for AMS UMA systems.

]Is the AMD uma limited to < 4GB?

The RS780 frame buffer can be placed above 4GB. I remember booting a
Tilapia board a while back and finding the frame buffer is above 4GB
by default. A setup option can be used to select above or below.


]Thanks,
]Rudolf




From Zheng.Bao at amd.com  Fri Nov  5 08:19:08 2010
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Fri, 5 Nov 2010 15:19:08 +0800
Subject: [coreboot] [PATCH]: Entry key of fintek superio is 8787 instead of
	87
Message-ID: <DD1CC71B621B004FA76856E5129D6B1704411ABF@sbjgexmb1.amd.com>

According to the description in datasheet of f71889,

"To enable configuration, the entry key 0x87 must be written to
the index port"

"
 -o 4e 87
 -o 4e 87	(enable configuration)
 -o 4e aa	(disable configuration)
"
This piece of text appears in most of the datasheet of fintek superio.
It doesnt say it quite clear, but it seems that the 0x87 should
be written twice. I tried on f81865, which is not in the coreboot tree
yet. If the 0x87 is only written once, you can only R/W the index/data
port once. All the subsequent RW will fail. Writing twice will be ok.

Plus, in the superiotool, the function
enter_conf_mode_winbond_fintek_ite_8787
also write 8787.

The fintek superio chips seem to enable the UART automatically when the
power is on. So I didnt find it failed to access.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>


Index: src/superio/fintek/f71805f/f71805f_early_serial.c
===================================================================
--- src/superio/fintek/f71805f/f71805f_early_serial.c	(revision 6024)
+++ src/superio/fintek/f71805f/f71805f_early_serial.c	(working copy)
@@ -27,6 +27,7 @@
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
Index: src/superio/fintek/f71859/f71859_early_serial.c
===================================================================
--- src/superio/fintek/f71859/f71859_early_serial.c	(revision 6024)
+++ src/superio/fintek/f71859/f71859_early_serial.c	(working copy)
@@ -27,6 +27,7 @@
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
Index: src/superio/fintek/f71889/f71889_early_serial.c
===================================================================
--- src/superio/fintek/f71889/f71889_early_serial.c	(revision 6024)
+++ src/superio/fintek/f71889/f71889_early_serial.c	(working copy)
@@ -26,6 +26,7 @@
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
Index: src/superio/fintek/f71863fg/f71863fg_early_serial.c
===================================================================
--- src/superio/fintek/f71863fg/f71863fg_early_serial.c	(revision 6024)
+++ src/superio/fintek/f71863fg/f71863fg_early_serial.c	(working copy)
@@ -27,6 +27,7 @@
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
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From stefan.reinauer at coresystems.de  Fri Nov  5 08:51:40 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Nov 2010 00:51:40 -0700
Subject: [coreboot] [PATCH]: Entry key of fintek superio is 8787 instead
 of	87
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1704411ABF@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B1704411ABF@sbjgexmb1.amd.com>
Message-ID: <4CD3B78C.6040707@coresystems.de>

On 11/5/10 12:19 AM, Bao, Zheng wrote:
> According to the description in datasheet of f71889,
>
> "To enable configuration, the entry key 0x87 must be written to
> the index port"
>
> "
>  -o 4e 87
>  -o 4e 87	(enable configuration)
>  -o 4e aa	(disable configuration)
> "
> This piece of text appears in most of the datasheet of fintek superio.
> It doesnt say it quite clear, but it seems that the 0x87 should
> be written twice. I tried on f81865, which is not in the coreboot tree
> yet. If the 0x87 is only written once, you can only R/W the index/data
> port once. All the subsequent RW will fail. Writing twice will be ok.
>
> Plus, in the superiotool, the function
> enter_conf_mode_winbond_fintek_ite_8787
> also write 8787.
>
> The fintek superio chips seem to enable the UART automatically when the
> power is on. So I didnt find it failed to access.
>
> Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Stefan Reinauer <stepan at coreboot.org>

Stefan



From svn at coreboot.org  Fri Nov  5 08:59:07 2010
From: svn at coreboot.org (repository service)
Date: Fri, 05 Nov 2010 08:59:07 +0100
Subject: [coreboot] [commit] r6025 - in trunk/src/superio/fintek: f71805f
	f71859 f71863fg f71889
Message-ID: <E1PEHCV-0001SY-1y@ra.coresystems.de>

Author: zbao
Date: Fri Nov  5 08:59:06 2010
New Revision: 6025
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6025

Log:
According to the description in datasheet of f71889,

"To enable configuration, the entry key 0x87 must be written to
the index port"

"
 -o 4e 87
 -o 4e 87	(enable configuration)
 -o 4e aa	(disable configuration)
"
This piece of text appears in most of the datasheet of fintek superio.
It doesnt say it quite clear, but it seems that the 0x87 should
be written twice. I tried on f81865, which is not in the coreboot tree
yet. If the 0x87 is only written once, you can only R/W the index/data
port once. All the subsequent RW will fail. Writing twice will be ok.

Plus, in the superiotool, the function enter_conf_mode_winbond_fintek_ite_8787
also write 8787.

The fintek superio chips seem to enable the UART automatically when the
power is on. So I didnt find it failed to access.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/superio/fintek/f71805f/f71805f_early_serial.c
   trunk/src/superio/fintek/f71859/f71859_early_serial.c
   trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c
   trunk/src/superio/fintek/f71889/f71889_early_serial.c

Modified: trunk/src/superio/fintek/f71805f/f71805f_early_serial.c
==============================================================================
--- trunk/src/superio/fintek/f71805f/f71805f_early_serial.c	Fri Nov  5 01:34:12 2010	(r6024)
+++ trunk/src/superio/fintek/f71805f/f71805f_early_serial.c	Fri Nov  5 08:59:06 2010	(r6025)
@@ -27,6 +27,7 @@
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)

Modified: trunk/src/superio/fintek/f71859/f71859_early_serial.c
==============================================================================
--- trunk/src/superio/fintek/f71859/f71859_early_serial.c	Fri Nov  5 01:34:12 2010	(r6024)
+++ trunk/src/superio/fintek/f71859/f71859_early_serial.c	Fri Nov  5 08:59:06 2010	(r6025)
@@ -27,6 +27,7 @@
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)

Modified: trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c
==============================================================================
--- trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c	Fri Nov  5 01:34:12 2010	(r6024)
+++ trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c	Fri Nov  5 08:59:06 2010	(r6025)
@@ -27,6 +27,7 @@
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)

Modified: trunk/src/superio/fintek/f71889/f71889_early_serial.c
==============================================================================
--- trunk/src/superio/fintek/f71889/f71889_early_serial.c	Fri Nov  5 01:34:12 2010	(r6024)
+++ trunk/src/superio/fintek/f71889/f71889_early_serial.c	Fri Nov  5 08:59:06 2010	(r6025)
@@ -26,6 +26,7 @@
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)



From xcarcelle at proformatique.com  Fri Nov  5 11:00:47 2010
From: xcarcelle at proformatique.com (Xavier Carcelle)
Date: Fri, 5 Nov 2010 11:00:47 +0100 (CET)
Subject: [coreboot] questions on coreboot bootlog w/ EP80579(Truxton
	platform)
Message-ID: <399587453.16126.1288951247804.JavaMail.root@Paperboy>

Hi there, 


I am currently testing coreboot for the Intel EP80579 w/ the Truxton platform w/ DDR2 (not ECC) on the DIMM0 slot of the platform. I am having the following bootlog but don't understand what is the output meaning ? 


Thanks, 


Xavier. 



"coreboot-4.0-r5689 

coreboot-4.0-r5689 50AI 00 
01 51AI 00 
01 52AI 00 
01 53AI 0080 08 08 0e 0a 00 40 00 05 3d 50 00 82 08 00 00 AI 100c 08 38 01 02 00 03 3d 50 50 60 3c 1e 3c 2d 01 AI 2025 37 10 220 
01 55AI 00 
01 56AI 00 
01 57AI 00ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff AI 10ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff AI 20ff ff ff ff 
00 


00 
MHz DDR 
Sc cd` - 25c cd` - 0000000000000201` - c cd` - DR 
ffffffffDRB = 00000000 
TOM = 0000 
TOLM = 0000 
cl = 00 
trc = 7e 
trfc = 00 
tras = 00 
trtp = 40 
twtr = 00 
drt0 = ffffffea 
drt1 = fc700000 
magic = 009a62b1 
mrs = 69020000 
0000T @Q000000000000000000000000000000000010T @Q000000000000000000000000000000000020T @Q000000000000000000000000000000000030T @0 
``c` CS01 
q00000010DDR 
R 
00T @QR 
01T @Q0000T @Q001000000000000000000000000000000010T @Q000000000000000000000000000000000020T @Q0000000000000000000000000000000000 
0000T @Q001000000000000000000000000000000010T @Q000000000000000000000000000000000020T @Q000000000000000000000000000000000030T @S 
00:00.0000: 86 80 20 50 06 00 10 00 01 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00 20: 00 00 00 00" 

-------------- next part --------------
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From svn at coreboot.org  Fri Nov  5 13:44:26 2010
From: svn at coreboot.org (repository service)
Date: Fri, 05 Nov 2010 13:44:26 +0100
Subject: [coreboot] [commit] r6026 - in trunk/src/superio/fintek: f71805f
	f71859 f71863fg f71889
Message-ID: <E1PELec-0007YE-7b@ra.coresystems.de>

Author: uwe
Date: Fri Nov  5 13:44:25 2010
New Revision: 6026
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6026

Log:
Follow-up for r6025, do 0x87 twice in superio.c, too.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/superio/fintek/f71805f/superio.c
   trunk/src/superio/fintek/f71859/superio.c
   trunk/src/superio/fintek/f71863fg/superio.c
   trunk/src/superio/fintek/f71889/superio.c

Modified: trunk/src/superio/fintek/f71805f/superio.c
==============================================================================
--- trunk/src/superio/fintek/f71805f/superio.c	Fri Nov  5 08:59:06 2010	(r6025)
+++ trunk/src/superio/fintek/f71805f/superio.c	Fri Nov  5 13:44:25 2010	(r6026)
@@ -30,6 +30,7 @@
 static void pnp_enter_conf_state(device_t dev)
 {
 	outb(0x87, dev->path.pnp.port);
+	outb(0x87, dev->path.pnp.port);
 }
 
 static void pnp_exit_conf_state(device_t dev)

Modified: trunk/src/superio/fintek/f71859/superio.c
==============================================================================
--- trunk/src/superio/fintek/f71859/superio.c	Fri Nov  5 08:59:06 2010	(r6025)
+++ trunk/src/superio/fintek/f71859/superio.c	Fri Nov  5 13:44:25 2010	(r6026)
@@ -31,6 +31,7 @@
 static void pnp_enter_conf_state(device_t dev)
 {
 	outb(0x87, dev->path.pnp.port);
+	outb(0x87, dev->path.pnp.port);
 }
 
 static void pnp_exit_conf_state(device_t dev)

Modified: trunk/src/superio/fintek/f71863fg/superio.c
==============================================================================
--- trunk/src/superio/fintek/f71863fg/superio.c	Fri Nov  5 08:59:06 2010	(r6025)
+++ trunk/src/superio/fintek/f71863fg/superio.c	Fri Nov  5 13:44:25 2010	(r6026)
@@ -30,6 +30,7 @@
 static void pnp_enter_conf_state(device_t dev)
 {
 	outb(0x87, dev->path.pnp.port);
+	outb(0x87, dev->path.pnp.port);
 }
 
 static void pnp_exit_conf_state(device_t dev)

Modified: trunk/src/superio/fintek/f71889/superio.c
==============================================================================
--- trunk/src/superio/fintek/f71889/superio.c	Fri Nov  5 08:59:06 2010	(r6025)
+++ trunk/src/superio/fintek/f71889/superio.c	Fri Nov  5 13:44:25 2010	(r6026)
@@ -30,6 +30,7 @@
 static void pnp_enter_conf_state(device_t dev)
 {
 	outb(0x87, dev->path.pnp.port);
+	outb(0x87, dev->path.pnp.port);
 }
 
 static void pnp_exit_conf_state(device_t dev)



From svn at coreboot.org  Fri Nov  5 17:17:46 2010
From: svn at coreboot.org (repository service)
Date: Fri, 05 Nov 2010 17:17:46 +0100
Subject: [coreboot] [commit] r6027 - in trunk/src/mainboard: amd/dbm690t
	amd/mahogany amd/mahogany_fam10 amd/tilapia_fam10
	asrock/939a785gmh asus/m4a785-m getac/p470
	gigabyte/ga_2761gxdk gigabyte/ma785gmt gigabyte/ma7...
Message-ID: <E1PEOz4-00071h-G8@ra.coresystems.de>

Author: oxygene
Date: Fri Nov  5 17:17:46 2010
New Revision: 6027
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6027

Log:
Various PIRQ/MPTABLE/ACPI Kconfig fixes.

 - Use HAVE_ACPI_TABLES, HAVE_MP_TABLE, and HAVE_PIRQ_TABLE (instead of
   GENERATE_*) in the board's Kconfig file, as all other boards do.

 - Add missing HAVE_ACPI_TABLES/HAVE_MP_TABLE/HAVE_PIRQ_TABLE to boards
   which have the respective files. The only exception: EPIA-M700 doesn't
   select ACPI, as it doesn't have dsdt.asl. Added a comment that the user
   is supposed to run the 'get_dsdt' script and edit Kconfig afterwards.

 - Fix minor warning/error in
   src/mainboard/msi/ms9652_fam10/acpi_tables.c,
   now that the file is actually used.

 - msi/ms9652_fam10: use #include instead of Include() as we usually do
   now.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/src/mainboard/amd/dbm690t/Kconfig
   trunk/src/mainboard/amd/mahogany/Kconfig
   trunk/src/mainboard/amd/mahogany_fam10/Kconfig
   trunk/src/mainboard/amd/tilapia_fam10/Kconfig
   trunk/src/mainboard/asrock/939a785gmh/Kconfig
   trunk/src/mainboard/asus/m4a785-m/Kconfig
   trunk/src/mainboard/getac/p470/Kconfig
   trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
   trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
   trunk/src/mainboard/gigabyte/ma78gm/Kconfig
   trunk/src/mainboard/ibase/mb899/Kconfig
   trunk/src/mainboard/iei/juki-511p/Kconfig
   trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig
   trunk/src/mainboard/jetway/pa78vm5/Kconfig
   trunk/src/mainboard/kontron/986lcd-m/Kconfig
   trunk/src/mainboard/msi/ms9652_fam10/Kconfig
   trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c
   trunk/src/mainboard/msi/ms9652_fam10/dsdt.asl
   trunk/src/mainboard/via/epia-m700/Kconfig

Modified: trunk/src/mainboard/amd/dbm690t/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/amd/dbm690t/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -10,9 +10,9 @@
 	select SOUTHBRIDGE_AMD_SB600
 	select SUPERIO_ITE_IT8712F
 	select BOARD_HAS_FADT
-	select GENERATE_ACPI_TABLES
-	select GENERATE_MP_TABLE
-	select GENERATE_PIRQ_TABLE
+	select HAVE_ACPI_TABLES
+	select HAVE_MP_TABLE
+	select HAVE_PIRQ_TABLE
 	select HAVE_OPTION_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_BUS_CONFIG

Modified: trunk/src/mainboard/amd/mahogany/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/mahogany/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/amd/mahogany/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -11,9 +11,9 @@
 	select SOUTHBRIDGE_AMD_SB700
 	select SUPERIO_ITE_IT8718F
 	select BOARD_HAS_FADT
-	select GENERATE_ACPI_TABLES
-	select GENERATE_MP_TABLE
-	select GENERATE_PIRQ_TABLE
+	select HAVE_ACPI_TABLES
+	select HAVE_MP_TABLE
+	select HAVE_PIRQ_TABLE
 	select HAVE_OPTION_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_BUS_CONFIG

Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -13,8 +13,8 @@
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
-	select GENERATE_PIRQ_TABLE
-	select GENERATE_MP_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
@@ -22,7 +22,7 @@
 	select LIFT_BSP_APIC_ID
 	select SERIAL_CPU_INIT
 	select AMDMCT
-	select GENERATE_ACPI_TABLES
+	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
 	select ENABLE_APIC_EXT_ID

Modified: trunk/src/mainboard/amd/tilapia_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/amd/tilapia_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -13,8 +13,8 @@
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
-	select GENERATE_PIRQ_TABLE
-	select GENERATE_MP_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
@@ -22,7 +22,7 @@
 	select LIFT_BSP_APIC_ID
 	select SERIAL_CPU_INIT
 	select AMDMCT
-	select GENERATE_ACPI_TABLES
+	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
 	select ENABLE_APIC_EXT_ID

Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/asrock/939a785gmh/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -11,9 +11,9 @@
 	select SOUTHBRIDGE_AMD_SB700
 	select SUPERIO_WINBOND_W83627DHG
 	select BOARD_HAS_FADT
-	select GENERATE_ACPI_TABLES
-	select GENERATE_MP_TABLE
-	select GENERATE_PIRQ_TABLE
+	select HAVE_ACPI_TABLES
+	select HAVE_MP_TABLE
+	select HAVE_PIRQ_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_OPTION_TABLE
 	select HAVE_BUS_CONFIG

Modified: trunk/src/mainboard/asus/m4a785-m/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/asus/m4a785-m/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -13,15 +13,15 @@
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
-	select GENERATE_PIRQ_TABLE
-	select GENERATE_MP_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select LIFT_BSP_APIC_ID
 	select SERIAL_CPU_INIT
 	select AMDMCT
-	select GENERATE_ACPI_TABLES
+	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
 	select ENABLE_APIC_EXT_ID

Modified: trunk/src/mainboard/getac/p470/Kconfig
==============================================================================
--- trunk/src/mainboard/getac/p470/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/getac/p470/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -29,9 +29,9 @@
 	select SUPERIO_SMSC_FDC37N972
 	select SUPERIO_SMSC_SIO10N268
 	select BOARD_HAS_FADT
-	select GENERATE_ACPI_TABLES
-	select GENERATE_PIRQ_TABLE
-	select GENERATE_MP_TABLE
+	select HAVE_ACPI_TABLES
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_SLIC

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -12,6 +12,7 @@
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID

Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -13,8 +13,8 @@
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
-	select GENERATE_PIRQ_TABLE
-	select GENERATE_MP_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
@@ -22,7 +22,7 @@
 	select LIFT_BSP_APIC_ID
 	select SERIAL_CPU_INIT
 	select AMDMCT
-	select GENERATE_ACPI_TABLES
+	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 	select ENABLE_APIC_EXT_ID
 	select TINY_BOOTBLOCK

Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -13,8 +13,8 @@
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
-	select GENERATE_PIRQ_TABLE
-	select GENERATE_MP_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
@@ -22,7 +22,7 @@
 	select LIFT_BSP_APIC_ID
 	select SERIAL_CPU_INIT
 	select AMDMCT
-	select GENERATE_ACPI_TABLES
+	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 	select ENABLE_APIC_EXT_ID
 	select TINY_BOOTBLOCK

Modified: trunk/src/mainboard/ibase/mb899/Kconfig
==============================================================================
--- trunk/src/mainboard/ibase/mb899/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/ibase/mb899/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -9,9 +9,9 @@
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_WINBOND_W83627EHG
 	select BOARD_HAS_FADT
-	select GENERATE_ACPI_TABLES
-	select GENERATE_PIRQ_TABLE
-	select GENERATE_MP_TABLE
+	select HAVE_ACPI_TABLES
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select MMCONF_SUPPORT

Modified: trunk/src/mainboard/iei/juki-511p/Kconfig
==============================================================================
--- trunk/src/mainboard/iei/juki-511p/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/iei/juki-511p/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -27,6 +27,7 @@
 	select SUPERIO_WINBOND_W83977F
 	select ROMCC
 	select PIRQ_ROUTE
+	select HAVE_PIRQ_TABLE
 	select HAVE_OPTION_TABLE
 	select BOARD_ROMSIZE_KB_256
 

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -13,8 +13,8 @@
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
-	select GENERATE_PIRQ_TABLE
-	select GENERATE_MP_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
@@ -22,7 +22,7 @@
 	select LIFT_BSP_APIC_ID
 	select SERIAL_CPU_INIT
 	select AMDMCT
-	select GENERATE_ACPI_TABLES
+	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
 	select ENABLE_APIC_EXT_ID

Modified: trunk/src/mainboard/jetway/pa78vm5/Kconfig
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/jetway/pa78vm5/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -13,8 +13,8 @@
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
-	select GENERATE_PIRQ_TABLE
-	select GENERATE_MP_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
@@ -22,7 +22,7 @@
 	select LIFT_BSP_APIC_ID
 	select SERIAL_CPU_INIT
 	select AMDMCT
-	select GENERATE_ACPI_TABLES
+	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
 	select ENABLE_APIC_EXT_ID

Modified: trunk/src/mainboard/kontron/986lcd-m/Kconfig
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/kontron/986lcd-m/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -9,9 +9,9 @@
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_WINBOND_W83627THG
 	select BOARD_HAS_FADT
-	select GENERATE_ACPI_TABLES
-	select GENERATE_PIRQ_TABLE
-	select GENERATE_MP_TABLE
+	select HAVE_ACPI_TABLES
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select MMCONF_SUPPORT

Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -14,6 +14,7 @@
 	select HAVE_BUS_CONFIG
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
+	select HAVE_ACPI_TABLES
 	select CACHE_AS_RAM
 	select HAVE_OPTION_TABLE
 	select HAVE_HARD_RESET

Modified: trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c	Fri Nov  5 17:17:46 2010	(r6027)
@@ -151,7 +151,7 @@
 	current += dsdt->length;
 	memcpy(dsdt, &AmlCode, dsdt->length);
 	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
-	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
+	dsdt->checksum = acpi_checksum((u8 *)dsdt, dsdt->length);
 	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
 		     dsdt->length);
 	printk(BIOS_DEBUG, "ACPI:     * FADT\n");

Modified: trunk/src/mainboard/msi/ms9652_fam10/dsdt.asl
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/dsdt.asl	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/msi/ms9652_fam10/dsdt.asl	Fri Nov  5 17:17:46 2010	(r6027)
@@ -23,7 +23,7 @@
 
 DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 {
-	Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
+	#include "../../../../src/northbridge/amd/amdk8/amdk8_util.asl"
 
 	/* For now only define 2 power states:
 	 *  - S0 which is fully on

Modified: trunk/src/mainboard/via/epia-m700/Kconfig
==============================================================================
--- trunk/src/mainboard/via/epia-m700/Kconfig	Fri Nov  5 13:44:25 2010	(r6026)
+++ trunk/src/mainboard/via/epia-m700/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
@@ -7,6 +7,10 @@
 	select NORTHBRIDGE_VIA_VX800
 	select SUPERIO_WINBOND_W83697HF
 	select BOARD_HAS_FADT
+	select HAVE_PIRQ_TABLE
+	# Note: For ACPI, you need to use the 'get_dsdt' script and uncomment
+	# the "select HAVE_ACPI_TABLES" line below.
+	# select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO



From marcj303 at gmail.com  Fri Nov  5 17:21:28 2010
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 5 Nov 2010 10:21:28 -0600
Subject: [coreboot] build questions
In-Reply-To: <AANLkTikwoZjV+xcnBf_gHLbog1YRjQfLPpph68Oa-BZv@mail.gmail.com>
References: <AANLkTikwoZjV+xcnBf_gHLbog1YRjQfLPpph68Oa-BZv@mail.gmail.com>
Message-ID: <AANLkTimCeNBmtzRMLWN8y8-V6UM_q3MQis1MULjwzoog@mail.gmail.com>

On Sun, Oct 31, 2010 at 3:04 PM, Flemming Richter Mikkelsen
<quatrox at member.fsf.org> wrote:
> Hello.
>
> Today I tried to build coreboot for the very first time.
> I discovered that the debug configs caused some
> harmless warnings of the type "referenced but not used".
>
> Also, I tried scan-build. ?I never tried this before, and
> therefore I don't know it limitations. ?A make generated
> a list of 60 bugs. ?Not all of them are real bugs though.
>
> It looks like it found that we use math operation on a
> uninitialized value:
>
> File: ? northbridge/amd/amdfam10/../amdmct/mct/mctndi_d.c
> Location: ? ? ? line 98, column 6
> Description: ? ?The left expression of the compound assignment is an
> uninitialized value. The computed value will also be garbage
>
> DctSelBaseOffset -= Base;
>
> Anyway, the computed value is never used.
>
> Would it make sense to remove unused variables?
> If so, I can try to create a few patches. ?I think scan-build
> is almost useless when it generate a list of 60 "bugs".
>

Hi and welcome to coreboot!

We are always interested in getting more people submitting patches.
Please send yours. We will do our best to review and commit them.

Regard,
Marc

-- 
http://se-eng.com



From marcj303 at gmail.com  Fri Nov  5 17:27:22 2010
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 5 Nov 2010 10:27:22 -0600
Subject: [coreboot] MCP55 Mac Address copying/change
In-Reply-To: <201011041855.28624.harald.gutmann@gmx.net>
References: <201011041855.28624.harald.gutmann@gmx.net>
Message-ID: <AANLkTimRq6LASAqYXhxQjXjCC8h0pPW+c=qtyqLZWHRJ@mail.gmail.com>

On Thu, Nov 4, 2010 at 11:55 AM, Harald Gutmann <harald.gutmann at gmx.net> wrote:
> Hello!
>
> Yesterday I tried coreboot again, and it worked fine so far.
>
> But I faced a nasty problem, like the last time I tried it with the MAC
> address on MCP55. This is nothing serious as you can change it by editing the
> romcache.inc from the southbridge, but it's nasty.
>
> I was thinking about fixing this in a decent way. I'd love to see a KConfig
> value to enter in the configure process to get this done, or even to copy the
> mac address of the board.
>
> As of now the MAC is stored in the romcache.inc file of the southbridge, and as
> far as I guess, this value is read in the mcp55_nic.c and used. There is as of
> now in the bugtracker a script to apply the new mac after compiling the image,
> but I think this is not a really good solution.
>
> If my guess is right, readout from romcache.inc and usage in mcp55_nic.c it
> should be possible to solve this via ?KConfig, and not read the value from the
> romcache.inc, but store it a config value and take this value. Possibly with a
> fallback on the romcache.inc value.
>
> My questions on this suggestion are:
> Would there be any good reason not to do it that way?
> Is my guess right? ?(Until now I didn't look that careful into the code of
> mcp55_nic.c.)
>
> If my guess is right, and there is no problem to do as suggested, I'd prepare
> a patch for it.
> Any comments are welcome.
>

Hi Harald,

It seems like a Kconfig option would be a good idea. It can alway
default to a reasonable value. Another idea I have seen floating
around is to have the value stored in cbfs. Then it could be updated
post coreboot build.

Marc


-- 
http://se-eng.com



From patrick at georgi-clan.de  Fri Nov  5 17:40:04 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 05 Nov 2010 17:40:04 +0100
Subject: [coreboot] MCP55 Mac Address copying/change
In-Reply-To: <AANLkTimRq6LASAqYXhxQjXjCC8h0pPW+c=qtyqLZWHRJ@mail.gmail.com>
References: <201011041855.28624.harald.gutmann@gmx.net>
	<AANLkTimRq6LASAqYXhxQjXjCC8h0pPW+c=qtyqLZWHRJ@mail.gmail.com>
Message-ID: <4CD43364.6060000@georgi-clan.de>

Am 05.11.2010 17:27, schrieb Marc Jones:
> It seems like a Kconfig option would be a good idea. It can alway
> default to a reasonable value. Another idea I have seen floating
> around is to have the value stored in cbfs. Then it could be updated
> post coreboot build.
Not sure, but don't some chipsets handle MAC addresses via the romstrap
area? If so, kconfig might be a better place (for all boards), so the
MAC can be compiled into the romstrap as part of the build process.

The only question is the format the MAC should be in.
The Makefile could rewrite 1:23:45:67:89:ab to a set of #defines (MAC1,
.., MAC6 with a byte each?), so whatever the romstrap format for MAC
addresses is could be modelled in code.


Patrick



From jakllsch at kollasch.net  Fri Nov  5 17:48:43 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Fri, 5 Nov 2010 16:48:43 +0000
Subject: [coreboot] MCP55 Mac Address copying/change
In-Reply-To: <201011041855.28624.harald.gutmann@gmx.net>
References: <201011041855.28624.harald.gutmann@gmx.net>
Message-ID: <20101105164843.GD25395@tarantulon.kollasch.net>

On Thu, Nov 04, 2010 at 06:55:28PM +0100, Harald Gutmann wrote:
> Hello!
> 
> Yesterday I tried coreboot again, and it worked fine so far.
> 
> But I faced a nasty problem, like the last time I tried it with the MAC 
> address on MCP55. This is nothing serious as you can change it by editing the 
> romcache.inc from the southbridge, but it's nasty.
> 
> I was thinking about fixing this in a decent way. I'd love to see a KConfig 
> value to enter in the configure process to get this done, or even to copy the 
> mac address of the board.

Look at the romstrap of the vendor-provided firmware update image for
a nvidia board.  You'll find it doesn't contain your board's address.

IMO this issue would be best solved in the vicinity of flashrom.

It's trivial to follow the romstrap pointers and copy over
the address.

Attached is a utility to do just that.

	Jonathan Kollasch
-------------- next part --------------
/*
 * Copyright (c) 2010 Jonathan A. Kollasch
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * transfer UUID/MAC address in nvidia romstrap
 */

#include <stdint.h>
#include <stdio.h>

#ifdef __NetBSD__
#include <sys/endian.h>
#else
#warning assuming LE host
#define le32toh(x) (x)
#endif

FILE *srcrom;
FILE *dstrom;
uint32_t srcbase;
uint32_t dstbase;
uint32_t srcrsp;
uint32_t dstrsp;

uint8_t uuid[16];

int
get_rom(FILE *f, uint32_t *v)
{
	uint32_t tmp;
	size_t ret;

	ret = fread(&tmp, sizeof(tmp), 1, f) != 1;

	if (ret == 0 && v != NULL)
		*v = tmp;

	return ret;
}

int
main(int argc, char *argv[])
{
	uint32_t srctmp;
	uint32_t dsttmp;

	if (argc < 3)
		return 1;

	srcrom = fopen(argv[1], "r");
	if (srcrom == NULL)
		return 1;

	dstrom = fopen(argv[2], "r+");
	if (dstrom == NULL)
		return 1;

	/* seek to the romstrap pointer, find offset of ROM image */
	fseek(srcrom, -0x20, SEEK_END);
	srcbase = 0x100000000ULL - (ftell(srcrom) + 0x20);
	//printf("%x\n", srcbase);

	fseek(dstrom, -0x20, SEEK_END);
	dstbase = 0x100000000ULL - (ftell(dstrom) + 0x20);
	//printf("%x\n", dstbase);

	/* read romstrap pointer */
	if (get_rom(srcrom, &srcrsp))
		return 1;
	srcrsp = le32toh(srcrsp);
	//printf("srcrsp %x\n", srcrsp);

	if (get_rom(dstrom, &dstrsp))
		return 1;
	dstrsp = le32toh(dstrsp);
	//printf("dstrsp %x\n", dstrsp);

	/* move to romstrap table */
	fseek(srcrom, srcrsp - srcbase, SEEK_SET);
	fseek(dstrom, dstrsp - dstbase, SEEK_SET);

	/* check for romstrap signature */
	if (get_rom(srcrom, &srctmp))
		return 1;
	srctmp = le32toh(srctmp);
	if (srctmp != 0x2b16d065)
		return 1;

	if (get_rom(dstrom, &dsttmp))
		return 1;
	dsttmp = le32toh(dsttmp);
	if (dsttmp != 0x2b16d065)
		return 1;

	/* move to next pointer */
	fseek(srcrom, srcrsp - srcbase + 0x0c, SEEK_SET);
	fseek(dstrom, dstrsp - dstbase + 0x0c, SEEK_SET);

	/* read pointer */
	if (get_rom(srcrom, &srctmp))
		return 1;
	srctmp = le32toh(srctmp);
	if (srctmp != (srcrsp + 0x10)) {
		//printf("source list not at usual location\n");
	}

	if (get_rom(dstrom, &dsttmp))
		return 1;
	dsttmp = le32toh(dsttmp);
	if (dsttmp != (dstrsp + 0x10)) {
		//printf("dest list not at usual location\n");
	}
	// /* follow pointer */
	//fseek(srcrom, srctmp - srcbase, SEEK_SET);
	//fseek(dstrom, dsttmp - dstbase, SEEK_SET);

	//printf("sll %x\n", srctmp);
	//printf("dll %x\n", dsttmp);

	/* move to beginning of MAC/UUID */
	fseek(srcrom, srctmp - srcbase + 0x20, SEEK_SET);
	fseek(dstrom, dsttmp - dstbase + 0x20, SEEK_SET);

	/* copy */
	if (fread(uuid, sizeof(uuid), 1, srcrom) != 1)
		return 1;
	if (fwrite(uuid, sizeof(uuid), 1, dstrom) != 1)
		return 1;

	fclose(srcrom);
	fclose(dstrom);

	printf("copied address %02x:%02x:%02x:%02x:%02x:%02x\n", uuid[5], uuid[4], uuid[3], uuid[2], uuid[1], uuid[0]);

	return 0;
}

From dustin.harrison at sutus.com  Fri Nov  5 17:50:24 2010
From: dustin.harrison at sutus.com (Dustin Harrison)
Date: Fri, 05 Nov 2010 09:50:24 -0700
Subject: [coreboot] questions on coreboot bootlog w/
	EP80579(Truxton	platform)
In-Reply-To: <399587453.16126.1288951247804.JavaMail.root@Paperboy>
References: <399587453.16126.1288951247804.JavaMail.root@Paperboy>
Message-ID: <4CD435D0.6030608@sutus.com>

Hi Xavier,

I have never seen that kind of output when using Truxton.  All I can 
suggest is to make sure your serial settings are correct and double 
check any modifications you may have made to the coreboot source.

Note though, trunk does not support non-ECC RAM.  The raminit_ep80579.c 
code will refuse to boot if it detects non-ECC RAM.

Dustin

On 05/11/2010 3:00 AM, Xavier Carcelle wrote:
> Hi there,
>
> I am currently testing coreboot for the Intel EP80579 w/ the Truxton 
> platform w/ DDR2 (not ECC) on the DIMM0 slot of the platform. I am 
> having the following bootlog but don't understand what is the output 
> meaning ?
>
> Thanks,
>
> Xavier.
>
> "coreboot-4.0-r5689
> coreboot-4.0-r5689 50AI 00
> 01 51AI 00
> 01 52AI 00
> 01 53AI 0080 08 08 0e 0a 00 40 00 05 3d 50 00 82 08 00 00 AI 100c 08 
> 38 01 02 00 03 3d 50 50 60 3c 1e 3c 2d 01 AI 2025 37 10 220
> 01 55AI 00
> 01 56AI 00
> 01 57AI 00ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff AI 10ff ff 
> ff ff ff ff ff ff ff ff ff ff ff ff ff ff AI 20ff ff ff ff
> 00
>
> 00
>  MHz DDR
> Sc cd` - 25c cd` - 0000000000000201` - c cd` - DR
> ffffffffDRB = 00000000
> TOM = 0000
> TOLM = 0000
> cl = 00
> trc = 7e
> trfc = 00
> tras = 00
> trtp = 40
> twtr = 00
> drt0 = ffffffea
> drt1 = fc700000
> magic = 009a62b1
> mrs = 69020000
> 0000T @Q000000000000000000000000000000000010T 
> @Q000000000000000000000000000000000020T 
> @Q000000000000000000000000000000000030T @0
> ``c` CS01
> q00000010DDR
> R
> 00T @QR
> 01T @Q0000T @Q001000000000000000000000000000000010T 
> @Q000000000000000000000000000000000020T 
> @Q0000000000000000000000000000000000
> 0000T @Q001000000000000000000000000000000010T 
> @Q000000000000000000000000000000000020T 
> @Q000000000000000000000000000000000030T @S
> 00:00.0000: 86 80 20 50 06 00 10 00 01 00 00 06 00 00 80 00 10: 00 00 
> 00 00 00 00 00 90 00 00 00 00 00 00 00 00 20: 00 00 00 00"
>
>
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From patrick at georgi-clan.de  Fri Nov  5 19:18:34 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 05 Nov 2010 19:18:34 +0100
Subject: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig
Message-ID: <4CD44A7A.2040606@georgi-clan.de>

Hi,
see patch. It might be possible to find a better place to this variable
(are "qrank dimms" really a per-board thing?), but for now this should
provide absolutely equivalent to the romstage.c defines.

Move QRANK_DIMM_SUPPORT to Kconfig, removing it from romstage.c

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
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From peter at stuge.se  Fri Nov  5 19:20:59 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 5 Nov 2010 19:20:59 +0100
Subject: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig
In-Reply-To: <4CD44A7A.2040606@georgi-clan.de>
References: <4CD44A7A.2040606@georgi-clan.de>
Message-ID: <20101105182059.29522.qmail@stuge.se>

Patrick Georgi wrote:
> (are "qrank dimms" really a per-board thing?)

Which boards do not have the variable set?


//Peter



From patrick at georgi-clan.de  Fri Nov  5 19:27:12 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 05 Nov 2010 19:27:12 +0100
Subject: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig
In-Reply-To: <20101105182059.29522.qmail@stuge.se>
References: <4CD44A7A.2040606@georgi-clan.de>
	<20101105182059.29522.qmail@stuge.se>
Message-ID: <4CD44C80.1070903@georgi-clan.de>

Am 05.11.2010 19:20, schrieb Peter Stuge:
> Patrick Georgi wrote:
>> (are "qrank dimms" really a per-board thing?)
> 
> Which boards do not have the variable set?
About 30, I think. I only did a grep .. | wc -l comparison:

$ grep NORTHBRIDGE_AMD_AMDK8 src/mainboard/*/*/Kconfig |wc -l
86

So 86 boards are eligible for that option.

$ svn st |grep romstage.c |wc -l
63

63 boards have that option dropped (the patch is the only change in that
tree).

So there are 23 boards that do not set it.


Patrick



From scott at notabs.org  Fri Nov  5 19:28:59 2010
From: scott at notabs.org (Scott Duplichan)
Date: Fri, 5 Nov 2010 13:28:59 -0500
Subject: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig
In-Reply-To: <20101105182059.29522.qmail@stuge.se>
References: <4CD44A7A.2040606@georgi-clan.de>
	<20101105182059.29522.qmail@stuge.se>
Message-ID: <0694BE6C2D1140F18B56EF577867960E@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Peter Stuge
Sent: Friday, November 05, 2010 01:21 PM
To: coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig

]Patrick Georgi wrote:
]> (are "qrank dimms" really a per-board thing?)
]
]Which boards do not have the variable set?

I am no quad rank dimm expert, but I think few boards support them. One is Serengeti
Cheetah. I remember asking why one processor socket has 4 dimm slots and another 8.
I was told it was for quad rank dimm testing. The chip selects for two normal dimm sockets
are combined and routed to a quad rank socket, if I remember correctly. I don't even
have any quad ranked dimms to test with. I think they are rare.

Thanks,
Scott


]//Peter




From ward at gnu.org  Fri Nov  5 19:41:55 2010
From: ward at gnu.org (Ward Vandewege)
Date: Fri, 5 Nov 2010 14:41:55 -0400
Subject: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig
In-Reply-To: <0694BE6C2D1140F18B56EF577867960E@m3a78>
References: <4CD44A7A.2040606@georgi-clan.de>
	<20101105182059.29522.qmail@stuge.se>
	<0694BE6C2D1140F18B56EF577867960E@m3a78>
Message-ID: <20101105184155.GA1111@countzero.vandewege.net>

On Fri, Nov 05, 2010 at 01:28:59PM -0500, Scott Duplichan wrote:
> I am no quad rank dimm expert, but I think few boards support them. One is Serengeti
> Cheetah. I remember asking why one processor socket has 4 dimm slots and another 8.
> I was told it was for quad rank dimm testing. The chip selects for two normal dimm sockets
> are combined and routed to a quad rank socket, if I remember correctly. I don't even
> have any quad ranked dimms to test with. I think they are rare.

Actually, they are not *that* rare, since they are readily available:

  http://www.newegg.com/Product/ProductList.aspx?Submit=ENE&DEPA=0&Order=BESTMATCH&Description=ddr3+quad+rank&x=0&y=0

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From scott at notabs.org  Fri Nov  5 19:58:26 2010
From: scott at notabs.org (Scott Duplichan)
Date: Fri, 5 Nov 2010 13:58:26 -0500
Subject: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig
In-Reply-To: <20101105184155.GA1111@countzero.vandewege.net>
References: <4CD44A7A.2040606@georgi-clan.de>
	<20101105182059.29522.qmail@stuge.se>
	<0694BE6C2D1140F18B56EF577867960E@m3a78>
	<20101105184155.GA1111@countzero.vandewege.net>
Message-ID: <5D9F70E29E3944958F0A7D9B528928DA@m3a78>

-----Original Message-----
From: Ward Vandewege [mailto:ward at gnu.org] 
Sent: Friday, November 05, 2010 01:42 PM
To: Scott Duplichan
Cc: 'Peter Stuge'; coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig

]On Fri, Nov 05, 2010 at 01:28:59PM -0500, Scott Duplichan wrote:
]> I am no quad rank dimm expert, but I think few boards support them. One is Serengeti
]> Cheetah. I remember asking why one processor socket has 4 dimm slots and another 8.
]> I was told it was for quad rank dimm testing. The chip selects for two normal dimm sockets
]> are combined and routed to a quad rank socket, if I remember correctly. I don't even
]> have any quad ranked dimms to test with. I think they are rare.
]
]Actually, they are not *that* rare, since they are readily available:
]
]  ]http://www.newegg.com/Product/ProductList.aspx?Submit=ENE&DEPA=0&Order=BESTMATCH&Description=ddr3]+quad+rank&x=0&y=0

Sure enough. And not a bad price (per MB), either. Thanks for pointing them out.

Though I would question the maturity of coreboot support for registered
DDR3 in general, and specifically for 1333 speed or quad rank. I believe
these were perfected internally at AMD only recently. How well has coreboot
been tested with various speeds of registered DDR3? There is a lot more
complexity in the memory init code when registered DIMMs of any rank count
are used. And there is still the question of what boards supported by coreboot
really have hardware support for quadrank. I would hate to mislead someone
into buying a system loaded with registered memory with the idea of running
coreboot, unless it is known to work.

Thanks,
Scott

]-- 
]Ward Vandewege <ward at fsf.org>
]Free Software Foundation - Senior Systems Administrator




From patrick at georgi-clan.de  Fri Nov  5 20:05:41 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 05 Nov 2010 20:05:41 +0100
Subject: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig
In-Reply-To: <5D9F70E29E3944958F0A7D9B528928DA@m3a78>
References: <4CD44A7A.2040606@georgi-clan.de>	<20101105182059.29522.qmail@stuge.se>	<0694BE6C2D1140F18B56EF577867960E@m3a78>	<20101105184155.GA1111@countzero.vandewege.net>
	<5D9F70E29E3944958F0A7D9B528928DA@m3a78>
Message-ID: <4CD45585.4070704@georgi-clan.de>

Am 05.11.2010 19:58, schrieb Scott Duplichan:
> really have hardware support for quadrank. I would hate to mislead someone
> into buying a system loaded with registered memory with the idea of running
> coreboot, unless it is known to work.
I think (and hope) that I didn't mark any board as quad rank capable
that wasn't marked that way before, but I can't tell if the original
options are set correctly.

In this regard, the tree with this patch is as good as without.


Patrick



From patrick at georgi-clan.de  Fri Nov  5 20:11:28 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 05 Nov 2010 20:11:28 +0100
Subject: [coreboot] Questions about more AMD related flags
Message-ID: <4CD456E0.1030305@georgi-clan.de>

Hi,

while I opened that can of worms over with QRANK_DIMM_SUPPORT, and
people are listening ;-), let me widen the debate some more:

SET_NB_CFG_54:
1. It's used in two places (dualcore and quadcore AMD code)
2. There, it's set active if undeclared before
3. All other declarations set this active

Any reason to keep this variable at all? If yes, I'll move it to
Kconfig, otherwise I'll just drop it.

and
SET_FIDVID*:
These have _very_ weird behaviour, being set to some defaults in the two
init_cpus.c (and fidvid.c seems to expect to be included after that
one?), and some other settings somewhere else.
I tried to untangle that while moving to Kconfig, but didn't quite
succeed, so is here anyone who knows which defaults (or dependencies)
are correct for each of the following? So far I have:

For K8:
+config SET_FIDVID
+       bool
+       default y if K8_REV_F_SUPPORT
+       default n
+
+config SET_FIDVID_CORE0_ONLY
+       bool
+       default y
+       depends on SET_FIDVID
+
+config SET_FIDVID_CORE_RANGE
+       bool
+       default n
+       depends on SET_FIDVID
+
+config SET_FIDVID_ONE_BY_ONE
+       bool
+       default y
+       depends on SET_FIDVID
+
+config SET_FIDVID_DEBUG
+       bool
+       default n
+       depends on SET_FIDVID
+
+config SET_FIDVID_STORE_AP_APICID_AT_FIRST
+       bool
+       default y
+       depends on SET_FIDVID

For Fam10h:
+config SET_FIDVID
+       bool
+       default y
+
+config SET_FIDVID_CORE0_ONLY
+       bool
+       default n
+       depends on SET_FIDVID
+
+config SET_FIDVID_CORE_RANGE
+       bool
+       default n
+       depends on SET_FIDVID
+
+config SET_FIDVID_DEBUG
+       bool
+       default y
+       depends on SET_FIDVID
+
+config SET_FIDVID_STORE_AP_APICID_AT_FIRST
+       bool
+       default y
+       depends on SET_FIDVID


Corrections welcome

Thanks,
Patrick



From mylesgw at gmail.com  Fri Nov  5 20:15:15 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 5 Nov 2010 13:15:15 -0600
Subject: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig
In-Reply-To: <4CD45585.4070704@georgi-clan.de>
References: <4CD44A7A.2040606@georgi-clan.de>	<20101105182059.29522.qmail@stuge.se>	<0694BE6C2D1140F18B56EF577867960E@m3a78>	<20101105184155.GA1111@countzero.vandewege.net><5D9F70E29E3944958F0A7D9B528928DA@m3a78>
	<4CD45585.4070704@georgi-clan.de>
Message-ID: <AE49FBFAEF954C62BD6F0D5267B78465@chimp>


> Am 05.11.2010 19:58, schrieb Scott Duplichan:
> > really have hardware support for quadrank. I would hate to mislead
> someone
> > into buying a system loaded with registered memory with the idea of
> running
> > coreboot, unless it is known to work.
> I think (and hope) that I didn't mark any board as quad rank capable
> that wasn't marked that way before, but I can't tell if the original
> options are set correctly.
> 
> In this regard, the tree with this patch is as good as without.
Agreed.

Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles




From svn at coreboot.org  Fri Nov  5 23:59:50 2010
From: svn at coreboot.org (repository service)
Date: Fri, 05 Nov 2010 23:59:50 +0100
Subject: [coreboot] [commit] r6028 - in trunk/src: mainboard/amd/dbm690t
	mainboard/amd/mahogany mainboard/amd/mahogany_fam10
	mainboard/amd/pistachio mainboard/amd/serengeti_cheetah
	mainboard/amd/serengeti_cheetah_fam1...
Message-ID: <E1PEVGA-0004uL-MR@ra.coresystems.de>

Author: oxygene
Date: Fri Nov  5 23:59:49 2010
New Revision: 6028
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6028

Log:
Move QRANK_DIMM_SUPPORT to Kconfig, removing it from romstage.c

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/mainboard/amd/dbm690t/Kconfig
   trunk/src/mainboard/amd/dbm690t/romstage.c
   trunk/src/mainboard/amd/mahogany/Kconfig
   trunk/src/mainboard/amd/mahogany/romstage.c
   trunk/src/mainboard/amd/mahogany_fam10/Kconfig
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/pistachio/Kconfig
   trunk/src/mainboard/amd/pistachio/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/Kconfig
   trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
   trunk/src/mainboard/amd/tilapia_fam10/Kconfig
   trunk/src/mainboard/amd/tilapia_fam10/romstage.c
   trunk/src/mainboard/arima/hdama/Kconfig
   trunk/src/mainboard/arima/hdama/romstage.c
   trunk/src/mainboard/asrock/939a785gmh/Kconfig
   trunk/src/mainboard/asrock/939a785gmh/romstage.c
   trunk/src/mainboard/asus/a8n_e/Kconfig
   trunk/src/mainboard/asus/a8n_e/romstage.c
   trunk/src/mainboard/asus/a8v-e_se/Kconfig
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/asus/m2v-mx_se/Kconfig
   trunk/src/mainboard/asus/m2v-mx_se/romstage.c
   trunk/src/mainboard/asus/m4a785-m/Kconfig
   trunk/src/mainboard/asus/m4a785-m/romstage.c
   trunk/src/mainboard/broadcom/blast/Kconfig
   trunk/src/mainboard/broadcom/blast/romstage.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
   trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
   trunk/src/mainboard/gigabyte/m57sli/Kconfig
   trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c
   trunk/src/mainboard/gigabyte/m57sli/romstage.c
   trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
   trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
   trunk/src/mainboard/gigabyte/ma78gm/Kconfig
   trunk/src/mainboard/gigabyte/ma78gm/romstage.c
   trunk/src/mainboard/hp/dl145_g1/Kconfig
   trunk/src/mainboard/hp/dl145_g1/romstage.c
   trunk/src/mainboard/hp/dl145_g3/Kconfig
   trunk/src/mainboard/hp/dl145_g3/romstage.c
   trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig
   trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
   trunk/src/mainboard/ibm/e325/Kconfig
   trunk/src/mainboard/ibm/e325/romstage.c
   trunk/src/mainboard/ibm/e326/Kconfig
   trunk/src/mainboard/ibm/e326/romstage.c
   trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig
   trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
   trunk/src/mainboard/iwill/dk8_htx/Kconfig
   trunk/src/mainboard/iwill/dk8_htx/romstage.c
   trunk/src/mainboard/iwill/dk8s2/Kconfig
   trunk/src/mainboard/iwill/dk8s2/romstage.c
   trunk/src/mainboard/iwill/dk8x/Kconfig
   trunk/src/mainboard/iwill/dk8x/romstage.c
   trunk/src/mainboard/jetway/pa78vm5/Kconfig
   trunk/src/mainboard/jetway/pa78vm5/romstage.c
   trunk/src/mainboard/kontron/kt690/Kconfig
   trunk/src/mainboard/kontron/kt690/romstage.c
   trunk/src/mainboard/msi/ms7135/Kconfig
   trunk/src/mainboard/msi/ms7135/romstage.c
   trunk/src/mainboard/msi/ms7260/Kconfig
   trunk/src/mainboard/msi/ms7260/ap_romstage.c
   trunk/src/mainboard/msi/ms7260/romstage.c
   trunk/src/mainboard/msi/ms9185/Kconfig
   trunk/src/mainboard/msi/ms9185/romstage.c
   trunk/src/mainboard/msi/ms9282/Kconfig
   trunk/src/mainboard/msi/ms9282/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/Kconfig
   trunk/src/mainboard/msi/ms9652_fam10/romstage.c
   trunk/src/mainboard/newisys/khepri/Kconfig
   trunk/src/mainboard/newisys/khepri/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
   trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
   trunk/src/mainboard/sunw/ultra40/Kconfig
   trunk/src/mainboard/sunw/ultra40/romstage.c
   trunk/src/mainboard/supermicro/h8dme/Kconfig
   trunk/src/mainboard/supermicro/h8dme/ap_romstage.c
   trunk/src/mainboard/supermicro/h8dme/romstage.c
   trunk/src/mainboard/supermicro/h8dmr/Kconfig
   trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c
   trunk/src/mainboard/supermicro/h8dmr/romstage.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
   trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig
   trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
   trunk/src/mainboard/technexion/tim5690/Kconfig
   trunk/src/mainboard/technexion/tim5690/romstage.c
   trunk/src/mainboard/technexion/tim8690/Kconfig
   trunk/src/mainboard/technexion/tim8690/romstage.c
   trunk/src/mainboard/tyan/s2875/Kconfig
   trunk/src/mainboard/tyan/s2875/romstage.c
   trunk/src/mainboard/tyan/s2880/Kconfig
   trunk/src/mainboard/tyan/s2880/romstage.c
   trunk/src/mainboard/tyan/s2881/Kconfig
   trunk/src/mainboard/tyan/s2881/romstage.c
   trunk/src/mainboard/tyan/s2882/Kconfig
   trunk/src/mainboard/tyan/s2882/romstage.c
   trunk/src/mainboard/tyan/s2885/Kconfig
   trunk/src/mainboard/tyan/s2885/romstage.c
   trunk/src/mainboard/tyan/s2891/Kconfig
   trunk/src/mainboard/tyan/s2891/romstage.c
   trunk/src/mainboard/tyan/s2892/Kconfig
   trunk/src/mainboard/tyan/s2892/romstage.c
   trunk/src/mainboard/tyan/s2895/Kconfig
   trunk/src/mainboard/tyan/s2895/romstage.c
   trunk/src/mainboard/tyan/s2912/Kconfig
   trunk/src/mainboard/tyan/s2912/ap_romstage.c
   trunk/src/mainboard/tyan/s2912/romstage.c
   trunk/src/mainboard/tyan/s2912_fam10/Kconfig
   trunk/src/mainboard/tyan/s2912_fam10/romstage.c
   trunk/src/mainboard/tyan/s4880/Kconfig
   trunk/src/mainboard/tyan/s4880/romstage.c
   trunk/src/mainboard/tyan/s4882/Kconfig
   trunk/src/mainboard/tyan/s4882/romstage.c
   trunk/src/northbridge/amd/amdk8/Kconfig
   trunk/src/northbridge/amd/amdk8/raminit.c
   trunk/src/northbridge/amd/amdk8/raminit_f.c

Modified: trunk/src/mainboard/amd/dbm690t/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/dbm690t/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,6 +21,7 @@
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/dbm690t/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -18,7 +18,6 @@
  */
 
 #define SET_FIDVID 1
-#define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/amd/mahogany/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/mahogany/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/mahogany/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,6 +24,7 @@
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
 	select GFXUMA
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/mahogany/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -18,7 +18,6 @@
  */
 
 #define SET_FIDVID 1
-#define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -28,6 +28,7 @@
 	select ENABLE_APIC_EXT_ID
 	select TINY_BOOTBLOCK
 	select GFXUMA
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,7 +24,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0

Modified: trunk/src/mainboard/amd/pistachio/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/pistachio/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/pistachio/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,6 +21,7 @@
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/amd/pistachio/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/pistachio/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -18,7 +18,6 @@
  */
 
 #define SET_FIDVID 1
-#define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/amd/serengeti_cheetah/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/serengeti_cheetah/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,6 +25,7 @@
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -4,7 +4,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 

Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,7 +1,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -26,6 +26,7 @@
 	select ENABLE_APIC_EXT_ID
 	select LIFT_BSP_APIC_ID
 	select TINY_BOOTBLOCK
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,7 +24,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0

Modified: trunk/src/mainboard/amd/tilapia_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/tilapia_fam10/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -28,6 +28,7 @@
 	select ENABLE_APIC_EXT_ID
 	select TINY_BOOTBLOCK
 	select GFXUMA
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,7 +24,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0

Modified: trunk/src/mainboard/arima/hdama/Kconfig
==============================================================================
--- trunk/src/mainboard/arima/hdama/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/arima/hdama/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -15,6 +15,7 @@
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select BOARD_ROMSIZE_KB_512
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/arima/hdama/romstage.c
==============================================================================
--- trunk/src/mainboard/arima/hdama/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/arima/hdama/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -67,7 +67,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/resourcemap.c"

Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/asrock/939a785gmh/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,6 +24,7 @@
 	select BOARD_ROMSIZE_KB_1024
 	select GFXUMA
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -19,7 +19,6 @@
  */
 
 #define SET_FIDVID 1
-#define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/asus/a8n_e/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/asus/a8n_e/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -17,6 +17,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select CK804_USE_NIC
 	select CK804_USE_ACI
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 
 /* Used by raminit. */
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS == 1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/asus/a8v-e_se/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -16,6 +16,7 @@
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 unsigned int get_sbdn(unsigned bus);
 
 /* Used by raminit. */
-#define QRANK_DIMM_SUPPORT 1
 
 /* Used by init_cpus and fidvid */
 #define SET_FIDVID 1

Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -36,6 +36,7 @@
 	select VGA
 	select TINY_BOOTBLOCK
 	select HAVE_MAINBOARD_RESOURCES
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 unsigned int get_sbdn(unsigned bus);
 
 /* Used by raminit. */
-#define QRANK_DIMM_SUPPORT 1
 
 /* Used by init_cpus and fidvid */
 #define SET_FIDVID 1

Modified: trunk/src/mainboard/asus/m4a785-m/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/asus/m4a785-m/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -27,6 +27,7 @@
 	select ENABLE_APIC_EXT_ID
 	select TINY_BOOTBLOCK
 	select GFXUMA
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,7 +24,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0

Modified: trunk/src/mainboard/broadcom/blast/Kconfig
==============================================================================
--- trunk/src/mainboard/broadcom/blast/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/broadcom/blast/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -16,6 +16,7 @@
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/broadcom/blast/romstage.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/broadcom/blast/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,4 +1,3 @@
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -19,6 +19,7 @@
 	select K8_REV_F_SUPPORT
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -27,7 +27,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -23,7 +23,6 @@
 
 #define K8_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/gigabyte/m57sli/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -23,6 +23,7 @@
 	select K8_REV_F_SUPPORT
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 

Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,7 +21,6 @@
 
 #define K8_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -28,6 +28,7 @@
 	select TINY_BOOTBLOCK
 	select GFXUMA
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,7 +24,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by init_cpus and fidvid
 #define SET_FIDVID 1

Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -28,6 +28,7 @@
 	select TINY_BOOTBLOCK
 	select GFXUMA
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,7 +24,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0

Modified: trunk/src/mainboard/hp/dl145_g1/Kconfig
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/hp/dl145_g1/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -16,6 +16,7 @@
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
 #	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/hp/dl145_g1/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,4 +1,3 @@
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/hp/dl145_g3/Kconfig
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/hp/dl145_g3/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,6 +21,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/hp/dl145_g3/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -27,7 +27,6 @@
 
 #define K8_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -23,6 +23,7 @@
 	select ENABLE_APIC_EXT_ID
 	select AMDMCT
 	select TINY_BOOTBLOCK
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -28,7 +28,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/ibm/e325/Kconfig
==============================================================================
--- trunk/src/mainboard/ibm/e325/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/ibm/e325/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -16,6 +16,7 @@
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select WAIT_BEFORE_CPUS_INIT
 	select BOARD_ROMSIZE_KB_512
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/ibm/e325/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e325/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/ibm/e325/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -64,7 +64,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"

Modified: trunk/src/mainboard/ibm/e326/Kconfig
==============================================================================
--- trunk/src/mainboard/ibm/e326/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/ibm/e326/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -16,6 +16,7 @@
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select WAIT_BEFORE_CPUS_INIT
 	select BOARD_ROMSIZE_KB_512
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/ibm/e326/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e326/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/ibm/e326/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -64,7 +64,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -28,6 +28,7 @@
 	select ENABLE_APIC_EXT_ID
 	select TINY_BOOTBLOCK
 	select GFXUMA
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,7 +24,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0

Modified: trunk/src/mainboard/iwill/dk8_htx/Kconfig
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/iwill/dk8_htx/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,6 +21,7 @@
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,7 +1,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1

Modified: trunk/src/mainboard/iwill/dk8s2/Kconfig
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/iwill/dk8s2/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -18,6 +18,7 @@
 	select ATI_RAGE_XL
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,7 +1,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1

Modified: trunk/src/mainboard/iwill/dk8x/Kconfig
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/iwill/dk8x/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -17,6 +17,7 @@
 	select WAIT_BEFORE_CPUS_INIT
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,7 +1,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1

Modified: trunk/src/mainboard/jetway/pa78vm5/Kconfig
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/jetway/pa78vm5/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -28,6 +28,7 @@
 	select ENABLE_APIC_EXT_ID
 	select TINY_BOOTBLOCK
 	select GFXUMA
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0

Modified: trunk/src/mainboard/kontron/kt690/Kconfig
==============================================================================
--- trunk/src/mainboard/kontron/kt690/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/kontron/kt690/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -22,6 +22,7 @@
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/kontron/kt690/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/kontron/kt690/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -19,7 +19,6 @@
  */
 
 #define SET_FIDVID 1
-#define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/msi/ms7135/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7135/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms7135/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -16,6 +16,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select CK804_USE_NIC
 	select CK804_USE_ACI
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/msi/ms7135/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms7135/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 #define SERIAL_DEV PNP_DEV(0x4e, W83627THF_SP1)
 
 /* Used by raminit. */
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS == 1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/msi/ms7260/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7260/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms7260/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,6 +21,7 @@
 	select K8_REV_F_SUPPORT
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/msi/ms7260/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/ap_romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms7260/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,7 +24,6 @@
 #define __PRE_RAM__
 
 #define SET_NB_CFG_54 1			/* Used by RAM init. */
-#define QRANK_DIMM_SUPPORT 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 
 #include <stdint.h>

Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms7260/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 // #define RES_DEBUG 1
 
 #define K8_ALLOCATE_IO_RANGE 1
-#define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS == 1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/msi/ms9185/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9185/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms9185/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,6 +21,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms9185/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -26,7 +26,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1

Modified: trunk/src/mainboard/msi/ms9282/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9282/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms9282/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -19,6 +19,7 @@
 	select K8_REV_F_SUPPORT
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms9282/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 // used by init_cpus and fidvid (disabled until someone tests this)
 // #define SET_FIDVID 1

Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -24,6 +24,7 @@
 	select AMDMCT
 	select TINY_BOOTBLOCK
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -22,7 +22,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/newisys/khepri/Kconfig
==============================================================================
--- trunk/src/mainboard/newisys/khepri/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/newisys/khepri/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -15,6 +15,7 @@
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/newisys/khepri/romstage.c
==============================================================================
--- trunk/src/mainboard/newisys/khepri/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/newisys/khepri/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -72,7 +72,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -22,6 +22,7 @@
 	select K8_REV_F_SUPPORT
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 

Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,7 +21,6 @@
 
 #define K8_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/sunw/ultra40/Kconfig
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/sunw/ultra40/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -16,6 +16,7 @@
 	select BOARD_ROMSIZE_KB_1024
 	select CK804_USE_NIC
 	select CK804_USE_ACI
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/sunw/ultra40/romstage.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/sunw/ultra40/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,6 +1,5 @@
 #define K8_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/supermicro/h8dme/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -22,6 +22,7 @@
 	select LIFT_BSP_APIC_ID
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 

Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -18,7 +18,6 @@
 
 #define K8_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/supermicro/h8dmr/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,6 +21,7 @@
 	select LIFT_BSP_APIC_ID
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 

Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,7 +21,6 @@
 
 #define K8_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -23,6 +23,7 @@
 	select RAMINIT_SYSINFO
 	select TINY_BOOTBLOCK
 	select ENABLE_APIC_EXT_ID
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -22,7 +22,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -22,6 +22,7 @@
 	select RAMINIT_SYSINFO
 	select TINY_BOOTBLOCK
 	select ENABLE_APIC_EXT_ID
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -22,7 +22,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/technexion/tim5690/Kconfig
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/technexion/tim5690/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -22,6 +22,7 @@
 	select HAVE_MAINBOARD_RESOURCES
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/technexion/tim5690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/technexion/tim5690/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -18,7 +18,6 @@
  */
 
 #define SET_FIDVID 1
-#define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/technexion/tim8690/Kconfig
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/technexion/tim8690/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,6 +21,7 @@
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/technexion/tim8690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/technexion/tim8690/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -18,7 +18,6 @@
  */
 
 #define SET_FIDVID 1
-#define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/tyan/s2875/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2875/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2875/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -15,6 +15,7 @@
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2875/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2875/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2875/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -62,7 +62,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/tyan/s2880/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2880/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2880/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -15,6 +15,7 @@
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2880/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2880/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -62,7 +62,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/resourcemap.c"

Modified: trunk/src/mainboard/tyan/s2881/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2881/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2881/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -17,6 +17,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select DRIVERS_SIL_3114
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2881/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2881/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,4 +1,3 @@
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/tyan/s2882/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2882/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2882/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -16,6 +16,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select DRIVERS_SIL_3114
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2882/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2882/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -62,7 +62,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/resourcemap.c"

Modified: trunk/src/mainboard/tyan/s2885/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2885/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2885/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -17,6 +17,7 @@
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2885/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2885/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -62,7 +62,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/tyan/s2891/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2891/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2891/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -18,6 +18,7 @@
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2891/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,5 +1,4 @@
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/tyan/s2892/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2892/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2892/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -17,6 +17,7 @@
 	select SERIAL_CPU_INIT
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2892/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2892/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,4 +1,3 @@
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/tyan/s2895/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2895/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2895/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -17,6 +17,7 @@
 	select SERIAL_CPU_INIT
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2895/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -1,6 +1,5 @@
 #define K8_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/tyan/s2912/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2912/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,6 +21,7 @@
 	select K8_REV_F_SUPPORT
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/ap_romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2912/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -25,7 +25,6 @@
 #define SET_NB_CFG_54 1
 
 //used by raminit
-#define QRANK_DIMM_SUPPORT 1
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 

Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2912/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -21,7 +21,6 @@
 
 #define K8_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -23,6 +23,7 @@
 	select AMDMCT
 	select TINY_BOOTBLOCK
 	select MMCONF_SUPPORT_DEFAULT
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -22,7 +22,6 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/tyan/s4880/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s4880/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s4880/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -15,6 +15,7 @@
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s4880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4880/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s4880/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -76,7 +76,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/tyan/s4882/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s4882/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s4882/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -15,6 +15,7 @@
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s4882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4882/romstage.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/mainboard/tyan/s4882/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -84,7 +84,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/northbridge/amd/amdk8/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/amdk8/Kconfig	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/northbridge/amd/amdk8/Kconfig	Fri Nov  5 23:59:49 2010	(r6028)
@@ -49,6 +49,10 @@
 	bool
 	default n
 
+config QRANK_DIMM_SUPPORT
+	bool
+	default n
+
 if K8_REV_F_SUPPORT
 
 config DIMM_DDR2

Modified: trunk/src/northbridge/amd/amdk8/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/northbridge/amd/amdk8/raminit.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -18,10 +18,6 @@
 # error "CONFIG_RAMTOP must be a power of 2"
 #endif
 
-#ifndef QRANK_DIMM_SUPPORT
-#define QRANK_DIMM_SUPPORT 0
-#endif
-
 void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
@@ -595,7 +591,7 @@
 	unsigned long side2;
 	unsigned long rows;
 	unsigned long col;
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	unsigned long rank;
 #endif
 };
@@ -609,7 +605,7 @@
 	sz.side2 = 0;
 	sz.rows = 0;
 	sz.col = 0;
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	sz.rank = 0;
 #endif
 
@@ -653,7 +649,7 @@
 	if ((value != 2) && (value != 4 )) {
 		goto val_err;
 	}
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	sz.rank = value;
 #endif
 
@@ -682,7 +678,7 @@
 	sz.side2 = 0;
 	sz.rows = 0;
 	sz.col = 0;
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	sz.rank = 0;
 #endif
  out:
@@ -730,7 +726,7 @@
 	/* Set the appropriate DIMM base address register */
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	if (sz.rank == 4) {
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
@@ -741,7 +737,7 @@
 	if (base0) {
 		dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
 		dch |= DCH_MEMCLK_EN0 << index;
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 		if (sz.rank == 4) {
 			dch |= DCH_MEMCLK_EN0 << (index + 2);
 		}
@@ -763,7 +759,7 @@
 
 	map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
 	map &= ~(0xf << (index * 4));
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	if (sz.rank == 4) {
 		map &= ~(0xf << ( (index + 2) * 4));
 	}
@@ -774,7 +770,7 @@
 	if (sz.side1 >= (25 +3)) {
 		if (is_cpu_pre_d0()) {
 			map |= (sz.side1 - (25 + 3)) << (index *4);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 			if (sz.rank == 4) {
 	 			map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
 			}
@@ -782,7 +778,7 @@
 		}
 		else {
 			map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 			if (sz.rank == 4) {
 				map |=  cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
 			}
@@ -1526,7 +1522,7 @@
 	}
 #if 0
 //down speed for full load 4 rank support
-#if QRANK_DIMM_SUPPORT
+#if CONFIG_QRANK_DIMM_SUPPORT
 	if (dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
 		int ranks = 4;
 		for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
@@ -1793,7 +1789,7 @@
 {
 	uint32_t dcl;
 	int value;
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	int rank;
 #endif
 	int dimm;
@@ -1802,7 +1798,7 @@
 		return -1;
 	}
 
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	rank = spd_read_byte(ctrl->channel0[i], 5);	/* number of physical banks */
 	if (rank < 0) {
 		return -1;
@@ -1810,7 +1806,7 @@
 #endif
 
 	dimm = 1<<(DCL_x4DIMM_SHIFT+i);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	if (rank==4) {
 		dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
 	}

Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f.c	Fri Nov  5 17:17:46 2010	(r6027)
+++ trunk/src/northbridge/amd/amdk8/raminit_f.c	Fri Nov  5 23:59:49 2010	(r6028)
@@ -32,10 +32,6 @@
 #include "option_table.h"
 #endif
 
-#ifndef QRANK_DIMM_SUPPORT
-#define QRANK_DIMM_SUPPORT 0
-#endif
-
 #if CONFIG_DEBUG_RAM_SETUP
 #define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
 #else
@@ -870,7 +866,7 @@
 		/* Set the appropriate DIMM base address register */
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 		if (sz->rank == 4) {
 			pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
 			pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
@@ -898,7 +894,7 @@
 		} else {
 			dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
 			dword &= ~(ClkDis0 >> index);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 			if (sz->rank == 4) {
 				dword &= ~(ClkDis0 >> (index+2));
 			}
@@ -908,7 +904,7 @@
 			if (meminfo->is_Width128) { // ChannelA+B
 				dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
 				dword &= ~(ClkDis0 >> index);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 				if (sz->rank == 4) {
 					dword &= ~(ClkDis0 >> (index+2));
 				}
@@ -961,7 +957,7 @@
 	}
 	map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
 	map &= ~(0xf << (index * 4));
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	if (sz->rank == 4) {
 		map &= ~(0xf << ( (index + 2) * 4));
 	}
@@ -972,7 +968,7 @@
 		unsigned temp_map;
 		temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
 		map |= temp_map << (index*4);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 		if (sz->rank == 4) {
 			map |=  temp_map << ( (index + 2) * 4);
 		}
@@ -1312,7 +1308,7 @@
 	} else {
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 		if (meminfo->sz[index].rank == 4) {
 			pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
 			pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
@@ -2194,7 +2190,7 @@
 static void set_4RankRDimm(const struct mem_controller *ctrl,
 			const struct mem_param *param, struct mem_info *meminfo)
 {
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	int value;
 	int i;
 	long dimm_mask = meminfo->dimm_mask;
@@ -2234,7 +2230,7 @@
 	uint32_t mask_single_rank;
 	uint32_t mask_page_1k;
 	int value;
-#if QRANK_DIMM_SUPPORT == 1
+#if CONFIG_QRANK_DIMM_SUPPORT
 	int rank;
 #endif
 
@@ -2267,20 +2263,20 @@
 
 		value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
 
-		#if QRANK_DIMM_SUPPORT == 1
+		#if CONFIG_QRANK_DIMM_SUPPORT
 			rank = meminfo->sz[i].rank;
 		#endif
 
 		if (value==4) {
 			mask_x4 |= (1<<i);
-			#if QRANK_DIMM_SUPPORT == 1
+			#if CONFIG_QRANK_DIMM_SUPPORT
 			if (rank==4) {
 				mask_x4 |= 1<<(i+2);
 			}
 			#endif
 		} else if (value==16) {
 			mask_x16 |= (1<<i);
-			#if QRANK_DIMM_SUPPORT == 1
+			#if CONFIG_QRANK_DIMM_SUPPORT
 			 if (rank==4) {
 				 mask_x16 |= 1<<(i+2);
 			 }



From njacobs8 at hetnet.nl  Sat Nov  6 00:50:10 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Sat, 6 Nov 2010 00:50:10 +0100
Subject: [coreboot] [PATCH] Geode GX2 print(k) V2
In-Reply-To: <20101105001403.GT3256@greenwood>
References: <201011042335.56685.njacobs8@hetnet.nl>
	<20101105001403.GT3256@greenwood>
Message-ID: <201011060050.10210.njacobs8@hetnet.nl>

Op vrijdag 5 november 2010 01:14:03 schreef u:
> On Thu, Nov 04, 2010 at 11:35:56PM +0100, Nils wrote:
> > Remove banner wrapper function and unify print(k).
> > 
> > Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
> 
> Thanks, 6021.
> 
> 
> Uwe.

Thanks for the review and commit.

Nils.



From njacobs8 at hetnet.nl  Sat Nov  6 00:51:11 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Sat, 6 Nov 2010 00:51:11 +0100
Subject: [coreboot] [PATCH] Add cpu speed selection to Geode GX2 boards
In-Reply-To: <20101105002348.GV3256@greenwood>
References: <201011022233.44143.njacobs8@hetnet.nl>
	<20101105002348.GV3256@greenwood>
Message-ID: <201011060051.11709.njacobs8@hetnet.nl>

Op vrijdag 5 november 2010 01:23:48 schreef u:
> On Tue, Nov 02, 2010 at 10:33:44PM +0100, Nils wrote:
> > This patch adds Kconfig cpu speed selection to Geode GX2 boards as
> > requested by Uwe.
> > 
> > Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
> 
> Thanks, r6023.
> 
> 
> Uwe.

Thanks for the review and commit.

Nils.



From njacobs8 at hetnet.nl  Sat Nov  6 00:56:15 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Sat, 6 Nov 2010 00:56:15 +0100
Subject: [coreboot] [PATCH] Define unused DIMM1 to 0xFF on Geode GX2
	boards
In-Reply-To: <20101105002003.GU3256@greenwood>
References: <201011022233.22980.njacobs8@hetnet.nl>
	<20101105002003.GU3256@greenwood>
Message-ID: <201011060056.16016.njacobs8@hetnet.nl>

Op vrijdag 5 november 2010 01:20:03 schreef u:
> On Tue, Nov 02, 2010 at 10:33:22PM +0100, Nils wrote:
> > This patch defines the unused DIMM1 to 0xFF to make it obvious it is a
> > bogus value.
> > 
> > Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>
> 
> Thanks, r6022. I added some comments too to make it clearer why it's
> 0xFF, I hope the comments are correct and make sense.
> 
> 
> Uwe.

Thanks for the review and commit.
Your comments look great.

Nils.



From njacobs8 at hetnet.nl  Sat Nov  6 01:26:50 2010
From: njacobs8 at hetnet.nl (Nils)
Date: Sat, 6 Nov 2010 01:26:50 +0100
Subject: [coreboot] [PATCH 0/4] Geode GX2 auto DRAM detect patch V2
In-Reply-To: <20101105002952.GW3256@greenwood>
References: <201011012028.27545.njacobs8@hetnet.nl>
	<20101105002952.GW3256@greenwood>
Message-ID: <201011060126.50249.njacobs8@hetnet.nl>

Op vrijdag 5 november 2010 01:29:52 schreef u:
> On Mon, Nov 01, 2010 at 08:28:27PM +0100, Nils wrote:
> > >Shouldn't there be a "while (1)" around the hlt instruction?
> > 
> > ?? i don't know should it?
> > The code seems to work, but if it is preferred/needed i will add it.
> 
> As far as I know the "hlt" instruction on x86 does not really terminally
> "halt" the processor, it can be woken up again by certain events (NMI,
> debug exceptions, whatever). So usually you only see the "hlt"
> instruction in a while(1) loop if you want the code to not ever continue
> execution after the "hlt" instruction. But someone please correct me
> if I'm wrong.
> 
> 
> Uwe.

Ok thanks for the explanation.
It sounds plausible.
I copied it from the LX code.
I will study this a bit more when i find some time and try to make a patch.

Thanks, Nils.



From svn at coreboot.org  Sat Nov  6 01:57:20 2010
From: svn at coreboot.org (repository service)
Date: Sat, 06 Nov 2010 01:57:20 +0100
Subject: [coreboot] [commit] r6029 - in trunk/src/mainboard:
	amd/mahogany_fam10 amd/serengeti_cheetah
	amd/serengeti_cheetah_fam10 amd/tilapia_fam10 asus/a8n_e
	asus/a8v-e_se asus/m2v-mx_se asus/m4a785-m gigabyte/ga_276...
Message-ID: <E1PEX5s-0002rH-9g@ra.coresystems.de>

Author: uwe
Date: Sat Nov  6 01:57:19 2010
New Revision: 6029
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6029

Log:
Remove comments that are obsolete since r6028.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
   trunk/src/mainboard/amd/tilapia_fam10/romstage.c
   trunk/src/mainboard/asus/a8n_e/romstage.c
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/asus/m2v-mx_se/romstage.c
   trunk/src/mainboard/asus/m4a785-m/romstage.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
   trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c
   trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
   trunk/src/mainboard/gigabyte/ma78gm/romstage.c
   trunk/src/mainboard/iwill/dk8_htx/romstage.c
   trunk/src/mainboard/iwill/dk8s2/romstage.c
   trunk/src/mainboard/iwill/dk8x/romstage.c
   trunk/src/mainboard/jetway/pa78vm5/romstage.c
   trunk/src/mainboard/msi/ms7135/romstage.c
   trunk/src/mainboard/msi/ms9185/romstage.c
   trunk/src/mainboard/msi/ms9282/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
   trunk/src/mainboard/supermicro/h8dme/ap_romstage.c
   trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c
   trunk/src/mainboard/tyan/s2891/romstage.c
   trunk/src/mainboard/tyan/s2912/ap_romstage.c

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -23,8 +23,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0

Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -3,8 +3,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 
 #include <stdint.h>

Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -1,7 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1
 

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -23,8 +23,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0

Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -23,8 +23,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0

Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 /* Used by it8712f_enable_serial(). */
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 
-/* Used by raminit. */
-
 #if CONFIG_LOGICAL_CPUS == 1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 
 unsigned int get_sbdn(unsigned bus);
 
-/* Used by raminit. */
-
 /* Used by init_cpus and fidvid */
 #define SET_FIDVID 1
 

Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 
 unsigned int get_sbdn(unsigned bus);
 
-/* Used by raminit. */
-
 /* Used by init_cpus and fidvid */
 #define SET_FIDVID 1
 

Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -23,8 +23,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -26,8 +26,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 
 #include <stdint.h>

Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 
 #include <stdint.h>

Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -23,8 +23,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by init_cpus and fidvid
 #define SET_FIDVID 1
 #define SET_FIDVID_CORE_RANGE 0

Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -23,8 +23,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0

Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -1,7 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1
 

Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -1,7 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1
 

Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -1,7 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1
 

Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0

Modified: trunk/src/mainboard/msi/ms7135/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/msi/ms7135/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, W83627THF_SP1)
 
-/* Used by raminit. */
-
 #if CONFIG_LOGICAL_CPUS == 1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/msi/ms9185/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -25,8 +25,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 //used by incoherent_ht
 //#define K8_ALLOCATE_IO_RANGE 1
 

Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/msi/ms9282/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 // used by init_cpus and fidvid (disabled until someone tests this)
 // #define SET_FIDVID 1
 #define SET_FIDVID 0

Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 
 #include <stdint.h>

Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 
 #include <stdint.h>

Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 
 #include <stdint.h>

Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/tyan/s2891/romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -1,5 +1,3 @@
-//used by raminit
-
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/ap_romstage.c	Fri Nov  5 23:59:49 2010	(r6028)
+++ trunk/src/mainboard/tyan/s2912/ap_romstage.c	Sat Nov  6 01:57:19 2010	(r6029)
@@ -24,8 +24,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by raminit
-
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 
 #include <stdint.h>



From scott at notabs.org  Sat Nov  6 05:32:05 2010
From: scott at notabs.org (Scott Duplichan)
Date: Fri, 5 Nov 2010 23:32:05 -0500
Subject: [coreboot] Questions about more AMD related flags
In-Reply-To: <4CD456E0.1030305@georgi-clan.de>
References: <4CD456E0.1030305@georgi-clan.de>
Message-ID: <C68A1B90FCA546B98B88D3CE40AD5175@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Patrick Georgi
Sent: Friday, November 05, 2010 02:11 PM
To: coreboot at coreboot.org
Subject: [coreboot] Questions about more AMD related flags

]Hi,
]
]while I opened that can of worms over with QRANK_DIMM_SUPPORT, and
]people are listening ;-), let me widen the debate some more:
]
]SET_NB_CFG_54:
]1. It's used in two places (dualcore and quadcore AMD code)
]2. There, it's set active if undeclared before
]3. All other declarations set this active
]
]Any reason to keep this variable at all? If yes, I'll move it to
]Kconfig, otherwise I'll just drop it.


I am familiar with the recent history of this bit. It defaults to
zero, resulting in the 'weird' local apic id numbering. BIOS is 
supposed to set it early to get the normal apic id numbering. 
While I do not know the origin of this strange bit, I do know
it was scheduled for removal in future AMD processors. Unfortunately
the removal plan was rejected. I would certainly get rid of
SET_NB_CFG_54. Just let coreboot set this bit early so that there
is no need to deal with two different local apic id formats.

Thanks,
Scott


]Thanks,
]Patrick




From patrick at georgi-clan.de  Sat Nov  6 13:56:45 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 06 Nov 2010 13:56:45 +0100
Subject: [coreboot] [PATCH]Move SET_FIDVID* to Kconfig
Message-ID: <4CD5508D.8080900@georgi-clan.de>

Hi,

I moved the SET_FIDVID family of configuration options to Kconfig,
adapting its use (CONFIG_ prefix), and tried to minimize the board
specific settings.

They get some defaults in src/cpu/amd/model_*xx/Kconfig, which are
derived from the various #ifndef ... #define ... #endif blocks I removed
in the cpu specific code.

All "#define SET_FIDVID 0" in romstage.c files weren't necessary due to
these defaults, as well as all "#define SET_FIDVID 1" in Fam10 boards,
so these were stripped.
Some "select SET_FIDVID" could probably still be removed.

SET_FIDVID_CORE_RANGE was always 0, so I just chose that in the CPU
config, instead of per-board.
SET_FIDVID_CORE0_ONLY was always 1, so again, I moved this to the CPU.

Any change in SET_FIDVID* configuration values as a result of this patch
is a bug in this patch.


Regards,
Patrick

Move SET_FIDVID family of configuration options to Kconfig.
Reduce their per-board use and rely on per-cpu values instead.

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
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From xdrudis at tinet.cat  Sat Nov  6 15:32:30 2010
From: xdrudis at tinet.cat (xdrudis)
Date: Sat, 6 Nov 2010 15:32:30 +0100
Subject: [coreboot] Questions about more AMD related flags
In-Reply-To: <4CD456E0.1030305@georgi-clan.de>
References: <4CD456E0.1030305@georgi-clan.de>
Message-ID: <20101106143230.GB18239@ideafix.casa.ct>

On Fri, Nov 05, 2010 at 08:11:28PM +0100, Patrick Georgi wrote:
> SET_FIDVID*:
> These have _very_ weird behaviour, being set to some defaults in the two
> init_cpus.c (and fidvid.c seems to expect to be included after that
> one?), and some other settings somewhere else.
> I tried to untangle that while moving to Kconfig, but didn't quite
> succeed, so is here anyone who knows which defaults (or dependencies)
> are correct for each of the following? So far I have:
>

I've been playing with fidvid.c a little for my single FAM10 cpu (4
cores) slowly at my scarce free time.

I'm quite ignorant and the only result I got has been a consistent
hang in prep_fid_vid after warm reset with my changes, and without 
them it sometimes hanged around there and often later.

So don't quite believe me but 
> 
> For Fam10h:
> +config SET_FIDVID
> +       bool
> +       default y
> +

This enables or disables all cpu and northbridge frecuency and voltage
settings required by BKDG . In order to comply with BKDG it should be
on for all FAM10.  I believe it is set to 1 in all FAM10 boards ?

> +config SET_FIDVID_CORE0_ONLY
> +       bool
> +       default n
> +       depends on SET_FIDVID
> +

I remember I didn't realise for a while that SET_FIDVID_CORE0_ONLY
was off but it was, so I agree it was weird to me, but I thought it 
was just me. There are things in the BKDG that need to be done 
for each core, not just core0, so I decided it 
was rightly off. I'd say FAM10 needs  SET_FIDVID_CORE0_ONLY
to off irrespective of board.

For example, 
fixPsNbVidBeforeWR() in src/cpu/amd/model_10xxx/fidvid.c 
implements steps 1-6 of BKDG 2.4.2.9.1 in case of 
needing nb vid update. The BKDG #31116 rev 3.48 April 2010
says the pstate MSRs need writes for all cores.
The BSP core 0 will always do it, because mainboard/.../romstage.c
calls init_fidvid_bsp(). But the other cores wouldn't 
do it if SET_FIDVID_CORE0_ONLY was on (init_cpus() would call
init_fidvid_ap for core0 of nodes other than BSP but not 
for cores 1,2,3,... of any node)  

Is this what you were asking ?

> +config SET_FIDVID_CORE_RANGE
> +       bool
> +       default n
> +       depends on SET_FIDVID
> +

bool ? I Only saw it used in init_fidvid_bsp as the second 
parameter to for_each_ap, and it does:

if 1 iterates over core0 in nodes >0
if 2 iterates over cores 1 .. max (skips core0 of each node)
else iterates over all cores in all nodes (except bsp core 0)

this iterations wait for the cores to give their results and 
then calculates the common fid (frequency Id for the
northbridge, wich must be the minimum i.e. slowest required for
all processors). I guess one can check for each core or for
one core in each processor (node). BKDG says 

   "F3xD4[NbFid] must be matched between all processors in the coherent
   fabric of a multi-socket sys- tem. The lowest setting from all
   processors in a multi-socket system (determined by using the following
   equa- tions on each processor and selecting the lowest value) is used
   as the common NbFid. "

So I would suppose you don't really need to check all cores in 
a processor. If they share the northbridge how could they
require different frequencies for it ?. But this is only with
respect to the frecuency. Maybe you want to wait for all simply
to make sure you already set the NBVid before you set the NbFid?
I believe for tilapia_fam10 you already have waited 
at wait_all_other_cores_started  before calling init_fidvid_bsp,
so you could have SET_FIDVID_CORE_RANGE to 1 and save a little.
I think it's always 0, though.

> +config SET_FIDVID_DEBUG
> +       bool
> +       default y
> +       depends on SET_FIDVID
> +

For me it's ok at 1 . For FAM10 at least it is only use to enable
traces for fidvid code (frequency and voltage setting).


> +config SET_FIDVID_STORE_AP_APICID_AT_FIRST
> +       bool
> +       default y
> +       depends on SET_FIDVID
> 
> 

model_10xx/fidvid.c 
// if we are tight of CAR stack, disable it
#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1

I don't fully understand the advantage of enabling it.
Apparently it only enables a table of core apicids 
that is first built and then read to wait for each core
to tell you its nbfid. Why can't you directly iterate
once and wait and calculate the nbfid (which is what
would happen if this was 0) ?.
The other difference is that setting it to 0 would
make it not use SET_FIDVID_CORE_RANGE, and iterate 
always for all cores that have calculated fid, 
(in fact iterate for all cores
if SET_FIDVID_CORE0_ONLY is 0 as it should, or only
cores 0 if SET_FIDVID_CORE0_ONLY is 1 against BKDG). 

I don't know about fam f, it uses a different fidvid.c .



From patrick at georgi-clan.de  Sat Nov  6 19:43:32 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 06 Nov 2010 19:43:32 +0100
Subject: [coreboot] [PATCH/RFC]Move SYSTEM_TYPE to Kconfig
Message-ID: <4CD5A1D4.1040802@georgi-clan.de>

Hi,

we currently have a config variable SYSTEM_TYPE in AMD based boards'
romstage.c, which defines if the board is "server", "desktop" or
"mobile". Among other things, the AMD code expects "server" to do ECC.

I broke that out to Kconfig, but extended the categories to the ACPI set
(which the OS can use for tuning the power management profile
accordingly). Now, it's declared in Kconfig with ACPI categories (which
provides a couple more values, like "SOHO Server" and "Performance
Server"), and based on these, the AMD value is chosen.

The Kconfig selection is also used to set the preferred PM profile in
ACPI (on the modified boards only for now).

The upside of this approach is that we only set the board type once, and
have it trickle down to whoever cares for it - so consistency is
implicitely ensured through the build system.
We also won't have to worry about this field should we ever get to the
point that the fadt is handled by unified code instead of per-board code
(and I hope we'll get there eventually).

The downside is that some things can't be modelled quite right (eg. one
AMD board was marked "server" for the AMD code, but "workstation" for
ACPI - I made that a "SOHO Server" instead in this patch).

If this patch is accepted, I'd build another patch that adapts those
boards which provide an FADT (which contains the PM profile field) to
this new config option. All others are of "unspecified" type by default
if they're ever made ACPI aware.


Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
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From uwe at hermann-uwe.de  Sat Nov  6 20:14:22 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 6 Nov 2010 20:14:22 +0100
Subject: [coreboot] [PATCH/RFC]Move SYSTEM_TYPE to Kconfig
In-Reply-To: <4CD5A1D4.1040802@georgi-clan.de>
References: <4CD5A1D4.1040802@georgi-clan.de>
Message-ID: <20101106191421.GY3256@greenwood>

On Sat, Nov 06, 2010 at 07:43:32PM +0100, Patrick Georgi wrote:
> Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

Yep, great idea + patch. If it survives abuild:

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


> Index: src/cpu/amd/Kconfig
> ===================================================================
> --- src/cpu/amd/Kconfig	(Revision 6029)
> +++ src/cpu/amd/Kconfig	(Arbeitskopie)
> @@ -20,3 +20,10 @@
>  source src/cpu/amd/model_lx/Kconfig
>  
>  source src/cpu/amd/sc520/Kconfig
> +



> +config SYSTEM_TYPE_AMD

Maybe add a short comment here (similar to the commit msg) so that people
who read the files know why this is done etc.


> +	int
> +	default 0 if SYSTEM_TYPE_UNSPECIFIED | SYSTEM_TYPE_ENTERPRISE_SERVER | SYSTEM_TYPE_SOHO_SERVER | SYSTEM_TYPE_PERFORMANCE_SERVER
> +	default 1 if SYSTEM_TYPE_DESKTOP | SYSTEM_TYPE_WORKSTATION
> +	default 2 if SYSTEM_TYPE_LAPTOP | SYSTEM_TYPE_APPLIANCE_PC
> +

> Index: src/mainboard/Kconfig
> ===================================================================
> --- src/mainboard/Kconfig	(Revision 6029)
> +++ src/mainboard/Kconfig	(Arbeitskopie)
> @@ -247,6 +247,50 @@
>  	default 0x200000 if COREBOOT_ROMSIZE_KB_2048
>  	default 0x400000 if COREBOOT_ROMSIZE_KB_4096
>  
> +choice
> +	prompt "System Type"
> +	default SYSTEM_TYPE_UNSPECIFIED
> +	help
> +	  Chipset configuration and OS behaviour can be tuned for several
> +          use cases.
> +
> +config SYSTEM_TYPE_UNSPECIFIED
> +	bool "Unspecified"

Maybe change
	bool "Unspecified"
to just
	bool
?

The choice should not be user-visible, right? So no string needs to be
supplied (the CONFIG_* name is self-describing already, too).

Ditto for the other SYSTEM_TYPE_* options.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From towardsoss at gmail.com  Sat Nov  6 22:52:27 2010
From: towardsoss at gmail.com (Niklas Cholmkvist)
Date: Sat, 06 Nov 2010 23:52:27 +0200
Subject: [coreboot] Buying a new mainboard. Which vendors support coreboot?
Message-ID: <1289080347.7473.14.camel@gnewsense>

Hi,

I would like a mainboard from a vendor that supports coreboot, but also
has an Intel GMA(3D acceleration) on the same mainboard.(Intel GMA
because of my percieved 'good 3D FLOSS drivers'...though irrelevant to
coreboot)
I've read that AMD is very supportive of coreboot. Do you think it's
possible that there is an AMD mainboard with an Intel GMA(3D
acceleration) on it?
-- 

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From patrick at georgi-clan.de  Sun Nov  7 00:01:29 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 07 Nov 2010 00:01:29 +0100
Subject: [coreboot] [RFC]Static testing of our tree
Message-ID: <4CD5DE49.1020306@georgi-clan.de>

Hi,

I'm currently thinking about various tests we could do on our tree to
avoid regressions, not just in functionality (which is somewhat hard to
do with all the board specific code we have), but also in style and
practices.

My first attempt is the attached script
(lint-001-no-global-config-in-romstage), which checks for preprocessor
symbols defined in mainboard romstages that are used elsewhere in the tree.
As you can see from my other mails these days, I'm currently trying to
cut down on these, by moving them to Kconfig.
This has several reasons: First, it's necessary to have these symbols
available globally when we start building the romstage in more separate
compilation units (more on that below). Second, it's basically a second
configuration mechanism besides the one we have, which is Kconfig.

The script, when run from the top level directory of a coreboot
checkout, emits the symbols that are defined in some romstage and are
used elsewhere. No further information is given as the idea is to give a
relatively quick overview on the tree, and fetching a list of files
where those symbols are in use would be expensive.

I propose to store this script (and similar ones) somewhere under util/,
and hook them up in the Makefile ("make lint"?) and in the autobuilder
(qa.coreboot.org), and have that report failure if they return any output.
That way, no change can readd this "second config system" without being
noticed.
I don't propose to do this now - that would mean that the autobuilder
reports errors for the next couple of weeks, but once we got the tree in
shape that it passes the test of the script, it could go in and make
sure that this issue doesn't come up again.


Another test could ensure that no mainboard code (and maybe even more
parts of the tree later-on) #includes *.c files.
That effort is useful because smaller compilation units make it easier
to track down bugs, to validate code, and so on.
If I ask you, could you tell (without looking) if init_cpus.c or
fidvid.c should be included first on an AMD K8/Fam10 board? It shouldn't
matter, but it does.

It's init_cpus.c, by the way ;-)


External tools, such as lint, splint could also be added into that
framework, should they be actually useful for our code (many aren't
because of their assumptions on C coding within OS environments).


This mail is marked RFC for a reason - what do you think?


Regards,
Patrick
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From svn at coreboot.org  Sun Nov  7 00:36:50 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 00:36:50 +0100
Subject: [coreboot] [commit] r6030 - in trunk/src/superio: renesas/m3885x
	serverengines/pilot via/vt1211
Message-ID: <E1PEsJW-00072E-9H@ra.coresystems.de>

Author: uwe
Date: Sun Nov  7 00:36:49 2010
New Revision: 6030
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6030

Log:
Various Super I/O fixes and corrections.

 - VIA VT1211:
   - Add missing LDNs and respective code to handle them.
   - Add some TODOs for other stuff that needs fixing.
   - Use VT1211_SP1 instead of hardcoding the LDN number (2).
   - Fixup pnp_dev_info[] as per datasheet, but some TODOs remain.
   - Various coding style fixes and changes to u8/u16/etc.
 
 - Serverengines Pilot: Various coding style fixes and changes to u8/u16/etc.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/superio/renesas/m3885x/superio.c
   trunk/src/superio/serverengines/pilot/pilot.h
   trunk/src/superio/serverengines/pilot/pilot_early_init.c
   trunk/src/superio/serverengines/pilot/pilot_early_serial.c
   trunk/src/superio/via/vt1211/Makefile.inc
   trunk/src/superio/via/vt1211/chip.h
   trunk/src/superio/via/vt1211/vt1211.c
   trunk/src/superio/via/vt1211/vt1211.h

Modified: trunk/src/superio/renesas/m3885x/superio.c
==============================================================================
--- trunk/src/superio/renesas/m3885x/superio.c	Sat Nov  6 01:57:19 2010	(r6029)
+++ trunk/src/superio/renesas/m3885x/superio.c	Sun Nov  7 00:36:49 2010	(r6030)
@@ -44,15 +44,14 @@
 	m3885_configure_multikey();
 }
 
-
 static void m3885x_read_resources(device_t dev)
 {
-	// nothing, but this function avoids an error on serial console.
+	/* Nothing, but this function avoids an error on serial console. */
 }
 
 static void m3885x_enable_resources(device_t dev)
 {
-	// nothing, but this function avoids an error on serial console.
+	/* Nothing, but this function avoids an error on serial console. */
 }
 
 static struct device_operations ops = {
@@ -74,5 +73,3 @@
 	CHIP_NAME("Renesas M3885x Super I/O")
 	.enable_dev = enable_dev,
 };
-
-

Modified: trunk/src/superio/serverengines/pilot/pilot.h
==============================================================================
--- trunk/src/superio/serverengines/pilot/pilot.h	Sat Nov  6 01:57:19 2010	(r6029)
+++ trunk/src/superio/serverengines/pilot/pilot.h	Sun Nov  7 00:36:49 2010	(r6030)
@@ -21,8 +21,8 @@
 
 /* PILOT Super I/O is only based on LPC observation done on factory system. */
 
-#define PILOT_SP1 0x02 /* Com1 */
 #define PILOT_LD1 0x01 /* Logical device 1 */
+#define PILOT_SP1 0x02 /* Com1 */
 #define PILOT_LD4 0x04 /* Logical device 4 */
 #define PILOT_LD5 0x05 /* Logical device 5 */
 #define PILOT_LD7 0x07 /* Logical device 7 */

Modified: trunk/src/superio/serverengines/pilot/pilot_early_init.c
==============================================================================
--- trunk/src/superio/serverengines/pilot/pilot_early_init.c	Sat Nov  6 01:57:19 2010	(r6029)
+++ trunk/src/superio/serverengines/pilot/pilot_early_init.c	Sun Nov  7 00:36:49 2010	(r6030)
@@ -29,7 +29,7 @@
  */
 static void pilot_early_init(device_t dev)
 {
-	unsigned port = dev >> 8;
+	u16 port = dev >> 8;
 
 	print_debug("Using port: ");
 	print_debug_hex16(port);
@@ -55,6 +55,7 @@
 	pnp_set_enable(PNP_DEV(port, 0x3), 0);
 	pnp_exit_ext_func_mode(dev);
 */
+
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_logical_device(PNP_DEV(port, 0x4));
 	pnp_exit_ext_func_mode(dev);
@@ -95,6 +96,7 @@
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_enable(PNP_DEV(port, 0x7), 0);
 	pnp_exit_ext_func_mode(dev);
+
 /*
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_logical_device(PNP_DEV(port, 0x8));

Modified: trunk/src/superio/serverengines/pilot/pilot_early_serial.c
==============================================================================
--- trunk/src/superio/serverengines/pilot/pilot_early_serial.c	Sat Nov  6 01:57:19 2010	(r6029)
+++ trunk/src/superio/serverengines/pilot/pilot_early_serial.c	Sun Nov  7 00:36:49 2010	(r6030)
@@ -25,20 +25,20 @@
 #include "pilot.h"
 
 /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */
-static inline void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(device_t dev)
 {
-	unsigned port = dev >> 8;
+	u16 port = dev >> 8;
 	outb(0x5A, port);
 }
 
 static void pnp_exit_ext_func_mode(device_t dev)
 {
-	unsigned port = dev >> 8;
+	u16 port = dev >> 8;
 	outb(0xA5, port);
 }
 
 /* Serial config is a fairly standard procedure. */
-static void pilot_enable_serial(device_t dev, unsigned iobase)
+static void pilot_enable_serial(device_t dev, u16 iobase)
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_logical_device(dev);
@@ -51,7 +51,7 @@
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_logical_device(dev);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
+	pnp_set_iobase(dev, PNP_IDX_IO0, 0x0000);
 	pnp_set_enable(dev, 0);
 	pnp_exit_ext_func_mode(dev);
 }

Modified: trunk/src/superio/via/vt1211/Makefile.inc
==============================================================================
--- trunk/src/superio/via/vt1211/Makefile.inc	Sat Nov  6 01:57:19 2010	(r6029)
+++ trunk/src/superio/via/vt1211/Makefile.inc	Sun Nov  7 00:36:49 2010	(r6030)
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-#config chip.h
 ramstage-$(CONFIG_SUPERIO_VIA_VT1211) += vt1211.c
+

Modified: trunk/src/superio/via/vt1211/chip.h
==============================================================================
--- trunk/src/superio/via/vt1211/chip.h	Sat Nov  6 01:57:19 2010	(r6029)
+++ trunk/src/superio/via/vt1211/chip.h	Sun Nov  7 00:36:49 2010	(r6030)
@@ -18,8 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef _SUPERIO_VIA_VT1211
-#define _SUPERIO_VIA_VT1211
+#ifndef SUPERIO_VIA_VT1211_CHIP_H
+#define SUPERIO_VIA_VT1211_CHIP_H
 
 #include <uart8250.h>
 
@@ -29,4 +29,4 @@
 	struct uart8250 com1, com2;
 };
 
-#endif /* _SUPERIO_VIA_VT1211 */
+#endif

Modified: trunk/src/superio/via/vt1211/vt1211.c
==============================================================================
--- trunk/src/superio/via/vt1211/vt1211.c	Sat Nov  6 01:57:19 2010	(r6029)
+++ trunk/src/superio/via/vt1211/vt1211.c	Sun Nov  7 00:36:49 2010	(r6030)
@@ -19,33 +19,30 @@
  * MA 02110-1301 USA
  */
 
- /* vt1211 routines and defines*/
-
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pnp.h>
 #include <uart8250.h>
 #include <stdlib.h>
-
 #include "vt1211.h"
 #include "chip.h"
 
-static unsigned char vt1211hwmonitorinits[]={
-	0x10,0x3, 0x11,0x10, 0x12,0xd, 0x13,0x7f,
+static u8 hwm_io_regs[] = {
+	0x10,0x03, 0x11,0x10, 0x12,0x0d, 0x13,0x7f,
 	0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a,
-	0x18,0x0, 0x19,0x0, 0x1a,0x0, 0x1b,0x0,
-	0x1d,0xff, 0x1e,0x0, 0x1f,0x73, 0x20,0x67,
+	0x18,0x00, 0x19,0x00, 0x1a,0x00, 0x1b,0x00,
+	0x1d,0xff, 0x1e,0x00, 0x1f,0x73, 0x20,0x67,
 	0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2,
-	0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x0,
-	0x2a,0x0, 0x2b,0xff, 0x2c,0x0, 0x2d,0xff,
-	0x2e,0x0, 0x2f,0xff, 0x30,0x0, 0x31,0xff,
-	0x32,0x0, 0x33,0xff, 0x34,0x0, 0x39,0xff,
-	0x3a,0x0, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff,
-	0x3e,0x0, 0x3f,0xb0, 0x43,0xff, 0x44,0xff,
-	0x46,0xff, 0x47,0x50, 0x4a,0x3, 0x4b,0xc0,
-	0x4c,0x0, 0x4d,0x0, 0x4e,0xf, 0x5d,0x77,
-	0x5c,0x0, 0x5f,0x33, 0x40,0x1
+	0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x00,
+	0x2a,0x00, 0x2b,0xff, 0x2c,0x00, 0x2d,0xff,
+	0x2e,0x00, 0x2f,0xff, 0x30,0x00, 0x31,0xff,
+	0x32,0x00, 0x33,0xff, 0x34,0x00, 0x39,0xff,
+	0x3a,0x00, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff,
+	0x3e,0x00, 0x3f,0xb0, 0x43,0xff, 0x44,0xff,
+	0x46,0xff, 0x47,0x50, 0x4a,0x03, 0x4b,0xc0,
+	0x4c,0x00, 0x4d,0x00, 0x4e,0x0f, 0x5d,0x77,
+	0x5c,0x00, 0x5f,0x33, 0x40,0x01,
 };
 
 static void pnp_enter_ext_func_mode(device_t dev)
@@ -59,32 +56,39 @@
 	outb(0xaa, dev->path.pnp.port);
 }
 
-static void vt1211_set_iobase(device_t dev, unsigned index, unsigned iobase)
+static void vt1211_set_iobase(device_t dev, u8 index, u16 iobase)
 {
 	switch (dev->path.pnp.device) {
-		case VT1211_FDC:
-		case VT1211_PP:
-		case VT1211_SP1:
-		case VT1211_SP2:
-			pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff);
-			break;
-		case VT1211_HWM:
-		default:
-			pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
-			pnp_write_config(dev, index + 1, iobase & 0xff);
-			break;
+	case VT1211_FDC:
+	case VT1211_PP:
+	case VT1211_SP1:
+	case VT1211_SP2:
+		pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff);
+		break;
+	case VT1211_ROM:
+		/* TODO: Error. VT1211_ROM doesn't have an I/O base. */
+		break;
+	case VT1211_MIDI:
+	case VT1211_GAME:
+	case VT1211_GPIO:
+	case VT1211_WDG:
+	case VT1211_WUC:
+	case VT1211_HWM:
+	case VT1211_FIR:
+	default:
+		pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
+		pnp_write_config(dev, index + 1, iobase & 0xff);
+		break;
 	}
 }
 
-static void init_hwm(unsigned long base)
+/* Initialize VT1211 hardware monitor registers, which are at 0xECXX. */
+static void init_hwm(u16 base)
 {
 	int i;
 
- 	/* initialize vt1211 hardware monitor registers, which are at 0xECXX */
-	for(i = 0; i < sizeof(vt1211hwmonitorinits); i += 2) {
- 			outb(vt1211hwmonitorinits[i + 1],
-					base + vt1211hwmonitorinits[i]);
-	}
+	for (i = 0; i < sizeof(hwm_io_regs); i += 2)
+		outb(hwm_io_regs[i + 1], base + hwm_io_regs[i]);
 }
 
 static void vt1211_init(struct device *dev)
@@ -92,14 +96,10 @@
 	struct superio_via_vt1211_config *conf = dev->chip_info;
 	struct resource *res0;
 
-	if (!dev->enabled) {
+	if (!dev->enabled)
 		return;
-	}
 
 	switch (dev->path.pnp.device) {
-	case VT1211_FDC:
-	case VT1211_PP:
-		break;
 	case VT1211_SP1:
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		init_uart8250(res0->base, &conf->com1);
@@ -112,14 +112,25 @@
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		init_hwm(res0->base);
 		break;
+	case VT1211_FDC:
+	case VT1211_PP:
+	case VT1211_MIDI:
+	case VT1211_GAME:
+	case VT1211_GPIO:
+	case VT1211_WDG:
+	case VT1211_WUC:
+	case VT1211_FIR:
+	case VT1211_ROM:
+		/* TODO: Any init needed for these LDNs? */
+		break;
 	default:
-		printk(BIOS_INFO, "vt1211 asked to initialise unknown device!\n");
+		printk(BIOS_INFO, "VT1211: Cannot init unknown device!\n");
 	}
 }
 
 static void vt1211_pnp_enable_resources(device_t dev)
 {
-	printk(BIOS_DEBUG, "%s - enabling\n",dev_path(dev));
+	printk(BIOS_DEBUG, "%s - enabling\n", dev_path(dev));
 	pnp_enter_ext_func_mode(dev);
 	pnp_enable_resources(dev);
 	pnp_exit_ext_func_mode(dev);
@@ -130,41 +141,39 @@
 	struct resource *res;
 
 #if CONFIG_CONSOLE_SERIAL8250 == 1
-	if( dev->path.pnp.device == 2 ){
-		for(res = dev->resource_list; res; res = res->next){
+	/* TODO: Do the same for SP2? */
+	if (dev->path.pnp.device == VT1211_SP1) {
+		for (res = dev->resource_list; res; res = res->next) {
 			res->flags |= IORESOURCE_STORED;
 			report_resource_stored(dev, res, "");
 		}
 		return;
 	}
 #endif
+
 	pnp_enter_ext_func_mode(dev);
-	/* Select the device */
+
 	pnp_set_logical_device(dev);
 
 	/* Paranoia says I should disable the device here... */
-	for(res = dev->resource_list; res; res = res->next){
+	for (res = dev->resource_list; res; res = res->next) {
 		if (!(res->flags & IORESOURCE_ASSIGNED)) {
-			printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx not assigned\n",
-				dev_path(dev), res->index,
-				resource_type(res),
-				res->size);
+			printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx "
+			       "not assigned\n", dev_path(dev), res->index,
+			       resource_type(res), res->size);
 			continue;
 		}
 
-		/* Now store the resource */
+		/* Now store the resource. */
 		if (res->flags & IORESOURCE_IO) {
 			vt1211_set_iobase(dev, res->index, res->base);
-		}
-		else if (res->flags & IORESOURCE_DRQ) {
+		} else if (res->flags & IORESOURCE_DRQ) {
 			pnp_set_drq(dev, res->index, res->base);
-		}
-		else if (res->flags  & IORESOURCE_IRQ) {
+		} else if (res->flags  & IORESOURCE_IRQ) {
 			pnp_set_irq(dev, res->index, res->base);
-		}
-		else {
-			printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n",
-				dev_path(dev), res->index);
+		} else {
+			printk(BIOS_ERR, "ERROR: %s %02lx unknown resource "
+			       "type\n", dev_path(dev), res->index);
 			return;
 		}
 		res->flags |= IORESOURCE_STORED;
@@ -177,12 +186,13 @@
 
 static void vt1211_pnp_enable(device_t dev)
 {
-	if (!dev->enabled) {
-		pnp_enter_ext_func_mode(dev);
-		pnp_set_logical_device(dev);
-		pnp_set_enable(dev, 0);
-		pnp_exit_ext_func_mode(dev);
-	}
+	if (dev->enabled)
+		return;
+
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_exit_ext_func_mode(dev);
 }
 
 struct device_operations ops = {
@@ -193,21 +203,25 @@
 	.init             = vt1211_init,
 };
 
+/* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */
 static struct pnp_info pnp_dev_info[] = {
-	{ &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-	{ &ops, VT1211_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-	{ &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0,            { 0x07f8, 0}, },
-	{ &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0,            { 0x07f8, 0}, },
-	{ &ops, VT1211_HWM, PNP_IO0 , { 0xff00, 0 }, },
+	{ &ops, VT1211_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
+	{ &ops, VT1211_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
+	{ &ops, VT1211_SP1,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
+	{ &ops, VT1211_SP2,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
+	{ &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 }, },
+	{ &ops, VT1211_GAME, PNP_IO0, { 0xfff8, 0 }, },
+	{ &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
+	{ &ops, VT1211_WDG,  PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
+	{ &ops, VT1211_WUC,  PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
+	{ &ops, VT1211_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff00, 0 }, },
+	{ &ops, VT1211_FIR,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xff00, 0 }, },
+	{ &ops, VT1211_ROM, },
 };
 
 static void enable_dev(struct device *dev)
 {
-	printk(BIOS_DEBUG, "vt1211 enabling PNP devices.\n");
-	pnp_enable_devices(dev,
-			&ops,
-			ARRAY_SIZE(pnp_dev_info),
-			pnp_dev_info);
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_via_vt1211_ops = {

Modified: trunk/src/superio/via/vt1211/vt1211.h
==============================================================================
--- trunk/src/superio/via/vt1211/vt1211.h	Sat Nov  6 01:57:19 2010	(r6029)
+++ trunk/src/superio/via/vt1211/vt1211.h	Sun Nov  7 00:36:49 2010	(r6030)
@@ -18,17 +18,16 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/* vt1211 PNP devices */
-
-#define VT1211_FDC		0	/* Floppy */
-#define VT1211_PP		1	/* Parallel Port */
-#define VT1211_SP1		2	/* COM1 */
-#define VT1211_SP2		3	/* COM2 */
-#define VT1211_MIDI		6	/* MIDI */
-#define VT1211_GAME		7	/* Game port */
-#define VT1211_GPIO		8	/* GPIO pins */
-#define VT1211_WATCHDOG		9	/* Watchdog timer */
-#define VT1211_WAKEUP		10	/* Wakeup control */
-#define VT1211_HWM		11	/* Hardware monitor */
-#define VT1211_FIR		12	/* Irda */
-#define VT1211_ROM		13	/* ROM control */
+/* Logical device numbers (LDNs). */
+#define VT1211_FDC		0x00	/* Floppy */
+#define VT1211_PP		0x01	/* Parallel port */
+#define VT1211_SP1		0x02	/* COM1 */
+#define VT1211_SP2		0x03	/* COM2 */
+#define VT1211_MIDI		0x06	/* MIDI */
+#define VT1211_GAME		0x07	/* Game port (GMP) */
+#define VT1211_GPIO		0x08	/* GPIO */
+#define VT1211_WDG		0x09	/* Watchdog timer (WDG) */
+#define VT1211_WUC		0x0a	/* Wake-up control (WUC) */
+#define VT1211_HWM		0x0b	/* Hardware monitor (HM) */
+#define VT1211_FIR		0x0c	/* Very fast IR (VFIR/FIR) */
+#define VT1211_ROM		0x0d	/* Flash ROM */



From xdrudis at tinet.cat  Sun Nov  7 01:01:35 2010
From: xdrudis at tinet.cat (xdrudis)
Date: Sun, 7 Nov 2010 01:01:35 +0100
Subject: [coreboot] Buying a new mainboard. Which vendors support
 coreboot?
In-Reply-To: <1289080347.7473.14.camel@gnewsense>
References: <1289080347.7473.14.camel@gnewsense>
Message-ID: <20101107000135.GB3983@ideafix.casa.ct>

On Sat, Nov 06, 2010 at 11:52:27PM +0200, Niklas Cholmkvist wrote:
> Hi,
> 
> I would like a mainboard from a vendor that supports coreboot, but also
> has an Intel GMA(3D acceleration) on the same mainboard.(Intel GMA
> because of my percieved 'good 3D FLOSS drivers'...though irrelevant to
> coreboot)
> I've read that AMD is very supportive of coreboot. Do you think it's
> possible that there is an AMD mainboard with an Intel GMA(3D
> acceleration) on it?

I don't think so. I think the bus between the CPU and northbridge
is different, and it can't be easily done. And if it could be done
I don't see Intel willing. It's the same reason there aren't intel
addon graphic cards.

But if you find one please tell me. I ended up with and AMD cpu + nvidia
vga in order to at least have nouveau, but I hate buying from nvidia.




From jakllsch at kollasch.net  Sun Nov  7 01:14:33 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Sun, 7 Nov 2010 00:14:33 +0000
Subject: [coreboot] Buying a new mainboard. Which vendors support
 coreboot?
In-Reply-To: <1289080347.7473.14.camel@gnewsense>
References: <1289080347.7473.14.camel@gnewsense>
Message-ID: <20101107001433.GE25395@tarantulon.kollasch.net>

On Sat, Nov 06, 2010 at 11:52:27PM +0200, Niklas Cholmkvist wrote:
> Hi,
> 
> I would like a mainboard from a vendor that supports coreboot, but also
> has an Intel GMA(3D acceleration) on the same mainboard.(Intel GMA
> because of my percieved 'good 3D FLOSS drivers'...though irrelevant to
> coreboot)
> I've read that AMD is very supportive of coreboot. Do you think it's
> possible that there is an AMD mainboard with an Intel GMA(3D
> acceleration) on it?
> -- 
> 

No, you won't find Intel graphics with a AMD processor.

What makes you think the open source ATI drivers aren't
any good?  AFAICT they're doing pretty well these days.

	Jonathan Kollasch



From xdrudis at tinet.cat  Sun Nov  7 02:02:48 2010
From: xdrudis at tinet.cat (xdrudis)
Date: Sun, 7 Nov 2010 02:02:48 +0100
Subject: [coreboot] Questions about more AMD related flags
In-Reply-To: <20101106143230.GB18239@ideafix.casa.ct>
References: <4CD456E0.1030305@georgi-clan.de>
	<20101106143230.GB18239@ideafix.casa.ct>
Message-ID: <20101107010248.GB4315@ideafix.casa.ct>

On Sat, Nov 06, 2010 at 03:32:30PM +0100, xdrudis wrote:

> 
> So I would suppose you don't really need to check all cores in 
> a processor. If they share the northbridge how could they
> require different frequencies for it ?. But this is only with
> respect to the frecuency. Maybe you want to wait for all simply
> to make sure you already set the NBVid before you set the NbFid?
> I believe for tilapia_fam10 you already have waited 
> at wait_all_other_cores_started  before calling init_fidvid_bsp,
> so you could have SET_FIDVID_CORE_RANGE to 1 and save a little.

Sorry, I was mistaken. wait_all_other_cores_started does not mean
wait for all cores that have started (until they're done) 
but wait for all cores to start. I mean that 
wait_all_other_cores_started waits
until cores have written  F10_APSTATE_STARTED to the lapic and 
init_fidvid_bsp waits until they have written F10_APSTATE_RESET,
just after seting nbvid an changing to pstate 1 and then core0 to pstate 0

I'm not 100% that BKDG 2.4.2.9.1 requires synchronization
after each step, which we don't do, but if it is required between
steps 6 and 8 then SET_FIDVID_CORE_RANGE can't be set to 1
because we wouldn't be waiting for all cores to change to p1.
 



From xdrudis at tinet.cat  Sun Nov  7 02:28:59 2010
From: xdrudis at tinet.cat (xdrudis)
Date: Sun, 7 Nov 2010 02:28:59 +0100
Subject: [coreboot] [PATCH]Move SET_FIDVID* to Kconfig
In-Reply-To: <4CD5508D.8080900@georgi-clan.de>
References: <4CD5508D.8080900@georgi-clan.de>
Message-ID: <20101107012859.GC3983@ideafix.casa.ct>

On Sat, Nov 06, 2010 at 01:56:45PM +0100, Patrick Georgi wrote:
> Hi,
> 
> I moved the SET_FIDVID family of configuration options to Kconfig,
> adapting its use (CONFIG_ prefix), and tried to minimize the board
> specific settings.
> 
> They get some defaults in src/cpu/amd/model_*xx/Kconfig, which are
> derived from the various #ifndef ... #define ... #endif blocks I removed
> in the cpu specific code.
> 
> All "#define SET_FIDVID 0" in romstage.c files weren't necessary due to
> these defaults, as well as all "#define SET_FIDVID 1" in Fam10 boards,
> so these were stripped.
> Some "select SET_FIDVID" could probably still be removed.
>

So far so good. I'm not sure FIDVID can be an option for fam10 .
BKDG require it but I don't know if any fam10 cpu can boot without it.
 
> SET_FIDVID_CORE0_ONLY was always 1, so again, I moved this to the CPU.
>

It isn't always 1. It's 0 for FAM10. But the patch is right as far as I 
can see asleep as I am.




From scott at notabs.org  Sun Nov  7 04:43:25 2010
From: scott at notabs.org (Scott Duplichan)
Date: Sat, 6 Nov 2010 22:43:25 -0500
Subject: [coreboot] [PATCH] ASL should report AMD SB600/SB700 RTC as not
	PIIX4 compatible
Message-ID: <C1B279D76F3742FF985A073E46F24E58@m3a78>

DSDT.asl should not report the AMD SB600/SB700 RTC as Intel PIIX4
compatible. The extended cmos is accessed differently for AMD
and Intel RTCs. Not sure what if any OS cares about this distinction,
but non-Intel compatible seems like a safer way to report the AMD RTC.
Tested with Win7 on Mahogany_fam10 and kino-780am2-fam10.

Signed-off-by: Scott Duplichan <scott at notabs.org>


Index: src/mainboard/amd/dbm690t/dsdt.asl
===================================================================
--- src/mainboard/amd/dbm690t/dsdt.asl	(revision 6030)
+++ src/mainboard/amd/dbm690t/dsdt.asl	(working copy)
@@ -1308,7 +1308,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/amd/mahogany/dsdt.asl
===================================================================
--- src/mainboard/amd/mahogany/dsdt.asl	(revision 6030)
+++ src/mainboard/amd/mahogany/dsdt.asl	(working copy)
@@ -1324,7 +1324,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/amd/mahogany_fam10/dsdt.asl
===================================================================
--- src/mainboard/amd/mahogany_fam10/dsdt.asl	(revision 6030)
+++ src/mainboard/amd/mahogany_fam10/dsdt.asl	(working copy)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/amd/pistachio/dsdt.asl
===================================================================
--- src/mainboard/amd/pistachio/dsdt.asl	(revision 6030)
+++ src/mainboard/amd/pistachio/dsdt.asl	(working copy)
@@ -1307,7 +1307,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/amd/tilapia_fam10/dsdt.asl
===================================================================
--- src/mainboard/amd/tilapia_fam10/dsdt.asl	(revision 6030)
+++ src/mainboard/amd/tilapia_fam10/dsdt.asl	(working copy)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/asrock/939a785gmh/dsdt.asl
===================================================================
--- src/mainboard/asrock/939a785gmh/dsdt.asl	(revision 6030)
+++ src/mainboard/asrock/939a785gmh/dsdt.asl	(working copy)
@@ -1282,7 +1282,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/asus/m4a785-m/dsdt.asl
===================================================================
--- src/mainboard/asus/m4a785-m/dsdt.asl	(revision 6030)
+++ src/mainboard/asus/m4a785-m/dsdt.asl	(working copy)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/gigabyte/ma785gmt/dsdt.asl
===================================================================
--- src/mainboard/gigabyte/ma785gmt/dsdt.asl	(revision 6030)
+++ src/mainboard/gigabyte/ma785gmt/dsdt.asl	(working copy)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/gigabyte/ma78gm/dsdt.asl
===================================================================
--- src/mainboard/gigabyte/ma78gm/dsdt.asl	(revision 6030)
+++ src/mainboard/gigabyte/ma78gm/dsdt.asl	(working copy)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/iei/kino-780am2-fam10/dsdt.asl
===================================================================
--- src/mainboard/iei/kino-780am2-fam10/dsdt.asl	(revision 6030)
+++ src/mainboard/iei/kino-780am2-fam10/dsdt.asl	(working copy)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/jetway/pa78vm5/dsdt.asl
===================================================================
--- src/mainboard/jetway/pa78vm5/dsdt.asl	(revision 6030)
+++ src/mainboard/jetway/pa78vm5/dsdt.asl	(working copy)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/kontron/kt690/dsdt.asl
===================================================================
--- src/mainboard/kontron/kt690/dsdt.asl	(revision 6030)
+++ src/mainboard/kontron/kt690/dsdt.asl	(working copy)
@@ -1308,7 +1308,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/technexion/tim5690/dsdt.asl
===================================================================
--- src/mainboard/technexion/tim5690/dsdt.asl	(revision 6030)
+++ src/mainboard/technexion/tim5690/dsdt.asl	(working copy)
@@ -1308,7 +1308,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
Index: src/mainboard/technexion/tim8690/dsdt.asl
===================================================================
--- src/mainboard/technexion/tim8690/dsdt.asl	(revision 6030)
+++ src/mainboard/technexion/tim8690/dsdt.asl	(working copy)
@@ -1308,7 +1308,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

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From stefan.reinauer at coresystems.de  Sun Nov  7 05:49:09 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 06 Nov 2010 21:49:09 -0700
Subject: [coreboot] [commit] r6030 - in trunk/src/superio:
 renesas/m3885x serverengines/pilot via/vt1211
In-Reply-To: <E1PEsJW-00072E-9H@ra.coresystems.de>
References: <E1PEsJW-00072E-9H@ra.coresystems.de>
Message-ID: <4CD62FC5.8060300@coresystems.de>

On 11/6/10 4:36 PM, repository service wrote:
> Modified: trunk/src/superio/serverengines/pilot/pilot_early_init.c
> ==============================================================================
> --- trunk/src/superio/serverengines/pilot/pilot_early_init.c	Sat Nov  6 01:57:19 2010	(r6029)
> +++ trunk/src/superio/serverengines/pilot/pilot_early_init.c	Sun Nov  7 00:36:49 2010	(r6030)
> @@ -29,7 +29,7 @@
>   */
>  static void pilot_early_init(device_t dev)
>  {
> -	unsigned port = dev >> 8;
> +	u16 port = dev >> 8;
>  
>  	print_debug("Using port: ");
>  	print_debug_hex16(port);
> @@ -55,6 +55,7 @@
>  	pnp_set_enable(PNP_DEV(port, 0x3), 0);
>  	pnp_exit_ext_func_mode(dev);
>  */
> +
>  	pnp_enter_ext_func_mode(dev);
>  	pnp_set_logical_device(PNP_DEV(port, 0x4));
>  	pnp_exit_ext_func_mode(dev);
> @@ -95,6 +96,7 @@
>  	pnp_enter_ext_func_mode(dev);
>  	pnp_set_enable(PNP_DEV(port, 0x7), 0);
>  	pnp_exit_ext_func_mode(dev);
> +
>  /*
>  	pnp_enter_ext_func_mode(dev);
>  	pnp_set_logical_device(PNP_DEV(port, 0x8));
I know I have been one of the biggest advocators of this kind of change.
However, I just recently got reminded that there are CPUs without I/O
operations. On these the IO range is usually memory mapped. So this kind
of trick with shifting dev and also assuming that a port I/O address
fits in 16bit is not always possible. Now, who knows if any such system
(except the dead alpha) exists that actually requires Super I/O drivers.
However, we should keep this in mind for other code (like the UART stuff)

Stefan



From stefan.reinauer at coresystems.de  Sun Nov  7 05:49:32 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 06 Nov 2010 21:49:32 -0700
Subject: [coreboot] [RFC]Static testing of our tree
In-Reply-To: <4CD5DE49.1020306@georgi-clan.de>
References: <4CD5DE49.1020306@georgi-clan.de>
Message-ID: <4CD62FDC.40908@coresystems.de>

On 11/6/10 4:01 PM, Patrick Georgi wrote:
> Hi,
>
> I'm currently thinking about various tests we could do on our tree to
> avoid regressions, not just in functionality (which is somewhat hard to
> do with all the board specific code we have), but also in style and
> practices.
Great idea!

> My first attempt is the attached script
> (lint-001-no-global-config-in-romstage), which checks for preprocessor
> symbols defined in mainboard romstages that are used elsewhere in the tree.
> As you can see from my other mails these days, I'm currently trying to
> cut down on these, by moving them to Kconfig.
> This has several reasons: First, it's necessary to have these symbols
> available globally when we start building the romstage in more separate
> compilation units (more on that below). Second, it's basically a second
> configuration mechanism besides the one we have, which is Kconfig.
>
> The script, when run from the top level directory of a coreboot
> checkout, emits the symbols that are defined in some romstage and are
> used elsewhere. No further information is given as the idea is to give a
> relatively quick overview on the tree, and fetching a list of files
> where those symbols are in use would be expensive.

Once you feel like this should go in the tree, I will gladly ack it.

> I propose to store this script (and similar ones) somewhere under util/,
> and hook them up in the Makefile ("make lint"?) and in the autobuilder
> (qa.coreboot.org), and have that report failure if they return any output.
Excellent!

> I don't propose to do this now - that would mean that the autobuilder
> reports errors for the next couple of weeks, but once we got the tree in
> shape that it passes the test of the script, it could go in and make
> sure that this issue doesn't come up again.

Please, if anyone can help with the task of cleaning this up so we can
add the check earlier, go ahead! It's a great way of improving coreboot
without having to know too much about hardware details!

> Another test could ensure that no mainboard code (and maybe even more
> parts of the tree later-on) #includes *.c files.
> That effort is useful because smaller compilation units make it easier
> to track down bugs, to validate code, and so on.
> If I ask you, could you tell (without looking) if init_cpus.c or
> fidvid.c should be included first on an AMD K8/Fam10 board? It shouldn't
> matter, but it does.
>
> It's init_cpus.c, by the way ;-)
This kind of stuff has been nasty ever since we were able to write RAM
init in C. And the small differences in the variants make the code
incredibly hard to maintain. Why does romstage.c have to cope with
init_cpus.c at all... CONFIG_CPU_AMD_K8 should let Makefile.inc
somewhere under the cpu/ directory know that we want this. Not each
individual mainboard.

That said, can we use the Makefile.inc file lists to fake #include
statements for romcc? This way we could get rid of the annoyance for
non-CAR boards, too. I wonder how complicated it would be to keep the
order intact so romcc does not choke. Maybe we can also fix/enhance
romcc to be a bit nicer to us...?

> External tools, such as lint, splint could also be added into that
> framework, should they be actually useful for our code (many aren't
> because of their assumptions on C coding within OS environments).
Should we go ahead and enable scan-build? It suffers from the same
problems, and it makes the build incredibly slow, but some of the stuff
it finds sure is interesting. (Maybe we should just manually run it and
post the results somewhere on qa.coreboot.org if people are interested
in fixing this stuff?

> This mail is marked RFC for a reason - what do you think?
This is the right path. Can't wait to see this go in the tree.

Stefan




From patrick at georgi-clan.de  Sun Nov  7 08:37:00 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 07 Nov 2010 08:37:00 +0100
Subject: [coreboot] [PATCH]Move SET_FIDVID* to Kconfig
In-Reply-To: <20101107012859.GC3983@ideafix.casa.ct>
References: <4CD5508D.8080900@georgi-clan.de>
	<20101107012859.GC3983@ideafix.casa.ct>
Message-ID: <4CD6571C.1080804@georgi-clan.de>

Am 07.11.2010 02:28, schrieb xdrudis:
> So far so good. I'm not sure FIDVID can be an option for fam10 .
> BKDG require it but I don't know if any fam10 cpu can boot without it.
It is an option right now (just in romstage.c) - maybe we should drop
some of these options on Fam10 completely (and their uses as well), but
for now all I want to do is move them to Kconfig.

>> SET_FIDVID_CORE0_ONLY was always 1, so again, I moved this to the CPU.
>>
> It isn't always 1. It's 0 for FAM10. But the patch is right as far as I 
> can see asleep as I am.
Indeed. I mixed that up in the explanation, but not in the code.

Thank you for looking into it, it's highly appreciated!


Patrick



From patrick at georgi-clan.de  Sun Nov  7 08:58:21 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 07 Nov 2010 08:58:21 +0100
Subject: [coreboot] [RFC]Static testing of our tree
In-Reply-To: <4CD62FDC.40908@coresystems.de>
References: <4CD5DE49.1020306@georgi-clan.de> <4CD62FDC.40908@coresystems.de>
Message-ID: <4CD65C1D.5070709@georgi-clan.de>

Am 07.11.2010 05:49, schrieb Stefan Reinauer:
>> I don't propose to do this now - that would mean that the autobuilder
>> reports errors for the next couple of weeks, but once we got the tree in
>> shape that it passes the test of the script, it could go in and make
>> sure that this issue doesn't come up again.
> Please, if anyone can help with the task of cleaning this up so we can
> add the check earlier, go ahead! It's a great way of improving coreboot
> without having to know too much about hardware details!
I improved the script to be location independent and to avoid a couple
of false positives (GPIO_DEV used to match FOO_GPIO_DEV).

The current list is:
CK804_MB_SETUP is defined in mainboard(s) and used elsewhere
DEFAULT_RCBA is defined in mainboard(s) and used elsewhere
DEVPRES1_CONFIG is defined in mainboard(s) and used elsewhere
DEVPRES_CONFIG is defined in mainboard(s) and used elsewhere
DIMM0 is defined in mainboard(s) and used elsewhere
DIMM1 is defined in mainboard(s) and used elsewhere
DIMM_MAP_LOGICAL is defined in mainboard(s) and used elsewhere
DQS_TRAIN_DEBUG is defined in mainboard(s) and used elsewhere
FIRST_CPU is defined in mainboard(s) and used elsewhere
IA32_PERF_STS is defined in mainboard(s) and used elsewhere
K8_ALLOCATE_IO_RANGE is defined in mainboard(s) and used elsewhere
K8_REV_F_SUPPORT_F0_F1_WORKAROUND is defined in mainboard(s) and used
elsewhere
MCP55_MB_SETUP is defined in mainboard(s) and used elsewhere
MCP55_PCI_E_X_0 is defined in mainboard(s) and used elsewhere
MCP55_PCI_E_X_1 is defined in mainboard(s) and used elsewhere
PAYLOAD_IS_SEABIOS is defined in mainboard(s) and used elsewhere
PLLMSRhi is defined in mainboard(s) and used elsewhere
PLLMSRlo is defined in mainboard(s) and used elsewhere
RCBA is defined in mainboard(s) and used elsewhere
RES_DEBUG is defined in mainboard(s) and used elsewhere
SATA_MAP is defined in mainboard(s) and used elsewhere
SB_VFSMAF is defined in mainboard(s) and used elsewhere
SECOND_CPU is defined in mainboard(s) and used elsewhere
SET_NB_CFG_54 is defined in mainboard(s) and used elsewhere
SYSTEM_TYPE is defined in mainboard(s) and used elsewhere
TOTAL_CPUS is defined in mainboard(s) and used elsewhere
UART_DLL is defined in mainboard(s) and used elsewhere
UART_DLM is defined in mainboard(s) and used elsewhere
UART_FCR is defined in mainboard(s) and used elsewhere
UART_IER is defined in mainboard(s) and used elsewhere
UART_IIR is defined in mainboard(s) and used elsewhere
UART_LCR is defined in mainboard(s) and used elsewhere
UART_LSR is defined in mainboard(s) and used elsewhere
UART_MCR is defined in mainboard(s) and used elsewhere
UART_MSR is defined in mainboard(s) and used elsewhere
UART_RBR is defined in mainboard(s) and used elsewhere
UART_SCR is defined in mainboard(s) and used elsewhere
UART_TBR is defined in mainboard(s) and used elsewhere
USE_COM1 is defined in mainboard(s) and used elsewhere
USE_COM2 is defined in mainboard(s) and used elsewhere
USE_VCP is defined in mainboard(s) and used elsewhere
gCom1Base is defined in mainboard(s) and used elsewhere
gCom2Base is defined in mainboard(s) and used elsewhere

(in a tree with the SET_FIDVID patch, so that group is already taken
care of)

>> It's init_cpus.c, by the way ;-)
> This kind of stuff has been nasty ever since we were able to write RAM
> init in C. And the small differences in the variants make the code
> incredibly hard to maintain. Why does romstage.c have to cope with
> init_cpus.c at all... CONFIG_CPU_AMD_K8 should let Makefile.inc
> somewhere under the cpu/ directory know that we want this. Not each
> individual mainboard.
That's part romcc, part newconfig legacy.
With romcc the intuitive way was to include .c-files at a central place,
and the build system was painful enough that no-one bothered to try to
autogenerate that central place from higher level data.

Once we have the config stuff nailed down, the only issue with romcc is
the order of the files - if we'd get function prototype support in
romcc, that would simplify that step a lot.
>From a quick glance it seems that romcc immediately flattens functions
as they come in and thus requires all functions to be present that are
used at that point, so that won't be a simple change.

I think we can live without that change.

> That said, can we use the Makefile.inc file lists to fake #include
> statements for romcc? This way we could get rid of the annoyance for
> non-CAR boards, too. I wonder how complicated it would be to keep the
> order intact so romcc does not choke. Maybe we can also fix/enhance
> romcc to be a bit nicer to us...?
I intend to work on that once CAR boards are done, so the order is:
- remove the #define config mechanism
- remove #include *.c from CAR romstages
- remove #include *.c from romcc romstages

>> External tools, such as lint, splint could also be added into that
>> framework, should they be actually useful for our code (many aren't
>> because of their assumptions on C coding within OS environments).
> Should we go ahead and enable scan-build? It suffers from the same
> problems, and it makes the build incredibly slow, but some of the stuff
> it finds sure is interesting. (Maybe we should just manually run it and
> post the results somewhere on qa.coreboot.org if people are interested
> in fixing this stuff?
Maybe a periodic run (every 10 revisions), similar to how doxygen is
handled? But that only makes sense if someone is actually interested in
taking them on.


Patrick



From xdrudis at tinet.cat  Sun Nov  7 09:06:48 2010
From: xdrudis at tinet.cat (xdrudis)
Date: Sun, 7 Nov 2010 09:06:48 +0100
Subject: [coreboot] [PATCH]Move SET_FIDVID* to Kconfig
In-Reply-To: <4CD6571C.1080804@georgi-clan.de>
References: <4CD5508D.8080900@georgi-clan.de>
	<20101107012859.GC3983@ideafix.casa.ct>
	<4CD6571C.1080804@georgi-clan.de>
Message-ID: <20101107080647.GA4135@ideafix.casa.ct>

On Sun, Nov 07, 2010 at 08:37:00AM +0100, Patrick Georgi wrote:
> Am 07.11.2010 02:28, schrieb xdrudis:
> It is an option right now (just in romstage.c) - maybe we should drop
> some of these options on Fam10 completely (and their uses as well), but
> for now all I want to do is move them to Kconfig.
> 

Sure. I didn't mean if had to be the same patch.

> 
> Thank you for looking into it, it's highly appreciated!
>

Thank you for your work (and to the others too).



From svn at coreboot.org  Sun Nov  7 09:15:13 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 09:15:13 +0100
Subject: [coreboot] [commit] r6031 - trunk/src/mainboard/intel/eagleheights
Message-ID: <E1PF0PB-00081o-H3@ra.coresystems.de>

Author: oxygene
Date: Sun Nov  7 09:15:13 2010
New Revision: 6031
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6031

Log:
Remove unused defines (UART_*)
All other uses of these symbols have their own (identical)
definitions.

abuild-tested and trivial

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/src/mainboard/intel/eagleheights/romstage.c

Modified: trunk/src/mainboard/intel/eagleheights/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/romstage.c	Sun Nov  7 00:36:49 2010	(r6030)
+++ trunk/src/mainboard/intel/eagleheights/romstage.c	Sun Nov  7 09:15:13 2010	(r6031)
@@ -40,24 +40,6 @@
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 



From r.marek at assembler.cz  Sun Nov  7 10:32:20 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Nov 2010 10:32:20 +0100
Subject: [coreboot] interesting request for serial console over enet
In-Reply-To: <AANLkTi=hwYw__ozW8AOmZ5aMsHiz_H5CX8LUX7Pb7oFx@mail.gmail.com>
References: <AANLkTi=hwYw__ozW8AOmZ5aMsHiz_H5CX8LUX7Pb7oFx@mail.gmail.com>
Message-ID: <4CD67224.8090500@assembler.cz>

Dne 5.11.2010 00:54, ron minnich napsal(a):
> someone I know from a Big telecom company just pushed an interesting
> idea on me.
>
> If coreboot+seabios would provide a bios service for serial console
> over enet, it would improve their life a lot. They could stop building
> cyclades boxes into their racks, and stop worrying about which
> mainboards had serial ports. I know that coreboot can now do console
> over enet; would be neat if seabios could provide a path for payloads
> to use it.

What about to write add-on to gPXE? Some simple handler for int10/int16 call 
sitting on it would certainly help (it can do DHCP/BOOT to get idea about GW)

I think they must have ARP there too. So the only part which is really  missing
is just the handler for the BIOS.

I think the current coreboot ethernet console has some issues if it is not on 
bus0. I guess I could change that a bit to provide ramstage support if this is 
the case.

Thanks,
Rudolf



From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:32 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:32 +0100
Subject: [coreboot] [patch 10/16] Add M2V pirq table
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124727.324618906@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:29 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:29 +0100
Subject: [coreboot] [patch 07/16] Add pointer to PCIe bridge documentation.
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124726.473364793@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:27 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:27 +0100
Subject: [coreboot] [patch 05/16] Add VT8237A id to vt8237r_early_smbus
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124725.900476304@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:28 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:28 +0100
Subject: [coreboot] [patch 06/16] Add VT8237A init to vt8237r_early_smbus
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124726.187356623@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:36 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:36 +0100
Subject: [coreboot] [patch 14/16] Since XP only implements parts of ACPI 2.0,
	it chokes on the TOM2 qword in the SSDT,
	which is present if a board uses k8acpi_write_vars.
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124728.476755141@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:22 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:22 +0100
Subject: [coreboot] [patch 00/16] ASUS M2V support (v3)
Message-ID: <20101107124622.274545089@yumi.uguu.de>

Updated patch series for ASUS M2V support.

I've tried breaking it up a bit more.

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:25 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:25 +0100
Subject: [coreboot] [patch 03/16] Introduce get_vt8237_lpc() function
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124725.363035490@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:23 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:23 +0100
Subject: [coreboot] [patch 01/16] Add VT8237A device id
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124724.773656834@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:33 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:33 +0100
Subject: [coreboot] [patch 11/16] Add M2V mptable
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124727.564773743@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:35 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:35 +0100
Subject: [coreboot] [patch 13/16] Add PIRQ_ROUTE support for vt8237.
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124728.132063662@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:24 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:24 +0100
Subject: [coreboot] [patch 02/16] Add VT8237A init
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124725.050376910@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:34 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:34 +0100
Subject: [coreboot] [patch 12/16] Add M2V basic ACPI support.
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124727.866289935@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:31 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:31 +0100
Subject: [coreboot] [patch 09/16] Add minimal ASUS M2V support
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124727.080137544@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:38 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:38 +0100
Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs should be
	marked as reserved in the E820 memory map,
	in case the OS wants to change the BARs.
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124729.095637758@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:26 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:26 +0100
Subject: [coreboot] [patch 04/16] Use get_vt8237_lpc() in
	vt8237_sb_enable_fid_vid().
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124725.620984807@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:37 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:37 +0100
Subject: [coreboot] [patch 15/16] Query cpu instead of using
	CONFIG_CPU_ADDR_BITS on AMD cpus
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124728.822979237@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Sun Nov  7 13:46:30 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 07 Nov 2010 13:46:30 +0100
Subject: [coreboot] [patch 08/16] Comment clarifications.
References: <20101107124622.274545089@yumi.uguu.de>
Message-ID: <20101107124726.800573205@yamamaya.is-a-geek.org>

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From svn at coreboot.org  Sun Nov  7 17:49:32 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 17:49:32 +0100
Subject: [coreboot] [commit] r6032 - in trunk/src/mainboard/ecs: . p6iwp-fe
Message-ID: <E1PF8Qu-0006IX-BW@ra.coresystems.de>

Author: uwe
Date: Sun Nov  7 17:49:31 2010
New Revision: 6032
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6032

Log:
ECS P6IWP-Fe: Fix typo, add missing license header.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/mainboard/ecs/Kconfig
   trunk/src/mainboard/ecs/p6iwp-fe/devicetree.cb

Modified: trunk/src/mainboard/ecs/Kconfig
==============================================================================
--- trunk/src/mainboard/ecs/Kconfig	Sun Nov  7 09:15:13 2010	(r6031)
+++ trunk/src/mainboard/ecs/Kconfig	Sun Nov  7 17:49:31 2010	(r6032)
@@ -23,7 +23,7 @@
 	prompt "Mainboard model"
 
 config BOARD_ECS_P6IWP_FE
-	bool "P6IWP-FE"
+	bool "P6IWP-Fe"
 
 endchoice
 

Modified: trunk/src/mainboard/ecs/p6iwp-fe/devicetree.cb
==============================================================================
--- trunk/src/mainboard/ecs/p6iwp-fe/devicetree.cb	Sun Nov  7 09:15:13 2010	(r6031)
+++ trunk/src/mainboard/ecs/p6iwp-fe/devicetree.cb	Sun Nov  7 17:49:31 2010	(r6032)
@@ -1,3 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Anders Jenbo <anders at jenbo.dk>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
 chip northbridge/intel/i82810		# Northbridge
   device lapic_cluster 0 on		# APIC cluster
     chip cpu/intel/socket_PGA370	# CPU



From scott at notabs.org  Sun Nov  7 18:06:40 2010
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 7 Nov 2010 11:06:40 -0600
Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs should
	bemarked as reserved in the E820 memory map,
	in case the OS wants to change the BARs.
In-Reply-To: <20101107124729.095637758@yamamaya.is-a-geek.org>
References: <20101107124622.274545089@yumi.uguu.de>
	<20101107124729.095637758@yamamaya.is-a-geek.org>
Message-ID: <C4BEBE9836EE4F428CF721D0BE43A2C6@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Tobias Diedrich
Sent: Sunday, November 07, 2010 06:47 AM
To: coreboot at coreboot.org
Cc: Rudolf Marek; Tobias Diedrich
Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs should bemarked as reserved in the E820 memory map,in case the OS
wants to change the BARs.

]Linux also needs the MMCONF area to be reserved either in E820 or
]as an ACPI motherboard resource or it will not enable MMCONFIG
]and the extended pcie configuration area will be unaccessible:
]
]This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
]resource flags to do this.
]I also added a new resource for the mapped bios rom area just below 4GB.
]I'm not sure if the choice for the index parameter of new_resource()
]is correct though.
]Note that the bios rom decode is enabled in
]src/southbridge/via/vt8237r/vt8237r_early_smbus.c
]for the whole 4MB area (even though the comment says 1MB).

Thank you Tobias. To be even more conservative, the upper 5 MB of the
first 4GB can be reserved for flash memory. This is because many LPC
flash chips place the jedec ID register of the boot device at address
ffbc0000.

Thanks,
Scott




From hackurx at gmail.com  Sun Nov  7 18:16:28 2010
From: hackurx at gmail.com (HacKurx)
Date: Sun, 7 Nov 2010 18:16:28 +0100
Subject: [coreboot] coreboot on dell mini 9
In-Reply-To: <AANLkTikS--9WJFubgA6hGv0spqCOvieBf-ZWnkjYyvZy@mail.gmail.com>
References: <AANLkTikS--9WJFubgA6hGv0spqCOvieBf-ZWnkjYyvZy@mail.gmail.com>
Message-ID: <AANLkTi=ya6XbLDhrJk=ioGfBqefxuLf19XabhFygikXY@mail.gmail.com>

Please can someone help me know if I can install coreboot on my Laptop?
-------------- next part --------------
flashrom v0.9.3-r1225 on Linux 2.6.35.6-48.fc14.i686 (i686), built with libpci 3.1.7, GCC 4.5.1 20100924 (Red Hat 4.5.1-4), little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 6 usecs, 778M loops per second, 10 myus = 12 us, 100 myus = 100 us, 1000 myus = 1086 us, 10000 myus = 10018 us, 24 myus = 26 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "Dell Inc."
DMI string system-product-name: "Inspiron 910"
DMI string system-version: "A05"
DMI string baseboard-manufacturer: "Dell Inc."
DMI string baseboard-product-name: "CN0J14"
DMI string baseboard-version: "A05"
DMI string chassis-type: "Portable"
Laptop detected via DMI
-------------- next part --------------
00:00.0 Host bridge [0600]: Intel Corporation Mobile 945GME Express Memory Controller Hub [8086:27ac] (rev 03)
	Subsystem: Dell Device [1028:02b0]
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: [e0] Vendor Specific Information: Len=09 <?>
	Kernel driver in use: agpgart-intel
00: 86 80 ac 27 06 01 90 20 03 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
40: 01 90 d1 fe 01 40 d1 fe 01 00 00 e0 01 80 d1 fe
50: 00 00 30 00 1b 00 00 00 00 00 00 00 00 00 00 00
60: 01 00 80 40 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 10 11 11 00 00 13 11 00 ff 03 00 00 40 1a 79 00
a0: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 09 01 00 00
e0: 09 00 09 71 23 25 4a a1 0e 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 05 00 10 00 00 00

00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile 945GME Express Integrated Graphics Controller [8086:27ae] (rev 03) (prog-if 00 [VGA controller])
	Subsystem: Dell Device [1028:02b0]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at f0000000 (32-bit, non-prefetchable) [size=512K]
	Region 1: I/O ports at 1800 [size=8]
	Region 2: Memory at d0000000 (32-bit, prefetchable) [size=256M]
	Region 3: Memory at f0300000 (32-bit, non-prefetchable) [size=256K]
	Expansion ROM at <unassigned> [disabled]
	Capabilities: [90] MSI: Enable- Count=1/1 Maskable- 64bit-
		Address: 00000000  Data: 0000
	Capabilities: [d0] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: i915
	Kernel modules: i915
00: 86 80 ae 27 07 00 90 00 03 00 00 03 00 00 80 00
10: 00 00 00 f0 01 18 00 00 08 00 00 d0 00 00 30 f0
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 90 00 00 00 00 00 00 00 07 01 00 00
40: 00 00 00 00 48 00 00 00 09 00 09 71 23 25 4a a1
50: 0e 00 30 00 1b 00 00 00 00 00 00 00 00 00 80 3f
60: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 05 d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 60 64 34 ff 00 00 00 86 0f 05 00 00 00 00 00

00:02.1 Display controller [0380]: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller [8086:27a6] (rev 03)
	Subsystem: Dell Device [1028:02b0]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Region 0: Memory at f0080000 (32-bit, non-prefetchable) [size=512K]
	Capabilities: [d0] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
00: 86 80 a6 27 07 00 90 00 03 00 80 03 00 00 80 00
10: 00 00 08 f0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 d0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 48 00 00 00 09 00 09 71 23 25 4a a1
50: 0e 00 30 00 1b 00 00 00 00 00 00 00 00 00 80 3f
60: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 60 64 34 ff 00 00 00 86 0f 05 00 00 00 00 00

00:1b.0 Audio device [0403]: Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8] (rev 02)
	Subsystem: Dell Device [1028:02b0]
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 44
	Region 0: Memory at f0540000 (64-bit, non-prefetchable) [size=16K]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [60] MSI: Enable+ Count=1/1 Maskable- 64bit+
		Address: 00000000fee0100c  Data: 4189
	Capabilities: [70] Express (v1) Root Complex Integrated Endpoint, MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
			ExtTag- RBE- FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 128 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 <64ns, L1 <1us
			ClockPM- Surprise- LLActRep- BwNot-
		LnkCtl:	ASPM Disabled; Disabled- Retrain- CommClk-
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
	Capabilities: [100 v1] Virtual Channel
		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
		Arb:	Fixed- WRR32- WRR64- WRR128-
		Ctrl:	ArbSelect=Fixed
		Status:	InProgress-
		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=01
			Status:	NegoPending- InProgress-
		VC1:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=1 ArbSelect=Fixed TC/VC=80
			Status:	NegoPending- InProgress-
	Capabilities: [130 v1] Root Complex Link
		Desc:	PortNumber=0f ComponentID=02 EltType=Config
		Link0:	Desc:	TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+
			Addr:	00000000fed1c000
	Kernel driver in use: HDA Intel
	Kernel modules: snd-hda-intel
00: 86 80 d8 27 06 04 10 00 02 00 03 04 10 00 00 00
10: 04 00 54 f0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 00 00
40: 03 00 00 03 00 00 00 00 00 00 00 00 00 80 00 00
50: 01 60 42 c8 00 00 00 00 00 00 00 00 00 00 00 00
60: 05 70 81 00 0c 10 e0 fe 00 00 00 00 89 41 00 00
70: 10 00 91 00 00 00 00 00 00 08 10 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1c.0 PCI bridge [0604]: Intel Corporation N10/ICH 7 Family PCI Express Port 1 [8086:27d0] (rev 02) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
	I/O behind bridge: 00003000-00003fff
	Memory behind bridge: f0100000-f01fffff
	Prefetchable memory behind bridge: 0000000040000000-00000000401fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
			ExtTag- RBE- FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us
			ClockPM- Surprise- LLActRep+ BwNot-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
			Slot #2, PowerLimit 6.500W; Interlock- NoCompl-
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet- LinkState-
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
		RootCap: CRSVisible-
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
	Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
		Address: fee0300c  Data: 4151
	Capabilities: [90] Subsystem: Dell Device [1028:02b0]
	Capabilities: [a0] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [100 v1] Virtual Channel
		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
		Arb:	Fixed+ WRR32- WRR64- WRR128-
		Ctrl:	ArbSelect=Fixed
		Status:	InProgress-
		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=01
			Status:	NegoPending- InProgress-
		VC1:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable- ID=0 ArbSelect=Fixed TC/VC=00
			Status:	NegoPending- InProgress-
	Capabilities: [180 v1] Root Complex Link
		Desc:	PortNumber=01 ComponentID=02 EltType=Config
		Link0:	Desc:	TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+
			Addr:	00000000fed1c001
	Kernel driver in use: pcieport
00: 86 80 d0 27 07 04 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 02 02 00 30 30 00 20
20: 10 f0 10 f0 01 40 11 40 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 04 00
40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 2c 11 01
50: 40 00 11 30 e0 a0 10 00 08 00 40 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 01 00 0c 30 e0 fe 51 41 00 00 00 00 00 00
90: 0d a0 00 00 28 10 b0 02 00 00 00 00 00 00 00 00
a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 80 00 11 c0 00 00 00 00
e0: 00 0f c7 00 06 07 08 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1c.1 PCI bridge [0604]: Intel Corporation N10/ICH 7 Family PCI Express Port 2 [8086:27d2] (rev 02) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
	I/O behind bridge: 00004000-00004fff
	Memory behind bridge: f0200000-f02fffff
	Prefetchable memory behind bridge: 0000000040200000-00000000403fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
			ExtTag- RBE- FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us
			ClockPM- Surprise- LLActRep+ BwNot-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
			Slot #3, PowerLimit 6.500W; Interlock- NoCompl-
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet- LinkState-
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
		RootCap: CRSVisible-
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
	Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
		Address: fee0300c  Data: 4159
	Capabilities: [90] Subsystem: Dell Device [1028:02b0]
	Capabilities: [a0] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [100 v1] Virtual Channel
		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
		Arb:	Fixed+ WRR32- WRR64- WRR128-
		Ctrl:	ArbSelect=Fixed
		Status:	InProgress-
		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=01
			Status:	NegoPending- InProgress-
		VC1:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable- ID=0 ArbSelect=Fixed TC/VC=00
			Status:	NegoPending- InProgress-
	Capabilities: [180 v1] Root Complex Link
		Desc:	PortNumber=02 ComponentID=02 EltType=Config
		Link0:	Desc:	TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+
			Addr:	00000000fed1c001
	Kernel driver in use: pcieport
00: 86 80 d2 27 07 04 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 03 03 00 40 40 00 20
20: 20 f0 20 f0 21 40 31 40 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 07 02 04 00
40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 2c 11 02
50: 40 00 11 30 e0 a0 18 00 08 00 40 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 01 00 0c 30 e0 fe 59 41 00 00 00 00 00 00
90: 0d a0 00 00 28 10 b0 02 00 00 00 00 00 00 00 00
a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 80 00 11 c0 00 00 00 00
e0: 00 0f c7 00 06 07 08 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1c.2 PCI bridge [0604]: Intel Corporation N10/ICH 7 Family PCI Express Port 3 [8086:27d4] (rev 02) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=04, subordinate=04, sec-latency=0
	I/O behind bridge: 00002000-00002fff
	Memory behind bridge: 40400000-407fffff
	Prefetchable memory behind bridge: 00000000f0600000-00000000f06fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
			ExtTag- RBE- FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us
			ClockPM- Surprise- LLActRep+ BwNot-
		LnkCtl:	ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
			Slot #4, PowerLimit 6.500W; Interlock- NoCompl-
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet- LinkState-
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
		RootCap: CRSVisible-
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
	Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
		Address: fee0300c  Data: 4161
	Capabilities: [90] Subsystem: Dell Device [1028:02b0]
	Capabilities: [a0] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [100 v1] Virtual Channel
		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
		Arb:	Fixed+ WRR32- WRR64- WRR128-
		Ctrl:	ArbSelect=Fixed
		Status:	InProgress-
		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=01
			Status:	NegoPending- InProgress-
		VC1:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable- ID=0 ArbSelect=Fixed TC/VC=00
			Status:	NegoPending- InProgress-
	Capabilities: [180 v1] Root Complex Link
		Desc:	PortNumber=03 ComponentID=02 EltType=Config
		Link0:	Desc:	TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+
			Addr:	00000000fed1c001
	Kernel driver in use: pcieport
00: 86 80 d4 27 07 04 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 04 04 00 20 20 00 20
20: 40 40 70 40 61 f0 61 f0 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 03 04 00
40: 10 80 41 01 c0 0f 00 00 00 00 11 00 11 2c 11 03
50: 43 00 11 30 e0 a0 20 00 08 00 40 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 01 00 0c 30 e0 fe 61 41 00 00 00 00 00 00
90: 0d a0 00 00 28 10 b0 02 00 00 00 00 00 00 00 00
a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 80 00 11 c0 00 00 00 00
e0: 00 0f c7 00 06 07 08 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1d.0 USB Controller [0c03]: Intel Corporation N10/ICH 7 Family USB UHCI Controller #1 [8086:27c8] (rev 02) (prog-if 00 [UHCI])
	Subsystem: Dell Device [1028:02b0]
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 23
	Region 4: I/O ports at 1820 [size=32]
	Kernel driver in use: uhci_hcd
00: 86 80 c8 27 05 00 80 02 02 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 21 18 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 00 00 00 00 00 00 00 00 05 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1d.1 USB Controller [0c03]: Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9] (rev 02) (prog-if 00 [UHCI])
	Subsystem: Dell Device [1028:02b0]
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 19
	Region 4: I/O ports at 1840 [size=32]
	Kernel driver in use: uhci_hcd
00: 86 80 c9 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 41 18 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1d.2 USB Controller [0c03]: Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca] (rev 02) (prog-if 00 [UHCI])
	Subsystem: Dell Device [1028:02b0]
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 18
	Region 4: I/O ports at 1860 [size=32]
	Kernel driver in use: uhci_hcd
00: 86 80 ca 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 61 18 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 03 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1d.3 USB Controller [0c03]: Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb] (rev 02) (prog-if 00 [UHCI])
	Subsystem: Dell Device [1028:02b0]
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin D routed to IRQ 16
	Region 4: I/O ports at 1880 [size=32]
	Kernel driver in use: uhci_hcd
00: 86 80 cb 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 81 18 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 00 00 00 00 00 00 00 00 07 04 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1d.7 USB Controller [0c03]: Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc] (rev 02) (prog-if 20 [EHCI])
	Subsystem: Dell Device [1028:02b0]
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 23
	Region 0: Memory at f0544000 (32-bit, non-prefetchable) [size=1K]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+
	Capabilities: [58] Debug port: BAR=1 offset=00a0
	Kernel driver in use: ehci_hcd
00: 86 80 cc 27 06 00 90 02 02 20 03 0c 00 00 00 00
10: 00 40 54 f0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 58 c2 c9 00 80 00 00 0a 00 a0 20 00 00 00 00
60: 20 20 ff 01 00 00 00 00 01 00 00 01 00 00 08 80
70: 00 00 df 3f 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 aa ff 00 ff 00 ff 00 20 00 00 88
e0: 00 00 00 00 db b6 6d 00 00 00 00 00 00 00 00 00
f0: 00 80 00 09 88 85 40 00 86 0f 02 00 06 17 02 20

00:1e.0 PCI bridge [0604]: Intel Corporation 82801 Mobile PCI Bridge [8086:2448] (rev e2) (prog-if 01 [Subtractive decode])
	Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Bus: primary=00, secondary=05, subordinate=05, sec-latency=32
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: fff00000-000fffff
	Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff
	Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [50] Subsystem: Dell Device [1028:02b0]
00: 86 80 48 24 04 00 10 00 e2 01 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 05 05 20 f0 00 80 22
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00
50: 0d 00 00 00 28 10 b0 02 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] (rev 02)
	Subsystem: Dell Device [1028:02b0]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: [e0] Vendor Specific Information: Len=0c <?>
	Kernel modules: leds-ss4200, iTCO_wdt, intel-rng
00: 86 80 b9 27 07 00 10 02 02 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
40: 01 10 00 00 80 00 00 00 81 11 00 00 10 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 80 80 80 80 90 00 00 00 80 80 80 80 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 0f 3f 81 06 7c 00 2d ff 7c 00 00 00 00 00
90: 69 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: b8 06 00 00 38 00 00 00 13 1c 0a 40 00 03 00 00
b0: 00 00 f0 00 00 00 00 00 00 00 09 08 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 33 22 11 00 67 45 00 00 cf ff 00 00 01 00 00 00
e0: 09 00 0c 10 b4 02 24 17 00 00 00 00 00 00 00 00
f0: 01 c0 d1 fe 00 00 00 00 86 0f 02 00 00 00 00 00

00:1f.1 IDE interface [0101]: Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df] (rev 02) (prog-if 8a [Master SecP PriP])
	Subsystem: Dell Device [1028:02b0]
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 19
	Region 0: I/O ports at 01f0 [size=8]
	Region 1: I/O ports at 03f4 [size=1]
	Region 2: I/O ports at 0170 [size=8]
	Region 3: I/O ports at 0374 [size=1]
	Region 4: I/O ports at 1810 [size=16]
	Kernel driver in use: ata_piix
00: 86 80 df 27 05 00 80 02 02 8a 01 01 00 00 00 00
10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00
20: 11 18 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00
40: 07 e3 00 40 00 00 00 00 01 00 01 00 00 00 00 00
50: 00 00 00 00 12 30 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1f.3 SMBus [0c05]: Intel Corporation N10/ICH 7 Family SMBus Controller [8086:27da] (rev 02)
	Subsystem: Dell Device [1028:02b0]
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin B routed to IRQ 19
	Region 4: I/O ports at 18a0 [size=32]
	Kernel modules: i2c-i801
00: 86 80 da 27 01 00 80 02 02 00 05 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: a1 18 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00
40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

02:00.0 System peripheral [0880]: JMicron Technology Corp. SD/MMC Host Controller [197b:2382]
	Subsystem: Dell Device [1028:02b0]
	Physical Slot: 1
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at f0100000 (32-bit, non-prefetchable) [size=256]
	[virtual] Expansion ROM at 40000000 [disabled] [size=64K]
	Capabilities: [a4] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [80] Express (v1) Endpoint, MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
		LnkCap:	Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 unlimited, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
	Capabilities: [94] MSI: Enable- Count=1/1 Maskable- 64bit-
		Address: fffffffc  Data: 0000
	Kernel driver in use: sdhci-pci
	Kernel modules: sdhci-pci
00: 7b 19 82 23 07 00 10 00 00 00 80 08 10 00 80 00
10: 00 00 10 f0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 a4 00 00 00 00 00 00 00 07 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 94 01 00 00 80 00 00 10 20 08 00 11 fc 03 01
90: 40 00 11 10 05 00 00 00 fc ff ff ff 00 00 00 00
a0: 00 00 00 00 01 80 03 00 08 00 00 00 46 11 47 88
b0: 20 30 88 7f fc 00 00 80 22 11 a2 00 00 00 00 00
c0: b3 8a 38 a0 03 45 02 02 00 00 00 08 1f 10 00 30
d0: 38 00 00 80 17 08 00 10 00 00 eb 00 00 00 e2 40
e0: 0f cc 06 00 59 19 ff ff 00 00 10 00 02 00 00 00
f0: 00 00 00 00 00 00 00 00 00 60 00 60 5d e9 18 80

02:00.2 SD Host controller [0805]: JMicron Technology Corp. Standard SD Host Controller [197b:2381] (prog-if 01)
	Subsystem: Dell Device [1028:02b0]
	Physical Slot: 1
	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at f0100400 (32-bit, non-prefetchable) [size=256]
	Capabilities: [a4] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [80] Express (v1) Endpoint, MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
		LnkCap:	Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 unlimited, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
	Capabilities: [94] MSI: Enable- Count=1/1 Maskable- 64bit-
		Address: fffffffc  Data: 0000
	Kernel modules: sdhci-pci
00: 7b 19 81 23 03 00 10 00 00 01 05 08 10 00 80 00
10: 00 04 10 f0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 a4 00 00 00 00 00 00 00 07 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 94 01 00 00 80 00 00 10 00 08 00 11 fc 03 01
90: 40 00 11 10 05 00 00 00 fc ff ff ff 00 00 00 00
a0: 00 00 00 00 01 80 03 00 08 00 00 00 46 11 47 88
b0: 20 30 88 7f fc 00 00 80 22 11 a2 00 00 00 00 00
c0: b3 8a 38 a0 03 45 02 02 00 00 00 08 1f 10 00 30
d0: 38 00 00 80 17 08 00 10 00 00 eb 00 00 00 e2 40
e0: 0f cc 06 00 59 19 ff ff 00 00 10 00 02 00 00 00
f0: 00 00 00 00 00 00 00 00 00 60 00 60 36 dd 18 80

02:00.3 System peripheral [0880]: JMicron Technology Corp. MS Host Controller [197b:2383]
	Subsystem: Dell Device [1028:02b0]
	Physical Slot: 1
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at f0100800 (32-bit, non-prefetchable) [size=256]
	Capabilities: [a4] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [80] Express (v1) Endpoint, MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
		LnkCap:	Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 unlimited, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
	Capabilities: [94] MSI: Enable- Count=1/1 Maskable- 64bit-
		Address: fffffffc  Data: 0000
	Kernel driver in use: jmb38x_ms
	Kernel modules: jmb38x_ms
00: 7b 19 83 23 07 00 10 00 00 00 80 08 10 00 80 00
10: 00 08 10 f0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 a4 00 00 00 00 00 00 00 07 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 94 01 00 00 80 00 00 10 00 08 00 11 fc 03 01
90: 40 00 11 10 05 00 00 00 fc ff ff ff 00 00 00 00
a0: 00 00 00 00 01 80 03 00 08 00 00 00 46 11 47 88
b0: 20 30 88 7f fc 00 00 80 22 11 a2 00 00 00 00 00
c0: b3 8a 38 a0 03 45 02 02 00 00 00 08 1f 10 00 30
d0: 38 00 00 80 17 08 00 10 00 00 eb 00 00 00 e2 40
e0: 0f cc 06 00 59 19 ff ff 00 00 10 00 02 00 00 00
f0: 00 00 00 00 00 00 00 00 00 60 00 60 80 3a 18 80

03:00.0 Network controller [0280]: Atheros Communications Inc. AR928X Wireless Network Adapter (PCI-Express) [168c:002a] (rev 01)
	Subsystem: Atheros Communications Inc. Device [168c:1000]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 17
	Region 0: Memory at f0200000 (64-bit, non-prefetchable) [size=64K]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
		Address: 00000000  Data: 0000
	Capabilities: [60] Express (v1) Legacy Endpoint, MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr+ UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 2.5GT/s, Width x1, ASPM unknown, Latency L0 <512ns, L1 <64us
			ClockPM- Surprise- LLActRep- BwNot-
		LnkCtl:	ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
	Capabilities: [90] MSI-X: Enable- Count=1 Masked-
		Vector table: BAR=0 offset=00000000
		PBA: BAR=0 offset=00000000
	Capabilities: [100 v1] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		AERCap:	First Error Pointer: 14, GenCap+ CGenEn- ChkCap+ ChkEn-
	Capabilities: [140 v1] Virtual Channel
		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
		Arb:	Fixed- WRR32- WRR64- WRR128-
		Ctrl:	ArbSelect=Fixed
		Status:	InProgress-
		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=01
			Status:	NegoPending- InProgress-
	Capabilities: [160 v1] Device Serial Number 00-00-00-00-00-00-00-00
	Kernel driver in use: ath9k
	Kernel modules: ath9k
00: 8c 16 2a 00 07 00 10 00 01 00 80 02 10 00 00 00
10: 04 00 20 f0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 8c 16 00 10
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00
40: 01 50 c2 5b 00 00 00 00 00 00 00 00 00 00 00 00
50: 05 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 90 11 00 c0 0c 04 05 10 20 0b 00 11 38 03 00
70: 48 00 11 10 00 00 00 00 c0 03 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8101E/RTL8102E PCI Express Fast Ethernet controller [10ec:8136] (rev 02)
	Subsystem: Dell Device [1028:02b0]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 43
	Region 0: I/O ports at 2000 [size=256]
	Region 2: Memory at f0610000 (64-bit, prefetchable) [size=4K]
	Region 4: Memory at f0600000 (64-bit, prefetchable) [size=64K]
	[virtual] Expansion ROM at f0620000 [disabled] [size=128K]
	Capabilities: [40] Power Management version 3
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
		Address: 00000000fee0300c  Data: 4179
	Capabilities: [70] Express (v2) Endpoint, MSI 01
		DevCap:	MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 4096 bytes
		DevSta:	CorrErr+ UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend-
		LnkCap:	Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us
			ClockPM+ Surprise- LLActRep- BwNot-
		LnkCtl:	ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
			ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis+
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB
	Capabilities: [ac] MSI-X: Enable- Count=2 Masked-
		Vector table: BAR=4 offset=00000000
		PBA: BAR=4 offset=00000800
	Capabilities: [cc] Vital Product Data
		Unknown small resource type 00, will not decode more.
	Capabilities: [100 v1] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr+ BadTLP+ BadDLLP- Rollover+ Timeout+ NonFatalErr+
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		AERCap:	First Error Pointer: 14, GenCap+ CGenEn- ChkCap+ ChkEn-
	Capabilities: [140 v1] Virtual Channel
		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
		Arb:	Fixed- WRR32- WRR64- WRR128-
		Ctrl:	ArbSelect=Fixed
		Status:	InProgress-
		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=01
			Status:	NegoPending- InProgress-
	Capabilities: [160 v1] Device Serial Number eb-06-00-00-ff-ff-00-00
	Kernel driver in use: r8169
	Kernel modules: r8169
00: ec 10 36 81 07 04 10 00 02 00 00 02 10 00 00 00
10: 01 20 00 00 00 00 00 00 0c 00 61 f0 00 00 00 00
20: 0c 00 60 f0 00 00 00 00 00 00 00 00 28 10 b0 02
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00
40: 01 50 c3 ff 08 00 00 00 00 00 00 00 00 00 00 00
50: 05 70 81 00 0c 30 e0 fe 00 00 00 00 79 41 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 10 ac 02 02 c1 8c 04 05 10 50 1b 00 11 3c 07 00
80: 43 01 11 10 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 11 cc 01 00
b0: 04 00 00 00 04 08 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 80
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

-------------- next part --------------
superiotool r6024
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e...
  Failed. Returned data: sid=0xff, id=0x00, rev=0x00
Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e...
  Failed. Returned data: sid=0xff, id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for VIA Super I/O at 0x3f0...
  PCI device 1106:0686 not found.
No Super I/O found

From towardsoss at gmail.com  Sun Nov  7 18:27:21 2010
From: towardsoss at gmail.com (Niklas Cholmkvist)
Date: Sun, 07 Nov 2010 19:27:21 +0200
Subject: [coreboot] Buying a new mainboard. Which vendors
	support	coreboot?
In-Reply-To: <20101107001433.GE25395@tarantulon.kollasch.net>
References: <1289080347.7473.14.camel@gnewsense>
	<20101107001433.GE25395@tarantulon.kollasch.net>
Message-ID: <1289150841.5865.17.camel@gnewsense>

Hi,

Jonathan wrote:
> What makes you think the open source ATI drivers aren't
> any good?  AFAICT they're doing pretty well these days.
Do you know any? Experiences are helpful for me.
-- 

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From svn at coreboot.org  Sun Nov  7 18:47:01 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 18:47:01 +0100
Subject: [coreboot] [commit] r6033 - in trunk/src/mainboard/gigabyte: .
	ma785gmt ma78gm
Message-ID: <E1PF9KX-0001Ge-RB@ra.coresystems.de>

Author: uwe
Date: Sun Nov  7 18:47:01 2010
New Revision: 6033
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6033

Log:
Fix a few incorrect GIGABYTE board names (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/mainboard/gigabyte/Kconfig
   trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
   trunk/src/mainboard/gigabyte/ma78gm/Kconfig

Modified: trunk/src/mainboard/gigabyte/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/Kconfig	Sun Nov  7 17:49:31 2010	(r6032)
+++ trunk/src/mainboard/gigabyte/Kconfig	Sun Nov  7 18:47:01 2010	(r6033)
@@ -30,9 +30,9 @@
 config BOARD_GIGABYTE_M57SLI
 	bool "GA-M57SLI-S4"
 config BOARD_GIGABYTE_GA785GMT
-	bool "MA785GMT"
+	bool "GA-MA785GMT-UD2H"
 config BOARD_GIGABYTE_MA78GM
-	bool "MA78GM-US2H"
+	bool "GA-MA78GM-US2H"
 
 endchoice
 

Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Sun Nov  7 17:49:31 2010	(r6032)
+++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Sun Nov  7 18:47:01 2010	(r6033)
@@ -40,7 +40,7 @@
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "Gigabyte GA785GMT"
+	default "GA-MA785GMT-UD2H"
 
 config MAX_CPUS
 	int

Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Sun Nov  7 17:49:31 2010	(r6032)
+++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Sun Nov  7 18:47:01 2010	(r6033)
@@ -40,7 +40,7 @@
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "GIGABYTE MA78GM"
+	default "GA-MA78GM-US2H"
 
 config MAX_CPUS
 	int



From svn at coreboot.org  Sun Nov  7 18:49:07 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 18:49:07 +0100
Subject: [coreboot] [commit] r6034 - in trunk/src/mainboard: arima/hdama
	ibm/e325 ibm/e326 tyan/s2882
Message-ID: <E1PF9MZ-0003kG-Gi@ra.coresystems.de>

Author: oxygene
Date: Sun Nov  7 18:49:05 2010
New Revision: 6034
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6034

Log:
FIRST_CPU, SECOND_CPU, TOTAL_CPUS are only used in one
other place, and that defines these symbols itself (and
identical, too). Drop them.

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/src/mainboard/arima/hdama/romstage.c
   trunk/src/mainboard/ibm/e325/romstage.c
   trunk/src/mainboard/ibm/e326/romstage.c
   trunk/src/mainboard/tyan/s2882/romstage.c

Modified: trunk/src/mainboard/arima/hdama/romstage.c
==============================================================================
--- trunk/src/mainboard/arima/hdama/romstage.c	Sun Nov  7 18:47:01 2010	(r6033)
+++ trunk/src/mainboard/arima/hdama/romstage.c	Sun Nov  7 18:49:05 2010	(r6034)
@@ -78,12 +78,6 @@
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

Modified: trunk/src/mainboard/ibm/e325/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e325/romstage.c	Sun Nov  7 18:47:01 2010	(r6033)
+++ trunk/src/mainboard/ibm/e325/romstage.c	Sun Nov  7 18:49:05 2010	(r6034)
@@ -75,12 +75,6 @@
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

Modified: trunk/src/mainboard/ibm/e326/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e326/romstage.c	Sun Nov  7 18:47:01 2010	(r6033)
+++ trunk/src/mainboard/ibm/e326/romstage.c	Sun Nov  7 18:49:05 2010	(r6034)
@@ -75,12 +75,6 @@
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

Modified: trunk/src/mainboard/tyan/s2882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2882/romstage.c	Sun Nov  7 18:47:01 2010	(r6033)
+++ trunk/src/mainboard/tyan/s2882/romstage.c	Sun Nov  7 18:49:05 2010	(r6034)
@@ -73,12 +73,6 @@
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"



From hackurx at gmail.com  Sun Nov  7 16:09:49 2010
From: hackurx at gmail.com (HacKurx)
Date: Sun, 7 Nov 2010 16:09:49 +0100
Subject: [coreboot] coreboot on dell mini 9
Message-ID: <AANLkTikS--9WJFubgA6hGv0spqCOvieBf-ZWnkjYyvZy@mail.gmail.com>

Hello,

Is it possible to install coreboot on dell mini9?
I enclose my command to see.
Thank you for your help and sorry for my English.



---------------------------------
[hackurx at Admin ~]$ su root
Mot de passe :
[root at Admin hackurx]# cd Dell-mini9/
[root at Admin Dell-mini9]# lspci -nnvvvxxxx > lscpi.log
[root at Admin Dell-mini9]# lspnp -vv > lspnp.log
Commande non trouv?e
[root at Admin Dell-mini9]# lsusb -vvv > lsusb.log
[root at Admin Dell-mini9]# superiotool -deV > superiotool.log
[root at Admin Dell-mini9]# inteltool -a > inteltool.log
[root at Admin Dell-mini9]# ectool > ectool.log
[root at Admin Dell-mini9]# msrtool > msrtool.log
msrtool 5566
Detected system linux: Linux with /dev/cpu/*/msr

Unable to detect a known target; can not decode any MSRs! (Use -t to force)
Please send a report or patch to coreboot at coreboot.org. Thanks for your help!

[root at Admin Dell-mini9]# msrtool -t > msrtool.log
msrtool: option requires an argument -- 't'
msrtool 5566
Detected system linux: Linux with /dev/cpu/*/msr

Unable to detect a known target; can not decode any MSRs! (Use -t to force)
Please send a report or patch to coreboot at coreboot.org. Thanks for your help!

[root at Admin Dell-mini9]# msrtool --t > msrtool.log
msrtool: invalid option -- '-'
msrtool: option requires an argument -- 't'
msrtool 5566
Detected system linux: Linux with /dev/cpu/*/msr

Unable to detect a known target; can not decode any MSRs! (Use -t to force)
Please send a report or patch to coreboot at coreboot.org. Thanks for your help!

[root at Admin Dell-mini9]# msrtool t > msrtool.log
msrtool 5566
Detected system linux: Linux with /dev/cpu/*/msr

Unable to detect a known target; can not decode any MSRs! (Use -t to force)
Please send a report or patch to coreboot at coreboot.org. Thanks for your help!

[root at Admin Dell-mini9]# msrtool -t > msrtool.log
msrtool: option requires an argument -- 't'
msrtool 5566
Detected system linux: Linux with /dev/cpu/*/msr

Unable to detect a known target; can not decode any MSRs! (Use -t to force)
Please send a report or patch to coreboot at coreboot.org. Thanks for your help!

[root at Admin Dell-mini9]# dmidecode > dmidecode.log
[root at Admin Dell-mini9]# biosdecode > biosdecode.log
[root at Admin Dell-mini9]# nvramtool -x > nvramtool.log
[root at Admin Dell-mini9]# dmesg > dmesg.log
[root at Admin Dell-mini9]# flashrom -V -p
internal:laptop=force_I_want_a_brick > flashrom_info.log
========================================================================
WARNING! You seem to be running flashrom on a laptop.
Laptops, notebooks and netbooks are difficult to support and we recommend
to use the vendor flashing utility. The embedded controller (EC) in these
machines often interacts badly with flashing.
See http://www.flashrom.org/Laptops for details.

If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Proceeding anyway because user specified laptop=force_I_want_a_brick
[root at Admin Dell-mini9]# flashrom -V -p
internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log
========================================================================
WARNING! You seem to be running flashrom on a laptop.
Laptops, notebooks and netbooks are difficult to support and we recommend
to use the vendor flashing utility. The embedded controller (EC) in these
machines often interacts badly with flashing.
See http://www.flashrom.org/Laptops for details.

If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Proceeding anyway because user specified laptop=force_I_want_a_brick
[root at Admin Dell-mini9]#
----------------------------------------
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From svn at coreboot.org  Sun Nov  7 19:20:35 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 19:20:35 +0100
Subject: [coreboot] [commit] r6035 - in trunk/src: include/device
	mainboard/asus/p2b southbridge/via/vt8237r
Message-ID: <E1PF9r1-0004jT-CL@ra.coresystems.de>

Author: ruik
Date: Sun Nov  7 19:20:32 2010
New Revision: 6035
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6035

Log:
This adds the VT8237A LPC device id and the pci_driver struct in
vt8237r_lpc.c

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Added:
   trunk/src/mainboard/asus/p2b/acpi_tables.c
   trunk/src/mainboard/asus/p2b/dsdt.asl
   trunk/src/mainboard/asus/p2b/romstage.c.orig
Modified:
   trunk/src/include/device/pci_ids.h
   trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c

Modified: trunk/src/include/device/pci_ids.h
==============================================================================
--- trunk/src/include/device/pci_ids.h	Sun Nov  7 18:49:05 2010	(r6034)
+++ trunk/src/include/device/pci_ids.h	Sun Nov  7 19:20:32 2010	(r6035)
@@ -1226,6 +1226,7 @@
 #define PCI_DEVICE_ID_VIA_K8T890CE_BR	0xb188
 #define PCI_DEVICE_ID_VIA_VT6420_SATA	0x3149
 #define PCI_DEVICE_ID_VIA_VT8237R_LPC	0x3227
+#define PCI_DEVICE_ID_VIA_VT8237A_LPC	0x3337
 #define PCI_DEVICE_ID_VIA_VT8237S_LPC	0x3372
 #define PCI_DEVICE_ID_VIA_VT8237_SATA	0x5372
 #define PCI_DEVICE_ID_VIA_VT8237_VLINK	0x287e

Added: trunk/src/mainboard/asus/p2b/acpi_tables.c
==============================================================================

Added: trunk/src/mainboard/asus/p2b/dsdt.asl
==============================================================================

Added: trunk/src/mainboard/asus/p2b/romstage.c.orig
==============================================================================

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c	Sun Nov  7 18:49:05 2010	(r6034)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c	Sun Nov  7 19:20:32 2010	(r6035)
@@ -543,6 +543,12 @@
 	.device	= PCI_DEVICE_ID_VIA_VT8237R_LPC,
 };
 
+static const struct pci_driver lpc_driver_a __pci_driver = {
+	.ops	= &vt8237r_lpc_ops_r,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_VT8237A_LPC,
+};
+
 static const struct pci_driver lpc_driver_s __pci_driver = {
 	.ops	= &vt8237r_lpc_ops_s,
 	.vendor	= PCI_VENDOR_ID_VIA,



From svn at coreboot.org  Sun Nov  7 19:20:55 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 19:20:55 +0100
Subject: [coreboot] [commit] r6036 - in trunk/src:
	mainboard/amd/serengeti_cheetah
	mainboard/gigabyte/ga_2761gxdk mainboard/gigabyte/m57sli
	mainboard/hp/dl145_g3 mainboard/iwill/dk8_htx
	mainboard/iwill/dk8s2 mainboard...
Message-ID: <E1PF9rL-00058Y-CD@ra.coresystems.de>

Author: oxygene
Date: Sun Nov  7 19:20:51 2010
New Revision: 6036
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6036

Log:
Move K8_ALLOCATE_IO_RANGE to Kconfig.

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
   trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
   trunk/src/mainboard/gigabyte/m57sli/Kconfig
   trunk/src/mainboard/gigabyte/m57sli/romstage.c
   trunk/src/mainboard/hp/dl145_g3/Kconfig
   trunk/src/mainboard/hp/dl145_g3/romstage.c
   trunk/src/mainboard/iwill/dk8_htx/romstage.c
   trunk/src/mainboard/iwill/dk8s2/romstage.c
   trunk/src/mainboard/iwill/dk8x/romstage.c
   trunk/src/mainboard/msi/ms7260/Kconfig
   trunk/src/mainboard/msi/ms7260/romstage.c
   trunk/src/mainboard/msi/ms9185/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
   trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
   trunk/src/mainboard/sunw/ultra40/Kconfig
   trunk/src/mainboard/sunw/ultra40/romstage.c
   trunk/src/mainboard/supermicro/h8dme/Kconfig
   trunk/src/mainboard/supermicro/h8dme/romstage.c
   trunk/src/mainboard/supermicro/h8dmr/Kconfig
   trunk/src/mainboard/supermicro/h8dmr/romstage.c
   trunk/src/mainboard/tyan/s2895/Kconfig
   trunk/src/mainboard/tyan/s2895/romstage.c
   trunk/src/mainboard/tyan/s2912/Kconfig
   trunk/src/mainboard/tyan/s2912/romstage.c
   trunk/src/northbridge/amd/amdk8/Kconfig
   trunk/src/northbridge/amd/amdk8/incoherent_ht.c

Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -1,8 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by incoherent_ht
-//#define K8_ALLOCATE_IO_RANGE 1
-
 //used by init_cpus and fidvid
 #define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -20,6 +20,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
 	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -21,9 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define K8_ALLOCATE_IO_RANGE 1
-
-
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/gigabyte/m57sli/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -24,6 +24,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
 	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define K8_ALLOCATE_IO_RANGE 1
-
-
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/hp/dl145_g3/Kconfig
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/hp/dl145_g3/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -22,6 +22,7 @@
 	select RAMINIT_SYSINFO
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/hp/dl145_g3/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -25,9 +25,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define K8_ALLOCATE_IO_RANGE 1
-
-
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -1,8 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by incoherent_ht
-//#define K8_ALLOCATE_IO_RANGE 1
-
 //used by init_cpus and fidvid
 #define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0

Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -1,8 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by incoherent_ht
-//#define K8_ALLOCATE_IO_RANGE 1
-
 //used by init_cpus and fidvid
 #define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0

Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -1,8 +1,5 @@
 #define SET_NB_CFG_54 1
 
-//used by incoherent_ht
-//#define K8_ALLOCATE_IO_RANGE 1
-
 //used by init_cpus and fidvid
 #define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0

Modified: trunk/src/mainboard/msi/ms7260/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7260/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/msi/ms7260/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -22,6 +22,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
 	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/msi/ms7260/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -24,7 +24,6 @@
 // #define DQS_TRAIN_DEBUG 1
 // #define RES_DEBUG 1
 
-#define K8_ALLOCATE_IO_RANGE 1
 #if CONFIG_LOGICAL_CPUS == 1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/msi/ms9185/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -25,9 +25,6 @@
 
 #define SET_NB_CFG_54 1
 
-//used by incoherent_ht
-//#define K8_ALLOCATE_IO_RANGE 1
-
 //used by init_cpus and fidvid
 #define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0

Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -23,6 +23,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
 	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define K8_ALLOCATE_IO_RANGE 1
-
-
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/sunw/ultra40/Kconfig
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/sunw/ultra40/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -17,6 +17,7 @@
 	select CK804_USE_NIC
 	select CK804_USE_ACI
 	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/sunw/ultra40/romstage.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/sunw/ultra40/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -1,6 +1,3 @@
-#define K8_ALLOCATE_IO_RANGE 1
-
-
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/supermicro/h8dme/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -23,6 +23,7 @@
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
 	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -16,9 +16,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define K8_ALLOCATE_IO_RANGE 1
-
-
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/supermicro/h8dmr/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -22,6 +22,7 @@
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
 	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define K8_ALLOCATE_IO_RANGE 1
-
-
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/tyan/s2895/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2895/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/tyan/s2895/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -18,6 +18,7 @@
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/tyan/s2895/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -1,6 +1,3 @@
-#define K8_ALLOCATE_IO_RANGE 1
-
-
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/mainboard/tyan/s2912/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/tyan/s2912/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -22,6 +22,7 @@
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
 	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/mainboard/tyan/s2912/romstage.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define K8_ALLOCATE_IO_RANGE 1
-
-
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #endif

Modified: trunk/src/northbridge/amd/amdk8/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/amdk8/Kconfig	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/northbridge/amd/amdk8/Kconfig	Sun Nov  7 19:20:51 2010	(r6036)
@@ -53,6 +53,10 @@
 	bool
 	default n
 
+config K8_ALLOCATE_IO_RANGE
+	bool
+	default n
+
 if K8_REV_F_SUPPORT
 
 config DIMM_DDR2

Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/incoherent_ht.c	Sun Nov  7 19:20:32 2010	(r6035)
+++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c	Sun Nov  7 19:20:51 2010	(r6036)
@@ -11,10 +11,6 @@
 	#define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
 #endif
 
-#ifndef K8_ALLOCATE_IO_RANGE
-	#define K8_ALLOCATE_IO_RANGE 0
-#endif
-
 // Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
 #ifndef K8_ALLOCATE_MMIO_RANGE
 	#define K8_ALLOCATE_MMIO_RANGE 0
@@ -720,7 +716,7 @@
 	uint8_t next_busn;
 	uint8_t ht_c_num;
 	uint8_t nodes;
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
 	unsigned next_io_base;
 #endif
 
@@ -740,7 +736,7 @@
 
 	next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
 
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
 	/* io range allocation */
 	tempreg = 0 | (((reg>>8) & 0x3) << 4 )|  (0x3<<12); //limit
 	pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);
@@ -753,7 +749,7 @@
 	for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
 		pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
 
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
 		/* io range allocation */
 		pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
 		pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
@@ -786,7 +782,7 @@
 			pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
 			next_busn+=0x3f+1;
 
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
 			/* io range allocation */
 			tempreg = nodeid | (linkn<<4) |  ((next_io_base+0x3)<<12); //limit
 			pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
@@ -810,7 +806,7 @@
 			pci_write_config32(dev, regpos, reg);
 		}
 
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
 		/* io range allocation */
 		for(i = 0; i< 4; i++) {
 			unsigned regpos;



From svn at coreboot.org  Sun Nov  7 19:25:12 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 19:25:12 +0100
Subject: [coreboot] [commit] r6037 - trunk/src/mainboard/asus/p2b
Message-ID: <E1PF9vU-0003o7-6T@ra.coresystems.de>

Author: ruik
Date: Sun Nov  7 19:25:11 2010
New Revision: 6037
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6037

Log:
Remove empty files added by accident. Sorry about that.
Rudolf

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Deleted:
   trunk/src/mainboard/asus/p2b/acpi_tables.c
   trunk/src/mainboard/asus/p2b/dsdt.asl
   trunk/src/mainboard/asus/p2b/romstage.c.orig



From r.marek at assembler.cz  Sun Nov  7 19:25:43 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Nov 2010 19:25:43 +0100
Subject: [coreboot] [patch 01/16] Add VT8237A device id
In-Reply-To: <20101107124724.773656834@yamamaya.is-a-geek.org>
References: <20101107124622.274545089@yumi.uguu.de>
	<20101107124724.773656834@yamamaya.is-a-geek.org>
Message-ID: <4CD6EF27.3010009@assembler.cz>

Acked-by: Rudolf Marek <r.marek at assembler.cz>

Checked in too.

Rudolf



From svn at coreboot.org  Sun Nov  7 19:28:34 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 19:28:34 +0100
Subject: [coreboot] [commit] r6038 - trunk/src/southbridge/via/vt8237r
Message-ID: <E1PF9yk-0000CQ-UE@ra.coresystems.de>

Author: ruik
Date: Sun Nov  7 19:28:34 2010
New Revision: 6038
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6038

Log:
This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.c
and vt8237r_lpc.c.

While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Modified:
   trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c
   trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c

Modified: trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c	Sun Nov  7 19:25:11 2010	(r6037)
+++ trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c	Sun Nov  7 19:28:34 2010	(r6038)
@@ -168,6 +168,75 @@
 
 }
 
+static void vt8237a_vlink_init(struct device *dev)
+{
+	u8 reg;
+	device_t devfun7;
+
+	devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+				  PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
+	/* No pairing NB was found. */
+	if (!devfun7)
+		return;
+
+	/*
+	 * This init code is valid only for the VT8237A! For different
+	 * sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different
+	 * init code is required.
+	 *
+	 * FIXME: This is based on vt8237r_vlink_init() in
+	 *        k8t890/k8t890_ctrl.c and modified to fit what the AMI
+	 *        BIOS on my M2V wrote to these registers (by looking
+	 *        at lspci -nxxx output).
+	 *        Works for me.
+	 */
+
+	/* disable auto disconnect */
+	reg = pci_read_config8(devfun7, 0x42);
+	reg &= ~0x4;
+	pci_write_config8(devfun7, 0x42, reg);
+
+	/* NB part setup */
+	pci_write_config8(devfun7, 0xb5, 0x88);
+	pci_write_config8(devfun7, 0xb6, 0x88);
+	pci_write_config8(devfun7, 0xb7, 0x61);
+
+	reg = pci_read_config8(devfun7, 0xb4);
+	reg |= 0x11;
+	pci_write_config8(devfun7, 0xb4, reg);
+
+	pci_write_config8(devfun7, 0xb0, 0x6);
+	pci_write_config8(devfun7, 0xb1, 0x1);
+
+	/* SB part setup */
+	pci_write_config8(dev, 0xb7, 0x50);
+	pci_write_config8(dev, 0xb9, 0x88);
+	pci_write_config8(dev, 0xba, 0x8a);
+	pci_write_config8(dev, 0xbb, 0x88);
+
+	reg = pci_read_config8(dev, 0xbd);
+	reg |= 0x3;
+	reg &= ~0x4;
+	pci_write_config8(dev, 0xbd, reg);
+
+	reg = pci_read_config8(dev, 0xbc);
+	reg &= ~0x7;
+	pci_write_config8(dev, 0xbc, reg);
+
+	pci_write_config8(dev, 0x48, 0x23);
+
+	/* enable auto disconnect, for STPGNT and HALT */
+	reg = pci_read_config8(devfun7, 0x42);
+	reg |= 0x7;
+	pci_write_config8(devfun7, 0x42, reg);
+}
+
 static void ctrl_enable(struct device *dev)
 {
 	/* Enable the 0:13 and 0:13.1. */
@@ -193,6 +262,12 @@
 		vt8237s_vlink_init(dev);
 	}
 
+	devsb = dev_find_device(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
+	if (devsb) {
+		vt8237a_vlink_init(dev);
+	}
+
 	/* Configure PCI1 and copy mirror registers from D0F3. */
 	vt8237_cfg(dev);
 	dump_south(dev);

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c	Sun Nov  7 19:25:11 2010	(r6037)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c	Sun Nov  7 19:28:34 2010	(r6038)
@@ -319,6 +319,58 @@
 	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 }
 
+static void vt8237a_init(struct device *dev)
+{
+	/*
+	 * FIXME: This is based on vt8237s_init() and the values the AMI
+	 *        BIOS on my M2V wrote to these registers (by loking
+	 *        at lspci -nxxx output).
+	 *        Works for me.
+	 */
+	u32 tmp;
+
+	/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
+	tmp = pci_read_config8(dev, 0x4f);
+	tmp |= 0x08;
+	pci_write_config8(dev, 0x4f, tmp);
+
+	/*
+	 * bit2: REQ5 as PCI request input - should be together with INTE-INTH.
+	 * bit5: usb power control lines as gpio
+	 */
+	pci_write_config8(dev, 0xe4, 0x24);
+	/*
+	 * Enable APIC wakeup from INTH
+	 * Enable SATA LED, disable special CPU Frequency Change -
+	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+	 */
+	pci_write_config8(dev, 0xe5, 0x69);
+
+	/* Reduce further the STPCLK/LDTSTP signal to 5us. */
+	pci_write_config8(dev, 0xec, 0x4);
+
+	/* Host Bus Power Management Control, maybe not needed */
+	pci_write_config8(dev, 0x8c, 0x5);
+
+	/* Enable HPET at VT8237R_HPET_ADDR. */
+	pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+
+	southbridge_init_common(dev);
+
+	/* Share INTE-INTH with INTA-INTD for simplicity */
+	pci_write_config8(dev, 0x46, 0x00);
+
+	/* FIXME: Intel needs more bit set for C2/C3. */
+
+	/*
+	 * Allow SLP# signal to assert LDTSTOP_L.
+	 * Will work for C3 and for FID/VID change.
+	 */
+	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+
+	dump_south(dev);
+}
+
 static void vt8237s_init(struct device *dev)
 {
 	u32 tmp;
@@ -537,6 +589,14 @@
 	.scan_bus		= scan_static_bus,
 };
 
+static const struct device_operations vt8237r_lpc_ops_a = {
+	.read_resources		= vt8237r_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= vt8237a_init,
+	.scan_bus		= scan_static_bus,
+};
+
 static const struct pci_driver lpc_driver_r __pci_driver = {
 	.ops	= &vt8237r_lpc_ops_r,
 	.vendor	= PCI_VENDOR_ID_VIA,
@@ -544,7 +604,7 @@
 };
 
 static const struct pci_driver lpc_driver_a __pci_driver = {
-	.ops	= &vt8237r_lpc_ops_r,
+	.ops	= &vt8237r_lpc_ops_a,
 	.vendor	= PCI_VENDOR_ID_VIA,
 	.device	= PCI_DEVICE_ID_VIA_VT8237A_LPC,
 };



From r.marek at assembler.cz  Sun Nov  7 19:29:13 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Nov 2010 19:29:13 +0100
Subject: [coreboot] [patch 02/16] Add VT8237A init
In-Reply-To: <20101107124725.050376910@yamamaya.is-a-geek.org>
References: <20101107124622.274545089@yumi.uguu.de>
	<20101107124725.050376910@yamamaya.is-a-geek.org>
Message-ID: <4CD6EFF9.4090903@assembler.cz>

Acked-by: Rudolf Marek <r.marek at assembler.cz>

Checked in too.

Rudolf



From svn at coreboot.org  Sun Nov  7 19:37:40 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 19:37:40 +0100
Subject: [coreboot] [commit] r6039 - trunk/src/southbridge/via/k8t890
Message-ID: <E1PFA7Y-0005Ww-LU@ra.coresystems.de>

Author: ruik
Date: Sun Nov  7 19:37:39 2010
New Revision: 6039
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6039

Log:
Add pointer to public PCIe bridge documentation on
http://linux.via.com.tw/ as VX800 seems to be compatible.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Modified:
   trunk/src/southbridge/via/k8t890/k8t890_pcie.c

Modified: trunk/src/southbridge/via/k8t890/k8t890_pcie.c
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890_pcie.c	Sun Nov  7 19:28:34 2010	(r6038)
+++ trunk/src/southbridge/via/k8t890/k8t890_pcie.c	Sun Nov  7 19:37:39 2010	(r6039)
@@ -24,6 +24,12 @@
 #include <device/pci_ids.h>
 #include "k8t890.h"
 
+/*
+ * Note:
+ * The pcie bridges are similar to the VX800 ones documented at
+ * http://linux.via.com.tw/
+ */
+
 static void peg_init(struct device *dev)
 {
 	u8 reg;



From r.marek at assembler.cz  Sun Nov  7 19:38:04 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Nov 2010 19:38:04 +0100
Subject: [coreboot] [patch 07/16] Add pointer to PCIe bridge
	documentation.
In-Reply-To: <20101107124726.473364793@yamamaya.is-a-geek.org>
References: <20101107124622.274545089@yumi.uguu.de>
	<20101107124726.473364793@yamamaya.is-a-geek.org>
Message-ID: <4CD6F20C.1040602@assembler.cz>

Acked-by: Rudolf Marek <r.marek at assembler.cz>
And commited.

R.



From svn at coreboot.org  Sun Nov  7 19:46:14 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 19:46:14 +0100
Subject: [coreboot] [commit] r6040 - trunk/src/southbridge/via/vt8237r
Message-ID: <E1PFAFq-0003DP-Bc@ra.coresystems.de>

Author: ruik
Date: Sun Nov  7 19:46:13 2010
New Revision: 6040
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6040

Log:
Instead of duplicating the pci_locate_device calls multiple times,
add a get_vt8237_lpc() function.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>

Acked-by: Rudolf Marek <r.marek at assembler.cz>

Modified:
   trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sun Nov  7 19:37:39 2010	(r6039)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sun Nov  7 19:46:13 2010	(r6040)
@@ -134,6 +134,21 @@
 
 #define PSONREADY_TIMEOUT 0x7fffffff
 
+static device_t get_vt8237_lpc(void)
+{
+	device_t dev;
+
+	/* Power management controller */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+	if (dev != PCI_DEV_INVALID)
+		return dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+	return dev;
+}
+
 /**
  * Enable the SMBus on VT8237R-based systems.
  */
@@ -143,15 +158,9 @@
 	int loops;
 
 	/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			die("Power management controller not found\n");
-	}
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		die("Power management controller not found\n");
 
 	/* Make sure the RTC power well is up before touching smbus. */
 	loops = 0;
@@ -292,15 +301,9 @@
 	device_t dev;
 
 	/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			return;
-	}
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		return;
 
 	/* ROM decode last 1MB FFC00000 - FFFFFFFF. */
 	pci_write_config8(dev, 0x41, 0x7f);
@@ -316,15 +319,9 @@
 	print_debug("IN TEST WAKEUP\n");
 
 	/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			die("Power management controller not found\n");
-	}
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		die("Power management controller not found\n");
 
 	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
 	pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);



From svn at coreboot.org  Sun Nov  7 19:51:14 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 19:51:14 +0100
Subject: [coreboot] [commit] r6041 - trunk/src/southbridge/via/vt8237r
Message-ID: <E1PFAKg-0004Dj-Bu@ra.coresystems.de>

Author: ruik
Date: Sun Nov  7 19:51:13 2010
New Revision: 6041
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6041

Log:
Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid() too.
I broke this out into a seperate part to keep the other half as
straight-forward as possible.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Modified:
   trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sun Nov  7 19:46:13 2010	(r6040)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sun Nov  7 19:51:13 2010	(r6041)
@@ -244,17 +244,15 @@
 void vt8237_sb_enable_fid_vid(void)
 {
 	device_t dev, devctl;
+	u16 devid;
 
 	/* Power management controller */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-		if (dev == PCI_DEV_INVALID)
-			return;
+	dev = get_vt8237_lpc();
+	if (dev == PCI_DEV_INVALID)
+		return;
 
+	devid = pci_read_config16(dev, PCI_DEVICE_ID);
+	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) {
 		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 					   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
 



From r.marek at assembler.cz  Sun Nov  7 19:52:04 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Nov 2010 19:52:04 +0100
Subject: [coreboot] [patch 04/16] Use get_vt8237_lpc()
	in	vt8237_sb_enable_fid_vid().
In-Reply-To: <20101107124725.620984807@yamamaya.is-a-geek.org>
References: <20101107124622.274545089@yumi.uguu.de>
	<20101107124725.620984807@yamamaya.is-a-geek.org>
Message-ID: <4CD6F554.80408@assembler.cz>

Acked-by: Rudolf Marek <r.marek at assembler.cz>

And also commited as 6041.

R.



From xdrudis at tinet.cat  Sun Nov  7 19:56:57 2010
From: xdrudis at tinet.cat (xdrudis)
Date: Sun, 7 Nov 2010 19:56:57 +0100
Subject: [coreboot] coreboot on dell mini 9
In-Reply-To: <AANLkTi=ya6XbLDhrJk=ioGfBqefxuLf19XabhFygikXY@mail.gmail.com>
References: <AANLkTikS--9WJFubgA6hGv0spqCOvieBf-ZWnkjYyvZy@mail.gmail.com>
	<AANLkTi=ya6XbLDhrJk=ioGfBqefxuLf19XabhFygikXY@mail.gmail.com>
Message-ID: <20101107185657.GA9900@ideafix.casa.ct>

On Sun, Nov 07, 2010 at 06:16:28PM +0100, HacKurx wrote:
> Please can someone help me know if I can install coreboot on my Laptop?

I haven't looked at the components, but I hear that in general laptops 
are very difficult. I guess it has improved with usb console but still, 
assuming that the chips in your laptop were supported, will it be possible
for you to replace or reflash the flash chip with the firmware in case the first
attempt fails and it doesn't boot ? It's easier in a desktop PC than
a laptop. 



From svn at coreboot.org  Sun Nov  7 19:57:12 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 19:57:12 +0100
Subject: [coreboot] [commit] r6042 - trunk/src/southbridge/via/vt8237r
Message-ID: <E1PFAQS-0003eP-52@ra.coresystems.de>

Author: ruik
Date: Sun Nov  7 19:57:10 2010
New Revision: 6042
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6042

Log:
This adds the VT8237A LPC pci_locate_device call in vt8237r_early_smbus.c
Depends on the "Introduce get_vt8237_lpc() function" patch.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Modified:
   trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sun Nov  7 19:51:13 2010	(r6041)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sun Nov  7 19:57:10 2010	(r6042)
@@ -146,6 +146,11 @@
 
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 				PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+	if (dev != PCI_DEV_INVALID)
+		return dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);
 	return dev;
 }
 



From r.marek at assembler.cz  Sun Nov  7 19:58:34 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Nov 2010 19:58:34 +0100
Subject: [coreboot] [patch 05/16] Add VT8237A id to vt8237r_early_smbus
In-Reply-To: <20101107124725.900476304@yamamaya.is-a-geek.org>
References: <20101107124622.274545089@yumi.uguu.de>
	<20101107124725.900476304@yamamaya.is-a-geek.org>
Message-ID: <4CD6F6DA.8030100@assembler.cz>

Acked-by: Rudolf Marek <r.marek at assembler.cz>
As 6042.

Rudolf



From scott at notabs.org  Sun Nov  7 20:05:21 2010
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 7 Nov 2010 13:05:21 -0600
Subject: [coreboot] [patch 15/16] Query cpu instead of
	usingCONFIG_CPU_ADDR_BITS on AMD cpus
In-Reply-To: <20101107124728.822979237@yamamaya.is-a-geek.org>
References: <20101107124622.274545089@yumi.uguu.de>
	<20101107124728.822979237@yamamaya.is-a-geek.org>
Message-ID: <0DEBDF99CA6F448BB630D301E3FBEBAC@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Tobias Diedrich
Sent: Sunday, November 07, 2010 06:47 AM
To: coreboot at coreboot.org
Cc: Rudolf Marek; Tobias Diedrich
Subject: [coreboot] [patch 15/16] Query cpu instead of usingCONFIG_CPU_ADDR_BITS on AMD cpus

]This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up the
]Linux kernel, which was previously complaining that the MTRR setup
]is wrong, if the cpu supports more than CONFIG_CPU_ADDR_BITS bits of
]address space.
]
]dmesg without patch:
]|MTRR variable ranges enabled:
]|  0 base 0000000000 mask 0F00000000 write-back
]|  1 base 0100000000 mask 0FC0000000 write-back
]|  2 base 00E0000000 mask 0FE0000000 uncachable
]|  3 disabled
]|  4 disabled
]|  5 disabled
]|  6 disabled
]|  7 disabled
]|mtrr: your BIOS has configured an incorrect mask, fixing it.
]
]dmesg with patch:
]|MTRR variable ranges enabled:
]|  0 base 0000000000 mask FF00000000 write-back
]|  1 base 0100000000 mask FFC0000000 write-back
]|  2 base 00E0000000 mask FFE0000000 uncachable
]|  3 disabled
]|  4 disabled
]|  5 disabled
]|  6 disabled
]|  7 disabled
]
]Shamelessly copied from Linux arch/x86/kernel/cpu/mtrr/main.c
]
]Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
]
]---
]
]Index: src/cpu/amd/mtrr/amd_mtrr.c
]===================================================================
]--- src/cpu/amd/mtrr/amd_mtrr.c	(revision 5985)
]+++ src/cpu/amd/mtrr/amd_mtrr.c	(working copy)
]@@ -1,5 +1,6 @@
] #include <console/console.h>
] #include <device/device.h>
]+#include <arch/cpu.h>
] #include <cpu/x86/mtrr.h>
] #include <cpu/amd/mtrr.h>
] #include <cpu/x86/cache.h>
]@@ -175,11 +176,13 @@
] 
] 	enable_cache();
] 
]-	/* FIXME we should probably query the cpu for this
]-	 * but so far this is all any recent AMD cpu has supported.
]-	 */
] 	address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
] 
]+	/* AMD specific MSR to query number of address bits */
]+	if (cpuid_eax(0x80000000) >= 0x80000008) {
]+		address_bits = cpuid_eax(0x80000008) & 0xff;
]+	}
]+
] 	/* Now that I have mapped what is memory and what is not
] 	 * Setup the mtrrs so we can cache the memory.
] 	 */


Thank you Tobias. It also fixes a Win7 checked build BSOD when kconfig
CPU_ADDR_BITS is set too small. Tested with Kino-780AM2 by setting
CPU_ADDR_BITS to 36 and confirming 48 bits are set in msr 201.

Acked-by: Scott Duplichan <scott at notabs.org>

It looks like Intel eventually adopted this cpuid feature, though
I have no way to test the Intel implementation.

One comment could be clarified:

- /* AMD specific MSR to query number of address bits */
+ /* AMD specific cpuid function to query number of address bits */

Thanks,
Scott





From harald.gutmann at gmx.net  Sun Nov  7 20:12:41 2010
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Sun, 7 Nov 2010 20:12:41 +0100
Subject: [coreboot] MCP55 Mac Address copying/change
In-Reply-To: <20101105164843.GD25395@tarantulon.kollasch.net>
References: <201011041855.28624.harald.gutmann@gmx.net>
	<20101105164843.GD25395@tarantulon.kollasch.net>
Message-ID: <201011072012.41727.harald.gutmann@gmx.net>

On Friday 05 November 2010 17:48:43 Jonathan A. Kollasch wrote:
> Look at the romstrap of the vendor-provided firmware update image for
> a nvidia board.  You'll find it doesn't contain your board's address.

I know that point, and it is definitely a good idea to solve that part via 
flashrom. Also as I just found a tread on the LinuxBios ML [1] which discussed 
that topic, and the main point why it would be a better solution to treat this 
in flashrom is, that you can use the same image for different mainboards without 
compiling the image for every single board.

Just for my personal interest, could someone explain me what actually is 
called romstrap? Google was not really informative on that point, except some 
"romstrap overrides" during graphic card bios flashing.


Further the question arises for me if following the romstrap pointer would 
also work on proprietary bios, or if this could only be managed correctly with 
coreboot images?

Otherwise I'd suggest to create a flashrom option which copies the actual MAC 
on flashing the new image.

> IMO this issue would be best solved in the vicinity of flashrom.
> 
> It's trivial to follow the romstrap pointers and copy over
> the address.
> 
> Attached is a utility to do just that.
Thanks you for the utility, there is also one (perl script) in the bugtracker  
(#135) [2] which does a similar operation, but with a supplied mac.
I think that both utilities are not "perfect", because as I've seen yours 
needs a second rom image which contains the right mac, and on the script in 
the bugtracker you need to supply it. 

Personally I'd prefer to read the actual running mac from the system. (Which 
could be done by your utility - but needs a full read cycle of the bios flash.)
Is there any fast method to read the onboards NIC mac address "faster"?

> 	Jonathan Kollasch

Kind regards,
Harald Gutmann


[1] http://www.mail-archive.com/linuxbios at linuxbios.org/msg11462.html
[2] http://tracker.coreboot.org/trac/coreboot/attachment/ticket/135/change-
mcp55-mac.pl



From svn at coreboot.org  Sun Nov  7 20:17:19 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 20:17:19 +0100
Subject: [coreboot] [commit] r6043 - trunk/src/southbridge/via/vt8237r
Message-ID: <E1PFAjv-0003wK-1g@ra.coresystems.de>

Author: ruik
Date: Sun Nov  7 20:17:18 2010
New Revision: 6043
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6043

Log:
Depends on the "Introduce get_vt8237_lpc() function" and
"Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid()" patches.

This adds VT8237A specific VLINK/LPC init in vt8237r_early_smbus.c
I ran some tests and apparently both the

|			/* So the chip knows we are on AMD. */
|			pci_write_config8(devctl, 0x7c, 0x7f);

and

|	/*
|	 * Allow SLP# signal to assert LDTSTOP_L.
|	 * Will work for C3 and for FID/VID change.
|	 */
|	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);

in vt8237r_early_smbus.c are needed on VT8237A, otherwise I get a (non-fatal)
fid/vid change error on boot.

While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Modified:
   trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sun Nov  7 19:57:10 2010	(r6042)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sun Nov  7 20:17:18 2010	(r6043)
@@ -257,19 +257,30 @@
 		return;
 
 	devid = pci_read_config16(dev, PCI_DEVICE_ID);
-	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) {
-		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
 
-		if (devctl == PCI_DEV_INVALID)
-			return;
+	/* generic setup */
+
+	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
+	pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
+
+	/* Enable ACPI accessm RTC signal gated with PSON. */
+	pci_write_config8(dev, 0x81, 0x84);
+
+	/* chipset-specific parts */
 
-		/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
-		pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
+	/* VLINK: FIXME: can we drop the devid check and just look for the VLINK device? */
+	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC ||
+	    devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) {
+		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+					   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
 
-		/* Enable ACPI accessm RTC signal gated with PSON. */
-		pci_write_config8(dev, 0x81, 0x84);
+		if (devctl != PCI_DEV_INVALID) {
+			/* So the chip knows we are on AMD. */
+			pci_write_config8(devctl, 0x7c, 0x7f);
+		}
+	}
 
+	if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) {
 		/*
 		 * Allow SLP# signal to assert LDTSTOP_L.
 		 * Will work for C3 and for FID/VID change.
@@ -280,17 +291,10 @@
 		/* Reduce further the STPCLK/LDTSTP signal to 5us. */
 		pci_write_config8(dev, 0xec, 0x4);
 
-		/* So the chip knows we are on AMD. */
-		pci_write_config8(devctl, 0x7c, 0x7f);
-
 		return;
 	}
 
-	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
-	pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
-
-	/* Enable ACPI accessm RTC signal gated with PSON. */
-	pci_write_config8(dev, 0x81, 0x84);
+	/* VT8237R and VT8237A */
 
 	/*
 	 * Allow SLP# signal to assert LDTSTOP_L.



From r.marek at assembler.cz  Sun Nov  7 20:17:32 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Nov 2010 20:17:32 +0100
Subject: [coreboot] [patch 06/16] Add VT8237A init to vt8237r_early_smbus
In-Reply-To: <20101107124726.187356623@yamamaya.is-a-geek.org>
References: <20101107124622.274545089@yumi.uguu.de>
	<20101107124726.187356623@yamamaya.is-a-geek.org>
Message-ID: <4CD6FB4C.6090004@assembler.cz>

Acked-by: Rudolf Marek <r.marek at assembler.cz>

As 6043.

Rudolf



From svn at coreboot.org  Sun Nov  7 20:27:46 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 20:27:46 +0100
Subject: [coreboot] [commit] r6044 - trunk/src/mainboard/asus
Message-ID: <E1PFAu2-00011g-C9@ra.coresystems.de>

Author: ruik
Date: Sun Nov  7 20:27:45 2010
New Revision: 6044
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6044

Log:
This adds the m2v directory and necessary files to src/mainboards/asus and
adjusts the Kconfig.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Modified:
   trunk/src/mainboard/asus/Kconfig

Modified: trunk/src/mainboard/asus/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/Kconfig	Sun Nov  7 20:17:18 2010	(r6043)
+++ trunk/src/mainboard/asus/Kconfig	Sun Nov  7 20:27:45 2010	(r6044)
@@ -25,6 +25,8 @@
 	bool "A8N-E"
 config BOARD_ASUS_A8V_E_SE
 	bool "A8V-E SE"
+config BOARD_ASUS_M2V
+	bool "M2V"
 config BOARD_ASUS_M2V_MX_SE
 	bool "M2V-MX SE"
 config BOARD_ASUS_M4A785M
@@ -50,6 +52,7 @@
 
 source "src/mainboard/asus/a8n_e/Kconfig"
 source "src/mainboard/asus/a8v-e_se/Kconfig"
+source "src/mainboard/asus/m2v/Kconfig"
 source "src/mainboard/asus/m2v-mx_se/Kconfig"
 source "src/mainboard/asus/m4a785-m/Kconfig"
 source "src/mainboard/asus/mew-am/Kconfig"



From r.marek at assembler.cz  Sun Nov  7 20:28:49 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Nov 2010 20:28:49 +0100
Subject: [coreboot] [patch 09/16] Add minimal ASUS M2V support
In-Reply-To: <20101107124727.080137544@yamamaya.is-a-geek.org>
References: <20101107124622.274545089@yumi.uguu.de>
	<20101107124727.080137544@yamamaya.is-a-geek.org>
Message-ID: <4CD6FDF1.8080406@assembler.cz>

Looks good.

Acked-by: Rudolf Marek <r.marek at assembler.cz>

In as 6044.

Rudolf



From marcj303 at gmail.com  Sun Nov  7 21:02:52 2010
From: marcj303 at gmail.com (Marc Jones)
Date: Sun, 7 Nov 2010 13:02:52 -0700
Subject: [coreboot] [PATCH] ASL should report AMD SB600/SB700 RTC as not
 PIIX4 compatible
In-Reply-To: <C1B279D76F3742FF985A073E46F24E58@m3a78>
References: <C1B279D76F3742FF985A073E46F24E58@m3a78>
Message-ID: <AANLkTinpeduZ9WHCiEGvrfLSLW7=5vWRD1F6UY9PjQfL@mail.gmail.com>

On Sat, Nov 6, 2010 at 9:43 PM, Scott Duplichan <scott at notabs.org> wrote:
> DSDT.asl should not report the AMD SB600/SB700 RTC as Intel PIIX4
> compatible. The extended cmos is accessed differently for AMD
> and Intel RTCs. Not sure what if any OS cares about this distinction,
> but non-Intel compatible seems like a safer way to report the AMD RTC.
> Tested with Win7 on Mahogany_fam10 and kino-780am2-fam10.
>
> Signed-off-by: Scott Duplichan <scott at notabs.org>

Acked-by: Marc Jones <marcj303 at gmail.com>


-- 
http://se-eng.com



From svn at coreboot.org  Sun Nov  7 21:08:46 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 21:08:46 +0100
Subject: [coreboot] [commit] r6045 - trunk/src/mainboard/asus/m2v
Message-ID: <E1PFBXi-0003R3-IL@ra.coresystems.de>

Author: ruik
Date: Sun Nov  7 21:08:45 2010
New Revision: 6045
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6045

Log:
Should be part of 6044. I forgot to add the directory :/

This adds the m2v directory and necessary files to src/mainboards/asus and
adjusts the Kconfig.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Added:
   trunk/src/mainboard/asus/m2v/
   trunk/src/mainboard/asus/m2v/Kconfig
   trunk/src/mainboard/asus/m2v/chip.h
   trunk/src/mainboard/asus/m2v/cmos.layout
   trunk/src/mainboard/asus/m2v/devicetree.cb
   trunk/src/mainboard/asus/m2v/mainboard.c
   trunk/src/mainboard/asus/m2v/romstage.c

Added: trunk/src/mainboard/asus/m2v/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asus/m2v/Kconfig	Sun Nov  7 21:08:45 2010	(r6045)
@@ -0,0 +1,77 @@
+if BOARD_ASUS_M2V
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_SOCKET_AM2
+	select DIMM_DDR2
+	select QRANK_DIMM_SUPPORT
+	select HAVE_OPTION_TABLE
+	select K8_HT_FREQ_1G_SUPPORT
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_VIA_VT8237R
+	select SOUTHBRIDGE_VIA_K8T890
+	select SUPERIO_ITE_IT8712F
+	select CACHE_AS_RAM
+	select BOARD_ROMSIZE_KB_512
+	select RAMINIT_SYSINFO
+	select TINY_BOOTBLOCK
+
+config MAINBOARD_DIR
+	string
+	default asus/m2v
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xcc000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x4000
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+	hex
+	default 0x1000
+
+config APIC_ID_OFFSET
+	hex
+	default 0x10
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "M2V"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0
+
+config MAX_CPUS
+	int
+	default 2
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+
+config HEAP_SIZE
+	hex
+	default 0x40000
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x20
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1043
+
+endif # BOARD_ASUS_M2V

Added: trunk/src/mainboard/asus/m2v/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asus/m2v/chip.h	Sun Nov  7 21:08:45 2010	(r6045)
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};

Added: trunk/src/mainboard/asus/m2v/cmos.layout
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asus/m2v/cmos.layout	Sun Nov  7 21:08:45 2010	(r6045)
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399         1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432         8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     DDR400
+8     1     DDR333
+8     2     DDR266
+8     3     DDR200
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+

Added: trunk/src/mainboard/asus/m2v/devicetree.cb
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asus/m2v/devicetree.cb	Sun Nov  7 21:08:45 2010	(r6045)
@@ -0,0 +1,74 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device lapic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_AM2			# CPU
+      device lapic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/via/vt8237r		# Southbridge
+          register "ide0_enable" = "1"		# Enable IDE channel 0
+          register "ide1_enable" = "1"		# Enable IDE channel 1
+          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
+          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
+          register "fn_ctrl_lo" = "0xc0"	# Enable SB functions
+          register "fn_ctrl_hi" = "0x0d"	# Enable SB functions
+          device pci 0.0 on end			# HT
+          device pci f.1 on end			# IDE
+          device pci 11.0 on			# LPC
+            chip drivers/generic/generic	# DIMM 0-0-0
+              device i2c 50 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-0-1
+              device i2c 51 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-0
+              device i2c 52 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-1
+              device i2c 53 on end
+            end
+            chip superio/ite/it8712f		# Super I/O
+              device pnp 2e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.2 off end		# Com2 (N/A on this board)
+              device pnp 2e.3 on		# Lpt1
+                io 0x60 = 0x378
+                irq 0x70 = 7
+                drq 0x74 = 3
+              end
+              device pnp 2e.4 on		# Environment controller
+                io 0x60 = 0xd00
+                io 0x62 = 0xc00
+                irq 0x70 = 0x00
+              end
+              device pnp 2e.5 off end		# PS/2 keyboard
+              device pnp 2e.6 off end		# PS/2 mouse
+              device pnp 2e.7 off end		# GPIO config
+              device pnp 2e.8 off end		# Midi port
+              device pnp 2e.9 off end		# Game port
+              device pnp 2e.a off end		# IR
+            end
+          end
+          device pci 12.0 off end		# VIA LAN (off, other chip used)
+          device pci 13.0 on end		# br
+          device pci 13.1 on end		# br2, need to have it here to discover it
+        end
+        chip southbridge/via/k8t890		# "Southbridge" K8T890
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end

Added: trunk/src/mainboard/asus/m2v/mainboard.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asus/m2v/mainboard.c	Sun Nov  7 21:08:45 2010	(r6045)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot at tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("ASUS M2V")
+};

Added: trunk/src/mainboard/asus/m2v/romstage.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asus/m2v/romstage.c	Sun Nov  7 21:08:45 2010	(r6045)
@@ -0,0 +1,299 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 AMD
+ * (Written by Yinghai Lu <yinghailu at amd.com> for AMD)
+ * Copyright (C) 2006 MSI
+ * (Written by Bingxun Shi <bingxunshi at gmail.com> for MSI)
+ * Copyright (C) 2008 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+unsigned int get_sbdn(unsigned bus);
+
+/* Used by init_cpus and fidvid */
+#define SET_FIDVID 1
+
+/* If we want to wait for core1 done before DQS training, set it to 0. */
+#define SET_FIDVID_CORE0_ONLY 1
+
+#if CONFIG_K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
+#define IT8712F_GPIO_BASE		0x0a20
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+static void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+// defines S3_NVRAM_EARLY:
+#include "southbridge/via/k8t890/k8t890_early_car.c"
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
+#include "lib/generic_sdram.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_fxx/fidvid.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
+
+void soft_reset(void)
+{
+	uint8_t tmp;
+
+	set_bios_reset();
+	print_debug("soft reset\n");
+
+	/* PCI reset */
+	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
+	tmp |= 0x01;
+	/* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
+	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
+
+	while (1) {
+		/* daisy daisy ... */
+		hlt();
+	}
+}
+
+unsigned int get_sbdn(unsigned bus)
+{
+	device_t dev;
+
+	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
+					PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
+	return (dev >> 15) & 0x1f;
+}
+
+struct gpio_init_val {
+	u8 addr;
+	u8 val;
+};
+
+static const struct gpio_init_val gpio_init_data[] = {
+	/* multi-function pin selection */
+	{ 0x25, 0x00 },
+	{ 0x28, 0x00 }, /* gp46 is infrared receive input */
+	{ 0x29, 0x40 }, /* reserved value?!? */
+	{ 0x2a, 0x00 },
+	{ 0x2c, 0x1d }, /* pin91 is VIN7 instead of PCIRSTIN# */
+	/* gpio i/o port base */
+	{ 0x62, IT8712F_GPIO_BASE >> 8 },
+	{ 0x63, IT8712F_GPIO_BASE & 0xff },
+	/* 0xb8 - 0xbc: gpio pull-up enable */
+	{ 0xb8, 0x00 },
+	/* 0xc0 - 0xc4: gpio alternate function select */
+	{ 0xc0, 0x00 },
+	{ 0xc3, 0x00 },
+	{ 0xc4, 0xc0 },
+	/* 0xc8 - 0xcc: gpio output enable */
+	{ 0xc8, 0x00 },
+	{ 0xcb, 0x00 },
+	{ 0xcc, 0xc0 },
+	/* end of list */
+	{ 0, 0 },
+};
+
+static void m2v_it8712f_gpio_init(void)
+{
+	const struct gpio_init_val *giv;
+
+	printk(BIOS_SPEW, "it8712f gpio init...\n");
+
+	/*
+	 * it8712f gpio config
+	 *
+	 * Most importantly this switches pin 91 from
+	 * PCIRSTIN# to VIN7.
+	 * Note that only PCIRST3# and PCIRST5# are affected
+	 * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always
+	 * direct buffers of #LRESET (low pin count bus reset).
+	 * If this is not done All PCIRST are in reset state and the
+	 * pcie slots don't initialize.
+	 *
+	 * pci reset handling:
+	 * pin 91: VIN7 (alternate PCIRSTIN#)
+	 * pin 48: PCIRST5# / gpio port 5 bit 0
+	 * pin 84: PCIRST4# / gpio port 1 bit 0
+	 * pin 31: PCIRST1# / gpio port 1 bit 4
+	 * pin 33: PCIRST2# / gpio port 1 bit 2
+	 * pin 34: PCIRST3# / gpio port 1 bit 1
+	 *
+	 * PCIRST[0-5]# are connected as follows:
+	 * pcirst1# -> pci bus
+	 * pcirst2# -> ide bus
+	 * pcirst3# -> pcie devices
+	 * pcirst4# -> pcie graphics
+	 * pcirst5# -> maybe n/c (untested)
+	 *
+	 * For software control of PCIRST[1-5]#:
+	 * 0x2a=0x17 (deselect pcirst# hardwiring, enable 0x25 control)
+	 * 0x25=0x17 (select gpio function)
+	 * 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable
+	 * 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable
+	 */
+	it8712f_enter_conf();
+	giv = gpio_init_data;
+	while (giv->addr) {
+		printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
+				giv->addr, giv->val);
+		it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val);
+		giv++;
+	}
+	it8712f_exit_conf();
+}
+
+static void m2v_bus_init(void)
+{
+	device_t dev;
+
+	printk(BIOS_SPEW, "m2v_bus_init\n");
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_K8T890CF_0), 0);
+	pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_K8T890CF_5), 0);
+	/*
+	 * bit | meaning
+	 * 6   | 0: hide scratch register function 0:0.6 (we don't use it)
+	 * 5   | 1: enable pcie bridge 0:2.0
+	 * 4   | 0: hide   pcie bridge 0:3.3 (not connected)
+	 * 3   | 1: enable pcie bridge 0:3.2
+	 * 2   | 1: enable pcie bridge 0:3.1
+	 * 1   | 1: enable pcie bridge 0:3.0
+	 */
+	pci_write_config8(dev, 0xf0, 0x2e);
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr[] = {
+		// Node 0
+		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
+		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+		// Node 1
+		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
+		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+	};
+	unsigned bsp_apicid = 0;
+	int needs_reset = 0;
+	struct sys_info *sysinfo =
+	    (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+	it8712f_24mhz_clkin();
+	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	it8712f_kill_watchdog();
+	uart_init();
+	console_init();
+	enable_rom_decode();
+	m2v_bus_init();
+	m2v_it8712f_gpio_init();
+
+	printk(BIOS_INFO, "now booting... \n");
+
+	if (bist == 0)
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+
+	/* Halt if there was a built in self test failure. */
+	report_bist_failure(bist);
+	setup_default_resource_map();
+	setup_coherent_ht_domain();
+	wait_all_core0_started();
+
+	printk(BIOS_INFO, "now booting... All core 0 started\n");
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* It is said that we should start core1 after all core0 launched. */
+	start_other_cores();
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+	init_timer();
+	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
+
+	needs_reset = optimize_link_coherent_ht();
+	print_debug_hex8(needs_reset);
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+	print_debug_hex8(needs_reset);
+	needs_reset |= k8t890_early_setup_ht();
+	print_debug_hex8(needs_reset);
+
+	if (needs_reset) {
+		printk(BIOS_DEBUG, "ht reset -\n");
+		soft_reset();
+		printk(BIOS_DEBUG, "FAILED!\n");
+	}
+
+	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
+	/* allow LDT STOP asserts */
+	vt8237_sb_enable_fid_vid();
+
+	enable_fid_change();
+	print_debug("after enable_fid_change\n");
+
+	init_fidvid_bsp(bsp_apicid);
+
+	/* Stop the APs so we can start them later in init. */
+	allow_all_aps_stop(bsp_apicid);
+
+	/* It's the time to set ctrl now. */
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	enable_smbus();
+	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+	post_cache_as_ram();
+}
+



From svn at coreboot.org  Sun Nov  7 21:11:41 2010
From: svn at coreboot.org (repository service)
Date: Sun, 07 Nov 2010 21:11:41 +0100
Subject: [coreboot] [commit] r6046 - in trunk/src/mainboard: amd/dbm690t
	amd/mahogany amd/mahogany_fam10 amd/pistachio
	amd/tilapia_fam10 asrock/939a785gmh asus/m4a785-m
	gigabyte/ma785gmt gigabyte/ma78gm iei/kino-780am...
Message-ID: <E1PFBaX-00054m-41@ra.coresystems.de>

Author: sduplichan
Date: Sun Nov  7 21:11:39 2010
New Revision: 6046
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6046

Log:
DSDT.asl should not report the AMD SB600/SB700 RTC as Intel PIIX4
compatible. The extended cmos is accessed differently for AMD
and Intel RTCs. Not sure what if any OS cares about this distinction,
but non-Intel compatible seems like a safer way to report the AMD RTC.
Tested with Win7 on Mahogany_fam10 and kino-780am2-fam10.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/amd/dbm690t/dsdt.asl
   trunk/src/mainboard/amd/mahogany/dsdt.asl
   trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl
   trunk/src/mainboard/amd/pistachio/dsdt.asl
   trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl
   trunk/src/mainboard/asrock/939a785gmh/dsdt.asl
   trunk/src/mainboard/asus/m4a785-m/dsdt.asl
   trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl
   trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl
   trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl
   trunk/src/mainboard/jetway/pa78vm5/dsdt.asl
   trunk/src/mainboard/kontron/kt690/dsdt.asl
   trunk/src/mainboard/technexion/tim5690/dsdt.asl
   trunk/src/mainboard/technexion/tim8690/dsdt.asl

Modified: trunk/src/mainboard/amd/dbm690t/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/amd/dbm690t/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1308,7 +1308,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/amd/mahogany/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/mahogany/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/amd/mahogany/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1324,7 +1324,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/amd/pistachio/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/pistachio/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/amd/pistachio/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1307,7 +1307,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/asrock/939a785gmh/dsdt.asl
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/asrock/939a785gmh/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1282,7 +1282,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/asus/m4a785-m/dsdt.asl
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/asus/m4a785-m/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/jetway/pa78vm5/dsdt.asl
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/jetway/pa78vm5/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1366,7 +1366,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/kontron/kt690/dsdt.asl
==============================================================================
--- trunk/src/mainboard/kontron/kt690/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/kontron/kt690/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1308,7 +1308,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/technexion/tim5690/dsdt.asl
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/technexion/tim5690/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1308,7 +1308,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)

Modified: trunk/src/mainboard/technexion/tim8690/dsdt.asl
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/dsdt.asl	Sun Nov  7 21:08:45 2010	(r6045)
+++ trunk/src/mainboard/technexion/tim8690/dsdt.asl	Sun Nov  7 21:11:39 2010	(r6046)
@@ -1308,7 +1308,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)



From ranma+coreboot at tdiedrich.de  Sun Nov  7 21:32:34 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 7 Nov 2010 21:32:34 +0100
Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs should
	bemarked	as reserved in the E820 memory map,
	in case the OS wants to change	the BARs.
In-Reply-To: <C4BEBE9836EE4F428CF721D0BE43A2C6@m3a78>
References: <20101107124622.274545089@yumi.uguu.de>
	<20101107124729.095637758@yamamaya.is-a-geek.org>
	<C4BEBE9836EE4F428CF721D0BE43A2C6@m3a78>
Message-ID: <20101107203233.GC12326@yumi.tdiedrich.de>

Scott Duplichan wrote:
> From: Tobias Diedrich
> ]Linux also needs the MMCONF area to be reserved either in E820 or
> ]as an ACPI motherboard resource or it will not enable MMCONFIG
> ]and the extended pcie configuration area will be unaccessible:
> ]
> ]This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
> ]resource flags to do this.
> ]I also added a new resource for the mapped bios rom area just below 4GB.
> ]I'm not sure if the choice for the index parameter of new_resource()
> ]is correct though.
> ]Note that the bios rom decode is enabled in
> ]src/southbridge/via/vt8237r/vt8237r_early_smbus.c
> ]for the whole 4MB area (even though the comment says 1MB).
> 
> Thank you Tobias. To be even more conservative, the upper 5 MB of the
> first 4GB can be reserved for flash memory. This is because many LPC
> flash chips place the jedec ID register of the boot device at address
> ffbc0000.

I think that probably doesn't apply here, since the LPC flash
shouldn't get chip-select outside the selected area.
However src/southbridge/via/vt8237r/bootblock.c (which I had missed
because I got my board to work without touching this file)
says its actually 8MB big for VT8237A and VT8237S.

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From scott at notabs.org  Sun Nov  7 21:49:17 2010
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 7 Nov 2010 14:49:17 -0600
Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs
	shouldbemarked	as reserved in the E820 memory map,
	in case the OS wants to change	the BARs.
In-Reply-To: <20101107203233.GC12326@yumi.tdiedrich.de>
References: <20101107124622.274545089@yumi.uguu.de><20101107124729.095637758@yamamaya.is-a-geek.org><C4BEBE9836EE4F428CF721D0BE43A2C6@m3a78>
	<20101107203233.GC12326@yumi.tdiedrich.de>
Message-ID: <658CE7A9CCF14520BDFBF75DCE048437@m3a78>

-----Original Message-----
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Tobias Diedrich
Sent: Sunday, November 07, 2010 02:33 PM
To: Scott Duplichan
Cc: 'Rudolf Marek'; coreboot at coreboot.org
Subject: Re: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs shouldbemarked as reserved in the E820 memory map,in case the
OS wants to change the BARs.

]Scott Duplichan wrote:
]> From: Tobias Diedrich
]> ]Linux also needs the MMCONF area to be reserved either in E820 or
]> ]as an ACPI motherboard resource or it will not enable MMCONFIG
]> ]and the extended pcie configuration area will be unaccessible:
]> ]
]> ]This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
]> ]resource flags to do this.
]> ]I also added a new resource for the mapped bios rom area just below 4GB.
]> ]I'm not sure if the choice for the index parameter of new_resource()
]> ]is correct though.
]> ]Note that the bios rom decode is enabled in
]> ]src/southbridge/via/vt8237r/vt8237r_early_smbus.c
]> ]for the whole 4MB area (even though the comment says 1MB).
]> 
]> Thank you Tobias. To be even more conservative, the upper 5 MB of the
]> first 4GB can be reserved for flash memory. This is because many LPC
]> flash chips place the jedec ID register of the boot device at address
]> ffbc0000.
]
]I think that probably doesn't apply here, since the LPC flash
]shouldn't get chip-select outside the selected area.
]However src/southbridge/via/vt8237r/bootblock.c (which I had missed
]because I got my board to work without touching this file)
]says its actually 8MB big for VT8237A and VT8237S.

Hello Tobias,

Here is my concern,
1) Coreboot reserves only 4MB (ffc00000-ffffffff).
2) The OS then assigns a PCI memory range that ends at ffbfffff.
3) A bios flash update program is run from the OS. It expands the
   flash decode range if needed then tries to read the flash jedec
   ID at ffbc0000. Both the flash chip and PCI device are set to
   decode ffbc0000. I do not know which device wins. If the flash
   wins and overrides the PCI device, things will be OK unless the
   OS needs to access the PCI device before flashing is complete.
   If the PCI device wins and overrides the flash, then the flash
   update utility will not be able to read the jedec ID.

Thanks,
Scott

]-- 
]Tobias						PGP: http://8ef7ddba.uguu.de




From r.marek at assembler.cz  Sun Nov  7 22:14:53 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Nov 2010 22:14:53 +0100
Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs
 shouldbemarked as reserved in the E820 memory map,
 in case the OS wants to change	the BARs.
In-Reply-To: <658CE7A9CCF14520BDFBF75DCE048437@m3a78>
References: <20101107124622.274545089@yumi.uguu.de><20101107124729.095637758@yamamaya.is-a-geek.org><C4BEBE9836EE4F428CF721D0BE43A2C6@m3a78>
	<20101107203233.GC12326@yumi.tdiedrich.de>
	<658CE7A9CCF14520BDFBF75DCE048437@m3a78>
Message-ID: <4CD716CD.6030200@assembler.cz>

Hi,

I thought our resource allocator did not touch the high region because of 
lapic/hpet/apic stuff. Maybe it is no longer true. I got some issue with PCI 
sata  add on card (linux complaining about resource overlap on SB700)

Maybe this is heading to same direction?

Thanks,
Rudolf



From scott at notabs.org  Sun Nov  7 22:51:57 2010
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 7 Nov 2010 15:51:57 -0600
Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs
	shouldbemarked as reserved in the E820 memory map,
	in case the OS wants to change	the BARs.
In-Reply-To: <4CD716CD.6030200@assembler.cz>
References: <20101107124622.274545089@yumi.uguu.de><20101107124729.095637758@yamamaya.is-a-geek.org><C4BEBE9836EE4F428CF721D0BE43A2C6@m3a78>
	<20101107203233.GC12326@yumi.tdiedrich.de>
	<658CE7A9CCF14520BDFBF75DCE048437@m3a78>
	<4CD716CD.6030200@assembler.cz>
Message-ID: <12F1B5FD3EB1454EA68896D9C68AAC75@m3a78>

-----Original Message-----
From: Rudolf Marek [mailto:r.marek at assembler.cz] 
Sent: Sunday, November 07, 2010 03:15 PM
To: Scott Duplichan
Cc: 'Tobias Diedrich'; coreboot at coreboot.org
Subject: Re: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs shouldbemarked as reserved in the E820 memory map,in case the
OS wants to change the BARs.

]Hi,
]
]I thought our resource allocator did not touch the high region because of 
]lapic/hpet/apic stuff. Maybe it is no longer true. I got some issue with PCI 
]sata  add on card (linux complaining about resource overlap on SB700)

Hello Rudolf,

You are right about coreboot, at least for the present time. However,
the allocation scheme still needs some work. For example, fec00000
and above is never allocated to a pci device because of the I/O apic,
which is on the pci bus. However, mmconf is not protected from pci use,
because it falls under 'APIC_CLUSTER: 0', and not a pci bus:
http://www.coreboot.org/pipermail/coreboot/2010-October/061320.html

I think the immediate concern for reserving flash memory space is
because the OS is allowed to make PCI resource assignments on its own.
The OS could use any range not reserved in e820. However, windows,
and possibly linux, also restrict PCI use to address ranges that ACPI
_CRS show as belonging to the pci bus. Coreboot still needs work in
this area. So maybe my example is a little far-fetched. But a commercial
BIOS reserves all the memory decoded by the flash chip, so coreboot
should probably do the same unless there is a specific reason not to.

]Maybe this is heading to same direction?

Could be. I have two overlap situations with win7 to avoid. One is the
mmconf problem described above. The other is when two video cards are
present, they both claim the legacy vga memory and I/O ranges.

]Thanks,
]Rudolf




From ranma+coreboot at tdiedrich.de  Mon Nov  8 00:31:51 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Mon, 8 Nov 2010 00:31:51 +0100
Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs
	shouldbemarked	as reserved in the E820 memory map,
	in case the OS wants to change	the BARs.
In-Reply-To: <658CE7A9CCF14520BDFBF75DCE048437@m3a78>
References: <20101107203233.GC12326@yumi.tdiedrich.de>
	<658CE7A9CCF14520BDFBF75DCE048437@m3a78>
Message-ID: <20101107233151.GD12326@yumi.tdiedrich.de>

Scott Duplichan wrote:
> From: Tobias Diedrich
> ]Scott Duplichan wrote:
> ]> Thank you Tobias. To be even more conservative, the upper 5 MB of the
> ]> first 4GB can be reserved for flash memory. This is because many LPC
> ]> flash chips place the jedec ID register of the boot device at address
> ]> ffbc0000.
> ]
> ]I think that probably doesn't apply here, since the LPC flash
> ]shouldn't get chip-select outside the selected area.
> ]However src/southbridge/via/vt8237r/bootblock.c (which I had missed
> ]because I got my board to work without touching this file)
> ]says its actually 8MB big for VT8237A and VT8237S.
> 
> Hello Tobias,
> 
> Here is my concern,
> 1) Coreboot reserves only 4MB (ffc00000-ffffffff).
> 2) The OS then assigns a PCI memory range that ends at ffbfffff.
> 3) A bios flash update program is run from the OS. It expands the
>    flash decode range if needed then tries to read the flash jedec
>    ID at ffbc0000. Both the flash chip and PCI device are set to
>    decode ffbc0000. I do not know which device wins. If the flash
>    wins and overrides the PCI device, things will be OK unless the
>    OS needs to access the PCI device before flashing is complete.
>    If the PCI device wins and overrides the flash, then the flash
>    update utility will not be able to read the jedec ID.

When coreboot reserves the full decode range (so it can't be
expanded any further) it should be fine though.

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From svn at coreboot.org  Mon Nov  8 01:30:59 2010
From: svn at coreboot.org (repository service)
Date: Mon, 08 Nov 2010 01:30:59 +0100
Subject: [coreboot] build service results for r6044
Message-ID: <E1PFFdT-0006x4-G8@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "ruik" checked in revision 6044 to
the coreboot repository. This caused the following 
changes:

Change Log:
This adds the m2v directory and necessary files to src/mainboards/asus and
adjusts the Kconfig.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>



Build Log:
Configuration of a-trend:atc-6220 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=atc-6220&vendor=a-trend&num=1
Configuration of a-trend:atc-6240 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=atc-6240&vendor=a-trend&num=1
Configuration of abit:be6-ii_v2_0 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=be6-ii_v2_0&vendor=abit&num=1
Configuration of advantech:pcm-5820 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=pcm-5820&vendor=advantech&num=1
Configuration of amd:db800 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=db800&vendor=amd&num=1
Configuration of amd:dbm690t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=dbm690t&vendor=amd&num=1
Configuration of amd:mahogany has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=mahogany&vendor=amd&num=1
Configuration of amd:mahogany_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=mahogany_fam10&vendor=amd&num=1
Configuration of amd:norwich has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=norwich&vendor=amd&num=1
Configuration of amd:pistachio has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=pistachio&vendor=amd&num=1
Configuration of amd:rumba has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=rumba&vendor=amd&num=1
Configuration of amd:serengeti_cheetah has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=serengeti_cheetah&vendor=amd&num=1
Configuration of amd:serengeti_cheetah_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=serengeti_cheetah_fam10&vendor=amd&num=1
Configuration of amd:tilapia_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=tilapia_fam10&vendor=amd&num=1
Configuration of arima:hdama has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=hdama&vendor=arima&num=1
Configuration of artecgroup:dbe61 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=dbe61&vendor=artecgroup&num=1
Configuration of asi:mb_5blgp has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=mb_5blgp&vendor=asi&num=1
Configuration of asi:mb_5blmp has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=mb_5blmp&vendor=asi&num=1
Configuration of asrock:939a785gmh has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=939a785gmh&vendor=asrock&num=1
Configuration of asus:a8n_e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=a8n_e&vendor=asus&num=1
Configuration of asus:a8v-e_se has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=a8v-e_se&vendor=asus&num=1
Configuration of asus:m2v-mx_se has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=m2v-mx_se&vendor=asus&num=1
Configuration of asus:m4a785-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=m4a785-m&vendor=asus&num=1
Configuration of asus:mew-am has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=mew-am&vendor=asus&num=1
Configuration of asus:mew-vm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=mew-vm&vendor=asus&num=1
Configuration of asus:p2b has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=p2b&vendor=asus&num=1
Configuration of asus:p2b-d has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=p2b-d&vendor=asus&num=1
Configuration of asus:p2b-ds has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=p2b-ds&vendor=asus&num=1
Configuration of asus:p2b-f has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=p2b-f&vendor=asus&num=1
Configuration of asus:p2b-ls has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=p2b-ls&vendor=asus&num=1
Configuration of asus:p3b-f has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=p3b-f&vendor=asus&num=1
Configuration of axus:tc320 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=tc320&vendor=axus&num=1
Configuration of azza:pt-6ibd has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=pt-6ibd&vendor=azza&num=1
Configuration of bcom:winnet100 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=winnet100&vendor=bcom&num=1
Configuration of bcom:winnetp680 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=winnetp680&vendor=bcom&num=1
Configuration of biostar:m6tba has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=m6tba&vendor=biostar&num=1
Configuration of broadcom:blast has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=blast&vendor=broadcom&num=1
Configuration of compaq:deskpro_en_sff_p600 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=deskpro_en_sff_p600&vendor=compaq&num=1
Configuration of dell:s1850 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s1850&vendor=dell&num=1
Configuration of digitallogic:adl855pc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=adl855pc&vendor=digitallogic&num=1
Configuration of digitallogic:msm586seg has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=msm586seg&vendor=digitallogic&num=1
Configuration of digitallogic:msm800sev has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=msm800sev&vendor=digitallogic&num=1
Configuration of eaglelion:5bcm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=5bcm&vendor=eaglelion&num=1
Configuration of ecs:p6iwp-fe has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=p6iwp-fe&vendor=ecs&num=1
Configuration of emulation:qemu-x86 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=qemu-x86&vendor=emulation&num=1
Configuration of getac:p470 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=p470&vendor=getac&num=1
Configuration of gigabyte:ga-6bxc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ga-6bxc&vendor=gigabyte&num=1
Configuration of gigabyte:ga-6bxe has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ga-6bxe&vendor=gigabyte&num=1
Configuration of gigabyte:ga_2761gxdk has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ga_2761gxdk&vendor=gigabyte&num=1
Configuration of gigabyte:m57sli has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=m57sli&vendor=gigabyte&num=1
Configuration of gigabyte:ma785gmt has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ma785gmt&vendor=gigabyte&num=1
Configuration of gigabyte:ma78gm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ma78gm&vendor=gigabyte&num=1
Configuration of hp:dl145_g1 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=dl145_g1&vendor=hp&num=1
Configuration of hp:dl145_g3 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=dl145_g3&vendor=hp&num=1
Configuration of hp:dl165_g6_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=dl165_g6_fam10&vendor=hp&num=1
Configuration of hp:e_vectra_p2706t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=e_vectra_p2706t&vendor=hp&num=1
Configuration of ibase:mb899 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=mb899&vendor=ibase&num=1
Configuration of ibm:e325 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=e325&vendor=ibm&num=1
Configuration of ibm:e326 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=e326&vendor=ibm&num=1
Configuration of iei:juki-511p has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=juki-511p&vendor=iei&num=1
Configuration of iei:kino-780am2-fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=kino-780am2-fam10&vendor=iei&num=1
Configuration of iei:nova4899r has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=nova4899r&vendor=iei&num=1
Configuration of iei:pcisa-lx-800-r10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=pcisa-lx-800-r10&vendor=iei&num=1
Configuration of intel:d810e2cb has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=d810e2cb&vendor=intel&num=1
Configuration of intel:d945gclf has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=d945gclf&vendor=intel&num=1
Configuration of intel:eagleheights has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=eagleheights&vendor=intel&num=1
Configuration of intel:jarrell has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=jarrell&vendor=intel&num=1
Configuration of intel:mtarvon has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=mtarvon&vendor=intel&num=1
Configuration of intel:truxton has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=truxton&vendor=intel&num=1
Configuration of intel:xe7501devkit has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=xe7501devkit&vendor=intel&num=1
Configuration of iwill:dk8_htx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=dk8_htx&vendor=iwill&num=1
Configuration of iwill:dk8s2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=dk8s2&vendor=iwill&num=1
Configuration of iwill:dk8x has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=dk8x&vendor=iwill&num=1
Configuration of jetway:j7f24 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=j7f24&vendor=jetway&num=1
Configuration of jetway:pa78vm5 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=pa78vm5&vendor=jetway&num=1
Configuration of kontron:986lcd-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=986lcd-m&vendor=kontron&num=1
Configuration of kontron:kt690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=kt690&vendor=kontron&num=1
Configuration of lanner:em8510 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=em8510&vendor=lanner&num=1
Configuration of lippert:frontrunner has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=frontrunner&vendor=lippert&num=1
Configuration of lippert:hurricane-lx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=hurricane-lx&vendor=lippert&num=1
Configuration of lippert:literunner-lx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=literunner-lx&vendor=lippert&num=1
Configuration of lippert:roadrunner-lx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=roadrunner-lx&vendor=lippert&num=1
Configuration of lippert:spacerunner-lx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=spacerunner-lx&vendor=lippert&num=1
Configuration of mitac:6513wu has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=6513wu&vendor=mitac&num=1
Configuration of msi:ms6119 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ms6119&vendor=msi&num=1
Configuration of msi:ms6147 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ms6147&vendor=msi&num=1
Configuration of msi:ms6156 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ms6156&vendor=msi&num=1
Configuration of msi:ms6178 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ms6178&vendor=msi&num=1
Configuration of msi:ms7135 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ms7135&vendor=msi&num=1
Configuration of msi:ms7260 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ms7260&vendor=msi&num=1
Configuration of msi:ms9185 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ms9185&vendor=msi&num=1
Configuration of msi:ms9282 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ms9282&vendor=msi&num=1
Configuration of msi:ms9652_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ms9652_fam10&vendor=msi&num=1
Configuration of nec:powermate2000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=powermate2000&vendor=nec&num=1
Configuration of newisys:khepri has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=khepri&vendor=newisys&num=1
Configuration of nokia:ip530 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ip530&vendor=nokia&num=1
Configuration of nvidia:l1_2pvv has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=l1_2pvv&vendor=nvidia&num=1
Configuration of pcengines:alix1c has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=alix1c&vendor=pcengines&num=1
Configuration of pcengines:alix2d has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=alix2d&vendor=pcengines&num=1
Configuration of rca:rm4100 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=rm4100&vendor=rca&num=1
Configuration of roda:rk886ex has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=rk886ex&vendor=roda&num=1
Configuration of soyo:sy-6ba-plus-iii has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=sy-6ba-plus-iii&vendor=soyo&num=1
Configuration of sunw:ultra40 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ultra40&vendor=sunw&num=1
Configuration of supermicro:h8dme has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=h8dme&vendor=supermicro&num=1
Configuration of supermicro:h8dmr has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=h8dmr&vendor=supermicro&num=1
Configuration of supermicro:h8dmr_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=h8dmr_fam10&vendor=supermicro&num=1
Configuration of supermicro:h8qme_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=h8qme_fam10&vendor=supermicro&num=1
Configuration of supermicro:x6dai_g has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=x6dai_g&vendor=supermicro&num=1
Configuration of supermicro:x6dhe_g has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=x6dhe_g&vendor=supermicro&num=1
Configuration of supermicro:x6dhe_g2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=x6dhe_g2&vendor=supermicro&num=1
Configuration of supermicro:x6dhr_ig has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=x6dhr_ig&vendor=supermicro&num=1
Configuration of supermicro:x6dhr_ig2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=x6dhr_ig2&vendor=supermicro&num=1
Configuration of technexion:tim5690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=tim5690&vendor=technexion&num=1
Configuration of technexion:tim8690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=tim8690&vendor=technexion&num=1
Configuration of technologic:ts5300 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ts5300&vendor=technologic&num=1
Configuration of televideo:tc7020 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=tc7020&vendor=televideo&num=1
Configuration of thomson:ip1000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=ip1000&vendor=thomson&num=1
Configuration of traverse:geos has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=geos&vendor=traverse&num=1
Configuration of tyan:s1846 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s1846&vendor=tyan&num=1
Configuration of tyan:s2735 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2735&vendor=tyan&num=1
Configuration of tyan:s2850 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2850&vendor=tyan&num=1
Configuration of tyan:s2875 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2875&vendor=tyan&num=1
Configuration of tyan:s2880 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2880&vendor=tyan&num=1
Configuration of tyan:s2881 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2881&vendor=tyan&num=1
Configuration of tyan:s2882 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2882&vendor=tyan&num=1
Configuration of tyan:s2885 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2885&vendor=tyan&num=1
Configuration of tyan:s2891 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2891&vendor=tyan&num=1
Configuration of tyan:s2892 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2892&vendor=tyan&num=1
Configuration of tyan:s2895 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2895&vendor=tyan&num=1
Configuration of tyan:s2912 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2912&vendor=tyan&num=1
Configuration of tyan:s2912_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s2912_fam10&vendor=tyan&num=1
Configuration of tyan:s4880 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s4880&vendor=tyan&num=1
Configuration of tyan:s4882 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s4882&vendor=tyan&num=1
Configuration of via:epia has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=epia&vendor=via&num=1
Configuration of via:epia-cn has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=epia-cn&vendor=via&num=1
Configuration of via:epia-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=epia-m&vendor=via&num=1
Configuration of via:epia-m700 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=epia-m700&vendor=via&num=1
Configuration of via:epia-n has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=epia-n&vendor=via&num=1
Configuration of via:pc2500e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=pc2500e&vendor=via&num=1
Configuration of via:vt8454c has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=vt8454c&vendor=via&num=1
Configuration of winent:pl6064 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=pl6064&vendor=winent&num=1
Configuration of wyse:s50 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6044&device=s50&vendor=wyse&num=1


If something broke during this checkin please be a pain 
in ruik's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Mon Nov  8 02:03:45 2010
From: svn at coreboot.org (repository service)
Date: Mon, 08 Nov 2010 02:03:45 +0100
Subject: [coreboot] build service results for r6045
Message-ID: <E1PFG9B-000851-RD@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "ruik" checked in revision 6045 to
the coreboot repository. This caused the following 
changes:

Change Log:
Should be part of 6044. I forgot to add the directory :/

This adds the m2v directory and necessary files to src/mainboards/asus and
adjusts the Kconfig.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>



Build Log:
Configuration of a-trend:atc-6220 has been fixed
Configuration of a-trend:atc-6240 has been fixed
Configuration of abit:be6-ii_v2_0 has been fixed
Configuration of advantech:pcm-5820 has been fixed
Configuration of amd:db800 has been fixed
Configuration of amd:dbm690t has been fixed
Configuration of amd:mahogany has been fixed
Configuration of amd:mahogany_fam10 has been fixed
Configuration of amd:norwich has been fixed
Configuration of amd:pistachio has been fixed
Configuration of amd:rumba has been fixed
Configuration of amd:serengeti_cheetah has been fixed
Configuration of amd:serengeti_cheetah_fam10 has been fixed
Configuration of amd:tilapia_fam10 has been fixed
Configuration of arima:hdama has been fixed
Configuration of artecgroup:dbe61 has been fixed
Configuration of asi:mb_5blgp has been fixed
Configuration of asi:mb_5blmp has been fixed
Configuration of asrock:939a785gmh has been fixed
Configuration of asus:a8n_e has been fixed
Configuration of asus:a8v-e_se has been fixed
Configuration of asus:m2v-mx_se has been fixed
Configuration of asus:m4a785-m has been fixed
Configuration of asus:mew-am has been fixed
Configuration of asus:mew-vm has been fixed
Configuration of asus:p2b has been fixed
Configuration of asus:p2b-d has been fixed
Configuration of asus:p2b-ds has been fixed
Configuration of asus:p2b-f has been fixed
Configuration of asus:p2b-ls has been fixed
Configuration of asus:p3b-f has been fixed
Configuration of axus:tc320 has been fixed
Configuration of azza:pt-6ibd has been fixed
Configuration of bcom:winnet100 has been fixed
Configuration of bcom:winnetp680 has been fixed
Configuration of biostar:m6tba has been fixed
Configuration of broadcom:blast has been fixed
Configuration of compaq:deskpro_en_sff_p600 has been fixed
Configuration of dell:s1850 has been fixed
Configuration of digitallogic:adl855pc has been fixed
Configuration of digitallogic:msm586seg has been fixed
Configuration of digitallogic:msm800sev has been fixed
Configuration of eaglelion:5bcm has been fixed
Configuration of ecs:p6iwp-fe has been fixed
Configuration of emulation:qemu-x86 has been fixed
Configuration of getac:p470 has been fixed
Configuration of gigabyte:ga-6bxc has been fixed
Configuration of gigabyte:ga-6bxe has been fixed
Configuration of gigabyte:ga_2761gxdk has been fixed
Configuration of gigabyte:m57sli has been fixed
Configuration of gigabyte:ma785gmt has been fixed
Configuration of gigabyte:ma78gm has been fixed
Configuration of hp:dl145_g1 has been fixed
Configuration of hp:dl145_g3 has been fixed
Configuration of hp:dl165_g6_fam10 has been fixed
Configuration of hp:e_vectra_p2706t has been fixed
Configuration of ibase:mb899 has been fixed
Configuration of ibm:e325 has been fixed
Configuration of ibm:e326 has been fixed
Configuration of iei:juki-511p has been fixed
Configuration of iei:kino-780am2-fam10 has been fixed
Configuration of iei:nova4899r has been fixed
Configuration of iei:pcisa-lx-800-r10 has been fixed
Configuration of intel:d810e2cb has been fixed
Configuration of intel:d945gclf has been fixed
Configuration of intel:eagleheights has been fixed
Configuration of intel:jarrell has been fixed
Configuration of intel:mtarvon has been fixed
Configuration of intel:truxton has been fixed
Configuration of intel:xe7501devkit has been fixed
Configuration of iwill:dk8_htx has been fixed
Configuration of iwill:dk8s2 has been fixed
Configuration of iwill:dk8x has been fixed
Configuration of jetway:j7f24 has been fixed
Configuration of jetway:pa78vm5 has been fixed
Configuration of kontron:986lcd-m has been fixed
Configuration of kontron:kt690 has been fixed
Configuration of lanner:em8510 has been fixed
Configuration of lippert:frontrunner has been fixed
Configuration of lippert:hurricane-lx has been fixed
Configuration of lippert:literunner-lx has been fixed
Configuration of lippert:roadrunner-lx has been fixed
Configuration of lippert:spacerunner-lx has been fixed
Configuration of mitac:6513wu has been fixed
Configuration of msi:ms6119 has been fixed
Configuration of msi:ms6147 has been fixed
Configuration of msi:ms6156 has been fixed
Configuration of msi:ms6178 has been fixed
Configuration of msi:ms7135 has been fixed
Configuration of msi:ms7260 has been fixed
Configuration of msi:ms9185 has been fixed
Configuration of msi:ms9282 has been fixed
Configuration of msi:ms9652_fam10 has been fixed
Configuration of nec:powermate2000 has been fixed
Configuration of newisys:khepri has been fixed
Configuration of nokia:ip530 has been fixed
Configuration of nvidia:l1_2pvv has been fixed
Configuration of pcengines:alix1c has been fixed
Configuration of pcengines:alix2d has been fixed
Configuration of rca:rm4100 has been fixed
Configuration of roda:rk886ex has been fixed
Configuration of soyo:sy-6ba-plus-iii has been fixed
Configuration of sunw:ultra40 has been fixed
Configuration of supermicro:h8dme has been fixed
Configuration of supermicro:h8dmr has been fixed
Configuration of supermicro:h8dmr_fam10 has been fixed
Configuration of supermicro:h8qme_fam10 has been fixed
Configuration of supermicro:x6dai_g has been fixed
Configuration of supermicro:x6dhe_g has been fixed
Configuration of supermicro:x6dhe_g2 has been fixed
Configuration of supermicro:x6dhr_ig has been fixed
Configuration of supermicro:x6dhr_ig2 has been fixed
Configuration of technexion:tim5690 has been fixed
Configuration of technexion:tim8690 has been fixed
Configuration of technologic:ts5300 has been fixed
Configuration of televideo:tc7020 has been fixed
Configuration of thomson:ip1000 has been fixed
Configuration of traverse:geos has been fixed
Configuration of tyan:s1846 has been fixed
Configuration of tyan:s2735 has been fixed
Configuration of tyan:s2850 has been fixed
Configuration of tyan:s2875 has been fixed
Configuration of tyan:s2880 has been fixed
Configuration of tyan:s2881 has been fixed
Configuration of tyan:s2882 has been fixed
Configuration of tyan:s2885 has been fixed
Configuration of tyan:s2891 has been fixed
Configuration of tyan:s2892 has been fixed
Configuration of tyan:s2895 has been fixed
Configuration of tyan:s2912 has been fixed
Configuration of tyan:s2912_fam10 has been fixed
Configuration of tyan:s4880 has been fixed
Configuration of tyan:s4882 has been fixed
Configuration of via:epia has been fixed
Configuration of via:epia-cn has been fixed
Configuration of via:epia-m has been fixed
Configuration of via:epia-m700 has been fixed
Configuration of via:epia-n has been fixed
Configuration of via:pc2500e has been fixed
Configuration of via:vt8454c has been fixed
Configuration of winent:pl6064 has been fixed
Configuration of wyse:s50 has been fixed


If something broke during this checkin please be a pain 
in ruik's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Mon Nov  8 03:17:16 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 08 Nov 2010 03:17:16 +0100
Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI
 BARs	shouldbemarked as reserved in the E820 memory map,
 in case the OS wants to change	the BARs.
In-Reply-To: <20101107233151.GD12326@yumi.tdiedrich.de>
References: <20101107203233.GC12326@yumi.tdiedrich.de>	<658CE7A9CCF14520BDFBF75DCE048437@m3a78>
	<20101107233151.GD12326@yumi.tdiedrich.de>
Message-ID: <4CD75DAC.4060400@gmx.net>

On 08.11.2010 00:31, Tobias Diedrich wrote:
> When coreboot reserves the full decode range (so it can't be
> expanded any further) it should be fine though.
>   

So far I have not seen flash decode ranges larger than 16 MB on any x86
chipset. Reserving less than 16 MB is very dangerous on all Intel/AMD
chipsets released in the last 6+ years because flashrom may maximize the
decode area to 16 MB after the machine has booted.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Mon Nov  8 15:30:44 2010
From: peter at stuge.se (Peter Stuge)
Date: Mon, 8 Nov 2010 15:30:44 +0100
Subject: [coreboot] MCP55 Mac Address copying/change
In-Reply-To: <201011072012.41727.harald.gutmann@gmx.net>
References: <201011041855.28624.harald.gutmann@gmx.net>
	<20101105164843.GD25395@tarantulon.kollasch.net>
	<201011072012.41727.harald.gutmann@gmx.net>
Message-ID: <20101108143044.12112.qmail@stuge.se>

Harald Gutmann wrote:
> Just for my personal interest, could someone explain me what
> actually is called romstrap?

It's a horrible name for permanent settings that are stored in the
boot flash.


> Is there any fast method to read the onboards NIC mac address "faster"?

ip l sh eth0|grep link/ether|awk '{print $2}'


//Peter



From peter at stuge.se  Mon Nov  8 15:44:30 2010
From: peter at stuge.se (Peter Stuge)
Date: Mon, 8 Nov 2010 15:44:30 +0100
Subject: [coreboot] [RFC]Static testing of our tree
In-Reply-To: <4CD5DE49.1020306@georgi-clan.de>
References: <4CD5DE49.1020306@georgi-clan.de>
Message-ID: <20101108144430.15682.qmail@stuge.se>

Patrick Georgi wrote:
> I propose to store this script (and similar ones) somewhere under
> util/, and hook them up in the Makefile ("make lint"?) and in the
> autobuilder (qa.coreboot.org), and have that report failure if they
> return any output.

How long does it take to run?

As soon as there are no more warnings I think it should be in the
commit hook.


//Peter



From svn at coreboot.org  Mon Nov  8 16:00:02 2010
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 08 Nov 2010 16:00:02 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1PFTCU-0008Gx-Gp@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20101108/5d31fdd3/attachment.html>

From svn at coreboot.org  Mon Nov  8 16:16:31 2010
From: svn at coreboot.org (repository service)
Date: Mon, 08 Nov 2010 16:16:31 +0100
Subject: [coreboot] [commit] r6047 - in trunk/src/superio/ite: it8661f
	it8671f it8673f it8705f it8712f it8716f it8718f
Message-ID: <E1PFTSR-0001eW-6r@ra.coresystems.de>

Author: uwe
Date: Mon Nov  8 16:16:30 2010
New Revision: 6047
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6047

Log:
Random ITE Super I/O fixes.

 - Drop some of the less useful / outdated / duplicated comments.

 - Simplify and streamline some code to look like the other Super I/Os.

 - Use u8/16/etc. everywhere.

 - ITE IT8718F: Add missing GPIO LDN.
 
 - Add missing braces around SIO_DATA #defines, potential bug even.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/superio/ite/it8661f/Makefile.inc
   trunk/src/superio/ite/it8661f/chip.h
   trunk/src/superio/ite/it8661f/it8661f.h
   trunk/src/superio/ite/it8661f/it8661f_early_serial.c
   trunk/src/superio/ite/it8661f/superio.c
   trunk/src/superio/ite/it8671f/Makefile.inc
   trunk/src/superio/ite/it8671f/chip.h
   trunk/src/superio/ite/it8671f/it8671f.h
   trunk/src/superio/ite/it8671f/it8671f_early_serial.c
   trunk/src/superio/ite/it8671f/superio.c
   trunk/src/superio/ite/it8673f/Makefile.inc
   trunk/src/superio/ite/it8673f/chip.h
   trunk/src/superio/ite/it8673f/it8673f.h
   trunk/src/superio/ite/it8673f/it8673f_early_serial.c
   trunk/src/superio/ite/it8673f/superio.c
   trunk/src/superio/ite/it8705f/Makefile.inc
   trunk/src/superio/ite/it8705f/chip.h
   trunk/src/superio/ite/it8705f/it8705f.h
   trunk/src/superio/ite/it8705f/it8705f_early_serial.c
   trunk/src/superio/ite/it8705f/superio.c
   trunk/src/superio/ite/it8712f/Makefile.inc
   trunk/src/superio/ite/it8712f/chip.h
   trunk/src/superio/ite/it8712f/it8712f.h
   trunk/src/superio/ite/it8712f/it8712f_early_serial.c
   trunk/src/superio/ite/it8712f/superio.c
   trunk/src/superio/ite/it8716f/Makefile.inc
   trunk/src/superio/ite/it8716f/chip.h
   trunk/src/superio/ite/it8716f/it8716f.h
   trunk/src/superio/ite/it8716f/it8716f_early_init.c
   trunk/src/superio/ite/it8716f/it8716f_early_serial.c
   trunk/src/superio/ite/it8716f/superio.c
   trunk/src/superio/ite/it8718f/Makefile.inc
   trunk/src/superio/ite/it8718f/chip.h
   trunk/src/superio/ite/it8718f/it8718f.h
   trunk/src/superio/ite/it8718f/it8718f_early_serial.c
   trunk/src/superio/ite/it8718f/superio.c

Modified: trunk/src/superio/ite/it8661f/Makefile.inc
==============================================================================
--- trunk/src/superio/ite/it8661f/Makefile.inc	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8661f/Makefile.inc	Mon Nov  8 16:16:30 2010	(r6047)
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-#config chip.h
 ramstage-$(CONFIG_SUPERIO_ITE_IT8661F) += superio.c
+

Modified: trunk/src/superio/ite/it8661f/chip.h
==============================================================================
--- trunk/src/superio/ite/it8661f/chip.h	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8661f/chip.h	Mon Nov  8 16:16:30 2010	(r6047)
@@ -18,10 +18,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef _SUPERIO_ITE_IT8661F
-#define _SUPERIO_ITE_IT8661F
+#ifndef SUPERIO_ITE_IT8661F_CHIP_H
+#define SUPERIO_ITE_IT8661F_CHIP_H
 
-/* This chip doesn't seem to have keyboard and mouse support. */
+/* This chip doesn't have keyboard and mouse support. */
 
 #include <device/device.h>
 #include <uart8250.h>
@@ -32,4 +32,4 @@
 	struct uart8250 com1, com2;
 };
 
-#endif /* _SUPERIO_ITE_IT8661F */
+#endif

Modified: trunk/src/superio/ite/it8661f/it8661f.h
==============================================================================
--- trunk/src/superio/ite/it8661f/it8661f.h	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8661f/it8661f.h	Mon Nov  8 16:16:30 2010	(r6047)
@@ -19,9 +19,6 @@
  */
 
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */
-/* Status: Untested on real hardware, but it compiles. */
-
-/* This chip doesn't seem to have keyboard and mouse support. */
 
 #define IT8661F_FDC  0x00 /* Floppy */
 #define IT8661F_SP1  0x01 /* Com1 */

Modified: trunk/src/superio/ite/it8661f/it8661f_early_serial.c
==============================================================================
--- trunk/src/superio/ite/it8661f/it8661f_early_serial.c	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8661f/it8661f_early_serial.c	Mon Nov  8 16:16:30 2010	(r6047)
@@ -24,7 +24,7 @@
 /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
 #define SIO_BASE                   0x3f0
 #define SIO_INDEX                  SIO_BASE
-#define SIO_DATA                   SIO_BASE+1
+#define SIO_DATA                   (SIO_BASE + 1)
 
 /* Global configuration registers. */
 #define IT8661F_CONFIG_REG_CC      0x02   /* Configure Control (write-only). */
@@ -34,18 +34,18 @@
 
 #define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */
 
-/* Special values used for entering MB PnP mode. The first four bytes of
-   each line determine the address port, the last four are data. */
-static const uint8_t init_values[] = {
+/*
+ * Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data.
+ */
+static const u8 init_values[] = {
 	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
 	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
 	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
 	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
 };
 
-/* The content of IT8661F_CONFIG_REG_LDN (index 0x07) must be set to the
-   LDN the register belongs to, before you can access the register. */
-static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+static void it8661f_sio_write(u8 ldn, u8 index, u8 value)
 {
 	outb(IT8661F_CONFIG_REG_LDN, SIO_BASE);
 	outb(ldn, SIO_DATA);
@@ -53,10 +53,10 @@
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8661F Super I/O chip. */
-static void it8661f_enable_serial(device_t dev, unsigned iobase)
+/* Enable the serial port(s). */
+static void it8661f_enable_serial(device_t dev, u16 iobase)
 {
-	uint8_t i;
+	int i;
 
 	/* (1) Enter the configuration state (MB PnP mode). */
 
@@ -70,19 +70,20 @@
 	outb(0x55, IT8661F_CONFIGURATION_PORT);
 
 	/* Sequentially write the 32 special values. */
-	for (i = 0; i < 32; i++) {
+	for (i = 0; i < 32; i++)
 		outb(init_values[i], SIO_BASE);
-	}
 
 	/* (2) Modify the data of configuration registers. */
 
-	/* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
-	   PP (3), IR (4). Bits 5-7 are reserved. */
+	/*
+	 * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
+	 * PP (3), IR (4). Bits 5-7 are reserved.
+	 */
 	it8661f_sio_write(0x00, IT8661F_CONFIG_REG_LDE, 0x1f);
 
 	/* Enable serial port(s). */
-	it8661f_sio_write(IT8661F_SP1,  0x30, 0x1); /* Serial port 1 */
-	it8661f_sio_write(IT8661F_SP2,  0x30, 0x1); /* Serial port 2 */
+	it8661f_sio_write(IT8661F_SP1, 0x30, 0x1); /* Serial port 1 */
+	it8661f_sio_write(IT8661F_SP2, 0x30, 0x1); /* Serial port 2 */
 
 	/* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode
 	   (clear bit 0). */

Modified: trunk/src/superio/ite/it8661f/superio.c
==============================================================================
--- trunk/src/superio/ite/it8661f/superio.c	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8661f/superio.c	Mon Nov  8 16:16:30 2010	(r6047)
@@ -18,8 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* This chip doesn't seem to have keyboard and mouse support. */
-
 #include <device/device.h>
 #include <device/pnp.h>
 #include <uart8250.h>
@@ -29,14 +27,11 @@
 
 static void init(device_t dev)
 {
-	struct superio_ite_it8661f_config *conf;
+	struct superio_ite_it8661f_config *conf = dev->chip_info;
 	struct resource *res0, *res1;
 
-	if (!dev->enabled) {
+	if (!dev->enabled)
 		return;
-	}
-
-	conf = dev->chip_info;
 
 	switch (dev->path.pnp.device) {
 	case IT8661F_FDC: /* TODO. */

Modified: trunk/src/superio/ite/it8671f/Makefile.inc
==============================================================================
--- trunk/src/superio/ite/it8671f/Makefile.inc	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8671f/Makefile.inc	Mon Nov  8 16:16:30 2010	(r6047)
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-#config chip.h
 ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c
+

Modified: trunk/src/superio/ite/it8671f/chip.h
==============================================================================
--- trunk/src/superio/ite/it8671f/chip.h	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8671f/chip.h	Mon Nov  8 16:16:30 2010	(r6047)
@@ -18,8 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef _SUPERIO_ITE_IT8671F
-#define _SUPERIO_ITE_IT8671F
+#ifndef SUPERIO_ITE_IT8671F_CHIP_H
+#define SUPERIO_ITE_IT8671F_CHIP_H
 
 #include <device/device.h>
 #include <pc80/keyboard.h>
@@ -32,4 +32,4 @@
 	struct pc_keyboard keyboard;
 };
 
-#endif /* _SUPERIO_ITE_IT8671F */
+#endif

Modified: trunk/src/superio/ite/it8671f/it8671f.h
==============================================================================
--- trunk/src/superio/ite/it8671f/it8671f.h	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8671f/it8671f.h	Mon Nov  8 16:16:30 2010	(r6047)
@@ -19,11 +19,10 @@
  */
 
 /* Datasheet: Not available online, got it from ITE per request. */
-/* Status: Com1 is tested and works. */
 
 #define IT8671F_FDC  0x00 /* Floppy */
 #define IT8671F_SP1  0x01 /* Com1 */
 #define IT8671F_SP2  0x02 /* Com2 */
 #define IT8671F_PP   0x03 /* Parallel port */
-#define IT8671F_KBCK 0x05 /* Keyboard */
-#define IT8671F_KBCM 0x06 /* Mouse */
+#define IT8671F_KBCK 0x05 /* PS/2 keyboard */
+#define IT8671F_KBCM 0x06 /* PS/2 mouse */

Modified: trunk/src/superio/ite/it8671f/it8671f_early_serial.c
==============================================================================
--- trunk/src/superio/ite/it8671f/it8671f_early_serial.c	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8671f/it8671f_early_serial.c	Mon Nov  8 16:16:30 2010	(r6047)
@@ -38,18 +38,14 @@
  * Special values used for entering MB PnP mode. The first four bytes of
  * each line determine the address port, the last four are data.
  */
-static const uint8_t init_values[] = {
+static const u8 init_values[] = {
 	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
 	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
 	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
 	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
 };
 
-/*
- * The content of IT8671F_CONFIG_REG_LDN (index 0x07) must be set to the
- * LDN the register belongs to, before you can access the register.
- */
-static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+static void it8671f_sio_write(u8 ldn, u8 index, u8 value)
 {
 	outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
 	outb(ldn, SIO_DATA);
@@ -60,7 +56,7 @@
 /* Enter the configuration state (MB PnP mode). */
 static void it8671f_enter_conf(void)
 {
-	uint8_t i;
+	int i;
 
 	/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
 	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
@@ -90,13 +86,15 @@
 	it8671f_exit_conf();
 }
 
-/* Enable the serial ports on the IT8671F Super I/O chip. */
-static void it8671f_enable_serial(device_t dev, unsigned iobase)
+/* Enable the serial port(s). */
+static void it8671f_enable_serial(device_t dev, u16 iobase)
 {
 	it8671f_enter_conf();
 
-	/* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
-           PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */
+	/*
+	 * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
+         * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7).
+	 */
 	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
 
 	/* Enable serial port(s). */

Modified: trunk/src/superio/ite/it8671f/superio.c
==============================================================================
--- trunk/src/superio/ite/it8671f/superio.c	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8671f/superio.c	Mon Nov  8 16:16:30 2010	(r6047)
@@ -28,14 +28,11 @@
 
 static void init(device_t dev)
 {
-	struct superio_ite_it8671f_config *conf;
+	struct superio_ite_it8671f_config *conf = dev->chip_info;
 	struct resource *res0, *res1;
 
-	if (!dev->enabled) {
+	if (!dev->enabled)
 		return;
-	}
-
-	conf = dev->chip_info;
 
 	switch (dev->path.pnp.device) {
 	case IT8671F_FDC: /* TODO. */

Modified: trunk/src/superio/ite/it8673f/Makefile.inc
==============================================================================
--- trunk/src/superio/ite/it8673f/Makefile.inc	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8673f/Makefile.inc	Mon Nov  8 16:16:30 2010	(r6047)
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-#config chip.h
 ramstage-$(CONFIG_SUPERIO_ITE_IT8673F) += superio.c
+

Modified: trunk/src/superio/ite/it8673f/chip.h
==============================================================================
--- trunk/src/superio/ite/it8673f/chip.h	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8673f/chip.h	Mon Nov  8 16:16:30 2010	(r6047)
@@ -18,8 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef _SUPERIO_ITE_IT8673F
-#define _SUPERIO_ITE_IT8673F
+#ifndef SUPERIO_ITE_IT8673F_CHIP_H
+#define SUPERIO_ITE_IT8673F_CHIP_H
 
 #include <device/device.h>
 #include <pc80/keyboard.h>
@@ -32,4 +32,4 @@
 	struct pc_keyboard keyboard;
 };
 
-#endif /* _SUPERIO_ITE_IT8673F */
+#endif

Modified: trunk/src/superio/ite/it8673f/it8673f.h
==============================================================================
--- trunk/src/superio/ite/it8673f/it8673f.h	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8673f/it8673f.h	Mon Nov  8 16:16:30 2010	(r6047)
@@ -19,12 +19,11 @@
  */
 
 /* Datasheet: http://www.datasheet4u.com/html/I/T/8/IT8673F_ITE.pdf.html */
-/* Status: Untested on real hardware, but it compiles. */
 
 #define IT8673F_FDC  0x00 /* Floppy */
 #define IT8673F_SP1  0x01 /* Com1 */
 #define IT8673F_SP2  0x02 /* Com2 */
 #define IT8673F_PP   0x03 /* Parallel port */
 #define IT8673F_FAN  0x04 /* Fan controller */
-#define IT8673F_KBCK 0x05 /* Keyboard */
-#define IT8673F_KBCM 0x06 /* Mouse */
+#define IT8673F_KBCK 0x05 /* PS/2 keyboard */
+#define IT8673F_KBCM 0x06 /* PS/2 mouse */

Modified: trunk/src/superio/ite/it8673f/it8673f_early_serial.c
==============================================================================
--- trunk/src/superio/ite/it8673f/it8673f_early_serial.c	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8673f/it8673f_early_serial.c	Mon Nov  8 16:16:30 2010	(r6047)
@@ -24,7 +24,7 @@
 /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
 #define SIO_BASE                    0x3f0
 #define SIO_INDEX                   SIO_BASE
-#define SIO_DATA                    SIO_BASE+1
+#define SIO_DATA                    (SIO_BASE + 1)
 
 /* Global configuration registers. */
 #define IT8673F_CONFIG_REG_CC       0x02   /* Configure Control (write-only). */
@@ -34,18 +34,18 @@
 
 #define IT8673F_CONFIGURATION_PORT  0x0279 /* Write-only. */
 
-/* Special values used for entering MB PnP mode. The first four bytes of
-   each line determine the address port, the last four are data. */
-static const uint8_t init_values[] = {
+/*
+ * Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data.
+ */
+static const u8 init_values[] = {
 	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
 	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
 	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
 	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
 };
 
-/* The content of IT8673F_CONFIG_REG_LDN (index 0x07) must be set to the
-   LDN the register belongs to, before you can access the register. */
-static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+static void it8673f_sio_write(u8 ldn, u8 index, u8 value)
 {
 	outb(IT8673F_CONFIG_REG_LDN, SIO_BASE);
 	outb(ldn, SIO_DATA);
@@ -53,10 +53,10 @@
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8673F Super I/O chip. */
-static void it8673f_enable_serial(device_t dev, unsigned iobase)
+/* Enable the serial port(s). */
+static void it8673f_enable_serial(device_t dev, u16 iobase)
 {
-	uint8_t i;
+	int i;
 
 	/* (1) Enter the configuration state (MB PnP mode). */
 
@@ -70,15 +70,14 @@
 	outb(0x55, IT8673F_CONFIGURATION_PORT);
 
 	/* Sequentially write the 32 special values. */
-	for (i = 0; i < 32; i++) {
+	for (i = 0; i < 32; i++)
 		outb(init_values[i], SIO_BASE);
-	}
 
 	/* (2) Modify the data of configuration registers. */
 
 	/* Enable all devices. */
-	it8673f_sio_write(IT8673F_SP1,  0x30, 0x1); /* Serial port 1 */
-	it8673f_sio_write(IT8673F_SP2,  0x30, 0x1); /* Serial port 2 */
+	it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */
+	it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */
 
 	/* Select 24MHz CLKIN (clear bit 0). */
 	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00);

Modified: trunk/src/superio/ite/it8673f/superio.c
==============================================================================
--- trunk/src/superio/ite/it8673f/superio.c	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8673f/superio.c	Mon Nov  8 16:16:30 2010	(r6047)
@@ -28,14 +28,11 @@
 
 static void init(device_t dev)
 {
-	struct superio_ite_it8673f_config *conf;
+	struct superio_ite_it8673f_config *conf = dev->chip_info;
 	struct resource *res0, *res1;
 
-	if (!dev->enabled) {
+	if (!dev->enabled)
 		return;
-	}
-
-	conf = dev->chip_info;
 
 	switch (dev->path.pnp.device) {
 	case IT8673F_FDC: /* TODO. */

Modified: trunk/src/superio/ite/it8705f/Makefile.inc
==============================================================================
--- trunk/src/superio/ite/it8705f/Makefile.inc	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8705f/Makefile.inc	Mon Nov  8 16:16:30 2010	(r6047)
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-#config chip.h
 ramstage-$(CONFIG_SUPERIO_ITE_IT8705F) += superio.c
+

Modified: trunk/src/superio/ite/it8705f/chip.h
==============================================================================
--- trunk/src/superio/ite/it8705f/chip.h	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8705f/chip.h	Mon Nov  8 16:16:30 2010	(r6047)
@@ -18,10 +18,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef _SUPERIO_ITE_IT8705F
-#define _SUPERIO_ITE_IT8705F
+#ifndef SUPERIO_ITE_IT8705F_CHIP_H
+#define SUPERIO_ITE_IT8705F_CHIP_H
 
-/* This chip doesn't seem to have keyboard and mouse support. */
+/* This chip doesn't have keyboard and mouse support. */
 
 #include <device/device.h>
 #include <uart8250.h>
@@ -32,4 +32,4 @@
 	struct uart8250 com1, com2;
 };
 
-#endif /* _SUPERIO_ITE_IT8705F */
+#endif

Modified: trunk/src/superio/ite/it8705f/it8705f.h
==============================================================================
--- trunk/src/superio/ite/it8705f/it8705f.h	Sun Nov  7 21:11:39 2010	(r6046)
+++ trunk/src/superio/ite/it8705f/it8705f.h	Mon Nov  8 16: