[coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7 (revised)

[Scott Duplichan]

-----Original Message-----
From: Marc Jones [mailto:marcj303 at gmail.com] 
Sent: Thursday, November 04, 2010 12:35 PM
To: Scott Duplichan
Cc: Arne Georg Gleditsch; Peter Stuge; Carl-Daniel Hailfinger; coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7 (revised)

]On Thu, Nov 4, 2010 at 10:03 AM, Scott Duplichan <scott at notabs.org> wrote:
]> -----Original Message-----
]
]> ]> +    // disable processor pcie mmio, if enabled
]> ]> +    if (is_family10h()) {
]> ]> +            msr_t temp;
]> ]> +            pcie_mmio_save = temp = rdmsr (0xc0010058);
]> ]> +            temp.lo &= ~1;
]> ]> +            wrmsr (0xc0010058, temp);
]> ]> +    }
]> ]> +
]> ]>      /* Get PCIe configuration space. */
]> ]>      MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0;
]> ]
]> ]This pci_read_config32 is targeting the Fam10 mmconf area, which is now
]> ]disabled.  Are we relying on the rs780 mmconf to back this address
]> ]region at this point?
]>
]> When I step through this pci_read_config32 call (on simnow) I see it using
]> the cf8/cfc method for config access, not the mmio method.
]
]
]This should be MMCONF with CONFIG_MMCONF_SUPPORT=y. Is that not the
]case? Did we miss something?

Yes, CONFIG_MMCONF_SUPPORT=y for my test. OK, so let's step through
pci_write_config32(). That sould be simple enough, probably 3 or 4
processor instructions? It turns out 112 instructions with the 
optimized build! Anyway, pci_read_config32() first calls get_pbus(dev).
In the context above, get_pbus(dev) returns null. It then passes this
null pointer to ops_pci_bus, which falls back to the cf8/cfc method
because that is what pci_check_direct() found to work. I believe for
whatever reasons, the fallback code is used for early execution. Once
execution reaches post code 40, the mmconf method is used.

Thanks,
Scott

]Marc
]
]
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