[coreboot] [commit] r6053 - trunk/src/superio/ite/it8661f
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svn at coreboot.org
Wed Nov 10 01:08:44 CET 2010
Author: uwe
Date: Wed Nov 10 01:08:42 2010
New Revision: 6053
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6053
Log:
ITE IT8661F changes to match the common code structure.
- it8661f_enable_serial() is now in the usual format, using pnp_* functions.
- Factor out pnp_enter_ext_func_mode()/pnp_exit_ext_func_mode().
- Factor out it8661f_set_clkin() to set the CLKIN to 24/48MHz.
- Factor out it8661f_enable_logical_devices(), might not be needed though.
We leave it here until it's confirmed on hardware that it's not needed.
- Move some #defines to it8661f.h.
- Drop no longer used it8661f_sio_write().
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Modified:
trunk/src/superio/ite/it8661f/it8661f.h
trunk/src/superio/ite/it8661f/it8661f_early_serial.c
trunk/src/superio/ite/it8661f/superio.c
Modified: trunk/src/superio/ite/it8661f/it8661f.h
==============================================================================
--- trunk/src/superio/ite/it8661f/it8661f.h Tue Nov 9 23:31:11 2010 (r6052)
+++ trunk/src/superio/ite/it8661f/it8661f.h Wed Nov 10 01:08:42 2010 (r6053)
@@ -23,6 +23,7 @@
/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */
+/* Logical device numbers (LDNs). */
#define IT8661F_FDC 0x00 /* Floppy */
#define IT8661F_SP1 0x01 /* Com1 */
#define IT8661F_SP2 0x02 /* Com2 */
@@ -30,4 +31,25 @@
#define IT8661F_IR 0x04 /* IR */
#define IT8661F_GPIO 0x05 /* GPIO & Alternate Function Configuration */
+/* Register and bit definitions. */
+#define IT8661F_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8661F_REG_LDE 0x23 /* PnP Logical Device Enable. */
+#define IT8661F_REG_SWSUSP 0x24 /* Software Suspend + Clock Select. */
+
+#define IT8661F_ISA_PNP_PORT 0x0279 /* Write-only. */
+
+#define IT8661F_CLKIN_24_MHZ 0
+#define IT8661F_CLKIN_48_MHZ 1
+
+/*
+ * Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data.
+ */
+static const u8 init_values[] = {
+ 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
+ 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
+ 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
+ 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
+};
+
#endif
Modified: trunk/src/superio/ite/it8661f/it8661f_early_serial.c
==============================================================================
--- trunk/src/superio/ite/it8661f/it8661f_early_serial.c Tue Nov 9 23:31:11 2010 (r6052)
+++ trunk/src/superio/ite/it8661f/it8661f_early_serial.c Wed Nov 10 01:08:42 2010 (r6053)
@@ -21,74 +21,59 @@
#include <arch/romcc_io.h>
#include "it8661f.h"
-/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
-#define SIO_BASE 0x3f0
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8661F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8661F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8661F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */
-#define IT8661F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend + Clock Select. */
+/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
+/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
+/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
+/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ int i;
+ u16 port = dev >> 8;
+
+ /* TODO: Don't hardcode Super I/O config port to 0x3f0. */
+ outb(0x86, IT8661F_ISA_PNP_PORT);
+ outb(0x80, IT8661F_ISA_PNP_PORT);
+ outb(0x55, IT8661F_ISA_PNP_PORT);
+ outb(0x55, IT8661F_ISA_PNP_PORT);
+
+ /* Sequentially write the 32 special values. */
+ for (i = 0; i < 32; i++)
+ outb(init_values[i], port);
+}
-#define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ pnp_write_config(dev, IT8661F_REG_CC, (1 << 1));
+}
/*
- * Special values used for entering MB PnP mode. The first four bytes of
- * each line determine the address port, the last four are data.
+ * The logical devices will only be involved in the ISA PnP sequence if their
+ * respective enable bits in IT8661F_REG_LDE are set.
+ *
+ * TODO: Find out if we actually need this (we use MB PnP mode).
+ *
+ * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved.
*/
-static const u8 init_values[] = {
- 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
- 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
- 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
- 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
-};
+static void it8661f_enable_logical_devices(device_t dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_write_config(dev, IT8661F_REG_LDE, 0x1f);
+ pnp_exit_ext_func_mode(dev);
+}
-static void it8661f_sio_write(u8 ldn, u8 index, u8 value)
+static void it8661f_set_clkin(device_t dev, u8 clkin)
{
- outb(IT8661F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
+ pnp_enter_ext_func_mode(dev);
+ pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1));
+ pnp_exit_ext_func_mode(dev);
}
-/* Enable the serial port(s). */
static void it8661f_enable_serial(device_t dev, u16 iobase)
{
- int i;
-
- /* (1) Enter the configuration state (MB PnP mode). */
-
- /* Perform MB PnP setup to put the SIO chip at 0x3f0. */
- /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
- /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
- /* Base address 0x370: 0x86 0x80 0xaa 0x55. */
- outb(0x86, IT8661F_CONFIGURATION_PORT);
- outb(0x80, IT8661F_CONFIGURATION_PORT);
- outb(0x55, IT8661F_CONFIGURATION_PORT);
- outb(0x55, IT8661F_CONFIGURATION_PORT);
-
- /* Sequentially write the 32 special values. */
- for (i = 0; i < 32; i++)
- outb(init_values[i], SIO_BASE);
-
- /* (2) Modify the data of configuration registers. */
-
- /*
- * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
- * PP (3), IR (4). Bits 5-7 are reserved.
- */
- it8661f_sio_write(0x00, IT8661F_CONFIG_REG_LDE, 0x1f);
-
- /* Enable serial port(s). */
- it8661f_sio_write(IT8661F_SP1, 0x30, 0x1); /* Serial port 1 */
- it8661f_sio_write(IT8661F_SP2, 0x30, 0x1); /* Serial port 2 */
-
- /* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode
- (clear bit 0). */
- it8661f_sio_write(0x00, IT8661F_CONFIG_REG_SWSUSP, 0x00);
-
- /* (3) Exit the configuration state (MB PnP mode). */
- it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02);
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
}
Modified: trunk/src/superio/ite/it8661f/superio.c
==============================================================================
--- trunk/src/superio/ite/it8661f/superio.c Tue Nov 9 23:31:11 2010 (r6052)
+++ trunk/src/superio/ite/it8661f/superio.c Wed Nov 10 01:08:42 2010 (r6053)
@@ -25,10 +25,12 @@
#include "chip.h"
#include "it8661f.h"
+/* TODO: Add pnp_enter_ext_func_mode() etc. and wrap functions. */
+
static void init(device_t dev)
{
struct superio_ite_it8661f_config *conf = dev->chip_info;
- struct resource *res0, *res1;
+ struct resource *res0;
if (!dev->enabled)
return;
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