[coreboot] [PATCH] ICH5: Add i82801ex_enable_rom() function
uwe at hermann-uwe.de
Thu Nov 25 20:42:54 CET 2010
On Thu, Nov 25, 2010 at 10:50:19AM +0000, Mark Marshall wrote:
> All of the blocks of code you are removing to a config_u32 and a
> config_u8 write. The code you've added does a config_u32 and a
> config_u16 write. Is this correct? Also the addresses that the
> writes go to are different - the removed code writes to 0xE8 and
> 0xF0 - your new code uses 0xE8 and 0xEE.
Yep, I think the patch is correct. Those
pci_write_config8(dev, 0xf0, 0x00);
lines I removed actually _disabled_ access to the 1MB ROM range,
no idea why. The power-on default is that the range is enabled,
so no need to touch the 0xf0 register (FB_DEC_EN2) or 0xe3 (FB_DEC_EN1).
The two remaining lines in the function are now
pci_write_config32(dev, FB_SEL1, 0x00000000);
pci_write_config16(dev, FB_SEL2, 0x0000);
which configures all ROM ranges to be accessible by the FWH chip
with IDSEL = 0, unless I misunderstand something here.
http://hermann-uwe.de | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
More information about the coreboot