From patrick at georgi-clan.de  Fri Oct  1 00:19:56 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 01 Oct 2010 00:19:56 +0200
Subject: [coreboot] [PATCH] Make hidden configuration flags visible (i945)
Message-ID: <4CA50D0C.8050208@georgi-clan.de>

Hi,

attached patch moves several config flags that, for historical reasons,
were put in romstage.c into Kconfig.

This ensures that all parts of the coreboot build on affected boards
have a chance to use these flags, which will be useful when removing
.c-includes in romstage.c

It's also a first step towards removing yet another config system
(manual #defines) from the tree.

Maybe these flags could be done away with somehow, maybe they should be
declared in other parts of the tree (eg. chipset). This is a first safe
step, so I didn't think too much about moving them elsewhere.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From mylesgw at gmail.com  Fri Oct  1 00:24:40 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Sep 2010 16:24:40 -0600
Subject: [coreboot] [PATCH] Make hidden configuration flags visible
	(i945)
In-Reply-To: <4CA50D0C.8050208@georgi-clan.de>
References: <4CA50D0C.8050208@georgi-clan.de>
Message-ID: <AANLkTi=S-3-vaBoyau8AiN76JA7qW_Y3wGCudjV5QQuy@mail.gmail.com>

On Thu, Sep 30, 2010 at 4:19 PM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Hi,
>
> attached patch moves several config flags that, for historical reasons,
> were put in romstage.c into Kconfig.

+choice
+	prompt "Chipset variant"
+	default I945GM
+	depends on NORTHBRIDGE_INTEL_I945
+	help
+	  Different i945 variants require slightly different setup.
+
+config I945GM
+	bool "i945GM (Mobile) chipset"
+
+config I945GC
+	bool "i945GC chipset"
+
+endchoice

I don't think this should be exposed to the user.  A board Kconfig
should select it, but there shouldn't be a menu prompt for it.

Thanks,
Myles



From patrick at georgi-clan.de  Fri Oct  1 00:31:21 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 01 Oct 2010 00:31:21 +0200
Subject: [coreboot] [PATCH] Make hidden configuration flags visible
	(i945)
In-Reply-To: <AANLkTi=S-3-vaBoyau8AiN76JA7qW_Y3wGCudjV5QQuy@mail.gmail.com>
References: <4CA50D0C.8050208@georgi-clan.de>
	<AANLkTi=S-3-vaBoyau8AiN76JA7qW_Y3wGCudjV5QQuy@mail.gmail.com>
Message-ID: <4CA50FB9.20804@georgi-clan.de>

Am 01.10.2010 00:24, schrieb Myles Watson:
> +choice
> +	prompt "Chipset variant"
> +	default I945GM
> +	depends on NORTHBRIDGE_INTEL_I945
> +	help
> +	  Different i945 variants require slightly different setup.
> +
> +config I945GM
> +	bool "i945GM (Mobile) chipset"
> +
> +config I945GC
> +	bool "i945GC chipset"
> +
> +endchoice
> 
> I don't think this should be exposed to the user.  A board Kconfig
> should select it, but there shouldn't be a menu prompt for it.
How to make it invisible, simply by removing the "prompt"? My primary
interest was in using choice to make sure Kconfig allows only either of
the values.


Patrick



From mylesgw at gmail.com  Fri Oct  1 00:35:06 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Sep 2010 16:35:06 -0600
Subject: [coreboot] [PATCH] Make hidden configuration flags visible
	(i945)
In-Reply-To: <4CA50FB9.20804@georgi-clan.de>
References: <4CA50D0C.8050208@georgi-clan.de>
	<AANLkTi=S-3-vaBoyau8AiN76JA7qW_Y3wGCudjV5QQuy@mail.gmail.com>
	<4CA50FB9.20804@georgi-clan.de>
Message-ID: <AANLkTikwCURY-n0Pm95nvO_U-pD6mBKchshbzV0w7e2U@mail.gmail.com>

On Thu, Sep 30, 2010 at 4:31 PM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 01.10.2010 00:24, schrieb Myles Watson:
>> +choice
>> + ? ? prompt "Chipset variant"
>> + ? ? default I945GM
>> + ? ? depends on NORTHBRIDGE_INTEL_I945
>> + ? ? help
>> + ? ? ? Different i945 variants require slightly different setup.
>> +
>> +config I945GM
>> + ? ? bool "i945GM (Mobile) chipset"
>> +
>> +config I945GC
>> + ? ? bool "i945GC chipset"
>> +
>> +endchoice
>>
>> I don't think this should be exposed to the user. ?A board Kconfig
>> should select it, but there shouldn't be a menu prompt for it.
> How to make it invisible, simply by removing the "prompt"? My primary
> interest was in using choice to make sure Kconfig allows only either of
> the values.

If that works, it's fine with me.  Otherwise, if there's only these
two variants, it could be collapsed to a single Kconfig option.  I
just think it's good to avoid options that are never correct in
user-visible Kconfig.

Thanks,
Myles



From svn at coreboot.org  Fri Oct  1 01:15:37 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 01:15:37 +0200
Subject: [coreboot] [commit] r5888 - in trunk/src/cpu: amd/car intel/car
	via/car
Message-ID: <E1P1SLh-0008Aj-8B@ra.coresystems.de>

Author: uwe
Date: Fri Oct  1 01:15:36 2010
New Revision: 5888
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5888

Log:
Various cosmetic and coding style fixes in CAR code (trivial).

Also, whitespace fixes, consistency fixes, and drop some of the less
useful comments.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/cpu/amd/car/cache_as_ram.inc
   trunk/src/cpu/intel/car/cache_as_ram.inc
   trunk/src/cpu/via/car/cache_as_ram.inc

Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc	Thu Sep 30 23:22:40 2010	(r5887)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc	Fri Oct  1 01:15:36 2010	(r5888)
@@ -18,76 +18,82 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define CacheSize CONFIG_DCACHE_RAM_SIZE
-#define CacheBase (0xd0000 - CacheSize)
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
+
+#define CacheSize		CONFIG_DCACHE_RAM_SIZE
+#define CacheBase		(0xd0000 - CacheSize)
 
-/* leave some space for global variable to pass to RAM stage */
-#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
+/* Leave some space for global variable to pass to RAM stage. */
+#define GlobalVarSize		CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 
-/* for CAR with FAM10 */
-#define CacheSizeAPStack 0x400 /* 1K */
+/* For CAR with Fam10h. */
+#define CacheSizeAPStack	0x400 /* 1K */
 
-#define MSR_MCFG_BASE  0xC0010058
-#define MSR_FAM10      0xC001102A
+#define MSR_MCFG_BASE		0xC0010058
+#define MSR_FAM10		0xC001102A
 
-#define jmp_if_k8(x)	comisd	%xmm2, %xmm1; jb x
+#define jmp_if_k8(x)		comisd	%xmm2, %xmm1; jb x
 
-#define CPUID_MASK	0x0ff00f00
+#define CPUID_MASK		0x0ff00f00
 #define CPUID_VAL_FAM10_ROTATED	0x0f000010
 
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
 /*
  * XMM map:
- *   xmm1: cpu family
- *   xmm2: fam10 comparison value
- *   xmm3: backup ebx
+ *   xmm1: CPU family
+ *   xmm2: Fam10h comparison value
+ *   xmm3: Backup EBX
  */
 
-	/* Save the BIST result */
+	/* Save the BIST result. */
 	movl	%eax, %ebp
 
-	/* for normal part %ebx already contain cpu_init_detected from fallback call */
+	/*
+	 * For normal part %ebx already contain cpu_init_detected
+	 * from fallback call.
+	 */
 
 cache_as_ram_setup:
 	post_code(0xa0)
 
-	/* enable SSE */
-	movl %cr4, %eax
-	orl $(3<<9), %eax
-	movl %eax, %cr4
+	/* Enable SSE. */
+	movl	%cr4, %eax
+	orl	$(3 << 9), %eax
+	movl	%eax, %cr4
 
-	/* figure out cpu family */
+	/* Figure out the CPU family. */
 	cvtsi2sd %ebx, %xmm3
 	movl	$0x01, %eax
 	cpuid
-	/* base family is bits 8..11, extended family is bits 20..27 */
+	/* Base family is bits 8..11, extended family is bits 20..27. */
 	andl	$CPUID_MASK, %eax
-	/* reorder bits for easier comparison by value */
+	/* Reorder bits for easier comparison by value. */
 	roll	$0x10, %eax
 	cvtsi2sd %eax, %xmm1
 	movl	$CPUID_VAL_FAM10_ROTATED, %eax
 	cvtsi2sd %eax, %xmm2
 	cvtsd2si %xmm3, %ebx
 
-	/* check if cpu_init_detected */
+	/* Check if cpu_init_detected. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	andl	$(1 << 11), %eax
-	movl	%eax, %ebx	/* We store the status */
+	movl	%eax, %ebx	/* We store the status. */
 
 	jmp_if_k8(CAR_FAM10_out_post_errata)
 
-	/* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */
-
-	/* Only BSP needed, for other nodes set during HT/memory init. */
-	/* So we need to check if it is BSP */
+	/*
+	 * For GH, CAR need to set DRAM Base/Limit registers to direct that
+	 * to node0.
+	 * Only BSP needed, for other nodes set during HT/memory init.
+	 * So we need to check if it is BSP.
+	 */
 	movl	$0x1b, %ecx
 	rdmsr
-	bt	$8, %eax /*BSC */
+	bt	$8, %eax /* BSC */
 	jnc	CAR_FAM10_out
 
-	/* Enable RT tables on BSP */
+	/* Enable RT tables on BSP. */
 	movl	$0x8000c06c, %eax
 	movw	$0xcf8, %dx
 	outl	%eax, %dx
@@ -96,7 +102,7 @@
 	btr	$0, %eax
 	outl	%eax, %dx
 
-	/* Setup temporary DRAM map: [0,16M) bit 0-23 */
+	/* Setup temporary DRAM map: [0,16M) bit 0-23. */
 	movl	$0x8000c144, %eax
 	movw	$0xcf8, %dx
 	outl	%eax, %dx
@@ -113,8 +119,9 @@
 
 CAR_FAM10_out:
 
-	/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
-	 * Re-enable it in after RAM is initialized and before CAR is disabled
+	/*
+	 * Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
+	 * Re-enable it in after RAM is initialized and before CAR is disabled.
 	 */
 	movl	$MSR_FAM10, %ecx
 	rdmsr
@@ -122,23 +129,13 @@
 	wrmsr
 
 	/* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
-
-	/* read-address has to be stored in the ecx register */
 	movl	$MSR_FAM10, %ecx
-
-	/* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */
 	rdmsr
-
-	/* Set bit 35 to 1 in EAX:EDX */
-	bts	$35-32, %edx
-
-	/* write back the modified register EDX:EAX to the MSR specified in ECX */
+	bts	$35-32, %edx	/* Set bit 35 in EDX:EAX (bit 3 in EDX). */
 	wrmsr
 
-	/* Erratum 343 end */
-
 #if CONFIG_MMCONF_SUPPORT
-	/* Set MMIO Config space BAR */
+	/* Set MMIO Config space BAR. */
 	movl	$MSR_MCFG_BASE, %ecx
 	rdmsr
 
@@ -152,7 +149,7 @@
 
 CAR_FAM10_out_post_errata:
 
-	/* Set MtrrFixDramModEn for clear fixed mtrr */
+	/* Set MtrrFixDramModEn for clear fixed MTRR. */
 enable_fixed_mtrr_dram_modify:
 	movl	$SYSCFG_MSR, %ecx
 	rdmsr
@@ -160,7 +157,7 @@
 	orl	$SYSCFG_MSR_MtrrFixDramModEn, %eax
 	wrmsr
 
-	/* Clear all MTRRs */
+	/* Clear all MTRRs. */
 	xorl	%edx, %edx
 	movl	$fixed_mtrr_msr, %esi
 
@@ -176,59 +173,63 @@
 	jmp	clear_fixed_var_mtrr
 clear_fixed_var_mtrr_out:
 
-/* 0x06 is the WB IO type for a given 4k segment.
+/*
+ * 0x06 is the WB IO type for a given 4k segment.
  * 0x1e is the MEM IO type for a given 4k segment (K10 and above).
  * segs is the number of 4k segments in the area of the particular
- *   register we want to use for CAR.
+ *      register we want to use for CAR.
  * reg is the register where the IO type should be stored.
  */
 .macro extractmask segs, reg
 .if \segs <= 0
-	/* The xorl here is superfluous because at the point of first execution
+	/*
+	 * The xorl here is superfluous because at the point of first execution
 	 * of this macro, %eax and %edx are cleared. Later invocations of this
 	 * macro will have a monotonically increasing segs parameter.
 	 */
-	xorl \reg, \reg
+	xorl	\reg, \reg
 .else
 	jmp_if_k8(1f)
 
 .if \segs == 1
-	movl $0x1e000000, \reg /* WB MEM type */
+	movl	$0x1e000000, \reg /* WB MEM type */
 .elseif \segs == 2
-	movl $0x1e1e0000, \reg /* WB MEM type */
+	movl	$0x1e1e0000, \reg /* WB MEM type */
 .elseif \segs == 3
-	movl $0x1e1e1e00, \reg /* WB MEM type */
+	movl	$0x1e1e1e00, \reg /* WB MEM type */
 .elseif \segs >= 4
-	movl $0x1e1e1e1e, \reg /* WB MEM type */
+	movl	$0x1e1e1e1e, \reg /* WB MEM type */
 .endif
 	jmp 2f
 1:
 .if \segs == 1
-	movl $0x06000000, \reg /* WB IO type */
+	movl	$0x06000000, \reg /* WB IO type */
 .elseif \segs == 2
-	movl $0x06060000, \reg /* WB IO type */
+	movl	$0x06060000, \reg /* WB IO type */
 .elseif \segs == 3
-	movl $0x06060600, \reg /* WB IO type */
+	movl	$0x06060600, \reg /* WB IO type */
 .elseif \segs >= 4
-	movl $0x06060606, \reg /* WB IO type */
+	movl	$0x06060606, \reg /* WB IO type */
 .endif
 2:
 .endif /* if \segs <= 0 */
 .endm
 
-/* size is the cache size in bytes we want to use for CAR.
- * windowoffset is the 32k-aligned window into CAR size
+/*
+ * size is the cache size in bytes we want to use for CAR.
+ * windowoffset is the 32k-aligned window into CAR size.
  */
 .macro simplemask carsize, windowoffset
 	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
 	extractmask gas_bug_workaround, %eax
 	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
 	extractmask gas_bug_workaround, %edx
-/* Without the gas bug workaround, the entire macro would consist only of the
- * two lines below.
-	extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
-	extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
- */
+	/*
+	 * Without the gas bug workaround, the entire macro would consist
+	 * only of the two lines below:
+	 *   extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
+	 *   extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+	 */
 .endm
 
 #if CacheSize > 0x10000
@@ -242,18 +243,18 @@
 #endif
 
 #if CacheSize > 0x8000
-	/* enable caching for 32K-64K using fixed mtrr */
+	/* Enable caching for 32K-64K using fixed MTRR. */
 	movl	$MTRRfix4K_C0000_MSR, %ecx
 	simplemask CacheSize, 0x8000
 	wrmsr
 #endif
 
-	/* enable caching for 0-32K using fixed mtrr */
+	/* Enable caching for 0-32K using fixed MTRR. */
 	movl	$MTRRfix4K_C8000_MSR, %ecx
 	simplemask CacheSize, 0
 	wrmsr
 
-	/* enable memory access for first MBs using top_mem */
+	/* Enable memory access for first MBs using top_mem. */
 	movl	$TOP_MEM, %ecx
 	xorl	%edx, %edx
 	movl	$(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
@@ -267,13 +268,13 @@
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
 
-	/* enable write base caching so we can do execute in place
-	 * on the flash rom.
+	/* Enable write base caching so we can do execute in place (XIP)
+	 * on the flash ROM.
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
-	movl    $REAL_XIP_ROM_BASE, %eax
-	orl     $MTRR_TYPE_WRBACK, %eax
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
@@ -285,14 +286,13 @@
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-	/* Set the default memory type and enable fixed and variable MTRRs */
+	/* Set the default memory type and enable fixed and variable MTRRs. */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
-	/* Enable Variable and Fixed MTRRs */
-	movl	$0x00000c00, %eax
+	movl	$0x00000c00, %eax	/* Enable variable and fixed MTRRs. */
 	wrmsr
 
-	/* Enable the MTRRs and IORRs in SYSCFG */
+	/* Enable the MTRRs and IORRs in SYSCFG. */
 	movl	$SYSCFG_MSR, %ecx
 	rdmsr
 	orl	$(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
@@ -300,35 +300,35 @@
 
 	post_code(0xa1)
 
-	/* enable cache */
+	/* Enable cache. */
 	movl	%cr0, %eax
 	andl	$0x9fffffff, %eax
 	movl	%eax, %cr0
 
 	jmp_if_k8(fam10_end_part1)
 
-	/* So we need to check if it is BSP */
+	/* So we need to check if it is BSP. */
 	movl	$0x1b, %ecx
 	rdmsr
-	bt	$8, %eax /*BSC */
+	bt	$8, %eax /* BSC */
 	jnc	CAR_FAM10_ap
 fam10_end_part1:
 
 	post_code(0xa2)
 
-	/* Read the range with lodsl*/
+	/* Read the range with lodsl. */
 	cld
 	movl	$CacheBase, %esi
 	movl	$(CacheSize >> 2), %ecx
 	rep	lodsl
 
-	/* Clear the range */
+	/* Clear the range. */
 	movl	$CacheBase, %edi
 	movl	$(CacheSize >> 2), %ecx
 	xorl	%eax, %eax
 	rep	stosl
 
-	/* set up the stack pointer */
+	/* Set up the stack pointer. */
 	movl	$(CacheBase + CacheSize - GlobalVarSize), %eax
 	movl	%eax, %esp
 
@@ -336,42 +336,47 @@
 
 	jmp	CAR_FAM10_ap_out
 CAR_FAM10_ap:
-	/* need to set stack pointer for AP */
-	/* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/
-	/* So need to get the NodeID and CoreID at first */
-	/* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */
+	/*
+	 * Need to set stack pointer for AP.
+	 * It will be from:
+	 *   CacheBase + (CacheSize - GlobalVarSize) / 2
+	 *   - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack
+	 * So need to get the NodeID and CoreID at first.
+	 * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need
+	 * to reverse it.
+	 */
 
-	/* store our init detected */
+	/* Store our init detected. */
 	movl	%ebx, %esi
 
-	/* get the coreid bits at first */
+	/* Get the coreid bits at first. */
 	movl	$0x80000008, %eax
 	cpuid
 	shrl	$12, %ecx
 	andl	$0x0f, %ecx
 	movl	%ecx, %edi
 
-	/* get the initial apic id */
+	/* Get the initial APIC ID. */
 	movl	$1, %eax
 	cpuid
 	shrl	$24, %ebx
 
-	/* get the nb cfg bit 54 */
-	movl	$0xc001001f, %ecx /* NB_CFG_MSR */
+	/* Get the nb cfg bit 54. */
+	movl	$0xc001001f, %ecx	/* NB_CFG_MSR */
 	rdmsr
-	movl	%edi, %ecx	/* CoreID bits */
+	movl	%edi, %ecx		/* CoreID bits */
 	bt	$(54-32), %edx
 	jc	roll_cfg
 	rolb	%cl, %bl
 roll_cfg:
 
-	/* calculate stack pointer */
+	/* Calculate stack pointer. */
 	movl	$CacheSizeAPStack, %eax
 	mull	%ebx
-	movl	$(CacheBase + (CacheSize - GlobalVarSize)/2), %esp
+	movl	$(CacheBase + (CacheSize - GlobalVarSize) / 2), %esp
 	subl	%eax, %esp
 
-	/* retrive init detected */
+	/* Retrive init detected. */
 	movl	%esi, %ebx
 
 	post_code(0xa4)
@@ -380,35 +385,38 @@
 
 	post_code(0xa5)
 
-	/* disable SSE */
-	movl %cr4, %eax
-	andl $~(3<<9), %eax
-	movl %eax, %cr4
+	/* Disable SSE. */
+	movl	%cr4, %eax
+	andl	$~(3 << 9), %eax
+	movl	%eax, %cr4
 
-	/* Restore the BIST result */
+	/* Restore the BIST result. */
 	movl	%ebp, %eax
 
-	/* We need to set ebp ? No need */
+	/* We need to set EBP? No need. */
 	movl	%esp, %ebp
-	pushl	%ebx  /* init detected */
-	pushl	%eax  /* bist */
+	pushl	%ebx		/* Init detected. */
+	pushl	%eax		/* BIST */
 	call	cache_as_ram_main
-	/* We will not go back */
+	/* We will not go back. */
 
-	post_code(0xaf)		/* Should never see this postcode */
+	post_code(0xaf)		/* Should never see this POST code. */
 
 fixed_mtrr_msr:
 	.long	0x250, 0x258, 0x259
 	.long	0x268, 0x269, 0x26A
 	.long	0x26B, 0x26C, 0x26D
 	.long	0x26E, 0x26F
+
 var_mtrr_msr:
 	.long	0x200, 0x201, 0x202, 0x203
 	.long	0x204, 0x205, 0x206, 0x207
 	.long	0x208, 0x209, 0x20A, 0x20B
 	.long	0x20C, 0x20D, 0x20E, 0x20F
+
 var_iorr_msr:
 	.long	0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
+
 mem_top:
 	.long	0xC001001A, 0xC001001D
 	.long	0x000 /* NULL, end of table */

Modified: trunk/src/cpu/intel/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/car/cache_as_ram.inc	Thu Sep 30 23:22:40 2010	(r5887)
+++ trunk/src/cpu/intel/car/cache_as_ram.inc	Fri Oct  1 01:15:36 2010	(r5888)
@@ -21,18 +21,18 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define CacheSize CONFIG_DCACHE_RAM_SIZE
-#define CacheBase (0xd0000 - CacheSize)
-
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/lapic_def.h>
 
-	/* Save the BIST result */
+#define CacheSize		CONFIG_DCACHE_RAM_SIZE
+#define CacheBase		(0xd0000 - CacheSize)
+
+	/* Save the BIST result. */
 	movl	%eax, %ebp
 
 CacheAsRam:
-	// Check whether the processor has HT capability
+	/* Check whether the processor has HT capability. */
 	movl	$01, %eax
 	cpuid
 	btl	$28, %edx
@@ -41,20 +41,26 @@
 	cmpb	$01, %bh
 	jbe	NotHtProcessor
 
-	// It is a HT processor; Send SIPI to the other logical processor
-	// within this processor so that the CAR related common system 
-	// registers are programmed accordingly.
+	/*
+	 * It is a HT processor. Send SIPI to the other logical processor
+	 * within this processor so that the CAR related common system
+	 * registers are programmed accordingly.
+	 */
 
-	// Use some register that is common to both logical processors
-	// as semaphore. Refer Appendix B, Vol.3
+	/*
+	 * Use some register that is common to both logical processors
+	 * as semaphore. Refer Appendix B, Vol.3.
+	 */
 	xorl	%eax, %eax
 	xorl	%edx, %edx
 	movl	$MTRRfix64K_00000_MSR, %ecx
 	wrmsr
 
-	// Figure out the logical AP's APIC ID; the following logic will
-	// work only for processors with 2 threads.
-	// Refer to Vol 3. Table 7-1 for details about this logic
+	/*
+	 * Figure out the logical AP's APIC ID; the following logic will
+	 * work only for processors with 2 threads.
+	 * Refer to Vol 3. Table 7-1 for details about this logic.
+	 */
 	movl	$0xFEE00020, %esi
 	movl	(%esi), %ebx
 	andl	$0xFF000000, %ebx
@@ -66,17 +72,19 @@
 LogicalAP0:
 	orb	$0x01, %bl
 Send_SIPI:
-	bswapl	%ebx  // ebx - logical AP's APIC ID
+	bswapl	%ebx	/* EBX - logical AP's APIC ID. */
 
-	// Fill up the IPI command registers in the Local APIC mapped to
-	// default address and issue SIPI to the other logical processor
-	// within this processor die.
+	/*
+	 * Fill up the IPI command registers in the Local APIC mapped to
+	 * default address and issue SIPI to the other logical processor
+	 * within this processor die.
+	 */
 Retry_SIPI:
 	movl	%ebx, %eax
 	movl	$0xFEE00310, %esi
 	movl	%eax, (%esi)
 
-	// SIPI vector - F900:0000
+	/* SIPI vector - F900:0000 */
 	movl	$0x000006F9, %eax
 	movl	$0xFEE00300, %esi
 	movl	%eax, (%esi)
@@ -91,7 +99,7 @@
 	andl	$0x00001000, %eax
 	jnz	Retry_SIPI
 
-	// Wait for the Logical AP to complete initialization
+	/* Wait for the Logical AP to complete initialization. */
 LogicalAP_SIPINotdone:
 	movl	$MTRRfix64K_00000_MSR, %ecx
 	rdmsr
@@ -99,14 +107,13 @@
 	jz	LogicalAP_SIPINotdone
 
 NotHtProcessor:
-	/* Set the default memory type and enable fixed and variable MTRRs */
+	/* Set the default memory type and enable fixed and variable MTRRs. */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
-	/* Enable Variable and Fixed MTRRs */
-	movl	$0x00000c00, %eax
+	movl	$0x00000c00, %eax	/* Enable variable and fixed MTRRs. */
 	wrmsr
 
-	/* Clear all MTRRs */
+	/* Clear all MTRRs. */
 	xorl	%edx, %edx
 	movl	$fixed_mtrr_msr, %esi
 
@@ -126,6 +133,7 @@
 	.long	0x268, 0x269, 0x26A
 	.long	0x26B, 0x26C, 0x26D
 	.long	0x26E, 0x26F
+
 var_mtrr_msr:
 	.long	0x200, 0x201, 0x202, 0x203
 	.long	0x204, 0x205, 0x206, 0x207
@@ -135,14 +143,16 @@
 
 clear_fixed_var_mtrr_out:
 
-/* 0x06 is the WB IO type for a given 4k segment.
+/*
+ * 0x06 is the WB IO type for a given 4k segment.
  * segs is the number of 4k segments in the area of the particular
  *      register we want to use for CAR.
  * reg  is the register where the IO type should be stored.
  */
 .macro extractmask segs, reg
 .if \segs <= 0
-	/* The xorl here is superfluous because at the point of first execution
+	/*
+	 * The xorl here is superfluous because at the point of first execution
 	 * of this macro, %eax and %edx are cleared. Later invocations of this
 	 * macro will have a monotonically increasing segs parameter.
 	 */
@@ -158,19 +168,21 @@
 .endif
 .endm
 
-/* size is the cache size in bytes we want to use for CAR.
- * windowoffset is the 32k-aligned window into CAR size
+/*
+ * size is the cache size in bytes we want to use for CAR.
+ * windowoffset is the 32k-aligned window into CAR size.
  */
 .macro simplemask carsize, windowoffset
 	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
 	extractmask gas_bug_workaround, %eax
 	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
 	extractmask gas_bug_workaround, %edx
-/* Without the gas bug workaround, the entire macro would consist only of the
- * two lines below.
-	extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
-	extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
- */
+	/*
+	 * Without the gas bug workaround, the entire macro would consist
+	 * only of the two lines below:
+	 *   extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
+	 *   extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+	 */
 .endm
 
 #if CacheSize > 0x10000
@@ -184,13 +196,13 @@
 #endif
 
 #if CacheSize > 0x8000
-	/* enable caching for 32K-64K using fixed mtrr */
+	/* Enable caching for 32K-64K using fixed MTRR. */
 	movl	$MTRRfix4K_C0000_MSR, %ecx
 	simplemask CacheSize, 0x8000
 	wrmsr
 #endif
 
-	/* enable caching for 0-32K using fixed mtrr */
+	/* Enable caching for 0-32K using fixed MTRR. */
 	movl	$MTRRfix4K_C8000_MSR, %ecx
 	simplemask CacheSize, 0
 	wrmsr
@@ -203,8 +215,9 @@
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
 
-	/* enable write base caching so we can do execute in place
-	 * on the flash rom.
+	/*
+	 * Enable write base caching so we can do execute in place (XIP)
+	 * on the flash ROM.
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
@@ -218,27 +231,27 @@
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-	/* enable cache */
+	/* Enable cache. */
 	movl	%cr0, %eax
 	andl	$0x9fffffff, %eax
 	movl	%eax, %cr0
 
-	/* Read the range with lodsl*/
+	/* Read the range with lodsl. */
 	movl	$CacheBase, %esi
 	cld
 	movl	$(CacheSize >> 2), %ecx
 	rep	lodsl
 
-	/* Clear the range */
+	/* Clear the range. */
 	movl	$CacheBase, %edi
 	movl	$(CacheSize >> 2), %ecx
 	xorl	%eax, %eax
 	rep	stosl
 
 #if 0
-	/* check the cache as ram */
+	/* Check the cache as ram. */
 	movl	$CacheBase, %esi
-	movl	$(CacheSize>>2), %ecx
+	movl	$(CacheSize >> 2), %ecx
 .xin1:
 	movl	%esi, %eax
 	movl	%eax, (%esi)
@@ -249,29 +262,30 @@
 .xout1:
 
 	movl	$CacheBase, %esi
-//        movl    $(CacheSize>>2), %ecx
-	movl $4, %ecx
+	// movl	$(CacheSize >> 2), %ecx
+	movl	$4, %ecx
 .xin1x:
 	movl	%esi, %eax
 
 	movl	$0x4000, %edx
 	movb	%ah, %al
 .testx1:
-	outb %al, $0x80
+	outb	%al, $0x80
 	decl	%edx
-	jnz .testx1
+	jnz	.testx1
 
 	movl	(%esi), %eax
-	cmpb 0xff, %al
-	je .xin2  /* dont show */
+	cmpb	0xff, %al
+	je	.xin2	/* Don't show. */
 
 	movl	$0x4000, %edx
 .testx2:
-	outb %al, $0x80
+	outb	%al, $0x80
 	decl	%edx
-	jnz .testx2
+	jnz	.testx2
 
-.xin2:  decl     %ecx
+.xin2:
+	decl	%ecx
 	je	.xout1x
 	add	$4, %esi
 	jmp	.xin1x
@@ -281,21 +295,22 @@
 	movl	$(CacheBase + CacheSize - 4), %eax
 	movl	%eax, %esp
 lout:
-	/* Restore the BIST result */
+	/* Restore the BIST result. */
 	movl	%ebp, %eax
 
-	/* We need to set ebp ? No need */
+	/* We need to set EBP? No need. */
 	movl	%esp, %ebp
-	pushl	%eax  /* bist */
+	pushl	%eax  /* BIST */
 	call	main
 
-        /* We don't need cache as ram for now on */
-        /* disable cache */
+	/* We don't need CAR for now on. */
+
+	/* Disable cache. */
 	movl	%cr0, %eax
-	orl	$(0x1<<30),%eax
+	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
-        /* clear sth */
+	/* Clear sth. */
 	movl	$MTRRfix4K_C8000_MSR, %ecx
 	xorl	%edx, %edx
 	xorl	%eax, %eax
@@ -306,25 +321,25 @@
 	wrmsr
 #endif
 
-	/* Set the default memory type and disable fixed
-	 * and enable variable MTRRs
+	/*
+	 * Set the default memory type and disable fixed
+	 * and enable variable MTRRs.
 	 */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
-        /* Enable Variable and Disable Fixed MTRRs */
-	movl	$0x00000800, %eax
+	movl	$0x00000800, %eax /* Enable variable and disable fixed MTRRs. */
 	wrmsr
 
-        /* enable cache */
+	/* Enable cache. */
 	movl	%cr0, %eax
-	andl	$0x9fffffff,%eax
+	andl	$0x9fffffff, %eax
 	movl	%eax, %cr0
 
-	/* clear boot_complete flag */
+	/* Clear boot_complete flag. */
 	xorl	%ebp, %ebp
 __main:
 	post_code(0x11)
-	cld			/* clear direction flag */
+	cld			/* Clear direction flag. */
 
 	movl	%ebp, %esi
 

Modified: trunk/src/cpu/via/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/via/car/cache_as_ram.inc	Thu Sep 30 23:22:40 2010	(r5887)
+++ trunk/src/cpu/via/car/cache_as_ram.inc	Fri Oct  1 01:15:36 2010	(r5888)
@@ -25,31 +25,30 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define CacheSize CONFIG_DCACHE_RAM_SIZE
-#define CacheBase CONFIG_DCACHE_RAM_BASE
-
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
-	/* Save the BIST result */
+#define CacheSize		CONFIG_DCACHE_RAM_SIZE
+#define CacheBase		CONFIG_DCACHE_RAM_BASE
+
+	/* Save the BIST result. */
 	movl	%eax, %ebp
 
 CacheAsRam:
 
-	/* disable cache */
+	/* Disable cache. */
 	movl	%cr0, %eax
-	orl	$(0x1<<30),%eax
-	movl	%eax,%cr0
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
 	invd
 
-	/* Set the default memory type and enable fixed and variable MTRRs */
+	/* Set the default memory type and enable fixed and variable MTRRs. */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
-	/* Enable Variable and Fixed MTRRs */
-	movl	$0x00000c00, %eax
+	movl	$0x00000c00, %eax	/* Enable variable and fixed MTRRs. */
 	wrmsr
 
-	/* Clear all MTRRs */
+	/* Clear all MTRRs. */
 	xorl	%edx, %edx
 	movl	$fixed_mtrr_msr, %esi
 
@@ -80,13 +79,13 @@
 clear_fixed_var_mtrr_out:
 	movl	$MTRRphysBase_MSR(0), %ecx
 	xorl	%edx, %edx
-	movl	$(CacheBase|MTRR_TYPE_WRBACK),%eax
+	movl	$(CacheBase | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(0), %ecx
 	/* This assumes we never access addresses above 2^36 in CAR. */
-	movl	$0x0000000f,%edx
-	movl	$(~(CacheSize-1)|0x800),%eax
+	movl	$0x0000000f, %edx
+	movl	$(~(CacheSize - 1) | 0x800), %eax
 	wrmsr
 
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
@@ -95,13 +94,14 @@
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
 
-	/* enable write base caching so we can do execute in place
-	 * on the flash rom.
+	/*
+	 * Enable write base caching so we can do execute in place (XIP)
+	 * on the flash ROM.
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
-	movl    $REAL_XIP_ROM_BASE, %eax
-	orl     $MTRR_TYPE_WRBACK, %eax
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
@@ -111,39 +111,41 @@
 
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
-	/* Enable Variable and Fixed MTRRs */
-	movl	$0x00000800, %eax
+	movl	$0x00000800, %eax	/* Enable variable and fixed MTRRs. */
 	wrmsr
 
 	movl	%cr0, %eax
 	andl	$0x9fffffff, %eax
 	movl	%eax, %cr0
 
-	/* Read the range with lodsl*/
+	/* Read the range with lodsl. */
 	cld
 	movl	$CacheBase, %esi
 	movl	%esi, %edi
-	movl	$(CacheSize>>2), %ecx
+	movl	$(CacheSize >> 2), %ecx
 	rep	lodsl
 
 	movl	$CacheBase, %esi
 	movl	%esi, %edi
 	movl	$(CacheSize >> 2), %ecx
 
-	/* 0x5c5c5c5c is a memory test pattern.
-	 * TODO: Check if everything works with the zero pattern as well. */
-	/*xorl	%eax, %eax*/
-	xorl	$0x5c5c5c5c,%eax
+	/*
+	 * 0x5c5c5c5c is a memory test pattern.
+	 * TODO: Check if everything works with the zero pattern as well.
+	 */
+	/* xorl	%eax, %eax */
+	xorl	$0x5c5c5c5c, %eax
 	rep	stosl
 
 #ifdef CARTEST
 	movl	REAL_XIP_ROM_BASE, %esi
 	movl	%esi, %edi
-	movl	$(CONFIG_XIP_ROM_SIZE>>2), %ecx
+	movl	$(CONFIG_XIP_ROM_SIZE >> 2), %ecx
 	rep	lodsl
 #endif
 
-	/* The key point of this CAR code is C7 cache does not turn into
+	/*
+	 * The key point of this CAR code is C7 cache does not turn into
 	 * "no fill" mode, which is not compatible with general CAR code.
 	 */
 
@@ -155,27 +157,27 @@
 	post_code(0x40)
 	xorl	%edx, %edx
 	xorl	%eax, %eax
-	movl	$0x5c5c,%edx
-	pushl %edx
-	pushl %edx
-	pushl %edx
-	pushl %edx
-	pushl %edx
+	movl	$0x5c5c, %edx
+	pushl	%edx
+	pushl	%edx
+	pushl	%edx
+	pushl	%edx
+	pushl	%edx
 	popl	%esi
 	popl	%esi
 	popl	%eax
 	popl	%eax
 	popl	%eax
-	cmpl %edx,%eax
-	jne stackerr
+	cmpl	%edx, %eax
+	jne	stackerr
 #endif
 
-	/* Restore the BIST result */
+	/* Restore the BIST result. */
 	movl	%ebp, %eax
 
-	/* We need to set ebp ? No need */
+	/* We need to set EBP? No need. */
 	movl	%esp, %ebp
-	pushl	%eax  /* bist */
+	pushl	%eax	/* BIST */
 	call	main
 
 	/*
@@ -184,94 +186,96 @@
 	 *       want to go back.
 	 */
 
-	/* We don't need cache as ram for now on */
-	/* disable cache */
-	movl    %cr0, %eax
-	orl    $(0x1<<30),%eax
-	movl    %eax, %cr0
-
+	/* We don't need CAR for now on. */
 
-	/* Set the default memory type and disable fixed and enable variable MTRRs */
-	movl    $MTRRdefType_MSR, %ecx
-	xorl    %edx, %edx
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
 
-	/* Enable Variable and Disable Fixed MTRRs */
-	movl    $0x00000800, %eax
+	/*
+	 * Set the default memory type and disable fixed and enable
+	 * variable MTRRs.
+	 */
+	movl	$MTRRdefType_MSR, %ecx
+	xorl	%edx, %edx
+	movl	$0x00000800, %eax /* Enable variable & disable fixed MTRRs. */
 	wrmsr
 
-	/* enable caching for first 1M using variable mtrr */
+	/* Enable caching for first 1M using variable MTRR. */
 	movl	$MTRRphysBase_MSR(0), %ecx
-	xorl    %edx, %edx
-	movl     $(0 | 6), %eax
-	//movl     $(0 | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	movl	$(0 | 6), %eax
+	// movl	$(0 | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
-	/* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
+	/*
+	 * Enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
 	 * If 1M cacheable, then when S3 resume, there is stange color on
-	 * screen for 2 sec. suppose problem of a0000-dfffff and cache.
+	 * screen for 2 sec. Suppose problem of a0000-dfffff and cache.
 	 * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.
 	 */
 
 	movl	$MTRRphysMask_MSR(0), %ecx
-	movl    $0x0000000f, %edx /* AMD 40 bit 0xff*/
- 	movl    $((~(( 0 + 0x80000) - 1)) | 0x800), %eax
+	movl	$0x0000000f, %edx	/* AMD 40 bit 0xff */
+	movl	$((~((0 + 0x80000) - 1)) | 0x800), %eax
 	wrmsr
 
 	movl	$MTRRphysBase_MSR(1), %ecx
-	xorl    %edx, %edx
-	movl     $(0x80000 | 6), %eax
-	orl     $(0 | 6), %eax
+	xorl	%edx, %edx
+	movl	$(0x80000 | 6), %eax
+	orl	$(0 | 6), %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl    $0x0000000f, %edx /* AMD 40 bit 0xff*/
- 	movl    $((~(( 0 + 0x20000) - 1)) | 0x800), %eax
+	movl	$0x0000000f, %edx	/* AMD 40 bit 0xff */
+	movl	$((~((0 + 0x20000) - 1)) | 0x800), %eax
 	wrmsr
 
 	movl	$MTRRphysBase_MSR(2), %ecx
-	xorl    %edx, %edx
-	movl     $(0xc0000 | 6), %eax
-	orl     $(0 | 6), %eax
+	xorl	%edx, %edx
+	movl	$(0xc0000 | 6), %eax
+	orl	$(0 | 6), %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(2), %ecx
-	movl    $0x0000000f, %edx /* AMD 40 bit 0xff*/
-	movl    $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
+	movl	$0x0000000f, %edx	/* AMD 40 bit 0xff */
+	movl	$((~(( 0 + 0x40000) - 1)) | 0x800), %eax
 	wrmsr
 
-	/* cache XIP_ROM_BASE-SIZE to speedup coreboot code */
+	/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
 	movl	$MTRRphysBase_MSR(3), %ecx
-	xorl    %edx, %edx
-	movl     $REAL_XIP_ROM_BASE,%eax
-	orl     $(0 | 6), %eax
+	xorl	%edx, %edx
+	movl	$REAL_XIP_ROM_BASE,%eax
+	orl	$(0 | 6), %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(3), %ecx
-	xorl    %edx, %edx
-	movl     $CONFIG_XIP_ROM_SIZE,%eax
+	xorl	%edx, %edx
+	movl	$CONFIG_XIP_ROM_SIZE, %eax
 	decl	%eax
 	notl	%eax
-	orl     $(0 | 0x800), %eax
+	orl	$(0 | 0x800), %eax
 	wrmsr
 
-	/* enable cache */
-	movl    %cr0, %eax
-	andl    $0x9fffffff,%eax
-	movl    %eax, %cr0
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$0x9fffffff, %eax
+	movl	%eax, %cr0
 	invd
 
-	/* clear boot_complete flag */
+	/* Clear boot_complete flag. */
 	xorl	%ebp, %ebp
 __main:
 	post_code(0x11)
-	cld			/* clear direction flag */
+	cld			/* Clear direction flag. */
 
 	movl	%ebp, %esi
 
-	movl $ROMSTAGE_STACK, %esp
+	movl	$ROMSTAGE_STACK, %esp
 	movl	%esp, %ebp
-	pushl %esi
-	call copy_and_run
+	pushl	%esi
+	call	copy_and_run
 
 .Lhlt:
 	post_code(0xee)



From jakllsch at kollasch.net  Fri Oct  1 01:26:29 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Thu, 30 Sep 2010 23:26:29 +0000
Subject: [coreboot] [patch] spelling fixes for comments in
 src/northbridge/amd/amdk8/misc_control.c
Message-ID: <20100930232629.GA12447@tarantulon.kollasch.net>

Fix spelling/typos in comments.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
---
-------------- next part --------------
Index: src/northbridge/amd/amdk8/misc_control.c
===================================================================
--- src/northbridge/amd/amdk8/misc_control.c	(revision 5887)
+++ src/northbridge/amd/amdk8/misc_control.c	(working copy)
@@ -1,6 +1,6 @@
 /* Turn off machine check triggers when reading
- * pci space where there are no devices.
- * This is necessary when scaning the bus for
+ * PCI space where there are no devices.
+ * This is necessary when scanning the bus for
  * devices which is done by the kernel
  *
  * written in 2003 by Eric Biederman
@@ -26,13 +26,13 @@
  *
  * @param
  *
- * There is only one AGP aperture resource needed. The resoruce is added to
+ * There is only one AGP aperture resource needed. The resource is added to
  * the northbridge of BSP.
  *
  * The same trick can be used to augment legacy VGA resources which can
- * be detect by generic pci reousrce allocator for VGA devices.
+ * be detect by generic PCI resource allocator for VGA devices.
  * BAD: it is more tricky than I think, the resource allocation code is
- * implemented in a way to NOT DOING legacy VGA resource allcation on
+ * implemented in a way to NOT DOING legacy VGA resource allocation on
  * purpose :-(.
  */
 static void mcf3_read_resources(device_t dev)
@@ -42,7 +42,7 @@
 	/* Read the generic PCI resources */
 	pci_dev_read_resources(dev);
 
-	/* If we are not the first processor don't allocate the gart apeture */
+	/* If we are not the first processor don't allocate the GART aperture */
 	if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
 		return;
 	}
@@ -51,7 +51,7 @@
 	get_option(&iommu, "iommu");
 
 	if (iommu) {
-		/* Add a Gart apeture resource */
+		/* Add a GART aperture resource */
 		resource = new_resource(dev, 0x94);
 		resource->size = CONFIG_AGP_APERTURE_SIZE;
 		resource->align = log2(resource->size);
@@ -79,7 +79,7 @@
 		/* Get the base address */
 		gart_base = ((resource->base) >> 25) & 0x00007fff;
 
-		/* Update the other northbriges */
+		/* Update the other northbridges */
 		pdev = 0;
 		while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
 			/* Store the GART size but don't enable it */

From peter at stuge.se  Fri Oct  1 01:33:54 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Oct 2010 01:33:54 +0200
Subject: [coreboot] [PATCH] Make hidden configuration flags
	visible	(i945)
In-Reply-To: <4CA50D0C.8050208@georgi-clan.de>
References: <4CA50D0C.8050208@georgi-clan.de>
Message-ID: <20100930233354.16519.qmail@stuge.se>

Patrick Georgi wrote:
> attached patch moves several config flags that, for historical
> reasons, were put in romstage.c into Kconfig.

In principle I think this is a great improvement!

But some comments..


> +++ src/northbridge/intel/i945/Kconfig	(Arbeitskopie)
> @@ -26,3 +26,43 @@
>  	default "8086,27a2"
>  	depends on NORTHBRIDGE_INTEL_I945
>  
> +choice
> +	prompt "Chipset variant"
> +	default I945GM
> +	depends on NORTHBRIDGE_INTEL_I945
> +	help
> +	  Different i945 variants require slightly different setup.
> +
> +config I945GM
> +	bool "i945GM (Mobile) chipset"
> +
> +config I945GC
> +	bool "i945GC chipset"
> +
> +endchoice

I think GC should come first and maybe even be the default, because
it's the base chipset and C < M.

That said, would it work to simply make these options be
NORTHBRIDGE_INTEL_I945GC and _I945GM, and have both of them then
select in the common (current) I945 code? That way there only needs
to be one select for this in mainboards, it's hidden from users, and
it can't really become incorrect.


> +config OVERRIDE_CLOCK_DISABLE
> +	bool
> +	default n
> +	depends on NORTHBRIDGE_INTEL_I945
> +	help
> +	  Usually system firmware turns off system memory clock signals to
> +	  unused SO-DIMM slots to reduce EMI and power consumption.
> +	  However, the Kontron 986LCD-M does not like unused clock signals to
> +	  be disabled. If other similar mainboard occur, it would make sense
> +	  to make this an entry in the sysinfo structure, and pre-initialize that
> +	  structure in the mainboard's romstage.c main() function. For now a
> +	  #define will do.

Well, it is still a #define, but maybe fix up this comment a little
now that it is being touched anyway.. Also, second last line is a bit
long.


> +config MAXIMUM_SUPPORTED_FREQUENCY
> +	int
> +	default 0
> +	depends on NORTHBRIDGE_INTEL_I945
> +	help
> +	  If non-zero, this designates the maximum DDR frequency the board supports,
> +	  despite what the chipset should be capable of.

Maybe shorten this long line a little as well.


If it works to create different NORTHBRIDGE_ configs, this is

Acked-by: Peter Stuge <peter at stuge.se>



From peter at stuge.se  Fri Oct  1 01:35:13 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Oct 2010 01:35:13 +0200
Subject: [coreboot] [patch] spelling fixes for comments
	in	src/northbridge/amd/amdk8/misc_control.c
In-Reply-To: <20100930232629.GA12447@tarantulon.kollasch.net>
References: <20100930232629.GA12447@tarantulon.kollasch.net>
Message-ID: <20100930233513.18155.qmail@stuge.se>

Jonathan A. Kollasch wrote:
> Fix spelling/typos in comments.
> 
> Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>

This is fine to self-ack. Anyway,

Acked-by: Peter Stuge <peter at stuge.se>



From jakllsch at kollasch.net  Fri Oct  1 03:03:27 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Fri, 1 Oct 2010 01:03:27 +0000
Subject: [coreboot] [patch] drop meaningless K8_4RANK_DIMM_SUPPORT define
Message-ID: <20101001010326.GB12447@tarantulon.kollasch.net>

Don't define K8_4RANK_DIMM_SUPPORT, nothing uses it.
All these boards define QRANK_DIMM_SUPPORT anyway,
which is probably what was meant.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>
---
-------------- next part --------------
Index: src/mainboard/msi/ms9282/romstage.c
===================================================================
--- src/mainboard/msi/ms9282/romstage.c	(revision 5888)
+++ src/mainboard/msi/ms9282/romstage.c	(working copy)
@@ -96,8 +96,6 @@
        return smbus_read_byte(device, address);
 }
 
-//#define K8_4RANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/amdk8_f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
Index: src/mainboard/asus/a8v-e_se/romstage.c
===================================================================
--- src/mainboard/asus/a8v-e_se/romstage.c	(revision 5888)
+++ src/mainboard/asus/a8v-e_se/romstage.c	(working copy)
@@ -100,8 +100,6 @@
 // defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"
 
-#define K8_4RANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
Index: src/mainboard/asus/m2v-mx_se/romstage.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/romstage.c	(revision 5888)
+++ src/mainboard/asus/m2v-mx_se/romstage.c	(working copy)
@@ -82,8 +82,6 @@
 // defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"
 
-#define K8_4RANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

From buurin at gmail.com  Fri Oct  1 06:31:47 2010
From: buurin at gmail.com (Keith Hui)
Date: Fri, 1 Oct 2010 00:31:47 -0400
Subject: [coreboot] [PATCH] Drop unneeded header from i82371eb_enable_rom.c
Message-ID: <AANLkTimqGrjawxPNPti9D6ZixzkOrEY_M8HxPqYoP0ZT@mail.gmail.com>

A "I am alive" ping kind of patch while I continue to figure out ACPI
for 440BX boards among other things.

Drops <stdint.h> from the file. My coreboot still compiles fine
without it. abuild tested.

Signed-off-by: Keith Hui <buurin at gmail.com>
-------------- next part --------------
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From svn at coreboot.org  Fri Oct  1 08:27:35 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 08:27:35 +0200
Subject: [coreboot] [commit] r5889 - in trunk/src/northbridge/amd/amdmct:
	mct mct_ddr3
Message-ID: <E1P1Z5j-0006qc-Tv@ra.coresystems.de>

Author: zbao
Date: Fri Oct  1 08:27:35 2010
New Revision: 5889
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5889

Log:
Trivial. Re-indent the code.


Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Zheng Bao <zheng.bao at amd.com>

Modified:
   trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c
   trunk/src/northbridge/amd/amdmct/mct/mctsrc.c
   trunk/src/northbridge/amd/amdmct/mct/mcttmrl.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c

Modified: trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -65,9 +65,9 @@
 				DramBase = pDCTstat->NodeSysBase >> 8;
 				dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8;
 				dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114);
-					if (dct0_size >= 0x10000) {
-						dct0_size -= HoleSize;
-					}
+				if (dct0_size >= 0x10000) {
+					dct0_size -= HoleSize;
+				}
 
 				dct0_size -= DramBase;
 				dct1_size -= dct0_size;

Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mctsrc.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct/mctsrc.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -961,7 +961,7 @@
 				val += val0;
 			}
 
-		pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
+			pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
 		}
 	}
 	SetEccDQSRcvrEn_D(pDCTstat, Channel);
@@ -979,8 +979,8 @@
 		if (!pDCTstat->NodePresent)
 			break;
 		if (pDCTstat->DCTSysLimit) {
-		for(i=0; i<2; i++)
-		CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
+			for(i=0; i<2; i++)
+				CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
 		}
 	}
 }

Modified: trunk/src/northbridge/amd/amdmct/mct/mcttmrl.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mcttmrl.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct/mcttmrl.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -220,8 +220,8 @@
 
 	if (pDCTstat->GangedMode) {
 		Channel = 0; // for safe
-	for (i=0; i<2; i++)
-		pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
+		for (i=0; i<2; i++)
+			pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
 	} else {
 		pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal;
 	}

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -61,9 +61,9 @@
 				DramBase = pDCTstat->NodeSysBase >> 8;
 				dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8;
 				dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114);
-					if (dct0_size >= 0x10000) {
-						dct0_size -= HoleSize;
-					}
+				if (dct0_size >= 0x10000) {
+					dct0_size -= HoleSize;
+				}
 
 				dct0_size -= DramBase;
 				dct1_size -= dct0_size;

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -914,7 +914,7 @@
 				val += val1;
 			}
 
-		pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
+			pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
 		}
 	}
 	SetEccDQSRcvrEn_D(pDCTstat, Channel);
@@ -932,8 +932,8 @@
 		if (!pDCTstat->NodePresent)
 			break;
 		if (pDCTstat->DCTSysLimit) {
-		for(i=0; i<2; i++)
-		CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
+			for(i=0; i<2; i++)
+				CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
 		}
 	}
 }

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -213,8 +213,8 @@
 
 	if (pDCTstat->GangedMode) {
 		Channel = 0; /* for safe */
-	for (i=0; i<2; i++)
-		pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
+		for (i=0; i<2; i++)
+			pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
 	} else {
 		pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal;
 	}



From patrick at georgi-clan.de  Fri Oct  1 09:00:49 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 01 Oct 2010 09:00:49 +0200
Subject: [coreboot] [PATCH] Make hidden configuration
	flags	visible	(i945)
In-Reply-To: <20100930233354.16519.qmail@stuge.se>
References: <4CA50D0C.8050208@georgi-clan.de>
	<20100930233354.16519.qmail@stuge.se>
Message-ID: <4CA58721.8000001@georgi-clan.de>

Am 01.10.2010 01:33, schrieb Peter Stuge:
> That said, would it work to simply make these options be
> NORTHBRIDGE_INTEL_I945GC and _I945GM, and have both of them then
> select in the common (current) I945 code? That way there only needs
> to be one select for this in mainboards, it's hidden from users, and
> it can't really become incorrect.
Thought about it - why I didn't do that: It significantly changes the
design of that part of the code.
The change above simply moves stuff around.


Patrick



From svn at coreboot.org  Fri Oct  1 09:22:36 2010
From: svn at coreboot.org (coreboot)
Date: Fri, 01 Oct 2010 07:22:36 -0000
Subject: [coreboot] #152: v3 Geode cs5536 UART2 wrongly configured
In-Reply-To: <063.cc40a3a37577eb1ad33c3456c205b8d1@coreboot.org>
References: <063.cc40a3a37577eb1ad33c3456c205b8d1@coreboot.org>
Message-ID: <078.e85bd9bcff3932cd51f2b6c66608059a@coreboot.org>

#152: v3 Geode cs5536 UART2 wrongly configured
--------------------------------------------+-------------------------------
    Reporter:  edwin_beasant@?              |          Owner:  hailfinger      
        Type:  defect                       |         Status:  closed          
    Priority:  major                        |      Milestone:  Going mainstream
   Component:  coreboot                     |     Resolution:  fixed           
    Keywords:  serial com2 geode cs5536     |   Dependencies:                  
Patch Status:  patch has been committed     |  
--------------------------------------------+-------------------------------
Changes (by uwe):

  * status:  new => closed
  * patchstatus:  patch is ready to be committed => patch has been
                  committed
  * resolution:  => fixed


Comment:

 Patch was comitted for v2, and v3 is obsolete now, so closing the issue.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/152#comment:4>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Oct  1 09:23:34 2010
From: svn at coreboot.org (coreboot)
Date: Fri, 01 Oct 2010 07:23:34 -0000
Subject: [coreboot] #82: Fix the memory map in coreboot v3
In-Reply-To: <043.620d0bf677396cfb59c722124e8f9213@coreboot.org>
References: <043.620d0bf677396cfb59c722124e8f9213@coreboot.org>
Message-ID: <058.f38580c86a12d0f6fadae09e69e58fc9@coreboot.org>

#82: Fix the memory map in coreboot v3
----------------------------------+-----------------------------------------
    Reporter:  oxygene            |          Owner:  hailfinger            
        Type:  defect             |         Status:  closed                
    Priority:  major              |      Milestone:  Setting up coreboot v3
   Component:  coreboot           |     Resolution:  abandoned             
    Keywords:                     |   Dependencies:                        
Patch Status:  there is no patch  |  
----------------------------------+-----------------------------------------
Changes (by uwe):

  * status:  new => closed
  * resolution:  => abandoned


Comment:

 v3 is obsolete, closing issue.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/82#comment:3>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Oct  1 09:26:19 2010
From: svn at coreboot.org (coreboot)
Date: Fri, 01 Oct 2010 07:26:19 -0000
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
Message-ID: <058.98d1662a179cf0d1d8d773df96a2ada8@coreboot.org>

#163: Board still requires RAMBASE <1MB
-----------------------------------------+----------------------------------
    Reporter:  oxygene                   |          Owner:  stepan@?             
        Type:  defect                    |         Status:  closed               
    Priority:  minor                     |      Milestone:                       
   Component:  coreboot                  |     Resolution:  fixed                
    Keywords:                            |   Dependencies:                       
Patch Status:  patch has been committed  |  
-----------------------------------------+----------------------------------
Changes (by uwe):

  * status:  new => closed
  * patchstatus:  there is no patch => patch has been committed
  * resolution:  => fixed


Comment:

 Last occurences of this were obviously fixed in r5779, closing issue.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/163#comment:1>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Oct  1 09:27:51 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 09:27:51 +0200
Subject: [coreboot] [commit] r5890 - in trunk/src: cpu/amd/car cpu/intel/car
	cpu/via/car include/cpu/x86
Message-ID: <E1P1a23-00084D-VC@ra.coresystems.de>

Author: uwe
Date: Fri Oct  1 09:27:51 2010
New Revision: 5890
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5890

Log:
CAR simplifications, typos, readability improvements (trivial).

 - Use some more #defines instead of hard-coding values.

 - Merge multiple movl/orl or movl/andl lines into one where possible.

 - Add some TODOs in places which seem to have either an incorrect
   code or incorrect comment.

 - Fix typos: s/for/from/, s/BSC/BSP/, s/size/carsize/.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/cpu/amd/car/cache_as_ram.inc
   trunk/src/cpu/intel/car/cache_as_ram.inc
   trunk/src/cpu/via/car/cache_as_ram.inc
   trunk/src/include/cpu/x86/mtrr.h

Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc	Fri Oct  1 08:27:35 2010	(r5889)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc	Fri Oct  1 09:27:51 2010	(r5890)
@@ -90,7 +90,7 @@
 	 */
 	movl	$0x1b, %ecx
 	rdmsr
-	bt	$8, %eax /* BSC */
+	bt	$8, %eax	/* BSP */
 	jnc	CAR_FAM10_out
 
 	/* Enable RT tables on BSP. */
@@ -135,15 +135,14 @@
 	wrmsr
 
 #if CONFIG_MMCONF_SUPPORT
-	/* Set MMIO Config space BAR. */
+	/* Set MMIO config space BAR. */
 	movl	$MSR_MCFG_BASE, %ecx
 	rdmsr
-
 	andl	$(~(0xfff00000 | (0xf << 2))), %eax
-	orl	$((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000) | (8 << 2) | (1 << 0)), %eax
+	orl	$((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000), %eax
+	orl	$((8 << 2) | (1 << 0)), %eax
 	andl	$(~(0x0000ffff)), %edx
 	orl	$(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx
-
 	wrmsr
 #endif
 
@@ -216,7 +215,7 @@
 .endm
 
 /*
- * size is the cache size in bytes we want to use for CAR.
+ * carsize is the cache size in bytes we want to use for CAR.
  * windowoffset is the 32k-aligned window into CAR size.
  */
 .macro simplemask carsize, windowoffset
@@ -289,7 +288,7 @@
 	/* Set the default memory type and enable fixed and variable MTRRs. */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
-	movl	$0x00000c00, %eax	/* Enable variable and fixed MTRRs. */
+	movl	$(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
 	wrmsr
 
 	/* Enable the MTRRs and IORRs in SYSCFG. */
@@ -302,7 +301,7 @@
 
 	/* Enable cache. */
 	movl	%cr0, %eax
-	andl	$0x9fffffff, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	movl	%eax, %cr0
 
 	jmp_if_k8(fam10_end_part1)
@@ -310,7 +309,7 @@
 	/* So we need to check if it is BSP. */
 	movl	$0x1b, %ecx
 	rdmsr
-	bt	$8, %eax /* BSC */
+	bt	$8, %eax	/* BSP */
 	jnc	CAR_FAM10_ap
 fam10_end_part1:
 
@@ -365,7 +364,7 @@
 	movl	$0xc001001f, %ecx	/* NB_CFG_MSR */
 	rdmsr
 	movl	%edi, %ecx		/* CoreID bits */
-	bt	$(54-32), %edx
+	bt	$(54 - 32), %edx
 	jc	roll_cfg
 	rolb	%cl, %bl
 roll_cfg:

Modified: trunk/src/cpu/intel/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/car/cache_as_ram.inc	Fri Oct  1 08:27:35 2010	(r5889)
+++ trunk/src/cpu/intel/car/cache_as_ram.inc	Fri Oct  1 09:27:51 2010	(r5890)
@@ -110,7 +110,7 @@
 	/* Set the default memory type and enable fixed and variable MTRRs. */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
-	movl	$0x00000c00, %eax	/* Enable variable and fixed MTRRs. */
+	movl	$(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
 	wrmsr
 
 	/* Clear all MTRRs. */
@@ -169,7 +169,7 @@
 .endm
 
 /*
- * size is the cache size in bytes we want to use for CAR.
+ * carsize is the cache size in bytes we want to use for CAR.
  * windowoffset is the 32k-aligned window into CAR size.
  */
 .macro simplemask carsize, windowoffset
@@ -221,8 +221,7 @@
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
-	movl	$REAL_XIP_ROM_BASE, %eax
-	orl	$MTRR_TYPE_WRBACK, %eax
+	movl	$(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
@@ -233,7 +232,7 @@
 
 	/* Enable cache. */
 	movl	%cr0, %eax
-	andl	$0x9fffffff, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	movl	%eax, %cr0
 
 	/* Read the range with lodsl. */
@@ -303,7 +302,7 @@
 	pushl	%eax  /* BIST */
 	call	main
 
-	/* We don't need CAR for now on. */
+	/* We don't need CAR from now on. */
 
 	/* Disable cache. */
 	movl	%cr0, %eax
@@ -332,7 +331,7 @@
 
 	/* Enable cache. */
 	movl	%cr0, %eax
-	andl	$0x9fffffff, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	movl	%eax, %cr0
 
 	/* Clear boot_complete flag. */

Modified: trunk/src/cpu/via/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/via/car/cache_as_ram.inc	Fri Oct  1 08:27:35 2010	(r5889)
+++ trunk/src/cpu/via/car/cache_as_ram.inc	Fri Oct  1 09:27:51 2010	(r5890)
@@ -45,7 +45,7 @@
 	/* Set the default memory type and enable fixed and variable MTRRs. */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
-	movl	$0x00000c00, %eax	/* Enable variable and fixed MTRRs. */
+	movl	$(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
 	wrmsr
 
 	/* Clear all MTRRs. */
@@ -100,8 +100,7 @@
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
-	movl	$REAL_XIP_ROM_BASE, %eax
-	orl	$MTRR_TYPE_WRBACK, %eax
+	movl	$(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
@@ -109,13 +108,16 @@
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
 
+	/* Set the default memory type and enable fixed and variable MTRRs. */
+	/* TODO: Or also enable fixed MTRRs? Bug in the code? */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
-	movl	$0x00000800, %eax	/* Enable variable and fixed MTRRs. */
+	movl	$(MTRRdefTypeEn), %eax
 	wrmsr
 
+	/* Enable cache. */
 	movl	%cr0, %eax
-	andl	$0x9fffffff, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	movl	%eax, %cr0
 
 	/* Read the range with lodsl. */
@@ -186,27 +188,24 @@
 	 *       want to go back.
 	 */
 
-	/* We don't need CAR for now on. */
+	/* We don't need CAR from now on. */
 
 	/* Disable cache. */
 	movl	%cr0, %eax
 	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
-	/*
-	 * Set the default memory type and disable fixed and enable
-	 * variable MTRRs.
-	 */
+	/* Set the default memory type and enable variable MTRRs. */
+	/* TODO: Or also enable fixed MTRRs? Bug in the code? */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
-	movl	$0x00000800, %eax /* Enable variable & disable fixed MTRRs. */
+	movl	$(MTRRdefTypeEn), %eax
 	wrmsr
 
 	/* Enable caching for first 1M using variable MTRR. */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	xorl	%edx, %edx
-	movl	$(0 | 6), %eax
-	// movl	$(0 | MTRR_TYPE_WRBACK), %eax
+	movl	$(0 | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	/*
@@ -223,8 +222,7 @@
 
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
-	movl	$(0x80000 | 6), %eax
-	orl	$(0 | 6), %eax
+	movl	$(0x80000 | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
@@ -234,8 +232,7 @@
 
 	movl	$MTRRphysBase_MSR(2), %ecx
 	xorl	%edx, %edx
-	movl	$(0xc0000 | 6), %eax
-	orl	$(0 | 6), %eax
+	movl	$(0xc0000 | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(2), %ecx
@@ -246,21 +243,17 @@
 	/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
 	movl	$MTRRphysBase_MSR(3), %ecx
 	xorl	%edx, %edx
-	movl	$REAL_XIP_ROM_BASE,%eax
-	orl	$(0 | 6), %eax
+	movl	$(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(3), %ecx
 	xorl	%edx, %edx
-	movl	$CONFIG_XIP_ROM_SIZE, %eax
-	decl	%eax
-	notl	%eax
-	orl	$(0 | 0x800), %eax
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
 
 	/* Enable cache. */
 	movl	%cr0, %eax
-	andl	$0x9fffffff, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	movl	%eax, %cr0
 	invd
 

Modified: trunk/src/include/cpu/x86/mtrr.h
==============================================================================
--- trunk/src/include/cpu/x86/mtrr.h	Fri Oct  1 08:27:35 2010	(r5889)
+++ trunk/src/include/cpu/x86/mtrr.h	Fri Oct  1 09:27:51 2010	(r5890)
@@ -15,6 +15,9 @@
 #define MTRRcap_MSR     0x0fe
 #define MTRRdefType_MSR 0x2ff
 
+#define MTRRdefTypeEn		(1 << 11)
+#define MTRRdefTypeFixEn	(1 << 10)
+
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 



From svn at coreboot.org  Fri Oct  1 09:31:33 2010
From: svn at coreboot.org (coreboot)
Date: Fri, 01 Oct 2010 07:31:33 -0000
Subject: [coreboot] #76: coreboot messages should be accessible in dmesg
In-Reply-To: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
References: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
Message-ID: <057.6178a789d5bf2ea69b534f895f572d2a@coreboot.org>

#76: coreboot messages should be accessible in dmesg
----------------------------------+-----------------------------------------
    Reporter:  stepan             |          Owner:  rminnich
        Type:  enhancement        |         Status:  new     
    Priority:  major              |      Milestone:          
   Component:  coreboot           |     Resolution:          
    Keywords:                     |   Dependencies:          
Patch Status:  there is no patch  |  
----------------------------------+-----------------------------------------
Changes (by uwe):

  * milestone:  Setting up coreboot v3 =>


Comment:

 v3 is obsolete, but having the feature in v4 would be great.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/76#comment:6>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Oct  1 09:32:49 2010
From: svn at coreboot.org (coreboot)
Date: Fri, 01 Oct 2010 07:32:49 -0000
Subject: [coreboot] #110: Allow for per-device subsystem IDs
In-Reply-To: <039.46c40d60a2fcef7a54c110b21fe0291b@coreboot.org>
References: <039.46c40d60a2fcef7a54c110b21fe0291b@coreboot.org>
Message-ID: <054.69b4f9434909258b6611a93c943c6d05@coreboot.org>

#110: Allow for per-device subsystem IDs
----------------------------------+-----------------------------------------
    Reporter:  uwe                |          Owner:  somebody
        Type:  enhancement        |         Status:  new     
    Priority:  minor              |      Milestone:          
   Component:  coreboot           |     Resolution:          
    Keywords:                     |   Dependencies:          
Patch Status:  there is no patch  |  
----------------------------------+-----------------------------------------

Comment (by uwe):

 Yep, this should be fixed somehow in v4, too.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/110#comment:2>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Oct  1 09:48:34 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 09:48:34 +0200
Subject: [coreboot] build service results for r5890
Message-ID: <E1P1aM6-0005FE-2a@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "uwe" checked in revision 5890 to
the coreboot repository. This caused the following 
changes:

Change Log:
CAR simplifications, typos, readability improvements (trivial).

 - Use some more #defines instead of hard-coding values.

 - Merge multiple movl/orl or movl/andl lines into one where possible.

 - Add some TODOs in places which seem to have either an incorrect
   code or incorrect comment.

 - Fix typos: s/for/from/, s/BSC/BSP/, s/size/carsize/.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of amd:mahogany_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=mahogany_fam10&vendor=amd&num=2
Compilation of amd:serengeti_cheetah_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=serengeti_cheetah_fam10&vendor=amd&num=2
Compilation of amd:tilapia_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=tilapia_fam10&vendor=amd&num=2
Compilation of asus:m4a785-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=m4a785-m&vendor=asus&num=2
Compilation of digitallogic:adl855pc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=adl855pc&vendor=digitallogic&num=2
Compilation of gigabyte:ma785gmt has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=ma785gmt&vendor=gigabyte&num=2
Compilation of gigabyte:ma78gm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=ma78gm&vendor=gigabyte&num=2
Compilation of hp:dl165_g6_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=dl165_g6_fam10&vendor=hp&num=2
Compilation of iei:kino-780am2-fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=kino-780am2-fam10&vendor=iei&num=2
Compilation of intel:d810e2cb has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=d810e2cb&vendor=intel&num=2
Compilation of jetway:pa78vm5 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=pa78vm5&vendor=jetway&num=2
Compilation of lanner:em8510 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=em8510&vendor=lanner&num=2
Compilation of msi:ms9652_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=ms9652_fam10&vendor=msi&num=2
Compilation of rca:rm4100 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=rm4100&vendor=rca&num=2
Compilation of supermicro:h8dmr_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=h8dmr_fam10&vendor=supermicro&num=2
Compilation of supermicro:h8qme_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=h8qme_fam10&vendor=supermicro&num=2
Compilation of thomson:ip1000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=ip1000&vendor=thomson&num=2
Compilation of tyan:s2912_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=s2912_fam10&vendor=tyan&num=2
Compilation of via:vt8454c has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5890&device=vt8454c&vendor=via&num=2


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Fri Oct  1 10:02:45 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 10:02:45 +0200
Subject: [coreboot] [commit] r5891 - in trunk/src: mainboard/getac/p470
	mainboard/ibase/mb899 mainboard/intel/d945gclf
	mainboard/kontron/986lcd-m mainboard/roda/rk886ex
	northbridge/intel/i945
Message-ID: <E1P1aZp-0007gO-W9@ra.coresystems.de>

Author: oxygene
Date: Fri Oct  1 10:02:45 2010
New Revision: 5891
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5891

Log:
Move several i945 config #defines from romstage.c to Kconfig.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/getac/p470/Kconfig
   trunk/src/mainboard/getac/p470/romstage.c
   trunk/src/mainboard/ibase/mb899/Kconfig
   trunk/src/mainboard/ibase/mb899/romstage.c
   trunk/src/mainboard/intel/d945gclf/Kconfig
   trunk/src/mainboard/intel/d945gclf/romstage.c
   trunk/src/mainboard/kontron/986lcd-m/Kconfig
   trunk/src/mainboard/kontron/986lcd-m/romstage.c
   trunk/src/mainboard/roda/rk886ex/Kconfig
   trunk/src/mainboard/roda/rk886ex/romstage.c
   trunk/src/northbridge/intel/i945/Kconfig
   trunk/src/northbridge/intel/i945/raminit.c

Modified: trunk/src/mainboard/getac/p470/Kconfig
==============================================================================
--- trunk/src/mainboard/getac/p470/Kconfig	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/mainboard/getac/p470/Kconfig	Fri Oct  1 10:02:45 2010	(r5891)
@@ -43,6 +43,8 @@
 	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
+	select I945GM
+	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/getac/p470/romstage.c
==============================================================================
--- trunk/src/mainboard/getac/p470/romstage.c	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/mainboard/getac/p470/romstage.c	Fri Oct  1 10:02:45 2010	(r5891)
@@ -19,10 +19,6 @@
  * MA 02110-1301 USA
  */
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>

Modified: trunk/src/mainboard/ibase/mb899/Kconfig
==============================================================================
--- trunk/src/mainboard/ibase/mb899/Kconfig	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/mainboard/ibase/mb899/Kconfig	Fri Oct  1 10:02:45 2010	(r5891)
@@ -20,6 +20,8 @@
 	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
+	select I945GM
+	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/ibase/mb899/romstage.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/romstage.c	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/mainboard/ibase/mb899/romstage.c	Fri Oct  1 10:02:45 2010	(r5891)
@@ -19,11 +19,6 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-//#define OVERRIDE_CLOCK_DISABLE 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>

Modified: trunk/src/mainboard/intel/d945gclf/Kconfig
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/Kconfig	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/mainboard/intel/d945gclf/Kconfig	Fri Oct  1 10:02:45 2010	(r5891)
@@ -40,6 +40,8 @@
 	select BOARD_ROMSIZE_KB_512
 	select GFXUMA
 	select TINY_BOOTBLOCK
+	select I945GC
+	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/intel/d945gclf/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/romstage.c	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/mainboard/intel/d945gclf/romstage.c	Fri Oct  1 10:02:45 2010	(r5891)
@@ -19,10 +19,6 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GC 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>

Modified: trunk/src/mainboard/kontron/986lcd-m/Kconfig
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/Kconfig	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/mainboard/kontron/986lcd-m/Kconfig	Fri Oct  1 10:02:45 2010	(r5891)
@@ -20,6 +20,9 @@
 	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
+	select CHANNEL_XOR_RANDOMIZATION
+	select I945GM
+	select OVERRIDE_CLOCK_DISABLE
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/romstage.c	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/mainboard/kontron/986lcd-m/romstage.c	Fri Oct  1 10:02:45 2010	(r5891)
@@ -19,19 +19,6 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-/* Usually system firmware turns off system memory clock signals to
- * unused SO-DIMM slots to reduce EMI and power consumption.
- * However, the Kontron 986LCD-M does not like unused clock signals to
- * be disabled. If other similar mainboard occur, it would make sense
- * to make this an entry in the sysinfo structure, and pre-initialize that
- * structure in the mainboard's romstage.c main() function. For now a
- * #define will do.
- */
-#define OVERRIDE_CLOCK_DISABLE 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>

Modified: trunk/src/mainboard/roda/rk886ex/Kconfig
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/Kconfig	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/mainboard/roda/rk886ex/Kconfig	Fri Oct  1 10:02:45 2010	(r5891)
@@ -19,6 +19,8 @@
 	select HAVE_ACPI_TABLES
 	select HAVE_ACPI_RESUME
 	select BOARD_ROMSIZE_KB_1024
+	select I945GM
+	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
 	string
@@ -56,4 +58,8 @@
 	hex
 	default 0x6886
 
+config MAXIMUM_SUPPORTED_FREQUENCY
+	int
+	default 400
+
 endif # BOARD_RODA_RK886EX

Modified: trunk/src/mainboard/roda/rk886ex/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/mainboard/roda/rk886ex/romstage.c	Fri Oct  1 10:02:45 2010	(r5891)
@@ -21,12 +21,6 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-// Rocky freezing temperature settings:
-#define MAXIMUM_SUPPORTED_FREQUENCY 400
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>

Modified: trunk/src/northbridge/intel/i945/Kconfig
==============================================================================
--- trunk/src/northbridge/intel/i945/Kconfig	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/northbridge/intel/i945/Kconfig	Fri Oct  1 10:02:45 2010	(r5891)
@@ -26,3 +26,41 @@
 	default "8086,27a2"
 	depends on NORTHBRIDGE_INTEL_I945
 
+choice
+	default I945GM
+	depends on NORTHBRIDGE_INTEL_I945
+	help
+	  Different i945 variants require slightly different setup.
+
+config I945GM
+	bool "i945GM (Mobile) chipset"
+
+config I945GC
+	bool "i945GC chipset"
+
+endchoice
+
+config CHANNEL_XOR_RANDOMIZATION
+	bool
+	default n
+	depends on NORTHBRIDGE_INTEL_I945
+
+config OVERRIDE_CLOCK_DISABLE
+	bool
+	default n
+	depends on NORTHBRIDGE_INTEL_I945
+	help
+	  Usually system firmware turns off system memory clock
+	  signals to unused SO-DIMM slots to reduce EMI and power
+	  consumption.
+	  However, some boards do not like unused clock signals to
+	  be disabled.
+
+config MAXIMUM_SUPPORTED_FREQUENCY
+	int
+	default 0
+	depends on NORTHBRIDGE_INTEL_I945
+	help
+	  If non-zero, this designates the maximum DDR frequency
+	  the board supports, despite what the chipset should be
+	  capable of.

Modified: trunk/src/northbridge/intel/i945/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/i945/raminit.c	Fri Oct  1 09:27:51 2010	(r5890)
+++ trunk/src/northbridge/intel/i945/raminit.c	Fri Oct  1 10:02:45 2010	(r5891)
@@ -90,7 +90,7 @@
 static int memclk(void)
 {
 	int offset = 0;
-#ifdef CHIPSET_I945GM
+#if CONFIG_I945GM
 	offset++;
 #endif
 	switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
@@ -102,7 +102,7 @@
 	return -1;
 }
 
-#ifdef CHIPSET_I945GM
+#if CONFIG_I945GM
 static int fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
@@ -114,7 +114,7 @@
 	return -1;
 }
 #endif
-#ifdef CHIPSET_I945GC
+#if CONFIG_I945GC
 static int fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
@@ -131,8 +131,8 @@
 {
 	u32 reg32;
 
-#ifdef MAXIMUM_SUPPORTED_FREQUENCY
-	return MAXIMUM_SUPPORTED_FREQUENCY;
+#if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
+	return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
 #endif
 
 	reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
@@ -1045,7 +1045,7 @@
 	return nc;
 }
 
-#ifdef CHIPSET_I945GM
+#if CONFIG_I945GM
 /* Strength multiplier tables */
 static const u8 dual_channel_strength_multiplier[] = {
 	0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@@ -1101,7 +1101,7 @@
 	0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
 };
 #endif
-#ifdef CHIPSET_I945GC
+#if CONFIG_I945GC
 static const u8 dual_channel_strength_multiplier[] = {
 	0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
 	0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@@ -2155,7 +2155,7 @@
 	/**
 	 * We add the indices according to our clocks from CLKCFG.
 	 */
-#ifdef CHIPSET_I945GM
+#if CONFIG_I945GM
 	static const u32 data_clock_crossing[] = {
 		0x00100401, 0x00000000, /* DDR400 FSB400 */
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2201,7 +2201,7 @@
 	};
 
 #endif
-#ifdef CHIPSET_I945GC
+#if CONFIG_I945GC
 	/* i945 G/P */
 	static const u32 data_clock_crossing[] = {
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2420,7 +2420,7 @@
 	if (sysinfo->interleaved) {
 
 		reg32 = MCHBAR32(DCC);
-#if CHANNEL_XOR_RANDOMIZATION
+#if CONFIG_CHANNEL_XOR_RANDOMIZATION
 		reg32 &= ~(1 << 10);
 		reg32 |= (1 << 9);
 #else
@@ -2792,10 +2792,10 @@
 {
 	u8 clocks[2] = { 0, 0 };
 
-#ifdef CHIPSET_I945GM
+#if CONFIG_I945GM
 #define CLOCKS_WIDTH 2
 #endif
-#ifdef CHIPSET_I945GC
+#if CONFIG_I945GC
 #define CLOCKS_WIDTH 3
 #endif
 	if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
@@ -2810,15 +2810,11 @@
 	if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
 		clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
 
-#ifdef OVERRIDE_CLOCK_DISABLE
+#if CONFIG_OVERRIDE_CLOCK_DISABLE
 	/* Usually system firmware turns off system memory clock signals
 	 * to unused SO-DIMM slots to reduce EMI and power consumption.
 	 * However, the Kontron 986LCD-M does not like unused clock
 	 * signals to be disabled.
-	 * If other similar mainboard occur, it would make sense to make
-	 * this an entry in the sysinfo structure, and pre-initialize that
-	 * structure in the mainboard's romstage.c main() function.
-	 * For now an #ifdef will do.
 	 */
 
 	clocks[0] = 0xf; /* force all clock gate pairs to enable */



From patrick at georgi-clan.de  Fri Oct  1 10:04:22 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 01 Oct 2010 10:04:22 +0200
Subject: [coreboot] [PATCH] Make hidden configuration
	flags	visible	(i945)
In-Reply-To: <20100930233354.16519.qmail@stuge.se>
References: <4CA50D0C.8050208@georgi-clan.de>
	<20100930233354.16519.qmail@stuge.se>
Message-ID: <4CA59606.1080909@georgi-clan.de>

Am 01.10.2010 01:33, schrieb Peter Stuge:
> Acked-by: Peter Stuge <peter at stuge.se>
Thanks, r5891

The help texts are cleaned up, and the chipset variant setting isn't
user visible anymore (I think - tested in "make config" only)


Patrick



From wt at penguintechs.org  Fri Oct  1 10:15:53 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Fri, 1 Oct 2010 01:15:53 -0700
Subject: [coreboot] [PATCH] Unify the Socket 940 CAR configuration.
In-Reply-To: <5E26AFBED2304C099094A9F406B0D0B5@chimp>
References: <1285879009-14153-1-git-send-email-wt@penguintechs.org>
	<5E26AFBED2304C099094A9F406B0D0B5@chimp>
Message-ID: <AANLkTinmJqc9B2i0giidOsM8HpiApNDSrv1tu5eUMEwp@mail.gmail.com>

Notice that it is also changing the base of the CAR area and, in some
cases, the size of the global variable region. Should I be worried
about those?

Thanks,
wt

On Thu, Sep 30, 2010 at 2:58 PM, Myles Watson <mylesgw at gmail.com> wrote:
>> I am looking for some comments on the following patch. It unifies the
>> socket 940 cache-as-ram implementation. Previously, the affected boards
>> had their own CAR options in their Kconfig files. There is a default set
>> of CAR configs in the socket.
>>
>> Does anyone have comments on why this patch should or should not be
>> committed?
>
> Pro:
> It's simpler.
>
> Con:
> It probably slows booting a little, since there's more stack to copy. ?I
> have no idea how much.
>
> The code handles either CAR size already, so it shouldn't break anything.
>
> Thanks,
> Myles
>
>
>



From svn at coreboot.org  Fri Oct  1 10:51:30 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 10:51:30 +0200
Subject: [coreboot] build service results for r5891
Message-ID: <E1P1bL0-00017u-Rb@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5891 to
the coreboot repository. This caused the following 
changes:

Change Log:
Move several i945 config #defines from romstage.c to Kconfig.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Compilation of amd:mahogany_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=mahogany_fam10&vendor=amd&num=2
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=serengeti_cheetah_fam10&vendor=amd&num=2
Compilation of amd:tilapia_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=tilapia_fam10&vendor=amd&num=2
Compilation of asus:m4a785-m is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=m4a785-m&vendor=asus&num=2
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=adl855pc&vendor=digitallogic&num=2
Compilation of getac:p470 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=p470&vendor=getac&num=2
Compilation of gigabyte:ma785gmt is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=ma785gmt&vendor=gigabyte&num=2
Compilation of gigabyte:ma78gm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=ma78gm&vendor=gigabyte&num=2
Compilation of hp:dl165_g6_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=dl165_g6_fam10&vendor=hp&num=2
Compilation of ibase:mb899 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=mb899&vendor=ibase&num=2
Compilation of iei:kino-780am2-fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=kino-780am2-fam10&vendor=iei&num=2
Compilation of intel:d810e2cb is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=d810e2cb&vendor=intel&num=2
Compilation of intel:d945gclf has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=d945gclf&vendor=intel&num=2
Compilation of jetway:pa78vm5 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=pa78vm5&vendor=jetway&num=2
Compilation of kontron:986lcd-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=986lcd-m&vendor=kontron&num=2
Compilation of lanner:em8510 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=em8510&vendor=lanner&num=2
Compilation of msi:ms9652_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=ms9652_fam10&vendor=msi&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=rm4100&vendor=rca&num=2
Compilation of roda:rk886ex has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=rk886ex&vendor=roda&num=2
Compilation of supermicro:h8dmr_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=h8dmr_fam10&vendor=supermicro&num=2
Compilation of supermicro:h8qme_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=h8qme_fam10&vendor=supermicro&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=ip1000&vendor=thomson&num=2
Compilation of tyan:s2912_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=s2912_fam10&vendor=tyan&num=2
Compilation of via:vt8454c is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5891&device=vt8454c&vendor=via&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Fri Oct  1 11:02:07 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Oct 2010 11:02:07 +0200
Subject: [coreboot] [PATCH] Split NORTHBRIDGE_INTEL_I945 into more
	precise	_I945GC and _I945GM
Message-ID: <20101001090207.16378.qmail@stuge.se>

Patrick Georgi wrote:
> Am 01.10.2010 01:33, schrieb Peter Stuge:
> > would it work to simply make these options be
> > NORTHBRIDGE_INTEL_I945GC and _I945GM
..
> Thought about it - why I didn't do that: It significantly changes
> the design of that part of the code.
> The change above simply moves stuff around.

Patrick Georgi wrote:
> > Acked-by: Peter Stuge <peter at stuge.se>
> Thanks, r5891
> 
> The help texts are cleaned up, and the chipset variant setting isn't
> user visible anymore (I think - tested in "make config" only)

Attached is the patch to remove the separate variant setting and put
the info in the NORTHBRIDGE_ option.

Build tested on Getac (GM) and d945gclf (GC).


//Peter
-------------- next part --------------
Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GM

Both chipsets use the src/northbridge/intel/i945 code but that code
needs to know which chipset is actually used. Having separate
NORTHBRIDGE_ options allows the I945GC/I945GM choice to be removed
since code can test the NORTHBRIDGE_ option directly.

Signed-off-by: Peter Stuge <peter at stuge.se>

Index: src/mainboard/getac/p470/Kconfig
===================================================================
--- src/mainboard/getac/p470/Kconfig	(revision 5891)
+++ src/mainboard/getac/p470/Kconfig	(working copy)
@@ -23,7 +23,7 @@
 	select ARCH_X86
 	select CPU_INTEL_CORE
 	select CPU_INTEL_SOCKET_MFCPGA478
-	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SOUTHBRIDGE_TI_PCIXX12
 	select SUPERIO_SMSC_FDC37N972
@@ -43,7 +43,6 @@
 	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
-	select I945GM
 	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
Index: src/mainboard/kontron/986lcd-m/Kconfig
===================================================================
--- src/mainboard/kontron/986lcd-m/Kconfig	(revision 5891)
+++ src/mainboard/kontron/986lcd-m/Kconfig	(working copy)
@@ -5,7 +5,7 @@
 	select ARCH_X86
 	select CPU_INTEL_CORE
 	select CPU_INTEL_SOCKET_MFCPGA478
-	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_WINBOND_W83627THG
 	select BOARD_HAS_FADT
@@ -21,7 +21,6 @@
 	select GFXUMA
 	select TINY_BOOTBLOCK
 	select CHANNEL_XOR_RANDOMIZATION
-	select I945GM
 	select OVERRIDE_CLOCK_DISABLE
 
 config MAINBOARD_DIR
Index: src/mainboard/ibase/mb899/Kconfig
===================================================================
--- src/mainboard/ibase/mb899/Kconfig	(revision 5891)
+++ src/mainboard/ibase/mb899/Kconfig	(working copy)
@@ -5,7 +5,7 @@
 	select ARCH_X86
 	select CPU_INTEL_CORE
 	select CPU_INTEL_SOCKET_MFCPGA478
-	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_WINBOND_W83627EHG
 	select BOARD_HAS_FADT
@@ -20,7 +20,6 @@
 	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
-	select I945GM
 	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
Index: src/mainboard/roda/rk886ex/Kconfig
===================================================================
--- src/mainboard/roda/rk886ex/Kconfig	(revision 5891)
+++ src/mainboard/roda/rk886ex/Kconfig	(working copy)
@@ -5,7 +5,7 @@
 	select ARCH_X86
 	select CPU_INTEL_CORE
 	select CPU_INTEL_SOCKET_MFCPGA478
-	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SOUTHBRIDGE_TI_PCI7420
 	select SUPERIO_SMSC_LPC47N227
@@ -19,7 +19,6 @@
 	select HAVE_ACPI_TABLES
 	select HAVE_ACPI_RESUME
 	select BOARD_ROMSIZE_KB_1024
-	select I945GM
 	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
Index: src/mainboard/intel/d945gclf/Kconfig
===================================================================
--- src/mainboard/intel/d945gclf/Kconfig	(revision 5891)
+++ src/mainboard/intel/d945gclf/Kconfig	(working copy)
@@ -22,7 +22,7 @@
 	def_bool y
 	select ARCH_X86
 	select CPU_INTEL_SOCKET_441
-	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_I945GC
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_SMSC_LPC47M15X
 	select BOARD_HAS_FADT
@@ -40,7 +40,6 @@
 	select BOARD_ROMSIZE_KB_512
 	select GFXUMA
 	select TINY_BOOTBLOCK
-	select I945GC
 	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
Index: src/northbridge/intel/Makefile.inc
===================================================================
--- src/northbridge/intel/Makefile.inc	(revision 5891)
+++ src/northbridge/intel/Makefile.inc	(working copy)
@@ -7,4 +7,5 @@
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945
Index: src/northbridge/intel/i945/Kconfig
===================================================================
--- src/northbridge/intel/i945/Kconfig	(revision 5891)
+++ src/northbridge/intel/i945/Kconfig	(working copy)
@@ -17,38 +17,27 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-config NORTHBRIDGE_INTEL_I945
+config NORTHBRIDGE_INTEL_I945GC
 	bool
 	select HAVE_DEBUG_RAM_SETUP
 
+config NORTHBRIDGE_INTEL_I945GM
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+
+if NORTHBRIDGE_INTEL_I945GC || NORTHBRIDGE_INTEL_I945GM
+
 config FALLBACK_VGA_BIOS_ID
 	string
 	default "8086,27a2"
-	depends on NORTHBRIDGE_INTEL_I945
 
-choice
-	default I945GM
-	depends on NORTHBRIDGE_INTEL_I945
-	help
-	  Different i945 variants require slightly different setup.
-
-config I945GM
-	bool "i945GM (Mobile) chipset"
-
-config I945GC
-	bool "i945GC chipset"
-
-endchoice
-
 config CHANNEL_XOR_RANDOMIZATION
 	bool
 	default n
-	depends on NORTHBRIDGE_INTEL_I945
 
 config OVERRIDE_CLOCK_DISABLE
 	bool
 	default n
-	depends on NORTHBRIDGE_INTEL_I945
 	help
 	  Usually system firmware turns off system memory clock
 	  signals to unused SO-DIMM slots to reduce EMI and power
@@ -59,8 +48,9 @@
 config MAXIMUM_SUPPORTED_FREQUENCY
 	int
 	default 0
-	depends on NORTHBRIDGE_INTEL_I945
 	help
 	  If non-zero, this designates the maximum DDR frequency
 	  the board supports, despite what the chipset should be
 	  capable of.
+
+endif
Index: src/northbridge/intel/i945/raminit.c
===================================================================
--- src/northbridge/intel/i945/raminit.c	(revision 5891)
+++ src/northbridge/intel/i945/raminit.c	(working copy)
@@ -90,7 +90,7 @@
 static int memclk(void)
 {
 	int offset = 0;
-#if CONFIG_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 	offset++;
 #endif
 	switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
@@ -102,7 +102,7 @@
 	return -1;
 }
 
-#if CONFIG_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 static int fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
@@ -113,8 +113,7 @@
 	}
 	return -1;
 }
-#endif
-#if CONFIG_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 static int fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
@@ -1045,7 +1044,7 @@
 	return nc;
 }
 
-#if CONFIG_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 /* Strength multiplier tables */
 static const u8 dual_channel_strength_multiplier[] = {
 	0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@@ -1100,8 +1099,7 @@
 	0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 	0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
 };
-#endif
-#if CONFIG_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 static const u8 dual_channel_strength_multiplier[] = {
 	0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
 	0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@@ -2155,7 +2153,7 @@
 	/**
 	 * We add the indices according to our clocks from CLKCFG.
 	 */
-#if CONFIG_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 	static const u32 data_clock_crossing[] = {
 		0x00100401, 0x00000000, /* DDR400 FSB400 */
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2200,8 +2198,7 @@
 		0xffffffff, 0xffffffff, /*  nonexistant  */
 	};
 
-#endif
-#if CONFIG_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 	/* i945 G/P */
 	static const u32 data_clock_crossing[] = {
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2792,10 +2789,9 @@
 {
 	u8 clocks[2] = { 0, 0 };
 
-#if CONFIG_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 #define CLOCKS_WIDTH 2
-#endif
-#if CONFIG_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 #define CLOCKS_WIDTH 3
 #endif
 	if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)

From svn at coreboot.org  Fri Oct  1 11:11:15 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 11:11:15 +0200
Subject: [coreboot] [commit] r5892 - trunk/src/cpu/amd/car
Message-ID: <E1P1be7-00047b-T9@ra.coresystems.de>

Author: uwe
Date: Fri Oct  1 11:11:15 2010
New Revision: 5892
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5892

Log:
Add missing parenthesis (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/cpu/amd/car/cache_as_ram.inc

Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc	Fri Oct  1 10:02:45 2010	(r5891)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc	Fri Oct  1 11:11:15 2010	(r5892)
@@ -139,7 +139,7 @@
 	movl	$MSR_MCFG_BASE, %ecx
 	rdmsr
 	andl	$(~(0xfff00000 | (0xf << 2))), %eax
-	orl	$((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000), %eax
+	orl	$((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000)), %eax
 	orl	$((8 << 2) | (1 << 0)), %eax
 	andl	$(~(0x0000ffff)), %edx
 	orl	$(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx



From svn at coreboot.org  Fri Oct  1 11:13:18 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 11:13:18 +0200
Subject: [coreboot] [commit] r5893 - in trunk/src: mainboard/getac/p470
	mainboard/ibase/mb899 mainboard/intel/d945gclf
	mainboard/kontron/986lcd-m mainboard/roda/rk886ex
	northbridge/intel northbridge/intel/i945
Message-ID: <E1P1bg6-0007Do-RJ@ra.coresystems.de>

Author: oxygene
Date: Fri Oct  1 11:13:18 2010
New Revision: 5893
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5893

Log:
Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GM

Both chipsets use the src/northbridge/intel/i945 code but that code
needs to know which chipset is actually used. Having separate
NORTHBRIDGE_ options allows the I945GC/I945GM choice to be removed
since code can test the NORTHBRIDGE_ option directly.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>

Modified:
   trunk/src/mainboard/getac/p470/Kconfig
   trunk/src/mainboard/ibase/mb899/Kconfig
   trunk/src/mainboard/intel/d945gclf/Kconfig
   trunk/src/mainboard/kontron/986lcd-m/Kconfig
   trunk/src/mainboard/roda/rk886ex/Kconfig
   trunk/src/northbridge/intel/Makefile.inc
   trunk/src/northbridge/intel/i945/Kconfig
   trunk/src/northbridge/intel/i945/raminit.c

Modified: trunk/src/mainboard/getac/p470/Kconfig
==============================================================================
--- trunk/src/mainboard/getac/p470/Kconfig	Fri Oct  1 11:11:15 2010	(r5892)
+++ trunk/src/mainboard/getac/p470/Kconfig	Fri Oct  1 11:13:18 2010	(r5893)
@@ -23,7 +23,7 @@
 	select ARCH_X86
 	select CPU_INTEL_CORE
 	select CPU_INTEL_SOCKET_MFCPGA478
-	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SOUTHBRIDGE_TI_PCIXX12
 	select SUPERIO_SMSC_FDC37N972
@@ -43,7 +43,6 @@
 	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
-	select I945GM
 	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR

Modified: trunk/src/mainboard/ibase/mb899/Kconfig
==============================================================================
--- trunk/src/mainboard/ibase/mb899/Kconfig	Fri Oct  1 11:11:15 2010	(r5892)
+++ trunk/src/mainboard/ibase/mb899/Kconfig	Fri Oct  1 11:13:18 2010	(r5893)
@@ -5,7 +5,7 @@
 	select ARCH_X86
 	select CPU_INTEL_CORE
 	select CPU_INTEL_SOCKET_MFCPGA478
-	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_WINBOND_W83627EHG
 	select BOARD_HAS_FADT
@@ -20,7 +20,6 @@
 	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
-	select I945GM
 	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR

Modified: trunk/src/mainboard/intel/d945gclf/Kconfig
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/Kconfig	Fri Oct  1 11:11:15 2010	(r5892)
+++ trunk/src/mainboard/intel/d945gclf/Kconfig	Fri Oct  1 11:13:18 2010	(r5893)
@@ -22,7 +22,7 @@
 	def_bool y
 	select ARCH_X86
 	select CPU_INTEL_SOCKET_441
-	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_I945GC
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_SMSC_LPC47M15X
 	select BOARD_HAS_FADT
@@ -40,7 +40,6 @@
 	select BOARD_ROMSIZE_KB_512
 	select GFXUMA
 	select TINY_BOOTBLOCK
-	select I945GC
 	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR

Modified: trunk/src/mainboard/kontron/986lcd-m/Kconfig
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/Kconfig	Fri Oct  1 11:11:15 2010	(r5892)
+++ trunk/src/mainboard/kontron/986lcd-m/Kconfig	Fri Oct  1 11:13:18 2010	(r5893)
@@ -5,7 +5,7 @@
 	select ARCH_X86
 	select CPU_INTEL_CORE
 	select CPU_INTEL_SOCKET_MFCPGA478
-	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_WINBOND_W83627THG
 	select BOARD_HAS_FADT
@@ -21,7 +21,6 @@
 	select GFXUMA
 	select TINY_BOOTBLOCK
 	select CHANNEL_XOR_RANDOMIZATION
-	select I945GM
 	select OVERRIDE_CLOCK_DISABLE
 
 config MAINBOARD_DIR

Modified: trunk/src/mainboard/roda/rk886ex/Kconfig
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/Kconfig	Fri Oct  1 11:11:15 2010	(r5892)
+++ trunk/src/mainboard/roda/rk886ex/Kconfig	Fri Oct  1 11:13:18 2010	(r5893)
@@ -5,7 +5,7 @@
 	select ARCH_X86
 	select CPU_INTEL_CORE
 	select CPU_INTEL_SOCKET_MFCPGA478
-	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SOUTHBRIDGE_TI_PCI7420
 	select SUPERIO_SMSC_LPC47N227
@@ -19,7 +19,6 @@
 	select HAVE_ACPI_TABLES
 	select HAVE_ACPI_RESUME
 	select BOARD_ROMSIZE_KB_1024
-	select I945GM
 	select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR

Modified: trunk/src/northbridge/intel/Makefile.inc
==============================================================================
--- trunk/src/northbridge/intel/Makefile.inc	Fri Oct  1 11:11:15 2010	(r5892)
+++ trunk/src/northbridge/intel/Makefile.inc	Fri Oct  1 11:13:18 2010	(r5893)
@@ -7,4 +7,5 @@
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945

Modified: trunk/src/northbridge/intel/i945/Kconfig
==============================================================================
--- trunk/src/northbridge/intel/i945/Kconfig	Fri Oct  1 11:11:15 2010	(r5892)
+++ trunk/src/northbridge/intel/i945/Kconfig	Fri Oct  1 11:13:18 2010	(r5893)
@@ -17,38 +17,27 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-config NORTHBRIDGE_INTEL_I945
+config NORTHBRIDGE_INTEL_I945GC
 	bool
 	select HAVE_DEBUG_RAM_SETUP
 
+config NORTHBRIDGE_INTEL_I945GM
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+
+if NORTHBRIDGE_INTEL_I945GC || NORTHBRIDGE_INTEL_I945GM
+
 config FALLBACK_VGA_BIOS_ID
 	string
 	default "8086,27a2"
-	depends on NORTHBRIDGE_INTEL_I945
-
-choice
-	default I945GM
-	depends on NORTHBRIDGE_INTEL_I945
-	help
-	  Different i945 variants require slightly different setup.
-
-config I945GM
-	bool "i945GM (Mobile) chipset"
-
-config I945GC
-	bool "i945GC chipset"
-
-endchoice
 
 config CHANNEL_XOR_RANDOMIZATION
 	bool
 	default n
-	depends on NORTHBRIDGE_INTEL_I945
 
 config OVERRIDE_CLOCK_DISABLE
 	bool
 	default n
-	depends on NORTHBRIDGE_INTEL_I945
 	help
 	  Usually system firmware turns off system memory clock
 	  signals to unused SO-DIMM slots to reduce EMI and power
@@ -59,8 +48,9 @@
 config MAXIMUM_SUPPORTED_FREQUENCY
 	int
 	default 0
-	depends on NORTHBRIDGE_INTEL_I945
 	help
 	  If non-zero, this designates the maximum DDR frequency
 	  the board supports, despite what the chipset should be
 	  capable of.
+
+endif

Modified: trunk/src/northbridge/intel/i945/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/i945/raminit.c	Fri Oct  1 11:11:15 2010	(r5892)
+++ trunk/src/northbridge/intel/i945/raminit.c	Fri Oct  1 11:13:18 2010	(r5893)
@@ -90,7 +90,7 @@
 static int memclk(void)
 {
 	int offset = 0;
-#if CONFIG_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 	offset++;
 #endif
 	switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
@@ -102,7 +102,7 @@
 	return -1;
 }
 
-#if CONFIG_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 static int fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
@@ -113,8 +113,7 @@
 	}
 	return -1;
 }
-#endif
-#if CONFIG_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 static int fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
@@ -1045,7 +1044,7 @@
 	return nc;
 }
 
-#if CONFIG_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 /* Strength multiplier tables */
 static const u8 dual_channel_strength_multiplier[] = {
 	0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@@ -1100,8 +1099,7 @@
 	0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 	0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
 };
-#endif
-#if CONFIG_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 static const u8 dual_channel_strength_multiplier[] = {
 	0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
 	0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@@ -2155,7 +2153,7 @@
 	/**
 	 * We add the indices according to our clocks from CLKCFG.
 	 */
-#if CONFIG_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 	static const u32 data_clock_crossing[] = {
 		0x00100401, 0x00000000, /* DDR400 FSB400 */
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2200,8 +2198,7 @@
 		0xffffffff, 0xffffffff, /*  nonexistant  */
 	};
 
-#endif
-#if CONFIG_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 	/* i945 G/P */
 	static const u32 data_clock_crossing[] = {
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2792,10 +2789,9 @@
 {
 	u8 clocks[2] = { 0, 0 };
 
-#if CONFIG_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 #define CLOCKS_WIDTH 2
-#endif
-#if CONFIG_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 #define CLOCKS_WIDTH 3
 #endif
 	if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)



From patrick at georgi-clan.de  Fri Oct  1 11:14:16 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 01 Oct 2010 11:14:16 +0200
Subject: [coreboot] [PATCH] Split NORTHBRIDGE_INTEL_I945 into
 more	precise _I945GC and _I945GM
In-Reply-To: <20101001090207.16378.qmail@stuge.se>
References: <20101001090207.16378.qmail@stuge.se>
Message-ID: <4CA5A668.9060602@georgi-clan.de>

Am 01.10.2010 11:02, schrieb Peter Stuge:
> Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GM
> 
> Both chipsets use the src/northbridge/intel/i945 code but that code
> needs to know which chipset is actually used. Having separate
> NORTHBRIDGE_ options allows the I945GC/I945GM choice to be removed
> since code can test the NORTHBRIDGE_ option directly.
> 
> Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>
and committed in r5893

Also fixes my stupid compile breakage in r5891

Thanks,
Patrick



From patrick at georgi-clan.de  Fri Oct  1 11:20:41 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 01 Oct 2010 11:20:41 +0200
Subject: [coreboot] [PATCH]Remove useless defines
Message-ID: <4CA5A7E9.8080703@georgi-clan.de>

Hi,

attached patch removes a couple of defines that seem to be the result of
copy&paste, without actually being used.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: 20101001-2-remove-useless-defines
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20101001/434df223/attachment.ksh>

From peter at stuge.se  Fri Oct  1 11:27:45 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Oct 2010 11:27:45 +0200
Subject: [coreboot] [PATCH]Remove useless defines
In-Reply-To: <4CA5A7E9.8080703@georgi-clan.de>
References: <4CA5A7E9.8080703@georgi-clan.de>
Message-ID: <20101001092745.19880.qmail@stuge.se>

Patrick Georgi wrote:
> attached patch removes a couple of defines that seem to be the result of
> copy&paste, without actually being used.
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Fri Oct  1 11:31:42 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 11:31:42 +0200
Subject: [coreboot] build service results for r5892
Message-ID: <E1P1bxu-0001rh-Dz@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "uwe" checked in revision 5892 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add missing parenthesis (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of amd:mahogany_fam10 has been fixed
Compilation of amd:serengeti_cheetah_fam10 has been fixed
Compilation of amd:tilapia_fam10 has been fixed
Compilation of asus:m4a785-m has been fixed
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=adl855pc&vendor=digitallogic&num=2
Compilation of getac:p470 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=p470&vendor=getac&num=2
Compilation of gigabyte:ma785gmt has been fixed
Compilation of gigabyte:ma78gm has been fixed
Compilation of hp:dl165_g6_fam10 has been fixed
Compilation of ibase:mb899 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=mb899&vendor=ibase&num=2
Compilation of iei:kino-780am2-fam10 has been fixed
Compilation of intel:d810e2cb is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=d810e2cb&vendor=intel&num=2
Compilation of intel:d945gclf is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=d945gclf&vendor=intel&num=2
Compilation of jetway:pa78vm5 has been fixed
Compilation of kontron:986lcd-m is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=986lcd-m&vendor=kontron&num=2
Compilation of lanner:em8510 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=em8510&vendor=lanner&num=2
Compilation of msi:ms9652_fam10 has been fixed
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=rm4100&vendor=rca&num=2
Compilation of roda:rk886ex is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=rk886ex&vendor=roda&num=2
Compilation of supermicro:h8dmr_fam10 has been fixed
Compilation of supermicro:h8qme_fam10 has been fixed
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=ip1000&vendor=thomson&num=2
Compilation of tyan:s2912_fam10 has been fixed
Compilation of via:vt8454c is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5892&device=vt8454c&vendor=via&num=2


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Fri Oct  1 11:49:47 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Oct 2010 11:49:47 +0200
Subject: [coreboot] [PATCH] Make i945/raminit.c:fsbclk() return u16 rather
	than int
Message-ID: <20101001094947.22870.qmail@stuge.se>

Attached.


//Peter
-------------- next part --------------
Make i945/raminit.c:fsbclk() return u16 rather than int

This is needed for Gentoo gcc-4.1.2 to build the i945 code. A warning is
thrown because the comparison in the last hunk is between u16 and -1 and
can never be true.

Signed-off-by: Peter Stuge <peter at stuge.se>

Index: src/northbridge/intel/i945/raminit.c
===================================================================
--- src/northbridge/intel/i945/raminit.c	(revision 5893)
+++ src/northbridge/intel/i945/raminit.c	(working copy)
@@ -103,7 +103,7 @@
 }
 
 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
-static int fsbclk(void)
+static u16 fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
 	case 0: return 400;
@@ -111,10 +111,10 @@
 	case 3: return 667;
 	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
-	return -1;
+	return 0xffff;
 }
 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
-static int fsbclk(void)
+static u16 fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
 	case 0: return 1066;
@@ -122,7 +122,7 @@
 	case 2: return 800;
 	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
-	return -1;
+	return 0xffff;
 }
 #endif
 
@@ -1929,7 +1929,7 @@
 	MCHBAR32(PLLMON) = 0x80800000;
 
 	sysinfo->fsb_frequency = fsbclk();
-	if (sysinfo->fsb_frequency == -1)
+	if (sysinfo->fsb_frequency == 0xffff)
 		die("Unsupported FSB speed");
 
 	/* Program CPCTL according to FSB speed */

From svn at coreboot.org  Fri Oct  1 11:57:05 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 11:57:05 +0200
Subject: [coreboot] build service results for r5893
Message-ID: <E1P1cMT-00088z-7W@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5893 to
the coreboot repository. This caused the following 
changes:

Change Log:
Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GM

Both chipsets use the src/northbridge/intel/i945 code but that code
needs to know which chipset is actually used. Having separate
NORTHBRIDGE_ options allows the I945GC/I945GM choice to be removed
since code can test the NORTHBRIDGE_ option directly.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=adl855pc&vendor=digitallogic&num=2
Compilation of getac:p470 has been fixed
Compilation of ibase:mb899 has been fixed
Compilation of intel:d810e2cb is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=d810e2cb&vendor=intel&num=2
Compilation of intel:d945gclf has been fixed
Compilation of kontron:986lcd-m has been fixed
Compilation of lanner:em8510 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=em8510&vendor=lanner&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=rm4100&vendor=rca&num=2
Compilation of roda:rk886ex has been fixed
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=ip1000&vendor=thomson&num=2
Compilation of via:vt8454c is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=vt8454c&vendor=via&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Fri Oct  1 11:58:45 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 11:58:45 +0200
Subject: [coreboot] [commit] r5894 - in trunk/src/mainboard: dell/s1850
	intel/eagleheights intel/jarrell intel/mtarvon intel/truxton
	supermicro/x6dai_g supermicro/x6dhe_g supermicro/x6dhe_g2
	supermicro/x6dhr_ig superm...
Message-ID: <E1P1cO5-0008M4-0C@ra.coresystems.de>

Author: oxygene
Date: Fri Oct  1 11:58:44 2010
New Revision: 5894
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5894

Log:
Remove a couple of defines that seem to be the result of
copy&paste, without actually being used.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/dell/s1850/romstage.c
   trunk/src/mainboard/intel/eagleheights/romstage.c
   trunk/src/mainboard/intel/jarrell/romstage.c
   trunk/src/mainboard/intel/mtarvon/romstage.c
   trunk/src/mainboard/intel/truxton/romstage.c
   trunk/src/mainboard/supermicro/x6dai_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c

Modified: trunk/src/mainboard/dell/s1850/romstage.c
==============================================================================
--- trunk/src/mainboard/dell/s1850/romstage.c	Fri Oct  1 11:13:18 2010	(r5893)
+++ trunk/src/mainboard/dell/s1850/romstage.c	Fri Oct  1 11:58:44 2010	(r5894)
@@ -20,9 +20,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
 
 #define DEVPRES_CONFIG  ( \
@@ -35,9 +32,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0808090a
-#define RECVENB_CONFIG  0x0808090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/intel/eagleheights/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/romstage.c	Fri Oct  1 11:13:18 2010	(r5893)
+++ trunk/src/mainboard/intel/eagleheights/romstage.c	Fri Oct  1 11:58:44 2010	(r5894)
@@ -59,9 +59,6 @@
 #define UART_MSR 0x06
 #define UART_SCR 0x07
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 

Modified: trunk/src/mainboard/intel/jarrell/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/jarrell/romstage.c	Fri Oct  1 11:13:18 2010	(r5893)
+++ trunk/src/mainboard/intel/jarrell/romstage.c	Fri Oct  1 11:58:44 2010	(r5894)
@@ -29,10 +29,6 @@
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-/* Beta values:         0x00090800 */
-/* Silver values:       0x000a0900 */
-#define RECVENA_CONFIG  0x000a090a
-#define RECVENB_CONFIG  0x000a090a
 #define DIMM_MAP_LOGICAL 0x0124
 
 static inline int spd_read_byte(unsigned device, unsigned address)

Modified: trunk/src/mainboard/intel/mtarvon/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/mtarvon/romstage.c	Fri Oct  1 11:13:18 2010	(r5893)
+++ trunk/src/mainboard/intel/mtarvon/romstage.c	Fri Oct  1 11:58:44 2010	(r5894)
@@ -38,9 +38,6 @@
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 

Modified: trunk/src/mainboard/intel/truxton/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/truxton/romstage.c	Fri Oct  1 11:13:18 2010	(r5893)
+++ trunk/src/mainboard/intel/truxton/romstage.c	Fri Oct  1 11:58:44 2010	(r5894)
@@ -40,9 +40,6 @@
 #include "cpu/x86/bist.h"
 #include "spd.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
 
 static inline int spd_read_byte(u16 device, u8 address)

Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/romstage.c	Fri Oct  1 11:13:18 2010	(r5893)
+++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c	Fri Oct  1 11:58:44 2010	(r5894)
@@ -21,9 +21,6 @@
 #include "northbridge/intel/e7525/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
 
@@ -36,9 +33,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0808090a
-#define RECVENB_CONFIG  0x0808090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Fri Oct  1 11:13:18 2010	(r5893)
+++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Fri Oct  1 11:58:44 2010	(r5894)
@@ -22,9 +22,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
 
@@ -37,9 +34,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0808090a
-#define RECVENB_CONFIG  0x0808090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c	Fri Oct  1 11:13:18 2010	(r5893)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c	Fri Oct  1 11:58:44 2010	(r5894)
@@ -20,9 +20,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP2)
 
@@ -35,9 +32,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0708090a
-#define RECVENB_CONFIG  0x0708090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Fri Oct  1 11:13:18 2010	(r5893)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Fri Oct  1 11:58:44 2010	(r5894)
@@ -20,9 +20,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
 
@@ -36,9 +33,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0808090a
-#define RECVENB_CONFIG  0x0808090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Fri Oct  1 11:13:18 2010	(r5893)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Fri Oct  1 11:58:44 2010	(r5894)
@@ -20,9 +20,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
 
@@ -36,9 +33,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0808090a
-#define RECVENB_CONFIG  0x0808090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);



From svn at coreboot.org  Fri Oct  1 12:02:39 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 12:02:39 +0200
Subject: [coreboot] [commit] r5895 - trunk/src/northbridge/intel/i945
Message-ID: <E1P1cRr-0005Sh-WA@ra.coresystems.de>

Author: oxygene
Date: Fri Oct  1 12:02:33 2010
New Revision: 5895
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5895

Log:
Make i945/raminit.c:fsbclk() return u16 rather than int

This is needed for Gentoo gcc-4.1.2 to build the i945 code. A warning is
thrown because the comparison in the last hunk is between u16 and -1 and
can never be true.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>

Modified:
   trunk/src/northbridge/intel/i945/raminit.c

Modified: trunk/src/northbridge/intel/i945/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/i945/raminit.c	Fri Oct  1 11:58:44 2010	(r5894)
+++ trunk/src/northbridge/intel/i945/raminit.c	Fri Oct  1 12:02:33 2010	(r5895)
@@ -103,7 +103,7 @@
 }
 
 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
-static int fsbclk(void)
+static u16 fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
 	case 0: return 400;
@@ -111,10 +111,10 @@
 	case 3: return 667;
 	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
-	return -1;
+	return 0xffff;
 }
 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
-static int fsbclk(void)
+static u16 fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
 	case 0: return 1066;
@@ -122,7 +122,7 @@
 	case 2: return 800;
 	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
-	return -1;
+	return 0xffff;
 }
 #endif
 
@@ -1929,7 +1929,7 @@
 	MCHBAR32(PLLMON) = 0x80800000;
 
 	sysinfo->fsb_frequency = fsbclk();
-	if (sysinfo->fsb_frequency == -1)
+	if (sysinfo->fsb_frequency == 0xffff)
 		die("Unsupported FSB speed");
 
 	/* Program CPCTL according to FSB speed */



From svn at coreboot.org  Fri Oct  1 12:19:22 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 12:19:22 +0200
Subject: [coreboot] build service results for r5894
Message-ID: <E1P1ci2-0006Nk-SY@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5894 to
the coreboot repository. This caused the following 
changes:

Change Log:
Remove a couple of defines that seem to be the result of
copy&paste, without actually being used.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=adl855pc&vendor=digitallogic&num=2
Compilation of intel:d810e2cb is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=d810e2cb&vendor=intel&num=2
Compilation of lanner:em8510 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=em8510&vendor=lanner&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=rm4100&vendor=rca&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=ip1000&vendor=thomson&num=2
Compilation of via:vt8454c is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=vt8454c&vendor=via&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Fri Oct  1 12:45:40 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 12:45:40 +0200
Subject: [coreboot] build service results for r5895
Message-ID: <E1P1d7U-0005Nr-RD@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5895 to
the coreboot repository. This caused the following 
changes:

Change Log:
Make i945/raminit.c:fsbclk() return u16 rather than int

This is needed for Gentoo gcc-4.1.2 to build the i945 code. A warning is
thrown because the comparison in the last hunk is between u16 and -1 and
can never be true.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=adl855pc&vendor=digitallogic&num=2
Compilation of intel:d810e2cb is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=d810e2cb&vendor=intel&num=2
Compilation of lanner:em8510 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=em8510&vendor=lanner&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=rm4100&vendor=rca&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=ip1000&vendor=thomson&num=2
Compilation of via:vt8454c is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=vt8454c&vendor=via&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From wt at penguintechs.org  Fri Oct  1 12:51:44 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Fri,  1 Oct 2010 03:51:44 -0700
Subject: [coreboot] [PATCH] Make via/vt8454c use the big bootblock.
Message-ID: <1285930304-19097-1-git-send-email-wt@penguintechs.org>

This change gets the board building again. Since it is late here, I am
going to go to sleep. Anyone can feel free to commit this change if they
ack it.

Thanks,
wt
8<-------------------------------------------------------------------
The tiny boot block breaks cache-as-ram for this board. Specifically,
the crt0s.romstage.o target will not build without this change.

Signed-off-by: Warren Turkal <wt at penguintechs.org>
---
 src/mainboard/via/vt8454c/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig
index 6c08007..3ef94a3 100644
--- a/src/mainboard/via/vt8454c/Kconfig
+++ b/src/mainboard/via/vt8454c/Kconfig
@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_HARD_RESET
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512
-	select TINY_BOOTBLOCK
+#	select TINY_BOOTBLOCK
 
 config MAINBOARD_DIR
 	string
-- 
1.7.1




From patrick at georgi-clan.de  Fri Oct  1 13:16:12 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 01 Oct 2010 13:16:12 +0200
Subject: [coreboot] [PATCH]Move CACHE_AS_RAM_ADDRESS_DEBUG to Kconfig,
	default to false
Message-ID: <4CA5C2FC.5070407@georgi-clan.de>

Hi,

attached patch moves CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into
Kconfig, renames it slightly, makes it visible only on relevant
northbridges, drops it entirely from via boards (as they seem to have
picked it up from AMD code without using it themselves), and make it
default to false for all boards.

Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>


Patrick
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From svn at coreboot.org  Fri Oct  1 13:34:07 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 13:34:07 +0200
Subject: [coreboot] [commit] r5896 - in trunk/src/mainboard: amd/dbm690t
	amd/mahogany asrock/939a785gmh kontron/kt690
	technexion/tim5690 technexion/tim8690
Message-ID: <E1P1dsN-0001hd-Eb@ra.coresystems.de>

Author: oxygene
Date: Fri Oct  1 13:34:05 2010
New Revision: 5896
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5896

Log:
ICS951462_ADDRESS defined but _never_ used. Drop it.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>

Modified:
   trunk/src/mainboard/amd/dbm690t/romstage.c
   trunk/src/mainboard/amd/mahogany/romstage.c
   trunk/src/mainboard/asrock/939a785gmh/romstage.c
   trunk/src/mainboard/kontron/kt690/romstage.c
   trunk/src/mainboard/technexion/tim5690/romstage.c
   trunk/src/mainboard/technexion/tim8690/romstage.c

Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c	Fri Oct  1 12:02:33 2010	(r5895)
+++ trunk/src/mainboard/amd/dbm690t/romstage.c	Fri Oct  1 13:34:05 2010	(r5896)
@@ -30,7 +30,6 @@
 #define DIMM0 0x50
 #define DIMM1 0x51
 
-#define ICS951462_ADDRESS	0x69
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>

Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c	Fri Oct  1 12:02:33 2010	(r5895)
+++ trunk/src/mainboard/amd/mahogany/romstage.c	Fri Oct  1 13:34:05 2010	(r5896)
@@ -30,7 +30,6 @@
 #define DIMM0 0x50
 #define DIMM1 0x51
 
-#define ICS951462_ADDRESS	0x69
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>

Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c	Fri Oct  1 12:02:33 2010	(r5895)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c	Fri Oct  1 13:34:05 2010	(r5896)
@@ -31,7 +31,6 @@
 #define DIMM0 0x50
 #define DIMM1 0x51
 
-#define ICS951462_ADDRESS	0x69
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>

Modified: trunk/src/mainboard/kontron/kt690/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/romstage.c	Fri Oct  1 12:02:33 2010	(r5895)
+++ trunk/src/mainboard/kontron/kt690/romstage.c	Fri Oct  1 13:34:05 2010	(r5896)
@@ -31,7 +31,6 @@
 #define DIMM0 0x50
 #define DIMM1 0x51
 
-#define ICS951462_ADDRESS	0x69
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>

Modified: trunk/src/mainboard/technexion/tim5690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/romstage.c	Fri Oct  1 12:02:33 2010	(r5895)
+++ trunk/src/mainboard/technexion/tim5690/romstage.c	Fri Oct  1 13:34:05 2010	(r5896)
@@ -30,7 +30,6 @@
 #define DIMM0 0x50
 #define DIMM1 0x51
 
-#define ICS951462_ADDRESS	0x69
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>

Modified: trunk/src/mainboard/technexion/tim8690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/romstage.c	Fri Oct  1 12:02:33 2010	(r5895)
+++ trunk/src/mainboard/technexion/tim8690/romstage.c	Fri Oct  1 13:34:05 2010	(r5896)
@@ -30,7 +30,6 @@
 #define DIMM0 0x50
 #define DIMM1 0x51
 
-#define ICS951462_ADDRESS	0x69
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>



From stefan.reinauer at coresystems.de  Fri Oct  1 13:38:35 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 01 Oct 2010 13:38:35 +0200
Subject: [coreboot] [PATCH] Make via/vt8454c use the big bootblock.
In-Reply-To: <1285930304-19097-1-git-send-email-wt@penguintechs.org>
References: <1285930304-19097-1-git-send-email-wt@penguintechs.org>
Message-ID: <4CA5C83B.1040005@coresystems.de>

 On 10/1/10 12:51 PM, Warren Turkal wrote:
> This change gets the board building again. Since it is late here, I am
> going to go to sleep. Anyone can feel free to commit this change if they
> ack it.
NACK! Please don't go back to big bootblock. Instead rather fix the code.

Stefan



From svn at coreboot.org  Fri Oct  1 14:15:31 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 14:15:31 +0200
Subject: [coreboot] build service results for r5896
Message-ID: <E1P1eWR-0004Ei-UI@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5896 to
the coreboot repository. This caused the following 
changes:

Change Log:
ICS951462_ADDRESS defined but _never_ used. Drop it.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=adl855pc&vendor=digitallogic&num=2
Compilation of intel:d810e2cb is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=d810e2cb&vendor=intel&num=2
Compilation of lanner:em8510 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=em8510&vendor=lanner&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=rm4100&vendor=rca&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=ip1000&vendor=thomson&num=2
Compilation of via:vt8454c is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=vt8454c&vendor=via&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Fri Oct  1 14:24:58 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 14:24:58 +0200
Subject: [coreboot] [commit] r5897 - trunk/src/cpu/via/car
Message-ID: <E1P1efa-0005HU-64@ra.coresystems.de>

Author: stepan
Date: Fri Oct  1 14:24:57 2010
New Revision: 5897
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5897

Log:
fix VIA C7 code.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/cpu/via/car/cache_as_ram.inc

Modified: trunk/src/cpu/via/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/via/car/cache_as_ram.inc	Fri Oct  1 13:34:05 2010	(r5896)
+++ trunk/src/cpu/via/car/cache_as_ram.inc	Fri Oct  1 14:24:57 2010	(r5897)
@@ -100,7 +100,8 @@
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
-	movl	$(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
@@ -243,7 +244,8 @@
 	/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
 	movl	$MTRRphysBase_MSR(3), %ecx
 	xorl	%edx, %edx
-	movl	$(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(3), %ecx



From svn at coreboot.org  Fri Oct  1 14:45:03 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 14:45:03 +0200
Subject: [coreboot] build service results for r5897
Message-ID: <E1P1ez1-0002qf-0q@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5897 to
the coreboot repository. This caused the following 
changes:

Change Log:
fix VIA C7 code.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5897&device=adl855pc&vendor=digitallogic&num=2
Compilation of intel:d810e2cb is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5897&device=d810e2cb&vendor=intel&num=2
Compilation of lanner:em8510 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5897&device=em8510&vendor=lanner&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5897&device=rm4100&vendor=rca&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5897&device=ip1000&vendor=thomson&num=2
Compilation of via:vt8454c has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Fri Oct  1 14:45:13 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Oct 2010 14:45:13 +0200
Subject: [coreboot] [PATCH]Move CACHE_AS_RAM_ADDRESS_DEBUG to Kconfig,
	default to false
In-Reply-To: <4CA5C2FC.5070407@georgi-clan.de>
References: <4CA5C2FC.5070407@georgi-clan.de>
Message-ID: <20101001124513.16895.qmail@stuge.se>

Patrick Georgi wrote:
> attached patch moves CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into
> Kconfig, renames it slightly, makes it visible only on relevant
> northbridges, drops it entirely from via boards (as they seem to have
> picked it up from AMD code without using it themselves), and make it
> default to false for all boards.
> 
> Some romstages used to set this to "true" (ie. "print debug output"),
> but I didn't follow up on it in Kconfig - if you need it to debug CAR,
> enable it yourself.
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>



From wt at penguintechs.org  Fri Oct  1 14:20:45 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Fri, 1 Oct 2010 05:20:45 -0700
Subject: [coreboot] [PATCH] Make via/vt8454c use the big bootblock.
In-Reply-To: <4CA5C83B.1040005@coresystems.de>
References: <1285930304-19097-1-git-send-email-wt@penguintechs.org>
	<4CA5C83B.1040005@coresystems.de>
Message-ID: <AANLkTikk=KCm4+VR2rr3paDtHmxgGx-H0Q3tf2eqYOOz@mail.gmail.com>

For what it's worth, I agree. I will look into this more after I wake up.

wt

On Fri, Oct 1, 2010 at 4:38 AM, Stefan Reinauer
<stefan.reinauer at coresystems.de> wrote:
> ?On 10/1/10 12:51 PM, Warren Turkal wrote:
>> This change gets the board building again. Since it is late here, I am
>> going to go to sleep. Anyone can feel free to commit this change if they
>> ack it.
> NACK! Please don't go back to big bootblock. Instead rather fix the code.
>
> Stefan
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From jakllsch at kollasch.net  Fri Oct  1 15:24:53 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Fri, 1 Oct 2010 13:24:53 +0000
Subject: [coreboot] [patch] use mptable_write_buses() for ms7135
Message-ID: <20101001132453.GC12447@tarantulon.kollasch.net>

Use mptable_write_buses() for msi/ms7135 mptable.
Also, drop unnecessary comment.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
---
-------------- next part --------------
Index: src/mainboard/msi/ms7135/mptable.c
===================================================================
--- src/mainboard/msi/ms7135/mptable.c	(revision 5896)
+++ src/mainboard/msi/ms7135/mptable.c	(working copy)
@@ -30,23 +30,20 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern unsigned char bus_isa;
 extern unsigned char bus_ck804[6];
 extern unsigned apicid_ck804;
 
-extern unsigned bus_type[256];
-
-
-
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
 	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "MS7135      ";
 	struct mp_config_table *mc;
+	int bus_isa;
 	unsigned sbdn;
 
-	int bus_num;
+	get_bus_conf();
+	sbdn = sysconf.sbdn;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	memset(mc, 0, sizeof(*mc));
@@ -66,19 +63,8 @@
 	mc->reserved = 0;
 
 	smp_write_processors(mc);
+	mptable_write_buses(mc, NULL, &bus_isa);
 
-	get_bus_conf();
-	sbdn = sysconf.sbdn;
-
-/* Bus:		Bus ID	Type*/
-	/* define numbers for pci and isa bus */
-	for (bus_num = 0; bus_num < 256; bus_num++) {
-		if (bus_type[bus_num])
-			smp_write_bus(mc, bus_num, "PCI   ");
-	}
-	smp_write_bus(mc, bus_isa, "ISA   ");
-
-
 /* I/O APICs:	APIC ID	Version	State		Address*/
 	{
 		device_t dev;
@@ -98,7 +84,6 @@
 			/* copied from stock bios */
 			/*0x01800500,0x1800d509,0x00520d08*/
 
-			/* if this register is what i think it is ... */
 			dword = 0x08d0d218;
 			pci_write_config32(dev, 0x7c, dword);
 

From svn at coreboot.org  Fri Oct  1 16:35:07 2010
From: svn at coreboot.org (coreboot)
Date: Fri, 01 Oct 2010 14:35:07 -0000
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
Message-ID: <058.c4905997b68639c6b43f22031ad8ed81@coreboot.org>

#163: Board still requires RAMBASE <1MB
-----------------------------------------+----------------------------------
    Reporter:  oxygene                   |          Owner:  stepan@?             
        Type:  defect                    |         Status:  closed               
    Priority:  minor                     |      Milestone:                       
   Component:  coreboot                  |     Resolution:  fixed                
    Keywords:                            |   Dependencies:                       
Patch Status:  patch has been committed  |  
-----------------------------------------+----------------------------------

Comment (by Buy tegretol online):

 Looking where to buy tegretol online? No problem!<a
 href=http://www.youthcabinet.org/forum/topics/buy-tegretol-cheap-
 tegretoll>buy tegretol online
 </a>

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/163#comment:2>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Oct  1 16:50:13 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 16:50:13 +0200
Subject: [coreboot] [commit] r5898 - in trunk/src: .
	mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah
	mainboard/amd/serengeti_cheetah_fam10
	mainboard/amd/tilapia_fam10 mainboard/asus/a8v-e_se mainboard/asu...
Message-ID: <E1P1gw9-0000jT-E9@ra.coresystems.de>

Author: oxygene
Date: Fri Oct  1 16:50:12 2010
New Revision: 5898
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5898

Log:
Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,
rename it slightly, make it visible only on relevant northbridges,
drop it entirely from via boards (as they seem to have picked it
up from AMD code without using it themselves), and make it
default to false for all boards.

Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/Kconfig
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
   trunk/src/mainboard/amd/tilapia_fam10/romstage.c
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/asus/m2v-mx_se/romstage.c
   trunk/src/mainboard/asus/m4a785-m/romstage.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
   trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c
   trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
   trunk/src/mainboard/gigabyte/ma78gm/romstage.c
   trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
   trunk/src/mainboard/iwill/dk8_htx/romstage.c
   trunk/src/mainboard/iwill/dk8s2/romstage.c
   trunk/src/mainboard/iwill/dk8x/romstage.c
   trunk/src/mainboard/jetway/pa78vm5/romstage.c
   trunk/src/mainboard/msi/ms7260/ap_romstage.c
   trunk/src/mainboard/msi/ms7260/romstage.c
   trunk/src/mainboard/msi/ms9185/romstage.c
   trunk/src/mainboard/msi/ms9282/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
   trunk/src/mainboard/supermicro/h8dme/ap_romstage.c
   trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c
   trunk/src/mainboard/tyan/s2912/ap_romstage.c
   trunk/src/mainboard/via/epia-m700/romstage.c
   trunk/src/northbridge/amd/amdfam10/Kconfig
   trunk/src/northbridge/amd/amdfam10/debug.c
   trunk/src/northbridge/amd/amdk8/Kconfig
   trunk/src/northbridge/amd/amdk8/debug.c
   trunk/src/northbridge/via/vx800/examples/romstage.c

Modified: trunk/src/Kconfig
==============================================================================
--- trunk/src/Kconfig	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/Kconfig	Fri Oct  1 16:50:12 2010	(r5898)
@@ -499,6 +499,16 @@
 
 	  If unsure, say N.
 
+config HAVE_DEBUG_CAR
+	def_bool n
+
+config DEBUG_CAR
+	bool "Output verbose Cache-as-RAM debug messages"
+	default n
+	depends on HAVE_DEBUG_CAR
+	help
+	  This option enables additional CAR related debug messages.
+
 config DEBUG_PIRQ
 	bool "Check PIRQ table consistency"
 	default n

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -2,7 +2,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -1,5 +1,4 @@
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -24,8 +24,6 @@
 
 #define RAMINIT_SYSINFO 1
 
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
 unsigned int get_sbdn(unsigned bus);
 
 /* Used by raminit. */

Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -24,8 +24,6 @@
 
 #define RAMINIT_SYSINFO 1
 
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
 unsigned int get_sbdn(unsigned bus);
 
 /* Used by raminit. */

Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -25,7 +25,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -23,7 +23,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -1,5 +1,4 @@
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -1,5 +1,4 @@
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -1,5 +1,4 @@
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -23,7 +23,6 @@
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/msi/ms7260/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/ap_romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/msi/ms7260/ap_romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -24,7 +24,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 #define SET_NB_CFG_54 1			/* Used by RAM init. */
 #define QRANK_DIMM_SUPPORT 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0

Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/msi/ms7260/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -20,7 +20,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
 // #define RAM_TIMING_DEBUG 1
 // #define DQS_TRAIN_DEBUG 1
 // #define RES_DEBUG 1

Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/msi/ms9185/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -24,7 +24,6 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/msi/ms9282/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -23,7 +23,6 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -23,7 +23,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -23,7 +23,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -23,7 +23,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/ap_romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/tyan/s2912/ap_romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -23,7 +23,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

Modified: trunk/src/mainboard/via/epia-m700/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m700/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/mainboard/via/epia-m700/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -23,7 +23,6 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 #define PAYLOAD_IS_SEABIOS 0
 
 #include <stdint.h>

Modified: trunk/src/northbridge/amd/amdfam10/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/Kconfig	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/northbridge/amd/amdfam10/Kconfig	Fri Oct  1 16:50:12 2010	(r5898)
@@ -21,6 +21,7 @@
 	bool
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
+	select HAVE_DEBUG_CAR
 	select HYPERTRANSPORT_PLUGIN_SUPPORT
 	select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
 	select MMCONF_SUPPORT

Modified: trunk/src/northbridge/amd/amdfam10/debug.c
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/debug.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/northbridge/amd/amdfam10/debug.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -26,7 +26,7 @@
 
 static inline void print_debug_addr(const char *str, void *val)
 {
-#if defined(CACHE_AS_RAM_ADDRESS_DEBUG) && CACHE_AS_RAM_ADDRESS_DEBUG == 1
+#if CONFIG_DEBUG_CAR
 		printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
 #endif
 }

Modified: trunk/src/northbridge/amd/amdk8/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/amdk8/Kconfig	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/northbridge/amd/amdk8/Kconfig	Fri Oct  1 16:50:12 2010	(r5898)
@@ -21,6 +21,7 @@
 	bool
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
+	select HAVE_DEBUG_CAR
 	select HYPERTRANSPORT_PLUGIN_SUPPORT
 
 config AGP_APERTURE_SIZE

Modified: trunk/src/northbridge/amd/amdk8/debug.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/debug.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/northbridge/amd/amdk8/debug.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -3,13 +3,9 @@
  *
  */
 
-#ifndef CACHE_AS_RAM_ADDRESS_DEBUG
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-#endif
-
 static inline void print_debug_addr(const char *str, void *val)
 {
-#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
+#if CONFIG_DEBUG_CAR
 		printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
 #endif
 }

Modified: trunk/src/northbridge/via/vx800/examples/romstage.c
==============================================================================
--- trunk/src/northbridge/via/vx800/examples/romstage.c	Fri Oct  1 14:24:57 2010	(r5897)
+++ trunk/src/northbridge/via/vx800/examples/romstage.c	Fri Oct  1 16:50:12 2010	(r5898)
@@ -21,7 +21,6 @@
 #define ASSEMBLY 1
 #define __PRE_RAM__
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #include <stdint.h>
 #include <device/pci_def.h>



From svn at coreboot.org  Fri Oct  1 17:12:06 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 17:12:06 +0200
Subject: [coreboot] build service results for r5898
Message-ID: <E1P1hHK-00076U-NB@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5898 to
the coreboot repository. This caused the following 
changes:

Change Log:
Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,
rename it slightly, make it visible only on relevant northbridges,
drop it entirely from via boards (as they seem to have picked it
up from AMD code without using it themselves), and make it
default to false for all boards.

Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5898&device=adl855pc&vendor=digitallogic&num=2
Compilation of intel:d810e2cb is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5898&device=d810e2cb&vendor=intel&num=2
Compilation of lanner:em8510 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5898&device=em8510&vendor=lanner&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5898&device=rm4100&vendor=rca&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5898&device=ip1000&vendor=thomson&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Fri Oct  1 17:16:20 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 17:16:20 +0200
Subject: [coreboot] [commit] r5899 - trunk/src/cpu/intel/car
Message-ID: <E1P1hLQ-0007ve-H7@ra.coresystems.de>

Author: myles
Date: Fri Oct  1 17:16:20 2010
New Revision: 5899
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5899

Log:
Fix some breakage from 5890.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/cpu/intel/car/cache_as_ram.inc

Modified: trunk/src/cpu/intel/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/car/cache_as_ram.inc	Fri Oct  1 16:50:12 2010	(r5898)
+++ trunk/src/cpu/intel/car/cache_as_ram.inc	Fri Oct  1 17:16:20 2010	(r5899)
@@ -221,7 +221,8 @@
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
-	movl	$(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx



From svn at coreboot.org  Fri Oct  1 17:23:42 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 17:23:42 +0200
Subject: [coreboot] [commit] r5900 - trunk/src/lib
Message-ID: <E1P1hSY-0002Tz-4I@ra.coresystems.de>

Author: myles
Date: Fri Oct  1 17:23:41 2010
New Revision: 5900
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5900

Log:
Fix make warnings:

Makefile:261: warning: overriding commands for target `coreboot-builds/a-trend_atc-6220/lib/lzma.ramstage.o'
Makefile:261: warning: ignoring old commands for target `coreboot-builds/a-trend_atc-6220/lib/lzma.ramstage.o'

lzma.c is already included unconditionally in the same file.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/lib/Makefile.inc

Modified: trunk/src/lib/Makefile.inc
==============================================================================
--- trunk/src/lib/Makefile.inc	Fri Oct  1 17:16:20 2010	(r5899)
+++ trunk/src/lib/Makefile.inc	Fri Oct  1 17:23:41 2010	(r5900)
@@ -28,8 +28,6 @@
 
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 
-ramstage-$(CONFIG_COMPRESSED_PAYLOAD_LZMA) += lzma.c
-
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 
 smm-y += memcpy.c



From rminnich at gmail.com  Fri Oct  1 17:33:24 2010
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Oct 2010 08:33:24 -0700
Subject: [coreboot] [PATCH] Unify the Socket 940 CAR configuration.
In-Reply-To: <AANLkTinmJqc9B2i0giidOsM8HpiApNDSrv1tu5eUMEwp@mail.gmail.com>
References: <1285879009-14153-1-git-send-email-wt@penguintechs.org>
	<5E26AFBED2304C099094A9F406B0D0B5@chimp>
	<AANLkTinmJqc9B2i0giidOsM8HpiApNDSrv1tu5eUMEwp@mail.gmail.com>
Message-ID: <AANLkTi=RUpuw8iZ=iHaRf505AuBqCvFCXjuV3MgPhFvW@mail.gmail.com>

On Fri, Oct 1, 2010 at 1:15 AM, Warren Turkal <wt at penguintechs.org> wrote:
> Notice that it is also changing the base of the CAR area and,


That one scares me. IIRC that's a sensitive value. Or am I wrong?

ron



From svn at coreboot.org  Fri Oct  1 17:36:39 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 17:36:39 +0200
Subject: [coreboot] build service results for r5899
Message-ID: <E1P1hf5-0006Aj-Dj@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 5899 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix some breakage from 5890.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Build Log:
Compilation of digitallogic:adl855pc has been fixed
Compilation of intel:d810e2cb has been fixed
Compilation of lanner:em8510 has been fixed
Compilation of rca:rm4100 has been fixed
Compilation of thomson:ip1000 has been fixed


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From mylesgw at gmail.com  Fri Oct  1 17:36:27 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 Oct 2010 09:36:27 -0600
Subject: [coreboot] [PATCH] Unify the Socket 940 CAR configuration.
In-Reply-To: <AANLkTi=RUpuw8iZ=iHaRf505AuBqCvFCXjuV3MgPhFvW@mail.gmail.com>
References: <1285879009-14153-1-git-send-email-wt@penguintechs.org><5E26AFBED2304C099094A9F406B0D0B5@chimp><AANLkTinmJqc9B2i0giidOsM8HpiApNDSrv1tu5eUMEwp@mail.gmail.com>
	<AANLkTi=RUpuw8iZ=iHaRf505AuBqCvFCXjuV3MgPhFvW@mail.gmail.com>
Message-ID: <0A0250B81A6A4A988EB39F2F275F8E08@chimp>

> On Fri, Oct 1, 2010 at 1:15 AM, Warren Turkal <wt at penguintechs.org> wrote:
> > Notice that it is also changing the base of the CAR area and,
>  
> That one scares me. IIRC that's a sensitive value. Or am I wrong?

I think it should be fine as long as the size of the CAR area is changed at
the same time.  The other boards that use Socket 940 already use these
settings.

That said, it's very easy to break things in CAR.

Thanks,
Myles




From peter at stuge.se  Fri Oct  1 17:53:22 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Oct 2010 17:53:22 +0200
Subject: [coreboot] [commit] r5900 - trunk/src/lib
In-Reply-To: <E1P1hSY-0002Tz-4I@ra.coresystems.de>
References: <E1P1hSY-0002Tz-4I@ra.coresystems.de>
Message-ID: <20101001155322.10007.qmail@stuge.se>

repository service wrote:
> lzma.c is already included unconditionally in the same file.
..
> -ramstage-$(CONFIG_COMPRESSED_PAYLOAD_LZMA) += lzma.c

Why include lzma.c unconditionally if the payload will not be
compressed?


//Peter



From mylesgw at gmail.com  Fri Oct  1 18:05:14 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 Oct 2010 10:05:14 -0600
Subject: [coreboot] [commit] r5900 - trunk/src/lib
In-Reply-To: <20101001155322.10007.qmail@stuge.se>
References: <E1P1hSY-0002Tz-4I@ra.coresystems.de>
	<20101001155322.10007.qmail@stuge.se>
Message-ID: <4EAFBA4EEE544374BA4CE12CC991E6F3@chimp>

> repository service wrote:
> > lzma.c is already included unconditionally in the same file.
> ..
> > -ramstage-$(CONFIG_COMPRESSED_PAYLOAD_LZMA) += lzma.c
> 
> Why include lzma.c unconditionally if the payload will not be
> compressed?

CONFIG_COMPRESSED_PAYLOAD_LZMA != CONFIG_COMPRESSED_PAYLOAD_LZMA_SUPPORTED
This config option is for adding the payload, not for all payloads.

Right now we don't have a good way to advertise lzma support in a coreboot
image.

If build coreboot with no payload (CONFIG_COMPRESSED_PAYLOAD_LZMA = n), then
add a payload with cbfstool, how does cbfstool know that you can't handle a
compressed payload?

In selfboot.c, the code assumes that lzma support is always present for that
reason.

I don't know how much difference it makes.  You'd have to modify a few
places in the code to be able to build an image without lzma support.

Thanks,
Myles




From svn at coreboot.org  Fri Oct  1 19:37:45 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 19:37:45 +0200
Subject: [coreboot] [commit] r5901 - in trunk/src/cpu/intel: model_106cx
	model_6ex model_6fx
Message-ID: <E1P1jYH-00029Q-LL@ra.coresystems.de>

Author: uwe
Date: Fri Oct  1 19:37:45 2010
New Revision: 5901
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5901

Log:
Cosmetics, whitespace and coding-style fixes for Intel CAR (trivial).

This is abuild-tested.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
   trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
   trunk/src/cpu/intel/model_6fx/cache_as_ram.inc

Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	Fri Oct  1 17:23:41 2010	(r5900)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	Fri Oct  1 19:37:45 2010	(r5901)
@@ -18,140 +18,140 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
-	/* Save the BIST result */
-	movl    %eax, %ebp
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp
 
 cache_as_ram:
 	post_code(0x20)
 
-	/* Send INIT IPI to all excluding ourself */
-        movl	$0x000C4500, %eax
-        movl	$0xFEE00300, %esi
-        movl	%eax, (%esi)
+	/* Send INIT IPI to all excluding ourself. */
+	movl	$0x000C4500, %eax
+	movl	$0xFEE00300, %esi
+	movl	%eax, (%esi)
 
-	/* Zero out all Fixed Range and Variable Range MTRRs */
+	/* Zero out all fixed range and variable range MTRRs. */
 	movl	$mtrr_table, %esi
-	movl	$( (mtrr_table_end - mtrr_table) / 2), %edi
-	xorl    %eax, %eax
-	xorl    %edx, %edx
+	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	xorl	%eax, %eax
+	xorl	%edx, %edx
 clear_mtrrs:
-	movw    (%esi), %bx
-	movzx   %bx, %ecx
+	movw	(%esi), %bx
+	movzx	%bx, %ecx
 	wrmsr
 	add	$2, %esi
 	dec	%edi
 	jnz	clear_mtrrs
 
-	/* Configure the default memory type to uncacheable */
+	/* Configure the default memory type to uncacheable. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	andl	$(~0x00000cff), %eax
 	wrmsr
 
-	/* Set cache as ram base address */
+	/* Set Cache-as-RAM base address. */
 	movl	$(MTRRphysBase_MSR(0)), %ecx
 	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
 	xorl	%edx, %edx
 	wrmsr
 
-	/* Set cache as ram mask */
+	/* Set Cache-as-RAM mask. */
 	movl	$(MTRRphysMask_MSR(0)), %ecx
-	movl	$(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
+	movl	$(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
 	xorl	%edx, %edx
 	wrmsr
 
-	/* Enable MTRR */
+	/* Enable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	orl	$(1 << 11), %eax
 	wrmsr
 
-	/* Enable L2 Cache */
+	/* Enable L2 cache. */
 	movl	$0x11e, %ecx
 	rdmsr
 	orl	$(1 << 8), %eax
 	wrmsr
 
-	/* CR0.CD = 0, CR0.NW = 0 */
+	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
         movl	%cr0, %eax
-	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	invd
 	movl	%eax, %cr0
 
-	/* Clear the cache memory reagion */
+	/* Clear the cache memory reagion. */
 	movl	$CACHE_AS_RAM_BASE, %esi
 	movl	%esi, %edi
 	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
-	//movl	$0x23322332, %eax
+	// movl	$0x23322332, %eax
 	xorl	%eax, %eax
 	rep	stosl
 
-	/* Enable Cache As RAM mode by disabling cache */
+	/* Enable Cache-as-RAM mode by disabling cache. */
 	movl	%cr0, %eax
 	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* Enable cache for our code in Flash because we do XIP here */
-        movl    $MTRRphysBase_MSR(1), %ecx
-        xorl    %edx, %edx
+	movl	$MTRRphysBase_MSR(1), %ecx
+	xorl	%edx, %edx
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
-        movl    $REAL_XIP_ROM_BASE, %eax
-        orl     $MTRR_TYPE_WRBACK, %eax
-        wrmsr
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRBACK, %eax
+	wrmsr
 
-        movl    $MTRRphysMask_MSR(1), %ecx
+	movl	$MTRRphysMask_MSR(1), %ecx
 	xorl	%edx, %edx
-        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
-        wrmsr
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-        /* enable cache */
-        movl	%cr0, %eax
-	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	movl	%eax, %cr0
 
-	/* Set up stack pointer */
+	/* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
-	/* leave some space for the struct ehci_debug_info */
+	/* Leave some space for the struct ehci_debug_info. */
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
 #endif
 	movl	%eax, %esp
 
-	/* Restore the BIST result */
+	/* Restore the BIST result. */
 	movl	%ebp, %eax
 	movl	%esp, %ebp
 	pushl	%eax
 
 	post_code(0x23)
 
-	/* Call romstage.c main function */
+	/* Call romstage.c main function. */
 	call	main
 
 	post_code(0x2f)
 
 	post_code(0x30)
 
-	/* Disable Cache */
+	/* Disable cache. */
 	movl	%cr0, %eax
-	orl    $(1 << 30), %eax
+	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
 	post_code(0x31)
 
-	/* Disable MTRR */
+	/* Disable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	andl	$(~(1 << 11)), %eax
@@ -175,40 +175,40 @@
 
 	post_code(0x33)
 
-	/* Enable Cache */
+	/* Enable cache. */
 	movl	%cr0, %eax
-	andl    $~( (1 << 30) | (1 << 29) ), %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
 	movl	%eax, %cr0
 
 	post_code(0x36)
 
-	/* Disable Cache */
+	/* Disable cache. */
 	movl	%cr0, %eax
-	orl    $(1 << 30), %eax
+	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
 	post_code(0x38)
 
-	/* Enable Write Back and Speculative Reads for the first 1MB */
+	/* Enable Write Back and Speculative Reads for the first 1MB. */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(0), %ecx
-	movl	$(~(1024*1024 -1) | (1 << 11)), %eax
+	movl	$(~(1024 * 1024 - 1) | (1 << 11)), %eax
 	xorl	%edx, %edx
 	wrmsr
 
 	post_code(0x39)
 
-	/* And Enable Cache again after setting MTRRs */
+	/* And enable cache again after setting MTRRs. */
 	movl	%cr0, %eax
-	andl    $~( (1 << 30) | (1 << 29) ), %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
 	movl	%eax, %cr0
 
 	post_code(0x3a)
 
-	/* Enable MTRR */
+	/* Enable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	orl	$(1 << 11), %eax
@@ -216,23 +216,23 @@
 
 	post_code(0x3b)
 
-	/* Invalidate the cache again */
+	/* Invalidate the cache again. */
 	invd
 
 	post_code(0x3c)
 
-	/* clear boot_complete flag */
+	/* Clear boot_complete flag. */
 	xorl	%ebp, %ebp
 __main:
 	post_code(0x11)
-	cld			/* clear direction flag */
+	cld			/* Clear direction flag. */
 
 	movl	%ebp, %esi
 
-	movl $ROMSTAGE_STACK, %esp
+	movl	$ROMSTAGE_STACK, %esp
 	movl	%esp, %ebp
-	pushl %esi
-	call copy_and_run
+	pushl	%esi
+	call	copy_and_run
 
 .Lhlt:
 	post_code(0xee)
@@ -241,14 +241,14 @@
 
 mtrr_table:
 	/* Fixed MTRRs */
-        .word 0x250, 0x258, 0x259
-        .word 0x268, 0x269, 0x26A
-        .word 0x26B, 0x26C, 0x26D
-        .word 0x26E, 0x26F
+	.word 0x250, 0x258, 0x259
+	.word 0x268, 0x269, 0x26A
+	.word 0x26B, 0x26C, 0x26D
+	.word 0x26E, 0x26F
 	/* Variable MTRRs */
-        .word 0x200, 0x201, 0x202, 0x203
-        .word 0x204, 0x205, 0x206, 0x207
-        .word 0x208, 0x209, 0x20A, 0x20B
-        .word 0x20C, 0x20D, 0x20E, 0x20F
+	.word 0x200, 0x201, 0x202, 0x203
+	.word 0x204, 0x205, 0x206, 0x207
+	.word 0x208, 0x209, 0x20A, 0x20B
+	.word 0x20C, 0x20D, 0x20E, 0x20F
 mtrr_table_end:
 

Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Fri Oct  1 17:23:41 2010	(r5900)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Fri Oct  1 19:37:45 2010	(r5901)
@@ -18,140 +18,140 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
-	/* Save the BIST result */
-	movl    %eax, %ebp
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp
 
 cache_as_ram:
 	post_code(0x20)
 
-	/* Send INIT IPI to all excluding ourself */
-        movl	$0x000C4500, %eax
-        movl	$0xFEE00300, %esi
-        movl	%eax, (%esi)
+	/* Send INIT IPI to all excluding ourself. */
+	movl	$0x000C4500, %eax
+	movl	$0xFEE00300, %esi
+	movl	%eax, (%esi)
 
-	/* Zero out all Fixed Range and Variable Range MTRRs */
+	/* Zero out all fixed range and variable range MTRRs. */
 	movl	$mtrr_table, %esi
-	movl	$( (mtrr_table_end - mtrr_table) / 2), %edi
-	xorl    %eax, %eax
-	xorl    %edx, %edx
+	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	xorl	%eax, %eax
+	xorl	%edx, %edx
 clear_mtrrs:
-	movw    (%esi), %bx
-	movzx   %bx, %ecx
+	movw	(%esi), %bx
+	movzx	%bx, %ecx
 	wrmsr
 	add	$2, %esi
 	dec	%edi
 	jnz	clear_mtrrs
 
-	/* Configure the default memory type to uncacheable */
+	/* Configure the default memory type to uncacheable. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	andl	$(~0x00000cff), %eax
 	wrmsr
 
-	/* Set cache as ram base address */
+	/* Set Cache-as-RAM base address. */
 	movl	$(MTRRphysBase_MSR(0)), %ecx
 	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
 	xorl	%edx, %edx
 	wrmsr
 
-	/* Set cache as ram mask */
+	/* Set Cache-as-RAM mask. */
 	movl	$(MTRRphysMask_MSR(0)), %ecx
-	movl	$(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
+	movl	$(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
 	movl	$0x0000000f, %edx
 	wrmsr
 
-	/* Enable MTRR */
+	/* Enable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	orl	$(1 << 11), %eax
 	wrmsr
 
-	/* Enable L2 Cache */
+	/* Enable L2 cache. */
 	movl	$0x11e, %ecx
 	rdmsr
 	orl	$(1 << 8), %eax
 	wrmsr
 
-	/* CR0.CD = 0, CR0.NW = 0 */
+	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
         movl	%cr0, %eax
-	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	invd
 	movl	%eax, %cr0
 
-	/* Clear the cache memory reagion */
+	/* Clear the cache memory reagion. */
 	movl	$CACHE_AS_RAM_BASE, %esi
 	movl	%esi, %edi
 	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
-	//movl	$0x23322332, %eax
+	// movl	$0x23322332, %eax
 	xorl	%eax, %eax
 	rep	stosl
 
-	/* Enable Cache As RAM mode by disabling cache */
+	/* Enable Cache-as-RAM mode by disabling cache. */
 	movl	%cr0, %eax
 	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* Enable cache for our code in Flash because we do XIP here */
-        movl    $MTRRphysBase_MSR(1), %ecx
-        xorl    %edx, %edx
+	movl	$MTRRphysBase_MSR(1), %ecx
+	xorl	%edx, %edx
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
-        movl    $REAL_XIP_ROM_BASE, %eax
-        orl     $MTRR_TYPE_WRBACK, %eax
-        wrmsr
-
-        movl    $MTRRphysMask_MSR(1), %ecx
-        movl    $0x0000000f, %edx
-        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
-        wrmsr
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRBACK, %eax
+	wrmsr
+
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$0x0000000f, %edx
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-        /* enable cache */
-        movl	%cr0, %eax
-	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	movl	%eax, %cr0
 
-	/* Set up stack pointer */
+	/* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
-	/* leave some space for the struct ehci_debug_info */
+	/* Leave some space for the struct ehci_debug_info. */
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
 #endif
 	movl	%eax, %esp
 
-	/* Restore the BIST result */
+	/* Restore the BIST result. */
 	movl	%ebp, %eax
 	movl	%esp, %ebp
 	pushl	%eax
 
 	post_code(0x23)
 
-	/* Call romstage.c main function */
+	/* Call romstage.c main function. */
 	call	main
 
 	post_code(0x2f)
 
 	post_code(0x30)
 
-	/* Disable Cache */
+	/* Disable cache. */
 	movl	%cr0, %eax
-	orl    $(1 << 30), %eax
+	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
 	post_code(0x31)
 
-	/* Disable MTRR */
+	/* Disable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	andl	$(~(1 << 11)), %eax
@@ -175,41 +175,40 @@
 
 	post_code(0x33)
 
-	/* Enable Cache */
+	/* Enable cache. */
 	movl	%cr0, %eax
-	andl    $~( (1 << 30) | (1 << 29) ), %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
 	movl	%eax, %cr0
 
-
 	post_code(0x36)
 
-	/* Disable Cache */
+	/* Disable cache. */
 	movl	%cr0, %eax
-	orl    $(1 << 30), %eax
+	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
 	post_code(0x38)
 
-	/* Enable Write Back and Speculative Reads for the first 1MB */
+	/* Enable Write Back and Speculative Reads for the first 1MB. */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(0), %ecx
-	movl	$(~(1024*1024 -1) | (1 << 11)), %eax
+	movl	$(~(1024 * 1024 - 1) | (1 << 11)), %eax
 	movl	$0x0000000f, %edx	// 36bit address space
 	wrmsr
 
 	post_code(0x39)
 
-	/* And Enable Cache again after setting MTRRs */
+	/* And enable cache again after setting MTRRs. */
 	movl	%cr0, %eax
-	andl    $~( (1 << 30) | (1 << 29) ), %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
 	movl	%eax, %cr0
 
 	post_code(0x3a)
 
-	/* Enable MTRR */
+	/* Enable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	orl	$(1 << 11), %eax
@@ -217,23 +216,23 @@
 
 	post_code(0x3b)
 
-	/* Invalidate the cache again */
+	/* Invalidate the cache again. */
 	invd
 
 	post_code(0x3c)
 
-	/* clear boot_complete flag */
+	/* Clear boot_complete flag. */
 	xorl	%ebp, %ebp
 __main:
 	post_code(0x11)
-	cld			/* clear direction flag */
+	cld			/* Clear direction flag. */
 
 	movl	%ebp, %esi
 
-	movl $ROMSTAGE_STACK, %esp
+	movl	$ROMSTAGE_STACK, %esp
 	movl	%esp, %ebp
-	pushl %esi
-	call copy_and_run
+	pushl	%esi
+	call	copy_and_run
 
 .Lhlt:
 	post_code(0xee)
@@ -242,14 +241,14 @@
 
 mtrr_table:
 	/* Fixed MTRRs */
-        .word 0x250, 0x258, 0x259
-        .word 0x268, 0x269, 0x26A
-        .word 0x26B, 0x26C, 0x26D
-        .word 0x26E, 0x26F
+	.word 0x250, 0x258, 0x259
+	.word 0x268, 0x269, 0x26A
+	.word 0x26B, 0x26C, 0x26D
+	.word 0x26E, 0x26F
 	/* Variable MTRRs */
-        .word 0x200, 0x201, 0x202, 0x203
-        .word 0x204, 0x205, 0x206, 0x207
-        .word 0x208, 0x209, 0x20A, 0x20B
-        .word 0x20C, 0x20D, 0x20E, 0x20F
+	.word 0x200, 0x201, 0x202, 0x203
+	.word 0x204, 0x205, 0x206, 0x207
+	.word 0x208, 0x209, 0x20A, 0x20B
+	.word 0x20C, 0x20D, 0x20E, 0x20F
 mtrr_table_end:
 

Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	Fri Oct  1 17:23:41 2010	(r5900)
+++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	Fri Oct  1 19:37:45 2010	(r5901)
@@ -18,22 +18,22 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
-	/* Save the BIST result */
-	movl    %eax, %ebp
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp
 
 cache_as_ram:
 	post_code(0x20)
 
-	/* Send INIT IPI to all excluding ourself */
-        movl	$0x000C4500, %eax
-        movl	$0xFEE00300, %esi
-        movl	%eax, (%esi)
+	/* Send INIT IPI to all excluding ourself. */
+	movl	$0x000C4500, %eax
+	movl	$0xFEE00300, %esi
+	movl	%eax, (%esi)
 
 	/* Disable prefetchers */
 	movl	$0x01a0, %ecx
@@ -42,123 +42,123 @@
 	orl	$((1 << 5) | (1 << 7)), %edx
 	wrmsr
 
-	/* Zero out all Fixed Range and Variable Range MTRRs */
+	/* Zero out all fixed range and variable range MTRRs. */
 	movl	$mtrr_table, %esi
-	movl	$( (mtrr_table_end - mtrr_table) / 2), %edi
-	xorl    %eax, %eax
-	xorl    %edx, %edx
+	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	xorl	%eax, %eax
+	xorl	%edx, %edx
 clear_mtrrs:
-	movw    (%esi), %bx
-	movzx   %bx, %ecx
+	movw	(%esi), %bx
+	movzx	%bx, %ecx
 	wrmsr
 	add	$2, %esi
 	dec	%edi
 	jnz	clear_mtrrs
 
-	/* Configure the default memory type to uncacheable */
+	/* Configure the default memory type to uncacheable. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	andl	$(~0x00000cff), %eax
 	wrmsr
 
-	/* Set cache as ram base address */
+	/* Set Cache-as-RAM base address. */
 	movl	$(MTRRphysBase_MSR(0)), %ecx
 	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
 	xorl	%edx, %edx
 	wrmsr
 
-	/* Set cache as ram mask */
+	/* Set Cache-as-RAM mask. */
 	movl	$(MTRRphysMask_MSR(0)), %ecx
-	movl	$(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
+	movl	$(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
 	movl	$0x0000000f, %edx
 	wrmsr
 
-	/* Enable MTRR */
+	/* Enable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	orl	$(1 << 11), %eax
 	wrmsr
 
-	/* Enable L2 Cache */
+	/* Enable L2 cache. */
 	movl	$0x11e, %ecx
 	rdmsr
 	orl	$(1 << 8), %eax
 	wrmsr
 
-	/* CR0.CD = 0, CR0.NW = 0 */
+	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
         movl	%cr0, %eax
-	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	invd
 	movl	%eax, %cr0
 
-	/* Clear the cache memory reagion */
+	/* Clear the cache memory reagion. */
 	movl	$CACHE_AS_RAM_BASE, %esi
 	movl	%esi, %edi
 	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
-	//movl	$0x23322332, %eax
+	// movl	$0x23322332, %eax
 	xorl	%eax, %eax
 	rep	stosl
 
-	/* Enable Cache As RAM mode by disabling cache */
+	/* Enable Cache-as-RAM mode by disabling cache. */
 	movl	%cr0, %eax
 	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* Enable cache for our code in Flash because we do XIP here */
-        movl    $MTRRphysBase_MSR(1), %ecx
-        xorl    %edx, %edx
+	movl	$MTRRphysBase_MSR(1), %ecx
+	xorl	%edx, %edx
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
-        movl    $REAL_XIP_ROM_BASE, %eax
-        orl     $MTRR_TYPE_WRBACK, %eax
-        wrmsr
-
-        movl    $MTRRphysMask_MSR(1), %ecx
-        movl    $0x0000000f, %edx
-        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
-        wrmsr
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRBACK, %eax
+	wrmsr
+
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$0x0000000f, %edx
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-        /* enable cache */
-        movl	%cr0, %eax
-	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
 	movl	%eax, %cr0
 
-	/* Set up stack pointer */
+	/* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
-	/* leave some space for the struct ehci_debug_info */
+	/* Leave some space for the struct ehci_debug_info. */
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
 #endif
 	movl	%eax, %esp
 
-	/* Restore the BIST result */
+	/* Restore the BIST result. */
 	movl	%ebp, %eax
 	movl	%esp, %ebp
 	pushl	%eax
 
 	post_code(0x23)
 
-	/* Call romstage.c main function */
+	/* Call romstage.c main function. */
 	call	main
 
 	post_code(0x2f)
 
 	post_code(0x30)
 
-	/* Disable Cache */
+	/* Disable cache. */
 	movl	%cr0, %eax
-	orl    $(1 << 30), %eax
+	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
 	post_code(0x31)
 
-	/* Disable MTRR */
+	/* Disable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	andl	$(~(1 << 11)), %eax
@@ -182,40 +182,40 @@
 
 	post_code(0x33)
 
-	/* Enable Cache */
+	/* Enable cache. */
 	movl	%cr0, %eax
-	andl    $~( (1 << 30) | (1 << 29) ), %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
 	movl	%eax, %cr0
 
 	post_code(0x36)
 
-	/* Disable Cache */
+	/* Disable cache. */
 	movl	%cr0, %eax
-	orl    $(1 << 30), %eax
+	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
 	post_code(0x38)
 
-	/* Enable Write Back and Speculative Reads for the first 1MB */
+	/* Enable Write Back and Speculative Reads for the first 1MB. */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(0), %ecx
-	movl	$(~(1024*1024 -1) | (1 << 11)), %eax
+	movl	$(~(1024 * 1024 - 1) | (1 << 11)), %eax
 	movl	$0x0000000f, %edx	// 36bit address space
 	wrmsr
 
 	post_code(0x39)
 
-	/* And Enable Cache again after setting MTRRs */
+	/* And enable cache again after setting MTRRs. */
 	movl	%cr0, %eax
-	andl    $~( (1 << 30) | (1 << 29) ), %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
 	movl	%eax, %cr0
 
 	post_code(0x3a)
 
-	/* Enable MTRR */
+	/* Enable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
 	orl	$(1 << 11), %eax
@@ -230,23 +230,23 @@
 	andl	$~((1 << 5) | (1 << 7)), %edx
 	wrmsr
 
-	/* Invalidate the cache again */
+	/* Invalidate the cache again. */
 	invd
 
 	post_code(0x3c)
 
-	/* clear boot_complete flag */
+	/* Clear boot_complete flag. */
 	xorl	%ebp, %ebp
 __main:
 	post_code(0x11)
-	cld			/* clear direction flag */
+	cld			/* Clear direction flag. */
 
 	movl	%ebp, %esi
 
-	movl $ROMSTAGE_STACK, %esp
+	movl	$ROMSTAGE_STACK, %esp
 	movl	%esp, %ebp
-	pushl %esi
-	call copy_and_run
+	pushl	%esi
+	call	copy_and_run
 
 .Lhlt:
 	post_code(0xee)
@@ -255,14 +255,14 @@
 
 mtrr_table:
 	/* Fixed MTRRs */
-        .word 0x250, 0x258, 0x259
-        .word 0x268, 0x269, 0x26A
-        .word 0x26B, 0x26C, 0x26D
-        .word 0x26E, 0x26F
+	.word 0x250, 0x258, 0x259
+	.word 0x268, 0x269, 0x26A
+	.word 0x26B, 0x26C, 0x26D
+	.word 0x26E, 0x26F
 	/* Variable MTRRs */
-        .word 0x200, 0x201, 0x202, 0x203
-        .word 0x204, 0x205, 0x206, 0x207
-        .word 0x208, 0x209, 0x20A, 0x20B
-        .word 0x20C, 0x20D, 0x20E, 0x20F
+	.word 0x200, 0x201, 0x202, 0x203
+	.word 0x204, 0x205, 0x206, 0x207
+	.word 0x208, 0x209, 0x20A, 0x20B
+	.word 0x20C, 0x20D, 0x20E, 0x20F
 mtrr_table_end:
 



From mylesgw at gmail.com  Fri Oct  1 19:55:49 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 Oct 2010 11:55:49 -0600
Subject: [coreboot] [commit] r5901 - in trunk/src/cpu/intel:
	model_106cxmodel_6ex model_6fx
In-Reply-To: <E1P1jYH-00029Q-LL@ra.coresystems.de>
References: <E1P1jYH-00029Q-LL@ra.coresystems.de>
Message-ID: <30767EF4E6AA40BB931F442DC639F014@chimp>

> Modified:
>    trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
>    trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
>    trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
It looks like src/cpu/intel/car/cache_as_ram.inc could use the same love.

I'd be interested to see how much uglier it made these files to combine
them.  There's very little difference between the 6ex & 6fx code.

Thanks,
Myles




From mylesgw at gmail.com  Fri Oct  1 20:01:59 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 Oct 2010 12:01:59 -0600
Subject: [coreboot] [Patch] Quieter build
Message-ID: <AANLkTimQN-ThBWxM=Jps7fm11KV3jfVeKzB=vHP_FL-i@mail.gmail.com>

I'd like to redirect the output of iasl to a file.  Patch attached.

Here's a little justification:
http://qa.coreboot.org/log_buildbrd.php?revision=5900&device=serengeti_cheetah&vendor=amd&num=2

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
-------------- next part --------------
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From peter at stuge.se  Fri Oct  1 21:32:46 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Oct 2010 21:32:46 +0200
Subject: [coreboot] [commit] r5900 - trunk/src/lib
In-Reply-To: <4EAFBA4EEE544374BA4CE12CC991E6F3@chimp>
References: <E1P1hSY-0002Tz-4I@ra.coresystems.de>
	<20101001155322.10007.qmail@stuge.se>
	<4EAFBA4EEE544374BA4CE12CC991E6F3@chimp>
Message-ID: <20101001193247.6695.qmail@stuge.se>

Myles Watson wrote:
> > > lzma.c is already included unconditionally in the same file.
> > 
> > Why include lzma.c unconditionally if the payload will not be
> > compressed?
..
> If build coreboot with no payload (CONFIG_COMPRESSED_PAYLOAD_LZMA = n),
> then add a payload with cbfstool, how does cbfstool know that you can't
> handle a compressed payload?

Good point. Thanks!


//Peter



From mylesgw at gmail.com  Fri Oct  1 21:37:13 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 Oct 2010 13:37:13 -0600
Subject: [coreboot] [commit] r5900 - trunk/src/lib
In-Reply-To: <20101001193247.6695.qmail@stuge.se>
References: <E1P1hSY-0002Tz-4I@ra.coresystems.de><20101001155322.10007.qmail@stuge.se><4EAFBA4EEE544374BA4CE12CC991E6F3@chimp>
	<20101001193247.6695.qmail@stuge.se>
Message-ID: <FB59292F73A342AEA4049594829BDAB2@chimp>



> Myles Watson wrote:
> > > > lzma.c is already included unconditionally in the same file.
> > >
> > > Why include lzma.c unconditionally if the payload will not be
> > > compressed?
> ..
> > If build coreboot with no payload (CONFIG_COMPRESSED_PAYLOAD_LZMA = n),
> > then add a payload with cbfstool, how does cbfstool know that you can't
> > handle a compressed payload?
> 
> Good point. Thanks!

You're welcome.  It was a good question.  Sorry about the grammar of the
response :)  "If you build coreboot ..."

Thanks,
Myles




From peter at stuge.se  Fri Oct  1 21:46:10 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Oct 2010 21:46:10 +0200
Subject: [coreboot] [PATCH] Enable or disable the power button in Kconfig
Message-ID: <20101001194610.8333.qmail@stuge.se>

Please see the attached patch. I would like to especially ask those
who have worked on boards which use the 5536 to check if maybe their
board should select a different POWER_BUTTON_* now. Again, existing
behavior should be unchanged from previous except on ALIX.1.

Jens, please confirm if my understanding of the old vs. new
hurricane-lx board version vs. power button behavior is correct.


Thanks!

//Peter
-------------- next part --------------
Enable or disable the power button in Kconfig

Some mainboards need to disable the power button to avoid turning off
shortly after being turned on. Other boards ship with a jumper over
the power button and should allow the user to configure the behavior.

The patch adds infrastructure in the form of four mutually exclusive
options which can be selected in a mainboard Kconfig (power button
forced on/off, and user-controllable with default on/off) and one
result bool which source code can test. (Enable the button or not.)

The options have been implemented in CS5536 code and all mainboards
which select SOUTHBRIDGE_AMD_CS5536, but should be used also by other
chipsets where applicable. Note that if chipset code uses the result
bool ENABLE_POWER_BUTTON, then every board using that chipset must
select one out of the four control options.

All touched boards should have unchanged behavior, except ALIX.1[CD]
where the power button can now be configured by the user.

Build tested for alix1c, alix2d, hurricane-lx and wyse-s50. Confirmed
to work as advertised on alix1c both with button enabled and disabled.

Signed-off-by: Peter Stuge <peter at stuge.se>

Index: src/southbridge/amd/cs5536/cs5536_early_setup.c
===================================================================
--- src/southbridge/amd/cs5536/cs5536_early_setup.c	(revision 5901)
+++ src/southbridge/amd/cs5536/cs5536_early_setup.c	(working copy)
@@ -92,8 +92,9 @@
 
 static void cs5536_setup_power_button(void)
 {
-	/*      Power Button Setup */
+#if CONFIG_ENABLE_POWER_BUTTON
 	outl(0x40020000, PMS_IO_BASE + 0x40);
+#endif
 
 	/* setup WORK_AUX/GPIO24, it is the external signal for 5536
 	 * vsb_work_aux controls all voltage rails except Vstandby & Vmem.
Index: src/Kconfig
===================================================================
--- src/Kconfig	(revision 5901)
+++ src/Kconfig	(working copy)
@@ -732,4 +732,43 @@
 	hex
 	default 0x10
 
+# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
+# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISBALE options are
+# mutually exclusive. One of these options must be selected in the
+# mainboard Kconfig if the chipset supports enabling and disabling of
+# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
+# in mainboard/Kconfig to know if the button should be enabled or not.
+
+config POWER_BUTTON_DEFAULT_ENABLE
+	def_bool n
+	help
+	  Select when the board has a power button which can optionally be
+	  disabled by the user.
+
+config POWER_BUTTON_DEFAULT_DISABLE
+	def_bool n
+	help
+	  Select when the board has a power button which can optionally be
+	  enabled by the user, e.g. when the board ships with a jumper over
+	  the power switch contacts.
+
+config POWER_BUTTON_FORCE_ENABLE
+	def_bool n
+	help
+	  Select when the board requires that the power button is always
+	  enabled.
+
+config POWER_BUTTON_FORCE_DISABLE
+	def_bool n
+	help
+	  Select when the board requires that the power button is always
+	  disabled, e.g. when it has been hardwired to ground.
+
+config POWER_BUTTON_IS_OPTIONAL
+	bool
+	default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
+	default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
+	help
+	  Internal option that controls ENABLE_POWER_BUTTON visibility.
+
 source src/Kconfig.deprecated_options
Index: src/mainboard/Kconfig
===================================================================
--- src/mainboard/Kconfig	(revision 5901)
+++ src/mainboard/Kconfig	(working copy)
@@ -247,4 +247,22 @@
 	default 0x200000 if COREBOOT_ROMSIZE_KB_2048
 	default 0x400000 if COREBOOT_ROMSIZE_KB_4096
 
+config ENABLE_POWER_BUTTON
+	bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL
+	default y if POWER_BUTTON_DEFAULT_ENABLE
+	default n if POWER_BUTTON_DEFAULT_DISABLE
+	help
+	  The selected mainboard can have the power button semi-permanently
+	  connected to ground (typically with a jumper) so that the button
+	  appears to be constantly depressed. If this option is enabled on
+	  a board with the jumper connected then the board will turn on, but
+	  automatically turn off after a short timeout, usually 4 seconds.
+
+	  Select Y here if you have removed the jumper and want to use an
+	  actual power button with this board.
+
+config ENABLE_POWER_BUTTON
+	def_bool y if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_ENABLE
+	def_bool n if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_DISABLE
+
 endmenu
Index: src/mainboard/wyse/s50/Kconfig
===================================================================
--- src/mainboard/wyse/s50/Kconfig	(revision 5901)
+++ src/mainboard/wyse/s50/Kconfig	(working copy)
@@ -28,6 +28,7 @@
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select BOARD_ROMSIZE_KB_256
+	select POWER_BUTTON_FORCE_DISABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/wyse/s50/romstage.c
===================================================================
--- src/mainboard/wyse/s50/romstage.c	(revision 5901)
+++ src/mainboard/wyse/s50/romstage.c	(working copy)
@@ -134,9 +134,6 @@
 
 	cs5536_early_setup();
 	
-	/* disable the power button */
-	outl(0x00, PMS_IO_BASE + 0x40);
-
 	/* cs5536_disable_internal_uart	 disable them. Set them up now... */
 	cs5536_setup_onchipuart(1);
 
Index: src/mainboard/digitallogic/msm800sev/Kconfig
===================================================================
--- src/mainboard/digitallogic/msm800sev/Kconfig	(revision 5901)
+++ src/mainboard/digitallogic/msm800sev/Kconfig	(working copy)
@@ -11,6 +11,7 @@
 	select PIRQ_ROUTE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/traverse/geos/Kconfig
===================================================================
--- src/mainboard/traverse/geos/Kconfig	(revision 5901)
+++ src/mainboard/traverse/geos/Kconfig	(working copy)
@@ -10,6 +10,7 @@
 	select PIRQ_ROUTE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_1024
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/amd/rumba/Kconfig
===================================================================
--- src/mainboard/amd/rumba/Kconfig	(revision 5901)
+++ src/mainboard/amd/rumba/Kconfig	(working copy)
@@ -27,6 +27,7 @@
 	select UDELAY_TSC
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/amd/norwich/Kconfig
===================================================================
--- src/mainboard/amd/norwich/Kconfig	(revision 5901)
+++ src/mainboard/amd/norwich/Kconfig	(working copy)
@@ -10,6 +10,7 @@
 	select PIRQ_ROUTE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/amd/db800/Kconfig
===================================================================
--- src/mainboard/amd/db800/Kconfig	(revision 5901)
+++ src/mainboard/amd/db800/Kconfig	(working copy)
@@ -11,6 +11,7 @@
 	select PIRQ_ROUTE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/iei/pcisa-lx-800-r10/Kconfig
===================================================================
--- src/mainboard/iei/pcisa-lx-800-r10/Kconfig	(revision 5901)
+++ src/mainboard/iei/pcisa-lx-800-r10/Kconfig	(working copy)
@@ -10,6 +10,7 @@
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select BOARD_ROMSIZE_KB_256
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/artecgroup/dbe61/Kconfig
===================================================================
--- src/mainboard/artecgroup/dbe61/Kconfig	(revision 5901)
+++ src/mainboard/artecgroup/dbe61/Kconfig	(working copy)
@@ -10,6 +10,7 @@
 	select PIRQ_ROUTE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/pcengines/alix1c/Kconfig
===================================================================
--- src/mainboard/pcengines/alix1c/Kconfig	(revision 5901)
+++ src/mainboard/pcengines/alix1c/Kconfig	(working copy)
@@ -11,6 +11,7 @@
 	select PIRQ_ROUTE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
+	select POWER_BUTTON_DEFAULT_DISABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/pcengines/alix2d/Kconfig
===================================================================
--- src/mainboard/pcengines/alix2d/Kconfig	(revision 5901)
+++ src/mainboard/pcengines/alix2d/Kconfig	(working copy)
@@ -10,6 +10,7 @@
 	select PIRQ_ROUTE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
+	select POWER_BUTTON_FORCE_DISABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/pcengines/alix2d/romstage.c
===================================================================
--- src/mainboard/pcengines/alix2d/romstage.c	(revision 5901)
+++ src/mainboard/pcengines/alix2d/romstage.c	(working copy)
@@ -120,12 +120,6 @@
 static void mb_gpio_init(void)
 {
 	/*
-	 * Disable power button, since it is hardwired to ground on this board,
-	 * and the power would be cut off atfer a 4-second delay otherwise.
-	 */
-	outl(0x00020000, PMS_IO_BASE + 0x40);
-
-	/*
 	 * Enable LEDs GPIO outputs to light up the leds
 	 * This is how the original tinyBIOS sets them after boot.
 	 * Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it
Index: src/mainboard/lippert/roadrunner-lx/Kconfig
===================================================================
--- src/mainboard/lippert/roadrunner-lx/Kconfig	(revision 5901)
+++ src/mainboard/lippert/roadrunner-lx/Kconfig	(working copy)
@@ -13,6 +13,7 @@
 	# Standard chip is a 512 KB FWH. Replacing it with a 1 MB
 	# SST 49LF008A is possible.
 	select BOARD_ROMSIZE_KB_512
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/lippert/hurricane-lx/Kconfig
===================================================================
--- src/mainboard/lippert/hurricane-lx/Kconfig	(revision 5901)
+++ src/mainboard/lippert/hurricane-lx/Kconfig	(working copy)
@@ -29,11 +29,19 @@
 config BOARD_OLD_REVISION
 	bool "Board is old pre-3.0 revision"
 	default n
+	select POWER_BUTTON_FORCE_DISABLE
 	help
 	  Look on the bottom side for a number like 406-0001-30.  The last 2
 	  digits state the PCB revision (3.0 in this example).  For 2.0 or older
 	  boards choose Y, for 3.0 and newer say N.
 
+	  Old revision boards need a jumper shorting the power button to
+	  power on automatically. So we must disable the button's fail-safe
+	  function, or the board will shut down after 4 s.
+
+config POWER_BUTTON_FORCE_ENABLE
+	def_bool y if !BOARD_OLD_REVISION
+
 config ONBOARD_UARTS_RS485
 	bool "Switch on-board serial ports to RS485"
 	default n
Index: src/mainboard/lippert/hurricane-lx/romstage.c
===================================================================
--- src/mainboard/lippert/hurricane-lx/romstage.c	(revision 5901)
+++ src/mainboard/lippert/hurricane-lx/romstage.c	(working copy)
@@ -148,14 +148,7 @@
 
 	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
-#if CONFIG_BOARD_OLD_REVISION
-	/*
-	 * Old revision boards need a jumper shorting the power button to power
-	 * on automatically. So we must disable the button's fail-safe function,
-	 * or the board will shut down after 4 s.
-	 */
-	outl(0, PMS_IO_BASE + PM_FSD); // Fail-Save Delay register
-#else
+#if !CONFIG_BOARD_OLD_REVISION
 	int err;
 	/* bit0 = Spread Spectrum */
 	if ((err = smc_send_config(SMC_CONFIG))) {
Index: src/mainboard/lippert/spacerunner-lx/Kconfig
===================================================================
--- src/mainboard/lippert/spacerunner-lx/Kconfig	(revision 5901)
+++ src/mainboard/lippert/spacerunner-lx/Kconfig	(working copy)
@@ -14,6 +14,7 @@
 	# Board is equipped with a 1 MB SPI flash, however, due to limitations
 	# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
 	select BOARD_ROMSIZE_KB_512
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/lippert/literunner-lx/Kconfig
===================================================================
--- src/mainboard/lippert/literunner-lx/Kconfig	(revision 5901)
+++ src/mainboard/lippert/literunner-lx/Kconfig	(working copy)
@@ -14,6 +14,7 @@
 	# Board is equipped with a 1 MB SPI flash, however, due to limitations
 	# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
 	select BOARD_ROMSIZE_KB_512
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string
Index: src/mainboard/winent/pl6064/Kconfig
===================================================================
--- src/mainboard/winent/pl6064/Kconfig	(revision 5901)
+++ src/mainboard/winent/pl6064/Kconfig	(working copy)
@@ -11,6 +11,7 @@
 	select PIRQ_ROUTE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
+	select POWER_BUTTON_FORCE_ENABLE
 
 config MAINBOARD_DIR
 	string

From rminnich at gmail.com  Fri Oct  1 22:52:57 2010
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Oct 2010 13:52:57 -0700
Subject: [coreboot] BBC EFI story
Message-ID: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>

This story is full of errors. I thought I'd point out a few.

"New PCs could start in just seconds, thanks to an update to one of
the oldest parts of desktop computers."

I've got news for the UEFI forum: OLD computers, starting 10 years
ago, have been starting in seconds, thanks to the coreboot project. We
first showed a 12 second boot at the Atlanta Linux Symposium in Oct.
2000. It is hardly news that one can boot a computer quickly. The
project then was called LinuxBIOS; the project today is called
Coreboot. Coreboot works on embedded systems, desktops, laptops, and
supercomputers. It has run in the iRobot packbot for 10 years,
searching mines and saving lives. Some of the biggest supercomputers
in the world have run coreboot. Work on coreboot was, in fact, funded
first by the US Gov't (Dept. of Energy) and more recently by the
German Government (see, for example,
http://www.coreboot.org/pipermail/coreboot-announce/2010-May/000007.html)

So why, might you ask, did vendors not pick this technology up 10
years ago? Technology that worked on x86, 64-bit x86, Power PC, and
DEC Alpha? The reason is simple: it's open source. And, while vendors
finally did decide that an open source operating system might be
acceptable, they have had a lot of trouble accepting an open source
BIOS. They feel that too much information is divulged if the BIOS is
open source. They make a lot of excuses, but in the end, they finally
admit that the issue is that they don't want the hardware to be that
open.

"The upgrade will spell the end for the 25-year-old PC start-up
software known as Bios that initialises a machine so its operating
system can get going."

The BIOS could have been ended ten years ago, but for a simple fact:
many customers don't much like EFI. It's clumsy, slow, and closed. And
it's hard to work around, as it is designed to hide information.

"The code was not intended to live nearly this long, and adapting it
to modern PCs is one reason they take as long as they do to warm up."

There's a lot more to it than that. The closed nature of the BIOS
software made it very hard to replace. And, again, the vendors have
shown time and again that they prefer a closed, proprietary solution
to an open source solution. That's the real problem.

"Alternatives to UEFI, such as Open Firmware and Coreboot, do exist
and are typically used on computers that do not run chips based on
Intel's x86 architecture."

This statement is completely wrong. Coreboot has run on x86 systems
from the start and, in fact, only runs on x86 systems now. Open
Firmware also runs on x86 systems and is in fact the BIOS for the One
Laptop Per Child project -- an x86 system.

""At the moment it can be 25-30 seconds of boot time before you see
the first bit of OS sign-on," he said. "With UEFI we're getting it
under a handful of seconds.""

It's nice to see UEFI catching up only 10 years later; the first
versions took 10 minutes to boot. Automobile computers, using ARM
processors, and an open source BIOS called U-boot, boot Linux in 8/10
of a second. So, while UEFI is where coreboot was ten years ago, we've
all moved on; seconds is kind of slow nowadays.

"He said that 2011 would be the year that sales of UEFI machines start
to dominate."

Dominate what? Certainly not cell phones. Certainly not the ipad. In
fact, UEFI is going to dominate a segment that matters less and less
nowadays -- PC-compatible desktops and laptops.

I think you can do better than this article; the BBC is one of the
finest news organizations in the world. It seems you took a puff-piece
from the UEFI group and removed the quotes. I'm very disappointed in
the BBC.

Thanks
Ron Minnich
Founder, LinuxBIOS, which is now coreboot.



From footplus at gmail.com  Fri Oct  1 23:03:40 2010
From: footplus at gmail.com (=?UTF-8?B?QXVyw6lsaWVu?=)
Date: Fri, 1 Oct 2010 23:03:40 +0200
Subject: [coreboot] [PATCH] Enable or disable the power button in Kconfig
In-Reply-To: <20101001194610.8333.qmail@stuge.se>
References: <20101001194610.8333.qmail@stuge.se>
Message-ID: <AANLkTikh=_2o3MSv4bS5CJm2R5VGATdL-Vi1AUz9FRnY@mail.gmail.com>

On Fri, Oct 1, 2010 at 9:46 PM, Peter Stuge <peter at stuge.se> wrote:

> Please see the attached patch. I would like to especially ask those
> who have worked on boards which use the 5536 to check if maybe their
> board should select a different POWER_BUTTON_* now. Again, existing
> behavior should be unchanged from previous except on ALIX.1.
>
>
Hi Peter,

I just run-tested this version, with power button disabled, on ALIX.1d, and
with the power jumper present on the board (factory default). It works
perfectly.

Thanks for this patch :)

Acked-by: Aurelien Guillaume <aurelien at iwi.me>

Best regards,
-- 
Aur?lien Guillaume, aka. f00ty
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From uwe at hermann-uwe.de  Fri Oct  1 23:27:59 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 1 Oct 2010 23:27:59 +0200
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
Message-ID: <20101001212759.GV3256@greenwood>

See patch.

abuilt-tested.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
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From uwe at hermann-uwe.de  Fri Oct  1 23:31:21 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 1 Oct 2010 23:31:21 +0200
Subject: [coreboot] [commit] r5901 - in trunk/src/cpu/intel:
 model_106cxmodel_6ex model_6fx
In-Reply-To: <30767EF4E6AA40BB931F442DC639F014@chimp>
References: <E1P1jYH-00029Q-LL@ra.coresystems.de>
	<30767EF4E6AA40BB931F442DC639F014@chimp>
Message-ID: <20101001213121.GW3256@greenwood>

On Fri, Oct 01, 2010 at 11:55:49AM -0600, Myles Watson wrote:
> > Modified:
> >    trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
> >    trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
> >    trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
> It looks like src/cpu/intel/car/cache_as_ram.inc could use the same love.

Hm, I think I already cleaned up that one.

 
> I'd be interested to see how much uglier it made these files to combine
> them.  There's very little difference between the 6ex & 6fx code.

Indeed, I'll post a patch to unify 6ex, 6fx, and 106cx at the very
least, their differences are minimal.

The other ones are a bit different, but I'll post a few more patches to
factor out common stuff and further simplify the code, which might
allow us to factor out more generic code maybe, we'll see.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From uwe at hermann-uwe.de  Fri Oct  1 23:35:47 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 1 Oct 2010 23:35:47 +0200
Subject: [coreboot] [Patch] Quieter build
In-Reply-To: <AANLkTimQN-ThBWxM=Jps7fm11KV3jfVeKzB=vHP_FL-i@mail.gmail.com>
References: <AANLkTimQN-ThBWxM=Jps7fm11KV3jfVeKzB=vHP_FL-i@mail.gmail.com>
Message-ID: <20101001213546.GX3256@greenwood>

On Fri, Oct 01, 2010 at 12:01:59PM -0600, Myles Watson wrote:
> I'd like to redirect the output of iasl to a file.  Patch attached.
> 
> Here's a little justification:
> http://qa.coreboot.org/log_buildbrd.php?revision=5900&device=serengeti_cheetah&vendor=amd&num=2
> 
> Signed-off-by: Myles Watson <mylesgw at gmail.com>

Yep, makes sense.

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From peter at stuge.se  Fri Oct  1 23:39:53 2010
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Oct 2010 23:39:53 +0200
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <20101001212759.GV3256@greenwood>
References: <20101001212759.GV3256@greenwood>
Message-ID: <20101001213953.20724.qmail@stuge.se>

Uwe Hermann wrote:
> Factor out common CAR asm snippets.
> 
> This makes the CAR implementations a lot more readable, shorter and
> easier to follow, and also reduces the amount of uselessly duplicated code.
> 
> For example there are more than 12 open-coded "enable cache" instances
> spread all over the place (and 12 "disable cache" ones), multiple
> "enable mtrr", "save BIST", "restore BIST", etc. etc.
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

Nice! I would kill some blank lines too, but this is a really nice 
improvement either way!

Acked-by: Peter Stuge <peter at stuge.se>



From mylesgw at gmail.com  Fri Oct  1 23:39:43 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 Oct 2010 15:39:43 -0600
Subject: [coreboot] [commit] r5901 - in trunk/src/cpu/intel:
	model_106cxmodel_6ex model_6fx
In-Reply-To: <20101001213121.GW3256@greenwood>
References: <E1P1jYH-00029Q-LL@ra.coresystems.de>
	<30767EF4E6AA40BB931F442DC639F014@chimp>
	<20101001213121.GW3256@greenwood>
Message-ID: <292C08139A204117B0A9BB2A663B4B3B@chimp>

> On Fri, Oct 01, 2010 at 11:55:49AM -0600, Myles Watson wrote:
> > > Modified:
> > >    trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
> > >    trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
> > >    trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
> > It looks like src/cpu/intel/car/cache_as_ram.inc could use the same
> love.
> 
> Hm, I think I already cleaned up that one.
Sorry about that.  I was trying to diff it with model_6ex/cache_as_ram.inc,
and lots of the comments, indenting, etc. didn't match yet.

> > I'd be interested to see how much uglier it made these files to combine
> > them.  There's very little difference between the 6ex & 6fx code.
> 
> Indeed, I'll post a patch to unify 6ex, 6fx, and 106cx at the very
> least, their differences are minimal.
> 
> The other ones are a bit different, but I'll post a few more patches to
> factor out common stuff and further simplify the code, which might
> allow us to factor out more generic code maybe, we'll see.

Thanks for doing it!
Myles





From svn at coreboot.org  Fri Oct  1 23:46:05 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 23:46:05 +0200
Subject: [coreboot] [commit] r5902 - in trunk/src: cpu/amd/car cpu/intel/car
	cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx
	cpu/via/car include/cpu/x86
Message-ID: <E1P1nQb-0001ym-Dc@ra.coresystems.de>

Author: uwe
Date: Fri Oct  1 23:46:04 2010
New Revision: 5902
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5902

Log:
Factor out common CAR asm snippets.

This makes the CAR implementations a lot more readable, shorter and
easier to follow, and also reduces the amount of uselessly duplicated code.

For example there are more than 12 open-coded "enable cache" instances
spread all over the place (and 12 "disable cache" ones), multiple
"enable mtrr", "save BIST", "restore BIST", etc. etc.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Peter Stuge <peter at stuge.se>

Added:
   trunk/src/include/cpu/x86/car.h
Modified:
   trunk/src/cpu/amd/car/cache_as_ram.inc
   trunk/src/cpu/intel/car/cache_as_ram.inc
   trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
   trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
   trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
   trunk/src/cpu/via/car/cache_as_ram.inc

Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc	Fri Oct  1 19:37:45 2010	(r5901)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc	Fri Oct  1 23:46:04 2010	(r5902)
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <cpu/x86/car.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 
@@ -45,8 +46,7 @@
  *   xmm3: Backup EBX
  */
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
+	save_bist_result()
 
 	/*
 	 * For normal part %ebx already contain cpu_init_detected
@@ -56,10 +56,7 @@
 cache_as_ram_setup:
 	post_code(0xa0)
 
-	/* Enable SSE. */
-	movl	%cr4, %eax
-	orl	$(3 << 9), %eax
-	movl	%eax, %cr4
+	enable_sse()
 
 	/* Figure out the CPU family. */
 	cvtsi2sd %ebx, %xmm3
@@ -299,10 +296,7 @@
 
 	post_code(0xa1)
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	jmp_if_k8(fam10_end_part1)
 
@@ -384,13 +378,9 @@
 
 	post_code(0xa5)
 
-	/* Disable SSE. */
-	movl	%cr4, %eax
-	andl	$~(3 << 9), %eax
-	movl	%eax, %cr4
+	disable_sse()
 
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
+	restore_bist_result()
 
 	/* We need to set EBP? No need. */
 	movl	%esp, %ebp

Modified: trunk/src/cpu/intel/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/car/cache_as_ram.inc	Fri Oct  1 19:37:45 2010	(r5901)
+++ trunk/src/cpu/intel/car/cache_as_ram.inc	Fri Oct  1 23:46:04 2010	(r5902)
@@ -21,6 +21,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/lapic_def.h>
@@ -28,8 +29,7 @@
 #define CacheSize		CONFIG_DCACHE_RAM_SIZE
 #define CacheBase		(0xd0000 - CacheSize)
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
+	save_bist_result()
 
 CacheAsRam:
 	/* Check whether the processor has HT capability. */
@@ -231,10 +231,7 @@
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	/* Read the range with lodsl. */
 	movl	$CacheBase, %esi
@@ -295,8 +292,7 @@
 	movl	$(CacheBase + CacheSize - 4), %eax
 	movl	%eax, %esp
 lout:
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
+	restore_bist_result()
 
 	/* We need to set EBP? No need. */
 	movl	%esp, %ebp
@@ -305,10 +301,7 @@
 
 	/* We don't need CAR from now on. */
 
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 	/* Clear sth. */
 	movl	$MTRRfix4K_C8000_MSR, %ecx
@@ -330,10 +323,7 @@
 	movl	$0x00000800, %eax /* Enable variable and disable fixed MTRRs. */
 	wrmsr
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
-	movl	%eax, %cr0
+	enable_cache();
 
 	/* Clear boot_complete flag. */
 	xorl	%ebp, %ebp

Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	Fri Oct  1 19:37:45 2010	(r5901)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	Fri Oct  1 23:46:04 2010	(r5902)
@@ -18,14 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
+	save_bist_result()
 
 cache_as_ram:
 	post_code(0x20)
@@ -66,19 +66,12 @@
 	xorl	%edx, %edx
 	wrmsr
 
-	/* Enable MTRR. */
-	movl	$MTRRdefType_MSR, %ecx
-	rdmsr
-	orl	$(1 << 11), %eax
-	wrmsr
+	enable_mtrr()
 
-	/* Enable L2 cache. */
-	movl	$0x11e, %ecx
-	rdmsr
-	orl	$(1 << 8), %eax
-	wrmsr
+	enable_l2_cache()
 
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+	/* TODO: enable_cache()? But that doesn't have "invd". */
         movl	%cr0, %eax
 	andl	$(~((1 << 30) | (1 << 29))), %eax
 	invd
@@ -93,9 +86,7 @@
 	rep	stosl
 
 	/* Enable Cache-as-RAM mode by disabling cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* Enable cache for our code in Flash because we do XIP here */
@@ -116,10 +107,7 @@
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	/* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -130,8 +118,8 @@
 #endif
 	movl	%eax, %esp
 
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
+	restore_bist_result()
+
 	movl	%esp, %ebp
 	pushl	%eax
 
@@ -144,18 +132,11 @@
 
 	post_code(0x30)
 
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 	post_code(0x31)
 
-	/* Disable MTRR. */
-	movl	$MTRRdefType_MSR, %ecx
-	rdmsr
-	andl	$(~(1 << 11)), %eax
-	wrmsr
+	disable_mtrr()
 
 	post_code(0x31)
 
@@ -175,17 +156,11 @@
 
 	post_code(0x33)
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$~((1 << 30) | (1 << 29)), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	post_code(0x36)
 
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 	post_code(0x38)
 
@@ -202,17 +177,11 @@
 	post_code(0x39)
 
 	/* And enable cache again after setting MTRRs. */
-	movl	%cr0, %eax
-	andl	$~((1 << 30) | (1 << 29)), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	post_code(0x3a)
 
-	/* Enable MTRR. */
-	movl	$MTRRdefType_MSR, %ecx
-	rdmsr
-	orl	$(1 << 11), %eax
-	wrmsr
+	enable_mtrr()
 
 	post_code(0x3b)
 

Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Fri Oct  1 19:37:45 2010	(r5901)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Fri Oct  1 23:46:04 2010	(r5902)
@@ -18,14 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
+	save_bist_result()
 
 cache_as_ram:
 	post_code(0x20)
@@ -66,19 +66,12 @@
 	movl	$0x0000000f, %edx
 	wrmsr
 
-	/* Enable MTRR. */
-	movl	$MTRRdefType_MSR, %ecx
-	rdmsr
-	orl	$(1 << 11), %eax
-	wrmsr
+	enable_mtrr()
 
-	/* Enable L2 cache. */
-	movl	$0x11e, %ecx
-	rdmsr
-	orl	$(1 << 8), %eax
-	wrmsr
+	enable_l2_cache()
 
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+	/* TODO: enable_cache()? But that doesn't have "invd". */
         movl	%cr0, %eax
 	andl	$(~((1 << 30) | (1 << 29))), %eax
 	invd
@@ -93,9 +86,7 @@
 	rep	stosl
 
 	/* Enable Cache-as-RAM mode by disabling cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* Enable cache for our code in Flash because we do XIP here */
@@ -116,10 +107,7 @@
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	/* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -130,8 +118,8 @@
 #endif
 	movl	%eax, %esp
 
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
+	restore_bist_result()
+
 	movl	%esp, %ebp
 	pushl	%eax
 
@@ -144,18 +132,11 @@
 
 	post_code(0x30)
 
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 	post_code(0x31)
 
-	/* Disable MTRR. */
-	movl	$MTRRdefType_MSR, %ecx
-	rdmsr
-	andl	$(~(1 << 11)), %eax
-	wrmsr
+	disable_mtrr()
 
 	post_code(0x31)
 
@@ -175,17 +156,11 @@
 
 	post_code(0x33)
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$~((1 << 30) | (1 << 29)), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	post_code(0x36)
 
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 	post_code(0x38)
 
@@ -202,17 +177,11 @@
 	post_code(0x39)
 
 	/* And enable cache again after setting MTRRs. */
-	movl	%cr0, %eax
-	andl	$~((1 << 30) | (1 << 29)), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	post_code(0x3a)
 
-	/* Enable MTRR. */
-	movl	$MTRRdefType_MSR, %ecx
-	rdmsr
-	orl	$(1 << 11), %eax
-	wrmsr
+	enable_mtrr()
 
 	post_code(0x3b)
 

Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	Fri Oct  1 19:37:45 2010	(r5901)
+++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	Fri Oct  1 23:46:04 2010	(r5902)
@@ -18,14 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
+	save_bist_result()
 
 cache_as_ram:
 	post_code(0x20)
@@ -73,19 +73,12 @@
 	movl	$0x0000000f, %edx
 	wrmsr
 
-	/* Enable MTRR. */
-	movl	$MTRRdefType_MSR, %ecx
-	rdmsr
-	orl	$(1 << 11), %eax
-	wrmsr
+	enable_mtrr()
 
-	/* Enable L2 cache. */
-	movl	$0x11e, %ecx
-	rdmsr
-	orl	$(1 << 8), %eax
-	wrmsr
+	enable_l2_cache()
 
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+	/* TODO: enable_cache()? But that doesn't have "invd". */
         movl	%cr0, %eax
 	andl	$(~((1 << 30) | (1 << 29))), %eax
 	invd
@@ -100,9 +93,7 @@
 	rep	stosl
 
 	/* Enable Cache-as-RAM mode by disabling cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* Enable cache for our code in Flash because we do XIP here */
@@ -123,10 +114,7 @@
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	/* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -137,8 +125,8 @@
 #endif
 	movl	%eax, %esp
 
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
+	restore_bist_result()
+
 	movl	%esp, %ebp
 	pushl	%eax
 
@@ -151,18 +139,11 @@
 
 	post_code(0x30)
 
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 	post_code(0x31)
 
-	/* Disable MTRR. */
-	movl	$MTRRdefType_MSR, %ecx
-	rdmsr
-	andl	$(~(1 << 11)), %eax
-	wrmsr
+	disable_mtrr()
 
 	post_code(0x31)
 
@@ -182,17 +163,11 @@
 
 	post_code(0x33)
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$~((1 << 30) | (1 << 29)), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	post_code(0x36)
 
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 	post_code(0x38)
 
@@ -209,17 +184,11 @@
 	post_code(0x39)
 
 	/* And enable cache again after setting MTRRs. */
-	movl	%cr0, %eax
-	andl	$~((1 << 30) | (1 << 29)), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	post_code(0x3a)
 
-	/* Enable MTRR. */
-	movl	$MTRRdefType_MSR, %ecx
-	rdmsr
-	orl	$(1 << 11), %eax
-	wrmsr
+	enable_mtrr()
 
 	post_code(0x3b)
 

Modified: trunk/src/cpu/via/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/via/car/cache_as_ram.inc	Fri Oct  1 19:37:45 2010	(r5901)
+++ trunk/src/cpu/via/car/cache_as_ram.inc	Fri Oct  1 23:46:04 2010	(r5902)
@@ -25,21 +25,18 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
 #define CacheSize		CONFIG_DCACHE_RAM_SIZE
 #define CacheBase		CONFIG_DCACHE_RAM_BASE
 
-	/* Save the BIST result. */
-	movl	%eax, %ebp
+	save_bist_result()
 
 CacheAsRam:
 
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 	invd
 
 	/* Set the default memory type and enable fixed and variable MTRRs. */
@@ -116,10 +113,7 @@
 	movl	$(MTRRdefTypeEn), %eax
 	wrmsr
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
-	movl	%eax, %cr0
+	enable_cache()
 
 	/* Read the range with lodsl. */
 	cld
@@ -175,8 +169,7 @@
 	jne	stackerr
 #endif
 
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
+	restore_bist_result()
 
 	/* We need to set EBP? No need. */
 	movl	%esp, %ebp
@@ -191,10 +184,7 @@
 
 	/* We don't need CAR from now on. */
 
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
-	movl	%eax, %cr0
+	disable_cache()
 
 	/* Set the default memory type and enable variable MTRRs. */
 	/* TODO: Or also enable fixed MTRRs? Bug in the code? */
@@ -253,10 +243,7 @@
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
 
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
-	movl	%eax, %cr0
+	enable_cache()
 	invd
 
 	/* Clear boot_complete flag. */

Added: trunk/src/include/cpu/x86/car.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/include/cpu/x86/car.h	Fri Oct  1 23:46:04 2010	(r5902)
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <cpu/x86/mtrr.h>
+
+/* Save the BIST result. */
+#define save_bist_result() \
+	movl	%eax, %ebp
+
+/* Restore the BIST result. */
+#define restore_bist_result() \
+	movl	%ebp, %eax
+
+/* Enable cache. */
+#define enable_cache() \
+	movl	%cr0, %eax; \
+	andl	$(~((1 << 30) | (1 << 29))), %eax; \
+	movl	%eax, %cr0
+
+/* Disable cache. */
+#define disable_cache() \
+	movl	%cr0, %eax; \
+	orl	$(1 << 30), %eax; \
+	movl	%eax, %cr0
+
+/* Enable MTRR. */
+#define enable_mtrr() \
+	movl	$MTRRdefType_MSR, %ecx; \
+	rdmsr; \
+	orl	$(1 << 11), %eax; \
+	wrmsr
+
+/* Disable MTRR. */
+#define disable_mtrr() \
+	movl	$MTRRdefType_MSR, %ecx; \
+	rdmsr; \
+	andl	$(~(1 << 11)), %eax; \
+	wrmsr
+
+/* Enable L2 cache. */
+#define enable_l2_cache() \
+	movl	$0x11e, %ecx; \
+	rdmsr; \
+	orl	$(1 << 8), %eax; \
+	wrmsr
+
+/* Enable SSE. */
+#define enable_sse() \
+	movl	%cr4, %eax; \
+	orl	$(3 << 9), %eax; \
+	movl	%eax, %cr4
+
+/* Disable SSE. */
+#define disable_sse() \
+	movl	%cr4, %eax; \
+	andl	$~(3 << 9), %eax; \
+	movl	%eax, %cr4
+



From mylesgw at gmail.com  Fri Oct  1 23:46:31 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 Oct 2010 15:46:31 -0600
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <20101001212759.GV3256@greenwood>
References: <20101001212759.GV3256@greenwood>
Message-ID: <D20747B0D2134E3E82D6CFB191437651@chimp>


This was surprising:

+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH

The macros are well named.  I'd prefer including comments only for ones that
need an explanation.

+/* Disable cache. */
+#define disable_cache() \
+	movl	%cr0, %eax; \
+	orl	$(1 << 30), %eax; \
+	movl	%eax, %cr0
+

Thanks,
Myles




From svn at coreboot.org  Fri Oct  1 23:48:52 2010
From: svn at coreboot.org (repository service)
Date: Fri, 01 Oct 2010 23:48:52 +0200
Subject: [coreboot] [commit] r5903 - trunk
Message-ID: <E1P1nTI-0005hX-Sv@ra.coresystems.de>

Author: myles
Date: Fri Oct  1 23:48:52 2010
New Revision: 5903
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5903

Log:
Redirect the output of iasl to a file to make the build quieter.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/Makefile

Modified: trunk/Makefile
==============================================================================
--- trunk/Makefile	Fri Oct  1 23:46:04 2010	(r5902)
+++ trunk/Makefile	Fri Oct  1 23:48:52 2010	(r5903)
@@ -229,7 +229,7 @@
 $(obj)/$(1).ramstage.o: src/$(1).asl
 	@printf "    IASL       $$(subst $(top)/,,$$(@))\n"
 	$(CPP) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl
-	iasl -p $$(obj)/$(1) -tc $$(basename $$@).asl
+	iasl -p $$(obj)/$(1) -tc $$(basename $$@).asl > $$(basename $$@).asl.out
 	mv $$(obj)/$(1).hex $$(basename $$@).c
 	$(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$@).c
 	# keep %.o: %.c rule from catching the temporary .c file after a make clean



From mylesgw at gmail.com  Fri Oct  1 23:49:37 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 Oct 2010 15:49:37 -0600
Subject: [coreboot] [Patch] Quieter build
In-Reply-To: <20101001213546.GX3256@greenwood>
References: <AANLkTimQN-ThBWxM=Jps7fm11KV3jfVeKzB=vHP_FL-i@mail.gmail.com>
	<20101001213546.GX3256@greenwood>
Message-ID: <AANLkTi=NkoR5FSAN++t3H_KenNw-AWd9=+w=Af8GTLOS@mail.gmail.com>

On Fri, Oct 1, 2010 at 3:35 PM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> On Fri, Oct 01, 2010 at 12:01:59PM -0600, Myles Watson wrote:
>> I'd like to redirect the output of iasl to a file. ?Patch attached.
>>
>> Here's a little justification:
>> http://qa.coreboot.org/log_buildbrd.php?revision=5900&device=serengeti_cheetah&vendor=amd&num=2
>>
>> Signed-off-by: Myles Watson <mylesgw at gmail.com>
>
> Yep, makes sense.
>
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Rev 5903.

Thanks,
Myles



From stefan.reinauer at coresystems.de  Sat Oct  2 00:09:31 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Oct 2010 00:09:31 +0200
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <20101001212759.GV3256@greenwood>
References: <20101001212759.GV3256@greenwood>
Message-ID: <4CA65C1B.3090908@coresystems.de>

 On 10/1/10 11:27 PM, Uwe Hermann wrote:
> See patch.
>
> abuilt-tested.
>
>
> Uwe.
IMHO the patch makes it really hard to actually see what the code does.
I think Idwer was recently running into a problem where the use of
post_code would trash %eax were hard to comprehend. Now we seem have a
lot more code that comes from somewhere else and touches registers
without it being obvious to the reader of the code.

Just my 2ct.

Stefan



From uwe at hermann-uwe.de  Sat Oct  2 00:07:56 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 2 Oct 2010 00:07:56 +0200
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <D20747B0D2134E3E82D6CFB191437651@chimp>
References: <20101001212759.GV3256@greenwood>
	<D20747B0D2134E3E82D6CFB191437651@chimp>
Message-ID: <20101001220756.GN6119@greenwood>

On Fri, Oct 01, 2010 at 03:46:31PM -0600, Myles Watson wrote:
> 
> This was surprising:
> 
> + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
> + * Copyright (C) 2007-2008 coresystems GmbH

Yeah, I copied most of the stuff from model_6ex or something like that,
hence the (C) lines, but it's all generic simple stuff, maybe I should
have made it (C) Uwe Hermann <uwe at hermann-uwe.de> ?

 
> The macros are well named.  I'd prefer including comments only for ones that
> need an explanation.

I'll extend the comments a bit more later, wanted to leave that for
another patch.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From mylesgw at gmail.com  Sat Oct  2 00:34:03 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 Oct 2010 16:34:03 -0600
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <20101001220756.GN6119@greenwood>
References: <20101001212759.GV3256@greenwood>
	<D20747B0D2134E3E82D6CFB191437651@chimp>
	<20101001220756.GN6119@greenwood>
Message-ID: <C198D17DAC704525A16781797E6C3BB9@chimp>

> On Fri, Oct 01, 2010 at 03:46:31PM -0600, Myles Watson wrote:
> >
> > This was surprising:
> >
> > + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
> > + * Copyright (C) 2007-2008 coresystems GmbH
> 
> Yeah, I copied most of the stuff from model_6ex or something like that,
> hence the (C) lines, but it's all generic simple stuff, maybe I should
> have made it (C) Uwe Hermann <uwe at hermann-uwe.de> ?

That would work for me.  I also wouldn't have been surprised to see 

(C) 2000 Ronald G. Minnich <rminnich at gmail.com>, or whoever the original
author of the CAR code was.

I doubt those snippets have changed a lot over the years.

Thanks,
Myles




From mylesgw at gmail.com  Sat Oct  2 00:38:34 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 Oct 2010 16:38:34 -0600
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <4CA65C1B.3090908@coresystems.de>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
Message-ID: <804A776E676144E0BD0C3EC615A6EDFA@chimp>

> IMHO the patch makes it really hard to actually see what the code does.
> I think Idwer was recently running into a problem where the use of
> post_code would trash %eax were hard to comprehend. Now we seem have a
> lot more code that comes from somewhere else and touches registers
> without it being obvious to the reader of the code.

I agree for Save/Restore BIST, since it's only one line.  I like the macros
for longer snippets, though.  Would a comment like 

/* Clobbers %eax, %edx, ... */

be the right way to fix it?  Would it be better to have the clobber list in
the name?

disable_sse_with_eax()?

Thanks,
Myles




From rminnich at gmail.com  Sat Oct  2 00:46:23 2010
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Oct 2010 15:46:23 -0700
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <C198D17DAC704525A16781797E6C3BB9@chimp>
References: <20101001212759.GV3256@greenwood>
	<D20747B0D2134E3E82D6CFB191437651@chimp>
	<20101001220756.GN6119@greenwood>
	<C198D17DAC704525A16781797E6C3BB9@chimp>
Message-ID: <AANLkTin22ahUnniiNRDvsvcbKyJjWhj4R+VXrcCRy2Wu@mail.gmail.com>

On Fri, Oct 1, 2010 at 3:34 PM, Myles Watson <mylesgw at gmail.com> wrote:

> (C) 2000 Ronald G. Minnich <rminnich at gmail.com>, or whoever the original
> author of the CAR code was.


Would that I were that smart :-)

the real guy who gets the credit is Eswar and it would be nice to see
his name preserved in there somehow. He really did us a huge favor
when he showed us How It Is Done.

ron



From peter at stuge.se  Sat Oct  2 01:09:37 2010
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Oct 2010 01:09:37 +0200
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <4CA65C1B.3090908@coresystems.de>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
Message-ID: <20101001230937.30426.qmail@stuge.se>

Stefan Reinauer wrote:
> IMHO the patch makes it really hard to actually see what the code
> does.

I think this is the same argument as the one against pci_cfg8_set()
and similar functions which would gather read+modify+write into one
step.

I disagree that it's a problem. I think that anyone looking at this
code should be able to remember e.g. that the bist is saved in ebp,
or that enabling the cache clobbers eax..

I think it is far more valuable if this code can be slightly more
high level, shorter, and much more heterogenous.

Also, apropos shorter, this code should not have to keep a lot of
state across many operations, which IMO reduces the problem.


> Now we seem have a lot more code that comes from somewhere else and
> touches registers without it being obvious to the reader of the
> code.

We could make a strict policy that all macros used in any CAR code
must come from car.h.


//Peter



From nathan at traverse.com.au  Sat Oct  2 02:58:35 2010
From: nathan at traverse.com.au (Nathan Williams)
Date: Sat, 02 Oct 2010 10:58:35 +1000
Subject: [coreboot] [PATCH] Enable or disable the power button in Kconfig
In-Reply-To: <20101001194610.8333.qmail@stuge.se>
References: <20101001194610.8333.qmail@stuge.se>
Message-ID: <4CA683BB.7020008@traverse.com.au>

Peter Stuge wrote:
> Please see the attached patch. I would like to especially ask those
> who have worked on boards which use the 5536 to check if maybe their
> board should select a different POWER_BUTTON_* now. Again, existing
> behavior should be unchanged from previous except on ALIX.1.
> 

Please make traverse/geos use POWER_BUTTON_DEFAULT_DISABLE.  There's a jumper like the Alix1.

Also, there's a typo in src/Kconfig:

+# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
+# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISBALE options are

Regards,
Nathan



From svn at coreboot.org  Sat Oct  2 03:35:42 2010
From: svn at coreboot.org (coreboot)
Date: Sat, 02 Oct 2010 01:35:42 -0000
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
Message-ID: <058.26bed74dd53c3328238e7a93b75343f1@coreboot.org>

#163: Board still requires RAMBASE <1MB
-----------------------------------------+----------------------------------
    Reporter:  oxygene                   |          Owner:  stepan@?             
        Type:  defect                    |         Status:  closed               
    Priority:  minor                     |      Milestone:                       
   Component:  coreboot                  |     Resolution:  fixed                
    Keywords:                            |   Dependencies:                       
Patch Status:  patch has been committed  |  
-----------------------------------------+----------------------------------

Comment (by RedeFusegaida):

 An Ultra Higher Efficiency search that tends to make the Solo-Baric?? <a
 href=http://seymour8morse.sosblog.com/The-first-blog-b1/Grundig-Shortwave-
 Stereo-b1-p3.htm>L7</a> genuinely a statement item. The cone offers you
 deeper and stronger bass at greater listening levels with less distortion
 due to a smaller amount tendency to flex. Simply because, when a woofer
 cone flexes, there is a reduction of output. This decline of output
 translates into much less bass.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/163#comment:3>
coreboot <http://www.coreboot.org/>


From peter at stuge.se  Sat Oct  2 03:47:55 2010
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Oct 2010 03:47:55 +0200
Subject: [coreboot] [PATCH] Enable or disable the power button in	Kconfig
In-Reply-To: <4CA683BB.7020008@traverse.com.au>
References: <20101001194610.8333.qmail@stuge.se>
	<4CA683BB.7020008@traverse.com.au>
Message-ID: <20101002014755.13975.qmail@stuge.se>

Nathan Williams wrote:
> make traverse/geos use POWER_BUTTON_DEFAULT_DISABLE
> 
> typo

Thanks! Both are fixed locally.


//Peter



From hagigatali at gmail.com  Sat Oct  2 09:49:03 2010
From: hagigatali at gmail.com (ali hagigat)
Date: Sat, 2 Oct 2010 11:19:03 +0330
Subject: [coreboot] BBC EFI story
In-Reply-To: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
References: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
Message-ID: <AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>

Dear Ron Minnich,
I started with Wiki pages of Coreboot and i found Kontron, 986LCD-mITX
as a supported mother board. I though its documentation is open
because Coreboot is open source and ordered 4 motherboards, over
11000$.
After investigating more about Intel manuals I found out that many
registers of North bridge, 82945 have not been expressed!! and Intel
gives this information to big BIOS companies ONLY.
At least you could update Wiki pages to state this fact clearly to
stop people waste money.
How people can contribute the code while they do not have
documentation and necessary information?

On Sat, Oct 2, 2010 at 12:22 AM, ron minnich <rminnich at gmail.com> wrote:
> This story is full of errors. I thought I'd point out a few.
>
> "New PCs could start in just seconds, thanks to an update to one of
> the oldest parts of desktop computers."
>
> I've got news for the UEFI forum: OLD computers, starting 10 years
> ago, have been starting in seconds, thanks to the coreboot project. We
> first showed a 12 second boot at the Atlanta Linux Symposium in Oct.
> 2000. It is hardly news that one can boot a computer quickly. The
> project then was called LinuxBIOS; the project today is called
> Coreboot. Coreboot works on embedded systems, desktops, laptops, and
> supercomputers. It has run in the iRobot packbot for 10 years,
> searching mines and saving lives. Some of the biggest supercomputers
> in the world have run coreboot. Work on coreboot was, in fact, funded
> first by the US Gov't (Dept. of Energy) and more recently by the
> German Government (see, for example,
> http://www.coreboot.org/pipermail/coreboot-announce/2010-May/000007.html)
>
> So why, might you ask, did vendors not pick this technology up 10
> years ago? Technology that worked on x86, 64-bit x86, Power PC, and
> DEC Alpha? The reason is simple: it's open source. And, while vendors
> finally did decide that an open source operating system might be
> acceptable, they have had a lot of trouble accepting an open source
> BIOS. They feel that too much information is divulged if the BIOS is
> open source. They make a lot of excuses, but in the end, they finally
> admit that the issue is that they don't want the hardware to be that
> open.
>
> "The upgrade will spell the end for the 25-year-old PC start-up
> software known as Bios that initialises a machine so its operating
> system can get going."
>
> The BIOS could have been ended ten years ago, but for a simple fact:
> many customers don't much like EFI. It's clumsy, slow, and closed. And
> it's hard to work around, as it is designed to hide information.
>
> "The code was not intended to live nearly this long, and adapting it
> to modern PCs is one reason they take as long as they do to warm up."
>
> There's a lot more to it than that. The closed nature of the BIOS
> software made it very hard to replace. And, again, the vendors have
> shown time and again that they prefer a closed, proprietary solution
> to an open source solution. That's the real problem.
>
> "Alternatives to UEFI, such as Open Firmware and Coreboot, do exist
> and are typically used on computers that do not run chips based on
> Intel's x86 architecture."
>
> This statement is completely wrong. Coreboot has run on x86 systems
> from the start and, in fact, only runs on x86 systems now. Open
> Firmware also runs on x86 systems and is in fact the BIOS for the One
> Laptop Per Child project -- an x86 system.
>
> ""At the moment it can be 25-30 seconds of boot time before you see
> the first bit of OS sign-on," he said. "With UEFI we're getting it
> under a handful of seconds.""
>
> It's nice to see UEFI catching up only 10 years later; the first
> versions took 10 minutes to boot. Automobile computers, using ARM
> processors, and an open source BIOS called U-boot, boot Linux in 8/10
> of a second. So, while UEFI is where coreboot was ten years ago, we've
> all moved on; seconds is kind of slow nowadays.
>
> "He said that 2011 would be the year that sales of UEFI machines start
> to dominate."
>
> Dominate what? Certainly not cell phones. Certainly not the ipad. In
> fact, UEFI is going to dominate a segment that matters less and less
> nowadays -- PC-compatible desktops and laptops.
>
> I think you can do better than this article; the BBC is one of the
> finest news organizations in the world. It seems you took a puff-piece
> from the UEFI group and removed the quotes. I'm very disappointed in
> the BBC.
>
> Thanks
> Ron Minnich
> Founder, LinuxBIOS, which is now coreboot.
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From svn at coreboot.org  Sat Oct  2 10:57:06 2010
From: svn at coreboot.org (coreboot)
Date: Sat, 02 Oct 2010 08:57:06 -0000
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
Message-ID: <058.0bfec39e29674a4007db88abea55f59c@coreboot.org>

#163: Board still requires RAMBASE <1MB
-----------------------------------------+----------------------------------
    Reporter:  oxygene                   |          Owner:  stepan@?             
        Type:  defect                    |         Status:  closed               
    Priority:  minor                     |      Milestone:                       
   Component:  coreboot                  |     Resolution:  fixed                
    Keywords:                            |   Dependencies:                       
Patch Status:  patch has been committed  |  
-----------------------------------------+----------------------------------

Comment (by Ailironaka):

 How do you do?
 I am 31 years old woman and I live in Venezuela, Santa Rosa. My interests
 it is a family and spiritual self-improvement. For a long time dreamed to
 make international friends

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/163#comment:4>
coreboot <http://www.coreboot.org/>


From corey.osgood at gmail.com  Sat Oct  2 11:00:56 2010
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 2 Oct 2010 05:00:56 -0400
Subject: [coreboot] BBC EFI story
In-Reply-To: <AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>
References: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
	<AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>
Message-ID: <AANLkTimpfhNBCQU8KEXPq1=-CZzTYhNPS2apkagBJx6O@mail.gmail.com>

On Sat, Oct 2, 2010 at 3:49 AM, ali hagigat <hagigatali at gmail.com> wrote:
> Dear Ron Minnich,
> I started with Wiki pages of Coreboot and i found Kontron, 986LCD-mITX
> as a supported mother board. I though its documentation is open
> because Coreboot is open source

Don't blame coreboot for your own misunderstanding. Just because a
project is open source doesn't mean every bit of data on how the code
was written has public documentation. The linux kernel (and I imagine
BSD, solaris, etc) is also open source, but some of the hardware
supported within doesn't have public datasheets, or the datasheets
that are public are incomplete.

> and ordered 4 motherboards, over 11000$.
> After investigating more about Intel manuals I found out that many
> registers of North bridge, 82945 have not been expressed!! and Intel
> gives this information to big BIOS companies ONLY.

This is incorrect. Intel will give this info to anyone who can present
them with a good reason for needing it. For whatever reason, they
don't want their competition knowing how to program the registers in
their chipsets. This is unfortunate, but a fact of life. You can
either deal with it and try to write a port without this
documentation, hire someone to write it for you, return your 4
motherboards in favor of AMD hardware, or live with the BIOS that was
presumably included with your boards.

> At least you could update Wiki pages to state this fact clearly to
> stop people waste money.

Most people don't insist on understanding every single line of chipset
code to port a motherboard. If your chipset is supported, it should be
relatively easy to port a board to it. Coresystems even went out of
their way to make sure the 945 port included the revision-specific
fixes for every revision of the 945, and also to support variants of
the 945 that most likely were not necessary for the board they were
working with. Instead of complaining about the lack of
chipset-specific documentation, why don't you dive in and try writing
a port based on the existing 945 boards?

> How people can contribute the code while they do not have
> documentation and necessary information?

The person who wrote the chipset port obviously couldn't, which means
that a company went to Intel with a contract/business case, acquired
the datasheets under NDA, wrote the code, and Intel then approved it
for public release. I understand that this can be frustrating, but
it's something that the coreboot project has no control over. If we
could make the datasheets for every chipset publicly available, we
would, but that's not how it works. NDA stands for Non-Disclosure
Agreement, which means that whoever gets that documentation does so
bound by law not to reveal the information in it, except what's
approved by e.g. Intel for release.

However, coreboot is written in such a way that it's theoretically
possible to write a port for a motherboard without ever looking at the
chipset code. As I look through the various boards that are already
using the 945 port, I don't see any of those nasty undocumented
registers being touched in mainboard code, that's all tucked away
inside the chipset code, and so you shouldn't need to touch it. So,
once again I urge you to stop asking/expecting the impossible, and
instead focus on using the resources available to reach your goal.

-Corey

>
> On Sat, Oct 2, 2010 at 12:22 AM, ron minnich <rminnich at gmail.com> wrote:
>> This story is full of errors. I thought I'd point out a few.
>>
>> "New PCs could start in just seconds, thanks to an update to one of
>> the oldest parts of desktop computers."
>>
>> I've got news for the UEFI forum: OLD computers, starting 10 years
>> ago, have been starting in seconds, thanks to the coreboot project. We
>> first showed a 12 second boot at the Atlanta Linux Symposium in Oct.
>> 2000. It is hardly news that one can boot a computer quickly. The
>> project then was called LinuxBIOS; the project today is called
>> Coreboot. Coreboot works on embedded systems, desktops, laptops, and
>> supercomputers. It has run in the iRobot packbot for 10 years,
>> searching mines and saving lives. Some of the biggest supercomputers
>> in the world have run coreboot. Work on coreboot was, in fact, funded
>> first by the US Gov't (Dept. of Energy) and more recently by the
>> German Government (see, for example,
>> http://www.coreboot.org/pipermail/coreboot-announce/2010-May/000007.html)
>>
>> So why, might you ask, did vendors not pick this technology up 10
>> years ago? Technology that worked on x86, 64-bit x86, Power PC, and
>> DEC Alpha? The reason is simple: it's open source. And, while vendors
>> finally did decide that an open source operating system might be
>> acceptable, they have had a lot of trouble accepting an open source
>> BIOS. They feel that too much information is divulged if the BIOS is
>> open source. They make a lot of excuses, but in the end, they finally
>> admit that the issue is that they don't want the hardware to be that
>> open.
>>
>> "The upgrade will spell the end for the 25-year-old PC start-up
>> software known as Bios that initialises a machine so its operating
>> system can get going."
>>
>> The BIOS could have been ended ten years ago, but for a simple fact:
>> many customers don't much like EFI. It's clumsy, slow, and closed. And
>> it's hard to work around, as it is designed to hide information.
>>
>> "The code was not intended to live nearly this long, and adapting it
>> to modern PCs is one reason they take as long as they do to warm up."
>>
>> There's a lot more to it than that. The closed nature of the BIOS
>> software made it very hard to replace. And, again, the vendors have
>> shown time and again that they prefer a closed, proprietary solution
>> to an open source solution. That's the real problem.
>>
>> "Alternatives to UEFI, such as Open Firmware and Coreboot, do exist
>> and are typically used on computers that do not run chips based on
>> Intel's x86 architecture."
>>
>> This statement is completely wrong. Coreboot has run on x86 systems
>> from the start and, in fact, only runs on x86 systems now. Open
>> Firmware also runs on x86 systems and is in fact the BIOS for the One
>> Laptop Per Child project -- an x86 system.
>>
>> ""At the moment it can be 25-30 seconds of boot time before you see
>> the first bit of OS sign-on," he said. "With UEFI we're getting it
>> under a handful of seconds.""
>>
>> It's nice to see UEFI catching up only 10 years later; the first
>> versions took 10 minutes to boot. Automobile computers, using ARM
>> processors, and an open source BIOS called U-boot, boot Linux in 8/10
>> of a second. So, while UEFI is where coreboot was ten years ago, we've
>> all moved on; seconds is kind of slow nowadays.
>>
>> "He said that 2011 would be the year that sales of UEFI machines start
>> to dominate."
>>
>> Dominate what? Certainly not cell phones. Certainly not the ipad. In
>> fact, UEFI is going to dominate a segment that matters less and less
>> nowadays -- PC-compatible desktops and laptops.
>>
>> I think you can do better than this article; the BBC is one of the
>> finest news organizations in the world. It seems you took a puff-piece
>> from the UEFI group and removed the quotes. I'm very disappointed in
>> the BBC.
>>
>> Thanks
>> Ron Minnich
>> Founder, LinuxBIOS, which is now coreboot.
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From wt at penguintechs.org  Sat Oct  2 10:59:32 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sat,  2 Oct 2010 01:59:32 -0700
Subject: [coreboot] [PATCH] Add CPP logic to VIA CAR init code.
Message-ID: <1286009972-6589-1-git-send-email-wt@penguintechs.org>

VIA/AMD experts,

This patch get's the via/vt8454c back to building. However, I am not
sure if the code that is being #ifdef'ed out will actually ever be used
on a via platform. The code comes straight from the amd CAR
implementation. A couple of questions are raised by this:
1) Should we just delete the code from the via file instead of this
   patch?
2) Should the amd and via CAR code be integrated into one file? Maybe
   just portions of the files if not the whole files?

Also, another happy side effect of this change is that all the c7 boards
seem to build with tiny bootblocks. Would everyone be ok with my making
that change?

Thanks,
wt
8<----------------------------------------------------------------------
The execute-in-place (XIP) config options need to be set in order to get
XIP functionality, so it needs to be excluded when those settings are
not set.

Signed-off-by: Warren Turkal <wt at penguintechs.org>
---
 src/cpu/via/car/cache_as_ram.inc |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index be00fe3..d18ac3a 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -85,6 +85,8 @@ clear_fixed_var_mtrr_out:
 	movl	$(~(CacheSize - 1) | 0x800), %eax
 	wrmsr
 
+#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
@@ -106,6 +108,8 @@ clear_fixed_var_mtrr_out:
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
 
+#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+
 	/* Set the default memory type and enable fixed and variable MTRRs. */
 	/* TODO: Or also enable fixed MTRRs? Bug in the code? */
 	movl	$MTRRdefType_MSR, %ecx
-- 
1.7.1




From wt at penguintechs.org  Sat Oct  2 11:26:15 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sat, 2 Oct 2010 02:26:15 -0700
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <20101001212759.GV3256@greenwood>
References: <20101001212759.GV3256@greenwood>
Message-ID: <AANLkTikHx8KXOau7vGz3SYgxCgsqA=KTRDYD4dQm=xCq@mail.gmail.com>

For line 31 and 37 of src/include/x86/car.h, does cache mean L1 cache?
If so, it might be nice to make the macros say l1 explicitly. Also, I
agree with Myles on not having redundant comments.

It might also be nice for the comments before each macro to indicate
which registers get trashed within the macro. Maybe even make the
register name a parameter of the macro, though I'm not sure if that
would make sense.

Also, {en,dis}able mtrr should document which mtrr is getting
{en,dis}abled as it looks like a specific one and not all of them. The
name of those macros should probably reflect which mtrr as well.

Thanks,
wt

On Fri, Oct 1, 2010 at 2:27 PM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> See patch.
>
> abuilt-tested.
>
>
> Uwe.
> --
> http://hermann-uwe.de ? ? | http://sigrok.org
> http://randomprojects.org | http://unmaintained-free-software.org
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From wt at penguintechs.org  Sat Oct  2 11:33:28 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sat, 2 Oct 2010 02:33:28 -0700
Subject: [coreboot] [commit] r5897 - trunk/src/cpu/via/car
In-Reply-To: <E1P1efa-0005HU-64@ra.coresystems.de>
References: <E1P1efa-0005HU-64@ra.coresystems.de>
Message-ID: <AANLkTinwBddN-xxDB+w_YAsKqJ6xhmfSF_59KZoFCap_@mail.gmail.com>

Stefan,

Is there a technical reason to split the logical "or" considering that
the values constants that are known at compile time? It seems like the
additional orl could be avoided by how the code was before?

BTW, I am asking to learn, not because I think it's wrong.

Thanks,
wt

On Fri, Oct 1, 2010 at 5:24 AM, repository service <svn at coreboot.org> wrote:
> Author: stepan
> Date: Fri Oct ?1 14:24:57 2010
> New Revision: 5897
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/5897
>
> Log:
> fix VIA C7 code.
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
> Acked-by: Stefan Reinauer <stepan at coresystems.de>
>
> Modified:
> ? trunk/src/cpu/via/car/cache_as_ram.inc
>
> Modified: trunk/src/cpu/via/car/cache_as_ram.inc
> ==============================================================================
> --- trunk/src/cpu/via/car/cache_as_ram.inc ? ? ?Fri Oct ?1 13:34:05 2010 ? ? ? ?(r5896)
> +++ trunk/src/cpu/via/car/cache_as_ram.inc ? ? ?Fri Oct ?1 14:24:57 2010 ? ? ? ?(r5897)
> @@ -100,7 +100,8 @@
> ? ? ? ? */
> ? ? ? ?movl ? ?$MTRRphysBase_MSR(1), %ecx
> ? ? ? ?xorl ? ?%edx, %edx
> - ? ? ? movl ? ?$(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
> + ? ? ? movl ? ?$REAL_XIP_ROM_BASE, %eax
> + ? ? ? orl ? ? $MTRR_TYPE_WRBACK, %eax
> ? ? ? ?wrmsr
>
> ? ? ? ?movl ? ?$MTRRphysMask_MSR(1), %ecx
> @@ -243,7 +244,8 @@
> ? ? ? ?/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
> ? ? ? ?movl ? ?$MTRRphysBase_MSR(3), %ecx
> ? ? ? ?xorl ? ?%edx, %edx
> - ? ? ? movl ? ?$(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
> + ? ? ? movl ? ?$REAL_XIP_ROM_BASE, %eax
> + ? ? ? orl ? ? $MTRR_TYPE_WRBACK, %eax
> ? ? ? ?wrmsr
>
> ? ? ? ?movl ? ?$MTRRphysMask_MSR(3), %ecx
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From hagigatali at gmail.com  Sat Oct  2 12:19:56 2010
From: hagigatali at gmail.com (ali hagigat)
Date: Sat, 2 Oct 2010 13:49:56 +0330
Subject: [coreboot] BBC EFI story
In-Reply-To: <4CA6EE8D.5030400@coresystems.de>
References: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
	<AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>
	<4CA6EE8D.5030400@coresystems.de>
Message-ID: <AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>

On Sat, Oct 2, 2010 at 12:04 PM, Stefan Reinauer
<stefan.reinauer at coresystems.de> wrote:
> ?On 10/2/10 9:49 AM, ali hagigat wrote:
>>ordered 4 motherboards, over
>> 11000$.
> You made a very bad deal on those mainboards if that's USD. If I
> remember correctly the list price should rather be 1/10th of that for 4
> mainboards.

I have ordered them by Kontron, it is a company in Germany. They do
not sell motherboards, they sell a complete case of a computer and the
price was nearly 2600$(KISS 2U, KISS 4U).

>> gives this information to big BIOS companies ONLY.
> Not so true, other people made it, too. I even explained to you how to
> do it.
Stefan, you are working for a big company and you wrote for me that we
could get that privileged license for documentation hardly after one
year!!

>> At least you could update Wiki pages to state this fact clearly to
>> stop people waste money.
> I doubt we can keep the world from making bad decisions and seeking the fault in others by just putting a few words in a wiki.
>
Many may make this mistake because nobody can study Intel documents in
details to know that there is unexplained parts in the manual before
even getting a board. Now I have made it clear, before i do not think
even one person mentioned the issue.

>Have you even tried to understand
> the public documentation? We have over 50 contributors, so it seems
> others have made it, because they tried. Why don't you?

My plan was to gather a thorough knowledge of one example of Coreboot.
I dislike much to deal with a subject which in incomplete.

from	Corey Osgood <corey.osgood at gmail.com>
to	ali hagigat <hagigatali at gmail.com>
cc	coreboot at coreboot.org
date	Sat, Oct 2, 2010 at 12:30 PM
subject	Re: [coreboot] BBC EFI story

>Most people don't insist on understanding every single line of chipset
>code to port a motherboard. If your chipset is supported, it should be
>relatively easy to port a board to it.

I do not want to port Coreboot first. My immediate purpose was to
study and become proficient in the subject. How I can port Coreboot
without even knowing it and researching on it first.

>I understand that this can be frustrating, but it's something that the >coreboot project has no control over.
>NDA stands for Non-Disclosure Agreement, which means that

At least you could add some lines about NDA story and incomplete data
sheets in Wiki or you could made the following fact clear :

"Anybody who wants to study and learn Coreboot must know that the
documentation of hardware is incomplete and there are some hidden
cases which will never become clear!!"

>Don't blame coreboot for your own misunderstanding. Just because a
>project is open source doesn't mean every bit of data on how the code
>was written has public documentation. The linux kernel (and I imagine
>BSD, solaris, etc) is also open source, but some of the hardware
>supported within doesn't have public datasheets, or the datasheets
>that are public are incomplete.

Linux Kernel contains variety of software structures, techniques and
logic except the architecture, Coreboot is about BIOS and it deals
with hardware directly and mostly, having a complete hardware
documentation is necessary and compulsory for Coreboot while Linux
Kernel have many logical sections apart from architecture and they are
used and learned independently. They are in two different categories
in my opinion.



From patrick at georgi-clan.de  Sat Oct  2 13:04:38 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 02 Oct 2010 13:04:38 +0200
Subject: [coreboot] [commit] r5897 - trunk/src/cpu/via/car
In-Reply-To: <AANLkTinwBddN-xxDB+w_YAsKqJ6xhmfSF_59KZoFCap_@mail.gmail.com>
References: <E1P1efa-0005HU-64@ra.coresystems.de>
	<AANLkTinwBddN-xxDB+w_YAsKqJ6xhmfSF_59KZoFCap_@mail.gmail.com>
Message-ID: <4CA711C6.9010007@georgi-clan.de>

Am 02.10.2010 11:33, schrieb Warren Turkal:
> Stefan,
> 
> Is there a technical reason to split the logical "or" considering that
> the values constants that are known at compile time? It seems like the
> additional orl could be avoided by how the code was before?
> 
> BTW, I am asking to learn, not because I think it's wrong.
With the bootblock, it's not known at compile time - it's resolved at
link time:
- first it's compiled
- then linked at a harmless address (maybe 0? not sure)
- then the size is determined, and a new offset is calculated
- then it's linked again, at the new offset


Patrick



From uwe at hermann-uwe.de  Sat Oct  2 14:43:04 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 2 Oct 2010 14:43:04 +0200
Subject: [coreboot] [PATCH] Drop unneeded header from
 i82371eb_enable_rom.c
In-Reply-To: <AANLkTimqGrjawxPNPti9D6ZixzkOrEY_M8HxPqYoP0ZT@mail.gmail.com>
References: <AANLkTimqGrjawxPNPti9D6ZixzkOrEY_M8HxPqYoP0ZT@mail.gmail.com>
Message-ID: <20101002124303.GY3256@greenwood>

On Fri, Oct 01, 2010 at 12:31:47AM -0400, Keith Hui wrote:
> A "I am alive" ping kind of patch while I continue to figure out ACPI
> for 440BX boards among other things.
> 
> Drops <stdint.h> from the file. My coreboot still compiles fine
> without it. abuild tested.
> 
> Signed-off-by: Keith Hui <buurin at gmail.com>

Hm, not sure about this one. The file _does_ use stuff from stdint.h
directly, so technically having the #include is correct. On the other
hand, that .c file is included itself from romstage.c usually and
that file already #includes stdint.h (directly or indirectly itself).

Note that we're currently trying to move away from including .c files
directly, as soon as that is done and the files are compiled separately
the #include may very well be required then (well, I think).


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Sat Oct  2 14:51:38 2010
From: svn at coreboot.org (repository service)
Date: Sat, 02 Oct 2010 14:51:38 +0200
Subject: [coreboot] [commit] r5904 - trunk/src/northbridge/amd/amdk8
Message-ID: <E1P21Yw-0000L4-QE@ra.coresystems.de>

Author: uwe
Date: Sat Oct  2 14:51:38 2010
New Revision: 5904
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5904

Log:
Fix spelling/typos in comments.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/northbridge/amd/amdk8/misc_control.c

Modified: trunk/src/northbridge/amd/amdk8/misc_control.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/misc_control.c	Fri Oct  1 23:48:52 2010	(r5903)
+++ trunk/src/northbridge/amd/amdk8/misc_control.c	Sat Oct  2 14:51:38 2010	(r5904)
@@ -1,6 +1,6 @@
 /* Turn off machine check triggers when reading
- * pci space where there are no devices.
- * This is necessary when scaning the bus for
+ * PCI space where there are no devices.
+ * This is necessary when scanning the bus for
  * devices which is done by the kernel
  *
  * written in 2003 by Eric Biederman
@@ -26,13 +26,13 @@
  *
  * @param
  *
- * There is only one AGP aperture resource needed. The resoruce is added to
+ * There is only one AGP aperture resource needed. The resource is added to
  * the northbridge of BSP.
  *
  * The same trick can be used to augment legacy VGA resources which can
- * be detect by generic pci reousrce allocator for VGA devices.
+ * be detect by generic PCI resource allocator for VGA devices.
  * BAD: it is more tricky than I think, the resource allocation code is
- * implemented in a way to NOT DOING legacy VGA resource allcation on
+ * implemented in a way to NOT DOING legacy VGA resource allocation on
  * purpose :-(.
  */
 static void mcf3_read_resources(device_t dev)
@@ -42,7 +42,7 @@
 	/* Read the generic PCI resources */
 	pci_dev_read_resources(dev);
 
-	/* If we are not the first processor don't allocate the gart apeture */
+	/* If we are not the first processor don't allocate the GART aperture */
 	if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
 		return;
 	}
@@ -51,7 +51,7 @@
 	get_option(&iommu, "iommu");
 
 	if (iommu) {
-		/* Add a Gart apeture resource */
+		/* Add a GART aperture resource */
 		resource = new_resource(dev, 0x94);
 		resource->size = CONFIG_AGP_APERTURE_SIZE;
 		resource->align = log2(resource->size);
@@ -79,7 +79,7 @@
 		/* Get the base address */
 		gart_base = ((resource->base) >> 25) & 0x00007fff;
 
-		/* Update the other northbriges */
+		/* Update the other northbridges */
 		pdev = 0;
 		while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
 			/* Store the GART size but don't enable it */



From uwe at hermann-uwe.de  Sat Oct  2 14:48:55 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 2 Oct 2010 14:48:55 +0200
Subject: [coreboot] [patch] spelling fixes for comments in
 src/northbridge/amd/amdk8/misc_control.c
In-Reply-To: <20100930232629.GA12447@tarantulon.kollasch.net>
References: <20100930232629.GA12447@tarantulon.kollasch.net>
Message-ID: <20101002124855.GZ3256@greenwood>

On Thu, Sep 30, 2010 at 11:26:29PM +0000, Jonathan A. Kollasch wrote:
> Fix spelling/typos in comments.
> 
> Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>

Thanks, r5904.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Sat Oct  2 16:10:09 2010
From: svn at coreboot.org (repository service)
Date: Sat, 02 Oct 2010 16:10:09 +0200
Subject: [coreboot] [commit] r5905 - in trunk/src/mainboard: asus/a8v-e_se
	asus/m2v-mx_se msi/ms9282
Message-ID: <E1P22mv-0002Lq-FF@ra.coresystems.de>

Author: uwe
Date: Sat Oct  2 16:10:08 2010
New Revision: 5905
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5905

Log:
Don't define K8_4RANK_DIMM_SUPPORT, nothing uses it.

All these boards define QRANK_DIMM_SUPPORT anyway,
which is probably what was meant.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/asus/m2v-mx_se/romstage.c
   trunk/src/mainboard/msi/ms9282/romstage.c

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Sat Oct  2 14:51:38 2010	(r5904)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Sat Oct  2 16:10:08 2010	(r5905)
@@ -98,8 +98,6 @@
 // defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"
 
-#define K8_4RANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Sat Oct  2 14:51:38 2010	(r5904)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Sat Oct  2 16:10:08 2010	(r5905)
@@ -80,8 +80,6 @@
 // defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"
 
-#define K8_4RANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c	Sat Oct  2 14:51:38 2010	(r5904)
+++ trunk/src/mainboard/msi/ms9282/romstage.c	Sat Oct  2 16:10:08 2010	(r5905)
@@ -95,8 +95,6 @@
        return smbus_read_byte(device, address);
 }
 
-//#define K8_4RANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/amdk8_f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"



From uwe at hermann-uwe.de  Sat Oct  2 16:07:39 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 2 Oct 2010 16:07:39 +0200
Subject: [coreboot] [patch] drop meaningless K8_4RANK_DIMM_SUPPORT define
In-Reply-To: <20101001010326.GB12447@tarantulon.kollasch.net>
References: <20101001010326.GB12447@tarantulon.kollasch.net>
Message-ID: <20101002140739.GA3256@greenwood>

On Fri, Oct 01, 2010 at 01:03:27AM +0000, Jonathan A. Kollasch wrote:
> Don't define K8_4RANK_DIMM_SUPPORT, nothing uses it.
> All these boards define QRANK_DIMM_SUPPORT anyway,
> which is probably what was meant.

Indeed.

 
> Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>

Thanks, r5905.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From gregg.drwho8 at gmail.com  Sat Oct  2 16:15:52 2010
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sat, 2 Oct 2010 10:15:52 -0400
Subject: [coreboot] Trac spam
Message-ID: <AANLkTikbg52bjkG2rUbA8kBoQ1qARnhUKjDeRroYjGMU@mail.gmail.com>

Hello!
This is getting monotonous. It seems every time a trac entry is
updated, it aquires some blockhead's random example of junk. In this
case its #163. Now I realize that everyone does know about them, but I
am simply bringing it up so that we can get the matter resolved.

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From stefan.reinauer at coresystems.de  Sat Oct  2 17:11:52 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Oct 2010 17:11:52 +0200
Subject: [coreboot] Trac spam
In-Reply-To: <AANLkTikbg52bjkG2rUbA8kBoQ1qARnhUKjDeRroYjGMU@mail.gmail.com>
References: <AANLkTikbg52bjkG2rUbA8kBoQ1qARnhUKjDeRroYjGMU@mail.gmail.com>
Message-ID: <4CA74BB8.6010008@coresystems.de>

 On 10/2/10 4:15 PM, Gregg Levine wrote:
> This is getting monotonous. It seems every time a trac entry is
> updated, it aquires some blockhead's random example of junk. In this
> case its #163. Now I realize that everyone does know about them, but I
> am simply bringing it up so that we can get the matter resolved.
Yes, it sucks!

The alternative is to have people complaining they can't post tickets
without an (svn) account. For some reason the captcha in trac's
spam-filter plugin does not seem to work. If someone knows how to get
this combo working, please drop me a note,...

Stefan




From rminnich at gmail.com  Sat Oct  2 17:16:58 2010
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 Oct 2010 08:16:58 -0700
Subject: [coreboot] BBC EFI story
In-Reply-To: <AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>
References: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
	<AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>
	<4CA6EE8D.5030400@coresystems.de>
	<AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>
Message-ID: <AANLkTik=2RKbgyg7SGzBV+L5qQgk=j8+pA64WpkJC7Hx@mail.gmail.com>

On Sat, Oct 2, 2010 at 3:19 AM, ali hagigat <hagigatali at gmail.com> wrote:


> Stefan, you are working for a big company and you wrote for me that we
> could get that privileged license for documentation hardly after one
> year!!

Stefan's company is hardly a big company.

> Many may make this mistake because nobody can study Intel documents in
> details to know that there is unexplained parts in the manual before
> even getting a board. Now I have made it clear, before i do not think
> even one person mentioned the issue.

I can only say that we have this discussion with people all the time
on this list: "Will my board work".
You made a mistake because you did not ask anyone before you spent
money. You should have done some research.

Other people have managed to figure these things out; you could have
too. I don't think you should blame us for your mistake.

ron



From stefan.reinauer at coresystems.de  Sat Oct  2 17:34:58 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Oct 2010 17:34:58 +0200
Subject: [coreboot] RFC: Typed -- was Re: [PATCH] Drop unneeded header from
	i82371eb_enable_rom.c
In-Reply-To: <20101002124303.GY3256@greenwood>
References: <AANLkTimqGrjawxPNPti9D6ZixzkOrEY_M8HxPqYoP0ZT@mail.gmail.com>
	<20101002124303.GY3256@greenwood>
Message-ID: <4CA75122.5000208@coresystems.de>

 On 10/2/10 2:43 PM, Uwe Hermann wrote:
> Hm, not sure about this one. The file _does_ use stuff from stdint.h


What's the general feeling about types... Should we get rid of the
stdint.h usage and go for u8/u16/u32/s8/s16/s32 completely?

Stefan



From uwe at hermann-uwe.de  Sat Oct  2 17:49:48 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 2 Oct 2010 17:49:48 +0200
Subject: [coreboot] [PATCH] AMD SB600 uses a hardcoded USB Debug Port number
Message-ID: <20101002154948.GB3256@greenwood>

See patch.

Will post a patch for changing the port on SB700 soon, on that
southbridge it is indeed possible according to the datasheet.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
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From uwe at hermann-uwe.de  Sat Oct  2 17:52:05 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 2 Oct 2010 17:52:05 +0200
Subject: [coreboot] RFC: Typed -- was Re: [PATCH] Drop unneeded header
 from i82371eb_enable_rom.c
In-Reply-To: <4CA75122.5000208@coresystems.de>
References: <AANLkTimqGrjawxPNPti9D6ZixzkOrEY_M8HxPqYoP0ZT@mail.gmail.com>
	<20101002124303.GY3256@greenwood> <4CA75122.5000208@coresystems.de>
Message-ID: <20101002155205.GC3256@greenwood>

On Sat, Oct 02, 2010 at 05:34:58PM +0200, Stefan Reinauer wrote:
>  On 10/2/10 2:43 PM, Uwe Hermann wrote:
> > Hm, not sure about this one. The file _does_ use stuff from stdint.h
> 
> 
> What's the general feeling about types... Should we get rid of the
> stdint.h usage and go for u8/u16/u32/s8/s16/s32 completely?

Definately, long-term we should use u8 etc. in the whole code base.

However, currently u8 and friends are also defined in our stdint.h so
that's a different issue (or we move the u8 defines).


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From uwe at hermann-uwe.de  Sat Oct  2 18:06:14 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 2 Oct 2010 18:06:14 +0200
Subject: [coreboot] [PATCH] Allow selecting the physical USB Debug Port on
	AMD SB700
Message-ID: <20101002160614.GD3256@greenwood>

See patch.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
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From rminnich at gmail.com  Sat Oct  2 18:11:31 2010
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 Oct 2010 09:11:31 -0700
Subject: [coreboot] RFC: Typed -- was Re: [PATCH] Drop unneeded header
 from i82371eb_enable_rom.c
In-Reply-To: <4CA75122.5000208@coresystems.de>
References: <AANLkTimqGrjawxPNPti9D6ZixzkOrEY_M8HxPqYoP0ZT@mail.gmail.com>
	<20101002124303.GY3256@greenwood> <4CA75122.5000208@coresystems.de>
Message-ID: <AANLkTim7i1k+-v8-DizNheo2c9F6rsfbrEsft-j5xzP0@mail.gmail.com>

On Sat, Oct 2, 2010 at 8:34 AM, Stefan Reinauer
<stefan.reinauer at coresystems.de> wrote:
> ?On 10/2/10 2:43 PM, Uwe Hermann wrote:
>> Hm, not sure about this one. The file _does_ use stuff from stdint.h
>
>
> What's the general feeling about types... Should we get rid of the
> stdint.h usage and go for u8/u16/u32/s8/s16/s32 completely?


I always felt we should get rid of stdint.h and define our own. Using
stdint.h leaves you hostage to whatever the gcc guys may do with that
file in the future.

ron



From kevin at koconnor.net  Sat Oct  2 18:43:23 2010
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 2 Oct 2010 12:43:23 -0400
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <4CA65C1B.3090908@coresystems.de>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
Message-ID: <20101002164323.GA10337@morn.localdomain>

On Sat, Oct 02, 2010 at 12:09:31AM +0200, Stefan Reinauer wrote:
>  On 10/1/10 11:27 PM, Uwe Hermann wrote:
> > See patch.
> >
> > abuilt-tested.
> >
> >
> > Uwe.
> IMHO the patch makes it really hard to actually see what the code does.
> I think Idwer was recently running into a problem where the use of
> post_code would trash %eax were hard to comprehend. Now we seem have a
> lot more code that comes from somewhere else and touches registers
> without it being obvious to the reader of the code.
> 
> Just my 2ct.

Well, lets make it 4cts.

I think the code is easier to read when it is all right there.  The
CAR code is doing something very complex - trying to abstract out a
few minor operations I think could further obscure what is occurring.

-Kevin



From peter at stuge.se  Sat Oct  2 20:09:49 2010
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Oct 2010 20:09:49 +0200
Subject: [coreboot] Trac spam
In-Reply-To: <4CA74BB8.6010008@coresystems.de>
References: <AANLkTikbg52bjkG2rUbA8kBoQ1qARnhUKjDeRroYjGMU@mail.gmail.com>
	<4CA74BB8.6010008@coresystems.de>
Message-ID: <20101002180949.5810.qmail@stuge.se>

Stefan Reinauer wrote:
> > I am simply bringing it up so that we can get the matter resolved.

Gregg, it is not really so easy to resolve. We do want the bug
tracker to be easy to add information to.


> Yes, it sucks!

So far I don't think it's too bad, but there will be more of course.


> The alternative is to have people complaining they can't post tickets
> without an (svn) account.

Maybe a Trac account would be sufficient. I'm run other Trac
instances with the requirement that an account is created (with email
address, so that people will receive ticket updates) and the email
address must be verified (random string link in email) before the
account can actually use Trac. This works well so far.

Sandia have developed a Trac plugin to allow moderators to process
all input to Trac, it looks good, but it seems to fit the best only
when the group of moderators is very much homogenous, and when
everyone have equal desire to help with moderation. I was hesitant to
implement it in other Tracs.


> For some reason the captcha in trac's spam-filter plugin does not
> seem to work. If someone knows how to get this combo working,
> please drop me a note,...

What's the failure mode? One spam filter plugin has this scoring
system where a captcha is only one source of points. Maybe it needs
more configuration? Let's take it off-list.


//Peter



From rminnich at gmail.com  Sat Oct  2 20:27:19 2010
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 Oct 2010 11:27:19 -0700
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <20101002164323.GA10337@morn.localdomain>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
	<20101002164323.GA10337@morn.localdomain>
Message-ID: <AANLkTin_4_-cW9x5C6C3dzvRpqtve2_V9EMbnfWg8zwW@mail.gmail.com>

On Sat, Oct 2, 2010 at 9:43 AM, Kevin O'Connor <kevin at koconnor.net> wrote:

> I think the code is easier to read when it is all right there. ?The
> CAR code is doing something very complex - trying to abstract out a
> few minor operations I think could further obscure what is occurring.

I agree with Kevin on this one. The CAR code is basically write-once.
It changes almost never. Rules about common code don't really apply
quite so much.

I find the non-abstracted version much easier to understand.

ron



From peter at stuge.se  Sat Oct  2 20:57:50 2010
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Oct 2010 20:57:50 +0200
Subject: [coreboot] Intel datasheets require NDAs
In-Reply-To: <AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>
References: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
	<AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>
	<4CA6EE8D.5030400@coresystems.de>
	<AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>
Message-ID: <20101002185750.11610.qmail@stuge.se>

ali hagigat wrote:
> >> At least you could update Wiki pages to state this fact clearly
> >> to stop people waste money.
> >
> > I doubt we can keep the world from making bad decisions and
> > seeking the fault in others by just putting a few words in a
> > wiki.
> 
> Many may make this mistake because nobody can study Intel documents
> in details to know that there is unexplained parts in the manual
> before even getting a board. Now I have made it clear, before i do
> not think even one person mentioned the issue.

I have personally talked about this on many occasions, in several
presentations which were recorded and are now linked to from the
wiki, on the mailing list and in the IRC channel in previous
discussions, and finally whenever I discuss documentation aspects
with anyone in person at what is by now numerous occasions where I've
shown coreboot at open source exhibitions.

I believe "the issue" that you refer to is that working with code on
the firmware level requires specific information about the hardware.

As was pointed out, this is not a fact which coreboot decides over,
it's up to the vendors of CPUs and chipsets, ie. electronic components.

Anyone with a background in the electronics industry will know that
20-30 years ago (or even more recent) vendors were very proud to
publish documentation about their products, as a way to demonstrate
their capabilities and benefits over their competition.

Some companies still do. Looking at the market for individual simpler
ICs you will find that most vendors publish great datasheets for
their components. I spent some time evaluating different AD and DA
converters from one such company yesterday.

The world of PC components was similar, but the trend is that more
and more of the inner workings of PCs are becoming too complex for
many to dare to publish information, without the NDAs.

I understand that this fact is completely unknown to someone who is
new to the electronics field in general or the PC electronics field
in particular.

However, coreboot does have a lot of documentation (maybe too much)
and the participants are extraordinarily helpful to those who are
interested and willing to learn about this wonderful world.

The wiki does have a page with links to datasheets. The page is
called Datasheets. It's here: http://www.coreboot.org/Datasheets

In your reading of the wiki I am sure that you've come across this
page. As you may have noticed, there are almost no links to Intel
components at all on that page. The majority of documentation is
about AMD components, with VIA coming in as number two. There are
also links to datasheets for various smaller superio components.

I think this should have been a clue to you that all vendors do not
have exactly the same policy, and further I think it should have
made you realize that Intel hardware may not be the best candidate
if your desire is to study and learn about every register write that
is performed in the coreboot code.

Now, the i945 code in coreboot is still there and still readable,
even if it does not come with a book about how it was written and how
it is structured. I don't think these things are really needed
either. The code is really nicely written, function names are
descriptive, and I believe that by cross-referencing the i945 code
with datasheets for components from other vendors at a similar level
of performance there is still a lot that you will be able to learn!

I assume that you have some plan for how to use your 4 KISS systems,
and this is still very much possible of course. Since you have
hardware that you can not study in detail maybe you can at least make
good use of it by focusing more on what happens after coreboot,
instead of what happens within coreboot if that is not something you
can do without documentation in hand.


> My plan was to gather a thorough knowledge of one example of Coreboot.
> I dislike much to deal with a subject which in incomplete.

Believe me when I say that no one board will be a good way to learn
about all of coreboot. Over two hundred mainboards are supported by
coreboot, and as you may learn there are immense differences between
e.g. an Intel i945 platform, and an AMD GeodeLX platform. Just like
with programming languages; any time you spend on one thing will help
you become more proficient with programming in general.


> I do not want to port Coreboot first. My immediate purpose was to
> study and become proficient in the subject. How I can port Coreboot
> without even knowing it and researching on it first.

The norm has been that people learn about coreboot while working on
it. In my experience it is more difficult but more importantly
extremely inefficient to learn about something without actually doing
it. I'm a firm believer in learning by doing. Otherwise something may
have been learned, but it will not neccessarily be understood.

If you have more of an academic inclination, then like others have
mentioned, I think it would have been wise to ask questions, and ask
the important questions. It seems to me that when you started with
this project you needed to become more familiar among other things
with GNU make, and that is just one of many tools which the coreboot
project builds upon.

The fact that something as "simple" as the build system was already
requiring learning more about some tool would have indicated to me
that I would be forced to do a lot of research to really understand
the project more completely.


> At least you could add some lines about NDA story and incomplete
> data sheets in Wiki

I think this is a really good idea. On which page do you think it it
would fit best? Datasheets? Documentation?


> or you could made the following fact clear :
> 
> "Anybody who wants to study and learn Coreboot must know that the
> documentation of hardware is incomplete and there are some hidden
> cases which will never become clear!!"

This is not a fact at all. This is your assumption, and I'm afraid it
isn't correct. If you look at the code for components from other
vendors then I think you will discover that some do actually provide
good and complete documentation. AMD really deserves a mention here.
We all certainly wish that all documentation would be made available
even sooner, so that coreboot no longer has to play catch-up with the
market, but I think the trend is going the right way at AMD.


> Linux Kernel
..
> Coreboot is about BIOS

coreboot is about firmware, not BIOS. I don't know how many times
I've expressed the significate difference between these two concepts.


> They are in two different categories in my opinion.

You will find that many people disagree with that. A large part of
Linux is it's device drivers. Try removing all device drivers from
Linux and see what you have left. It's really not useful at all.

Maybe you have been keeping up-to-date with the situation of drivers
for wireless networkinge devices in open source operating systems.
This is an issue which is really close to people's everyday lives,
and it has been a rather big challenge for all open source OSes. It's
only very recently that Linux has actually managed to attract the
vendors to *help* the project with code and maybe even documentation,
but in general the situation has been exactly the same for a long
time. I have a distinct memory of a presentation 7 years ago about
difficulties faced by FreeBSD developers to learn about how to
program these devices.

You never mentioned what your background is, and if you are used to a
system like Microsoft Windows then I'm not surprised that you find
the open source world very foreign, it is all about "owning the
problem" and really making sure to do enough research in order to
take inforfmed decisions. This of course requires information. If no
information is available, then sure, it can feel like a hopeless
situation, but for coreboot I can absolutely not agree with you that
this would be the case.

Finally, there's of course always the possibility to do reverse
engineering. But that is something that really requires skill, and
extraordinary patience.

I do hope that you can still make use of your computers, even though
you may not be able to find someone who can train you about the
meaning of every register in them.


Kind regards

//Peter



From peter at stuge.se  Sat Oct  2 21:02:38 2010
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Oct 2010 21:02:38 +0200
Subject: [coreboot] [PATCH] AMD SB600 uses a hardcoded USB Debug
	Port	number
In-Reply-To: <20101002154948.GB3256@greenwood>
References: <20101002154948.GB3256@greenwood>
Message-ID: <20101002190238.12130.qmail@stuge.se>

Uwe Hermann wrote:
> AMD SB600 uses a hardcoded USB Debug Port number.
> 
> It cannot be changed via software according to the datasheet, whereas
> this is indeed possible on AMD SB700. I tested using the SB700 mechanism
> on SB600 but it didn't work, so I suspect the datasheet is indeed correct.
> 
> Thus, don't show the kconfig option for selecting the physical USB port
> on the AMD SB600 southbridge.
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

Acked-by: Peter Stuge <peter at stuge.se>



From peter at stuge.se  Sat Oct  2 21:05:14 2010
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Oct 2010 21:05:14 +0200
Subject: [coreboot] [PATCH] Allow selecting the physical USB Debug
	Port	on AMD SB700
In-Reply-To: <20101002160614.GD3256@greenwood>
References: <20101002160614.GD3256@greenwood>
Message-ID: <20101002190514.12453.qmail@stuge.se>

Uwe Hermann wrote:
> Allow selecting the physical USB Debug Port on AMD SB700.
> 
> The AMD SB700 allows changing the physical USB port to be used as
> USB Debug Port, implement support for this.
> 
> Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the
> SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use
> D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices
> currently, AFAICS.
> 
> Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility.
> 
> Untested, but should work.
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

Acked-by: Peter Stuge <peter at stuge.se>


> +++ src/mainboard/asrock/939a785gmh/romstage.c	(Arbeitskopie)
> +++ src/mainboard/gigabyte/ma78gm/romstage.c	(Arbeitskopie)
> +++ src/mainboard/gigabyte/ma785gmt/romstage.c	(Arbeitskopie)
> +++ src/mainboard/amd/mahogany/romstage.c	(Arbeitskopie)
> +++ src/mainboard/amd/mahogany_fam10/romstage.c	(Arbeitskopie)
> +++ src/mainboard/amd/tilapia_fam10/romstage.c	(Arbeitskopie)
> +++ src/mainboard/iei/kino-780am2-fam10/romstage.c	(Arbeitskopie)
> +++ src/mainboard/jetway/pa78vm5/romstage.c	(Arbeitskopie)
> +++ src/mainboard/asus/m4a785-m/romstage.c	(Arbeitskopie)

I hope we can get even more stuff out of romstage.


//Peter



From peter at stuge.se  Sat Oct  2 21:06:05 2010
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Oct 2010 21:06:05 +0200
Subject: [coreboot] RFC: Typed -- was Re: [PATCH] Drop unneeded
	header	from i82371eb_enable_rom.c
In-Reply-To: <4CA75122.5000208@coresystems.de>
References: <AANLkTimqGrjawxPNPti9D6ZixzkOrEY_M8HxPqYoP0ZT@mail.gmail.com>
	<20101002124303.GY3256@greenwood> <4CA75122.5000208@coresystems.de>
Message-ID: <20101002190605.12695.qmail@stuge.se>

Stefan Reinauer wrote:
> What's the general feeling about types... Should we get rid of the
> stdint.h usage and go for u8/u16/u32/s8/s16/s32 completely?

I like the short ones too.


//Peter



From peter at stuge.se  Sat Oct  2 21:10:29 2010
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Oct 2010 21:10:29 +0200
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <AANLkTin_4_-cW9x5C6C3dzvRpqtve2_V9EMbnfWg8zwW@mail.gmail.com>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
	<20101002164323.GA10337@morn.localdomain>
	<AANLkTin_4_-cW9x5C6C3dzvRpqtve2_V9EMbnfWg8zwW@mail.gmail.com>
Message-ID: <20101002191029.13141.qmail@stuge.se>

ron minnich wrote:
> I find the non-abstracted version much easier to understand.

FWIW I think write-once makes it even nicer to have high-level
operations in source code. Since it will change less often (ie. be
less well known) it's a good thing to not need to see every detail
the next time it is looked at.

It seems me and Uwe just can not win this. Too bad.


//Peter



From anders at jenbo.dk  Sat Oct  2 21:25:17 2010
From: anders at jenbo.dk (Anders Jenbo)
Date: Sat, 02 Oct 2010 21:25:17 +0200
Subject: [coreboot] Intel datasheets require NDAs
In-Reply-To: <20101002185750.11610.qmail@stuge.se>
References: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
	<AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>
	<4CA6EE8D.5030400@coresystems.de>
	<AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>
	<20101002185750.11610.qmail@stuge.se>
Message-ID: <1286047517.2089.1.camel@anders-laptop>

I also would like to know what your goal is, this would probably make it
much easyer to tell you what you need to know, instead of you complaning
each time you find you need some thing you didn't know you needed when
you started to do... somehting.

-Anders




From wt at penguintechs.org  Sat Oct  2 21:25:05 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sat, 2 Oct 2010 12:25:05 -0700
Subject: [coreboot] Trac spam
In-Reply-To: <20101002180949.5810.qmail@stuge.se>
References: <AANLkTikbg52bjkG2rUbA8kBoQ1qARnhUKjDeRroYjGMU@mail.gmail.com>
	<4CA74BB8.6010008@coresystems.de> <20101002180949.5810.qmail@stuge.se>
Message-ID: <AANLkTikMDzCWRZ2GSmLpOoVJbKNUNV+Mh2xFHTd5Zv7m@mail.gmail.com>

I know I am probably going to take crap over this suggestion, but why
don't we use something like sourceforge for the ticketing system. It
seems like there is a lot of distraction in maintaining the project
infrastructure like bug tracker, wiki, etc.

Thanks,
wt

On Sat, Oct 2, 2010 at 11:09 AM, Peter Stuge <peter at stuge.se> wrote:
> Stefan Reinauer wrote:
>> > I am simply bringing it up so that we can get the matter resolved.
>
> Gregg, it is not really so easy to resolve. We do want the bug
> tracker to be easy to add information to.
>
>
>> Yes, it sucks!
>
> So far I don't think it's too bad, but there will be more of course.
>
>
>> The alternative is to have people complaining they can't post tickets
>> without an (svn) account.
>
> Maybe a Trac account would be sufficient. I'm run other Trac
> instances with the requirement that an account is created (with email
> address, so that people will receive ticket updates) and the email
> address must be verified (random string link in email) before the
> account can actually use Trac. This works well so far.
>
> Sandia have developed a Trac plugin to allow moderators to process
> all input to Trac, it looks good, but it seems to fit the best only
> when the group of moderators is very much homogenous, and when
> everyone have equal desire to help with moderation. I was hesitant to
> implement it in other Tracs.
>
>
>> For some reason the captcha in trac's spam-filter plugin does not
>> seem to work. If someone knows how to get this combo working,
>> please drop me a note,...
>
> What's the failure mode? One spam filter plugin has this scoring
> system where a captcha is only one source of points. Maybe it needs
> more configuration? Let's take it off-list.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From wt at penguintechs.org  Sat Oct  2 21:27:58 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sat, 2 Oct 2010 12:27:58 -0700
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <20101002191029.13141.qmail@stuge.se>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
	<20101002164323.GA10337@morn.localdomain>
	<AANLkTin_4_-cW9x5C6C3dzvRpqtve2_V9EMbnfWg8zwW@mail.gmail.com>
	<20101002191029.13141.qmail@stuge.se>
Message-ID: <AANLkTi=ac6rjfAXEHUaFvKSuLv_geG74w9sMmAu5pe57@mail.gmail.com>

I think that making arguments against this code on grounds that it
doesn't feel like other common code is a little shortsighted. When
bugs are fixed in one bit of code, we should be able to take advantage
of those in other parts of code. For instance, I just had to
copy/paste some CPP logic to fix the via/vt8454c CAR init due to a
tiny bootblock. That would have already been fixed had the via and amd
logic been unified since they are basically identical bits of code.

Thanks,
wt

On Sat, Oct 2, 2010 at 12:10 PM, Peter Stuge <peter at stuge.se> wrote:
> ron minnich wrote:
>> I find the non-abstracted version much easier to understand.
>
> FWIW I think write-once makes it even nicer to have high-level
> operations in source code. Since it will change less often (ie. be
> less well known) it's a good thing to not need to see every detail
> the next time it is looked at.
>
> It seems me and Uwe just can not win this. Too bad.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From rminnich at gmail.com  Sat Oct  2 21:38:35 2010
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 Oct 2010 12:38:35 -0700
Subject: [coreboot] Trac spam
In-Reply-To: <AANLkTikMDzCWRZ2GSmLpOoVJbKNUNV+Mh2xFHTd5Zv7m@mail.gmail.com>
References: <AANLkTikbg52bjkG2rUbA8kBoQ1qARnhUKjDeRroYjGMU@mail.gmail.com>
	<4CA74BB8.6010008@coresystems.de>
	<20101002180949.5810.qmail@stuge.se>
	<AANLkTikMDzCWRZ2GSmLpOoVJbKNUNV+Mh2xFHTd5Zv7m@mail.gmail.com>
Message-ID: <AANLkTimqqx1OQ69_hQ4FoQG11AaErSrTfWuCV_4cjrnw@mail.gmail.com>

On Sat, Oct 2, 2010 at 12:25 PM, Warren Turkal <wt at penguintechs.org> wrote:
> I know I am probably going to take crap over this suggestion, but why
> don't we use something like sourceforge for the ticketing system. It
> seems like there is a lot of distraction in maintaining the project
> infrastructure like bug tracker, wiki, etc.


no crap at all, just that we've come full circle :-)

we started out on sourceforge in 1999 but it just did no do the job ...

ron



From rminnich at gmail.com  Sat Oct  2 21:42:51 2010
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 Oct 2010 12:42:51 -0700
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <AANLkTi=ac6rjfAXEHUaFvKSuLv_geG74w9sMmAu5pe57@mail.gmail.com>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
	<20101002164323.GA10337@morn.localdomain>
	<AANLkTin_4_-cW9x5C6C3dzvRpqtve2_V9EMbnfWg8zwW@mail.gmail.com>
	<20101002191029.13141.qmail@stuge.se>
	<AANLkTi=ac6rjfAXEHUaFvKSuLv_geG74w9sMmAu5pe57@mail.gmail.com>
Message-ID: <AANLkTim+bRVyP3wgexUqk0DmVc0EBFKD9AMRL5b8D6Tt@mail.gmail.com>

On Sat, Oct 2, 2010 at 12:27 PM, Warren Turkal <wt at penguintechs.org> wrote:
> I think that making arguments against this code on grounds that it
> doesn't feel like other common code is a little shortsighted. When
> bugs are fixed in one bit of code, we should be able to take advantage
> of those in other parts of code. For instance, I just had to
> copy/paste some CPP logic to fix the via/vt8454c CAR init due to a
> tiny bootblock. That would have already been fixed had the via and amd
> logic been unified since they are basically identical bits of code.


well, you have to be careful. We've had more than one problem with
"common" code that was not so common. CAR is so tricky, and one
platform changes may break another platform in ways we don't expect.
CAR, in fact, scares me. It's fragile. I'm particularly concerned
about the idea of unifying via and amd code. The changes some
well-intentioned people made years ago to some via northbridge code to
"clean it up" -- it broke many things -- are still fresh in my mind.

I contribute very little code at this point, really zero in the last
year, so I don't believe my opinions should be taken that seriously
:-) I'm really more than anything recommending you all to be very
careful. Anything you do to CAR needs to be extensively tested.

So let's call it my .01, not my .02 :-)

ron



From david.hendricks at gmail.com  Sat Oct  2 21:38:22 2010
From: david.hendricks at gmail.com (David Hendricks)
Date: Sat, 2 Oct 2010 12:38:22 -0700
Subject: [coreboot] BBC EFI story
In-Reply-To: <AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>
References: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
	<AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>
	<4CA6EE8D.5030400@coresystems.de>
	<AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>
Message-ID: <AANLkTikWHG_eUW7tujib5+wH_i0Bk2e=GQiUcmpj_uat@mail.gmail.com>

On Sat, Oct 2, 2010 at 3:19 AM, ali hagigat <hagigatali at gmail.com> wrote:

> >I understand that this can be frustrating, but it's something that the
> >coreboot project has no control over.
> >NDA stands for Non-Disclosure Agreement, which means that
>
> At least you could add some lines about NDA story and incomplete data
> sheets in Wiki or you could made the following fact clear :
>
> "Anybody who wants to study and learn Coreboot must know that the
> documentation of hardware is incomplete and there are some hidden
> cases which will never become clear!!"
>

Check out some of the AMD and VIA platforms supported by Coreboot. Those
vendors have been very helpful in contributing code and opening
documentation necessary to bootstrap their hardware. It's sad that Intel has
not done the same, not even for UEFI, however that is their prerogative.
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From uwe at hermann-uwe.de  Sat Oct  2 22:21:38 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 2 Oct 2010 22:21:38 +0200
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <AANLkTim+bRVyP3wgexUqk0DmVc0EBFKD9AMRL5b8D6Tt@mail.gmail.com>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
	<20101002164323.GA10337@morn.localdomain>
	<AANLkTin_4_-cW9x5C6C3dzvRpqtve2_V9EMbnfWg8zwW@mail.gmail.com>
	<20101002191029.13141.qmail@stuge.se>
	<AANLkTi=ac6rjfAXEHUaFvKSuLv_geG74w9sMmAu5pe57@mail.gmail.com>
	<AANLkTim+bRVyP3wgexUqk0DmVc0EBFKD9AMRL5b8D6Tt@mail.gmail.com>
Message-ID: <20101002202137.GE3256@greenwood>

On Sat, Oct 02, 2010 at 12:42:51PM -0700, ron minnich wrote:
> On Sat, Oct 2, 2010 at 12:27 PM, Warren Turkal <wt at penguintechs.org> wrote:
> > I think that making arguments against this code on grounds that it
> > doesn't feel like other common code is a little shortsighted. When
> > bugs are fixed in one bit of code, we should be able to take advantage
> > of those in other parts of code. For instance, I just had to
> > copy/paste some CPP logic to fix the via/vt8454c CAR init due to a
> > tiny bootblock. That would have already been fixed had the via and amd
> > logic been unified since they are basically identical bits of code.
> 
> 
> well, you have to be careful. We've had more than one problem with
> "common" code that was not so common. CAR is so tricky, and one
> platform changes may break another platform in ways we don't expect.
> CAR, in fact, scares me.

Yes, it scares me too (well, sort of :) It's one of the most complex and
non-obvious pieces of code we have in coreboot. Which makes it even more
important to make this code as clean and easily readable and
understandable as we can. Every little bit helps here, e.g. not open-coding
various asm snippets (in 3 or more slightly different variants) all over
the place is one very good measure to make it less confusing for people
trying to read the code. Less lines in cache_as_ram.inc is good.
Readable macros such as "enable_l2_cache" instead of some open-coded,
harder to understand assembler instructions is good.

High-level "look, here we enable cache"-style code is much better than
"look, here we set bit 2 in CR0, and clear bits 5-6 in some MSR and
write magic value 456 to magic address 123, now please go find the right
datasheet and look up what it actually does".

Of course I'm exagerrating a bit here, but I'm very convinced that
readability is of utmost importance in coreboot code, especially so
in CAR code.


> about the idea of unifying via and amd code.

Yeah, that should be considered very carefully indeed, and only be done
after sufficient testing on hardware (if it's feasible and makes sense
to do it al all, i.e., if the two implementations are >= 90% similar).

But the general idea of unifying similar code (especially if it stems
from copy-pasted code from elsewhere with only minimal customizations)
is very good and very necessary indeed. Yeah, things may break, that's
life. Someone will test it, we'll fix it, problem solved. No reason
to _not_ unify code which can be reasonably unified.

I'm actually planning to unify model_6ex, model_6fx, and model_106cx
CAR implementations myself, but that can be done relatively easily,
as the diff between all three files is just 2-3 simple lines.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From peter at stuge.se  Sat Oct  2 22:32:04 2010
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Oct 2010 22:32:04 +0200
Subject: [coreboot] Trac hosting
In-Reply-To: <AANLkTikMDzCWRZ2GSmLpOoVJbKNUNV+Mh2xFHTd5Zv7m@mail.gmail.com>
References: <AANLkTikbg52bjkG2rUbA8kBoQ1qARnhUKjDeRroYjGMU@mail.gmail.com>
	<4CA74BB8.6010008@coresystems.de>
	<20101002180949.5810.qmail@stuge.se>
	<AANLkTikMDzCWRZ2GSmLpOoVJbKNUNV+Mh2xFHTd5Zv7m@mail.gmail.com>
Message-ID: <20101002203204.22486.qmail@stuge.se>

Warren Turkal wrote:
> why don't we use something like sourceforge

Read their EULA carefully. They're a US company and it is full of
things I for one don't like so much. It's my experience that while
there is a bit of overhead to self-hosting, it's really valuable for
at least someone in the community to have systems access to the
hosted services.


//Peter



From svn at coreboot.org  Sat Oct  2 22:33:56 2010
From: svn at coreboot.org (repository service)
Date: Sat, 02 Oct 2010 22:33:56 +0200
Subject: [coreboot] [commit] r5906 - trunk/src/console
Message-ID: <E1P28mK-0006My-PF@ra.coresystems.de>

Author: uwe
Date: Sat Oct  2 22:33:56 2010
New Revision: 5906
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5906

Log:
AMD SB600 uses a hardcoded USB Debug Port number.

It cannot be changed via software according to the datasheet, whereas
this is indeed possible on AMD SB700. I tested using the SB700 mechanism
on SB600 but it didn't work, so I suspect the datasheet is indeed correct.

Thus, don't show the kconfig option for selecting the physical USB port
on the AMD SB600 southbridge.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/console/Kconfig

Modified: trunk/src/console/Kconfig
==============================================================================
--- trunk/src/console/Kconfig	Sat Oct  2 16:10:08 2010	(r5905)
+++ trunk/src/console/Kconfig	Sat Oct  2 22:33:56 2010	(r5906)
@@ -112,13 +112,13 @@
 
 	  If unsure, say N.
 
-# Note: This option doesn't make sense on Intel ICH southbridges as those
-# hardcode the physical USB port to be used as Debug Port to 1. It cannot
-# be changed by coreboot.
+# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges
+# as those hardcode the physical USB port to be used as Debug Port to 1.
+# It cannot be changed by coreboot.
 config USBDEBUG_DEFAULT_PORT
 	int "Default USB port to use as Debug Port"
 	default 1
-	depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX
+	depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600
 	help
 	  This option selects which physical USB port coreboot will try to
 	  use as EHCI Debug Port first (valid values are: 1-15).



From svn at coreboot.org  Sat Oct  2 22:35:41 2010
From: svn at coreboot.org (coreboot)
Date: Sat, 02 Oct 2010 20:35:41 -0000
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
Message-ID: <058.7f5ae1ee229c276cb13c505d6b565e88@coreboot.org>

#163: Board still requires RAMBASE <1MB
-----------------------------------------+----------------------------------
    Reporter:  oxygene                   |          Owner:  stepan@?             
        Type:  defect                    |         Status:  closed               
    Priority:  minor                     |      Milestone:                       
   Component:  coreboot                  |     Resolution:  fixed                
    Keywords:                            |   Dependencies:                       
Patch Status:  patch has been committed  |  
-----------------------------------------+----------------------------------

Comment (by Traficfoxs):

 Hello there :D
 <a href=http://www.triluliludownload.info>Trilulilu Download</a>

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/163#comment:5>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Sat Oct  2 22:36:29 2010
From: svn at coreboot.org (repository service)
Date: Sat, 02 Oct 2010 22:36:29 +0200
Subject: [coreboot] [commit] r5907 - in trunk/src: mainboard/amd/mahogany
	mainboard/amd/mahogany_fam10 mainboard/amd/tilapia_fam10
	mainboard/asrock/939a785gmh mainboard/asus/m4a785-m
	mainboard/gigabyte/ma785gmt mainbo...
Message-ID: <E1P28on-0001Xo-S7@ra.coresystems.de>

Author: uwe
Date: Sat Oct  2 22:36:26 2010
New Revision: 5907
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5907

Log:
Allow selecting the physical USB Debug Port on AMD SB700.

The AMD SB700 allows changing the physical USB port to be used as
USB Debug Port, implement support for this.

Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the
SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use
D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices
currently, AFAICS.

Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility.

Untested, but should work.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/amd/mahogany/romstage.c
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/tilapia_fam10/romstage.c
   trunk/src/mainboard/asrock/939a785gmh/romstage.c
   trunk/src/mainboard/asus/m4a785-m/romstage.c
   trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
   trunk/src/mainboard/gigabyte/ma78gm/romstage.c
   trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
   trunk/src/mainboard/jetway/pa78vm5/romstage.c
   trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c

Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c	Sat Oct  2 22:33:56 2010	(r5906)
+++ trunk/src/mainboard/amd/mahogany/romstage.c	Sat Oct  2 22:36:26 2010	(r5907)
@@ -128,7 +128,7 @@
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Sat Oct  2 22:33:56 2010	(r5906)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Sat Oct  2 22:36:26 2010	(r5907)
@@ -145,7 +145,7 @@
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Sat Oct  2 22:33:56 2010	(r5906)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Sat Oct  2 22:36:26 2010	(r5907)
@@ -145,7 +145,7 @@
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c	Sat Oct  2 22:33:56 2010	(r5906)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c	Sat Oct  2 22:36:26 2010	(r5907)
@@ -182,7 +182,7 @@
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c	Sat Oct  2 22:33:56 2010	(r5906)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c	Sat Oct  2 22:36:26 2010	(r5907)
@@ -146,7 +146,7 @@
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Sat Oct  2 22:33:56 2010	(r5906)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Sat Oct  2 22:36:26 2010	(r5907)
@@ -141,7 +141,7 @@
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Sat Oct  2 22:33:56 2010	(r5906)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Sat Oct  2 22:36:26 2010	(r5907)
@@ -145,7 +145,7 @@
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Sat Oct  2 22:33:56 2010	(r5906)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Sat Oct  2 22:36:26 2010	(r5907)
@@ -148,7 +148,7 @@
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c	Sat Oct  2 22:33:56 2010	(r5906)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c	Sat Oct  2 22:36:26 2010	(r5907)
@@ -152,7 +152,7 @@
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

Modified: trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c	Sat Oct  2 22:33:56 2010	(r5906)
+++ trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c	Sat Oct  2 22:36:26 2010	(r5907)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,22 +26,39 @@
 #define EHCI_BAR_INDEX		0x10		/* TODO: DBUG_PRT[31:29] */
 #define EHCI_DEBUG_OFFSET	0xE0		/* Hardcoded to 0xE0 */
 
-/* Required for successful build, but currently empty. */
+#define EHCI_EOR		(EHCI_BAR + 0x20)
+#define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
+
 void set_debug_port(unsigned int port)
 {
-	/* TODO: Allow changing the physical USB port used as Debug Port. */
+	u32 reg32;
+
+	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
+	reg32 = read32(DEBUGPORT_MISC_CONTROL);
+	reg32 &= ~(0xf << 28);
+	reg32 |= (port << 28);
+	reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
+	write32(DEBUGPORT_MISC_CONTROL, reg32);
 }
 
+/*
+ * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
+ * This code currently only supports the first one, i.e., USB Debug devices
+ * attached to physical USB ports belonging to the first EHCI device.
+ */
 static void sb700_enable_usbdebug(unsigned int port)
 {
-	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
-
-	/* Select the requested physical USB port (1-15) as the Debug Port. */
-	set_debug_port(port);
+	device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
 
 	/* Set the EHCI BAR address. */
 	pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
 
 	/* Enable access to the EHCI memory space registers. */
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+	/*
+	* Select the requested physical USB port (1-15) as the Debug Port.
+	* Must be called after the EHCI BAR has been set up (see above).
+	*/
+	set_debug_port(port);
 }



From gregg.drwho8 at gmail.com  Sat Oct  2 22:36:52 2010
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sat, 2 Oct 2010 16:36:52 -0400
Subject: [coreboot] Trac hosting
In-Reply-To: <20101002203204.22486.qmail@stuge.se>
References: <AANLkTikbg52bjkG2rUbA8kBoQ1qARnhUKjDeRroYjGMU@mail.gmail.com>
	<4CA74BB8.6010008@coresystems.de>
	<20101002180949.5810.qmail@stuge.se>
	<AANLkTikMDzCWRZ2GSmLpOoVJbKNUNV+Mh2xFHTd5Zv7m@mail.gmail.com>
	<20101002203204.22486.qmail@stuge.se>
Message-ID: <AANLkTi=hmyNrX2O6mAR2qN9MnNy9rqagtp4gWWcS5cCK@mail.gmail.com>

On Sat, Oct 2, 2010 at 4:32 PM, Peter Stuge <peter at stuge.se> wrote:
> Warren Turkal wrote:
>> why don't we use something like sourceforge
>
> Read their EULA carefully. They're a US company and it is full of
> things I for one don't like so much. It's my experience that while
> there is a bit of overhead to self-hosting, it's really valuable for
> at least someone in the community to have systems access to the
> hosted services.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
Hello!
Peter is right. I did read their EULA about the same time I discovered
the ancestor to Coreboot, and created an identity over there. It has
more fallacies then the ones that Microsoft insists we assert the
importance of before using their products.

And in an earlier one, Ron confirms that we did indeed use it, at the
same time period. Nothing done there but gather the electronic
equivalent of dust.

Now let's see what does happen concerning Trac. I freely admit
cleaning it up must be better then having to reset the Wiki every day.
Is that happening folks?!?!?
-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From c-d.hailfinger.devel.2006 at gmx.net  Sat Oct  2 22:49:28 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 02 Oct 2010 22:49:28 +0200
Subject: [coreboot] RFC: Typed -- was Re: [PATCH] Drop unneeded	header
 from i82371eb_enable_rom.c
In-Reply-To: <20101002190605.12695.qmail@stuge.se>
References: <AANLkTimqGrjawxPNPti9D6ZixzkOrEY_M8HxPqYoP0ZT@mail.gmail.com>	<20101002124303.GY3256@greenwood>
	<4CA75122.5000208@coresystems.de>
	<20101002190605.12695.qmail@stuge.se>
Message-ID: <4CA79AD8.1070104@gmx.net>

On 02.10.2010 21:06, Peter Stuge wrote:
> Stefan Reinauer wrote:
>   
>> What's the general feeling about types... Should we get rid of the
>> stdint.h usage and go for u8/u16/u32/s8/s16/s32 completely?
>>     
>
> I like the short ones too.
>   

+1

Regards,
Carl-Daniel



From svn at coreboot.org  Sat Oct  2 22:51:30 2010
From: svn at coreboot.org (repository service)
Date: Sat, 02 Oct 2010 22:51:30 +0200
Subject: [coreboot] [commit] r5908 - in trunk/src/cpu: amd/car intel/car
	intel/model_106cx intel/model_6ex intel/model_6fx via/car
Message-ID: <E1P293K-00086W-Hy@ra.coresystems.de>

Author: uwe
Date: Sat Oct  2 22:51:29 2010
New Revision: 5908
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5908

Log:
Add comments to make it clear why these two lines are written like that:

  movl    $REAL_XIP_ROM_BASE, %eax
  orl     $MTRR_TYPE_WRBACK, %eax

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/cpu/amd/car/cache_as_ram.inc
   trunk/src/cpu/intel/car/cache_as_ram.inc
   trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
   trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
   trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
   trunk/src/cpu/via/car/cache_as_ram.inc

Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc	Sat Oct  2 22:36:26 2010	(r5907)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc	Sat Oct  2 22:51:29 2010	(r5908)
@@ -269,6 +269,11 @@
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
+	/*
+	 * IMPORTANT: The two lines below can _not_ be written like this:
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr

Modified: trunk/src/cpu/intel/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/car/cache_as_ram.inc	Sat Oct  2 22:36:26 2010	(r5907)
+++ trunk/src/cpu/intel/car/cache_as_ram.inc	Sat Oct  2 22:51:29 2010	(r5908)
@@ -221,6 +221,11 @@
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
+	/*
+	 * IMPORTANT: The two lines below can _not_ be written like this:
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr

Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	Sat Oct  2 22:36:26 2010	(r5907)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	Sat Oct  2 22:51:29 2010	(r5908)
@@ -97,6 +97,11 @@
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
+	/*
+	 * IMPORTANT: The two lines below can _not_ be written like this:
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr

Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Sat Oct  2 22:36:26 2010	(r5907)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Sat Oct  2 22:51:29 2010	(r5908)
@@ -97,6 +97,11 @@
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
+	/*
+	 * IMPORTANT: The two lines below can _not_ be written like this:
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr

Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	Sat Oct  2 22:36:26 2010	(r5907)
+++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	Sat Oct  2 22:51:29 2010	(r5908)
@@ -104,6 +104,11 @@
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
+	/*
+	 * IMPORTANT: The two lines below can _not_ be written like this:
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr

Modified: trunk/src/cpu/via/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/via/car/cache_as_ram.inc	Sat Oct  2 22:36:26 2010	(r5907)
+++ trunk/src/cpu/via/car/cache_as_ram.inc	Sat Oct  2 22:51:29 2010	(r5908)
@@ -97,6 +97,11 @@
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
+	/*
+	 * IMPORTANT: The two lines below can _not_ be written like this:
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr



From c-d.hailfinger.devel.2006 at gmx.net  Sat Oct  2 23:05:17 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 02 Oct 2010 23:05:17 +0200
Subject: [coreboot] Trac spam
In-Reply-To: <AANLkTikMDzCWRZ2GSmLpOoVJbKNUNV+Mh2xFHTd5Zv7m@mail.gmail.com>
References: <AANLkTikbg52bjkG2rUbA8kBoQ1qARnhUKjDeRroYjGMU@mail.gmail.com>	<4CA74BB8.6010008@coresystems.de>
	<20101002180949.5810.qmail@stuge.se>
	<AANLkTikMDzCWRZ2GSmLpOoVJbKNUNV+Mh2xFHTd5Zv7m@mail.gmail.com>
Message-ID: <4CA79E8D.2040600@gmx.net>

On 02.10.2010 21:25, Warren Turkal wrote:
> I know I am probably going to take crap over this suggestion, but why
> don't we use something like sourceforge for the ticketing system. It
> seems like there is a lot of distraction in maintaining the project
> infrastructure like bug tracker, wiki, etc.
>   

I have used sourceforge for a project before, and believe me, it sucks.
Big time. Maybe they fixed some stuff, but the mailing list archives at
sourceforge are still the worst I have ever seen. Even running mbox
files through "more" has better usability.
svn and cvs at sourceforge are usually unreachable or extremely slow,
the download interface is clumsy, and thus the only remaining service
would be a ticket system. No idea if that can be integrated with
coreboot.org, and if that integration would be less work than fixing the
captcha issues with spam in trac (or moderating all trac comments which
contain hyperlinks).

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Sun Oct  3 00:23:23 2010
From: svn at coreboot.org (coreboot)
Date: Sat, 02 Oct 2010 22:23:23 -0000
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
Message-ID: <058.dd1f1bb9e55325f26ae66757eba0a452@coreboot.org>

#163: Board still requires RAMBASE <1MB
-----------------------------------------+----------------------------------
    Reporter:  oxygene                   |          Owner:  stepan@?             
        Type:  defect                    |         Status:  closed               
    Priority:  minor                     |      Milestone:                       
   Component:  coreboot                  |     Resolution:  fixed                
    Keywords:                            |   Dependencies:                       
Patch Status:  patch has been committed  |  
-----------------------------------------+----------------------------------

Comment (by anonymous):

 test

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/163#comment:6>
coreboot <http://www.coreboot.org/>


From c-d.hailfinger.devel.2006 at gmx.net  Sun Oct  3 00:44:19 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 03 Oct 2010 00:44:19 +0200
Subject: [coreboot] coreboot certified hardware
Message-ID: <4CA7B5C3.9000002@gmx.net>

Hi,

I wonder if we want to establish something like the "Designed for
Windows XP" or "Yes it runs with Netware" certificates? It would
certainly be a nice marketing aid for vendors, and at the same time it
would promote coreboot visibility.

If there is interest in such an idea, we will have to decide which
criteria have to be fulfilled to get such a certificate, and if the
certificate has an expiry date and/or is bound to a specific svn revision.
Off the top of my head, I can think of the following criteria:
- coreboot+SeaBIOS works well enough to boot $ENTERPRISE_LINUX,
$ENDUSER_LINUX and Windows 7 (Vista and XP as well?)
- Nvidia and ATI graphics drivers (both free and closed) work if booted
with a coreboot+SeaBIOS image?
- Frequency scaling and the various suspend methods work
- Soft poweroff works
- IRQ routing and all PCI/PCIe/AGP/whatever slots work
- Legacy ports (if present) work
- Fans work well enough (temperature-based scaling if present in the
"normal" BIOS)
- Source for a working coreboot image (including the Kconfig settings
for the board, and possibly NVRAM settings?) is available for free
without NDA
- Board port merged into coreboot svn
- SeaBIOS source code is available
- SeaBIOS code is merged into SeaBIOS git
- flashrom works on the board (no lockdown) or there is a way to boot
unlocked and run flashrom for your image of choice
- At least some serial output (coreboot version) if a serial port
(header) is present, otherwise... USB Debug? Floppy? LPC bus? POST card
on port 82h?

Did I forget something? Are some criteria useless? What would Jane User
expect from a normal mainboard if she didn't know coreboot was running?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From kevin at koconnor.net  Sun Oct  3 01:07:40 2010
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 2 Oct 2010 19:07:40 -0400
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <20101002202137.GE3256@greenwood>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
	<20101002164323.GA10337@morn.localdomain>
	<AANLkTin_4_-cW9x5C6C3dzvRpqtve2_V9EMbnfWg8zwW@mail.gmail.com>
	<20101002191029.13141.qmail@stuge.se>
	<AANLkTi=ac6rjfAXEHUaFvKSuLv_geG74w9sMmAu5pe57@mail.gmail.com>
	<AANLkTim+bRVyP3wgexUqk0DmVc0EBFKD9AMRL5b8D6Tt@mail.gmail.com>
	<20101002202137.GE3256@greenwood>
Message-ID: <20101002230740.GA25564@morn.localdomain>

On Sat, Oct 02, 2010 at 10:21:38PM +0200, Uwe Hermann wrote:
> Yes, it scares me too (well, sort of :) It's one of the most complex and
> non-obvious pieces of code we have in coreboot. Which makes it even more
> important to make this code as clean and easily readable and
> understandable as we can. Every little bit helps here, e.g. not open-coding
> various asm snippets (in 3 or more slightly different variants) all over
> the place is one very good measure to make it less confusing for people
> trying to read the code. Less lines in cache_as_ram.inc is good.
> Readable macros such as "enable_l2_cache" instead of some open-coded,
> harder to understand assembler instructions is good.

I think the three lines of assembler is easier to understand than
"enable_l2_cache".  Assembler isn't C - the macros defined aren't free
abstractions.  (In particular, it's not clear they clobber %eax.)

Again, just my 2ct.

> High-level "look, here we enable cache"-style code is much better than
> "look, here we set bit 2 in CR0, and clear bits 5-6 in some MSR and
> write magic value 456 to magic address 123, now please go find the right
> datasheet and look up what it actually does".

I think the bit definitions, msr addresses, port numbers, and special
addresses should use definitions.  For an example of this from
seabios, see:

http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=src/romlayout.S;h=a4695963cd4b10d1369273aef36562eb7f00dd65;hb=94dc9c49c283cd576c25692d17567035557a2505#l231

-Kevin



From russ at ashlandhome.net  Sun Oct  3 00:48:33 2010
From: russ at ashlandhome.net (Russell Whitaker)
Date: Sat, 2 Oct 2010 15:48:33 -0700 (PDT)
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <058.dd1f1bb9e55325f26ae66757eba0a452@coreboot.org>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
	<058.dd1f1bb9e55325f26ae66757eba0a452@coreboot.org>
Message-ID: <alpine.LNX.2.00.1010021538420.2346@bigred.russwhit.org>


Could you make closed tickets read only? Then if a spammer happens to
pick a closed ticket and he doesn't know why his spam didn't take,
he might think it's a moderated list and just go away.
   Russ




From gregg.drwho8 at gmail.com  Sun Oct  3 01:18:58 2010
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sat, 2 Oct 2010 19:18:58 -0400
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <alpine.LNX.2.00.1010021538420.2346@bigred.russwhit.org>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
	<058.dd1f1bb9e55325f26ae66757eba0a452@coreboot.org>
	<alpine.LNX.2.00.1010021538420.2346@bigred.russwhit.org>
Message-ID: <AANLkTimsqRjv7gaw0aSLFA7hJWoxjUobGk++_J+-Rf50@mail.gmail.com>

On Sat, Oct 2, 2010 at 6:48 PM, Russell Whitaker <russ at ashlandhome.net> wrote:
>
> Could you make closed tickets read only? Then if a spammer happens to
> pick a closed ticket and he doesn't know why his spam didn't take,
> he might think it's a moderated list and just go away.
> ?Russ
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Hello!
We are working on it, Russ, but that's an excellent suggestion. I just
wish I thought of it first.... What say all of you?

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From wt at penguintechs.org  Sun Oct  3 01:28:59 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sat, 2 Oct 2010 16:28:59 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <4CA7B5C3.9000002@gmx.net>
References: <4CA7B5C3.9000002@gmx.net>
Message-ID: <AANLkTik1FboBixuj6ShKA+YfyKh=fdff2cdrnreCsu_u@mail.gmail.com>

I think that a base coreboot certification should basically state that
all the hardware on the board is usable with a major free OS (e.g.
Linux-based OSes like Debian, Ubuntu, and Redhat maybe).

We could maybe have extended certifications for things like non-free
OS and driver compatibility.

My comments below are what I would expect minimum coreboot compliance to mean.

On Sat, Oct 2, 2010 at 3:44 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> I wonder if we want to establish something like the "Designed for
> Windows XP" or "Yes it runs with Netware" certificates? It would
> certainly be a nice marketing aid for vendors, and at the same time it
> would promote coreboot visibility.

Interesting idea. I think that we'd need participation from board
vendors for it to make much sense.

> If there is interest in such an idea, we will have to decide which
> criteria have to be fulfilled to get such a certificate, and if the
> certificate has an expiry date and/or is bound to a specific svn revision.
> Off the top of my head, I can think of the following criteria:
> - coreboot+SeaBIOS works well enough to boot $ENTERPRISE_LINUX,
> $ENDUSER_LINUX and Windows 7 (Vista and XP as well?)

Why should Windows be important criteria? Should we really withhold a
coreboot certification on the condition that a non-free OS work?

> - Nvidia and ATI graphics drivers (both free and closed) work if booted
> with a coreboot+SeaBIOS image?

Frankly, I think that ability to use the free drivers should be good
enough. We shouldn't be hold out any kind of coreboot certification on
the condition that non-free drivers work.

> - Frequency scaling and the various suspend methods work

yes

> - Soft poweroff works

yes

> - IRQ routing and all PCI/PCIe/AGP/whatever slots work

yes

> - Legacy ports (if present) work

How about any ports on the board should work, legacy or not?

> - Fans work well enough (temperature-based scaling if present in the
> "normal" BIOS)

I don't think that we should compare coreboot to the "normal" bios. We
should decide whether this feature is needed or not in a certified
system that is capable of it.

> - Source for a working coreboot image (including the Kconfig settings
> for the board, and possibly NVRAM settings?) is available for free
> without NDA

Yes.

> - Board port merged into coreboot svn

Yes.

> - SeaBIOS source code is available

Yes.

> - SeaBIOS code is merged into SeaBIOS git

Yes. Doesn't this imply the previous item?

> - flashrom works on the board (no lockdown) or there is a way to boot
> unlocked and run flashrom for your image of choice

Yes.

> - At least some serial output (coreboot version) if a serial port
> (header) is present, otherwise... USB Debug? Floppy? LPC bus? POST card
> on port 82h?

I thought that POST cards showed valued outputed on port 80h. What is 82h?

Basically every coreboot system should output POST codes that a POST
card can display if it's possible to insert a POST card.

Any physical ports (including headers for ports) on the board should
be supported.

Thanks,
wt



From corey.osgood at gmail.com  Sun Oct  3 01:29:23 2010
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 2 Oct 2010 16:29:23 -0700
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <AANLkTimsqRjv7gaw0aSLFA7hJWoxjUobGk++_J+-Rf50@mail.gmail.com>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
	<058.dd1f1bb9e55325f26ae66757eba0a452@coreboot.org>
	<alpine.LNX.2.00.1010021538420.2346@bigred.russwhit.org>
	<AANLkTimsqRjv7gaw0aSLFA7hJWoxjUobGk++_J+-Rf50@mail.gmail.com>
Message-ID: <AANLkTinfsQtianVsfRsDg+B-fnMnarnZ+vQYv5k1G6if@mail.gmail.com>

I was thinking of just filtering them by if the email is a member of
the mailing list, and instead of returning an error when the email
isn't a list member (which might pique the spammer's curiousity), just
drop it silently.

-Corey

On Sat, Oct 2, 2010 at 4:18 PM, Gregg Levine <gregg.drwho8 at gmail.com> wrote:
> On Sat, Oct 2, 2010 at 6:48 PM, Russell Whitaker <russ at ashlandhome.net> wrote:
>>
>> Could you make closed tickets read only? Then if a spammer happens to
>> pick a closed ticket and he doesn't know why his spam didn't take,
>> he might think it's a moderated list and just go away.
>> ?Russ
>>
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>
> Hello!
> We are working on it, Russ, but that's an excellent suggestion. I just
> wish I thought of it first.... What say all of you?
>
> -----
> Gregg C Levine gregg.drwho8 at gmail.com
> "This signature fought the Time Wars, time and again."
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From gregg.drwho8 at gmail.com  Sun Oct  3 01:35:06 2010
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sat, 2 Oct 2010 19:35:06 -0400
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <AANLkTinfsQtianVsfRsDg+B-fnMnarnZ+vQYv5k1G6if@mail.gmail.com>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>
	<058.dd1f1bb9e55325f26ae66757eba0a452@coreboot.org>
	<alpine.LNX.2.00.1010021538420.2346@bigred.russwhit.org>
	<AANLkTimsqRjv7gaw0aSLFA7hJWoxjUobGk++_J+-Rf50@mail.gmail.com>
	<AANLkTinfsQtianVsfRsDg+B-fnMnarnZ+vQYv5k1G6if@mail.gmail.com>
Message-ID: <AANLkTikpmhyGe+dFnxWo8H=D4k3ECM0QZifdFkK3zUUF@mail.gmail.com>

On Sat, Oct 2, 2010 at 7:29 PM, Corey Osgood <corey.osgood at gmail.com> wrote:
> I was thinking of just filtering them by if the email is a member of
> the mailing list, and instead of returning an error when the email
> isn't a list member (which might pique the spammer's curiousity), just
> drop it silently.
>
> -Corey
>
> On Sat, Oct 2, 2010 at 4:18 PM, Gregg Levine <gregg.drwho8 at gmail.com> wrote:
>> On Sat, Oct 2, 2010 at 6:48 PM, Russell Whitaker <russ at ashlandhome.net> wrote:
>>>
>>> Could you make closed tickets read only? Then if a spammer happens to
>>> pick a closed ticket and he doesn't know why his spam didn't take,
>>> he might think it's a moderated list and just go away.
>>> ?Russ
>>>
>>>
>>> --
>>> coreboot mailing list: coreboot at coreboot.org
>>> http://www.coreboot.org/mailman/listinfo/coreboot
>>>
>>
>> Hello!
>> We are working on it, Russ, but that's an excellent suggestion. I just
>> wish I thought of it first.... What say all of you?
>>
>> -----
>> Gregg C Levine gregg.drwho8 at gmail.com
>> "This signature fought the Time Wars, time and again."
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>

Hello!
Well that's going to work. As one individual I know would say, "That
sounds logical.". Please note Corey how I closed my original one by
way of response to our correspondent.

Now I remember participating in a LUG discussion on Trac a while ago,
and I actually do not recall what language was used to create it. I'll
probably ask on that list later today. But something needs to be
decided upon and soon.

Let's try both and see which one attracts the most issues.....
-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From wt at penguintechs.org  Sun Oct  3 01:51:31 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sat, 2 Oct 2010 16:51:31 -0700
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <20101002230740.GA25564@morn.localdomain>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
	<20101002164323.GA10337@morn.localdomain>
	<AANLkTin_4_-cW9x5C6C3dzvRpqtve2_V9EMbnfWg8zwW@mail.gmail.com>
	<20101002191029.13141.qmail@stuge.se>
	<AANLkTi=ac6rjfAXEHUaFvKSuLv_geG74w9sMmAu5pe57@mail.gmail.com>
	<AANLkTim+bRVyP3wgexUqk0DmVc0EBFKD9AMRL5b8D6Tt@mail.gmail.com>
	<20101002202137.GE3256@greenwood>
	<20101002230740.GA25564@morn.localdomain>
Message-ID: <AANLkTikHzT2KoYsC5QeUJ21XoL8OKE_edMn7eEyP0FP4@mail.gmail.com>

On Sat, Oct 2, 2010 at 4:07 PM, Kevin O'Connor <kevin at koconnor.net> wrote:
> I think the three lines of assembler is easier to understand than
> "enable_l2_cache". ?Assembler isn't C - the macros defined aren't free
> abstractions. ?(In particular, it's not clear they clobber %eax.)

I definitely agree that clobbering eax is not apparent from the
macros. Maybe we need a documented calling convention that says the
eax register can be destroyed at this point in the coreboot code?

> I think the bit definitions, msr addresses, port numbers, and special
> addresses should use definitions. ?For an example of this from
> seabios, see:

This seems reasonable.

wt



From c-d.hailfinger.devel.2006 at gmx.net  Sun Oct  3 02:06:02 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 03 Oct 2010 02:06:02 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTik1FboBixuj6ShKA+YfyKh=fdff2cdrnreCsu_u@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTik1FboBixuj6ShKA+YfyKh=fdff2cdrnreCsu_u@mail.gmail.com>
Message-ID: <4CA7C8EA.2040501@gmx.net>

On 03.10.2010 01:28, Warren Turkal wrote:
> I think that a base coreboot certification should basically state that
> all the hardware on the board is usable with a major free OS (e.g.
> Linux-based OSes like Debian, Ubuntu, and Redhat maybe).
>
> We could maybe have extended certifications for things like non-free
> OS and driver compatibility.
>   

Well, if we only care about Linux, you can avoid most (if not all) of
ACPI on many machines, and you can avoid SeaBIOS as well. Heck, you
could even avoid FILO and require a Linux kernel in flash. Whether such
ab board would be usable for end users is a totally different question.
IMHO being able to install a Linux distribution from CD is an absolute
must even if you only target professional users in clusters etc.
Windows support means a board is usable by the general population, and
this is something vendors care about deeply. We renamed LinuxBIOS to
coreboot exactly because people said all the time "I don't want Linux",
and EFI marketing would love to make fun of us if we ever said "Linux
only is good enough for certification".


> My comments below are what I would expect minimum coreboot compliance to mean.
>
> On Sat, Oct 2, 2010 at 3:44 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> If there is interest in such an idea, we will have to decide which
>> criteria have to be fulfilled to get such a certificate, and if the
>> certificate has an expiry date and/or is bound to a specific svn revision.
>> Off the top of my head, I can think of the following criteria:
>> - coreboot+SeaBIOS works well enough to boot $ENTERPRISE_LINUX,
>> $ENDUSER_LINUX and Windows 7 (Vista and XP as well?)
>>     
>
> Why should Windows be important criteria? Should we really withhold a
> coreboot certification on the condition that a non-free OS work?
>   

Please see above.


>> - Nvidia and ATI graphics drivers (both free and closed) work if booted
>> with a coreboot+SeaBIOS image?
>>     
>
> Frankly, I think that ability to use the free drivers should be good
> enough. We shouldn't be hold out any kind of coreboot certification on
> the condition that non-free drivers work.
>   

There are two aspects of the problem:
- We can't test everything (fact of life)
- Closed-source drivers have a huge market share, and won't go away any
time soon


>> - Legacy ports (if present) work
>>     
>
> How about any ports on the board should work, legacy or not?
>   

Absolutely. I just wanted to point out that many vendors don't care that
much about legacy anymore.


>> - Fans work well enough (temperature-based scaling if present in the
>> "normal" BIOS)
>>     
>
> I don't think that we should compare coreboot to the "normal" bios. We
> should decide whether this feature is needed or not in a certified
> system that is capable of it.
>   

Fans can be loud. If all fans run at 100% non-stop, machines can be
essentially unusable for noise reasons.


>> - SeaBIOS source code is available
>>     
>
> Yes.
>
>   
>> - SeaBIOS code is merged into SeaBIOS git
>>     
>
> Yes. Doesn't this imply the previous item?
>   

Indeed, but given that vendor code may not always be suitable for
merging, do we want to withhold certification if code is available but
not merged? And what happens if Kevin is on vacation?


>> - At least some serial output (coreboot version) if a serial port
>> (header) is present, otherwise... USB Debug? Floppy? LPC bus? POST card
>> on port 82h?
>>     
>
> I thought that POST cards showed valued outputed on port 80h. What is 82h?
>   

Some POST cards support port 80h/82h/84h and you can decide which port
they should listen to. Some multi-functional POST cards support
reprogramming in a way that allows you to send text output to port
82h/84h and normal POST codes to port 80h.


> Basically every coreboot system should output POST codes that a POST
> card can display if it's possible to insert a POST card.
>
> Any physical ports (including headers for ports) on the board should
> be supported.
>   

Yes.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stefan.reinauer at coresystems.de  Sun Oct  3 03:18:59 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sun, 03 Oct 2010 03:18:59 +0200
Subject: [coreboot] #163: Board still requires RAMBASE <1MB
In-Reply-To: <AANLkTinfsQtianVsfRsDg+B-fnMnarnZ+vQYv5k1G6if@mail.gmail.com>
References: <043.f7c7426094d5eb0bf3d8dbfeb19852e7@coreboot.org>	<058.dd1f1bb9e55325f26ae66757eba0a452@coreboot.org>	<alpine.LNX.2.00.1010021538420.2346@bigred.russwhit.org>	<AANLkTimsqRjv7gaw0aSLFA7hJWoxjUobGk++_J+-Rf50@mail.gmail.com>
	<AANLkTinfsQtianVsfRsDg+B-fnMnarnZ+vQYv5k1G6if@mail.gmail.com>
Message-ID: <4CA7DA03.4090304@coresystems.de>

 On 10/3/10 1:29 AM, Corey Osgood wrote:
> I was thinking of just filtering them by if the email is a member of
> the mailing list, and instead of returning an error when the email
> isn't a list member (which might pique the spammer's curiousity), just
> drop it silently.
>
> -Corey
If someone wants to write a Trac plugin for that I'll gladly give it a try.

Stefan





From gregg.drwho8 at gmail.com  Sun Oct  3 06:13:59 2010
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sun, 3 Oct 2010 00:13:59 -0400
Subject: [coreboot] Fwd: [nylug-talk] Trac questions
In-Reply-To: <Pine.LNX.4.44.1010022349210.25791-100000@bitblit.net>
References: <AANLkTin6ELu+fHQ+4SpE=jQyjLrtwyJ_50LgH6D7P+wW@mail.gmail.com>
	<Pine.LNX.4.44.1010022349210.25791-100000@bitblit.net>
Message-ID: <AANLkTimvucrrw2Rnj25_6qfn8rqzS4gzYTJACtHBwBrd@mail.gmail.com>

Hello!
Folks, this is from a member of the LUG here in NYC. He addresses the
methods that are confusing me, to prevent those spurious tickets from
surfacing. Naturally it is forwarded below my comments. Ron that's the
group that I was interested in having yourself, or one of the members
of the list present a good speech and even a demo or two on coreboot
to.

(Incidentally, he normally doesn't even want to give me the time of
day. Every time I bring up something on the older hardware here, he
acts like something resembling people I can't properly describe
without using four letter language, and I'm not doing it on this this.

I do have here a P4 based system a Dell Optiplex GX170L, and raised
some excellent questions for it, to properly get Slackware 13.1
running properly. I received some excellent help and even better
advice from several people. And he didn't over react.)

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."


---------- Forwarded message ----------
From: Ajai Khattri <ajai at bitblit.net>
Date: Sat, Oct 2, 2010 at 11:51 PM
Subject: Re: [nylug-talk] Trac questions
To: NYLUG Technical Discussion <nylug-talk at nylug.org>


On Sat, 2 Oct 2010, Gregg Levine wrote:

> I remember participating in a LUG meeting with that as its theme but I
> do not recall what it was written with. Or perhaps a related beastie,
> but both apply.

You probably will need to remove anonymous write access to tickets, the
wiki, etc. Very easy if you have the web admin plugin installed. Otherwise
it will fequire running tracadmin from the command-line.



--
A



From peter at stuge.se  Sun Oct  3 06:20:38 2010
From: peter at stuge.se (Peter Stuge)
Date: Sun, 3 Oct 2010 06:20:38 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTik1FboBixuj6ShKA+YfyKh=fdff2cdrnreCsu_u@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTik1FboBixuj6ShKA+YfyKh=fdff2cdrnreCsu_u@mail.gmail.com>
Message-ID: <20101003042038.10709.qmail@stuge.se>

Warren Turkal wrote:
> > - SeaBIOS source code is available
> > - SeaBIOS code is merged into SeaBIOS git
> 
> Yes. Doesn't this imply the previous item?

Heh, no. It's easy to think so, but don't fall into that trap.

Certification requires a fair amount of QA which isn't being done
right now is just my 2.


//Peter



From hagigatali at gmail.com  Sun Oct  3 06:26:38 2010
From: hagigatali at gmail.com (ali hagigat)
Date: Sun, 3 Oct 2010 07:56:38 +0330
Subject: [coreboot] Intel datasheets require NDAs
In-Reply-To: <1286047517.2089.1.camel@anders-laptop>
References: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
	<AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>
	<4CA6EE8D.5030400@coresystems.de>
	<AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>
	<20101002185750.11610.qmail@stuge.se>
	<1286047517.2089.1.camel@anders-laptop>
Message-ID: <AANLkTi=6QyURa0HiTgiSZ9+tL_01znbMhUbRexcgKtu7@mail.gmail.com>

I am afraid those unmentioned registers have a significant effect in
understanding the function and logic of the internal parts of the IC
and the standards used.
First, one must study to know what is going on, how can i work without
having enough information?!
I am not going to keep on complaining but the "incomplete
documentation" may be added to the first page of Wiki, in
www.coreboot.org/Welcome_to_coreboot.

On Sat, Oct 2, 2010 at 10:55 PM, Anders Jenbo <anders at jenbo.dk> wrote:
> I also would like to know what your goal is, this would probably make it
> much easyer to tell you what you need to know, instead of you complaning
> each time you find you need some thing you didn't know you needed when
> you started to do... somehting.
>
> -Anders
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From peter at stuge.se  Sun Oct  3 06:42:24 2010
From: peter at stuge.se (Peter Stuge)
Date: Sun, 3 Oct 2010 06:42:24 +0200
Subject: [coreboot] Intel datasheets require NDAs
In-Reply-To: <AANLkTi=6QyURa0HiTgiSZ9+tL_01znbMhUbRexcgKtu7@mail.gmail.com>
References: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
	<AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>
	<4CA6EE8D.5030400@coresystems.de>
	<AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>
	<20101002185750.11610.qmail@stuge.se>
	<1286047517.2089.1.camel@anders-laptop>
	<AANLkTi=6QyURa0HiTgiSZ9+tL_01znbMhUbRexcgKtu7@mail.gmail.com>
Message-ID: <20101003044224.13006.qmail@stuge.se>

ali hagigat wrote:
> I am afraid those unmentioned registers have a significant effect in
> understanding the function and logic of the internal parts of the IC
> and the standards used.

What function, logic and standards is it you want to understand
better? We may be able to recommend some reading material. If it is
anything but DMI or FSB then I am actually sure that we can do so.
And if it *is* DMI or FSB then I would be curious to know why.

I'm not saying that it is, but if your mission is to create competing
chipsets for Intel platforms then good luck to you, but I don't think
you will find coreboot very helpful, specifically because Intel does
not give out documentation freely. In that case I think you would
have no option other than reverse engineering, and that's just a lot
of wasted time IMO.

As Anders pointed out - we can only actually help you if you can say
what it is that you want to do!


> First, one must study to know what is going on, how can i work
> without having enough information?!

Personally I consider it critical to learn by experimentation, or
empirical studies if you prefer. And again, I think knowing and
understanding are two very different things.


> I am not going to keep on complaining but the "incomplete
> documentation" may be added to the first page of Wiki, in
> www.coreboot.org/Welcome_to_coreboot.

I'm afraid I don't think that is a great idea, because I think the
first page already has too much information.

You did not mention if you had seen the Documentation and Datasheets
pages on the wiki. I think that the latter page in particular might
be a good place to note that different vendors have different policy
about public documentation, but honestly, I think it is very obvious
already!


//Peter



From gregg.drwho8 at gmail.com  Sun Oct  3 07:40:11 2010
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sun, 3 Oct 2010 01:40:11 -0400
Subject: [coreboot] Intel datasheets require NDAs
In-Reply-To: <20101003044224.13006.qmail@stuge.se>
References: <AANLkTinTuTPM8cyx6vwxsN=pvK+ZEsK7RP7thYQQQoe8@mail.gmail.com>
	<AANLkTi=T=sUFoghK-Wg8b3+h_8JGd4s9oGF1fUrZFXTW@mail.gmail.com>
	<4CA6EE8D.5030400@coresystems.de>
	<AANLkTimKJg63UN+XnumDdpiq56_p6jHg9fhZzx8GCj=K@mail.gmail.com>
	<20101002185750.11610.qmail@stuge.se>
	<1286047517.2089.1.camel@anders-laptop>
	<AANLkTi=6QyURa0HiTgiSZ9+tL_01znbMhUbRexcgKtu7@mail.gmail.com>
	<20101003044224.13006.qmail@stuge.se>
Message-ID: <AANLkTi=-x9LB9TK_Pbaf6ieCn-7=8Xkq_u0jAZDY8sE3@mail.gmail.com>

On Sun, Oct 3, 2010 at 12:42 AM, Peter Stuge <peter at stuge.se> wrote:
> ali hagigat wrote:
>> I am afraid those unmentioned registers have a significant effect in
>> understanding the function and logic of the internal parts of the IC
>> and the standards used.
>
> What function, logic and standards is it you want to understand
> better? We may be able to recommend some reading material. If it is
> anything but DMI or FSB then I am actually sure that we can do so.
> And if it *is* DMI or FSB then I would be curious to know why.
>
> I'm not saying that it is, but if your mission is to create competing
> chipsets for Intel platforms then good luck to you, but I don't think
> you will find coreboot very helpful, specifically because Intel does
> not give out documentation freely. In that case I think you would
> have no option other than reverse engineering, and that's just a lot
> of wasted time IMO.
>
> As Anders pointed out - we can only actually help you if you can say
> what it is that you want to do!
>
>
>> First, one must study to know what is going on, how can i work
>> without having enough information?!
>
> Personally I consider it critical to learn by experimentation, or
> empirical studies if you prefer. And again, I think knowing and
> understanding are two very different things.
>
>
>> I am not going to keep on complaining but the "incomplete
>> documentation" may be added to the first page of Wiki, in
>> www.coreboot.org/Welcome_to_coreboot.
>
> I'm afraid I don't think that is a great idea, because I think the
> first page already has too much information.
>
> You did not mention if you had seen the Documentation and Datasheets
> pages on the wiki. I think that the latter page in particular might
> be a good place to note that different vendors have different policy
> about public documentation, but honestly, I think it is very obvious
> already!
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Hello!
Ali, have you mastered the art of installing any Linux distribution
onto a PC? I got started in 1999 when they were beginning to move off
of a pile of floppies for Slackware, (as described on the earlier
releases.) to one or more single CDs. It is a pretty straight forward
affair, the only issue that can surface besides configuring the
necessary services, is to setup the boot methods. I mention that here
because you did not state that either.

After that installing your needed programs, and source code for them.
This is also the way Coreboot is pulled over.

If you haven't, then please do. The commands given in the Wiki that
are necessary function for enabling us to understand your target(s)
are also especially useful. Incidentally I do not reccomend Ubuntu,
there are too many outstanding issues with it. Debian will work, up to
a particular point. SuSe will definitely work as well. Slackware
however is also perfectly suited as I have it running here.

Reason why I am bringing this up is that you have mentioned your
targets, but you haven't mentioned what you're going to be using to
build the image(s) with. Or, and this is quite significant, what your
planned activities will be.

Please also understand that the documention presented here,
http://www.coreboot.org/Datasheets provides an essential collection.
The Intel stuff is limited to the publically acessible collections
they have. The material which is given there for Intel should tell you
everything you need to know. It might even tell you what's what on the
different bridging hardware of the targets you are interested in
making use of.

Sorry group if I spoke up out of turn, but I suddenly realized that he
was in the exact same position I was in, shortly after discovering the
ancestor to this group.
-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From wt at penguintechs.org  Sun Oct  3 09:32:50 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 00:32:50 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <20101003042038.10709.qmail@stuge.se>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTik1FboBixuj6ShKA+YfyKh=fdff2cdrnreCsu_u@mail.gmail.com>
	<20101003042038.10709.qmail@stuge.se>
Message-ID: <AANLkTik_o6OMer5AqbDEjUzbbSRoXNS=OFW8DD9HFuVZ@mail.gmail.com>

On Sat, Oct 2, 2010 at 9:20 PM, Peter Stuge <peter at stuge.se> wrote:
> Warren Turkal wrote:
>> > - SeaBIOS source code is available
>> > - SeaBIOS code is merged into SeaBIOS git
>>
>> Yes. Doesn't this imply the previous item?
>
> Heh, no. It's easy to think so, but don't fall into that trap.

I mean that if we accept that the code in the SeaBIOS git repo is
complete for a given board, can we assume that the code is available?

wt



From hagigatali at gmail.com  Sun Oct  3 11:01:51 2010
From: hagigatali at gmail.com (ali hagigat)
Date: Sun, 3 Oct 2010 12:31:51 +0330
Subject: [coreboot] an AMD based platform
Message-ID: <AANLkTikuZEskNHfxSAsyek3Z4CF1cRbKpCYvnoJn0sBY@mail.gmail.com>

I want to ask the experts about an AMD based motherboard to research
on Coreboot, what you recommend will be valuable or please tell me
what motherboard in the list of supported motherboards of
Wiki-Coreboot is more modern and close to the following attributes:

I am looking for a motherboard with CPU and chip set similar to Intel.
For CPU,  I want it to have IA-32 and IA-32e architecture, I mean 32
bit machine with 64 bit extension to support 32 and also 64 bits
applications, with Vtx (virtual machine capability), muti-core, and
SIMD instructions with front side bus.

About Chipset, I want it to have regular logics of USB, SATA,
PCIExpress, SDRAM controller, FWH/SPI protocol for BIOS chip, PCI
bridge, IOAPIC, Integrated Graphics Controller, real time clock, LPC
interface,....a relatively modern board and superio with open
documentation.

Thank you to read my message.



From wt at penguintechs.org  Sun Oct  3 11:15:44 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 02:15:44 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <4CA7C8EA.2040501@gmx.net>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTik1FboBixuj6ShKA+YfyKh=fdff2cdrnreCsu_u@mail.gmail.com>
	<4CA7C8EA.2040501@gmx.net>
Message-ID: <AANLkTikFnUWUcPRNwy8gw7cB12+egjfE8kkM=vy7+qBg@mail.gmail.com>

On Sat, Oct 2, 2010 at 5:06 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 03.10.2010 01:28, Warren Turkal wrote:
>> I think that a base coreboot certification should basically state that
>> all the hardware on the board is usable with a major free OS (e.g.
>> Linux-based OSes like Debian, Ubuntu, and Redhat maybe).
>>
>> We could maybe have extended certifications for things like non-free
>> OS and driver compatibility.
>>
>
> Well, if we only care about Linux, you can avoid most (if not all) of
> ACPI on many machines, and you can avoid SeaBIOS as well. Heck, you
> could even avoid FILO and require a Linux kernel in flash. Whether such
> ab board would be usable for end users is a totally different question.

Booting into a certain OS is clearly not the only bar that we should
be looking for. It would need to comply with various standards like
ACPI, etc.

> IMHO being able to install a Linux distribution from CD is an absolute
> must even if you only target professional users in clusters etc.

I agree.

> Windows support means a board is usable by the general population, and
> this is something vendors care about deeply.

Out of curiosity, are there actually non-niche vendors that ship
Coreboot as their system firmware?

> We renamed LinuxBIOS to
> coreboot exactly because people said all the time "I don't want Linux",
> and EFI marketing would love to make fun of us if we ever said "Linux
> only is good enough for certification".

I believe that most of the folks who care enough to use Coreboot at
this time are probably running Linux or some other free OS. I also
believe that most developers who have access to systems are probably
running on or have easy access to some free OS. I also know that
non-free OSes are not easily available to everyone. It's not that I
believe that we can't test for non-free software support. It's just
that I believe that certifying the boards for Coreboot should not gate
on that having been done.

Ideally, having some OS independent test suite would be the best
approach I think, but I don't see that getting developed overnight. :)

Maybe we should have multiple compliance levels like "Coreboot
minimal" and "Coreboot standard"? The minimal could be some set of
requirements. The standard could be the minimal requirements plus some
extra set of requirements. We could also have tags for the compliance.
These could be used to indicate special support like Windows or
something like that.

Think of "Coreboot minimal" as enough to conveniently develop coreboot
further without expensive and specialized hardware. Its requirement
might look like the following:
* Full initialization of the cpu and supporting chipset
  - Intialized RAM
  - Cooling systems should work enough to protect the system from
burning itself up
* At least one of the following:
  - Outputs reasonable POST codes to a POST card if one can be plugged in
  - USB debug ports enabled, if available on the board
  - RS232 port enabled, if available on board
  - Some other agreed method for debugging the system during Coreboot
execution (e.g. debug LEDs on mobo, etc.)
* At least one of the following
  - At least one usb hub usable for keyboard, if one exists
  - PS/2 port usable for keyboard, if one exists
* All expansion slots initialized and usable
* ACPI
  - DSDT should exist
* Able to load VGA option ROM
* Able to boot into an OS not stored as a coreboot payload (e.g. boot
from CD, USB, or SATA drive). For the minimal certfication, I believe
that OS should be Debian since it's a well supported environment for
developing coreboot.

Think of "Coreboot Standard" as basically fully tested with free OSes.
Its requirements might look like the following:
* all requirements of the minimal certification
* Any requirement of the minimal certification that allows a subset to
be implemented should implement all the sub-items. For example, both
rs232 and usb debug ports should be enabled if they exists on the same
board instead of implementing one or the other.
* Uses tiny bootblock
* Uses cache-as-ram if the system is capable
* Soft poweroff works
* Extended initialization of supporting chipset
  - Fan uses vary speed based on temperature of CPU
* All legacy io ports (i.e. rs232, parallel, etc.) usable
* All USB ports usable
* All other external (including header) ports usable (e.g. firewire,
sound, etc.)
* better ACPI support
 - OSPM (e.g. G, S, D, and C states, etc.) fully exposed and usable
* CPU frequency scaling works
* After booting into Debian Linux, the OS should be able to rely on
any info provided by the Coreboot and any intervening payloads should
allow the system to be fully enumerated and configured as much as the
hardware will allow.

Tags could be used to identify specific extended support. For
instance, a system certified to boot Windows 7 could be "Coreboot
minimal+MSWin7" certified or "Coreboot standard+MSWin7" certified or
something like that. If anyone wanted to display the certification,
they could display it with or without the tags.

Possible tags:
MSWin{XP,7}
ReactOS
GPXE
AOE
ISCSI
...

We should probably note the known revisions that are compliant for
each board. This doesn't mean that every revision that would pass the
requirements needs to be listed. Only tested versions should be
listed. Those revisions would be the recommended revisions with users
using other revisions at their own risk. I could imagine something
like the following for a mobo:
minimal: 11 99 103 150
standard: 50 75 135 155
minimal+Win7: 77

The numbers are the Coreboot svn revisions that are tested. These
revisions should probably be listed in the wiki somewhere. There is
probably some better way to visualize the data. We may also need to
list SeaBIOS hashes for the certified builds.

*snip*

>> Frankly, I think that ability to use the free drivers should be good
>> enough. We shouldn't be hold out any kind of coreboot certification on
>> the condition that non-free drivers work.
>
> There are two aspects of the problem:
> - We can't test everything (fact of life)
> - Closed-source drivers have a huge market share, and won't go away any
> time soon

Agreed. I also think that some developers won't be able to test
certain non-free software. For instance, I wouldn't be able to test
that Windows 7 boots. I also don't have an Nvidia card to test their
drivers.

Given the fact that we can't test everything, we should make a minimal
amount of compliance only include things that can be tested by most
folks. I think that minimally certified hardware should really be
capable enough to develop Coreboot further on the hardware
conveniently. Standard certified hardware should work well for free
OSes if the OSes have appropriate driver support.

Also, minimally certified hardware can support more features. For
example, a minimally certified board could have logic for adjusting
fan speed intelligently. It would still be minimally certified until
someone developed the rest of the functionality for the standard level
certification and tested it.

*snip*

> Fans can be loud. If all fans run at 100% non-stop, machines can be
> essentially unusable for noise reasons.

While I agree with this, I think that a minimally certified piece of
hardware should not need working fan logic.

*snip*

> Indeed, but given that vendor code may not always be suitable for
> merging, do we want to withhold certification if code is available but
> not merged? And what happens if Kevin is on vacation?

If the code's not merged into SeaBIOS, we shouldn't certify the build.
If Kevin is the only person that can merge push the canonical SeaBIOS
tree, then I suppose it would need to wait on him. It's the same way
that a vendor can't really claim that their hardware with compliant
with Microsoft's certifications until MS signs off.

If it really becomes a problem that vendors want the certification
during a time when Kevin isn't around, that would be a good problem
for the project to have. :)

*snip*

Comments would be appreciated, especially on the minimal and standard
certification requirements above. Also, please take a look at the tags
and see if you can think of any additions.

Thanks,
wt



From wt at penguintechs.org  Sun Oct  3 11:22:04 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 02:22:04 -0700
Subject: [coreboot] an AMD based platform
In-Reply-To: <AANLkTikuZEskNHfxSAsyek3Z4CF1cRbKpCYvnoJn0sBY@mail.gmail.com>
References: <AANLkTikuZEskNHfxSAsyek3Z4CF1cRbKpCYvnoJn0sBY@mail.gmail.com>
Message-ID: <AANLkTinujaA+uhDFH3x_OCPjoMOR58b3NuyUO_4HWHze@mail.gmail.com>

If I were you, I would research the socket AM3 boards like the following:
amd/tilapia_fam10
asus/m4a785-m
gigabyte/ma785gmt

You might also find something useful in the socket AM2 boards:
amd/mahogany
amd/mahogany_fam10
amd/pistachio
asus/m2v-mx_se
gigabyte/ga_2761gxdk
gigabyte/m57sli
gigabyte/ma78gm
iei/kino-780am2-fam10
jetway/pa78vm5
msi/ms7260

BTW, I found the socket AM3 boards with the following command in the
root of my coreboot working copy:
$ for d in $(for f in $(rgrep -l AM3 src/mainboard/); do dirname $f;
done); do echo ${d##src/mainboard/}; done | sort -u

Thanks,
wt

On Sun, Oct 3, 2010 at 2:01 AM, ali hagigat <hagigatali at gmail.com> wrote:
> I want to ask the experts about an AMD based motherboard to research
> on Coreboot, what you recommend will be valuable or please tell me
> what motherboard in the list of supported motherboards of
> Wiki-Coreboot is more modern and close to the following attributes:
>
> I am looking for a motherboard with CPU and chip set similar to Intel.
> For CPU, ?I want it to have IA-32 and IA-32e architecture, I mean 32
> bit machine with 64 bit extension to support 32 and also 64 bits
> applications, with Vtx (virtual machine capability), muti-core, and
> SIMD instructions with front side bus.
>
> About Chipset, I want it to have regular logics of USB, SATA,
> PCIExpress, SDRAM controller, FWH/SPI protocol for BIOS chip, PCI
> bridge, IOAPIC, Integrated Graphics Controller, real time clock, LPC
> interface,....a relatively modern board and superio with open
> documentation.
>
> Thank you to read my message.
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From wt at penguintechs.org  Sun Oct  3 11:24:15 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 02:24:15 -0700
Subject: [coreboot] [PATCH] Add CPP logic to VIA CAR init code.
In-Reply-To: <1286009972-6589-1-git-send-email-wt@penguintechs.org>
References: <1286009972-6589-1-git-send-email-wt@penguintechs.org>
Message-ID: <AANLkTimtK1VqYYNkxGXqLpz5Ao=N_kj4zKyLM8LTDXRV@mail.gmail.com>

*ping* I really need an ack or nack on this.

Thanks,
wt

On Sat, Oct 2, 2010 at 1:59 AM, Warren Turkal <wt at penguintechs.org> wrote:
> VIA/AMD experts,
>
> This patch get's the via/vt8454c back to building. However, I am not
> sure if the code that is being #ifdef'ed out will actually ever be used
> on a via platform. The code comes straight from the amd CAR
> implementation. A couple of questions are raised by this:
> 1) Should we just delete the code from the via file instead of this
> ? patch?
> 2) Should the amd and via CAR code be integrated into one file? Maybe
> ? just portions of the files if not the whole files?
>
> Also, another happy side effect of this change is that all the c7 boards
> seem to build with tiny bootblocks. Would everyone be ok with my making
> that change?
>
> Thanks,
> wt
> 8<----------------------------------------------------------------------
> The execute-in-place (XIP) config options need to be set in order to get
> XIP functionality, so it needs to be excluded when those settings are
> not set.
>
> Signed-off-by: Warren Turkal <wt at penguintechs.org>
> ---
> ?src/cpu/via/car/cache_as_ram.inc | ? ?4 ++++
> ?1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
> index be00fe3..d18ac3a 100644
> --- a/src/cpu/via/car/cache_as_ram.inc
> +++ b/src/cpu/via/car/cache_as_ram.inc
> @@ -85,6 +85,8 @@ clear_fixed_var_mtrr_out:
> ? ? ? ?movl ? ?$(~(CacheSize - 1) | 0x800), %eax
> ? ? ? ?wrmsr
>
> +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
> +
> ?#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
> ?#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
> ?#else
> @@ -106,6 +108,8 @@ clear_fixed_var_mtrr_out:
> ? ? ? ?movl ? ?$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
> ? ? ? ?wrmsr
>
> +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
> +
> ? ? ? ?/* Set the default memory type and enable fixed and variable MTRRs. */
> ? ? ? ?/* TODO: Or also enable fixed MTRRs? Bug in the code? */
> ? ? ? ?movl ? ?$MTRRdefType_MSR, %ecx
> --
> 1.7.1
>
>



From stefan.reinauer at coresystems.de  Sun Oct  3 15:34:45 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sun, 03 Oct 2010 15:34:45 +0200
Subject: [coreboot] [PATCH] Add CPP logic to VIA CAR init code.
In-Reply-To: <AANLkTimtK1VqYYNkxGXqLpz5Ao=N_kj4zKyLM8LTDXRV@mail.gmail.com>
References: <1286009972-6589-1-git-send-email-wt@penguintechs.org>
	<AANLkTimtK1VqYYNkxGXqLpz5Ao=N_kj4zKyLM8LTDXRV@mail.gmail.com>
Message-ID: <4CA88675.9020303@coresystems.de>

 On 10/3/10 11:24 AM, Warren Turkal wrote:
> *ping* I really need an ack or nack on this.

NACK.. Still the wrong way, it just blindly comments out an arbitrary
piece of code.

However, the code has been fixed already in the repo.

Stefan
> Thanks,
> wt
>
> On Sat, Oct 2, 2010 at 1:59 AM, Warren Turkal <wt at penguintechs.org> wrote:
>> VIA/AMD experts,
>>
>> This patch get's the via/vt8454c back to building. However, I am not
>> sure if the code that is being #ifdef'ed out will actually ever be used
>> on a via platform. The code comes straight from the amd CAR
>> implementation. A couple of questions are raised by this:
>> 1) Should we just delete the code from the via file instead of this
>>   patch?
>> 2) Should the amd and via CAR code be integrated into one file? Maybe
>>   just portions of the files if not the whole files?
>>
>> Also, another happy side effect of this change is that all the c7 boards
>> seem to build with tiny bootblocks. Would everyone be ok with my making
>> that change?
>>
>> Thanks,
>> wt
>> 8<----------------------------------------------------------------------
>> The execute-in-place (XIP) config options need to be set in order to get
>> XIP functionality, so it needs to be excluded when those settings are
>> not set.
>>
>> Signed-off-by: Warren Turkal <wt at penguintechs.org>
>> ---
>>  src/cpu/via/car/cache_as_ram.inc |    4 ++++
>>  1 files changed, 4 insertions(+), 0 deletions(-)
>>
>> diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
>> index be00fe3..d18ac3a 100644
>> --- a/src/cpu/via/car/cache_as_ram.inc
>> +++ b/src/cpu/via/car/cache_as_ram.inc
>> @@ -85,6 +85,8 @@ clear_fixed_var_mtrr_out:
>>        movl    $(~(CacheSize - 1) | 0x800), %eax
>>        wrmsr
>>
>> +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
>> +
>>  #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
>>  #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
>>  #else
>> @@ -106,6 +108,8 @@ clear_fixed_var_mtrr_out:
>>        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
>>        wrmsr
>>
>> +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
>> +
>>        /* Set the default memory type and enable fixed and variable MTRRs. */
>>        /* TODO: Or also enable fixed MTRRs? Bug in the code? */
>>        movl    $MTRRdefType_MSR, %ecx
>> --
>> 1.7.1
>>
>>




From scott at notabs.org  Sun Oct  3 16:34:54 2010
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 3 Oct 2010 09:34:54 -0500
Subject: [coreboot] an AMD based platform
In-Reply-To: <AANLkTinujaA+uhDFH3x_OCPjoMOR58b3NuyUO_4HWHze@mail.gmail.com>
References: <AANLkTikuZEskNHfxSAsyek3Z4CF1cRbKpCYvnoJn0sBY@mail.gmail.com>
	<AANLkTinujaA+uhDFH3x_OCPjoMOR58b3NuyUO_4HWHze@mail.gmail.com>
Message-ID: <0DCF969BD9834ACD84FB852E7AF8AE4B@m3a78>

]If I were you, I would research the socket AM3 boards like the following:
]amd/tilapia_fam10
]asus/m4a785-m
]gigabyte/ma785gmt
]
]You might also find something useful in the socket AM2 boards:
]amd/mahogany
]amd/mahogany_fam10
]amd/pistachio
]asus/m2v-mx_se
]gigabyte/ga_2761gxdk
]gigabyte/m57sli
]gigabyte/ma78gm
]iei/kino-780am2-fam10
]jetway/pa78vm5
]msi/ms7260

There are good choices. A bonus of choosing an AMD RS780/SB700 system
is that you can use AMD simnow to debug. For learning coreboot, I chose
ECS A780GM-M3. This board can boot both family 0Fh and family 10h
processors. For coreboot work I am using only the newer family 10h
processor. I based the coreboot port on mahogany_fam10.

Thanks,
Scott

]BTW, I found the socket AM3 boards with the following command in the
]root of my coreboot working copy:
]$ for d in $(for f in $(rgrep -l AM3 src/mainboard/); do dirname $f;
]done); do echo ${d##src/mainboard/}; done | sort -u
]
]Thanks,
]wt





From vitplister at gmail.com  Sun Oct  3 18:08:09 2010
From: vitplister at gmail.com (Mattias Mattsson)
Date: Sun, 3 Oct 2010 18:08:09 +0200
Subject: [coreboot] MSI 890GXM-G65
Message-ID: <AANLkTini1z9W7tN5Tk_kgQmDbzxU2gze6+77iLE=gmNu@mail.gmail.com>

Hi,

I'm thinking of trying to port coreboot to MSI 890GXM-G65 (MS-7642):
http://www.msi.com/index.php?func=proddesc&prod_no=2012

I do not own it (yet), so I only now the specs from the manual:

North Bridge: AMD 890GX chipset
South Bridge: AMD SB850 chipset
Integrated ATI RadeonTM HD4290 GPU
CPU Socket: AM3
Super I/O: Fintek F71889ED (
http://www.motherboards.org/imageview.html?i=/images/reviews/motherboards/2040_p4_11.jpg
)

flashrom is supported according to this user report:
http://www.flashrom.org/pipermail/flashrom/2010-August/004393.html

Does it seems like a good target?
(Does coreboot have support for this chipset, if not is documentation
available?)


Thanks,
-mattias



From wt at penguintechs.org  Sun Oct  3 18:31:51 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 09:31:51 -0700
Subject: [coreboot] [PATCH] Add CPP logic to VIA CAR init code.
In-Reply-To: <4CA88675.9020303@coresystems.de>
References: <1286009972-6589-1-git-send-email-wt@penguintechs.org>
	<AANLkTimtK1VqYYNkxGXqLpz5Ao=N_kj4zKyLM8LTDXRV@mail.gmail.com>
	<4CA88675.9020303@coresystems.de>
Message-ID: <AANLkTikVMmNo1jJv2MRFFkVpv_y5_WnkuR9=WJr=eYJt@mail.gmail.com>

Is this what your orl change fixed?

wt

On Sun, Oct 3, 2010 at 6:34 AM, Stefan Reinauer
<stefan.reinauer at coresystems.de> wrote:
> ?On 10/3/10 11:24 AM, Warren Turkal wrote:
>> *ping* I really need an ack or nack on this.
>
> NACK.. Still the wrong way, it just blindly comments out an arbitrary
> piece of code.
>
> However, the code has been fixed already in the repo.
>
> Stefan
>> Thanks,
>> wt
>>
>> On Sat, Oct 2, 2010 at 1:59 AM, Warren Turkal <wt at penguintechs.org> wrote:
>>> VIA/AMD experts,
>>>
>>> This patch get's the via/vt8454c back to building. However, I am not
>>> sure if the code that is being #ifdef'ed out will actually ever be used
>>> on a via platform. The code comes straight from the amd CAR
>>> implementation. A couple of questions are raised by this:
>>> 1) Should we just delete the code from the via file instead of this
>>> ? patch?
>>> 2) Should the amd and via CAR code be integrated into one file? Maybe
>>> ? just portions of the files if not the whole files?
>>>
>>> Also, another happy side effect of this change is that all the c7 boards
>>> seem to build with tiny bootblocks. Would everyone be ok with my making
>>> that change?
>>>
>>> Thanks,
>>> wt
>>> 8<----------------------------------------------------------------------
>>> The execute-in-place (XIP) config options need to be set in order to get
>>> XIP functionality, so it needs to be excluded when those settings are
>>> not set.
>>>
>>> Signed-off-by: Warren Turkal <wt at penguintechs.org>
>>> ---
>>> ?src/cpu/via/car/cache_as_ram.inc | ? ?4 ++++
>>> ?1 files changed, 4 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
>>> index be00fe3..d18ac3a 100644
>>> --- a/src/cpu/via/car/cache_as_ram.inc
>>> +++ b/src/cpu/via/car/cache_as_ram.inc
>>> @@ -85,6 +85,8 @@ clear_fixed_var_mtrr_out:
>>> ? ? ? ?movl ? ?$(~(CacheSize - 1) | 0x800), %eax
>>> ? ? ? ?wrmsr
>>>
>>> +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
>>> +
>>> ?#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
>>> ?#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
>>> ?#else
>>> @@ -106,6 +108,8 @@ clear_fixed_var_mtrr_out:
>>> ? ? ? ?movl ? ?$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
>>> ? ? ? ?wrmsr
>>>
>>> +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
>>> +
>>> ? ? ? ?/* Set the default memory type and enable fixed and variable MTRRs. */
>>> ? ? ? ?/* TODO: Or also enable fixed MTRRs? Bug in the code? */
>>> ? ? ? ?movl ? ?$MTRRdefType_MSR, %ecx
>>> --
>>> 1.7.1
>>>
>>>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From wt at penguintechs.org  Sun Oct  3 18:54:37 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 09:54:37 -0700
Subject: [coreboot] [PATCH] Add CPP logic to VIA CAR init code.
In-Reply-To: <AANLkTikVMmNo1jJv2MRFFkVpv_y5_WnkuR9=WJr=eYJt@mail.gmail.com>
References: <1286009972-6589-1-git-send-email-wt@penguintechs.org>
	<AANLkTimtK1VqYYNkxGXqLpz5Ao=N_kj4zKyLM8LTDXRV@mail.gmail.com>
	<4CA88675.9020303@coresystems.de>
	<AANLkTikVMmNo1jJv2MRFFkVpv_y5_WnkuR9=WJr=eYJt@mail.gmail.com>
Message-ID: <AANLkTinu++sxqomSeHiKmeRVo86gqCghg4+SUfns7NKO@mail.gmail.com>

I see that is the change that fixed it. However, I'm still not sure I
understand the fix completely. When CONFIG_TINY_BOOTBLOCK is defined
and AUTO_XIP_ROM_BASE is not defined, we get the following line (line
number 159 or so) in build/mainboard/via/vt8454c/crt0.s:
 movl $AUTO_XIP_ROM_BASE, %eax

How does that assemble without an error?

Is the AUTO_XIP_ROM_BASE set to some value (presumably 0) by the
assembler for some reason that I don't see? For reference, here is the
equivalent line from crt0.disasm:
100 0115 B8000000 >---->-------movl>---$REAL_XIP_ROM_BASE, %eax

Thanks,
wt

On Sun, Oct 3, 2010 at 9:31 AM, Warren Turkal <wt at penguintechs.org> wrote:
> Is this what your orl change fixed?
>
> wt
>
> On Sun, Oct 3, 2010 at 6:34 AM, Stefan Reinauer
> <stefan.reinauer at coresystems.de> wrote:
>> ?On 10/3/10 11:24 AM, Warren Turkal wrote:
>>> *ping* I really need an ack or nack on this.
>>
>> NACK.. Still the wrong way, it just blindly comments out an arbitrary
>> piece of code.
>>
>> However, the code has been fixed already in the repo.
>>
>> Stefan
>>> Thanks,
>>> wt
>>>
>>> On Sat, Oct 2, 2010 at 1:59 AM, Warren Turkal <wt at penguintechs.org> wrote:
>>>> VIA/AMD experts,
>>>>
>>>> This patch get's the via/vt8454c back to building. However, I am not
>>>> sure if the code that is being #ifdef'ed out will actually ever be used
>>>> on a via platform. The code comes straight from the amd CAR
>>>> implementation. A couple of questions are raised by this:
>>>> 1) Should we just delete the code from the via file instead of this
>>>> ? patch?
>>>> 2) Should the amd and via CAR code be integrated into one file? Maybe
>>>> ? just portions of the files if not the whole files?
>>>>
>>>> Also, another happy side effect of this change is that all the c7 boards
>>>> seem to build with tiny bootblocks. Would everyone be ok with my making
>>>> that change?
>>>>
>>>> Thanks,
>>>> wt
>>>> 8<----------------------------------------------------------------------
>>>> The execute-in-place (XIP) config options need to be set in order to get
>>>> XIP functionality, so it needs to be excluded when those settings are
>>>> not set.
>>>>
>>>> Signed-off-by: Warren Turkal <wt at penguintechs.org>
>>>> ---
>>>> ?src/cpu/via/car/cache_as_ram.inc | ? ?4 ++++
>>>> ?1 files changed, 4 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
>>>> index be00fe3..d18ac3a 100644
>>>> --- a/src/cpu/via/car/cache_as_ram.inc
>>>> +++ b/src/cpu/via/car/cache_as_ram.inc
>>>> @@ -85,6 +85,8 @@ clear_fixed_var_mtrr_out:
>>>> ? ? ? ?movl ? ?$(~(CacheSize - 1) | 0x800), %eax
>>>> ? ? ? ?wrmsr
>>>>
>>>> +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
>>>> +
>>>> ?#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
>>>> ?#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
>>>> ?#else
>>>> @@ -106,6 +108,8 @@ clear_fixed_var_mtrr_out:
>>>> ? ? ? ?movl ? ?$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
>>>> ? ? ? ?wrmsr
>>>>
>>>> +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
>>>> +
>>>> ? ? ? ?/* Set the default memory type and enable fixed and variable MTRRs. */
>>>> ? ? ? ?/* TODO: Or also enable fixed MTRRs? Bug in the code? */
>>>> ? ? ? ?movl ? ?$MTRRdefType_MSR, %ecx
>>>> --
>>>> 1.7.1
>>>>
>>>>
>>
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>



From andi.mundt at web.de  Sun Oct  3 18:26:46 2010
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Sun, 3 Oct 2010 18:26:46 +0200
Subject: [coreboot] mtrr: your BIOS has set up an incorrect mask
Message-ID: <20101003162646.GA4071@flashgordon>

Hi, 

today, after quite some time running coreboot on my machine
(GA-M57SLI-S4), I updated coreboot to the latest revision, 5908.

Now, my system complains about "mtrr: your BIOS has set up an
incorrect mask, fixing it up." and I get a kernel oops. (See attached dmesg).

I looked in my old syslogs, and there I already find "mtrr: type mismatch for
e0000000,10000000 old: write-back new: write-combining", but no kernel
oops.

I have only very limited time to follow up on this, but if there's an
easy fix, it would be great.

Regards,
	Andi
-------------- next part --------------
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 2.6.32-5-amd64 (Debian 2.6.32-23) (dannf at debian.org) (gcc version 4.3.5 (Debian 4.3.5-3) ) #1 SMP Fri Sep 17 21:50:19 UTC 2010
[    0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-2.6.32-5-amd64 root=UUID=3f46729c-a47e-4b29-a5a6-6bbe2e6cc7a4 ro quiet splash
[    0.000000] KERNEL supported cpus:
[    0.000000]   Intel GenuineIntel
[    0.000000]   AMD AuthenticAMD
[    0.000000]   Centaur CentaurHauls
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009f400 (usable)
[    0.000000]  BIOS-e820: 000000000009f400 - 00000000000a0000 (reserved)
[    0.000000]  BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
[    0.000000]  BIOS-e820: 0000000000100000 - 00000000bffef000 (usable)
[    0.000000]  BIOS-e820: 00000000bffef000 - 00000000c0000000 (reserved)
[    0.000000]  BIOS-e820: 0000000100000000 - 0000000140000000 (usable)
[    0.000000] DMI 2.4 present.
[    0.000000] last_pfn = 0x140000 max_arch_pfn = 0x400000000
[    0.000000] MTRR default type: uncachable
[    0.000000] MTRR fixed ranges enabled:
[    0.000000]   00000-9FFFF write-back
[    0.000000]   A0000-BFFFF uncachable
[    0.000000]   C0000-FFFFF write-back
[    0.000000] MTRR variable ranges enabled:
[    0.000000]   0 base 0000000000 mask 0F00000000 write-back
[    0.000000]   1 base 0100000000 mask 0FC0000000 write-back
[    0.000000]   2 base 00C0000000 mask 0FC0000000 uncachable
[    0.000000]   3 disabled
[    0.000000]   4 disabled
[    0.000000]   5 disabled
[    0.000000]   6 disabled
[    0.000000]   7 disabled
[    0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: at /tmp/buildd/linux-2.6-2.6.32/debian/build/source_amd64_none/arch/x86/kernel/cpu/mtrr/generic.c:467 generic_get_mtrr+0xbf/0xf9()
[    0.000000] Hardware name: 
[    0.000000] mtrr: your BIOS has set up an incorrect mask, fixing it up.
[    0.000000] Modules linked in:
[    0.000000] Pid: 0, comm: swapper Not tainted 2.6.32-5-amd64 #1
[    0.000000] Call Trace:
[    0.000000]  [<ffffffff810217ef>] ? generic_get_mtrr+0xbf/0xf9
[    0.000000]  [<ffffffff810217ef>] ? generic_get_mtrr+0xbf/0xf9
[    0.000000]  [<ffffffff8104db34>] ? warn_slowpath_common+0x77/0xa3
[    0.000000]  [<ffffffff8104dbbc>] ? warn_slowpath_fmt+0x51/0x59
[    0.000000]  [<ffffffff810218fb>] ? mtrr_wrmsr+0x1c/0x49
[    0.000000]  [<ffffffff81021b00>] ? get_fixed_ranges+0x71/0x98
[    0.000000]  [<ffffffff810218fb>] ? mtrr_wrmsr+0x1c/0x49
[    0.000000]  [<ffffffff810219bf>] ? prepare_set+0x97/0x9d
[    0.000000]  [<ffffffff81021a18>] ? post_set+0x53/0x60
[    0.000000]  [<ffffffff814f70f2>] ? get_mtrr_state+0x2eb/0x2f6
[    0.000000]  [<ffffffff810217ef>] ? generic_get_mtrr+0xbf/0xf9
[    0.000000]  [<ffffffff812f8e4e>] ? printk+0x4e/0x58
[    0.000000]  [<ffffffff814f7cc9>] ? mtrr_trim_uncached_memory+0x91/0x311
[    0.000000]  [<ffffffff814f6c62>] ? mtrr_bp_init+0x1b1/0x1d4
[    0.000000]  [<ffffffff8123a15b>] ? dmi_name_in_serial+0x1d/0x28
[    0.000000]  [<ffffffff81500f47>] ? early_gart_iommu_check+0x9b/0x287
[    0.000000]  [<ffffffff814f315d>] ? setup_arch+0x43f/0x9cb
[    0.000000]  [<ffffffff811f6517>] ? extract_entropy+0x6a/0x125
[    0.000000]  [<ffffffff814ef140>] ? early_idt_handler+0x0/0x71
[    0.000000]  [<ffffffff814ef9d0>] ? start_kernel+0xdb/0x3e8
[    0.000000]  [<ffffffff814ef3b7>] ? x86_64_start_kernel+0xf9/0x106
[    0.000000] ---[ end trace a7919e7f17c0a725 ]---
[    0.000000] e820 update range: 00000000c0000000 - 0000000100000000 (usable) ==> (reserved)
[    0.000000] last_pfn = 0xbffef max_arch_pfn = 0x400000000
[    0.000000] initial memory mapped : 0 - 20000000
[    0.000000] init_memory_mapping: 0000000000000000-00000000bffef000
[    0.000000]  0000000000 - 00bfe00000 page 2M
[    0.000000]  00bfe00000 - 00bffef000 page 4k
[    0.000000] kernel direct mapping tables up to bffef000 @ 8000-d000
[    0.000000] init_memory_mapping: 0000000100000000-0000000140000000
[    0.000000]  0100000000 - 0140000000 page 2M
[    0.000000] kernel direct mapping tables up to 140000000 @ b000-11000
[    0.000000] RAMDISK: 372f4000 - 37fefaea
[    0.000000] ACPI: RSDP 00000000000fd900 00014 (v00 CORE  )
[    0.000000] ACPI: RSDT 00000000bfff2424 00040 (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: FACP 00000000bfff301a 000F4 (v01    GBT COREBOOT 00000000 CORE 0000002A)
[    0.000000] ACPI: DSDT 00000000bfff2540 00ADA (v01 LXBIOS LXB-DSDT 00000001 INTL 20100528)
[    0.000000] ACPI: FACS 00000000bfff2500 00040
[    0.000000] ACPI: HPET 00000000bfff310e 00038 (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: APIC 00000000bfff3146 00068 (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: MCFG 00000000bfff31ae 0002C (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: SRAT 00000000bfff31da 000C8 (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: SLIT 00000000bfff32a2 0002D (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: SSDT 00000000bfff32cf 0037A (v02 CORE   DYNADATA 0000002A CORE 0000002A)
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] SRAT: PXM 0 -> APIC 0 -> Node 0
[    0.000000] SRAT: PXM 0 -> APIC 1 -> Node 0
[    0.000000] SRAT: Node 0 PXM 0 0-a0000
[    0.000000] SRAT: Node 0 PXM 0 100000-c0000000
[    0.000000] SRAT: Node 0 PXM 0 100000000-140000000
[    0.000000] NUMA: Allocated memnodemap from c000 - e840
[    0.000000] NUMA: Using 20 for the hash shift.
[    0.000000] Bootmem setup node 0 0000000000000000-0000000140000000
[    0.000000]   NODE_DATA [000000000000e840 - 000000000001683f]
[    0.000000]   bootmap [0000000000017000 -  000000000003efff] pages 28
[    0.000000] (10 early reservations) ==> bootmem [0000000000 - 0140000000]
[    0.000000]   #0 [0000000000 - 0000001000]   BIOS data page ==> [0000000000 - 0000001000]
[    0.000000]   #1 [0000006000 - 0000008000]       TRAMPOLINE ==> [0000006000 - 0000008000]
[    0.000000]   #2 [0001000000 - 0001684414]    TEXT DATA BSS ==> [0001000000 - 0001684414]
[    0.000000]   #3 [00372f4000 - 0037fefaea]          RAMDISK ==> [00372f4000 - 0037fefaea]
[    0.000000]   #4 [000009f400 - 0000100000]    BIOS reserved ==> [000009f400 - 0000100000]
[    0.000000]   #5 [0001685000 - 000168503d]              BRK ==> [0001685000 - 000168503d]
[    0.000000]   #6 [0000008000 - 000000b000]          PGTABLE ==> [0000008000 - 000000b000]
[    0.000000]   #7 [000000b000 - 000000c000]          PGTABLE ==> [000000b000 - 000000c000]
[    0.000000]   #8 [0000001000 - 000000102d]        ACPI SLIT ==> [0000001000 - 000000102d]
[    0.000000]   #9 [000000c000 - 000000e840]       MEMNODEMAP ==> [000000c000 - 000000e840]
[    0.000000] found SMP MP-table at [ffff8800000fd920] fd920
[    0.000000]  [ffffea0000000000-ffffea00045fffff] PMD -> [ffff880001800000-ffff880004ffffff] on node 0
[    0.000000] Zone PFN ranges:
[    0.000000]   DMA      0x00000000 -> 0x00001000
[    0.000000]   DMA32    0x00001000 -> 0x00100000
[    0.000000]   Normal   0x00100000 -> 0x00140000
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[3] active PFN ranges
[    0.000000]     0: 0x00000000 -> 0x0000009f
[    0.000000]     0: 0x00000100 -> 0x000bffef
[    0.000000]     0: 0x00100000 -> 0x00140000
[    0.000000] On node 0 totalpages: 1048462
[    0.000000]   DMA zone: 56 pages used for memmap
[    0.000000]   DMA zone: 105 pages reserved
[    0.000000]   DMA zone: 3838 pages, LIFO batch:0
[    0.000000]   DMA32 zone: 14280 pages used for memmap
[    0.000000]   DMA32 zone: 768039 pages, LIFO batch:31
[    0.000000]   Normal zone: 3584 pages used for memmap
[    0.000000]   Normal zone: 258560 pages, LIFO batch:31
[    0.000000] ACPI: PM-Timer IO Port: 0x2008
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
[    0.000000] ACPI: IOAPIC (id[0x02] address[0xf6244000] gsi_base[0])
[    0.000000] IOAPIC[0]: apic_id 2, version 17, address 0xf6244000, GSI 0-23
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.000000] ACPI: IRQ0 used by override.
[    0.000000] ACPI: IRQ2 used by override.
[    0.000000] ACPI: IRQ9 used by override.
[    0.000000] Using ACPI (MADT) for SMP configuration information
[    0.000000] ACPI: HPET id: 0x102282a0 base: 0xfed00000
[    0.000000] SMP: Allowing 2 CPUs, 0 hotplug CPUs
[    0.000000] nr_irqs_gsi: 24
[    0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
[    0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000
[    0.000000] PM: Registered nosave memory: 00000000000f0000 - 0000000000100000
[    0.000000] PM: Registered nosave memory: 00000000bffef000 - 00000000c0000000
[    0.000000] PM: Registered nosave memory: 00000000c0000000 - 0000000100000000
[    0.000000] Allocating PCI resources starting at c0000000 (gap: c0000000:40000000)
[    0.000000] Booting paravirtualized kernel on bare hardware
[    0.000000] NR_CPUS:512 nr_cpumask_bits:512 nr_cpu_ids:2 nr_node_ids:1
[    0.000000] PERCPU: Embedded 30 pages/cpu @ffff880005200000 s90328 r8192 d24360 u1048576
[    0.000000] pcpu-alloc: s90328 r8192 d24360 u1048576 alloc=1*2097152
[    0.000000] pcpu-alloc: [0] 0 1 
[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 1030437
[    0.000000] Policy zone: Normal
[    0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-2.6.32-5-amd64 root=UUID=3f46729c-a47e-4b29-a5a6-6bbe2e6cc7a4 ro quiet splash
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000000] Initializing CPU#0
[    0.000000] Checking aperture...
[    0.000000] No AGP bridge found
[    0.000000] Node 0: aperture @ f0000000 size 64 MB
[    0.000000] Memory: 4115840k/5242880k available (3075k kernel code, 1049032k absent, 78008k reserved, 1879k data, 584k init)
[    0.000000] SLUB: Genslabs=14, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Hierarchical RCU implementation.
[    0.000000] NR_IRQS:4352 nr_irqs:424
[    0.000000] spurious 8259A interrupt: IRQ7.
[    0.000000] Console: colour VGA+ 80x25
[    0.000000] console [tty0] enabled
[    0.000000] hpet clockevent registered
[    0.000000] HPET: 3 timers in total, 0 timers will be used for per-cpu timer
[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 2499.996 MHz processor.
[    0.004005] Calibrating delay loop (skipped), value calculated using timer frequency.. 4999.99 BogoMIPS (lpj=9999984)
[    0.004024] Security Framework initialized
[    0.004030] SELinux:  Disabled at boot.
[    0.004308] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[    0.010162] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.011273] Mount-cache hash table entries: 256
[    0.011422] Initializing cgroup subsys ns
[    0.011425] Initializing cgroup subsys cpuacct
[    0.011428] Initializing cgroup subsys devices
[    0.011431] Initializing cgroup subsys freezer
[    0.011433] Initializing cgroup subsys net_cls
[    0.011459] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
[    0.011461] CPU: L2 Cache: 512K (64 bytes/line)
[    0.011464] CPU 0/0x0 -> Node 0
[    0.011465] tseg: 0000000000
[    0.011478] CPU: Physical Processor ID: 0
[    0.011479] CPU: Processor Core ID: 0
[    0.011482] mce: CPU supports 5 MCE banks
[    0.011492] using C1E aware idle routine
[    0.011494] Performance Events: AMD PMU driver.
[    0.011498] ... version:                0
[    0.011500] ... bit width:              48
[    0.011501] ... generic registers:      4
[    0.011503] ... value mask:             0000ffffffffffff
[    0.011504] ... max period:             00007fffffffffff
[    0.011506] ... fixed-purpose events:   0
[    0.011507] ... event mask:             000000000000000f
[    0.012137] ACPI: Core revision 20090903
[    0.012936] Setting APIC routing to flat
[    0.013258] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0
[    0.052956] CPU0: AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ stepping 01
[    0.056001] Booting processor 1 APIC 0x1 ip 0x6000
[    0.008000] Initializing CPU#1
[    0.008000] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
[    0.008000] CPU: L2 Cache: 512K (64 bytes/line)
[    0.008000] CPU 1/0x1 -> Node 0
[    0.008000] CPU: Physical Processor ID: 0
[    0.008000] CPU: Processor Core ID: 1
[    0.140026] CPU1: AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ stepping 01
[    0.140037] Brought up 2 CPUs
[    0.140040] Total of 2 processors activated (9999.97 BogoMIPS).
[    0.140236] CPU0 attaching sched-domain:
[    0.140238]  domain 0: span 0-1 level MC
[    0.140241]   groups: 0 1
[    0.140246] CPU1 attaching sched-domain:
[    0.140248]  domain 0: span 0-1 level MC
[    0.140250]   groups: 1 0
[    0.140317] devtmpfs: initialized
[    0.142860] regulator: core version 0.5
[    0.142860] NET: Registered protocol family 16
[    0.142860] node 0 link 0: io port [1000, 3fff]
[    0.142860] TOM: 00000000c0000000 aka 3072M
[    0.142860] node 0 link 0: mmio [a0000, bffff]
[    0.142860] node 0 link 0: mmio [f4000000, f62fffff]
[    0.142860] node 0 link 0: mmio [e0000000, efffffff]
[    0.142860] TOM2: 0000000140000000 aka 5120M
[    0.142860] bus: [00,07] on node 0 link 0
[    0.142860] bus: 00 index 0 io port: [0, ffff]
[    0.142860] bus: 00 index 1 mmio: [a0000, bffff]
[    0.142860] bus: 00 index 2 mmio: [f0000000, ffffffff]
[    0.142860] bus: 00 index 3 mmio: [c0000000, efffffff]
[    0.142860] bus: 00 index 4 mmio: [140000000, fcffffffff]
[    0.142860] ACPI: bus type pci registered
[    0.142860] PCI: MMCONFIG has no entries
[    0.142860] PCI: Using configuration type 1 for base access
[    0.144121] bio: create slab <bio-0> at 0
[    0.144263] ACPI: EC: Look up EC in DSDT
[    0.145069] ACPI: Interpreter enabled
[    0.145071] ACPI: (supports S0 S5)
[    0.145080] ACPI: Using IOAPIC for interrupt routing
[    0.145089] PCI: MMCONFIG has no entries
[    0.145788] ACPI: No dock devices found.
[    0.147262] ACPI: PCI Root Bridge [PCI0] (0000:00)
[    0.147442] pci 0000:00:01.0: reg 14 32bit mmio: [0xf6244000-0xf6244fff]
[    0.147475] pci 0000:00:01.1: reg 10 io port: [0x2c00-0x2c3f]
[    0.147485] pci 0000:00:01.1: reg 20 io port: [0x2c40-0x2c7f]
[    0.147489] pci 0000:00:01.1: reg 24 io port: [0x2c80-0x2cbf]
[    0.147508] pci 0000:00:01.1: PME# supported from D3hot D3cold
[    0.147513] pci 0000:00:01.1: PME# disabled
[    0.147565] pci 0000:00:01.3: reg 10 32bit mmio: [0xf6200000-0xf623ffff]
[    0.147642] pci 0000:00:02.0: reg 10 32bit mmio: [0xf6245000-0xf6245fff]
[    0.148007] pci 0000:00:02.0: supports D1 D2
[    0.148009] pci 0000:00:02.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.148012] pci 0000:00:02.0: PME# disabled
[    0.148029] pci 0000:00:02.1: reg 10 32bit mmio: [0xf624a000-0xf624a0ff]
[    0.148047] pci 0000:00:02.1: supports D1 D2
[    0.148049] pci 0000:00:02.1: PME# supported from D0 D1 D2 D3hot D3cold
[    0.148051] pci 0000:00:02.1: PME# disabled
[    0.148075] pci 0000:00:04.0: reg 20 io port: [0x2cc0-0x2ccf]
[    0.148100] pci 0000:00:05.0: reg 10 io port: [0x3000-0x3007]
[    0.148103] pci 0000:00:05.0: reg 14 io port: [0x3038-0x303b]
[    0.148106] pci 0000:00:05.0: reg 18 io port: [0x3008-0x300f]
[    0.148110] pci 0000:00:05.0: reg 1c io port: [0x303c-0x303f]
[    0.148113] pci 0000:00:05.0: reg 20 io port: [0x2cd0-0x2cdf]
[    0.148116] pci 0000:00:05.0: reg 24 32bit mmio: [0xf6246000-0xf6246fff]
[    0.148145] pci 0000:00:05.1: reg 10 io port: [0x3010-0x3017]
[    0.148148] pci 0000:00:05.1: reg 14 io port: [0x3040-0x3043]
[    0.148151] pci 0000:00:05.1: reg 18 io port: [0x3018-0x301f]
[    0.148155] pci 0000:00:05.1: reg 1c io port: [0x3044-0x3047]
[    0.148158] pci 0000:00:05.1: reg 20 io port: [0x2ce0-0x2cef]
[    0.148161] pci 0000:00:05.1: reg 24 32bit mmio: [0xf6247000-0xf6247fff]
[    0.148189] pci 0000:00:05.2: reg 10 io port: [0x3020-0x3027]
[    0.148192] pci 0000:00:05.2: reg 14 io port: [0x3048-0x304b]
[    0.148195] pci 0000:00:05.2: reg 18 io port: [0x3028-0x302f]
[    0.148199] pci 0000:00:05.2: reg 1c io port: [0x304c-0x304f]
[    0.148202] pci 0000:00:05.2: reg 20 io port: [0x2cf0-0x2cff]
[    0.148205] pci 0000:00:05.2: reg 24 32bit mmio: [0xf6248000-0xf6248fff]
[    0.148259] pci 0000:00:06.1: reg 10 32bit mmio: [0xf6240000-0xf6243fff]
[    0.148278] pci 0000:00:06.1: PME# supported from D3hot D3cold
[    0.148281] pci 0000:00:06.1: PME# disabled
[    0.148312] pci 0000:00:08.0: reg 10 32bit mmio: [0xf6249000-0xf6249fff]
[    0.148315] pci 0000:00:08.0: reg 14 io port: [0x3030-0x3037]
[    0.148319] pci 0000:00:08.0: reg 18 32bit mmio: [0xf624a100-0xf624a1ff]
[    0.148322] pci 0000:00:08.0: reg 1c 32bit mmio: [0xf624a200-0xf624a20f]
[    0.148340] pci 0000:00:08.0: supports D1 D2
[    0.148342] pci 0000:00:08.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.148346] pci 0000:00:08.0: PME# disabled
[    0.148378] pci 0000:00:0a.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.148380] pci 0000:00:0a.0: PME# disabled
[    0.148409] pci 0000:00:0b.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.148412] pci 0000:00:0b.0: PME# disabled
[    0.148441] pci 0000:00:0c.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.148443] pci 0000:00:0c.0: PME# disabled
[    0.148474] pci 0000:00:0d.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.148476] pci 0000:00:0d.0: PME# disabled
[    0.148505] pci 0000:00:0e.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.148507] pci 0000:00:0e.0: PME# disabled
[    0.148536] pci 0000:00:0f.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.148539] pci 0000:00:0f.0: PME# disabled
[    0.148624] pci 0000:01:08.0: reg 10 32bit mmio: [0xf6104000-0xf6105fff]
[    0.148663] pci 0000:01:0a.0: reg 10 32bit mmio: [0xf6106000-0xf61067ff]
[    0.148668] pci 0000:01:0a.0: reg 14 32bit mmio: [0xf6100000-0xf6103fff]
[    0.148691] pci 0000:01:0a.0: supports D1 D2
[    0.148693] pci 0000:01:0a.0: PME# supported from D0 D1 D2 D3hot
[    0.148696] pci 0000:01:0a.0: PME# disabled
[    0.148715] pci 0000:00:06.0: transparent bridge
[    0.148718] pci 0000:00:06.0: bridge 32bit mmio: [0xf6100000-0xf61fffff]
[    0.148872] pci 0000:07:00.0: reg 10 32bit mmio: [0xf4000000-0xf4ffffff]
[    0.148878] pci 0000:07:00.0: reg 14 64bit mmio pref: [0xe0000000-0xefffffff]
[    0.148884] pci 0000:07:00.0: reg 1c 64bit mmio: [0xf5000000-0xf5ffffff]
[    0.148889] pci 0000:07:00.0: reg 24 io port: [0x1000-0x107f]
[    0.148893] pci 0000:07:00.0: reg 30 32bit mmio pref: [0xf6000000-0xf601ffff]
[    0.148915] pci 0000:07:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'
[    0.148952] pci 0000:00:0f.0: bridge io port: [0x1000-0x1fff]
[    0.148955] pci 0000:00:0f.0: bridge 32bit mmio: [0xf4000000-0xf60fffff]
[    0.148958] pci 0000:00:0f.0: bridge 64bit mmio pref: [0xe0000000-0xefffffff]
[    0.148969] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
[    0.148994] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBF._PRT]
[    0.149007] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBE._PRT]
[    0.149020] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBD._PRT]
[    0.149033] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBC._PRT]
[    0.149046] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBB._PRT]
[    0.149058] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBA._PRT]
[    0.149070] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCID._PRT]
[    0.151109] vgaarb: device added: PCI:0000:07:00.0,decodes=io+mem,owns=io+mem,locks=none
[    0.151112] vgaarb: loaded
[    0.151196] PCI: Using ACPI for IRQ routing
[    0.151346] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 31
[    0.151350] hpet0: 3 comparators, 32-bit 25.000000 MHz counter
[    0.156027] Switching to clocksource hpet
[    0.157010] pnp: PnP ACPI init
[    0.157029] ACPI: bus type pnp registered
[    0.158744] pnp: PnP ACPI: found 6 devices
[    0.158746] ACPI: ACPI bus type pnp unregistered
[    0.163521] pci 0000:00:06.0: PCI bridge, secondary bus 0000:01
[    0.163523] pci 0000:00:06.0:   IO window: disabled
[    0.163526] pci 0000:00:06.0:   MEM window: 0xf6100000-0xf61fffff
[    0.163528] pci 0000:00:06.0:   PREFETCH window: disabled
[    0.163532] pci 0000:00:0a.0: PCI bridge, secondary bus 0000:02
[    0.163533] pci 0000:00:0a.0:   IO window: disabled
[    0.163536] pci 0000:00:0a.0:   MEM window: disabled
[    0.163538] pci 0000:00:0a.0:   PREFETCH window: disabled
[    0.163540] pci 0000:00:0b.0: PCI bridge, secondary bus 0000:03
[    0.163542] pci 0000:00:0b.0:   IO window: disabled
[    0.163544] pci 0000:00:0b.0:   MEM window: disabled
[    0.163546] pci 0000:00:0b.0:   PREFETCH window: disabled
[    0.163549] pci 0000:00:0c.0: PCI bridge, secondary bus 0000:04
[    0.163551] pci 0000:00:0c.0:   IO window: disabled
[    0.163553] pci 0000:00:0c.0:   MEM window: disabled
[    0.163555] pci 0000:00:0c.0:   PREFETCH window: disabled
[    0.163558] pci 0000:00:0d.0: PCI bridge, secondary bus 0000:05
[    0.163560] pci 0000:00:0d.0:   IO window: disabled
[    0.163562] pci 0000:00:0d.0:   MEM window: disabled
[    0.163564] pci 0000:00:0d.0:   PREFETCH window: disabled
[    0.163567] pci 0000:00:0e.0: PCI bridge, secondary bus 0000:06
[    0.163569] pci 0000:00:0e.0:   IO window: disabled
[    0.163571] pci 0000:00:0e.0:   MEM window: disabled
[    0.163573] pci 0000:00:0e.0:   PREFETCH window: disabled
[    0.163577] pci 0000:00:0f.0: PCI bridge, secondary bus 0000:07
[    0.163579] pci 0000:00:0f.0:   IO window: 0x1000-0x1fff
[    0.163582] pci 0000:00:0f.0:   MEM window: 0xf4000000-0xf60fffff
[    0.163585] pci 0000:00:0f.0:   PREFETCH window: 0x000000e0000000-0x000000efffffff
[    0.163592] pci 0000:00:06.0: setting latency timer to 64
[    0.163597] pci 0000:00:0a.0: setting latency timer to 64
[    0.163601] pci 0000:00:0b.0: setting latency timer to 64
[    0.163606] pci 0000:00:0c.0: setting latency timer to 64
[    0.163610] pci 0000:00:0d.0: setting latency timer to 64
[    0.163614] pci 0000:00:0e.0: setting latency timer to 64
[    0.163618] pci 0000:00:0f.0: setting latency timer to 64
[    0.163622] pci_bus 0000:00: resource 0 io:  [0x00-0xffff]
[    0.163625] pci_bus 0000:00: resource 1 mem: [0x000000-0xffffffffffffffff]
[    0.163627] pci_bus 0000:01: resource 1 mem: [0xf6100000-0xf61fffff]
[    0.163630] pci_bus 0000:01: resource 3 io:  [0x00-0xffff]
[    0.163632] pci_bus 0000:01: resource 4 mem: [0x000000-0xffffffffffffffff]
[    0.163635] pci_bus 0000:07: resource 0 io:  [0x1000-0x1fff]
[    0.163637] pci_bus 0000:07: resource 1 mem: [0xf4000000-0xf60fffff]
[    0.163639] pci_bus 0000:07: resource 2 pref mem [0xe0000000-0xefffffff]
[    0.163673] NET: Registered protocol family 2
[    0.163827] IP route cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.165287] TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
[    0.168942] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[    0.169437] TCP: Hash tables configured (established 524288 bind 65536)
[    0.169440] TCP reno registered
[    0.169539] NET: Registered protocol family 1
[    0.169668] pci 0000:00:05.0: Enabling HT MSI Mapping
[    0.169711] pci 0000:00:05.1: Enabling HT MSI Mapping
[    0.169754] pci 0000:00:05.2: Enabling HT MSI Mapping
[    0.169796] pci 0000:00:06.0: Enabling HT MSI Mapping
[    0.169842] pci 0000:00:06.1: Enabling HT MSI Mapping
[    0.169896] pci 0000:00:08.0: Enabling HT MSI Mapping
[    0.169949] pci 0000:00:0a.0: Enabling HT MSI Mapping
[    0.170006] pci 0000:00:0b.0: Enabling HT MSI Mapping
[    0.170066] pci 0000:00:0c.0: Enabling HT MSI Mapping
[    0.170130] pci 0000:00:0d.0: Enabling HT MSI Mapping
[    0.170197] pci 0000:00:0e.0: Enabling HT MSI Mapping
[    0.170267] pci 0000:00:0f.0: Enabling HT MSI Mapping
[    0.170286] pci 0000:07:00.0: Boot video device
[    0.170336] Unpacking initramfs...
[    0.447480] Freeing initrd memory: 13294k freed
[    0.455518] PCI-DMA: Disabling AGP.
[    0.455611] PCI-DMA: aperture base @ f0000000 size 65536 KB
[    0.455614] init_memory_mapping: 00000000f0000000-00000000f4000000
[    0.455617]  00f0000000 - 00f4000000 page 2M
[    0.455624] PCI-DMA: using GART IOMMU.
[    0.455628] PCI-DMA: Reserving 64MB of IOMMU area in the AGP aperture
[    0.456226] platform rtc_cmos: registered platform RTC device (no PNP device found)
[    0.456520] audit: initializing netlink socket (disabled)
[    0.456531] type=2000 audit(1286120951.456:1): initialized
[    0.459331] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[    0.460664] VFS: Disk quotas dquot_6.5.2
[    0.460720] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.460796] msgmni has been set to 8064
[    0.461031] alg: No test for stdrng (krng)
[    0.461084] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
[    0.461087] io scheduler noop registered
[    0.461089] io scheduler anticipatory registered
[    0.461090] io scheduler deadline registered
[    0.461121] io scheduler cfq registered (default)
[    0.461251]   alloc irq_desc for 24 on node 0
[    0.461253]   alloc kstat_irqs on node 0
[    0.461262] pcieport 0000:00:0a.0: irq 24 for MSI/MSI-X
[    0.461267] pcieport 0000:00:0a.0: setting latency timer to 64
[    0.461365]   alloc irq_desc for 25 on node 0
[    0.461367]   alloc kstat_irqs on node 0
[    0.461371] pcieport 0000:00:0b.0: irq 25 for MSI/MSI-X
[    0.461374] pcieport 0000:00:0b.0: setting latency timer to 64
[    0.461446]   alloc irq_desc for 26 on node 0
[    0.461448]   alloc kstat_irqs on node 0
[    0.461452] pcieport 0000:00:0c.0: irq 26 for MSI/MSI-X
[    0.461455] pcieport 0000:00:0c.0: setting latency timer to 64
[    0.461532]   alloc irq_desc for 27 on node 0
[    0.461533]   alloc kstat_irqs on node 0
[    0.461539] pcieport 0000:00:0d.0: irq 27 for MSI/MSI-X
[    0.461542] pcieport 0000:00:0d.0: setting latency timer to 64
[    0.461616]   alloc irq_desc for 28 on node 0
[    0.461618]   alloc kstat_irqs on node 0
[    0.461622] pcieport 0000:00:0e.0: irq 28 for MSI/MSI-X
[    0.461625] pcieport 0000:00:0e.0: setting latency timer to 64
[    0.461697]   alloc irq_desc for 29 on node 0
[    0.461698]   alloc kstat_irqs on node 0
[    0.461702] pcieport 0000:00:0f.0: irq 29 for MSI/MSI-X
[    0.461706] pcieport 0000:00:0f.0: setting latency timer to 64
[    0.462985] Linux agpgart interface v0.103
[    0.463030] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    0.463121] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    0.463350] input: Macintosh mouse button emulation as /devices/virtual/input/input0
[    0.463400] PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12
[    0.463817] serio: i8042 KBD port at 0x60,0x64 irq 1
[    0.463823] serio: i8042 AUX port at 0x60,0x64 irq 12
[    0.463899] mice: PS/2 mouse device common for all mice
[    0.463948] rtc_cmos rtc_cmos: RTC can wake from S4
[    0.463984] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0
[    0.464083] rtc0: alarms up to one year, y3k, 114 bytes nvram, hpet irqs
[    0.464093] cpuidle: using governor ladder
[    0.464095] cpuidle: using governor menu
[    0.464099] No iBFT detected.
[    0.464441] TCP cubic registered
[    0.464550] NET: Registered protocol family 10
[    0.465045] lo: Disabled Privacy Extensions
[    0.465348] Mobile IPv6
[    0.465351] NET: Registered protocol family 17
[    0.465435] PM: Resume from disk failed.
[    0.465445] registered taskstats version 1
[    0.465782] rtc_cmos rtc_cmos: setting system clock to 2010-10-03 15:49:12 UTC (1286120952)
[    0.465804] Initalizing network drop monitor service
[    0.465832] Freeing unused kernel memory: 584k freed
[    0.466134] Write protecting the kernel read-only data: 4216k
[    0.484379] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input1
[    0.552613] udev: starting version 160
[    0.636524] SCSI subsystem initialized
[    0.637160] usbcore: registered new interface driver usbfs
[    0.637189] usbcore: registered new interface driver hub
[    0.637231] usbcore: registered new device driver usb
[    0.650337] libata version 3.00 loaded.
[    0.653839] sata_nv 0000:00:05.0: version 3.5
[    0.653854]   alloc irq_desc for 20 on node 0
[    0.653856]   alloc kstat_irqs on node 0
[    0.653865] sata_nv 0000:00:05.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
[    0.653868] sata_nv 0000:00:05.0: Using SWNCQ mode
[    0.653965] sata_nv 0000:00:05.0: setting latency timer to 64
[    0.654099] scsi0 : sata_nv
[    0.654264] scsi1 : sata_nv
[    0.654304] ata1: SATA max UDMA/133 cmd 0x3000 ctl 0x3038 bmdma 0x2cd0 irq 20
[    0.654307] ata2: SATA max UDMA/133 cmd 0x3008 ctl 0x303c bmdma 0x2cd8 irq 20
[    0.654389]   alloc irq_desc for 21 on node 0
[    0.654391]   alloc kstat_irqs on node 0
[    0.654398] sata_nv 0000:00:05.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
[    0.654400] sata_nv 0000:00:05.1: Using SWNCQ mode
[    0.654441] sata_nv 0000:00:05.1: setting latency timer to 64
[    0.654543] scsi2 : sata_nv
[    0.654643] scsi3 : sata_nv
[    0.654680] ata3: SATA max UDMA/133 cmd 0x3010 ctl 0x3040 bmdma 0x2ce0 irq 21
[    0.654682] ata4: SATA max UDMA/133 cmd 0x3018 ctl 0x3044 bmdma 0x2ce8 irq 21
[    0.654749]   alloc irq_desc for 22 on node 0
[    0.654751]   alloc kstat_irqs on node 0
[    0.654756] sata_nv 0000:00:05.2: PCI INT C -> GSI 22 (level, low) -> IRQ 22
[    0.654758] sata_nv 0000:00:05.2: Using SWNCQ mode
[    0.654792] sata_nv 0000:00:05.2: setting latency timer to 64
[    0.654893] scsi4 : sata_nv
[    0.655000] scsi5 : sata_nv
[    0.655037] ata5: SATA max UDMA/133 cmd 0x3020 ctl 0x3048 bmdma 0x2cf0 irq 22
[    0.655039] ata6: SATA max UDMA/133 cmd 0x3028 ctl 0x304c bmdma 0x2cf8 irq 22
[    0.655677] forcedeth: Reverse Engineered nForce ethernet driver. Version 0.64.
[    0.655697] forcedeth 0000:00:08.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
[    0.655701] forcedeth 0000:00:08.0: setting latency timer to 64
[    0.655773] nv_probe: set workaround bit for reversed mac addr
[    0.657569] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    0.658938] Floppy drive(s): fd0 is 1.44M
[    0.660062] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
[    0.660070] ACPI: Power Button [PWRF]
[    0.676858] FDC 0 is a post-1991 82077
[    0.964019] ata5: SATA link down (SStatus 0 SControl 300)
[    0.964041] ata3: SATA link down (SStatus 0 SControl 300)
[    1.120021] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[    1.128199] ata1.00: HPA detected: current 976771055, native 976773168
[    1.128204] ata1.00: ATA-8: SAMSUNG HD503HI, 1AJ100E4, max UDMA/133
[    1.128207] ata1.00: 976771055 sectors, multi 0: LBA48 NCQ (depth 31/32)
[    1.136200] ata1.00: configured for UDMA/133
[    1.136300] scsi 0:0:0:0: Direct-Access     ATA      SAMSUNG HD503HI  1AJ1 PQ: 0 ANSI: 5
[    1.172750] forcedeth 0000:00:08.0: ifname eth0, PHY OUI 0x5043 @ 1, addr 00:e0:81:54:32:66
[    1.172754] forcedeth 0000:00:08.0: highdma csum vlan pwrctl mgmt gbit lnktim msi desc-v3
[    1.172932]   alloc irq_desc for 23 on node 0
[    1.172934]   alloc kstat_irqs on node 0
[    1.172943] ehci_hcd 0000:00:02.1: PCI INT B -> GSI 23 (level, low) -> IRQ 23
[    1.172990] ehci_hcd 0000:00:02.1: setting latency timer to 64
[    1.172992] ehci_hcd 0000:00:02.1: EHCI Host Controller
[    1.173020] ehci_hcd 0000:00:02.1: new USB bus registered, assigned bus number 1
[    1.173052] ehci_hcd 0000:00:02.1: debug port 1
[    1.173059] ehci_hcd 0000:00:02.1: cache line size of 64 is not supported
[    1.173079] ehci_hcd 0000:00:02.1: irq 23, io mem 0xf624a000
[    1.184015] ehci_hcd 0000:00:02.1: USB 2.0 started, EHCI 1.00
[    1.184038] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    1.184040] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.184043] usb usb1: Product: EHCI Host Controller
[    1.184044] usb usb1: Manufacturer: Linux 2.6.32-5-amd64 ehci_hcd
[    1.184046] usb usb1: SerialNumber: 0000:00:02.1
[    1.184126] usb usb1: configuration #1 chosen from 1 choice
[    1.184162] hub 1-0:1.0: USB hub found
[    1.184170] hub 1-0:1.0: 10 ports detected
[    1.184328] pata_amd 0000:00:04.0: version 0.4.1
[    1.184365] pata_amd 0000:00:04.0: setting latency timer to 64
[    1.184430] scsi6 : pata_amd
[    1.184497] scsi7 : pata_amd
[    1.184535] ata7: PATA max UDMA/133 cmd 0x1f0 ctl 0x3f6 bmdma 0x2cc0 irq 14
[    1.184537] ata8: PATA max UDMA/133 cmd 0x170 ctl 0x376 bmdma 0x2cc8 irq 15
[    1.269942] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    1.270108] ohci_hcd 0000:00:02.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22
[    1.270140] ohci_hcd 0000:00:02.0: setting latency timer to 64
[    1.270143] ohci_hcd 0000:00:02.0: OHCI Host Controller
[    1.270163] ohci_hcd 0000:00:02.0: new USB bus registered, assigned bus number 2
[    1.270186] ohci_hcd 0000:00:02.0: irq 22, io mem 0xf6245000
[    1.326021] usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
[    1.326024] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.326026] usb usb2: Product: OHCI Host Controller
[    1.326028] usb usb2: Manufacturer: Linux 2.6.32-5-amd64 ohci_hcd
[    1.326030] usb usb2: SerialNumber: 0000:00:02.0
[    1.326219] usb usb2: configuration #1 chosen from 1 choice
[    1.326254] hub 2-0:1.0: USB hub found
[    1.326265] hub 2-0:1.0: 10 ports detected
[    1.348277] ata7.00: ATAPI: Optiarc DVD RW AD-7173A, 1-03, max UDMA/66
[    1.348298] ata7: nv_mode_filter: 0x1f39f&0xfffff->0x1f39f, BIOS=0x0 (0x0) ACPI=0x0
[    1.364221] ata7.00: configured for UDMA/66
[    1.604021] ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[    1.612210] ata2.00: HPA detected: current 488395055, native 488397168
[    1.612215] ata2.00: ATA-7: SAMSUNG SP2504C, VT100-50, max UDMA7
[    1.612217] ata2.00: 488395055 sectors, multi 0: LBA48 NCQ (depth 31/32)
[    1.644222] ata2.00: configured for UDMA/133
[    1.644326] scsi 1:0:0:0: Direct-Access     ATA      SAMSUNG SP2504C  VT10 PQ: 0 ANSI: 5
[    1.649421] sd 0:0:0:0: [sda] 976771055 512-byte logical blocks: (500 GB/465 GiB)
[    1.649468] sd 0:0:0:0: [sda] Write Protect is off
[    1.649470] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[    1.649490] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    1.649625]  sda:
[    1.649829] sd 1:0:0:0: [sdb] 488395055 512-byte logical blocks: (250 GB/232 GiB)
[    1.649941] sd 1:0:0:0: [sdb] Write Protect is off
[    1.649944] sd 1:0:0:0: [sdb] Mode Sense: 00 3a 00 00
[    1.649963] sd 1:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    1.650094]  sdb: sdb1
[    1.655558] sd 1:0:0:0: [sdb] Attached SCSI disk
[    1.662515]  sda1 sda2 sda3
[    1.662976] sd 0:0:0:0: [sda] Attached SCSI disk
[    1.700019] usb 2-10: new low speed USB device using ohci_hcd and address 2
[    1.913040] usb 2-10: New USB device found, idVendor=1241, idProduct=1166
[    1.913042] usb 2-10: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    1.913112] usb 2-10: configuration #1 chosen from 1 choice
[    1.956018] ata4: SATA link down (SStatus 0 SControl 300)
[    2.268014] ata6: SATA link down (SStatus 0 SControl 300)
[    2.268906] scsi 6:0:0:0: CD-ROM            Optiarc  DVD RW AD-7173A  1-03 PQ: 0 ANSI: 5
[    2.269058] ata8: port disabled. ignoring.
[    2.288431]   alloc irq_desc for 18 on node 0
[    2.288435]   alloc kstat_irqs on node 0
[    2.288445] firewire_ohci 0000:01:0a.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
[    2.296035] sr0: scsi3-mmc drive: 48x/48x writer dvd-ram cd/rw xa/form2 cdda tray
[    2.296040] Uniform CD-ROM driver Revision: 3.20
[    2.296160] sr 6:0:0:0: Attached scsi CD-ROM sr0
[    2.308736] sd 0:0:0:0: Attached scsi generic sg0 type 0
[    2.309053] sd 1:0:0:0: Attached scsi generic sg1 type 0
[    2.309349] sr 6:0:0:0: Attached scsi generic sg2 type 5
[    2.312451] usbcore: registered new interface driver hiddev
[    2.322301] input: HID 1241:1166 as /devices/pci0000:00/0000:00:02.0/usb2/2-10/2-10:1.0/input/input3
[    2.322378] generic-usb 0003:1241:1166.0001: input,hidraw0: USB HID v1.00 Mouse [HID 1241:1166] on usb-0000:00:02.0-10/input0
[    2.322407] usbcore: registered new interface driver usbhid
[    2.322410] usbhid: v2.6:USB HID core driver
[    2.360014] firewire_ohci: Added fw-ohci device 0000:01:0a.0, OHCI version 1.10
[    2.360113]   alloc irq_desc for 16 on node 0
[    2.360116]   alloc kstat_irqs on node 0
[    2.360123] b43-pci-bridge 0000:01:08.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[    2.420069] ssb: Sonics Silicon Backplane found on PCI device 0000:01:08.0
[    2.571255] PM: Starting manual resume from disk
[    2.571260] PM: Resume from partition 8:1
[    2.571261] PM: Checking hibernation image.
[    2.571426] PM: Error -22 checking image file
[    2.571429] PM: Resume from disk failed.
[    2.597796] kjournald starting.  Commit interval 5 seconds
[    2.597805] EXT3-fs: sda2: orphan cleanup on readonly fs
[    2.613405] ext3_orphan_cleanup: deleting unreferenced inode 2232982
[    2.617439] ext3_orphan_cleanup: deleting unreferenced inode 2232990
[    2.625895] ext3_orphan_cleanup: deleting unreferenced inode 684190
[    2.629856] EXT3-fs: sda2: 3 orphan inodes deleted
[    2.629858] EXT3-fs: recovery complete.
[    2.649062] EXT3-fs: mounted filesystem with ordered data mode.
[    2.861112] firewire_core: created device fw0: GUID 0016e65600b7173c, S400
[    4.959141] udev: starting version 160
[    5.282636] processor LNXCPU:00: registered as cooling_device0
[    5.282675] processor LNXCPU:01: registered as cooling_device1
[    5.447582] input: PC Speaker as /devices/platform/pcspkr/input/input4
[    5.548955] parport_pc 00:04: reported by Plug and Play ACPI
[    5.548983] parport0: PC-style at 0x378, irq 7 [PCSPP,TRISTATE,EPP]
[    5.652091] parport_pc 00:05: reported by Plug and Play ACPI
[    5.835340] k8temp 0000:00:18.3: Temperature readouts might be wrong - check erratum #141
[    6.052109] i2c i2c-0: nForce2 SMBus adapter at 0x2c40
[    6.052130] i2c i2c-1: nForce2 SMBus adapter at 0x2c80
[    6.147276] [drm] Initialized drm 1.1.0 20060810
[    6.379495] cfg80211: Using static regulatory domain info
[    6.379499] cfg80211: Regulatory domain: US
[    6.379500] 	(start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
[    6.379505] 	(2402000 KHz - 2472000 KHz @ 40000 KHz), (600 mBi, 2700 mBm)
[    6.379506] 	(5170000 KHz - 5190000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
[    6.379510] 	(5190000 KHz - 5210000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
[    6.379511] 	(5210000 KHz - 5230000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
[    6.379513] 	(5230000 KHz - 5330000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
[    6.379515] 	(5735000 KHz - 5835000 KHz @ 40000 KHz), (600 mBi, 3000 mBm)
[    6.379612] cfg80211: Calling CRDA for country: US
[    6.665021] EDAC MC: Ver: 2.1.0 Sep 17 2010
[    6.697980] EDAC amd64_edac:  Ver: 3.2.0 Sep 17 2010
[    6.698064] EDAC amd64: This node reports that Memory ECC is currently disabled, set F3x44[22] (0000:00:18.3).
[    6.698072] EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will not load.
[    6.698073]  Either enable ECC checking or force module loading by setting 'ecc_enable_override'.
[    6.698075]  (Note that use of the override may cause unknown side effects.)
[    6.698092] amd64_edac: probe of 0000:00:18.2 failed with error -22
[    7.130438]   alloc irq_desc for 17 on node 0
[    7.130442]   alloc kstat_irqs on node 0
[    7.130452] nouveau 0000:07:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17
[    7.130457] nouveau 0000:07:00.0: setting latency timer to 64
[    7.133440] [drm] nouveau 0000:07:00.0: Detected an NV40 generation card (0x04b200a2)
[    7.133859] [drm] nouveau 0000:07:00.0: Attempting to load BIOS image from PROM
[    7.243034] b43-phy0: Broadcom 4318 WLAN found (core revision 9)
[    7.336472] [drm] nouveau 0000:07:00.0: ... appears to be valid
[    7.336476] [drm] nouveau 0000:07:00.0: BIT BIOS found
[    7.336478] [drm] nouveau 0000:07:00.0: Bios version 05.73.22.30
[    7.336481] [drm] nouveau 0000:07:00.0: TMDS table script pointers not stubbed
[    7.336484] [drm] nouveau 0000:07:00.0: BIT table 'd' not found
[    7.336486] [drm] nouveau 0000:07:00.0: Found Display Configuration Block version 3.0
[    7.336489] [drm] nouveau 0000:07:00.0: DCB connector table: VHER 0x30 5 10 2
[    7.336492] [drm] nouveau 0000:07:00.0:   0: 0x00001030: type 0x30 idx 0 tag 0x07
[    7.336495] [drm] nouveau 0000:07:00.0:   1: 0x00002130: type 0x30 idx 1 tag 0x08
[    7.336497] [drm] nouveau 0000:07:00.0:   2: 0x00000210: type 0x10 idx 2 tag 0xff
[    7.336500] [drm] nouveau 0000:07:00.0:   3: 0x00000211: type 0x11 idx 2 tag 0xff
[    7.336502] [drm] nouveau 0000:07:00.0:   4: 0x00000213: type 0x13 idx 2 tag 0xff
[    7.336505] [drm] nouveau 0000:07:00.0: Raw DCB entry 0: 01000300 00000028
[    7.336508] [drm] nouveau 0000:07:00.0: Raw DCB entry 1: 03000302 00000000
[    7.336510] [drm] nouveau 0000:07:00.0: Raw DCB entry 2: 04011320 00000028
[    7.336513] [drm] nouveau 0000:07:00.0: Raw DCB entry 3: 0c011322 00c00000
[    7.336515] [drm] nouveau 0000:07:00.0: Raw DCB entry 4: 020223f1 0040c080
[    7.336522] [drm] nouveau 0000:07:00.0: Parsing VBIOS init table 0 at offset 0xD50B
[    7.336593] [drm] nouveau 0000:07:00.0: Parsing VBIOS init table 1 at offset 0xDB97
[    7.392050] [drm] nouveau 0000:07:00.0: Parsing VBIOS init table 2 at offset 0xE281
[    7.392070] [drm] nouveau 0000:07:00.0: Parsing VBIOS init table 3 at offset 0xE3FC
[    7.411494] HDA Intel 0000:00:06.1: PCI INT B -> GSI 23 (level, low) -> IRQ 23
[    7.411499] hda_intel: Disable MSI for Nvidia chipset
[    7.411557] HDA Intel 0000:00:06.1: setting latency timer to 64
[    7.413243] phy0: Selected rate control algorithm 'minstrel'
[    7.413882] Registered led device: b43-phy0::tx
[    7.413904] Registered led device: b43-phy0::rx
[    7.413922] Registered led device: b43-phy0::radio
[    7.413990] Broadcom 43xx driver loaded [ Features: PMLS, Firmware-ID: FW13 ]
[    7.416055] [drm] nouveau 0000:07:00.0: Parsing VBIOS init table 4 at offset 0xE5EA
[    7.427600] [TTM] Zone  kernel: Available graphics memory: 2064860 kiB.
[    7.427614] [drm] nouveau 0000:07:00.0: 256 MiB VRAM
[    7.428417] [drm] nouveau 0000:07:00.0: 64 MiB GART (aperture)
[    7.428430] mtrr: type mismatch for e0000000,10000000 old: write-back new: write-combining
[    7.428539] [drm] nouveau 0000:07:00.0: Allocating FIFO number 0
[    7.429514] [drm] nouveau 0000:07:00.0: nouveau_channel_alloc: initialised FIFO 0
[    7.429521] [drm] nouveau 0000:07:00.0: Initial CRTC_OWNER is 0
[    7.429526] [drm] nouveau 0000:07:00.0: Saving VGA fonts
[    7.474616] [drm] nouveau 0000:07:00.0: Detected a DVI-I connector
[    7.474680] [drm] nouveau 0000:07:00.0: Detected a DVI-I connector
[    7.474717] [drm] nouveau 0000:07:00.0: Detected a TV connector
[    7.476050] [drm] nouveau 0000:07:00.0: Setting dpms mode 3 on vga encoder (output 0)
[    7.476054] [drm] nouveau 0000:07:00.0: Setting dpms mode 3 on tmds encoder (output 1)
[    7.476056] [drm] nouveau 0000:07:00.0: Setting dpms mode 3 on vga encoder (output 2)
[    7.476059] [drm] nouveau 0000:07:00.0: Setting dpms mode 3 on tmds encoder (output 3)
[    7.476062] [drm] nouveau 0000:07:00.0: Setting dpms mode 3 on TV encoder (output 4)
[    7.656375] [drm] nouveau 0000:07:00.0: allocated 1920x1200 fb: 0x49000, bo ffff88013e1f8600
[    7.669880] [drm] nouveau 0000:07:00.0: Output DVI-I-1 is running on CRTC 0 using output A
[    7.669885] [drm] nouveau 0000:07:00.0: 0xC941: Parsing digital output script table
[    7.724016] [drm] nouveau 0000:07:00.0: Setting dpms mode 0 on tmds encoder (output 1)
[    7.724019] [drm] nouveau 0000:07:00.0: Output DVI-I-1 is running on CRTC 0 using output A
[    7.725414] Console: switching to colour frame buffer device 240x75
[    7.726886] fb0: nouveaufb frame buffer device
[    7.726888] registered panic notifier
[    7.726893] [drm] Initialized nouveau 0.0.15 20090420 for 0000:07:00.0 on minor 0
[    8.132015] hda_codec: ALC883: BIOS auto-probing.
[    8.444105] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:06.1/input/input5
[    9.841744] Adding 4200956k swap on /dev/sda1.  Priority:-1 extents:1 across:4200956k 
[   10.198045] EXT3 FS on sda2, internal journal
[   10.316324] device-mapper: uevent: version 1.0.3
[   10.316586] device-mapper: ioctl: 4.15.0-ioctl (2009-04-01) initialised: dm-devel at redhat.com
[   10.498681] loop: module loaded
[   10.551290] powernow-k8: Found 1 AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ processors (2 cpu cores) (version 2.20.00)
[   10.551360] powernow-k8:    0 : fid 0x11 (2500 MHz), vid 0x9
[   10.551363] powernow-k8:    1 : fid 0x10 (2400 MHz), vid 0xa
[   10.551365] powernow-k8:    2 : fid 0xe (2200 MHz), vid 0xc
[   10.551367] powernow-k8:    3 : fid 0xc (2000 MHz), vid 0xe
[   10.551369] powernow-k8:    4 : fid 0x2 (1000 MHz), vid 0x12
[   10.599775] kvm: Nested Virtualization enabled
[   10.644466] it87: Found IT8716F chip at 0x290, revision 0
[   10.644476] it87: in3 is VCC (+5V)
[   10.644478] it87: in7 is VCCH (+5V Stand-By)
[   11.005018] Clocksource tsc unstable (delta = -209440066 ns)
[   11.281744] kjournald starting.  Commit interval 5 seconds
[   11.282240] EXT3 FS on sda3, internal journal
[   11.282252] EXT3-fs: mounted filesystem with ordered data mode.
[   13.228051] b43 ssb0:0: firmware: requesting b43/ucode5.fw
[   13.324250] b43 ssb0:0: firmware: requesting b43/pcm5.fw
[   13.403005] b43 ssb0:0: firmware: requesting b43/b0g0initvals5.fw
[   13.429650] b43 ssb0:0: firmware: requesting b43/b0g0bsinitvals5.fw
[   13.520031] b43-phy0: Loading OpenSource firmware version 410.31754
[   13.520040] b43-phy0: Hardware crypto acceleration not supported by firmware
[   13.520046] b43-phy0: QoS not supported by firmware
[   13.597995] ADDRCONF(NETDEV_UP): wlan0: link is not ready
[   16.680209] wlan0: direct probe to AP 00:23:69:c7:e9:aa (try 1)
[   16.683300] wlan0: direct probe responded
[   16.683306] wlan0: authenticate with AP 00:23:69:c7:e9:aa (try 1)
[   16.689513] wlan0: authenticated
[   16.689544] wlan0: associate with AP 00:23:69:c7:e9:aa (try 1)
[   16.696244] wlan0: RX AssocResp from 00:23:69:c7:e9:aa (capab=0x411 status=0 aid=1)
[   16.696250] wlan0: associated
[   16.698271] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
[   16.799898] padlock: VIA PadLock not detected.
[   20.526487] Bridge firewalling registered
[   20.548361] device dummy0 entered promiscuous mode
[   20.561830] br0: port 1(dummy0) entering forwarding state
[   21.764208] ip_tables: (C) 2000-2006 Netfilter Core Team
[   21.805102] nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
[   21.805876] CONFIG_NF_CT_ACCT is deprecated and will be removed soon. Please use
[   21.805882] nf_conntrack.acct=1 kernel parameter, acct=1 nf_conntrack module option or
[   21.805887] sysctl net.netfilter.nf_conntrack_acct=1 to enable it.
[   23.467133] fuse init (API version 7.13)
[   24.969940] RPC: Registered udp transport module.
[   24.969947] RPC: Registered tcp transport module.
[   24.969952] RPC: Registered tcp NFSv4.1 backchannel transport module.
[   25.303480] Installing knfsd (copyright (C) 1996 okir at monad.swb.de).
[   25.577088] svc: failed to register lockdv1 RPC service (errno 97).
[   25.579458] NFSD: Using /var/lib/nfs/v4recovery as the NFSv4 state recovery directory
[   25.593600] NFSD: starting 90-second grace period
[   26.756017] wlan0: no IPv6 routers present
[   29.553016] dummy0: no IPv6 routers present
[   31.257016] br0: no IPv6 routers present
[   31.621098] [drm] nouveau 0000:07:00.0: Allocating FIFO number 1
[   31.623664] [drm] nouveau 0000:07:00.0: nouveau_channel_alloc: initialised FIFO 1
[   32.069019] br1: no IPv6 routers present
[   32.878304] lp0: using parport0 (interrupt-driven).
[   33.573591] ppdev: user-space parallel port driver
[   78.974777] CPUFREQ: Per core ondemand sysfs interface is deprecated - up_threshold
[  182.316029] No probe response from AP 00:23:69:c7:e9:aa after 500ms, disconnecting.
[  276.185111] br0: port 1(dummy0) entering disabled state
[  276.252525] device dummy0 left promiscuous mode
[  276.252534] br0: port 1(dummy0) entering disabled state
[  276.568044] b43-phy0: Loading OpenSource firmware version 410.31754
[  276.568056] b43-phy0: Hardware crypto acceleration not supported by firmware
[  276.568062] b43-phy0: QoS not supported by firmware
[  276.649602] ADDRCONF(NETDEV_UP): wlan0: link is not ready
[  278.617418] wlan0: direct probe to AP 00:23:69:c7:e9:aa (try 1)
[  278.621323] wlan0: direct probe responded
[  278.621330] wlan0: authenticate with AP 00:23:69:c7:e9:aa (try 1)
[  278.623395] wlan0: authenticated
[  278.623439] wlan0: associate with AP 00:23:69:c7:e9:aa (try 1)
[  278.635343] wlan0: RX AssocResp from 00:23:69:c7:e9:aa (capab=0x411 status=0 aid=1)
[  278.635351] wlan0: associated
[  278.637450] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
[  280.762861] device dummy0 entered promiscuous mode
[  280.771875] br0: port 1(dummy0) entering forwarding state
[  288.857018] wlan0: no IPv6 routers present
[  289.768021] dummy0: no IPv6 routers present
[  291.409018] br0: no IPv6 routers present
[  292.516034] br1: no IPv6 routers present

From rminnich at gmail.com  Sun Oct  3 19:17:12 2010
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Oct 2010 10:17:12 -0700
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <20101001212759.GV3256@greenwood>
References: <20101001212759.GV3256@greenwood>
Message-ID: <AANLkTikwws193rL5Dv3+xeWwh3v1_m_NjLWRrMDzcqZB@mail.gmail.com>

OK, I've thought about why this patch makes me so uncomfortable. See
if I make sense.


The patch takes sequences like this:
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
-	movl	%eax, %cr0

and replaces them with this:

+	enable_cache()

Seems ok, right? Let's think about some rules in C:

int eax, ebx, ecx, edx;
eax = 1;
ebx = 2;
enable_cache();
ecx = eax;

Now, as we all know, in C, that function call won't affect those
variables. ecx will have a value of 2. We have a stack and there are
rules in C. So the variables are safe, and we're all used to thinking
that way. We think that way, in fact, by habit, even when looking at
assembly code. The syntax of the proposed patch makes it look very
much like a side-effect-free function call. That's one worry I have
all ready: it looks like a function, but it's not a function.

In other words, in C, local variables don't affect what goes on in the
function, and the function does not affect what goes on in local
variables. You don't have to go read the code for the function; that's
the whole point of a function. Functions provide a side-effect-free
way to get some operation done.

How different this is from assembly macros!

movl $2, %eax
enable_cache()
movl %eax, %ecx

If enable_cache is the function call it seems to be, %ecx will have 2.
As most of us know, it won't of course; it has some number with lots
of bits set, but it sure does not have 2.

Sure, we all know this; but what about a newcomer in 5 years; will
they know this?

So, what's the value of eax after the "call"? How can you know? Well,
you have to go read that code. You have to find the include file. You
have to have intimate understanding of the function, to make sure it
does not affect your "local variables" -- your registers. That's not a
function. The usage makes it look like a function, but it's not a
function. I think this practice is going to cause trouble.

So what are your options here? For each of the "functions", you can
track down the file, read the code, and make sure you understand it.
This is in my view *worse* than just having assembly code inline; you
have to hop around the tree but, more importantly, you have to
understand how the target is built, to make sure you're understanding
what's going on.

But wait! it gets worse! Just because you understand the file now
doesn't mean it won't change. You have to future-proof your code,
because, 5 or 10 years from now (some of the code is that old!), for
some new machine, somebody might make a change to enable_cache(), and
use one extra register, and break one target, and it might not be
noticed for a year. Yes, this sort of thing happens; it has happened
to me several times on different projects.

But wait! it gets worse! What if you are the person who wrote the
enable_cache() "function"? Then, if you ever need to change it, you
have to find each and every file that uses that function, and make
quite sure you understand the assembly code that surrounds the
"function", and make sure you won't break it. Now that's a lot of
work!

What if the function needs an extra parameter in a register due to
some new architecture? If that ever happens, and you need to add a new
register to the "function", you're going to have to once again find
all uses of it and fix all that code. Is it possible that in that
process errors might creep in? It's actually a certainty. Note that
we're build-testing, not boot-testing, a lot of these changes; that's
what broke one of my VIA boards -- permanently.

There is one way to future-proof the calls to these "functions". The
only safe assumption you can make after that "call" to disable_cache
is that all registers are dead: nothing safely carries across the
"call". Then I think you have less of a chance of a problem. That way,
one can make lots of changes to the functions and not have to track
down all uses to see if any are broken by it. Do you really want to do
this work? And are you sure that 5 years from now, new code authors
will be aware of that rule?

Just my $.015

ron



From wt at penguintechs.org  Sun Oct  3 19:17:42 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 10:17:42 -0700
Subject: [coreboot] [PATCH] Add CPP logic to VIA CAR init code.
In-Reply-To: <AANLkTinu++sxqomSeHiKmeRVo86gqCghg4+SUfns7NKO@mail.gmail.com>
References: <1286009972-6589-1-git-send-email-wt@penguintechs.org>
	<AANLkTimtK1VqYYNkxGXqLpz5Ao=N_kj4zKyLM8LTDXRV@mail.gmail.com>
	<4CA88675.9020303@coresystems.de>
	<AANLkTikVMmNo1jJv2MRFFkVpv_y5_WnkuR9=WJr=eYJt@mail.gmail.com>
	<AANLkTinu++sxqomSeHiKmeRVo86gqCghg4+SUfns7NKO@mail.gmail.com>
Message-ID: <AANLkTinQG1sZePDpDFFHuO8W9=ngWEZ0HkpPy-mejJwW@mail.gmail.com>

I think I see what is happening from the following explanation.
http://sourceware.org/binutils/docs-2.20/as/Symbol-Value.html#Symbol-Value

Kinda odd that the the symbol's value is only set to 0 after the
operators are applied to the symbol. I think this is why the file both
assembles without issue and the separate orl instruction works where
the "$(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK)" does not work. Does this
sound correct?

Thanks,
wt

On Sun, Oct 3, 2010 at 9:54 AM, Warren Turkal <wt at penguintechs.org> wrote:
> I see that is the change that fixed it. However, I'm still not sure I
> understand the fix completely. When CONFIG_TINY_BOOTBLOCK is defined
> and AUTO_XIP_ROM_BASE is not defined, we get the following line (line
> number 159 or so) in build/mainboard/via/vt8454c/crt0.s:
> ?movl $AUTO_XIP_ROM_BASE, %eax
>
> How does that assemble without an error?
>
> Is the AUTO_XIP_ROM_BASE set to some value (presumably 0) by the
> assembler for some reason that I don't see? For reference, here is the
> equivalent line from crt0.disasm:
> 100 0115 B8000000 >---->-------movl>---$REAL_XIP_ROM_BASE, %eax
>
> Thanks,
> wt
>
> On Sun, Oct 3, 2010 at 9:31 AM, Warren Turkal <wt at penguintechs.org> wrote:
>> Is this what your orl change fixed?
>>
>> wt
>>
>> On Sun, Oct 3, 2010 at 6:34 AM, Stefan Reinauer
>> <stefan.reinauer at coresystems.de> wrote:
>>> ?On 10/3/10 11:24 AM, Warren Turkal wrote:
>>>> *ping* I really need an ack or nack on this.
>>>
>>> NACK.. Still the wrong way, it just blindly comments out an arbitrary
>>> piece of code.
>>>
>>> However, the code has been fixed already in the repo.
>>>
>>> Stefan
>>>> Thanks,
>>>> wt
>>>>
>>>> On Sat, Oct 2, 2010 at 1:59 AM, Warren Turkal <wt at penguintechs.org> wrote:
>>>>> VIA/AMD experts,
>>>>>
>>>>> This patch get's the via/vt8454c back to building. However, I am not
>>>>> sure if the code that is being #ifdef'ed out will actually ever be used
>>>>> on a via platform. The code comes straight from the amd CAR
>>>>> implementation. A couple of questions are raised by this:
>>>>> 1) Should we just delete the code from the via file instead of this
>>>>> ? patch?
>>>>> 2) Should the amd and via CAR code be integrated into one file? Maybe
>>>>> ? just portions of the files if not the whole files?
>>>>>
>>>>> Also, another happy side effect of this change is that all the c7 boards
>>>>> seem to build with tiny bootblocks. Would everyone be ok with my making
>>>>> that change?
>>>>>
>>>>> Thanks,
>>>>> wt
>>>>> 8<----------------------------------------------------------------------
>>>>> The execute-in-place (XIP) config options need to be set in order to get
>>>>> XIP functionality, so it needs to be excluded when those settings are
>>>>> not set.
>>>>>
>>>>> Signed-off-by: Warren Turkal <wt at penguintechs.org>
>>>>> ---
>>>>> ?src/cpu/via/car/cache_as_ram.inc | ? ?4 ++++
>>>>> ?1 files changed, 4 insertions(+), 0 deletions(-)
>>>>>
>>>>> diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
>>>>> index be00fe3..d18ac3a 100644
>>>>> --- a/src/cpu/via/car/cache_as_ram.inc
>>>>> +++ b/src/cpu/via/car/cache_as_ram.inc
>>>>> @@ -85,6 +85,8 @@ clear_fixed_var_mtrr_out:
>>>>> ? ? ? ?movl ? ?$(~(CacheSize - 1) | 0x800), %eax
>>>>> ? ? ? ?wrmsr
>>>>>
>>>>> +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
>>>>> +
>>>>> ?#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
>>>>> ?#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
>>>>> ?#else
>>>>> @@ -106,6 +108,8 @@ clear_fixed_var_mtrr_out:
>>>>> ? ? ? ?movl ? ?$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
>>>>> ? ? ? ?wrmsr
>>>>>
>>>>> +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
>>>>> +
>>>>> ? ? ? ?/* Set the default memory type and enable fixed and variable MTRRs. */
>>>>> ? ? ? ?/* TODO: Or also enable fixed MTRRs? Bug in the code? */
>>>>> ? ? ? ?movl ? ?$MTRRdefType_MSR, %ecx
>>>>> --
>>>>> 1.7.1
>>>>>
>>>>>
>>>
>>>
>>> --
>>> coreboot mailing list: coreboot at coreboot.org
>>> http://www.coreboot.org/mailman/listinfo/coreboot
>>>
>>
>



From patrick.georgi at coresystems.de  Sun Oct  3 19:23:08 2010
From: patrick.georgi at coresystems.de (Patrick Georgi)
Date: Sun, 03 Oct 2010 19:23:08 +0200
Subject: [coreboot] [PATCH] Add CPP logic to VIA CAR init code.
In-Reply-To: <AANLkTinu++sxqomSeHiKmeRVo86gqCghg4+SUfns7NKO@mail.gmail.com>
References: <1286009972-6589-1-git-send-email-wt@penguintechs.org>	<AANLkTimtK1VqYYNkxGXqLpz5Ao=N_kj4zKyLM8LTDXRV@mail.gmail.com>	<4CA88675.9020303@coresystems.de>	<AANLkTikVMmNo1jJv2MRFFkVpv_y5_WnkuR9=WJr=eYJt@mail.gmail.com>
	<AANLkTinu++sxqomSeHiKmeRVo86gqCghg4+SUfns7NKO@mail.gmail.com>
Message-ID: <4CA8BBFC.1060807@coresystems.de>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Am 03.10.2010 18:54, schrieb Warren Turkal:
> I see that is the change that fixed it. However, I'm still not sure I
> understand the fix completely. When CONFIG_TINY_BOOTBLOCK is defined
> and AUTO_XIP_ROM_BASE is not defined, we get the following line (line
> number 159 or so) in build/mainboard/via/vt8454c/crt0.s:
>  movl $AUTO_XIP_ROM_BASE, %eax
> 
> How does that assemble without an error?
> 
> Is the AUTO_XIP_ROM_BASE set to some value (presumably 0) by the
> assembler for some reason that I don't see? For reference, here is the
> equivalent line from crt0.disasm:
> 100 0115 B8000000 >---->-------movl>---$REAL_XIP_ROM_BASE, %eax
This becomes a symbol in the .o file that is (must be) resolved on link
time. That's why it must be provided verbatim (without "|anything") in
the code.

What we _could_ do is to define REAL_XIP_ROM_BASE_WITH_FLAGS_SET (or
sth. to that effect) and run with that. It would eliminate the "orl"
line. I hesitated to do so because I wasn't sure if all systems use the
same flags (I didn't look if that's the case now), and didn't want to
provide lots of REAL_XIP_ROM_BASE_* for all combinations.


Patrick
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From phorsyon at gmx.net  Sun Oct  3 19:58:13 2010
From: phorsyon at gmx.net (phorsyon)
Date: Sun, 3 Oct 2010 19:58:13 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTikFnUWUcPRNwy8gw7cB12+egjfE8kkM=vy7+qBg@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net> <4CA7C8EA.2040501@gmx.net>
	<AANLkTikFnUWUcPRNwy8gw7cB12+egjfE8kkM=vy7+qBg@mail.gmail.com>
Message-ID: <201010031958.17479.phorsyon@gmx.net>

Hi!

I consider myself as enthusiast and would like to share my thoughts about 
coreboot certification and PR as a person from outside the coreboot project. I 
hope this will help you to see this project from another perspective and 
therefore helpful for your plans and further actions. Let me say I would 
really appreciate it, if vendors would ship their products preloaded with 
coreboot. ;-)

On Sunday 03 October 2010, Warren Turkal wrote:
> On Sat, Oct 2, 2010 at 5:06 PM, Carl-Daniel Hailfinger
> 
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
> > On 03.10.2010 01:28, Warren Turkal wrote:
> >> I think that a base coreboot certification should basically state that
> >> all the hardware on the board is usable with a major free OS (e.g.
> >> Linux-based OSes like Debian, Ubuntu, and Redhat maybe).
> >> 
> >> We could maybe have extended certifications for things like non-free
> >> OS and driver compatibility.
> > 
> > Well, if we only care about Linux, you can avoid most (if not all) of
> > ACPI on many machines, and you can avoid SeaBIOS as well. Heck, you
> > could even avoid FILO and require a Linux kernel in flash. Whether such
> > ab board would be usable for end users is a totally different question.
> 
> Booting into a certain OS is clearly not the only bar that we should
> be looking for. It would need to comply with various standards like
> ACPI, etc.

At first it would be helpful to define what you would like to achieve by 
introducing a coreboot certificate. Helping developers to find boards, which 
have basic support (as described earlier) for easy further development or 
helping users/customers to find boards which are coreboot compatible?

> > IMHO being able to install a Linux distribution from CD is an absolute
> > must even if you only target professional users in clusters etc.
> 
> I agree.
> 
> > Windows support means a board is usable by the general population, and
> > this is something vendors care about deeply.
> 
> Out of curiosity, are there actually non-niche vendors that ship
> Coreboot as their system firmware?

To make coreboot popular, it needs (a) a feature people want, (b) major 
vendors to deliver it and (c) available documentation for all components to 
make it work with most boards. These requirements are interdependent and must 
be solved as whole. To get c vendors must be convinced to want b and therefore 
coreboot needs a. So what's a? It surely is fast boot up, but depending on 
what your target audience is, it might also be boot non-free OSes and works 
with proprietary drivers. If you want to make vendors want b it's definitly 
required to target the average user.

> > We renamed LinuxBIOS to
> > coreboot exactly because people said all the time "I don't want Linux",
> > and EFI marketing would love to make fun of us if we ever said "Linux
> > only is good enough for certification".
> 
> I believe that most of the folks who care enough to use Coreboot at
> this time are probably running Linux or some other free OS. I also
> believe that most developers who have access to systems are probably
> running on or have easy access to some free OS. I also know that
> non-free OSes are not easily available to everyone. It's not that I
> believe that we can't test for non-free software support. It's just
> that I believe that certifying the boards for Coreboot should not gate
> on that having been done.

There is the possibility to depent on the vendors and the community. Vendors 
could test if non-free OSes work with coreboot (they test this anyway with 
their own BIOSes) and the community could assure this as well. That would 
require a place (e.g. the wiki) were the status of each board is tracked and 
an easy way to contribute. A Login would be required to keep the data on a 
sane level.

> Ideally, having some OS independent test suite would be the best
> approach I think, but I don't see that getting developed overnight. :)

That's automation. Automation is the second step. ;-)

> Maybe we should have multiple compliance levels like "Coreboot
> minimal" and "Coreboot standard"? The minimal could be some set of
> requirements. The standard could be the minimal requirements plus some
> extra set of requirements. We could also have tags for the compliance.
> These could be used to indicate special support like Windows or
> something like that.

If you think of a little certification logo/mark that vendors print on their 
boxes, then it has to be as simple and clear as possible. 

> Think of "Coreboot minimal" as enough to conveniently develop coreboot
> further without expensive and specialized hardware. Its requirement
> might look like the following:
> * Full initialization of the cpu and supporting chipset
>   - Intialized RAM
>   - Cooling systems should work enough to protect the system from
> burning itself up
> * At least one of the following:
>   - Outputs reasonable POST codes to a POST card if one can be plugged in
>   - USB debug ports enabled, if available on the board
>   - RS232 port enabled, if available on board
>   - Some other agreed method for debugging the system during Coreboot
> execution (e.g. debug LEDs on mobo, etc.)
> * At least one of the following
>   - At least one usb hub usable for keyboard, if one exists
>   - PS/2 port usable for keyboard, if one exists
> * All expansion slots initialized and usable
> * ACPI
>   - DSDT should exist
> * Able to load VGA option ROM
> * Able to boot into an OS not stored as a coreboot payload (e.g. boot
> from CD, USB, or SATA drive). For the minimal certfication, I believe
> that OS should be Debian since it's a well supported environment for
> developing coreboot.

What about calling it "Coreboot: Developer's Choice". Also freely available 
documentation would be a nice core requirement for that.

> Think of "Coreboot Standard" as basically fully tested with free OSes.
> Its requirements might look like the following:
> * all requirements of the minimal certification
> * Any requirement of the minimal certification that allows a subset to
> be implemented should implement all the sub-items. For example, both
> rs232 and usb debug ports should be enabled if they exists on the same
> board instead of implementing one or the other.
> * Uses tiny bootblock
> * Uses cache-as-ram if the system is capable
> * Soft poweroff works
> * Extended initialization of supporting chipset
>   - Fan uses vary speed based on temperature of CPU
> * All legacy io ports (i.e. rs232, parallel, etc.) usable
> * All USB ports usable
> * All other external (including header) ports usable (e.g. firewire,
> sound, etc.)
> * better ACPI support
>  - OSPM (e.g. G, S, D, and C states, etc.) fully exposed and usable
> * CPU frequency scaling works
> * After booting into Debian Linux, the OS should be able to rely on
> any info provided by the Coreboot and any intervening payloads should
> allow the system to be fully enumerated and configured as much as the
> hardware will allow.

This would target the normal user, so I would call it "Coreboot compatible" or 
"Coreboot approved". This mark should assure that all parts of the board work, 
meaning every feature, expected by the average user, hhis is important to 
please them. So that this mark actually means something to them. If they have 
a good reason to care about it, also the vendors have one, and this would give 
the coreboot project the authority dictate such high standards.

Things normal users care about to work:
- All build-in components (net, snd, gfx)
- All ports/expansion slots (exceptions: rs232, parallel, floppy)
- Everything related to power management as supported by the underlying 
hardware and drivers (All power states, ACPI). Also needed to improve drivers.
- Add-on components most importantly Nvidia/ATI cards
- The OS of choice (BSD, Linux, Windows)
- fast booting

Things normal users don't care about:
- most legacy stuff like rs232, parallel, floppy
- pro features like *PXE, AoE, iSCSI (Those could be combined under a logo 
like "Coreboot for Professionals")
- OSes besides the ones they use

> Tags could be used to identify specific extended support. For
> instance, a system certified to boot Windows 7 could be "Coreboot
> minimal+MSWin7" certified or "Coreboot standard+MSWin7" certified or
> something like that. If anyone wanted to display the certification,
> they could display it with or without the tags.
> 
> Possible tags:
> MSWin{XP,7}
> ReactOS
> GPXE
> AOE
> ISCSI
> ...

For OSes, users will expect that the major ones (BSD, Linux, Windows) will 
work flawlessy if labeled "Coreboot compatible". So if you focus on the average 
user, this should be respected. Listing the other features separately is a 
good idea, as normal users mostly won't care about them, but experienced users 
get the chance to check for them. To keep the logo itself simple, the feature 
list should be separated from the logo e.g. printed on the backside of a 
package. Or as mentioned above combined to another logo like "Coreboot for 
Professionals"

> We should probably note the known revisions that are compliant for
> each board. This doesn't mean that every revision that would pass the
> requirements needs to be listed. Only tested versions should be
> listed. Those revisions would be the recommended revisions with users
> using other revisions at their own risk. I could imagine something
> like the following for a mobo:
> minimal: 11 99 103 150
> standard: 50 75 135 155
> minimal+Win7: 77
> 
> The numbers are the Coreboot svn revisions that are tested. These
> revisions should probably be listed in the wiki somewhere. There is
> probably some better way to visualize the data. We may also need to
> list SeaBIOS hashes for the certified builds.

Keeping track of detailed information in the wiki is a good thing. If vendors 
decide to deliver coreboot it should be as easy as possible for them.

> *snip*
> 
> >> Frankly, I think that ability to use the free drivers should be good
> >> enough. We shouldn't be hold out any kind of coreboot certification on
> >> the condition that non-free drivers work.
> > 
> > There are two aspects of the problem:
> > - We can't test everything (fact of life)
> > - Closed-source drivers have a huge market share, and won't go away any
> > time soon
> 
> Agreed. I also think that some developers won't be able to test
> certain non-free software. For instance, I wouldn't be able to test
> that Windows 7 boots. I also don't have an Nvidia card to test their
> drivers.

That's were vendors and community could help out. See above.

> Given the fact that we can't test everything, we should make a minimal
> amount of compliance only include things that can be tested by most
> folks. I think that minimally certified hardware should really be
> capable enough to develop Coreboot further on the hardware
> conveniently. Standard certified hardware should work well for free
> OSes if the OSes have appropriate driver support.

That's why I would go for "Coreboot: Developer's Choice" and "Coreboot 
compatible" (or "Coreboot powered" for actual boards preloaded with coreboot), 
it makes it much clearer in my opinion. If there's one think you don't won't a 
certification mark to do, then it's confusing people more than helping them.

> Also, minimally certified hardware can support more features. For
> example, a minimally certified board could have logic for adjusting
> fan speed intelligently. It would still be minimally certified until
> someone developed the rest of the functionality for the standard level
> certification and tested it.

Agreed.

> *snip*
> 
> > Fans can be loud. If all fans run at 100% non-stop, machines can be
> > essentially unusable for noise reasons.
> 
> While I agree with this, I think that a minimally certified piece of
> hardware should not need working fan logic.

True, developers should be able to deal with it, but for users it's a must 
have feature.

> *snip*
> 
> > Indeed, but given that vendor code may not always be suitable for
> > merging, do we want to withhold certification if code is available but
> > not merged? And what happens if Kevin is on vacation?
> 
> If the code's not merged into SeaBIOS, we shouldn't certify the build.
> If Kevin is the only person that can merge push the canonical SeaBIOS
> tree, then I suppose it would need to wait on him. It's the same way
> that a vendor can't really claim that their hardware with compliant
> with Microsoft's certifications until MS signs off.

True, but to respect vendors and how they work (e.g. deadlines etc.), it would 
be clever to keep up a communication channel to announce e.g. "no certification 
from X to Y (due to $REASON)". This allows vendors to plan. The point being 
always try to work with, never against each other. ;-)

> If it really becomes a problem that vendors want the certification
> during a time when Kevin isn't around, that would be a good problem
> for the project to have. :)

Yes that's somehow true, but to some extend this could also be considered 
mismanagement. To prevent those situations each vendor would have to have (at 
least) one employee to stay in contact with coreboot project, which would have 
to ask for one. Also interproject communication (e.g. between flashrom, 
coreboot and seabios) is vital. I can't tell how this works atm., I assume 
quite good, but what I'm trying to point out is, that vendors (and users) are 
always looking for a complete package to solve their problems. Therefore I 
consider the free boot up infrastructure, meaning flashrom, coreboot and 
seabios, as a whole package. This makes working hand in hand very important.

> *snip*
> 
> Comments would be appreciated, especially on the minimal and standard
> certification requirements above. Also, please take a look at the tags
> and see if you can think of any additions.
> 
> Thanks,
> wt

Please keep in mind that I'm neither involved in the coreboot project or any 
related projects nor do I work for a hardware vendor. I simply try to express 
how I see the whole picture with the hope this could be of any help for your 
project.

Thanks,
phorsyon



From uwe at hermann-uwe.de  Sun Oct  3 20:47:35 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 3 Oct 2010 20:47:35 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
Message-ID: <20101003184734.GF3256@greenwood>

See patch.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
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From patrick at georgi-clan.de  Sun Oct  3 21:18:25 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 03 Oct 2010 21:18:25 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <20101003184734.GF3256@greenwood>
References: <20101003184734.GF3256@greenwood>
Message-ID: <4CA8D701.5010203@georgi-clan.de>

Am 03.10.2010 20:47, schrieb Uwe Hermann:
> -	movl	$0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
> -	jmp_if_k8(wbcache_post_fam10_setup)
> -	movl	$0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
> -wbcache_post_fam10_setup:
> +	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
This was to allow a single image to run through CAR with both K8 and
Fam10. I suppose that's not necessary anymore, given that the bootblock
doesn't use CAR, and any chip selection can and should happen there.

So I think it's safe to go ahead with that one - just stating since
you're seriously changing behaviour here.


Patrick



From xdrudis at tinet.cat  Sun Oct  3 21:28:39 2010
From: xdrudis at tinet.cat (xdrudis)
Date: Sun, 3 Oct 2010 21:28:39 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTikFnUWUcPRNwy8gw7cB12+egjfE8kkM=vy7+qBg@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTik1FboBixuj6ShKA+YfyKh=fdff2cdrnreCsu_u@mail.gmail.com>
	<4CA7C8EA.2040501@gmx.net>
	<AANLkTikFnUWUcPRNwy8gw7cB12+egjfE8kkM=vy7+qBg@mail.gmail.com>
Message-ID: <20101003192839.GB12660@ideafix.casa.ct>


My .02 from an end user (wannabe) pov:

In general I agree with Warren Turkal: 

I'd like a certification that ensures coreboot and free sofware work
with the hardware, irrelevant of what happens with non-free
software. I don't mind having other certification (tags) for non-free
software for whoever cares about it.  What I would regret having less
hardware certified because there wasn't a certification option for
free software uses. Coreboot is good for many things and one of them
is getting rid of legacy where possible. Requiring everyone to support
legacy just because it is a current big market segment will only
perpetuate this legacy burdened market. The argument works exchanging
non-free software with legacy, only that non-free software is nastier
than legacy. So legacy, nonfre-software should be optional for certification.
Free software support should be required for any certification, 
then some would also tag windows7 or whatever.

It would require some credible organization doing the tests, I
guess. Or maybe it would be a kind of trust system ? (the different
certificates and their exact meaning would be clear, then anyone could
certify some hard and customers would decide whether they believe a
certificate signed by one or other party, or even self signed by
a vendor).

The tests should be reproducible, so the exact versions of kernel,
distribution, etc.  should be stated, even if a particular choice is
not a requirement, documenting the choice tested should be.

There should be non-technical requirements too:
- support code GPLed and integrated
- maybe security criteria ? I don't know about it
- something on availability of the tested hardware ?

A problem I can see is what gets certified precisely . a mainboard?
a whole computer ? whatever as long as it is clearly stated ?

My experience is that of a consumer trying to buy hardware to
use with coreboot. I picked every component in my new PC according
to price, the performance I wanted and the information on coreboot.org,
more or less accepting the risk for the parts apparently less well
supported.

And I mostly got what I expected except partly with the CPU.
I would have liked more precise lists of what CPU models have 
been tested. I can't be sure but I suspect that my particular CPU wouldn't 
work on any supported mainboard right now (well, not even the shipped 
BIOS worked until I upgraded it). I've found out that the 
information on documentation of the CPU was accurate, an so it is 
just a matter of time/effort until it works, but the 
site gave the impression that any AMD CPU would work (there were lists
of mainboards and chipsets, but the CPU part was not very detailed, beyond 
brand or family). Then looking at the code I found some revisions didn't
even have a position in a bitfield. 

What I mean is that if it is a board that gets certified, then a customer
may buy it and put a new CPU there that doesn't work with coreboot. It may
happen with other hardware, but I can't think of any example. Maybe RAM ?
 
On Sun, Oct 03, 2010 at 02:15:44AM -0700, Warren Turkal wrote:
> On Sat, Oct 2, 2010 at 5:06 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
[...]
> > Well, if we only care about Linux, you can avoid most (if not all) of
> > ACPI on many machines, and you can avoid SeaBIOS as well. Heck, you
> > could even avoid FILO and require a Linux kernel in flash. Whether such
> > ab board would be usable for end users is a totally different question.
> 

So what ? If a consumer can buy a system with coreboot and gnu and linux 
that works and gives her all due freedoms why should she care for ACPI,etc?

I understand most users will want more, I just wouldn't rule out a certificate
option unrelated to legacy or current standards. Maybe some vendor wants 
to offer some advanced features that is too cumbersome to adapt to ACPI...
Or open hardware vendors may opt for just skipping ACPI and just giving
the hardware details and linux drivers...

> Booting into a certain OS is clearly not the only bar that we should
> be looking for. It would need to comply with various standards like
> ACPI, etc.
> 

It might be one of the bars. On the other hand ACPI compliance could
be certified by the ACPI consortium (there is one, I guess...), maybe .
Likewise for any other standard.

> > IMHO being able to install a Linux distribution from CD is an absolute
> > must even if you only target professional users in clusters etc.
> 
> I agree.
>

I agree  one of the certification options should require it
 
> > Windows support means a board is usable by the general population, and
> > this is something vendors care about deeply.
> 

And is something we don't need to help stay the same. So I say require it
only for some of the optional tags.

> > We renamed LinuxBIOS to
> > coreboot exactly because people said all the time "I don't want Linux",
> > and EFI marketing would love to make fun of us if we ever said "Linux
> > only is good enough for certification".
>

Laughing is healthy. Let them laugh.
I don't see the marketing problem if there are windows tags.
 
> I believe that most of the folks who care enough to use Coreboot at
> this time are probably running Linux or some other free OS. I also
> believe that most developers who have access to systems are probably
> running on or have easy access to some free OS. I also know that
> non-free OSes are not easily available to everyone. It's not that I
> believe that we can't test for non-free software support. It's just
> that I believe that certifying the boards for Coreboot should not gate
> on that having been done.
> 

Well, if A wants B to certify that coreboot supports OS W
on hardware H I guess A should contribute any changes to coreboot and
give B the hardware H and the necessary W licenses, if A can find some
B willing to use W. If W was free software the requirement would be
the same but it'd be much easier to comply with. If W license was
particulary nasty it might even be impossible to use W for testing
coreboot.

But A shouldn't be required to have any deal with windows to certificate
coreboot works in H without windows. SO corebot+windows certification
should generally be more expensive/cumbersome than
coreboot+freesoftware certification only (depending on the case, maybe
coreboot+hurd may be difficult to certify...). Sounds logical.

> Ideally, having some OS independent test suite would be the best
> approach I think, but I don't see that getting developed overnight. :)
> 

Is that feasible at all?

> Maybe we should have multiple compliance levels like "Coreboot
> minimal" and "Coreboot standard"? The minimal could be some set of
> requirements. The standard could be the minimal requirements plus some
> extra set of requirements. We could also have tags for the compliance.
> These could be used to indicate special support like Windows or
> something like that.
>

Very reasonable.
 
> * ACPI
>   - DSDT should exist

Is that needed to develop coreboot further ? Not sure it should be 
required for minimal. Maybe split minimal and minimal + DSDT

> * Able to load VGA option ROM

unless they find a way not to use it, like free framebuffer drivers
or so on ? If propietary software is not a requirement, propietary
firmware shouldn't either, whenever it can be worked around.

> * Able to boot into an OS not stored as a coreboot payload (e.g. boot
> from CD, USB, or SATA drive). For the minimal certfication, I believe
> that OS should be Debian since it's a well supported environment for
> developing coreboot.
>

I would simply say that it should boot a system that allows coreboot
development using only free software, and it should document which precise system,
version, etc. it is. Of course depending on what it is it may be easier 
or harder to find certifiers (or customers once certified).

And then we come to the thorny issue of what does "only free software" mean,
since debian for instance includes kernel blobs or similar issues...
 
> 
> Possible tags:
> MSWin{XP,7}
> ReactOS
> GPXE
> AOE
> ISCSI
> ...
>

The process for adding tags to the certification criteria should be 
clear and simple. We won't be able to find all useful tags from the 
start.

Something about power saving capabilities would be useful, not sure
what or how...
 
> We should probably note the known revisions that are compliant for
> each board. This doesn't mean that every revision that would pass the
> requirements needs to be listed. Only tested versions should be
> listed. Those revisions would be the recommended revisions with users
> using other revisions at their own risk. I could imagine something
> like the following for a mobo:
> minimal: 11 99 103 150
> standard: 50 75 135 155
> minimal+Win7: 77
> 

Ok. Adding the rest of hardware and software tested, like
Debian lenny , AMD Phenom II X4 910e, such and such DDR3 DIMMs,
such VGA...
The more diverse hardware and software tested the more work
to certify it, and the more tempting for consumers, who would 
evaluate the risk of using it with other hardware or software. 
One could risk buying a certified system with different amount 
of RAM than tested and install a different distribution, etc.
 
> >> Frankly, I think that ability to use the free drivers should be good
> >> enough. We shouldn't be hold out any kind of coreboot certification on
> >> the condition that non-free drivers work.
> >

ACK

> > There are two aspects of the problem:
> > - We can't test everything (fact of life)
> > - Closed-source drivers have a huge market share, and won't go away any
> > time soon
> 
> Agreed. I also think that some developers won't be able to test
> certain non-free software. For instance, I wouldn't be able to test
> that Windows 7 boots. I also don't have an Nvidia card to test their
> drivers.
> 

And if you test and find that it doesn't work with non-free drivers, 
that is an answer, but not very productive, is there a problem in some 
initialisation in coreboot or in the driver? You can't fix the driver, 
so supporting it is a tall order, so optional.

> 
> If the code's not merged into SeaBIOS, we shouldn't certify the build.

Yes. Not sure SeaBIOS is needed for the most basic certification, 
but in general if any support code is not commited then certification
should wait. Not sure this is a huge problem, I'd say one wants to
benefit from the community testing stuff before paying or otherwise
causing someone to thoroughly test for certification. So waiting
until a little after committed would be wise. Although I guess 
hardware is obsoleted quickly and vendors may want certification 
before they put it on the market... so I don't know how much of a 
burden this is, but I think it should be required. If Google Summer
of Code candidates where required to send patches, vendors should
be required to have support code good enough for being merged.

Sorry for being verbose. 



From c-d.hailfinger.devel.2006 at gmx.net  Sun Oct  3 22:51:34 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 03 Oct 2010 22:51:34 +0200
Subject: [coreboot] MSI 890GXM-G65
In-Reply-To: <AANLkTini1z9W7tN5Tk_kgQmDbzxU2gze6+77iLE=gmNu@mail.gmail.com>
References: <AANLkTini1z9W7tN5Tk_kgQmDbzxU2gze6+77iLE=gmNu@mail.gmail.com>
Message-ID: <4CA8ECD6.3090005@gmx.net>

Hi Mattias,

On 03.10.2010 18:08, Mattias Mattsson wrote:
> I'm thinking of trying to port coreboot to MSI 890GXM-G65 (MS-7642):
> http://www.msi.com/index.php?func=proddesc&prod_no=2012
>
> I do not own it (yet), so I only now the specs from the manual:
>
> North Bridge: AMD 890GX chipset
> South Bridge: AMD SB850 chipset
>   

I heard rumors that AMD 890GX/SB850 support is in the works, but it may
take some time to materialize, and I don't know who is working on it.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Sun Oct  3 23:04:32 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 03 Oct 2010 23:04:32 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <4CA8D701.5010203@georgi-clan.de>
References: <20101003184734.GF3256@greenwood> <4CA8D701.5010203@georgi-clan.de>
Message-ID: <4CA8EFE0.3040704@gmx.net>

On 03.10.2010 21:18, Patrick Georgi wrote:
> Am 03.10.2010 20:47, schrieb Uwe Hermann:
>   
>> -	movl	$0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
>> -	jmp_if_k8(wbcache_post_fam10_setup)
>> -	movl	$0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
>> -wbcache_post_fam10_setup:
>> +	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
>>     
> This was to allow a single image to run through CAR with both K8 and
> Fam10. I suppose that's not necessary anymore, given that the bootblock
> doesn't use CAR, and any chip selection can and should happen there.
>   

I want to be able to use my socket AM2+ board with K8 and Fam10
processors. If I also want fallback/normal images, this change forces me
to use 4 images instead of 2. And yes, people who use mainboards
actually may expect to be able to use processors from different
generations if the "normal" BIOS can handle that as well.
Due to that, I'd say Nack, but if you have strong technical reasons
(instead of cosmetic reasons) which result in a net benefit to end users
even if you factor in the feature loss, I will retract the Nack.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From patrick at georgi-clan.de  Sun Oct  3 23:07:27 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 03 Oct 2010 23:07:27 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <4CA8EFE0.3040704@gmx.net>
References: <20101003184734.GF3256@greenwood>
	<4CA8D701.5010203@georgi-clan.de> <4CA8EFE0.3040704@gmx.net>
Message-ID: <4CA8F08F.50307@georgi-clan.de>

Am 03.10.2010 23:04, schrieb Carl-Daniel Hailfinger:
> I want to be able to use my socket AM2+ board with K8 and Fam10
> processors. If I also want fallback/normal images, this change forces me
> to use 4 images instead of 2. And yes, people who use mainboards
> actually may expect to be able to use processors from different
> generations if the "normal" BIOS can handle that as well.
> Due to that, I'd say Nack, but if you have strong technical reasons
> (instead of cosmetic reasons) which result in a net benefit to end users
> even if you factor in the feature loss, I will retract the Nack.
You're still required to have an image for K8 and Fam10 each, simply
because we don't support runtime selection of northbridge code in the
romstage.

The only thing I worked on was getting through CAR on either CPU, then
jumped into the "right" image right afterwards (as was usual in pre-CBFS
images)

So we can debate if we want to keep the current support, but that
requires more work (architecture changes in coreboot) to support
multiple northbridges in all places, not just CAR.


Patrick



From uwe at hermann-uwe.de  Sun Oct  3 23:59:47 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 3 Oct 2010 23:59:47 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <4CA8F08F.50307@georgi-clan.de>
References: <20101003184734.GF3256@greenwood> <4CA8D701.5010203@georgi-clan.de>
	<4CA8EFE0.3040704@gmx.net> <4CA8F08F.50307@georgi-clan.de>
Message-ID: <20101003215947.GG3256@greenwood>

On Sun, Oct 03, 2010 at 11:07:27PM +0200, Patrick Georgi wrote:
> Am 03.10.2010 23:04, schrieb Carl-Daniel Hailfinger:
> > I want to be able to use my socket AM2+ board with K8 and Fam10
> > processors. If I also want fallback/normal images, this change forces me
> > to use 4 images instead of 2. And yes, people who use mainboards
> > actually may expect to be able to use processors from different
> > generations if the "normal" BIOS can handle that as well.
> > Due to that, I'd say Nack, but if you have strong technical reasons
> > (instead of cosmetic reasons) which result in a net benefit to end users
> > even if you factor in the feature loss, I will retract the Nack.
> You're still required to have an image for K8 and Fam10 each, simply
> because we don't support runtime selection of northbridge code in the
> romstage.
> 
> The only thing I worked on was getting through CAR on either CPU, then
> jumped into the "right" image right afterwards (as was usual in pre-CBFS
> images)
> 
> So we can debate if we want to keep the current support, but that
> requires more work (architecture changes in coreboot) to support
> multiple northbridges in all places, not just CAR.

I don't have plans to remove the possiblity for that in this patch.
Updated version attached which preserves the run-time choice, but
adds some hopefully correct comment.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
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From patrick at georgi-clan.de  Mon Oct  4 00:27:02 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 04 Oct 2010 00:27:02 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <20101003215947.GG3256@greenwood>
References: <20101003184734.GF3256@greenwood>
	<4CA8D701.5010203@georgi-clan.de> <4CA8EFE0.3040704@gmx.net>
	<4CA8F08F.50307@georgi-clan.de> <20101003215947.GG3256@greenwood>
Message-ID: <4CA90336.5010308@georgi-clan.de>

Am 03.10.2010 23:59, schrieb Uwe Hermann:
> +	/*
> +	 * Important: The code below makes a run-time decision depending on
> +	 * whether this is a K8 or Fam10h system. Depending on which it is,
> +	 * the CONFIG_CPU_ADDR_BITS_MASK value might be be different.
> +	 */
>  	movl	$MTRRphysMask_MSR(1), %ecx
> -	movl	$0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
> +	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx /* K8 */
>  	jmp_if_k8(wbcache_post_fam10_setup)
> -	movl	$0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
> +	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx /* Fam10h */
>  wbcache_post_fam10_setup:
>  	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
>  	wrmsr
> +
>  #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
How is this supposed to work?
"Set to the build specific value, and if it is fam10 (ie. jmp_if_k8 not
taken), set to the build specific value again"?


Curiously,
Patrick



From stefan.reinauer at coresystems.de  Mon Oct  4 00:48:42 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Mon, 04 Oct 2010 00:48:42 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <20101003215947.GG3256@greenwood>
References: <20101003184734.GF3256@greenwood>
	<4CA8D701.5010203@georgi-clan.de>	<4CA8EFE0.3040704@gmx.net>
	<4CA8F08F.50307@georgi-clan.de> <20101003215947.GG3256@greenwood>
Message-ID: <4CA9084A.9080704@coresystems.de>

 On 10/3/10 11:59 PM, Uwe Hermann wrote:
> +config CPU_ADDR_BITS_MASK
> +	hex
> +	default 0x00000000 if CPU_ADDR_BITS_32
> +	default 0x0000000f if CPU_ADDR_BITS_36
> +	default 0x000000ff if CPU_ADDR_BITS_40
> +	default 0x0000ffff if CPU_ADDR_BITS_48
> +	help
> +	  Map the number of address space bits supported by the CPU to the
> +	  mask field value as it needs to be written into the upper 32 bits
> +	  of the various MTRRphysMask_MSR MSRs.
> +
Such stuff belongs into an include file, not into Kconfig.



From uwe at hermann-uwe.de  Mon Oct  4 00:57:30 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 4 Oct 2010 00:57:30 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <4CA90336.5010308@georgi-clan.de>
References: <20101003184734.GF3256@greenwood> <4CA8D701.5010203@georgi-clan.de>
	<4CA8EFE0.3040704@gmx.net> <4CA8F08F.50307@georgi-clan.de>
	<20101003215947.GG3256@greenwood> <4CA90336.5010308@georgi-clan.de>
Message-ID: <20101003225730.GO6119@greenwood>

On Mon, Oct 04, 2010 at 12:27:02AM +0200, Patrick Georgi wrote:
> Am 03.10.2010 23:59, schrieb Uwe Hermann:
> > +	/*
> > +	 * Important: The code below makes a run-time decision depending on
> > +	 * whether this is a K8 or Fam10h system. Depending on which it is,
> > +	 * the CONFIG_CPU_ADDR_BITS_MASK value might be be different.
> > +	 */
> >  	movl	$MTRRphysMask_MSR(1), %ecx
> > -	movl	$0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
> > +	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx /* K8 */
> >  	jmp_if_k8(wbcache_post_fam10_setup)
> > -	movl	$0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
> > +	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx /* Fam10h */
> >  wbcache_post_fam10_setup:
> >  	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
> >  	wrmsr
> > +
> >  #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
> How is this supposed to work?
> "Set to the build specific value, and if it is fam10 (ie. jmp_if_k8 not
> taken), set to the build specific value again"?

Hm, seems I misunderstood how this works. I was under the impression
such a two-image solution (K8 + Fam10h code in one coreboot.rom) would
also set two different CONFIG_CPU_ADDR_BITS_MASK values, one for K8, and
one for Fam10h. And if the K8 image is running it will use
CONFIG_CPU_ADDR_BITS_MASK (=40) at runtime, but if the Fam10h image runs
it would use CONFIG_CPU_ADDR_BITS_MASK (=48) instead.
That's probably not how it would work though, it seems?

Anyway, I'll just leave this snippet alone for now. Updated patch will
follow, need to fix another kconfig-related issue brought up by Peter.

But note that the current form is also a bit dangerous. It hardcodes 40bits
for K8 and 48bits for Fam10h here unconditionally. I don't know if this
assumption is always correct for all CPUs. Using the correct per-CPU
CONFIG_CPU_ADDR_BITS_MASK would definately be safer (if this mechanism
can work here at all). Are we sure there are no K8 systems that support
CPUs with bits != 40? Are we sure there are no Fam10h CPUs with
bits != 48 (and that there never will be in the future)?


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From peter at stuge.se  Mon Oct  4 01:10:14 2010
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Oct 2010 01:10:14 +0200
Subject: [coreboot] PCI register read/mod/write code
Message-ID: <20101003231014.23261.qmail@stuge.se>

Rudolf just found a bug in the sb700 code:

u32 dword;
..
dword = pci_read_config8(dev, 0x64);
dword |= 1 << 10;
pci_write_config8(dev, 0x64, dword);


And I'm ranting now, because a pci_set8() macro/function could have
found this bug at compile time, and because I don't like these
constructs. (Compiler warnings would also have indicated a problem.
They're currently disabled for this code.)

Carl-Daniel is working on a patch, meanwhile consider this:

#define pci_set8(dev, reg, val) do { \
  if ((a) & ~0xff) can_only_set_low_8_bits(); \
  pci_set8_nocheck((dev), (reg), (val)); \
} while(0)

u8 pci_set8_nocheck(device_t dev, u32 reg, u8 val) {
  u8 tmp = pci_read_config8(dev, reg);
  tmp |= val;
  pci_write_config8(dev, reg, tmp);
  return tmp;
}

$ gcc -g -o a a.c
/tmp/cchpQWSr.o: In function `main':
/tmp/a.c:11: undefined reference to `can_only_set_low_8_bits'
collect2: ld returned 1 exit status

Now, this is ugly, and warnings is the only right way, but I still
very much think that one pci_set8() or pci_clear8() call is way
better than code to read+mod+write. The reason is that it's how I
think about these operations; "set bits xy in reg foo."
Read+mod+write is one lower level of abstraction, and not relevant
in the context of setting the bits. Ie. I don't want to write/see
*how* bits get set, I just want to write/see *that* bits get set.

I completely understand that everyone else may not have the same
mental model of these operations, but I hope many enough do..
(Yes, we've discussed before and it seemed not to be the case.)

Carl-Daniel mentioned that there may be a risk for confusion between
pci_set8() and pci_write_config8(), and this was also noted before.
Isn't it really reasonable to expect that people can actually keep
track of how those two functions are different?

I understand that my taste is more terse than most, and if consensus
is that _set8 _clear8 etc. names suck, then I'd be happy with other
fun names too, as long as read+mod+write blocks can be replaced with
single lines of code.

Like the CAR thing I think this really helps write- and readability,
and even thinkability, for our code. The latter helps make further
abstraction easier, which allows more refactoring. Bad goal?


//Peter



From peter at stuge.se  Mon Oct  4 01:19:07 2010
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Oct 2010 01:19:07 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <4CA9084A.9080704@coresystems.de>
References: <20101003184734.GF3256@greenwood>
	<4CA8D701.5010203@georgi-clan.de> <4CA8EFE0.3040704@gmx.net>
	<4CA8F08F.50307@georgi-clan.de> <20101003215947.GG3256@greenwood>
	<4CA9084A.9080704@coresystems.de>
Message-ID: <20101003231907.24422.qmail@stuge.se>

Stefan Reinauer wrote:
> > +config CPU_ADDR_BITS_MASK
> 
> Such stuff belongs into an include file, not into Kconfig.

Good point! I agree completely if it works in practise.


//Peter



From rminnich at gmail.com  Mon Oct  4 01:35:09 2010
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Oct 2010 16:35:09 -0700
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <20101003231014.23261.qmail@stuge.se>
References: <20101003231014.23261.qmail@stuge.se>
Message-ID: <AANLkTimbjgychOeRgvbhTd-uo1BBR4g+kiD-V7Pfu=Up@mail.gmail.com>

On Sun, Oct 3, 2010 at 4:10 PM, Peter Stuge <peter at stuge.se> wrote:
> Rudolf just found a bug in the sb700 code:
>
> u32 dword;
> ..
> dword = pci_read_config8(dev, 0x64);
> dword |= 1 << 10;
> pci_write_config8(dev, 0x64, dword);
>

but why wouldn't the compiler warn about using a dword where a u8 is required?


void pci_write_config8(device_t dev, unsigned where, uint8_t val)

There's no warning of any kind?

ron



From c-d.hailfinger.devel.2006 at gmx.net  Mon Oct  4 01:39:49 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Oct 2010 01:39:49 +0200
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <20101003231014.23261.qmail@stuge.se>
References: <20101003231014.23261.qmail@stuge.se>
Message-ID: <4CA91445.6070503@gmx.net>

On 04.10.2010 01:10, Peter Stuge wrote:
> Rudolf just found a bug in the sb700 code:
>
> u32 dword;
> ..
> dword = pci_read_config8(dev, 0x64);
> dword |= 1 << 10;
> pci_write_config8(dev, 0x64, dword);
>
>
> And I'm ranting now, because a pci_set8() macro/function could have
> found this bug at compile time, and because I don't like these
> constructs. (Compiler warnings would also have indicated a problem.
> They're currently disabled for this code.)
>
> Carl-Daniel is working on a patch, meanwhile consider this:
>
> #define pci_set8(dev, reg, val) do { \
>   if ((a) & ~0xff) can_only_set_low_8_bits(); \
>   

If val is a variable, this will cause linker errors. However, if we use
__builtin_constant_p to apply this check only to constants, it would work.


>   pci_set8_nocheck((dev), (reg), (val)); \
> } while(0)
>
> u8 pci_set8_nocheck(device_t dev, u32 reg, u8 val) {
>   u8 tmp = pci_read_config8(dev, reg);
>   tmp |= val;
>   pci_write_config8(dev, reg, tmp);
>   return tmp;
> }
>
> $ gcc -g -o a a.c
> /tmp/cchpQWSr.o: In function `main':
> /tmp/a.c:11: undefined reference to `can_only_set_low_8_bits'
> collect2: ld returned 1 exit status
>
> Now, this is ugly, and warnings is the only right way, but I still
> very much think that one pci_set8() or pci_clear8() call is way
> better than code to read+mod+write. The reason is that it's how I
> think about these operations; "set bits xy in reg foo."
> Read+mod+write is one lower level of abstraction, and not relevant
> in the context of setting the bits. Ie. I don't want to write/see
> *how* bits get set, I just want to write/see *that* bits get set.
>   

Absolutely. If we assume that the amount of errors per line of code is
constant, reducing the line count by a factor of 3 will reduce the error
rate by a factor of 3 as well. Besides that, improved readability is a
nice side effect.


> I completely understand that everyone else may not have the same
> mental model of these operations, but I hope many enough do..
> (Yes, we've discussed before and it seemed not to be the case.)
>
> Carl-Daniel mentioned that there may be a risk for confusion between
> pci_set8() and pci_write_config8(), and this was also noted before.
> Isn't it really reasonable to expect that people can actually keep
> track of how those two functions are different?
>
> I understand that my taste is more terse than most, and if consensus
> is that _set8 _clear8 etc. names suck, then I'd be happy with other
> fun names too, as long as read+mod+write blocks can be replaced with
> single lines of code.
>   

May I suggest alternative names:
pci_and8(), pci_or8()
pci_and_config8(), pci_or_config8()

I don't really care about the _config part of the name, but I think
"and" and "or" make it really obvious what the functions do. And if we
ever want a function which sets and clears bits at the same time,
pci_and_or_config8() makes the function purpose and the parameter order
very clear.

I will post a patch once a naming decision has been reached.

> Like the CAR thing I think this really helps write- and readability,
> and even thinkability, for our code. The latter helps make further
> abstraction easier, which allows more refactoring. Bad goal?
>   

You can also fit more code into a window, and that might help you get a
better overview besides allowing you to read less code if you only care
about accesses to one register.
A further benefit of such read-modify-write functions is avoidance of
register/device mixups. For example, consider the code snippets below:

val = pci_read_config8(dev, 0x13);
val |= 1;
pci_write_config8(dev, 0x18);

val = pci_read_config8(dev, 0x13);
val |= 1;
pci_write_config8(dev2, 0x13);

We can safely assume that neither the changed register nor the changed
device was intentional if no comment is attached. Avoiding such bugs
(which may be caused by cut-paste-modify actions) is worthwhile
especially if we can't pay anyone to look for such mixups in the code.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Mon Oct  4 01:41:00 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Oct 2010 01:41:00 +0200
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <AANLkTimbjgychOeRgvbhTd-uo1BBR4g+kiD-V7Pfu=Up@mail.gmail.com>
References: <20101003231014.23261.qmail@stuge.se>
	<AANLkTimbjgychOeRgvbhTd-uo1BBR4g+kiD-V7Pfu=Up@mail.gmail.com>
Message-ID: <4CA9148C.4060900@gmx.net>

On 04.10.2010 01:35, ron minnich wrote:
> On Sun, Oct 3, 2010 at 4:10 PM, Peter Stuge <peter at stuge.se> wrote:
>   
>> Rudolf just found a bug in the sb700 code:
>>
>> u32 dword;
>> ..
>> dword = pci_read_config8(dev, 0x64);
>> dword |= 1 << 10;
>> pci_write_config8(dev, 0x64, dword);
>>
>>     
>
> but why wouldn't the compiler warn about using a dword where a u8 is required?
>
>
> void pci_write_config8(device_t dev, unsigned where, uint8_t val)
>
> There's no warning of any kind?
>   

Apparently enabling warnings will break compilation if I understood Uwe
correctly.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From wt at penguintechs.org  Mon Oct  4 02:11:52 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 17:11:52 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <201010031958.17479.phorsyon@gmx.net>
References: <4CA7B5C3.9000002@gmx.net> <4CA7C8EA.2040501@gmx.net>
	<AANLkTikFnUWUcPRNwy8gw7cB12+egjfE8kkM=vy7+qBg@mail.gmail.com>
	<201010031958.17479.phorsyon@gmx.net>
Message-ID: <AANLkTikPoVL8L-mVL4G8eT6g+503GKBL3atikRVWb33v@mail.gmail.com>

On Sun, Oct 3, 2010 at 10:58 AM, phorsyon <phorsyon at gmx.net> wrote:
> I consider myself as enthusiast and would like to share my thoughts about
> coreboot certification and PR as a person from outside the coreboot project. I
> hope this will help you to see this project from another perspective and
> therefore helpful for your plans and further actions. Let me say I would
> really appreciate it, if vendors would ship their products preloaded with
> coreboot. ;-)

We are not vendors, and AFAIK no hardware OEM vendors ship with
coreboot pre-loaded.

> On Sunday 03 October 2010, Warren Turkal wrote:
*snip*

> At first it would be helpful to define what you would like to achieve by
> introducing a coreboot certificate. Helping developers to find boards, which
> have basic support (as described earlier) for easy further development or
> helping users/customers to find boards which are coreboot compatible?

I believe that is what this process is trying to do.

*snip*

> To make coreboot popular, it needs (a) a feature people want, (b) major
> vendors to deliver it and (c) available documentation for all components to
> make it work with most boards. These requirements are interdependent and must
> be solved as whole. To get c vendors must be convinced to want b and therefore
> coreboot needs a. So what's a? It surely is fast boot up, but depending on
> what your target audience is, it might also be boot non-free OSes and works
> with proprietary drivers. If you want to make vendors want b it's definitly
> required to target the average user.

I do not believe that (c) is strictly required in that you don't need
detailed bios developer guides once the code is available. It would be
useful, but I don't see it as being required.

We also need to be realistic. OEMs are not taking up coreboot in mass
right now. We need to set the certification bar at the point that it
would be useful for the coreboot project. I believe that setting the
certification bar allow a more rapid development of coreboot code
would be much more productive that pie-in-the-sky arguments about what
to do with all the OEMs that want to ship coreboot.

*snip*

> There is the possibility to depent on the vendors and the community. Vendors
> could test if non-free OSes work with coreboot (they test this anyway with
> their own BIOSes) and the community could assure this as well. That would
> require a place (e.g. the wiki) were the status of each board is tracked and
> an easy way to contribute. A Login would be required to keep the data on a
> sane level.

Vendors do not ship coreboot yet. I believe that we only have the
community at this point. Given that fact, we need to do what we can to
get vendors interested. I believe that maturing the coreboot codebase
is probably the most effective way to do that.

>> Ideally, having some OS independent test suite would be the best
>> approach I think, but I don't see that getting developed overnight. :)
>
> That's automation. Automation is the second step. ;-)

Indeed. For the record, I believe that Linux probably has a mature
enough ACPI stack and other systems to be pretty good barometer of
compliance short of having an independent test suite.

*snip*

> If you think of a little certification logo/mark that vendors print on their
> boxes, then it has to be as simple and clear as possible.

Agreed.

*snip description of coreboot minimal certification level*

> What about calling it "Coreboot: Developer's Choice". Also freely available
> documentation would be a nice core requirement for that.

I actually don't like "minimal." However, I also don't like "Coreboot:
Developer's Choice." What would you think about "Coreboot beta test"?

*snip description of coreboot standard certification level*

> This would target the normal user, so I would call it "Coreboot compatible" or
> "Coreboot approved".

"Coreboot compatible" is probably a better choice. I like that better
than "standard."

> This mark should assure that all parts of the board work,
> meaning every feature, expected by the average user, hhis is important to
> please them. So that this mark actually means something to them. If they have
> a good reason to care about it, also the vendors have one, and this would give
> the coreboot project the authority dictate such high standards.
>
> Things normal users care about to work:
> - All build-in components (net, snd, gfx)

I should have explicitly included this in the standard certification level.

> - All ports/expansion slots (exceptions: rs232, parallel, floppy)

Already said this in the standard certification level except that I
didn't make any exceptions. It's sloppy to leave physical and header
ports not working.

> - Everything related to power management as supported by the underlying
> hardware and drivers (All power states, ACPI). Also needed to improve drivers.

For the record, I included this in the "better ACPI support" section
of the standard certification. The OSPM part of ACPI includes all
power states of all parts of the system.

> - Add-on components most importantly Nvidia/ATI cards

I don't believe that we should bias toward some particular class of
add-on card or some vendor of add-on card.

> - The OS of choice (BSD, Linux, Windows)

While I agree with this sentiment, we can't test everything. I think
that we should agree on a standard test OS. That OS needs to be freely
obtainable to make the testing bar very low.

> - fast booting

I think this might be a little too subjective for certification. What
if a server vendor wanted to ship coreboot firmware that does a
longish running operation everytime before booting. Would that never
qualify for a coreboot certification?

> Things normal users don't care about:
> - most legacy stuff like rs232, parallel, floppy

As stated above, I think that leaving ports with physical or header
connections nonfunctional is just sloppy, and it would not reflect
well on the project to allow board in that state to get a standard
certification.

> - pro features like *PXE, AoE, iSCSI (Those could be combined under a logo
> like "Coreboot for Professionals")

I agree about things like PXE, AoE, and iSCSI being more important to
big iron. I'm not sure that we should have another certification level
to support them right out of the gate, however. More certification
levels is more confusing.

> - OSes besides the ones they use

Of course.

>> Tags could be used to identify specific extended support. For
>> instance, a system certified to boot Windows 7 could be "Coreboot
>> minimal+MSWin7" certified or "Coreboot standard+MSWin7" certified or
>> something like that. If anyone wanted to display the certification,
>> they could display it with or without the tags.
>>
>> Possible tags:
>> MSWin{XP,7}
>> ReactOS
>> GPXE
>> AOE
>> ISCSI
>> ...
>
> For OSes, users will expect that the major ones (BSD, Linux, Windows) will
> work flawlessy if labeled "Coreboot compatible". So if you focus on the average
> user, this should be respected. Listing the other features separately is a
> good idea, as normal users mostly won't care about them, but experienced users
> get the chance to check for them. To keep the logo itself simple, the feature
> list should be separated from the logo e.g. printed on the backside of a
> package. Or as mentioned above combined to another logo like "Coreboot for
> Professionals"

Frankly, I don't think that we are aiming for average users at this
time. We are aiming for the developers that can advocate coreboot's
use in OEM hardware or folks who see enough of an advantage to pay for
a port to their hardware. These are very sophisticated users.

*snip*

> Keeping track of detailed information in the wiki is a good thing. If vendors
> decide to deliver coreboot it should be as easy as possible for them.

I am not sure this data is simple enough for wiki. However, I haven't
given this too much thought.

> That's were vendors and community could help out. See above.

We don't have vendors shipping coreboot that I am aware of. From a
look at http://www.coreboot.org/Products, the closest we have is VIA,
and they aren't shipping coreboot on any systems that I know of.

*snip*

> That's why I would go for "Coreboot: Developer's Choice" and "Coreboot
> compatible" (or "Coreboot powered" for actual boards preloaded with coreboot),
> it makes it much clearer in my opinion. If there's one think you don't won't a
> certification mark to do, then it's confusing people more than helping them.

I agree that clarity is of the utmost importance. I also think that
"Coreboot: Developer's Choice

*snip*

>> While I agree with this, I think that a minimally certified piece of
>> hardware should not need working fan logic.
>
> True, developers should be able to deal with it, but for users it's a must
> have feature.

That's why I included that as part of the standard certification.

*snip*

> True, but to respect vendors and how they work (e.g. deadlines etc.), it would
> be clever to keep up a communication channel to announce e.g. "no certification
> from X to Y (due to $REASON)". This allows vendors to plan. The point being
> always try to work with, never against each other. ;-)

I think this is somewhat moot since we don't have vendors at this
point, but, of course, I believe that we should make this work with
vendors when they are ready.

>> If it really becomes a problem that vendors want the certification
>> during a time when Kevin isn't around, that would be a good problem
>> for the project to have. :)
>
> Yes that's somehow true, but to some extend this could also be considered
> mismanagement. To prevent those situations each vendor would have to have (at
> least) one employee to stay in contact with coreboot project, which would have
> to ask for one. Also interproject communication (e.g. between flashrom,
> coreboot and seabios) is vital. I can't tell how this works atm., I assume
> quite good, but what I'm trying to point out is, that vendors (and users) are
> always looking for a complete package to solve their problems. Therefore I
> consider the free boot up infrastructure, meaning flashrom, coreboot and
> seabios, as a whole package. This makes working hand in hand very important.

I don't think it's mismanagement unless we think that Kevin is away
enough to warrant adding others who can take this responsibility. If
that happens, it's a good problem to have, and I am sure we can modify
exactly what our definition of code state is to allow a certification.
If we start off with a more conservative definition and expand it in
the future, I think that'd be okay.

*snip*

> Please keep in mind that I'm neither involved in the coreboot project or any
> related projects nor do I work for a hardware vendor. I simply try to express
> how I see the whole picture with the hope this could be of any help for your
> project.

I definitely appreciate your PoV. I think we'll need a lot of
perspective to do something like this successfully.

Thanks,
wt



From scott at notabs.org  Mon Oct  4 02:14:36 2010
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 3 Oct 2010 19:14:36 -0500
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <20101003225730.GO6119@greenwood>
References: <20101003184734.GF3256@greenwood>
	<4CA8D701.5010203@georgi-clan.de><4CA8EFE0.3040704@gmx.net>
	<4CA8F08F.50307@georgi-clan.de><20101003215947.GG3256@greenwood>
	<4CA90336.5010308@georgi-clan.de> <20101003225730.GO6119@greenwood>
Message-ID: <9ACDC83B715142C3AF5D27E835DCB770@m3a78>

]
]But note that the current form is also a bit dangerous. It hardcodes 40bits
]for K8 and 48bits for Fam10h here unconditionally. I don't know if this
]assumption is always correct for all CPUs. Using the correct per-CPU
]CONFIG_CPU_ADDR_BITS_MASK would definately be safer (if this mechanism
]can work here at all). Are we sure there are no K8 systems that support
]CPUs with bits != 40? Are we sure there are no Fam10h CPUs with
]bits != 48 (and that there never will be in the future)?

Getting this info from cpuid is the way to go (It is reliable on AMD
systems). Hard-coding is next best. It is fixed per family:

0Fh 40
10h 48
11h 40
12h 40
13h (no product)
14h 36
15h 48

Hopefully AMD will start supplying coreboot-ready support code, which
will allow coreboot to run exactly the same reference code as every
other AMD BIOS.

Thanks,
Scott

]Uwe.
]-- 
]http://hermann-uwe.de     | http://sigrok.org
]http://randomprojects.org | http://unmaintained-free-software.org





From wt at penguintechs.org  Mon Oct  4 02:16:52 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 17:16:52 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <20101003192839.GB12660@ideafix.casa.ct>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTik1FboBixuj6ShKA+YfyKh=fdff2cdrnreCsu_u@mail.gmail.com>
	<4CA7C8EA.2040501@gmx.net>
	<AANLkTikFnUWUcPRNwy8gw7cB12+egjfE8kkM=vy7+qBg@mail.gmail.com>
	<20101003192839.GB12660@ideafix.casa.ct>
Message-ID: <AANLkTimMFf0qjFqpm8hgf2vE=xOJT1gxX2p26QEAsjSR@mail.gmail.com>

On Sun, Oct 3, 2010 at 12:28 PM, xdrudis <xdrudis at tinet.cat> wrote:
>> Booting into a certain OS is clearly not the only bar that we should
>> be looking for. It would need to comply with various standards like
>> ACPI, etc.
>
> It might be one of the bars. On the other hand ACPI compliance could
> be certified by the ACPI consortium (there is one, I guess...), maybe .
> Likewise for any other standard.

I think that we should require ACPI compliance as it is an integral
part of modern computing on X86 hardware, and it makes enumeration
significantly more efficient or just plain possible in some cases.

Also, I think that we need to be quite careful about overloading our
users with information. Otherwise, out users will be overwhelmed and
will not understand everything that we try to communicate with them.

Thanks,
wt



From c-d.hailfinger.devel.2006 at gmx.net  Mon Oct  4 03:22:46 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Oct 2010 03:22:46 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTikPoVL8L-mVL4G8eT6g+503GKBL3atikRVWb33v@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net>
	<4CA7C8EA.2040501@gmx.net>	<AANLkTikFnUWUcPRNwy8gw7cB12+egjfE8kkM=vy7+qBg@mail.gmail.com>	<201010031958.17479.phorsyon@gmx.net>
	<AANLkTikPoVL8L-mVL4G8eT6g+503GKBL3atikRVWb33v@mail.gmail.com>
Message-ID: <4CA92C66.7080701@gmx.net>

On 04.10.2010 02:11, Warren Turkal wrote:
> On Sun, Oct 3, 2010 at 10:58 AM, phorsyon <phorsyon at gmx.net> wrote:
>   
>> I consider myself as enthusiast and would like to share my thoughts about
>> coreboot certification and PR as a person from outside the coreboot project. I
>> hope this will help you to see this project from another perspective and
>> therefore helpful for your plans and further actions. Let me say I would
>> really appreciate it, if vendors would ship their products preloaded with
>> coreboot. ;-)
>>     
>
> We are not vendors, and AFAIK no hardware OEM vendors ship with
> coreboot pre-loaded.
>   

I think a few vendors ship some systems with coreboot if you ask nicely,
but they are either in the server or embedded space, not general
consumer space.


>> To make coreboot popular, it needs (a) a feature people want, (b) major
>> vendors to deliver it and (c) available documentation for all components to
>> make it work with most boards. These requirements are interdependent and must
>> be solved as whole. To get c vendors must be convinced to want b and therefore
>> coreboot needs a. So what's a? It surely is fast boot up, but depending on
>> what your target audience is, it might also be boot non-free OSes and works
>> with proprietary drivers. If you want to make vendors want b it's definitly
>> required to target the average user.
>>     
>
> I do not believe that (c) is strictly required in that you don't need
> detailed bios developer guides once the code is available. It would be
> useful, but I don't see it as being required.
>
> We also need to be realistic. OEMs are not taking up coreboot in mass
> right now. We need to set the certification bar at the point that it
> would be useful for the coreboot project. I believe that setting the
> certification bar allow a more rapid development of coreboot code
> would be much more productive that pie-in-the-sky arguments about what
> to do with all the OEMs that want to ship coreboot.
>   

OEMs want fire-and-forget solutions without functional regressions.
coreboot can serve as fire-and-forget solution, but if we certify
consumer mainboards which can't run Windows, the certificate will be
essentially worthless.

Remember the complaints about "Designed for Windows Vista" and the
machines which were too slow to be useful? People still remember that
marketing disaster years after it happened. If we ever certify some
hardware without caring about Windows, we should make that explicit, and
call it a feature. "Coreboot certified board for the anti-closed-source
movement, will refuse to run Windows". The variant which can run Windows
would be "Coreboot certified board". Except for niche vendors, nobody
will care about the anti-closed-source certification, making it moot.


> Vendors do not ship coreboot yet. 

AFAIK Artec, Tyan, Technexion, MSI and some other vendors ship coreboot
for specific systems on request. Not sure about the current state, but
AFAIK they did that in the past.


> I believe that we only have the
> community at this point. Given that fact, we need to do what we can to
> get vendors interested. I believe that maturing the coreboot codebase
> is probably the most effective way to do that.
>   

Booting Windows 7 on recent consumer boards is probably the best way to
show vendors that coreboot is a viable BIOS replacement. This needs
porting work, and of course it needs testing.


> For the record, I believe that Linux probably has a mature
> enough ACPI stack and other systems to be pretty good barometer of
> compliance short of having an independent test suite.
>   

Ummm... Linux will tolerate absolutely crappy ACPI code, and not even
complain loudly if it has to fix stuff. Given the current market share
of Linux, there is no money in verifying ACPI code under Linux for any
consumer mainboard.


>> What about calling it "Coreboot: Developer's Choice". Also freely available
>> documentation would be a nice core requirement for that.
>>     
>
> I actually don't like "minimal." However, I also don't like "Coreboot:
> Developer's Choice." What would you think about "Coreboot beta test"?
>   

For me, "Developer's choice" implies that the board already works
perfectly fine, and has all the hardware features which make it easy to
test new coreboot versions.
I believe in honest advertising, and if the machine barely works, we
should not certify it, but we could list it as "fun project if you want
to finish a port".


>> - Add-on components most importantly Nvidia/ATI cards
>>     
>
> I don't believe that we should bias toward some particular class of
> add-on card or some vendor of add-on card.
>   

Nobody is going to test with Tseng Labs graphics cards because they are
no longer on sale (actually, they haven't been on sale anytime in the
last 12 years).
Nobody is going to test with Intel graphics cards either unless you can
actually show that such cards are on sale for mere mortals.
So basically you have ATI(AMD) and Nvidia for external graphics, and
maybe Matrox in niche markets.
Intel and S3 and others are only available as onboard options.


>> - The OS of choice (BSD, Linux, Windows)
>>     
>
> While I agree with this sentiment, we can't test everything. I think
> that we should agree on a standard test OS. That OS needs to be freely
> obtainable to make the testing bar very low.
>   

So FreeDOS would be OK for you? Small, free, and it will probably run
just fine even if major parts of the board are malfunctioning because
the port is unfinished.


> Frankly, I don't think that we are aiming for average users at this
> time. We are aiming for the developers that can advocate coreboot's
> use in OEM hardware or folks who see enough of an advantage to pay for
> a port to their hardware. These are very sophisticated users.
>   

But OEMs won't care unless we can make average users happy. If you want
an OEM to ship coreboot by default, you better make sure the OEM won't
fall into the Linux netbook trap where people returned lots of machines
because they expected to be able to run Windows applications. OEMs are
also extremely cost-conscious, and if they can save a few cents per
board without risk, they will do it. The key words are "save money" and
"no risk". Given the per-mainboard licensing cost for BIOS, coreboot can
serve as an alternative if there is no risk involved.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Mon Oct  4 03:49:30 2010
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Oct 2010 18:49:30 -0700
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <4CA9148C.4060900@gmx.net>
References: <20101003231014.23261.qmail@stuge.se>
	<AANLkTimbjgychOeRgvbhTd-uo1BBR4g+kiD-V7Pfu=Up@mail.gmail.com>
	<4CA9148C.4060900@gmx.net>
Message-ID: <AANLkTi=eJ6YyP7wzP0bHpWW=63OhDa4OQGrX7C89ezzX@mail.gmail.com>

On Sun, Oct 3, 2010 at 4:41 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Apparently enabling warnings will break compilation if I understood Uwe
> correctly.

so we're going to build this complex C pre-processor macro foo,
further extending our dependence on the way the compilers work, when
the real issue is that we've disabled warnings?

And we'll fix one case, but we won't fix all the other potential
errors involving incorrect types?

After all, someone can still assign a u32 to a u8 and still get things lost.

I think we need to fix the real problem, the disabled warnings.

ron



From wt at penguintechs.org  Mon Oct  4 03:50:05 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 18:50:05 -0700
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <AANLkTikwws193rL5Dv3+xeWwh3v1_m_NjLWRrMDzcqZB@mail.gmail.com>
References: <20101001212759.GV3256@greenwood>
	<AANLkTikwws193rL5Dv3+xeWwh3v1_m_NjLWRrMDzcqZB@mail.gmail.com>
Message-ID: <AANLkTimb-RNS_3mS+TV7GMq1iR0TRtDuWuGBTL6zBQct@mail.gmail.com>

Maybe instead of making it look like a function like:
enable_cache()
it should just look like a normal macro like:
ENABLE_CACHE_ASM

Maybe that would make it more obvious that it's not a function.

Alternatively, we could say that all "function" calls in pre-CAR state
destroy all registers as a kind of pseudo-calling convention.

wt

On Sun, Oct 3, 2010 at 10:17 AM, ron minnich <rminnich at gmail.com> wrote:
> OK, I've thought about why this patch makes me so uncomfortable. See
> if I make sense.
>
>
> The patch takes sequences like this:
> - ? ? ? /* Enable cache. */
> - ? ? ? movl ? ?%cr0, %eax
> - ? ? ? andl ? ?$(~((1 << 30) | (1 << 29))), %eax
> - ? ? ? movl ? ?%eax, %cr0
>
> and replaces them with this:
>
> + ? ? ? enable_cache()
>
> Seems ok, right? Let's think about some rules in C:
>
> int eax, ebx, ecx, edx;
> eax = 1;
> ebx = 2;
> enable_cache();
> ecx = eax;
>
> Now, as we all know, in C, that function call won't affect those
> variables. ecx will have a value of 2. We have a stack and there are
> rules in C. So the variables are safe, and we're all used to thinking
> that way. We think that way, in fact, by habit, even when looking at
> assembly code. The syntax of the proposed patch makes it look very
> much like a side-effect-free function call. That's one worry I have
> all ready: it looks like a function, but it's not a function.
>
> In other words, in C, local variables don't affect what goes on in the
> function, and the function does not affect what goes on in local
> variables. You don't have to go read the code for the function; that's
> the whole point of a function. Functions provide a side-effect-free
> way to get some operation done.
>
> How different this is from assembly macros!
>
> movl $2, %eax
> enable_cache()
> movl %eax, %ecx
>
> If enable_cache is the function call it seems to be, %ecx will have 2.
> As most of us know, it won't of course; it has some number with lots
> of bits set, but it sure does not have 2.
>
> Sure, we all know this; but what about a newcomer in 5 years; will
> they know this?
>
> So, what's the value of eax after the "call"? How can you know? Well,
> you have to go read that code. You have to find the include file. You
> have to have intimate understanding of the function, to make sure it
> does not affect your "local variables" -- your registers. That's not a
> function. The usage makes it look like a function, but it's not a
> function. I think this practice is going to cause trouble.
>
> So what are your options here? For each of the "functions", you can
> track down the file, read the code, and make sure you understand it.
> This is in my view *worse* than just having assembly code inline; you
> have to hop around the tree but, more importantly, you have to
> understand how the target is built, to make sure you're understanding
> what's going on.
>
> But wait! it gets worse! Just because you understand the file now
> doesn't mean it won't change. You have to future-proof your code,
> because, 5 or 10 years from now (some of the code is that old!), for
> some new machine, somebody might make a change to enable_cache(), and
> use one extra register, and break one target, and it might not be
> noticed for a year. Yes, this sort of thing happens; it has happened
> to me several times on different projects.
>
> But wait! it gets worse! What if you are the person who wrote the
> enable_cache() "function"? Then, if you ever need to change it, you
> have to find each and every file that uses that function, and make
> quite sure you understand the assembly code that surrounds the
> "function", and make sure you won't break it. Now that's a lot of
> work!
>
> What if the function needs an extra parameter in a register due to
> some new architecture? If that ever happens, and you need to add a new
> register to the "function", you're going to have to once again find
> all uses of it and fix all that code. Is it possible that in that
> process errors might creep in? It's actually a certainty. Note that
> we're build-testing, not boot-testing, a lot of these changes; that's
> what broke one of my VIA boards -- permanently.
>
> There is one way to future-proof the calls to these "functions". The
> only safe assumption you can make after that "call" to disable_cache
> is that all registers are dead: nothing safely carries across the
> "call". Then I think you have less of a chance of a problem. That way,
> one can make lots of changes to the functions and not have to track
> down all uses to see if any are broken by it. Do you really want to do
> this work? And are you sure that 5 years from now, new code authors
> will be aware of that rule?
>
> Just my $.015
>
> ron
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From peter at stuge.se  Mon Oct  4 04:15:36 2010
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Oct 2010 04:15:36 +0200
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <AANLkTi=eJ6YyP7wzP0bHpWW=63OhDa4OQGrX7C89ezzX@mail.gmail.com>
References: <20101003231014.23261.qmail@stuge.se>
	<AANLkTimbjgychOeRgvbhTd-uo1BBR4g+kiD-V7Pfu=Up@mail.gmail.com>
	<4CA9148C.4060900@gmx.net>
	<AANLkTi=eJ6YyP7wzP0bHpWW=63OhDa4OQGrX7C89ezzX@mail.gmail.com>
Message-ID: <20101004021536.10957.qmail@stuge.se>

ron minnich wrote:
> > Apparently enabling warnings will break compilation if I understood Uwe
> > correctly.
> 
> so we're going to build this complex C pre-processor macro foo,
> further extending our dependence on the way the compilers work, when
> the real issue is that we've disabled warnings?

That's not what I suggested. I certainly don't think that's right. I
don't think Carl-Daniel does either. It was just an explanation for
why the compiler didn't complain.


> I think we need to fix the real problem, the disabled warnings.

I agree. I don't think this thread is so much about that, but it
would also be easy to have a check for this error (without special
macro foo) in the functions that I'd like to add.


//Peter



From wt at penguintechs.org  Mon Oct  4 06:38:32 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 21:38:32 -0700
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <4CA91445.6070503@gmx.net>
References: <20101003231014.23261.qmail@stuge.se> <4CA91445.6070503@gmx.net>
Message-ID: <AANLkTimOsK9zPhaqfC0ac2Gok4nBH+nBm62XonitdOw6@mail.gmail.com>

On Sun, Oct 3, 2010 at 4:39 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> May I suggest alternative names:
> pci_and8(), pci_or8()
> pci_and_config8(), pci_or_config8()

I am sure this it bike shedding, but here are a few other options for
the name scheme:
* pci_bit_and8()
* pci_bitwise_and8()
* pci_bit_andb()
* pci_bitwise_andb()

I am waffling between preferring pci_bitwise_andb() or
pci_bitwise_and8() for readability.

Thanks,
wt



From peter at stuge.se  Mon Oct  4 07:03:41 2010
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Oct 2010 07:03:41 +0200
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <AANLkTimOsK9zPhaqfC0ac2Gok4nBH+nBm62XonitdOw6@mail.gmail.com>
References: <20101003231014.23261.qmail@stuge.se> <4CA91445.6070503@gmx.net>
	<AANLkTimOsK9zPhaqfC0ac2Gok4nBH+nBm62XonitdOw6@mail.gmail.com>
Message-ID: <20101004050341.29815.qmail@stuge.se>

Warren Turkal wrote:
> I am sure this it bike shedding, but here are a few other options for
> the name scheme:
> * pci_bit_and8()
> * pci_bitwise_and8()
> * pci_bit_andb()
> * pci_bitwise_andb()

Don't like _set and _clear at all?


> I am waffling between preferring pci_bitwise_andb() or
> pci_bitwise_and8() for readability.

I think it's a good idea to be consistent with the other functions,
which are all using the numeric size.


//Peter



From wt at penguintechs.org  Mon Oct  4 07:33:20 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 22:33:20 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <4CA92C66.7080701@gmx.net>
References: <4CA7B5C3.9000002@gmx.net> <4CA7C8EA.2040501@gmx.net>
	<AANLkTikFnUWUcPRNwy8gw7cB12+egjfE8kkM=vy7+qBg@mail.gmail.com>
	<201010031958.17479.phorsyon@gmx.net>
	<AANLkTikPoVL8L-mVL4G8eT6g+503GKBL3atikRVWb33v@mail.gmail.com>
	<4CA92C66.7080701@gmx.net>
Message-ID: <AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>

On Sun, Oct 3, 2010 at 6:22 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 04.10.2010 02:11, Warren Turkal wrote:
>> On Sun, Oct 3, 2010 at 10:58 AM, phorsyon <phorsyon at gmx.net> wrote:
>>
>>> I consider myself as enthusiast and would like to share my thoughts about
>>> coreboot certification and PR as a person from outside the coreboot project. I
>>> hope this will help you to see this project from another perspective and
>>> therefore helpful for your plans and further actions. Let me say I would
>>> really appreciate it, if vendors would ship their products preloaded with
>>> coreboot. ;-)
>>>
>>
>> We are not vendors, and AFAIK no hardware OEM vendors ship with
>> coreboot pre-loaded.
>>
>
> I think a few vendors ship some systems with coreboot if you ask nicely,
> but they are either in the server or embedded space, not general
> consumer space.

This is interesting news for me. I think that's really great.

>>> To make coreboot popular, it needs (a) a feature people want, (b) major
>>> vendors to deliver it and (c) available documentation for all components to
>>> make it work with most boards. These requirements are interdependent and must
>>> be solved as whole. To get c vendors must be convinced to want b and therefore
>>> coreboot needs a. So what's a? It surely is fast boot up, but depending on
>>> what your target audience is, it might also be boot non-free OSes and works
>>> with proprietary drivers. If you want to make vendors want b it's definitly
>>> required to target the average user.
>>>
>>
>> I do not believe that (c) is strictly required in that you don't need
>> detailed bios developer guides once the code is available. It would be
>> useful, but I don't see it as being required.
>>
>> We also need to be realistic. OEMs are not taking up coreboot in mass
>> right now. We need to set the certification bar at the point that it
>> would be useful for the coreboot project. I believe that setting the
>> certification bar allow a more rapid development of coreboot code
>> would be much more productive that pie-in-the-sky arguments about what
>> to do with all the OEMs that want to ship coreboot.
>>
>
> OEMs want fire-and-forget solutions without functional regressions.
> coreboot can serve as fire-and-forget solution, but if we certify
> consumer mainboards which can't run Windows, the certificate will be
> essentially worthless.

I agree that OEMs would want that. However, I don't think that all the
coreboot developers could commit to that level of testing right now.
AFAICT, testing of any kind is very difficult to get done if I don't
own the affected hardware.

> Remember the complaints about "Designed for Windows Vista" and the
> machines which were too slow to be useful? People still remember that
> marketing disaster years after it happened. If we ever certify some
> hardware without caring about Windows, we should make that explicit, and
> call it a feature. "Coreboot certified board for the anti-closed-source
> movement, will refuse to run Windows".

First of all, I think you are attacking a straw man. My point has
nothing to do with being anti-closed-source. My point is that I don't
own a license for Windows and wouldn't be able to do the testing
necessary if that's a gate for certification. I have no problem with a
machine running Windows (or any other OS), but I don't think that
should be needed for for minimum compliance.

> The variant which can run Windows
> would be "Coreboot certified board". Except for niche vendors, nobody
> will care about the anti-closed-source certification, making it moot.

I just think that bar is too high to leverage the community of folks
that would like to see and even help coreboot progress.

>> Vendors do not ship coreboot yet.
>
> AFAIK Artec, Tyan, Technexion, MSI and some other vendors ship coreboot
> for specific systems on request. Not sure about the current state, but
> AFAIK they did that in the past.

With all due respect, I don't think this information has any bearing
on my position.

>> I believe that we only have the
>> community at this point. Given that fact, we need to do what we can to
>> get vendors interested. I believe that maturing the coreboot codebase
>> is probably the most effective way to do that.
>>
>
> Booting Windows 7 on recent consumer boards is probably the best way to
> show vendors that coreboot is a viable BIOS replacement. This needs
> porting work, and of course it needs testing.

How do I show booting Windows 7 for a board I am working on? If I
can't because I don't have a license for Windows, should I not be able
to get the coreboot certification?

>> For the record, I believe that Linux probably has a mature
>> enough ACPI stack and other systems to be pretty good barometer of
>> compliance short of having an independent test suite.
>>
>
> Ummm... Linux will tolerate absolutely crappy ACPI code, and not even
> complain loudly if it has to fix stuff. Given the current market share
> of Linux, there is no money in verifying ACPI code under Linux for any
> consumer mainboard.

Fair enough, but it's certainly got to be better than not running any
OS on the machine as it does demonstrate some level of functionality.

>>> What about calling it "Coreboot: Developer's Choice". Also freely available
>>> documentation would be a nice core requirement for that.
>>>
>>
>> I actually don't like "minimal." However, I also don't like "Coreboot:
>> Developer's Choice." What would you think about "Coreboot beta test"?
>>
>
> For me, "Developer's choice" implies that the board already works
> perfectly fine, and has all the hardware features which make it easy to
> test new coreboot versions.
> I believe in honest advertising, and if the machine barely works, we
> should not certify it, but we could list it as "fun project if you want
> to finish a port".

I agree that "Developer's choice" implies too much functionality. :)
However, I still think we need a way to invite more people and orgs
into the project. I think that we need some way to say that certain
boards are a good place to start for those looking to contribute.
Ideally, one day we won't even need this level of certification as
everything will just ship with coreboot. :)

>>> - Add-on components most importantly Nvidia/ATI cards
>>>
>>
>> I don't believe that we should bias toward some particular class of
>> add-on card or some vendor of add-on card.
>>
>
> Nobody is going to test with Tseng Labs graphics cards because they are
> no longer on sale (actually, they haven't been on sale anytime in the
> last 12 years).
> Nobody is going to test with Intel graphics cards either unless you can
> actually show that such cards are on sale for mere mortals.
> So basically you have ATI(AMD) and Nvidia for external graphics, and
> maybe Matrox in niche markets.
> Intel and S3 and others are only available as onboard options.

I have an ATI PCIe card and would likely use that to test, but
requiring both ATI and Nvidia out of me is a little much.

>>> - The OS of choice (BSD, Linux, Windows)
>>
>> While I agree with this sentiment, we can't test everything. I think
>> that we should agree on a standard test OS. That OS needs to be freely
>> obtainable to make the testing bar very low.
>>
>
> So FreeDOS would be OK for you? Small, free, and it will probably run
> just fine even if major parts of the board are malfunctioning because
> the port is unfinished.

To be clear, I think you are attacking another straw man. I
specifically suggested Debian of some form. I may not have been clear
with my reasons, so here they are: it does have a chance of having
drivers for the majority of the hardware, it uses more sophisticated
hardware initialization techniques, it's a well supported dev
environment for coreboot, and it's easy to find and download a legal
copy for free.

If there is software that can verify ACPI and other needed
functionality from FreeDOS, maybe it would make a good platform. I
honestly have no idea.

>> Frankly, I don't think that we are aiming for average users at this
>> time. We are aiming for the developers that can advocate coreboot's
>> use in OEM hardware or folks who see enough of an advantage to pay for
>> a port to their hardware. These are very sophisticated users.
>>
>
> But OEMs won't care unless we can make average users happy. If you want
> an OEM to ship coreboot by default, you better make sure the OEM won't
> fall into the Linux netbook trap where people returned lots of machines
> because they expected to be able to run Windows applications.

I am not denying that there is a demand for Windows. I am simply
saying that I would like to be able to participate in the
certification of board, and I don't have a copy of Windows to test
with.

> OEMs are
> also extremely cost-conscious, and if they can save a few cents per
> board without risk, they will do it. The key words are "save money" and
> "no risk". Given the per-mainboard licensing cost for BIOS, coreboot can
> serve as an alternative if there is no risk involved.

Makes sense. However, I think that OEMs that need Windows can be sure
to certify their systems for Windows.

Also, I don't think that Windows support should be part of the base
certification as it alienates a number of people who are really
interested in seeing and helping coreboot succeed.

Also, I think that we should start pretty minimally as definitions can
be changed as time goes on, but I don't want us to bite off more than
we can chew and just abandon the effort as a result.

Thanks,
wt



From wt at penguintechs.org  Mon Oct  4 07:40:11 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 22:40:11 -0700
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <20101004050341.29815.qmail@stuge.se>
References: <20101003231014.23261.qmail@stuge.se> <4CA91445.6070503@gmx.net>
	<AANLkTimOsK9zPhaqfC0ac2Gok4nBH+nBm62XonitdOw6@mail.gmail.com>
	<20101004050341.29815.qmail@stuge.se>
Message-ID: <AANLkTinHgLYTrYtX8Udi8owQOkspsBos9dKN8NJrG5Lz@mail.gmail.com>

On Sun, Oct 3, 2010 at 10:03 PM, Peter Stuge <peter at stuge.se> wrote:
> Warren Turkal wrote:
>> I am sure this it bike shedding, but here are a few other options for
>> the name scheme:
>> * pci_bit_and8()
>> * pci_bitwise_and8()
>> * pci_bit_andb()
>> * pci_bitwise_andb()
>
> Don't like _set and _clear at all?

What about _setbits_config8 and _clearbits_config8? That might be more readable.

>> I am waffling between preferring pci_bitwise_andb() or
>> pci_bitwise_and8() for readability.
>
> I think it's a good idea to be consistent with the other functions,
> which are all using the numeric size.

Good point.

Current list as I see it:
* pci_{set,clear}bits_config8()
* pci_{set,clear}8()
* pci_bit_{or,and}8()
* pci_bitwise_{or,and}8()

Did I miss any?

I currently prefer pci_{set,clear}bits_config8().

Thanks,
wt



From wt at penguintechs.org  Mon Oct  4 07:58:30 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Sun, 3 Oct 2010 22:58:30 -0700
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <9ACDC83B715142C3AF5D27E835DCB770@m3a78>
References: <20101003184734.GF3256@greenwood> <4CA8D701.5010203@georgi-clan.de>
	<4CA8EFE0.3040704@gmx.net> <4CA8F08F.50307@georgi-clan.de>
	<20101003215947.GG3256@greenwood> <4CA90336.5010308@georgi-clan.de>
	<20101003225730.GO6119@greenwood>
	<9ACDC83B715142C3AF5D27E835DCB770@m3a78>
Message-ID: <AANLkTimhdnKU3Y=KScNB9CjPccygZqEUgN61VbTw-6qx@mail.gmail.com>

Are there processors where that CPU_ADDR_BITS_MASK cannot be reliably
retrieved from CPUID? What is the harm in using a value that is too
small for the CAR setup? In other words could we use the least common
value for any CPU instead of having a different setting on each
different chip?

Thanks,
wt

On Sun, Oct 3, 2010 at 5:14 PM, Scott Duplichan <scott at notabs.org> wrote:
> ]
> ]But note that the current form is also a bit dangerous. It hardcodes 40bits
> ]for K8 and 48bits for Fam10h here unconditionally. I don't know if this
> ]assumption is always correct for all CPUs. Using the correct per-CPU
> ]CONFIG_CPU_ADDR_BITS_MASK would definately be safer (if this mechanism
> ]can work here at all). Are we sure there are no K8 systems that support
> ]CPUs with bits != 40? Are we sure there are no Fam10h CPUs with
> ]bits != 48 (and that there never will be in the future)?
>
> Getting this info from cpuid is the way to go (It is reliable on AMD
> systems). Hard-coding is next best. It is fixed per family:
>
> 0Fh 40
> 10h 48
> 11h 40
> 12h 40
> 13h (no product)
> 14h 36
> 15h 48
>
> Hopefully AMD will start supplying coreboot-ready support code, which
> will allow coreboot to run exactly the same reference code as every
> other AMD BIOS.
>
> Thanks,
> Scott
>
> ]Uwe.
> ]--
> ]http://hermann-uwe.de ? ? | http://sigrok.org
> ]http://randomprojects.org | http://unmaintained-free-software.org
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From patrick at georgi-clan.de  Mon Oct  4 08:49:17 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 04 Oct 2010 08:49:17 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net>
	<4CA7C8EA.2040501@gmx.net>	<AANLkTikFnUWUcPRNwy8gw7cB12+egjfE8kkM=vy7+qBg@mail.gmail.com>	<201010031958.17479.phorsyon@gmx.net>	<AANLkTikPoVL8L-mVL4G8eT6g+503GKBL3atikRVWb33v@mail.gmail.com>	<4CA92C66.7080701@gmx.net>
	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
Message-ID: <4CA978ED.8000002@georgi-clan.de>

Am 04.10.2010 07:33, schrieb Warren Turkal:
> How do I show booting Windows 7 for a board I am working on? If I
> can't because I don't have a license for Windows, should I not be able
> to get the coreboot certification?
That's the difference between a certification that's useful for vendors
and one that's useful for computing enthusiasts.

Whoever produces and sells boards will have some Windows 7 license (and
probably the dev builds to improve testing, as well as the Microsoft
test kits) lying around.

That means, certification would be for different purposes.. a "coreboot
+ Linux" certificate would state that the board is actually useful
beyond freedos (eg. networking works, HPET is around, ACPI is at least
somewhat useful, even if Linux's ACPI interpreter is more forgiving than
perl)

A "coreboot + Windows" certificate could build onto that, stating that
Windows operation was tested, too. Stacking them this way would ensure
that Windows support doesn't break Linux (or any other free OS).

But vendors will (except for some specialty shops or special customer
requests) require the latter - with no regard for the former, except
maybe to assess how much work they'd have to put in/sponsor to make a
coreboot port Windows compatible.

As a side note on "Windows compatible", I'm not 100% sure on this, but I
think the "Designed for Windows" set of certificates by Microsoft handle
firmware behaviour, too.


Patrick



From uwe at hermann-uwe.de  Mon Oct  4 09:39:55 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 4 Oct 2010 09:39:55 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <AANLkTimhdnKU3Y=KScNB9CjPccygZqEUgN61VbTw-6qx@mail.gmail.com>
References: <20101003184734.GF3256@greenwood> <4CA8D701.5010203@georgi-clan.de>
	<4CA8EFE0.3040704@gmx.net> <4CA8F08F.50307@georgi-clan.de>
	<20101003215947.GG3256@greenwood> <4CA90336.5010308@georgi-clan.de>
	<20101003225730.GO6119@greenwood>
	<9ACDC83B715142C3AF5D27E835DCB770@m3a78>
	<AANLkTimhdnKU3Y=KScNB9CjPccygZqEUgN61VbTw-6qx@mail.gmail.com>
Message-ID: <20101004073955.GP6119@greenwood>

On Sun, Oct 03, 2010 at 10:58:30PM -0700, Warren Turkal wrote:
> Are there processors where that CPU_ADDR_BITS_MASK cannot be reliably
> retrieved from CPUID? What is the harm in using a value that is too

Looks like there are, at least a code comment which was in there
suggests that:

/*
 * This routine needs to know how many address bits a given processor supports
 * (CONFIG_CPU_ADDR_BITS). CPUs get grumpy when you set too many bits in
 * their MTRR registers. We could generically use CPUID here and find out how
 * many are physically supported, but some CPUs are buggy, and report more
 * bits than they actually support.
 */

But I agree with you, I'd personally have no objections to using CPUID
per default, and allowing a "black-list" via kconfig variables which
use a value from the CPU's Kconfig if this CPU is known-bad (i.e.
reports an incorrect bit number).

Something like

  select CPU_REPORTS_INVALID_ADDR_BITS_NUMBER


> small for the CAR setup? In other words could we use the least common
> value for any CPU instead of having a different setting on each
> different chip?

What do you mean with "chip" here? The value is CPU-specific (not
socket-specific or board-specific). It's also implemented using a
per-CPU mechanism via kconfig in my patch.

 
Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Mon Oct  4 16:00:02 2010
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 04 Oct 2010 16:00:02 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1P2laE-0004vM-T9@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20101004/232c5681/attachment.html>

From scott at notabs.org  Mon Oct  4 16:02:01 2010
From: scott at notabs.org (Scott Duplichan)
Date: Mon, 4 Oct 2010 09:02:01 -0500
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <AANLkTimhdnKU3Y=KScNB9CjPccygZqEUgN61VbTw-6qx@mail.gmail.com>
References: <20101003184734.GF3256@greenwood>
	<4CA8D701.5010203@georgi-clan.de><4CA8EFE0.3040704@gmx.net>
	<4CA8F08F.50307@georgi-clan.de><20101003215947.GG3256@greenwood>
	<4CA90336.5010308@georgi-clan.de><20101003225730.GO6119@greenwood><9ACDC83B715142C3AF5D27E835DCB770@m3a78>
	<AANLkTimhdnKU3Y=KScNB9CjPccygZqEUgN61VbTw-6qx@mail.gmail.com>
Message-ID: <EF06E43393D443AF82FC3CA7999BE56D@m3a78>


]Are there processors where that CPU_ADDR_BITS_MASK cannot be reliably
]retrieved from CPUID? What is the harm in using a value that is too
]small for the CAR setup? In other words could we use the least common
]value for any CPU instead of having a different setting on each
]different chip?

My recent experience is with AMD processors. There are no known problems
with the AMD cpuid reporting of max physical address size for families
0Fh and beyond.

In my experience, using too few bits is workable. I once hard-coded
a 36-bit mask for a BIOS that boots both family 12h and family 14h.
Certainly coreboot should use the correct mask though. 

Thanks,
Scott

]Thanks,
]wt





From patrick at georgi-clan.de  Mon Oct  4 17:48:03 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 04 Oct 2010 17:48:03 +0200
Subject: [coreboot] [PATCH]First attempt at eliminating #include *.c
Message-ID: <4CA9F733.9050908@georgi-clan.de>

Hi,

attached patch removes several "#include *.c" from romstage.c in i945
based boards and moves those files to romstage-srcs instead (ie.
separate compilation units).

There's one global change, the removal of ramtest.c from CAR romstage.cs

It's abuild tested and boot tested on kontron/986lcd-m. Probably should
be tested (so that ramtest.c stuff is a separate patch), but the global
changes were actually the last change I made.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From phorsyon at gmx.net  Mon Oct  4 19:50:22 2010
From: phorsyon at gmx.net (phorsyon)
Date: Mon, 4 Oct 2010 19:50:22 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <4CA978ED.8000002@georgi-clan.de>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
	<4CA978ED.8000002@georgi-clan.de>
Message-ID: <201010041950.25088.phorsyon@gmx.net>

On 04.10.2010 02:11, Warren Turkal wrote:
*snip*

> > What about calling it "Coreboot: Developer's Choice". Also freely
> > available documentation would be a nice core requirement for that.
> 
> I actually don't like "minimal." However, I also don't like "Coreboot:
> Developer's Choice." What would you think about "Coreboot beta test"?

For me "beta test" sounds like almost done, but needs testing. What about 
simply calling it "Coreboot: Under development". I can't imagine it to be 
printed on a box though, but as you said your're focussing on the community, 
at least for now, a list in the wiki showing all certified products will be 
more appropriate.

*snip*

> > This mark should assure that all parts of the board work,
> > meaning every feature, expected by the average user, hhis is important to
> > please them. So that this mark actually means something to them. If they
> > have a good reason to care about it, also the vendors have one, and this
> > would give the coreboot project the authority dictate such high
> > standards.
> > 
> > Things normal users care about to work:
> > - All build-in components (net, snd, gfx)
> 
> I should have explicitly included this in the standard certification level.
> 
> > - All ports/expansion slots (exceptions: rs232, parallel, floppy)
> 
> Already said this in the standard certification level except that I
> didn't make any exceptions. It's sloppy to leave physical and header
> ports not working.

This probably was a little unclear. I meant to list what users expectations 
are, but not what criteria for certification should be. From a technical 
perspective I totally agree that every connector/header should be funtional.

> > - Everything related to power management as supported by the underlying
> > hardware and drivers (All power states, ACPI). Also needed to improve
> > drivers.
> 
> For the record, I included this in the "better ACPI support" section
> of the standard certification. The OSPM part of ACPI includes all
> power states of all parts of the system.
> 
> > - Add-on components most importantly Nvidia/ATI cards
> 
> I don't believe that we should bias toward some particular class of
> add-on card or some vendor of add-on card.

As Carl-Daniel stated, there are practically just ATI/AMD and Nvidia. And I 
also agree that it can't be expected every developer has both to test with. 
But you are not the only dev, it's possible to delegate test to each other and 
probalby to kreep track of that in the wiki. There is a testsystem:
http://www.coreboot.org/Distributed_and_Automated_Testsystem
I have not digged into it, but it's probably possible to extend it for semi-
automatic testing. So that if dev A has written code which also needs testing 
for hardware only dev B has access to, dev A can call for dev B to test it. To 
scale well such a system would require information about who has which 
hardware to run tests on. This would allow for automatic notification.

> > - The OS of choice (BSD, Linux, Windows)
> 
> While I agree with this sentiment, we can't test everything. I think
> that we should agree on a standard test OS. That OS needs to be freely
> obtainable to make the testing bar very low.

If that's for the development certification, I totally agree. I always had the 
consumer in mind.

> > - fast booting
> 
> I think this might be a little too subjective for certification. What
> if a server vendor wanted to ship coreboot firmware that does a
> longish running operation everytime before booting. Would that never
> qualify for a coreboot certification?

As mentioned above it's  meant as user expectations not certification criteria. 

> > Things normal users don't care about:
> > - most legacy stuff like rs232, parallel, floppy
> 
> As stated above, I think that leaving ports with physical or header
> connections nonfunctional is just sloppy, and it would not reflect
> well on the project to allow board in that state to get a standard
> certification.

Agreed

> > - pro features like *PXE, AoE, iSCSI (Those could be combined under a
> > logo like "Coreboot for Professionals")
> 
> I agree about things like PXE, AoE, and iSCSI being more important to
> big iron. I'm not sure that we should have another certification level
> to support them right out of the gate, however. More certification
> levels is more confusing.

Probably having these listed as separate features would be best.

*snip*

> > Keeping track of detailed information in the wiki is a good thing. If
> > vendors decide to deliver coreboot it should be as easy as possible for
> > them.
> 
> I am not sure this data is simple enough for wiki. However, I haven't
> given this too much thought.

It defintely would be helpful for new developers and leave a good impression to 
verndors/OEMs. Right now it's not that easy for an outstanding person to tell 
what works and how well (also e.g. has freely available documentations or 
not). So improving infrastructure on this side will pay off, I guess.

I think of a combination of the automatic testing + semi-automatic testing as 
described above and a status site to keep track of this details. For example 
board $FOO has this components where this where tested an that not. Also 
additional test like with works Nvidia or ATI GPU could be introduced. This 
system could deliver all the status information needed, so anyone could tell 
where the project stands. The lazy evaluation would allow to make good use of 
the rare hardware around the developers. It's also an invitation for testers 
only, as they would always know what still needs testing and do the test if 
they find the time. This eliminates the need to setup the full automatic 
testsystem, which apparently aims for vendors only.  So you may want to think 
that through. ;-)

*snip*

On Monday 04 October 2010, Patrick Georgi wrote:
> Am 04.10.2010 07:33, schrieb Warren Turkal:
> > How do I show booting Windows 7 for a board I am working on? If I
> > can't because I don't have a license for Windows, should I not be able
> > to get the coreboot certification?
> 
> That's the difference between a certification that's useful for vendors
> and one that's useful for computing enthusiasts.

Carl-Daniel and myself were refering to the former one and Warrens seems to 
focus on the latter one. What do you think about doing one after another? 
Start off with minimal certificate to attract more developers and call it e.g. 
"Coreboot Beta Test" or "Coreboot under development". And at some later point, 
if OEMs got interested, go for a consumer certificate like "Coreboot 
compatible" or "Coreboot certified". The latter one should focus on the average 
user's needs/expectations, delivering a fire-and-forget solution for OEMs. The 
minimal certificate won't need to be printed on a box, as a product list on web 
would do fine. This would also prevent later confusion due to having more than 
one certificate logo out in the wild at the same time, as minimal and consumer 
certification time periods may overlap.

> Whoever produces and sells boards will have some Windows 7 license (and
> probably the dev builds to improve testing, as well as the Microsoft
> test kits) lying around.

True, the OEMs are likely to help out on that matter.

> That means, certification would be for different purposes.. a "coreboot
> + Linux" certificate would state that the board is actually useful
> beyond freedos (eg. networking works, HPET is around, ACPI is at least
> somewhat useful, even if Linux's ACPI interpreter is more forgiving than
> perl)
> 
> A "coreboot + Windows" certificate could build onto that, stating that
> Windows operation was tested, too. Stacking them this way would ensure
> that Windows support doesn't break Linux (or any other free OS).

A "Coreboot + $OS" logo could give a bad impression, as it will look like 
coreboot can only boot a specific OS. So a minimal and a consumer version of a 
certificate, where only the latter one would be printed on the box would have a 
more to-the-point expression to others. 

> But vendors will (except for some specialty shops or special customer
> requests) require the latter - with no regard for the former, except
> maybe to assess how much work they'd have to put in/sponsor to make a
> coreboot port Windows compatible.
> 
> As a side note on "Windows compatible", I'm not 100% sure on this, but I
> think the "Designed for Windows" set of certificates by Microsoft handle
> firmware behaviour, too.

This certaintly has the potential to threaten a coreboot certification. Even if 
there's no criteria now, Microsoft could add one to prevent OEMs to certify 
for both Windows and Coreboot at the same time. When the time comes for a 
coreboot consumer certificate some investigation on that matter is needed too.

> 
> Patrick




From rminnich at gmail.com  Mon Oct  4 19:56:07 2010
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Oct 2010 10:56:07 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <201010041950.25088.phorsyon@gmx.net>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
	<4CA978ED.8000002@georgi-clan.de>
	<201010041950.25088.phorsyon@gmx.net>
Message-ID: <AANLkTi=HoeizfAEe4YB9N1RoCznN8kFKwWDGkNuCvYu3@mail.gmail.com>

On Mon, Oct 4, 2010 at 10:50 AM, phorsyon <phorsyon at gmx.net> wrote:

> This certaintly has the potential to threaten a coreboot certification. Even if
> there's no criteria now, Microsoft could add one to prevent OEMs to certify
> for both Windows and Coreboot at the same time. When the time comes for a
> coreboot consumer certificate some investigation on that matter is needed too.

MS told me five years ago they'd be happy to certify coreboot as long
as we changed the name from linuxbios.

They have nothing against coreboot in principle -- quite the contrary.

ron



From phorsyon at gmx.net  Mon Oct  4 20:23:04 2010
From: phorsyon at gmx.net (phorsyon)
Date: Mon, 4 Oct 2010 20:23:04 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTi=HoeizfAEe4YB9N1RoCznN8kFKwWDGkNuCvYu3@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net> <201010041950.25088.phorsyon@gmx.net>
	<AANLkTi=HoeizfAEe4YB9N1RoCznN8kFKwWDGkNuCvYu3@mail.gmail.com>
Message-ID: <201010042023.06761.phorsyon@gmx.net>

On Monday 04 October 2010, ron minnich wrote:
> On Mon, Oct 4, 2010 at 10:50 AM, phorsyon <phorsyon at gmx.net> wrote:
> > This certaintly has the potential to threaten a coreboot certification.
> > Even if there's no criteria now, Microsoft could add one to prevent OEMs
> > to certify for both Windows and Coreboot at the same time. When the time
> > comes for a coreboot consumer certificate some investigation on that
> > matter is needed too.
> 
> MS told me five years ago they'd be happy to certify coreboot as long
> as we changed the name from linuxbios.
> 
> They have nothing against coreboot in principle -- quite the contrary.
> 
> ron

Well that's at least one thing less to care.
LinuxBIOS wasn't a good name anyway. BIOS just sounds so "legacy". ;-)



From uwe at hermann-uwe.de  Mon Oct  4 20:41:36 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 4 Oct 2010 20:41:36 +0200
Subject: [coreboot] [PATCH]First attempt at eliminating #include *.c
In-Reply-To: <4CA9F733.9050908@georgi-clan.de>
References: <4CA9F733.9050908@georgi-clan.de>
Message-ID: <20101004184136.GH3256@greenwood>

On Mon, Oct 04, 2010 at 05:48:03PM +0200, Patrick Georgi wrote:
> Hi,
> 
> attached patch removes several "#include *.c" from romstage.c in i945
> based boards and moves those files to romstage-srcs instead (ie.
> separate compilation units).
> 
> There's one global change, the removal of ramtest.c from CAR romstage.cs
> 
> It's abuild tested and boot tested on kontron/986lcd-m. Probably should
> be tested (so that ramtest.c stuff is a separate patch), but the global
> changes were actually the last change I made.
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Looks good.

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

There's one small warning e.g. on kontron/986lcd-m:
Makefile:261: warning: overriding commands for target `build/cpu/x86/name/name.ramstage.o'
Makefile:261: warning: ignoring old commands for target `build/cpu/x86/name/name.ramstage.o'

Also, building with Debug Port support breaks, but should be simple to
fix, it's just a missing prototype or #include I think:

cc1: warnings being treated as errors
src/mainboard/kontron/986lcd-m/romstage.c: In function ?main?:
src/mainboard/kontron/986lcd-m/romstage.c:352: error: implicit declaration of function ?i82801gx_enable_usbdebug?
src/mainboard/kontron/986lcd-m/romstage.c:353: error: implicit declaration of function ?early_usbdebug_init?
make: *** [build/mainboard/kontron/986lcd-m/romstage.pre.inc] Error 1


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From mylesgw at gmail.com  Mon Oct  4 21:17:36 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 4 Oct 2010 13:17:36 -0600
Subject: [coreboot] [PATCH]First attempt at eliminating #include *.c
In-Reply-To: <20101004184136.GH3256@greenwood>
References: <4CA9F733.9050908@georgi-clan.de> <20101004184136.GH3256@greenwood>
Message-ID: <AANLkTi=w94ZurrjPFvSE_nu8sFXaE8yLaQWEtAcmd3oK@mail.gmail.com>

> There's one small warning e.g. on kontron/986lcd-m:
> Makefile:261: warning: overriding commands for target `build/cpu/x86/name/name.ramstage.o'
> Makefile:261: warning: ignoring old commands for target `build/cpu/x86/name/name.ramstage.o'

I think those warnings come from putting subdirs-y += ../../x86/name
in each model (multiple times per socket) instead of each socket.
Sorry I didn't catch that when I reviewed that patch.  I started
moving them, but I don't know for sure which sockets should include
it.  Could you move them into the correct sockets & remove them from
the models?

Thanks,
Myles



From peter at stuge.se  Mon Oct  4 21:23:14 2010
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Oct 2010 21:23:14 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <201010041950.25088.phorsyon@gmx.net>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
	<4CA978ED.8000002@georgi-clan.de>
	<201010041950.25088.phorsyon@gmx.net>
Message-ID: <20101004192314.7903.qmail@stuge.se>

phorsyon wrote:
> a minimal and a consumer version of a certificate

As was mentioned, the more certifications there are, the less easy it
is for the market to make use of them.

I don't think we can afford to try to market two different
certifications. I would only like to try for one; "consumer coreboot"
or rather; "coreboot complete"

Developers don't want problems any more than average users just
because they may know how to deal with problems.

Anyway, if we would have criteria then we could also track them.

Any interested developer could easily discover what was missing for
a board to be coreboot complete, judge if it is a good choice for
them at the moment, and if not just look for completeness of other
boards.


//Peter



From mylesgw at gmail.com  Mon Oct  4 22:02:12 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 4 Oct 2010 14:02:12 -0600
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <20101003231014.23261.qmail@stuge.se>
References: <20101003231014.23261.qmail@stuge.se>
Message-ID: <AANLkTin4C57kkVZ0-EycRR4=bYQALM1NuqOkdnjEJRqL@mail.gmail.com>

On Sun, Oct 3, 2010 at 5:10 PM, Peter Stuge <peter at stuge.se> wrote:
> Rudolf just found a bug in the sb700 code:
>
> u32 dword;
> ..
> dword = pci_read_config8(dev, 0x64);
> dword |= 1 << 10;
> pci_write_config8(dev, 0x64, dword);
>
>
> And I'm ranting now, because a pci_set8() macro/function could have
> found this bug at compile time, and because I don't like these
> constructs. (Compiler warnings would also have indicated a problem.
> They're currently disabled for this code.)

How and where are compiler warnings disabled for this code?

Thanks,
Myles



From svn at coreboot.org  Mon Oct  4 22:43:55 2010
From: svn at coreboot.org (repository service)
Date: Mon, 04 Oct 2010 22:43:55 +0200
Subject: [coreboot] [commit] r5909 - in trunk/src/cpu/intel: model_68x
	model_6bx model_6xx
Message-ID: <E1P2rt5-00050V-MN@ra.coresystems.de>

Author: uwe
Date: Mon Oct  4 22:43:55 2010
New Revision: 5909
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5909

Log:
Add missing Intel Pentium II/III era CPU IDs.

Add links to the respective Intel specification updates or manuals where
the IDs are listed. Mention the possible core steppings of each CPU ID.

There are duplicate IDs in model_6xx and model_68x for now, not sure if
those should be eliminated, but there were already duplicates before this
patch, so that's probably an extra issue to look into.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/cpu/intel/model_68x/model_68x_init.c
   trunk/src/cpu/intel/model_6bx/model_6bx_init.c
   trunk/src/cpu/intel/model_6xx/model_6xx_init.c

Modified: trunk/src/cpu/intel/model_68x/model_68x_init.c
==============================================================================
--- trunk/src/cpu/intel/model_68x/model_68x_init.c	Sat Oct  2 22:51:29 2010	(r5908)
+++ trunk/src/cpu/intel/model_68x/model_68x_init.c	Mon Oct  4 22:43:55 2010	(r5909)
@@ -100,8 +100,26 @@
 	.init     = model_68x_init,
 };
 
+/*
+ * Intel Celeron Processor Identification Information
+ * http://www.intel.com/design/celeron/qit/update.pdf
+ *
+ * Intel Pentium III Processor Identification and Package Information
+ * http://www.intel.com/design/pentiumiii/qit/update.pdf
+ *
+ * Intel Pentium III Processor Specification Update
+ * http://download.intel.com/design/intarch/specupdt/24445358.pdf
+ *
+ * Mobile Intel Pentium III/III-M Processor Specification Update
+ * http://download.intel.com/design/intarch/specupdt/24530663.pdf
+ */
 static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, 0x0680 },
+	{ X86_VENDOR_INTEL, 0x0681 }, /* PIII, cA2/cA2c/A2/BA2/PA2/MA2 */
+	{ X86_VENDOR_INTEL, 0x0683 }, /* PIII/Celeron, cB0/cB0c/B0/BB0/PB0/MB0*/
+	{ X86_VENDOR_INTEL, 0x0686 }, /* PIII/Celeron, cC0/C0/BC0/PC0/MC0 */
+	{ X86_VENDOR_INTEL, 0x068a }, /* PIII/Celeron, cD0/D0/BD0/PD0 */
+
 	{ 0, 0 },
 };
 

Modified: trunk/src/cpu/intel/model_6bx/model_6bx_init.c
==============================================================================
--- trunk/src/cpu/intel/model_6bx/model_6bx_init.c	Sat Oct  2 22:51:29 2010	(r5908)
+++ trunk/src/cpu/intel/model_6bx/model_6bx_init.c	Mon Oct  4 22:43:55 2010	(r5909)
@@ -86,9 +86,16 @@
 	.init     = model_6bx_init,
 };
 
+/*
+ * Pentium III Processor Identification and Package Information.
+ * http://www.intel.com/design/pentiumiii/qit/update.pdf
+ *
+ * Intel Pentium III Processor Specification Update
+ * http://download.intel.com/design/intarch/specupdt/24445358.pdf
+ */
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_INTEL, 0x06B1 },
-	{ X86_VENDOR_INTEL, 0x06B4 }, /* Low Voltage PIII Micro-FCBGA Socket 479 */
+	{ X86_VENDOR_INTEL, 0x06b1 }, /* Pentium III/Celeron, tA1/A1/FPA1 */
+	{ X86_VENDOR_INTEL, 0x06b4 }, /* Pentium III, tB1/FPB1 */
 	{ 0, 0 },
 };
 

Modified: trunk/src/cpu/intel/model_6xx/model_6xx_init.c
==============================================================================
--- trunk/src/cpu/intel/model_6xx/model_6xx_init.c	Sat Oct  2 22:51:29 2010	(r5908)
+++ trunk/src/cpu/intel/model_6xx/model_6xx_init.c	Mon Oct  4 22:43:55 2010	(r5909)
@@ -51,20 +51,63 @@
 static struct device_operations cpu_dev_ops = {
 	.init     = model_6xx_init,
 };
+
+/*
+ * Intel Pentium Pro Processor Specification Update
+ * http://download.intel.com/design/archives/processors/pro/docs/24268935.pdf
+ *
+ * Intel Pentium II Processor Specification Update
+ * http://download.intel.com/design/PentiumII/specupdt/24333749.pdf
+ *
+ * Mobile Intel Pentium II Processor Specification Update
+ * http://download.intel.com/design/intarch/specupdt/24388757.pdf
+ *
+ * Intel Celeron Processor Identification Information
+ * http://www.intel.com/design/celeron/qit/update.pdf
+ *
+ * Intel Pentium II Xeon Processor Specification Update
+ * http://download.intel.com/support/processors/pentiumii/xeon/24377632.pdf
+ *
+ * Intel Pentium III Processor Identification and Package Information
+ * http://www.intel.com/design/pentiumiii/qit/update.pdf
+ *
+ * Intel Pentium III Processor Specification Update
+ * http://download.intel.com/design/intarch/specupdt/24445358.pdf
+ *
+ * Mobile Intel Pentium III/III-M Processor Specification Update
+ * http://download.intel.com/design/intarch/specupdt/24530663.pdf
+ */
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_INTEL, 0x0650 },
-	{ X86_VENDOR_INTEL, 0x0652 },
-	{ X86_VENDOR_INTEL, 0x0660 }, /* Celeron (Mendocino) */
-	{ X86_VENDOR_INTEL, 0x0665 },
-	{ X86_VENDOR_INTEL, 0x0672 },
-	{ X86_VENDOR_INTEL, 0x0673 },
+	{ X86_VENDOR_INTEL, 0x0611 }, /* Pentium Pro, B0 */
+	{ X86_VENDOR_INTEL, 0x0612 }, /* Pentium Pro, C0 */
+	{ X86_VENDOR_INTEL, 0x0616 }, /* Pentium Pro, sA0 */
+	{ X86_VENDOR_INTEL, 0x0617 }, /* Pentium Pro, sA1 */
+	{ X86_VENDOR_INTEL, 0x0619 }, /* Pentium Pro, sB1 */
+
+	{ X86_VENDOR_INTEL, 0x0633 }, /* PII, C0 */
+	{ X86_VENDOR_INTEL, 0x0634 }, /* PII, C1 */
+
+	{ X86_VENDOR_INTEL, 0x0650 }, /* PII/Celeron, dA0/mdA0/A0 */
+	{ X86_VENDOR_INTEL, 0x0651 }, /* PII/Celeron, dA1/A1 */
+	{ X86_VENDOR_INTEL, 0x0652 }, /* PII/Celeron/Xeon, dB0/mdB0/B0 */
+	{ X86_VENDOR_INTEL, 0x0653 }, /* PII/Xeon, dB1/B1 */
+
+	{ X86_VENDOR_INTEL, 0x0660 }, /* Celeron, A0 */
+	{ X86_VENDOR_INTEL, 0x0665 }, /* Celeron, B0 */
+	{ X86_VENDOR_INTEL, 0x066a }, /* PII, mdxA0/dmmA0 + others */
+
+	{ X86_VENDOR_INTEL, 0x0672 }, /* PIII, kB0 */
+	{ X86_VENDOR_INTEL, 0x0673 }, /* PIII, kC0 */
+
 	{ X86_VENDOR_INTEL, 0x0680 },
-	{ X86_VENDOR_INTEL, 0x0681 },
-	{ X86_VENDOR_INTEL, 0x0683 },
-	{ X86_VENDOR_INTEL, 0x0686 },
-	{ X86_VENDOR_INTEL, 0x06A0 },
-	{ X86_VENDOR_INTEL, 0x06A1 },
-	{ X86_VENDOR_INTEL, 0x06A4 },
+	{ X86_VENDOR_INTEL, 0x0681 }, /* PIII, cA2/cA2c/A2/BA2/PA2/MA2 */
+	{ X86_VENDOR_INTEL, 0x0683 }, /* PIII/Celeron, cB0/cB0c/B0/BB0/PB0/MB0*/
+	{ X86_VENDOR_INTEL, 0x0686 }, /* PIII/Celeron, cC0/C0/BC0/PC0/MC0 */
+	{ X86_VENDOR_INTEL, 0x068a }, /* PIII/Celeron, cD0/D0/BD0/PD0 */
+
+	{ X86_VENDOR_INTEL, 0x06a0 }, /* PIII, A0 */
+	{ X86_VENDOR_INTEL, 0x06a1 }, /* PIII, A1 */
+	{ X86_VENDOR_INTEL, 0x06a4 }, /* PIII, B0 */
 	{ 0, 0 },
 };
 



From rminnich at gmail.com  Tue Oct  5 00:14:34 2010
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Oct 2010 15:14:34 -0700
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <20101003231014.23261.qmail@stuge.se>
References: <20101003231014.23261.qmail@stuge.se>
Message-ID: <AANLkTi=tjwp-YjfJvEi_aQXk9Ozdf++qVXcgTuDzhHeH@mail.gmail.com>

On Sun, Oct 3, 2010 at 4:10 PM, Peter Stuge <peter at stuge.se> wrote:
> Rudolf just found a bug in the sb700 code:
>
> u32 dword;
> ..
> dword = pci_read_config8(dev, 0x64);
> dword |= 1 << 10;
> pci_write_config8(dev, 0x64, dword);


Actually, I don't even have a problem with this construct. Why?
Because it's in just about every kernel I've ever worked with. It's a
common technique. Sure, in this case, it's a trivially simple change
and you can write a function for it. But, as soon as things get more
complex, with multiline tests and bit sets, you can't use the
functions, and we're back to the same type of coding. Then we end up
with mixed idioms.

It's a good idea for our code base to adhere to such common idioms. It
makes for an easier time for people coming in from, e.g., Linux. I
don't find the functions easier.

Also, as pointed out, the proposed functions solve one special case.
Better to fix the real problem, which is that the compiler can tell us
about this type of error but we're not letting it. That will fix all
such problems, not just the pci subsystem.

Just another penny or so.

ron



From uwe at hermann-uwe.de  Tue Oct  5 00:57:49 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 5 Oct 2010 00:57:49 +0200
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <20101003231907.24422.qmail@stuge.se>
References: <20101003184734.GF3256@greenwood> <4CA8D701.5010203@georgi-clan.de>
	<4CA8EFE0.3040704@gmx.net> <4CA8F08F.50307@georgi-clan.de>
	<20101003215947.GG3256@greenwood> <4CA9084A.9080704@coresystems.de>
	<20101003231907.24422.qmail@stuge.se>
Message-ID: <20101004225748.GI3256@greenwood>

On Mon, Oct 04, 2010 at 01:19:07AM +0200, Peter Stuge wrote:
> Stefan Reinauer wrote:
> > > +config CPU_ADDR_BITS_MASK
> > 
> > Such stuff belongs into an include file, not into Kconfig.
> 
> Good point! I agree completely if it works in practise.

Are you guys suggesting something like this?

Index: src/include/cpu/cpu.h
===================================================================
--- src/include/cpu/cpu.h       (Revision 5909)
+++ src/include/cpu/cpu.h       (Arbeitskopie)
@@ -27,4 +27,21 @@
 /** end of compile time generated pci driver array */
 extern struct cpu_driver ecpu_drivers[];

+/*
+ * Map the number of address space bits supported by the CPU to the
+ * mask field value as it needs to be written into the upper 32 bits
+ * of the various MTRRphysMask_MSR MSRs.
+ */
+#if defined(CONFIG_CPU_ADDR_BITS) && (CONFIG_CPU_ADDR_BITS == 32)
+#define CONFIG_CPU_ADDR_BITS_MASK 0x00000000
+#elif defined(CONFIG_CPU_ADDR_BITS) && (CONFIG_CPU_ADDR_BITS == 36)
+#define CONFIG_CPU_ADDR_BITS_MASK 0x0000000f
+#elif defined(CONFIG_CPU_ADDR_BITS) && (CONFIG_CPU_ADDR_BITS == 40)
+#define CONFIG_CPU_ADDR_BITS_MASK 0x000000ff
+#elif defined(CONFIG_CPU_ADDR_BITS) && (CONFIG_CPU_ADDR_BITS == 48)
+#define CONFIG_CPU_ADDR_BITS_MASK 0x0000ffff
+#else
+#error No CPU_ADDR_BITS value was selected or an unknown value was selected
+#endif
+
 #endif /* CPU_CPU_H */

I guess that would work, but I'm not sure if that's really a better place for
the code or whether it looks more elegant than in a Kconfig file:

+config CPU_ADDR_BITS_MASK
+       hex
+       default 0x00000000 if CPU_ADDR_BITS_32
+       default 0x0000000f if CPU_ADDR_BITS_36
+       default 0x000000ff if CPU_ADDR_BITS_40
+       default 0x0000ffff if CPU_ADDR_BITS_48
+       help
+         Map the number of address space bits supported by the CPU to the
+         mask field value as it needs to be written into the upper 32 bits
+         of the various MTRRphysMask_MSR MSRs.

Also, if the variable is defined in a header file it should probably not have
the CONFIG_ prefix in the name right? I.e. CPU_ADDR_BITS_MASK, not
CONFIG_CPU_ADDR_BITS_MASK. Which IMHO is also a bit odd, as it _is_ indeed a
value derived from a (not user-visible) kconfig option.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From mylesgw at gmail.com  Tue Oct  5 02:03:30 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 4 Oct 2010 18:03:30 -0600
Subject: [coreboot] [PATCH] Streamline CPU_ADDR_BITS usage
In-Reply-To: <20101004225748.GI3256@greenwood>
References: <20101003184734.GF3256@greenwood>
	<4CA8D701.5010203@georgi-clan.de><4CA8EFE0.3040704@gmx.net>
	<4CA8F08F.50307@georgi-clan.de><20101003215947.GG3256@greenwood>
	<4CA9084A.9080704@coresystems.de><20101003231907.24422.qmail@stuge.se>
	<20101004225748.GI3256@greenwood>
Message-ID: <E1335A69A06C43C9A9BC520FB5461FA7@chimp>

> On Mon, Oct 04, 2010 at 01:19:07AM +0200, Peter Stuge wrote:
> > Stefan Reinauer wrote:
> > > > +config CPU_ADDR_BITS_MASK
> > >
> > > Such stuff belongs into an include file, not into Kconfig.
> >
> > Good point! I agree completely if it works in practise.
> 
> Are you guys suggesting something like this?
> 
> Index: src/include/cpu/cpu.h
> ===================================================================
> --- src/include/cpu/cpu.h       (Revision 5909)
> +++ src/include/cpu/cpu.h       (Arbeitskopie)
> @@ -27,4 +27,21 @@
>  /** end of compile time generated pci driver array */
>  extern struct cpu_driver ecpu_drivers[];
>
> +/*
> + * Map the number of address space bits supported by the CPU to the
> + * mask field value as it needs to be written into the upper 32 bits
> + * of the various MTRRphysMask_MSR MSRs.
> + */
> +#if defined(CONFIG_CPU_ADDR_BITS) && (CONFIG_CPU_ADDR_BITS == 32)
> +#define CONFIG_CPU_ADDR_BITS_MASK 0x00000000
> +#elif defined(CONFIG_CPU_ADDR_BITS) && (CONFIG_CPU_ADDR_BITS == 36)
> +#define CONFIG_CPU_ADDR_BITS_MASK 0x0000000f
> +#elif defined(CONFIG_CPU_ADDR_BITS) && (CONFIG_CPU_ADDR_BITS == 40)
> +#define CONFIG_CPU_ADDR_BITS_MASK 0x000000ff
> +#elif defined(CONFIG_CPU_ADDR_BITS) && (CONFIG_CPU_ADDR_BITS == 48)
> +#define CONFIG_CPU_ADDR_BITS_MASK 0x0000ffff
> +#else
> +#error No CPU_ADDR_BITS value was selected or an unknown value was
> selected
> +#endif
> +
>  #endif /* CPU_CPU_H */

I have no idea what others were envisioning, but I would think something
like this would work for me.

In a processor-specific file:
#define CPU_ADDR_BITS 40

In cpu.h:
#define CPU_ADDR_BITS_MASK (0xffff >> (48 - CPU_ADDR_BITS))

or for the future:
#define CPU_ADDR_BITS_MASK (0xffffff >> (56 - CPU_ADDR_BITS))

Thanks,
Myles





From uwe at hermann-uwe.de  Tue Oct  5 03:08:00 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 5 Oct 2010 03:08:00 +0200
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <AANLkTin4C57kkVZ0-EycRR4=bYQALM1NuqOkdnjEJRqL@mail.gmail.com>
References: <20101003231014.23261.qmail@stuge.se>
	<AANLkTin4C57kkVZ0-EycRR4=bYQALM1NuqOkdnjEJRqL@mail.gmail.com>
Message-ID: <20101005010759.GJ3256@greenwood>

On Mon, Oct 04, 2010 at 02:02:12PM -0600, Myles Watson wrote:
> On Sun, Oct 3, 2010 at 5:10 PM, Peter Stuge <peter at stuge.se> wrote:
> > Rudolf just found a bug in the sb700 code:
> >
> > u32 dword;
> > ..
> > dword = pci_read_config8(dev, 0x64);
> > dword |= 1 << 10;
> > pci_write_config8(dev, 0x64, dword);
> >
> >
> > And I'm ranting now, because a pci_set8() macro/function could have
> > found this bug at compile time, and because I don't like these
> > constructs. (Compiler warnings would also have indicated a problem.
> > They're currently disabled for this code.)
> 
> How and where are compiler warnings disabled for this code?

That was a misunderstanding I think, I mentioed (on IRC) warnings being
disabled for some parts of the coreboot code (tiny bootblock and others),
but that was not related to this specific code (sb700_sm.c).

The file gets compiled with:

gcc -m32 -Wa,--divide -fno-stack-protector -Wl,--build-id=none   -MMD
-Isrc -Isrc/include -Ibuild -Isrc/arch/i386/include
-Isrc/devices/oprom/include -include /home/uwe/v4_bar/build/config.h -Os
-nostdinc -pipe -g -nostdlib -Wall -Wundef -Wstrict-prototypes
-Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs
-Wstrict-aliasing -Wshadow -Werror -fno-common -ffreestanding
-fno-builtin -fomit-frame-pointer -c -o
build/southbridge/amd/sb700/sb700_sm.driver.o
src/southbridge/amd/sb700/sb700_sm.c


However, that doesn't expose the bug in this case. What would work is to
add '-Wconversion', that finds the bug:

src/southbridge/amd/sb700/sb700_sm.c:88: error: conversion to ?uint8_t? from ?u32? may alter its value

However, it also spews 30 or more of these lines for every single file
we have in coreboot, so it's not really a practical option to enable
permanently (or at least not at this point in time).


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From peter at stuge.se  Tue Oct  5 03:45:17 2010
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 Oct 2010 03:45:17 +0200
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <AANLkTi=tjwp-YjfJvEi_aQXk9Ozdf++qVXcgTuDzhHeH@mail.gmail.com>
References: <20101003231014.23261.qmail@stuge.se>
	<AANLkTi=tjwp-YjfJvEi_aQXk9Ozdf++qVXcgTuDzhHeH@mail.gmail.com>
Message-ID: <20101005014518.15748.qmail@stuge.se>

ron minnich wrote:
> > dword = pci_read_config8(dev, 0x64);
> > dword |= 1 << 10;
> > pci_write_config8(dev, 0x64, dword);
> 
> Actually, I don't even have a problem with this construct. Why?
> Because it's in just about every kernel I've ever worked with.
> It's a common technique.

Other kids doing it isn't neccessarily a good reason.


> simple
> complex
> mixed idioms.

I think the ratio of simple vs. complex operations is significant.
The majority I've seen in the code are simple, but granted I haven't
read every file. I agree that mixed idioms are annoying if nothing
else, but I think the benefit from replacing all the simple cases is
important enough to do it.

Those complex cases will stand out more and may thus get more careful
review, hopefully finding bugs earlier. There's a high ratio of noise
and repetition in the quoted code.


> It's a good idea for our code base to adhere to such common idioms.
> It makes for an easier time for people coming in from, e.g., Linux.
> I don't find the functions easier.

Maybe we could try them on for size for a while anyway? I wrote a
semantic patch to have coccinelle do this change. The spatch isn't
complete however, I should also try to make it remove variables that
are now unused. Anyway, both .cocci and resulting .patch are
attached.

I was surprised but happy to discover that comments in the third file
src/cpu/amd/quadcore/quadcore.c actually match the code almost word
for word after the change. Apparently I'm not completely alone in my
way of thinking about these things. ;)

Testing this it became obvious why I prefer set and clear: they take
un-modified bits as input, whereas pci_and8() would require callers
to do the ~() trick, which I also think is very nice to get rid of.


Commands used to generate patch and diffstat:
grep -lr =.*pci_read_config src|grep -v '/\.svn/'|uniq|xargs spatch -sp_file pci_set_clear.cocci > pci_set_clear.patch
sed -e '/^---/{h;d}' -e '/^+++/{p;x}' -e 's,^--- src/,+++ src/,' pci_set_clear.patch |sed 's,^+++ /tmp,--- /tmp,'|diffstat > pci_set_clear.diffstat


> Also, as pointed out, the proposed functions solve one special case.
> Better to fix the real problem, which is that the compiler can tell
> us about this type of error but we're not letting it. That will fix
> all such problems, not just the pci subsystem.

I completely agree that we need to get the deal with warnings sorted.
I will admit that I used the bug a little bit as an excuse to bring
these functions up again, because I associated strongly when looking
at the bug.


//Peter
-------------- next part --------------
@ doubleor8 @
expression tmp, dev, reg, val, val2;
@@
  tmp = pci_read_config8(dev, reg);
- tmp |= val;
- tmp |= val2;
+ tmp |= val | val2;
  pci_write_config8(dev, reg, tmp);
@ doubleand8 @
expression tmp, dev, reg, val, val2;
@@
  tmp = pci_read_config8(dev, reg);
- tmp &= ~val;
- tmp &= ~val2;
+ tmp &= ~(val | val2);
  pci_write_config8(dev, reg, tmp);
@ set8 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config8(dev, reg);
- tmp |= val;
- pci_write_config8(dev, reg, tmp);
+ pci_set8(dev, reg, val);
@ clear8 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config8(dev, reg);
- tmp &= ~val;
- pci_write_config8(dev, reg, tmp);
+ pci_clear8(dev, reg, val);
@ doubleor16 @
expression tmp, dev, reg, val, val2;
@@
  tmp = pci_read_config16(dev, reg);
- tmp |= val;
- tmp |= val2;
+ tmp |= val | val2;
  pci_write_config16(dev, reg, tmp);
@ doubleand16 @
expression tmp, dev, reg, val, val2;
@@
  tmp = pci_read_config16(dev, reg);
- tmp &= ~val;
- tmp &= ~val2;
+ tmp &= ~(val | val2);
  pci_write_config16(dev, reg, tmp);
@ set16 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config16(dev, reg);
- tmp |= val;
- pci_write_config16(dev, reg, tmp);
+ pci_set16(dev, reg, val);
@ clear16 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config16(dev, reg);
- tmp &= ~val;
- pci_write_config16(dev, reg, tmp);
+ pci_clear16(dev, reg, val);
@ doubleor32 @
expression tmp, dev, reg, val, val2;
@@
  tmp = pci_read_config32(dev, reg);
- tmp |= val;
- tmp |= val2;
+ tmp |= val | val2;
  pci_write_config32(dev, reg, tmp);
@ doubleand32 @
expression tmp, dev, reg, val, val2;
@@
  tmp = pci_read_config32(dev, reg);
- tmp &= ~val;
- tmp &= ~val2;
+ tmp &= ~(val | val2);
  pci_write_config32(dev, reg, tmp);
@ set32 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config32(dev, reg);
- tmp |= val;
- pci_write_config32(dev, reg, tmp);
+ pci_set32(dev, reg, val);
@ clear32 @
expression tmp, dev, reg, val;
@@
- tmp = pci_read_config32(dev, reg);
- tmp &= ~val;
- pci_write_config32(dev, reg, tmp);
+ pci_clear32(dev, reg, val);
-------------- next part --------------
Incomplete proof of concept patch. NOT! Signed off.

 cpu/amd/dualcore/amd_sibling.c                     |    4 
 cpu/amd/dualcore/dualcore.c                        |    8 -
 cpu/amd/model_10xxx/init_cpus.c                    |    8 -
 cpu/amd/model_fxx/fidvid.c                         |    4 
 cpu/amd/quadcore/amd_sibling.c                     |    4 
 cpu/amd/quadcore/quadcore.c                        |    8 -
 devices/hypertransport.c                           |    4 
 devices/pci_device.c                               |    4 
 devices/pciexp_device.c                            |    4 
 drivers/sil/3114/sil_sata.c                        |    8 -
 mainboard/amd/dbm690t/mainboard.c                  |    8 -
 mainboard/amd/mahogany/mainboard.c                 |    5 -
 mainboard/amd/mahogany_fam10/mainboard.c           |    5 -
 mainboard/amd/pistachio/mainboard.c                |   16 ---
 mainboard/amd/tilapia_fam10/mainboard.c            |   21 ----
 mainboard/arima/hdama/mptable.c                    |    4 
 mainboard/asus/a8n_e/romstage.c                    |    8 -
 mainboard/asus/a8v-e_se/romstage.c                 |    4 
 mainboard/asus/m2v-mx_se/romstage.c                |    5 -
 mainboard/asus/m4a785-m/mainboard.c                |   13 --
 mainboard/broadcom/blast/mptable.c                 |    4 
 mainboard/dell/s1850/romstage.c                    |   36 ++------
 mainboard/dell/s1850/watchdog.c                    |    4 
 mainboard/getac/p470/romstage.c                    |   20 +---
 mainboard/gigabyte/ga_2761gxdk/romstage.c          |   16 +--
 mainboard/gigabyte/m57sli/romstage.c               |   16 +--
 mainboard/gigabyte/ma785gmt/mainboard.c            |   21 ----
 mainboard/gigabyte/ma78gm/mainboard.c              |    5 -
 mainboard/hp/dl145_g3/mptable.c                    |    8 -
 mainboard/hp/dl165_g6_fam10/mptable.c              |    8 -
 mainboard/ibase/mb899/romstage.c                   |   20 +---
 mainboard/intel/d945gclf/romstage.c                |   20 +---
 mainboard/intel/jarrell/jarrell_fixups.c           |    4 
 mainboard/intel/jarrell/watchdog.c                 |   16 ---
 mainboard/jetway/pa78vm5/mainboard.c               |    5 -
 mainboard/kontron/986lcd-m/romstage.c              |   20 +---
 mainboard/kontron/kt690/mainboard.c                |    8 -
 mainboard/msi/ms7135/romstage.c                    |    9 --
 mainboard/msi/ms7260/romstage.c                    |   16 +--
 mainboard/msi/ms9185/mptable.c                     |    4 
 mainboard/msi/ms9282/romstage.c                    |    4 
 mainboard/msi/ms9652_fam10/romstage.c              |    4 
 mainboard/nvidia/l1_2pvv/romstage.c                |   16 +--
 mainboard/roda/rk886ex/romstage.c                  |   20 +---
 mainboard/sunw/ultra40/romstage.c                  |    4 
 mainboard/supermicro/h8dme/romstage.c              |   16 +--
 mainboard/supermicro/h8dmr/romstage.c              |   16 +--
 mainboard/supermicro/h8dmr_fam10/romstage.c        |   16 +--
 mainboard/supermicro/h8qme_fam10/romstage.c        |   16 +--
 mainboard/supermicro/x6dai_g/watchdog.c            |    4 
 mainboard/supermicro/x6dhe_g/watchdog.c            |    4 
 mainboard/supermicro/x6dhe_g2/watchdog.c           |    4 
 mainboard/supermicro/x6dhr_ig/watchdog.c           |    4 
 mainboard/supermicro/x6dhr_ig2/watchdog.c          |    4 
 mainboard/technexion/tim5690/mainboard.c           |    4 
 mainboard/technexion/tim5690/tn_post_code.c        |   40 ++-------
 mainboard/technexion/tim8690/mainboard.c           |   13 --
 mainboard/tyan/s2891/romstage.c                    |   13 --
 mainboard/tyan/s2892/romstage.c                    |   10 --
 mainboard/tyan/s2895/romstage.c                    |   16 +--
 mainboard/tyan/s2912/romstage.c                    |   17 +--
 mainboard/tyan/s2912_fam10/romstage.c              |   17 +--
 mainboard/via/epia-m/romstage.c                    |    5 -
 mainboard/via/epia-m700/romstage.c                 |    4 
 mainboard/via/epia-n/romstage.c                    |    5 -
 mainboard/via/epia/romstage.c                      |    5 -
 mainboard/via/vt8454c/romstage.c                   |    4 
 northbridge/amd/amdfam10/misc_control.c            |    4 
 northbridge/amd/amdfam10/reset_test.c              |    4 
 northbridge/amd/amdk8/coherent_ht.c                |   10 --
 northbridge/amd/amdk8/exit_from_self.c             |   18 ----
 northbridge/amd/amdk8/incoherent_ht.c              |    4 
 northbridge/amd/amdk8/misc_control.c               |   13 --
 northbridge/amd/amdk8/raminit.c                    |    8 -
 northbridge/amd/amdk8/raminit_f.c                  |   22 +----
 northbridge/amd/amdk8/raminit_f_dqs.c              |   16 ---
 northbridge/amd/amdk8/reset_test.c                 |    8 -
 northbridge/intel/e7501/raminit.c                  |   34 ++-----
 northbridge/intel/e7520/raminit.c                  |    4 
 northbridge/intel/e7525/raminit.c                  |    4 
 northbridge/intel/i3100/raminit.c                  |    4 
 northbridge/intel/i82830/raminit.c                 |   13 --
 northbridge/intel/i855/raminit.c                   |    4 
 northbridge/intel/i945/early_init.c                |   24 +----
 northbridge/intel/i945/raminit.c                   |   31 +------
 northbridge/via/cn400/agp.c                        |    4 
 northbridge/via/cn400/northbridge.c                |   12 --
 northbridge/via/cn400/raminit.c                    |    8 -
 northbridge/via/cn400/vlink.c                      |   16 ---
 northbridge/via/cn700/agp.c                        |    4 
 northbridge/via/cn700/northbridge.c                |    8 -
 northbridge/via/cx700/cx700_agp.c                  |    8 -
 northbridge/via/cx700/cx700_lpc.c                  |   24 +----
 northbridge/via/cx700/cx700_sata.c                 |   20 +---
 northbridge/via/cx700/cx700_usb.c                  |    4 
 northbridge/via/cx700/raminit.c                    |   40 ++-------
 northbridge/via/vx800/dev_init.c                   |   80 ++++--------------
 northbridge/via/vx800/driving_setting.c            |   12 --
 northbridge/via/vx800/examples/romstage.c          |    4 
 northbridge/via/vx800/rank_map.c                   |    8 -
 northbridge/via/vx800/uma_ram_setting.c            |   13 --
 northbridge/via/vx800/vx800_lpc.c                  |   28 +-----
 southbridge/amd/amd8111/amd8111_acpi.c             |    4 
 southbridge/amd/amd8111/amd8111_early_ctrl.c       |    4 
 southbridge/amd/amd8111/amd8111_lpc.c              |   21 +---
 southbridge/amd/amd8111/amd8111_pci.c              |    5 -
 southbridge/amd/amd8131/amd8131_bridge.c           |   32 +------
 southbridge/amd/amd8132/amd8132_bridge.c           |   33 +------
 southbridge/amd/amd8151/amd8151_agp3.c             |    8 -
 southbridge/amd/cs5530/cs5530_enable_rom.c         |    4 
 southbridge/amd/cs5536/cs5536_ide.c                |    4 
 southbridge/amd/rs690/rs690.c                      |    8 -
 southbridge/amd/rs690/rs690_gfx.c                  |    8 -
 southbridge/amd/rs690/rs690_ht.c                   |    9 --
 southbridge/amd/rs690/rs690_pcie.c                 |   27 +-----
 southbridge/amd/rs780/rs780.c                      |   16 ---
 southbridge/amd/rs780/rs780_early_setup.c          |   12 --
 southbridge/amd/rs780/rs780_gfx.c                  |    9 --
 southbridge/amd/rs780/rs780_ht.c                   |    9 --
 southbridge/amd/sb600/sb600_early_setup.c          |   92 +++++----------------
 southbridge/amd/sb600/sb600_ide.c                  |   12 --
 southbridge/amd/sb600/sb600_lpc.c                  |   16 ---
 southbridge/amd/sb600/sb600_pci.c                  |   64 +++-----------
 southbridge/amd/sb600/sb600_sata.c                 |   38 ++------
 southbridge/amd/sb600/sb600_sm.c                   |   14 ---
 southbridge/amd/sb600/sb600_usb.c                  |   32 +------
 southbridge/amd/sb700/sb700_early_setup.c          |   80 ++++--------------
 southbridge/amd/sb700/sb700_ide.c                  |   16 ---
 southbridge/amd/sb700/sb700_lpc.c                  |   16 ---
 southbridge/amd/sb700/sb700_pci.c                  |   57 ++-----------
 southbridge/amd/sb700/sb700_sata.c                 |   34 +------
 southbridge/amd/sb700/sb700_sm.c                   |   26 +----
 southbridge/amd/sb700/sb700_usb.c                  |   20 +---
 southbridge/broadcom/bcm21000/bcm21000_pcie.c      |    9 --
 southbridge/broadcom/bcm5780/bcm5780_pcie.c        |    5 -
 southbridge/broadcom/bcm5785/bcm5785_early_setup.c |   34 +------
 southbridge/broadcom/bcm5785/bcm5785_enable_rom.c  |    4 
 southbridge/broadcom/bcm5785/bcm5785_sata.c        |    4 
 southbridge/broadcom/bcm5785/bcm5785_usb.c         |    4 
 southbridge/intel/esb6300/esb6300_lpc.c            |   13 --
 southbridge/intel/esb6300/esb6300_pci.c            |    8 -
 southbridge/intel/esb6300/esb6300_pic.c            |    4 
 southbridge/intel/i3100/i3100_lpc.c                |    8 -
 southbridge/intel/i82371eb/i82371eb_early_pm.c     |    8 -
 southbridge/intel/i82371eb/i82371eb_early_smbus.c  |    8 -
 southbridge/intel/i82801ax/i82801ax_pci.c          |   10 --
 southbridge/intel/i82801ax/i82801ax_watchdog.c     |    4 
 southbridge/intel/i82801bx/i82801bx_pci.c          |   10 --
 southbridge/intel/i82801bx/i82801bx_watchdog.c     |    4 
 southbridge/intel/i82801dx/i82801dx_pci.c          |    5 -
 southbridge/intel/i82801dx/i82801dx_smihandler.c   |    8 -
 southbridge/intel/i82801ex/i82801ex_lpc.c          |   16 ---
 southbridge/intel/i82801ex/i82801ex_pci.c          |    8 -
 southbridge/intel/i82801ex/i82801ex_watchdog.c     |    4 
 southbridge/intel/i82801gx/i82801gx.c              |    4 
 southbridge/intel/i82801gx/i82801gx_azalia.c       |   12 --
 southbridge/intel/i82801gx/i82801gx_lpc.c          |    4 
 southbridge/intel/i82801gx/i82801gx_pci.c          |    9 --
 southbridge/intel/i82801gx/i82801gx_pcie.c         |   16 ---
 southbridge/intel/i82801gx/i82801gx_sata.c         |   12 --
 southbridge/intel/i82801gx/i82801gx_smihandler.c   |    4 
 southbridge/intel/i82801gx/i82801gx_usb.c          |    4 
 southbridge/intel/i82801gx/i82801gx_usb_ehci.c     |   15 ---
 southbridge/intel/i82801gx/i82801gx_watchdog.c     |    4 
 southbridge/intel/pxhd/pxhd_bridge.c               |    4 
 southbridge/nvidia/ck804/ck804.c                   |    6 -
 southbridge/nvidia/ck804/ck804_enable_rom.c        |    4 
 southbridge/nvidia/ck804/ck804_ide.c               |    4 
 southbridge/nvidia/ck804/ck804_lpc.c               |   12 --
 southbridge/nvidia/ck804/ck804_pci.c               |    9 --
 southbridge/nvidia/ck804/ck804_pcie.c              |    5 -
 southbridge/nvidia/ck804/ck804_sata.c              |    4 
 southbridge/nvidia/ck804/ck804_usb2.c              |    4 
 southbridge/nvidia/mcp55/mcp55.c                   |    4 
 southbridge/nvidia/mcp55/mcp55_azalia.c            |   12 --
 southbridge/nvidia/mcp55/mcp55_early_setup_car.c   |    8 -
 southbridge/nvidia/mcp55/mcp55_enable_rom.c        |   12 --
 southbridge/nvidia/mcp55/mcp55_ide.c               |    4 
 southbridge/nvidia/mcp55/mcp55_lpc.c               |    8 -
 southbridge/nvidia/mcp55/mcp55_pci.c               |   14 ---
 southbridge/nvidia/mcp55/mcp55_pcie.c              |    5 -
 southbridge/nvidia/mcp55/mcp55_sata.c              |    4 
 southbridge/nvidia/mcp55/mcp55_usb2.c              |    4 
 southbridge/sis/sis966/sis966.c                    |    4 
 southbridge/sis/sis966/sis966_early_setup_car.c    |    8 -
 southbridge/sis/sis966/sis966_ide.c                |    4 
 southbridge/sis/sis966/sis966_lpc.c                |    8 -
 southbridge/sis/sis966/sis966_nic.c                |    4 
 southbridge/sis/sis966/sis966_pcie.c               |    5 -
 southbridge/ti/pci7420/pci7420_cardbus.c           |    8 -
 southbridge/via/k8t890/k8t890_bridge.c             |    4 
 southbridge/via/k8t890/k8t890_ctrl.c               |    8 -
 southbridge/via/k8t890/k8t890_early_car.c          |    4 
 southbridge/via/k8t890/k8t890_host.c               |   12 --
 southbridge/via/k8t890/k8t890_traf_ctrl.c          |    5 -
 southbridge/via/vt8231/vt8231.c                    |    4 
 southbridge/via/vt8231/vt8231_early_serial.c       |    4 
 southbridge/via/vt8231/vt8231_early_smbus.c        |    8 -
 southbridge/via/vt8231/vt8231_ide.c                |    4 
 southbridge/via/vt8231/vt8231_lpc.c                |   20 +---
 southbridge/via/vt8231/vt8231_nic.c                |    4 
 southbridge/via/vt8235/vt8235.c                    |    8 -
 southbridge/via/vt8235/vt8235_ide.c                |    4 
 southbridge/via/vt8235/vt8235_lpc.c                |   24 +----
 southbridge/via/vt8235/vt8235_nic.c                |    4 
 southbridge/via/vt8237r/vt8237_ctrl.c              |   12 --
 southbridge/via/vt8237r/vt8237r_early_smbus.c      |    4 
 southbridge/via/vt8237r/vt8237r_ide.c              |    8 -
 southbridge/via/vt8237r/vt8237r_lpc.c              |   32 +------
 southbridge/via/vt8237r/vt8237r_sata.c             |    4 
 southbridge/via/vt8237r/vt8237r_usb.c              |    8 -
 211 files changed, 644 insertions(+), 1909 deletions(-)

--- src/cpu/amd/model_10xxx/init_cpus.c	2010-10-01 09:27:05.000000000 +0200
+++ /tmp/cocci-output-5159-af6345-init_cpus.c	2010-10-05 03:02:08.273450418 +0200
@@ -238,9 +238,7 @@ static void enable_apic_ext_id(u32 node)
 {
 	u32 val;
 
-	val = pci_read_config32(NODE_HT(node), 0x68);
-	val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
-	pci_write_config32(NODE_HT(node), 0x68, val);
+	pci_set32(NODE_HT(node), 0x68, (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST));
 }
 
 static void STOP_CAR_AND_CPU(void)
@@ -426,9 +424,7 @@ static void start_node(u8 node)
 #endif
 
 	/* Allow APs to make requests (ROM fetch) */
-	val = pci_read_config32(NODE_HT(node), 0x6c);
-	val &= ~(1 << 1);
-	pci_write_config32(NODE_HT(node), 0x6c, val);
+	pci_clear32(NODE_HT(node), 0x6c, (1 << 1));
 
 	printk(BIOS_DEBUG, " done.\n");
 }
--- src/cpu/amd/model_fxx/fidvid.c	2010-10-01 09:27:04.000000000 +0200
+++ /tmp/cocci-output-5159-f90259-fidvid.c	2010-10-05 03:02:09.512443971 +0200
@@ -52,9 +52,7 @@ static void enable_fid_change(void)
 
 		/* disable the DRAM interface at first, it will be enabled
 		 * by raminit again */
-		dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94);
-		dword |= (1 << 14);
-		pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword);
+		pci_set32(PCI_DEV(0, 0x18 + i, 2), 0x94, (1 << 14));
 
 		dword = 0x23070700;	/* enable FID/VID change */
 //              dword = 0x00070000; /* enable FID/VID change */
--- src/cpu/amd/quadcore/quadcore.c	2010-10-01 09:27:04.000000000 +0200
+++ /tmp/cocci-output-5159-188a6a-quadcore.c	2010-10-05 03:02:10.440443856 +0200
@@ -69,13 +69,9 @@ static void real_start_other_core(u32 no
 
 	/* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
 	   accesses and error logging to core0 */
-	dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44);
-	dword |= 1 << 27;	// NbMcaToMstCpuEn bit
-	pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword);
+	pci_set32(NODE_PCI(nodeid, 3), 0x44, 1 << 27);
 	// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
-	dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
-	dword |= 1 << 5;
-	pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword);
+	pci_set32(NODE_PCI(nodeid, 0), 0x68, 1 << 5);
 
 	if(cores > 1) {
 		dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
--- src/cpu/amd/quadcore/amd_sibling.c	2010-10-01 09:27:04.000000000 +0200
+++ /tmp/cocci-output-5159-af31e0-amd_sibling.c	2010-10-05 03:02:10.736445301 +0200
@@ -67,9 +67,7 @@ static void enable_apic_ext_id(u32 nodes
 	for(nodeid=0; nodeid<nodes; nodeid++){
 		u32 val;
 		dev = get_node_pci(nodeid, 0);
-		val = pci_read_config32(dev, 0x68);
-		val |= (1<<17)|(1<<18);
-		pci_write_config32(dev, 0x68, val);
+		pci_set32(dev, 0x68, (1 << 17) | (1 << 18));
 	}
 }
 
--- src/cpu/amd/dualcore/dualcore.c	2010-10-01 09:27:04.000000000 +0200
+++ /tmp/cocci-output-5159-6d84dc-dualcore.c	2010-10-05 03:02:11.032443892 +0200
@@ -45,13 +45,9 @@ static inline void real_start_other_core
 {
 	uint32_t dword;
 	// set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0
-	dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44);
-	dword |= 1<<27; // NbMcaToMstCpuEn bit
-	pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword);
+	pci_set32(PCI_DEV(0, 0x18 + nodeid, 3), 0x44, 1 << 27);
 	// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
-	dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68);
-	dword |= 1<<5;
-	pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword);
+	pci_set32(PCI_DEV(0, 0x18 + nodeid, 0), 0x68, 1 << 5);
 }
 
 //it is running on core0 of node0
--- src/cpu/amd/dualcore/amd_sibling.c	2010-10-01 09:27:04.000000000 +0200
+++ /tmp/cocci-output-5159-4258ec-amd_sibling.c	2010-10-05 03:02:11.304444501 +0200
@@ -45,9 +45,7 @@ static void enable_apic_ext_id(int nodes
         for(nodeid=0; nodeid<nodes; nodeid++){
                 uint32_t val;
                 dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
-                val = pci_read_config32(dev, 0x68);
-		val |= (1<<17)|(1<<18);
-		pci_write_config32(dev, 0x68, val);
+                pci_set32(dev, 0x68, (1 << 17) | (1 << 18));
         }
 }
 
--- src/devices/pciexp_device.c	2010-10-01 09:27:03.000000000 +0200
+++ /tmp/cocci-output-5159-869853-pciexp_device.c	2010-10-05 03:02:11.676444238 +0200
@@ -40,9 +40,7 @@ static void pciexp_tune_dev(device_t dev
 	// TODO make this depending on ASPM
 	/* Enable ASPM Role Based Error Reporting */
 	u32 reg32;
-	reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
-	reg32 |= PCI_EXP_DEVCAP_RBER;
-	pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+	pci_set32(dev, cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
 #endif
 }
 
--- src/devices/hypertransport.c	2010-10-01 09:27:03.000000000 +0200
+++ /tmp/cocci-output-5159-a94e33-hypertransport.c	2010-10-05 03:02:12.072452863 +0200
@@ -368,9 +368,7 @@ static void ht_collapse_early_enumeratio
 		}
 
 		/* Clear the unitid */
-		flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
-		flags &= ~0x1f;
-		pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
+		pci_clear16(&dummy, pos + PCI_CAP_FLAGS, 0x1f);
 		printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n",
 			dev_path(&dummy), dummy.vendor, dummy.device);
 	}
--- src/devices/pci_device.c	2010-10-01 09:27:03.000000000 +0200
+++ /tmp/cocci-output-5159-69ea6d-pci_device.c	2010-10-05 03:02:12.976444094 +0200
@@ -626,9 +626,7 @@ void pci_bus_enable_resources(struct dev
 void pci_bus_reset(struct bus *bus)
 {
 	unsigned ctl;
-	ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
-	ctl |= PCI_BRIDGE_CTL_BUS_RESET;
-	pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
+	pci_set16(bus->dev, PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
 	mdelay(10);
 	ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 	pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
--- src/drivers/sil/3114/sil_sata.c	2010-10-01 09:27:15.000000000 +0200
+++ /tmp/cocci-output-5159-569390-sil_sata.c	2010-10-05 03:02:14.212452144 +0200
@@ -19,16 +19,12 @@ static void si_sata_init(struct device *
 {
 	uint32_t dword;
 	/* enable change device id and class id */
-	dword = pci_read_config32(dev,0x40);
-	dword |= (1<<0);
-	pci_write_config32(dev, 0x40, dword);
+	pci_set32(dev, 0x40, (1 << 0));
 	/* Set IDE Class, Native mode, two drives per channel */
 	dword = 0x01018f00;
 	pci_write_config32(dev, 0x08, dword);
 	/* disable change device id and class id*/
-	dword = pci_read_config32(dev,0x40);
-	dword &= ~(1<<0);
-	pci_write_config32(dev, 0x40, dword);
+	pci_clear32(dev, 0x40, (1 << 0));
 	printk(BIOS_INFO, "SIL3114 set to IDE compatible mode\n");
 }
 
--- src/northbridge/amd/amdk8/raminit_f.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-1b9604-raminit_f.c	2010-10-05 03:02:14.452444680 +0200
@@ -891,9 +891,7 @@ static void set_dimm_size(const struct m
 #endif
 
 		if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
-			dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
-			dword &= ~(ClkDis0 >> index);
-			pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
+			pci_clear32(ctrl->f2, DRAM_CTRL_MISC, (ClkDis0 >> index));
 
 		} else {
 			dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
@@ -1523,9 +1521,7 @@ static long spd_enable_2channels(const s
 			/* mux capable and single dimm in channelB */
 			if (mux_cap) {
 				printk(BIOS_SPEW, "Enable 64MuxMode & BurstLength32\n");
-				dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
-				dcm |= DCM_Mode64BitMux;
-				pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
+				pci_set32(ctrl->f2, DRAM_CTRL_MISC, DCM_Mode64BitMux);
 				dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 				//dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
 				pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
@@ -2217,9 +2213,7 @@ static void set_4RankRDimm(const struct 
 
 	if (value == 1) {
 		uint32_t dch;
-		dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
-		dch |= DCH_FourRankRDimm;
-		pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+		pci_set32(ctrl->f2, DRAM_CONFIG_HIGH, DCH_FourRankRDimm);
 	}
 #endif
 }
@@ -2494,11 +2488,7 @@ static void set_SlowAccessMode(const str
 {
 	uint32_t dch;
 
-	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
-
-	dch |= (1<<20);
-
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+	pci_set32(ctrl->f2, DRAM_CONFIG_HIGH, (1 << 20));
 }
 #endif
 
@@ -3079,9 +3069,7 @@ static void sdram_enable(int controllers
 			//Rev F0/F1 workaround
 #if 1
 				/* Set the DqsRcvEnTrain bit */
-			dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
-			dword |= DC_DqsRcvEnTrain;
-			pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
+			pci_set32(ctrl[i].f2, DRAM_CTRL, DC_DqsRcvEnTrain);
 #endif
 			tsc0[i] = rdtsc();
 		}
--- src/northbridge/amd/amdk8/raminit_f_dqs.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-2c5361-raminit_f_dqs.c	2010-10-05 03:02:17.756443856 +0200
@@ -556,9 +556,7 @@ static unsigned TrainRcvrEn(const struct
 	{
 #if 1
 		/* Set the DqsRcvEnTrain bit */
-		dword = pci_read_config32(ctrl->f2, DRAM_CTRL);
-		dword |= DC_DqsRcvEnTrain;
-		pci_write_config32(ctrl->f2, DRAM_CTRL, dword);
+		pci_set32(ctrl->f2, DRAM_CTRL, DC_DqsRcvEnTrain);
 #endif
 	}
 	}
@@ -841,9 +839,7 @@ static unsigned TrainRcvrEn(const struct
 	if(!cpu_f0_f1)
 #endif
 	{
-		dword = pci_read_config32(ctrl->f2, DRAM_CTRL);
-		dword &= ~DC_DqsRcvEnTrain;
-		pci_write_config32(ctrl->f2, DRAM_CTRL, dword);
+		pci_clear32(ctrl->f2, DRAM_CTRL, DC_DqsRcvEnTrain);
 	}
 	}
 
@@ -1572,13 +1568,9 @@ static void f0_svm_workaround(int contro
 
 		if(!cpu_f0_f1[i]) continue;
 
-		dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
-		dword &= ~DC_DqsRcvEnTrain;
-		pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
+		pci_clear32(ctrl[i].f2, DRAM_CTRL, DC_DqsRcvEnTrain);
 
-		dword = pci_read_config32(ctrl[i].f2, DRAM_INIT);
-		dword |= DI_EnDramInit;
-		pci_write_config32(ctrl[i].f2, DRAM_INIT, dword);
+		pci_set32(ctrl[i].f2, DRAM_INIT, DI_EnDramInit);
 		dword &= ~DI_EnDramInit;
 		pci_write_config32(ctrl[i].f2, DRAM_INIT, dword);
 
--- src/northbridge/amd/amdk8/reset_test.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-e2ab30-reset_test.c	2010-10-05 03:02:20.976444101 +0200
@@ -39,17 +39,13 @@ static inline void distinguish_cpu_reset
 	u32 htic;
 	device_t device;
 	device = PCI_DEV(0, 0x18 + nodeid, 0);
-	htic = pci_read_config32(device, HT_INIT_CONTROL);
-	htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
-	pci_write_config32(device, HT_INIT_CONTROL, htic);
+	pci_set32(device, HT_INIT_CONTROL, HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect);
 }
 
 static void set_bios_reset(void)
 {
 	u32 htic;
-	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
-	htic &= ~HTIC_BIOSR_Detect;
-	pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+	pci_clear32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, HTIC_BIOSR_Detect);
 }
 
 static unsigned node_link_to_bus(unsigned node, unsigned link)
--- src/northbridge/amd/amdk8/raminit.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-254824-raminit.c	2010-10-05 03:02:21.308443845 +0200
@@ -1833,9 +1833,7 @@ static int update_dimm_ecc(const struct 
 		return -1;
 	}
 	if (value != 2) {
-		dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-		dcl &= ~DCL_DimmEccEn;
-		pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+		pci_clear32(ctrl->f2, DRAM_CONFIG_LOW, DCL_DimmEccEn);
 	}
 	return 1;
 }
@@ -2249,9 +2247,7 @@ static void sdram_enable(int controllers
 		else {
 			/* Disable dram receivers */
 			uint32_t dcl;
-			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
-			dcl |= DCL_DisInRcvrs;
-			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+			pci_set32(ctrl[i].f2, DRAM_CONFIG_LOW, DCL_DisInRcvrs);
 		}
 	}
 
--- src/northbridge/amd/amdk8/incoherent_ht.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-bc211a-incoherent_ht.c	2010-10-05 03:02:25.092449188 +0200
@@ -116,9 +116,7 @@ static void ht_collapse_previous_enumera
 		}
 
 		/* Clear the unitid */
-		flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
-		flags &= ~0x1f;
-		pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
+		pci_clear16(dev, pos + PCI_CAP_FLAGS, 0x1f);
 	}
 }
 
--- src/northbridge/amd/amdk8/coherent_ht.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-36d3bc-coherent_ht.c	2010-10-05 03:02:26.300443882 +0200
@@ -147,11 +147,7 @@ static void disable_probes(void)
 
 	print_spew("Disabling read/write/fill probes for UP... ");
 
-	val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
-	val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
-		HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P |
-		HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
-	pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
+	pci_set32(NODE_HT(0), HT_TRANSACTION_CONTROL, HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C | HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P);
 
 	print_spew("done.\n");
 
@@ -202,9 +198,7 @@ static void enable_routing(u8 node)
 	print_spew("Enabling routing table for node ");
 	print_spew_hex8(node);
 
-	val=pci_read_config32(NODE_HT(node), 0x6c);
-	val &= ~((1<<1)|(1<<0));
-	pci_write_config32(NODE_HT(node), 0x6c, val);
+	pci_clear32(NODE_HT(node), 0x6c, ((1 << 1) | (1 << 0)));
 
 	print_spew(" done.\n");
 }
--- src/northbridge/amd/amdk8/exit_from_self.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-fcca79-exit_from_self.c	2010-10-05 03:02:28.248444280 +0200
@@ -75,12 +75,7 @@ void exit_from_self(int controllers, con
 		printk(BIOS_DEBUG, "before exit errata - timer enabled\n");
 
 		if (is_post_rev_g) {
-			dcl =
-			    pci_read_config32(ctrl[i].f2,
-					      DRAM_TIMING_HIGH);
-			dcl |= (1 << 18);
-			pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH,
-					   dcl);
+			pci_set32(ctrl[i].f2, DRAM_TIMING_HIGH, (1 << 18));
 		}
 
 		dcl = DI_EnDramInit;
@@ -90,17 +85,10 @@ void exit_from_self(int controllers, con
 
 		printk(BIOS_DEBUG, "before exit errata - after mdelay\n");
 
-		dcl = pci_read_config32(ctrl[i].f2, DRAM_INIT);
-		dcl &= ~DI_EnDramInit;
-		pci_write_config32(ctrl[i].f2, DRAM_INIT, dcl);
+		pci_clear32(ctrl[i].f2, DRAM_INIT, DI_EnDramInit);
 
 		if (is_post_rev_g) {
-			dcl =
-			    pci_read_config32(ctrl[i].f2,
-					      DRAM_TIMING_HIGH);
-			dcl &= ~(1 << 18);
-			pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH,
-					   dcl);
+			pci_clear32(ctrl[i].f2, DRAM_TIMING_HIGH, (1 << 18));
 		}
 
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_BANK_ADDR_MAP);
--- src/northbridge/amd/amdk8/misc_control.c	2010-10-05 01:05:54.000000000 +0200
+++ /tmp/cocci-output-5159-2e0206-misc_control.c	2010-10-05 03:02:28.568443933 +0200
@@ -118,22 +118,15 @@ static void misc_control_init(struct dev
 	/* Disable Machine checks from Invalid Locations.
 	 * This is needed for PC backwards compatibility.
 	 */
-	cmd = pci_read_config32(dev, 0x44);
-	cmd |= (1<<6) | (1<<25);
-	pci_write_config32(dev, 0x44, cmd );
+	pci_set32(dev, 0x44, (1 << 6) | (1 << 25));
 #if CONFIG_K8_REV_F_SUPPORT == 0
 	if (is_cpu_pre_c0()) {
 
 		/* Errata 58
 		 * Disable CPU low power states C2, C1 and throttling
 		 */
-		cmd = pci_read_config32(dev, 0x80);
-		cmd &= ~(1<<0);
-		pci_write_config32(dev, 0x80, cmd );
-		cmd = pci_read_config32(dev, 0x84);
-		cmd &= ~(1<<24);
-		cmd &= ~(1<<8);
-		pci_write_config32(dev, 0x84, cmd );
+		pci_clear32(dev, 0x80, (1 << 0));
+		pci_clear32(dev, 0x84, ((1 << 24) | (1 << 8)));
 
 		/* Errata 66
 		 * Limit the number of downstream posted requests to 1
--- src/northbridge/amd/amdfam10/reset_test.c	2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-6362c6-reset_test.c	2010-10-05 03:02:28.920445071 +0200
@@ -95,9 +95,7 @@ static void set_bios_reset(void)
 
 	for(i = 0; i < nodes; i++) {
 		dev = NODE_PCI(i,0);
-		htic = pci_read_config32(dev, HT_INIT_CONTROL);
-		htic &= ~HTIC_BIOSR_Detect;
-		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+		pci_clear32(dev, HT_INIT_CONTROL, HTIC_BIOSR_Detect);
 	}
 }
 
--- src/northbridge/amd/amdfam10/misc_control.c	2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-52a7ca-misc_control.c	2010-10-05 03:02:29.236444958 +0200
@@ -130,9 +130,7 @@ static void misc_control_init(struct dev
 	/* Disable Machine checks from Invalid Locations.
 	 * This is needed for PC backwards compatibility.
 	 */
-	cmd = pci_read_config32(dev, 0x44);
-	cmd |= (1<<6) | (1<<25);
-	pci_write_config32(dev, 0x44, cmd );
+	pci_set32(dev, 0x44, (1 << 6) | (1 << 25));
 
 	printk(BIOS_DEBUG, "done.\n");
 }
--- src/northbridge/via/cn400/agp.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-673e7f-agp.c	2010-10-05 03:02:29.504446503 +0200
@@ -87,9 +87,7 @@ static void agp_init(device_t dev)
 	pci_write_config8(dev, 0xc2, 0x40);
 
 	/* Enable CPU/PMSTR GART Access and DBI function. */
-	reg32 = pci_read_config8(dev, 0xbf);
-	reg32 |= 0x8c;
-	pci_write_config8(dev, 0xbf, reg32);
+	pci_set8(dev, 0xbf, 0x8c);
 
 	/* Enable AGP Aperture. */
 	pci_write_config32(dev, 0x90, 0x0180);
--- src/northbridge/via/cn400/raminit.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-99fde2-raminit.c	2010-10-05 03:02:29.856443993 +0200
@@ -137,9 +137,7 @@ static void c3_cpu_setup(device_t dev)
 	pci_write_config8(dev, 0x57, 0x69);
 
 	/* CPU Host Bus Final Setup */
-	reg8 = pci_read_config8(dev, 0x54);
-	reg8 |= 0x08;
-	pci_write_config8(dev, 0x54, reg8);
+	pci_set8(dev, 0x54, 0x08);
 
 }
 
@@ -550,9 +548,7 @@ static void ddr_ram_setup(void)
 			Don't change Frequency from power up defaults
 			This seems to lockup the RAM interface
 		*/
-		c = pci_read_config8(ctrl.d0f2, 0x54);
-		c |= 0x10;
-		pci_write_config8(ctrl.d0f2, 0x54, c);
+		pci_set8(ctrl.d0f2, 0x54, 0x10);
 		i = 0x008; 		// Used later to set SDRAM MSR
 	}
 
--- src/northbridge/via/cn400/northbridge.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-41cea7-northbridge.c	2010-10-05 03:02:30.632444027 +0200
@@ -92,22 +92,16 @@ static void memctrl_init(device_t dev)
 	pci_write_config8(dev, 0x81, paged);
 	pci_write_config8(dev, 0x83, pagee);
 	/* PAGE F are read/writable */
-	shadowreg = pci_read_config8(dev, 0x82);
-	shadowreg |= pagef;
-	pci_write_config8(dev, 0x82, shadowreg);
+	pci_set8(dev, 0x82, pagef);
 		pci_write_config8(vlink_dev, 0x61, pagec);
 		pci_write_config8(vlink_dev, 0x62, paged);
 		pci_write_config8(vlink_dev, 0x64, pagee);
 
-		shadowreg = pci_read_config8(vlink_dev, 0x63);
-		shadowreg |= pagef;
-		pci_write_config8(vlink_dev, 0x63, shadowreg);
+		pci_set8(vlink_dev, 0x63, pagef);
 
 	/* Activate VGA Frame Buffer */
 
-	reg8 = pci_read_config8(dev, 0xA0);
-	reg8 |= 0x01;
-	pci_write_config8(dev, 0xA0, reg8);
+	pci_set8(dev, 0xA0, 0x01);
 
 #ifdef DEBUG_CN400
 	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
--- src/northbridge/via/cn400/vlink.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-f98929-vlink.c	2010-10-05 03:02:31.132443968 +0200
@@ -46,9 +46,7 @@ static void vlink_init(device_t dev)
 	printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
 
 	/* Disconnect the VLink Before Changing Settings */
-	reg = pci_read_config8(dev, 0x47);
-	reg |= 0x04;
-	pci_write_config8(dev, 0x47, reg);
+	pci_set8(dev, 0x47, 0x04);
 
 	/* Wait for anything pending to flush */
 	noop_1k(20);
@@ -85,27 +83,21 @@ static void vlink_init(device_t dev)
 	/* V-Link NB Compensation Control */
 	pci_write_config8(dev, 0xB5, 0x46);
 	pci_write_config8(dev, 0xB6, 0x68);
-	reg = pci_read_config8(dev, 0xB4);
-	reg |= 0x01;
-	pci_write_config8(dev, 0xB4, reg);
+	pci_set8(dev, 0xB4, 0x01);
 
 	/* V-Link NB Receive Strobe Delay */
 	pci_write_config8(dev, 0xB7, 0x02);
 
 	/* V-Link SB Compensation Control */
 	pci_write_config8(dev, 0xB9, 0x84);
-	reg = pci_read_config8(dev, 0xB8);
-	reg |= 0x01;
-	pci_write_config8(dev, 0xB8, reg);
+	pci_set8(dev, 0xB8, 0x01);
 
 	pci_write_config8(dev, 0xBA, 0x6a);
 	pci_write_config8(dev, 0xBB, 0x01);
 
 #ifdef DEBUG_CN400
 	/* Reconnect the VLink Before Continuing*/
-	reg = pci_read_config8(dev, 0x47);
-	reg &= ~0x04;
-	pci_write_config8(dev, 0x47, reg);
+	pci_clear8(dev, 0x47, 0x04);
 
 	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
--- src/northbridge/via/cn700/agp.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-2b9eca-agp.c	2010-10-05 03:02:31.588443867 +0200
@@ -76,9 +76,7 @@ static void agp_init(device_t dev)
 	pci_write_config32(dev, 0x10, 0xf8000008);
 
 	/* Enable CPU/PMSTR GART Access. */
-	reg32 = pci_read_config8(dev, 0xbf);
-	reg32 |= 0x80;
-	pci_write_config8(dev, 0xbf, reg32);
+	pci_set8(dev, 0xbf, 0x80);
 
 	/* Enable AGP Aperture. */
 	reg32 = pci_read_config32(dev, 0x94);
--- src/northbridge/via/cn700/northbridge.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-4d0cbc-northbridge.c	2010-10-05 03:02:31.940443851 +0200
@@ -69,9 +69,7 @@ static void memctrl_init(device_t dev)
 	pci_write_config8(dev, 0x81, paged);
 	pci_write_config8(dev, 0x82, pagee);
 	/* PAGE F are read/writable */
-	shadowreg = pci_read_config8(dev, 0x83);
-	shadowreg |= pagef;
-	pci_write_config8(dev, 0x83, shadowreg);
+	pci_set8(dev, 0x83, pagef);
 	/* vlink mirror */
 	vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
 				    PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
@@ -80,9 +78,7 @@ static void memctrl_init(device_t dev)
 		pci_write_config8(vlink_dev, 0x62, paged);
 		pci_write_config8(vlink_dev, 0x64, pagee);
 
-		shadowreg = pci_read_config8(vlink_dev, 0x63);
-		shadowreg |= pagef;
-		pci_write_config8(vlink_dev, 0x63, shadowreg);
+		pci_set8(vlink_dev, 0x63, pagef);
 	}
 }
 
--- src/northbridge/via/cx700/cx700_sata.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-c55eec-cx700_sata.c	2010-10-05 03:02:32.400443929 +0200
@@ -77,9 +77,7 @@ static void sata_init(struct device *dev
 	pci_write_config8(dev, 0x6b, reg8);
 
 	/* Enable EIDE (secondary channel) even if SATA disabled */
-	reg8 = pci_read_config8(dev, 0xc0);
-	reg8 |= 0x1;
-	pci_write_config8(dev, 0xc0, reg8);
+	pci_set8(dev, 0xc0, 0x1);
 
 	// Enable bus mastering, memory space acces, io space access
 	pci_write_config16(dev, 0x04, 0x0007);
@@ -95,9 +93,7 @@ static void sata_init(struct device *dev
 	pci_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
 
 	/* Enable read/write prefetch buffers */
-	reg8 = pci_read_config8(dev, 0xc1);
-	reg8 |= 0x30;
-	pci_write_config8(dev, 0xc1, reg8);
+	pci_set8(dev, 0xc1, 0x30);
 
 	/* Set FIFO thresholds like */
 	pci_write_config8(dev, 0xc3, 0x1);	/* FIFO flushed when 1/2 full */
@@ -111,16 +107,12 @@ static void sata_init(struct device *dev
 	pci_write_config8(dev, 0x46, 0x8);
 
 	/* EIDE Configuration */
-	reg8 = pci_read_config8(dev, 0xc4);
-	reg8 |= 0x10;
-	pci_write_config8(dev, 0xc4, reg8);
+	pci_set8(dev, 0xc4, 0x10);
 
 	pci_write_config8(dev, 0xc5, 0xc);
 
 	/* Interrupt Line */
-	reg8 = pci_read_config8(dev, 0x45);
-	reg8 &= ~(1 << 4);	/* Interrupt Line Write Protect off */
-	pci_write_config8(dev, 0x45, reg8);
+	pci_clear8(dev, 0x45, (1 << 4));
 
 	pci_write_config8(dev, 0x3c, 0x0e);	/* Interrupt */
 
@@ -128,9 +120,7 @@ static void sata_init(struct device *dev
 	pci_write_config16(dev, 0x48, 0x5d5d);
 
 	/* Enable only compatibility mode. */
-	reg8 = pci_read_config8(dev, 0x42);
-	reg8 &= ~0xa0;
-	pci_write_config8(dev, 0x42, reg8);
+	pci_clear8(dev, 0x42, 0xa0);
 	reg8 = pci_read_config8(dev, 0x42);
 	printk(BIOS_DEBUG, "Reg 0x42 read back as 0x%x\n", reg8);
 
--- src/northbridge/via/cx700/raminit.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-fc4080-raminit.c	2010-10-05 03:02:32.788443855 +0200
@@ -456,9 +456,7 @@ static void sdram_set_safe_values(const 
 	 * This is a necessary sequence.
 	 */
 	udelay(2000);
-	regs = pci_read_config8(MEMCTRL, 0x90);
-	regs |= 0x7;
-	pci_write_config8(MEMCTRL, 0x90, regs);
+	pci_set8(MEMCTRL, 0x90, 0x7);
 	udelay(2000);
 	regs = pci_read_config8(MEMCTRL, 0x90);
 	regs &= ~0x7;
@@ -475,9 +473,7 @@ static void sdram_set_safe_values(const 
 	udelay(1);
 	regs &= ~0xc0;
 	pci_write_config8(MEMCTRL, 0x6b, regs);
-	regs = pci_read_config8(MEMCTRL, 0x6f);
-	regs |= 0x1;
-	pci_write_config8(MEMCTRL, 0x6f, regs);
+	pci_set8(MEMCTRL, 0x6f, 0x1);
 
 	/**********************************************/
 	/*      Set DRAM Timing Setting (DDR2 533)    */
@@ -671,9 +667,7 @@ static void sdram_set_safe_values(const 
 		pci_write_config8(HOSTCTRL, Host_Reg_Val[val], Host_Reg_Val[val + 1]);
 
 	/* F2_RX51[7]=0, disable DRDY timing */
-	regs = pci_read_config8(HOSTCTRL, 0x51);
-	regs &= ~0x80;
-	pci_write_config8(HOSTCTRL, 0x51, regs);
+	pci_clear8(HOSTCTRL, 0x51, 0x80);
 
 	/**********************************************/
 	/*           Set DRAM BurstLength             */
@@ -899,9 +893,7 @@ static void sdram_set_safe_values(const 
 	val |= t;
 	pci_write_config8(HOSTCTRL, 0x57, val);
 
-	regs = pci_read_config8(HOSTCTRL, 0x51);
-	regs |= t;
-	pci_write_config8(HOSTCTRL, 0x51, regs);
+	pci_set8(HOSTCTRL, 0x51, t);
 
 	regs = pci_read_config8(MEMCTRL, 0x90);
 	regs &= 0x7;
@@ -913,9 +905,7 @@ static void sdram_set_safe_values(const 
 	regs |= val;
 	pci_write_config8(MEMCTRL, 0x76, regs);
 
-	regs = pci_read_config8(MEMCTRL, 0x6f);
-	regs |= 0x10;
-	pci_write_config8(MEMCTRL, 0x6f, regs);
+	pci_set8(MEMCTRL, 0x6f, 0x10);
 
 	/***************************************************/
 	/*    Find suitable DQS value for ChA and ChB      */
@@ -983,9 +973,7 @@ static void step_2_19(const struct mem_c
 	u8 val;
 
 	//  Step 2
-	val = pci_read_config8(MEMCTRL, 0x69);
-	val &= ~0x03;
-	pci_write_config8(MEMCTRL, 0x69, val);
+	pci_clear8(MEMCTRL, 0x69, 0x03);
 
 	/* Step 3 Apply NOP. */
 	print_spew("RAM Enable 1: Apply NOP\n");
@@ -1445,9 +1433,7 @@ static void sdram_enable(const struct me
 	reg8 &= 0x11;
 	pci_write_config8(MEMCTRL, 0x50, reg8);
 	pci_write_config8(MEMCTRL, 0x51, reg8);
-	reg8 = pci_read_config8(MEMCTRL, 0x6b);
-	reg8 &= ~0x08;
-	pci_write_config8(MEMCTRL, 0x6b, reg8);
+	pci_clear8(MEMCTRL, 0x6b, 0x08);
 
 	/****************************************************************/
 	/*             DRAM re-initialize for burst length              */
@@ -1474,9 +1460,7 @@ static void sdram_enable(const struct me
 	reg8 &= 0x11;
 	pci_write_config8(MEMCTRL, 0x51, reg8);
 
-	reg8 = pci_read_config8(MEMCTRL, 0x6b);
-	reg8 &= ~0x08;
-	pci_write_config8(MEMCTRL, 0x6b, reg8);
+	pci_clear8(MEMCTRL, 0x6b, 0x08);
 
 	for (i = 0; i < 4; i += 2) {
 		reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
@@ -1609,13 +1593,9 @@ static void sdram_enable(const struct me
 	outl(0x80000188, 0xcf8);
 	outb(0xcf, 0xcfc);
 
-	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xa5);
-	reg8 |= 0x10;
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xa5, reg8);
+	pci_set8(PCI_DEV(0, 0, 0), 0xa5, 0x10);
 
-	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0x91);
-	reg8 |= 0x20;
-	pci_write_config8(PCI_DEV(0, 0, 0), 0x91, reg8);
+	pci_set8(PCI_DEV(0, 0, 0), 0x91, 0x20);
 #endif
 
 	static const struct regmask {
--- src/northbridge/via/cx700/cx700_agp.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-a74494-cx700_agp.c	2010-10-05 03:02:35.760445670 +0200
@@ -36,18 +36,14 @@ static void agp_bridge_init(device_t dev
 
 	pci_write_config8(north_dev, 0xa2, 0x4a);
 
-	reg8 = pci_read_config8(north_dev, 0xc0);
-	reg8 |= 0x1;
-	pci_write_config8(north_dev, 0xc0, reg8);
+	pci_set8(north_dev, 0xc0, 0x1);
 
 	/*
 	 * Since Internal Graphic already set to AGP3.0 compatible in its Capability Pointer
 	 * We must set RAGP8X=1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b
 	 */
 	north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x0324, 0);
-	reg8 = pci_read_config8(north_dev, 0xb5);
-	reg8 |= 0x3;
-	pci_write_config8(north_dev, 0xb5, reg8);
+	pci_set8(north_dev, 0xb5, 0x3);
 	pci_write_config8(north_dev, 0x94, 0x20);
 	pci_write_config8(north_dev, 0x13, 0xd0);
 
--- src/northbridge/via/cx700/cx700_lpc.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-d9291b-cx700_lpc.c	2010-10-05 03:02:36.060447035 +0200
@@ -172,9 +172,7 @@ static void cx700_set_lpc_registers(stru
 	printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n");
 
 	// enable the internal I/O decode
-	enables = pci_read_config8(dev, 0x6C);
-	enables |= 0x80;
-	pci_write_config8(dev, 0x6C, enables);
+	pci_set8(dev, 0x6C, 0x80);
 
 	// Map 4MB of FLASH into the address space
 //      pci_write_config8(dev, 0x41, 0x7f);
@@ -182,14 +180,10 @@ static void cx700_set_lpc_registers(stru
 	// Set bit 6 of 0x40, because Award does it (IO recovery time)
 	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
 	// interrupts can be properly marked as level triggered.
-	enables = pci_read_config8(dev, 0x40);
-	enables |= 0x44;
-	pci_write_config8(dev, 0x40, enables);
+	pci_set8(dev, 0x40, 0x44);
 
 	/* DMA Line buffer control */
-	enables = pci_read_config8(dev, 0x42);
-	enables |= 0xf0;
-	pci_write_config8(dev, 0x42, enables);
+	pci_set8(dev, 0x42, 0xf0);
 
 	/* I/O recovery time */
 	pci_write_config8(dev, 0x4c, 0x44);
@@ -204,17 +198,11 @@ static void cx700_set_lpc_registers(stru
 	pci_write_config8(dev, 0x48, 0x0c);
 
 	/* Set SM Misc Control: Enable Internal APIC . */
-	enables = pci_read_config8(dev, 0x58);
-	enables |= 1 << 6;
-	pci_write_config8(dev, 0x58, enables);
-	enables = pci_read_config8(dev, 0x4d);
-	enables |= 1 << 3;
-	pci_write_config8(dev, 0x4d, enables);
+	pci_set8(dev, 0x58, 1 << 6);
+	pci_set8(dev, 0x4d, 1 << 3);
 
 	/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
-	enables = pci_read_config8(dev, 0x4f);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4f, enables);
+	pci_set8(dev, 0x4f, 0x08);
 
 	/* enable KBC configuration */
 	pci_write_config8(dev, 0x51, 0x1f);
--- src/northbridge/via/cx700/cx700_usb.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-254bad-cx700_usb.c	2010-10-05 03:02:36.544451651 +0200
@@ -33,9 +33,7 @@ static void usb_init(struct device *dev)
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
 
-	reg8 = pci_read_config8(dev, 0xca);
-	reg8 |= (1 << 0);
-	pci_write_config8(dev, 0xca, reg8);
+	pci_set8(dev, 0xca, (1 << 0));
 
 	printk(BIOS_DEBUG, "done.\n");
 }
--- src/northbridge/via/vx800/driving_setting.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-853091-driving_setting.c	2010-10-05 03:02:36.769444168 +0200
@@ -218,9 +218,7 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr
 			Data |= 0x30;
 			pci_write_config8(MEMCTRL, 0xD4, Data);
 
-			Data = pci_read_config8(MEMCTRL, 0x9e);
-			Data |= 0x01;
-			pci_write_config8(MEMCTRL, 0x9e, Data);
+			pci_set8(MEMCTRL, 0x9e, 0x01);
 		}
 
 	}
@@ -261,14 +259,10 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr
 		pci_write_config8(MEMCTRL, 0xD4, Data);
 
 		//enable CHB differential DQS input
-		Data = pci_read_config8(MEMCTRL, 0x9E);
-		Data |= 0x02;
-		pci_write_config8(MEMCTRL, 0x9E, Data);
+		pci_set8(MEMCTRL, 0x9E, 0x02);
 	}
 	//enable ODT Control
-	Data = pci_read_config8(MEMCTRL, 0x9e);
-	Data |= 0x80;
-	pci_write_config8(MEMCTRL, 0x9e, Data);
+	pci_set8(MEMCTRL, 0x9e, 0x80);
 }
 
 void DrivingDQS(DRAM_SYS_ATTR * DramAttr)
--- src/northbridge/via/vx800/uma_ram_setting.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-cf52e9-uma_ram_setting.c	2010-10-05 03:02:37.265443981 +0200
@@ -81,9 +81,7 @@ void SetUMARam(void)
 	SLD1F0Val = 0;
 	VgaPortVal = 0;
 
-	ByteVal = pci_read_config8(MEMCTRL, 0xa1);
-	ByteVal |= 0x80;
-	pci_write_config8(MEMCTRL, 0xa1, ByteVal);
+	pci_set8(MEMCTRL, 0xa1, 0x80);
 
 	//set VGA Timer
 	pci_write_config8(MEMCTRL, 0xa2, 0xee);
@@ -179,15 +177,10 @@ void SetUMARam(void)
 	pci_write_config8(PCI_DEV(0, 0, 3), 0xa0, 0x01);
 
 	//enable GFx memory space access control for S.L and mmio
-	ByteVal = pci_read_config8(d0f0_dev, 0xD4);
-	ByteVal |= 0x03;
-	//ByteVal |= 0x01;
-	pci_write_config8(d0f0_dev, 0xD4, ByteVal);
+	pci_set8(d0f0_dev, 0xD4, 0x03);
 
 	//enable Base VGA 16 Bits Decode
-	ByteVal = pci_read_config8(d0f0_dev, 0xfe);
-	ByteVal |= 0x10;
-	pci_write_config8(d0f0_dev, 0xfe, ByteVal);
+	pci_set8(d0f0_dev, 0xfe, 0x10);
 
 	//disable CHB L.L
 	//set VGA memory selection
--- src/northbridge/via/vx800/examples/romstage.c	2010-10-01 20:34:21.000000000 +0200
+++ /tmp/cocci-output-5159-cf82b2-romstage.c	2010-10-05 03:02:38.057447117 +0200
@@ -98,9 +98,7 @@ static void enable_shadow_ram(void)
 	uint8_t shadowreg;
 	pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
 	/* 0xf0000-0xfffff - ACPI tables */
-	shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
-	shadowreg |= 0x30;
-	pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
+	pci_set8(PCI_DEV(0, 0, 3), 0x83, 0x30);
 	/* 0xe0000-0xeffff - elfload? */
 
 	pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff);
--- src/northbridge/via/vx800/dev_init.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-b972cf-dev_init.c	2010-10-05 03:02:38.677443869 +0200
@@ -360,9 +360,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr
 
 	/* Step 2 */
 	/* Disable bank paging and multi page. */
-	Data = pci_read_config8(MEMCTRL, 0x69);
-	Data &= ~0x03;
-	pci_write_config8(MEMCTRL, 0x69, Data);
+	pci_clear8(MEMCTRL, 0x69, 0x03);
 
 	Reg6BVal = pci_read_config8(MEMCTRL, 0x6b);
 	Reg6BVal &= ~0x07;
@@ -515,9 +513,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr
 	pci_write_config8(MEMCTRL, 0x6b, Data);
 
 	/* Enable bank paging and multi page. */
-	Data = pci_read_config8(MEMCTRL, 0x69);
-	Data |= 0x03;
-	pci_write_config8(MEMCTRL, 0x69, Data);
+	pci_set8(MEMCTRL, 0x69, 0x03);
 }
 
 /*===================================================================
@@ -900,9 +896,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
 	 * Step 4. Enable the initialization mode of DRAM Controller C with
 	 * NB's PLL clock.
 	 */
-	Data = pci_read_config8(MEMCTRL, 0xdb);
-	Data |= 0x60;
-	pci_write_config8(MEMCTRL, 0xdb, Data);
+	pci_set8(MEMCTRL, 0xdb, 0x60);
 
 	/* Step 5. NOP command enable. */
 	Data = pci_read_config8(MEMCTRL, 0xdb);
@@ -911,9 +905,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
 	pci_write_config8(MEMCTRL, 0xdb, Data);
 
 	/* Step 6. Issue a nop cycle, RegDB[1] 0 -> 1. */
-	Data = pci_read_config8(MEMCTRL, 0xdb);
-	Data |= 0x2;
-	pci_write_config8(MEMCTRL, 0xdb, Data);
+	pci_set8(MEMCTRL, 0xdb, 0x2);
 	Data &= 0xFD;
 	pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -940,9 +932,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
 	pci_write_config8(MEMCTRL, 0xf9, Data);
 
 	/* step 9. Issue a precharge all cycle, RegD3[7] 0 -> 1. */
-	Data = pci_read_config8(MEMCTRL, 0xdb);
-	Data |= 0x2;
-	pci_write_config8(MEMCTRL, 0xdb, Data);
+	pci_set8(MEMCTRL, 0xdb, 0x2);
 	Data &= 0xFD;
 	pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -960,9 +950,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
 	pci_write_config8(MEMCTRL, 0xf9, Data);
 
 	/* Step 12. Issue EMRS cycle. */
-	Data = pci_read_config8(MEMCTRL, 0xdb);
-	Data |= 0x2;
-	pci_write_config8(MEMCTRL, 0xdb, Data);
+	pci_set8(MEMCTRL, 0xdb, 0x2);
 	Data &= 0xFD;
 	pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -980,9 +968,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
 	pci_write_config8(MEMCTRL, 0xf9, Data);
 
 	/* Step 15. Issue MRS cycle. */
-	Data = pci_read_config8(MEMCTRL, 0xdb);
-	Data |= 0x2;
-	pci_write_config8(MEMCTRL, 0xdb, Data);
+	pci_set8(MEMCTRL, 0xdb, 0x2);
 	Data &= 0xFD;
 	pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1000,9 +986,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
 	pci_write_config8(MEMCTRL, 0xf9, Data);
 
 	/* Step 17. Issue precharge all cycle. */
-	Data = pci_read_config8(MEMCTRL, 0xdb);
-	Data |= 0x2;
-	pci_write_config8(MEMCTRL, 0xdb, Data);
+	pci_set8(MEMCTRL, 0xdb, 0x2);
 	Data &= 0xFD;
 	pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1022,9 +1006,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
 	//repeat issue 8 CBR cycle, between each cycle stop 100us
 	for (Idx = 0; Idx < 8; Idx++) {
 		// issue CBR cycle
-		Data = pci_read_config8(MEMCTRL, 0xdb);
-		Data |= 0x2;
-		pci_write_config8(MEMCTRL, 0xdb, Data);
+		pci_set8(MEMCTRL, 0xdb, 0x2);
 		Data &= 0xFD;
 		pci_write_config8(MEMCTRL, 0xdb, Data);
 		WaitMicroSec(100);
@@ -1059,9 +1041,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
 	pci_write_config8(MEMCTRL, 0xf9, Data);
 
 	//step 24.  issue MRS cycle
-	Data = pci_read_config8(MEMCTRL, 0xdb);
-	Data |= 0x2;
-	pci_write_config8(MEMCTRL, 0xdb, Data);
+	pci_set8(MEMCTRL, 0xdb, 0x2);
 	Data &= 0xFD;
 	pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1079,9 +1059,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
 	pci_write_config8(MEMCTRL, 0xf9, Data);
 
 	//step 27.  issue EMRS cycle
-	Data = pci_read_config8(MEMCTRL, 0xdb);
-	Data |= 0x2;
-	pci_write_config8(MEMCTRL, 0xdb, Data);
+	pci_set8(MEMCTRL, 0xdb, 0x2);
 	Data &= 0xFD;
 	pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1093,9 +1071,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr
 	pci_write_config8(MEMCTRL, 0xf9, Data);
 
 	//step 29. issue EMRS cycle
-	Data = pci_read_config8(MEMCTRL, 0xdb);
-	Data |= 0x2;
-	pci_write_config8(MEMCTRL, 0xdb, Data);
+	pci_set8(MEMCTRL, 0xdb, 0x2);
 	Data &= 0xFD;
 	pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1141,9 +1117,7 @@ CB_STATUS VerifyChc(void)
 		pci_write_config8(MEMCTRL, 0xf9, Data);
 
 		/* Issue active cycle. */
-		Data = pci_read_config8(MEMCTRL, 0xdb);
-		Data |= 0x2;
-		pci_write_config8(MEMCTRL, 0xdb, Data);
+		pci_set8(MEMCTRL, 0xdb, 0x2);
 		Data &= 0xFD;
 		pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1161,9 +1135,7 @@ CB_STATUS VerifyChc(void)
 		pci_write_config8(MEMCTRL, 0xf9, Data);
 
 		/* Issue read/completion cycle. */
-		Data = pci_read_config8(MEMCTRL, 0xdb);
-		Data |= 0x2;
-		pci_write_config8(MEMCTRL, 0xdb, Data);
+		pci_set8(MEMCTRL, 0xdb, 0x2);
 		Data &= 0xFD;
 		pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1181,9 +1153,7 @@ CB_STATUS VerifyChc(void)
 		pci_write_config8(MEMCTRL, 0xf9, Data);
 
 		/* Issue write cycle. */
-		Data = pci_read_config8(MEMCTRL, 0xdb);
-		Data |= 0x2;
-		pci_write_config8(MEMCTRL, 0xdb, Data);
+		pci_set8(MEMCTRL, 0xdb, 0x2);
 		Data &= 0xFD;
 		pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1201,9 +1171,7 @@ CB_STATUS VerifyChc(void)
 		pci_write_config8(MEMCTRL, 0xf9, Data);
 
 		/* Issue read/completion cycle. */
-		Data = pci_read_config8(MEMCTRL, 0xdb);
-		Data |= 0x2;
-		pci_write_config8(MEMCTRL, 0xdb, Data);
+		pci_set8(MEMCTRL, 0xdb, 0x2);
 		Data &= 0xFD;
 		pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1221,9 +1189,7 @@ CB_STATUS VerifyChc(void)
 		pci_write_config8(MEMCTRL, 0xf9, Data);
 
 		//  issue active cycle
-		Data = pci_read_config8(MEMCTRL, 0xdb);
-		Data |= 0x2;
-		pci_write_config8(MEMCTRL, 0xdb, Data);
+		pci_set8(MEMCTRL, 0xdb, 0x2);
 		Data &= 0xFD;
 		pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1241,9 +1207,7 @@ CB_STATUS VerifyChc(void)
 		pci_write_config8(MEMCTRL, 0xf9, Data);
 
 		//  issue read/completion cycle
-		Data = pci_read_config8(MEMCTRL, 0xdb);
-		Data |= 0x2;
-		pci_write_config8(MEMCTRL, 0xdb, Data);
+		pci_set8(MEMCTRL, 0xdb, 0x2);
 		Data &= 0xFD;
 		pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1261,9 +1225,7 @@ CB_STATUS VerifyChc(void)
 		pci_write_config8(MEMCTRL, 0xf9, Data);
 
 		//  issue read cycle
-		Data = pci_read_config8(MEMCTRL, 0xdb);
-		Data |= 0x2;
-		pci_write_config8(MEMCTRL, 0xdb, Data);
+		pci_set8(MEMCTRL, 0xdb, 0x2);
 		Data &= 0xFD;
 		pci_write_config8(MEMCTRL, 0xdb, Data);
 
@@ -1281,9 +1243,7 @@ CB_STATUS VerifyChc(void)
 		pci_write_config8(MEMCTRL, 0xf9, Data);
 
 		/* Issue read/completion cycle. */
-		Data = pci_read_config8(MEMCTRL, 0xdb);
-		Data |= 0x2;
-		pci_write_config8(MEMCTRL, 0xdb, Data);
+		pci_set8(MEMCTRL, 0xdb, 0x2);
 		Data &= 0xFD;
 		pci_write_config8(MEMCTRL, 0xdb, Data);
 
--- src/northbridge/via/vx800/rank_map.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-86195f-rank_map.c	2010-10-05 03:02:39.729452751 +0200
@@ -172,9 +172,7 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * 
 
 	//must set BA2 enable if any 8-bank device exists
 	if (HasThreeBitBA) {
-		Data = pci_read_config8(MEMCTRL, 0x53);
-		Data |= 0x80;
-		pci_write_config8(MEMCTRL, 0x53, Data);
+		pci_set8(MEMCTRL, 0x53, 0x80);
 	}
 #if 1
 	for (RankIndex = 0; DramAttr->RankSize[RankIndex] != 0; RankIndex++) {
@@ -213,9 +211,7 @@ void DRAMSetRankMAType(DRAM_SYS_ATTR * D
 	Data &= 0x1;
 	pci_write_config8(MEMCTRL, 0x50, Data);
 	// disable MA32/16 MA33/17 swap   in memory init it has this Reg fill
-	Data = pci_read_config8(MEMCTRL, 0x6b);
-	Data &= ~0x08;
-	pci_write_config8(MEMCTRL, 0x6b, Data);
+	pci_clear8(MEMCTRL, 0x6b, 0x08);
 
 	Data = 0x00;
 	for (SlotNum = 0; SlotNum < MAX_DIMMS; SlotNum++) {
--- src/northbridge/via/vx800/vx800_lpc.c	2010-10-01 09:27:06.000000000 +0200
+++ /tmp/cocci-output-5159-d93d22-vx800_lpc.c	2010-10-05 03:02:40.273459181 +0200
@@ -201,9 +201,7 @@ static void setup_pm(device_t dev)
 static void S3_ps2_kb_ms_wakeup(struct device *dev)
 {
 	u8 enables;
-	enables = pci_read_config8(dev, 0x51);
-	enables |= 2;
-	pci_write_config8(dev, 0x51, enables);
+	pci_set8(dev, 0x51, 2);
 
 	outb(0xe0, 0x2e);
 	outb(0x0b, 0x2f);	//if 09,then only support kb wakeup
@@ -238,9 +236,7 @@ static void vx800_sb_init(struct device 
 	unsigned char enables;
 
 	// enable the internal I/O decode
-	enables = pci_read_config8(dev, 0x6C);
-	enables |= 0x80;
-	pci_write_config8(dev, 0x6C, enables);
+	pci_set8(dev, 0x6C, 0x80);
 
 	// Map 4MB of FLASH into the address space
 //      pci_write_config8(dev, 0x41, 0x7f);
@@ -248,14 +244,10 @@ static void vx800_sb_init(struct device 
 	// Set bit 6 of 0x40, because Award does it (IO recovery time)
 	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
 	// interrupts can be properly marked as level triggered.
-	enables = pci_read_config8(dev, 0x40);
-	enables |= 0x44;
-	pci_write_config8(dev, 0x40, enables);
+	pci_set8(dev, 0x40, 0x44);
 
 	/* DMA Line buffer control */
-	enables = pci_read_config8(dev, 0x42);
-	enables |= 0xf0;
-	pci_write_config8(dev, 0x42, enables);
+	pci_set8(dev, 0x42, 0xf0);
 
 	/* I/O recovery time */
 	pci_write_config8(dev, 0x4c, 0x44);
@@ -265,23 +257,17 @@ static void vx800_sb_init(struct device 
 
 	/* Set 0x5b to 0x01 to match Award */
 	//pci_write_config8(dev, 0x5b, 0x01);
-	enables = pci_read_config8(dev, 0x5b);
-	enables |= 0x01;
-	pci_write_config8(dev, 0x5b, enables);
+	pci_set8(dev, 0x5b, 0x01);
 
 	/* Set Read Pass Write Control Enable */
 	pci_write_config8(dev, 0x48, 0x0c);
 
 	/* Set 0x58 to 0x42 APIC and RTC. */
 	//pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0.
-	enables = pci_read_config8(dev, 0x58);
-	enables |= 0x41;	//
-	pci_write_config8(dev, 0x58, enables);
+	pci_set8(dev, 0x58, 0x41);
 
 	/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
-	enables = pci_read_config8(dev, 0x4f);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4f, enables);
+	pci_set8(dev, 0x4f, 0x08);
 
 	/* enable serial irq */
 	pci_write_config8(dev, 0x52, 0x9);
--- src/northbridge/intel/i855/raminit.c	2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-31e198-raminit.c	2010-10-05 03:02:40.760444095 +0200
@@ -406,9 +406,7 @@ static void set_initialize_complete(cons
 {
 	uint32_t drc_reg;
 
-	drc_reg = pci_read_config32(NORTHBRIDGE_MMC, DRC);
-	drc_reg |= (1 << 29);
-	pci_write_config32(NORTHBRIDGE_MMC, DRC, drc_reg);
+	pci_set32(NORTHBRIDGE_MMC, DRC, (1 << 29));
 }
 
 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
--- src/northbridge/intel/i945/early_init.c	2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-4c8699-early_init.c	2010-10-05 03:02:41.736443862 +0200
@@ -516,9 +516,7 @@ static void i945_setup_pci_express_x16(v
 
 	printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
 
-	reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
-	reg16 |= DEVEN_D1F0;
-	pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
+	pci_set16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0);
 
 	reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x208);
 	reg32 &= ~(1 << 8);
@@ -530,13 +528,9 @@ static void i945_setup_pci_express_x16(v
 	 */
 
 	/* First we reset the secondary bus */
-	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
-	reg16 |= (1 << 6); /* SRESET */
-	pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+	pci_set16(PCI_DEV(0, 0x01, 0), 0x3e, (1 << 6));
 	/* Read back and clear reset bit. */
-	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
-	reg16 &= ~(1 << 6); /* SRESET */
-	pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+	pci_clear16(PCI_DEV(0, 0x01, 0), 0x3e, (1 << 6));
 
 	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
 	printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
@@ -641,14 +635,10 @@ static void i945_setup_pci_express_x16(v
 		pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
 
 		/* DEVEN */
-		reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), 0x54);
-		reg32 &= ~((1 << 3) | (1 << 4));
-		pci_write_config32(PCI_DEV(0, 0x0, 0), 0x54, reg32);
+		pci_clear32(PCI_DEV(0, 0x0, 0), 0x54, ((1 << 3) | (1 << 4)));
 
 		/* Set VGA enable bit in PCIe bridge */
-		reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), 0x3e);
-		reg16 |= (1 << 3);
-		pci_write_config16(PCI_DEV(0, 0x1, 0), 0x3e, reg16);
+		pci_set16(PCI_DEV(0, 0x1, 0), 0x3e, (1 << 3));
 	}
 
 	/* Enable GPEs */
@@ -785,9 +775,7 @@ disable_pciexpress_x16_link:
 		printk(BIOS_DEBUG, "ok\n");
 
 	/* Finally: Disable the PCI config header */
-	reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
-	reg16 &= ~DEVEN_D1F0;
-	pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
+	pci_clear16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0);
 }
 
 static void i945_setup_root_complex_topology(void)
--- src/northbridge/intel/i945/raminit.c	2010-10-01 11:41:29.000000000 +0200
+++ /tmp/cocci-output-5159-515b3c-raminit.c	2010-10-05 03:02:43.012443829 +0200
@@ -254,9 +254,7 @@ static void sdram_detect_errors(struct s
 		}
 
 		/* Set SLP_S3# Assertion Stretch Enable */
-		reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
-		reg8 |= (1 << 3);
-		pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+		pci_set8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 3));
 
 		if (do_reset) {
 			printk(BIOS_DEBUG, "Reset required.\n");
@@ -267,9 +265,7 @@ static void sdram_detect_errors(struct s
 	}
 
 	/* Set DRAM initialization bit in ICH7 */
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
-	reg8 |= (1<<7);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
+	pci_set8(PCI_DEV(0, 0x1f, 0), 0xa2, (1 << 7));
 
 	/* clear self refresh if not wake-up from suspend */
 	if (sysinfo->boot_path != 2) {
@@ -2056,10 +2052,7 @@ static void sdram_program_graphics_frequ
 	}
 	pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
 
-	reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
-
-	reg8 |= (1<<3) | (1<<1);
-	pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
+	pci_set8(PCI_DEV(0, 2, 0), GCFC + 1, (1 << 3) | (1 << 1));
 
 	reg8 |= 0x0f;
 	pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
@@ -2112,9 +2105,7 @@ static void sdram_program_memory_frequen
 	 */
 	goto cache_code;
 vco_update:
-	reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
-	reg8 &= ~(1 << 7);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
+	pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa2, (1 << 7));
 
 	clkcfg &= ~(1 << 10);
 	MCHBAR32(CLKCFG) = clkcfg;
@@ -2581,13 +2572,9 @@ static void sdram_power_management(struc
 		MCHBAR32(FSBPMC4) |= (1 << 4);
 	}
 
-	reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
-	reg8 |= (1 << 4);
-	pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
-
-	reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
-	reg8 |= (1 << 2);
-	pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
+	pci_set8(PCI_DEV(0, 0x0, 0), 0xfc, (1 << 4));
+
+	pci_set8(PCI_DEV(0, 0x2, 0), 0xc1, (1 << 2));
 
 #ifdef C2_SELF_REFRESH_DISABLE
 
@@ -3147,9 +3134,7 @@ void sdram_initialize(int boot_path)
 	sdram_enable_rcomp();
 
 	/* Tell ICH7 that we're done */
-	reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
-	reg8 &= ~(1 << 7);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
+	pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa2, (1 << 7));
 
 	printk(BIOS_DEBUG, "RAM initialization finished.\n");
 
--- src/northbridge/intel/e7501/raminit.c	2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-7507a1-raminit.c	2010-10-05 03:02:47.444443983 +0200
@@ -1449,9 +1449,7 @@ static void configure_e7501_cas_latency(
 	pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
 
 	/* set master DLL reset */
-	dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
-	dword |= (1 << 26);
-	pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
+	pci_set32(PCI_DEV(0, 0, 0), 0x88, (1 << 26));
 
 	dword &= 0x0c0007ff;	/* patch try register 88 is undocumented tnz */
 	dword |= 0xd2109800;
@@ -1461,9 +1459,7 @@ static void configure_e7501_cas_latency(
 	pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL,
 			   maybe_dram_read_timing);
 
-	dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);	/* reset master DLL reset */
-	dword &= ~(1 << 26);
-	pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
+	pci_clear32(PCI_DEV(0, 0, 0), 0x88, (1 << 26));
 
 	return;
 
@@ -1674,13 +1670,9 @@ static void enable_e7501_clocks(uint8_t 
 static void RAM_RESET_DDR_PTR(void)
 {
 	uint8_t byte;
-	byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
-	byte |= (1 << 4);
-	pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
-
-	byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
-	byte &= ~(1 << 4);
-	pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
+	pci_set8(PCI_DEV(0, 0, 0), 0x88, (1 << 4));
+
+	pci_clear8(PCI_DEV(0, 0, 0), 0x88, (1 << 4));
 }
 
 //----------------------------------------------------------------------------------
@@ -1762,9 +1754,7 @@ static void ram_set_rcomp_regs(void)
 	RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
 
 	/*enable access to the rcomp bar */
-	dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
-	dword |= (1 << 22);
-	pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
+	pci_set32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, (1 << 22));
 
 	// Set the RCOMP MMIO base address
 	pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
@@ -1851,9 +1841,7 @@ static void ram_set_rcomp_regs(void)
 	SLOW_DOWN_IO;
 
 	/*disable access to the rcomp bar */
-	dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
-	dword &= ~(1 << 22);
-	pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
+	pci_clear32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, (1 << 22));
 
 }
 
@@ -1961,15 +1949,11 @@ static void sdram_enable(int controllers
 	configure_e7501_ram_addresses(ctrl, dimm_mask);
 
 	/* Finally enable refresh */
-	dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
-	dram_controller_mode |= (1 << 29);
-	pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
+	pci_set32(PCI_DEV(0, 0, 0), DRC, (1 << 29));
 	EXTRA_DELAY;
 	initialize_ecc();
 
-	dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);	/* FCS_EN */
-	dram_controller_mode |= (1 << 17);	// NOTE: undocumented reserved bit
-	pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
+	pci_set32(PCI_DEV(0, 0, 0), DRC, (1 << 17));
 
 	RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
 	DUMPNORTH();
--- src/northbridge/intel/e7520/raminit.c	2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-017572-raminit.c	2010-10-05 03:02:49.172443879 +0200
@@ -1326,9 +1326,7 @@ static void sdram_enable(int controllers
 	}
 
 	/* Bring memory subsystem on line */
-	data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
-	data32 |= (1 << 31);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32);
+	pci_set32(PCI_DEV(0, 0x00, 0), 0x98, (1 << 31));
 	/* wait for completion */
 	print_debug("Waiting for mem complete\n");
 	while(1) {
--- src/northbridge/intel/e7525/raminit.c	2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-0ecb7a-raminit.c	2010-10-05 03:02:50.880443887 +0200
@@ -1293,9 +1293,7 @@ static void sdram_enable(int controllers
 	}
 
 	/* Bring memory subsystem on line */
-	data32 = pci_read_config32(ctrl->f0, 0x98);
-	data32 |= (1 << 31);
-	pci_write_config32(ctrl->f0, 0x98, data32);
+	pci_set32(ctrl->f0, 0x98, (1 << 31));
 	/* wait for completion */
 	print_debug("Waiting for mem complete\n");
 	while(1) {
--- src/northbridge/intel/i3100/raminit.c	2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-90d064-raminit.c	2010-10-05 03:02:52.688451877 +0200
@@ -1183,9 +1183,7 @@ static void sdram_enable(int controllers
 	}
 
 	/* Bring memory subsystem on line */
-	data32 = pci_read_config32(ctrl->f0, 0x98);
-	data32 |= (1 << 31);
-	pci_write_config32(ctrl->f0, 0x98, data32);
+	pci_set32(ctrl->f0, 0x98, (1 << 31));
 	/* wait for completion */
 	print_debug("Waiting for mem complete\n");
 	while(1) {
--- src/northbridge/intel/i82830/raminit.c	2010-10-01 09:27:07.000000000 +0200
+++ /tmp/cocci-output-5159-b68265-raminit.c	2010-10-05 03:02:54.684453048 +0200
@@ -471,10 +471,7 @@ static void northbridge_set_registers(vo
 		igd_memory = 0x0;
 	}
 
-	value = pci_read_config16(NORTHBRIDGE, GCC1);
-	value |= igd_memory << 4;
-	value |= 1; // 64MB aperture
-	pci_write_config16(NORTHBRIDGE, GCC1, value);
+	pci_set16(NORTHBRIDGE, GCC1, igd_memory << 4 | 1);
 
 	printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");
 }
@@ -494,15 +491,11 @@ static void sdram_initialize(void)
 
 	/* Enable Refresh */
 	PRINTK_DEBUG("Enabling Refresh\n");
-	reg32 = pci_read_config32(NORTHBRIDGE, DRC);
-	reg32 |= (RAM_COMMAND_REFRESH << 8);
-	pci_write_config32(NORTHBRIDGE, DRC, reg32);
+	pci_set32(NORTHBRIDGE, DRC, (RAM_COMMAND_REFRESH << 8));
 
 	/* Set initialization complete */
 	PRINTK_DEBUG("Setting initialization complete\n");
-	reg32 = pci_read_config32(NORTHBRIDGE, DRC);
-	reg32 |= (RAM_COMMAND_IC << 29);
-	pci_write_config32(NORTHBRIDGE, DRC, reg32);
+	pci_set32(NORTHBRIDGE, DRC, (RAM_COMMAND_IC << 29));
 
 	/* Setup Initial Northbridge Registers */
 	northbridge_set_registers();
--- src/southbridge/ti/pci7420/pci7420_cardbus.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-174a81-pci7420_cardbus.c	2010-10-05 03:02:55.325444094 +0200
@@ -49,14 +49,10 @@ static void pci7420_cardbus_init(device_
 		smartcard_enabled = config->smartcard_enabled;
 	}
 
-	reg32 = pci_read_config32(dev, SYSCTL);
-	reg32 |= RIMUX;
-	pci_write_config32(dev, SYSCTL, reg32);
+	pci_set32(dev, SYSCTL, RIMUX);
 
 	/* Enable SPKROUT */
-	reg8 = pci_read_config8(dev, CARDCTL);
-	reg8 |= SPKROUTEN;
-	pci_write_config8(dev, CARDCTL, reg8);
+	pci_set8(dev, CARDCTL, SPKROUTEN);
 
 	/* Power switch select and FM disable */
 	reg16 = pci_read_config16(dev, GENCTL);
--- src/southbridge/amd/sb600/sb600_ide.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-040714-sb600_ide.c	2010-10-05 03:02:55.765445227 +0200
@@ -31,20 +31,14 @@ static void ide_init(struct device *dev)
 	u8 byte;
 
 	/* RPR10.1 disable MSI */
-	dword = pci_read_config32(dev, 0x70);
-	dword &= ~(1 << 16);
-	pci_write_config32(dev, 0x70, dword);
+	pci_clear32(dev, 0x70, (1 << 16));
 
 	/* Ultra DMA mode */
 	/* enable UDMA */
-	byte = pci_read_config8(dev, 0x54);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x54, byte);
+	pci_set8(dev, 0x54, 1 << 0);
 
 	/* Enable I/O Access&& Bus Master */
-	dword = pci_read_config16(dev, 0x4);
-	dword |= 1 << 2;
-	pci_write_config16(dev, 0x4, dword);
+	pci_set16(dev, 0x4, 1 << 2);
 
 #if CONFIG_PCI_ROM_RUN == 1
 	pci_dev_init(dev);
--- src/southbridge/amd/sb600/sb600_lpc.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-1edd52-sb600_lpc.c	2010-10-05 03:02:56.049445413 +0200
@@ -37,27 +37,19 @@ static void lpc_init(device_t dev)
 
 	/* Enable the LPC Controller */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	dword = pci_read_config32(sm_dev, 0x64);
-	dword |= 1 << 20;
-	pci_write_config32(sm_dev, 0x64, dword);
+	pci_set32(sm_dev, 0x64, 1 << 20);
 
 	/* Initialize isa dma */
 	isa_dma_init();
 
 	/* RPR 7.2 Enable DMA transaction on the LPC bus */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 2);
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, (1 << 2));
 
 	/* RPR 7.3 Disable the timeout mechanism on LPC */
-	byte = pci_read_config8(dev, 0x48);
-	byte &= ~(1 << 7);
-	pci_write_config8(dev, 0x48, byte);
+	pci_clear8(dev, 0x48, (1 << 7));
 
 	/* RPR 7.5 Disable LPC MSI Capability */
-	byte = pci_read_config8(dev, 0x78);
-	byte &= ~(1 << 1);
-	pci_write_config8(dev, 0x78, byte);
+	pci_clear8(dev, 0x78, (1 << 1));
 
 }
 
--- src/southbridge/amd/sb600/sb600_pci.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-35d54e-sb600_pci.c	2010-10-05 03:02:56.505444294 +0200
@@ -32,67 +32,43 @@ static void pci_init(struct device *dev)
 
 	/* RPR 4.1 Enables the PCI-bridge subtractive decode */
 	/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 7;
-	pci_write_config8(dev, 0x4B, byte);
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 5;
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x4B, 1 << 7);
+	pci_set8(dev, 0x40, 1 << 5);
 
 	/* RPR4.2 PCI-bridge upstream dual address window */
 	/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
-	byte = pci_read_config8(dev, 0x50);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x50, byte);
+	pci_set8(dev, 0x50, 1 << 0);
 
 	/* RPR 4.3 PCI bus 64-byte DMA read access */
 	/* Enhance the PCI bus DMA performance */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 4;
-	pci_write_config8(dev, 0x4B, byte);
+	pci_set8(dev, 0x4B, 1 << 4);
 
 	/* RPR 4.4 Enables the PCIB writes to be cacheline aligned. */
 	/* The size of the writes will be set in the Cacheline Register */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 1;
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, 1 << 1);
 
 	/* RPR 4.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
 	pci_write_config8(dev, 0x0D, 0x40);
 	pci_write_config8(dev, 0x1B, 0x40);
 
 	/* RPR 4.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 6;
-	pci_write_config8(dev, 0x4B, byte);
+	pci_set8(dev, 0x4B, 1 << 6);
 
 	/* RPR 4.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x4B, byte);
+	pci_set8(dev, 0x4B, 1 << 0);
 
 	/* RPR 4.8 Adjusts the GNT# de-assertion time */
-	word = pci_read_config16(dev, 0x64);
-	word |= 1 << 12;
-	pci_write_config16(dev, 0x64, word);
+	pci_set16(dev, 0x64, 1 << 12);
 
 	/* RPR 4.9 Fast Back to Back transactions support */
-	byte = pci_read_config8(dev, 0x48);
-	byte |= 1 << 2;
-	pci_write_config8(dev, 0x48, byte);
+	pci_set8(dev, 0x48, 1 << 2);
 
 	/* RPR 4.10 Enable Lock Operation */
-	byte = pci_read_config8(dev, 0x48);
-	byte |= 1 << 3;
-	pci_write_config8(dev, 0x48, byte);
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 2);
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x48, 1 << 3);
+	pci_set8(dev, 0x40, (1 << 2));
 
 	/* RPR 4.11 Enable additional optional PCI clock */
-	word = pci_read_config16(dev, 0x64);
-	word |= 1 << 8;
-	pci_write_config16(dev, 0x64, word);
+	pci_set16(dev, 0x64, 1 << 8);
 
 	/* rpr4.12 Disable Fewer-Retry Mode for A11-A13 only. 0x64[5:4] clear */
 	byte = pci_read_config8(dev, 0x64);
@@ -100,24 +76,16 @@ static void pci_init(struct device *dev)
 	pci_write_config8(dev, 0x64, byte);
 
 	/* rpr4.14 Disabling Downstream Flush, for A12 only, 0x64[18]. */
-	dword = pci_read_config32(dev, 0x64);
-	dword |= (1 << 18);
-	pci_write_config32(dev, 0x64, dword);
+	pci_set32(dev, 0x64, (1 << 18));
 
 	/* RPR 4.13 Enable One-Prefetch-Channel Mode */
-	dword = pci_read_config32(dev, 0x64);
-	dword |= 1 << 20;
-	pci_write_config32(dev, 0x64, dword);
+	pci_set32(dev, 0x64, 1 << 20);
 
 	/* RPR 4.15 Disable PCIB MSI Capability */
-	byte = pci_read_config8(dev, 0x40);
-	byte &= ~(1 << 3);
-	pci_write_config8(dev, 0x40, byte);
+	pci_clear8(dev, 0x40, (1 << 3));
 
 	/* rpr4.16 Adjusting CLKRUN# */
-	dword = pci_read_config32(dev, 0x64);
-	dword |= (1 << 15);
-	pci_write_config32(dev, 0x64, dword);
+	pci_set32(dev, 0x64, (1 << 15));
 }
 
 static struct pci_operations lops_pci = {
--- src/southbridge/amd/sb600/sb600_usb.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-53c3e5-sb600_usb.c	2010-10-05 03:02:56.837444068 +0200
@@ -39,9 +39,7 @@ static void usb_init(struct device *dev)
 	/* Enable OHCI0-4 and EHCI Controllers */
 	device_t sm_dev;
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	byte = pci_read_config8(sm_dev, 0x68);
-	byte |= 0x3F;
-	pci_write_config8(sm_dev, 0x68, byte);
+	pci_set8(sm_dev, 0x68, 0x3F);
 
 	/* RPR 5.2 Enables the USB PME Event,Enable USB resume support */
 	byte = pm_ioread(0x61);
@@ -62,25 +60,17 @@ static void usb_init(struct device *dev)
 	pm_iowrite(0x65, byte);
 
 	/* RPR 5.11 Disable OHCI MSI Capability */
-	word = pci_read_config16(dev, 0x40);
-	word |= (0x1F << 8);
-	pci_write_config16(dev, 0x40, word);
+	pci_set16(dev, 0x40, (0x1F << 8));
 
 	/* RPR 5.8 Disable the OHCI Dynamic Power Saving feature  */
-	dword = pci_read_config32(dev, 0x50);
-	dword &= ~(1 << 16);
-	pci_write_config32(dev, 0x50, dword);
+	pci_clear32(dev, 0x50, (1 << 16));
 
 	/* RPR 5.12 Enable prevention of OHCI accessing the invalid system memory address range */
-	word = pci_read_config16(dev, 0x50);
-	word |= 1 << 15;
-	pci_write_config16(dev, 0x50, word);
+	pci_set16(dev, 0x50, 1 << 15);
 
 	/* RPR 5.15 Disable SMI handshake in between USB and ACPI for USB legacy support. */
 	/* The BIOS should always set this bit to prevent the malfunction on USB legacy keyboard/mouse support */
-	word = pci_read_config16(dev, 0x50);
-	word |= 1 << 12;
-	pci_write_config16(dev, 0x50, word);
+	pci_set16(dev, 0x50, 1 << 12);
 }
 
 static void usb_init2(struct device *dev)
@@ -110,19 +100,13 @@ static void usb_init2(struct device *dev
 	write16(usb2_bar0 + 0xBC, word);
 
 	/* RPR5.10 Disable EHCI MSI support */
-	byte = pci_read_config8(dev, 0x50);
-	byte |= (1 << 6);
-	pci_write_config8(dev, 0x50, byte);
+	pci_set8(dev, 0x50, (1 << 6));
 
 	/* RPR5.13 Disable C3 time enhancement feature */
-	dword = pci_read_config32(dev, 0x50);
-	dword &= ~(1 << 28);
-	pci_write_config32(dev, 0x50, dword);
+	pci_clear32(dev, 0x50, (1 << 28));
 
 	/* RPR5.14 Disable USB PHY PLL Reset signal to come from ACPI */
-	byte = pci_read_config8(dev, 0x54);
-	byte &= ~(1 << 0);
-	pci_write_config8(dev, 0x54, byte);
+	pci_clear8(dev, 0x54, (1 << 0));
 }
 
 static void usb_set_resources(struct device *dev)
--- src/southbridge/amd/sb600/sb600_sata.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d0f17b-sb600_sata.c	2010-10-05 03:02:57.237444025 +0200
@@ -74,10 +74,7 @@ static void sata_init(struct device *dev
 	byte = pci_read_config8(sm_dev, 0xad);
 	byte |= (1 << 1);
 	/* Enable SATA and power saving */
-	byte = pci_read_config8(sm_dev, 0xad);
-	byte |= (1 << 0);
-	byte |= (1 << 5);
-	pci_write_config8(sm_dev, 0xad, byte);
+	pci_set8(sm_dev, 0xad, (1 << 0) | (1 << 5));
 	/* Set the interrupt Mapping to INTG# */
 	byte = pci_read_config8(sm_dev, 0xaf);
 	byte = 0x6 << 2;
@@ -103,32 +100,21 @@ static void sata_init(struct device *dev
 	pci_write_config32(dev, 0x2c, dword);
 
 	/* SERR-Enable */
-	word = pci_read_config16(dev, 0x04);
-	word |= (1 << 8);
-	pci_write_config16(dev, 0x04, word);
+	pci_set16(dev, 0x04, (1 << 8));
 
 	/* Dynamic power saving */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 2);
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, (1 << 2));
 
 	/* Set SATA Operation Mode, Set to IDE mode */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 0);
-	byte |= (1 << 4);
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, (1 << 0) | (1 << 4));
 
 	dword = 0x01018f00;
 	pci_write_config32(dev, 0x8, dword);
 
-	byte = pci_read_config8(dev, 0x40);
-	byte &= ~(1 << 0);
-	pci_write_config8(dev, 0x40, byte);
+	pci_clear8(dev, 0x40, (1 << 0));
 
 	/* Enable the SATA watchdog counter */
-	byte = pci_read_config8(dev, 0x44);
-	byte |= (1 << 0);
-	pci_write_config8(dev, 0x44, byte);
+	pci_set8(dev, 0x44, (1 << 0));
 
 	/* Program the watchdog counter to 0x10 */
 	byte = 0x10;
@@ -152,18 +138,12 @@ static void sata_init(struct device *dev
 	pci_write_config8(dev, 0xBD, byte);
 
 	/* RPR 6.8  */
-	word = pci_read_config16(dev, 0x42);
-	word |= 1 << 7;
-	pci_write_config16(dev, 0x42, word);
+	pci_set16(dev, 0x42, 1 << 7);
 	/* RPR 6.9  */
-	dword = pci_read_config32(dev, 0x40);
-	dword |= 1 << 25;
-	pci_write_config32(dev, 0x40, dword);
+	pci_set32(dev, 0x40, 1 << 25);
 
 	/* Enable the I/O, MM, BusMaster access for SATA */
-	byte = pci_read_config8(dev, 0x4);
-	byte |= 7 << 0;
-	pci_write_config8(dev, 0x4, byte);
+	pci_set8(dev, 0x4, 7 << 0);
 
 	/* RPR6.6 SATA drive detection. */
 	/* Use BAR5+0x128,BAR0 for Primary Slave */
--- src/southbridge/amd/sb600/sb600_sm.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-62ee4e-sb600_sm.c	2010-10-05 03:02:57.749443841 +0200
@@ -60,18 +60,12 @@ static void sm_init(device_t dev)
 	/* Don't rename APIC ID */
 	clear_ioapic(ioapic_base);
 
-	dword = pci_read_config8(dev, 0x62);
-	dword |= 1 << 2;
-	pci_write_config8(dev, 0x62, dword);
-
-	dword = pci_read_config32(dev, 0x78);
-	dword |= 1 << 9;
-	pci_write_config32(dev, 0x78, dword);	/* enable 0xCD6 0xCD7 */
+	pci_set8(dev, 0x62, 1 << 2);
+
+	pci_set32(dev, 0x78, 1 << 9);	/* enable 0xCD6 0xCD7 */
 
 	/* bit 10: MultiMediaTimerIrqEn */
-	dword = pci_read_config8(dev, 0x64);
-	dword |= 1 << 10;
-	pci_write_config8(dev, 0x64, dword);
+	pci_set8(dev, 0x64, 1 << 10);
 	/* enable serial irq */
 	byte = pci_read_config8(dev, 0x69);
 	byte |= 1 << 7;		/* enable serial irq function */
--- src/southbridge/amd/sb600/sb600_early_setup.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-389437-sb600_early_setup.c	2010-10-05 03:02:58.381444095 +0200
@@ -76,26 +76,18 @@ static void sb600_lpc_init(void)
 	 * This bit has no meaning if debug strap is not enabled. So if the
 	 * board keeps rebooting and the code fails to reach here, we could
 	 * disable the debug strap first. */
-	reg32 = pci_read_config32(dev, 0x4C);
-	reg32 |= 1 << 31;
-	pci_write_config32(dev, 0x4C, reg32);
+	pci_set32(dev, 0x4C, 1 << 31);
 
 	/* Enable lpc controller */
-	reg32 = pci_read_config32(dev, 0x64);
-	reg32 |= 1 << 20;
-	pci_write_config32(dev, 0x64, reg32);
+	pci_set32(dev, 0x64, 1 << 20);
 
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);	/* LPC Controller */
 	/* Decode port 0x3f8-0x3ff (Serial 0) */
 	// XXX Serial port decode on LPC is hardcoded to 0x3f8
-	reg8 = pci_read_config8(dev, 0x44);
-	reg8 |= 1 << 6;
-	pci_write_config8(dev, 0x44, reg8);
+	pci_set8(dev, 0x44, 1 << 6);
 
 	/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
-	reg8 = pci_read_config8(dev, 0x47);
-	reg8 |= (1 << 5) | (1 << 6);
-	pci_write_config8(dev, 0x47, reg8);
+	pci_set8(dev, 0x47, (1 << 5) | (1 << 6));
 
 	/* SuperIO, LPC ROM */
 	reg8 = pci_read_config8(dev, 0x48);
@@ -219,40 +211,28 @@ void sb600_pci_port80(void)
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
 
 	/* Chip Control: Enable subtractive decoding */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 5;
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, 1 << 5);
 
 	/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 7;
-	pci_write_config8(dev, 0x4B, byte);
+	pci_set8(dev, 0x4B, 1 << 7);
 
 	/* The same IO Base and IO Limit here is meaningful because we set the
 	 * bridge to be subtractive. During early setup stage, we have to make
 	 * sure that data can go through port 0x80.
 	 */
 	/* IO Base: 0xf000 */
-	byte = pci_read_config8(dev, 0x1C);
-	byte |= 0xF << 4;
-	pci_write_config8(dev, 0x1C, byte);
+	pci_set8(dev, 0x1C, 0xF << 4);
 
 	/* IO Limit: 0xf000 */
-	byte = pci_read_config8(dev, 0x1D);
-	byte |= 0xF << 4;
-	pci_write_config8(dev, 0x1D, byte);
+	pci_set8(dev, 0x1D, 0xF << 4);
 
 	/* PCI Command: Enable IO response */
-	byte = pci_read_config8(dev, 0x04);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x04, byte);
+	pci_set8(dev, 0x04, 1 << 0);
 
 	/* LPC controller */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
 
-	byte = pci_read_config8(dev, 0x4A);
-	byte &= ~(1 << 5);	/* disable lpc port 80 */
-	pci_write_config8(dev, 0x4A, byte);
+	pci_clear8(dev, 0x4A, (1 << 5));
 }
 
 void sb600_lpc_port80(void)
@@ -263,15 +243,11 @@ void sb600_lpc_port80(void)
 
 	/* Enable LPC controller */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
-	reg32 = pci_read_config32(dev, 0x64);
-	reg32 |= 0x00100000;	/* lpcEnable */
-	pci_write_config32(dev, 0x64, reg32);
+	pci_set32(dev, 0x64, 0x00100000);
 
 	/* Enable port 80 LPC decode in pci function 3 configuration space. */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);
-	byte = pci_read_config8(dev, 0x4a);
-	byte |= 1 << 5;		/* enable port 80 */
-	pci_write_config8(dev, 0x4a, byte);
+	pci_set8(dev, 0x4a, 1 << 5);
 }
 
 /* sbDevicesPorInitTable */
@@ -311,9 +287,7 @@ static void sb600_devices_por_init(void)
 	pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
 
 	/* enable smbus controller interface */
-	byte = pci_read_config8(dev, 0xd2);
-	byte |= (1 << 0);
-	pci_write_config8(dev, 0xd2, byte);
+	pci_set8(dev, 0xd2, (1 << 0));
 
 	/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
 	pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
@@ -341,9 +315,7 @@ static void sb600_devices_por_init(void)
 	/* pci_write_config8(dev, 0x43, 0x1); */
 
 	/* Disabling Legacy USB Fast SMI# */
-	byte = pci_read_config8(dev, 0x62);
-	byte |= 0x24;
-	pci_write_config8(dev, 0x62, byte);
+	pci_set8(dev, 0x62, 0x24);
 
 	/* Features Enable */
 	pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
@@ -371,9 +343,7 @@ static void sb600_devices_por_init(void)
 	printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
 	/* Disable prefetch */
-	byte = pci_read_config8(dev, 0x63);
-	byte |= 0x1;
-	pci_write_config8(dev, 0x63, byte);
+	pci_set8(dev, 0x63, 0x1);
 
 	/* LPC Device, BDF:0-20-3 */
 	printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
@@ -398,9 +368,7 @@ static void sb600_devices_por_init(void)
 	pci_write_config8(dev, 0x48, byte);
 	pci_write_config8(dev, 0x49, 0xFF);
 	/* Enable 0x480-0x4bf, 0x4700-0x470B */
-	byte = pci_read_config8(dev, 0x4A);
-	byte |= ((1 << 1) + (1 << 6));	/*0x42, save the configuraion for port 0x80. */
-	pci_write_config8(dev, 0x4A, byte);
+	pci_set8(dev, 0x4A, ((1 << 1) + (1 << 6)));
 
 	/* Set LPC ROM size, it has been done in sb600_lpc_init().
 	 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
@@ -568,18 +536,12 @@ static void sb600_pci_cfg(void)
 	/* SMBus Device, BDF:0-20-0 */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
 	/* Eable the hidden revision ID, available after A13. */
-	byte = pci_read_config8(dev, 0x70);
-	byte |= (1 << 8);
-	pci_write_config8(dev, 0x70, byte);
+	pci_set8(dev, 0x70, (1 << 8));
 	/* rpr2.20 Disable Timer IRQ Enhancement for proper operation of the 8254 timer, 0xae[5]. */
-	byte = pci_read_config8(dev, 0xae);
-	byte |= (1 << 5);
-	pci_write_config8(dev, 0xae, byte);
+	pci_set8(dev, 0xae, (1 << 5));
 
 	/* Enable watchdog decode timer */
-	byte = pci_read_config8(dev, 0x41);
-	byte |= (1 << 3);
-	pci_write_config8(dev, 0x41, byte);
+	pci_set8(dev, 0x41, (1 << 3));
 
 	/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
 	 * generated PCIRST#. */
@@ -608,9 +570,7 @@ static void sb600_pci_cfg(void)
 	/* LPC Device, BDF:0-20-3 */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
 	/* rpr7.2 Enabling LPC DMA function. */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 2);
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, (1 << 2));
 	/* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */
 	byte = pci_read_config8(dev, 0x48);
 	byte &= 0x7f;
@@ -625,24 +585,18 @@ static void sb600_pci_cfg(void)
 	/* rpr6.8 Disabling SATA MSI Capability, for A13 and above, 0x42[7]. */
 	if (0x12 < get_sb600_revision()) {
 		u32 reg32;
-		reg32 = pci_read_config32(dev, 0x40);
-		reg32 |= (1 << 23);
-		pci_write_config32(dev, 0x40, reg32);
+		pci_set32(dev, 0x40, (1 << 23));
 	}
 
 	/* EHCI Device, BDF:0-19-5, ehci usb controller */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4386), 0);
 	/* rpr5.10 Disabling USB EHCI MSI Capability. 0x50[6]. */
-	byte = pci_read_config8(dev, 0x50);
-	byte |= (1 << 6);
-	pci_write_config8(dev, 0x50, byte);
+	pci_set8(dev, 0x50, (1 << 6));
 
 	/* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0);
 	/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
-	byte = pci_read_config8(dev, 0x41);
-	byte |= 0x1f;
-	pci_write_config8(dev, 0x41, byte);
+	pci_set8(dev, 0x41, 0x1f);
 
 }
 
--- src/southbridge/amd/sb700/sb700_early_setup.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-49d7ab-sb700_early_setup.c	2010-10-05 03:02:59.249443935 +0200
@@ -66,9 +66,7 @@ static u8 set_sb700_revision(void)
 			 * the rivision ID, we don't have to make such a big function.
 			 * We just get reg 0x8 in smbus dev. 0x39 is A11, 0x3A is A12. */
 			rev = 0x12;
-			byte = pci_read_config8(dev, 0x40);
-			byte |= 1 << 0;
-			pci_write_config8(dev, 0x40, byte);
+			pci_set8(dev, 0x40, 1 << 0);
 
 			pci_write_config8(dev, 0x08, 0x3A); /* Change 0x39 to 0x3A. */
 
@@ -108,26 +106,18 @@ static void sb700_lpc_init(void)
 	 * This bit has no meaning if debug strap is not enabled. So if the
 	 * board keeps rebooting and the code fails to reach here, we could
 	 * disable the debug strap first. */
-	reg32 = pci_read_config32(dev, 0x4C);
-	reg32 |= 1 << 31;
-	pci_write_config32(dev, 0x4C, reg32);
+	pci_set32(dev, 0x4C, 1 << 31);
 
 	/* Enable lpc controller */
-	reg32 = pci_read_config32(dev, 0x64);
-	reg32 |= 1 << 20;
-	pci_write_config32(dev, 0x64, reg32);
+	pci_set32(dev, 0x64, 1 << 20);
 
 	dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);	/* LPC Controller */
 	/* Decode port 0x3f8-0x3ff (Serial 0) */
 	// XXX Serial port decode on LPC is hardcoded to 0x3f8
-	reg8 = pci_read_config8(dev, 0x44);
-	reg8 |= 1 << 6;
-	pci_write_config8(dev, 0x44, reg8);
+	pci_set8(dev, 0x44, 1 << 6);
 
 	/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
-	reg8 = pci_read_config8(dev, 0x47);
-	reg8 |= (1 << 5) | (1 << 6);
-	pci_write_config8(dev, 0x47, reg8);
+	pci_set8(dev, 0x47, (1 << 5) | (1 << 6));
 
 	/* SuperIO, LPC ROM */
 	reg8 = pci_read_config8(dev, 0x48);
@@ -240,40 +230,28 @@ void sb700_pci_port80(void)
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
 
 	/* Chip Control: Enable subtractive decoding */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 5;
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, 1 << 5);
 
 	/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 7;
-	pci_write_config8(dev, 0x4B, byte);
+	pci_set8(dev, 0x4B, 1 << 7);
 
 	/* The same IO Base and IO Limit here is meaningful because we set the
 	 * bridge to be subtractive. During early setup stage, we have to make
 	 * sure that data can go through port 0x80.
 	 */
 	/* IO Base: 0xf000 */
-	byte = pci_read_config8(dev, 0x1C);
-	byte |= 0xF << 4;
-	pci_write_config8(dev, 0x1C, byte);
+	pci_set8(dev, 0x1C, 0xF << 4);
 
 	/* IO Limit: 0xf000 */
-	byte = pci_read_config8(dev, 0x1D);
-	byte |= 0xF << 4;
-	pci_write_config8(dev, 0x1D, byte);
+	pci_set8(dev, 0x1D, 0xF << 4);
 
 	/* PCI Command: Enable IO response */
-	byte = pci_read_config8(dev, 0x04);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x04, byte);
+	pci_set8(dev, 0x04, 1 << 0);
 
 	/* LPC controller */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
 
-	byte = pci_read_config8(dev, 0x4A);
-	byte &= ~(1 << 5);	/* disable lpc port 80 */
-	pci_write_config8(dev, 0x4A, byte);
+	pci_clear8(dev, 0x4A, (1 << 5));
 }
 
 void sb700_lpc_port80(void)
@@ -284,15 +262,11 @@ void sb700_lpc_port80(void)
 
 	/* Enable LPC controller */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
-	reg32 = pci_read_config32(dev, 0x64);
-	reg32 |= 0x00100000;	/* lpcEnable */
-	pci_write_config32(dev, 0x64, reg32);
+	pci_set32(dev, 0x64, 0x00100000);
 
 	/* Enable port 80 LPC decode in pci function 3 configuration space. */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);
-	byte = pci_read_config8(dev, 0x4a);
-	byte |= 1 << 5;		/* enable port 80 */
-	pci_write_config8(dev, 0x4a, byte);
+	pci_set8(dev, 0x4a, 1 << 5);
 }
 
 /* sbDevicesPorInitTable */
@@ -332,9 +306,7 @@ static void sb700_devices_por_init(void)
 	pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
 
 	/* enable smbus controller interface */
-	byte = pci_read_config8(dev, 0xd2);
-	byte |= (1 << 0);
-	pci_write_config8(dev, 0xd2, byte);
+	pci_set8(dev, 0xd2, (1 << 0));
 
 	/* KB2RstEnable */
 	pci_write_config8(dev, 0x40, 0x44);
@@ -355,9 +327,7 @@ static void sb700_devices_por_init(void)
 	/* pci_write_config8(dev, 0x43, 0x1); */
 
 	/* Disabling Legacy USB Fast SMI# */
-	byte = pci_read_config8(dev, 0x62);
-	byte |= 0x24;
-	pci_write_config8(dev, 0x62, byte);
+	pci_set8(dev, 0x62, 0x24);
 
 	/* Features Enable */
 	pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET interrupt. */
@@ -382,9 +352,7 @@ static void sb700_devices_por_init(void)
 	printk(BIOS_INFO, "sb700_devices_por_init(): IDE Device, BDF:0-20-1\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
 	/* Disable prefetch */
-	byte = pci_read_config8(dev, 0x63);
-	byte |= 0x1;
-	pci_write_config8(dev, 0x63, byte);
+	pci_set8(dev, 0x63, 0x1);
 
 	/* LPC Device, BDF:0-20-3 */
 	printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n");
@@ -409,9 +377,7 @@ static void sb700_devices_por_init(void)
 	pci_write_config8(dev, 0x48, byte);
 	pci_write_config8(dev, 0x49, 0xFF);
 	/* Enable 0x480-0x4bf, 0x4700-0x470B */
-	byte = pci_read_config8(dev, 0x4A);
-	byte |= ((1 << 1) + (1 << 6));	/*0x42, save the configuraion for port 0x80. */
-	pci_write_config8(dev, 0x4A, byte);
+	pci_set8(dev, 0x4A, ((1 << 1) + (1 << 6)));
 
 	/* Set LPC ROM size, it has been done in sb700_lpc_init().
 	 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
@@ -530,9 +496,7 @@ static void sb700_pci_cfg(void)
 	/* SMBus Device, BDF:0-20-0 */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
 	/* Enable watchdog decode timer */
-	byte = pci_read_config8(dev, 0x41);
-	byte |= (1 << 3);
-	pci_write_config8(dev, 0x41, byte);
+	pci_set8(dev, 0x41, (1 << 3));
 
 	/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
 	 * generated PCIRST#. */
@@ -553,9 +517,7 @@ static void sb700_pci_cfg(void)
 	 * comments are compatible. */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
 	/* Enabling LPC DMA function. */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 2);
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, (1 << 2));
 	/* Disabling LPC TimeOut. 0x48[7] clear. */
 	byte = pci_read_config8(dev, 0x48);
 	byte &= 0x7f;
@@ -568,9 +530,7 @@ static void sb700_pci_cfg(void)
 	/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
 	/* rpr7.12 SATA MSI and D3 Power State Capability. */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, 1 << 0);
 	if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12)
 		pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */
 	else
--- src/southbridge/amd/sb700/sb700_sm.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-add399-sb700_sm.c	2010-10-05 03:03:00.041443990 +0200
@@ -63,29 +63,19 @@ static void sm_init(device_t dev)
 	clear_ioapic(ioapic_base);
 
 	/* 2.10 Interrupt Routing/Filtering */
-	dword = pci_read_config8(dev, 0x62);
-	dword |= 3;
-	pci_write_config8(dev, 0x62, dword);
+	pci_set8(dev, 0x62, 3);
 
 	/* Delay back to back interrupts to the CPU. */
-	dword = pci_read_config16(dev, 0x64);
-	dword |= 1 << 13;
-	pci_write_config16(dev, 0x64, dword);
+	pci_set16(dev, 0x64, 1 << 13);
 
 	/* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */
 	/* rpr 2.1 Enabling Legacy Interrupt */
-	dword = pci_read_config8(dev, 0x62);
-	dword |= 1 << 2;
-	pci_write_config8(dev, 0x62, dword);
-
-	dword = pci_read_config32(dev, 0x78);
-	dword |= 1 << 9;
-	pci_write_config32(dev, 0x78, dword);	/* enable 0xCD6 0xCD7 */
+	pci_set8(dev, 0x62, 1 << 2);
+
+	pci_set32(dev, 0x78, 1 << 9);	/* enable 0xCD6 0xCD7 */
 
 	/* bit 10: MultiMediaTimerIrqEn */
-	dword = pci_read_config8(dev, 0x64);
-	dword |= 1 << 10;
-	pci_write_config8(dev, 0x64, dword);
+	pci_set8(dev, 0x64, 1 << 10);
 	/* enable serial irq */
 	byte = pci_read_config8(dev, 0x69);
 	byte |= 1 << 7;		/* enable serial irq function */
@@ -94,9 +84,7 @@ static void sm_init(device_t dev)
 	pci_write_config8(dev, 0x69, byte);
 
 	/* IRQ0From8254 */
-	byte = pci_read_config8(dev, 0x41);
-	byte &= ~(1 << 7);
-	pci_write_config8(dev, 0x41, byte);
+	pci_clear8(dev, 0x41, (1 << 7));
 
 	byte = pm_ioread(0x61);
 	byte |= 1 << 1;		/* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
--- src/southbridge/amd/sb700/sb700_sata.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-db020f-sb700_sata.c	2010-10-05 03:03:00.649443920 +0200
@@ -97,10 +97,7 @@ static void sata_init(struct device *dev
 	byte = pci_read_config8(sm_dev, 0xad);
 	byte |= (1 << 1);
 	/* Enable SATA and power saving */
-	byte = pci_read_config8(sm_dev, 0xad);
-	byte |= (1 << 0);
-	byte |= (1 << 5);
-	pci_write_config8(sm_dev, 0xad, byte);
+	pci_set8(sm_dev, 0xad, (1 << 0) | (1 << 5));
 
 	/* RPR 7.2 SATA Initialization */
 	/* Set the interrupt Mapping to INTG# */
@@ -127,40 +124,27 @@ static void sata_init(struct device *dev
 	printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
 
 	/* disable combined mode */
-	byte = pci_read_config8(sm_dev, 0xAD);
-	byte &= ~(1 << 3);
-	pci_write_config8(sm_dev, 0xAD, byte);
+	pci_clear8(sm_dev, 0xAD, (1 << 3));
 	/* Program the 2C to 0x43801002 */
 	dword = 0x43801002;
 	pci_write_config32(dev, 0x2c, dword);
 
 	/* SERR-Enable */
-	word = pci_read_config16(dev, 0x04);
-	word |= (1 << 8);
-	pci_write_config16(dev, 0x04, word);
+	pci_set16(dev, 0x04, (1 << 8));
 
 	/* Dynamic power saving */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 2);
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, (1 << 2));
 
 	/* Set SATA Operation Mode, Set to IDE mode */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 0);
-	byte |= (1 << 4);
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, (1 << 0) | (1 << 4));
 
 	dword = 0x01018f00;
 	pci_write_config32(dev, 0x8, dword);
 
-	byte = pci_read_config8(dev, 0x40);
-	byte &= ~(1 << 0);
-	pci_write_config8(dev, 0x40, byte);
+	pci_clear8(dev, 0x40, (1 << 0));
 
 	/* Enable the SATA watchdog counter */
-	byte = pci_read_config8(dev, 0x44);
-	byte |= (1 << 0);
-	pci_write_config8(dev, 0x44, byte);
+	pci_set8(dev, 0x44, (1 << 0));
 
 	/* Set bit 29 and 24 for A12 */
 	dword = pci_read_config32(dev, 0x40);
@@ -186,9 +170,7 @@ static void sata_init(struct device *dev
 	pci_write_config8(dev, 0x46, byte);
 	sb700_setup_sata_phys(dev);
 	/* Enable the I/O, MM, BusMaster access for SATA */
-	byte = pci_read_config8(dev, 0x4);
-	byte |= 7 << 0;
-	pci_write_config8(dev, 0x4, byte);
+	pci_set8(dev, 0x4, 7 << 0);
 
 	/* RPR7.7 SATA drive detection. */
 	/* Use BAR5+0x128,BAR0 for Primary Slave */
--- src/southbridge/amd/sb700/sb700_ide.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-460f15-sb700_ide.c	2010-10-05 03:03:01.161444037 +0200
@@ -35,27 +35,19 @@ static void ide_init(struct device *dev)
 
 	/* RPR9.1 disable MSI */
 	/* TODO: For A14, it should set as 1. I doubt it. */
-	dword = pci_read_config32(dev, 0x70);
-	dword &= ~(1 << 16);
-	pci_write_config32(dev, 0x70, dword);
+	pci_clear32(dev, 0x70, (1 << 16));
 
 	/* Ultra DMA mode */
 	/* enable UDMA */
-	byte = pci_read_config8(dev, 0x54);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x54, byte);
+	pci_set8(dev, 0x54, 1 << 0);
 
 	/* Enable I/O Access&& Bus Master */
-	dword = pci_read_config16(dev, 0x4);
-	dword |= 1 << 2;
-	pci_write_config16(dev, 0x4, dword);
+	pci_set16(dev, 0x4, 1 << 2);
 
 	/* set ide as primary, if you want to boot from IDE, you'd better set it
 	 * in $vendor/$mainboard/devicetree.cb */
 	if (conf->boot_switch_sata_ide == 1) {
-		byte = pci_read_config8(dev, 0xAD);
-		byte |= 1 << 4;
-		pci_write_config8(dev, 0xAD, byte);
+		pci_set8(dev, 0xAD, 1 << 4);
 	}
 
 #if CONFIG_PCI_ROM_RUN == 1
--- src/southbridge/amd/sb700/sb700_lpc.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-dde956-sb700_lpc.c	2010-10-05 03:03:01.385444630 +0200
@@ -37,9 +37,7 @@ static void lpc_init(device_t dev)
 
 	/* Enable the LPC Controller */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	dword = pci_read_config32(sm_dev, 0x64);
-	dword |= 1 << 20;
-	pci_write_config32(sm_dev, 0x64, dword);
+	pci_set32(sm_dev, 0x64, 1 << 20);
 
 	/* Initialize isa dma */
 #if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
@@ -49,19 +47,13 @@ static void lpc_init(device_t dev)
 #endif
 
 	/* Enable DMA transaction on the LPC bus */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 2);
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, (1 << 2));
 
 	/* Disable the timeout mechanism on LPC */
-	byte = pci_read_config8(dev, 0x48);
-	byte &= ~(1 << 7);
-	pci_write_config8(dev, 0x48, byte);
+	pci_clear8(dev, 0x48, (1 << 7));
 
 	/* Disable LPC MSI Capability */
-	byte = pci_read_config8(dev, 0x78);
-	byte &= ~(1 << 1);
-	pci_write_config8(dev, 0x78, byte);
+	pci_clear8(dev, 0x78, (1 << 1));
 }
 
 static void sb700_lpc_read_resources(device_t dev)
--- src/southbridge/amd/sb700/sb700_pci.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-ab7260-sb700_pci.c	2010-10-05 03:03:01.733444609 +0200
@@ -32,79 +32,48 @@ static void pci_init(struct device *dev)
 
 	/* RPR 5.1 Enables the PCI-bridge subtractive decode */
 	/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 7;
-	pci_write_config8(dev, 0x4B, byte);
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 5;
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x4B, 1 << 7);
+	pci_set8(dev, 0x40, 1 << 5);
 
 	/* RPR5.2 PCI-bridge upstream dual address window */
 	/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
-	byte = pci_read_config8(dev, 0x50);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x50, byte);
+	pci_set8(dev, 0x50, 1 << 0);
 
 	/* RPR 5.3 PCI bus 64-byte DMA read access */
 	/* Enhance the PCI bus DMA performance */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 4;
-	pci_write_config8(dev, 0x4B, byte);
+	pci_set8(dev, 0x4B, 1 << 4);
 
 	/* RPR 5.4 Enables the PCIB writes to be cacheline aligned. */
 	/* The size of the writes will be set in the Cacheline Register */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= 1 << 1;
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, 1 << 1);
 
 	/* RPR 5.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
 	pci_write_config8(dev, 0x0D, 0x40);
 	pci_write_config8(dev, 0x1B, 0x40);
 
 	/* RPR 5.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 6;
-	pci_write_config8(dev, 0x4B, byte);
+	pci_set8(dev, 0x4B, 1 << 6);
 
 	/* RPR 5.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1 << 0;
-	pci_write_config8(dev, 0x4B, byte);
+	pci_set8(dev, 0x4B, 1 << 0);
 
 	/* RPR 5.8 Adjusts the GNT# de-assertion time */
-	word = pci_read_config16(dev, 0x64);
-	word |= 1 << 12;
-	pci_write_config16(dev, 0x64, word);
+	pci_set16(dev, 0x64, 1 << 12);
 
 	/* RPR 5.9 Fast Back to Back transactions support */
-	byte = pci_read_config8(dev, 0x48);
-	byte |= 1 << 2;
-	/* pci_write_config8(dev, 0x48, byte); */
-
-	/* RPR 5.10 Enable Lock Operation */
-	/* byte = pci_read_config8(dev, 0x48); */
-	byte |= 1 << 3;
-	pci_write_config8(dev, 0x48, byte);
+	pci_set8(dev, 0x48, 1 << 2 | 1 << 3);
 
 	/* RPR 5.11 Enable additional optional PCI clock */
-	word = pci_read_config16(dev, 0x64);
-	word |= 1 << 8;
-	pci_write_config16(dev, 0x64, word);
+	pci_set16(dev, 0x64, 1 << 8);
 
 	/* RPR 5.12 Enable One-Prefetch-Channel Mode */
-	dword = pci_read_config32(dev, 0x64);
-	dword |= 1 << 20;
-	pci_write_config32(dev, 0x64, dword);
+	pci_set32(dev, 0x64, 1 << 20);
 
 	/* RPR 5.13 Disable PCIB MSI Capability */
-	byte = pci_read_config8(dev, 0x40);
-	byte &= ~(1 << 3);
-	pci_write_config8(dev, 0x40, byte);
+	pci_clear8(dev, 0x40, (1 << 3));
 
 	/* rpr5.14 Adjusting CLKRUN# */
-	dword = pci_read_config32(dev, 0x64);
-	dword |= (1 << 15);
-	pci_write_config32(dev, 0x64, dword);
+	pci_set32(dev, 0x64, (1 << 15));
 }
 
 static struct pci_operations lops_pci = {
--- src/southbridge/amd/sb700/sb700_usb.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-14c970-sb700_usb.c	2010-10-05 03:03:01.985444222 +0200
@@ -38,9 +38,7 @@ static void usb_init(struct device *dev)
 	/* 6.1 Enable OHCI0-4 and EHCI Controllers */
 	device_t sm_dev;
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	byte = pci_read_config8(sm_dev, 0x68);
-	byte |= 0xFF;
-	pci_write_config8(sm_dev, 0x68, byte);
+	pci_set8(sm_dev, 0x68, 0xFF);
 
 	/* RPR 6.2 Enables the USB PME Event,Enable USB resume support */
 	byte = pm_ioread(0x61);
@@ -61,9 +59,7 @@ static void usb_init(struct device *dev)
 	pm_iowrite(0x65, byte);
 
 	/* RPR 6.10 Disable OHCI MSI Capability. */
-	word = pci_read_config16(dev, 0x40);
-	word |= (0x3 << 8);
-	pci_write_config16(dev, 0x40, word);
+	pci_set16(dev, 0x40, (0x3 << 8));
 }
 
 static void usb_init2(struct device *dev)
@@ -92,9 +88,7 @@ static void usb_init2(struct device *dev
 	write32(usb2_bar0 + 0xA4, dword);
 
 	/* RPR6.11 Disabling EHCI Advance Asynchronous Enhancement */
-	dword = pci_read_config32(dev, 0x50);
-	dword |= (1 << 28);
-	pci_write_config32(dev, 0x50, dword);
+	pci_set32(dev, 0x50, (1 << 28));
 
 	/* RPR 6.12 EHCI Advance PHY Power Savings */
 	/* RPR says it is just for A12. CIMM sets it when it is above A11. */
@@ -107,14 +101,10 @@ static void usb_init2(struct device *dev
 
 	/* RPR6.13 Enabling Fix for EHCI Controller Dirver Yellow Sign Issue */
 	/* RPR says it is just for A12. CIMM sets it when it is above A11. */
-	dword = pci_read_config32(dev, 0x50);
-	dword |= (1 << 20);
-	pci_write_config32(dev, 0x50, dword);
+	pci_set32(dev, 0x50, (1 << 20));
 
 	/* RPR6.15 EHCI Async Park Mode */
-	dword = pci_read_config32(dev, 0x50);
-	dword |= (1 << 23);
-	pci_write_config32(dev, 0x50, dword);
+	pci_set32(dev, 0x50, (1 << 23));
 
 	/* Each step below causes the linux crashes. Leave them here
 	 * for future debugging. */
--- src/southbridge/amd/rs690/rs690.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-1b8207-rs690.c	2010-10-05 03:03:02.317444546 +0200
@@ -40,9 +40,7 @@ void static rs690_config_misc_clk(device
 	/* u8 byte; */
 	struct bus pbus; /* fake bus for dev0 fun1 */
 
-	reg = pci_read_config32(nb_dev, 0x4c);
-	reg |= 1 << 0;
-	pci_write_config32(nb_dev, 0x4c, reg);
+	pci_set32(nb_dev, 0x4c, 1 << 0);
 
 	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
 	word &= 0xf00;
@@ -97,9 +95,7 @@ void static rs690_config_misc_clk(device
 	/* TODO: */
 #endif
 
-	reg = pci_read_config32(nb_dev, 0x4c);
-	reg &= ~(1 << 0);
-	pci_write_config32(nb_dev, 0x4c, reg);
+	pci_clear32(nb_dev, 0x4c, (1 << 0));
 
 	set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
 }
--- src/southbridge/amd/rs690/rs690_ht.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-abe400-rs690_ht.c	2010-10-05 03:03:02.649447540 +0200
@@ -56,18 +56,13 @@ static void pcie_init(struct device *dev
 	printk(BIOS_INFO, "pcie_init in rs690_ht.c\n");
 
 	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1 << 8);	/* System error enable */
-	dword |= (1 << 30);	/* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
 
 	/*
 	 * 1 is APIC enable
 	 * 18 is enable nb to accept A4 interrupt request from SB.
 	 */
-	dword = pci_read_config32(dev, 0x4C);
-	dword |= 1 << 1 | 1 << 18;	/* Clear possible errors */
-	pci_write_config32(dev, 0x4C, dword);
+	pci_set32(dev, 0x4C, 1 << 1 | 1 << 18);
 }
 
 static struct pci_operations lops_pci = {
--- src/southbridge/amd/rs690/rs690_pcie.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-2e7ec4-rs690_pcie.c	2010-10-05 03:03:02.861445658 +0200
@@ -114,10 +114,7 @@ static void pcie_init(struct device *dev
 	printk(BIOS_DEBUG, "pcie_init in rs690_pcie.c\n");
 
 	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1 << 8);	/* System error enable */
-	dword |= (1 << 30);	/* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
 }
 #endif
 
@@ -227,13 +224,9 @@ void rs690_gpp_sb_init(device_t nb_dev, 
 	set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 6);
 
 	/* SLOT_IMPLEMENTED in pcieConfig space */
-	reg8 = pci_read_config8(dev, 0x5b);
-	reg8 |= 1 << 0;
-	pci_write_config8(dev, 0x5b, reg8);
-
-	reg16 = pci_read_config16(dev, 0x5a);
-	reg16 |= 0x100;
-	pci_write_config16(dev, 0x5a, reg16);
+	pci_set8(dev, 0x5b, 1 << 0);
+
+	pci_set16(dev, 0x5a, 0x100);
 	nbmisc_write_index(nb_dev, 0x34, 0);
 
 	/* check compliance rpr step 2.1*/
@@ -307,9 +300,7 @@ void rs690_gpp_sb_init(device_t nb_dev, 
 	/* To eable L0s in the RS690 for the GPP port(s) */
 	set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
 	set_pcie_enable_bits(dev, 0xa0, 0xf << 8, 0x9 << 8);
-	reg16 = pci_read_config16(dev, 0x68);
-	reg16 |= 1 << 0;
-	pci_write_config16(dev, 0x68, reg16);
+	pci_set16(dev, 0x68, 1 << 0);
 
 	/* step 6d: ASPM L1 for the southbridge link */
 	/* To enalbe L1s in the southbridage*/
@@ -366,9 +357,7 @@ void pcie_config_misc_clk(device_t nb_de
 	u32 reg;
 	struct bus pbus; /* fake bus for dev0 fun1 */
 
-	reg = pci_read_config32(nb_dev, 0x4c);
-	reg |= 1 << 0;
-	pci_write_config32(nb_dev, 0x4c, reg);
+	pci_set32(nb_dev, 0x4c, 1 << 0);
 
 	if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
 		/* TXCLK Clock Gating */
@@ -394,8 +383,6 @@ void pcie_config_misc_clk(device_t nb_de
 		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
 	}
 
-	reg = pci_read_config32(nb_dev, 0x4c);
-	reg &= ~(1 << 0);
-	pci_write_config32(nb_dev, 0x4c, reg);
+	pci_clear32(nb_dev, 0x4c, (1 << 0));
 }
 #endif
--- src/southbridge/amd/rs690/rs690_gfx.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-393d56-rs690_gfx.c	2010-10-05 03:03:03.381443944 +0200
@@ -161,9 +161,7 @@ static void rs690_internal_gfx_enable(de
 	}
 
 	/* Set K8 MC for UMA, Family F. */
-	l_dword = pci_read_config32(k8_f2, 0xa0);
-	l_dword |= 0x2c;
-	pci_write_config32(k8_f2, 0xa0, l_dword);
+	pci_set32(k8_f2, 0xa0, 0x2c);
 	l_dword = pci_read_config32(k8_f2, 0x94);
 	l_dword &= 0xf0ffffff;
 	l_dword |= 0x07000000;
@@ -555,9 +553,7 @@ void rs690_gfx_init(device_t nb_dev, dev
 
 	/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM.
 	 * SLOT_IMPLEMENTED at PCIE_CAP */
-	reg16 = pci_read_config16(dev, 0x5a);
-	reg16 |= 0x100;
-	pci_write_config16(dev, 0x5a, reg16);
+	pci_set16(dev, 0x5a, 0x100);
 	printk(BIOS_INFO, "rs690_gfx_init step8.9.\n");
 
 	/* step 8.10 Setting this register to 0x1 will hide the Advanced Error Rporting Capabilities in the PCIE Brider.
--- src/southbridge/amd/rs780/rs780.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-261642-rs780.c	2010-10-05 03:03:04.125444235 +0200
@@ -37,9 +37,7 @@ void static rs780_config_misc_clk(device
 	u8 byte;
 	struct bus pbus; /* fake bus for dev0 fun1 */
 
-	reg = pci_read_config32(nb_dev, 0x4c);
-	reg |= 1 << 0;
-	pci_write_config32(nb_dev, 0x4c, reg);
+	pci_set32(nb_dev, 0x4c, 1 << 0);
 
 	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
 	word &= 0xf00;
@@ -100,9 +98,7 @@ void static rs780_config_misc_clk(device
 	/* TODO: */
 #endif
 
-	reg = pci_read_config32(nb_dev, 0x4c);
-	reg &= ~(1 << 0);
-	pci_write_config32(nb_dev, 0x4c, reg);
+	pci_clear32(nb_dev, 0x4c, (1 << 0));
 
 	set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
 }
@@ -126,17 +122,13 @@ static void rs780_nb_pci_table(device_t 
 
 	pci_write_config8(nb_dev, 0x4c, 0x42);
 
-	temp8 = pci_read_config8(nb_dev, 0x4e);
-	temp8 |= 0x05;
-	pci_write_config8(nb_dev, 0x4e, temp8);
+	pci_set8(nb_dev, 0x4e, 0x05);
 
 	temp32 = pci_read_config32(nb_dev, 0x4c);
 	printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32);
 
 	/* disable GFX debug. */
-	temp8 = pci_read_config8(nb_dev, 0x8d);
-	temp8 &= ~(1<<1);
-	pci_write_config8(nb_dev, 0x8d, temp8);
+	pci_clear8(nb_dev, 0x8d, (1 << 1));
 
 	/* set temporary NB TOM to 0x40000000. */
 	rs780_set_tom(nb_dev);
--- src/southbridge/amd/rs780/rs780_early_setup.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d508d3-rs780_early_setup.c	2010-10-05 03:03:04.681444087 +0200
@@ -391,19 +391,13 @@ static void fam10_optimization(void)
 	pci_write_config32(cpu_f0, 0x94, 0x00000000);
 
 	/* Table 8-15 */
-	val = pci_read_config32(cpu_f0, 0x68);
-	val |= 1 << 24;
-	pci_write_config32(cpu_f0, 0x68, val);
+	pci_set32(cpu_f0, 0x68, 1 << 24);
 
 	/* Table 8-16 */
-	val = pci_read_config32(cpu_f0, 0x84);
-	val &= ~(1 << 12);
-	pci_write_config32(cpu_f0, 0x84, val);
+	pci_clear32(cpu_f0, 0x84, (1 << 12));
 
 	/* Table 8-17 */
-	val = pci_read_config32(cpu_f2, 0x90);
-	val &= ~(1 << 10);
-	pci_write_config32(cpu_f2, 0x90, val);
+	pci_clear32(cpu_f2, 0x90, (1 << 10));
 
 	/* Table 8-18 */
 	pci_write_config32(cpu_f3, 0x6C, 0x60018051);
--- src/southbridge/amd/rs780/rs780_gfx.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-b26cc0-rs780_gfx.c	2010-10-05 03:03:05.701443884 +0200
@@ -319,9 +319,7 @@ static void internal_gfx_pci_dev_init(st
 	printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
 	     deviceid, vendorid);
 
-	command = pci_read_config16(dev, 0x04);
-	command |= 0x7;
-	pci_write_config16(dev, 0x04, command);
+	pci_set16(dev, 0x04, 0x7);
 
 	/* Clear vgainfo. */
 	bpointer = (unsigned char *) &vgainfo;
@@ -492,10 +490,7 @@ static void internal_gfx_pci_dev_init(st
 	/* GFX_InitLate. */
 	{
 		u8 temp8;
-		temp8 = pci_read_config8(dev, 0x4);
-		//temp8 &= ~1; /* CIM clears this bit. Strangely, I can'd. */
-		temp8 |= 1<<1|1<<2;
-		pci_write_config8(dev, 0x4, temp8);
+		pci_set8(dev, 0x4, 1 << 1 | 1 << 2);
 	}
 
 #ifdef DONT_TRUST_RESOURCE_ALLOCATION
--- src/southbridge/amd/rs780/rs780_ht.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-bbe852-rs780_ht.c	2010-10-05 03:03:07.833458349 +0200
@@ -56,18 +56,13 @@ static void pcie_init(struct device *dev
 	printk(BIOS_INFO, "pcie_init in rs780_ht.c\n");
 
 	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1 << 8);	/* System error enable */
-	dword |= (1 << 30);	/* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
 
 	/*
 	 * 1 is APIC enable
 	 * 18 is enable nb to accept A4 interrupt request from SB.
 	 */
-	dword = pci_read_config32(dev, 0x4C);
-	dword |= 1 << 1 | 1 << 18;	/* Clear possible errors */
-	pci_write_config32(dev, 0x4C, dword);
+	pci_set32(dev, 0x4C, 1 << 1 | 1 << 18);
 }
 
 static struct pci_operations lops_pci = {
--- src/southbridge/amd/cs5530/cs5530_enable_rom.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-5729bc-cs5530_enable_rom.c	2010-10-05 03:03:08.177448361 +0200
@@ -41,7 +41,5 @@ static void cs5530_enable_rom(void)
 	pci_write_config8(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
 
 	/* Set positive decode on ROM. */
-	reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
-	reg8 |= BIOS_ROM_POSITIVE_DECODE;
-	pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
+	pci_set8(dev, DECODE_CONTROL_REG2, BIOS_ROM_POSITIVE_DECODE);
 }
--- src/southbridge/amd/cs5536/cs5536_ide.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-08a7b3-cs5536_ide.c	2010-10-05 03:03:08.413453051 +0200
@@ -41,9 +41,7 @@ static void ide_init(struct device *dev)
 
 	// Enable the channel and Post Write Buffer
 	// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
-	ide_cfg = pci_read_config32(dev, IDE_CFG);
-	ide_cfg |= CHANEN | PWB;
-	pci_write_config32(dev, IDE_CFG, ide_cfg);
+	pci_set32(dev, IDE_CFG, CHANEN | PWB);
 }
 
 static struct device_operations ide_ops = {
--- src/southbridge/amd/amd8111/amd8111_early_ctrl.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-882ef8-amd8111_early_ctrl.c	2010-10-05 03:03:08.681451429 +0200
@@ -24,9 +24,7 @@ static void enable_cf9_x(unsigned sbbusn
 
 	dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI
 	/* enable cf9 */
-	byte = pci_read_config8(dev, 0x41);
-	byte |= (1<<6) | (1<<5);
-	pci_write_config8(dev, 0x41, byte);
+	pci_set8(dev, 0x41, (1 << 6) | (1 << 5));
 }
 
 static void enable_cf9(void)
--- src/southbridge/amd/amd8111/amd8111_acpi.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-71d21a-amd8111_acpi.c	2010-10-05 03:03:08.973450602 +0200
@@ -171,9 +171,7 @@ static void acpi_enable_resources(device
 	pci_dev_enable_resources(dev);
 
 	/* Enable the ACPI/SMBUS Bar */
-	byte = pci_read_config8(dev, 0x41);
-	byte |= (1 << 7);
-	pci_write_config8(dev, 0x41, byte);
+	pci_set8(dev, 0x41, (1 << 7));
 
 	/* Set the class code */
 	pci_write_config32(dev, 0x60, 0x06800000);
--- src/southbridge/amd/amd8111/amd8111_lpc.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-2f7778-amd8111_lpc.c	2010-10-05 03:03:09.433450711 +0200
@@ -32,9 +32,7 @@ static void lpc_init(struct device *dev)
 	int nmi_option;
 
 	/* IO APIC initialization */
-	byte = pci_read_config8(dev, 0x4B);
-	byte |= 1;
-	pci_write_config8(dev, 0x4B, byte);
+	pci_set8(dev, 0x4B, 1);
 	/* Don't rename IO APIC */
 	setup_ioapic(IO_APIC_ADDR, 0);
 
@@ -43,26 +41,17 @@ static void lpc_init(struct device *dev)
 	pci_write_config8(dev, 0x46, byte | (1<<0));
 
 	/* Enable 5Mib Rom window */
-	byte = pci_read_config8(dev, 0x43);
-	byte |= 0xc0;
-	pci_write_config8(dev, 0x43, byte);
+	pci_set8(dev, 0x43, 0xc0);
 
 	/* Enable Port 92 fast reset */
-	byte = pci_read_config8(dev, 0x41);
-	byte |= (1 << 5);
-	pci_write_config8(dev, 0x41, byte);
+	pci_set8(dev, 0x41, (1 << 5));
 
 	/* Enable Error reporting */
 	/* Set up sync flood detected */
-	byte = pci_read_config8(dev, 0x47);
-	byte |= (1 << 1);
-	pci_write_config8(dev, 0x47, byte);
+	pci_set8(dev, 0x47, (1 << 1));
 
 	/* Set up NMI on errors */
-	byte = pci_read_config8(dev, 0x40);
-	byte |= (1 << 1); /* clear PW2LPC error */
-	byte |= (1 << 6); /* clear LPCERR */
-	pci_write_config8(dev, 0x40, byte);
+	pci_set8(dev, 0x40, (1 << 1) | (1 << 6));
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
 	if (nmi_option) {
--- src/southbridge/amd/amd8111/amd8111_pci.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-722e40-amd8111_pci.c	2010-10-05 03:03:09.772444020 +0200
@@ -12,10 +12,7 @@ static void pci_init(struct device *dev)
 	uint32_t dword;
 
 	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* System error enable */
-	dword |= (7<<28); /* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (7 << 28));
 
 	/* System,Parity,timer,and abort error enable */
 	dword = pci_read_config32(dev, 0x3c);
--- src/southbridge/amd/amd8131/amd8131_bridge.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-e3782e-amd8131_bridge.c	2010-10-05 03:03:10.056443928 +0200
@@ -239,9 +239,7 @@ static unsigned int amd8131_scan_bus(str
 		bus->dev->enabled = 0;
 
 		/* Disable the PCI-X clocks */
-		pcix_misc = pci_read_config32(bus->dev, 0x40);
-		pcix_misc &= ~(0x1f << 16);
-		pci_write_config32(bus->dev, 0x40, pcix_misc);
+		pci_clear32(bus->dev, 0x40, (0x1f << 16));
 
 		return max;
 	}
@@ -281,9 +279,7 @@ static void amd8131_pcix_init(device_t d
 	int nmi_option;
 
 	/* Enable memory write and invalidate ??? */
-	byte = pci_read_config8(dev, 0x04);
-        byte |= 0x10;
-        pci_write_config8(dev, 0x04, byte);
+	pci_set8(dev, 0x04, 0x10);
 
 	/* Set drive strength */
 	word = pci_read_config16(dev, 0xe0);
@@ -300,9 +296,7 @@ static void amd8131_pcix_init(device_t d
 
 	/* Set discard unrequested prefetch data */
 	/* Errata #51 */
-	word = pci_read_config16(dev, 0x4c);
-        word |= 1;
-        pci_write_config16(dev, 0x4c, word);
+	pci_set16(dev, 0x4c, 1);
 
 	/* Set split transaction limits */
 	word = pci_read_config16(dev, 0xa8);
@@ -312,33 +306,23 @@ static void amd8131_pcix_init(device_t d
 
 	/* Set up error reporting, enable all */
 	/* system error enable */
-	dword = pci_read_config32(dev, 0x04);
-        dword |= (1<<8);
-        pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8));
 
 	/* system and error parity enable */
-	dword = pci_read_config32(dev, 0x3c);
-        dword |= (3<<16);
-        pci_write_config32(dev, 0x3c, dword);
+	pci_set32(dev, 0x3c, (3 << 16));
 
 	/* NMI enable */
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
 	if(nmi_option) {
-		dword = pci_read_config32(dev, 0x44);
-        	dword |= (1<<0);
-        	pci_write_config32(dev, 0x44, dword);
+		pci_set32(dev, 0x44, (1 << 0));
 	}
 
 	/* Set up CRC flood enable */
 	dword = pci_read_config32(dev, 0xc0);
 	if(dword) {  /* do device A only */
-		dword = pci_read_config32(dev, 0xc4);
-		dword |= (1<<1);
-		pci_write_config32(dev, 0xc4, dword);
-		dword = pci_read_config32(dev, 0xc8);
-		dword |= (1<<1);
-		pci_write_config32(dev, 0xc8, dword);
+		pci_set32(dev, 0xc4, (1 << 1));
+		pci_set32(dev, 0xc8, (1 << 1));
 	}
 	return;
 }
--- src/southbridge/amd/amd8132/amd8132_bridge.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-1dc0e4-amd8132_bridge.c	2010-10-05 03:03:10.700444328 +0200
@@ -240,14 +240,10 @@ static void amd8132_pcix_init(device_t d
 
 	/* Set up error reporting, enable all */
 	/* system error enable */
-	dword = pci_read_config32(dev, 0x04);
-        dword |= (1<<8);
-        pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8));
 
 	/* system and error parity enable */
-	dword = pci_read_config32(dev, 0x3c);
-        dword |= (3<<16);
-        pci_write_config32(dev, 0x3c, dword);
+	pci_set32(dev, 0x3c, (3 << 16));
 
         dword = pci_read_config32(dev, 0x40);
 //        dword &= ~(1<<31); /* WriteChainEnable */
@@ -267,21 +263,14 @@ static void amd8132_pcix_init(device_t d
 	dword |= (0x61<<24); //LPMARBCOUNT
         pci_write_config32(dev, 0x48, dword);
 
-        dword = pci_read_config32(dev, 0x4c);
-        dword |= (1<<6); //intial prefetch for memory read line request
-	dword |= (1<<9); //continuous prefetch Enable for memory read line request
-        pci_write_config32(dev, 0x4c, dword);
+        pci_set32(dev, 0x4c, (1 << 6) | (1 << 9));
 
 
        /* Disable Single-Bit-Error Correction [30] = 0 */
-        dword = pci_read_config32(dev, 0x70);
-        dword &= ~(1<<30);
-        pci_write_config32(dev, 0x70, dword);
+        pci_clear32(dev, 0x70, (1 << 30));
 
 	//link
-        dword = pci_read_config32(dev, 0xd4);
-        dword |= (0x5c<<16);
-        pci_write_config32(dev, 0xd4, dword);
+        pci_set32(dev, 0xd4, (0x5c << 16));
 
         /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
         dword = pci_read_config32(dev, 0xdc);
@@ -304,9 +293,7 @@ static void amd8132_pcix_init(device_t d
 
 	        if (chip_rev == 0x11) {
         	        /* [18] Clock Gate Enable = 1 */
-                	dword = pci_read_config32(dev, 0xf0);
-	                dword |= 0x00040008;
-        	        pci_write_config32(dev, 0xf0, dword);
+                	pci_set32(dev, 0xf0, 0x00040008);
 	        }
 
 	}
@@ -401,12 +388,8 @@ static void amd8132_ioapic_init(device_t
         if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
                 //for b1 b2
                 /* Errata #73 */
-                dword = pci_read_config32(dev, 0x80);
-                dword |= (0x1f<<5);
-                pci_write_config32(dev, 0x80, dword);
-                dword = pci_read_config32(dev, 0x88);
-                dword |= (0x1f<<5);
-                pci_write_config32(dev, 0x88, dword);
+                pci_set32(dev, 0x80, (0x1f << 5));
+                pci_set32(dev, 0x88, (0x1f << 5));
 
                 /* Errata #74 */
                 dword = pci_read_config32(dev, 0x7c);
--- src/southbridge/amd/amd8151/amd8151_agp3.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-b14863-amd8151_agp3.c	2010-10-05 03:03:11.360443934 +0200
@@ -40,14 +40,10 @@ static void agp3dev_enable(device_t dev)
 	uint32_t value;
 
 	/* AGP enable */
-	value = pci_read_config32(dev, 0xa8);
-	value |= (3<<8)|2; //AGP 8x
-	pci_write_config32(dev, 0xa8, value);
+	pci_set32(dev, 0xa8, (3 << 8) | 2);
 
 	/* enable BM and MEM */
-	value = pci_read_config32(dev, 0x4);
-	value |= 6;
-	pci_write_config32(dev, 0x4, value);
+	pci_set32(dev, 0x4, 6);
 #if 0
 	/* FIXME: should we add agp aperture base and size here ?
 	 * or it is done by AGP drivers */
--- src/southbridge/sis/sis966/sis966_early_setup_car.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-45d5bb-sis966_early_setup_car.c	2010-10-05 03:03:11.640444100 +0200
@@ -29,9 +29,7 @@ void sis966_early_pcie_setup(unsigned bu
 	int i;
 	device_t dev;
 	dev = PCI_DEV(busnx, devnx+1, 1);
-	dword = pci_read_config32(dev, 0xe4);
-	dword |= 0x3f0; // disable it at first
-	pci_write_config32(dev, 0xe4, dword);
+	pci_set32(dev, 0xe4, 0x3f0);
 
 	for(i=0; i<3; i++) {
 		tgio_ctrl = inl(anactrl_io_base + 0xcc);
@@ -53,9 +51,7 @@ void sis966_early_pcie_setup(unsigned bu
 //	wait 100us
 	udelay(100);
 
-	dword = pci_read_config32(dev, 0xe4);
-	dword &= ~(0x3f0); // enable
-	pci_write_config32(dev, 0xe4, dword);
+	pci_clear32(dev, 0xe4, (0x3f0));
 
 //	need to wait 100ms
 	mdelay(100);
--- src/southbridge/sis/sis966/sis966.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-18667b-sis966.c	2010-10-05 03:03:11.912444022 +0200
@@ -173,9 +173,7 @@ void sis966_enable(device_t dev)
 		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
 		if(!sm_dev) return;
 
-		final_reg = pci_read_config32(sm_dev, 0xe8);
-		final_reg &= ~0x0057cf00;
-		pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
+		pci_clear32(sm_dev, 0xe8, 0x0057cf00); //enable all at first
 	}
 
 	if (!dev->enabled) {
--- src/southbridge/sis/sis966/sis966_ide.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-617418-sis966_ide.c	2010-10-05 03:03:12.316443956 +0200
@@ -140,9 +140,7 @@ print_debug("IDE_INIT:---------->\n");
 	byte = 0x20 ; // Latency: 64-->32
 	pci_write_config8(dev, 0xd, byte);
 
-	dword = pci_read_config32(dev, 0xf8);
-	dword |= 12;
-	pci_write_config32(dev, 0xf8, dword);
+	pci_set32(dev, 0xf8, 12);
 #if CONFIG_PCI_ROM_RUN == 1
 	pci_dev_init(dev);
 #endif
--- src/southbridge/sis/sis966/sis966_lpc.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-a0d0a1-sis966_lpc.c	2010-10-05 03:03:12.736443792 +0200
@@ -63,9 +63,7 @@ static void lpc_common_init(device_t dev
 	uint32_t ioapic_base;
 
 	/* IO APIC initialization */
-	byte = pci_read_config8(dev, 0x74);
-	byte |= (1<<0); // enable APIC
-	pci_write_config8(dev, 0x74, byte);
+	pci_set8(dev, 0x74, (1 << 0));
 	ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
 
 	setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
@@ -130,9 +128,7 @@ static void lpc_init(device_t dev)
 
         /* Enable Error reporting */
         /* Set up sync flood detected */
-        byte = pci_read_config8(dev, 0x47);
-        byte |= (1 << 1);
-        pci_write_config8(dev, 0x47, byte);
+        pci_set8(dev, 0x47, (1 << 1));
 
         /* Set up NMI on errors */
         byte = inb(0x70); // RTC70
--- src/southbridge/sis/sis966/sis966_nic.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-965067-sis966_nic.c	2010-10-05 03:03:13.352452844 +0200
@@ -119,9 +119,7 @@ static void set_apc(struct device *dev)
     outl(inl(0xcfc)&0xffffffbf,0xcfc);
 
     // CFG reg0x73 bit=1, tell driver MAC Address load to APC
-    bTmp = pci_read_config8(dev, 0x73);
-    bTmp|=0x1;
-    pci_write_config8(dev, 0x73, bTmp);
+    pci_set8(dev, 0x73, 0x1);
 }
 
 //-----------------------------------------------------------------------------
--- src/southbridge/sis/sis966/sis966_pcie.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-5f2ece-sis966_pcie.c	2010-10-05 03:03:14.052452108 +0200
@@ -37,10 +37,7 @@ static void pcie_init(struct device *dev
 	uint32_t dword;
 
 	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* System error enable */
-	dword |= (1<<30); /* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
 
 }
 
--- src/southbridge/via/k8t890/k8t890_early_car.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-dfd8cb-k8t890_early_car.c	2010-10-05 03:03:14.316454049 +0200
@@ -54,9 +54,7 @@ u8 k8t890_early_setup_ht(void)
 	 */
 
 	pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
-	reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1);
-	reg |= 0x1;
-	pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
+	pci_set8(PCI_DEV(0, 0x0, 2), 0xa1, 0x1);
 
 	/* check if connected non coherent, initcomplete (find the SB on K8 side) */
 	ldtnr = 0;
--- src/southbridge/via/k8t890/k8t890_ctrl.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-2300c6-k8t890_ctrl.c	2010-10-05 03:03:14.660444167 +0200
@@ -120,17 +120,13 @@ static void vt8237r_vlink_init(struct de
 	pci_write_config8(dev, 0xb6, 0x88);
 	pci_write_config8(dev, 0xb7, 0x61);
 
-	reg = pci_read_config8(dev, 0xb4);
-	reg |= 0x11;
-	pci_write_config8(dev, 0xb4, reg);
+	pci_set8(dev, 0xb4, 0x11);
 
 	pci_write_config8(dev, 0xb9, 0x98);
 	pci_write_config8(dev, 0xba, 0x77);
 	pci_write_config8(dev, 0xbb, 0x11);
 
-	reg = pci_read_config8(dev, 0xb8);
-	reg |= 0x1;
-	pci_write_config8(dev, 0xb8, reg);
+	pci_set8(dev, 0xb8, 0x1);
 
 	pci_write_config8(dev, 0xb0, 0x06);
 	pci_write_config8(dev, 0xb1, 0x01);
--- src/southbridge/via/k8t890/k8t890_host.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-d31f46-k8t890_host.c	2010-10-05 03:03:14.940445492 +0200
@@ -37,19 +37,13 @@ static void host_init(struct device *dev
 	u8 reg;
 
 	/* AGP Capability Header Control */
-	reg = pci_read_config8(dev, 0x4d);
-	reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */
-	pci_write_config8(dev, 0x4d, reg);
+	pci_set8(dev, 0x4d, 0x20);
 
 	/* GD Output Stagger Delay */
-	reg = pci_read_config8(dev, 0x42);
-	reg |= 0x10; /* AD[31:16] with 1ns */
-	pci_write_config8(dev, 0x42, reg);
+	pci_set8(dev, 0x42, 0x10);
 
 	/* AGP Control */
-	reg = pci_read_config8(dev, 0xbc);
-	reg |= 0x20; /* AGP Read Snoop DRAM Post-Write Buffer */
-	pci_write_config8(dev, 0xbc, reg);
+	pci_set8(dev, 0xbc, 0x20);
 
 }
 
--- src/southbridge/via/k8t890/k8t890_traf_ctrl.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-6032a0-k8t890_traf_ctrl.c	2010-10-05 03:03:15.164444389 +0200
@@ -38,10 +38,7 @@ static void mmconfig_set_resources(devic
 		resource->flags |= IORESOURCE_STORED;
 		pci_write_config8(dev, K8T890_MMCONFIG_MBAR,
 				  (resource->base >> 28));
-		reg = pci_read_config8(dev, 0x60);
-		reg |= 0x3;
-		/* Enable MMCONFIG decoding. */
-		pci_write_config8(dev, 0x60, reg);
+		pci_set8(dev, 0x60, 0x3);
 	}
 	pci_dev_set_resources(dev);
 }
--- src/southbridge/via/k8t890/k8t890_bridge.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-1561fe-k8t890_bridge.c	2010-10-05 03:03:15.620463908 +0200
@@ -47,9 +47,7 @@ static void bridge_enable(struct device 
 	dump_south(dev);
 
 	/* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */
-	tmp = pci_read_config8(dev, PCI_COMMAND);
-	tmp &= ~0x3;
-	pci_write_config8(dev, PCI_COMMAND, tmp);
+	pci_clear8(dev, PCI_COMMAND, 0x3);
 
 }
 
--- src/southbridge/via/vt8231/vt8231_early_smbus.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-ad6c08-vt8231_early_smbus.c	2010-10-05 03:03:15.900448608 +0200
@@ -36,16 +36,12 @@ static void enable_smbus(void)
 	pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
 
 	// Enable SMBus
-	c = pci_read_config8(dev, 0xd2);
-	c |= 5;
-	pci_write_config8(dev, 0xd2, c);
+	pci_set8(dev, 0xd2, 5);
 
 	/* make it work for I/O ...
 	 */
 	dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0);
-	c = pci_read_config8(dev, 4);
-	c |= 1;
-	pci_write_config8(dev, 4, c);
+	pci_set8(dev, 4, 1);
 	print_debug_hex8(c);
 	print_debug(" is the comm register\n");
 
--- src/southbridge/via/vt8231/vt8231_ide.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-64e52f-vt8231_ide.c	2010-10-05 03:03:16.292455708 +0200
@@ -37,9 +37,7 @@ static void ide_init(struct device *dev)
 	printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
 
 	// Enable prefetch buffers
-	enables = pci_read_config8(dev, 0x41);
-	enables |= 0xf0;
-	pci_write_config8(dev, 0x41, enables);
+	pci_set8(dev, 0x41, 0xf0);
 
 	// Lower thresholds (cause award does it)
 	enables = pci_read_config8(dev, 0x43);
--- src/southbridge/via/vt8231/vt8231_lpc.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-9ae2cf-vt8231_lpc.c	2010-10-05 03:03:16.584447231 +0200
@@ -58,9 +58,7 @@ static void vt8231_init(struct device *d
 	printk(BIOS_DEBUG, "vt8231 init\n");
 
 	// enable the internal I/O decode
-	enables = pci_read_config8(dev, 0x6C);
-	enables |= 0x80;
-	pci_write_config8(dev, 0x6C, enables);
+	pci_set8(dev, 0x6C, 0x80);
 
 	// Map 4MB of FLASH into the address space
 	pci_write_config8(dev, 0x41, 0x7f);
@@ -72,28 +70,20 @@ static void vt8231_init(struct device *d
 	pci_write_config8(dev, 0x40, enables);
 
 	// Set 0x42 to 0xf0 to match Award bios
-	enables = pci_read_config8(dev, 0x42);
-	enables |= 0xf0;
-	pci_write_config8(dev, 0x42, enables);
+	pci_set8(dev, 0x42, 0xf0);
 
 	// Set bit 3 of 0x4a, to match award (dummy pci request)
-	enables = pci_read_config8(dev, 0x4a);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4a, enables);
+	pci_set8(dev, 0x4a, 0x08);
 
 	// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
-	enables = pci_read_config8(dev, 0x4f);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4f, enables);
+	pci_set8(dev, 0x4f, 0x08);
 
 	// Set 0x58 to 0x03 to match Award
 	pci_write_config8(dev, 0x58, 0x03);
 
 	// enable the ethernet/RTC
 	if (dev) {
-		enables = pci_read_config8(dev, 0x51);
-		enables |= 0x18;
-		pci_write_config8(dev, 0x51, enables);
+		pci_set8(dev, 0x51, 0x18);
 	}
 
 	// enable IDE, since Linux won't do it.
--- src/southbridge/via/vt8231/vt8231_nic.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-f4bf29-vt8231_nic.c	2010-10-05 03:03:16.888444556 +0200
@@ -15,9 +15,7 @@ static void nic_init(struct device *dev)
 	printk(BIOS_DEBUG, "Configuring VIA LAN\n");
 
 	/* We don't need stepping - though the device supports it */
-	byte = pci_read_config8(dev, PCI_COMMAND);
-	byte &= ~PCI_COMMAND_WAIT;
-	pci_write_config8(dev, PCI_COMMAND, byte);
+	pci_clear8(dev, PCI_COMMAND, PCI_COMMAND_WAIT);
 }
 
 static struct device_operations nic_ops = {
--- src/southbridge/via/vt8231/vt8231_early_serial.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-ddc598-vt8231_early_serial.c	2010-10-05 03:03:17.092446248 +0200
@@ -44,9 +44,7 @@ static void enable_vt8231_serial(void)
 	/* first, you have to enable the superio and superio config.
 	   put a 6 reg 80
 	*/
-	c = pci_read_config8(dev, 0x50);
-	c |= 6;
-	pci_write_config8(dev, 0x50, c);
+	pci_set8(dev, 0x50, 6);
 	outb(2, 0x80);
 	// now go ahead and set up com1.
 	// set address
--- src/southbridge/via/vt8231/vt8231.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-7b055d-vt8231.c	2010-10-05 03:03:17.288449909 +0200
@@ -17,9 +17,7 @@ static void keyboard_on(void)
 	unsigned char regval;
 
 	if (lpc_dev) {
-		regval = pci_read_config8(lpc_dev, 0x51);
-		regval |= 0x0f;
-		pci_write_config8(lpc_dev, 0x51, regval);
+		pci_set8(lpc_dev, 0x51, 0x0f);
 	}
 	pc_keyboard_init(0);
 }
--- src/southbridge/via/vt8235/vt8235_ide.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-8a9892-vt8235_ide.c	2010-10-05 03:03:17.476444953 +0200
@@ -37,9 +37,7 @@ static void ide_init(struct device *dev)
 	printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
 
 	// Enable prefetch buffers
-	enables = pci_read_config8(dev, 0x41);
-	enables |= 0xf0;
-	pci_write_config8(dev, 0x41, enables);
+	pci_set8(dev, 0x41, 0xf0);
 
 	// Lower thresholds (cause award does it)
 	enables = pci_read_config8(dev, 0x43);
--- src/southbridge/via/vt8235/vt8235_lpc.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-9b1de3-vt8235_lpc.c	2010-10-05 03:03:17.712444236 +0200
@@ -156,9 +156,7 @@ static void vt8235_init(struct device *d
 	printk(BIOS_DEBUG, "vt8235 init\n");
 
 	// enable the internal I/O decode
-	enables = pci_read_config8(dev, 0x6C);
-	enables |= 0x80;
-	pci_write_config8(dev, 0x6C, enables);
+	pci_set8(dev, 0x6C, 0x80);
 
 	// Map 4MB of FLASH into the address space
 	pci_write_config8(dev, 0x41, 0x7f);
@@ -166,32 +164,22 @@ static void vt8235_init(struct device *d
 	// Set bit 6 of 0x40, because Award does it (IO recovery time)
 	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
 	// interrupts can be properly marked as level triggered.
-	enables = pci_read_config8(dev, 0x40);
-	enables |= 0x45;
-	pci_write_config8(dev, 0x40, enables);
+	pci_set8(dev, 0x40, 0x45);
 
 	// Set 0x42 to 0xf0 to match Award bios
-	enables = pci_read_config8(dev, 0x42);
-	enables |= 0xf0;
-	pci_write_config8(dev, 0x42, enables);
+	pci_set8(dev, 0x42, 0xf0);
 
 	/* Set 0x58 to 0x03 to match Award */
 	pci_write_config8(dev, 0x58, 0x03);
 
 	/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
-	enables = pci_read_config8(dev, 0x4f);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4f, enables);
+	pci_set8(dev, 0x4f, 0x08);
 
 	// Set bit 3 of 0x4a, to match award (dummy pci request)
-	enables = pci_read_config8(dev, 0x4a);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4a, enables);
+	pci_set8(dev, 0x4a, 0x08);
 
 	// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
-	enables = pci_read_config8(dev, 0x4f);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4f, enables);
+	pci_set8(dev, 0x4f, 0x08);
 
 	// Set 0x58 to 0x03 to match Award
 	pci_write_config8(dev, 0x58, 0x03);
--- src/southbridge/via/vt8235/vt8235_nic.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d67e45-vt8235_nic.c	2010-10-05 03:03:18.172462278 +0200
@@ -15,9 +15,7 @@ static void nic_init(struct device *dev)
 	printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n");
 
 	/* We don't need stepping - though the device supports it */
-	byte = pci_read_config8(dev, PCI_COMMAND);
-	byte &= ~PCI_COMMAND_WAIT;
-	pci_write_config8(dev, PCI_COMMAND, byte);
+	pci_clear8(dev, PCI_COMMAND, PCI_COMMAND_WAIT);
 }
 
 static struct device_operations nic_ops = {
--- src/southbridge/via/vt8235/vt8235.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-c1383a-vt8235.c	2010-10-05 03:03:18.412453259 +0200
@@ -68,9 +68,7 @@ static void vt8235_enable(struct device 
 	setup_i8259();
 
 	/* enable RTC and ethernet */
-	regval = pci_read_config8(dev, 0x51);
-	regval |= 0x18;
-	pci_write_config8(dev, 0x51, regval);
+	pci_set8(dev, 0x51, 0x18);
 
 	/* turn on keyboard */
 	keyboard_on(dev);
@@ -78,9 +76,7 @@ static void vt8235_enable(struct device 
 	/* enable USB 1.1 & USB 2.0 - redundant really since we've
 	 * already been there - see note above
 	 */
-   	regval = pci_read_config8(dev, 0x50);
-	regval &= ~(0x36);
-	pci_write_config8(dev, 0x50, regval);
+   	pci_clear8(dev, 0x50, (0x36));
 }
 
 struct chip_operations southbridge_via_vt8235_ops = {
--- src/southbridge/via/vt8237r/vt8237r_sata.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-4cb8b6-vt8237r_sata.c	2010-10-05 03:03:18.656447930 +0200
@@ -70,9 +70,7 @@ static void sata_ii_init(struct device *
 	pci_write_config8(dev, 0x65, reg);
 
 	/* Set all manual termination 50ohm bits [2:0] and enable [4]. */
-	reg = pci_read_config8(dev, 0x6a);
-	reg |= 0xf;
-	pci_write_config8(dev, 0x6a, reg);
+	pci_set8(dev, 0x6a, 0xf);
 
 	/*
 	 * Analog PHY - gen2
--- src/southbridge/via/vt8237r/vt8237_ctrl.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-0dac21-vt8237_ctrl.c	2010-10-05 03:03:18.916444572 +0200
@@ -120,9 +120,7 @@ static void vt8237s_vlink_init(struct de
 	 */
 
 	/* disable auto disconnect */
-	reg = pci_read_config8(devfun7, 0x42);
-	reg &= ~0x4;
-	pci_write_config8(devfun7, 0x42, reg);
+	pci_clear8(devfun7, 0x42, 0x4);
 
 	/* NB part setup */
 	pci_write_config8(devfun7, 0xb5, 0x66);
@@ -148,17 +146,13 @@ static void vt8237s_vlink_init(struct de
 	reg &= ~0x4;
 	pci_write_config8(dev, 0xbd, reg);
 
-	reg = pci_read_config8(dev, 0xbc);
-	reg &= ~0x7;
-	pci_write_config8(dev, 0xbc, reg);
+	pci_clear8(dev, 0xbc, 0x7);
 
 	/* Program V-link 8X 8bit full duplex, parity enabled.  */
 	pci_write_config8(dev, 0x48, 0x23 | 0x80);
 
 	/* enable auto disconnect, for STPGNT and HALT */
-	reg = pci_read_config8(devfun7, 0x42);
-	reg |= 0x7;
-	pci_write_config8(devfun7, 0x42, reg);
+	pci_set8(devfun7, 0x42, 0x7);
 
 }
 
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-1ff234-vt8237r_early_smbus.c	2010-10-05 03:03:19.216444421 +0200
@@ -413,9 +413,7 @@ int vt8237_early_network_init(struct vt8
 		return 0;
 	}
 
-	tmp = pci_read_config32(dev, 0x5c);
-	tmp |= 0x08000000;	/* Enable ERDBG. */
-	pci_write_config32(dev, 0x5c, tmp);
+	pci_set32(dev, 0x5c, 0x08000000);
 
 	status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3);
 
--- src/southbridge/via/vt8237r/vt8237r_ide.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-8c360c-vt8237r_ide.c	2010-10-05 03:03:19.708445034 +0200
@@ -53,16 +53,12 @@ static void ide_init(struct device *dev)
 	enables &= 0xFA;
 	pci_write_config8(dev, 0x09, enables);
 
-	enables = pci_read_config8(dev, IDE_CONF_II);
-	enables &= ~0xc0;
-	pci_write_config8(dev, IDE_CONF_II, enables);
+	pci_clear8(dev, IDE_CONF_II, 0xc0);
 	enables = pci_read_config8(dev, IDE_CONF_II);
 	printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables);
 
 	/* Enable prefetch buffers. */
-	enables = pci_read_config8(dev, IDE_CONF_I);
-	enables |= 0xf0;
-	pci_write_config8(dev, IDE_CONF_I, enables);
+	pci_set8(dev, IDE_CONF_I, 0xf0);
 
 	/* Flush FIFOs at half. */
 	enables = pci_read_config8(dev, IDE_CONF_FIFO);
--- src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-90af6c-vt8237r_lpc.c	2010-10-05 03:03:19.984443978 +0200
@@ -257,22 +257,16 @@ static void vt8237r_init(struct device *
 	 * Setup to match EPIA default
 	 * PCS0# on Pin U1
 	 */
-	enables = pci_read_config8(dev, 0xe5);
-	enables |= 0x23;
-	pci_write_config8(dev, 0xe5, enables);
+	pci_set8(dev, 0xe5, 0x23);
 
 	/*
 	 * Enable Flash Write Access.
 	 * Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
 	 */
-	enables = pci_read_config8(dev, 0xe4);
-	enables |= 0x2B;
-	pci_write_config8(dev, 0xe4, enables);
+	pci_set8(dev, 0xe4, 0x2B);
 
 	/* Enables Extra RTC Ports */
-	enables = pci_read_config8(dev, 0x4E);
-	enables |= 0x80;
-	pci_write_config8(dev, 0x4E, enables);
+	pci_set8(dev, 0x4E, 0x80);
 
 #else
 	printk(BIOS_SPEW, "Entering vt8237r_init.\n");
@@ -287,9 +281,7 @@ static void vt8237r_init(struct device *
 #endif
 
 	/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
-	enables = pci_read_config8(dev, 0x4f);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4f, enables);
+	pci_set8(dev, 0x4f, 0x08);
 
 #if CONFIG_EPIA_VT8237R_INIT
 	/*
@@ -360,16 +352,12 @@ static void vt8237_common_init(struct de
 	u8 enables, byte;
 
 	/* Enable addr/data stepping. */
-	byte = pci_read_config8(dev, PCI_COMMAND);
-	byte |= PCI_COMMAND_WAIT;
-	pci_write_config8(dev, PCI_COMMAND, byte);
+	pci_set8(dev, PCI_COMMAND, PCI_COMMAND_WAIT);
 
 /* EPIA-N(L) Uses CN400 for BIOS Access */
 #if !CONFIG_EPIA_VT8237R_INIT
 	/* Enable the internal I/O decode. */
-	enables = pci_read_config8(dev, 0x6C);
-	enables |= 0x80;
-	pci_write_config8(dev, 0x6C, enables);
+	pci_set8(dev, 0x6C, 0x80);
 
 	/*
 	 * ROM decode
@@ -392,14 +380,10 @@ static void vt8237_common_init(struct de
 	 * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
 	 * that PCI interrupts can be properly marked as level triggered.
 	 */
-	enables = pci_read_config8(dev, 0x40);
-	enables |= 0x44;
-	pci_write_config8(dev, 0x40, enables);
+	pci_set8(dev, 0x40, 0x44);
 
 	/* Line buffer control */
-	enables = pci_read_config8(dev, 0x42);
-	enables |= 0xf8;
-	pci_write_config8(dev, 0x42, enables);
+	pci_set8(dev, 0x42, 0xf8);
 
 	/* Delay transaction control */
 	pci_write_config8(dev, 0x43, 0xb);
--- src/southbridge/via/vt8237r/vt8237r_usb.c	2010-10-01 09:27:00.000000000 +0200
+++ /tmp/cocci-output-5159-654cc6-vt8237r_usb.c	2010-10-05 03:03:20.516444329 +0200
@@ -49,9 +49,7 @@ static void usb_i_init(struct device *de
 	pci_write_config8(dev, 0x0d, 0x20);
 
 	/* Enable Sub Device ID Back Door and set Generic */
-	reg8 = pci_read_config8(dev, 0x42);
-	reg8 |= 0x10;
-	pci_write_config8(dev, 0x42, reg8);
+	pci_set8(dev, 0x42, 0x10);
 	pci_write_config16(dev, 0x2e, 0xAA07);
 	reg8 &= ~0x10;
 	pci_write_config8(dev, 0x42, reg8);
@@ -100,9 +98,7 @@ static void usb_ii_init(struct device *d
 	printk(BIOS_DEBUG, "Entering %s\n", __func__);
 
 	/* Set memory Write and Invalidate */
-	reg8 = pci_read_config8(dev, 0x04);
-	reg8 |= 0x10;
-	pci_write_config8(dev, 0x04, reg8);
+	pci_set8(dev, 0x04, 0x10);
 
 	/* Set Cache line Size and Latency Timer */
 	pci_write_config8(dev, 0x0c, 0x08);
--- src/southbridge/intel/pxhd/pxhd_bridge.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-c5f225-pxhd_bridge.c	2010-10-05 03:03:20.808444207 +0200
@@ -163,9 +163,7 @@ static void ioapic_init(device_t dev)
 {
 	uint32_t value, ioapic_base;
 	/* Enable bus mastering so IOAPICs work */
-	value = pci_read_config16(dev, PCI_COMMAND);
-	value |= PCI_COMMAND_MASTER;
-	pci_write_config16(dev, PCI_COMMAND, value);
+	pci_set16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
 	ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
--- src/southbridge/intel/i3100/i3100_lpc.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-b469a9-i3100_lpc.c	2010-10-05 03:03:21.144444042 +0200
@@ -393,14 +393,10 @@ static void i3100_lpc_enable_resources(d
 	pci_dev_enable_resources(dev);
 
 	/* Enable the ACPI bar */
-	acpi_cntl = pci_read_config8(dev, 0x44);
-	acpi_cntl |= (1 << 7);
-	pci_write_config8(dev, 0x44, acpi_cntl);
+	pci_set8(dev, 0x44, (1 << 7));
 
 	/* Enable the GPIO bar */
-	gpio_cntl = pci_read_config8(dev, 0x4c);
-	gpio_cntl |= (1 << 4);
-	pci_write_config8(dev, 0x4c, gpio_cntl);
+	pci_set8(dev, 0x4c, (1 << 4));
 
 	/* Enable the RCBA */
 	pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0));
--- src/southbridge/intel/i82371eb/i82371eb_early_pm.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-80af32-i82371eb_early_pm.c	2010-10-05 03:03:21.668447323 +0200
@@ -41,13 +41,9 @@ static void enable_pm(void)
 	pci_write_config32(dev, PMBA, PM_IO_BASE | 1);
 
 	/* Enable access to the PM I/O space. */
-	reg16 = pci_read_config16(dev, PCI_COMMAND);
-	reg16 |= PCI_COMMAND_IO;
-	pci_write_config16(dev, PCI_COMMAND, reg16);
+	pci_set16(dev, PCI_COMMAND, PCI_COMMAND_IO);
 
 	/* PM I/O Space Enable (PMIOSE). */
-	reg8 = pci_read_config8(dev, PMREGMISC);
-	reg8 |= PMIOSE;
-	pci_write_config8(dev, PMREGMISC, reg8);
+	pci_set8(dev, PMREGMISC, PMIOSE);
 }
 
--- src/southbridge/intel/i82371eb/i82371eb_early_smbus.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-e9dc9a-i82371eb_early_smbus.c	2010-10-05 03:03:21.880444089 +0200
@@ -44,14 +44,10 @@ static void enable_smbus(void)
 	pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
 
 	/* Enable the SMBus controller host interface. */
-	reg8 = pci_read_config8(dev, SMBHSTCFG);
-	reg8 |= SMB_HST_EN;
-	pci_write_config8(dev, SMBHSTCFG, reg8);
+	pci_set8(dev, SMBHSTCFG, SMB_HST_EN);
 
 	/* Enable access to the SMBus I/O space. */
-	reg16 = pci_read_config16(dev, PCI_COMMAND);
-	reg16 |= PCI_COMMAND_IO;
-	pci_write_config16(dev, PCI_COMMAND, reg16);
+	pci_set16(dev, PCI_COMMAND, PCI_COMMAND_IO);
 
 	/* Clear any lingering errors, so the transaction will run. */
 	outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);
--- src/southbridge/intel/i82801ax/i82801ax_watchdog.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-8fad66-i82801ax_watchdog.c	2010-10-05 03:03:22.132444328 +0200
@@ -35,9 +35,7 @@ void watchdog_off(void)
 	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 
 	/* Enable I/O space. */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Get TCO base. */
 	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
--- src/southbridge/intel/i82801ax/i82801ax_pci.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-c63a14-i82801ax_pci.c	2010-10-05 03:03:22.384443905 +0200
@@ -29,13 +29,9 @@ static void pci_init(struct device *dev)
 	uint16_t reg16;
 
 	/* Clear system errors */
-	reg16 = pci_read_config16(dev, 0x06);
-	reg16 |= 0xf900;	/* Clear possible errors */
-	pci_write_config16(dev, 0x06, reg16);
-
-	reg16 = pci_read_config16(dev, 0x1e);
-	reg16 |= 0xf800;	/* Clear possible errors */
-	pci_write_config16(dev, 0x1e, reg16);
+	pci_set16(dev, 0x06, 0xf900);
+
+	pci_set16(dev, 0x1e, 0xf800);
 }
 
 static struct device_operations pci_ops = {
--- src/southbridge/intel/i82801bx/i82801bx_watchdog.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-3c7627-i82801bx_watchdog.c	2010-10-05 03:03:22.632444196 +0200
@@ -35,9 +35,7 @@ void watchdog_off(void)
 	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 
 	/* Enable I/O space. */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Get TCO base. */
 	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
--- src/southbridge/intel/i82801bx/i82801bx_pci.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-e6dfb6-i82801bx_pci.c	2010-10-05 03:03:22.880444398 +0200
@@ -29,13 +29,9 @@ static void pci_init(struct device *dev)
 	uint16_t reg16;
 
 	/* Clear system errors */
-	reg16 = pci_read_config16(dev, 0x06);
-	reg16 |= 0xf900;	/* Clear possible errors */
-	pci_write_config16(dev, 0x06, reg16);
-
-	reg16 = pci_read_config16(dev, 0x1e);
-	reg16 |= 0xf800;	/* Clear possible errors */
-	pci_write_config16(dev, 0x1e, reg16);
+	pci_set16(dev, 0x06, 0xf900);
+
+	pci_set16(dev, 0x1e, 0xf800);
 }
 
 static struct device_operations pci_ops = {
--- src/southbridge/intel/i82801dx/i82801dx_smihandler.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-7439bd-i82801dx_smihandler.c	2010-10-05 03:03:23.152444072 +0200
@@ -270,9 +270,7 @@ static void busmaster_disable_on_bus(int
                                 continue;
 
                         /* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
+                        pci_clear32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
                         /* If this is a bridge, then follow it. */
                         hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -332,9 +330,7 @@ static void southbridge_smi_sleep(unsign
 		 * to "OFF" before entering S5.
 		 */
 		if (s5pwr == MAINBOARD_POWER_KEEP) {
-			reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-			reg8 |= 1;
-			pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+			pci_set8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, 1);
 		}
 
 		/* also iterates over all bridges on bus 0 */
--- src/southbridge/intel/i82801dx/i82801dx_pci.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-0aa12e-i82801dx_pci.c	2010-10-05 03:03:24.120444637 +0200
@@ -29,10 +29,7 @@ static void pci_init(struct device *dev)
 	/* Enable pci error detecting */
 	uint32_t dword;
 	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1 << 8);	/* SERR# Enable */
-	dword |= (1 << 6);	/* Parity Error Response */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 6));
 }
 
 static struct device_operations pci_ops = {
--- src/southbridge/intel/i82801ex/i82801ex_lpc.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-f4a23b-i82801ex_lpc.c	2010-10-05 03:03:24.380443784 +0200
@@ -243,12 +243,8 @@ static void lpc_init(struct device *dev)
 	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 
 	/* IO APIC initialization */
-	value = pci_read_config32(dev, 0xd0);
-	value |= (1 << 8)|(1<<7)|(1<<1);
-	pci_write_config32(dev, 0xd0, value);
-	value = pci_read_config32(dev, 0xd4);
-	value |= (1<<1);
-	pci_write_config32(dev, 0xd4, value);
+	pci_set32(dev, 0xd0, (1 << 8) | (1 << 7) | (1 << 1));
+	pci_set32(dev, 0xd4, (1 << 1));
 	setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
 
 	i82801ex_enable_serial_irqs(dev);
@@ -327,14 +323,10 @@ static void i82801ex_lpc_enable_resource
 	pci_dev_enable_resources(dev);
 
 	/* Enable the ACPI bar */
-	acpi_cntl = pci_read_config8(dev, 0x44);
-	acpi_cntl |= (1 << 4);
-	pci_write_config8(dev, 0x44, acpi_cntl);
+	pci_set8(dev, 0x44, (1 << 4));
 
 	/* Enable the GPIO bar */
-	gpio_cntl = pci_read_config8(dev, 0x5c);
-	gpio_cntl |= (1 << 4);
-	pci_write_config8(dev, 0x5c, gpio_cntl);
+	pci_set8(dev, 0x5c, (1 << 4));
 }
 
 static struct pci_operations lops_pci = {
--- src/southbridge/intel/i82801ex/i82801ex_pci.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-3e82cd-i82801ex_pci.c	2010-10-05 03:03:24.984444686 +0200
@@ -10,9 +10,7 @@ static void pci_init(struct device *dev)
 	uint16_t word;
 
 	/* Clear system errors */
-	word = pci_read_config16(dev, 0x06);
-	word |= 0xf900; /* Clear possible errors */
-	pci_write_config16(dev, 0x06, word);
+	pci_set16(dev, 0x06, 0xf900);
 
 #if 0
 	/* System error enable */
@@ -23,9 +21,7 @@ static void pci_init(struct device *dev)
 	pci_write_config32(dev, 0x04, dword);
 #endif
 
-	word = pci_read_config16(dev, 0x1e);
-	word |= 0xf800; /* Clear possible errors */
-	pci_write_config16(dev, 0x1e, word);
+	pci_set16(dev, 0x1e, 0xf800);
 }
 
 static struct device_operations pci_ops  = {
--- src/southbridge/intel/i82801ex/i82801ex_watchdog.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-7f0346-i82801ex_watchdog.c	2010-10-05 03:03:25.236445468 +0200
@@ -12,9 +12,7 @@ void watchdog_off(void)
 	/* turn off the ICH5 watchdog */
         dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
         /* Enable I/O space */
-        value = pci_read_config16(dev, 0x04);
-        value |= (1 << 10);
-        pci_write_config16(dev, 0x04, value);
+        pci_set16(dev, 0x04, (1 << 10));
         /* Get TCO base */
         base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
         /* Disable the watchdog timer */
--- src/southbridge/intel/i82801gx/i82801gx_azalia.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-8eb164-i82801gx_azalia.c	2010-10-05 03:03:25.488443725 +0200
@@ -266,9 +266,7 @@ static void azalia_init(struct device *d
 
 	// TODO Actually check if we're AC97 or HDA instead of hardcoding this
 	// here, in devicetree.cb and/or romstage.c.
-	reg8 = pci_read_config8(dev, 0x40);
-	reg8 |= (1 << 3); // Clear Clock Detect Bit
-	pci_write_config8(dev, 0x40, reg8);
+	pci_set8(dev, 0x40, (1 << 3));
 	reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
 	pci_write_config8(dev, 0x40, reg8);
 	reg8 |= (1 << 2); // Enable clock detection
@@ -278,13 +276,9 @@ static void azalia_init(struct device *d
 	printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
 
 	//
-	reg8 = pci_read_config8(dev, 0x40); // Audio Control
-	reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
-	pci_write_config8(dev, 0x40, reg8);
+	pci_set8(dev, 0x40, 1);
 
-	reg8 = pci_read_config8(dev, 0x4d); // Docking Status
-	reg8 &= ~(1 << 7); // Docking not supported
-	pci_write_config8(dev, 0x4d, reg8);
+	pci_clear8(dev, 0x4d, (1 << 7));
 #if 0
 	/* Set routing pin */
 	pci_write_config32(dev, 0xf8, 0x0);
--- src/southbridge/intel/i82801gx/i82801gx_watchdog.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-4e9f54-i82801gx_watchdog.c	2010-10-05 03:03:26.032443963 +0200
@@ -33,9 +33,7 @@ void watchdog_off(void)
 	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 
 	/* Enable I/O space. */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Get TCO base. */
 	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
--- src/southbridge/intel/i82801gx/i82801gx_pcie.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-d3824a-i82801gx_pcie.c	2010-10-05 03:03:26.284444060 +0200
@@ -31,9 +31,7 @@ static void pci_init(struct device *dev)
 	printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
 
 	/* Enable Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	pci_set32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
 	/* Set Cache Line Size to 0x10 */
 	// This has no effect but the OS might expect it
@@ -46,14 +44,10 @@ static void pci_init(struct device *dev)
 	pci_write_config16(dev, 0x3e, reg16);
 
 	/* Enable IO xAPIC on this PCIe port */
-	reg32 = pci_read_config32(dev, 0xd8);
-	reg32 |= (1 << 7);
-	pci_write_config32(dev, 0xd8, reg32);
+	pci_set32(dev, 0xd8, (1 << 7));
 
 	/* Enable Backbone Clock Gating */
-	reg32 = pci_read_config32(dev, 0xe1);
-	reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
-	pci_write_config32(dev, 0xe1, reg32);
+	pci_set32(dev, 0xe1, (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
 
 #if CONFIG_MMCONF_SUPPORT
 	/* Set VC0 transaction class */
@@ -71,9 +65,7 @@ static void pci_init(struct device *dev)
 #endif
 	/* Enable common clock configuration */
 	// Are there cases when we don't want that?
-	reg16 = pci_read_config16(dev, 0x50);
-	reg16 |= (1 << 6);
-	pci_write_config16(dev, 0x50, reg16);
+	pci_set16(dev, 0x50, (1 << 6));
 
 #ifdef EVEN_MORE_DEBUG
 	reg32 = pci_read_config32(dev, 0x20);
--- src/southbridge/intel/i82801gx/i82801gx_sata.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-39ee02-i82801gx_sata.c	2010-10-05 03:03:26.660443835 +0200
@@ -50,9 +50,7 @@ static void sata_init(struct device *dev
 		/* No AHCI: clear AHCI base */
 		pci_write_config32(dev, 0x24, 0x00000000);
 		/* And without AHCI BAR no memory decoding */
-		reg16 = pci_read_config16(dev, PCI_COMMAND);
-		reg16 &= ~PCI_COMMAND_MEMORY;
-		pci_write_config16(dev, PCI_COMMAND, reg16);
+		pci_clear16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 
 		pci_write_config8(dev, 0x09, 0x80);
 
@@ -120,9 +118,7 @@ static void sata_init(struct device *dev
 		pci_write_config32(dev, 0x24, 0x00000000);
 
 		/* And without AHCI BAR no memory decoding */
-		reg16 = pci_read_config16(dev, PCI_COMMAND);
-		reg16 &= ~PCI_COMMAND_MEMORY;
-		pci_write_config16(dev, PCI_COMMAND, reg16);
+		pci_clear16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 
 		/* Native mode capable on both primary and secondary (0xa)
 		 * or'ed with enabled (0x50) = 0xf
@@ -176,9 +172,7 @@ static void sata_init(struct device *dev
 	pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
 
 	/* Sata Initialization Register */
-	reg32 = pci_read_config32(dev, 0x94);
-	reg32 |= (1 << 30); // due to some bug
-	pci_write_config32(dev, 0x94, reg32);
+	pci_set32(dev, 0x94, (1 << 30));
 }
 
 static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
--- src/southbridge/intel/i82801gx/i82801gx_lpc.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-4d4f8f-i82801gx_lpc.c	2010-10-05 03:03:27.136444057 +0200
@@ -273,9 +273,7 @@ static void i82801gx_configure_cstates(d
 {
 	u8 reg8;
 
-	reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
-	reg8 |= (1 << 4) | (1 << 3) | (1 << 2);	// Enable Popup & Popdown
-	pci_write_config8(dev, 0xa9, reg8);
+	pci_set8(dev, 0xa9, (1 << 4) | (1 << 3) | (1 << 2));
 
 	// Set Deeper Sleep configuration to recommended values
 	reg8 = pci_read_config8(dev, 0xaa);
--- src/southbridge/intel/i82801gx/i82801gx_pci.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-b0a77b-i82801gx_pci.c	2010-10-05 03:03:27.844446750 +0200
@@ -30,18 +30,13 @@ static void pci_init(struct device *dev)
 	u8 reg8;
 
 	/* Enable Bus Master */
-	reg16 = pci_read_config16(dev, PCI_COMMAND);
-	reg16 |= PCI_COMMAND_MASTER;
-	pci_write_config16(dev, PCI_COMMAND, reg16);
+	pci_set16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
 	/* This device has no interrupt */
 	pci_write_config8(dev, INTR, 0xff);
 
 	/* disable parity error response and SERR */
-	reg16 = pci_read_config16(dev, BCTRL);
-	reg16 &= ~(1 << 0);
-	reg16 &= ~(1 << 1);
-	pci_write_config16(dev, BCTRL, reg16);
+	pci_clear16(dev, BCTRL, ((1 << 0) | (1 << 1)));
 
 	/* Master Latency Count must be set to 0x04! */
 	reg8 = pci_read_config8(dev, SMLT);
--- src/southbridge/intel/i82801gx/i82801gx_usb.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-34ef54-i82801gx_usb.c	2010-10-05 03:03:28.096448394 +0200
@@ -39,9 +39,7 @@ static void usb_init(struct device *dev)
 	pci_write_config8(dev, 0xca, 0x00);
 
 	// Yes. Another Erratum
-	reg8 = pci_read_config8(dev, 0xca);
-	reg8 |= (1 << 0);
-	pci_write_config8(dev, 0xca, reg8);
+	pci_set8(dev, 0xca, (1 << 0));
 
 	printk(BIOS_DEBUG, "done.\n");
 }
--- src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-83ad10-i82801gx_usb_ehci.c	2010-10-05 03:03:28.312444949 +0200
@@ -34,14 +34,9 @@ static void usb_ehci_init(struct device 
 	u8 reg8;
 
 	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	reg32 |= PCI_COMMAND_SERR;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
-
-	reg32 = pci_read_config32(dev, 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(dev, 0xdc, reg32);
+	pci_set32(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
+
+	pci_set32(dev, 0xdc, (1 << 31) | (1 << 27));
 
 	reg32 = pci_read_config32(dev, 0xfc);
 	reg32 &= ~(3 << 2);
@@ -55,9 +50,7 @@ static void usb_ehci_init(struct device 
 	write32(base + 0x24, reg32);
 
 	/* workaround */
-	reg8 = pci_read_config8(dev, 0x84);
-	reg8 |= (1 << 4);
-	pci_write_config8(dev, 0x84, reg8);
+	pci_set8(dev, 0x84, (1 << 4));
 
 	printk(BIOS_DEBUG, "done.\n");
 }
--- src/southbridge/intel/i82801gx/i82801gx.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-12c78a-i82801gx.c	2010-10-05 03:03:28.548446943 +0200
@@ -28,9 +28,7 @@ void i82801gx_enable(device_t dev)
 	u32 reg32;
 
 	/* Enable SERR */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_SERR;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	pci_set32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 }
 
 struct chip_operations southbridge_intel_i82801gx_ops = {
--- src/southbridge/intel/i82801gx/i82801gx_smihandler.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-0ceffd-i82801gx_smihandler.c	2010-10-05 03:03:28.724443949 +0200
@@ -263,9 +263,7 @@ static void busmaster_disable_on_bus(int
                                 continue;
 
                         /* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
+                        pci_clear32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
                         /* If this is a bridge, then follow it. */
                         hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
--- src/southbridge/intel/esb6300/esb6300_lpc.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-05f5bd-esb6300_lpc.c	2010-10-05 03:03:29.488443816 +0200
@@ -238,10 +238,7 @@ static void lpc_init(struct device *dev)
 	pci_write_config32(dev, 0x58, 0x00001181);
 
 	/* IO APIC initialization */
-	value = pci_read_config32(dev, 0xd0);
-	value |= (1 << 8)|(1<<7);
-	value |= (6 << 0)|(1<<13)|(1<<11);
-	pci_write_config32(dev, 0xd0, value);
+	pci_set32(dev, 0xd0, (1 << 8) | (1 << 7) | (6 << 0) | (1 << 13) | (1 << 11));
 	setup_ioapic(0xfec00000, 0); // don't rename IO APIC ID
 
 	/* disable reset timer */
@@ -343,14 +340,10 @@ static void esb6300_lpc_enable_resources
 	pci_dev_enable_resources(dev);
 
 	/* Enable the ACPI bar */
-	acpi_cntl = pci_read_config8(dev, 0x44);
-	acpi_cntl |= (1 << 4);
-	pci_write_config8(dev, 0x44, acpi_cntl);
+	pci_set8(dev, 0x44, (1 << 4));
 
 	/* Enable the GPIO bar */
-	gpio_cntl = pci_read_config8(dev, 0x5c);
-	gpio_cntl |= (1 << 4);
-	pci_write_config8(dev, 0x5c, gpio_cntl);
+	pci_set8(dev, 0x5c, (1 << 4));
 }
 
 static struct pci_operations lops_pci = {
--- src/southbridge/intel/esb6300/esb6300_pci.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-33667a-esb6300_pci.c	2010-10-05 03:03:29.956446794 +0200
@@ -11,13 +11,9 @@ static void pci_init(struct device *dev)
 	uint16_t word;
 
 	/* Clear system errors */
-	word = pci_read_config16(dev, 0x06);
-	word |= 0xf900; /* Clear possible errors */
-	pci_write_config16(dev, 0x06, word);
+	pci_set16(dev, 0x06, 0xf900);
 
-	word = pci_read_config16(dev, 0x1e);
-	word |= 0xf800; /* Clear possible errors */
-	pci_write_config16(dev, 0x1e, word);
+	pci_set16(dev, 0x1e, 0xf800);
 }
 
 static struct device_operations pci_ops  = {
--- src/southbridge/intel/esb6300/esb6300_pic.c	2010-10-01 09:27:02.000000000 +0200
+++ /tmp/cocci-output-5159-3030e4-esb6300_pic.c	2010-10-05 03:03:30.160444351 +0200
@@ -15,9 +15,7 @@ static void pic_init(struct device *dev)
 	uint16_t word;
 
 	/* Clear system errors */
-	word = pci_read_config16(dev, 0x06);
-	word |= 0xf900; /* Clear possible errors */
-	pci_write_config16(dev, 0x06, word);
+	pci_set16(dev, 0x06, 0xf900);
 
 	/* enable interrupt lines */
 	pci_write_config8(dev, 0x3c, 0xff);
--- src/southbridge/broadcom/bcm21000/bcm21000_pcie.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-2b6d05-bcm21000_pcie.c	2010-10-05 03:03:30.384446661 +0200
@@ -36,15 +36,10 @@ static void pcie_init(struct device *dev
 	printk(BIOS_DEBUG, "PCIE enable.... dev= %s\n",dev_path(dev));
 
 	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* System error enable */
-	dword |= (1<<30); /* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
 
 	/* enable MSI on PCIE: */
-	msicap = pci_read_config32(dev, 0xa0);
-	msicap |= (1<<16); /* enable MSI*/
-	pci_write_config32(dev, 0xa0, msicap);
+	pci_set32(dev, 0xa0, (1 << 16));
 }
 
 static struct pci_operations lops_pci = {
--- src/southbridge/broadcom/bcm5780/bcm5780_pcie.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d13a97-bcm5780_pcie.c	2010-10-05 03:03:30.620444263 +0200
@@ -16,10 +16,7 @@ static void pcie_init(struct device *dev
 	uint32_t dword;
 
 	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* System error enable */
-	dword |= (1<<30); /* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
 
 }
 
--- src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d20bc7-bcm5785_early_setup.c	2010-10-05 03:03:30.832444207 +0200
@@ -16,16 +16,10 @@ static void bcm5785_enable_lpc(void)
         dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
 
         /* LPC Control 0 */
-        byte = pci_read_config8(dev, 0x44);
-        /* Serial 0 */
-        byte |= (1<<6);
-        pci_write_config8(dev, 0x44, byte);
+        pci_set8(dev, 0x44, (1 << 6));
 
         /* LPC Control 4 */
-        byte = pci_read_config8(dev, 0x48);
-        /* superio port 0x2e/4e enable */
-        byte |=(1<<1)|(1<<0);
-        pci_write_config8(dev, 0x48, byte);
+        pci_set8(dev, 0x48, (1 << 1) | (1 << 0));
 }
 
 static void bcm5785_enable_wdt_port_cf9(void)
@@ -163,9 +157,7 @@ static void bcm5785_early_setup(void)
         dword |= /* (1<<27)|*/(1<<14); // IDE enable
         pci_write_config32(dev, 0x64, dword);
 
-        byte = pci_read_config8(dev, 0x84);
-        byte |= (1<<0); // SATA enable
-        pci_write_config8(dev, 0x84, byte);
+        pci_set8(dev, 0x84, (1 << 0));
 
 // WDT and cf9 for later in coreboot_ram to call hard_reset
         bcm5785_enable_wdt_port_cf9();
@@ -175,30 +167,20 @@ static void bcm5785_early_setup(void)
 
 // IDE related
 	//F0
-        byte = pci_read_config8(dev, 0x4e);
-        byte |= (1<<4); //enable IDE ext regs
-        pci_write_config8(dev, 0x4e, byte);
+        pci_set8(dev, 0x4e, (1 << 4));
 
 	//F1
         dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
-        byte = pci_read_config8(dev, 0x48);
-        byte &= ~1; // disable pri channel
-        pci_write_config8(dev, 0x48, byte);
+        pci_clear8(dev, 0x48, 1);
         pci_write_config8(dev, 0xb0, 0x01);
         pci_write_config8(dev, 0xb2, 0x02);
-        byte = pci_read_config8(dev, 0x06);
-        byte |= (1<<4); // so b0, b2 can not be changed from now
-        pci_write_config8(dev, 0x06, byte);
-        byte = pci_read_config8(dev, 0x49);
-        byte |= 1; // enable second channel
-        pci_write_config8(dev, 0x49, byte);
+        pci_set8(dev, 0x06, (1 << 4));
+        pci_set8(dev, 0x49, 1);
 
 	//F2
         dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
 
-        byte = pci_read_config8(dev, 0x40);
-        byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
-        pci_write_config8(dev, 0x40, byte);
+        pci_set8(dev, 0x40, (1 << 3) | (1 << 2));
 
         pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
 
--- src/southbridge/broadcom/bcm5785/bcm5785_usb.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-a915e7-bcm5785_usb.c	2010-10-05 03:03:31.176444750 +0200
@@ -14,9 +14,7 @@ static void usb_init(struct device *dev)
 {
         uint32_t dword;
 
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<2)|(1<<1)|(1<<0);
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 2) | (1 << 1) | (1 << 0));
 
 	pci_write_config8(dev, 0x41, 0x00); // Serversworks said
 
--- src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-c6c0de-bcm5785_enable_rom.c	2010-10-05 03:03:31.464454519 +0200
@@ -8,7 +8,5 @@ static void bcm5785_enable_rom(void)
 	addr = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
 
 	/* Set the 4MB enable bit bit */
-	byte = pci_read_config8(addr, 0x41);
-	byte |= 0x0e;
-	pci_write_config8(addr, 0x41, byte);
+	pci_set8(addr, 0x41, 0x0e);
 }
--- src/southbridge/broadcom/bcm5785/bcm5785_sata.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-66c2c6-bcm5785_sata.c	2010-10-05 03:03:31.688446517 +0200
@@ -22,9 +22,7 @@ static void sata_init(struct device *dev
 	int i;
 
 	if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
-		byte = pci_read_config8(dev, 0x78);
-		byte |= (1<<7);
-        	pci_write_config8(dev, 0x78, byte);
+		pci_set8(dev, 0x78, (1 << 7));
 
 	        res = find_resource(dev, 0x24);
                 mmio_base = res->base;
--- src/southbridge/nvidia/ck804/ck804_enable_rom.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-4aba10-ck804_enable_rom.c	2010-10-05 03:03:31.964459260 +0200
@@ -19,7 +19,5 @@ static void ck804_enable_rom(void)
 	addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0);
 
 	/* Set the 4MB enable bit. */
-	byte = pci_read_config8(addr, 0x88);
-	byte |= 0x80;
-	pci_write_config8(addr, 0x88, byte);
+	pci_set8(addr, 0x88, 0x80);
 }
--- src/southbridge/nvidia/ck804/ck804_ide.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-dfde00-ck804_ide.c	2010-10-05 03:03:32.192460753 +0200
@@ -41,9 +41,7 @@ static void ide_init(struct device *dev)
 	byte = 0x20;		/* Latency: 64 --> 32 */
 	pci_write_config8(dev, 0xd, byte);
 
-	dword = pci_read_config32(dev, 0xf8);
-	dword |= 12;
-	pci_write_config32(dev, 0xf8, dword);
+	pci_set32(dev, 0xf8, 12);
 
 #if CONFIG_PCI_ROM_RUN == 1
 	pci_dev_init(dev);
--- src/southbridge/nvidia/ck804/ck804_lpc.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-c9b565-ck804_lpc.c	2010-10-05 03:03:32.464444184 +0200
@@ -42,17 +42,13 @@ static void lpc_common_init(device_t dev
 	uint32_t dword;
 
 	/* I/O APIC initialization */
-	byte = pci_read_config8(dev, 0x74);
-	byte |= (1 << 0);	/* Enable APIC. */
-	pci_write_config8(dev, 0x74, byte);
+	pci_set8(dev, 0x74, (1 << 0));
 	dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1);	/* 0x14 */
 
 	setup_ioapic(dword, 0); // Don't rename IOAPIC ID
 
 #if 1
-	dword = pci_read_config32(dev, 0xe4);
-	dword |= (1 << 23);
-	pci_write_config32(dev, 0xe4, dword);
+	pci_set32(dev, 0xe4, (1 << 23));
 #endif
 }
 
@@ -154,9 +150,7 @@ static void lpc_init(device_t dev)
 
 	/* Enable Error reporting. */
 	/* Set up sync flood detected. */
-	byte = pci_read_config8(dev, 0x47);
-	byte |= (1 << 1);
-	pci_write_config8(dev, 0x47, byte);
+	pci_set8(dev, 0x47, (1 << 1));
 
 	/* Set up NMI on errors. */
 	byte = inb(0x70);		/* RTC70 */
--- src/southbridge/nvidia/ck804/ck804_pci.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-b2ae2c-ck804_pci.c	2010-10-05 03:03:32.940444316 +0200
@@ -17,10 +17,7 @@ static void pci_init(struct device *dev)
 	device_t pci_domain_dev;
 	struct resource *mem, *pref;
 
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1 << 8);	/* System error enable */
-	dword |= (1 << 30);	/* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
 
 #if 0
 	word = pci_read_config16(dev, 0x48);
@@ -30,9 +27,7 @@ static void pci_init(struct device *dev)
 #endif
 
 #if 1
-	dword = pci_read_config32(dev, 0x4c);
-	dword |= 0x00440000;	/* TABORT_SER_ENABLE Park Last Enable. */
-	pci_write_config32(dev, 0x4c, dword);
+	pci_set32(dev, 0x4c, 0x00440000);
 #endif
 
 	pci_domain_dev = dev->bus->dev;
--- src/southbridge/nvidia/ck804/ck804_pcie.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-99595a-ck804_pcie.c	2010-10-05 03:03:33.180445262 +0200
@@ -15,10 +15,7 @@ static void pcie_init(struct device *dev
 	uint32_t dword;
 
 	/* Enable PCI error detecting. */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1 << 8);	/* System error enable */
-	dword |= (1 << 30);	/* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
 }
 
 static struct pci_operations lops_pci = {
--- src/southbridge/nvidia/ck804/ck804_sata.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-9ca8c7-ck804_sata.c	2010-10-05 03:03:33.452445810 +0200
@@ -134,9 +134,7 @@ static void sata_init(struct device *dev
 	pci_write_config32(dev, 0xe0, dword);
 #endif
 
-	dword = pci_read_config32(dev, 0xf8);
-	dword |= 2;
-	pci_write_config32(dev, 0xf8, dword);
+	pci_set32(dev, 0xf8, 2);
 
 #if CK804_SATA_RESET_FOR_ATAPI
 	dword = pci_read_config32(dev, 0xac);
--- src/southbridge/nvidia/ck804/ck804_usb2.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-fc41b4-ck804_usb2.c	2010-10-05 03:03:33.796452017 +0200
@@ -13,9 +13,7 @@
 static void usb2_init(struct device *dev)
 {
 	uint32_t dword;
-	dword = pci_read_config32(dev, 0xf8);
-	dword |= 40;
-	pci_write_config32(dev, 0xf8, dword);
+	pci_set32(dev, 0xf8, 40);
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
--- src/southbridge/nvidia/ck804/ck804.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-21a5c5-ck804.c	2010-10-05 03:03:34.004445229 +0200
@@ -141,11 +141,7 @@ void ck804_enable(device_t dev)
 		return;
 
 	if (index == 0) {
-		final_reg = pci_read_config32(lpc_dev, 0xe8);
-		final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10)
-			| (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22)
-			| (1 << 18) | (1 << 15));
-		pci_write_config32(lpc_dev, 0xe8, final_reg);
+		pci_clear32(lpc_dev, 0xe8, ((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10) | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22) | (1 << 18) | (1 << 15)));
 
 		reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
 		reg |= (1 << 20);
--- src/southbridge/nvidia/mcp55/mcp55_enable_rom.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-6f865d-mcp55_enable_rom.c	2010-10-05 03:03:34.376454667 +0200
@@ -43,13 +43,7 @@ static void mcp55_enable_rom(void)
 #endif
 
 	/* Set the 4MB enable bit bit */
-	byte = pci_read_config8(addr, 0x88);
-	byte |= 0xff; //256K
-	pci_write_config8(addr, 0x88, byte);
-	byte = pci_read_config8(addr, 0x8c);
-	byte |= 0xff; //1M
-	pci_write_config8(addr, 0x8c, byte);
-	word = pci_read_config16(addr, 0x90);
-	word |= 0x7fff; //15M
-	pci_write_config16(addr, 0x90, word);
+	pci_set8(addr, 0x88, 0xff);
+	pci_set8(addr, 0x8c, 0xff);
+	pci_set16(addr, 0x90, 0x7fff);
 }
--- src/southbridge/nvidia/mcp55/mcp55_ide.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-8f850a-mcp55_ide.c	2010-10-05 03:03:34.612449686 +0200
@@ -60,9 +60,7 @@ static void ide_init(struct device *dev)
 	byte = 0x20 ; // Latency: 64-->32
 	pci_write_config8(dev, 0xd, byte);
 
-	dword = pci_read_config32(dev, 0xf8);
-	dword |= 12;
-	pci_write_config32(dev, 0xf8, dword);
+	pci_set32(dev, 0xf8, 12);
 #if CONFIG_PCI_ROM_RUN == 1
 	pci_dev_init(dev);
 #endif
--- src/southbridge/nvidia/mcp55/mcp55_lpc.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-3341f6-mcp55_lpc.c	2010-10-05 03:03:34.852446114 +0200
@@ -58,9 +58,7 @@ static void lpc_common_init(device_t dev
 	uint32_t ioapic_base;
 
 	/* IO APIC initialization */
-	byte = pci_read_config8(dev, 0x74);
-	byte |= (1<<0); // enable APIC
-	pci_write_config8(dev, 0x74, byte);
+	pci_set8(dev, 0x74, (1 << 0));
 	ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
 
 	if (master)
@@ -134,9 +132,7 @@ static void lpc_init(device_t dev)
 
 	/* Enable Error reporting */
 	/* Set up sync flood detected */
-	byte = pci_read_config8(dev, 0x47);
-	byte |= (1 << 1);
-	pci_write_config8(dev, 0x47, byte);
+	pci_set8(dev, 0x47, (1 << 1));
 
 	/* Set up NMI on errors */
 	byte = inb(0x70); // RTC70
--- src/southbridge/nvidia/mcp55/mcp55_pci.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-5cc8de-mcp55_pci.c	2010-10-05 03:03:35.520451313 +0200
@@ -38,23 +38,15 @@ static void pci_init(struct device *dev)
 	struct resource *mem, *pref;
 
 	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* System error enable */
-	dword |= (1<<30); /* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
 
 #if 1
 	//only need (a01,xx]
-	word = pci_read_config16(dev, 0x48);
-	word |= (1<<0); /* MRL2MRM */
-	word |= (1<<2); /* MR2MRM */
-	pci_write_config16(dev, 0x48, word);
+	pci_set16(dev, 0x48, (1 << 0) | (1 << 2));
 #endif
 
 #if 1
-	dword = pci_read_config32(dev, 0x4c);
-	dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
-	pci_write_config32(dev, 0x4c, dword);
+	pci_set32(dev, 0x4c, 0x00440000);
 #endif
 
 	pci_domain_dev = dev->bus->dev;
--- src/southbridge/nvidia/mcp55/mcp55.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-09b6c1-mcp55.c	2010-10-05 03:03:35.852452048 +0200
@@ -210,9 +210,7 @@ void mcp55_enable(device_t dev)
 		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
 		if(!sm_dev) return;
 
-		final_reg = pci_read_config32(sm_dev, 0xe8);
-		final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
-		pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
+		pci_clear32(sm_dev, 0xe8, ((1 << 16) | (1 << 8) | (1 << 20) | (1 << 14) | (1 << 22) | (1 << 18) | (1 << 17) | (1 << 15) | (1 << 11) | (1 << 10) | (1 << 9))); //enable all at first
 #if 0
 		reg_old = reg = pci_read_config32(sm_dev, 0xe4);
 //		reg |= (1<<0);
--- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-d937e6-mcp55_early_setup_car.c	2010-10-05 03:03:36.356444101 +0200
@@ -143,9 +143,7 @@ static void mcp55_early_pcie_setup(unsig
 	int i;
 	device_t dev;
 	dev = PCI_DEV(busnx, devnx+1, 1);
-	dword = pci_read_config32(dev, 0xe4);
-	dword |= 0x3f0; // disable it at first
-	pci_write_config32(dev, 0xe4, dword);
+	pci_set32(dev, 0xe4, 0x3f0);
 
 	for(i=0; i<3; i++) {
 		tgio_ctrl = inl(anactrl_io_base + 0xcc);
@@ -167,9 +165,7 @@ static void mcp55_early_pcie_setup(unsig
 	// wait 100us
 	udelay(100);
 
-	dword = pci_read_config32(dev, 0xe4);
-	dword &= ~(0x3f0); // enable
-	pci_write_config32(dev, 0xe4, dword);
+	pci_clear32(dev, 0xe4, (0x3f0));
 
 	// need to wait 100ms
 	mdelay(100);
--- src/southbridge/nvidia/mcp55/mcp55_pcie.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-6ea02d-mcp55_pcie.c	2010-10-05 03:03:37.948451351 +0200
@@ -35,10 +35,7 @@ static void pcie_init(struct device *dev
 	uint32_t dword;
 
 	/* System error enable */
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* System error enable */
-	dword |= (1<<30); /* Clear possible errors */
-	pci_write_config32(dev, 0x04, dword);
+	pci_set32(dev, 0x04, (1 << 8) | (1 << 30));
 
 }
 
--- src/southbridge/nvidia/mcp55/mcp55_sata.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-106c47-mcp55_sata.c	2010-10-05 03:03:38.364448907 +0200
@@ -62,9 +62,7 @@ static void sata_init(struct device *dev
 #endif
 	pci_write_config32(dev, 0x50, dword);
 
-	dword = pci_read_config32(dev, 0xf8);
-	dword |= 2;
-	pci_write_config32(dev, 0xf8, dword);
+	pci_set32(dev, 0xf8, 2);
 
 
 }
--- src/southbridge/nvidia/mcp55/mcp55_usb2.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-0e87c9-mcp55_usb2.c	2010-10-05 03:03:38.676453272 +0200
@@ -34,9 +34,7 @@ extern struct ehci_debug_info dbg_info;
 static void usb2_init(struct device *dev)
 {
 	uint32_t dword;
-	dword = pci_read_config32(dev, 0xf8);
-	dword |= 40;
-	pci_write_config32(dev, 0xf8, dword);
+	pci_set32(dev, 0xf8, 40);
 }
 
 static void usb2_set_resources(struct device *dev)
--- src/southbridge/nvidia/mcp55/mcp55_azalia.c	2010-10-01 09:27:01.000000000 +0200
+++ /tmp/cocci-output-5159-fd6031-mcp55_azalia.c	2010-10-05 03:03:38.980450218 +0200
@@ -228,9 +228,7 @@ static void azalia_init(struct device *d
 
 	pci_write_config8(dev, 0x3c, 0x0a); // unused?
 
-	reg8 = pci_read_config8(dev, 0x40);
-	reg8 |= (1 << 3); // Clear Clock Detect Bit
-	pci_write_config8(dev, 0x40, reg8);
+	pci_set8(dev, 0x40, (1 << 3));
 	reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
 	pci_write_config8(dev, 0x40, reg8);
 	reg8 |= (1 << 2); // Enable clock detection
@@ -240,13 +238,9 @@ static void azalia_init(struct device *d
 	printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
 
 	//
-	reg8 = pci_read_config8(dev, 0x40); // Audio Control
-	reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
-	pci_write_config8(dev, 0x40, reg8);
+	pci_set8(dev, 0x40, 1);
 
-	reg8 = pci_read_config8(dev, 0x4d); // Docking Status
-	reg8 &= ~(1 << 7); // Docking not supported
-	pci_write_config8(dev, 0x4d, reg8);
+	pci_clear8(dev, 0x4d, (1 << 7));
 
 	res = find_resource(dev, 0x10);
 	if (!res)
--- src/mainboard/hp/dl145_g3/mptable.c	2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-429b75-mptable.c	2010-10-05 03:03:39.557444053 +0200
@@ -129,9 +129,7 @@ static void *smp_write_config_table(void
 		dev = dev_find_device(0x1166, 0x0205, 0);
 		if(dev) {
 			uint32_t dword;
-			dword = pci_read_config32(dev, 0x64);
-			dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
-			pci_write_config32(dev, 0x64, dword);
+			pci_set32(dev, 0x64, (1 << 30));
 		}
 		// set GEVENT pins to NO OP
 		outb(0x33, 0xcd6); outb(0x00, 0xcd7);
@@ -145,9 +143,7 @@ static void *smp_write_config_table(void
 		dev = dev_find_device(0x1166, 0x205, 0);
 		if (dev) {
 			uint32_t dword;
-			dword = pci_read_config32(dev, 0x64);
-			dword |= (1<<26);
-			pci_write_config32(dev, 0x64, dword);
+			pci_set32(dev, 0x64, (1 << 26));
 		}
 	}
 
--- src/mainboard/hp/dl165_g6_fam10/mptable.c	2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-a39f44-mptable.c	2010-10-05 03:03:40.093443914 +0200
@@ -110,9 +110,7 @@ static void *smp_write_config_table(void
 		dev = dev_find_device(0x1166, 0x0205, 0);
 		if(dev) {
 			uint32_t dword;
-			dword = pci_read_config32(dev, 0x64);
-			dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
-			pci_write_config32(dev, 0x64, dword);
+			pci_set32(dev, 0x64, (1 << 30));
 		}
 		// set GEVENT pins to NO OP
 		/* outb(0x33, 0xcd6); outb(0x00, 0xcd7);
@@ -126,9 +124,7 @@ static void *smp_write_config_table(void
 		dev = dev_find_device(0x1166, 0x205, 0);
 		if (dev) {
 			uint32_t dword;
-			dword = pci_read_config32(dev, 0x64);
-			dword |= (1<<26);
-			pci_write_config32(dev, 0x64, dword);
+			pci_set32(dev, 0x64, (1 << 26));
 		}
 	}
 
--- src/mainboard/amd/dbm690t/mainboard.c	2010-10-01 09:27:10.000000000 +0200
+++ /tmp/cocci-output-5159-9efd96-mainboard.c	2010-10-05 03:03:40.589443797 +0200
@@ -101,9 +101,7 @@ static void get_ide_dma66(void)
 	printk(BIOS_INFO, "%s.\n", __func__);
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
-	byte = pci_read_config8(sm_dev, 0xA9);
-	byte |= (1 << 5);	/* Set Gpio9 as input */
-	pci_write_config8(sm_dev, 0xA9, byte);
+	pci_set8(sm_dev, 0xA9, (1 << 5));
 
 	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
 	byte = pci_read_config8(ide_dev, 0x56);
@@ -145,9 +143,7 @@ static void set_thermal_config(void)
 
 	/* set GPIO 64 to input */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x56);
-	word |= 1 << 7;
-	pci_write_config16(sm_dev, 0x56, word);
+	pci_set16(sm_dev, 0x56, 1 << 7);
 
 	/* set GPIO 64 internal pull-up */
 	byte = pm2_ioread(0xf0);
--- src/mainboard/amd/pistachio/mainboard.c	2010-10-01 09:27:10.000000000 +0200
+++ /tmp/cocci-output-5159-9d9f69-mainboard.c	2010-10-05 03:03:41.013444592 +0200
@@ -163,19 +163,13 @@ static void set_thermal_config(void)
 
 	/* GPM5 as GPIO not USB OC */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	dword = pci_read_config32(sm_dev, 0x64);
-	dword |= 1 << 19;
-	pci_write_config32(sm_dev, 0x64, dword);
+	pci_set32(sm_dev, 0x64, 1 << 19);
 
 	/* Enable Client Management Index/Data registers */
-	dword = pci_read_config32(sm_dev, 0x78);
-	dword |= 1 << 11;	/* Cms_enable */
-	pci_write_config32(sm_dev, 0x78, dword);
+	pci_set32(sm_dev, 0x78, 1 << 11);
 
 	/* MiscfuncEnable */
-	byte = pci_read_config8(sm_dev, 0x41);
-	byte |= (1 << 5);
-	pci_write_config8(sm_dev, 0x41, byte);
+	pci_set8(sm_dev, 0x41, (1 << 5));
 
 	/* set GPM5 as input */
 	/* set index register 0C50h to 13h (miscellaneous control) */
@@ -215,9 +209,7 @@ static void set_thermal_config(void)
 	pm2_iowrite(0x42, byte);
 
 	/* set GPIO 64 to input */
-	word = pci_read_config16(sm_dev, 0x56);
-	word |= 1 << 7;
-	pci_write_config16(sm_dev, 0x56, word);
+	pci_set16(sm_dev, 0x56, 1 << 7);
 
 	/* set GPIO 64 internal pull-up */
 	byte = pm2_ioread(0xf0);
--- src/mainboard/amd/tilapia_fam10/mainboard.c	2010-10-01 09:27:10.000000000 +0200
+++ /tmp/cocci-output-5159-6b4283-mainboard.c	2010-10-05 03:03:41.409444072 +0200
@@ -95,10 +95,7 @@ void set_pcie_reset()
 
 	/* set the GPIO65 output enable and the value is 0 */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x7e);
-	word &= ~(1 << 0);
-	word &= ~(1 << 4);
-	pci_write_config16(sm_dev, 0x7e, word);
+	pci_clear16(sm_dev, 0x7e, ((1 << 0) | (1 << 4)));
 }
 
 #if 0	     /* TODO: */
@@ -142,9 +139,7 @@ u8 is_dev3_present(void)
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
 	/* put the GPIO68 output to tristate */
-	word = pci_read_config16(sm_dev, 0x7e);
-	word |= 1 << 6;
-	pci_write_config16(sm_dev, 0x7e,word);
+	pci_set16(sm_dev, 0x7e, 1 << 6);
 
 	/* read the GPIO68 input status */
 	word = pci_read_config16(sm_dev, 0x7e);
@@ -204,13 +199,7 @@ static void set_gpio40_gfx(void)
 		printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
 		/* when the gpio40 is configured as GPIO, this will enable the output */
 		pci_write_config32(sm_dev, 0xf8, 0x4);
-		dword = pci_read_config32(sm_dev, 0xfc);
-		dword &= ~(1 << 10);
-
-        	/* When the gpio40 is configured as GPIO, this will represent the output value*/
-		/* 1 :enable two x8  , 0 : master slot enable only */
-		dword &=  ~(1 << 26);
-		pci_write_config32(sm_dev, 0xfc, dword);
+		pci_clear32(sm_dev, 0xfc, ((1 << 10) | (1 << 26)));
 	}
 }
 
@@ -244,9 +233,7 @@ static void set_thermal_config(void)
 
 	/* set GPIO 64 to input */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x56);
-	word |= 1 << 7;
-	pci_write_config16(sm_dev, 0x56, word);
+	pci_set16(sm_dev, 0x56, 1 << 7);
 
 	/* set GPIO 64 internal pull-up */
 	byte = pm2_ioread(0xf0);
--- src/mainboard/amd/mahogany/mainboard.c	2010-10-01 09:27:10.000000000 +0200
+++ /tmp/cocci-output-5159-f9589f-mainboard.c	2010-10-05 03:03:41.797444036 +0200
@@ -59,10 +59,7 @@ void set_pcie_reset()
 	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
-	word = pci_read_config16(sm_dev, 0xA8);
-	word &= ~((1 << 0) | (1 << 2));	/* Set Gpio6,4 as output */
-	word &= ~((1 << 8) | (1 << 10));
-	pci_write_config16(sm_dev, 0xA8, word);
+	pci_clear16(sm_dev, 0xA8, (((1 << 0) | (1 << 2)) | ((1 << 8) | (1 << 10))));
 }
 
 #if 0	     /* not tested yet */
--- src/mainboard/amd/mahogany_fam10/mainboard.c	2010-10-01 09:27:10.000000000 +0200
+++ /tmp/cocci-output-5159-e49a8d-mainboard.c	2010-10-05 03:03:42.045446539 +0200
@@ -59,10 +59,7 @@ void set_pcie_reset()
 	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
-	word = pci_read_config16(sm_dev, 0xA8);
-	word &= ~((1 << 0) | (1 << 2));	/* Set Gpio6,4 as output */
-	word &= ~((1 << 8) | (1 << 10));
-	pci_write_config16(sm_dev, 0xA8, word);
+	pci_clear16(sm_dev, 0xA8, (((1 << 0) | (1 << 2)) | ((1 << 8) | (1 << 10))));
 }
 
 #if 0	     /* not tested yet. */
--- src/mainboard/msi/ms7135/romstage.c	2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-ac1c37-romstage.c	2010-10-05 03:03:42.289445802 +0200
@@ -99,15 +99,10 @@ static void sio_setup(void)
 	uint8_t byte;
 
 	/* Subject decoding */
-	byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
+	pci_set8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, 0x20);
 
 	/* LPC Positive Decode 0 */
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
-	/* Serial 0, Serial 1 */
-	dword |= (1 << 0) | (1 << 1);
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
+	pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 0) | (1 << 1));
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/msi/ms7260/romstage.c	2010-10-01 20:34:21.000000000 +0200
+++ /tmp/cocci-output-5159-bb1731-romstage.c	2010-10-05 03:03:42.537444376 +0200
@@ -123,17 +123,11 @@ static void sio_setup(void)
 	uint32_t dword;
 	uint8_t byte;
 
-	byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
-	dword |= (1 << 0);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
-	dword |= (1 << 16);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
+	pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/msi/ms9185/mptable.c	2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-61b92d-mptable.c	2010-10-05 03:03:42.853444933 +0200
@@ -122,9 +122,7 @@ static void *smp_write_config_table(void
                 dev = dev_find_device(0x1166, 0x0205, 0);
                 if(dev) {
                         uint32_t dword;
-                        dword = pci_read_config32(dev, 0x6c);
-                        dword |= (1<<4); // enable interrupts
-                        pci_write_config32(dev, 0x6c, dword);
+                        pci_set32(dev, 0x6c, (1 << 4));
                 }
                 }
 
--- src/mainboard/msi/ms9282/romstage.c	2010-10-05 01:05:54.000000000 +0200
+++ /tmp/cocci-output-5159-6f4ffb-romstage.c	2010-10-05 03:03:43.193445295 +0200
@@ -134,9 +134,7 @@ static void sio_setup(void)
         byte |= 0x20;
         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 
-        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-        dword |= (1<<0);
-        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+        pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
 }
 
 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
--- src/mainboard/msi/ms9652_fam10/romstage.c	2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-033705-romstage.c	2010-10-05 03:03:43.505445181 +0200
@@ -130,9 +130,7 @@ static void sio_setup(void)
 	byte |= 0x20;
 	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
 }
 
 #include "spd_addr.h"
--- src/mainboard/via/epia/romstage.c	2010-10-01 09:27:12.000000000 +0200
+++ /tmp/cocci-output-5159-4da27c-romstage.c	2010-10-05 03:03:43.865446726 +0200
@@ -68,10 +68,7 @@ static void enable_shadow_ram(void)
 	device_t dev = 0;
 	unsigned char shadowreg;
 
-	shadowreg = pci_read_config8(dev, 0x63);
-	/* 0xf0000-0xfffff */
-	shadowreg |= 0x30;
-	pci_write_config8(dev, 0x63, shadowreg);
+	pci_set8(dev, 0x63, 0x30);
 }
 
 static void main(unsigned long bist)
--- src/mainboard/via/epia-m700/romstage.c	2010-10-01 20:34:21.000000000 +0200
+++ /tmp/cocci-output-5159-bef3cd-romstage.c	2010-10-05 03:03:44.109444668 +0200
@@ -160,9 +160,7 @@ static void enable_shadow_ram(void)
 	pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
 
 	/* 0xf0000-0xfffff - ACPI tables */
-	shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
-	shadowreg |= 0x30;
-	pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
+	pci_set8(PCI_DEV(0, 0, 3), 0x83, 0x30);
 
 	/* 0xe0000-0xeffff - elfload? */
 	/*
--- src/mainboard/via/epia-m/romstage.c	2010-10-01 09:27:12.000000000 +0200
+++ /tmp/cocci-output-5159-ea7f2e-romstage.c	2010-10-05 03:03:44.924455417 +0200
@@ -62,10 +62,7 @@ static void enable_shadow_ram(void)
 	device_t dev = 0; /* no need to look up 0:0.0 */
 	unsigned char shadowreg;
 	/* dev 0 for southbridge */
-	shadowreg = pci_read_config8(dev, 0x63);
-	/* 0xf0000-0xfffff */
-	shadowreg |= 0x30;
-	pci_write_config8(dev, 0x63, shadowreg);
+	pci_set8(dev, 0x63, 0x30);
 }
 
 static void main(unsigned long bist)
--- src/mainboard/via/epia-n/romstage.c	2010-10-01 09:27:12.000000000 +0200
+++ /tmp/cocci-output-5159-be57a0-romstage.c	2010-10-05 03:03:45.184444652 +0200
@@ -98,10 +98,7 @@ static void enable_shadow_ram(void)
 {
 	unsigned char shadowreg;
 
-	shadowreg = pci_read_config8(ctrl.d0f3, 0x82);
-	/* 0xf0000-0xfffff Read/Write*/
-	shadowreg |= 0x30;
-	pci_write_config8(ctrl.d0f3, 0x82, shadowreg);
+	pci_set8(ctrl.d0f3, 0x82, 0x30);
 }
 
 static void main(unsigned long bist)
--- src/mainboard/via/vt8454c/romstage.c	2010-10-01 09:27:12.000000000 +0200
+++ /tmp/cocci-output-5159-f130f9-romstage.c	2010-10-05 03:03:45.468449238 +0200
@@ -81,9 +81,7 @@ static void enable_shadow_ram(const stru
 	pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a);
 
 	/* 0xf0000-0xfffff - ACPI tables */
-	shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
-	shadowreg |= 0x30;
-	pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
+	pci_set8(PCI_DEV(0, 0, 3), 0x83, 0x30);
 }
 
 void main(unsigned long bist)
--- src/mainboard/asus/a8n_e/romstage.c	2010-10-01 09:27:14.000000000 +0200
+++ /tmp/cocci-output-5159-185ca0-romstage.c	2010-10-05 03:03:45.716445191 +0200
@@ -93,14 +93,10 @@ static void sio_setup(void)
 	uint8_t byte;
 
 	/* Subject decoding */
-	byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
+	pci_set8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, 0x20);
 
 	/* LPC Positive Decode 0 */
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
-	dword |= (1 << 0) | (1 << 1);	/* Serial 0, Serial 1 */
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
+	pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 0) | (1 << 1));
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/asus/a8v-e_se/romstage.c	2010-10-05 01:05:54.000000000 +0200
+++ /tmp/cocci-output-5159-2b5a2b-romstage.c	2010-10-05 03:03:46.024445650 +0200
@@ -85,9 +85,7 @@ void soft_reset(void)
 	print_debug("soft reset \n");
 
 	/* PCI reset */
-	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
-	tmp |= 0x01;
-	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
+	pci_set8(PCI_DEV(0, 0x11, 0), 0x4f, 0x01);
 
 	while (1) {
 		/* daisy daisy ... */
--- src/mainboard/asus/m2v-mx_se/romstage.c	2010-10-05 01:05:54.000000000 +0200
+++ /tmp/cocci-output-5159-4ae108-romstage.c	2010-10-05 03:03:46.392445712 +0200
@@ -115,10 +115,7 @@ void soft_reset(void)
 	print_debug("soft reset \n");
 
 	/* PCI reset */
-	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
-	tmp |= 0x01;
-	/* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
-	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
+	pci_set8(PCI_DEV(0, 0x11, 0), 0x4f, 0x01);
 
 	while (1) {
 		/* daisy daisy ... */
--- src/mainboard/asus/m4a785-m/mainboard.c	2010-10-01 09:27:14.000000000 +0200
+++ /tmp/cocci-output-5159-f5280f-mainboard.c	2010-10-05 03:03:46.712444476 +0200
@@ -94,10 +94,7 @@ void set_pcie_reset()
 
 	/* set the GPIO65 output enable and the value is 0 */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x7e);
-	word &= ~(1 << 0);
-	word &= ~(1 << 4);
-	pci_write_config16(sm_dev, 0x7e, word);
+	pci_clear16(sm_dev, 0x7e, ((1 << 0) | (1 << 4)));
 }
 
 #if 0	     /* TODO: */
@@ -143,9 +140,7 @@ u8 is_dev3_present(void)
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
 	/* put the GPIO68 output to tristate */
-	word = pci_read_config16(sm_dev, 0x7e);
-	word |= 1 << 6;
-	pci_write_config16(sm_dev, 0x7e,word);
+	pci_set16(sm_dev, 0x7e, 1 << 6);
 
 	/* read the GPIO68 input status */
 	word = pci_read_config16(sm_dev, 0x7e);
@@ -189,9 +184,7 @@ static void set_thermal_config(void)
 
 	/* set GPIO 64 to input */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x56);
-	word |= 1 << 7;
-	pci_write_config16(sm_dev, 0x56, word);
+	pci_set16(sm_dev, 0x56, 1 << 7);
 
 	/* set GPIO 64 internal pull-up */
 	byte = pm2_ioread(0xf0);
--- src/mainboard/dell/s1850/romstage.c	2010-10-01 12:04:15.000000000 +0200
+++ /tmp/cocci-output-5159-a9745f-romstage.c	2010-10-05 03:03:47.088443890 +0200
@@ -188,46 +188,32 @@ static void main(unsigned long bist)
 	 * we're going to clone it.
 	 */
 	/* enable a hidden device. */
-	b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
-	b |= 0x8;
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
+	pci_set8(PCI_DEV(0, 0, 0), 0xf4, 0x8);
 
 	/* read-write lock in CMOS on LPC bridge on ICH5 */
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
 
 	/* operate on undocumented device */
-	l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
-	l |= 0x1000;
-	pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
-
-	l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
-	l |= 0x8000;
-	pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
+	pci_set32(PCI_DEV(0, 0, 2), 0xa4, 0x1000);
+
+	pci_set32(PCI_DEV(0, 0, 2), 0x9c, 0x8000);
 
 	/* disable undocumented device */
-	b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
-	b &= ~0x8;
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
+	pci_clear8(PCI_DEV(0, 0, 0), 0xf4, 0x8);
 
 	/* set up LPC bridge bits, some of which reply on undocumented
 	 * registers
 	 */
 
-	b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
-	b |= 4;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
-
-	b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
-	b |= 2;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
+	pci_set8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
+
+	pci_set8(PCI_DEV(0, 0x1f, 0), 0xd4, 2);
 
 	/* ACPI base address */
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
 
 	/* Enable specific ACPI features */
-	b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
-	b |= 0x10;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
+	pci_set8(PCI_DEV(0, 0x1f, 0), 0x44, 0x10);
 
 	/* ACPI control */
 	w = inw(0x868);
@@ -248,9 +234,7 @@ static void main(unsigned long bist)
 #endif
 
 	/* another device enable? */
-	b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
-	b |= 2;
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
+	pci_set8(PCI_DEV(0, 0, 0), 0xf4, 2);
 
 	/* ?? */
 	l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
--- src/mainboard/dell/s1850/watchdog.c	2010-10-01 09:27:12.000000000 +0200
+++ /tmp/cocci-output-5159-dcd499-watchdog.c	2010-10-05 03:03:47.504444667 +0200
@@ -28,9 +28,7 @@ static void disable_ich5_watchdog(void)
 		die("Missing ich5?");
 	}
 	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Set and enable acpibase */
 	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
--- src/mainboard/roda/rk886ex/romstage.c	2010-10-01 10:04:58.000000000 +0200
+++ /tmp/cocci-output-5159-e3e971-romstage.c	2010-10-05 03:03:47.724443941 +0200
@@ -201,22 +201,14 @@ static void early_ich7_init(void)
 	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 
 	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
-	reg8 &= ~(1 << 2);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+	pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 2));
 
 	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+	pci_set8(PCI_DEV(0, 0x1f, 0), 0xad, (3 << 0));
+
+	pci_set32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
+
+	pci_set32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
 
 	RCBA32(0x0088) = 0x0011d000;
 	RCBA16(0x01fc) = 0x060f;
--- src/mainboard/sunw/ultra40/romstage.c	2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-91b832-romstage.c	2010-10-05 03:03:48.248443877 +0200
@@ -115,9 +115,7 @@ static void sio_setup(void)
         byte |= 0x20;
         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 
-        dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-        dword |= (1<<29)|(1<<0);
-        pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
+        pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 29) | (1 << 0));
 
         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 
--- src/mainboard/tyan/s2891/romstage.c	2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-8d63d1-romstage.c	2010-10-05 03:03:48.680443992 +0200
@@ -81,23 +81,16 @@ static void sio_setup(void)
 	uint8_t byte;
 
 	/* subject decoding*/
-	byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
+	pci_set8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, 0x20);
 
 	/* LPC Positive Decode 0 */
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	/* Serial 0, Serial 1 */
-	dword |= (1<<0) | (1<<1);
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
+	pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 0) | (1 << 1));
 
 #if 1
 	/* s2891 has onboard LPC port 80 */
 	/*Hope I can enable port 80 here
 	It will decode port 80 to LPC, If you are using PCI post code you can not do this */
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
-	dword |= (1<<16);
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
+	pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 #endif
 }
 
--- src/mainboard/tyan/s2892/romstage.c	2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-ebff70-romstage.c	2010-10-05 03:03:49.044443866 +0200
@@ -83,13 +83,9 @@ static void sio_setup(void)
 	uint32_t dword;
 	uint8_t byte;
 
-	byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0);
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
+	pci_set8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+	pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/tyan/s2895/romstage.c	2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-7b902a-romstage.c	2010-10-05 03:03:49.420444055 +0200
@@ -103,17 +103,11 @@ static void sio_setup(void)
 
 	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 
-	byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<29)|(1<<0);
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
-	dword |= (1<<16);
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
+	pci_set8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+	pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, (1 << 29) | (1 << 0));
+
+	pci_set32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 
 	lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
--- src/mainboard/tyan/s2912/romstage.c	2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-166204-romstage.c	2010-10-05 03:03:49.856444434 +0200
@@ -133,18 +133,11 @@ static void sio_setup(void)
 	uint32_t dword;
 	uint8_t byte;
 
-	byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-	/*serial 0 */
-	dword |= (1<<0);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-	dword |= (1<<16);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+	pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/tyan/s2912_fam10/romstage.c	2010-10-01 09:27:11.000000000 +0200
+++ /tmp/cocci-output-5159-41ee43-romstage.c	2010-10-05 03:03:50.292443864 +0200
@@ -123,18 +123,11 @@ static void sio_setup(void)
 	uint32_t dword;
 	uint8_t byte;
 
-	byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-	/*serial 0 */
-	dword |= (1<<0);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-	dword |= (1<<16);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+	pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 }
 
 #include "spd_addr.h"
--- src/mainboard/arima/hdama/mptable.c	2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-2d9115-mptable.c	2010-10-05 03:03:50.752444024 +0200
@@ -325,9 +325,7 @@ static void reboot_if_hotswap(void)
 		pci_write_config8(dev, 0x41, 0xf1);
 		/* reset */
 		dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
-		htic = pci_read_config32(dev, HT_INIT_CONTROL);
-		htic &= ~HTIC_BIOSR_Detect;
-		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+		pci_clear32(dev, HT_INIT_CONTROL, HTIC_BIOSR_Detect);
 		outb(0x0e, 0x0cf9);
 	}
 	else {
--- src/mainboard/getac/p470/romstage.c	2010-10-01 10:04:58.000000000 +0200
+++ /tmp/cocci-output-5159-6e087a-romstage.c	2010-10-05 03:03:51.488444034 +0200
@@ -236,22 +236,14 @@ static void early_ich7_init(void)
 	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 
 	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
-	reg8 &= ~(1 << 2);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+	pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 2));
 
 	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+	pci_set8(PCI_DEV(0, 0x1f, 0), 0xad, (3 << 0));
+
+	pci_set32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
+
+	pci_set32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
 
 	RCBA32(0x0088) = 0x0011d000;
 	RCBA16(0x01fc) = 0x060f;
--- src/mainboard/ibase/mb899/romstage.c	2010-10-01 10:04:58.000000000 +0200
+++ /tmp/cocci-output-5159-74d9db-romstage.c	2010-10-05 03:03:52.300445076 +0200
@@ -198,22 +198,14 @@ static void early_ich7_init(void)
 	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 
 	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
-	reg8 &= ~(1 << 2);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+	pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 2));
 
 	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+	pci_set8(PCI_DEV(0, 0x1f, 0), 0xad, (3 << 0));
+
+	pci_set32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
+
+	pci_set32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
 
 	RCBA32(0x0088) = 0x0011d000;
 	RCBA16(0x01fc) = 0x060f;
--- src/mainboard/intel/d945gclf/romstage.c	2010-10-01 10:04:58.000000000 +0200
+++ /tmp/cocci-output-5159-71095d-romstage.c	2010-10-05 03:03:52.896444072 +0200
@@ -160,22 +160,14 @@ static void early_ich7_init(void)
 	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 
 	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
-	reg8 &= ~(1 << 2);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+	pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 2));
 
 	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+	pci_set8(PCI_DEV(0, 0x1f, 0), 0xad, (3 << 0));
+
+	pci_set32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
+
+	pci_set32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
 
 	RCBA32(0x0088) = 0x0011d000;
 	RCBA16(0x01fc) = 0x060f;
--- src/mainboard/intel/jarrell/jarrell_fixups.c	2010-10-01 09:27:14.000000000 +0200
+++ /tmp/cocci-output-5159-46b550-jarrell_fixups.c	2010-10-05 03:03:53.392443835 +0200
@@ -13,9 +13,7 @@ static void mch_reset(void)
                 base = ICH5_GPIOBASE;
 
                 /* Enable GPIO Bar */
-                value = pci_read_config32(dev, 0x5c);
-                value |= 0x10;
-                pci_write_config32(dev, 0x5c, value);
+                pci_set32(dev, 0x5c, 0x10);
 
 		/* Set GPIO 19 mux to IO usage */
 		value = inl(base);
--- src/mainboard/intel/jarrell/watchdog.c	2010-10-01 09:27:14.000000000 +0200
+++ /tmp/cocci-output-5159-320361-watchdog.c	2010-10-05 03:03:53.800447098 +0200
@@ -26,9 +26,7 @@ static void disable_ich5_watchdog(void)
 		die("Missing ich5?");
 	}
 	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Set and enable acpibase */
 	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
@@ -54,18 +52,14 @@ static void disable_jarell_frb3(void)
 		die("Missing ich5?");
 	}
 	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 0);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 0));
 
 	/* Set gpio base */
 	pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
 	base = ICH5_GPIOBASE;
 
 	/* Enable GPIO Bar */
-	value = pci_read_config32(dev, 0x5c);
-	value |= 0x10;
-	pci_write_config32(dev, 0x5c, value);
+	pci_set32(dev, 0x5c, 0x10);
 
 	/* Configure GPIO 48 and 40 as GPIO */
 	value = inl(base + 0x30);
@@ -111,9 +105,7 @@ static void ich5_watchdog_on(void)
 		die("Missing ich5?");
 	}
 	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Set and enable acpibase */
 	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
--- src/mainboard/kontron/kt690/mainboard.c	2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-601b65-mainboard.c	2010-10-05 03:03:54.200447019 +0200
@@ -101,9 +101,7 @@ static void get_ide_dma66(void)
 	printk(BIOS_INFO, "%s.\n", __func__);
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
-	byte = pci_read_config8(sm_dev, 0xA9);
-	byte |= (1 << 5);	/* Set Gpio9 as input */
-	pci_write_config8(sm_dev, 0xA9, byte);
+	pci_set8(sm_dev, 0xA9, (1 << 5));
 
 	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
 	byte = pci_read_config8(ide_dev, 0x56);
@@ -145,9 +143,7 @@ static void set_thermal_config(void)
 
 	/* set GPIO 64 to input */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x56);
-	word |= 1 << 7;
-	pci_write_config16(sm_dev, 0x56, word);
+	pci_set16(sm_dev, 0x56, 1 << 7);
 
 	/* set GPIO 64 internal pull-up */
 	byte = pm2_ioread(0xf0);
--- src/mainboard/kontron/986lcd-m/romstage.c	2010-10-01 10:04:58.000000000 +0200
+++ /tmp/cocci-output-5159-2f549d-romstage.c	2010-10-05 03:03:54.552450241 +0200
@@ -288,22 +288,14 @@ static void early_ich7_init(void)
 	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 
 	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
-	reg8 &= ~(1 << 2);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+	pci_clear8(PCI_DEV(0, 0x1f, 0), 0xa4, (1 << 2));
 
 	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+	pci_set8(PCI_DEV(0, 0x1f, 0), 0xad, (3 << 0));
+
+	pci_set32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
+
+	pci_set32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
 
 	RCBA32(0x0088) = 0x0011d000;
 	RCBA16(0x01fc) = 0x060f;
--- src/mainboard/supermicro/h8dmr_fam10/romstage.c	2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-8bfa37-romstage.c	2010-10-05 03:03:55.096446028 +0200
@@ -118,17 +118,11 @@ static void sio_setup(void)
 	/* set FAN ctrl to DC mode */
 	smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff);
 
-	byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
-	dword |= (1 << 0);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
-	dword |= (1 << 16);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
+	pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 
 }
 
--- src/mainboard/supermicro/h8dme/romstage.c	2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-84cc96-romstage.c	2010-10-05 03:03:55.440444280 +0200
@@ -182,17 +182,11 @@ static void sio_setup(void)
 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 	smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff);	/* set FAN ctrl to DC mode */
 
-	byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
-	dword |= (1 << 0);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
-	dword |= (1 << 16);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
+	pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 }
 
 /* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
--- src/mainboard/supermicro/h8dmr/romstage.c	2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-146759-romstage.c	2010-10-05 03:03:55.852444245 +0200
@@ -126,17 +126,11 @@ static void sio_setup(void)
 //	smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 	smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 
-        byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20;
-        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
-        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-        dword |= (1<<0);
-        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-        dword |= (1<<16);
-        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+        pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+        pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+        pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/supermicro/x6dai_g/watchdog.c	2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-08a955-watchdog.c	2010-10-05 03:03:56.184447144 +0200
@@ -15,9 +15,7 @@ static void disable_esb6300_watchdog(voi
 		die("Missing 6300ESB?");
 	}
 	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Set and enable acpibase */
 	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
--- src/mainboard/supermicro/x6dhe_g/watchdog.c	2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-9fdfcc-watchdog.c	2010-10-05 03:03:56.396446359 +0200
@@ -28,9 +28,7 @@ static void disable_esb6300_watchdog(voi
 		die("Missing esb6300?");
 	}
 	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Set and enable acpibase */
 	pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1);
--- src/mainboard/supermicro/x6dhr_ig2/watchdog.c	2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-49e430-watchdog.c	2010-10-05 03:03:56.620445987 +0200
@@ -28,9 +28,7 @@ static void disable_ich5_watchdog(void)
 		die("Missing ich5?");
 	}
 	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Set and enable acpibase */
 	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
--- src/mainboard/supermicro/x6dhe_g2/watchdog.c	2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-e09992-watchdog.c	2010-10-05 03:03:56.836446663 +0200
@@ -28,9 +28,7 @@ static void disable_esb6300_watchdog(voi
 		die("Missing esb6300?");
 	}
 	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Set and enable acpibase */
 	pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1);
--- src/mainboard/supermicro/x6dhr_ig/watchdog.c	2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-5a058b-watchdog.c	2010-10-05 03:03:57.052446427 +0200
@@ -28,9 +28,7 @@ static void disable_ich5_watchdog(void)
 		die("Missing ich5?");
 	}
 	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
+	pci_set16(dev, 0x04, (1 << 10));
 
 	/* Set and enable acpibase */
 	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
--- src/mainboard/supermicro/h8qme_fam10/romstage.c	2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-4ddcaa-romstage.c	2010-10-05 03:03:57.280444624 +0200
@@ -121,17 +121,11 @@ static void sio_setup(void)
 //	smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 	smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 
-        byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20;
-        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
-        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-        dword |= (1<<0);
-        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-        dword |= (1<<16);
-        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+        pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+        pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+        pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 
 }
 
--- src/mainboard/broadcom/blast/mptable.c	2010-10-01 09:27:08.000000000 +0200
+++ /tmp/cocci-output-5159-2472ef-mptable.c	2010-10-05 03:03:57.652446216 +0200
@@ -101,9 +101,7 @@ static void *smp_write_config_table(void
                 dev = dev_find_device(0x1166, 0x0205, 0);
                 if(dev) {
                         uint32_t dword;
-                        dword = pci_read_config32(dev, 0x6c);
-                        dword |= (1<<4); // enable interrupts
-                        pci_write_config32(dev, 0x6c, dword);
+                        pci_set32(dev, 0x6c, (1 << 4));
 
                 }
 
--- src/mainboard/jetway/pa78vm5/mainboard.c	2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-75257e-mainboard.c	2010-10-05 03:03:58.064451811 +0200
@@ -61,10 +61,7 @@ void set_pcie_reset()
 	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
-	word = pci_read_config16(sm_dev, 0xA8);
-	word &= ~((1 << 0) | (1 << 2));	/* Set Gpio6,4 as output */
-	word &= ~((1 << 8) | (1 << 10));
-	pci_write_config16(sm_dev, 0xA8, word);
+	pci_clear16(sm_dev, 0xA8, (((1 << 0) | (1 << 2)) | ((1 << 8) | (1 << 10))));
 }
 
 #if 0	     /* not tested yet. */
--- src/mainboard/nvidia/l1_2pvv/romstage.c	2010-10-01 09:27:14.000000000 +0200
+++ /tmp/cocci-output-5159-3510ec-romstage.c	2010-10-05 03:03:58.360453032 +0200
@@ -137,17 +137,11 @@ static void sio_setup(void)
 	uint32_t dword;
 	uint8_t byte;
 
-	byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-	dword |= (1<<16);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+	pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+	pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/technexion/tim5690/tn_post_code.c	2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-2418ee-tn_post_code.c	2010-10-05 03:03:58.748450358 +0200
@@ -67,13 +67,9 @@ void technexion_post_code_init(void)
    reg8_data &= ~(1<<7); // 0: GPIO if not used by SATA
    pmio_write(0x5e, reg8_data);
 
-   reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<0);
-   pci_write_config8(dev, 0xa8, reg8_data);
-
-   reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<0);
-   pci_write_config8(dev, 0xa9, reg8_data);
+   pci_set8(dev, 0xa8, (1 << 0));
+
+   pci_clear8(dev, 0xa9, (1 << 0));
 
    // LED[bit3]:GPIO6
    // This is reference SB600 RRG 4.1.1 GPIO
@@ -81,32 +77,20 @@ void technexion_post_code_init(void)
    reg8_data |= (1<<7); // 1: GPIO if not used by SATA
    pmio_write(0x60, reg8_data);
 
-   reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<2);
-   pci_write_config8(dev, 0xa8, reg8_data);
-
-   reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<2);
-   pci_write_config8(dev, 0xa9, reg8_data);
+   pci_set8(dev, 0xa8, (1 << 2));
+
+   pci_clear8(dev, 0xa9, (1 << 2));
    // LED[bit4]:GPIO7
    // This is reference SB600 RRG 4.1.1 GPIO
-   reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<3);
-   pci_write_config8(dev, 0xa8, reg8_data);
-
-   reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<3);
-   pci_write_config8(dev, 0xa9, reg8_data);
+   pci_set8(dev, 0xa8, (1 << 3));
+
+   pci_clear8(dev, 0xa9, (1 << 3));
 
    // LED[bit5]:GPIO8
    // This is reference SB600 RRG 4.1.1 GPIO
-   reg8_data = pci_read_config8(dev, 0xa8);
-   reg8_data |= (1<<4);
-   pci_write_config8(dev, 0xa8, reg8_data);
-
-   reg8_data = pci_read_config8(dev, 0xa9);
-   reg8_data &= ~(1<<4);
-   pci_write_config8(dev, 0xa9, reg8_data);
+   pci_set8(dev, 0xa8, (1 << 4));
+
+   pci_clear8(dev, 0xa9, (1 << 4));
 
    // LED[bit6]:GPIO10
    // This is reference SB600 RRG 4.1.1 GPIO
--- src/mainboard/technexion/tim5690/mainboard.c	2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-63c83c-mainboard.c	2010-10-05 03:03:59.085444155 +0200
@@ -143,9 +143,7 @@ static void set_thermal_config(void)
 
 	/* set GPIO 64 to input */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x56);
-	word |= 1 << 7;
-	pci_write_config16(sm_dev, 0x56, word);
+	pci_set16(sm_dev, 0x56, 1 << 7);
 
 	/* set GPIO 64 internal pull-up */
 	byte = pm2_ioread(0xf0);
--- src/mainboard/technexion/tim8690/mainboard.c	2010-10-01 09:27:13.000000000 +0200
+++ /tmp/cocci-output-5159-b9e0a6-mainboard.c	2010-10-05 03:03:59.469444833 +0200
@@ -62,18 +62,13 @@ static void enable_onboard_nic(void)
 
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
-	byte = pci_read_config8(sm_dev, 0x9a);
-	byte |= ( 1 << 7);
-	pci_write_config8(sm_dev, 0x9a, byte);
+	pci_set8(sm_dev, 0x9a, (1 << 7));
 
 	byte=pm_ioread(0x59);
 	byte &= ~( 1<< 5);
 	pm_iowrite(0x59,byte);
 
-	byte = pci_read_config8(sm_dev, 0xA8);
-
-	byte |= (1 << 1); //set bit 1 to high
-	pci_write_config8(sm_dev, 0xA8, byte);
+	pci_set8(sm_dev, 0xA8, (1 << 1));
 }
 
 /* set thermal config
@@ -105,9 +100,7 @@ static void set_thermal_config(void)
 
 	/* set GPIO 64 to input */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x56);
-	word |= 1 << 7;
-	pci_write_config16(sm_dev, 0x56, word);
+	pci_set16(sm_dev, 0x56, 1 << 7);
 
 	/* set GPIO 64 internal pull-up */
 	byte = pm2_ioread(0xf0);
--- src/mainboard/gigabyte/ga_2761gxdk/romstage.c	2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-eb5c62-romstage.c	2010-10-05 03:03:59.781444095 +0200
@@ -135,17 +135,11 @@ static void sio_setup(void)
         uint32_t dword;
         uint8_t byte;
 
-        byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20;
-        pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
-
-        dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0);
-        dword |= (1<<0);
-        pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
-
-        dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4);
-        dword |= (1<<16);
-        pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
+        pci_set8(PCI_DEV(0, SIS966_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+        pci_set32(PCI_DEV(0, SIS966_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+        pci_set32(PCI_DEV(0, SIS966_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/gigabyte/m57sli/romstage.c	2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-e149a2-romstage.c	2010-10-05 03:04:00.145443945 +0200
@@ -137,17 +137,11 @@ static void sio_setup(void)
         uint32_t dword;
         uint8_t byte;
 
-        byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20;
-        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
-        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-        dword |= (1<<0);
-        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
-        dword |= (1<<16);
-        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+        pci_set8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, 0x20);
+
+        pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, (1 << 0));
+
+        pci_set32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, (1 << 16));
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--- src/mainboard/gigabyte/ma78gm/mainboard.c	2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-d453a7-mainboard.c	2010-10-05 03:04:00.521446761 +0200
@@ -60,10 +60,7 @@ void set_pcie_reset()
 	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
-	word = pci_read_config16(sm_dev, 0xA8);
-	word &= ~((1 << 0) | (1 << 2));	/* Set Gpio6,4 as output */
-	word &= ~((1 << 8) | (1 << 10));
-	pci_write_config16(sm_dev, 0xA8, word);
+	pci_clear16(sm_dev, 0xA8, (((1 << 0) | (1 << 2)) | ((1 << 8) | (1 << 10))));
 }
 
 
--- src/mainboard/gigabyte/ma785gmt/mainboard.c	2010-10-01 09:27:09.000000000 +0200
+++ /tmp/cocci-output-5159-310315-mainboard.c	2010-10-05 03:04:00.793446056 +0200
@@ -95,10 +95,7 @@ void set_pcie_reset()
 
 	/* set the GPIO65 output enable and the value is 0 */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x7e);
-	word &= ~(1 << 0);
-	word &= ~(1 << 4);
-	pci_write_config16(sm_dev, 0x7e, word);
+	pci_clear16(sm_dev, 0x7e, ((1 << 0) | (1 << 4)));
 }
 
 
@@ -115,9 +112,7 @@ int is_dev3_present(void)
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
 	/* put the GPIO68 output to tristate */
-	word = pci_read_config16(sm_dev, 0x7e);
-	word |= 1 << 6;
-	pci_write_config16(sm_dev, 0x7e,word);
+	pci_set16(sm_dev, 0x7e, 1 << 6);
 
 	/* read the GPIO68 input status */
 	word = pci_read_config16(sm_dev, 0x7e);
@@ -178,13 +173,7 @@ static void set_gpio40_gfx(void)
 		printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
 		/* when the gpio40 is configured as GPIO, this will enable the output */
 		pci_write_config32(sm_dev, 0xf8, 0x4);
-		dword = pci_read_config32(sm_dev, 0xfc);
-		dword &= ~(1 << 10);
-
-        	/* When the gpio40 is configured as GPIO, this will represent the output value*/
-		/* 1 :enable two x8  , 0 : master slot enable only */
-		dword &=  ~(1 << 26);
-		pci_write_config32(sm_dev, 0xfc, dword);
+		pci_clear32(sm_dev, 0xfc, ((1 << 10) | (1 << 26)));
 	}
 }
 
@@ -218,9 +207,7 @@ static void set_thermal_config(void)
 
 	/* set GPIO 64 to input */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x56);
-	word |= 1 << 7;
-	pci_write_config16(sm_dev, 0x56, word);
+	pci_set16(sm_dev, 0x56, 1 << 7);
 
 	/* set GPIO 64 internal pull-up */
 	byte = pm2_ioread(0xf0);

From david.hendricks at gmail.com  Tue Oct  5 07:59:31 2010
From: david.hendricks at gmail.com (David Hendricks)
Date: Mon, 4 Oct 2010 22:59:31 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <20101004192314.7903.qmail@stuge.se>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
	<4CA978ED.8000002@georgi-clan.de> <201010041950.25088.phorsyon@gmx.net>
	<20101004192314.7903.qmail@stuge.se>
Message-ID: <AANLkTimROPLy7jwLcLhNDF0SPNL6R-hw2HS6YPi0zm_B@mail.gmail.com>

On Mon, Oct 4, 2010 at 12:23 PM, Peter Stuge <peter at stuge.se> wrote:

> phorsyon wrote:
> > a minimal and a consumer version of a certificate
>
> As was mentioned, the more certifications there are, the less easy it
> is for the market to make use of them.
>
> I don't think we can afford to try to market two different
> certifications. I would only like to try for one; "consumer coreboot"
> or rather; "coreboot complete"
>
> Developers don't want problems any more than average users just
> because they may know how to deal with problems.
>
> Anyway, if we would have criteria then we could also track them.
>
> Any interested developer could easily discover what was missing for
> a board to be coreboot complete, judge if it is a good choice for
> them at the moment, and if not just look for completeness of other
> boards.


I agree with Peter here, and will add my $0.02 to the thread...

Certification is a *huge* process, at least if you want it to mean anything.
I would expect that a true certification effort would rival development of
the code itself. Multiple levels of certification only complicate the
process and confuse users. And quite honestly, I don't expect that to happen
unless a lot of dedicated resources are poured into it.

Perhaps the best thing is simply to publish a giant testing matrix for each
board. Certify against the absolute bare minimum technical requirements, ie,
can all on-board devices be initialized by firmware, are SMBIOS tables
populated, etc. Leave it up to the system builder to decide whether or not
if it's usable for the application.

Maybe someone (FSF?) wants to create a higher-level standard that includes
Coreboot along with a full free software stack, but that shouldn't be key to
Coreboot certification at any level or you risk alienating major commercial
partners. Heck, everyone in the Coreboot community ought to be flattered if
a major OEM ships a "Made for Win7" computer with Coreboot on it.

Certify stuff that you know, leave everything else up to vendors.
-------------- next part --------------
An HTML attachment was scrubbed...
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From arne.gleditsch at numascale.com  Tue Oct  5 09:43:59 2010
From: arne.gleditsch at numascale.com (Arne Georg Gleditsch)
Date: Tue, 05 Oct 2010 09:43:59 +0200
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <20101005014518.15748.qmail@stuge.se> (Peter Stuge's message of
	"Tue, 5 Oct 2010 03:45:17 +0200")
References: <20101003231014.23261.qmail@stuge.se>
	<AANLkTi=tjwp-YjfJvEi_aQXk9Ozdf++qVXcgTuDzhHeH@mail.gmail.com>
	<20101005014518.15748.qmail@stuge.se>
Message-ID: <87mxqt2if4.fsf@taniquetil.gledits.ch>

Peter Stuge <peter at stuge.se> writes:
> I think the ratio of simple vs. complex operations is significant.
> The majority I've seen in the code are simple, but granted I haven't
> read every file. I agree that mixed idioms are annoying if nothing
> else, but I think the benefit from replacing all the simple cases is
> important enough to do it.

I'll add my couple of cents here as well: I think this change is a win.
I acknowledge the concern about mixed idioms, but I think the
simplification in the general case outweighs it.

I think I prefer the names pci_set_configX and pci_clear_configX,
though.  In the cases where you need to mix idioms, I feel they make it
more obvious that you deal with the same components as
pci_{read,write}_configX.  I'd also consider using "setb" and "clearb"
just to make it explicit that the functions operate on individual bits
and not the entire register, but that's secondary.

(Finally, I think it might be worthwhile to add
pci_clear_and_set_configX as well.)

-- 
							Arne.



From wt at penguintechs.org  Tue Oct  5 10:26:38 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Tue, 5 Oct 2010 01:26:38 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTimROPLy7jwLcLhNDF0SPNL6R-hw2HS6YPi0zm_B@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
	<4CA978ED.8000002@georgi-clan.de> <201010041950.25088.phorsyon@gmx.net>
	<20101004192314.7903.qmail@stuge.se>
	<AANLkTimROPLy7jwLcLhNDF0SPNL6R-hw2HS6YPi0zm_B@mail.gmail.com>
Message-ID: <AANLkTikStpx9167n_eC4FyQovxRu-nZtYujEWW3Kxnh8@mail.gmail.com>

On Mon, Oct 4, 2010 at 10:59 PM, David Hendricks
<david.hendricks at gmail.com> wrote:
> On Mon, Oct 4, 2010 at 12:23 PM, Peter Stuge <peter at stuge.se> wrote:
>>
>> phorsyon wrote:
>> > a minimal and a consumer version of a certificate
>>
>> As was mentioned, the more certifications there are, the less easy it
>> is for the market to make use of them.
>>
>> I don't think we can afford to try to market two different
>> certifications. I would only like to try for one; "consumer coreboot"
>> or rather; "coreboot complete"
>>
>> Developers don't want problems any more than average users just
>> because they may know how to deal with problems.
>>
>> Anyway, if we would have criteria then we could also track them.
>>
>> Any interested developer could easily discover what was missing for
>> a board to be coreboot complete, judge if it is a good choice for
>> them at the moment, and if not just look for completeness of other
>> boards.
>
> I agree with Peter here, and will add my $0.02 to the thread...
> Certification is a *huge* process, at least if you want it to mean anything.
> I would expect that a true certification effort would rival development of
> the code itself. Multiple levels of certification only complicate the
> process and confuse users. And quite honestly, I don't expect that to happen
> unless a lot of dedicated resources are poured into it.

Agreed.

> Perhaps the best thing is simply to publish a giant testing matrix for each
> board.

This would certainly be a huge improvement. Maybe this should be our
actual first step?

> Certify against the absolute bare minimum technical requirements, ie,
> can all on-board devices be initialized by firmware, are SMBIOS tables
> populated, etc.

I actually fully agree with this. However, we would need some way to
tell if things like the SMBIOS tables are populated. That means that
we'd need some form of software to run after the coreboot step to
verify. Since we don't have a piece of software that is only that, how
do we test for certification? I see a couple options:
* don't certify anything until we develop a coreboot confirmation
payload of some type
* certify based on some software stack that we can currently use

Given that I don't see a coreboot confirmation payload being developed
overnight, I would think that we should start with some software stack
that we can currently use. In my eyes, this means using some easy to
obtain Linux distribution and a bit of software to test compliance
with some set of standards.

How would others solve the problem of testing for compliance?

> Leave it up to the system builder to decide whether or not
> if it's usable for the application.

Agreed.

> Maybe someone (FSF?) wants to create a higher-level standard that includes
> Coreboot along with a full free software stack, but that shouldn't be key to
> Coreboot certification at any level or you risk alienating major commercial
> partners.

Agreed. I wasn't trying to place a higher-level standard like "Works
with Linux." I was trying to find the lowest barrier way to test for
some minimum level of compliance.

> Heck, everyone in the Coreboot community ought to be flattered if
> a major OEM ships a "Made for Win7" computer with Coreboot on it.
> Certify stuff that you know, leave everything else up to vendors.

I think this is one of the best perspective statements in this thread so far. :)

Thanks,
wt



From corey.osgood at gmail.com  Tue Oct  5 10:32:48 2010
From: corey.osgood at gmail.com (Corey Osgood)
Date: Tue, 5 Oct 2010 04:32:48 -0400
Subject: [coreboot] PCI register read/mod/write code
In-Reply-To: <AANLkTi=tjwp-YjfJvEi_aQXk9Ozdf++qVXcgTuDzhHeH@mail.gmail.com>
References: <20101003231014.23261.qmail@stuge.se>
	<AANLkTi=tjwp-YjfJvEi_aQXk9Ozdf++qVXcgTuDzhHeH@mail.gmail.com>
Message-ID: <AANLkTikM7KB-udX9W-G80Ub6t1S1qgo25r-y76579okV@mail.gmail.com>

On Mon, Oct 4, 2010 at 6:14 PM, ron minnich <rminnich at gmail.com> wrote:
> On Sun, Oct 3, 2010 at 4:10 PM, Peter Stuge <peter at stuge.se> wrote:
>> Rudolf just found a bug in the sb700 code:
>>
>> u32 dword;
>> ..
>> dword = pci_read_config8(dev, 0x64);
>> dword |= 1 << 10;
>> pci_write_config8(dev, 0x64, dword);
>
>
> Actually, I don't even have a problem with this construct. Why?
> Because it's in just about every kernel I've ever worked with. It's a
> common technique. Sure, in this case, it's a trivially simple change
> and you can write a function for it. But, as soon as things get more
> complex, with multiline tests and bit sets, you can't use the
> functions, and we're back to the same type of coding. Then we end up
> with mixed idioms.
>
> It's a good idea for our code base to adhere to such common idioms. It
> makes for an easier time for people coming in from, e.g., Linux. I
> don't find the functions easier.
>
> Also, as pointed out, the proposed functions solve one special case.
> Better to fix the real problem, which is that the compiler can tell us
> about this type of error but we're not letting it. That will fix all
> such problems, not just the pci subsystem.
>
> Just another penny or so.
>
> ron

I'm fully in agreement with Ron here. Lets fix whatever's broken so we
can let the compiler tell us when we make foolish mistakes, rather
then writing some mess that's sure to cause some WTFs down the road.
This is *one* instance in which someone used an 8-bit instead of a
16-bit function by mistake. Lets not go nuts trying to idiot-proof
things. Instead of hacking away at all the pci functions, and almost
definitely causing some unintended breakage, can't we just pay a
little more attention during reviews?

-Corey



From r.marek at assembler.cz  Tue Oct  5 10:59:52 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 05 Oct 2010 10:59:52 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTikStpx9167n_eC4FyQovxRu-nZtYujEWW3Kxnh8@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net>	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>	<4CA978ED.8000002@georgi-clan.de>
	<201010041950.25088.phorsyon@gmx.net>	<20101004192314.7903.qmail@stuge.se>	<AANLkTimROPLy7jwLcLhNDF0SPNL6R-hw2HS6YPi0zm_B@mail.gmail.com>
	<AANLkTikStpx9167n_eC4FyQovxRu-nZtYujEWW3Kxnh8@mail.gmail.com>
Message-ID: <4CAAE908.5090708@assembler.cz>

Hi,

Maybe good start to use some existing test suite

http://www.h-online.com/open/news/item/Ubuntu-Kernel-Developer-releases-Firmware-Test-Suite-1053102.html

http://smackerelofopinion.blogspot.com/2010/08/firmware-test-suite-biosacpi-health.html

https://launchpad.net/~firmware-testing-team
http://linuxfirmwarekit.org/


This is based on http://linuxfirmwarekit.org/

Thanks,
Rudolf



From svn at coreboot.org  Tue Oct  5 11:07:10 2010
From: svn at coreboot.org (repository service)
Date: Tue, 05 Oct 2010 11:07:10 +0200
Subject: [coreboot] [commit] r5910 - in trunk: src/lib
	src/mainboard/amd/db800 src/mainboard/amd/mahogany_fam10
	src/mainboard/amd/norwich src/mainboard/amd/rumba
	src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard...
Message-ID: <E1P33UM-0000hH-QC@ra.coresystems.de>

Author: oxygene
Date: Tue Oct  5 11:07:10 2010
New Revision: 5910
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5910

Log:
Remove lib/ramtest.c-include from all CAR boards.
Remove many more .c-includes from i945 based boards.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/lib/Makefile.inc
   trunk/src/lib/ramtest.c
   trunk/src/mainboard/amd/db800/romstage.c
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/norwich/romstage.c
   trunk/src/mainboard/amd/rumba/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
   trunk/src/mainboard/amd/tilapia_fam10/romstage.c
   trunk/src/mainboard/arima/hdama/romstage.c
   trunk/src/mainboard/artecgroup/dbe61/romstage.c
   trunk/src/mainboard/asus/a8n_e/romstage.c
   trunk/src/mainboard/asus/m4a785-m/romstage.c
   trunk/src/mainboard/bcom/winnetp680/romstage.c
   trunk/src/mainboard/broadcom/blast/romstage.c
   trunk/src/mainboard/digitallogic/adl855pc/romstage.c
   trunk/src/mainboard/digitallogic/msm800sev/romstage.c
   trunk/src/mainboard/getac/p470/romstage.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
   trunk/src/mainboard/gigabyte/m57sli/romstage.c
   trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
   trunk/src/mainboard/gigabyte/ma78gm/romstage.c
   trunk/src/mainboard/hp/dl145_g1/romstage.c
   trunk/src/mainboard/hp/dl145_g3/romstage.c
   trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
   trunk/src/mainboard/ibase/mb899/romstage.c
   trunk/src/mainboard/ibm/e325/romstage.c
   trunk/src/mainboard/ibm/e326/romstage.c
   trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
   trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
   trunk/src/mainboard/intel/d810e2cb/romstage.c
   trunk/src/mainboard/intel/d945gclf/romstage.c
   trunk/src/mainboard/intel/eagleheights/romstage.c
   trunk/src/mainboard/intel/mtarvon/romstage.c
   trunk/src/mainboard/iwill/dk8_htx/romstage.c
   trunk/src/mainboard/iwill/dk8s2/romstage.c
   trunk/src/mainboard/iwill/dk8x/romstage.c
   trunk/src/mainboard/jetway/j7f24/romstage.c
   trunk/src/mainboard/jetway/pa78vm5/romstage.c
   trunk/src/mainboard/kontron/986lcd-m/romstage.c
   trunk/src/mainboard/lanner/em8510/romstage.c
   trunk/src/mainboard/lippert/frontrunner/romstage.c
   trunk/src/mainboard/lippert/hurricane-lx/romstage.c
   trunk/src/mainboard/lippert/literunner-lx/romstage.c
   trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
   trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
   trunk/src/mainboard/msi/ms7135/romstage.c
   trunk/src/mainboard/msi/ms7260/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/romstage.c
   trunk/src/mainboard/newisys/khepri/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
   trunk/src/mainboard/pcengines/alix1c/romstage.c
   trunk/src/mainboard/pcengines/alix2d/romstage.c
   trunk/src/mainboard/rca/rm4100/romstage.c
   trunk/src/mainboard/roda/rk886ex/romstage.c
   trunk/src/mainboard/sunw/ultra40/romstage.c
   trunk/src/mainboard/supermicro/h8dme/romstage.c
   trunk/src/mainboard/supermicro/h8dmr/romstage.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
   trunk/src/mainboard/thomson/ip1000/romstage.c
   trunk/src/mainboard/traverse/geos/romstage.c
   trunk/src/mainboard/tyan/s2735/romstage.c
   trunk/src/mainboard/tyan/s2850/romstage.c
   trunk/src/mainboard/tyan/s2875/romstage.c
   trunk/src/mainboard/tyan/s2880/romstage.c
   trunk/src/mainboard/tyan/s2881/romstage.c
   trunk/src/mainboard/tyan/s2882/romstage.c
   trunk/src/mainboard/tyan/s2885/romstage.c
   trunk/src/mainboard/tyan/s2891/romstage.c
   trunk/src/mainboard/tyan/s2892/romstage.c
   trunk/src/mainboard/tyan/s2895/romstage.c
   trunk/src/mainboard/tyan/s2912/romstage.c
   trunk/src/mainboard/tyan/s2912_fam10/romstage.c
   trunk/src/mainboard/tyan/s4880/romstage.c
   trunk/src/mainboard/tyan/s4882/romstage.c
   trunk/src/mainboard/via/epia-cn/romstage.c
   trunk/src/mainboard/via/epia-m700/romstage.c
   trunk/src/mainboard/via/pc2500e/romstage.c
   trunk/src/mainboard/via/vt8454c/romstage.c
   trunk/src/mainboard/winent/pl6064/romstage.c
   trunk/src/mainboard/wyse/s50/romstage.c
   trunk/src/northbridge/intel/i945/Makefile.inc
   trunk/src/northbridge/intel/i945/debug.c
   trunk/src/northbridge/intel/i945/early_init.c
   trunk/src/northbridge/intel/i945/errata.c
   trunk/src/northbridge/intel/i945/i945.h
   trunk/src/northbridge/intel/i945/raminit.c
   trunk/src/northbridge/intel/i945/raminit.h
   trunk/src/northbridge/intel/i945/udelay.c
   trunk/src/pc80/Makefile.inc
   trunk/src/southbridge/intel/i82801gx/Makefile.inc
   trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h
   trunk/util/abuild/abuild

Modified: trunk/src/lib/Makefile.inc
==============================================================================
--- trunk/src/lib/Makefile.inc	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/lib/Makefile.inc	Tue Oct  5 11:07:10 2010	(r5910)
@@ -21,6 +21,7 @@
 romstage-y += memcmp.c
 romstage-y += cbfs.c
 romstage-y += lzma.c
+romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
 #romstage-y += lzmadecode.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c

Modified: trunk/src/lib/ramtest.c
==============================================================================
--- trunk/src/lib/ramtest.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/lib/ramtest.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -1,4 +1,6 @@
+#include <stdint.h>
 #include <lib.h> /* Prototypes */
+#include <console/console.h>
 
 static void write_phys(unsigned long addr, u32 value)
 {

Modified: trunk/src/mainboard/amd/db800/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/db800/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/amd/db800/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -25,7 +25,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -45,10 +45,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

Modified: trunk/src/mainboard/amd/norwich/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/norwich/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/amd/norwich/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -25,7 +25,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/amd/rumba/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/rumba/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/amd/rumba/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -4,7 +4,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -45,11 +45,11 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -45,10 +45,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

Modified: trunk/src/mainboard/arima/hdama/romstage.c
==============================================================================
--- trunk/src/mainboard/arima/hdama/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/arima/hdama/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -7,7 +7,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/artecgroup/dbe61/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -48,7 +48,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -45,10 +45,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c
==============================================================================
--- trunk/src/mainboard/bcom/winnetp680/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/bcom/winnetp680/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -27,11 +27,11 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
+#include <lib.h>
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)

Modified: trunk/src/mainboard/broadcom/blast/romstage.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/broadcom/blast/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -13,7 +13,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/adl855pc/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -8,7 +8,6 @@
 #include "pc80/udelay_io.c"
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"

Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm800sev/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -6,7 +6,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/getac/p470/romstage.c
==============================================================================
--- trunk/src/mainboard/getac/p470/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/getac/p470/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -26,24 +26,20 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
+#include <lib.h>
 
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 
-#include "northbridge/intel/i945/udelay.c"
+void enable_smbus(void);
 
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void setup_ich7_gpios(void)
 {
 	u32 gpios;
 
@@ -87,18 +83,6 @@
 	outl(gpios, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -55,7 +55,6 @@
 #include "southbridge/sis/sis966/sis966_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -53,7 +53,6 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -41,10 +41,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -45,10 +45,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/hp/dl145_g1/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -13,7 +13,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/hp/dl145_g3/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -55,7 +55,6 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -49,11 +49,11 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/amd/model_10xxx/apic_timer.c"
 #include "lib/delay.c"

Modified: trunk/src/mainboard/ibase/mb899/romstage.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/ibase/mb899/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -26,6 +26,7 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
+#include <lib.h>
 
 #include "superio/winbond/w83627ehg/w83627ehg.h"
 
@@ -34,21 +35,17 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 
-#include "northbridge/intel/i945/udelay.c"
-
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
 
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+
+void enable_smbus(void);
+
+void setup_ich7_gpios(void)
 {
 	printk(BIOS_DEBUG, " GPIOS...");
 	/* General Registers */
@@ -64,18 +61,6 @@
 	outl(0x00010035, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ

Modified: trunk/src/mainboard/ibm/e325/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e325/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/ibm/e325/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -9,7 +9,6 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/ibm/e326/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e326/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/ibm/e326/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -9,7 +9,6 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -48,10 +48,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -25,7 +25,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/intel/d810e2cb/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/d810e2cb/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/intel/d810e2cb/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -26,7 +26,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801bx/i82801bx.h"
 #include "southbridge/intel/i82801bx/i82801bx_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"
@@ -36,6 +35,7 @@
 #include "cpu/x86/bist.h"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "gpio.c"
+#include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 

Modified: trunk/src/mainboard/intel/d945gclf/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/intel/d945gclf/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -26,6 +26,7 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
+#include <lib.h>
 
 #include "superio/smsc/lpc47m15x/lpc47m15x.h"
 
@@ -34,21 +35,17 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
 #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
 
-#include "northbridge/intel/i945/udelay.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
 
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+
+void enable_smbus(void);
+
+void setup_ich7_gpios(void)
 {
 	/* TODO: This is highly board specific and should be moved */
 	printk(BIOS_DEBUG, " GPIOS...");
@@ -65,18 +62,6 @@
 	outl(0x000300fd, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ

Modified: trunk/src/mainboard/intel/eagleheights/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/intel/eagleheights/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -34,7 +34,6 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "reset.c"

Modified: trunk/src/mainboard/intel/mtarvon/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/mtarvon/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/intel/mtarvon/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -28,7 +28,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "northbridge/intel/i3100/raminit.h"

Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -91,7 +91,6 @@
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "lib/ramtest.c"
 
  /* tyan does not want the default */
 #include "resourcemap.c"

Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -91,7 +91,6 @@
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "lib/ramtest.c"
 
  /* tyan does not want the default */
 #include "northbridge/amd/amdk8/resourcemap.c"

Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -91,7 +91,6 @@
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "lib/ramtest.c"
 
  /* tyan does not want the default */
 #include "northbridge/amd/amdk8/resourcemap.c"

Modified: trunk/src/mainboard/jetway/j7f24/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/j7f24/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/jetway/j7f24/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -27,13 +27,13 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
+#include <lib.h>
 
 #if CONFIG_TTYS0_BASE == 0x2f8
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)

Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -46,10 +46,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/kontron/986lcd-m/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -21,6 +21,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <lib.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
@@ -35,21 +36,17 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
 
-#include "northbridge/intel/i945/udelay.c"
+void enable_smbus(void);
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
 
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+
+void setup_ich7_gpios(void)
 {
 	printk(BIOS_DEBUG, " GPIOS...");
 	/* General Registers */
@@ -65,18 +62,6 @@
 	outl(0x00010035, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ

Modified: trunk/src/mainboard/lanner/em8510/romstage.c
==============================================================================
--- trunk/src/mainboard/lanner/em8510/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/lanner/em8510/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -30,7 +30,6 @@
 #include "pc80/udelay_io.c"
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"

Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/lippert/frontrunner/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -4,7 +4,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/hurricane-lx/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -28,7 +28,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/literunner-lx/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/lippert/literunner-lx/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -29,7 +29,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -28,7 +28,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -29,7 +29,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/msi/ms7135/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/msi/ms7135/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -49,7 +49,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/msi/ms7260/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -56,12 +56,12 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -46,7 +46,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>
 

Modified: trunk/src/mainboard/newisys/khepri/romstage.c
==============================================================================
--- trunk/src/mainboard/newisys/khepri/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/newisys/khepri/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -14,7 +14,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -53,7 +53,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix1c/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/pcengines/alix1c/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix2d/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/pcengines/alix2d/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/rca/rm4100/romstage.c
==============================================================================
--- trunk/src/mainboard/rca/rm4100/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/rca/rm4100/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -27,7 +27,7 @@
 #include <arch/hlt.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"

Modified: trunk/src/mainboard/roda/rk886ex/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/roda/rk886ex/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -28,24 +28,20 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
+#include <lib.h>
 
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 
-#include "northbridge/intel/i945/udelay.c"
+void enable_smbus(void);
 
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void setup_ich7_gpios(void)
 {
 	printk(BIOS_DEBUG, " GPIOS...");
 	/* General Registers */
@@ -61,18 +57,6 @@
 	outl(0x00010030, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ

Modified: trunk/src/mainboard/sunw/ultra40/romstage.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/sunw/ultra40/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -16,7 +16,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -46,7 +46,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -49,7 +49,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -43,7 +43,7 @@
 #include <cpu/x86/lapic.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>
 

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -43,7 +43,7 @@
 #include <cpu/x86/lapic.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>
 

Modified: trunk/src/mainboard/thomson/ip1000/romstage.c
==============================================================================
--- trunk/src/mainboard/thomson/ip1000/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/thomson/ip1000/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -28,7 +28,7 @@
 #include <arch/llshell.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"

Modified: trunk/src/mainboard/traverse/geos/romstage.c
==============================================================================
--- trunk/src/mainboard/traverse/geos/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/traverse/geos/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -25,7 +25,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/tyan/s2735/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2735/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2735/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -8,7 +8,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"

Modified: trunk/src/mainboard/tyan/s2850/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2850/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2850/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/tyan/s2875/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2875/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2875/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/tyan/s2880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2880/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2880/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/tyan/s2881/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2881/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -13,7 +13,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/tyan/s2882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2882/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2882/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/tyan/s2885/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2885/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -8,7 +8,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2891/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -14,7 +14,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/tyan/s2892/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2892/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -14,7 +14,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2895/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -15,7 +15,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"

Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2912/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -53,7 +53,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -46,7 +46,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>
 

Modified: trunk/src/mainboard/tyan/s4880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4880/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s4880/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/tyan/s4882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4882/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/tyan/s4882/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -8,7 +8,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/via/epia-cn/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-cn/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/via/epia-cn/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -27,7 +27,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"

Modified: trunk/src/mainboard/via/epia-m700/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m700/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/via/epia-m700/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -33,7 +33,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "northbridge/via/vx800/vx800.h"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"

Modified: trunk/src/mainboard/via/pc2500e/romstage.c
==============================================================================
--- trunk/src/mainboard/via/pc2500e/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/via/pc2500e/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -27,7 +27,7 @@
 #include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"

Modified: trunk/src/mainboard/via/vt8454c/romstage.c
==============================================================================
--- trunk/src/mainboard/via/vt8454c/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/via/vt8454c/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -27,7 +27,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "northbridge/via/cx700/raminit.h"
 #include "cpu/x86/bist.h"
 

Modified: trunk/src/mainboard/winent/pl6064/romstage.c
==============================================================================
--- trunk/src/mainboard/winent/pl6064/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/winent/pl6064/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

Modified: trunk/src/mainboard/wyse/s50/romstage.c
==============================================================================
--- trunk/src/mainboard/wyse/s50/romstage.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/mainboard/wyse/s50/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -25,7 +25,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>

Modified: trunk/src/northbridge/intel/i945/Makefile.inc
==============================================================================
--- trunk/src/northbridge/intel/i945/Makefile.inc	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/northbridge/intel/i945/Makefile.inc	Tue Oct  5 11:07:10 2010	(r5910)
@@ -20,3 +20,9 @@
 driver-y += northbridge.c
 driver-y += gma.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+romstage-y += udelay.c
+romstage-y += raminit.c
+romstage-y += early_init.c
+romstage-y += errata.c
+romstage-y += debug.c

Modified: trunk/src/northbridge/intel/i945/debug.c
==============================================================================
--- trunk/src/northbridge/intel/i945/debug.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/northbridge/intel/i945/debug.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -19,11 +19,18 @@
  * MA 02110-1301 USA
  */
 
+#include <lib.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
+#include "i945.h"
+
 #define SMBUS_MEM_DEVICE_START 0x50
 #define SMBUS_MEM_DEVICE_END 0x53
 #define SMBUS_MEM_DEVICE_INC 1
 
-static inline void print_pci_devices(void)
+void print_pci_devices(void)
 {
 	device_t dev;
 	for(dev = PCI_DEV(0, 0, 0);
@@ -42,7 +49,7 @@
 	}
 }
 
-static inline void dump_pci_device(unsigned dev)
+void dump_pci_device(unsigned dev)
 {
 	int i;
 
@@ -61,7 +68,7 @@
 	}
 }
 
-static inline void dump_pci_devices(void)
+void dump_pci_devices(void)
 {
 	device_t dev;
 	for(dev = PCI_DEV(0, 0, 0);
@@ -78,7 +85,7 @@
 	}
 }
 
-static inline void dump_spd_registers(void)
+void dump_spd_registers(void)
 {
         unsigned device;
         device = SMBUS_MEM_DEVICE_START;
@@ -103,7 +110,7 @@
 	}
 }
 
-static inline void dump_mem(unsigned start, unsigned end)
+void dump_mem(unsigned start, unsigned end)
 {
         unsigned i;
 	print_debug("dump_mem:");

Modified: trunk/src/northbridge/intel/i945/early_init.c
==============================================================================
--- trunk/src/northbridge/intel/i945/early_init.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/northbridge/intel/i945/early_init.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -17,10 +17,16 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdint.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
 #include "i945.h"
 #include "pcie_config.c"
 
-static int i945_silicon_revision(void)
+int i945_silicon_revision(void)
 {
 	return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION);
 }
@@ -856,7 +862,7 @@
 	pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
 }
 
-static void i945_early_initialization(void)
+void i945_early_initialization(void)
 {
 	/* Print some chipset specific information */
 	switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) {
@@ -879,7 +885,7 @@
 	RCBA32(0x2010) |= (1 << 10);
 }
 
-static void i945_late_initialization(void)
+void i945_late_initialization(void)
 {
 	i945_setup_egress_port();
 

Modified: trunk/src/northbridge/intel/i945/errata.c
==============================================================================
--- trunk/src/northbridge/intel/i945/errata.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/northbridge/intel/i945/errata.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdint.h>
+#include "i945.h"
 #include "raminit.h"
 
 int fixup_i945_errata(void)

Modified: trunk/src/northbridge/intel/i945/i945.h
==============================================================================
--- trunk/src/northbridge/intel/i945/i945.h	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/northbridge/intel/i945/i945.h	Tue Oct  5 11:07:10 2010	(r5910)
@@ -333,5 +333,22 @@
 
 static inline void barrier(void) { asm("" ::: "memory"); }
 
+int i945_silicon_revision(void);
+void i945_early_initialization(void);
+void i945_late_initialization(void);
+
+/* provided by southbridge code */
+int smbus_read_byte(unsigned device, unsigned address);
+
+/* provided by mainboard code */
+void setup_ich7_gpios(void);
+
+/* debugging functions */
+void print_pci_devices(void);
+void dump_pci_device(unsigned dev);
+void dump_pci_devices(void);
+void dump_spd_registers(void);
+void dump_mem(unsigned start, unsigned end);
+
 #endif
 #endif

Modified: trunk/src/northbridge/intel/i945/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/i945/raminit.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/northbridge/intel/i945/raminit.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -17,10 +17,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <pc80/mc146818rtc.h>
 #include <spd.h>
+#include <string.h>
+#include <arch/romcc_io.h>
 #include "raminit.h"
 #include "i945.h"
 
@@ -45,6 +48,11 @@
 #define RAM_EMRS_2			(0x1 << 21)
 #define RAM_EMRS_3			(0x2 << 21)
 
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
 static __attribute__((noinline)) void do_ram_command(u32 command)
 {
 	u32 reg32;

Modified: trunk/src/northbridge/intel/i945/raminit.h
==============================================================================
--- trunk/src/northbridge/intel/i945/raminit.h	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/northbridge/intel/i945/raminit.h	Tue Oct  5 11:07:10 2010	(r5910)
@@ -71,4 +71,6 @@
 void sdram_initialize(int boot_path);
 unsigned long get_top_of_ram(void);
 int fixup_i945_errata(void);
+void udelay(u32 us);
+
 #endif				/* RAMINIT_H */

Modified: trunk/src/northbridge/intel/i945/udelay.c
==============================================================================
--- trunk/src/northbridge/intel/i945/udelay.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/northbridge/intel/i945/udelay.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -18,6 +18,7 @@
  */
 
 #include <delay.h>
+#include <stdint.h>
 #include <cpu/x86/tsc.h>
 #include <cpu/x86/msr.h>
 

Modified: trunk/src/pc80/Makefile.inc
==============================================================================
--- trunk/src/pc80/Makefile.inc	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/pc80/Makefile.inc	Tue Oct  5 11:07:10 2010	(r5910)
@@ -6,6 +6,7 @@
 
 romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c
 romstage-$(CONFIG_CACHE_AS_RAM) += serial.c
+romstage-$(CONFIG_USBDEBUG) += usbdebug_serial.c
 subdirs-y += vga
 
 $(obj)/pc80/mc146818rtc.ramstage.o : $(OPTION_TABLE_H)

Modified: trunk/src/southbridge/intel/i82801gx/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/Makefile.inc	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/southbridge/intel/i82801gx/Makefile.inc	Tue Oct  5 11:07:10 2010	(r5910)
@@ -35,3 +35,7 @@
 
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smi.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smihandler.c
+
+romstage-y += i82801gx_early_smbus.c
+romstage-$(CONFIG_USBDEBUG) += i82801gx_usb_debug.c
+

Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c	Tue Oct  5 11:07:10 2010	(r5910)
@@ -18,11 +18,17 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
 #include <device/pci_ids.h>
+#include <device/pci_def.h>
 #include "i82801gx.h"
 #include "i82801gx_smbus.h"
 
-static void enable_smbus(void)
+int smbus_read_byte(unsigned device, unsigned address);
+
+void enable_smbus(void)
 {
 	device_t dev;
 
@@ -52,7 +58,7 @@
 	print_debug("SMBus controller enabled.\n");
 }
 
-static inline int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned device, unsigned address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }

Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h	Tue Oct  5 11:07:10 2010	(r5910)
@@ -20,6 +20,8 @@
 
 #include <device/smbus_def.h>
 
+void enable_smbus(void);
+
 static void smbus_delay(void)
 {
 	inb(0x80);

Modified: trunk/util/abuild/abuild
==============================================================================
--- trunk/util/abuild/abuild	Mon Oct  4 22:43:55 2010	(r5909)
+++ trunk/util/abuild/abuild	Tue Oct  5 11:07:10 2010	(r5910)
@@ -203,6 +203,7 @@
 			echo "CONFIG_SCANBUILD_ENABLE=y" >> .config
 			echo "CONFIG_SCANBUILD_REPORT_LOCATION=\"$TARGET/scan-build-results-tmp\"" >> .config
 		fi
+		echo "CONFIG_USBDEBUG=y" >> .config
 	fi
 
 	#yes "" | $MAKE oldconfig -j $cpus obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log



From svn at coreboot.org  Tue Oct  5 11:24:33 2010
From: svn at coreboot.org (repository service)
Date: Tue, 05 Oct 2010 11:24:33 +0200
Subject: [coreboot] build service results for r5910
Message-ID: <E1P33lB-0001ES-6u@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5910 to
the coreboot repository. This caused the following 
changes:

Change Log:
Remove lib/ramtest.c-include from all CAR boards.
Remove many more .c-includes from i945 based boards.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Build Log:
Compilation of amd:dbm690t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=dbm690t&vendor=amd&num=2
Compilation of amd:mahogany has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=mahogany&vendor=amd&num=2
Compilation of amd:mahogany_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=mahogany_fam10&vendor=amd&num=2
Compilation of amd:pistachio has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=pistachio&vendor=amd&num=2
Compilation of amd:tilapia_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=tilapia_fam10&vendor=amd&num=2
Compilation of asrock:939a785gmh has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=939a785gmh&vendor=asrock&num=2
Compilation of asus:a8n_e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=a8n_e&vendor=asus&num=2
Compilation of asus:m4a785-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=m4a785-m&vendor=asus&num=2
Compilation of getac:p470 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=p470&vendor=getac&num=2
Compilation of gigabyte:ga_2761gxdk has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ga_2761gxdk&vendor=gigabyte&num=2
Compilation of gigabyte:m57sli has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=m57sli&vendor=gigabyte&num=2
Compilation of gigabyte:ma785gmt has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ma785gmt&vendor=gigabyte&num=2
Compilation of gigabyte:ma78gm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ma78gm&vendor=gigabyte&num=2
Compilation of ibase:mb899 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=mb899&vendor=ibase&num=2
Compilation of iei:kino-780am2-fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=kino-780am2-fam10&vendor=iei&num=2
Compilation of intel:d945gclf has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=d945gclf&vendor=intel&num=2
Compilation of jetway:pa78vm5 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=pa78vm5&vendor=jetway&num=2
Compilation of kontron:986lcd-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=986lcd-m&vendor=kontron&num=2
Compilation of kontron:kt690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=kt690&vendor=kontron&num=2
Compilation of msi:ms7135 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ms7135&vendor=msi&num=2
Compilation of msi:ms7260 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ms7260&vendor=msi&num=2
Compilation of msi:ms9282 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ms9282&vendor=msi&num=2
Compilation of msi:ms9652_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ms9652_fam10&vendor=msi&num=2
Compilation of nvidia:l1_2pvv has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=l1_2pvv&vendor=nvidia&num=2
Compilation of roda:rk886ex has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=rk886ex&vendor=roda&num=2
Compilation of sunw:ultra40 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ultra40&vendor=sunw&num=2
Compilation of supermicro:h8dme has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=h8dme&vendor=supermicro&num=2
Compilation of supermicro:h8dmr has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=h8dmr&vendor=supermicro&num=2
Compilation of supermicro:h8dmr_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=h8dmr_fam10&vendor=supermicro&num=2
Compilation of supermicro:h8qme_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=h8qme_fam10&vendor=supermicro&num=2
Compilation of technexion:tim5690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=tim5690&vendor=technexion&num=2
Compilation of technexion:tim8690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=tim8690&vendor=technexion&num=2
Compilation of tyan:s2891 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=s2891&vendor=tyan&num=2
Compilation of tyan:s2892 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=s2892&vendor=tyan&num=2
Compilation of tyan:s2895 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=s2895&vendor=tyan&num=2
Compilation of tyan:s2912 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=s2912&vendor=tyan&num=2
Compilation of tyan:s2912_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=s2912_fam10&vendor=tyan&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From wt at penguintechs.org  Tue Oct  5 11:59:13 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Tue, 5 Oct 2010 02:59:13 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <4CAAE908.5090708@assembler.cz>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
	<4CA978ED.8000002@georgi-clan.de> <201010041950.25088.phorsyon@gmx.net>
	<20101004192314.7903.qmail@stuge.se>
	<AANLkTimROPLy7jwLcLhNDF0SPNL6R-hw2HS6YPi0zm_B@mail.gmail.com>
	<AANLkTikStpx9167n_eC4FyQovxRu-nZtYujEWW3Kxnh8@mail.gmail.com>
	<4CAAE908.5090708@assembler.cz>
Message-ID: <AANLkTikKA_veW1YHwB3WmctCFZwZrOGStm6Q5v5PtXTh@mail.gmail.com>

Does that software kit run in Linux? Is it relying on Linux's ACPI
implementation some how?

Thanks,
wt

On Tue, Oct 5, 2010 at 1:59 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
> Hi,
>
> Maybe good start to use some existing test suite
>
> http://www.h-online.com/open/news/item/Ubuntu-Kernel-Developer-releases-Firmware-Test-Suite-1053102.html
>
> http://smackerelofopinion.blogspot.com/2010/08/firmware-test-suite-biosacpi-health.html
>
> https://launchpad.net/~firmware-testing-team
> http://linuxfirmwarekit.org/
>
>
> This is based on http://linuxfirmwarekit.org/
>
> Thanks,
> Rudolf
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From wt at penguintechs.org  Tue Oct  5 12:00:36 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Tue,  5 Oct 2010 03:00:36 -0700
Subject: [coreboot] [PATCH] Reduce duplicate definition in CAR code.
Message-ID: <1286272836-1767-1-git-send-email-wt@penguintechs.org>

Here is a patch that I feel improves the readability of the CAR code a
little bit. What do you all think?

For the record, the intel and amd implementations have the same lists.
These could probably be pulled into a common macro used by all three
implementations.

Thanks,
wt
8<------------------
Macros for the register addresses for the MTRR MSRs are already defined
in include/cpu/x86/car.h. This patch uses those macros instead of
creating a second instance of that same data.

Signed-off-by: Warren Turkal <wt at penguintechs.org>
---
 src/cpu/via/car/cache_as_ram.inc |   35 ++++++++++++++++++++++++-----------
 1 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index d6df4a9..bbd4420 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -47,7 +47,7 @@ CacheAsRam:
 
 	/* Clear all MTRRs. */
 	xorl	%edx, %edx
-	movl	$fixed_mtrr_msr, %esi
+	movl	$all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
 	lodsl	(%esi), %eax
@@ -60,17 +60,30 @@ clear_fixed_var_mtrr:
 
 	jmp	clear_fixed_var_mtrr
 
-fixed_mtrr_msr:
-	.long	0x250, 0x258, 0x259
-	.long	0x268, 0x269, 0x26A
-	.long	0x26B, 0x26C, 0x26D
-	.long	0x26E, 0x26F
-
-var_mtrr_msr:
-	.long	0x200, 0x201, 0x202, 0x203
-	.long	0x204, 0x205, 0x206, 0x207
-	.long	0x208, 0x209, 0x20A, 0x20B
-	.long	0x20C, 0x20D, 0x20E, 0x20F
+all_mtrr_msrs:
+	/* fixed mtrr MSRs */
+	.long	MTRRfix64K_00000_MSR
+	.long	MTRRfix16K_80000_MSR
+	.long	MTRRfix16K_A0000_MSR
+	.long	MTRRfix4K_C0000_MSR
+	.long	MTRRfix4K_C8000_MSR
+	.long	MTRRfix4K_D0000_MSR
+	.long	MTRRfix4K_D8000_MSR
+	.long	MTRRfix4K_E0000_MSR
+	.long	MTRRfix4K_E8000_MSR
+	.long	MTRRfix4K_F0000_MSR
+	.long	MTRRfix4K_F8000_MSR
+
+	/* var mtrr MSRs */
+	.long	MTRRphysBase_MSR(0), MTRRphysBase_MSR(1)
+	.long	MTRRphysBase_MSR(2), MTRRphysBase_MSR(3)
+	.long	MTRRphysBase_MSR(4), MTRRphysBase_MSR(5)
+	.long	MTRRphysBase_MSR(6), MTRRphysBase_MSR(7)
+	.long	MTRRphysBase_MSR(8), MTRRphysBase_MSR(9)
+	.long	MTRRphysBase_MSR(10), MTRRphysBase_MSR(11)
+	.long	MTRRphysBase_MSR(12), MTRRphysBase_MSR(13)
+	.long	MTRRphysBase_MSR(14), MTRRphysBase_MSR(15)
+
 	.long	0x000 /* NULL, end of table */
 
 clear_fixed_var_mtrr_out:
-- 
1.7.1




From vidwer at gmail.com  Tue Oct  5 12:42:41 2010
From: vidwer at gmail.com (Idwer Vollering)
Date: Tue, 5 Oct 2010 12:42:41 +0200
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <4CA65C1B.3090908@coresystems.de>
References: <20101001212759.GV3256@greenwood> <4CA65C1B.3090908@coresystems.de>
Message-ID: <AANLkTikTexcKgfTGFmktf78Vd4dHm7NJmatJTUW--ec=@mail.gmail.com>

2010/10/2 Stefan Reinauer <stefan.reinauer at coresystems.de>

>  On 10/1/10 11:27 PM, Uwe Hermann wrote:
> > See patch.
> >
> > abuilt-tested.
> >
> >
> > Uwe.
> IMHO the patch makes it really hard to actually see what the code does.
> I think Idwer was recently running into a problem where the use of
> post_code would trash %eax were hard to comprehend. Now we seem have a
> lot more code that comes from somewhere else and touches registers
> without it being obvious to the reader of the code.
>

Uwe pointed me to this errata:
http://www.intel.com/Assets/PDF/specupdate/253176.pdf

Is processor init (with or without CAR but preferably with) still possible ?

The CPU that's used on the board is either a "N = Intel ? Pentium ? 4
processor" or a "R = Intel ? Pentium ? 4 processor on 90 nm process", cpuid
is 0xf29.


> Just my 2ct.
>
> Stefan
>

Idwer

>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From r.marek at assembler.cz  Tue Oct  5 12:47:26 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 05 Oct 2010 12:47:26 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTikKA_veW1YHwB3WmctCFZwZrOGStm6Q5v5PtXTh@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
	<4CA978ED.8000002@georgi-clan.de>
	<201010041950.25088.phorsyon@gmx.net>
	<20101004192314.7903.qmail@stuge.se>
	<AANLkTimROPLy7jwLcLhNDF0SPNL6R-hw2HS6YPi0zm_B@mail.gmail.com>
	<AANLkTikStpx9167n_eC4FyQovxRu-nZtYujEWW3Kxnh8@mail.gmail.com>
	<4CAAE908.5090708@assembler.cz>
	<AANLkTikKA_veW1YHwB3WmctCFZwZrOGStm6Q5v5PtXTh@mail.gmail.com>
Message-ID: <4CAB023E.4020502@assembler.cz>

Hi,

I used it like year ago. It is basically some linux program that is doing 
various checks using tools or kernel.

Someone needs to try out agin.

R.



From patrick at georgi-clan.de  Tue Oct  5 12:56:41 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 Oct 2010 12:56:41 +0200
Subject: [coreboot] [PATCH]Move USB debug port includes out of romstage
Message-ID: <4CAB0469.5080708@georgi-clan.de>

Hi,

attached patch does:
- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug
port enabled southbridges
- drop USB debug code includes from romstage.cs and use romstage-srcs in
the build system instead
- Disable USBDEBUG in abuild, I forgot this by accident before the
previous commit

It's abuild tested.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From r.marek at assembler.cz  Tue Oct  5 13:05:01 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 05 Oct 2010 13:05:01 +0200
Subject: [coreboot] [PATCH] Factor out common CAR asm snippets
In-Reply-To: <AANLkTimb-RNS_3mS+TV7GMq1iR0TRtDuWuGBTL6zBQct@mail.gmail.com>
References: <20101001212759.GV3256@greenwood>	<AANLkTikwws193rL5Dv3+xeWwh3v1_m_NjLWRrMDzcqZB@mail.gmail.com>
	<AANLkTimb-RNS_3mS+TV7GMq1iR0TRtDuWuGBTL6zBQct@mail.gmail.com>
Message-ID: <4CAB065D.7060207@assembler.cz>

> Alternatively, we could say that all "function" calls in pre-CAR state
> destroy all registers as a kind of pseudo-calling convention.

You cant you need to save BIST somewhere.

Please can we leave the only assembly code in coreboot alone? I think there are 
other places which needs to get improved.

Like for example review the SB700 code and check if everything is
ok. I started to fix the Windows7 boot and immediately lot of skeletons
fall off the closet (yes the little bug in SB700 mentioned in another thread is 
small example) I don't want to hijack this thread with details but a lot of time 
could be invested to do the code review with datasheet at hand to see
if the code is doing what is written in the comments and programming 
requirements. Which I think is more needed than fixing code which works.

Small examples:

/* Features Enable */
pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET interrupt. */

Oh yeah we enable SMI for USB and USB IR12 stuff strange huh?

->/* Don't rename APIC ID */
<------>/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
<------> * We need to check out why and change back. */
<------>clear_ioapic(ioapic_base);

it talks for itself...

<------>/* IRQ0From8254 */
<------>byte = pci_read_config8(dev, 0x41);
<------>byte &= ~(1 << 7);
<------>pci_write_config8(dev, 0x41, byte);

Actually anyone idea about this? Not found in datasheet.


---->/* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */
Oh yeah we should init i8259....

Please note that this is just little drop while I started to LOOK into this, 
probably it is much worse. Lets get to something more productive shall we?

Thanks,
Rudolf



From uwe at hermann-uwe.de  Tue Oct  5 14:21:57 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 5 Oct 2010 14:21:57 +0200
Subject: [coreboot] [PATCH]Move USB debug port includes out of romstage
In-Reply-To: <4CAB0469.5080708@georgi-clan.de>
References: <4CAB0469.5080708@georgi-clan.de>
Message-ID: <20101005122157.GA11394@greenwood>

On Tue, Oct 05, 2010 at 12:56:41PM +0200, Patrick Georgi wrote:
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Looks good.

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From mylesgw at gmail.com  Tue Oct  5 14:46:19 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 Oct 2010 06:46:19 -0600
Subject: [coreboot] [PATCH]Move USB debug port includes out of romstage
In-Reply-To: <4CAB0469.5080708@georgi-clan.de>
References: <4CAB0469.5080708@georgi-clan.de>
Message-ID: <AANLkTin+ENEVz6jd0Qh0SqHJkCZ7-i-dOia60ghp90ZM@mail.gmail.com>

On Tue, Oct 5, 2010 at 4:56 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Hi,
>
> attached patch does:
> - move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1
> - move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug
> port enabled southbridges
> - drop USB debug code includes from romstage.cs and use romstage-srcs in
> the build system instead
> - Disable USBDEBUG in abuild, I forgot this by accident before the
> previous commit

Since you're changing USBDEBUG code, it seems like a good idea to keep
it in abuild... at least until it has stabilized.

Thanks,
Myles



From svn at coreboot.org  Tue Oct  5 15:40:32 2010
From: svn at coreboot.org (repository service)
Date: Tue, 05 Oct 2010 15:40:32 +0200
Subject: [coreboot] [commit] r5911 - in trunk/src: include
	mainboard/amd/dbm690t mainboard/amd/mahogany
	mainboard/amd/mahogany_fam10 mainboard/amd/pistachio
	mainboard/amd/tilapia_fam10 mainboard/asrock/939a785gmh main...
Message-ID: <E1P37ku-00076s-JR@ra.coresystems.de>

Author: oxygene
Date: Tue Oct  5 15:40:31 2010
New Revision: 5911
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5911

Log:
- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges
- drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/include/ehci.h
   trunk/src/include/usbdebug.h
   trunk/src/mainboard/amd/dbm690t/romstage.c
   trunk/src/mainboard/amd/mahogany/romstage.c
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/pistachio/romstage.c
   trunk/src/mainboard/amd/tilapia_fam10/romstage.c
   trunk/src/mainboard/asrock/939a785gmh/romstage.c
   trunk/src/mainboard/asus/m4a785-m/romstage.c
   trunk/src/mainboard/getac/p470/romstage.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
   trunk/src/mainboard/gigabyte/m57sli/romstage.c
   trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
   trunk/src/mainboard/gigabyte/ma78gm/romstage.c
   trunk/src/mainboard/ibase/mb899/romstage.c
   trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
   trunk/src/mainboard/intel/d945gclf/romstage.c
   trunk/src/mainboard/jetway/pa78vm5/romstage.c
   trunk/src/mainboard/kontron/986lcd-m/romstage.c
   trunk/src/mainboard/kontron/kt690/romstage.c
   trunk/src/mainboard/msi/ms7260/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
   trunk/src/mainboard/roda/rk886ex/romstage.c
   trunk/src/mainboard/technexion/tim5690/romstage.c
   trunk/src/mainboard/technexion/tim8690/romstage.c
   trunk/src/mainboard/tyan/s2912/romstage.c
   trunk/src/mainboard/tyan/s2912_fam10/romstage.c
   trunk/src/pc80/usbdebug_serial.c
   trunk/src/southbridge/amd/sb600/Kconfig
   trunk/src/southbridge/amd/sb600/Makefile.inc
   trunk/src/southbridge/amd/sb600/sb600.h
   trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
   trunk/src/southbridge/amd/sb700/Kconfig
   trunk/src/southbridge/amd/sb700/Makefile.inc
   trunk/src/southbridge/amd/sb700/sb700.h
   trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
   trunk/src/southbridge/intel/i82801gx/Kconfig
   trunk/src/southbridge/intel/i82801gx/i82801gx.h
   trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
   trunk/src/southbridge/nvidia/ck804/Kconfig
   trunk/src/southbridge/nvidia/ck804/Makefile.inc
   trunk/src/southbridge/nvidia/ck804/ck804.h
   trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
   trunk/src/southbridge/nvidia/mcp55/Kconfig
   trunk/src/southbridge/nvidia/mcp55/Makefile.inc
   trunk/src/southbridge/nvidia/mcp55/mcp55.h
   trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
   trunk/src/southbridge/sis/sis966/Kconfig
   trunk/src/southbridge/sis/sis966/Makefile.inc
   trunk/src/southbridge/sis/sis966/sis966.h
   trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c

Modified: trunk/src/include/ehci.h
==============================================================================
--- trunk/src/include/ehci.h	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/include/ehci.h	Tue Oct  5 15:40:31 2010	(r5911)
@@ -23,6 +23,8 @@
 #ifndef EHCI_H
 #define EHCI_H
 
+#define EHCI_BAR_INDEX		0x10
+
 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 
 /* Section 2.2 Host Controller Capability Registers */

Modified: trunk/src/include/usbdebug.h
==============================================================================
--- trunk/src/include/usbdebug.h	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/include/usbdebug.h	Tue Oct  5 15:40:31 2010	(r5911)
@@ -41,6 +41,7 @@
 void set_ehci_debug(unsigned ehci_deug);
 unsigned get_ehci_debug(void);
 void set_debug_port(unsigned port);
+void early_usbdebug_init(void);
 void usbdebug_ram_tx_byte(unsigned char data);
 void usbdebug_tx_byte(unsigned char data);
 

Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/amd/dbm690t/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -51,10 +51,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/amd/mahogany/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -50,11 +50,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -59,11 +59,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

Modified: trunk/src/mainboard/amd/pistachio/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/amd/pistachio/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -45,11 +45,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -59,11 +59,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -51,11 +51,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -59,11 +59,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

Modified: trunk/src/mainboard/getac/p470/romstage.c
==============================================================================
--- trunk/src/mainboard/getac/p470/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/getac/p470/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -27,6 +27,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
+#include <usbdebug.h>
 
 #include <pc80/mc146818rtc.h>
 

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -51,13 +51,11 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/sis/sis966/sis966_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
+#include "southbridge/sis/sis966/sis966.h"
 #include "southbridge/sis/sis966/sis966_early_smbus.c"
 #include "southbridge/sis/sis966/sis966_enable_rom.c"
 #include "northbridge/amd/amdk8/raminit.h"

Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -49,10 +49,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -55,11 +55,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -59,11 +59,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

Modified: trunk/src/mainboard/ibase/mb899/romstage.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/ibase/mb899/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -33,6 +33,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
+#include <usbdebug.h>
 #include <cpu/x86/bist.h>
 
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -62,11 +62,7 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/fintek/f71859/f71859_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

Modified: trunk/src/mainboard/intel/d945gclf/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/intel/d945gclf/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -33,6 +33,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
+#include <usbdebug.h>
 #include <cpu/x86/bist.h>
 
 #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"

Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -66,10 +66,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
 #endif
 
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>

Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/kontron/986lcd-m/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -27,6 +27,7 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
+#include <usbdebug.h>
 
 #include "superio/winbond/w83627thg/w83627thg.h"
 

Modified: trunk/src/mainboard/kontron/kt690/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/kontron/kt690/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -53,10 +53,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
 
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/msi/ms7260/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -52,10 +52,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -42,10 +42,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 #include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>

Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -49,10 +49,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 #include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>

Modified: trunk/src/mainboard/roda/rk886ex/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/roda/rk886ex/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -33,6 +33,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
+#include <usbdebug.h>
 #include <cpu/x86/bist.h>
 
 #include "northbridge/intel/i945/i945.h"

Modified: trunk/src/mainboard/technexion/tim5690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/technexion/tim5690/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -51,11 +51,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

Modified: trunk/src/mainboard/technexion/tim8690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/technexion/tim8690/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -51,11 +51,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/tyan/s2912/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -49,11 +49,8 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
 #include <lib.h>
+#include <usbdebug.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -42,10 +42,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#if CONFIG_USBDEBUG
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
 #include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>

Modified: trunk/src/pc80/usbdebug_serial.c
==============================================================================
--- trunk/src/pc80/usbdebug_serial.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/pc80/usbdebug_serial.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -19,13 +19,15 @@
  */
 
 #include "../lib/usbdebug.c"
+#include <arch/io.h>
+#include <ehci.h>
 
-static void early_usbdebug_init(void)
+void early_usbdebug_init(void)
 {
 	struct ehci_debug_info *dbg_info = (struct ehci_debug_info *)
 	    (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info));
 
-	usbdebug_init(EHCI_BAR, EHCI_DEBUG_OFFSET, dbg_info);
+	usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
 }
 
 void usbdebug_tx_byte(unsigned char data)

Modified: trunk/src/southbridge/amd/sb600/Kconfig
==============================================================================
--- trunk/src/southbridge/amd/sb600/Kconfig	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/amd/sb600/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
@@ -22,3 +22,11 @@
 	select IOAPIC
 	select HAVE_USBDEBUG
 
+config EHCI_BAR
+	hex
+	default 0xfef00000 if SOUTHBRIDGE_AMD_SB600
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0xe0 if SOUTHBRIDGE_AMD_SB600
+

Modified: trunk/src/southbridge/amd/sb600/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/sb600/Makefile.inc	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/amd/sb600/Makefile.inc	Tue Oct  5 15:40:31 2010	(r5911)
@@ -8,3 +8,4 @@
 driver-y += sb600_ac97.c
 driver-y += sb600_pci.c
 ramstage-y += sb600_reset.c
+romstage-y += sb600_enable_usbdebug.c

Modified: trunk/src/southbridge/amd/sb600/sb600.h
==============================================================================
--- trunk/src/southbridge/amd/sb600/sb600.h	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/amd/sb600/sb600.h	Tue Oct  5 15:40:31 2010	(r5911)
@@ -40,4 +40,5 @@
 void sb600_lpc_port80(void);
 void sb600_pci_port80(void);
 
+void sb600_enable_usbdebug(unsigned int port);
 #endif /* SB600_H */

Modified: trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
==============================================================================
--- trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -18,12 +18,11 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
-
-#define EHCI_BAR		0xFEF00000	/* EHCI BAR address */
-#define EHCI_BAR_INDEX		0x10		/* TODO: DBUG_PRT[31:29] */
-#define EHCI_DEBUG_OFFSET	0xE0		/* Hardcoded to 0xE0 */
+#include "sb600.h"
 
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
@@ -31,7 +30,7 @@
 	/* TODO: Allow changing the physical USB port used as Debug Port. */
 }
 
-static void sb600_enable_usbdebug(unsigned int port)
+void sb600_enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
 
@@ -39,7 +38,7 @@
 	set_debug_port(port);
 
 	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
 	/* Enable access to the EHCI memory space registers. */
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

Modified: trunk/src/southbridge/amd/sb700/Kconfig
==============================================================================
--- trunk/src/southbridge/amd/sb700/Kconfig	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/amd/sb700/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
@@ -27,3 +27,11 @@
 	default n
 	depends on SOUTHBRIDGE_AMD_SB700
 
+config EHCI_BAR
+	hex
+	default 0xfef00000 if SOUTHBRIDGE_AMD_SB700
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0xe0 if SOUTHBRIDGE_AMD_SB700
+

Modified: trunk/src/southbridge/amd/sb700/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/sb700/Makefile.inc	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/amd/sb700/Makefile.inc	Tue Oct  5 15:40:31 2010	(r5911)
@@ -7,3 +7,4 @@
 driver-y += sb700_hda.c
 driver-y += sb700_pci.c
 ramstage-y += sb700_reset.c
+romstage-y += sb700_enable_usbdebug.c

Modified: trunk/src/southbridge/amd/sb700/sb700.h
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700.h	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/amd/sb700/sb700.h	Tue Oct  5 15:40:31 2010	(r5911)
@@ -59,4 +59,5 @@
 
 #endif
 
+void sb700_enable_usbdebug(unsigned int port);
 #endif /* SB700_H */

Modified: trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -19,14 +19,13 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
+#include "sb700.h"
 
-#define EHCI_BAR		0xFEF00000	/* EHCI BAR address */
-#define EHCI_BAR_INDEX		0x10		/* TODO: DBUG_PRT[31:29] */
-#define EHCI_DEBUG_OFFSET	0xE0		/* Hardcoded to 0xE0 */
-
-#define EHCI_EOR		(EHCI_BAR + 0x20)
+#define EHCI_EOR		(CONFIG_EHCI_BAR + 0x20)
 #define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
 
 void set_debug_port(unsigned int port)
@@ -46,12 +45,12 @@
  * This code currently only supports the first one, i.e., USB Debug devices
  * attached to physical USB ports belonging to the first EHCI device.
  */
-static void sb700_enable_usbdebug(unsigned int port)
+void sb700_enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
 
 	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
 	/* Enable access to the EHCI memory space registers. */
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

Modified: trunk/src/southbridge/intel/i82801gx/Kconfig
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/Kconfig	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/intel/i82801gx/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
@@ -24,3 +24,11 @@
 	select HAVE_USBDEBUG
 	select USE_WATCHDOG_ON_BOOT
 
+config EHCI_BAR
+	hex
+	default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX
+

Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx.h	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/intel/i82801gx/i82801gx.h	Tue Oct  5 15:40:31 2010	(r5911)
@@ -39,10 +39,13 @@
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
+#if !defined(ASSEMBLY)
 #if !defined(__PRE_RAM__)
 #include "chip.h"
 extern void i82801gx_enable(device_t dev);
 #endif
+void i82801gx_enable_usbdebug(unsigned int port);
+#endif
 
 #define MAINBOARD_POWER_OFF	0
 #define MAINBOARD_POWER_ON	1

Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -18,12 +18,12 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
-
-#define EHCI_BAR		0xFEF00000	/* EHCI BAR address */
-#define EHCI_BAR_INDEX		0x10		/* Hardwired 0x10 (>= ICH4). */
-#define EHCI_DEBUG_OFFSET	0xA0		/* Hardwired 0xa0 (>= ICH5). */
+#include "i82801gx.h"
 
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
@@ -31,20 +31,20 @@
 	/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
 }
 
-static void i82801gx_enable_usbdebug(unsigned int port)
+void i82801gx_enable_usbdebug(unsigned int port)
 {
 	u32 dbgctl;
 	device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
 
 	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
 	/* Enable access to the EHCI memory space registers. */
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 
 	/* Force ownership of the Debug Port to the EHCI controller. */
 	printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
-	dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET);
+	dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
 	dbgctl |= (1 << 30);
-	write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl);
+	write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
 }

Modified: trunk/src/southbridge/nvidia/ck804/Kconfig
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/Kconfig	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/nvidia/ck804/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
@@ -8,3 +8,11 @@
 	hex
 	default 0x80 if SOUTHBRIDGE_NVIDIA_CK804
 
+config EHCI_BAR
+	hex
+	default 0xfef00000 if SOUTHBRIDGE_NVIDIA_CK804
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0x98 if SOUTHBRIDGE_NVIDIA_CK804
+

Modified: trunk/src/southbridge/nvidia/ck804/Makefile.inc
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/Makefile.inc	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/nvidia/ck804/Makefile.inc	Tue Oct  5 15:40:31 2010	(r5911)
@@ -15,5 +15,8 @@
 
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c
 
+romstage-y += ck804_enable_usbdebug.c
+
 chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds
+

Modified: trunk/src/southbridge/nvidia/ck804/ck804.h
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804.h	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/nvidia/ck804/ck804.h	Tue Oct  5 15:40:31 2010	(r5911)
@@ -4,5 +4,6 @@
 #include "chip.h"
 
 void ck804_enable(device_t dev);
+void ck804_enable_usbdebug(unsigned int port);
 
 #endif

Modified: trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -22,8 +22,11 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
+#include "ck804.h"
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -31,10 +34,6 @@
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#define EHCI_BAR		0xFEF00000	/* EHCI BAR address */
-#define EHCI_BAR_INDEX		0x10
-#define EHCI_DEBUG_OFFSET	0x98
-
 void set_debug_port(unsigned int port)
 {
 	u32 dword;
@@ -47,7 +46,7 @@
 	pci_write_config32(dev, 0x74, dword);
 }
 
-static void ck804_enable_usbdebug(unsigned int port)
+void ck804_enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
 
@@ -55,7 +54,7 @@
 	set_debug_port(port);
 
 	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
 	/* Enable access to the EHCI memory space registers. */
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/Kconfig	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/nvidia/mcp55/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
@@ -6,3 +6,12 @@
 config ID_SECTION_OFFSET
 	hex
 	default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55
+
+config EHCI_BAR
+	hex
+	default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55
+

Modified: trunk/src/southbridge/nvidia/mcp55/Makefile.inc
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/Makefile.inc	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/nvidia/mcp55/Makefile.inc	Tue Oct  5 15:40:31 2010	(r5911)
@@ -15,5 +15,7 @@
 
 ramstage-y += mcp55_reset.c
 
+romstage-y += mcp55_enable_usbdebug.c
+
 chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds

Modified: trunk/src/southbridge/nvidia/mcp55/mcp55.h
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55.h	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55.h	Tue Oct  5 15:40:31 2010	(r5911)
@@ -29,4 +29,5 @@
 #else
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
 #endif
+void mcp55_enable_usbdebug(unsigned int port);
 #endif /* MCP55_H */

Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -22,8 +22,11 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
+#include "mcp55.h"
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -31,10 +34,6 @@
 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#define EHCI_BAR		0xFEF00000	/* EHCI BAR address */
-#define EHCI_BAR_INDEX		0x10
-#define EHCI_DEBUG_OFFSET	0x98
-
 void set_debug_port(unsigned int port)
 {
 	u32 dword;
@@ -47,7 +46,7 @@
 	pci_write_config32(dev, 0x74, dword);
 }
 
-static void mcp55_enable_usbdebug(unsigned int port)
+void mcp55_enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
 
@@ -55,7 +54,7 @@
 	set_debug_port(port);
 
 	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
 	/* Enable access to the EHCI memory space registers. */
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

Modified: trunk/src/southbridge/sis/sis966/Kconfig
==============================================================================
--- trunk/src/southbridge/sis/sis966/Kconfig	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/sis/sis966/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
@@ -6,3 +6,11 @@
 config ID_SECTION_OFFSET
 	hex
 	default 0x80 if SOUTHBRIDGE_SIS_SIS966
+
+config EHCI_BAR
+	hex
+	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0x98 if SOUTHBRIDGE_SIS_SIS966

Modified: trunk/src/southbridge/sis/sis966/Makefile.inc
==============================================================================
--- trunk/src/southbridge/sis/sis966/Makefile.inc	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/sis/sis966/Makefile.inc	Tue Oct  5 15:40:31 2010	(r5911)
@@ -9,6 +9,7 @@
 driver-y += sis966_pcie.c
 driver-y += sis966_aza.c
 ramstage-y += sis966_reset.c
+romstage-y += sis966_enable_usbdebug.c
 
 chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds

Modified: trunk/src/southbridge/sis/sis966/sis966.h
==============================================================================
--- trunk/src/southbridge/sis/sis966/sis966.h	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/sis/sis966/sis966.h	Tue Oct  5 15:40:31 2010	(r5911)
@@ -32,5 +32,6 @@
 #include "chip.h"
 
 void sis966_enable(device_t dev);
+void sis966_enable_usbdebug(unsigned int port);
 
 #endif /* SIS966_H */

Modified: trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c
==============================================================================
--- trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c	Tue Oct  5 11:07:10 2010	(r5910)
+++ trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c	Tue Oct  5 15:40:31 2010	(r5911)
@@ -24,8 +24,11 @@
 /* TODO: Check whether this actually works (might be copy-paste leftover). */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
+#include "sis966.h"
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
 #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -33,10 +36,6 @@
 #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
-#define EHCI_BAR		0xFEF00000	/* EHCI BAR address */
-#define EHCI_BAR_INDEX		0x10
-#define EHCI_DEBUG_OFFSET	0x98
-
 void set_debug_port(unsigned int port)
 {
 	u32 dword;
@@ -49,7 +48,7 @@
 	pci_write_config32(dev, 0x74, dword);
 }
 
-static void sis966_enable_usbdebug(unsigned int port)
+void sis966_enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
 
@@ -57,7 +56,7 @@
 	set_debug_port(port);
 
 	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
 
 	/* Enable access to the EHCI memory space registers. */
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);



From patrick at georgi-clan.de  Tue Oct  5 15:40:46 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 Oct 2010 15:40:46 +0200
Subject: [coreboot] [PATCH]Move USB debug port includes out of romstage
In-Reply-To: <AANLkTin+ENEVz6jd0Qh0SqHJkCZ7-i-dOia60ghp90ZM@mail.gmail.com>
References: <4CAB0469.5080708@georgi-clan.de>
	<AANLkTin+ENEVz6jd0Qh0SqHJkCZ7-i-dOia60ghp90ZM@mail.gmail.com>
Message-ID: <4CAB2ADE.70105@georgi-clan.de>

Am 05.10.2010 14:46, schrieb Myles Watson:
> Since you're changing USBDEBUG code, it seems like a good idea to keep
> it in abuild... at least until it has stabilized.
Kept it in.


Patrick



From svn at coreboot.org  Tue Oct  5 16:06:13 2010
From: svn at coreboot.org (repository service)
Date: Tue, 05 Oct 2010 16:06:13 +0200
Subject: [coreboot] build service results for r5911
Message-ID: <E1P389l-0007ow-2l@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5911 to
the coreboot repository. This caused the following 
changes:

Change Log:
- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges
- drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Build Log:
Compilation of amd:dbm690t has been fixed
Compilation of amd:mahogany has been fixed
Compilation of amd:mahogany_fam10 has been fixed
Compilation of amd:pistachio has been fixed
Compilation of amd:tilapia_fam10 has been fixed
Compilation of asrock:939a785gmh has been fixed
Compilation of asus:a8n_e has been fixed
Compilation of asus:m4a785-m has been fixed
Compilation of getac:p470 has been fixed
Compilation of gigabyte:ga_2761gxdk has been fixed
Compilation of gigabyte:m57sli has been fixed
Compilation of gigabyte:ma785gmt has been fixed
Compilation of gigabyte:ma78gm has been fixed
Compilation of ibase:mb899 has been fixed
Compilation of iei:kino-780am2-fam10 has been fixed
Compilation of intel:d945gclf has been fixed
Compilation of jetway:pa78vm5 has been fixed
Compilation of kontron:986lcd-m has been fixed
Compilation of kontron:kt690 has been fixed
Compilation of msi:ms7135 has been fixed
Compilation of msi:ms7260 has been fixed
Compilation of msi:ms9282 has been fixed
Compilation of msi:ms9652_fam10 has been fixed
Compilation of nvidia:l1_2pvv has been fixed
Compilation of roda:rk886ex has been fixed
Compilation of sunw:ultra40 has been fixed
Compilation of supermicro:h8dme has been fixed
Compilation of supermicro:h8dmr has been fixed
Compilation of supermicro:h8dmr_fam10 has been fixed
Compilation of supermicro:h8qme_fam10 has been fixed
Compilation of technexion:tim5690 has been fixed
Compilation of technexion:tim8690 has been fixed
Compilation of tyan:s2891 has been fixed
Compilation of tyan:s2892 has been fixed
Compilation of tyan:s2895 has been fixed
Compilation of tyan:s2912 has been fixed
Compilation of tyan:s2912_fam10 has been fixed


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From patrick at georgi-clan.de  Tue Oct  5 16:41:57 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 Oct 2010 16:41:57 +0200
Subject: [coreboot] [PATCH]De-define CK804 flags
Message-ID: <4CAB3935.9090203@georgi-clan.de>

Hi,

attached patch moves a couple more config flags out of romstage:
CK804_USE_NIC, CK804_USE_ACI.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From JRottmann at LiPPERTEmbedded.de  Tue Oct  5 17:25:20 2010
From: JRottmann at LiPPERTEmbedded.de (Jens Rottmann)
Date: Tue, 05 Oct 2010 17:25:20 +0200
Subject: [coreboot] [PATCH] Enable or disable the power button in Kconfig
In-Reply-To: <20101001194610.8333.qmail@stuge.se>
References: <20101001194610.8333.qmail@stuge.se>
Message-ID: <4CAB4360.7020805@LiPPERTEmbedded.de>

Hi Peter,

sorry for the delay, was on vacation.

Nice new feature!  :)

> please confirm if my understanding of the old vs. new
> hurricane-lx board version vs. power button behavior is correct.

Yes, your patch correctly preserves current behavior.

However, I'd like to make use of your nice new feature and give the user
the option to enable the button after they have removed the jumper -
patch attached.

Thanks a lot!!
Jens
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From mylesgw at gmail.com  Tue Oct  5 17:32:50 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 Oct 2010 09:32:50 -0600
Subject: [coreboot] [PATCH]De-define CK804 flags
In-Reply-To: <4CAB3935.9090203@georgi-clan.de>
References: <4CAB3935.9090203@georgi-clan.de>
Message-ID: <AANLkTim4QOrQXGT5OJZbVz878n1O5qvdONtyDTuJ3vxP@mail.gmail.com>

On Tue, Oct 5, 2010 at 8:41 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Hi,
>
> attached patch moves a couple more config flags out of romstage:
> CK804_USE_NIC, CK804_USE_ACI.
>
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Myles Watson <mylesgw at gmail.com>

I'd like to keep CK804 & MCP55 as similar as possible.  Patches attached.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From rminnich at gmail.com  Tue Oct  5 17:36:24 2010
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 Oct 2010 08:36:24 -0700
Subject: [coreboot] [PATCH] Reduce duplicate definition in CAR code.
In-Reply-To: <1286272836-1767-1-git-send-email-wt@penguintechs.org>
References: <1286272836-1767-1-git-send-email-wt@penguintechs.org>
Message-ID: <AANLkTin_0uQdpXsrEiY-mxi3r1Vj6K+_jBNv5Uaf37zJ@mail.gmail.com>

On Tue, Oct 5, 2010 at 3:00 AM, Warren Turkal <wt at penguintechs.org> wrote:
> Here is a patch that I feel improves the readability of the CAR code a
> little bit. What do you all think?


I think it's quite nice, as you replace mysterious numbers with a
meaningful name.

ron



From peter at stuge.se  Tue Oct  5 17:57:13 2010
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 Oct 2010 17:57:13 +0200
Subject: [coreboot] [PATCH]Move USB debug port includes out of romstage
In-Reply-To: <4CAB0469.5080708@georgi-clan.de>
References: <4CAB0469.5080708@georgi-clan.de>
Message-ID: <20101005155713.26249.qmail@stuge.se>

Patrick Georgi wrote:
> - move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB
> debug port enabled southbridges

Only comment is that I really like the

if SOUTH

config FOO
  default xy

endif

pattern in Kconfig files, so that the SOUTH isn't needed in each
place.


//Peter



From peter at stuge.se  Tue Oct  5 18:04:59 2010
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 Oct 2010 18:04:59 +0200
Subject: [coreboot] [PATCH]De-define CK804 flags
In-Reply-To: <AANLkTim4QOrQXGT5OJZbVz878n1O5qvdONtyDTuJ3vxP@mail.gmail.com>
References: <4CAB3935.9090203@georgi-clan.de>
	<AANLkTim4QOrQXGT5OJZbVz878n1O5qvdONtyDTuJ3vxP@mail.gmail.com>
Message-ID: <20101005160459.27107.qmail@stuge.se>

Myles Watson wrote:
> > attached patch moves a couple more config flags out of romstage:
> > CK804_USE_NIC, CK804_USE_ACI.
> >
> > Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
> Acked-by: Myles Watson <mylesgw at gmail.com>

Acked-by: Peter Stuge <peter at stuge.se>


> I'd like to keep CK804 & MCP55 as similar as possible.  Patches attached.
> 
> Signed-off-by: Myles Watson <mylesgw at gmail.com>

Acked-by: Peter Stuge <peter at stuge.se>



From peter at stuge.se  Tue Oct  5 18:26:34 2010
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 Oct 2010 18:26:34 +0200
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTikKA_veW1YHwB3WmctCFZwZrOGStm6Q5v5PtXTh@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
	<4CA978ED.8000002@georgi-clan.de>
	<201010041950.25088.phorsyon@gmx.net>
	<20101004192314.7903.qmail@stuge.se>
	<AANLkTimROPLy7jwLcLhNDF0SPNL6R-hw2HS6YPi0zm_B@mail.gmail.com>
	<AANLkTikStpx9167n_eC4FyQovxRu-nZtYujEWW3Kxnh8@mail.gmail.com>
	<4CAAE908.5090708@assembler.cz>
	<AANLkTikKA_veW1YHwB3WmctCFZwZrOGStm6Q5v5PtXTh@mail.gmail.com>
Message-ID: <20101005162634.30508.qmail@stuge.se>

Warren Turkal wrote:
> Does that software kit run in Linux?

Yes.


> Is it relying on Linux's ACPI implementation some how?

No.


//Peter



From rminnich at gmail.com  Tue Oct  5 18:34:07 2010
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 Oct 2010 09:34:07 -0700
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <20101005162634.30508.qmail@stuge.se>
References: <4CA7B5C3.9000002@gmx.net>
	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>
	<4CA978ED.8000002@georgi-clan.de>
	<201010041950.25088.phorsyon@gmx.net>
	<20101004192314.7903.qmail@stuge.se>
	<AANLkTimROPLy7jwLcLhNDF0SPNL6R-hw2HS6YPi0zm_B@mail.gmail.com>
	<AANLkTikStpx9167n_eC4FyQovxRu-nZtYujEWW3Kxnh8@mail.gmail.com>
	<4CAAE908.5090708@assembler.cz>
	<AANLkTikKA_veW1YHwB3WmctCFZwZrOGStm6Q5v5PtXTh@mail.gmail.com>
	<20101005162634.30508.qmail@stuge.se>
Message-ID: <AANLkTik5JdmeNdBWigQiORPVgcEdg4oS+kCX5KFxU4JB@mail.gmail.com>

Making your own certification is hard. Using someone else's test is
easier. Maybe we should invert the problem. Have a page which shows,
for each board, what suite of tests it passes under coreboot.

- boots vista
- boots windows 7
- boots linux
- runs intels firmware validation

and so on.

ron



From patrick at georgi-clan.de  Tue Oct  5 19:16:38 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 Oct 2010 19:16:38 +0200
Subject: [coreboot] [PATCH]De-define CK804 flags
In-Reply-To: <AANLkTim4QOrQXGT5OJZbVz878n1O5qvdONtyDTuJ3vxP@mail.gmail.com>
References: <4CAB3935.9090203@georgi-clan.de>
	<AANLkTim4QOrQXGT5OJZbVz878n1O5qvdONtyDTuJ3vxP@mail.gmail.com>
Message-ID: <4CAB5D76.10608@georgi-clan.de>

Am 05.10.2010 17:32, schrieb Myles Watson:
> On Tue, Oct 5, 2010 at 8:41 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
>> Hi,
>>
>> attached patch moves a couple more config flags out of romstage:
>> CK804_USE_NIC, CK804_USE_ACI.
>>
>> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
> Acked-by: Myles Watson <mylesgw at gmail.com>
> 
> I'd like to keep CK804 & MCP55 as similar as possible.  Patches attached.
One issue: you didn't handle all MCP55_NUMs, there are some #defines
left. I didn't work on the _NUM stuff at all as I don't know its meaning.


Patrick



From svn at coreboot.org  Tue Oct  5 19:59:12 2010
From: svn at coreboot.org (repository service)
Date: Tue, 05 Oct 2010 19:59:12 +0200
Subject: [coreboot] [commit] r5912 - in trunk/src: mainboard/asus/a8n_e
	mainboard/gigabyte/m57sli mainboard/msi/ms7135
	mainboard/msi/ms7260 mainboard/msi/ms9282
	mainboard/msi/ms9652_fam10 mainboard/nvidia/l1_2pvv main...
Message-ID: <E1P3BnE-0000Qq-Q3@ra.coresystems.de>

Author: myles
Date: Tue Oct  5 19:59:12 2010
New Revision: 5912
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5912

Log:
attached patch moves a couple more config flags out of romstage:
CK804_USE_NIC, CK804_USE_ACI, CK804_NUM.
MCP55_USE_NIC, MCP55_USE_ACI, MCP55_NUM.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Pter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asus/a8n_e/romstage.c
   trunk/src/mainboard/gigabyte/m57sli/Kconfig
   trunk/src/mainboard/gigabyte/m57sli/romstage.c
   trunk/src/mainboard/msi/ms7135/Kconfig
   trunk/src/mainboard/msi/ms7135/romstage.c
   trunk/src/mainboard/msi/ms7260/Kconfig
   trunk/src/mainboard/msi/ms7260/romstage.c
   trunk/src/mainboard/msi/ms9282/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/Kconfig
   trunk/src/mainboard/msi/ms9652_fam10/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
   trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
   trunk/src/mainboard/sunw/ultra40/Kconfig
   trunk/src/mainboard/sunw/ultra40/romstage.c
   trunk/src/mainboard/supermicro/h8dme/Kconfig
   trunk/src/mainboard/supermicro/h8dme/romstage.c
   trunk/src/mainboard/supermicro/h8dmr/Kconfig
   trunk/src/mainboard/supermicro/h8dmr/romstage.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
   trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
   trunk/src/mainboard/tyan/s2891/romstage.c
   trunk/src/mainboard/tyan/s2895/romstage.c
   trunk/src/mainboard/tyan/s2912/Kconfig
   trunk/src/mainboard/tyan/s2912/romstage.c
   trunk/src/mainboard/tyan/s2912_fam10/Kconfig
   trunk/src/mainboard/tyan/s2912_fam10/romstage.c
   trunk/src/southbridge/nvidia/ck804/Kconfig
   trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
   trunk/src/southbridge/nvidia/mcp55/Kconfig
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c

Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -42,10 +42,6 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-/* Used by ck894_early_setup(). */
-#define CK804_NUM 1
-
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/gigabyte/m57sli/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -8,6 +8,8 @@
 	select NORTHBRIDGE_AMD_AMDK8
 	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
 	select SOUTHBRIDGE_NVIDIA_MCP55
+	select MCP55_USE_NIC
+	select MCP55_USE_AZA
 	select SUPERIO_ITE_IT8716F
 	select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
 	select HAVE_BUS_CONFIG

Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -90,10 +90,6 @@
 	return smbus_read_byte(device, address);
 }
 
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
 #define MCP55_PCI_E_X_0 0
 
 #define MCP55_MB_SETUP \

Modified: trunk/src/mainboard/msi/ms7135/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7135/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/msi/ms7135/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -15,6 +15,8 @@
 	select HAVE_MP_TABLE
 	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
+	select CK804_USE_NIC
+	select CK804_USE_ACI
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/msi/ms7135/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/msi/ms7135/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -43,10 +43,6 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-/* Used by ck804_early_setup(). */
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/msi/ms7260/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7260/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/msi/ms7260/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -8,6 +8,8 @@
 	select NORTHBRIDGE_AMD_AMDK8
 	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
 	select SOUTHBRIDGE_NVIDIA_MCP55
+	select MCP55_USE_NIC
+	select MCP55_USE_AZA
 	select SUPERIO_WINBOND_W83627EHG
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE

Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/msi/ms7260/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -92,9 +92,6 @@
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
 #define MCP55_PCI_E_X_0 0
 
 #define MCP55_MB_SETUP \

Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/msi/ms9282/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -105,7 +105,6 @@
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 //set GPIO to input mode
 #define MCP55_MB_SETUP \

Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -8,6 +8,8 @@
 	select DIMM_REGISTERED
 	select NORTHBRIDGE_AMD_AMDFAM10
 	select SOUTHBRIDGE_NVIDIA_MCP55
+	select MCP55_USE_NIC
+	select MCP55_USE_AZA
 	select SUPERIO_WINBOND_W83627EHG
 	select HAVE_BUS_CONFIG
 	select HAVE_PIRQ_TABLE

Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -89,10 +89,6 @@
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
 #define MCP55_PCI_E_X_0 1
 
 #define MCP55_MB_SETUP \

Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -9,6 +9,8 @@
 	select NORTHBRIDGE_AMD_AMDK8
 	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
 	select SOUTHBRIDGE_NVIDIA_MCP55
+	select MCP55_USE_NIC
+	select MCP55_USE_AZA
 	select SUPERIO_WINBOND_W83627EHG
 	select HAVE_OPTION_TABLE
 	select HAVE_BUS_CONFIG
@@ -44,6 +46,10 @@
 	int
 	default 1
 
+config MCP55_NUM
+	int
+	default 2
+
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 2

Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -100,10 +100,6 @@
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 2
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
 #define MCP55_PCI_E_X_0 2
 #define MCP55_PCI_E_X_1 4
 

Modified: trunk/src/mainboard/sunw/ultra40/Kconfig
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/sunw/ultra40/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -14,6 +14,8 @@
 	select HAVE_MP_TABLE
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_1024
+	select CK804_USE_NIC
+	select CK804_USE_ACI
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/sunw/ultra40/romstage.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/sunw/ultra40/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -78,9 +78,6 @@
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 
 //set GPIO to input mode

Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/supermicro/h8dme/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -9,6 +9,8 @@
 	select NORTHBRIDGE_AMD_AMDK8
 	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
 	select SOUTHBRIDGE_NVIDIA_MCP55
+	select MCP55_USE_NIC
+	select MCP55_USE_AZA
 	select SUPERIO_WINBOND_W83627HF
 	select HAVE_OPTION_TABLE
 	select HAVE_BUS_CONFIG

Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -155,10 +155,6 @@
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
 #define MCP55_PCI_E_X_0 4
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"

Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/supermicro/h8dmr/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -9,6 +9,8 @@
 	select NORTHBRIDGE_AMD_AMDK8
 	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
 	select SOUTHBRIDGE_NVIDIA_MCP55
+	select MCP55_USE_NIC
+	select MCP55_USE_AZA
 	select SUPERIO_WINBOND_W83627HF
 	select HAVE_OPTION_TABLE
 	select HAVE_BUS_CONFIG

Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -100,10 +100,6 @@
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
 #define MCP55_PCI_E_X_0 4
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -8,6 +8,8 @@
 	select DIMM_REGISTERED
 	select NORTHBRIDGE_AMD_AMDFAM10
 	select SOUTHBRIDGE_NVIDIA_MCP55
+	select MCP55_USE_NIC
+	select MCP55_USE_AZA
 	select SUPERIO_WINBOND_W83627HF
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -89,10 +89,6 @@
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
 #define MCP55_PCI_E_X_0 4
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -92,10 +92,6 @@
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 0
-#define MCP55_USE_AZA 0
-
 #define MCP55_PCI_E_X_0 4
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"

Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/tyan/s2891/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -62,12 +62,9 @@
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define CK804_NUM 1
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
 
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/tyan/s2895/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -72,9 +72,6 @@
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 
 //set GPIO to input mode

Modified: trunk/src/mainboard/tyan/s2912/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/tyan/s2912/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -9,6 +9,7 @@
 	select NORTHBRIDGE_AMD_AMDK8
 	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
 	select SOUTHBRIDGE_NVIDIA_MCP55
+	select MCP55_USE_NIC
 	select SUPERIO_WINBOND_W83627HF
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE

Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/tyan/s2912/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -100,9 +100,6 @@
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-
 #define MCP55_PCI_E_X_0 1
 
 #define MCP55_MB_SETUP \

Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -8,6 +8,7 @@
 	select DIMM_REGISTERED
 	select NORTHBRIDGE_AMD_AMDFAM10
 	select SOUTHBRIDGE_NVIDIA_MCP55
+	select MCP55_USE_NIC
 	select SUPERIO_WINBOND_W83627HF
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE

Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -89,9 +89,6 @@
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-
 #define MCP55_PCI_E_X_0 1
 
 #define MCP55_MB_SETUP \

Modified: trunk/src/southbridge/nvidia/ck804/Kconfig
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/southbridge/nvidia/ck804/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -16,3 +16,14 @@
 	hex
 	default 0x98 if SOUTHBRIDGE_NVIDIA_CK804
 
+config CK804_USE_NIC
+	bool
+	default n if SOUTHBRIDGE_NVIDIA_CK804
+
+config CK804_USE_ACI
+	bool
+	default n if SOUTHBRIDGE_NVIDIA_CK804
+
+config CK804_NUM
+	int
+	default 1 if SOUTHBRIDGE_NVIDIA_CK804

Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -52,7 +52,7 @@
 #define CK804_PCI_E_X 4
 #endif
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
 #define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
 #ifndef CK804B_BUSN
@@ -63,14 +63,6 @@
 #endif
 #endif
 
-#ifndef CK804_USE_NIC
-#define CK804_USE_NIC 0
-#endif
-
-#ifndef CK804_USE_ACI
-#define CK804_USE_ACI 0
-#endif
-
 #define CK804_CHIP_REV 3
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
@@ -89,12 +81,12 @@
 {
 	static const unsigned int ctrl_devport_conf[] = {
 		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 		PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE,
 #endif
 
 		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 		PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE,
 #endif
 	};
@@ -106,11 +98,11 @@
 {
 	static const unsigned int ctrl_devport_conf_clear[] = {
 		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 		PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
 #endif
 		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 		PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
 #endif
 	};
@@ -126,7 +118,7 @@
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000,
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
@@ -141,7 +133,7 @@
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
@@ -155,7 +147,7 @@
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
 #endif
@@ -164,7 +156,7 @@
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
@@ -173,7 +165,7 @@
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff,
@@ -190,7 +182,7 @@
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
@@ -200,7 +192,7 @@
 #endif
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 #endif
 
@@ -226,7 +218,7 @@
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
-#if  CK804_NUM > 1
+#if  CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
@@ -240,25 +232,25 @@
 #endif
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
 #endif
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
 #endif
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
 #endif
 
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
-#if CK804_USE_NIC == 1
+#if CONFIG_CK804_USE_NIC
 	RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
@@ -266,17 +258,17 @@
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23),
 #endif
 
-#if CK804_USE_ACI == 1
+#if CONFIG_CK804_USE_ACI
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 #endif
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),
 #endif
 
-#if CK804_NUM > 1
-#if CK804_USE_NIC == 1
+#if CONFIG_CK804_NUM > 1
+#if CONFIG_CK804_USE_NIC
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
 	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
 	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
@@ -296,7 +288,7 @@
 	setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
 	setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64);
 	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
 	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);

Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -55,14 +55,6 @@
 #define CK804B_PCI_E_X 4
 #endif
 
-#ifndef CK804_USE_NIC
-#define CK804_USE_NIC 0
-#endif
-
-#ifndef CK804_USE_ACI
-#define CK804_USE_ACI 0
-#endif
-
 #define CK804_CHIP_REV 3
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
@@ -198,7 +190,7 @@
 //SYSCTRL
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
-#if CK804_USE_NIC == 1
+#if CONFIG_CK804_USE_NIC
 		RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
@@ -206,7 +198,7 @@
 		RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23),
 #endif
 
-#if CK804_USE_ACI == 1
+#if CONFIG_CK804_USE_ACI
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 #endif
@@ -271,7 +263,7 @@
 
 		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
 
-#if CK804_USE_NIC == 1
+#if CONFIG_CK804_USE_NIC
 		RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),

Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/Kconfig	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/southbridge/nvidia/mcp55/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
@@ -1,7 +1,7 @@
 config SOUTHBRIDGE_NVIDIA_MCP55
 	bool
-	select IOAPIC
 	select HAVE_USBDEBUG
+	select IOAPIC
 
 config ID_SECTION_OFFSET
 	hex
@@ -15,3 +15,14 @@
 	hex
 	default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55
 
+config MCP55_USE_NIC
+	bool
+	default n if SOUTHBRIDGE_NVIDIA_MCP55
+
+config MCP55_USE_AZA
+	bool
+	default n if SOUTHBRIDGE_NVIDIA_MCP55
+
+config MCP55_NUM
+	int
+	default 1 if SOUTHBRIDGE_NVIDIA_MCP55

Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	Tue Oct  5 15:40:31 2010	(r5911)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	Tue Oct  5 19:59:12 2010	(r5912)
@@ -89,14 +89,6 @@
 	#define MCP55_PCI_E_X_3	4
 #endif
 
-#ifndef MCP55_USE_NIC
-	#define MCP55_USE_NIC	0
-#endif
-
-#ifndef MCP55_USE_AZA
-	#define MCP55_USE_AZA	0
-#endif
-
 #define MCP55_CHIP_REV	3
 
 static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
@@ -269,7 +261,7 @@
 	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
 	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
 
-#if MCP55_USE_AZA == 1
+#if CONFIG_MCP55_USE_AZA
 	RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
 
 //	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
@@ -279,7 +271,7 @@
 	MCP55_MB_SETUP
 #endif
 
-#if MCP55_USE_AZA == 1
+#if CONFIG_MCP55_USE_AZA
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
@@ -308,7 +300,7 @@
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
 
 
-#if MCP55_USE_NIC == 1
+#if CONFIG_MCP55_USE_NIC
 	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
 
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
@@ -399,7 +391,7 @@
 				devn[mcp55_num] = devnx;
 				io_base[mcp55_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than MCP55
 				mcp55_num++;
-				if(mcp55_num == MCP55_NUM) goto out;
+				if(mcp55_num == CONFIG_MCP55_NUM) goto out;
 				break; // only one MCP55 on one chain
 			}
 		}



From mylesgw at gmail.com  Tue Oct  5 20:01:51 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 Oct 2010 12:01:51 -0600
Subject: [coreboot] [PATCH]De-define CK804 flags
In-Reply-To: <4CAB5D76.10608@georgi-clan.de>
References: <4CAB3935.9090203@georgi-clan.de>
	<AANLkTim4QOrQXGT5OJZbVz878n1O5qvdONtyDTuJ3vxP@mail.gmail.com>
	<4CAB5D76.10608@georgi-clan.de>
Message-ID: <AANLkTi=hTsvOZjsD_AtiifjE5HOX-L_i=wCh8QY1TU+1@mail.gmail.com>

On Tue, Oct 5, 2010 at 11:16 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 05.10.2010 17:32, schrieb Myles Watson:
>> On Tue, Oct 5, 2010 at 8:41 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
>>> Hi,
>>>
>>> attached patch moves a couple more config flags out of romstage:
>>> CK804_USE_NIC, CK804_USE_ACI.
>>>
>>> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
>> Acked-by: Myles Watson <mylesgw at gmail.com>
>>
>> I'd like to keep CK804 & MCP55 as similar as possible. ?Patches attached.
> Acked-by: Peter Stuge <peter at stuge.se>
Rev 5912.

> One issue: you didn't handle all MCP55_NUMs, there are some #defines
> left.
I didn't see any, but I'll fix them if you point them out.

> I didn't work on the _NUM stuff at all as I don't know its meaning.
It is how many chips there are on the board.  Most boards only have
one CK804 or MCP55, but some have two.

Thanks,
Myles



From svn at coreboot.org  Tue Oct  5 20:21:59 2010
From: svn at coreboot.org (repository service)
Date: Tue, 05 Oct 2010 20:21:59 +0200
Subject: [coreboot] [commit] r5913 - in trunk/src/mainboard: sunw/ultra40
	tyan/s2895
Message-ID: <E1P3C9H-0003rJ-LP@ra.coresystems.de>

Author: myles
Date: Tue Oct  5 20:21:58 2010
New Revision: 5913
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5913

Log:
Add second CK804 for tyan/s2895 and sunw/ultra40.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/mainboard/sunw/ultra40/Kconfig
   trunk/src/mainboard/tyan/s2895/Kconfig

Modified: trunk/src/mainboard/sunw/ultra40/Kconfig
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
+++ trunk/src/mainboard/sunw/ultra40/Kconfig	Tue Oct  5 20:21:58 2010	(r5913)
@@ -37,6 +37,10 @@
 	bool
 	default n
 
+config CK804_NUM
+	int
+	default 2
+
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 2

Modified: trunk/src/mainboard/tyan/s2895/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2895/Kconfig	Tue Oct  5 19:59:12 2010	(r5912)
+++ trunk/src/mainboard/tyan/s2895/Kconfig	Tue Oct  5 20:21:58 2010	(r5913)
@@ -26,6 +26,10 @@
 	hex
 	default 0x10
 
+config CK804_NUM
+	int
+	default 2
+
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 2



From svn at coreboot.org  Tue Oct  5 20:22:01 2010
From: svn at coreboot.org (repository service)
Date: Tue, 05 Oct 2010 20:22:01 +0200
Subject: [coreboot] [commit] r5914 - trunk/util/mkelfImage/linux-i386
Message-ID: <E1P3C9J-0003tc-Mb@ra.coresystems.de>

Author: stuge
Date: Tue Oct  5 20:22:00 2010
New Revision: 5914
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5914

Log:
mkelfImage: set kernel_alignment so 2.6.31+ work

The kernel initialization code as of boot protocol 2.10 is now reading the
kernel_alignment field.  With the field left unset the kernel attempts to
align things to 4GB which is unlikely to work, so change the alignment to
the kernel's normal value of 16MB so newer kernels processed by mkelfImage
will boot.

Signed-off-by: "Eric W. Biederman" <ebiederm at xmission.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/util/mkelfImage/linux-i386/convert_params.c

Modified: trunk/util/mkelfImage/linux-i386/convert_params.c
==============================================================================
--- trunk/util/mkelfImage/linux-i386/convert_params.c	Tue Oct  5 20:21:58 2010	(r5913)
+++ trunk/util/mkelfImage/linux-i386/convert_params.c	Tue Oct  5 20:22:00 2010	(r5914)
@@ -178,7 +178,10 @@
         uint32_t cmd_line_ptr;                  /* 0x228 */
         /* 2.03+ */
         uint32_t initrd_addr_max;               /* 0x22c */
-	uint8_t  reserved15[0x2d0 - 0x230];     /* 0x230 */
+	/* 2.05+ */
+	uint32_t kernel_alignment;		/* 0x230 */
+	uint8_t  relocateable_kernel;		/* 0x234 */
+	uint8_t  reserved15[0x2d0 - 0x235];     /* 0x235 */
 
 	struct e820entry e820_map[E820MAX];	/* 0x2d0 */
 	uint8_t  reserved16[688];		/* 0x550 */
@@ -1512,6 +1515,9 @@
 	/* No loader flags */
 	info->real_mode->loader_flags = 0;
 
+	/* Set it to 16M, instead of 0 which means 4G */
+	info->real_mode->kernel_alignment = 16*1024*1024;
+
 	/* Ramdisk address and size ... */
 	info->real_mode->initrd_start = 0;
 	info->real_mode->initrd_size = 0;



From peter at stuge.se  Tue Oct  5 20:22:46 2010
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 Oct 2010 20:22:46 +0200
Subject: [coreboot] [PATCH] mkelfImage: set kernel_alignment so
	2.6.31+	work
In-Reply-To: <B19746E1-B067-476F-B0C2-BD86C971CAD1@coresystems.de>
References: <201005151529.04593.ttelford.groups@gmail.com>
	<20100515215752.10498.qmail@stuge.se>
	<201005151626.04049.ttelford.groups@gmail.com>
	<201005151628.12643.ttelford.groups@gmail.com>
	<m1pr0syv6b.fsf_-_@fess.ebiederm.org>
	<B19746E1-B067-476F-B0C2-BD86C971CAD1@coresystems.de>
Message-ID: <20101005182246.13020.qmail@stuge.se>

Stefan Reinauer wrote:
> On 19.05.2010, at 13:42, ebiederm at xmission.com (Eric W. Biederman) wrote:
>> The kernel initialization code as of boot protocol 2.10 is now reading the
>> kernel_alignment field.  With the field left the kernel attempts to align
>> things to 4GB which is unlikely to work, so change the alignment to the
>> kernels normal value of 16MB so newer kernels process by mkelfImage will
>> boot.
>>
>> Signed-off-by: "Eric W. Biederman" <ebiederm at xmission.com>
..
> Awesome!
>
> Acked-by: Stefan Reinauer <stepan at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>

r5914



From jakllsch at kollasch.net  Tue Oct  5 20:54:42 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 5 Oct 2010 18:54:42 +0000
Subject: [coreboot] [patch] socket 754 kconfig modernization
Message-ID: <20101005185442.GD12447@tarantulon.kollasch.net>

Modernize socket_754 Kconfig with CAR and address bits information.
Also, update the board that uses this socket to match.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
---
-------------- next part --------------
Index: src/cpu/amd/socket_754/Kconfig
===================================================================
--- src/cpu/amd/socket_754/Kconfig	(revision 5914)
+++ src/cpu/amd/socket_754/Kconfig	(working copy)
@@ -1,13 +1,31 @@
 config CPU_AMD_SOCKET_754
 	bool
+
+if CPU_AMD_SOCKET_754
+
+config SOCKET_SPECIFIC_OPTIONS
+	def_bool y
 	select CPU_AMD_MODEL_FXX
+	select CACHE_AS_RAM
 
 config CPU_SOCKET_TYPE
 	hex
 	default 0x10
-	depends on CPU_AMD_SOCKET_754
 
 config DIMM_SUPPORT
 	hex
 	default 0x108
-	depends on CPU_AMD_SOCKET_754
+
+config CPU_ADDR_BITS
+	int
+	default 40
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+
+endif
Index: src/mainboard/msi/ms7135/Kconfig
===================================================================
--- src/mainboard/msi/ms7135/Kconfig	(revision 5914)
+++ src/mainboard/msi/ms7135/Kconfig	(working copy)
@@ -13,7 +13,6 @@
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
 	select CK804_USE_NIC
 	select CK804_USE_ACI
@@ -66,12 +65,4 @@
 	int
 	default 13
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xc8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 endif # BOARD_MSI_MS7135

From jakllsch at kollasch.net  Tue Oct  5 21:01:07 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 5 Oct 2010 19:01:07 +0000
Subject: [coreboot] [patch] use mptable_write_buses() for msi/ms7135
Message-ID: <20101005190107.GE12447@tarantulon.kollasch.net>

Use mptable_write_buses().
Remove unhelpful comment.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
---
-------------- next part --------------
Index: src/mainboard/msi/ms7135/mptable.c
===================================================================
--- src/mainboard/msi/ms7135/mptable.c	(revision 5914)
+++ src/mainboard/msi/ms7135/mptable.c	(working copy)
@@ -30,23 +30,20 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern unsigned char bus_isa;
 extern unsigned char bus_ck804[6];
 extern unsigned apicid_ck804;
 
-extern unsigned bus_type[256];
-
-
-
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
 	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "MS7135      ";
 	struct mp_config_table *mc;
+	int bus_isa;
 	unsigned sbdn;
 
-	int bus_num;
+	get_bus_conf();
+	sbdn = sysconf.sbdn;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	memset(mc, 0, sizeof(*mc));
@@ -66,19 +63,8 @@
 	mc->reserved = 0;
 
 	smp_write_processors(mc);
+	mptable_write_buses(mc, NULL, &bus_isa);
 
-	get_bus_conf();
-	sbdn = sysconf.sbdn;
-
-/* Bus:		Bus ID	Type*/
-	/* define numbers for pci and isa bus */
-	for (bus_num = 0; bus_num < 256; bus_num++) {
-		if (bus_type[bus_num])
-			smp_write_bus(mc, bus_num, "PCI   ");
-	}
-	smp_write_bus(mc, bus_isa, "ISA   ");
-
-
 /* I/O APICs:	APIC ID	Version	State		Address*/
 	{
 		device_t dev;
@@ -98,7 +84,6 @@
 			/* copied from stock bios */
 			/*0x01800500,0x1800d509,0x00520d08*/
 
-			/* if this register is what i think it is ... */
 			dword = 0x08d0d218;
 			pci_write_config32(dev, 0x7c, dword);
 

From jakllsch at kollasch.net  Tue Oct  5 21:20:06 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 5 Oct 2010 19:20:06 +0000
Subject: [coreboot] [patch] remove duplicate line from pci_ids.h
Message-ID: <20101005192006.GF12447@tarantulon.kollasch.net>

Remove duplicate line from pci_ids.h.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
---



From jakllsch at kollasch.net  Tue Oct  5 21:27:21 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 5 Oct 2010 19:27:21 +0000
Subject: [coreboot] [patch] avoid printf format warning in debugging path
Message-ID: <20101005192721.GG12447@tarantulon.kollasch.net>

Use %p instead of %x to print void *.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>
---



From jakllsch at kollasch.net  Tue Oct  5 21:34:02 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 5 Oct 2010 19:34:02 +0000
Subject: [coreboot] [patch] avoid printf format warning in debugging path
Message-ID: <20101005193402.GH12447@tarantulon.kollasch.net>

Use %p instead of %x to print void *.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>
---
-------------- next part --------------
Index: src/northbridge/amd/amdk8/debug.c
===================================================================
--- src/northbridge/amd/amdk8/debug.c	(revision 5914)
+++ src/northbridge/amd/amdk8/debug.c	(working copy)
@@ -6,7 +6,7 @@
 static inline void print_debug_addr(const char *str, void *val)
 {
 #if CONFIG_DEBUG_CAR
-		printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
+	printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
 #endif
 }
 

From mylesgw at gmail.com  Tue Oct  5 21:35:17 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 Oct 2010 13:35:17 -0600
Subject: [coreboot] [patch] avoid printf format warning in debugging path
In-Reply-To: <20101005192721.GG12447@tarantulon.kollasch.net>
References: <20101005192721.GG12447@tarantulon.kollasch.net>
Message-ID: <A0B5CAA8C4784311B4A9B067C2E00EC0@chimp>

> Subject: [coreboot] [patch] avoid printf format warning in debugging path
> 
> Use %p instead of %x to print void *.
I didn't see the patch for this one or the previous one.

Thanks,
Myles





From jakllsch at kollasch.net  Tue Oct  5 21:36:44 2010
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 5 Oct 2010 19:36:44 +0000
Subject: [coreboot] [patch] remove duplicate line from pci_ids.h
Message-ID: <20101005193644.GI12447@tarantulon.kollasch.net>

Remove duplicate line from pci_ids.h.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
---
-------------- next part --------------
Index: src/include/device/pci_ids.h
===================================================================
--- src/include/device/pci_ids.h	(revision 5914)
+++ src/include/device/pci_ids.h	(working copy)
@@ -1048,7 +1048,6 @@
 #define PCI_DEVICE_ID_NVIDIA_CK804_IDE          0x0053
 #define PCI_DEVICE_ID_NVIDIA_CK804_SATA0        0x0054
 #define PCI_DEVICE_ID_NVIDIA_CK804_SATA1        0x0055
-#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1        0x0055
 #define PCI_DEVICE_ID_NVIDIA_CK804_ENET         0x0056
 #define PCI_DEVICE_ID_NVIDIA_CK804_NIC          0x0056
 #define PCI_DEVICE_ID_NVIDIA_CK804_ENET2        0x0057

From svn at coreboot.org  Tue Oct  5 21:38:04 2010
From: svn at coreboot.org (repository service)
Date: Tue, 05 Oct 2010 21:38:04 +0200
Subject: [coreboot] [commit] r5915 - trunk/src/northbridge/amd/amdk8
Message-ID: <E1P3DKu-00079T-Pl@ra.coresystems.de>

Author: myles
Date: Tue Oct  5 21:38:04 2010
New Revision: 5915
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5915

Log:
Use %p instead of %x to print void *.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>

Modified:
   trunk/src/northbridge/amd/amdk8/debug.c

Modified: trunk/src/northbridge/amd/amdk8/debug.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/debug.c	Tue Oct  5 20:22:00 2010	(r5914)
+++ trunk/src/northbridge/amd/amdk8/debug.c	Tue Oct  5 21:38:04 2010	(r5915)
@@ -6,7 +6,7 @@
 static inline void print_debug_addr(const char *str, void *val)
 {
 #if CONFIG_DEBUG_CAR
-		printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
+	printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
 #endif
 }
 



From svn at coreboot.org  Tue Oct  5 21:39:35 2010
From: svn at coreboot.org (repository service)
Date: Tue, 05 Oct 2010 21:39:35 +0200
Subject: [coreboot] [commit] r5916 - trunk/src/include/device
Message-ID: <E1P3DMN-0000qF-Na@ra.coresystems.de>

Author: myles
Date: Tue Oct  5 21:39:35 2010
New Revision: 5916
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5916

Log:
Remove duplicate line from pci_ids.h.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>

Modified:
   trunk/src/include/device/pci_ids.h

Modified: trunk/src/include/device/pci_ids.h
==============================================================================
--- trunk/src/include/device/pci_ids.h	Tue Oct  5 21:38:04 2010	(r5915)
+++ trunk/src/include/device/pci_ids.h	Tue Oct  5 21:39:35 2010	(r5916)
@@ -1048,7 +1048,6 @@
 #define PCI_DEVICE_ID_NVIDIA_CK804_IDE          0x0053
 #define PCI_DEVICE_ID_NVIDIA_CK804_SATA0        0x0054
 #define PCI_DEVICE_ID_NVIDIA_CK804_SATA1        0x0055
-#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1        0x0055
 #define PCI_DEVICE_ID_NVIDIA_CK804_ENET         0x0056
 #define PCI_DEVICE_ID_NVIDIA_CK804_NIC          0x0056
 #define PCI_DEVICE_ID_NVIDIA_CK804_ENET2        0x0057



From mylesgw at gmail.com  Tue Oct  5 21:40:37 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 Oct 2010 13:40:37 -0600
Subject: [coreboot] [patch] remove duplicate line from pci_ids.h
In-Reply-To: <20101005193644.GI12447@tarantulon.kollasch.net>
References: <20101005193644.GI12447@tarantulon.kollasch.net>
Message-ID: <AANLkTimZvN_Z9tA7QUYc9zx8SAJqhJ5PQ2aSM3NySPCd@mail.gmail.com>

On Tue, Oct 5, 2010 at 1:36 PM, Jonathan A. Kollasch
<jakllsch at kollasch.net> wrote:
> Remove duplicate line from pci_ids.h.
>
> Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
> Acked-off-by: Jonathan Kollasch <jakllsch at kollasch.net>

Rev 5916.

Thanks,
Myles



From wt at penguintechs.org  Tue Oct  5 21:49:57 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Tue, 5 Oct 2010 12:49:57 -0700
Subject: [coreboot] [PATCH] Reduce duplicate definition in CAR code.
In-Reply-To: <AANLkTin_0uQdpXsrEiY-mxi3r1Vj6K+_jBNv5Uaf37zJ@mail.gmail.com>
References: <1286272836-1767-1-git-send-email-wt@penguintechs.org>
	<AANLkTin_0uQdpXsrEiY-mxi3r1Vj6K+_jBNv5Uaf37zJ@mail.gmail.com>
Message-ID: <AANLkTin-p=W0LTSdGbEd05oEoudGnzzUu1hdbguSBWZK@mail.gmail.com>

Is that an Ack? If so, I will work on a more serious patch that does
this for all car implementations and moves the lists to a header.

I am thinking of using a macro like MTRR_ADDR_LIST_ASM in the header.
What do you think about that? I don't want it to look like a function
call. What do you think about that?

Thanks,
wt

On Tue, Oct 5, 2010 at 8:36 AM, ron minnich <rminnich at gmail.com> wrote:
> On Tue, Oct 5, 2010 at 3:00 AM, Warren Turkal <wt at penguintechs.org> wrote:
>> Here is a patch that I feel improves the readability of the CAR code a
>> little bit. What do you all think?
>
>
> I think it's quite nice, as you replace mysterious numbers with a
> meaningful name.
>
> ron
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From mylesgw at gmail.com  Tue Oct  5 21:40:59 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 Oct 2010 13:40:59 -0600
Subject: [coreboot] [patch] avoid printf format warning in debugging path
In-Reply-To: <20101005193402.GH12447@tarantulon.kollasch.net>
References: <20101005193402.GH12447@tarantulon.kollasch.net>
Message-ID: <AANLkTi=rq3hkBBfB6niA=E6cUsWr2aBQgFDanoR6VdiT@mail.gmail.com>

On Tue, Oct 5, 2010 at 1:34 PM, Jonathan A. Kollasch
<jakllsch at kollasch.net> wrote:
> Use %p instead of %x to print void *.
>
> Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
> Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>
Rev 5915.

Thanks,
Myles



From rminnich at gmail.com  Tue Oct  5 22:15:36 2010
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 Oct 2010 13:15:36 -0700
Subject: [coreboot] [PATCH] Reduce duplicate definition in CAR code.
In-Reply-To: <AANLkTin-p=W0LTSdGbEd05oEoudGnzzUu1hdbguSBWZK@mail.gmail.com>
References: <1286272836-1767-1-git-send-email-wt@penguintechs.org>
	<AANLkTin_0uQdpXsrEiY-mxi3r1Vj6K+_jBNv5Uaf37zJ@mail.gmail.com>
	<AANLkTin-p=W0LTSdGbEd05oEoudGnzzUu1hdbguSBWZK@mail.gmail.com>
Message-ID: <AANLkTinfYX=-gs1TtX9RKEpQKmpc6SfNSx7fr_rweafH@mail.gmail.com>

I think I'm happier if other newer commiters ack this stuff. I don't
work with the code frequently enough to feel comfortable acking some
of these things.

I'm very happy with macros that make data definitions clearer. I'm
very worried about assembly code macros because this is tricky
assembly and people fall into certain habits in terms of thinking
macros are side-effect-free, which they are not in this case.

thanks!

ron



From wt at penguintechs.org  Tue Oct  5 22:18:57 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Tue, 5 Oct 2010 13:18:57 -0700
Subject: [coreboot] [PATCH] Reduce duplicate definition in CAR code.
In-Reply-To: <AANLkTinfYX=-gs1TtX9RKEpQKmpc6SfNSx7fr_rweafH@mail.gmail.com>
References: <1286272836-1767-1-git-send-email-wt@penguintechs.org>
	<AANLkTin_0uQdpXsrEiY-mxi3r1Vj6K+_jBNv5Uaf37zJ@mail.gmail.com>
	<AANLkTin-p=W0LTSdGbEd05oEoudGnzzUu1hdbguSBWZK@mail.gmail.com>
	<AANLkTinfYX=-gs1TtX9RKEpQKmpc6SfNSx7fr_rweafH@mail.gmail.com>
Message-ID: <AANLkTi=hDp2CmrxJ067wmm3JW3_RV39LMLK_tQq-Apvv@mail.gmail.com>

On Tue, Oct 5, 2010 at 1:15 PM, ron minnich <rminnich at gmail.com> wrote:
> I think I'm happier if other newer commiters ack this stuff. I don't
> work with the code frequently enough to feel comfortable acking some
> of these things.

Fair enough. Anyone else have any comments?

> I'm very happy with macros that make data definitions clearer. I'm
> very worried about assembly code macros because this is tricky
> assembly and people fall into certain habits in terms of thinking
> macros are side-effect-free, which they are not in this case.

Let me throw together a patch and see what you and others think.

Thanks,
wt



From wt at penguintechs.org  Wed Oct  6 00:02:11 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Tue,  5 Oct 2010 15:02:11 -0700
Subject: [coreboot] [PATCH try 2] Reduce duplicate definition in CAR code.
Message-ID: <1286316131-6936-1-git-send-email-wt@penguintechs.org>

Here's another cut at this patch that is more comprehensive. I have
included all major vendor car implementations. What do you all think
about this approach?

Thanks,
wt
8<------------
Macros for the register addresses for the MTRR MSRs are already defined
in include/cpu/x86/car.h. This patch uses those macros instead of
creating a second instance of that same data.

I also combined common MTRR definitions into a macro.

Signed-off-by: Warren Turkal <wt at penguintechs.org>
---
 src/cpu/amd/car/cache_as_ram.inc   |   24 +++++-------------------
 src/cpu/intel/car/cache_as_ram.inc |   17 ++++-------------
 src/cpu/via/car/cache_as_ram.inc   |   17 ++++-------------
 src/include/cpu/amd/mtrr.h         |    9 +++++++++
 src/include/cpu/x86/mtrr.h         |   31 +++++++++++++++++++++++++++++++
 5 files changed, 53 insertions(+), 45 deletions(-)

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 5318272..a8c6972 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -155,7 +155,7 @@ enable_fixed_mtrr_dram_modify:
 
 	/* Clear all MTRRs. */
 	xorl	%edx, %edx
-	movl	$fixed_mtrr_msr, %esi
+	movl	$all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
 	lodsl	(%esi), %eax
@@ -396,23 +396,9 @@ CAR_FAM10_ap_out:
 
 	post_code(0xaf)		/* Should never see this POST code. */
 
-fixed_mtrr_msr:
-	.long	0x250, 0x258, 0x259
-	.long	0x268, 0x269, 0x26A
-	.long	0x26B, 0x26C, 0x26D
-	.long	0x26E, 0x26F
-
-var_mtrr_msr:
-	.long	0x200, 0x201, 0x202, 0x203
-	.long	0x204, 0x205, 0x206, 0x207
-	.long	0x208, 0x209, 0x20A, 0x20B
-	.long	0x20C, 0x20D, 0x20E, 0x20F
-
-var_iorr_msr:
-	.long	0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
-
-mem_top:
-	.long	0xC001001A, 0xC001001D
-	.long	0x000 /* NULL, end of table */
+all_mtrr_msrs:
+X86_MTRR_MSRS_TABLE_ENTRIES_ASM
+AMD_MTRR_MSRS_TABLE_ENTRIES_ASM
+END_MTRR_MSRS_TABLE_ENTRY_ASM
 
 cache_as_ram_setup_out:
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index d8465f4..84e2f2f 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -115,7 +115,7 @@ NotHtProcessor:
 
 	/* Clear all MTRRs. */
 	xorl	%edx, %edx
-	movl	$fixed_mtrr_msr, %esi
+	movl	$all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
 	lodsl	(%esi), %eax
@@ -128,18 +128,9 @@ clear_fixed_var_mtrr:
 
 	jmp	clear_fixed_var_mtrr
 
-fixed_mtrr_msr:
-	.long	0x250, 0x258, 0x259
-	.long	0x268, 0x269, 0x26A
-	.long	0x26B, 0x26C, 0x26D
-	.long	0x26E, 0x26F
-
-var_mtrr_msr:
-	.long	0x200, 0x201, 0x202, 0x203
-	.long	0x204, 0x205, 0x206, 0x207
-	.long	0x208, 0x209, 0x20A, 0x20B
-	.long	0x20C, 0x20D, 0x20E, 0x20F
-	.long	0x000 /* NULL, end of table */
+all_mtrr_msrs:
+X86_MTRR_MSRS_TABLE_ENTRIES_ASM
+END_MTRR_MSRS_TABLE_ENTRY_ASM
 
 clear_fixed_var_mtrr_out:
 
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index d6df4a9..80f8c13 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -47,7 +47,7 @@ CacheAsRam:
 
 	/* Clear all MTRRs. */
 	xorl	%edx, %edx
-	movl	$fixed_mtrr_msr, %esi
+	movl	$all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
 	lodsl	(%esi), %eax
@@ -60,18 +60,9 @@ clear_fixed_var_mtrr:
 
 	jmp	clear_fixed_var_mtrr
 
-fixed_mtrr_msr:
-	.long	0x250, 0x258, 0x259
-	.long	0x268, 0x269, 0x26A
-	.long	0x26B, 0x26C, 0x26D
-	.long	0x26E, 0x26F
-
-var_mtrr_msr:
-	.long	0x200, 0x201, 0x202, 0x203
-	.long	0x204, 0x205, 0x206, 0x207
-	.long	0x208, 0x209, 0x20A, 0x20B
-	.long	0x20C, 0x20D, 0x20E, 0x20F
-	.long	0x000 /* NULL, end of table */
+all_mtrr_msrs:
+X86_MTRR_MSRS_TABLE_ENTRIES_ASM
+END_MTRR_MSRS_TABLE_ENTRY_ASM
 
 clear_fixed_var_mtrr_out:
 	movl	$MTRRphysBase_MSR(0), %ecx
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index c7b3fca..1649632 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -31,6 +31,15 @@
 #define TOP_MEM_MASK			0x007fffff
 #define TOP_MEM_MASK_KB			(TOP_MEM_MASK >> 10)
 
+#if defined(ASSEMBLY)
+.macro AMD_MTRR_MSRS_TABLE_ENTRIES_ASM
+	/* Variable IORR MTRR MSRs */
+	.long	0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
+	/* Top of memory MTRR MSRs */
+	.long	0xC001001A, 0xC001001D
+.endm /* AMD_MTRR_MSRS_TABLE_ENTRIES_ASM */
+#endif /* defined(ASSEMBLY) */
+
 #if !defined(__PRE_RAM__) && !defined(ASSEMBLY)
 void amd_setup_mtrrs(void);
 #endif
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index e79c90e..ba3ab08 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -34,6 +34,37 @@
 #define MTRRfix4K_F0000_MSR 0x26e
 #define MTRRfix4K_F8000_MSR 0x26f
 
+#if defined (ASSEMBLY)
+.macro X86_MTRR_MSRS_TABLE_ENTRIES_ASM
+	/* fixed mtrr MSRs */
+	.long	MTRRfix64K_00000_MSR
+	.long	MTRRfix16K_80000_MSR
+	.long	MTRRfix16K_A0000_MSR
+	.long	MTRRfix4K_C0000_MSR
+	.long	MTRRfix4K_C8000_MSR
+	.long	MTRRfix4K_D0000_MSR
+	.long	MTRRfix4K_D8000_MSR
+	.long	MTRRfix4K_E0000_MSR
+	.long	MTRRfix4K_E8000_MSR
+	.long	MTRRfix4K_F0000_MSR
+	.long	MTRRfix4K_F8000_MSR
+
+	/* var mtrr MSRs */
+	.long	MTRRphysBase_MSR(0), MTRRphysBase_MSR(1)
+	.long	MTRRphysBase_MSR(2), MTRRphysBase_MSR(3)
+	.long	MTRRphysBase_MSR(4), MTRRphysBase_MSR(5)
+	.long	MTRRphysBase_MSR(6), MTRRphysBase_MSR(7)
+	.long	MTRRphysBase_MSR(8), MTRRphysBase_MSR(9)
+	.long	MTRRphysBase_MSR(10), MTRRphysBase_MSR(11)
+	.long	MTRRphysBase_MSR(12), MTRRphysBase_MSR(13)
+	.long	MTRRphysBase_MSR(14), MTRRphysBase_MSR(15)
+.endm /* X86_MTRR_MSRS_TABLE_ENTRIES_ASM */
+
+.macro END_MTRR_MSRS_TABLE_ENTRY_ASM
+	.long	0x000 /* NULL, end of table */
+.endm /* END_MTRR_MSRS_TABLE_ASM */
+#endif /* defined (ASSEMBLY) */
+
 #if !defined (ASSEMBLY) && !defined(__PRE_RAM__)
 #include <device/device.h>
 void enable_fixed_mtrr(void);
-- 
1.7.1




From rminnich at gmail.com  Wed Oct  6 00:18:09 2010
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 Oct 2010 15:18:09 -0700
Subject: [coreboot] [PATCH try 2] Reduce duplicate definition in CAR
	code.
In-Reply-To: <1286316131-6936-1-git-send-email-wt@penguintechs.org>
References: <1286316131-6936-1-git-send-email-wt@penguintechs.org>
Message-ID: <AANLkTinNh8dYSF-ZfGMeZPTza04z4JzBM9-OMCpQOBU1@mail.gmail.com>

It's proven dangerous in the past to cross mtrr settings across vendors.

Which is what you are doing. Then somebody patches, e.g.,
cpu/x86/mtrr.h for some fix to via, and we find out a year later it is
not right for some flavor of AMD. MTRRs have been a rolling headache
for 10 years now.

Sure they should all be the same. Sometimes there are weird issues.

So what I'd prefer, personally: leave the settings in each vendor
file: amd, via, whatever, don't make the common settings in
cpu/x86/mtrr.h. But use your nice macros to set those up.

ron



From wt at penguintechs.org  Wed Oct  6 00:28:36 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Tue, 5 Oct 2010 15:28:36 -0700
Subject: [coreboot] [PATCH try 2] Reduce duplicate definition in CAR
	code.
In-Reply-To: <AANLkTinNh8dYSF-ZfGMeZPTza04z4JzBM9-OMCpQOBU1@mail.gmail.com>
References: <1286316131-6936-1-git-send-email-wt@penguintechs.org>
	<AANLkTinNh8dYSF-ZfGMeZPTza04z4JzBM9-OMCpQOBU1@mail.gmail.com>
Message-ID: <AANLkTik5VH2a4E0TpSgVrdkbbUCs+8NobkHbnh7brX0j@mail.gmail.com>

The common mtrr registers are separated into their own macros. For
instance, check out the AMD car code. AMD has additional mtrr
registers that are used. There is an AMD_MTRR_MSRS_TABLE_ENTRIES_ASM
as a result. Is this not enough to separate the vendors?

Or is your assertion that the values in
X86_MTRR_MSRS_TABLE_ENTRIES_ASM can vary?

Thanks,
wt

On Tue, Oct 5, 2010 at 3:18 PM, ron minnich <rminnich at gmail.com> wrote:
> It's proven dangerous in the past to cross mtrr settings across vendors.
>
> Which is what you are doing. Then somebody patches, e.g.,
> cpu/x86/mtrr.h for some fix to via, and we find out a year later it is
> not right for some flavor of AMD. MTRRs have been a rolling headache
> for 10 years now.
>
> Sure they should all be the same. Sometimes there are weird issues.
>
> So what I'd prefer, personally: leave the settings in each vendor
> file: amd, via, whatever, don't make the common settings in
> cpu/x86/mtrr.h. But use your nice macros to set those up.
>
> ron
>



From rminnich at gmail.com  Wed Oct  6 00:46:03 2010
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 Oct 2010 15:46:03 -0700
Subject: [coreboot] [PATCH try 2] Reduce duplicate definition in CAR
	code.
In-Reply-To: <AANLkTik5VH2a4E0TpSgVrdkbbUCs+8NobkHbnh7brX0j@mail.gmail.com>
References: <1286316131-6936-1-git-send-email-wt@penguintechs.org>
	<AANLkTinNh8dYSF-ZfGMeZPTza04z4JzBM9-OMCpQOBU1@mail.gmail.com>
	<AANLkTik5VH2a4E0TpSgVrdkbbUCs+8NobkHbnh7brX0j@mail.gmail.com>
Message-ID: <AANLkTi=GgvA7CXatyBt-Enm61qp5uBT3zAYUq+s6WWi5@mail.gmail.com>

On Tue, Oct 5, 2010 at 3:28 PM, Warren Turkal <wt at penguintechs.org> wrote:
> The common mtrr registers are separated into their own macros. For
> instance, check out the AMD car code. AMD has additional mtrr
> registers that are used. There is an AMD_MTRR_MSRS_TABLE_ENTRIES_ASM
> as a result. Is this not enough to separate the vendors?
>
> Or is your assertion that the values in
> X86_MTRR_MSRS_TABLE_ENTRIES_ASM can vary?


oops, I misread it. OK, got it, makes sense.

I think you can leave the _ASM off since you are using as .macro
anyway -- you can't use it anywhere but assembly. If we're all certain
that those registers are all safely common across all systems, I guess
it works for me.

Possibly we should get some testing to make sure it's good.

ron



From wt at penguintechs.org  Wed Oct  6 00:54:39 2010
From: wt at penguintechs.org (Warren Turkal)
Date: Tue, 5 Oct 2010 15:54:39 -0700
Subject: [coreboot] [PATCH try 2] Reduce duplicate definition in CAR
	code.
In-Reply-To: <AANLkTi=GgvA7CXatyBt-Enm61qp5uBT3zAYUq+s6WWi5@mail.gmail.com>
References: <1286316131-6936-1-git-send-email-wt@penguintechs.org>
	<AANLkTinNh8dYSF-ZfGMeZPTza04z4JzBM9-OMCpQOBU1@mail.gmail.com>
	<AANLkTik5VH2a4E0TpSgVrdkbbUCs+8NobkHbnh7brX0j@mail.gmail.com>
	<AANLkTi=GgvA7CXatyBt-Enm61qp5uBT3zAYUq+s6WWi5@mail.gmail.com>
Message-ID: <AANLkTin0dfAgckD1bjzyVbWeFDcUCAGB8PsSztdGbSgQ@mail.gmail.com>

I have run "util/abuild/abuild -a -c 8", and nothing showed up except
some lib/gcc.c stuff that I have no idea how to fix.

I put the _ASM on to note that it's adding asm code. I figured that'd
make it more obvious. Is it obvious enough without the _ASM?

wt

On Tue, Oct 5, 2010 at 3:46 PM, ron minnich <rminnich at gmail.com> wrote:
> On Tue, Oct 5, 2010 at 3:28 PM, Warren Turkal <wt at penguintechs.org> wrote:
>> The common mtrr registers are separated into their own macros. For
>> instance, check out the AMD car code. AMD has additional mtrr
>> registers that are used. There is an AMD_MTRR_MSRS_TABLE_ENTRIES_ASM
>> as a result. Is this not enough to separate the vendors?
>>
>> Or is your assertion that the values in
>> X86_MTRR_MSRS_TABLE_ENTRIES_ASM can vary?
>
>
> oops, I misread it. OK, got it, makes sense.
>
> I think you can leave the _ASM off since you are using as .macro
> anyway -- you can't use it anywhere but assembly. If we're all certain
> that those registers are all safely common across all systems, I guess
> it works for me.
>
> Possibly we should get some testing to make sure it's good.
>
> ron
>



From rminnich at gmail.com  Wed Oct  6 00:56:49 2010
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 Oct 2010 15:56:49 -0700
Subject: [coreboot] [PATCH try 2] Reduce duplicate definition in CAR
	code.
In-Reply-To: <AANLkTin0dfAgckD1bjzyVbWeFDcUCAGB8PsSztdGbSgQ@mail.gmail.com>
References: <1286316131-6936-1-git-send-email-wt@penguintechs.org>
	<AANLkTinNh8dYSF-ZfGMeZPTza04z4JzBM9-OMCpQOBU1@mail.gmail.com>
	<AANLkTik5VH2a4E0TpSgVrdkbbUCs+8NobkHbnh7brX0j@mail.gmail.com>
	<AANLkTi=GgvA7CXatyBt-Enm61qp5uBT3zAYUq+s6WWi5@mail.gmail.com>
	<AANLkTin0dfAgckD1bjzyVbWeFDcUCAGB8PsSztdGbSgQ@mail.gmail.com>
Message-ID: <AANLkTik_0qqrHxkUhsoPK=--1zCisAq-wSqjthn9-Zhb@mail.gmail.com>

On Tue, Oct 5, 2010 at 3:54 PM, Warren Turkal <wt at penguintechs.org> wrote:
> I have run "util/abuild/abuild -a -c 8", and nothing showed up except
> some lib/gcc.c stuff that I have no idea how to fix.
>
> I put the _ASM on to note that it's adding asm code. I figured that'd
> make it more obvious. Is it obvious enough without the _ASM?


It is to me ...

ron



From peter at stuge.se  Wed Oct  6 01:15:59 2010
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 Oct 2010 01:15:59 +0200
Subject: [coreboot] [PATCH try 2] Reduce duplicate definition in
	CAR	code.
In-Reply-To: <AANLkTin0dfAgckD1bjzyVbWeFDcUCAGB8PsSztdGbSgQ@mail.gmail.com>
References: <1286316131-6936-1-git-send-email-wt@penguintechs.org>
	<AANLkTinNh8dYSF-ZfGMeZPTza04z4JzBM9-OMCpQOBU1@mail.gmail.com>
	<AANLkTik5VH2a4E0TpSgVrdkbbUCs+8NobkHbnh7brX0j@mail.gmail.com>
	<AANLkTi=GgvA7CXatyBt-Enm61qp5uBT3zAYUq+s6WWi5@mail.gmail.com>
	<AANLkTin0dfAgckD1bjzyVbWeFDcUCAGB8PsSztdGbSgQ@mail.gmail.com>
Message-ID: <20101005231559.12221.qmail@stuge.se>

Warren Turkal wrote:
> I have run "util/abuild/abuild -a -c 8", and nothing showed up except
> some lib/gcc.c stuff that I have no idea how to fix.

No good to break things. What were the errors?


//Peter



From peter at stuge.se  Wed Oct  6 06:24:17 2010
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 Oct 2010 06:24:17 +0200
Subject: [coreboot] [PATCH] mkelfImage: set kernel_alignment
	so	2.6.31+work
In-Reply-To: <m1iq6gzys0.fsf@fess.ebiederm.org>
References: <m1sk5mxnrf.fsf@fess.ebiederm.org>
	<201005201834.28053.ttelford.groups@gmail.com>
	<m1632ixeot.fsf@fess.ebiederm.org>
	<37A8727F-04C5-4B53-8820-A7BD67DD9AE6@gmail.com>
	<801DF75286A94D53ADFFD53EB5E72EC3@chimp>
	<m1wrux3v4u.fsf@fess.ebiederm.org>
	<EFF785CB5B6B4EAC950B57C42A7CFA41@chimp>
	<m1vdah0zu9.fsf@fess.ebiederm.org>
	<AANLkTimRpWrJ75BTqhwmh5uzGh0u1SySFYxwMw9R8lV0@mail.gmail.com>
	<m1iq6gzys0.fsf@fess.ebiederm.org>
Message-ID: <20101006042417.11595.qmail@stuge.se>

Eric W. Biederman wrote:
> >> At the moment I want to mandate a bzImage for x86, but I'm not
> >> certain if that is practical the way we build images for coreboot.
..
> I think I need to ensure that linux builds a bImage.  So that you
> can have an uncompress bzImage.  For this embedded case.

bImage would help make mkelfImage's life easier staying forward
compatible?


//Peter



From ebiederm at xmission.com  Wed Oct  6 07:43:19 2010
From: ebiederm at xmission.com (Eric W. Biederman)
Date: Tue, 05 Oct 2010 22:43:19 -0700
Subject: [coreboot] [PATCH] mkelfImage: set kernel_alignment so
	2.6.31+work
In-Reply-To: <20101006042417.11595.qmail@stuge.se> (Peter Stuge's message of
	"Wed, 6 Oct 2010 06:24:17 +0200")
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Peter Stuge <peter at stuge.se> writes:

> Eric W. Biederman wrote:
>> >> At the moment I want to mandate a bzImage for x86, but I'm not
>> >> certain if that is practical the way we build images for coreboot.
> ..
>> I think I need to ensure that linux builds