[coreboot] [commit] r5889 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3

repository service svn at coreboot.org
Fri Oct 1 08:27:35 CEST 2010


Author: zbao
Date: Fri Oct  1 08:27:35 2010
New Revision: 5889
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5889

Log:
Trivial. Re-indent the code.


Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Zheng Bao <zheng.bao at amd.com>

Modified:
   trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c
   trunk/src/northbridge/amd/amdmct/mct/mctsrc.c
   trunk/src/northbridge/amd/amdmct/mct/mcttmrl.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c

Modified: trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -65,9 +65,9 @@
 				DramBase = pDCTstat->NodeSysBase >> 8;
 				dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8;
 				dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114);
-					if (dct0_size >= 0x10000) {
-						dct0_size -= HoleSize;
-					}
+				if (dct0_size >= 0x10000) {
+					dct0_size -= HoleSize;
+				}
 
 				dct0_size -= DramBase;
 				dct1_size -= dct0_size;

Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mctsrc.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct/mctsrc.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -961,7 +961,7 @@
 				val += val0;
 			}
 
-		pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
+			pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
 		}
 	}
 	SetEccDQSRcvrEn_D(pDCTstat, Channel);
@@ -979,8 +979,8 @@
 		if (!pDCTstat->NodePresent)
 			break;
 		if (pDCTstat->DCTSysLimit) {
-		for(i=0; i<2; i++)
-		CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
+			for(i=0; i<2; i++)
+				CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
 		}
 	}
 }

Modified: trunk/src/northbridge/amd/amdmct/mct/mcttmrl.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mcttmrl.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct/mcttmrl.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -220,8 +220,8 @@
 
 	if (pDCTstat->GangedMode) {
 		Channel = 0; // for safe
-	for (i=0; i<2; i++)
-		pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
+		for (i=0; i<2; i++)
+			pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
 	} else {
 		pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal;
 	}

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -61,9 +61,9 @@
 				DramBase = pDCTstat->NodeSysBase >> 8;
 				dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8;
 				dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114);
-					if (dct0_size >= 0x10000) {
-						dct0_size -= HoleSize;
-					}
+				if (dct0_size >= 0x10000) {
+					dct0_size -= HoleSize;
+				}
 
 				dct0_size -= DramBase;
 				dct1_size -= dct0_size;

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -914,7 +914,7 @@
 				val += val1;
 			}
 
-		pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
+			pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
 		}
 	}
 	SetEccDQSRcvrEn_D(pDCTstat, Channel);
@@ -932,8 +932,8 @@
 		if (!pDCTstat->NodePresent)
 			break;
 		if (pDCTstat->DCTSysLimit) {
-		for(i=0; i<2; i++)
-		CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
+			for(i=0; i<2; i++)
+				CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
 		}
 	}
 }

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c	Fri Oct  1 08:27:35 2010	(r5889)
@@ -213,8 +213,8 @@
 
 	if (pDCTstat->GangedMode) {
 		Channel = 0; /* for safe */
-	for (i=0; i<2; i++)
-		pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
+		for (i=0; i<2; i++)
+			pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
 	} else {
 		pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal;
 	}




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