[coreboot] [PATCH try 2] Reduce duplicate definition in CAR code.

Warren Turkal wt at penguintechs.org
Wed Oct 6 00:02:11 CEST 2010


Here's another cut at this patch that is more comprehensive. I have
included all major vendor car implementations. What do you all think
about this approach?

Thanks,
wt
8<------------
Macros for the register addresses for the MTRR MSRs are already defined
in include/cpu/x86/car.h. This patch uses those macros instead of
creating a second instance of that same data.

I also combined common MTRR definitions into a macro.

Signed-off-by: Warren Turkal <wt at penguintechs.org>
---
 src/cpu/amd/car/cache_as_ram.inc   |   24 +++++-------------------
 src/cpu/intel/car/cache_as_ram.inc |   17 ++++-------------
 src/cpu/via/car/cache_as_ram.inc   |   17 ++++-------------
 src/include/cpu/amd/mtrr.h         |    9 +++++++++
 src/include/cpu/x86/mtrr.h         |   31 +++++++++++++++++++++++++++++++
 5 files changed, 53 insertions(+), 45 deletions(-)

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 5318272..a8c6972 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -155,7 +155,7 @@ enable_fixed_mtrr_dram_modify:
 
 	/* Clear all MTRRs. */
 	xorl	%edx, %edx
-	movl	$fixed_mtrr_msr, %esi
+	movl	$all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
 	lodsl	(%esi), %eax
@@ -396,23 +396,9 @@ CAR_FAM10_ap_out:
 
 	post_code(0xaf)		/* Should never see this POST code. */
 
-fixed_mtrr_msr:
-	.long	0x250, 0x258, 0x259
-	.long	0x268, 0x269, 0x26A
-	.long	0x26B, 0x26C, 0x26D
-	.long	0x26E, 0x26F
-
-var_mtrr_msr:
-	.long	0x200, 0x201, 0x202, 0x203
-	.long	0x204, 0x205, 0x206, 0x207
-	.long	0x208, 0x209, 0x20A, 0x20B
-	.long	0x20C, 0x20D, 0x20E, 0x20F
-
-var_iorr_msr:
-	.long	0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
-
-mem_top:
-	.long	0xC001001A, 0xC001001D
-	.long	0x000 /* NULL, end of table */
+all_mtrr_msrs:
+X86_MTRR_MSRS_TABLE_ENTRIES_ASM
+AMD_MTRR_MSRS_TABLE_ENTRIES_ASM
+END_MTRR_MSRS_TABLE_ENTRY_ASM
 
 cache_as_ram_setup_out:
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index d8465f4..84e2f2f 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -115,7 +115,7 @@ NotHtProcessor:
 
 	/* Clear all MTRRs. */
 	xorl	%edx, %edx
-	movl	$fixed_mtrr_msr, %esi
+	movl	$all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
 	lodsl	(%esi), %eax
@@ -128,18 +128,9 @@ clear_fixed_var_mtrr:
 
 	jmp	clear_fixed_var_mtrr
 
-fixed_mtrr_msr:
-	.long	0x250, 0x258, 0x259
-	.long	0x268, 0x269, 0x26A
-	.long	0x26B, 0x26C, 0x26D
-	.long	0x26E, 0x26F
-
-var_mtrr_msr:
-	.long	0x200, 0x201, 0x202, 0x203
-	.long	0x204, 0x205, 0x206, 0x207
-	.long	0x208, 0x209, 0x20A, 0x20B
-	.long	0x20C, 0x20D, 0x20E, 0x20F
-	.long	0x000 /* NULL, end of table */
+all_mtrr_msrs:
+X86_MTRR_MSRS_TABLE_ENTRIES_ASM
+END_MTRR_MSRS_TABLE_ENTRY_ASM
 
 clear_fixed_var_mtrr_out:
 
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index d6df4a9..80f8c13 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -47,7 +47,7 @@ CacheAsRam:
 
 	/* Clear all MTRRs. */
 	xorl	%edx, %edx
-	movl	$fixed_mtrr_msr, %esi
+	movl	$all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
 	lodsl	(%esi), %eax
@@ -60,18 +60,9 @@ clear_fixed_var_mtrr:
 
 	jmp	clear_fixed_var_mtrr
 
-fixed_mtrr_msr:
-	.long	0x250, 0x258, 0x259
-	.long	0x268, 0x269, 0x26A
-	.long	0x26B, 0x26C, 0x26D
-	.long	0x26E, 0x26F
-
-var_mtrr_msr:
-	.long	0x200, 0x201, 0x202, 0x203
-	.long	0x204, 0x205, 0x206, 0x207
-	.long	0x208, 0x209, 0x20A, 0x20B
-	.long	0x20C, 0x20D, 0x20E, 0x20F
-	.long	0x000 /* NULL, end of table */
+all_mtrr_msrs:
+X86_MTRR_MSRS_TABLE_ENTRIES_ASM
+END_MTRR_MSRS_TABLE_ENTRY_ASM
 
 clear_fixed_var_mtrr_out:
 	movl	$MTRRphysBase_MSR(0), %ecx
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index c7b3fca..1649632 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -31,6 +31,15 @@
 #define TOP_MEM_MASK			0x007fffff
 #define TOP_MEM_MASK_KB			(TOP_MEM_MASK >> 10)
 
+#if defined(ASSEMBLY)
+.macro AMD_MTRR_MSRS_TABLE_ENTRIES_ASM
+	/* Variable IORR MTRR MSRs */
+	.long	0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
+	/* Top of memory MTRR MSRs */
+	.long	0xC001001A, 0xC001001D
+.endm /* AMD_MTRR_MSRS_TABLE_ENTRIES_ASM */
+#endif /* defined(ASSEMBLY) */
+
 #if !defined(__PRE_RAM__) && !defined(ASSEMBLY)
 void amd_setup_mtrrs(void);
 #endif
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index e79c90e..ba3ab08 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -34,6 +34,37 @@
 #define MTRRfix4K_F0000_MSR 0x26e
 #define MTRRfix4K_F8000_MSR 0x26f
 
+#if defined (ASSEMBLY)
+.macro X86_MTRR_MSRS_TABLE_ENTRIES_ASM
+	/* fixed mtrr MSRs */
+	.long	MTRRfix64K_00000_MSR
+	.long	MTRRfix16K_80000_MSR
+	.long	MTRRfix16K_A0000_MSR
+	.long	MTRRfix4K_C0000_MSR
+	.long	MTRRfix4K_C8000_MSR
+	.long	MTRRfix4K_D0000_MSR
+	.long	MTRRfix4K_D8000_MSR
+	.long	MTRRfix4K_E0000_MSR
+	.long	MTRRfix4K_E8000_MSR
+	.long	MTRRfix4K_F0000_MSR
+	.long	MTRRfix4K_F8000_MSR
+
+	/* var mtrr MSRs */
+	.long	MTRRphysBase_MSR(0), MTRRphysBase_MSR(1)
+	.long	MTRRphysBase_MSR(2), MTRRphysBase_MSR(3)
+	.long	MTRRphysBase_MSR(4), MTRRphysBase_MSR(5)
+	.long	MTRRphysBase_MSR(6), MTRRphysBase_MSR(7)
+	.long	MTRRphysBase_MSR(8), MTRRphysBase_MSR(9)
+	.long	MTRRphysBase_MSR(10), MTRRphysBase_MSR(11)
+	.long	MTRRphysBase_MSR(12), MTRRphysBase_MSR(13)
+	.long	MTRRphysBase_MSR(14), MTRRphysBase_MSR(15)
+.endm /* X86_MTRR_MSRS_TABLE_ENTRIES_ASM */
+
+.macro END_MTRR_MSRS_TABLE_ENTRY_ASM
+	.long	0x000 /* NULL, end of table */
+.endm /* END_MTRR_MSRS_TABLE_ASM */
+#endif /* defined (ASSEMBLY) */
+
 #if !defined (ASSEMBLY) && !defined(__PRE_RAM__)
 #include <device/device.h>
 void enable_fixed_mtrr(void);
-- 
1.7.1





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