[coreboot] [commit] r5922 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3
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svn at coreboot.org
Fri Oct 8 05:35:12 CEST 2010
Author: zbao
Date: Fri Oct 8 05:35:12 2010
New Revision: 5922
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5922
Log:
Trivial. Fix the typo.
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Zheng Bao <zheng.bao at amd.com>
Modified:
trunk/src/northbridge/amd/amdmct/mct/mctsrc.c
trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mctsrc.c Fri Oct 8 01:42:17 2010 (r5921)
+++ trunk/src/northbridge/amd/amdmct/mct/mctsrc.c Fri Oct 8 05:35:12 2010 (r5922)
@@ -848,7 +848,7 @@
struct DCTStatStruc *pDCTstat)
{
/* Initialize the DQS Positions in preparation for
- * Reciever Enable Training.
+ * Receiver Enable Training.
* Write Position is 1/2 Memclock Delay
* Read Position is 1/2 Memclock Delay
*/
@@ -863,7 +863,7 @@
struct DCTStatStruc *pDCTstat, u8 Channel)
{
/* Initialize the DQS Positions in preparation for
- * Reciever Enable Training.
+ * Receiver Enable Training.
* Write Position is no Delay
* Read Position is 1/2 Memclock Delay
*/
Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Fri Oct 8 01:42:17 2010 (r5921)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Fri Oct 8 05:35:12 2010 (r5922)
@@ -800,7 +800,7 @@
struct DCTStatStruc *pDCTstat)
{
/* Initialize the DQS Positions in preparation for
- * Reciever Enable Training.
+ * Receiver Enable Training.
* Write Position is 1/2 Memclock Delay
* Read Position is 1/2 Memclock Delay
*/
@@ -814,7 +814,7 @@
struct DCTStatStruc *pDCTstat, u8 Channel)
{
/* Initialize the DQS Positions in preparation for
- * Reciever Enable Training.
+ * Receiver Enable Training.
* Write Position is no Delay
* Read Position is 1/2 Memclock Delay
*/
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