[coreboot] [PATCH] Convert all Intel i810 boards to CAR
uwe at hermann-uwe.de
Wed Oct 13 21:00:00 CEST 2010
patch is committed with Peter's ack in r5949 as it's not really directly
related to this discussion and also boot-tested by me on MSI MS-6178
as mentioned in the patch description.
On Wed, Oct 13, 2010 at 09:50:52AM -0400, Joseph Smith wrote:
> On 10/13/2010 01:24 AM, Warren Turkal wrote:
> >On Tuesday 12 October 2010 19:22:43 Joseph Smith wrote:
> >>FC-PGA's support SSE2 while the PGA's do not. that is the difference. I
> >>created FC_PGA370 to make the CAR coversion simpler. Hope that helps.
> >I must be misunderstanding this entirely.
> >First, you say there is a difference in that the FC version support SSE2. Then,
> >you say that the FC_PGA370 socket is simply a mechanism to make conversion to
> >CAR easier.
Hm, this stuff may need some clarification and/or fixing in coreboot indeed.
As far as I can see, e.g. from
there were 3 different sockets named socket370, all of which were
physically compatible, but not electrically.
I'm not so sure about the naming, but these seem to be the different
packages / form factors of the sockets:
- Plastic pin grid array (PPGA)
- Flip-chip pin grid array (FC-PGA)
- Flip-chip pin grid array (FC-PGA2)
Now, whether or not we need or want different socket_* directories for
these I'm not sure yet, probably needs some investigation.
However, as we're switchting all CPUs/boards to CAR sooner or later,
having an extra dir just for the CAR (vs. ROMCC) version of the socket
will not be required.
As for SSE/SSE2, that seems to be a mess in coreboot too right now.
The socket_PGA370 does "select MMX" and explictly disables SSE2 (and
doesn't select or disable "SSE" explicitly).
The socket_FC_PGA370 does "select MMX" and "select SSE" (but not SSE2!)
There is no default for MMX and SSE in src/cpu/Kconfig, but SSE2
defaults of off there.
This is all a bit inconsistent I think, need to look into it a bit more.
> >Does that mean that FC_PGA370 is simply PGA370 + CAR, or do PGA370 sockets
> >really not support SSE2 chips?
Not sure if the socket is the correct place to "select" either of
MMX/SSE/SSE2 anyway, that's a CPU-property and should probably be
selected in model_* (even if for newer CPUs all of those are always "y").
> >So I guess I would be satisfied if I knew that the minimum size l2 cache for a
> >chip that fits in the PGA370 was 4K since that's what the patch says and since
> >that's really what matters for the DCACHE_RAM_SIZE.
I don't think so. The DCACHE_RAM_SIZE specifies the amount of L1
data-cache to use for CAR as far as I know (not L2 cache). Unless I'm
mistaken, it also doesn't specify the actual size of the L1 cache, just
the size we want to use for CAR (but please someone correct me if I'm wrong).
Actually L2 cache is completely disabled for the 6xx CPUs at the moment, and
intel/car/cache_as_ram.inc doesn't use L2 at all (unless I'm very
mistaken). Other CAR implementations may or may not use L2 though, not sure.
> >Also, are we sure that the DCACHE_RAM_BASE used will work? I.e. has it been
> >tested on real hardware?
Yes, I mentioned that in the patch description, I boot-tested it on
But you're right, the CACHE_BASE variables differ, but I guess they both
work (0xc0000 works, I can test the other later just to make sure). We should
probably use the same base address for all users of intel/car/cache_as_ram.inc
for less confusion.
> I'm sure CAR will work on the PGA's,
> although they may need Keith's L2 patch.
No, don't think it's needed for CAR.
> More or less it was decided a while ago to split the
> model_6xx romcc clump-o-crap out into their own CAR model
> directories (starting with model_68x).
Yep, we'll move out more CPUs from 6xx into their own directories.
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