[coreboot] coreboot support for AMD HT3
Maximilian.Thuermer at ziti.uni-heidelberg.de
Thu Oct 14 15:17:11 CEST 2010
Scott Duplichan wrote:
> > At 1600x1200, 16-bit color is almost perfect. But the same
> > resolution with 32-bit color results in a display that jumps so
> > much it cannot be read. Why would 32-bit color make a difference?
Twice the bandwidth needed to get the graphics data out of RAM.
> > I am thinking that refreshing 1600x1200 pixels 60 times per second
> > takes a lot data, and that data has to cross the HT link. True
> > color takes more data than high color, and true color may be
> > exceeding the capacity of the cpu-RS780 link. The link is running
> > at the slowest possible setting, 200 MHz, 8-bit.
Ouch! :\ That would seem to cause the problem.
Can't say about HT3 I'm afraid.
HT3 is all there and working perfectly as long as it is between two
CPUS or CPU and HTX expansion slot. I noticed frequencies not being set
correctly in HT init for Southbridge links, all other links seem
to run at their optimal speed. Normally, Southbridges support HT1 frequencies
up to HT1000 which should be sufficient for your problem to vanish. Either you try overwriting
the coreboot settings manually on CPU and SB side (HT Specification and BKDG
should help here) or you try to fix the problem at its root which is that the Southbridge
capability registers do not seem to get read out alright by the HT init procedures.
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