[coreboot] [commit] r5952 - trunk/src/arch/i386/lib
repository service
svn at coreboot.org
Fri Oct 15 01:40:11 CEST 2010
Author: uwe
Date: Fri Oct 15 01:40:10 2010
New Revision: 5952
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5952
Log:
Cosmetics in ioapic.c (trivial, no functional changes).
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Modified:
trunk/src/arch/i386/lib/ioapic.c
Modified: trunk/src/arch/i386/lib/ioapic.c
==============================================================================
--- trunk/src/arch/i386/lib/ioapic.c Thu Oct 14 01:00:41 2010 (r5951)
+++ trunk/src/arch/i386/lib/ioapic.c Fri Oct 15 01:40:10 2010 (r5952)
@@ -34,7 +34,6 @@
write32(ioapic_base + 0x10, value);
}
-
void clear_ioapic(u32 ioapic_base)
{
u32 low, high;
@@ -42,8 +41,8 @@
printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
- /* Read the available number of interrupts */
- ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
+ /* Read the available number of interrupts. */
+ ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
if (!ioapic_interrupts || ioapic_interrupts == 0xff)
ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
@@ -55,11 +54,12 @@
io_apic_write(ioapic_base, i * 2 + 0x10, low);
io_apic_write(ioapic_base, i * 2 + 0x11, high);
- printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+ printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
+ i, high, low);
}
if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
- printk(BIOS_WARNING, "IO APIC not responding.\n");
+ printk(BIOS_WARNING, "IOAPIC not responding.\n");
return;
}
}
@@ -70,25 +70,25 @@
u32 low, high;
u32 i, ioapic_interrupts;
- printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base);
- printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n",
- bsp_lapicid);
+ printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
+ ioapic_base);
+ printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
+ bsp_lapicid);
if (ioapic_id) {
printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
- /* Set IOAPIC ID if it has been specified */
+ /* Set IOAPIC ID if it has been specified. */
io_apic_write(ioapic_base, 0x00,
(io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) |
- (ioapic_id << 24));
+ (ioapic_id << 24));
}
- /* Read the available number of interrupts */
- ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
+ /* Read the available number of interrupts. */
+ ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
if (!ioapic_interrupts || ioapic_interrupts == 0xff)
ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
-
// XXX this decision should probably be made elsewhere, and
// it's the C3, not the EPIA this depends on.
#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT
@@ -98,18 +98,20 @@
#endif
#ifdef IOAPIC_INTERRUPTS_ON_FSB
- /* For the Pentium 4 and above APICs deliver their interrupts
+ /*
+ * For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that.
*/
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
- io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0));
+ io_apic_write(ioapic_base, 0x03,
+ io_apic_read(ioapic_base, 0x03) | (1 << 0));
#endif
#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0);
#endif
- /* Enable Virtual Wire Mode */
+ /* Enable Virtual Wire Mode. */
low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
high = bsp_lapicid << (56 - 32);
@@ -117,11 +119,12 @@
io_apic_write(ioapic_base, 0x11, high);
if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
- printk(BIOS_WARNING, "IO APIC not responding.\n");
+ printk(BIOS_WARNING, "IOAPIC not responding.\n");
return;
}
- printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low);
+ printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
+ 0, high, low);
low = DISABLED;
high = NONE;
@@ -130,6 +133,7 @@
io_apic_write(ioapic_base, i * 2 + 0x10, low);
io_apic_write(ioapic_base, i * 2 + 0x11, high);
- printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+ printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
+ i, high, low);
}
}
More information about the coreboot
mailing list