[coreboot] [commit] r5959 - in trunk/src/southbridge/amd: rs690 rs780
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Sun Oct 17 23:59:43 CEST 2010
Author: uwe
Date: Sun Oct 17 23:59:43 2010
New Revision: 5959
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5959
Log:
In the RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set
to zero, so for boards with RS780 not on CPU's HT chain 0, the function will
mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3()
function will hang when it visits the MMIO.
The following patch fixes the problem, and is tested on a K8 board with RS780
on HT chain 1.
Signed-off-by: Liu Tao <liutao1980 at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Modified:
trunk/src/southbridge/amd/rs690/rs690_cmn.c
trunk/src/southbridge/amd/rs780/rs780_cmn.c
Modified: trunk/src/southbridge/amd/rs690/rs690_cmn.c
==============================================================================
--- trunk/src/southbridge/amd/rs690/rs690_cmn.c Sun Oct 17 23:34:45 2010 (r5958)
+++ trunk/src/southbridge/amd/rs690/rs690_cmn.c Sun Oct 17 23:59:43 2010 (r5959)
@@ -202,15 +202,23 @@
{
/* K8 Function1 is address map */
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+ device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
if (in_out) {
+ u32 dword, sblk;
+
+ /* Get SBLink value (HyperTransport I/O Hub Link ID). */
+ dword = pci_read_config32(k8_f0, 0x64);
+ sblk = (dword >> 8) & 0x3;
+
+ /* Fill MMIO limit/base pair. */
pci_write_config32(k8_f1, 0xbc,
(((pcie_base_add + 0x10000000 -
- 1) >> 8) & 0xffffff00) | 0x80);
+ 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
pci_write_config32(k8_f1, 0xb4,
- ((mmio_base_add + 0x10000000 -
- 1) >> 8) & 0xffffff00);
+ (((mmio_base_add + 0x10000000 -
+ 1) >> 8) & 0xffffff00) | (sblk << 4));
pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
} else {
pci_write_config32(k8_f1, 0xb8, 0);
Modified: trunk/src/southbridge/amd/rs780/rs780_cmn.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_cmn.c Sun Oct 17 23:34:45 2010 (r5958)
+++ trunk/src/southbridge/amd/rs780/rs780_cmn.c Sun Oct 17 23:59:43 2010 (r5959)
@@ -200,15 +200,23 @@
{
/* K8 Function1 is address map */
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+ device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
if (in_out) {
+ u32 dword, sblk;
+
+ /* Get SBLink value (HyperTransport I/O Hub Link ID). */
+ dword = pci_read_config32(k8_f0, 0x64);
+ sblk = (dword >> 8) & 0x3;
+
+ /* Fill MMIO limit/base pair. */
pci_write_config32(k8_f1, 0xbc,
(((pcie_base_add + 0x10000000 -
- 1) >> 8) & 0xffffff00) | 0x80);
+ 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
pci_write_config32(k8_f1, 0xb4,
- ((mmio_base_add + 0x10000000 -
- 1) >> 8) & 0xffffff00);
+ (((mmio_base_add + 0x10000000 -
+ 1) >> 8) & 0xffffff00) | (sblk << 4));
pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
} else {
pci_write_config32(k8_f1, 0xb8, 0);
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