[coreboot] [PATCH 6/8] ASUS M2V support: K8T890 PCIe bugfix
Tobias Diedrich
ranma+coreboot at tdiedrich.de
Wed Oct 27 13:44:30 CEST 2010
Need to clear downstream read cycle retry bit, or the bus scan will
hang.
Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
Index: src/southbridge/via/k8t890/k8t890_pcie.c
===================================================================
--- src.orig/southbridge/via/k8t890/k8t890_pcie.c 2010-10-27 11:34:19.000000000 +0200
+++ src/southbridge/via/k8t890/k8t890_pcie.c 2010-10-27 12:45:22.000000000 +0200
@@ -35,6 +41,13 @@
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg | 0x10);
+ /*
+ * Disable downstream read cycle retry,
+ * needed for asus m2v / k8t890cf or bus scan will hang.
+ */
+ reg = pci_read_config8(dev, 0xa3);
+ pci_write_config8(dev, 0xa3, reg & ~0x01);
+
/* Award has 0xb, VIA recomends 0x4. */
pci_write_config8(dev, 0xe1, 0xb);
@@ -75,6 +88,13 @@
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg | 0x10);
+ /*
+ * Disable downstream read cycle retry,
+ * needed for asus m2v / k8t890cf or bus scan will hang.
+ */
+ reg = pci_read_config8(dev, 0xa3);
+ pci_write_config8(dev, 0xa3, reg & ~0x01);
+
/* Award has 0xb, VIA recommends 0x4. */
pci_write_config8(dev, 0xe1, 0xb);
/* Set replay timer limit. */
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