[coreboot] [PATCH] fix 'AMD Fam10 code breaks with gcc 4.5.0'

Scott scott at notabs.org
Thu Sep 2 07:40:50 CEST 2010


The subversion comment for -r 5571 states:

   The AMD Fam10 code breaks with coreboot 4.5.0.
   Potentially caused by reordering. Going back to 4.4.4
   which is known working on Fam10 until gcc or the Fam10 code is fixed.

   Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
   Acked-by: Stefan Reinauer <stepan at coresystems.de>

I encountered the same problem and debugged it. The AP code that disables
cache as ram before the final halt has to be all inline. Function calls
require a valid stack, and the stack is kept in the very cache as ram that
the code is disabling. I found with gcc 450, the code for rdmsr, disable_cache,
and enable_cache and not getting inlined as intended. Function calls are
generated, and the first one after the AP clears msr 268 fails. The solution
is to force these functions to generate inline code by adding
__attribute__((always_inline)) to their declarations:

Index: src/include/cpu/x86/msr.h
--- src/include/cpu/x86/msr.h	(revision 5763)
+++ src/include/cpu/x86/msr.h	(working copy)
@@ -29,7 +29,7 @@
         msr_t msr;
 } msrinit_t;
-static inline msr_t rdmsr(unsigned index)
+static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
 	msr_t result;
 	__asm__ __volatile__ (
@@ -40,7 +40,7 @@
 	return result;
-static inline void wrmsr(unsigned index, msr_t msr)
+static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr)
 	__asm__ __volatile__ (
Index: src/include/cpu/x86/cache.h
--- src/include/cpu/x86/cache.h	(revision 5763)
+++ src/include/cpu/x86/cache.h	(working copy)
@@ -74,7 +74,7 @@
 	asm volatile("invd" ::: "memory");
-static inline void enable_cache(void)
+static inline __attribute__((always_inline)) void enable_cache(void)
 	unsigned long cr0;
 	cr0 = read_cr0();
@@ -82,7 +82,7 @@
-static inline void disable_cache(void)
+static inline __attribute__((always_inline)) void disable_cache(void)
 	/* Disable and write back the cache */
 	unsigned long cr0;


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