[coreboot] [commit] r5767 - trunk/src/mainboard/intel/mtarvon
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svn at coreboot.org
Fri Sep 3 00:02:54 CEST 2010
Author: myles
Date: Fri Sep 3 00:02:53 2010
New Revision: 5767
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5767
Log:
Fix compilation for mtarvon. CAR initialization does early_mtrr_init,
jarell/debug.c isn't ready for gcc, and skip_romstage() doesn't compile.
Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>
Modified:
trunk/src/mainboard/intel/mtarvon/romstage.c
Modified: trunk/src/mainboard/intel/mtarvon/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/mtarvon/romstage.c Thu Sep 2 22:30:31 2010 (r5766)
+++ trunk/src/mainboard/intel/mtarvon/romstage.c Fri Sep 3 00:02:53 2010 (r5767)
@@ -33,7 +33,6 @@
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "northbridge/intel/i3100/raminit.h"
#include "superio/intel/i3100/i3100.h"
-#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/intel/i3100/i3100_early_serial.c"
#include "northbridge/intel/i3100/memory_initialized.c"
@@ -52,10 +51,11 @@
#include "northbridge/intel/i3100/raminit.c"
#include "lib/generic_sdram.c"
-#include "../jarrell/debug.c"
+#if 0 /* skip_romstage doesn't compile with gcc */
#include "arch/i386/lib/stages.c"
+#endif
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
msr_t msr;
u16 perf;
@@ -72,11 +72,12 @@
};
if (bist == 0) {
+#if 0 /* skip_romstage doesn't compile with gcc */
/* Skip this if there was a built in self test failure */
- early_mtrr_init();
if (memory_initialized()) {
skip_romstage();
}
+#endif
}
/* Set up the console */
i3100_enable_superio();
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