[coreboot] [commit] r5776 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3

[repository service]

Author: oxygene
Date: Sat Sep  4 08:13:02 2010
New Revision: 5776
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5776

Log:
AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.

Signed-off-by: Kerry She <Kerry.she at amd.com>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>

Modified:
   trunk/src/northbridge/amd/amdmct/mct/mct_d.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c

Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mct_d.c	Fri Sep  3 17:16:36 2010	(r5775)
+++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c	Sat Sep  4 08:13:02 2010	(r5776)
@@ -3461,9 +3461,10 @@
 		i = 0; /* use i for the dct setting required */
 		if (pDCTstat->MAdimms[0] < 4)
 			i = 1;
-		if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4))
+		if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) {
 			dword &= 0xF18FFF18;
 			index_reg = 0x98;	/* force dct = 0 */
+		}
 	}
 
 	Set_NB32_index_wait(dev, index_reg, 0x0a, dword);

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c	Fri Sep  3 17:16:36 2010	(r5775)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c	Sat Sep  4 08:13:02 2010	(r5776)
@@ -3127,9 +3127,10 @@
 		i = 0; /* use i for the dct setting required */
 		if (pDCTstat->MAdimms[0] < 4)
 			i = 1;
-		if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4))
+		if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) {
 			dword &= 0xF18FFF18;
 			index_reg = 0x98;	/* force dct = 0 */
+		}
 	}
 
 	Set_NB32_index_wait(dev, index_reg, 0x0a, dword);