[coreboot] AMD cache setup is broken
Arne Georg Gleditsch
arne.gleditsch at numascale.com
Tue Sep 7 09:47:12 CEST 2010
"Scott Duplichan" <scott at notabs.org> writes:
> One necessary condition for caching MMIO such as the flash chip on
> AMD family 10h processors is not well known:
> If the processor has an L3 cache, then bit 15 of msr C001_102A
> (ClLinesToNbDis) must be set. This bit needs to eventually be cleared
> in order for the OS to use the L3 cache. But BIOS must not clear this
> bit until cacheable accesses to the flash chip are no longer needed.
> This situation applies only to family 10h processors that have L3 cache.
> Often BIOS clears this bit too early and slow execution results.As an
> experiment, you could add code to set this bit before the slow function
> and see what happens.
This is certainly interesting information. I'd like to test this out on
real hardware, but I'm afraid I can't promise it'll be in the immediate
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