[coreboot] AMD cache setup is broken
scott at notabs.org
Thu Sep 9 17:02:58 CEST 2010
]From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Arne Georg Gleditsch
]Sent: Thursday, September 09, 2010 04:58 AM
]To: Scott Duplichan
]Cc: 'Marc Jones'; coreboot at coreboot.org
]Subject: Re: [coreboot] AMD cache setup is broken
]Arne Georg Gleditsch <arne.gleditsch at numascale.com> writes:
]> + /* Clear ClLinesToNbDis */
]> + msr = rdmsr(BU_CFG2_MSR);
]> + msr.lo &= ~(1 << 15);
]> + wrmsr(BU_CFG2_MSR, msr);
]On an slightly unrelated note; do we want to clear bit 35 here as well?
]At the moment, this is only done for the BSP, causing the MSR settings
]to be inconsistent after boot. I see that errata 343 indicates that
]this should be cleared after CAR is disabled, so it might not matter all
]that much for the APs...
I think it would be best to clear bit 35 of msr c001_102a in the AP
cores as well as the BSP core. Otherwise, the OS might see AP cores
having slightly lower performance than the BSP core. This bit affects
family 10h revC and newer (45 nm).
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