[coreboot] AMD cache setup is broken
Arne Georg Gleditsch
arne.gleditsch at numascale.com
Mon Sep 13 10:51:08 CEST 2010
"Scott Duplichan" <scott at notabs.org> writes:
> I think it would be best to clear bit 35 of msr c001_102a in the AP
> cores as well as the BSP core. Otherwise, the OS might see AP cores
> having slightly lower performance than the BSP core. This bit affects
> family 10h revC and newer (45 nm).
Ok, so here's a patch adding this. Clearing bit 35 is done
unconditionally for all fam10 cpus, is that ok? Setting is done based
on processor type in defaults.h, as before.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch at numascale.com>
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