[coreboot] [PATCH] Add support for Asus M4A785-M, with build instructions

Juhana Helovuo juhe at iki.fi
Thu Sep 16 20:42:04 CEST 2010

On Mon, 2010-09-13 at 14:31 -0600, Myles Watson wrote:
> On Mon, Sep 13, 2010 at 1:35 PM, Arne Georg Gleditsch
> <arne.gleditsch at numascale.com> wrote:
> > Myles Watson <mylesgw at gmail.com> writes:
> >> So even though there are PCI resources located at 0xc0000000, RAM gets
> >> used for UMA at 0xd0000000 and tables get placed at 0xcfff0000.
> >
> > PCI resources at 0xd0000000?  Doesn't this conflict with the setting of
> > NV_BottomIO in src/northbridge/amd/amdmct/wrappers/mcti_d.c?
> That could be.  I'm totally ignorant of the fam10 code oustside of
> northbridge/amd/amdfam10.
> Looking at the boot log, it doesn't seem unreasonable to have PCI
> resources from starting at 0xc0000000.
> It seems like we have a couple of options:
> 1. Reclaim the area used for MMCONF on this board
> 2. Move NV_BottomIO
> Probably 2 is the best.  It's too bad to have that hard coded.


How to proceed with finding the proper memory setup? I tried reading
through amdfam10 code and RS780 southbridge code, but they are quite
incomprehensible without a hardware programming manual. Is such a
detailed documentation freely available somewhere, or is it under NDA

It appears that the northbridge is quite clever in mapping memory, since
Linux booted with Asus BIOS reports in /proc/iomem that there is usable
RAM up to 0x19fffffff, i.e. addresses up to 6.5 GB, even though there is
only 6 GB RAM installed.

The "extra" addresses apparently come from the fact that there is no
real RAM mapped to some addresses below 4G, and these addresses are used
for PCI memory-mapped IO.

Here are some parts of /proc/iomem:

00100000-cff8ffff : System RAM
d0000000-dfffffff : PCI Bus 0000:01
  d0000000-dfffffff : 0000:01:05.0
e0000000-efffffff : PCI MMCONFIG 0 [00-ff]
  e0000000-efffffff : pnp 00:0d
fdf00000-fdffffff : PCI Bus 0000:02
fe900000-feafffff : PCI Bus 0000:01
feb00000-febfffff : PCI Bus 0000:02
100000000-19fffffff : System RAM

My interpretation of this is roughly the following:

 00000000-cfffffff is 3.25 GB RAM.
 d0000000-dfffffff is not RAM, but is 256M memory-mapped IO addresses to VGA
 e0000000-efffffff is 256M RAM, but not usable to OS, because it is the UMA
 f0000000-ffffffff is not RAM, but IO addresses for more PCI, APICs, and other devices
100000000-19fffffff is 2.5 GB RAM

Does this look correct? If yes, then the northbridge is creating holes
into RAM, in order to have PCI memory-mapped IO in 32-bit addresses.

Now, if I wish to have Coreboot to cope with large memory and holes,
what manuals do I need to understand and modify the codes managing this?

Best regards,
Juhana Helovuo

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