[coreboot] [PATCH] [RFC] sata PHY settings callback on SB700

[Bao, Zheng]

The following words are got from SB700 rpr. It seems that the phy
settings have something to do with the eSATA.

SATA_PCI_config
0x01B48017
SATA_PCI_config
0x01B48019
SATA_PCI_config
0x01B48016
SATA_PCI_config
0x01B48016
SATA_PCI_config
0x01B48016
SATA_PCI_config
0x01B48016

SATA GENI PHY ports setting, Pre-emphasis setting, and
GENII PHY setting enable setup for port [0~5] This setting
is for the Travelly board. Since it's port0 and port1are
eSATA ports, the PCI_config 0x88 and 0x8C have different
settings than the rest of the ports. For non-esata port, the
setting should be 0x01B48016. For shinner board,
SATA_PCI_config 0x88/8C/90/94/98/9C [31:0] =
0x01B48016.

SATA_PCI_config 0xA0 [15:0] = 0xA09A
SATA_PCI_config 0xA2 [15:0] = 0xA09F
SATA_PCI_config 0xA4 [15:0] = 0xA07A
SATA_PCI_config 0xA6 [15:0] = 0xA07A
SATA_PCI_config 0xA8 [15:0] = 0xA07A
SATA_PCI_config 0xAA [15:0] = 0xA07A
SATA GEN II PHY port setting for port [0~5]. This setting is
for the Travelly board. Since it's port0 and port1 are
eSATA ports, the PCI_config 0xA0 and 0xA2 have different
settings than the rest of the ports. For non-esata port, the
setting should be 0xA07A. For shinner board,
SATA_PCI_config 0xA0/A2/A4/A6/A8/AA [15:0] = 0xA07A.

I am not quite familiar with the attribute weak. It seems to be a good
way.

Zheng


> -----Original Message-----
> From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Rudolf Marek
> Sent: Friday, September 17, 2010 10:49 PM
> To: Coreboot
> Subject: [coreboot] [PATCH] [RFC] sata PHY settings callback on SB700
> 
> Hi from Fort Worth,
> 
> Here is a proposed way how to handle the SATA PHY settings on SB700.
It
> consists
> of weak function which always exists (with defaults) and a possibility
to
> override this with normal function in main.c. This is the other way of
> doing
> that and not using the devictree.cb.
> 
> Please tell if it is ok this way. I suggest all people who ported
SB700
> should
> have a look on their SATA PHY settings too because it is most  likely
> PCB/MB
> dependent.
> 
> This patch is not tested but it could work.
> 
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
> 
> My holiday ends soonish but I temped to do bit of stuff during El Paso
-
> Forth
> Worth ride ;)
> 
> Thanks,
> Rudolf