From hamo.by at gmail.com Fri Apr 1 02:15:49 2011 From: hamo.by at gmail.com (Hamo) Date: Fri, 1 Apr 2011 08:15:49 +0800 Subject: [coreboot] [PATCH] Add build instructions for coreinfo in readme In-Reply-To: References: Message-ID: Can someone comment on this? On 3/30/11, Hamo wrote: > Add build instructions for coreinfo, specially pointing out installing > gcc-multilib on a 64bit system. > > Signed-off-by: Yang Hamo Bai > > This is the very first time I send a patch to coreboot, any comment is > welcome. Thanks. > -- Sent from my mobile device """ Keep It Simple,Stupid. """ Chinese Name: ?? Nick Name: Hamo Homepage: http://hamobai.com/ GPG KEY ID: 0xA4691A33 Key fingerprint = 09D5 2D78 8E2B 0995 CF8E 4331 33C4 3D24 A469 1A33 From svn at coreboot.org Fri Apr 1 02:39:07 2011 From: svn at coreboot.org (repository service) Date: Fri, 01 Apr 2011 02:39:07 +0200 Subject: [coreboot] [commit] r6470 - trunk/payloads/coreinfo Message-ID: Author: stepan Date: Fri Apr 1 02:39:07 2011 New Revision: 6470 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6470 Log: Add build instructions for coreinfo, specially pointing out installing gcc-multilib on a 64bit system. Signed-off-by: Yang Hamo Bai Acked-by: Stefan Reinauer Modified: trunk/payloads/coreinfo/README Modified: trunk/payloads/coreinfo/README ============================================================================== --- trunk/payloads/coreinfo/README Tue Mar 29 21:29:01 2011 (r6469) +++ trunk/payloads/coreinfo/README Fri Apr 1 02:39:07 2011 (r6470) @@ -1,3 +1,27 @@ This is a silly little program that demonstrates how cool libpayload is and also serves a purpose. Its fun and educational! +Requirements +------------ + +You should use the coreboot reference cross compiler. If you insist on using +your system compiler, some Linux distributions might require you to install +a package called gcc-multilib if you are on a 64bit system. + +Build +----- + +You need libpayload to build coreinfo. So, first, you need follow the README of +libpayload to build it but install libpayload into its own directory by doing +this: + + $ make DESTDIR=/path/to/libpayload/install install + +Then you can build coreinfo now: + + $ cd coreinfo + + $ make menuconfig + + $ make + From stefan.reinauer at coreboot.org Fri Apr 1 02:39:51 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Fri, 1 Apr 2011 02:39:51 +0200 Subject: [coreboot] [PATCH] Add build instructions for coreinfo in readme In-Reply-To: References: Message-ID: <20110401003951.GA9626@coreboot.org> * Hamo [110330 02:19]: > Add build instructions for coreinfo, specially pointing out installing > gcc-multilib on a 64bit system. > > Signed-off-by: Yang Hamo Bai > > This is the very first time I send a patch to coreboot, any comment is > welcome. Thanks. Thank you Hamo. Committed as r6470 with a slight change. From nathan at traverse.com.au Fri Apr 1 04:43:58 2011 From: nathan at traverse.com.au (Nathan Williams) Date: Fri, 01 Apr 2011 13:43:58 +1100 Subject: [coreboot] [PATCH] FILO: Kconfig option for forcing NAND flash mode Message-ID: <1301625838.25651.13.camel@dualcore.traverse> This patch adds support for enabling NAND flash even if it hasn't been set up by coreboot. Since DIVIL_LBAR_FLSH[x], NANDF_DATA and NANDF_CTL are likely to be incorrect, they can be specified in Kconfig as well. Signed-off-by: Nathan Williams Index: Config.in =================================================================== --- Config.in (revision 143) +++ Config.in (working copy) @@ -141,6 +141,46 @@ help Driver for Geode NAND flash storage +config FORCE_NAND_FLASH + bool "Enable NAND flash automatically" + default n + depends on FLASH_DISK + help + If Geode is currently set to IDE mode, change + to NAND flash mode. + +config DIVIL_LBAR_FLSH_HI + hex "LBAR_FLSH[x] (hi)" + default "0xfffff007" + depends on FORCE_NAND_FLASH + help + Local BAR Flash Chip Select. See AMD Geode CS5536 Companion + Device Data Book section 6.6.2.8 for details. + +config DIVIL_LBAR_FLSH_LO + hex "LBAR_FLSH[x] (lo)" + default "0x20000000" + depends on FORCE_NAND_FLASH + help + Local BAR Flash Chip Select. See AMD Geode CS5536 Companion + Device Data Book section 6.6.2.8 for details. + +config NANDF_DATA + hex "Initial NANDF_DATA" + default "0x00100010" + depends on FORCE_NAND_FLASH + help + Specify NAND Flash Data Timing MSR value. See AMD Geode + CS5536 Companion Device Data Book section 6.19.1.3 for details. + +config NANDF_CTL + hex "Initial NANDF_CTL" + default "0x00000010" + depends on FORCE_NAND_FLASH + help + Specify NAND Flash Control Timing MSR value. See AMD Geode + CS5536 Companion Device Data Book section 6.19.1.4 for details. + config SUPPORT_PCI bool "PCI support" default y Index: drivers/flash/lxflash.c =================================================================== --- drivers/flash/lxflash.c (revision 143) +++ drivers/flash/lxflash.c (working copy) @@ -523,8 +523,21 @@ int NAND_close(void) { - if (g_chipID >= 0) + if (g_chipID >= 0) { wrmsr(MSR_DIVIL_LBAR_FLSH0 + g_chipID, g_orig_flsh); +#ifdef CONFIG_FORCE_NAND_FLASH + // Set up NAND data and control timing for OS + msr_t tmp; + + tmp = rdmsr(MSR_NANDF_DATA); + tmp.lo = CONFIG_NANDF_DATA; + wrmsr(MSR_NANDF_DATA, tmp); + + tmp = rdmsr(MSR_NANDF_CTL); + tmp.lo = CONFIG_NANDF_CTL; + wrmsr(MSR_NANDF_CTL, tmp); +#endif + } } //////////////////////////////////////////////////////////////////////////////// @@ -547,19 +560,31 @@ msr = rdmsr(MSR_DIVIL_BALL_OPTS); if (msr.lo & PIN_OPT_IDE) { +#ifndef CONFIG_FORCE_NAND_FLASH printf("NAND controller not enabled!\n"); return -1; +#else + printf("Enabling NAND controller\n"); + msr.lo &= ~PIN_OPT_IDE; + wrmsr(MSR_DIVIL_BALL_OPTS, msr); +#endif } /////////////////////////////////////////////////////////////////////////////////// // init the MSR_DIVIL_LBAR_FLSHx register, I/O mapped mode, set a hardcoded base address // Later we restore initial state +#ifdef CONFIG_FORCE_NAND_FLASH + // When we NAND_close() restore to these values instead + g_orig_flsh.hi = CONFIG_DIVIL_LBAR_FLSH_HI; + g_orig_flsh.lo = CONFIG_DIVIL_LBAR_FLSH_LO; +#else g_orig_flsh = rdmsr(MSR_DIVIL_LBAR_FLSH0 + chipNum); if (!(g_orig_flsh.hi & NOR_NAND)) { printf("CS%d set up for NOR, aborting!\n", chipNum); return -1; } +#endif msr.hi = SET_FLSH_HIGH; msr.lo = SET_FLSH_LOW; From nathan at traverse.com.au Fri Apr 1 07:11:28 2011 From: nathan at traverse.com.au (Nathan Williams) Date: Fri, 01 Apr 2011 16:11:28 +1100 Subject: [coreboot] [PATCH] FILO: Add fallback autoboot option Message-ID: <1301634688.25651.24.camel@dualcore.traverse> This patch adds a fallback command line in case the autoboot command line fails. This could be used on an AMD Geode board to try booting a kernel off IDE, before falling back to NAND flash. Signed-off-by: Nathan Williams Index: main/filo.c =================================================================== --- main/filo.c (revision 143) +++ main/filo.c (working copy) @@ -37,11 +37,11 @@ #define ESCAPE '\x1b' #if !defined(CONFIG_AUTOBOOT_FILE) -#define autoboot() ((void) 0) /* nop */ +#define autoboot() ((int) 0) /* nop */ #endif #ifndef CONFIG_AUTOBOOT_DELAY -#define autoboot_delay() 0 /* success */ +#define autoboot_delay(boot_type) 0 /* success */ #endif struct sys_info sys_info; @@ -156,7 +156,7 @@ #ifdef CONFIG_AUTOBOOT_FILE #ifdef CONFIG_AUTOBOOT_DELAY -static inline int autoboot_delay(void) +static inline int autoboot_delay(const char *boot_type) { u64 timeout; int sec, tmp; @@ -164,7 +164,7 @@ key = 0; - printf("Press for default boot, or for boot prompt... "); + printf("Press for %s boot, or for boot prompt... ", boot_type); for (sec = CONFIG_AUTOBOOT_DELAY; sec>0 && key==0; sec--) { printf("%d", sec); timeout = currticks() + TICKS_PER_SEC; @@ -191,17 +191,33 @@ } #endif /* CONFIG_AUTOBOOT_DELAY */ -static void autoboot(void) +static int autoboot(void) { /* If Escape key is pressed already, skip autoboot */ if (havechar() && getchar()==ESCAPE) - return; + return 0; - if (autoboot_delay()==0) { + if (autoboot_delay("default")==0) { printf("boot: %s\n", CONFIG_AUTOBOOT_FILE); boot(CONFIG_AUTOBOOT_FILE); + return 1; } + return 0; } + +#ifdef CONFIG_FALLBACKBOOT_FILE +static void fallbackboot(void) +{ + /* If Escape key is pressed already, skip autoboot */ + if (havechar() && getchar()==ESCAPE) + return; + + if (autoboot_delay("fallback")==0) { + printf("boot: %s\n", CONFIG_FALLBACKBOOT_FILE); + boot(CONFIG_FALLBACKBOOT_FILE); + } +} +#endif /* FALLBACKBOOT_FILE */ #endif /* AUTOBOOT_FILE */ /* The main routine */ @@ -213,17 +229,30 @@ init(); /* Try default image */ - autoboot(); + if (autoboot()) { + /* Default boot has failed */ +#ifdef CONFIG_AUTOBOOT_FILE +#ifdef CONFIG_FALLBACKBOOT_FILE + fallbackboot(); + strncpy(line, CONFIG_FALLBACKBOOT_FILE, sizeof(line)-1); +#else + strncpy(line, CONFIG_AUTOBOOT_FILE, sizeof(line)-1); +#endif +#endif + line[sizeof(line)-1] = '\0'; + } else { + /* Either CONFIG_AUTOBOOT_FILE not defined, or delay escaped by user */ +#ifdef CONFIG_AUTOBOOT_FILE + strncpy(line, CONFIG_AUTOBOOT_FILE, sizeof(line)-1); + line[sizeof(line)-1] = '\0'; +#else + line[0] = '\0'; +#endif + } /* The above didn't work, ask user */ while (havechar()) getchar(); -#ifdef CONFIG_AUTOBOOT_FILE - strncpy(line, CONFIG_AUTOBOOT_FILE, sizeof(line)-1); - line[sizeof(line)-1] = '\0'; -#else - line[0] = '\0'; -#endif for (;;) { printf("boot: "); getline(line, sizeof line); Index: Config.in =================================================================== --- Config.in (revision 143) +++ Config.in (working copy) @@ -75,6 +75,23 @@ help Time in second before booting AUTOBOOT_FILE +config USE_FALLBACKBOOT + bool "Use a fallback command line" + default n + depends on USE_AUTOBOOT + help + If autoboot fails, try a fallback command line. + +config FALLBACKBOOT_FILE + string "Fallback kernel filename and parameters" + default "" + depends on USE_FALLBACKBOOT + help + #FALLBACKBOOT_FILE = "mem at 0xfff80000" + #FALLBACKBOOT_FILE = "hde1 at 0" + #FALLBACKBOOT_FILE = "uda1:/vmlinuz.elf" + #FALLBACKBOOT_FILE = "flashb at 0x00400000,0x154a00 console=tty0 console=ttyS0,115200" + config ISOLINUX_PARSER bool "Support for parsing isolinux.cfg config files" default n From svn at coreboot.org Fri Apr 1 09:28:35 2011 From: svn at coreboot.org (repository service) Date: Fri, 01 Apr 2011 09:28:35 +0200 Subject: [coreboot] [commit] r6471 - in trunk/src: mainboard/getac/p470/acpi southbridge/intel/i82801gx/acpi Message-ID: Author: svens Date: Fri Apr 1 09:28:35 2011 New Revision: 6471 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6471 Log: ICH7: Fix register naming error There's an off-by-one error in the ACPI GP_LVL declaration: it declares GL00 with a bit count of 6, and continues with GP07 afterwards. This should be GP06, as the first bitfield covers GP00-GP05. While at it, change it to GP00-GP05, as right now GL00 isn't used, and single bitfield are more usable here. Also adjust the Getac P470, as this is the only user of those defintions right now. Signed-off-by: Sven Schnelle Acked-by: Stefan Reinauer Modified: trunk/src/mainboard/getac/p470/acpi/ec.asl trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl Modified: trunk/src/mainboard/getac/p470/acpi/ec.asl ============================================================================== --- trunk/src/mainboard/getac/p470/acpi/ec.asl Fri Apr 1 02:39:07 2011 (r6470) +++ trunk/src/mainboard/getac/p470/acpi/ec.asl Fri Apr 1 09:28:35 2011 (r6471) @@ -491,16 +491,16 @@ If(And(RFDV, 0x08)) { Or(Local0, 0x08, Local0) } - If(And(GP16, 0x01)) { // GDIS + If(And(GP15, 0x01)) { // GDIS Or(Local0, 0x10, Local0) } - If(And(GP13, 0x01)) { // WIFI Led (WLED) + If(And(GP12, 0x01)) { // WIFI Led (WLED) Or(Local0, 0x20, Local0) } If(And(BTEN, 0x01)) { // BlueTooth Enable Or(Local0, 0x40, Local0) } - If(And(GP11, 0x01)) { // GPS Enable + If(And(GP10, 0x01)) { // GPS Enable Or(Local0, 0x80, Local0) } @@ -511,28 +511,28 @@ Method(SRFD, 1, Serialized) { If (And(Arg0, 0x01)) { - Store (1, GP15) // GLED - Store (1, GP16) // GDIS + Store (1, GP14) // GLED + Store (1, GP15) // GDIS } Else { + Store (0, GP14) Store (0, GP15) - Store (0, GP16) } /* WIFI */ If (And(Arg0, 0x02)) { - Store (1, GP13) // WLED - Store (1, GP26) // WLAN + Store (1, GP12) // WLED + Store (1, GP25) // WLAN } Else { - Store (0, GP13) - Store (0, GP26) + Store (0, GP12) + Store (0, GP25) } /* Bluetooth */ If (And(Arg0, 0x04)) { - Store (1, GP14) // BLED + Store (1, GP13) // BLED Store (1, BTEN) } Else { - Store (0, GP14) // BLED + Store (0, GP13) // BLED Store (0, BTEN) } Return (0) @@ -577,7 +577,7 @@ /* ??? */ Method(GTSD, 0, Serialized) { - Return (GP20) // TSDT + Return (GP19) // TSDT } /* Not even decent function names anymore? */ Modified: trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl ============================================================================== --- trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl Fri Apr 1 02:39:07 2011 (r6470) +++ trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl Fri Apr 1 09:28:35 2011 (r6471) @@ -59,29 +59,35 @@ GIO2, 8, GIO3, 8, Offset(0x0c), // GPIO Level - GL00, 6, - GP07, 1, // GDET + GP00, 1, + GP01, 1, + GP02, 1, + GP03, 1, + GP04, 1, + GP05, 1, + GP06, 1, // GDET + GP07, 1, GP08, 1, - GP09, 1, - GP10, 1, // HPMU - GP11, 1, // GPSE - GP12, 1, - GP13, 1, // WLED - GP14, 1, // BLED - GP15, 1, // GLED - GP16, 1, // GDIS + GP09, 1, // HPMU + GP10, 1, // GPSE + GP11, 1, + GP12, 1, // WLED + GP13, 1, // BLED + GP14, 1, // GLED + GP15, 1, // GDIS + GP16, 1, GP17, 1, - GP18, 1, - GP19, 1, // SPCI - GP20, 1, // TSDT - GP21, 1, // SCPU + GP18, 1, // SPCI + GP19, 1, // TSDT + GP20, 1, // SCPU + GP21, 1, GP22, 1, - GP23, 1, - GP24, 1, // LANP - GP25, 1, // DKLR - GP26, 1, // WLAN - GP27, 1, // SATA_PWR_EN #0 / SPOF - GP28, 1, // SATA_PWR_EN #1 / SPMU + GP23, 1, // LANP + GP24, 1, // DKLR + GP25, 1, // WLAN + GP26, 1, // SATA_PWR_EN #0 / SPOF + GP27, 1, // SATA_PWR_EN #1 / SPMU + GP28, 1, GP29, 1, GP30, 1, GP31, 1, From svn at coreboot.org Fri Apr 1 09:28:51 2011 From: svn at coreboot.org (repository service) Date: Fri, 01 Apr 2011 09:28:51 +0200 Subject: [coreboot] [commit] r6472 - trunk/src/superio/nsc/pc87392 Message-ID: Author: svens Date: Fri Apr 1 09:28:50 2011 New Revision: 6472 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6472 Log: Add GPIO definitions to PC87392 superio Signed-off-by: Sven Schnelle Acked-by: Peter Stuge Modified: trunk/src/superio/nsc/pc87392/pc87392.h Modified: trunk/src/superio/nsc/pc87392/pc87392.h ============================================================================== --- trunk/src/superio/nsc/pc87392/pc87392.h Fri Apr 1 09:28:35 2011 (r6471) +++ trunk/src/superio/nsc/pc87392/pc87392.h Fri Apr 1 09:28:50 2011 (r6472) @@ -28,4 +28,15 @@ #define PC87392_GPIO 0x07 #define PC87392_WDT 0x0A +#define PC87392_GPIO_PIN_OE 0x01 +#define PC87392_GPIO_PIN_TYPE_PUSH_PULL 0x02 +#define PC87392_GPIO_PIN_PULLUP 0x04 +#define PC87392_GPIO_PIN_LOCK 0x08 +#define PC87392_GPIO_PIN_TRIG_LEVEL 0x10 +#define PC87392_GPIO_PIN_TRIG_LOW 0x20 +#define PC87392_GPIO_PIN_DEBOUNCE 0x40 + +#define PC87392_GPIO_PIN_TRIGGERS_IRQ 0x01 +#define PC87392_GPIO_PIN_TRIGGERS_SMI 0x02 + #endif From svn at coreboot.org Fri Apr 1 09:28:58 2011 From: svn at coreboot.org (repository service) Date: Fri, 01 Apr 2011 09:28:58 +0200 Subject: [coreboot] [commit] r6473 - in trunk/src/mainboard/lenovo/x60: . acpi Message-ID: Author: svens Date: Fri Apr 1 09:28:56 2011 New Revision: 6473 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6473 Log: X60: add dock code for Ultrabase X6 Move the old docking code from romstage.c to dock.c, and use that code both in romstage and SMM code. Signed-off-by: Sven Schnelle Acked-by: Peter Stuge Added: trunk/src/mainboard/lenovo/x60/acpi/.ec.asl.swp trunk/src/mainboard/lenovo/x60/acpi/.gpe.asl.swp trunk/src/mainboard/lenovo/x60/acpi/dock.asl - copied, changed from r6472, trunk/src/mainboard/lenovo/x60/mainboard_smi.c trunk/src/mainboard/lenovo/x60/dock.c trunk/src/mainboard/lenovo/x60/dock.h trunk/src/mainboard/lenovo/x60/smi.h Modified: trunk/src/mainboard/lenovo/x60/Makefile.inc trunk/src/mainboard/lenovo/x60/acpi/ec.asl trunk/src/mainboard/lenovo/x60/acpi/gpe.asl trunk/src/mainboard/lenovo/x60/mainboard_smi.c trunk/src/mainboard/lenovo/x60/romstage.c Modified: trunk/src/mainboard/lenovo/x60/Makefile.inc ============================================================================== --- trunk/src/mainboard/lenovo/x60/Makefile.inc Fri Apr 1 09:28:50 2011 (r6472) +++ trunk/src/mainboard/lenovo/x60/Makefile.inc Fri Apr 1 09:28:56 2011 (r6473) @@ -17,4 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c dock.c +romstage-y += dock.c Added: trunk/src/mainboard/lenovo/x60/acpi/.ec.asl.swp ============================================================================== Files /dev/null 00:00:00 1970 (empty, because file is newly added) and trunk/src/mainboard/lenovo/x60/acpi/.ec.asl.swp Fri Apr 1 09:28:56 2011 (r6473) differ Added: trunk/src/mainboard/lenovo/x60/acpi/.gpe.asl.swp ============================================================================== Files /dev/null 00:00:00 1970 (empty, because file is newly added) and trunk/src/mainboard/lenovo/x60/acpi/.gpe.asl.swp Fri Apr 1 09:28:56 2011 (r6473) differ Copied and modified: trunk/src/mainboard/lenovo/x60/acpi/dock.asl (from r6472, trunk/src/mainboard/lenovo/x60/mainboard_smi.c) ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard_smi.c Fri Apr 1 09:28:50 2011 (r6472, copy source) +++ trunk/src/mainboard/lenovo/x60/acpi/dock.asl Fri Apr 1 09:28:56 2011 (r6473) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (c) 2011 Sven Schnelle * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,35 +19,37 @@ * MA 02110-1301 USA */ -#include -#include -#include -#include -#include "southbridge/intel/i82801gx/nvs.h" +#include "smi.h" -/* The southbridge SMI handler checks whether gnvs has a - * valid pointer before calling the trap handler - */ -extern global_nvs_t *gnvs; - -int mainboard_io_trap_handler(int smif) +OperationRegion (DLPC, SystemIO, 0x164c, 1) +Field(DLPC, ByteAcc, NoLock, Preserve) +{ + , 3, + DSTA, 1, +} +Device(DOCK) { - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - //gnvs->smif = 0; - break; - default: - return 0; + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + Sleep(250) + /* connect dock */ + TRAP(SMI_DOCK_CONNECT) + } else { + /* disconnect dock */ + TRAP(SMI_DOCK_DISCONNECT) + } + + Xor(Arg0, DSTA, Local0) + Return (Local0) } - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - //gnvs->smif = 0; - return 1; + Method(_STA, 0, NotSerialized) + { + Return (DSTA) + } } - Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/ec.asl Fri Apr 1 09:28:50 2011 (r6472) +++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl Fri Apr 1 09:28:56 2011 (r6473) @@ -19,6 +19,7 @@ * MA 02110-1301 USA */ +#include "smi.h" Device(EC) { Name (_HID, EISAID("PNP0C09")) @@ -83,6 +84,11 @@ \DSPC.BRTD() } + Method(_Q18, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) + } + /* AC status change: present */ Method(_Q26, 0, NotSerialized) { @@ -111,4 +117,5 @@ #include "sleepbutton.asl" #include "lid.asl" #include "beep.asl" +#include "dock.asl" } Modified: trunk/src/mainboard/lenovo/x60/acpi/gpe.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/gpe.asl Fri Apr 1 09:28:50 2011 (r6472) +++ trunk/src/mainboard/lenovo/x60/acpi/gpe.asl Fri Apr 1 09:28:56 2011 (r6473) @@ -1,3 +1,4 @@ +#include "smi.h" Scope (\_GPE) { Method(_L18, 0, NotSerialized) @@ -5,4 +6,16 @@ /* Read EC register to clear wake status */ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) } + + /* SLICE_ON_3M GPE (Dock status) */ + Method(_L1D, 0, NotSerialized) + { + if (GP13) { + Or(GIV1, 0x20, GIV1) + Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) + } else { + And(GIV1, 0xdf, GIV1) + Notify(\_SB.PCI0.LPCB.EC.DOCK, 0) + } + } } Added: trunk/src/mainboard/lenovo/x60/dock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/dock.c Fri Apr 1 09:28:56 2011 (r6473) @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "dock.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include "superio/nsc/pc87392/pc87392.h" + +static void dlpc_write_register(int reg, int value) +{ + outb(reg, 0x164e); + outb(value, 0x164f); +} + +static u8 dlpc_read_register(int reg) +{ + outb(reg, 0x164e); + return inb(0x164f); +} + +static void dock_write_register(int reg, int value) +{ + outb(reg, 0x2e); + outb(value, 0x2f); +} + +static u8 dock_read_register(int reg) +{ + outb(reg, 0x2e); + return inb(0x2f); +} + +static void dlpc_gpio_set_mode(int port, int mode) +{ + dlpc_write_register(0xf0, port); + dlpc_write_register(0xf1, mode); +} + +static void dock_gpio_set_mode(int port, int mode, int irq) +{ + dock_write_register(0xf0, port); + dock_write_register(0xf1, mode); + dock_write_register(0xf2, irq); +} + +static void dlpc_gpio_init(void) +{ + /* Select GPIO module */ + dlpc_write_register(0x07, 0x07); + /* GPIO Base Address 0x1680 */ + dlpc_write_register(0x60, 0x16); + dlpc_write_register(0x61, 0x80); + + /* Activate GPIO */ + dlpc_write_register(0x30, 0x01); + + dlpc_gpio_set_mode(0x00, 3); + dlpc_gpio_set_mode(0x01, 3); + dlpc_gpio_set_mode(0x02, 0); + dlpc_gpio_set_mode(0x03, 3); + dlpc_gpio_set_mode(0x04, 4); + dlpc_gpio_set_mode(0x20, 4); + dlpc_gpio_set_mode(0x21, 4); + dlpc_gpio_set_mode(0x23, 4); +} + +int dlpc_init(void) +{ + int timeout = 1000; + + /* Enable 14.318MHz CLK on CLKIN */ + dlpc_write_register(0x29, 0xa0); + while(!(dlpc_read_register(0x29) & 0x10) && timeout--) + udelay(1000); + + if (!timeout) + return 1; + + /* Select DLPC module */ + dlpc_write_register(0x07, 0x19); + /* DLPC Base Address 0x164c */ + dlpc_write_register(0x60, 0x16); + dlpc_write_register(0x61, 0x4c); + /* Activate DLPC */ + dlpc_write_register(0x30, 0x01); + + outb(0x07, 0x164c); + + timeout = 1000; + + while(!(inb(0x164c) & 8) && timeout--) + udelay(1000); + + if (!timeout) { + /* docking failed, disable DLPC switch */ + outb(0x00, 0x164c); + dlpc_write_register(0x30, 0x00); + return 1; + } + + dlpc_gpio_init(); + + return 0; +} + +int dock_connect(void) +{ + int timeout = 1000; + + /* Assert D_PLTRST# */ + outb(0xfe, 0x1680); + udelay(1000); + /* Deassert D_PLTRST# */ + outb(0xff, 0x1680); + + /* startup 14.318MHz Clock */ + dock_write_register(0x29, 0x06); + /* wait until clock is settled */ + while(!(dock_read_register(0x29) & 0x08) && timeout--) + udelay(1000); + + if (!timeout) + return 1; + + /* Pin 6: CLKRUN + * Pin 72: #DR1 + * Pin 19: #SMI + * Pin 73: #MTR + */ + dock_write_register(0x24, 0x37); + + /* PNF active HIGH */ + dock_write_register(0x25, 0xa0); + + /* disable FDC */ + dock_write_register(0x26, 0x01); + + /* Enable GPIO IRQ to #SMI */ + dock_write_register(0x28, 0x02); + + /* select GPIO */ + dock_write_register(0x07, 0x07); + + /* set base address */ + dock_write_register(0x60, 0x16); + dock_write_register(0x61, 0x20); + + /* init GPIO pins */ + dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE | + PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE | + PC87392_GPIO_PIN_PULLUP, + PC87392_GPIO_PIN_TRIGGERS_SMI); + + dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02); + + dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE | + PC87392_GPIO_PIN_PULLUP, + PC87392_GPIO_PIN_TRIGGERS_SMI); + + dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP | + PC87392_GPIO_PIN_OE , 0x00); + + dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL | + PC87392_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL | + PC87392_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP | + PC87392_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00); + + /* enable GPIO */ + dock_write_register(0x30, 0x01); + + outb(0x00, 0x1628); + outb(0x00, 0x1623); + outb(0x82, 0x1622); + outb(0xff, 0x1624); + + /* Enable USB and Ultrabay power */ + outb(0x03, 0x1628); + return 0; +} + +void dock_disconnect(void) +{ + /* disconnect LPC bus */ + outb(0x00, 0x164c); + /* Assert PLTRST and DLPCPD */ + outb(0xfc, 0x1680); +} + +int dock_present(void) +{ + return !((inb(DEFAULT_GPIOBASE + 0x0c) >> 13) & 1); +} Added: trunk/src/mainboard/lenovo/x60/dock.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/dock.h Fri Apr 1 09:28:56 2011 (r6473) @@ -0,0 +1,8 @@ +#ifndef THINKPAD_X60_DOCK_H +#define THINKPAD_X60_DOCK_H + +extern int dock_connect(void); +extern void dock_disconnect(void); +extern int dock_present(void); +extern int dlpc_init(void); +#endif Modified: trunk/src/mainboard/lenovo/x60/mainboard_smi.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard_smi.c Fri Apr 1 09:28:50 2011 (r6472) +++ trunk/src/mainboard/lenovo/x60/mainboard_smi.c Fri Apr 1 09:28:56 2011 (r6473) @@ -24,30 +24,55 @@ #include #include #include "southbridge/intel/i82801gx/nvs.h" +#include +#include "dock.h" +#include "smi.h" /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ extern global_nvs_t *gnvs; +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); + ec_set_ports(0x1604, 0x1600); +} + int mainboard_io_trap_handler(int smif) { + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - //gnvs->smif = 0; + case SMI_DOCK_CONNECT: + dlpc_init(); + if (!dock_connect()) { + /* set dock LED to indicate status */ + ec_write(0x0c, 0x88); + } else { + /* blink dock LED to indicate failure */ + ec_write(0x0c, 0xc8); + } + break; + + case SMI_DOCK_DISCONNECT: + dock_disconnect(); + ec_write(0x0c, 0x08); break; + default: - return 0; + return 1; } /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - //gnvs->smif = 0; - return 1; + * On failure, the IO Trap Handler returns a value != 0 */ + return 0; } Modified: trunk/src/mainboard/lenovo/x60/romstage.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/romstage.c Fri Apr 1 09:28:50 2011 (r6472) +++ trunk/src/mainboard/lenovo/x60/romstage.c Fri Apr 1 09:28:56 2011 (r6473) @@ -37,6 +37,7 @@ #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" +#include "dock.h" void setup_ich7_gpios(void) { @@ -107,78 +108,6 @@ outb(val, port+1); } -static void dock_write_register(int reg, int value) -{ - outb(reg, 0x164e); - outb(value, 0x164f); - /* original software reads the chip id after every - I/O operation. Not sure if they are doing it for - some code switching depending on hardware or just - to have a delay after every operation. - - Do it the same way for now, we may remove it later - if it isn't needed - */ - outb(0x20, 0x164e); - inb(0x164f); -} - -static void dock_dlpc_init(void) -{ - /* Select DLPC module */ - dock_write_register(0x07, 0x19); - /* DLPC Base Address 0x164c */ - dock_write_register(0x60, 0x16); - dock_write_register(0x61, 0x4c); - /* Activate DLPC */ - dock_write_register(0x30, 0x01); - outb(0x07, 0x164c); - - while(!(inb(0x164c) & 8)) - udelay(100 * 100); -} - -static void dock_gpio_set_mode(int port, int mode) -{ - dock_write_register(0xf0, port); - dock_write_register(0xf1, mode); - -} - -static void dock_gpio_init(void) -{ - /* Select GPIO module */ - dock_write_register(0x07, 0x07); - /* GPIO Base Address 0x1680 */ - dock_write_register(0x60, 0x16); - dock_write_register(0x61, 0x80); - - /* Activate GPIO */ - dock_write_register(0x30, 0x01); - - dock_gpio_set_mode(0x00, 3); - dock_gpio_set_mode(0x01, 3); - dock_gpio_set_mode(0x02, 0); - dock_gpio_set_mode(0x03, 3); - dock_gpio_set_mode(0x04, 4); - dock_gpio_set_mode(0x20, 4); - dock_gpio_set_mode(0x21, 4); - dock_gpio_set_mode(0x23, 4); -} - -static void connect_dock(void) -{ - /* Enable 14.318MHz CLK on CLKIN */ - dock_write_register(0x29, 0x00); - dock_write_register(0x29, 0xa0); - dock_gpio_init(); - /* Assert D_PLTRST# */ - outb(0xfe, 0x1680); - dock_dlpc_init(); - /* Deassert D_PLTRST# */ - outb(0xff, 0x1680); -} - static void early_superio_config(void) { device_t dev; @@ -306,12 +235,17 @@ ich7_enable_lpc(); - connect_dock(); - - early_superio_config(); - /* Set up the console */ - uart_init(); + /* dock_init initializes the DLPC switch on + * thinpad side, so this is required even + * if we're undocked. + */ + if (!dlpc_init() && dock_present()) { + dock_connect(); + early_superio_config(); + /* Set up the console */ + uart_init(); + } #if CONFIG_USBDEBUG i82801gx_enable_usbdebug(1); Added: trunk/src/mainboard/lenovo/x60/smi.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/smi.h Fri Apr 1 09:28:56 2011 (r6473) @@ -0,0 +1,7 @@ +#ifndef MAINBOARD_LENOVO_X60_SMI_H +#define MAINBOARD_LENOVO_X60_SMI_H + +#define SMI_DOCK_CONNECT 0x01 +#define SMI_DOCK_DISCONNECT 0x02 + +#endif From svn at coreboot.org Fri Apr 1 09:41:47 2011 From: svn at coreboot.org (repository service) Date: Fri, 01 Apr 2011 09:41:47 +0200 Subject: [coreboot] [commit] r6474 - trunk/src/mainboard/lenovo/x60/acpi Message-ID: Author: svens Date: Fri Apr 1 09:41:47 2011 New Revision: 6474 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6474 Log: remove swp files accidently added Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Deleted: trunk/src/mainboard/lenovo/x60/acpi/.ec.asl.swp trunk/src/mainboard/lenovo/x60/acpi/.gpe.asl.swp From jwangzju at gmail.com Fri Apr 1 18:47:24 2011 From: jwangzju at gmail.com (Jiang Wang) Date: Fri, 1 Apr 2011 12:47:24 -0400 Subject: [coreboot] XP is very slow on coreboot with SeaBIOS Message-ID: Hi there, My colleagues and me tested Windows XP SP3 on coreboot and SeaBIOS on ASUS M2V MX-SE motherboard. The XP is very slow when opening a new window (such as Visual Studio) and when suspending and waking up. We tried original AMI bios, which is much faster. Also, we noticed that on coreboot and SeaBIOS, interrupts some times consume about 20-60% CPU usage, which is very strange. We tried two coreboot version: 6179 and 6460. Both are slow. The SeaBIOS version is 0.6.1 I am not sure whether it is coreboot or SeaBIOS problem. Any suggestions? Regards, Jiang From marcj303 at gmail.com Fri Apr 1 20:15:10 2011 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 1 Apr 2011 12:15:10 -0600 Subject: [coreboot] [patch] rs780 4GB memory issues Message-ID: Use TOM2 for highest sysmem setting for northbound memory routing (DMA). This fixes 4GB memory issues. Signed-off-by: Marc Jones -- http://se-eng.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 780sysmem.patch Type: text/x-patch Size: 1040 bytes Desc: not available URL: From vidwer at gmail.com Fri Apr 1 20:29:39 2011 From: vidwer at gmail.com (Idwer Vollering) Date: Fri, 1 Apr 2011 20:29:39 +0200 Subject: [coreboot] [patch] fix compilation of all i82371eb boards when ACPI tables aren't generated Message-ID: When CONFIG_GENERATE_ACPI_TABLES is not used/set, this error appears: CC southbridge/intel/i82371eb/fadt.driver.o src/southbridge/intel/i82371eb/fadt.c:35:35: error: expected ')' before '*' token make: *** [build/southbridge/intel/i82371eb/fadt.driver.o] Error 1 These boards are affected (shell command): for f in $(find src/mainboard/ -name Kconfig); do grep -Hi i82371eb $f ; done | awk -F \/ '{ print $3 "/" $4 }'| sort abit/be6-ii_v2_0 asus/p2b asus/p2b-d asus/p2b-ds asus/p2b-f asus/p2b-ls asus/p3b-f a-trend/atc-6220 a-trend/atc-6240 azza/pt-6ibd biostar/m6tba compaq/deskpro_en_sff_p600 emulation/qemu-x86 gigabyte/ga-6bxc gigabyte/ga-6bxe msi/ms6119 msi/ms6147 msi/ms6156 nokia/ip530 soyo/sy-6ba-plus-iii tyan/s1846 Signed-off-by: Idwer Vollering --- Index: src/southbridge/intel/i82371eb/Makefile.inc =================================================================== --- src/southbridge/intel/i82371eb/Makefile.inc (revision 6474) +++ src/southbridge/intel/i82371eb/Makefile.inc (working copy) @@ -24,8 +24,10 @@ driver-y += usb.c driver-y += smbus.c driver-y += reset.c +ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y) driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c +endif romstage-y += early_pm.c romstage-y += early_smbus.c From buurin at gmail.com Fri Apr 1 21:28:22 2011 From: buurin at gmail.com (Keith Hui) Date: Fri, 1 Apr 2011 15:28:22 -0400 Subject: [coreboot] [PATCH] 440BX registered SDRAM support In-Reply-To: References: <20110329213451.GB19577@coreboot.org> Message-ID: ping? On Wed, Mar 30, 2011 at 11:38 PM, Keith Hui wrote: > On Tue, Mar 29, 2011 at 5:34 PM, Stefan Reinauer > wrote: >> * Keith Hui [110329 06:11]: >>> >> + ? ?if ((edosd & 0x84) == 0x84) { >>> >> + ? ? ? ?edosd = 0x10; // Registered SDRAM >>> >> + ? ?} else { >>> >> + ? ? ? ?// Clear [4:3] in case it's EDO. >>> >> + ? ? ? ?edosd &= 0x07; >>> >> +// ? ?} else if (edosd & 0x02) { >>> > Besides being commented out, this piece of code would never be executed, >>> > as there already is an else case. >>> > Also, modifying edosd in place is semi nice. >>> >>> So is this good, not so good, or bad? >>> >>> I want to know if I should split up edosd. >> >> Please do. >> > > And so I did. Signoff in the patch. > > edosd was a romcc-inspired trick because variables were a scarce resource. > > The nbxecc simplification in this patch completed one full pass of > memtest86+ each with a regular and registered ECC DIMM installed. > > With this patch the 440BX romstage is 60 bytes smaller, freeing up an > extra 64 bytes in the image. > > Thanks > Keith > From marcj303 at gmail.com Fri Apr 1 21:37:42 2011 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 1 Apr 2011 13:37:42 -0600 Subject: [coreboot] [patch] rs780 4GB memory issues In-Reply-To: References: Message-ID: On Fri, Apr 1, 2011 at 12:15 PM, Marc Jones wrote: > Use TOM2 for highest sysmem setting for northbound memory routing > (DMA). This fixes 4GB memory issues. > > Signed-off-by: Marc Jones > Fixed the whitespace I messed up. -- http://se-eng.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 780sysmem.patch Type: text/x-patch Size: 1008 bytes Desc: not available URL: From mlf.conv at gmail.com Fri Apr 1 21:37:15 2011 From: mlf.conv at gmail.com (Marek) Date: Fri, 1 Apr 2011 21:37:15 +0200 Subject: [coreboot] Gigabyte GA AMD E350N USB3 Board Message-ID: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> Hi, with regards to recent AMD patches, I'd like to ask whether it would be possible to install coreboot on Gigabyte GA AMD E350N USB3 board (AMD E350, chipset FCH A50 Hudson M1, iTE 8720). thanks Marek From r.marek at assembler.cz Fri Apr 1 21:54:05 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 01 Apr 2011 21:54:05 +0200 Subject: [coreboot] XP is very slow on coreboot with SeaBIOS In-Reply-To: References: Message-ID: <4D962D5D.3090503@assembler.cz> Hi, Do you use sata or IDE? Maybe IDE does not have DMA working in Windows. If you use IDE try to find out if PIO is used or DMA. Thanks Rudolf From jwangzju at gmail.com Fri Apr 1 22:05:06 2011 From: jwangzju at gmail.com (Jiang Wang) Date: Fri, 1 Apr 2011 16:05:06 -0400 Subject: [coreboot] XP is very slow on coreboot with SeaBIOS In-Reply-To: <4D962D5D.3090503@assembler.cz> References: <4D962D5D.3090503@assembler.cz> Message-ID: Hi Rudolf, We use SATA hard disk. Maybe something else is wrong? Thanks. Regards, Jiang On Fri, Apr 1, 2011 at 3:54 PM, Rudolf Marek wrote: > Hi, > > Do you use sata or IDE? Maybe IDE ?does not have DMA working in Windows. If > you use IDE try to find out if PIO is used or DMA. > > Thanks > Rudolf > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From scott at notabs.org Fri Apr 1 22:14:45 2011 From: scott at notabs.org (Scott Duplichan) Date: Fri, 1 Apr 2011 15:14:45 -0500 Subject: [coreboot] XP is very slow on coreboot with SeaBIOS In-Reply-To: References: <4D962D5D.3090503@assembler.cz> Message-ID: <7E31DD6D538F4FAF9DFCD8783389787F@m3a78> ]Hi Rudolf, ] ]We use SATA hard disk. Maybe something else is wrong? Thanks. Though your hardware connection is SATA, the software interface is probably IDE. WinXP has no in-box AHCI driver for SB700 or SB800. To make WinXP use AHCI with AMD requires pressing F6 during setup and giving it a driver floppy. Check device manager for a DMA mode such as 'Ultra DMA mode 6' shown in the attached image. Thanks, Scott ]Regards, ] ]Jiang ] ]On Fri, Apr 1, 2011 at 3:54 PM, Rudolf Marek wrote: ]> Hi, ]> ]> Do you use sata or IDE? Maybe IDE ?does not have DMA working in Windows. If ]> you use IDE try to find out if PIO is used or DMA. ]> ]> Thanks ]> Rudolf -------------- next part -------------- A non-text attachment was scrubbed... Name: ide-dma.png Type: image/png Size: 15642 bytes Desc: not available URL: From yuen at klacno.sk Fri Apr 1 20:59:27 2011 From: yuen at klacno.sk (yuen at klacno.sk) Date: Fri, 1 Apr 2011 20:59:27 +0200 (CEST) Subject: [coreboot] Asus B202 port Message-ID: <33890.10.125.50.142.1301684367.squirrel@webmail.klacno.sk> Hi, I'm working on port coreboot to Asus Eee Box B202 (http://www.asus.com/product.aspx?P_ID=QUObl5lSRQQ3lSqJ). Code is based on Intel d945gclf target. So far I have console running. Boot halts on sdram initialization before "Extended Mode Register Set(2)", sometime goes one or two steps ahead. Any idea how to move on? Cheers Marek Becka -------------- next part -------------- A non-text attachment was scrubbed... Name: dmi.dump Type: application/octet-stream Size: 10012 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: superio.dump Type: application/octet-stream Size: 1618 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: intel.dump Type: application/octet-stream Size: 191141 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot.log Type: text/x-log Size: 1791 bytes Desc: not available URL: From stefan.reinauer at coreboot.org Fri Apr 1 22:49:07 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Fri, 1 Apr 2011 22:49:07 +0200 Subject: [coreboot] [patch] rs780 4GB memory issues In-Reply-To: References: Message-ID: <20110401204907.GA3499@coreboot.org> * Marc Jones [110401 21:37]: > Use TOM2 for highest sysmem setting for northbound memory routing (DMA). This fixes 4GB memory issues. > > Signed-off-by: Marc Jones Acked-by: Stefan Reinauer From stefan.reinauer at coreboot.org Fri Apr 1 22:50:52 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Fri, 1 Apr 2011 22:50:52 +0200 Subject: [coreboot] [patch] fix compilation of all i82371eb boards when ACPI tables aren't generated In-Reply-To: References: Message-ID: <20110401205052.GB3499@coreboot.org> * Idwer Vollering [110401 20:29]: > Signed-off-by: Idwer Vollering > > --- > > Index: src/southbridge/intel/i82371eb/Makefile.inc > =================================================================== > --- src/southbridge/intel/i82371eb/Makefile.inc (revision 6474) > +++ src/southbridge/intel/i82371eb/Makefile.inc (working copy) > @@ -24,8 +24,10 @@ > driver-y += usb.c > driver-y += smbus.c > driver-y += reset.c > +ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y) > driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c > driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c > +endif > should this just be driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c driver-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c instead? From vidwer at gmail.com Fri Apr 1 22:57:52 2011 From: vidwer at gmail.com (Idwer Vollering) Date: Fri, 1 Apr 2011 22:57:52 +0200 Subject: [coreboot] [patch] fix compilation of all i82371eb boards when ACPI tables aren't generated In-Reply-To: <20110401205052.GB3499@coreboot.org> References: <20110401205052.GB3499@coreboot.org> Message-ID: 2011/4/1 Stefan Reinauer : > * Idwer Vollering [110401 20:29]: >> Signed-off-by: Idwer Vollering >> >> --- >> >> Index: src/southbridge/intel/i82371eb/Makefile.inc >> =================================================================== >> --- src/southbridge/intel/i82371eb/Makefile.inc (revision 6474) >> +++ src/southbridge/intel/i82371eb/Makefile.inc (working copy) >> @@ -24,8 +24,10 @@ >> ?driver-y += ?usb.c >> ?driver-y += ?smbus.c >> ?driver-y += ?reset.c >> +ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y) >> ?driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c >> ?driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c >> +endif >> > > should this just be > driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c > driver-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c > > instead? Ah, yes: for f in $(find -name Makefile.inc); do grep -H CONFIG_GENERATE_ACPI_TABLES $f ; done | wc -l 23 > > > From vidwer at gmail.com Fri Apr 1 23:00:34 2011 From: vidwer at gmail.com (Idwer Vollering) Date: Fri, 1 Apr 2011 23:00:34 +0200 Subject: [coreboot] [patch] fix compilation of all i82371eb boards when ACPI tables aren't generated In-Reply-To: References: <20110401205052.GB3499@coreboot.org> Message-ID: V2. Signed-off-by: Idwer Vollering --- Index: src/southbridge/intel/i82371eb/Makefile.inc =================================================================== --- src/southbridge/intel/i82371eb/Makefile.inc (revision 6474) +++ src/southbridge/intel/i82371eb/Makefile.inc (working copy) @@ -24,8 +24,8 @@ driver-y += usb.c driver-y += smbus.c driver-y += reset.c -driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c +driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +driver-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c romstage-y += early_pm.c romstage-y += early_smbus.c From r.marek at assembler.cz Fri Apr 1 23:36:13 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 01 Apr 2011 23:36:13 +0200 Subject: [coreboot] [patch] rs780 4GB memory issues In-Reply-To: References: Message-ID: <4D96454D.9070006@assembler.cz> Hi, How the patch actually works? It looks like it only prints TOM2 not using it. Thanks, Rudolf From r.marek at assembler.cz Fri Apr 1 23:37:56 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 01 Apr 2011 23:37:56 +0200 Subject: [coreboot] XP is very slow on coreboot with SeaBIOS In-Reply-To: <7E31DD6D538F4FAF9DFCD8783389787F@m3a78> References: <4D962D5D.3090503@assembler.cz> <7E31DD6D538F4FAF9DFCD8783389787F@m3a78> Message-ID: <4D9645B4.4060005@assembler.cz> Yeah Scott is right, although VIA SATA is not an AHCI. Please check if you see DMA there. If not maybe VIA drivers will help. Thanks, Rudolf From stefan.reinauer at coreboot.org Fri Apr 1 23:39:09 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Fri, 1 Apr 2011 23:39:09 +0200 Subject: [coreboot] Asus B202 port In-Reply-To: <33890.10.125.50.142.1301684367.squirrel@webmail.klacno.sk> References: <33890.10.125.50.142.1301684367.squirrel@webmail.klacno.sk> Message-ID: <20110401213909.GA23448@coreboot.org> * yuen at klacno.sk [110401 20:59]: > Hi, I'm working on port coreboot to Asus Eee Box B202 > (http://www.asus.com/product.aspx?P_ID=QUObl5lSRQQ3lSqJ). Code is based on > Intel d945gclf target. > > So far I have console running. Boot halts on sdram initialization before > "Extended Mode Register Set(2)", sometime goes one or two steps ahead. > > Any idea how to move on? Dump the MCHBAR registers before jedec init and compare them against an inteltool dump running with the original vendor bios. > Cheers > Marek Becka > coreboot-4.0-r6469M Fri Apr 1 18:17:34 CEST 2011 starting... > > Mobile Intel(R) 82945GMS/GU Express Chipset > (G)MCH capable of up to FSB 667 MHz > (G)MCH capable of up to DDR2-533 > > Setting up static southbridge registers... GPIOS... done. > Disabling Watchdog reboot... done. > Setting up static northbridge registers... done. > Waiting for MCHBAR to come up...ok > SMBus controller enabled. > Setting up RAM controller. > This mainboard supports only Single Channel Operation. > DDR II Channel 0 Socket 0: x16DS > lowest common cas = 3 > Probing Speed 1 > DIMM: 0 > Current CAS mask: 0038; idx=2, tCLK=50, tAC=60: Not fast enough! > Current CAS mask: 0030; idx=1, tCLK=3d, tAC=50: OK > DIMM: 1 > DIMM: 2 > DIMM: 3 > freq_cas_mask for speed 1: 0030 > Memory will be driven at 533MHz with CAS=4 clocks > tRAS = 12 cycles > tRP = 4 cycles > tRCD = 4 cycles > Refresh: 7.8us > tWR = 4 cycles > DIMM 0 side 0 = 512 MB > DIMM 0 side 1 = 512 MB > tRFC = 34 cycles > Setting Graphics Frequency... > FSB: 533 MHz Voltage: 1.05V Render: 166Mhz Display: 200MHz Hm.. FSB supports up to 667 > Setting Memory Frequency... CLKCFG=0x00010021, CLKCFG=0x00010031, ok > Setting mode of operation for memory channels...Single Channel 0 only. > DCC=0x00000400 > Programming Clock Crossing...MEM=667 FSB=533... ok This looks suspicious. It MEM=667 is not supported. > Setting RAM size... > C0DRB = 0x20202010 > C1DRB = 0x00000000 > TOLUD = 0x0040 > Setting row attributes... > C0DRA = 0x0033 > C1DRA = 0x0000 > DIMM0 has 8 banks. > one dimm per channel config.. > Initializing System Memory IO... > Programming Single Channel RCOMP > Table Index: 4 > Programming DLL Timings... > Enabling System Memory IO... > jedec enable sequence: bank 0 > Apply NOP > Sending RAM command 0x00010400...done > ram read: 00000000 > All Banks Precharge > Sending RAM command 0x00020400...done > ram read: 00000000 From stefan.reinauer at coreboot.org Fri Apr 1 23:42:47 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Fri, 1 Apr 2011 23:42:47 +0200 Subject: [coreboot] [patch] fix compilation of all i82371eb boards when ACPI tables aren't generated In-Reply-To: References: <20110401205052.GB3499@coreboot.org> Message-ID: <20110401214247.GA27104@coreboot.org> * Idwer Vollering [110401 23:00]: > V2. > > Signed-off-by: Idwer Vollering Acked-by: Stefan Reinauer > --- > > Index: src/southbridge/intel/i82371eb/Makefile.inc > =================================================================== > --- src/southbridge/intel/i82371eb/Makefile.inc (revision 6474) > +++ src/southbridge/intel/i82371eb/Makefile.inc (working copy) > @@ -24,8 +24,8 @@ > driver-y += usb.c > driver-y += smbus.c > driver-y += reset.c > -driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c > -driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c > +driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c > +driver-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c > > romstage-y += early_pm.c > romstage-y += early_smbus.c > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From jwangzju at gmail.com Fri Apr 1 23:44:13 2011 From: jwangzju at gmail.com (Jiang Wang) Date: Fri, 1 Apr 2011 17:44:13 -0400 Subject: [coreboot] XP is very slow on coreboot with SeaBIOS In-Reply-To: <4D9645B4.4060005@assembler.cz> References: <4D962D5D.3090503@assembler.cz> <7E31DD6D538F4FAF9DFCD8783389787F@m3a78> <4D9645B4.4060005@assembler.cz> Message-ID: I see. We checked DMA for the hard disk controller and it is not there. We are searching for VIA chipset drivers. I am still curious why the original AMI BIOS can support Windows (probably with DMA) better. Maybe AMI BIOS enables the DMA itself, so it does not need any driver? Regards, Jiang On Fri, Apr 1, 2011 at 5:37 PM, Rudolf Marek wrote: > Yeah Scott is right, although VIA SATA is not an AHCI. Please check if you > see DMA there. If not maybe VIA drivers will help. > > Thanks, > Rudolf > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From r.marek at assembler.cz Fri Apr 1 23:47:03 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 01 Apr 2011 23:47:03 +0200 Subject: [coreboot] XP is very slow on coreboot with SeaBIOS In-Reply-To: References: <4D962D5D.3090503@assembler.cz> <7E31DD6D538F4FAF9DFCD8783389787F@m3a78> <4D9645B4.4060005@assembler.cz> Message-ID: <4D9647D7.5080808@assembler.cz> Hi Most likely because of the ACPI IDE methods which tell OS how to do DMA without the driver. I did not need them for Linux so I did not bother to implement them. I thit it is like GTM etc check ACPI spec for details. Maybe it can be done static way just supply right methods. Thanks Rudolf From marcj303 at gmail.com Fri Apr 1 23:47:21 2011 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 1 Apr 2011 15:47:21 -0600 Subject: [coreboot] [patch] rs780 4GB memory issues In-Reply-To: <4D96454D.9070006@assembler.cz> References: <4D96454D.9070006@assembler.cz> Message-ID: On Fri, Apr 1, 2011 at 3:36 PM, Rudolf Marek wrote: > Hi, > > How the patch actually works? It looks like it only prints TOM2 not using > it. Argh, .. and half the change doesn't help... *sigh* Thanks for catching that! Marc -- http://se-eng.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 780sysmem.patch Type: text/x-patch Size: 1204 bytes Desc: not available URL: From jwangzju at gmail.com Sat Apr 2 00:09:48 2011 From: jwangzju at gmail.com (Jiang Wang) Date: Fri, 1 Apr 2011 18:09:48 -0400 Subject: [coreboot] XP is very slow on coreboot with SeaBIOS In-Reply-To: <4D9647D7.5080808@assembler.cz> References: <4D962D5D.3090503@assembler.cz> <7E31DD6D538F4FAF9DFCD8783389787F@m3a78> <4D9645B4.4060005@assembler.cz> <4D9647D7.5080808@assembler.cz> Message-ID: I see. Also, we installed VIA SATA driver on XP and the problem is solved. Thank you all. Regards, Jiang On Fri, Apr 1, 2011 at 5:47 PM, Rudolf Marek wrote: > Hi > > Most likely because of the ACPI IDE methods which tell OS how to do DMA > without the driver. I did not need them for Linux so I did not bother to > implement them. I thit it is like GTM etc check ACPI spec for details. Maybe > it can be done static way just supply right methods. > > Thanks > Rudolf > From stefan.reinauer at coreboot.org Sat Apr 2 00:30:48 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Sat, 2 Apr 2011 00:30:48 +0200 Subject: [coreboot] Asus B202 port In-Reply-To: <33890.10.125.50.142.1301684367.squirrel@webmail.klacno.sk> References: <33890.10.125.50.142.1301684367.squirrel@webmail.klacno.sk> Message-ID: <20110401223048.GA10969@coreboot.org> * yuen at klacno.sk [110401 20:59]: > Hi, I'm working on port coreboot to Asus Eee Box B202 > (http://www.asus.com/product.aspx?P_ID=QUObl5lSRQQ3lSqJ). Code is based on > Intel d945gclf target. > > So far I have console running. Boot halts on sdram initialization before > "Extended Mode Register Set(2)", sometime goes one or two steps ahead. > > Any idea how to move on? Several: * Are you selecting NORTHBRIDGE_INTEL_I945GC in your mainboard Kconfig file? Then you are using code for the wrong chipset. You need to select NORTHBRIDGE_INTEL_I945GM. * Are you using the coreboot reference toolchain? If not, and the above does not work, please build the coreboot reference toolchain with util/crossgcc/buildgcc, then delete your .xcompile file. Stefan From stefan.reinauer at coreboot.org Sat Apr 2 00:33:25 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Sat, 2 Apr 2011 00:33:25 +0200 Subject: [coreboot] [PATCH] better chipset reporting on i945 Message-ID: <20110401223325.GB10969@coreboot.org> See patch -------------- next part -------------- A non-text attachment was scrubbed... Name: i945_warn_chipset.diff Type: text/x-patch Size: 1487 bytes Desc: not available URL: From stefan.reinauer at coreboot.org Sat Apr 2 00:48:28 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Sat, 2 Apr 2011 00:48:28 +0200 Subject: [coreboot] Asus B202 port In-Reply-To: <33489.10.125.50.142.1301696022.squirrel@webmail.klacno.sk> References: <33890.10.125.50.142.1301684367.squirrel@webmail.klacno.sk> <20110401213909.GA23448@coreboot.org> <33489.10.125.50.142.1301696022.squirrel@webmail.klacno.sk> Message-ID: <20110401224828.GA20636@coreboot.org> * yuen at klacno.sk [110402 00:13]: > > >> Setting Graphics Frequency... > >> FSB: 533 MHz Voltage: 1.05V Render: 166Mhz Display: 200MHz > > Hm.. FSB supports up to 667 > > Atom N270 supports just 533Mhz And that's apparently what it is trying to use, too. > >> Setting Memory Frequency... CLKCFG=0x00010021, CLKCFG=0x00010031, ok > >> Setting mode of operation for memory channels...Single Channel 0 only. > >> DCC=0x00000400 > >> Programming Clock Crossing...MEM=667 FSB=533... ok > > > > This looks suspicious. It MEM=667 is not supported. > > Just idea ... maybe I should try it with debuggind messages off, if there > is something with CAR ... Unlikely, but worth a shot. See my other mail for suggestions. From scott at notabs.org Sat Apr 2 08:39:25 2011 From: scott at notabs.org (Scott Duplichan) Date: Sat, 2 Apr 2011 01:39:25 -0500 Subject: [coreboot] mingw build problem with seabios/tools/kconfig In-Reply-To: <20110314124201.GA32618@morn.localdomain> References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78><20110313225253.GA4004@morn.localdomain><20110314033049.GA14722@morn.localdomain><4D7D903D.7030305@coreboot.org> <20110314124201.GA32618@morn.localdomain> Message-ID: <491904E6ACC54DC9899C37BF17493DD4@m3a78> Kevin O'Connor wrote: ]On Sun, Mar 13, 2011 at 08:49:17PM -0700, Stefan Reinauer wrote: ]> On 3/13/11 8:30 PM, Kevin O'Connor wrote: ]> >>Here is how the ]> >>how the problem was overcome for coreboot: ]> >>http://tracker.coreboot.org/trac/coreboot/changeset/4952 ]> >>When I add the UNLINK_IF_NECESSARY part of this change, the rename succeeds. ]> >>Could seabios adopt this change? ]> >It's possible, but I'd prefer to keep the source code close to the ]> >Linux version - it makes merges later on easier. ]> ]> Then maybe we should send our patches upstream? ] ]Yes - getting the patches into the Linux kbuild source would be best. ] ]-Kevin I might not be the best one for explaining the benefit of Windows support to the linux crowd. So to get past this problem, I modified my mingw to accomodate the new seabios kconfig tool build. To make the mkdir function compatible with both environments, I changed its prototype to include a variable argument list after the first argument. To fix the rename function, I substituted the gnulib version of this function. To get past the default lib search differences, I added libregex and libws2_32 to libmingw32. To solve the missing uname problem, I added the gnulib version to libmingw32. The result is here: http://notabs.org/coreboot/windows-build.htm Now I can get through abuild, almost. I still get an occasional git failure (see attached). Not sure what causes it, but debugging that is for another day. Thanks, Scott -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: abuild.txt URL: From hamo.by at gmail.com Sat Apr 2 14:14:43 2011 From: hamo.by at gmail.com (Hamo) Date: Sat, 2 Apr 2011 20:14:43 +0800 Subject: [coreboot] Where is the source code of Coreboot for PPC? Message-ID: Hi lists, As I want to port Coreboot to ARM, I need to study the structure of Coreboot. Since Coreboot supported PPC once, I want to study the structure of the source code. But I can't find it. Can someone help me? Thanks. From joe at settoplinux.org Sat Apr 2 19:08:26 2011 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 02 Apr 2011 13:08:26 -0400 Subject: [coreboot] Where is the source code of Coreboot for PPC? In-Reply-To: References: Message-ID: <4D97580A.8090809@settoplinux.org> On 04/02/2011 08:14 AM, Hamo wrote: > Hi lists, > As I want to port Coreboot to ARM, I need to study the structure of > Coreboot. Since Coreboot supported PPC once, I want to study the > structure of the source code. But I can't find it. Can someone help > me? Thanks. > Doxygen gives a pretty good visual of the logical flow of coreboot in general. http://qa.coreboot.org/docs/doxygen/ I believe PPC was purged from the tree a little while ago so if you go back some revisions you will be able to find it. Hope that helps. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From peter at stuge.se Sun Apr 3 02:13:04 2011 From: peter at stuge.se (Peter Stuge) Date: Sun, 3 Apr 2011 02:13:04 +0200 Subject: [coreboot] Where is the source code of Coreboot for PPC? In-Reply-To: References: Message-ID: <20110403001304.22177.qmail@stuge.se> Hamo wrote: > As I want to port Coreboot to ARM, I need to study the structure of > Coreboot. Since Coreboot supported PPC once, I want to study the > structure of the source code. Is a good idea. > But I can't find it. Can someone help me? Thanks. It will be in the current coreboot repository. I suggest you go backwards in steps of 1000 commits, and when it's there I think you should also try to build the code. Note that it will probably use the old v2 style of configuring and building. (Use buildtarget in the mainboards directory, it's a little odd.) The ppc stuff has not been tested for a long time so it's possible that you would have to go back another 1000 revs to get a working build, once you find a rev that has the code. I think that we by now may be making a few PC-only assumptions in the coreboot code, but in principle we do not want to, so if there are any and they are identified then we want to not have them anymore. :) //Peter From corey.osgood at gmail.com Sun Apr 3 03:14:52 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Sat, 2 Apr 2011 21:14:52 -0400 Subject: [coreboot] Where is the source code of Coreboot for PPC? In-Reply-To: <20110403001304.22177.qmail@stuge.se> References: <20110403001304.22177.qmail@stuge.se> Message-ID: On Sat, Apr 2, 2011 at 8:13 PM, Peter Stuge wrote: > Hamo wrote: >> As I want to port Coreboot to ARM, I need to study the structure of >> Coreboot. Since Coreboot supported PPC once, I want to study the >> structure of the source code. > > Is a good idea. > > >> But I can't find it. Can someone help me? Thanks. > > It will be in the current coreboot repository. I suggest you go > backwards in steps of 1000 commits, and when it's there I think you > should also try to build the code. Note that it will probably use the > old v2 style of configuring and building. (Use buildtarget in the > mainboards directory, it's a little odd.) The ppc stuff has not been > tested for a long time so it's possible that you would have to go > back another 1000 revs to get a working build, once you find a rev > that has the code. > > I think that we by now may be making a few PC-only assumptions in the > coreboot code, but in principle we do not want to, so if there are > any and they are identified then we want to not have them anymore. :) Looks like you want to go prior to r4700 or so http://www.coreboot.org/pipermail/coreboot/2009-October/052650.html Note that coreboot has changed a LOT since then. -Corey From hamo.by at gmail.com Sun Apr 3 15:51:06 2011 From: hamo.by at gmail.com (Hamo) Date: Sun, 3 Apr 2011 21:51:06 +0800 Subject: [coreboot] Where is the source code of Coreboot for PPC? In-Reply-To: References: <20110403001304.22177.qmail@stuge.se> Message-ID: Thanks Corey. I got the source code I need. On Sun, Apr 3, 2011 at 9:14 AM, Corey Osgood wrote: > On Sat, Apr 2, 2011 at 8:13 PM, Peter Stuge wrote: >> Hamo wrote: >>> As I want to port Coreboot to ARM, I need to study the structure of >>> Coreboot. Since Coreboot supported PPC once, I want to study the >>> structure of the source code. >> >> Is a good idea. >> >> >>> But I can't find it. Can someone help me? Thanks. >> >> It will be in the current coreboot repository. I suggest you go >> backwards in steps of 1000 commits, and when it's there I think you >> should also try to build the code. Note that it will probably use the >> old v2 style of configuring and building. (Use buildtarget in the >> mainboards directory, it's a little odd.) The ppc stuff has not been >> tested for a long time so it's possible that you would have to go >> back another 1000 revs to get a working build, once you find a rev >> that has the code. >> >> I think that we by now may be making a few PC-only assumptions in the >> coreboot code, but in principle we do not want to, so if there are >> any and they are identified then we want to not have them anymore. :) > > Looks like you want to go prior to r4700 or so > > http://www.coreboot.org/pipermail/coreboot/2009-October/052650.html > > Note that coreboot has changed a LOT since then. > > -Corey > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- ? ? """ ? ? Keep It Simple,Stupid. ? ? """ Chinese Name: ?? Nick Name: Hamo Homepage: http://hamobai.com/ GPG KEY ID: 0xA4691A33 Key fingerprint = 09D5 2D78 8E2B 0995 CF8E? 4331 33C4 3D24 A469 1A33 From hamo.by at gmail.com Sun Apr 3 15:52:53 2011 From: hamo.by at gmail.com (Hamo) Date: Sun, 3 Apr 2011 21:52:53 +0800 Subject: [coreboot] Where is the source code of Coreboot for PPC? In-Reply-To: <4D97580A.8090809@settoplinux.org> References: <4D97580A.8090809@settoplinux.org> Message-ID: On Sun, Apr 3, 2011 at 1:08 AM, Joseph Smith wrote: > On 04/02/2011 08:14 AM, Hamo wrote: >> >> Hi lists, >> As I want to port Coreboot to ARM, I need to study the structure of >> Coreboot. Since Coreboot supported PPC once, I want to study the >> structure of the source code. But I can't find it. Can someone help >> me? Thanks. >> > Doxygen gives a pretty good visual of the logical flow of coreboot in > general. > > http://qa.coreboot.org/docs/doxygen/ That's GREAT. But some information is missing. > > I believe PPC was purged from the tree a little while ago so if you go back > some revisions you will be able to find it. > > Hope that helps. > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > -- ? ? """ ? ? Keep It Simple,Stupid. ? ? """ Chinese Name: ?? Nick Name: Hamo Homepage: http://hamobai.com/ GPG KEY ID: 0xA4691A33 Key fingerprint = 09D5 2D78 8E2B 0995 CF8E? 4331 33C4 3D24 A469 1A33 From hamo.by at gmail.com Sun Apr 3 15:57:22 2011 From: hamo.by at gmail.com (Hamo) Date: Sun, 3 Apr 2011 21:57:22 +0800 Subject: [coreboot] Where is the source code of Coreboot for PPC? In-Reply-To: <20110403001304.22177.qmail@stuge.se> References: <20110403001304.22177.qmail@stuge.se> Message-ID: On Sun, Apr 3, 2011 at 8:13 AM, Peter Stuge wrote: > Hamo wrote: >> As I want to port Coreboot to ARM, I need to study the structure of >> Coreboot. Since Coreboot supported PPC once, I want to study the >> structure of the source code. > > Is a good idea. > > >> But I can't find it. Can someone help me? Thanks. > > It will be in the current coreboot repository. I suggest you go > backwards in steps of 1000 commits, and when it's there I think you > should also try to build the code. Note that it will probably use the > old v2 style of configuring and building. (Use buildtarget in the > mainboards directory, it's a little odd.) The ppc stuff has not been > tested for a long time so it's possible that you would have to go > back another 1000 revs to get a working build, once you find a rev > that has the code. > > I think that we by now may be making a few PC-only assumptions in the > coreboot code, but in principle we do not want to, so if there are > any and they are identified then we want to not have them anymore. :) > > Shall I first make the PPC support available in the current source tree to make sure that all of the IA32-only code has disappeared or just begin my porting to ARM. If the former, I have no experiences developing PPC software and I don't have a PPC device. Can someone give me a hand on this? > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- ? ? """ ? ? Keep It Simple,Stupid. ? ? """ Chinese Name: ?? Nick Name: Hamo Homepage: http://hamobai.com/ GPG KEY ID: 0xA4691A33 Key fingerprint = 09D5 2D78 8E2B 0995 CF8E? 4331 33C4 3D24 A469 1A33 From peter at stuge.se Sun Apr 3 16:04:34 2011 From: peter at stuge.se (Peter Stuge) Date: Sun, 3 Apr 2011 16:04:34 +0200 Subject: [coreboot] Where is the source code of Coreboot for PPC? In-Reply-To: References: <20110403001304.22177.qmail@stuge.se> Message-ID: <20110403140434.26401.qmail@stuge.se> Hamo wrote: > > I think that we by now may be making a few PC-only assumptions in the > > coreboot code, but in principle we do not want to, so if there are > > any and they are identified then we want to not have them anymore. :) > > Shall I first make the PPC support available in the current source > tree to make sure that all of the IA32-only code has disappeared or > just begin my porting to ARM. I say go straight for ARM. //Peter From bari at onelabs.com Sun Apr 3 19:13:05 2011 From: bari at onelabs.com (bari) Date: Sun, 03 Apr 2011 12:13:05 -0500 Subject: [coreboot] Where is the source code of Coreboot for PPC? In-Reply-To: References: <20110403001304.22177.qmail@stuge.se> Message-ID: <4D98AAA1.70502@onelabs.com> Hamo wrote: > Shall I first make the PPC support available in the current source > tree to make sure that all of the IA32-only code has disappeared or > just begin my porting to ARM. No. Just work on ARM. There is not much interest in reviving PPC support for coreboot. PPC interest and applications are shrinking while ARM is exploding. -Bari From devtadas at gmail.com Sun Apr 3 20:49:27 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Sun, 3 Apr 2011 21:49:27 +0300 Subject: [coreboot] [PATCH] FILO: USB_DISK by default should be disabled (trivial) Message-ID: Hello, This is my first patch, so please don't throw stones to me :) "config USB_DISK" should somehow depend on libpayload's "config USB" at least, but I don't know how to hardcode it, so I make USB disk to be disabled, since USB is disabled by default. It would be great if you could suggest how to link that dependency. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: usb_disk_defaults.patch Type: text/x-patch Size: 518 bytes Desc: not available URL: From fastcoreboot at me.com Sun Apr 3 21:09:33 2011 From: fastcoreboot at me.com (john) Date: Sun, 3 Apr 2011 19:09:33 +0000 (UTC) Subject: [coreboot] =?utf-8?q?Support_for_Jasper_Forest_and_Sandy_bridge_o?= =?utf-8?q?n=09coreboot?= References: <20110329012143.GB16402@coreboot.org> Message-ID: Stefan Reinauer coreboot.org> writes: > > * sharib khan gmail.com> [110328 11:36]: > > It is possible for us to get the boot sequence and other required documents for > > these processors. > > You will have to get NDAed information from Intel about this. > > > Could you highlight what are the necessary changes required in coreboot while > > integrating a new processor. > > Please have a look at the existing chipsets. I suggest having a look at > the i945 northbridge and ich7 southbridge code. > > Expect a new chipset/processor combination to be around 6-12 months of > (fulltime) work, depending on your level of expertize. > I may be interested in funding the right person (or small team) to accelerate the completion of the coreboot work for Sandy Bridge. Is there a more appropriate (or better) way for me to find and fund the expert to do the work? Thanks! Regards, --John > > Also with my limited understanding of coreboot as of now I am assuming we > > should be able to use standard linux > > device drivers to support devices on our board. Is that correct? > > Yes, you can use the same Linux drivers that you use on a non-coreboot > system. They won't help you with the hardware initialization that > coreboot does, though. > > Stefan > From joe at settoplinux.org Mon Apr 4 01:26:32 2011 From: joe at settoplinux.org (Joseph Smith) Date: Sun, 03 Apr 2011 19:26:32 -0400 Subject: [coreboot] [PATCH] FILO: USB_DISK by default should be disabled (trivial) In-Reply-To: References: Message-ID: <4D990228.1020404@settoplinux.org> On 04/03/2011 02:49 PM, Tadas Slotkus wrote: > Hello, > > This is my first patch, so please don't throw stones to me :) > "config USB_DISK" should somehow depend on libpayload's "config USB" at > least, but I don't know how to hardcode it, so I make USB disk to be > disabled, since USB is disabled by default. It would be great if you > could suggest how to link that dependency. > Maybe instead libpayloads USB options should be enabled by default? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From nathan at traverse.com.au Mon Apr 4 03:36:13 2011 From: nathan at traverse.com.au (Nathan Williams) Date: Mon, 04 Apr 2011 11:36:13 +1000 Subject: [coreboot] [PATCH] FILO: Utility for generating an Artecboot image Message-ID: <1301880973.12222.20.camel@dualcore.traverse> This program outputs a binary file with artecboot header and Linux kernel that can be used with the FILO Artecboot loader. Signed-off-by: Nathan Williams --- /dev/null +++ util/artecimage.c @@ -0,0 +1,200 @@ +#include +#include +#include + +#define PROG_NAME "artecimage" +#define VERSION "1.1" + +#define BUFSIZE 512 + +// Artecboot header, gives information to loader + +#define ARTECBOOT_HEADER_MAGIC 0x10ADFACE +#define CURRENT_VERSION 0x0102 + +#define OS_UNKNOWN 0x00 +#define OS_LINUX 0x01 +#define OS_WINCE 0x02 + +#define FLAG_INITRD 0x0001 // if set, the loader will provide initrd to kernel +#define FLAG_FILESYSTEM 0x0002 // if set, the loader will use specified file names +#define FLAG_CMDLINE 0x0004 // if set, the loader will pass the new command line + +#define ABOOT_FILE_KERNEL "/kernel" +#define ABOOT_FILE_INITRD "/initrd" +#define ABOOT_FILE_HEADER "/header" + +#define DEV_SECTOR_SIZE 512 +#define DEV_SECTOR_BITS 9 + +typedef struct __attribute__ ((packed)) +{ + unsigned long magicHeader; + unsigned short bootVersion; + unsigned short headerSize; // also kernel image start + unsigned long imageSize; // NB! since 1.02 is the total image/partition size + unsigned long bitFlags; + unsigned short osType; + char cmdLine[256]; + unsigned long kernelStart; // used with Artecboot VFS / NULLFS + unsigned long kernelSize; // used with Artecboot VFS / NULLFS + unsigned long initrdStart; // used with Artecboot VFS / NULLFS + unsigned long initrdSize; // used with Artecboot VFS / NULLFS + char kernelFile[100]; // valid only with FLAG_FILESYSTEM + char initrdFile[100]; // valid only with FLAG_FILESYSTEM + +} ARTECBOOT_HEADER; + +void usage(void); + +int main(int argc, char **argv){ + ARTECBOOT_HEADER bootHdr; + FILE *BINFILE = 0; + FILE *KERNFILE = 0; + FILE *INITRDFILE = 0; + char buf[BUFSIZE]; + int c; + int i; + int verbose = 0; + + /* clear header */ + memset(&bootHdr, 0, sizeof(ARTECBOOT_HEADER)); + + while ((c = getopt(argc, argv, "c:hi:k:o:v")) != -1) { + switch(c) { + case 'c': + if (strlen(optarg) < sizeof(bootHdr.cmdLine)) { + strcpy(bootHdr.cmdLine, optarg); + bootHdr.bitFlags |= FLAG_CMDLINE; + } else { + usage(); + printf("\nCommand line exceeds %d char limit\n", (sizeof(bootHdr.cmdLine) - 1)); + return 1; + } + break; + case 'h': + usage(); + return 0; + break; + case 'i': + INITRDFILE = fopen(optarg,"r"); + if(INITRDFILE == NULL){ + usage(); + printf("\nError: Failed to open file '%s'\n\n", optarg); + return 1; + } + break; + case 'k': + KERNFILE = fopen(optarg,"r"); + if(KERNFILE == NULL){ + usage(); + printf("\nError: Failed to open file '%s'\n\n", optarg); + return 1; + } + break; + case 'o': + BINFILE = fopen(optarg,"w"); + if(BINFILE == NULL){ + usage(); + printf("\nError: Failed to open file '%s'\n\n", optarg); + return 1; + } + break; + case 'v': + verbose = 1; + break; + } + } + if(!BINFILE){ + usage(); + printf("\nError: No output file specified\n\n"); + return 1; + } + + if(!KERNFILE){ + usage(); + printf("\nError: No kernel image specified\n\n"); + return 1; + } + + bootHdr.magicHeader = ARTECBOOT_HEADER_MAGIC; + bootHdr.bootVersion = CURRENT_VERSION; + bootHdr.headerSize = sizeof(ARTECBOOT_HEADER); + + /* Get kernel image size */ + fseek(KERNFILE, 0L, SEEK_END); + bootHdr.imageSize = ftell(KERNFILE); + + bootHdr.kernelSize = bootHdr.imageSize; + bootHdr.kernelStart = DEV_SECTOR_SIZE; + + bootHdr.osType = OS_LINUX; + + if(INITRDFILE){ + /* Get initrd image size */ + fseek(INITRDFILE, 0L, SEEK_END); + bootHdr.initrdSize = ftell(INITRDFILE); + + /* Set INITRD flag */ + bootHdr.bitFlags |= FLAG_INITRD; + + /* Calculate start address (512 boundary) */ + bootHdr.initrdStart = (bootHdr.kernelStart + bootHdr.imageSize); + bootHdr.initrdStart = (bootHdr.initrdStart >> DEV_SECTOR_BITS) + 1; + bootHdr.initrdStart <<= DEV_SECTOR_BITS; + } + + fwrite(&bootHdr, 1, sizeof(ARTECBOOT_HEADER), BINFILE); + fseek(BINFILE, bootHdr.kernelStart, SEEK_SET); + + /* Copy kernel into output file */ + fseek(KERNFILE, 0, SEEK_SET); + while((i = fread(&buf, 1, BUFSIZE, KERNFILE)) != 0){ + fwrite(&buf, 1, i, BINFILE); + } + fclose(KERNFILE); + + if(INITRDFILE){ + fseek(BINFILE, bootHdr.initrdStart, SEEK_SET); + + /* Copy initrd into output file */ + fseek(INITRDFILE, 0, SEEK_SET); + while((i = fread(&buf, 1, BUFSIZE, INITRDFILE)) != 0){ + fwrite(&buf, 1, i, BINFILE); + } + fclose(INITRDFILE); + } + + fclose(BINFILE); + + if(verbose){ + printf("magicHeader: 0x%04lx\n", bootHdr.magicHeader); + printf("bootVersion: 0x%04x\n", bootHdr.bootVersion); + printf("headerSize: 0x%08x\n", bootHdr.headerSize); + printf("imageSize: 0x%08lx\n", bootHdr.imageSize); + printf("bitFlags: 0x%08lx\n", bootHdr.bitFlags); + printf("osType: 0x%04x\n", bootHdr.osType); + printf("cmdLine: %s\n", bootHdr.cmdLine); + printf("kernelStart: 0x%08lx\n", bootHdr.kernelStart); + printf("kernelSize: 0x%08lx\n", bootHdr.imageSize); + printf("initrdStart: 0x%08lx\n", bootHdr.initrdStart); + printf("initrdSize: 0x%08lx\n", bootHdr.initrdSize); + printf("kernelFile: %s\n", bootHdr.kernelFile); + printf("initrdFile: %s\n", bootHdr.initrdFile); + } + return 0; +} + +void usage(void) { + printf(PROG_NAME " v" VERSION "\n" + "Usage: " PROG_NAME " [-hv] [-c cmdline] [-i initrd] -k kernel -o outfile\n\n" + "Options:\n" + " -c cmdline Kernel command line (max 255 chars).\n" + " -h Display this help.\n" + " -i initrd initrd filename.\n" + " -k kernel Linux kernel filename.\n" + " -o outfile Write image to outfile.\n" + " -v Verbose.\n" + ); + return; +} From tpike1296 at aim.com Mon Apr 4 03:04:21 2011 From: tpike1296 at aim.com (X) Date: Sun, 3 Apr 2011 21:04:21 -0400 (EDT) Subject: [coreboot] Is my laptop supported? (gateway 450SX4) Message-ID: <8CDC07B5DBC5F45-468-15DA7@webmail-d090.sysops.aol.com> I am having a hard time figuring out if my laptop is supported...it is a gateway 450SX4 NS PC87391 LPC super I/O controller Intel? 845MZ chipset (MCH-M+ICH3-M) lspci -tvnn output: lspci -tvnn -[0000:00]-+-00.0 Intel Corporation 82845 845 [Brookdale] Chipset Host Bridge [8086:1a30] +-01.0-[01]----00.0 ATI Technologies Inc Radeon Mobility M6 LY [1002:4c59] +-1d.0 Intel Corporation 82801CA/CAM USB Controller #1 [8086:2482] +-1d.1 Intel Corporation 82801CA/CAM USB Controller #2 [8086:2484] +-1e.0-[02-0a]--+-[0000:03]---00.0 Atheros Communications Inc. AR2413 802.11bg NIC [168c:001a] | \-[0000:02]-+-02.0 Texas Instruments PCI1520 PC card Cardbus Controller [104c:ac55] | +-02.1 Texas Instruments PCI1520 PC card Cardbus Controller [104c:ac55] | +-03.0 ESS Technology ES1988 Allegro-1 [125d:1988] | \-05.0 Texas Instruments TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link) [104c:8026] +-1f.0 Intel Corporation 82801CAM ISA Bridge (LPC) [8086:248c] +-1f.1 Intel Corporation 82801CAM IDE U100 Controller [8086:248a] \-1f.3 Intel Corporation 82801CA/CAM SMBus Controller [8086:2483] Flashrom-v reports this: flashrom v0.9.2-r1141 on Linux 2.6.32-5-686 (i686), built with libpci 3.1.7, GCC 4.4.5 20100728 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1223M loops per second, 10 myus = 10 us, 100 myus = 94 us, 1000 myus = 1076 us, 10000 myus = 9857 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Gateway " DMI string system-product-name: "Gateway 450 " DMI string system-version: "Rev 1 " DMI string baseboard-manufacturer: "Gateway " DMI string baseboard-product-name: "Gateway 450 " DMI string baseboard-version: "Rev 1.0 " DMI string chassis-type: "Notebook" Laptop detected via DMI ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. BIOS info reported by gateway: BIOS Phoenix BIOS 512-KB Flash ROM SMBIOS 2.3 support ACPI 1.0b support APM 1.2 Wired for Management 2.0 (WfM 2.0) my CPU info: Packaging: Intel socketable micro-FCPGA Model name: Mobile Intel(R) Pentium(R) 4 - M CPU 2.00GHz Frequency: 2000Mhz L2 Cache: 512kb Bogomips: 3989.06 Numbering: family(15) model(2) stepping(7) flags: fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe up pebs bts cid Front Side Bus: 400 MHz front side bus any help is appreciated...and i will help in any way I can. -------------- next part -------------- An HTML attachment was scrubbed... URL: From corey.osgood at gmail.com Mon Apr 4 05:48:59 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Sun, 3 Apr 2011 23:48:59 -0400 Subject: [coreboot] Is my laptop supported? (gateway 450SX4) In-Reply-To: <8CDC07B5DBC5F45-468-15DA7@webmail-d090.sysops.aol.com> References: <8CDC07B5DBC5F45-468-15DA7@webmail-d090.sysops.aol.com> Message-ID: Sorry, your laptop is not supported, and unfortunately probably never will be. Most laptops have an embedded controller, it's what controls the screen brightness, lid actions, battery charging, etc, and most manufacturers of embedded controllers are very reluctant to give out the datasheets for them, especially for use in an open-source project, and almost definitely in a case where the particular chip is discontinued, because it means no profit from the exposure of the code. -Corey On Sun, Apr 3, 2011 at 9:04 PM, X wrote: > > I am having a hard time figuring out if my laptop is supported...it is a > gateway 450SX4 > > NS PC87391 LPC super I/O controller > Intel? 845MZ chipset (MCH-M+ICH3-M) > > > lspci -tvnn output: > > lspci -tvnn > -[0000:00]-+-00.0? Intel Corporation 82845 845 [Brookdale] Chipset Host > Bridge [8086:1a30] > ?????????? +-01.0-[01]----00.0? ATI Technologies Inc Radeon Mobility M6 LY > [1002:4c59] > ?????????? +-1d.0? Intel Corporation 82801CA/CAM USB Controller #1 > [8086:2482] > ?????????? +-1d.1? Intel Corporation 82801CA/CAM USB Controller #2 > [8086:2484] > ?????????? +-1e.0-[02-0a]--+-[0000:03]---00.0? Atheros Communications Inc. > AR2413 802.11bg NIC [168c:001a] > ?????????? |?????????????? \-[0000:02]-+-02.0? Texas Instruments PCI1520 PC > card Cardbus Controller [104c:ac55] > ?????????? |?????????????????????????? +-02.1? Texas Instruments PCI1520 PC > card Cardbus Controller [104c:ac55] > ?????????? |?????????????????????????? +-03.0? ESS Technology ES1988 > Allegro-1 [125d:1988] > ?????????? |?????????????????????????? \-05.0? Texas Instruments TSB43AB21 > IEEE-1394a-2000 Controller (PHY/Link) [104c:8026] > ?????????? +-1f.0? Intel Corporation 82801CAM ISA Bridge (LPC) [8086:248c] > ?????????? +-1f.1? Intel Corporation 82801CAM IDE U100 Controller > [8086:248a] > ?????????? \-1f.3? Intel Corporation 82801CA/CAM SMBus Controller > [8086:2483] > > > Flashrom-v reports this: > > flashrom v0.9.2-r1141 on Linux 2.6.32-5-686 (i686), built with libpci 3.1.7, > GCC 4.4.5 20100728 (prerelease), little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 1223M loops per > second, 10 myus = 10 us, 100 myus = 94 us, 1000 myus = 1076 us, 10000 myus = > 9857 us, 4 myus = 5 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Gateway???????????????????????? " > DMI string system-product-name: "Gateway 450???????????????????? " > DMI string system-version: "Rev 1?????????????????? " > DMI string baseboard-manufacturer: "Gateway???????????????????????? " > DMI string baseboard-product-name: "Gateway 450???????????????????? " > DMI string baseboard-version: "Rev 1.0???????????????? " > DMI string chassis-type: "Notebook" > Laptop detected via DMI > ======================================================================== > WARNING! You seem to be running flashrom on a laptop. > Laptops, notebooks and netbooks are difficult to support and we recommend > to use the vendor flashing utility. The embedded controller (EC) in these > machines often interacts badly with flashing. > See http://www.flashrom.org/Laptops for details. > > If flash is shared with the EC, erase is guaranteed to brick your laptop > and write may brick your laptop. > Read and probe may irritate your EC and cause fan failure, backlight > failure and sudden poweroff. > You have been warned. > ======================================================================== > Aborting. > > > > > > > BIOS info reported by gateway: > BIOS > > Phoenix BIOS > 512-KB Flash ROM > SMBIOS 2.3 support > ACPI 1.0b support > APM 1.2 > Wired for Management 2.0 (WfM 2.0) > > my CPU info: > > Packaging: Intel socketable micro-FCPGA > Model name: Mobile Intel(R) Pentium(R) 4 - M CPU 2.00GHz > Frequency: 2000Mhz > L2 Cache: 512kb > Bogomips: 3989.06 > Numbering: family(15) model(2) stepping(7) > flags: fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 > clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe up pebs bts cid > > Front Side Bus: 400 MHz front side bus > > any help is appreciated...and i will help in any way I can. > > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From schramp at holmes.nl Mon Apr 4 09:49:23 2011 From: schramp at holmes.nl (Ruud Schramp (DT)) Date: Mon, 4 Apr 2011 09:49:23 +0200 Subject: [coreboot] #176: inteltool: added PCI_DEVICE_ID_INTEL_X44 0x29e0 In-Reply-To: <068.d7cbfff7f125a01181cc843c46331aa0@coreboot.org> References: <053.c7446af4ed9414ee43522415c13b1108@coreboot.org> <068.d7cbfff7f125a01181cc843c46331aa0@coreboot.org> Message-ID: As requested. Signed-off-by: Ruud Schramp -------------- next part -------------- A non-text attachment was scrubbed... Name: inteltool.patch Type: application/octet-stream Size: 2017 bytes Desc: inteltool.patch URL: From schramp at holmes.nl Mon Apr 4 09:53:19 2011 From: schramp at holmes.nl (Ruud Schramp (DT)) Date: Mon, 4 Apr 2011 09:53:19 +0200 Subject: [coreboot] #176: inteltool: added PCI_DEVICE_ID_INTEL_X44 0x29F0 In-Reply-To: <068.d7cbfff7f125a01181cc843c46331aa0@coreboot.org> References: <053.c7446af4ed9414ee43522415c13b1108@coreboot.org> <068.d7cbfff7f125a01181cc843c46331aa0@coreboot.org> Message-ID: Signed-off-by: Ruud Schramp And again as combined patch with PCI-ID 0x29E0 and 0x29F0 -------------- next part -------------- A non-text attachment was scrubbed... Name: inteltool.patch Type: application/octet-stream Size: 2777 bytes Desc: inteltool.patch URL: From svn at coreboot.org Mon Apr 4 12:56:52 2011 From: svn at coreboot.org (repository service) Date: Mon, 04 Apr 2011 12:56:52 +0200 Subject: [coreboot] [commit] r6475 - trunk/src/mainboard/lenovo/x60 Message-ID: Author: svens Date: Mon Apr 4 12:56:52 2011 New Revision: 6475 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6475 Log: X60: deassert audio mute on boot Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/mainboard/lenovo/x60/mainboard.c Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Fri Apr 1 09:41:47 2011 (r6474) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 12:56:52 2011 (r6475) @@ -74,6 +74,9 @@ ec_write(0x13, 0xff); ec_write(0x14, 0xf4); ec_write(0x15, 0x3c); + + /* enable Audio */ + ec_clr_bit(0x3a, 0); } struct chip_operations mainboard_ops = { From svn at coreboot.org Mon Apr 4 12:57:10 2011 From: svn at coreboot.org (repository service) Date: Mon, 04 Apr 2011 12:57:10 +0200 Subject: [coreboot] [commit] r6476 - trunk/src/mainboard/lenovo/x60 Message-ID: Author: svens Date: Mon Apr 4 12:57:06 2011 New Revision: 6476 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6476 Log: X60: we have ACPI_RESUME Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/mainboard/lenovo/x60/Kconfig Modified: trunk/src/mainboard/lenovo/x60/Kconfig ============================================================================== --- trunk/src/mainboard/lenovo/x60/Kconfig Mon Apr 4 12:56:52 2011 (r6475) +++ trunk/src/mainboard/lenovo/x60/Kconfig Mon Apr 4 12:57:06 2011 (r6476) @@ -22,6 +22,7 @@ select CHANNEL_XOR_RANDOMIZATION select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME config MAINBOARD_DIR string From svn at coreboot.org Mon Apr 4 12:57:23 2011 From: svn at coreboot.org (repository service) Date: Mon, 04 Apr 2011 12:57:23 +0200 Subject: [coreboot] [commit] r6477 - trunk/src/mainboard/lenovo/x60 Message-ID: Author: svens Date: Mon Apr 4 12:57:17 2011 New Revision: 6477 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6477 Log: X60: blink suspend LED during resume Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/mainboard/lenovo/x60/mainboard.c Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 12:57:06 2011 (r6476) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 12:57:17 2011 (r6477) @@ -32,6 +32,7 @@ #include #include #include +#include static void backlight_enable(void) { @@ -50,6 +51,8 @@ static void mainboard_enable(device_t dev) { + device_t dev0; + backlight_enable(); trackpoint_enable(); /* FIXME: this should be ACPI's task @@ -77,6 +80,11 @@ /* enable Audio */ ec_clr_bit(0x3a, 0); + + /* If we're resuming from suspend, blink suspend LED */ + dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); + if (dev0 && pci_read_config32(dev0, SKPAD) == 0xcafed00d) + ec_write(0x0c, 0xc7); } struct chip_operations mainboard_ops = { From svn at coreboot.org Mon Apr 4 14:33:55 2011 From: svn at coreboot.org (repository service) Date: Mon, 04 Apr 2011 14:33:55 +0200 Subject: [coreboot] [commit] r6478 - trunk/src/mainboard/lenovo/x60 Message-ID: Author: svens Date: Mon Apr 4 14:33:54 2011 New Revision: 6478 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6478 Log: X60: log firmware version Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/mainboard/lenovo/x60/mainboard.c Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 12:57:17 2011 (r6477) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 14:33:54 2011 (r6478) @@ -51,7 +51,24 @@ static void mainboard_enable(device_t dev) { + unsigned char ecfw[9], c; + u16 fwvh, fwvl; device_t dev0; + int i; + + for(i = 0; i < 8; i++) { + c = ec_read(0xf0 + i); + if (c < 0x20 || c > 0x7f) + break; + ecfw[i] = c; + } + ecfw[i] = '\0'; + + fwvh = ec_read(0xe9); + fwvl = ec_read(0xe8); + + printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); backlight_enable(); trackpoint_enable(); From svn at coreboot.org Mon Apr 4 16:00:01 2011 From: svn at coreboot.org (coreboot tracker) Date: Mon, 04 Apr 2011 16:00:01 +0200 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From svn at coreboot.org Mon Apr 4 17:19:59 2011 From: svn at coreboot.org (repository service) Date: Mon, 04 Apr 2011 17:19:59 +0200 Subject: [coreboot] [commit] r6479 - trunk/src/mainboard/lenovo/x60/acpi Message-ID: Author: svens Date: Mon Apr 4 17:19:59 2011 New Revision: 6479 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6479 Log: X60: assert audio mute before entering Suspend Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl trunk/src/mainboard/lenovo/x60/acpi/platform.asl Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/ec.asl Mon Apr 4 14:33:54 2011 (r6478) +++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl Mon Apr 4 17:19:59 2011 (r6479) @@ -35,6 +35,8 @@ HSPA, 1, Offset (0x0C), LEDS, 8, /* LED state */ + Offset (0x3a), + AMUT, 1, /* Audio Mute */ Offset (0x3B), , 1, KBLT, 1, /* Keyboard Light */ @@ -66,6 +68,11 @@ { } + Method (MUTE, 1, NotSerialized) + { + Store(Arg0, AMUT) + } + /* Sleep Button pressed */ Method(_Q13, 0, NotSerialized) { Modified: trunk/src/mainboard/lenovo/x60/acpi/platform.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/platform.asl Mon Apr 4 14:33:54 2011 (r6478) +++ trunk/src/mainboard/lenovo/x60/acpi/platform.asl Mon Apr 4 17:19:59 2011 (r6479) @@ -67,8 +67,7 @@ Method(_PTS,1) { - // Call a trap so SMI can prepare for Sleep as well. - // TRAP(0x55) + \_SB.PCI0.LPCB.EC.MUTE(1) } /* The _WAK method is called on system wakeup */ From devtadas at gmail.com Mon Apr 4 18:51:52 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Mon, 04 Apr 2011 19:51:52 +0300 Subject: [coreboot] One more student would like to participate in GSoC Message-ID: <1301935912.13738.30.camel@ts-laptop> Hello, I am a student at Kaunas University of Technology in Lithuania, studying Informatics Engineering second course and I would love to participate in GSoC. I have received some datasheets from VIA for unsupported chipsets, I would like port them. I have good soldering skills and am able to make small printed circuit boards. Some of my homemade art PCBs: http://www.papile.projektas.lt/imgs/usb/ So I have to setup a convenient flashing system for future development which would be brick unaware. I am interested in these ideas: 1) flashrom remote flashing with modified SerialICE - needs to add flashing functionality. With SerialICE we won't need RAM working, so it will help developing chipset code. After reset SerialICE flashing part will be activated with dosens of bytes receiveid through serial port, and communication with HOST system will be initiated (HOST system then will send commands for flashing). If SerialICE won't get any bytes from serial port in a few milliseconds it will let the coreboot to run. We would use flashrom's codebase for flashing protocols... 2) flashrom as payload - for such implementation we should make a config system where we would choose which flash chip(s) are needed to be included in our payload's build. The rom image might be transferred through serial port. But payload needs RAM, so this idea is in discussion list. The first idea would be the primary objective for me. What do you think? Thanks, Tadas Slotkus P.S. I have been around coreboot for some time. My earlier email in mailing-lists: mrtadis at gmail.com, current irc nick: mrtadis) From marcj303 at gmail.com Mon Apr 4 19:56:16 2011 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 4 Apr 2011 11:56:16 -0600 Subject: [coreboot] One more student would like to participate in GSoC In-Reply-To: <1301935912.13738.30.camel@ts-laptop> References: <1301935912.13738.30.camel@ts-laptop> Message-ID: On Mon, Apr 4, 2011 at 10:51 AM, Tadas Slotkus wrote: > Hello, > > I am a student at Kaunas University of Technology in Lithuania, studying > Informatics Engineering second course and I would love to participate in > GSoC. > I have received some datasheets from VIA for unsupported chipsets, I > would like port them. > I have good soldering skills and am able to make small printed circuit > boards. Some of my homemade art PCBs: > http://www.papile.projektas.lt/imgs/usb/ > So I have to setup a convenient flashing system for future development > which would be brick unaware. I am interested in these ideas: > > 1) flashrom remote flashing with modified SerialICE - needs to add > flashing functionality. With SerialICE we won't need RAM working, so it > will help developing chipset code. After reset SerialICE flashing part > will be activated with dosens of bytes receiveid through serial port, > and communication with HOST system will be initiated (HOST system then > will send commands for flashing). If SerialICE won't get any bytes from > serial port in a few milliseconds it will let the coreboot to run. We > would use flashrom's codebase for flashing protocols... > > 2) flashrom as payload - for such implementation we should make a config > system where we would choose which flash chip(s) are needed to be > included in our payload's build. The rom image might be transferred > through serial port. But payload needs RAM, so this idea is in > discussion list. > > The first idea would be the primary objective for me. What do you think? > > > Thanks, > Tadas Slotkus > P.S. I have been around coreboot for some time. My earlier email in > mailing-lists: mrtadis at gmail.com, current irc nick: mrtadis) > Hi Tadas, We are happy that you are interested in a coreboot GSoC project. You have an interesting idea. Have you tried running SerialICE on a platform? I think that the main items you will need to consider in your proposal is the integration of SerialICE and coreboot. How will the early bootblock sections work? On the flashrom side, you will need to consider what the normal OS and library calls will do in this mode. Also, how will it integrate with flashrom so that it stays up to date with current chipsets and flash devices. Marc -- http://se-eng.com From stefan.reinauer at coreboot.org Mon Apr 4 21:43:28 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Mon, 4 Apr 2011 21:43:28 +0200 Subject: [coreboot] [PATCH] FILO: USB_DISK by default should be disabled (trivial) In-Reply-To: <4D990228.1020404@settoplinux.org> References: <4D990228.1020404@settoplinux.org> Message-ID: <20110404194328.GA16977@coreboot.org> * Joseph Smith [110404 01:26]: > On 04/03/2011 02:49 PM, Tadas Slotkus wrote: > >Hello, > > > >This is my first patch, so please don't throw stones to me :) > >"config USB_DISK" should somehow depend on libpayload's "config USB" at > >least, but I don't know how to hardcode it, so I make USB disk to be > >disabled, since USB is disabled by default. It would be great if you > >could suggest how to link that dependency. > > > Maybe instead libpayloads USB options should be enabled by default? Yeah, that sounds like a better idea From stefan.reinauer at coreboot.org Mon Apr 4 21:59:49 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Mon, 4 Apr 2011 21:59:49 +0200 Subject: [coreboot] [commit] r6478 - trunk/src/mainboard/lenovo/x60 In-Reply-To: References: Message-ID: <20110404195949.GB16977@coreboot.org> Sven, could you put this in a separate function called by mainboard enable? e.g. print_ec_version() or some such. * repository service [110404 14:33]: > Modified: trunk/src/mainboard/lenovo/x60/mainboard.c > ============================================================================== > --- trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 12:57:17 2011 (r6477) > +++ trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 14:33:54 2011 (r6478) > @@ -51,7 +51,24 @@ > > static void mainboard_enable(device_t dev) > { > + unsigned char ecfw[9], c; > + u16 fwvh, fwvl; > device_t dev0; > + int i; > + > + for(i = 0; i < 8; i++) { > + c = ec_read(0xf0 + i); > + if (c < 0x20 || c > 0x7f) > + break; > + ecfw[i] = c; > + } > + ecfw[i] = '\0'; > + > + fwvh = ec_read(0xe9); > + fwvl = ec_read(0xe8); > + > + printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, > + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); > > backlight_enable(); > trackpoint_enable(); > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From cubicool at gmail.com Tue Apr 5 01:07:21 2011 From: cubicool at gmail.com (Jeremy Moles) Date: Mon, 04 Apr 2011 19:07:21 -0400 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U Message-ID: <1301958441.2587.11.camel@lv-426> Hello everyone. I have my hands on a piece of hardware here using the Super I/O device listed in the subject; that is: Winbond LPC Super I/O WPCN381U - My first question is, has anyone else encountered this device? - SVN trunk of superiotool detects this device as: Found NSC PC87382 (sid=0xf4, srid=0x04) at 0x2e ...and I know from the manufacturer that the device is actually the one mentioned previously. However, I know from the specsheet that the hardware is pin-compatible with the Winbond PC87381, which has a very similar name to the device it "thinks" it is. http://www.winbond-usa.com/products/winbond_products/pdfs/APC/WPCN381U_pba.pdf Does this mean that superiotool is actually detecting it properly? - Finally, the device I want to use waits for input via the serial port, but before this can be initiated the device must be powered on via the Super I/O module. According to the manufacturer, I do this by activating the GPIO03 pin. I know superiotool is a read-only tool, given I know these pieces of data, is there an easy way to ping this particular bit? - My first approach to enable this device was to write a small kernel module that would call gpio_request(3); however, this always returns -ENOSYS or -EINVAL. This clearly isn't the right approach. :) I realize this is probably a question for LKML proper, but I figured I'd ask here first and see what the Fates have in store. :) From shiyamhoda at gmail.com Tue Apr 5 04:01:59 2011 From: shiyamhoda at gmail.com (Mohammad Hoda) Date: Tue, 5 Apr 2011 07:31:59 +0530 Subject: [coreboot] coreboot Digest, Vol 74, Issue 10 In-Reply-To: References: Message-ID: Hi there! Found about coreboot on GSoC. I would like to do your project, but to be frank I am completely blank. I have no idea what so ever about embedded programming. Do I stand any chance in getting a project for GSoC? even if I don't I would like to stay in touch, and learn. Thanks Mohammad -- Mohammad Jamilish Shiyamul Hoda ???? ???? ????? ????? ??????? ?????? ??????? ???? ???????? ??????? ??????? ???? From shiyamhoda at gmail.com Tue Apr 5 04:03:38 2011 From: shiyamhoda at gmail.com (Mohammad Hoda) Date: Tue, 5 Apr 2011 07:33:38 +0530 Subject: [coreboot] coreboot Digest, Vol 74, Issue 10 In-Reply-To: References: Message-ID: sorry forgot to change the subject On 05/04/2011, Mohammad Hoda wrote: > Hi there! > Found about coreboot on GSoC. I would like to do your project, but to > be frank I am completely blank. I have no idea what so ever about > embedded programming. > Do I stand any chance in getting a project for GSoC? > even if I don't I would like to stay in touch, and learn. > Thanks > Mohammad > > -- > Mohammad Jamilish Shiyamul Hoda > ???? ???? ????? ????? > ??????? ?????? ??????? ???? > ???????? ??????? ??????? ???? > -- Mohammad Jamilish Shiyamul Hoda ???? ???? ????? ????? ??????? ?????? ??????? ???? ???????? ??????? ??????? ???? From marcj303 at gmail.com Tue Apr 5 07:00:18 2011 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 4 Apr 2011 23:00:18 -0600 Subject: [coreboot] GSoC Student Dos and Don'ts Message-ID: Students, This is a good read if you are planning to participate in GSoC. http://google-opensource.blogspot.com/2011/03/dos-and-donts-of-google-summer-of-code.html Regards, Marc -- http://se-eng.com From shiyamhoda at gmail.com Tue Apr 5 08:22:05 2011 From: shiyamhoda at gmail.com (Mohammad Hoda) Date: Tue, 5 Apr 2011 06:22:05 +0000 (UTC) Subject: [coreboot] Mohammad Hoda wants to stay in touch on LinkedIn Message-ID: <311962054.532164.1301984525830.JavaMail.app@ela4-bed82.prod> LinkedIn ------------ I'd like to add you to my professional network on LinkedIn. - Mohammad Hoda Mohammad Hoda Student at West Bengal University of Technology India Confirm that you know Mohammad Hoda https://www.linkedin.com/e/onyp92-gm4fyxok-6a/isd/2636061642/w4SREZdq/ -- (c) 2011, LinkedIn Corporation -------------- next part -------------- An HTML attachment was scrubbed... URL: From gregg.drwho8 at gmail.com Tue Apr 5 08:27:21 2011 From: gregg.drwho8 at gmail.com (Gregg Levine) Date: Tue, 5 Apr 2011 02:27:21 -0400 Subject: [coreboot] Mohammad Hoda wants to stay in touch on LinkedIn In-Reply-To: <311962054.532164.1301984525830.JavaMail.app@ela4-bed82.prod> References: <311962054.532164.1301984525830.JavaMail.app@ela4-bed82.prod> Message-ID: On Tue, Apr 5, 2011 at 2:22 AM, Mohammad Hoda wrote: > > LinkedIn > > I'd like to add you to my professional network on LinkedIn. > > - Mohammad Hoda > > Mohammad Hoda > Student at West Bengal University of Technology > India > > Confirm that you know Mohammad > > ? 2011, LinkedIn Corporation > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot Hello! Please don't do that! You'll violate your agreements with them about six ways from next week, and get you thrown out of the grouping there. It's against their rules to send out your invites to people via a mail list such as this. And only time will tell as to what can happen next regarding what else you are planning on doing in this list. ----- Gregg C Levine gregg.drwho8 at gmail.com "This signature fought the Time Wars, time and again." From hamo.by at gmail.com Tue Apr 5 11:30:00 2011 From: hamo.by at gmail.com (Hamo) Date: Tue, 5 Apr 2011 17:30:00 +0800 Subject: [coreboot] [RFC][PATCH]add EXPERIMENTAL config entry Message-ID: Add EXPERIMENTAL config entry so that we can make all ARM-related entries depend on this now. We need to make all the ARM-related code available to ALL so that we can attract those interested in ARM to join us. During this process, some of the code may not be usable, so we need this to ensure that those normal users will not be upset with it. Signed-off-by: Yang Hamo Bai Index: src/Kconfig =================================================================== --- src/Kconfig (revision 6479) +++ src/Kconfig (working copy) @@ -21,6 +21,12 @@ menu "General setup" +config EXPERIMENTAL + bool "Prompt for developement and/or incomplete code" + default n + help + Some of the various things that Coreboot supports can be in a state of development where the functionality, stability, or the level of testing is not yet high enough fro general use. + config EXPERT bool "Expert mode" help From joe at settoplinux.org Tue Apr 5 14:18:43 2011 From: joe at settoplinux.org (Joseph Smith) Date: Tue, 05 Apr 2011 08:18:43 -0400 Subject: [coreboot] [RFC][PATCH]add EXPERIMENTAL config entry In-Reply-To: References: Message-ID: On Tue, 5 Apr 2011 17:30:00 +0800, Hamo wrote: > Add EXPERIMENTAL config entry so that we can make all ARM-related > entries depend on this now. > We need to make all the ARM-related code available to ALL so that we > can attract those interested in ARM to join us. During this process, > some of the code may not be usable, so we need this to ensure that > those normal users will not be upset with it. > > Signed-off-by: Yang Hamo Bai > > Index: src/Kconfig > =================================================================== > --- src/Kconfig (revision 6479) > +++ src/Kconfig (working copy) > @@ -21,6 +21,12 @@ > > menu "General setup" > > +config EXPERIMENTAL > + bool "Prompt for developement and/or incomplete code" > + default n > + help > + Some of the various things that Coreboot supports can be in a > state of development where the functionality, stability, or the level > of testing is not yet high enough fro general use. > + > config EXPERT > bool "Expert mode" > help > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot It is nice for everyone to have access to work in progress code but I am going to have to nak this only because config EXPERIMENTAL is way to broad and it opens the door for everyone to submit their half backed code arm or not. Then we end up with a tree full of unfinished code. I would consider acking something like config WIP_ARM or EXPERIMENTAL_ARM only because I would be really happy to see arm support. Sorry. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From svn at coreboot.org Tue Apr 5 15:00:15 2011 From: svn at coreboot.org (repository service) Date: Tue, 05 Apr 2011 15:00:15 +0200 Subject: [coreboot] [commit] r6480 - trunk/src/mainboard/lenovo/x60 Message-ID: Author: svens Date: Tue Apr 5 15:00:14 2011 New Revision: 6480 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6480 Log: X60: move ec version info code to log_ec_version() Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/mainboard/lenovo/x60/mainboard.c Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 17:19:59 2011 (r6479) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Tue Apr 5 15:00:14 2011 (r6480) @@ -49,11 +49,10 @@ ec_write(0x3a, 0x20); } -static void mainboard_enable(device_t dev) +static void log_ec_version(void) { unsigned char ecfw[9], c; u16 fwvh, fwvl; - device_t dev0; int i; for(i = 0; i < 8; i++) { @@ -69,9 +68,17 @@ printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); +} + +static void mainboard_enable(device_t dev) +{ + device_t dev0; + + log_ec_version(); backlight_enable(); trackpoint_enable(); + /* FIXME: this should be ACPI's task * but for now, enable it here */ wlan_enable(); From svn at coreboot.org Tue Apr 5 15:00:34 2011 From: svn at coreboot.org (repository service) Date: Tue, 05 Apr 2011 15:00:34 +0200 Subject: [coreboot] [commit] r6481 - trunk/src/mainboard/lenovo/x60 Message-ID: Author: svens Date: Tue Apr 5 15:00:33 2011 New Revision: 6481 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6481 Log: X60: use pnp_write_config() instead of custom function Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/mainboard/lenovo/x60/romstage.c Modified: trunk/src/mainboard/lenovo/x60/romstage.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/romstage.c Tue Apr 5 15:00:14 2011 (r6480) +++ trunk/src/mainboard/lenovo/x60/romstage.c Tue Apr 5 15:00:33 2011 (r6481) @@ -101,25 +101,20 @@ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); } -static void pnp_write_register(device_t dev, int reg, int val) -{ - unsigned int port = dev >> 8; - outb(reg, port); - outb(val, port+1); -} - static void early_superio_config(void) { - device_t dev; + int timeout = 100000; + device_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0x06); - dev=PNP_DEV(0x2e, 0x00); - pnp_write_register(dev, 0x29, 0x06); + while(!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) + udelay(1000); /* Enable COM1 */ - pnp_write_register(dev, 0x07, 0x03); - pnp_write_register(dev, 0x60, 0x03); - pnp_write_register(dev, 0x61, 0xf8); - pnp_write_register(dev, 0x30, 0x01); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); } static void rcba_config(void) From svens at stackframe.org Tue Apr 5 15:08:06 2011 From: svens at stackframe.org (Sven Schnelle) Date: Tue, 05 Apr 2011 15:08:06 +0200 Subject: [coreboot] [commit] r6478 - trunk/src/mainboard/lenovo/x60 In-Reply-To: <20110404195949.GB16977@coreboot.org> (Stefan Reinauer's message of "Mon\, 4 Apr 2011 21\:59\:49 +0200") References: <20110404195949.GB16977@coreboot.org> Message-ID: <8739lwdex5.fsf@begreifnix.stackframe.org> Hi Stefan, Stefan Reinauer writes: > Sven, could you put this in a separate function called by mainboard > enable? e.g. print_ec_version() or some such. Good idea. Committed as r6480. Thanks, Sven. From scouter389 at gmail.com Tue Apr 5 15:12:14 2011 From: scouter389 at gmail.com (James Wall) Date: Tue, 5 Apr 2011 08:12:14 -0500 Subject: [coreboot] I865 memory controller status Message-ID: Hello all, What is the status of the i865 memory controller? I have a board that all the other chips are supported but the memory controller is a big question mark. -------------- next part -------------- An HTML attachment was scrubbed... URL: From vidwer at gmail.com Tue Apr 5 16:02:56 2011 From: vidwer at gmail.com (Idwer Vollering) Date: Tue, 5 Apr 2011 16:02:56 +0200 Subject: [coreboot] I865 memory controller status In-Reply-To: References: Message-ID: 2011/4/5 James Wall : > Hello all, > What is the status of the i865 memory controller? That chipset as a whole is (currently) unsupported, however plans to support it are there. RAM init is work in progress, another developer and I have a total of three i865 boards. Since RAM init is the hardest part, and we don't work on it full time, support can be expected anything but soon. All I have at this moment is nonworking code, it dies/stops in the beginning of RAM init. I expect to be working on this somewhat more frequent/intensive in two or three weeks. Idwer > I have a board that all the other chips are supported but the memory controller is a > big question mark. > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From scouter389 at gmail.com Tue Apr 5 16:38:14 2011 From: scouter389 at gmail.com (James Wall) Date: Tue, 5 Apr 2011 09:38:14 -0500 Subject: [coreboot] I865 memory controller status In-Reply-To: References: Message-ID: On Apr 5, 2011 9:02 AM, "Idwer Vollering" wrote: > > 2011/4/5 James Wall : > > Hello all, > > What is the status of the i865 memory controller? > > That chipset as a whole is (currently) unsupported, however plans to > support it are there. > RAM init is work in progress, another developer and I have a total of > three i865 boards. Since RAM init is the hardest part, and we don't > work on it full time, support can be expected anything but soon. > > All I have at this moment is nonworking code, it dies/stops in the > beginning of RAM init. I expect to be working on this somewhat more > frequent/intensive in two or three weeks. > > Idwer I am willing to test but I have very little coding knowledge, mostly bash scripts and hello world c programming skills. > > I have a board that all the other chips are supported but the memory controller is a > big question mark. > > > > -- > > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From corey.osgood at gmail.com Tue Apr 5 18:25:35 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Tue, 5 Apr 2011 12:25:35 -0400 Subject: [coreboot] I865 memory controller status In-Reply-To: References: Message-ID: On Tue, Apr 5, 2011 at 10:38 AM, James Wall wrote: > > On Apr 5, 2011 9:02 AM, "Idwer Vollering" wrote: >> >> 2011/4/5 James Wall : >> > Hello all, >> > What is the status of the i865 memory controller? >> >> That chipset as a whole is (currently) unsupported, however plans to >> support it are there. >> RAM init is work in progress, another developer and I have a total of >> three i865 boards. Since RAM init is the hardest part, and we don't >> work on it full time, support can be expected anything but soon. >> >> All I have at this moment is nonworking code, it dies/stops in the >> beginning of RAM init. I expect to be working on this somewhat more >> frequent/intensive in two or three weeks. >> >> Idwer > > I am willing to test but I have very little coding knowledge, mostly bash > scripts and hello world c programming skills. Well most of coreboot coding is pci_write_configX(whatever the datasheet tells you). The hard part is figuring out all the stuff the datasheet doesn't tell you :( -Corey From joe at settoplinux.org Tue Apr 5 18:38:13 2011 From: joe at settoplinux.org (Joseph Smith) Date: Tue, 05 Apr 2011 12:38:13 -0400 Subject: [coreboot] I865 memory controller status In-Reply-To: References: Message-ID: <4D9B4575.4000801@settoplinux.org> On 04/05/2011 12:25 PM, Corey Osgood wrote: > On Tue, Apr 5, 2011 at 10:38 AM, James Wall wrote: >> >> On Apr 5, 2011 9:02 AM, "Idwer Vollering" wrote: >>> >>> 2011/4/5 James Wall: >>>> Hello all, >>>> What is the status of the i865 memory controller? >>> >>> That chipset as a whole is (currently) unsupported, however plans to >>> support it are there. >>> RAM init is work in progress, another developer and I have a total of >>> three i865 boards. Since RAM init is the hardest part, and we don't >>> work on it full time, support can be expected anything but soon. >>> >>> All I have at this moment is nonworking code, it dies/stops in the >>> beginning of RAM init. I expect to be working on this somewhat more >>> frequent/intensive in two or three weeks. >>> >>> Idwer >> >> I am willing to test but I have very little coding knowledge, mostly bash >> scripts and hello world c programming skills. > > Well most of coreboot coding is pci_write_configX(whatever the > datasheet tells you). The hard part is figuring out all the stuff the > datasheet doesn't tell you :( > Yeah and Intel is great at only giving you half the picture ;-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From scouter389 at gmail.com Wed Apr 6 00:25:36 2011 From: scouter389 at gmail.com (James Wall) Date: Tue, 5 Apr 2011 17:25:36 -0500 Subject: [coreboot] I865 memory controller status In-Reply-To: <4D9B4575.4000801@settoplinux.org> References: <4D9B4575.4000801@settoplinux.org> Message-ID: On Tue, Apr 5, 2011 at 11:38 AM, Joseph Smith wrote: > On 04/05/2011 12:25 PM, Corey Osgood wrote: > >> On Tue, Apr 5, 2011 at 10:38 AM, James Wall wrote: >> >>> >>> On Apr 5, 2011 9:02 AM, "Idwer Vollering" wrote: >>> >>>> >>>> 2011/4/5 James Wall: >>>> >>>>> Hello all, >>>>> What is the status of the i865 memory controller? >>>>> >>>> >>>> That chipset as a whole is (currently) unsupported, however plans to >>>> support it are there. >>>> RAM init is work in progress, another developer and I have a total of >>>> three i865 boards. Since RAM init is the hardest part, and we don't >>>> work on it full time, support can be expected anything but soon. >>>> >>>> All I have at this moment is nonworking code, it dies/stops in the >>>> beginning of RAM init. I expect to be working on this somewhat more >>>> frequent/intensive in two or three weeks. >>>> >>>> Idwer >>>> >>> >>> I am willing to test but I have very little coding knowledge, mostly bash >>> scripts and hello world c programming skills. >>> >> >> Well most of coreboot coding is pci_write_configX(whatever the >> datasheet tells you). The hard part is figuring out all the stuff the >> datasheet doesn't tell you :( >> >> Yeah and Intel is great at only giving you half the picture ;-) > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > I will look at the source code then for more ideas and to help understand the code then. thanks for the information. -------------- next part -------------- An HTML attachment was scrubbed... URL: From vidwer at gmail.com Wed Apr 6 00:33:21 2011 From: vidwer at gmail.com (Idwer Vollering) Date: Wed, 6 Apr 2011 00:33:21 +0200 Subject: [coreboot] I865 memory controller status In-Reply-To: References: <4D9B4575.4000801@settoplinux.org> Message-ID: 2011/4/6 James Wall : > > I will look at the source code then for more ideas and to help understand > the code then. thanks for the information. If you want to help porting, can you produce a serialice log (and send it to Josephd and me, offlist) ? See the website, www.serialice.com for installation instructions. The more output the better. > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From ntlloyd at uncg.edu Wed Apr 6 02:01:15 2011 From: ntlloyd at uncg.edu (Nickolas Lloyd) Date: Tue, 5 Apr 2011 20:01:15 -0400 Subject: [coreboot] [PATCH] Print what mainboard coreboot is being built for during build Message-ID: >From 404e7bd11e3dadf912b45057000e053db5ed7e90 Mon Sep 17 00:00:00 2001 From: Nickolas Lloyd Date: Tue, 5 Apr 2011 19:18:07 -0400 Subject: [PATCH] Print what mainboard coreboot is being built for during build Print a message before and after build saying what mainboard coreboot is being built for. ?Only print after build if build was successful Signed-off-by: Nickolas Lloyd --- ?Makefile ? ? | ? ?1 + ?Makefile.inc | ? ?4 +++- ?2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index 06847b6..ddc12a6 100644 --- a/Makefile +++ b/Makefile @@ -145,6 +145,7 @@ real-all: ?else ?real-all: real-target ?endif + ? ? ? @echo "Built coreboot for $(CONFIG_MAINBOARD_VENDOR) $(CONFIG_MAINBOARD_PART_NUMBER)" ?# must come rather early ?.SECONDEXPANSION: diff --git a/Makefile.inc b/Makefile.inc index 3f553c6..74b4455 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -31,7 +31,9 @@ export MAINBOARDDIR ?####################################################################### ?# root rule to resolve if in build mode (ie. configuration exists) ?real-target: $(obj)/config.h coreboot -coreboot: $(obj)/coreboot.rom +coreboot: building-msg $(obj)/coreboot.rom +building-msg: + ? ? ? @echo "Building coreboot for $(CONFIG_MAINBOARD_VENDOR) $(CONFIG_MAINBOARD_PART_NUMBER)" ?####################################################################### ?# our phony targets -- 1.7.4.1 From paulepanter at users.sourceforge.net Wed Apr 6 09:57:59 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Wed, 06 Apr 2011 09:57:59 +0200 Subject: [coreboot] [PATCH] Print what mainboard coreboot is being built for during build In-Reply-To: References: Message-ID: <1302076679.3893.2.camel@mattotaupa> Dear Nickolas, Am Dienstag, den 05.04.2011, 20:01 -0400 schrieb Nickolas Lloyd: > >From 404e7bd11e3dadf912b45057000e053db5ed7e90 Mon Sep 17 00:00:00 2001 > From: Nickolas Lloyd > Date: Tue, 5 Apr 2011 19:18:07 -0400 > Subject: [PATCH] Print what mainboard coreboot is being built for during build > > Print a message before and after build saying what mainboard coreboot > is being built for. Only print after build if build was successful > > Signed-off-by: Nickolas Lloyd > --- > Makefile | 1 + > Makefile.inc | 4 +++- > 2 files changed, 4 insertions(+), 1 deletions(-) > > diff --git a/Makefile b/Makefile > index 06847b6..ddc12a6 100644 > --- a/Makefile > +++ b/Makefile > @@ -145,6 +145,7 @@ real-all: > else > real-all: real-target > endif > + @echo "Built coreboot for $(CONFIG_MAINBOARD_VENDOR) > $(CONFIG_MAINBOARD_PART_NUMBER)" it looks like, your mailer mangled the patch. Please resend (?[PATCH][RESEND]?) with line breaks turned of in sections with code. > # must come rather early > .SECONDEXPANSION: > diff --git a/Makefile.inc b/Makefile.inc > index 3f553c6..74b4455 100644 > --- a/Makefile.inc > +++ b/Makefile.inc > @@ -31,7 +31,9 @@ export MAINBOARDDIR > ####################################################################### > # root rule to resolve if in build mode (ie. configuration exists) > real-target: $(obj)/config.h coreboot > -coreboot: $(obj)/coreboot.rom > +coreboot: building-msg $(obj)/coreboot.rom > +building-msg: > + @echo "Building coreboot for $(CONFIG_MAINBOARD_VENDOR) > $(CONFIG_MAINBOARD_PART_NUMBER)" > > ####################################################################### > # our phony targets > -- > 1.7.4.1 Thanks, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From andreas.franz at gmail.com Wed Apr 6 10:55:37 2011 From: andreas.franz at gmail.com (Andreas Franz) Date: Wed, 6 Apr 2011 10:55:37 +0200 Subject: [coreboot] VIA EPIA V5000 Problems Message-ID: Hello, I am trying to use Coreboot + Filo + Debian Linux on the VIA EPIA V5000 board. I had no problems compiling and flashing coreboot, but running into trouble when booting. The serial console states the following and than simply stops: vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing NOP PRECHARGE DUMMY READS CBR MRS NORMAL set ref. rate enable multi-page open Slot 00 is SDRAM 08000000 bytes x2 000c is the MA type Slot 01 is empty Slot 02 is empty Slot 03 is empty vt8601 done Loading image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check cmos_layout.bin CBFS: follow chain: fffc0000 + 28 + 487 + align -> fffc04c0 Check pci1106,3230.rom CBFS: follow chain: fffc04c0 + 38 + 10000 + align -> fffd0500 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (114688 bytes), entry @ 0x100000 I guess ist has something to do with RAM-init? Any help/hint is appreciated. Thanks Andreas Franz From hagigatali at gmail.com Wed Apr 6 13:08:39 2011 From: hagigatali at gmail.com (ali hagigat) Date: Wed, 6 Apr 2011 15:38:39 +0430 Subject: [coreboot] where can i ask detailed technical questions about hardware? Message-ID: I wonder if any one knows about some forums or sites for asking questions about the data sheets contents of mother board ICs. I am investing about Intel ICs. Though Intel has some forums but they are inactive and questions remain unanswered. Is there any active site to discuss Intel data sheets? Regards From peter at stuge.se Wed Apr 6 13:19:26 2011 From: peter at stuge.se (Peter Stuge) Date: Wed, 6 Apr 2011 13:19:26 +0200 Subject: [coreboot] where can i ask detailed technical questions about hardware? In-Reply-To: References: Message-ID: <20110406111926.23070.qmail@stuge.se> ali hagigat wrote: > Is there any active site to discuss Intel data sheets? Not really. :\ The proper forum for those discussions would be with your assigned Intel FAE. Of course, then you need to have access to one, which basically requires a large quantity project to make it interesting for Intel to assign some resources. You'll also need to sign a couple of NDAs. Pretty few people in the world have access to the information that is required to write firmware for PCs with Intel components. //Peter From mr.nuke.me at gmail.com Wed Apr 6 13:27:58 2011 From: mr.nuke.me at gmail.com (Alex G.) Date: Wed, 06 Apr 2011 14:27:58 +0300 Subject: [coreboot] where can i ask detailed technical questions about hardware? In-Reply-To: <20110406111926.23070.qmail@stuge.se> References: <20110406111926.23070.qmail@stuge.se> Message-ID: <4D9C4E3E.7070903@gmail.com> On 04/06/2011 02:19 PM, Peter Stuge wrote: > ali hagigat wrote: >> Is there any active site to discuss Intel data sheets? > > Not really. :\ Well, now and then there might be some people on #coreboot that have a nibble of extra knowledge on a specific topic, but nothing that would sum up to the end goal of writing firmware (read "writing firmware for _intel_ hardware"). > You'll also need to sign a couple > of NDAs. Just a couple? I heard it takes way over 6(six) months to get the paperwork done. Alex From peter at stuge.se Wed Apr 6 13:35:03 2011 From: peter at stuge.se (Peter Stuge) Date: Wed, 6 Apr 2011 13:35:03 +0200 Subject: [coreboot] where can i ask detailed technical questions about hardware? In-Reply-To: <4D9C4E3E.7070903@gmail.com> References: <20110406111926.23070.qmail@stuge.se> <4D9C4E3E.7070903@gmail.com> Message-ID: <20110406113503.24720.qmail@stuge.se> Alex G. wrote: > > You'll also need to sign a couple of NDAs. > > Just a couple? Yeah. > I heard it takes way over 6(six) months to get the paperwork done. I guess it depends. I've heard similar from coreboot community, but I've also talked to an Intel (embedded) FAE who had seen customers go through the paperwork in just a few weeks. In general the embedded guys seem to be a little more eager. :) //Peter From hagigatali at gmail.com Wed Apr 6 13:35:19 2011 From: hagigatali at gmail.com (ali hagigat) Date: Wed, 6 Apr 2011 16:05:19 +0430 Subject: [coreboot] where can i ask detailed technical questions about hardware? In-Reply-To: <20110406111926.23070.qmail@stuge.se> References: <20110406111926.23070.qmail@stuge.se> Message-ID: Hello Peter, Thank you very much to respond. I have the necessary data sheets now but some lines of the documents are ambiguous and obscure. I do not want to take up your time much but I wonder if I can ask you these questions. I can send you the data sheets and specify the lines we are going to talk about. Regards PS. If anybody else can help me, please let me know and please specify if I contact you personally or by Coreboot mailing list. On Wed, Apr 6, 2011 at 3:49 PM, Peter Stuge wrote: > ali hagigat wrote: >> Is there any active site to discuss Intel data sheets? > > Not really. :\ > > The proper forum for those discussions would be with your assigned > Intel FAE. Of course, then you need to have access to one, which > basically requires a large quantity project to make it interesting > for Intel to assign some resources. You'll also need to sign a couple > of NDAs. Pretty few people in the world have access to the > information that is required to write firmware for PCs with Intel > components. > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From hamo.by at gmail.com Wed Apr 6 14:20:27 2011 From: hamo.by at gmail.com (Hamo) Date: Wed, 6 Apr 2011 20:20:27 +0800 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry Message-ID: Add WIP_ARM config entry so that we can make all ARM-related entries depend on this now. We need to make all the ARM-related code available to ALL so that we can attract those interested in ARM to join us. During this process, some of the code may not be usable, so we need this to ensure that those normal users will not be upset with it. Signed-off-by: Yang Bai P.S. Can I use git diff to generate the patch? Index: src/Kconfig =================================================================== --- src/Kconfig (revision 6481) +++ src/Kconfig (working copy) @@ -21,6 +21,16 @@ menu "General setup" +config WIP_ARM + bool "Prompt for unfinished ARM options" + default n + help + This will show you the configuration options about Coreboot ARM + support. + + Warning: Since ARM porting is now working in process, the code + for ARM may be not usable. + config EXPERT bool "Expert mode" help From mr.nuke.me at gmail.com Wed Apr 6 15:21:50 2011 From: mr.nuke.me at gmail.com (Alex G.) Date: Wed, 06 Apr 2011 16:21:50 +0300 Subject: [coreboot] where can i ask detailed technical questions about hardware? In-Reply-To: References: <20110406111926.23070.qmail@stuge.se> Message-ID: <4D9C68EE.3090708@gmail.com> If you can redistribute those datasheets, I assume they are not under NDA, which means they are the public datasheets available on Intel's site. If they are public datasheets, you can simply reference the link and the page number. If they are not public, but you have the right to quote them, you may quote the ambiguous sections (within context) on the mailing list. Alex On 04/06/2011 02:35 PM, ali hagigat wrote: > Hello Peter, > > Thank you very much to respond. I have the necessary data sheets now > but some lines of the documents are ambiguous and obscure. I do not > want to take up your time much but I wonder if I can ask you these > questions. I can send you the data sheets and specify the lines we are > going to talk about. > > Regards > PS. If anybody else can help me, please let me know and please specify > if I contact you personally or by Coreboot mailing list. > From mr.nuke.me at gmail.com Wed Apr 6 15:24:35 2011 From: mr.nuke.me at gmail.com (Alex G.) Date: Wed, 06 Apr 2011 16:24:35 +0300 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: References: Message-ID: <4D9C6993.8050108@gmail.com> > P.S. Can I use git diff to generate the patch? Why not? It isn't _that_ difficult to patch -p1 instead of -p0. :) I've seen a few git diff patches flying around, and no one complained. Alex From paulepanter at users.sourceforge.net Wed Apr 6 16:25:13 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Wed, 06 Apr 2011 16:25:13 +0200 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: References: Message-ID: <1302099913.3893.31.camel@mattotaupa> Am Mittwoch, den 06.04.2011, 20:20 +0800 schrieb Hamo: > Add WIP_ARM config entry so that we can make all ARM-related > entries depend on this now. > We need to make all the ARM-related code available to ALL so that we > can attract those interested in ARM to join us. During this process, > some of the code may not be usable, so we need this to ensure that > those normal users will not be upset with it. Would a separate branch ? named for example arm-support ? not be more beneficial and when everything is working merge it into trunk/master? [?] Thanks, Paul > P.S. Can I use git diff to generate the patch? I guess you can even use `git format-patch`. PPS: Is this a good time to move to Git altogether? A mirror already exists. ;-) Since I am not doing any development, I am not the one to make that call. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From hamo.by at gmail.com Wed Apr 6 16:33:10 2011 From: hamo.by at gmail.com (Hamo) Date: Wed, 6 Apr 2011 22:33:10 +0800 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: <1302099913.3893.31.camel@mattotaupa> References: <1302099913.3893.31.camel@mattotaupa> Message-ID: On Wed, Apr 6, 2011 at 10:25 PM, Paul Menzel wrote: > Am Mittwoch, den 06.04.2011, 20:20 +0800 schrieb Hamo: >> Add WIP_ARM config entry so that we can make all ARM-related >> entries depend on this now. >> We need to make all the ARM-related code available to ALL so that we >> can attract those interested in ARM to join us. During this process, >> some of the code may not be usable, so we need this to ensure that >> those normal users will not be upset with it. > > Would a separate branch ? named for example arm-support ? not be more > beneficial and when everything is working merge it into trunk/master? If we just create a new branch, only a few fellows can know that we are porting coreboot to ARM, but if we add a new option, all the people who try to build coreboot will know it. Through this way, we can attract more people working on or testing this. > > [?] > > > Thanks, > > Paul > > >> P.S. Can I use git diff to generate the patch? > > I guess you can even use `git format-patch`. > > PPS: Is this a good time to move to Git altogether? A mirror already > exists. ;-) Since I am not doing any development, I am not the one to > make that call. +1 for move to GIT. > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- ? ? """ ? ? Keep It Simple,Stupid. ? ? """ Chinese Name: ?? Nick Name: Hamo Homepage: http://hamobai.com/ GPG KEY ID: 0xA4691A33 Key fingerprint = 09D5 2D78 8E2B 0995 CF8E? 4331 33C4 3D24 A469 1A33 From mr.nuke.me at gmail.com Wed Apr 6 16:46:57 2011 From: mr.nuke.me at gmail.com (Alex G.) Date: Wed, 06 Apr 2011 17:46:57 +0300 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: <1302099913.3893.31.camel@mattotaupa> References: <1302099913.3893.31.camel@mattotaupa> Message-ID: <4D9C7CE1.9020502@gmail.com> On 04/06/2011 05:25 PM, Paul Menzel wrote: > PPS: Is this a good time to move to Git altogether? A mirror already > exists. ;-) Since I am not doing any development, I am not the one to > make that call. > It's nice to have a git mirror, but contributors shouldn't be forced to use git, especially since subversion has been used for aeons with coreboot. Personally, I would be very unhappy to be forced to use git. -1 to gitification From joe at settoplinux.org Wed Apr 6 18:14:43 2011 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 06 Apr 2011 12:14:43 -0400 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: <4D9C7CE1.9020502@gmail.com> References: <1302099913.3893.31.camel@mattotaupa> <4D9C7CE1.9020502@gmail.com> Message-ID: <4D9C9173.7000306@settoplinux.org> On 04/06/2011 10:46 AM, Alex G. wrote: > On 04/06/2011 05:25 PM, Paul Menzel wrote: >> PPS: Is this a good time to move to Git altogether? A mirror already >> exists. ;-) Since I am not doing any development, I am not the one to >> make that call. >> > It's nice to have a git mirror, but contributors shouldn't be forced to > use git, especially since subversion has been used for aeons with > coreboot. Personally, I would be very unhappy to be forced to use git. > -1 to gitification > > Yes Alex, I prefer svn over git 10 to 1. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From marcj303 at gmail.com Wed Apr 6 18:16:00 2011 From: marcj303 at gmail.com (Marc Jones) Date: Wed, 6 Apr 2011 10:16:00 -0600 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: References: Message-ID: On Wed, Apr 6, 2011 at 6:20 AM, Hamo wrote: > Add WIP_ARM config entry so that we can make all ARM-related > entries depend on this now. > We need to make all the ARM-related code available to ALL so that we > can attract those interested in ARM to join us. During this process, > some of the code may not be usable, so we need this to ensure that > those normal users will not be upset with it. > > Signed-off-by: Yang Bai > > P.S. Can I use git diff to generate the patch? > > Index: src/Kconfig > =================================================================== > --- src/Kconfig (revision 6481) > +++ src/Kconfig (working copy) > @@ -21,6 +21,16 @@ > > ?menu "General setup" > > +config WIP_ARM > + ? ? ? bool "Prompt for unfinished ARM options" > + ? ? ? default n > + ? ? ? help > + ? ? ? ? This will show you the configuration options about Coreboot ARM > + ? ? ? ? support. > + > + ? ? ? ? Warning: Since ARM porting is now working in process, the code > + ? ? ? ? for ARM may be not usable. > + > ?config EXPERT > ? ? ? ?bool "Expert mode" > ? ? ? ?help Hi Hamo, Thank you for the patch, but I think that it is a little early to add this to the tree. You should be able to generate a patch with git diff. You can also share your git development tree if you want to share your development prior to submitting a patch. Marc -- http://se-eng.com From gregg.drwho8 at gmail.com Wed Apr 6 18:17:59 2011 From: gregg.drwho8 at gmail.com (Gregg Levine) Date: Wed, 6 Apr 2011 12:17:59 -0400 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: <4D9C9173.7000306@settoplinux.org> References: <1302099913.3893.31.camel@mattotaupa> <4D9C7CE1.9020502@gmail.com> <4D9C9173.7000306@settoplinux.org> Message-ID: On Wed, Apr 6, 2011 at 12:14 PM, Joseph Smith wrote: > On 04/06/2011 10:46 AM, Alex G. wrote: >> >> On 04/06/2011 05:25 PM, Paul Menzel wrote: >>> >>> PPS: Is this a good time to move to Git altogether? A mirror already >>> exists. ;-) Since I am not doing any development, I am not the one to >>> make that call. >>> >> It's nice to have a git mirror, but contributors shouldn't be forced to >> use git, especially since subversion has been used for aeons with >> coreboot. Personally, I would be very unhappy to be forced to use git. >> -1 to gitification >> >> > Yes Alex, I prefer svn over git 10 to 1. > > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Hello! Even though for some silly reason SVN, and the related #svn update command isn't working (# for prompt of hosting Linux system) on my hosting Linux system, I also prefer it over git. Every time I need to clone someones repository I practically indulge a certain deity with a thought that nothing goes wrong on its behalf. ----- Gregg C Levine gregg.drwho8 at gmail.com "This signature fought the Time Wars, time and again." From stefan.reinauer at coreboot.org Wed Apr 6 18:33:13 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Wed, 6 Apr 2011 18:33:13 +0200 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: <1302099913.3893.31.camel@mattotaupa> References: <1302099913.3893.31.camel@mattotaupa> Message-ID: <20110406163313.GA5484@coreboot.org> * Paul Menzel [110406 16:25]: > Am Mittwoch, den 06.04.2011, 20:20 +0800 schrieb Hamo: > > Add WIP_ARM config entry so that we can make all ARM-related > > entries depend on this now. > > We need to make all the ARM-related code available to ALL so that we > > can attract those interested in ARM to join us. During this process, > > some of the code may not be usable, so we need this to ensure that > > those normal users will not be upset with it. > > Would a separate branch ? named for example arm-support ? not be more > beneficial and when everything is working merge it into trunk/master? Yes! Also, Hamo, please don't start an ARM port by just adding WIP_ARM. It would be nice to see something more substantial than an unused config option. ;) From stefan.reinauer at coreboot.org Wed Apr 6 18:33:51 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Wed, 6 Apr 2011 18:33:51 +0200 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: References: <1302099913.3893.31.camel@mattotaupa> Message-ID: <20110406163351.GB5484@coreboot.org> * Hamo [110406 16:33]: > On Wed, Apr 6, 2011 at 10:25 PM, Paul Menzel > wrote: > > Am Mittwoch, den 06.04.2011, 20:20 +0800 schrieb Hamo: > >> Add WIP_ARM config entry so that we can make all ARM-related > >> entries depend on this now. > >> We need to make all the ARM-related code available to ALL so that we > >> can attract those interested in ARM to join us. During this process, > >> some of the code may not be usable, so we need this to ensure that > >> those normal users will not be upset with it. > > > > Would a separate branch ? named for example arm-support ? not be more > > beneficial and when everything is working merge it into trunk/master? > > If we just create a new branch, only a few fellows can know that we > are porting coreboot to ARM, > but if we add a new option, all the people who try to build coreboot > will know it. Through this way, > we can attract more people working on or testing this. We have the mailing list for letting people know. From stefan.reinauer at coreboot.org Wed Apr 6 18:34:54 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Wed, 6 Apr 2011 18:34:54 +0200 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: References: <1302099913.3893.31.camel@mattotaupa> <4D9C7CE1.9020502@gmail.com> <4D9C9173.7000306@settoplinux.org> Message-ID: <20110406163453.GC5484@coreboot.org> * Gregg Levine [110406 18:17]: > On Wed, Apr 6, 2011 at 12:14 PM, Joseph Smith wrote: > > On 04/06/2011 10:46 AM, Alex G. wrote: > >> > >> On 04/06/2011 05:25 PM, Paul Menzel wrote: > >>> > >>> PPS: Is this a good time to move to Git altogether? A mirror already > >>> exists. ;-) Since I am not doing any development, I am not the one to > >>> make that call. > >>> > >> It's nice to have a git mirror, but contributors shouldn't be forced to > >> use git, especially since subversion has been used for aeons with > >> coreboot. Personally, I would be very unhappy to be forced to use git. > >> -1 to gitification > >> > >> > > Yes Alex, I prefer svn over git 10 to 1. > > > > > > -- > > Thanks, > > Joseph Smith > > Set-Top-Linux > > www.settoplinux.org > > > > -- > > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > > Hello! > Even though for some silly reason SVN, and the related #svn update > command isn't working (# for prompt of hosting Linux system) on my > hosting Linux system, I also prefer it over git. > Gregg, are you behind some kind of corporate firewall? Any error messages? Stefan From gregg.drwho8 at gmail.com Wed Apr 6 18:43:31 2011 From: gregg.drwho8 at gmail.com (Gregg Levine) Date: Wed, 6 Apr 2011 12:43:31 -0400 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: <20110406163453.GC5484@coreboot.org> References: <1302099913.3893.31.camel@mattotaupa> <4D9C7CE1.9020502@gmail.com> <4D9C9173.7000306@settoplinux.org> <20110406163453.GC5484@coreboot.org> Message-ID: On Wed, Apr 6, 2011 at 12:34 PM, Stefan Reinauer wrote: > * Gregg Levine [110406 18:17]: >> On Wed, Apr 6, 2011 at 12:14 PM, Joseph Smith wrote: >> > On 04/06/2011 10:46 AM, Alex G. wrote: >> >> >> >> On 04/06/2011 05:25 PM, Paul Menzel wrote: >> >>> >> >>> PPS: Is this a good time to move to Git altogether? A mirror already >> >>> exists. ;-) Since I am not doing any development, I am not the one to >> >>> make that call. >> >>> >> >> It's nice to have a git mirror, but contributors shouldn't be forced to >> >> use git, especially since subversion has been used for aeons with >> >> coreboot. Personally, I would be very unhappy to be forced to use git. >> >> -1 to gitification >> >> >> >> >> > Yes Alex, I prefer svn over git 10 to 1. >> > >> > >> > -- >> > Thanks, >> > Joseph Smith >> > Set-Top-Linux >> > www.settoplinux.org >> > >> > -- >> > coreboot mailing list: coreboot at coreboot.org >> > http://www.coreboot.org/mailman/listinfo/coreboot >> > >> >> Hello! >> Even though for some silly reason SVN, and the related #svn update >> command isn't working (# for prompt of hosting Linux system) on my >> hosting Linux system, I also prefer it over git. >> > > > Gregg, are you behind some kind of corporate firewall? Any error > messages? > > Stefan > Hello! Not that I know of. Covad tells me they don't block anything except for port 25, unless the user has a good reason for wanting it unblocked. About the only error message I did see was a time out one. It seemed to spend a lot of time waiting, and waiting, and waiting, and then eventually the program would be on its back with all 32 legs in the air dead as a dodo, from timing out. ----- Gregg C Levine gregg.drwho8 at gmail.com "This signature fought the Time Wars, time and again." From mlf.conv at gmail.com Wed Apr 6 22:26:15 2011 From: mlf.conv at gmail.com (Marek) Date: Wed, 6 Apr 2011 22:26:15 +0200 Subject: [coreboot] Dell Adamo XPS Message-ID: Hi, I'd like to ask whether someone would be so kind to take a look at Dell Adamo XPS logs and give me some advice as to whether there is any chance to flashrom & coreboot this device: http://ul.to/fiyfu9so I'd be glad if anyone could give me further instructions on how to find out more information. thanks, Marek From vidwer at gmail.com Thu Apr 7 00:19:39 2011 From: vidwer at gmail.com (Idwer Vollering) Date: Thu, 7 Apr 2011 00:19:39 +0200 Subject: [coreboot] [PATCH] 440BX registered SDRAM support In-Reply-To: References: <20110329213451.GB19577@coreboot.org> Message-ID: 2011/4/1 Keith Hui : > ping? Adds support for initializing registered SDRAM modules on Intel 440BX > northbridge. > > Drops unneeded romcc-inspired programming tricks. > > Only set nbxecc flags (see 440BX datasheet, page 3-16) when a non-ECC > module has been detected > in a row via SPD; also drops an unneeded intermediate variable used in > setting them. > > Boot tested on ASUS P2B-LS with regular and registered ECC SDRAM under > Linux and memtest86+. > > Signed-off-by: Keith Hui > > Index: src/northbridge/intel/i440bx/raminit.c > =================================================================== > --- src/northbridge/intel/i440bx/raminit.c (revision 6460) > +++ src/northbridge/intel/i440bx/raminit.c (working copy) > @@ -721,19 +721,23 @@ > */ > static void set_dram_row_attributes(void) > { > - int i, dra, drb, col, width, value, rps, edosd, ecc, nbxecc; > + int i, dra, drb, col, width, value, rps; > u8 bpr; /* Top 8 bits of PGPOL */ > + u8 nbxecc = 0; /* NBXCFG[31:24] */ > + u8 edo, sd, regsd; /* EDO, SDRAM, registered SDRAM */ > > - edosd = 0; > + edo = 0; > + sd = 0; > + regsd = 1; > rps = 0; > drb = 0; > bpr = 0; > - nbxecc = 0xff; > > for (i = 0; i < DIMM_SOCKETS; i++) { > unsigned int device; > device = DIMM0 + i; > bpr >>= 2; > + nbxecc >>= 2; > > /* First check if a DIMM is actually present. */ > value = spd_read_byte(device, SPD_MEMORY_TYPE); > @@ -742,13 +746,13 @@ > || value == SPD_MEMORY_TYPE_SDRAM) { > > if (value == SPD_MEMORY_TYPE_EDO) { > - edosd |= 0x02; > + edo = 1; > } else if (value == SPD_MEMORY_TYPE_SDRAM) { > Can you add a #define for SPD_MEMORY_TYPE_REGISTERED_SDRAM to src/include/spd.h as well ? If that is relevant to do, ofcourse. > - edosd |= 0x04; > + sd = 1; > } > PRINT_DEBUG("Found DIMM in slot %d\n", i); > > - if (edosd == 0x06) { > + if (edo && sd) { > print_err("Mixing EDO/SDRAM unsupported!\n"); > die("HALT\n"); > } > @@ -764,24 +768,38 @@ > * TODO: Other register than NBXCFG also needs this > * ECC information. > */ > - ecc = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); > + value = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); > > /* Data width */ > width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); > > /* Exclude error checking data width from page size calculations */ > - if (ecc) { > + if (value) { > value = spd_read_byte(device, > SPD_ERROR_CHECKING_SDRAM_WIDTH); > width -= value; > /* ### ECC */ > /* Clear top 2 bits to help set up NBXCFG. */ > - ecc &= 0x3f; > + nbxecc &= 0x3f; > } else { > /* Without ECC, top 2 bits should be 11. */ > - ecc |= 0xc0; > + nbxecc |= 0xc0; > } > > + /* If any installed DIMM is *not* registered, this system cannot be > + * configured for registered SDRAM. > + * By registered, only the address and control lines need to be, which > + * we can tell by reading SPD byte 21, bit 1. > + */ > + value = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); > + > + PRINT_DEBUG("DIMM is "); > + if ((value & 0x02) == 0) { > + regsd = 0; > + PRINT_DEBUG("not "); > + } > + PRINT_DEBUG("registered\n"); > + > /* Calculate page size in bits. */ > value = ((1 << col) * width); > > @@ -801,7 +819,6 @@ > * Second bank of 1-bank DIMMs "doesn't have > * ECC" - or anything. > */ > - ecc |= 0x80; > if (dra == 2) { > dra = 0x0; /* 2KB */ > } else if (dra == 4) { > @@ -878,7 +895,6 @@ > > /* If there's no DIMM in the slot, set dra to 0x00. */ > dra = 0x00; > - ecc = 0xc0; > /* Still have to propagate DRB over. */ > drb &= 0xff; > drb |= (drb << 8); > @@ -895,7 +911,6 @@ > drb >>= 8; > > rps |= (dra & 0x0f) << (i * 4); > - nbxecc = (nbxecc >> 2) | (ecc & 0xc0); > } > > /* Set paging policy register. */ > @@ -910,20 +925,19 @@ > pci_write_config8(NB, NBXCFG + 3, nbxecc); > PRINT_DEBUG("NBXECC[31:24] has been set to 0x%02x\n", nbxecc); > > - /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM). > - * TODO: Registered SDRAM support. > - */ > - edosd &= 0x07; > - if (edosd & 0x02) { > - edosd |= 0x00; > - } else if (edosd & 0x04) { > - edosd |= 0x08; > + /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered SDRAM). */ > + > + /* i will be used to set DRAMC[4:3]. */ > + if (regsd && sd) { > + i = 0x10; // Registered SDRAM > The datasheets says that this are bits: i = 0x2, not 0x10. + } else if (sd) { > + i = 0x08; // SDRAM > i = 0x1, not 0x8 + } else { > + i = 0; // EDO > } > - edosd &= 0x18; > > - /* edosd is now in the form needed for DRAMC[4:3]. */ > value = pci_read_config8(NB, DRAMC) & 0xe7; > - value |= edosd; > + value |= i; > pci_write_config8(NB, DRAMC, value); > PRINT_DEBUG("DRAMC has been set to 0x%02x\n", value); > } > -------------- next part -------------- An HTML attachment was scrubbed... URL: From hamo.by at gmail.com Thu Apr 7 01:29:23 2011 From: hamo.by at gmail.com (Hamo) Date: Thu, 7 Apr 2011 07:29:23 +0800 Subject: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry In-Reply-To: References: <1302099913.3893.31.camel@mattotaupa> <4D9C7CE1.9020502@gmail.com> <4D9C9173.7000306@settoplinux.org> <20110406163453.GC5484@coreboot.org> Message-ID: Thanks to all of you. Maybe I need to fork the official tree and public my tree here. I am studying the structure of Coreboot now and maybe in the next a few days, I can finish it and begin my porting. On Thu, Apr 7, 2011 at 12:43 AM, Gregg Levine wrote: > On Wed, Apr 6, 2011 at 12:34 PM, Stefan Reinauer > wrote: >> * Gregg Levine [110406 18:17]: >>> On Wed, Apr 6, 2011 at 12:14 PM, Joseph Smith wrote: >>> > On 04/06/2011 10:46 AM, Alex G. wrote: >>> >> >>> >> On 04/06/2011 05:25 PM, Paul Menzel wrote: >>> >>> >>> >>> PPS: Is this a good time to move to Git altogether? A mirror already >>> >>> exists. ;-) Since I am not doing any development, I am not the one to >>> >>> make that call. >>> >>> >>> >> It's nice to have a git mirror, but contributors shouldn't be forced to >>> >> use git, especially since subversion has been used for aeons with >>> >> coreboot. Personally, I would be very unhappy to be forced to use git. >>> >> -1 to gitification >>> >> >>> >> >>> > Yes Alex, I prefer svn over git 10 to 1. >>> > >>> > >>> > -- >>> > Thanks, >>> > Joseph Smith >>> > Set-Top-Linux >>> > www.settoplinux.org >>> > >>> > -- >>> > coreboot mailing list: coreboot at coreboot.org >>> > http://www.coreboot.org/mailman/listinfo/coreboot >>> > >>> >>> Hello! >>> Even though for some silly reason SVN, and the related #svn update >>> command isn't working (# for prompt of hosting Linux system) on my >>> hosting Linux system, I also prefer it over git. >>> >> >> >> Gregg, are you behind some kind of corporate firewall? Any error >> messages? >> >> Stefan >> > > Hello! > Not that I know of. Covad tells me they don't block anything except > for port 25, unless the user has a good reason for wanting it > unblocked. > > About the only error message I did see was a time out one. It seemed > to spend a lot of time waiting, and waiting, and waiting, and then > eventually the program would be on its back with all 32 legs in the > air dead as a dodo, from timing out. > ----- > Gregg C Levine gregg.drwho8 at gmail.com > "This signature fought the Time Wars, time and again." > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From buurin at gmail.com Thu Apr 7 03:32:08 2011 From: buurin at gmail.com (Keith Hui) Date: Wed, 6 Apr 2011 21:32:08 -0400 Subject: [coreboot] [PATCH] 440BX registered SDRAM support In-Reply-To: References: <20110329213451.GB19577@coreboot.org> Message-ID: On Wed, Apr 6, 2011 at 6:19 PM, Idwer Vollering wrote: > > > Can you add a #define for SPD_MEMORY_TYPE_REGISTERED_SDRAM to > src/include/spd.h as well ? If that is relevant to do, ofcourse. There isn't a separate "registered SDRAM" type under SPD_MEMORY_TYPE. The SDRAM module being registered is described in byte 21, as (SPD_MODULE_ATTRIBUTES & MODULE_REGISTERED). *snip* >> >> + /* If any installed DIMM is *not* registered, this system cannot be >> + * configured for registered SDRAM. >> + * By registered, only the address and control lines need to be, which >> + * we can tell by reading SPD byte 21, bit 1. >> + */ >> + value = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); >> + >> + PRINT_DEBUG("DIMM is "); >> + if ((value & 0x02) == 0) { Speaking of which, this should be done to the patch: (Signed-off-by: Keith Hui ) - if ((value & 0x02) == 0) { + if ((value & MODULE_REGISTERED) == 0) { >> + regsd = 0; >> + PRINT_DEBUG("not "); >> + } >> + PRINT_DEBUG("registered\n"); >> + *snip* >> >> - /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM). >> - * TODO: Registered SDRAM support. >> - */ >> - edosd &= 0x07; >> - if (edosd & 0x02) { >> - edosd |= 0x00; >> - } else if (edosd & 0x04) { >> - edosd |= 0x08; >> + /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered SDRAM). */ >> + >> + /* i will be used to set DRAMC[4:3]. */ >> + if (regsd && sd) { >> + i = 0x10; // Registered SDRAM > > The datasheets says that this are bits: i = 0x2, not 0x10. > >> + } else if (sd) { >> + i = 0x08; // SDRAM > > i = 0x1, not 0x8 The relevant bits are in bits 4-3 of the register. So it actually is (2 << 3) and (1 << 3), which becomes what you see. This is done so I don't have to shift the bits later, which save a few instructions. Thanks Keith From marcj303 at gmail.com Thu Apr 7 04:35:14 2011 From: marcj303 at gmail.com (Marc Jones) Date: Wed, 6 Apr 2011 20:35:14 -0600 Subject: [coreboot] GSoC application deadline 4/8 Message-ID: Hello Students, As you probably know, the deadline for GSoC is just a day away. Please make sure to get your application submitted before the deadline. The mentors will start to review the applications, ask questions, and allow students to make adjustments early next week. Please make sure that you answer the standard coreboot part of the application. Feel free to stop in IRC or send email if you have any questions. http://www.coreboot.org/GSoC Regards, Marc -- http://se-eng.com From member at linkedin.com Thu Apr 7 08:51:18 2011 From: member at linkedin.com (QingPei Wang via LinkedIn) Date: Thu, 7 Apr 2011 06:51:18 +0000 (UTC) Subject: [coreboot] QingPei Wang wants to stay in touch on LinkedIn Message-ID: <1384118729.62263.1302159078355.JavaMail.app@ela4-bed33.prod> LinkedIn ------------QingPei Wang requested to add you as a connection on LinkedIn: ------------------------------------------ Jerome, I'd like to add you to my professional network on LinkedIn. - QingPei Wang Accept invitation from QingPei Wang http://www.linkedin.com/e/onyp92-gm7bw79r-4t/u6SZGvvJ_mvgyxl93y5eAqkCVLuNNcowgM/blk/I79532733_15/pmpxnSRJrSdvj4R5fnhv9ClRsDgZp6lQs6lzoQ5AomZIpn8_dj5vcPcTczcRejt9bQ9DhTdDjRZpbPsSdjoVdj0Rdz8LrCBxbOYWrSlI/EML_comm_afe/ View invitation from QingPei Wang http://www.linkedin.com/e/onyp92-gm7bw79r-4t/u6SZGvvJ_mvgyxl93y5eAqkCVLuNNcowgM/blk/I79532733_15/0RclYPcPsOcPkVdQALqnpPbOYWrSlI/svi/ ------------------------------------------ Why might connecting with QingPei Wang be a good idea? QingPei Wang's connections could be useful to you: After accepting QingPei Wang's invitation, check QingPei Wang's connections to see who else you may know and who you might want an introduction to. Building these connections can create opportunities in the future. -- (c) 2011, LinkedIn Corporation -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.reinauer at coreboot.org Thu Apr 7 08:53:34 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Wed, 06 Apr 2011 23:53:34 -0700 Subject: [coreboot] QingPei Wang wants to stay in touch on LinkedIn In-Reply-To: <1384118729.62263.1302159078355.JavaMail.app@ela4-bed33.prod> References: <1384118729.62263.1302159078355.JavaMail.app@ela4-bed33.prod> Message-ID: <4D9D5F6E.4080807@coreboot.org> Please stop sending LinkedIn invitations to the coreboot mailing list. On 4/6/11 11:51 PM, QingPei Wang via LinkedIn wrote: > > > LinkedIn > > QingPei Wang requested to add you as a connection on LinkedIn: > > Jerome, > > I'd like to add you to my professional network on LinkedIn. > > - QingPei Wang > > Accept > > > View invitation from QingPei Wang > > > > > > *WHY MIGHT CONNECTING WITH QINGPEI WANG BE A GOOD IDEA?* > > *QingPei Wang's connections could be useful to you* > After accepting QingPei Wang's invitation, check QingPei Wang's > connections to see who else you may know and who you might want an > introduction to. Building these connections can create opportunities > in the future. > > ? 2011, LinkedIn Corporation > -------------- next part -------------- An HTML attachment was scrubbed... URL: From ntlloyd at uncg.edu Wed Apr 6 18:37:37 2011 From: ntlloyd at uncg.edu (Nickolas Lloyd) Date: Wed, 6 Apr 2011 12:37:37 -0400 Subject: [coreboot] [PATCH][RESEND] Print what mainboard coreboot is being built for during build Message-ID: Sorry about the mangling, I've attached the patch this time. Nickolas -------------- next part -------------- From 404e7bd11e3dadf912b45057000e053db5ed7e90 Mon Sep 17 00:00:00 2001 From: Nickolas Lloyd Date: Tue, 5 Apr 2011 19:18:07 -0400 Subject: [PATCH] Print what mainboard coreboot is being built for during build Print a message before and after build saying what mainboard coreboot is being built for. Only printed after build if build was successful --- Makefile | 1 + Makefile.inc | 4 +++- 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index 06847b6..ddc12a6 100644 --- a/Makefile +++ b/Makefile @@ -145,6 +145,7 @@ real-all: else real-all: real-target endif + @echo "Built coreboot for $(CONFIG_MAINBOARD_VENDOR) $(CONFIG_MAINBOARD_PART_NUMBER)" # must come rather early .SECONDEXPANSION: diff --git a/Makefile.inc b/Makefile.inc index 3f553c6..74b4455 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -31,7 +31,9 @@ export MAINBOARDDIR ####################################################################### # root rule to resolve if in build mode (ie. configuration exists) real-target: $(obj)/config.h coreboot -coreboot: $(obj)/coreboot.rom +coreboot: building-msg $(obj)/coreboot.rom +building-msg: + @echo "Building coreboot for $(CONFIG_MAINBOARD_VENDOR) $(CONFIG_MAINBOARD_PART_NUMBER)" ####################################################################### # our phony targets -- 1.7.4.1 From spzakulec at gmail.com Thu Apr 7 00:29:49 2011 From: spzakulec at gmail.com (Steven Zakulec) Date: Wed, 6 Apr 2011 18:29:49 -0400 Subject: [coreboot] [flashrom] Dell Adamo XPS In-Reply-To: References: Message-ID: On Wed, Apr 6, 2011 at 4:26 PM, Marek wrote: > Hi, > > I'd like to ask whether someone would be so kind to take a look at Dell > Adamo XPS logs and give me some advice as to whether there is any chance to > flashrom & coreboot this device: > > http://ul.to/fiyfu9so > > I'd be glad if anyone could give me further instructions on how to find out > more information. > > thanks, > > Marek > _______________________________________________ > flashrom mailing list > flashrom at flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom > I'm attaching all the logs from your link Marek so everyone can see them. (If you can't send it directly to the mailing list, please use mediafire instead.) -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: biosdecode.log Type: application/octet-stream Size: 620 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: dmesg.log Type: application/octet-stream Size: 54952 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: dmidecode.log Type: application/octet-stream Size: 13686 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: ectool.log Type: application/octet-stream Size: 882 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... 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Name: nvramtool.log Type: application/octet-stream Size: 1184 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: lscpi.log Type: application/octet-stream Size: 100091 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: lspnp.log Type: application/octet-stream Size: 2153 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: lsusb.log Type: application/octet-stream Size: 59623 bytes Desc: not available URL: From mlf.conv at gmail.com Thu Apr 7 14:10:13 2011 From: mlf.conv at gmail.com (Marek) Date: Thu, 7 Apr 2011 14:10:13 +0200 Subject: [coreboot] [flashrom] Dell Adamo XPS In-Reply-To: References: Message-ID: <14B6DE90-3F35-4629-90B8-04681AB0738E@gmail.com> Hi Steven, will do next time, thanks for attaching the logs, I wasn't sure whether to attach them since they were quite large. I'm wondering how to figure out the EC used in AdamoXPS without opening it, i went through all the logs but wasn't able to find it. thanks, Marek On 7.4.2011, at 0:29, Steven Zakulec wrote: > > > On Wed, Apr 6, 2011 at 4:26 PM, Marek wrote: > Hi, > > I'd like to ask whether someone would be so kind to take a look at Dell Adamo XPS logs and give me some advice as to whether there is any chance to flashrom & coreboot this device: > > http://ul.to/fiyfu9so > > I'd be glad if anyone could give me further instructions on how to find out more information. > > thanks, > > Marek > _______________________________________________ > flashrom mailing list > flashrom at flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom > > I'm attaching all the logs from your link Marek so everyone can see them. (If you can't send it directly to the mailing list, please use mediafire instead.) > > > > > > > > > > > > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From cubicool at gmail.com Thu Apr 7 17:16:13 2011 From: cubicool at gmail.com (Jeremy Moles) Date: Thu, 07 Apr 2011 11:16:13 -0400 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U In-Reply-To: <1301958441.2587.11.camel@lv-426> References: <1301958441.2587.11.camel@lv-426> Message-ID: <1302189374.2489.4.camel@lv-426> Hey guys--I hate to bump this so soon, but my current project is pretty much stalled without being able to approach this issue one way or another. Does anyone have any good documentation I can read to learn how to interact with (either in userspace or kernel-level) LPC devices, specifically the PC87381 Super I/O device? Perhaps there's some code in coreboot demonstrating how GPIO ports are manipulated? On Mon, 2011-04-04 at 19:07 -0400, Jeremy Moles wrote: > Hello everyone. > > I have my hands on a piece of hardware here using the Super I/O device > listed in the subject; that is: > > Winbond LPC Super I/O WPCN381U > > - My first question is, has anyone else encountered this device? > > - SVN trunk of superiotool detects this device as: > > Found NSC PC87382 (sid=0xf4, srid=0x04) at 0x2e > > ...and I know from the manufacturer that the device is actually the one > mentioned previously. However, I know from the specsheet that the > hardware is pin-compatible with the Winbond PC87381, which has a very > similar name to the device it "thinks" it is. > > http://www.winbond-usa.com/products/winbond_products/pdfs/APC/WPCN381U_pba.pdf > > Does this mean that superiotool is actually detecting it properly? > > - Finally, the device I want to use waits for input via the serial port, > but before this can be initiated the device must be powered on via the > Super I/O module. According to the manufacturer, I do this by activating > the GPIO03 pin. I know superiotool is a read-only tool, given I know > these pieces of data, is there an easy way to ping this particular bit? > > - My first approach to enable this device was to write a small kernel > module that would call gpio_request(3); however, this always returns > -ENOSYS or -EINVAL. This clearly isn't the right approach. :) > > I realize this is probably a question for LKML proper, but I figured I'd > ask here first and see what the Fates have in store. :) From peter at stuge.se Thu Apr 7 17:21:56 2011 From: peter at stuge.se (Peter Stuge) Date: Thu, 7 Apr 2011 17:21:56 +0200 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U In-Reply-To: <1302189374.2489.4.camel@lv-426> References: <1301958441.2587.11.camel@lv-426> <1302189374.2489.4.camel@lv-426> Message-ID: <20110407152156.1233.qmail@stuge.se> Jeremy Moles wrote: > Does anyone have any good documentation I can read to learn how to > interact with (either in userspace or kernel-level) LPC devices, LPC is directly accessible to the CPU, so you use outb and inb to make IO accesses. > specifically the PC87381 Super I/O device? Perhaps there's some code > in coreboot demonstrating how GPIO ports are manipulated? Look at what superiotool does, and/or use isaset from lm-sensors. //Peter From peter at stuge.se Thu Apr 7 17:27:44 2011 From: peter at stuge.se (Peter Stuge) Date: Thu, 7 Apr 2011 17:27:44 +0200 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U In-Reply-To: <20110407152156.1233.qmail@stuge.se> References: <1301958441.2587.11.camel@lv-426> <1302189374.2489.4.camel@lv-426> <20110407152156.1233.qmail@stuge.se> Message-ID: <20110407152744.1876.qmail@stuge.se> Peter Stuge wrote: > > specifically the PC87381 Super I/O device? Perhaps there's some code > > in coreboot demonstrating how GPIO ports are manipulated? > > Look at what superiotool does To clarify, superiotool has functions internally for writing to registers in superios, because they are needed by the program. There's just no user interface for writing, and there hasn't been much discussion on how it would look. //Peter From cubicool at gmail.com Thu Apr 7 17:34:33 2011 From: cubicool at gmail.com (Jeremy Moles) Date: Thu, 07 Apr 2011 11:34:33 -0400 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U In-Reply-To: <20110407152744.1876.qmail@stuge.se> References: <1301958441.2587.11.camel@lv-426> <1302189374.2489.4.camel@lv-426> <20110407152156.1233.qmail@stuge.se> <20110407152744.1876.qmail@stuge.se> Message-ID: <1302190473.2489.9.camel@lv-426> On Thu, 2011-04-07 at 17:27 +0200, Peter Stuge wrote: > Peter Stuge wrote: > > > specifically the PC87381 Super I/O device? Perhaps there's some code > > > in coreboot demonstrating how GPIO ports are manipulated? > > > > Look at what superiotool does > > To clarify, superiotool has functions internally for writing to > registers in superios, because they are needed by the program. > There's just no user interface for writing, and there hasn't been > much discussion on how it would look. Okay, thanks. :) As a further question: as I mentioned in the first post, the information given to me (which is all we can get under our current NDA) is that to "power up" this device (unfortunately, the person giving us this information was certainly not a Linux engineer) we should manipulate the GPIO03 port. Aren't these pins that simply accept a single bit (I see the terms HIGH/LOW used frequently in GPIO documentation). This means I will need to find whatever register corresponds to GPIO03 and set just that particular HIGH bit? (Other keywords in their email were things like "GPIO:0x2" and GPIO:0x18", but I haven't been able to get any additional clarification from them...) At any rate, thanks for your help. Hopefully I can use isaset, and if not I'll try using regwrite() in superiotool directrly (which just wraps OUTB anyways)... > //Peter > From peter at stuge.se Thu Apr 7 17:39:49 2011 From: peter at stuge.se (Peter Stuge) Date: Thu, 7 Apr 2011 17:39:49 +0200 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U In-Reply-To: <1302190473.2489.9.camel@lv-426> References: <1301958441.2587.11.camel@lv-426> <1302189374.2489.4.camel@lv-426> <20110407152156.1233.qmail@stuge.se> <20110407152744.1876.qmail@stuge.se> <1302190473.2489.9.camel@lv-426> Message-ID: <20110407153949.3424.qmail@stuge.se> Jeremy Moles wrote: > > To clarify, superiotool has functions internally for writing to > > registers in superios, .. > I will need to find whatever register corresponds to GPIO03 and > set just that particular HIGH bit? Yes. Look at the data sheet and maybe as a help you can step through superiotool as well. > (Other keywords in their email were things like "GPIO:0x2" and > GPIO:0x18", but I haven't been able to get any additional > clarification from them...) Superios are easier to program than many other components, and are well documented, so you shouldn't have too much trouble. GPIO 3 is what you need to know about how the hardware is built. //Peter From cubicool at gmail.com Thu Apr 7 18:07:19 2011 From: cubicool at gmail.com (Jeremy Moles) Date: Thu, 07 Apr 2011 12:07:19 -0400 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U In-Reply-To: <20110407153949.3424.qmail@stuge.se> References: <1301958441.2587.11.camel@lv-426> <1302189374.2489.4.camel@lv-426> <20110407152156.1233.qmail@stuge.se> <20110407152744.1876.qmail@stuge.se> <1302190473.2489.9.camel@lv-426> <20110407153949.3424.qmail@stuge.se> Message-ID: <1302192439.2489.14.camel@lv-426> On Thu, 2011-04-07 at 17:39 +0200, Peter Stuge wrote: > Jeremy Moles wrote: > > > To clarify, superiotool has functions internally for writing to > > > registers in superios, > .. > > I will need to find whatever register corresponds to GPIO03 and > > set just that particular HIGH bit? > > Yes. Look at the data sheet and maybe as a help you can step through > superiotool as well. > > > > (Other keywords in their email were things like "GPIO:0x2" and > > GPIO:0x18", but I haven't been able to get any additional > > clarification from them...) > > Superios are easier to program than many other components, and are > well documented, so you shouldn't have too much trouble. GPIO 3 is > what you need to know about how the hardware is built. I do have a document describing the hardware pretty thoroughly, but I am unfamiliar with the terminology it uses and how I would map that into something I AM familiar with in Linux. When you say well-documented: is there a particular document you can think of offhand? At any rate, I'm sure I'm close to the edge of how much this list is willing to tolerate. :) Thanks for the help, hopefully I can make something out of this... > //Peter > From corey.osgood at gmail.com Thu Apr 7 19:15:06 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Thu, 7 Apr 2011 13:15:06 -0400 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U In-Reply-To: <1302192439.2489.14.camel@lv-426> References: <1301958441.2587.11.camel@lv-426> <1302189374.2489.4.camel@lv-426> <20110407152156.1233.qmail@stuge.se> <20110407152744.1876.qmail@stuge.se> <1302190473.2489.9.camel@lv-426> <20110407153949.3424.qmail@stuge.se> <1302192439.2489.14.camel@lv-426> Message-ID: On Thu, Apr 7, 2011 at 12:07 PM, Jeremy Moles wrote: > On Thu, 2011-04-07 at 17:39 +0200, Peter Stuge wrote: >> Jeremy Moles wrote: >> > > To clarify, superiotool has functions internally for writing to >> > > registers in superios, >> .. >> > I will need to find whatever register corresponds to GPIO03 and >> > set just that particular HIGH bit? >> >> Yes. Look at the data sheet and maybe as a help you can step through >> superiotool as well. >> >> >> > (Other keywords in their email were things like "GPIO:0x2" and >> > GPIO:0x18", but I haven't been able to get any additional >> > clarification from them...) >> >> Superios are easier to program than many other components, and are >> well documented, so you shouldn't have too much trouble. GPIO 3 is >> what you need to know about how the hardware is built. > > I do have a document describing the hardware pretty thoroughly, but > I am unfamiliar with the terminology it uses and how I would map that > into something I AM familiar with in Linux. > > When you say well-documented: is there a particular document you can > think of offhand? > > At any rate, I'm sure I'm close to the edge of how much this list is > willing to tolerate. :) Thanks for the help, hopefully I can make > something out of this... Perhaps this will help: http://www.coreboot.org/Developer_Manual/Super_IO Try looking at a datasheet for just about any Winbond super IO that does have a public datasheet, they all work generally the same way, just the LDNs and registers vary. Also, have you tried contacting Winbond/Nuvoton for the datasheet? I've never had them deny me a datasheet, and never had to sign an NDA for one either. And have you inspected the board to find the Super IO and confirm that it is a Winbond? Sometimes designs change, it wouldn't surprise me to find that it really is the NSC chip. -Corey From cubicool at gmail.com Thu Apr 7 19:26:56 2011 From: cubicool at gmail.com (Jeremy Moles) Date: Thu, 07 Apr 2011 13:26:56 -0400 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U In-Reply-To: References: <1301958441.2587.11.camel@lv-426> <1302189374.2489.4.camel@lv-426> <20110407152156.1233.qmail@stuge.se> <20110407152744.1876.qmail@stuge.se> <1302190473.2489.9.camel@lv-426> <20110407153949.3424.qmail@stuge.se> <1302192439.2489.14.camel@lv-426> Message-ID: <1302197216.2489.21.camel@lv-426> On Thu, 2011-04-07 at 13:15 -0400, Corey Osgood wrote: > On Thu, Apr 7, 2011 at 12:07 PM, Jeremy Moles wrote: > > On Thu, 2011-04-07 at 17:39 +0200, Peter Stuge wrote: > >> Jeremy Moles wrote: > >> > > To clarify, superiotool has functions internally for writing to > >> > > registers in superios, > >> .. > >> > I will need to find whatever register corresponds to GPIO03 and > >> > set just that particular HIGH bit? > >> > >> Yes. Look at the data sheet and maybe as a help you can step through > >> superiotool as well. > >> > >> > >> > (Other keywords in their email were things like "GPIO:0x2" and > >> > GPIO:0x18", but I haven't been able to get any additional > >> > clarification from them...) > >> > >> Superios are easier to program than many other components, and are > >> well documented, so you shouldn't have too much trouble. GPIO 3 is > >> what you need to know about how the hardware is built. > > > > I do have a document describing the hardware pretty thoroughly, but > > I am unfamiliar with the terminology it uses and how I would map that > > into something I AM familiar with in Linux. > > > > When you say well-documented: is there a particular document you can > > think of offhand? > > > > At any rate, I'm sure I'm close to the edge of how much this list is > > willing to tolerate. :) Thanks for the help, hopefully I can make > > something out of this... > > Perhaps this will help: > > http://www.coreboot.org/Developer_Manual/Super_IO > > Try looking at a datasheet for just about any Winbond super IO that > does have a public datasheet, they all work generally the same way, > just the LDNs and registers vary. I do have the datasheet for the hardware in question: http://jeremymoles.com/WPCN381U.pdf (This was downloaded from a public URL, though I cannot remember it now...) > Also, have you tried contacting Winbond/Nuvoton for the datasheet? > I've never had them deny me a datasheet, and never had to sign an NDA > for one either. And have you inspected the board to find the Super IO > and confirm that it is a Winbond? Sometimes designs change, it > wouldn't surprise me to find that it really is the NSC chip. It's not that the hardware specs are unvailable, it's simply that I lack the knowledge to be able to translate the information form the hardware vendor (i.e., their engineer telling me to simply ping GPIO-03 on the SuperI/O controller and the hardware lights up) into Linux code. :) In Windows, apparently, it's as easy as that... I tried running isaset to set every single register to 0xFF, but this doesn't do anything except turn the serial port off. Besides, I don't expect this would work anyways, as the GPIO registers I need are abstracted away in an LDN (7, in my case), and I think you need to inform the hardware of that FIRST before writing any bits. > -Corey From peter at stuge.se Thu Apr 7 19:52:51 2011 From: peter at stuge.se (Peter Stuge) Date: Thu, 7 Apr 2011 19:52:51 +0200 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U In-Reply-To: <1302197216.2489.21.camel@lv-426> References: <1301958441.2587.11.camel@lv-426> <1302189374.2489.4.camel@lv-426> <20110407152156.1233.qmail@stuge.se> <20110407152744.1876.qmail@stuge.se> <1302190473.2489.9.camel@lv-426> <20110407153949.3424.qmail@stuge.se> <1302192439.2489.14.camel@lv-426> <1302197216.2489.21.camel@lv-426> Message-ID: <20110407175251.18283.qmail@stuge.se> Jeremy Moles wrote: > It's not that the hardware specs are unvailable, it's simply that I > lack the knowledge to be able to translate the information form the > hardware vendor (i.e., their engineer telling me to simply ping > GPIO-03 on the SuperI/O controller and the hardware lights up) into > Linux code. :) In Windows, apparently, it's as easy as that... If anything I'd say it's more difficult in Windows. > the GPIO registers I need are abstracted away in an LDN (7, in my > case), and I think you need to inform the hardware of that FIRST > before writing any bits. Correct. Looking at chapter 5 it's also clear that actual data for GPIO pins is written using registers offset from an IO base address configured in the logical device. So steps are: set gpio ldn: regwrite(7,7) read io base address: regread(60h)<<8 | regread(61h) read current GPIO-0 value: inb(base address) set bit 3 in value (1<<3) write new GPIO-0 value: outb(base,newval) //Peter From marcj303 at gmail.com Fri Apr 8 00:05:42 2011 From: marcj303 at gmail.com (Marc Jones) Date: Thu, 7 Apr 2011 16:05:42 -0600 Subject: [coreboot] [PATCH][RESEND] Print what mainboard coreboot is being built for during build In-Reply-To: References: Message-ID: Hi Nickolas, On Wed, Apr 6, 2011 at 10:37 AM, Nickolas Lloyd wrote: > Sorry about the mangling, I've attached the patch this time. > > + @echo "Built coreboot for $(CONFIG_MAINBOARD_VENDOR) $(CONFIG_MAINBOARD_PART_NUMBER)" I think that you want the variables outside the "". Marc -- http://se-eng.com From russ at ashlandhome.net Fri Apr 8 00:56:38 2011 From: russ at ashlandhome.net (Russell Whitaker) Date: Thu, 7 Apr 2011 15:56:38 -0700 (PDT) Subject: [coreboot] [PATCH][RESEND] Print what mainboard coreboot is being built for during build In-Reply-To: References: Message-ID: On Thu, 7 Apr 2011, Marc Jones wrote: > Hi Nickolas, > > > > On Wed, Apr 6, 2011 at 10:37 AM, Nickolas Lloyd wrote: >> Sorry about the mangling, I've attached the patch this time. >> > >> + @echo "Built coreboot for $(CONFIG_MAINBOARD_VENDOR) $(CONFIG_MAINBOARD_PART_NUMBER)" > > I think that you want the variables outside the "". > At least here the echo command ignores the quotes. Try this: export ARCH=i686 then echo my arch is $ARCH echo "my arch is $ARCH" echo "my arch" is $ARCH all yeald the same result: my arch is i686 Russ From ntlloyd at uncg.edu Fri Apr 8 01:08:13 2011 From: ntlloyd at uncg.edu (Nickolas Lloyd) Date: Thu, 7 Apr 2011 19:08:13 -0400 Subject: [coreboot] [PATCH][RESEND] Print what mainboard coreboot is being built for during build In-Reply-To: References: Message-ID: In bash at least using double-quotes results in the evaluation of symbols, whereas single-quotes doesn't. I suspect it's the same for make. I can change it if you like though. Nick On Thu, Apr 7, 2011 at 6:56 PM, Russell Whitaker wrote: > > > On Thu, 7 Apr 2011, Marc Jones wrote: > >> Hi Nickolas, >> >> >> >> On Wed, Apr 6, 2011 at 10:37 AM, Nickolas Lloyd wrote: >>> >>> Sorry about the mangling, I've attached the patch this time. >>> >> >>> + ? ? ? @echo "Built coreboot for $(CONFIG_MAINBOARD_VENDOR) >>> $(CONFIG_MAINBOARD_PART_NUMBER)" >> >> I think that you want the variables outside the "". >> > At least here the echo command ignores the quotes. > Try this: > ?export ARCH=i686 > then > ?echo my arch is $ARCH > ?echo "my arch is $ARCH" > ?echo "my arch" is $ARCH > all yeald the same result: my arch is i686 > > ?Russ > From peter at stuge.se Fri Apr 8 01:26:10 2011 From: peter at stuge.se (Peter Stuge) Date: Fri, 8 Apr 2011 01:26:10 +0200 Subject: [coreboot] [PATCH][RESEND] Print what mainboard coreboot is being built for during build In-Reply-To: References: Message-ID: <20110407232610.19087.qmail@stuge.se> Nickolas Lloyd wrote: > In bash at least using double-quotes results in the evaluation of > symbols, whereas single-quotes doesn't. I suspect it's the same > for make. make expands $() regardless of whether it is inside quotes or not. make doesn't do much parsing, after expansion the command is passed to sh: $ cat Makefile X:=bar .PHONY: x x: @echo "foo $(X) baz" $ strace -fF make 2>&1 | grep echo read(3, "X:=bar\n\n.PHONY: x\nx:\n\t at echo \"foo "..., 4096) = 43 [pid 29660] execve("/bin/sh", ["/bin/sh", "-c", "echo \"foo bar baz\""], [/* 51 vars */]) = 0 > I can change it if you like though. Better keep it inside the quotes, so that weird names will not mess up the shell, if we'll ever have any names like that. Acked-by: Peter Stuge //Peter From schramp at holmes.nl Fri Apr 8 10:21:29 2011 From: schramp at holmes.nl (Ruud Schramp (DT)) Date: Fri, 8 Apr 2011 10:21:29 +0200 Subject: [coreboot] PATCH: superiotool probe for ServerEngines chip Message-ID: Hi guys, Do not know how to handle the unknown devices (LDN's) yet. For now I dump all IO base registers etc for information purposed. I have identified two LDN's as Serial port; (LDN 0x01 and LDN 0x02) Best regards, Ruud Signed-off-by: Ruud Schramp Example output: ./superiotool -d superiotool r Found serverengines Server Engine SE-SM 4210-P01 (id=0x02c0, rev=0x00) at 0x2e Register dump: idx 1f 20 21 22 23 2c 2d 2e val 00 02 c0 00 05 00 00 00 def NA 02 c0 00 00 RR RR RR LDN 0x00 (UNK) idx 30 60 61 70 f0 f1 f2 val 00 00 00 00 00 00 00 def NA NA NA NA NA NA NA LDN 0x01 (COM2) idx 30 60 61 70 f0 f1 f2 val 00 02 f8 03 00 00 00 def 00 02 f8 03 00 00 0c LDN 0x02 (COM1) idx 30 60 61 70 f0 f1 f2 val 01 03 f8 04 00 00 00 def 00 03 f8 04 00 00 0c LDN 0x03 (UNK) idx 30 60 61 70 f0 f1 f2 val 00 00 00 00 00 00 00 def NA NA NA NA NA NA NA LDN 0x04 (UNK) idx 30 60 61 70 f0 f1 f2 val 00 00 00 00 00 00 00 def NA NA NA NA NA NA NA LDN 0x05 (UNK) idx 30 60 61 70 f0 f1 f2 val 00 00 00 00 00 00 00 def NA NA NA NA NA NA NA LDN 0x06 (UNK) idx 30 60 61 70 f0 f1 f2 val 00 00 00 00 00 00 00 def NA NA NA NA NA NA NA LDN 0x07 (UNK) idx 30 60 61 70 f0 f1 f2 val 00 00 00 00 00 00 00 def NA NA NA NA NA NA NA -------------- next part -------------- A non-text attachment was scrubbed... Name: server_engines.patch Type: application/octet-stream Size: 4773 bytes Desc: server_engines.patch URL: From stefan.reinauer at coreboot.org Sat Apr 9 01:02:12 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Sat, 9 Apr 2011 01:02:12 +0200 Subject: [coreboot] [PATCH] drop ASSEMBLY define Message-ID: <20110408230212.GA10928@coreboot.org> see patch -------------- next part -------------- A non-text attachment was scrubbed... Name: drop-ASSEMBLY.diff Type: text/x-patch Size: 11349 bytes Desc: not available URL: From dev002 at pas-world.com Thu Apr 7 16:21:57 2011 From: dev002 at pas-world.com (Devel) Date: Thu, 07 Apr 2011 16:21:57 +0200 Subject: [coreboot] e-vectra flash Message-ID: <1302186117.12229.8.camel@athlon.precioventa.com> Hello, (Murphy's Law in action!) Well, I tried to use Coreboot + Seabios in old hp e-vectra. - Download coreboot. - Compile coreboot. - Flash with flashrom. Seems to be that is not easy, because old e-vectra do not boot. Any page that explains how to add devices like onboard vga, and onboard ethernet to image? Any pre-builded rom for this device? I will try to re-flash using eeprom programmer. Regards, -- Ordenadores, componentes y software: http://www.1pc.es/ Sistemas IT: http://www.precioventa.com/ From stefan.reinauer at coreboot.org Sat Apr 9 01:04:29 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Sat, 9 Apr 2011 01:04:29 +0200 Subject: [coreboot] e-vectra flash In-Reply-To: <1302186117.12229.8.camel@athlon.precioventa.com> References: <1302186117.12229.8.camel@athlon.precioventa.com> Message-ID: <20110408230428.GA12036@coreboot.org> * Devel [110407 16:21]: > Hello, > > (Murphy's Law in action!) > > Well, I tried to use Coreboot + Seabios in old hp e-vectra. > > - Download coreboot. > - Compile coreboot. > - Flash with flashrom. > Seems to be that is not easy, because old e-vectra do not boot. Please send the serial console log to the mailing list. From stefan.reinauer at coreboot.org Sat Apr 9 01:08:23 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Sat, 9 Apr 2011 01:08:23 +0200 Subject: [coreboot] PATCH: superiotool probe for ServerEngines chip In-Reply-To: References: Message-ID: <20110408230823.GA12287@coreboot.org> * Ruud Schramp (DT) [110408 10:21]: > Hi guys, > > Do not know how to handle the unknown devices (LDN's) yet. For now I > dump all IO base registers etc for information purposed. > > I have identified two LDN's as Serial port; (LDN 0x01 and LDN 0x02) > > Best regards, > > Ruud > > > Signed-off-by: Ruud Schramp > diff -uNr superiotool_org/serverengine.c superiotool/serverengine.c > --- superiotool_org/serverengine.c 1970-01-01 01:00:00.000000000 +0100 > +++ superiotool/serverengine.c 2011-04-08 10:13:33.000000000 +0200 please rename to serverengines.c > @@ -0,0 +1,106 @@ > +/* > + * This file is part of the superiotool project. > + * > + * Copyright (C) 2007 Uwe Hermann Please add your copyright here > + > +static const struct superio_registers reg_table[] = { > + /* TODO: M5113 doesn't seem to have ID registers? */ Astray line from original code? Please delete > + {0x02c0, "Server Engine SE-SM 4210-P01", { Drop Server Engine here. > + /* TODO: Not documented/available on M512x (?) */ Left over comment? Stefan From patrick at georgi-clan.de Sat Apr 9 07:38:33 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 09 Apr 2011 07:38:33 +0200 Subject: [coreboot] [PATCH] drop ASSEMBLY define In-Reply-To: <20110408230212.GA10928@coreboot.org> References: <20110408230212.GA10928@coreboot.org> Message-ID: <4D9FF0D9.60903@georgi-clan.de> Am 09.04.2011 01:02, schrieb Stefan Reinauer: > see patch Look good. Consider dropping the empty variable definitions entirely. Acked-by: Patrick Georgi From svens at stackframe.org Sat Apr 9 13:31:23 2011 From: svens at stackframe.org (Sven Schnelle) Date: Sat, 9 Apr 2011 13:31:23 +0200 Subject: [coreboot] [PATCH] i945: improve get_top_of_ram() Message-ID: <1302348683-13930-1-git-send-email-svens@stackframe.org> The current version doesn't honor TSEG, and fails to report the correct top of RAM if IGD is disabled. This is because it uses the BSM (base of stolen RAM) register. In that case, we should use the TOLUD register. Signed-off-by: Sven Schnelle --- src/northbridge/intel/i945/raminit.c | 30 +++++++++++++++++++++++++++--- 1 files changed, 27 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 8b7ffa1..c8bef11 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -3192,9 +3192,33 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) unsigned long get_top_of_ram(void) { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom; - return (unsigned long) tom; + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + } else { + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x10000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x20000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x80000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } + return (unsigned long)tom; } -- 1.7.4.1 From svn at coreboot.org Sun Apr 10 06:15:23 2011 From: svn at coreboot.org (repository service) Date: Sun, 10 Apr 2011 06:15:23 +0200 Subject: [coreboot] [commit] r6482 - in trunk: . src/arch/x86 src/include src/include/cpu/amd src/include/cpu/x86 src/mainboard/amd/serengeti_cheetah src/mainboard/gigabyte/ga_2761gxdk src/mainboard/gigabyte/m57sli sr... Message-ID: Author: stepan Date: Sun Apr 10 06:15:23 2011 New Revision: 6482 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6482 Log: In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__. http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html It's about time we follow this advice. Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and drop unused CPP define Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi Modified: trunk/Makefile trunk/Makefile.inc trunk/src/arch/x86/Makefile.bigbootblock.inc trunk/src/arch/x86/Makefile.bootblock.inc trunk/src/arch/x86/Makefile.inc trunk/src/include/cpu/amd/gx2def.h trunk/src/include/cpu/amd/lxdef.h trunk/src/include/cpu/amd/mtrr.h trunk/src/include/cpu/x86/mtrr.h trunk/src/include/fallback.h trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c trunk/src/mainboard/msi/ms7260/ap_romstage.c trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c trunk/src/mainboard/supermicro/h8dme/ap_romstage.c trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c trunk/src/mainboard/tyan/s2912/ap_romstage.c trunk/src/southbridge/amd/cs5535/cs5535.h trunk/src/southbridge/amd/cs5536/cs5536.h trunk/src/southbridge/intel/i82371eb/i82371eb.h trunk/src/southbridge/intel/i82801gx/i82801gx.h trunk/util/xcompile/xcompile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/Makefile Sun Apr 10 06:15:23 2011 (r6482) @@ -64,7 +64,6 @@ endif endif -CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E HOSTCC = gcc HOSTCXX = g++ HOSTCFLAGS := -I$(srck) -I$(objk) -g Modified: trunk/Makefile.inc ============================================================================== --- trunk/Makefile.inc Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/Makefile.inc Sun Apr 10 06:15:23 2011 (r6482) @@ -50,10 +50,8 @@ # Add source classes and their build options classes-y := ramstage romstage driver smm -ramstage-S-ccopts:=-DASSEMBLY romstage-c-ccopts:=-D__PRE_RAM__ -romstage-S-ccopts:=-DASSEMBLY -D__PRE_RAM__ -driver-S-ccopts:=-DASSEMBLY +romstage-S-ccopts:=-D__PRE_RAM__ ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) @@ -63,7 +61,7 @@ define ramstage-objs_asl_template $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" - $(CPP) -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl + $(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl iasl -p $$(obj)/$(1) -tc $$(basename $$@).asl mv $$(obj)/$(1).hex $$(basename $$@).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$@).c Modified: trunk/src/arch/x86/Makefile.bigbootblock.inc ============================================================================== --- trunk/src/arch/x86/Makefile.bigbootblock.inc Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/arch/x86/Makefile.bigbootblock.inc Sun Apr 10 06:15:23 2011 (r6482) @@ -26,7 +26,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/coreboot: $$(romstage-objs) $(obj)/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" Modified: trunk/src/arch/x86/Makefile.bootblock.inc ============================================================================== --- trunk/src/arch/x86/Makefile.bootblock.inc Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/arch/x86/Makefile.bootblock.inc Sun Apr 10 06:15:23 2011 (r6482) @@ -55,7 +55,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" @@ -105,5 +105,5 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@ Modified: trunk/src/arch/x86/Makefile.inc ============================================================================== --- trunk/src/arch/x86/Makefile.inc Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/arch/x86/Makefile.inc Sun Apr 10 06:15:23 2011 (r6482) @@ -225,7 +225,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -I$(src) -I. -I$(obj) -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@ + $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/include/cpu/amd/gx2def.h Sun Apr 10 06:15:23 2011 (r6482) @@ -511,7 +511,7 @@ #define PMLogic_BASE (0x9D00) -#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(void); void SystemPreInit(void); Modified: trunk/src/include/cpu/amd/lxdef.h ============================================================================== --- trunk/src/include/cpu/amd/lxdef.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/include/cpu/amd/lxdef.h Sun Apr 10 06:15:23 2011 (r6482) @@ -630,7 +630,7 @@ #define DELAY_UPPER_DISABLE_CLK135 (1 << 23) #define DELAY_LOWER_STATUS_MASK 0x7C0 -#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated); void SystemPreInit(void); Modified: trunk/src/include/cpu/amd/mtrr.h ============================================================================== --- trunk/src/include/cpu/amd/mtrr.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/include/cpu/amd/mtrr.h Sun Apr 10 06:15:23 2011 (r6482) @@ -33,7 +33,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined(__PRE_RAM__) && !defined(ASSEMBLY) +#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) void amd_setup_mtrrs(void); #endif Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/include/cpu/x86/mtrr.h Sun Apr 10 06:15:23 2011 (r6482) @@ -36,7 +36,7 @@ #define MTRRfix4K_F0000_MSR 0x26e #define MTRRfix4K_F8000_MSR 0x26f -#if !defined (ASSEMBLY) && !defined(__PRE_RAM__) +#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) #include void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); @@ -69,7 +69,7 @@ #endif -#if !defined (ASSEMBLY) +#if !defined (__ASSEMBLER__) #if defined(CONFIG_XIP_ROM_SIZE) # if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK extern unsigned long AUTO_XIP_ROM_BASE; Modified: trunk/src/include/fallback.h ============================================================================== --- trunk/src/include/fallback.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/include/fallback.h Sun Apr 10 06:15:23 2011 (r6482) @@ -1,12 +1,12 @@ #ifndef FALLBACK_H #define FALLBACK_H -#if !defined(ASSEMBLY) && !defined(__PRE_RAM__) +#if !defined(__ASSEMBLER__) && !defined(__PRE_RAM__) void set_boot_successful(void); void boot_successful(void); -#endif /* ASSEMBLY */ +#endif /* __ASSEMBLER__ */ #define RTC_BOOT_BYTE 48 Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -21,9 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include Modified: trunk/src/mainboard/msi/ms7260/ap_romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/msi/ms7260/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/tyan/s2912/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include Modified: trunk/src/southbridge/amd/cs5535/cs5535.h ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/southbridge/amd/cs5535/cs5535.h Sun Apr 10 06:15:23 2011 (r6482) @@ -115,7 +115,7 @@ /* Flash Memory Mask values */ #define FLASH_MEM_4K 0xFFFFF000 -#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if defined(__PRE_RAM__) void cs5535_disable_internal_uart(void); #else Modified: trunk/src/southbridge/amd/cs5536/cs5536.h ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/southbridge/amd/cs5536/cs5536.h Sun Apr 10 06:15:23 2011 (r6482) @@ -442,7 +442,7 @@ #define FLASH_IO_128B 0x0000FF80 #define FLASH_IO_256B 0x0000FF00 -#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if defined(__PRE_RAM__) void cs5536_setup_onchipuart(int uart); void cs5536_disable_internal_uart(void); Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/southbridge/intel/i82371eb/i82371eb.h Sun Apr 10 06:15:23 2011 (r6482) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined(ASSEMBLY) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #if !defined(__ACPI__) /* dsdt include */ Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/southbridge/intel/i82801gx/i82801gx.h Sun Apr 10 06:15:23 2011 (r6482) @@ -38,7 +38,7 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); Modified: trunk/util/xcompile/xcompile ============================================================================== --- trunk/util/xcompile/xcompile Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/util/xcompile/xcompile Sun Apr 10 06:15:23 2011 (r6482) @@ -89,7 +89,6 @@ # elf${TWIDTH}-${TARCH} toolchain AS:=${GCCPREFIX}as ${ASFLAGS} CC:=${GCCPREFIX}gcc ${CFLAGS} -CPP:=${GCCPREFIX}cpp AR:=${GCCPREFIX}ar LD:=${GCCPREFIX}ld ${LDFLAGS} STRIP:=${GCCPREFIX}strip From hagigatali at gmail.com Sun Apr 10 08:14:39 2011 From: hagigatali at gmail.com (ali hagigat) Date: Sun, 10 Apr 2011 10:44:39 +0430 Subject: [coreboot] a question about hardware and PCI Message-ID: I have a general question about a PCI-to-PCI bridge. If the device has a positive decoder and receives an address in the range of the addresses it should respond. Then it claims the address and forwards it to the secondary interface. Now suppose no target on the secondary interface claims the transaction and master-abort happens for the second interface. What will happen to the primary interface then? Why PCI specifications do not explain the connection between the state machines of the primary and secondary interfaces? From sh4r4d at gmail.com Sun Apr 10 08:21:39 2011 From: sh4r4d at gmail.com (sh4r4d at gmail.com) Date: Sun, 10 Apr 2011 11:51:39 +0530 Subject: [coreboot] Help for motherboard References: <86pqqouuco.fsf@personal.machine.of.sharard.com> <4D5FD0F9.10407@gmail.com> <86hbc0ufkg.fsf@personal.machine.of.sharard.com> <4D6004A4.9050409@gmail.com> Message-ID: <86wrj24oek.fsf@personal.machine.of.sharard.com> On Sat, Feb 19 2011, Alex G. wrote: > On 02/19/2011 06:58 PM, sharad wrote: >> >> I wanted general purpose regular desktop for programming, internet, >> GNU/Linux with common servers dovecote, tomcat, apache etc >> > Probably a socket AM2+ board will be best for you if you want to run > coreboot. > > The Gigabyte GA-MA785GMT-UD2H is the only AM3 board supported. Someone > recently had a problem getting it to run, but at worst, it needs a bit > of tweaking. It has a COM port header, so we can use that to debug if > something may not be working. It doesn't include the adapter for the com > port, but that should be cheap to get. > > http://www.coreboot.org/GIGABYTE_GA-MA785GMT-UD2H > > The board has 4 hardware versions, so you may encounter issues depending > on which version you get. I'd definitely suggest AM3 versus the older > AM2/AM2+. > > You can also pick your favorite board and port it (which we'd all love :p ). > > Alex On Fri, Mar 04 2011, bari wrote: > Sharad wrote: >> So I wanted to know if I have to purchase `GIGABYTE_GA-MA785GMT-US2H' >> as `GIGABYTE_GA-MA785GMT-UD2H' is not available, Could it be easy >> to get coreboot in it as `GIGABYTE_GA-MA785GMT-UD2H' have been already >> supported, might be it is a newer version of `GIGABYTE_GA-MA785GMT-UD2H'? >> Either board works with coreboot with minor tweaking. Compare the > chipset, memory type and super IO on boards. If coreboot supports the > devices then most of the work is already done. Gigabyte boards usually > have the dual BIOS device circuit that make flash programming a bit > more complicated. You might have to check if Flashrom ever was patched > to support it. > -Bari Little more query as these are newer boards in market GA-880GA-UD3H GA-880GMA-UD2H GA-880GM-UD2H As GA-MA785GMT-UD2H already supported, Could its support would be helpful for easily porting above 880 boards for me, if they have something in common with GA-MA785GMT-UD2H. Thanks -- Regards, -sharad From corey.osgood at gmail.com Sun Apr 10 08:46:39 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Sun, 10 Apr 2011 02:46:39 -0400 Subject: [coreboot] a question about hardware and PCI In-Reply-To: References: Message-ID: On Sun, Apr 10, 2011 at 2:14 AM, ali hagigat wrote: > I have a general question about a PCI-to-PCI bridge. > If the device has a positive decoder and receives an address in the > range of the addresses it should respond. Then it claims the address > and forwards it to the secondary interface. Now suppose no target on > the secondary interface claims the transaction and master-abort > happens for the second interface. What will happen to the primary > interface then? > Why PCI specifications do not explain the connection between the state > machines of the primary and secondary interfaces? http://lmgtfy.com/?q=unclaimed+pci+transactions&l=1 From svn at coreboot.org Sun Apr 10 09:41:57 2011 From: svn at coreboot.org (repository service) Date: Sun, 10 Apr 2011 09:41:57 +0200 Subject: [coreboot] [commit] r6483 - trunk/src/northbridge/intel/i945 Message-ID: Author: svens Date: Sun Apr 10 09:41:56 2011 New Revision: 6483 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6483 Log: i945: improve get_top_of_ram() The current version doesn't honor TSEG, and fails to report the correct top of RAM if IGD is disabled. This is because it uses the BSM (base of stolen RAM) register. In that case, we should use the TOLUD register. Signed-off-by: Sven Schnelle Acked-by: Stefan Reinauer Modified: trunk/src/northbridge/intel/i945/raminit.c Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Sun Apr 10 06:15:23 2011 (r6482) +++ trunk/src/northbridge/intel/i945/raminit.c Sun Apr 10 09:41:56 2011 (r6483) @@ -3192,9 +3192,33 @@ unsigned long get_top_of_ram(void) { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom; + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + } else { + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x10000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x20000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x80000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } return (unsigned long) tom; } From hamo.by at gmail.com Sun Apr 10 14:49:32 2011 From: hamo.by at gmail.com (Hamo) Date: Sun, 10 Apr 2011 20:49:32 +0800 Subject: [coreboot] ask for ideas and suggestions about CBFS support on ARM Message-ID: Dear lists, I have be studying CBFS filesystem these days. Since coreboot only supports IA32 architecture now, the CBFS has hard-coded boot address and all the boot-related code and master header are located at around 0xFFFFFFF0. But as ARM read their first instruction at 0x0, we need change the CBFS filesystem but not destroy IA32 support. When porting to ARM, how should the rom be organized? I have 2 ideas: 1. Totally rewrite the CBFS structure on ARM according to that one on IA32 to meet the requirement of ARM architecture, including move the reset code and bootblock to the start of ROM(at address 0x0) and put all the other components follow them. In this way, we should rewrite the CBFStool and add a new option to CBFStool to tell it the architecture we are using. 2. Use the same structure on IA32 architecture but set the master header's offset to other value than 0x0 so that we can put boot code at the start of rom. Which one should I take or Do we have any better choice? Hope for your help. -- ? ? """ ? ? Keep It Simple,Stupid. ? ? """ Chinese Name: ?? Nick Name: Hamo Homepage: http://hamobai.com/ GPG KEY ID: 0xA4691A33 Key fingerprint = 09D5 2D78 8E2B 0995 CF8E? 4331 33C4 3D24 A469 1A33 From c-d.hailfinger.devel.2006 at gmx.net Sun Apr 10 17:40:05 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sun, 10 Apr 2011 17:40:05 +0200 Subject: [coreboot] ask for ideas and suggestions about CBFS support on ARM In-Reply-To: References: Message-ID: <4DA1CF55.4050302@gmx.net> Hi Hamo, I wrote a CBFS design change proposal ~2 years ago which handled such issues just fine, but IIRC nobody had time to comment. I can try to dig it up again. Regards, Carl-Daniel Am 10.04.2011 14:49 schrieb Hamo: > Dear lists, > I have be studying CBFS filesystem these days. Since coreboot only > supports IA32 architecture now, the CBFS has hard-coded boot address > and all the boot-related code and master header are located at around > 0xFFFFFFF0. But as ARM read their first instruction at 0x0, we need > change the CBFS filesystem but not destroy IA32 support. When porting > to ARM, how should the rom be organized? I have 2 ideas: > 1. Totally rewrite the CBFS structure on ARM according to that one on > IA32 to meet the requirement of ARM architecture, including move the > reset code and bootblock to the start of ROM(at address 0x0) and put > all the other components follow them. In this way, we should rewrite > the CBFStool and add a new option to CBFStool to tell it the > architecture we are using. > 2. Use the same structure on IA32 architecture but set the master > header's offset to other value than 0x0 so that we can put boot code > at the start of rom. > Which one should I take or Do we have any better choice? > Hope for your help. > > -- http://www.hailfinger.org/ From svens at stackframe.org Sun Apr 10 17:45:49 2011 From: svens at stackframe.org (Sven Schnelle) Date: Sun, 10 Apr 2011 17:45:49 +0200 Subject: [coreboot] [PATCH 2/2] PMH7: Add chip config In-Reply-To: <1302450349-22654-1-git-send-email-svens@stackframe.org> References: <1302450349-22654-1-git-send-email-svens@stackframe.org> Message-ID: <1302450349-22654-2-git-send-email-svens@stackframe.org> Signed-off-by: Sven Schnelle --- src/ec/lenovo/pmh7/chip.h | 9 +++++++++ src/ec/lenovo/pmh7/pmh7.c | 4 ++++ src/mainboard/lenovo/x60/devicetree.cb | 1 + src/mainboard/lenovo/x60/mainboard.c | 2 -- 4 files changed, 14 insertions(+), 2 deletions(-) create mode 100644 src/ec/lenovo/pmh7/chip.h diff --git a/src/ec/lenovo/pmh7/chip.h b/src/ec/lenovo/pmh7/chip.h new file mode 100644 index 0000000..e11b772 --- /dev/null +++ b/src/ec/lenovo/pmh7/chip.h @@ -0,0 +1,9 @@ +#ifndef EC_LENOVO_PMH7_CHIP_H +#define EC_LENOVO_PMH7_CHIP_H + +extern struct chip_operations ec_lenovo_pmh7_ops; + +struct ec_lenovo_pmh7_config { + int backlight_enable:1; +}; +#endif diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 47573a9..5d13b4e 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -23,6 +23,7 @@ #include #include #include "pmh7.h" +#include "chip.h" void pmh7_register_set_bit(int reg, int bit) { @@ -67,6 +68,7 @@ void pmh7_backlight_enable(int on) static void enable_dev(device_t dev) { + struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); @@ -75,6 +77,8 @@ static void enable_dev(device_t dev) resource->size = 16; resource->align = 5; resource->gran = 5; + + pmh7_backlight_enable(conf->backlight_enable); } struct chip_operations ec_lenovo_pmh7_ops = { diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index cdd1eae..947e213 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -85,6 +85,7 @@ chip northbridge/intel/i945 chip ec/lenovo/pmh7 device pnp ff.1 on # dummy end + register "backlight_enable" = "0x01" end chip ec/lenovo/h8ec device pnp ff.2 on # dummy diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 616fdc5..4b46eb0 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -39,8 +39,6 @@ static void mainboard_enable(device_t dev) { device_t dev0; - pmh7_backlight_enable(1); - /* enable Audio */ h8ec_set_audio_mute(0); -- 1.7.4.1 From svens at stackframe.org Sun Apr 10 17:45:48 2011 From: svens at stackframe.org (Sven Schnelle) Date: Sun, 10 Apr 2011 17:45:48 +0200 Subject: [coreboot] [PATCH 1/2] EC: Add Lenovo H8EC Message-ID: <1302450349-22654-1-git-send-email-svens@stackframe.org> Move the EC support code from the X60 mainboard to a generic driver, as this EC is used in many thinkpads. Also move the ACPI code to this directory for this reason. This patch also adds a chip config, so that the initial setting for basic register can be specified in devicetree.cb Signed-off-by: Sven Schnelle --- src/ec/lenovo/Kconfig | 1 + src/ec/lenovo/Makefile.inc | 1 + src/ec/lenovo/h8ec/Kconfig | 3 + src/ec/lenovo/h8ec/Makefile.inc | 1 + src/ec/lenovo/h8ec/acpi/ac.asl | 44 ++++ src/ec/lenovo/h8ec/acpi/battery.asl | 296 ++++++++++++++++++++++++ src/ec/lenovo/h8ec/acpi/beep.asl | 32 +++ src/ec/lenovo/h8ec/acpi/ec.asl | 122 ++++++++++ src/ec/lenovo/h8ec/acpi/lid.asl | 54 +++++ src/ec/lenovo/h8ec/acpi/sleepbutton.asl | 49 ++++ src/ec/lenovo/h8ec/acpi/systemstatus.asl | 63 +++++ src/ec/lenovo/h8ec/acpi/thermal.asl | 41 ++++ src/ec/lenovo/h8ec/chip.h | 36 +++ src/ec/lenovo/h8ec/h8ec.c | 129 ++++++++++ src/ec/lenovo/h8ec/h8ec.h | 111 +++++++++ src/ec/lenovo/pmh7/pmh7.c | 9 + src/ec/lenovo/pmh7/pmh7.h | 1 + src/mainboard/lenovo/x60/Kconfig | 2 +- src/mainboard/lenovo/x60/acpi/ac.asl | 44 ---- src/mainboard/lenovo/x60/acpi/battery.asl | 296 ------------------------ src/mainboard/lenovo/x60/acpi/beep.asl | 32 --- src/mainboard/lenovo/x60/acpi/dock.asl | 56 +++-- src/mainboard/lenovo/x60/acpi/ec.asl | 129 +---------- src/mainboard/lenovo/x60/acpi/gpe.asl | 4 +- src/mainboard/lenovo/x60/acpi/lid.asl | 54 ----- src/mainboard/lenovo/x60/acpi/sleepbutton.asl | 49 ---- src/mainboard/lenovo/x60/acpi/systemstatus.asl | 66 ------ src/mainboard/lenovo/x60/acpi/thermal.asl | 41 ---- src/mainboard/lenovo/x60/devicetree.cb | 18 ++- src/mainboard/lenovo/x60/dsdt.asl | 7 +- src/mainboard/lenovo/x60/mainboard.c | 67 +----- 31 files changed, 1054 insertions(+), 804 deletions(-) create mode 100644 src/ec/lenovo/h8ec/Kconfig create mode 100644 src/ec/lenovo/h8ec/Makefile.inc create mode 100644 src/ec/lenovo/h8ec/acpi/ac.asl create mode 100644 src/ec/lenovo/h8ec/acpi/battery.asl create mode 100644 src/ec/lenovo/h8ec/acpi/beep.asl create mode 100644 src/ec/lenovo/h8ec/acpi/ec.asl create mode 100644 src/ec/lenovo/h8ec/acpi/lid.asl create mode 100644 src/ec/lenovo/h8ec/acpi/sleepbutton.asl create mode 100644 src/ec/lenovo/h8ec/acpi/systemstatus.asl create mode 100644 src/ec/lenovo/h8ec/acpi/thermal.asl create mode 100644 src/ec/lenovo/h8ec/chip.h create mode 100644 src/ec/lenovo/h8ec/h8ec.c create mode 100644 src/ec/lenovo/h8ec/h8ec.h delete mode 100644 src/mainboard/lenovo/x60/acpi/ac.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/battery.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/beep.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/lid.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/sleepbutton.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/systemstatus.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/thermal.asl diff --git a/src/ec/lenovo/Kconfig b/src/ec/lenovo/Kconfig index b564b62..bf9cef5 100644 --- a/src/ec/lenovo/Kconfig +++ b/src/ec/lenovo/Kconfig @@ -1 +1,2 @@ source src/ec/lenovo/pmh7/Kconfig +source src/ec/lenovo/h8ec/Kconfig diff --git a/src/ec/lenovo/Makefile.inc b/src/ec/lenovo/Makefile.inc index f9a3feb..fa87b73 100644 --- a/src/ec/lenovo/Makefile.inc +++ b/src/ec/lenovo/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_EC_LENOVO_PMH7) += pmh7 +subdirs-$(CONFIG_EC_LENOVO_H8EC) += h8ec diff --git a/src/ec/lenovo/h8ec/Kconfig b/src/ec/lenovo/h8ec/Kconfig new file mode 100644 index 0000000..17b933c --- /dev/null +++ b/src/ec/lenovo/h8ec/Kconfig @@ -0,0 +1,3 @@ +config EC_LENOVO_H8EC + select EC_ACPI + bool diff --git a/src/ec/lenovo/h8ec/Makefile.inc b/src/ec/lenovo/h8ec/Makefile.inc new file mode 100644 index 0000000..0dcc9db --- /dev/null +++ b/src/ec/lenovo/h8ec/Makefile.inc @@ -0,0 +1 @@ +driver-y += h8ec.c diff --git a/src/ec/lenovo/h8ec/acpi/ac.asl b/src/ec/lenovo/h8ec/acpi/ac.asl new file mode 100644 index 0000000..cbc84b2 --- /dev/null +++ b/src/ec/lenovo/h8ec/acpi/ac.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x46), + , 4, + HPAC, 1 +} + +Device(AC) +{ + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return (HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return (0x0f) + } +} diff --git a/src/ec/lenovo/h8ec/acpi/battery.asl b/src/ec/lenovo/h8ec/acpi/battery.asl new file mode 100644 index 0000000..7168581 --- /dev/null +++ b/src/ec/lenovo/h8ec/acpi/battery.asl @@ -0,0 +1,296 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x38), + B0ST, 4, /* Battery 0 state */ + , 1, + B0CH, 1, /* Battery 0 charging */ + B0DI, 1, /* Battery 0 discharging */ + B0PR, 1, /* Battery 0 present */ + Offset (0x39), + B1ST, 4, /* Battery 1 state */ + , 1, + B1CH, 1, /* Battery 1 charging, */ + B1DI, 1, /* Battery 1 discharging,*/ + B1PR, 1 /* Battery 1 present */ +} + +/* EC Registers */ +/* PAGE == 0x00 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BARC, 16, /* Battery remaining capacity */ + BAFC, 16, /* Battery full charge capacity */ + Offset(0xa8), + BAPR, 16, /* Battery present rate */ + BAVO, 16, /* Battery Voltage */ +} + +/* PAGE == 0x01 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + , 15, + BAMA, 1, +} + +/* PAGE == 0x02 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BADC, 16, /* Design Capacity */ + BADV, 16, /* Design voltage */ + , 16, + , 16, + , 16, + BASN, 16, +} + +/* PAGE == 0x04: Battery type */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BATY, 32 +} + + +/* PAGE == 0x05: Battery OEM information */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BAOE, 128 +} + +/* PAGE == 0x06: Battery name */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BANA, 128 +} + +/* Arg0: Battery + * Arg1: Battery Status Package + * Arg2: charging + * Arg3: discharging + */ +Method(BSTA, 4, NotSerialized) +{ + Acquire(ECLK, 0xffff) + Store(0, Local0) + Or(1, Arg0, PAGE) + Store(BAMA, Local1) + Store(Arg0, PAGE) /* Battery dynamic information */ + + Store(BAPR, Local2) + + if (Arg2) // charging + { + Or(2, Local0, Local0) + + If (LGreaterEqual (Local2, 0x8000)) { + Store(0, Local2) + } + } + + if (Arg3) // discharging + { + Or(1, Local0, Local0) + Subtract(0x10000, Local2, Local2) + } + + Store(Local0, Index(Arg1, 0x00)) + + if (Local1) { + Multiply (BARC, 10, Index(Arg1, 2)) + Multiply (Local2, BAVO, Local2) + Divide (Local2, 1000, Local3, Index(Arg1, 1)) + } else { + Store(BARC, Index(Arg1, 2)) + Store(Local2, Index(Arg1, 1)) + } + Store(BAVO, Index(Arg1, 3)) + Release(ECLK) + Return (Arg1) +} + +Method(BINF, 2, NotSerialized) +{ + Acquire(ECLK, 0xffff) + Or(1, Arg1, PAGE) /* Battery 0 static information */ + Xor(BAMA, 1, Index(Arg0, 0)) + Store(BAMA, Local0) + Store(Arg1, PAGE) + Store(BAFC, Local2) + Or(2, Arg1, PAGE) + Store(BADC, Local1) + + if (Local0) + { + Multiply (Local1, 10, Local1) + Multiply (Local2, 10, Local2) + } + + Store(Local1, Index(Arg0, 1)) // Design Capacity + Store(Local2, Index(Arg0, 2)) // Last full charge capacity + Store(BADV, Index(Arg0, 4)) // Design Voltage + Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity + + Store (BASN, Local0) + Name (SERN, Buffer (0x06) { " " }) + Store (4, Local1) + While (Local0) + { + Divide (Local0, 0x0A, Local2, Local0) + Add (Local2, 48, Index (SERN, Local1)) + Decrement (Local1) + } + Store (SERN, Index (Arg0, 10)) // Serial Number + + Or(4, Arg1, PAGE) + Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) + Store(BATY, TYPE) + Store(TYPE, Index (Arg0, 11)) // Battery type + Or(5, Arg1, PAGE) + Store(BAOE, Index (Arg0, 12)) // OEM information + Or(6, Arg1, PAGE) + Store(BANA, Index (Arg0, 9)) // Model number + Release(ECLK) + Return (Arg0) +} + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 0x00) + Name (_PCL, Package () { \_SB }) + + Name (BATS, Package () + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage (mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 1, // 7: granularity1 + 1, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Method (_BIF, 0, NotSerialized) + { + Return (BINF(BATS, 0)) + } + + Name (BATI, Package () + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method (_BST, 0, NotSerialized) + { + if (B0PR) { + Return (BSTA(0, BATI, B0CH, B0DI)) + } else { + Return (BATS) + } + } + + Method (_STA, 0, NotSerialized) + { + if (B0PR) { + Return (0x1f) + } else { + Return (0x0f) + } + } +} + +Device (BAT1) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 0x00) + Name (_PCL, Package () { \_SB }) + + Name (BATS, Package () + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage (mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 1, // 7: granularity1 + 1, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Method (_BIF, 0, NotSerialized) + { + Return (BINF(BATS, 0x10)) + } + + Name (BATI, Package () + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method (_BST, 0, NotSerialized) + { + if (B1PR) { + Return (BSTA(0x10, BATI, B1CH, B1DI)) + } else { + Return (BATS) + } + } + + Method (_STA, 0, NotSerialized) + { + if (B1PR) { + Return (0x1f) + } else { + Return (0x0f) + } + } +} diff --git a/src/ec/lenovo/h8ec/acpi/beep.asl b/src/ec/lenovo/h8ec/acpi/beep.asl new file mode 100644 index 0000000..718f41b --- /dev/null +++ b/src/ec/lenovo/h8ec/acpi/beep.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x06), + SNDS, 8 /* Write to this register to generate sound */ + +} + +Method(BEEP, 1, NotSerialized) +{ + Store (Arg0, SNDS) +} diff --git a/src/ec/lenovo/h8ec/acpi/ec.asl b/src/ec/lenovo/h8ec/acpi/ec.asl new file mode 100644 index 0000000..f09e557 --- /dev/null +++ b/src/ec/lenovo/h8ec/acpi/ec.asl @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "smi.h" +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, 28) + Mutex (ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x05), + HSPA, 1, + Offset (0x0C), + LEDS, 8, /* LED state */ + Offset (0x3a), + AMUT, 1, /* Audio Mute */ + Offset (0x3B), + , 1, + KBLT, 1, /* Keyboard Light */ + Offset (0x4e), + WAKE, 16, + Offset (0x78), + TMP0, 8, /* Thermal Zone 0 temperature */ + TMP1, 8, /* Thermal Zone 1 temperature */ + Offset (0x81), + PAGE, 8 /* Information Page Selector */ + } + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + Return (ECMD) + } + + Method (LED, 1, NotSerialized) + { + Store(Arg0, LEDS) + } + + Method (_INI, 0, NotSerialized) + { + } + + Method (MUTE, 1, NotSerialized) + { + Store(Arg0, AMUT) + } + + /* Sleep Button pressed */ + Method(_Q13, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80) + } + + /* Brightness up GPE */ + Method(_Q14, 0, NotSerialized) + { + \DSPC.BRTU () + } + + /* Brightness down GPE */ + Method(_Q15, 0, NotSerialized) + { + \DSPC.BRTD() + } + + /* AC status change: present */ + Method(_Q26, 0, NotSerialized) + { + Notify (AC, 0x80) + } + + /* AC status change: not present */ + Method(_Q27, 0, NotSerialized) + { + Notify (AC, 0x80) + } + + Method(_Q2A, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) + } + + Method(_Q2B, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) + } + + +#include "ac.asl" +#include "battery.asl" +#include "sleepbutton.asl" +#include "lid.asl" +#include "beep.asl" +} diff --git a/src/ec/lenovo/h8ec/acpi/lid.asl b/src/ec/lenovo/h8ec/acpi/lid.asl new file mode 100644 index 0000000..2dfa8d1 --- /dev/null +++ b/src/ec/lenovo/h8ec/acpi/lid.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x32), + , 2, + WKLD, 1, + Offset (0x46), + , 2, + LIDS, 1 +} + +Device(LID) +{ + Name(_HID, "PNP0C0D") + + Method(_LId, 0, NotSerialized) + { + return (LIDS) + } + + Method(_PRW, 0, NotSerialized) + { + Return (Package() { 0x18, 0x03 }) + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + Store(1, WKLD) + } else { + Store(0, WKLD) + } + } +} diff --git a/src/ec/lenovo/h8ec/acpi/sleepbutton.asl b/src/ec/lenovo/h8ec/acpi/sleepbutton.asl new file mode 100644 index 0000000..09e88aa --- /dev/null +++ b/src/ec/lenovo/h8ec/acpi/sleepbutton.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x32), + , 4, + WKFN, 1, + Offset(0x83), + FNKY, 8 +} + +Device(SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Method(_PRW, 0, NotSerialized) + { + Return (Package() { 0x18, 0x03 }) + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + Store(6, FNKY) /* Fn key acts as wake button */ + Store(1, WKFN) + } else { + Store(0, FNKY) /* Fn key normal operation */ + Store(0, WKFN) + } + } +} diff --git a/src/ec/lenovo/h8ec/acpi/systemstatus.asl b/src/ec/lenovo/h8ec/acpi/systemstatus.asl new file mode 100644 index 0000000..17e8ba7 --- /dev/null +++ b/src/ec/lenovo/h8ec/acpi/systemstatus.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +Scope (\_SI) +{ + Method(_SST, 1, NotSerialized) + { + If (LEqual (Arg0, 0)) { + /* Indicator off */ + + /* power LED off */ + \_SB.PCI0.LPCB.EC.LED(0x00) + /* suspend LED off */ + \_SB.PCI0.LPCB.EC.LED(0x07) + } + + If (LEqual (Arg0, 1)) { + /* working state */ + + /* power LED on */ + \_SB.PCI0.LPCB.EC.LED(0x80) + /* suspend LED off */ + \_SB.PCI0.LPCB.EC.LED(0x07) + } + + If (LEqual (Arg0, 2)) { + /* waking state */ + + /* power LED om */ + \_SB.PCI0.LPCB.EC.LED(0x80) + /* suspend LED blinking */ + \_SB.PCI0.LPCB.EC.LED(0xc7) + } + + If (LEqual (Arg0, 3)) { + /* sleep state */ + + /* power LED off */ + \_SB.PCI0.LPCB.EC.LED(0x00) + /* suspend LED on */ + \_SB.PCI0.LPCB.EC.LED(0x87) + } + } +} diff --git a/src/ec/lenovo/h8ec/acpi/thermal.asl b/src/ec/lenovo/h8ec/acpi/thermal.asl new file mode 100644 index 0000000..35b6f14 --- /dev/null +++ b/src/ec/lenovo/h8ec/acpi/thermal.asl @@ -0,0 +1,41 @@ +Scope(\_TZ) +{ + Method(C2K, 1, NotSerialized) + { + Multiply(Arg0, 10, Local0) + Add (Local0, 2732, Local0) + if (LLessEqual(Local0, 2732)) { + Return (3000) + } + + if (LGreater(Local0, 4012)) { + Return (3000) + } + Return (Local0) + } + + ThermalZone(THM0) + { + Method(_CRT, 0, NotSerialized) { + Return (C2K(127)) + } + Method(_TMP) { + Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) + } + } + + ThermalZone(THM1) + { + Method(_CRT, 0, NotSerialized) { + Return (C2K(99)) + } + + Method(_PSV, 0, NotSerialized) { + Return (C2K(94)) + } + + Method(_TMP) { + Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) + } + } +} diff --git a/src/ec/lenovo/h8ec/chip.h b/src/ec/lenovo/h8ec/chip.h new file mode 100644 index 0000000..1926874 --- /dev/null +++ b/src/ec/lenovo/h8ec/chip.h @@ -0,0 +1,36 @@ +#ifndef EC_LENOVO_H8EC_CHIP_H +#define EC_LENOVO_H8EC_CHIP_H + +extern struct chip_operations ec_lenovo_h8ec_ops; +struct ec_lenovo_h8ec_config { + + u8 config0; + u8 config1; + u8 config2; + u8 config3; + + u8 beepmask0; + u8 beepmask1; + + u8 event0_enable; + u8 event1_enable; + u8 event2_enable; + u8 event3_enable; + u8 event4_enable; + u8 event5_enable; + u8 event6_enable; + u8 event7_enable; + u8 event8_enable; + u8 event9_enable; + u8 eventa_enable; + u8 eventb_enable; + u8 eventc_enable; + u8 eventd_enable; + u8 evente_enable; + u8 eventf_enable; + + u8 trackpoint_enable; + u8 wlan_enable; + u8 wwan_enable; +}; +#endif diff --git a/src/ec/lenovo/h8ec/h8ec.c b/src/ec/lenovo/h8ec/h8ec.c new file mode 100644 index 0000000..df7edcf --- /dev/null +++ b/src/ec/lenovo/h8ec/h8ec.c @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "h8ec.h" +#include "chip.h" + +void h8ec_trackpoint_enable(int on) +{ + ec_write(H8EC_TRACKPOINT_CTRL, + on ? H8EC_TRACKPOINT_ON : H8EC_TRACKPOINT_OFF); + +} + +void h8ec_wlan_enable(int on) +{ + if (on) + ec_set_bit(0x3a, 5); + else + ec_clr_bit(0x3a, 5); +} + +static void h8ec_log_ec_version(void) +{ + unsigned char ecfw[9], c; + u16 fwvh, fwvl; + int i; + + for(i = 0; i < 8; i++) { + c = ec_read(0xf0 + i); + if (c < 0x20 || c > 0x7f) + break; + ecfw[i] = c; + } + ecfw[i] = '\0'; + + fwvh = ec_read(0xe9); + fwvl = ec_read(0xe8); + + printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); +} + +void h8ec_set_audio_mute(int on) +{ + if (on) + ec_clr_bit(0x3a, 0); + else + ec_set_bit(0x3a, 1); +} + +void h8ec_enable_event(int event) +{ + if (event < 0 || event > 127) + return; + + ec_set_bit(0x10 + (event >> 3), event & 7); +} + +void h8ec_disable_event(int event) +{ + if (event < 0 || event > 127) + return; + + ec_clr_bit(0x10 + (event >> 3), event & 7); + +} + +static void h8ec_enable(device_t dev) +{ + struct ec_lenovo_h8ec_config *conf = dev->chip_info; + h8ec_log_ec_version(); + + ec_write(H8EC_CONFIG0, conf->config0); + ec_write(H8EC_CONFIG1, conf->config1); + ec_write(H8EC_CONFIG2, conf->config2); + ec_write(H8EC_CONFIG3, conf->config3); + + ec_write(H8EC_SOUND_ENABLE0, conf->beepmask0); + ec_write(H8EC_SOUND_ENABLE1, conf->beepmask1); + ec_write(H8EC_SOUND_REPEAT, 0x00); + + ec_write(0x10, conf->event0_enable); + ec_write(0x11, conf->event1_enable); + ec_write(0x12, conf->event2_enable); + ec_write(0x13, conf->event3_enable); + ec_write(0x14, conf->event4_enable); + ec_write(0x15, conf->event5_enable); + ec_write(0x16, conf->event6_enable); + ec_write(0x17, conf->event7_enable); + ec_write(0x18, conf->event8_enable); + ec_write(0x19, conf->event9_enable); + ec_write(0x1a, conf->eventa_enable); + ec_write(0x1b, conf->eventb_enable); + ec_write(0x1c, conf->eventc_enable); + ec_write(0x1d, conf->eventd_enable); + ec_write(0x1e, conf->evente_enable); + ec_write(0x1f, conf->eventf_enable); + + h8ec_wlan_enable(conf->wlan_enable); + h8ec_trackpoint_enable(conf->trackpoint_enable); + +} + +struct chip_operations ec_lenovo_h8ec_ops = { + CHIP_NAME("Lenovo H8 EC") + .enable_dev = h8ec_enable +}; diff --git a/src/ec/lenovo/h8ec/h8ec.h b/src/ec/lenovo/h8ec/h8ec.h new file mode 100644 index 0000000..3d30e8c --- /dev/null +++ b/src/ec/lenovo/h8ec/h8ec.h @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef EC_LENOVO_H8EC_H +#define EC_LENOVO_H8EC_H + +void h8ec_trackpoint_enable(int on); +void h8ec_wlan_enable(int on); +void h8ec_set_audio_mute(int on); +void h8ec_enable_event(int event); +void h8ec_disable_event(int event); + +/* EC registers */ +#define H8EC_CONFIG0 0x00 +#define H8EC_CONFIG0_EVENTS_ENABLE 0x02 +#define H8EC_CONFIG0_HOTKEY_ENABLE 0x04 +#define H8EC_CONFIG0_SMM_H8EC_ENABLE 0x20 +#define H8EC_CONFIG0_TC_ENABLE 0x80 + +#define H8EC_CONFIG1 0x01 +#define H8EC_CONFIG1_BKLT_LID 0x01 +#define H8EC_CONFIG1_UBAY_PWR 0x20 + +#define H8EC_CONFIG2 0x02 +#define H8EC_CONFIG2_USB_DOCK 0x01 +#define H8EC_CONFIG2_DOCK_SPEAKER_MUTE 0x02 +#define H8EC_CONFIG2_DOCK_SPEAKER_MUTE_POL 0x04 + +#define H8EC_CONFIG3 0x03 + +#define H8EC_SOUND_ENABLE0 0x04 +#define H8EC_SOUND_ENABLE1 0x05 +#define H8EC_SOUND_REG 0x06 +#define H8EC_SOUND_REPEAT 0x07 + +#define H8EC_TRACKPOINT_CTRL 0x0B +#define H8EC_TRACKPOINT_AUTO 0x01 +#define H8EC_TRACKPOINT_OFF 0x02 +#define H8EC_TRACKPOINT_ON 0x03 + +#define H8EC_LED_CONTROL 0x0c +#define H8EC_LED_CONTROL_OFF 0x00 +#define H8EC_LED_CONTROL_ON 0x80 +#define H8EC_LED_CONTROL_BLINK 0xc0 + +#define H8EC_LED_CONTROL_POWER_LED 0x00 +#define H8EC_LED_CONTROL_BAT0_LED 0x01 +#define H8EC_LED_CONTROL_BAT1_LED 0x02 +#define H8EC_LED_CONTROL_UBAY_LED 0x04 +#define H8EC_LED_CONTROL_SUSPEND_LED 0x07 +#define H8EC_LED_CONTROL_DOCK_LED1 0x08 +#define H8EC_LED_CONTROL_DOCK_LED2 0x09 + +/* Embedded controller events */ +#define H8EC_EVENT_FN_F1 0x10 +#define H8EC_EVENT_FN_F2 0x11 +#define H8EC_EVENT_FN_F3 0x12 +#define H8EC_EVENT_FN_F4 0x13 +#define H8EC_EVENT_FN_HOME 0x14 +#define H8EC_EVENT_FN_END 0x15 +#define H8EC_EVENT_FN_F7 0x16 +#define H8EC_EVENT_FN_F8 0x17 +#define H8EC_EVENT_FN_F9 0x18 +#define H8EC_EVENT_FN_THINKVANTAGE 0x19 +#define H8EC_EVENT_FN_F11 0x1a +#define H8EC_EVENT_FN_F12 0x1b +#define H8EC_EVENT_FN_1 0x1c +#define H8EC_EVENT_FN_2 0x1d +#define H8EC_EVENT_FN_PGUP 0x1f + +#define H8EC_EVENT_AC_ON 0x26 +#define H8EC_EVENT_AC_OFF 0x27 + +#define H8EC_EVENT_PWRSW_PRESS 0x28 +#define H8EC_EVENT_PWRSW_RELEASE 0x29 + +#define H8EC_EVENT_LIDSW_CLOSE 0x2a +#define H8EC_EVENT_LIDSW_PUSH 0x2b + +#define H8EC_EVENT_UBAY_UNLOCK 0x2c +#define H8EC_EVENT_UBAY_LOCK 0x2d + +#define H8EC_EVENT_KEYPRESS 0x33 + +#define H8EC_EVENT_FN_PRESS 0x39 + +#define H8EC_EVENT_BAT0 0x4a +#define H8EC_EVENT_BAT0_STATE 0x4b + +#define H8EC_EVENT_BAT1 0x4c +#define H8EC_EVENT_BAT1_STATE 0x4d + +#define H8EC_EVENT_FN_F5 0x64 +#define H8EC_EVENT_FN_F6 0x65 +#endif diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index a46e179..47573a9 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -56,6 +56,15 @@ void pmh7_register_write(int reg, int val) outb(val, EC_LENOVO_PMH7_DATA); } +void pmh7_backlight_enable(int on) +{ + if (on) + pmh7_register_set_bit(0x50, 5); + else + pmh7_register_clear_bit(0x50, 5); + +} + static void enable_dev(device_t dev) { struct resource *resource; diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h index a4a61cc..8f4f5ab 100644 --- a/src/ec/lenovo/pmh7/pmh7.h +++ b/src/ec/lenovo/pmh7/pmh7.h @@ -31,4 +31,5 @@ void pmh7_register_clear_bit(int reg, int bit); char pmh7_register_read(int reg); void pmh7_register_write(int reg, int val); +void pmh7_backlight_enable(int on); #endif diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index ebd2c1c..9befde2 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87392 select EC_LENOVO_PMH7 - select EC_ACPI + select EC_LENOVO_H8EC select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/x60/acpi/ac.asl b/src/mainboard/lenovo/x60/acpi/ac.asl deleted file mode 100644 index cbc84b2..0000000 --- a/src/mainboard/lenovo/x60/acpi/ac.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x46), - , 4, - HPAC, 1 -} - -Device(AC) -{ - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) - - Method(_PSR, 0, NotSerialized) - { - return (HPAC) - } - - Method(_STA, 0, NotSerialized) - { - Return (0x0f) - } -} diff --git a/src/mainboard/lenovo/x60/acpi/battery.asl b/src/mainboard/lenovo/x60/acpi/battery.asl deleted file mode 100644 index 7168581..0000000 --- a/src/mainboard/lenovo/x60/acpi/battery.asl +++ /dev/null @@ -1,296 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x38), - B0ST, 4, /* Battery 0 state */ - , 1, - B0CH, 1, /* Battery 0 charging */ - B0DI, 1, /* Battery 0 discharging */ - B0PR, 1, /* Battery 0 present */ - Offset (0x39), - B1ST, 4, /* Battery 1 state */ - , 1, - B1CH, 1, /* Battery 1 charging, */ - B1DI, 1, /* Battery 1 discharging,*/ - B1PR, 1 /* Battery 1 present */ -} - -/* EC Registers */ -/* PAGE == 0x00 */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BARC, 16, /* Battery remaining capacity */ - BAFC, 16, /* Battery full charge capacity */ - Offset(0xa8), - BAPR, 16, /* Battery present rate */ - BAVO, 16, /* Battery Voltage */ -} - -/* PAGE == 0x01 */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - , 15, - BAMA, 1, -} - -/* PAGE == 0x02 */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BADC, 16, /* Design Capacity */ - BADV, 16, /* Design voltage */ - , 16, - , 16, - , 16, - BASN, 16, -} - -/* PAGE == 0x04: Battery type */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BATY, 32 -} - - -/* PAGE == 0x05: Battery OEM information */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BAOE, 128 -} - -/* PAGE == 0x06: Battery name */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BANA, 128 -} - -/* Arg0: Battery - * Arg1: Battery Status Package - * Arg2: charging - * Arg3: discharging - */ -Method(BSTA, 4, NotSerialized) -{ - Acquire(ECLK, 0xffff) - Store(0, Local0) - Or(1, Arg0, PAGE) - Store(BAMA, Local1) - Store(Arg0, PAGE) /* Battery dynamic information */ - - Store(BAPR, Local2) - - if (Arg2) // charging - { - Or(2, Local0, Local0) - - If (LGreaterEqual (Local2, 0x8000)) { - Store(0, Local2) - } - } - - if (Arg3) // discharging - { - Or(1, Local0, Local0) - Subtract(0x10000, Local2, Local2) - } - - Store(Local0, Index(Arg1, 0x00)) - - if (Local1) { - Multiply (BARC, 10, Index(Arg1, 2)) - Multiply (Local2, BAVO, Local2) - Divide (Local2, 1000, Local3, Index(Arg1, 1)) - } else { - Store(BARC, Index(Arg1, 2)) - Store(Local2, Index(Arg1, 1)) - } - Store(BAVO, Index(Arg1, 3)) - Release(ECLK) - Return (Arg1) -} - -Method(BINF, 2, NotSerialized) -{ - Acquire(ECLK, 0xffff) - Or(1, Arg1, PAGE) /* Battery 0 static information */ - Xor(BAMA, 1, Index(Arg0, 0)) - Store(BAMA, Local0) - Store(Arg1, PAGE) - Store(BAFC, Local2) - Or(2, Arg1, PAGE) - Store(BADC, Local1) - - if (Local0) - { - Multiply (Local1, 10, Local1) - Multiply (Local2, 10, Local2) - } - - Store(Local1, Index(Arg0, 1)) // Design Capacity - Store(Local2, Index(Arg0, 2)) // Last full charge capacity - Store(BADV, Index(Arg0, 4)) // Design Voltage - Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity - - Store (BASN, Local0) - Name (SERN, Buffer (0x06) { " " }) - Store (4, Local1) - While (Local0) - { - Divide (Local0, 0x0A, Local2, Local0) - Add (Local2, 48, Index (SERN, Local1)) - Decrement (Local1) - } - Store (SERN, Index (Arg0, 10)) // Serial Number - - Or(4, Arg1, PAGE) - Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) - Store(BATY, TYPE) - Store(TYPE, Index (Arg0, 11)) // Battery type - Or(5, Arg1, PAGE) - Store(BAOE, Index (Arg0, 12)) // OEM information - Or(6, Arg1, PAGE) - Store(BANA, Index (Arg0, 9)) // Model number - Release(ECLK) - Return (Arg0) -} - -Device (BAT0) -{ - Name (_HID, EisaId ("PNP0C0A")) - Name (_UID, 0x00) - Name (_PCL, Package () { \_SB }) - - Name (BATS, Package () - { - 0x00, // 0: PowerUnit: Report in mWh - 0xFFFFFFFF, // 1: Design cap - 0xFFFFFFFF, // 2: Last full charge cap - 0x01, // 3: Battery Technology - 10800, // 4: Design Voltage (mV) - 0x00, // 5: Warning design capacity - 200, // 6: Low design capacity - 1, // 7: granularity1 - 1, // 8: granularity2 - "", // 9: Model number - "", // A: Serial number - "", // B: Battery Type - "" // C: OEM information - }) - - Method (_BIF, 0, NotSerialized) - { - Return (BINF(BATS, 0)) - } - - Name (BATI, Package () - { - 0, // Battery State - // Bit 0 - discharge - // Bit 1 - charge - // Bit 2 - critical state - 0, // Battery present Rate - 0, // Battery remaining capacity - 0 // Battery present voltage - }) - - Method (_BST, 0, NotSerialized) - { - if (B0PR) { - Return (BSTA(0, BATI, B0CH, B0DI)) - } else { - Return (BATS) - } - } - - Method (_STA, 0, NotSerialized) - { - if (B0PR) { - Return (0x1f) - } else { - Return (0x0f) - } - } -} - -Device (BAT1) -{ - Name (_HID, EisaId ("PNP0C0A")) - Name (_UID, 0x00) - Name (_PCL, Package () { \_SB }) - - Name (BATS, Package () - { - 0x00, // 0: PowerUnit: Report in mWh - 0xFFFFFFFF, // 1: Design cap - 0xFFFFFFFF, // 2: Last full charge cap - 0x01, // 3: Battery Technology - 10800, // 4: Design Voltage (mV) - 0x00, // 5: Warning design capacity - 200, // 6: Low design capacity - 1, // 7: granularity1 - 1, // 8: granularity2 - "", // 9: Model number - "", // A: Serial number - "", // B: Battery Type - "" // C: OEM information - }) - - Method (_BIF, 0, NotSerialized) - { - Return (BINF(BATS, 0x10)) - } - - Name (BATI, Package () - { - 0, // Battery State - // Bit 0 - discharge - // Bit 1 - charge - // Bit 2 - critical state - 0, // Battery present Rate - 0, // Battery remaining capacity - 0 // Battery present voltage - }) - - Method (_BST, 0, NotSerialized) - { - if (B1PR) { - Return (BSTA(0x10, BATI, B1CH, B1DI)) - } else { - Return (BATS) - } - } - - Method (_STA, 0, NotSerialized) - { - if (B1PR) { - Return (0x1f) - } else { - Return (0x0f) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi/beep.asl b/src/mainboard/lenovo/x60/acpi/beep.asl deleted file mode 100644 index 718f41b..0000000 --- a/src/mainboard/lenovo/x60/acpi/beep.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x06), - SNDS, 8 /* Write to this register to generate sound */ - -} - -Method(BEEP, 1, NotSerialized) -{ - Store (Arg0, SNDS) -} diff --git a/src/mainboard/lenovo/x60/acpi/dock.asl b/src/mainboard/lenovo/x60/acpi/dock.asl index db61e05..d393f44 100644 --- a/src/mainboard/lenovo/x60/acpi/dock.asl +++ b/src/mainboard/lenovo/x60/acpi/dock.asl @@ -21,35 +21,47 @@ #include "smi.h" -OperationRegion (DLPC, SystemIO, 0x164c, 1) -Field(DLPC, ByteAcc, NoLock, Preserve) +Scope (\_SB) { - , 3, - DSTA, 1, -} -Device(DOCK) -{ - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) + OperationRegion (DLPC, SystemIO, 0x164c, 1) + Field(DLPC, ByteAcc, NoLock, Preserve) + { + , 3, + DSTA, 1, + } - Method(_DCK, 1, NotSerialized) + Device(DOCK) { - if (Arg0) { - Sleep(250) - /* connect dock */ - TRAP(SMI_DOCK_CONNECT) - } else { - /* disconnect dock */ - TRAP(SMI_DOCK_DISCONNECT) + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + Sleep(250) + /* connect dock */ + TRAP(SMI_DOCK_CONNECT) + } else { + /* disconnect dock */ + TRAP(SMI_DOCK_DISCONNECT) + } + + Xor(Arg0, DSTA, Local0) + Return (Local0) } - Xor(Arg0, DSTA, Local0) - Return (Local0) + Method(_STA, 0, NotSerialized) + { + Return (DSTA) + } } +} - Method(_STA, 0, NotSerialized) +Scope(\_SB.PCI0.LPCB.EC) +{ + Method(_Q18, 0, NotSerialized) { - Return (DSTA) + Notify(\_SB.DOCK, 3) } } diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl index 85ea491..878dd03 100644 --- a/src/mainboard/lenovo/x60/acpi/ec.asl +++ b/src/mainboard/lenovo/x60/acpi/ec.asl @@ -1,128 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include "smi.h" -Device(EC) -{ - Name (_HID, EISAID("PNP0C09")) - Name (_UID, 0) - - Name (_GPE, 28) - Mutex (ECLK, 0) - - OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) - Field (ERAM, ByteAcc, NoLock, Preserve) - { - Offset (0x05), - HSPA, 1, - Offset (0x0C), - LEDS, 8, /* LED state */ - Offset (0x3a), - AMUT, 1, /* Audio Mute */ - Offset (0x3B), - , 1, - KBLT, 1, /* Keyboard Light */ - Offset (0x4e), - WAKE, 16, - Offset (0x78), - TMP0, 8, /* Thermal Zone 0 temperature */ - TMP1, 8, /* Thermal Zone 1 temperature */ - Offset (0x81), - PAGE, 8 /* Information Page Selector */ - } - - Method (_CRS, 0) - { - Name (ECMD, ResourceTemplate() - { - IO (Decode16, 0x62, 0x62, 1, 1) - IO (Decode16, 0x66, 0x66, 1, 1) - }) - Return (ECMD) - } - - Method (LED, 1, NotSerialized) - { - Store(Arg0, LEDS) - } - - Method (_INI, 0, NotSerialized) - { - } - - Method (MUTE, 1, NotSerialized) - { - Store(Arg0, AMUT) - } - - /* Sleep Button pressed */ - Method(_Q13, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80) - } - - /* Brightness up GPE */ - Method(_Q14, 0, NotSerialized) - { - \DSPC.BRTU () - } - - /* Brightness down GPE */ - Method(_Q15, 0, NotSerialized) - { - \DSPC.BRTD() - } - - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) - } - - /* AC status change: present */ - Method(_Q26, 0, NotSerialized) - { - Notify (AC, 0x80) - } - - /* AC status change: not present */ - Method(_Q27, 0, NotSerialized) - { - Notify (AC, 0x80) - } - - Method(_Q2A, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) - } - - Method(_Q2B, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) - } - - -#include "ac.asl" -#include "battery.asl" -#include "sleepbutton.asl" -#include "lid.asl" -#include "beep.asl" -#include "dock.asl" -} +#include diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl index 64e8e31..3aa9615 100644 --- a/src/mainboard/lenovo/x60/acpi/gpe.asl +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -12,10 +12,10 @@ Scope (\_GPE) { if (GP13) { Or(GIV1, 0x20, GIV1) - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) + Notify(\_SB.DOCK, 3) } else { And(GIV1, 0xdf, GIV1) - Notify(\_SB.PCI0.LPCB.EC.DOCK, 0) + Notify(\_SB.DOCK, 0) } } } diff --git a/src/mainboard/lenovo/x60/acpi/lid.asl b/src/mainboard/lenovo/x60/acpi/lid.asl deleted file mode 100644 index 2dfa8d1..0000000 --- a/src/mainboard/lenovo/x60/acpi/lid.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x32), - , 2, - WKLD, 1, - Offset (0x46), - , 2, - LIDS, 1 -} - -Device(LID) -{ - Name(_HID, "PNP0C0D") - - Method(_LId, 0, NotSerialized) - { - return (LIDS) - } - - Method(_PRW, 0, NotSerialized) - { - Return (Package() { 0x18, 0x03 }) - } - - Method(_PSW, 1, NotSerialized) - { - if (Arg0) { - Store(1, WKLD) - } else { - Store(0, WKLD) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi/sleepbutton.asl b/src/mainboard/lenovo/x60/acpi/sleepbutton.asl deleted file mode 100644 index 09e88aa..0000000 --- a/src/mainboard/lenovo/x60/acpi/sleepbutton.asl +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x32), - , 4, - WKFN, 1, - Offset(0x83), - FNKY, 8 -} - -Device(SLPB) -{ - Name (_HID, EisaId ("PNP0C0E")) - Method(_PRW, 0, NotSerialized) - { - Return (Package() { 0x18, 0x03 }) - } - - Method(_PSW, 1, NotSerialized) - { - if (Arg0) { - Store(6, FNKY) /* Fn key acts as wake button */ - Store(1, WKFN) - } else { - Store(0, FNKY) /* Fn key normal operation */ - Store(0, WKFN) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi/systemstatus.asl b/src/mainboard/lenovo/x60/acpi/systemstatus.asl deleted file mode 100644 index 161be08..0000000 --- a/src/mainboard/lenovo/x60/acpi/systemstatus.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - - -Scope (\_SI) -{ - Method(_SST, 1, NotSerialized) - { - If (LEqual (Arg0, 0)) { - /* Indicator off */ - - /* power LED off */ - \_SB.PCI0.LPCB.EC.LED(0x00) - /* suspend LED off */ - \_SB.PCI0.LPCB.EC.LED(0x07) - } - - If (LEqual (Arg0, 1)) { - /* working state */ - - /* power LED on */ - \_SB.PCI0.LPCB.EC.LED(0x80) - /* suspend LED off */ - \_SB.PCI0.LPCB.EC.LED(0x07) - } - - If (LEqual (Arg0, 2)) { - /* waking state */ - - /* power LED om */ - \_SB.PCI0.LPCB.EC.LED(0x80) - /* suspend LED blinking */ - \_SB.PCI0.LPCB.EC.LED(0xc7) - } - - If (LEqual (Arg0, 3)) { - /* sleep state */ - - /* power LED off */ - \_SB.PCI0.LPCB.EC.LED(0x00) - /* suspend LED on */ - \_SB.PCI0.LPCB.EC.LED(0x87) - } - - - - } -} diff --git a/src/mainboard/lenovo/x60/acpi/thermal.asl b/src/mainboard/lenovo/x60/acpi/thermal.asl deleted file mode 100644 index 35b6f14..0000000 --- a/src/mainboard/lenovo/x60/acpi/thermal.asl +++ /dev/null @@ -1,41 +0,0 @@ -Scope(\_TZ) -{ - Method(C2K, 1, NotSerialized) - { - Multiply(Arg0, 10, Local0) - Add (Local0, 2732, Local0) - if (LLessEqual(Local0, 2732)) { - Return (3000) - } - - if (LGreater(Local0, 4012)) { - Return (3000) - } - Return (Local0) - } - - ThermalZone(THM0) - { - Method(_CRT, 0, NotSerialized) { - Return (C2K(127)) - } - Method(_TMP) { - Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) - } - } - - ThermalZone(THM1) - { - Method(_CRT, 0, NotSerialized) { - Return (C2K(99)) - } - - Method(_PSV, 0, NotSerialized) { - Return (C2K(94)) - } - - Method(_TMP) { - Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) - } - } -} diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 2817255..cdd1eae 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -86,13 +86,29 @@ chip northbridge/intel/i945 device pnp ff.1 on # dummy end end - chip ec/acpi + chip ec/lenovo/h8ec device pnp ff.2 on # dummy io 0x60 = 0x62 io 0x62 = 0x66 io 0x64 = 0x1600 io 0x66 = 0x1604 end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0x05" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + + register "wlan_enable" = "0x01" + register "trackpoint_enable" = "0x03" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 3467a8b..905c94a 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -40,10 +40,6 @@ DefinitionBlock( // mainboard specific devices #include "acpi/mainboard.asl" - // Thermal Zone - #include "acpi/thermal.asl" - // System status indicators - #include "acpi/systemstatus.asl" Scope (\_SB) { Device (PCI0) { @@ -54,4 +50,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + + // Dock support code + #include "acpi/dock.asl" } diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index c2aaaa9..616fdc5 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -32,78 +32,17 @@ #include #include #include +#include #include -static void backlight_enable(void) -{ - pmh7_register_set_bit(0x50, 5); -} - -static void trackpoint_enable(void) -{ - ec_write(0x0b, 0x03); -} - -static void wlan_enable(void) -{ - ec_write(0x3a, 0x20); -} - -static void log_ec_version(void) -{ - unsigned char ecfw[9], c; - u16 fwvh, fwvl; - int i; - - for(i = 0; i < 8; i++) { - c = ec_read(0xf0 + i); - if (c < 0x20 || c > 0x7f) - break; - ecfw[i] = c; - } - ecfw[i] = '\0'; - - fwvh = ec_read(0xe9); - fwvl = ec_read(0xe8); - - printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, - fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); -} - static void mainboard_enable(device_t dev) { device_t dev0; - log_ec_version(); - - backlight_enable(); - trackpoint_enable(); - - /* FIXME: this should be ACPI's task - * but for now, enable it here */ - wlan_enable(); - - /* enable ACPI events */ - ec_write(0x00, 0xa6); - ec_write(0x01, 0x05); - - ec_write(0x02, 0xa0); - ec_write(0x03, 0x05); - - /* set mask of enabled beeps */ - ec_write(0x04, 0xfe); - ec_write(0x05, 0x96); - - /* Unknown, but required for hotkeys - Maybe a mask for enabled keys? */ - - ec_write(0x12, 0xff); - ec_write(0x13, 0xff); - ec_write(0x14, 0xf4); - ec_write(0x15, 0x3c); + pmh7_backlight_enable(1); /* enable Audio */ - ec_clr_bit(0x3a, 0); + h8ec_set_audio_mute(0); /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); -- 1.7.4.1 From joe at settoplinux.org Sun Apr 10 18:10:27 2011 From: joe at settoplinux.org (Joseph Smith) Date: Sun, 10 Apr 2011 12:10:27 -0400 Subject: [coreboot] ask for ideas and suggestions about CBFS support on ARM In-Reply-To: References: Message-ID: <4DA1D673.3060704@settoplinux.org> On 04/10/2011 08:49 AM, Hamo wrote: > Dear lists, > I have be studying CBFS filesystem these days. Since coreboot only > supports IA32 architecture now, the CBFS has hard-coded boot address > and all the boot-related code and master header are located at around > 0xFFFFFFF0. But as ARM read their first instruction at 0x0, we need > change the CBFS filesystem but not destroy IA32 support. When porting > to ARM, how should the rom be organized? I have 2 ideas: > 1. Totally rewrite the CBFS structure on ARM according to that one on > IA32 to meet the requirement of ARM architecture, including move the > reset code and bootblock to the start of ROM(at address 0x0) and put > all the other components follow them. In this way, we should rewrite > the CBFStool and add a new option to CBFStool to tell it the > architecture we are using. > 2. Use the same structure on IA32 architecture but set the master > header's offset to other value than 0x0 so that we can put boot code > at the start of rom. > Which one should I take or Do we have any better choice? > Hope for your help. > How about spitting up the code using pre-processing directives? One for arm and one for IA32? Just a thought. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From patrick at georgi-clan.de Sun Apr 10 18:25:04 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sun, 10 Apr 2011 18:25:04 +0200 Subject: [coreboot] ask for ideas and suggestions about CBFS support on ARM In-Reply-To: <4DA1D673.3060704@settoplinux.org> References: <4DA1D673.3060704@settoplinux.org> Message-ID: <4DA1D9E0.1090501@georgi-clan.de> Am 10.04.2011 18:10, schrieb Joseph Smith: > How about spitting up the code using pre-processing directives? One for > arm and one for IA32? Just a thought. AHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH please. not. more. compile. time. options. Patrick From svens at stackframe.org Sun Apr 10 21:05:11 2011 From: svens at stackframe.org (Sven Schnelle) Date: Sun, 10 Apr 2011 21:05:11 +0200 Subject: [coreboot] [PATCH 2/2] PMH7: Add chip config In-Reply-To: <1302462311-26590-2-git-send-email-svens@stackframe.org> References: <1302462311-26590-2-git-send-email-svens@stackframe.org> Message-ID: <1302462311-26590-3-git-send-email-svens@stackframe.org> Signed-off-by: Sven Schnelle --- src/ec/lenovo/pmh7/chip.h | 9 +++++++++ src/ec/lenovo/pmh7/pmh7.c | 4 ++++ src/mainboard/lenovo/x60/devicetree.cb | 1 + src/mainboard/lenovo/x60/mainboard.c | 7 ------- 4 files changed, 14 insertions(+), 7 deletions(-) create mode 100644 src/ec/lenovo/pmh7/chip.h diff --git a/src/ec/lenovo/pmh7/chip.h b/src/ec/lenovo/pmh7/chip.h new file mode 100644 index 0000000..e11b772 --- /dev/null +++ b/src/ec/lenovo/pmh7/chip.h @@ -0,0 +1,9 @@ +#ifndef EC_LENOVO_PMH7_CHIP_H +#define EC_LENOVO_PMH7_CHIP_H + +extern struct chip_operations ec_lenovo_pmh7_ops; + +struct ec_lenovo_pmh7_config { + int backlight_enable:1; +}; +#endif diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 47573a9..5d13b4e 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -23,6 +23,7 @@ #include #include #include "pmh7.h" +#include "chip.h" void pmh7_register_set_bit(int reg, int bit) { @@ -67,6 +68,7 @@ void pmh7_backlight_enable(int on) static void enable_dev(device_t dev) { + struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); @@ -75,6 +77,8 @@ static void enable_dev(device_t dev) resource->size = 16; resource->align = 5; resource->gran = 5; + + pmh7_backlight_enable(conf->backlight_enable); } struct chip_operations ec_lenovo_pmh7_ops = { diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index f47fdae..d5ba7d9 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -85,6 +85,7 @@ chip northbridge/intel/i945 chip ec/lenovo/pmh7 device pnp ff.1 on # dummy end + register "backlight_enable" = "0x01" end chip ec/lenovo/h8 device pnp ff.2 on # dummy diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 15ed808..b9416b5 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -35,17 +35,10 @@ #include #include -static void backlight_enable(void) -{ - pmh7_register_set_bit(0x50, 5); -} - static void mainboard_enable(device_t dev) { device_t dev0; - backlight_enable(); - /* enable Audio */ h8_set_audio_mute(0); -- 1.7.4.1 From svens at stackframe.org Sun Apr 10 21:05:10 2011 From: svens at stackframe.org (Sven Schnelle) Date: Sun, 10 Apr 2011 21:05:10 +0200 Subject: [coreboot] [PATCH 1/2] EC: Add Lenovo H8 Message-ID: <1302462311-26590-2-git-send-email-svens@stackframe.org> Move the EC support code from the X60 mainboard to a generic driver, as this EC is used in many thinkpads. Also move the ACPI code to this directory for this reason. This patch also adds a chip config, so that the initial setting for basic register can be specified in devicetree.cb Signed-off-by: Sven Schnelle --- src/ec/lenovo/Kconfig | 1 + src/ec/lenovo/Makefile.inc | 1 + src/ec/lenovo/h8/Kconfig | 3 + src/ec/lenovo/h8/Makefile.inc | 1 + src/ec/lenovo/h8/acpi/ac.asl | 44 +++ src/ec/lenovo/h8/acpi/battery.asl | 296 +++++++++++++++++++ src/ec/lenovo/h8/acpi/beep.asl | 32 ++ src/ec/lenovo/h8/acpi/ec.asl | 122 ++++++++ src/ec/lenovo/h8/acpi/lid.asl | 54 ++++ src/ec/lenovo/h8/acpi/sleepbutton.asl | 49 ++++ src/ec/lenovo/h8/acpi/systemstatus.asl | 63 ++++ src/ec/lenovo/h8/acpi/thermal.asl | 41 +++ src/ec/lenovo/h8/chip.h | 36 +++ src/ec/lenovo/h8/h8.c | 129 +++++++++ src/ec/lenovo/h8/h8.h | 111 +++++++ src/ec/lenovo/pmh7/pmh7.c | 9 + src/ec/lenovo/pmh7/pmh7.h | 1 + src/mainboard/emulation/qemu | 368 ++++++++++++++++++++++++ src/mainboard/emulation/qemu-x86/dmi.h | 29 ++ src/mainboard/lenovo/x60/Kconfig | 2 +- src/mainboard/lenovo/x60/acpi/ac.asl | 44 --- src/mainboard/lenovo/x60/acpi/battery.asl | 296 ------------------- src/mainboard/lenovo/x60/acpi/beep.asl | 32 -- src/mainboard/lenovo/x60/acpi/dock.asl | 56 +++-- src/mainboard/lenovo/x60/acpi/ec.asl | 129 +-------- src/mainboard/lenovo/x60/acpi/gpe.asl | 4 +- src/mainboard/lenovo/x60/acpi/lid.asl | 54 ---- src/mainboard/lenovo/x60/acpi/sleepbutton.asl | 49 ---- src/mainboard/lenovo/x60/acpi/systemstatus.asl | 66 ----- src/mainboard/lenovo/x60/acpi/thermal.asl | 41 --- src/mainboard/lenovo/x60/devicetree.cb | 18 ++- src/mainboard/lenovo/x60/dsdt.asl | 7 +- src/mainboard/lenovo/x60/mainboard.c | 62 +---- 33 files changed, 1451 insertions(+), 799 deletions(-) create mode 100644 src/ec/lenovo/h8/Kconfig create mode 100644 src/ec/lenovo/h8/Makefile.inc create mode 100644 src/ec/lenovo/h8/acpi/ac.asl create mode 100644 src/ec/lenovo/h8/acpi/battery.asl create mode 100644 src/ec/lenovo/h8/acpi/beep.asl create mode 100644 src/ec/lenovo/h8/acpi/ec.asl create mode 100644 src/ec/lenovo/h8/acpi/lid.asl create mode 100644 src/ec/lenovo/h8/acpi/sleepbutton.asl create mode 100644 src/ec/lenovo/h8/acpi/systemstatus.asl create mode 100644 src/ec/lenovo/h8/acpi/thermal.asl create mode 100644 src/ec/lenovo/h8/chip.h create mode 100644 src/ec/lenovo/h8/h8.c create mode 100644 src/ec/lenovo/h8/h8.h create mode 100644 src/mainboard/emulation/qemu create mode 100644 src/mainboard/emulation/qemu-x86/dmi.h delete mode 100644 src/mainboard/lenovo/x60/acpi/ac.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/battery.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/beep.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/lid.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/sleepbutton.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/systemstatus.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/thermal.asl diff --git a/src/ec/lenovo/Kconfig b/src/ec/lenovo/Kconfig index b564b62..73f11ca 100644 --- a/src/ec/lenovo/Kconfig +++ b/src/ec/lenovo/Kconfig @@ -1 +1,2 @@ +source src/ec/lenovo/h8/Kconfig source src/ec/lenovo/pmh7/Kconfig diff --git a/src/ec/lenovo/Makefile.inc b/src/ec/lenovo/Makefile.inc index f9a3feb..8865030 100644 --- a/src/ec/lenovo/Makefile.inc +++ b/src/ec/lenovo/Makefile.inc @@ -1 +1,2 @@ +subdirs-$(CONFIG_EC_LENOVO_H8) += h8 subdirs-$(CONFIG_EC_LENOVO_PMH7) += pmh7 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig new file mode 100644 index 0000000..07bdb11 --- /dev/null +++ b/src/ec/lenovo/h8/Kconfig @@ -0,0 +1,3 @@ +config EC_LENOVO_H8 + select EC_ACPI + bool diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc new file mode 100644 index 0000000..86bc663 --- /dev/null +++ b/src/ec/lenovo/h8/Makefile.inc @@ -0,0 +1 @@ +driver-y += h8.c diff --git a/src/ec/lenovo/h8/acpi/ac.asl b/src/ec/lenovo/h8/acpi/ac.asl new file mode 100644 index 0000000..cbc84b2 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/ac.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x46), + , 4, + HPAC, 1 +} + +Device(AC) +{ + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return (HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return (0x0f) + } +} diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl new file mode 100644 index 0000000..7168581 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -0,0 +1,296 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x38), + B0ST, 4, /* Battery 0 state */ + , 1, + B0CH, 1, /* Battery 0 charging */ + B0DI, 1, /* Battery 0 discharging */ + B0PR, 1, /* Battery 0 present */ + Offset (0x39), + B1ST, 4, /* Battery 1 state */ + , 1, + B1CH, 1, /* Battery 1 charging, */ + B1DI, 1, /* Battery 1 discharging,*/ + B1PR, 1 /* Battery 1 present */ +} + +/* EC Registers */ +/* PAGE == 0x00 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BARC, 16, /* Battery remaining capacity */ + BAFC, 16, /* Battery full charge capacity */ + Offset(0xa8), + BAPR, 16, /* Battery present rate */ + BAVO, 16, /* Battery Voltage */ +} + +/* PAGE == 0x01 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + , 15, + BAMA, 1, +} + +/* PAGE == 0x02 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BADC, 16, /* Design Capacity */ + BADV, 16, /* Design voltage */ + , 16, + , 16, + , 16, + BASN, 16, +} + +/* PAGE == 0x04: Battery type */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BATY, 32 +} + + +/* PAGE == 0x05: Battery OEM information */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BAOE, 128 +} + +/* PAGE == 0x06: Battery name */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BANA, 128 +} + +/* Arg0: Battery + * Arg1: Battery Status Package + * Arg2: charging + * Arg3: discharging + */ +Method(BSTA, 4, NotSerialized) +{ + Acquire(ECLK, 0xffff) + Store(0, Local0) + Or(1, Arg0, PAGE) + Store(BAMA, Local1) + Store(Arg0, PAGE) /* Battery dynamic information */ + + Store(BAPR, Local2) + + if (Arg2) // charging + { + Or(2, Local0, Local0) + + If (LGreaterEqual (Local2, 0x8000)) { + Store(0, Local2) + } + } + + if (Arg3) // discharging + { + Or(1, Local0, Local0) + Subtract(0x10000, Local2, Local2) + } + + Store(Local0, Index(Arg1, 0x00)) + + if (Local1) { + Multiply (BARC, 10, Index(Arg1, 2)) + Multiply (Local2, BAVO, Local2) + Divide (Local2, 1000, Local3, Index(Arg1, 1)) + } else { + Store(BARC, Index(Arg1, 2)) + Store(Local2, Index(Arg1, 1)) + } + Store(BAVO, Index(Arg1, 3)) + Release(ECLK) + Return (Arg1) +} + +Method(BINF, 2, NotSerialized) +{ + Acquire(ECLK, 0xffff) + Or(1, Arg1, PAGE) /* Battery 0 static information */ + Xor(BAMA, 1, Index(Arg0, 0)) + Store(BAMA, Local0) + Store(Arg1, PAGE) + Store(BAFC, Local2) + Or(2, Arg1, PAGE) + Store(BADC, Local1) + + if (Local0) + { + Multiply (Local1, 10, Local1) + Multiply (Local2, 10, Local2) + } + + Store(Local1, Index(Arg0, 1)) // Design Capacity + Store(Local2, Index(Arg0, 2)) // Last full charge capacity + Store(BADV, Index(Arg0, 4)) // Design Voltage + Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity + + Store (BASN, Local0) + Name (SERN, Buffer (0x06) { " " }) + Store (4, Local1) + While (Local0) + { + Divide (Local0, 0x0A, Local2, Local0) + Add (Local2, 48, Index (SERN, Local1)) + Decrement (Local1) + } + Store (SERN, Index (Arg0, 10)) // Serial Number + + Or(4, Arg1, PAGE) + Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) + Store(BATY, TYPE) + Store(TYPE, Index (Arg0, 11)) // Battery type + Or(5, Arg1, PAGE) + Store(BAOE, Index (Arg0, 12)) // OEM information + Or(6, Arg1, PAGE) + Store(BANA, Index (Arg0, 9)) // Model number + Release(ECLK) + Return (Arg0) +} + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 0x00) + Name (_PCL, Package () { \_SB }) + + Name (BATS, Package () + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage (mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 1, // 7: granularity1 + 1, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Method (_BIF, 0, NotSerialized) + { + Return (BINF(BATS, 0)) + } + + Name (BATI, Package () + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method (_BST, 0, NotSerialized) + { + if (B0PR) { + Return (BSTA(0, BATI, B0CH, B0DI)) + } else { + Return (BATS) + } + } + + Method (_STA, 0, NotSerialized) + { + if (B0PR) { + Return (0x1f) + } else { + Return (0x0f) + } + } +} + +Device (BAT1) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 0x00) + Name (_PCL, Package () { \_SB }) + + Name (BATS, Package () + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage (mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 1, // 7: granularity1 + 1, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Method (_BIF, 0, NotSerialized) + { + Return (BINF(BATS, 0x10)) + } + + Name (BATI, Package () + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method (_BST, 0, NotSerialized) + { + if (B1PR) { + Return (BSTA(0x10, BATI, B1CH, B1DI)) + } else { + Return (BATS) + } + } + + Method (_STA, 0, NotSerialized) + { + if (B1PR) { + Return (0x1f) + } else { + Return (0x0f) + } + } +} diff --git a/src/ec/lenovo/h8/acpi/beep.asl b/src/ec/lenovo/h8/acpi/beep.asl new file mode 100644 index 0000000..718f41b --- /dev/null +++ b/src/ec/lenovo/h8/acpi/beep.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x06), + SNDS, 8 /* Write to this register to generate sound */ + +} + +Method(BEEP, 1, NotSerialized) +{ + Store (Arg0, SNDS) +} diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl new file mode 100644 index 0000000..98abfc1 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "smi.h" +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, 28) + Mutex (ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x05), + HSPA, 1, + Offset (0x0C), + LEDS, 8, /* LED state */ + Offset (0x3a), + AMUT, 1, /* Audio Mute */ + Offset (0x3B), + , 1, + KBLT, 1, /* Keyboard Light */ + Offset (0x4e), + WAKE, 16, + Offset (0x78), + TMP0, 8, /* Thermal Zone 0 temperature */ + TMP1, 8, /* Thermal Zone 1 temperature */ + Offset (0x81), + PAGE, 8 /* Information Page Selector */ + } + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + Return (ECMD) + } + + Method (LED, 1, NotSerialized) + { + Store(Arg0, LEDS) + } + + Method (_INI, 0, NotSerialized) + { + } + + Method (MUTE, 1, NotSerialized) + { + Store(Arg0, AMUT) + } + + /* Sleep Button pressed */ + Method(_Q13, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80) + } + + /* Brightness up GPE */ + Method(_Q14, 0, NotSerialized) + { + \DSPC.BRTU () + } + + /* Brightness down GPE */ + Method(_Q15, 0, NotSerialized) + { + \DSPC.BRTD() + } + + /* AC status change: present */ + Method(_Q26, 0, NotSerialized) + { + Notify (AC, 0x80) + } + + /* AC status change: not present */ + Method(_Q27, 0, NotSerialized) + { + Notify (AC, 0x80) + } + + Method(_Q2A, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) + } + + Method(_Q2B, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) + } + + +#include "ac.asl" +#include "battery.asl" +#include "sleepbutton.asl" +#include "lid.asl" +#include "beep.asl" +} diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl new file mode 100644 index 0000000..2dfa8d1 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x32), + , 2, + WKLD, 1, + Offset (0x46), + , 2, + LIDS, 1 +} + +Device(LID) +{ + Name(_HID, "PNP0C0D") + + Method(_LId, 0, NotSerialized) + { + return (LIDS) + } + + Method(_PRW, 0, NotSerialized) + { + Return (Package() { 0x18, 0x03 }) + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + Store(1, WKLD) + } else { + Store(0, WKLD) + } + } +} diff --git a/src/ec/lenovo/h8/acpi/sleepbutton.asl b/src/ec/lenovo/h8/acpi/sleepbutton.asl new file mode 100644 index 0000000..09e88aa --- /dev/null +++ b/src/ec/lenovo/h8/acpi/sleepbutton.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x32), + , 4, + WKFN, 1, + Offset(0x83), + FNKY, 8 +} + +Device(SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Method(_PRW, 0, NotSerialized) + { + Return (Package() { 0x18, 0x03 }) + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + Store(6, FNKY) /* Fn key acts as wake button */ + Store(1, WKFN) + } else { + Store(0, FNKY) /* Fn key normal operation */ + Store(0, WKFN) + } + } +} diff --git a/src/ec/lenovo/h8/acpi/systemstatus.asl b/src/ec/lenovo/h8/acpi/systemstatus.asl new file mode 100644 index 0000000..17e8ba7 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/systemstatus.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +Scope (\_SI) +{ + Method(_SST, 1, NotSerialized) + { + If (LEqual (Arg0, 0)) { + /* Indicator off */ + + /* power LED off */ + \_SB.PCI0.LPCB.EC.LED(0x00) + /* suspend LED off */ + \_SB.PCI0.LPCB.EC.LED(0x07) + } + + If (LEqual (Arg0, 1)) { + /* working state */ + + /* power LED on */ + \_SB.PCI0.LPCB.EC.LED(0x80) + /* suspend LED off */ + \_SB.PCI0.LPCB.EC.LED(0x07) + } + + If (LEqual (Arg0, 2)) { + /* waking state */ + + /* power LED om */ + \_SB.PCI0.LPCB.EC.LED(0x80) + /* suspend LED blinking */ + \_SB.PCI0.LPCB.EC.LED(0xc7) + } + + If (LEqual (Arg0, 3)) { + /* sleep state */ + + /* power LED off */ + \_SB.PCI0.LPCB.EC.LED(0x00) + /* suspend LED on */ + \_SB.PCI0.LPCB.EC.LED(0x87) + } + } +} diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl new file mode 100644 index 0000000..35b6f14 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -0,0 +1,41 @@ +Scope(\_TZ) +{ + Method(C2K, 1, NotSerialized) + { + Multiply(Arg0, 10, Local0) + Add (Local0, 2732, Local0) + if (LLessEqual(Local0, 2732)) { + Return (3000) + } + + if (LGreater(Local0, 4012)) { + Return (3000) + } + Return (Local0) + } + + ThermalZone(THM0) + { + Method(_CRT, 0, NotSerialized) { + Return (C2K(127)) + } + Method(_TMP) { + Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) + } + } + + ThermalZone(THM1) + { + Method(_CRT, 0, NotSerialized) { + Return (C2K(99)) + } + + Method(_PSV, 0, NotSerialized) { + Return (C2K(94)) + } + + Method(_TMP) { + Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) + } + } +} diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h new file mode 100644 index 0000000..d504654 --- /dev/null +++ b/src/ec/lenovo/h8/chip.h @@ -0,0 +1,36 @@ +#ifndef EC_LENOVO_H8EC_CHIP_H +#define EC_LENOVO_H8EC_CHIP_H + +extern struct chip_operations ec_lenovo_h8_ops; +struct ec_lenovo_h8_config { + + u8 config0; + u8 config1; + u8 config2; + u8 config3; + + u8 beepmask0; + u8 beepmask1; + + u8 event0_enable; + u8 event1_enable; + u8 event2_enable; + u8 event3_enable; + u8 event4_enable; + u8 event5_enable; + u8 event6_enable; + u8 event7_enable; + u8 event8_enable; + u8 event9_enable; + u8 eventa_enable; + u8 eventb_enable; + u8 eventc_enable; + u8 eventd_enable; + u8 evente_enable; + u8 eventf_enable; + + u8 trackpoint_enable; + u8 wlan_enable; + u8 wwan_enable; +}; +#endif diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c new file mode 100644 index 0000000..bc0ddde --- /dev/null +++ b/src/ec/lenovo/h8/h8.c @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "h8.h" +#include "chip.h" + +void h8_trackpoint_enable(int on) +{ + ec_write(H8_TRACKPOINT_CTRL, + on ? H8_TRACKPOINT_ON : H8_TRACKPOINT_OFF); + +} + +void h8_wlan_enable(int on) +{ + if (on) + ec_set_bit(0x3a, 5); + else + ec_clr_bit(0x3a, 5); +} + +static void h8_log_ec_version(void) +{ + unsigned char ecfw[9], c; + u16 fwvh, fwvl; + int i; + + for(i = 0; i < 8; i++) { + c = ec_read(0xf0 + i); + if (c < 0x20 || c > 0x7f) + break; + ecfw[i] = c; + } + ecfw[i] = '\0'; + + fwvh = ec_read(0xe9); + fwvl = ec_read(0xe8); + + printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); +} + +void h8_set_audio_mute(int on) +{ + if (on) + ec_clr_bit(0x3a, 0); + else + ec_set_bit(0x3a, 1); +} + +void h8_enable_event(int event) +{ + if (event < 0 || event > 127) + return; + + ec_set_bit(0x10 + (event >> 3), event & 7); +} + +void h8_disable_event(int event) +{ + if (event < 0 || event > 127) + return; + + ec_clr_bit(0x10 + (event >> 3), event & 7); + +} + +static void h8_enable(device_t dev) +{ + struct ec_lenovo_h8_config *conf = dev->chip_info; + h8_log_ec_version(); + + ec_write(H8_CONFIG0, conf->config0); + ec_write(H8_CONFIG1, conf->config1); + ec_write(H8_CONFIG2, conf->config2); + ec_write(H8_CONFIG3, conf->config3); + + ec_write(H8_SOUND_ENABLE0, conf->beepmask0); + ec_write(H8_SOUND_ENABLE1, conf->beepmask1); + ec_write(H8_SOUND_REPEAT, 0x00); + + ec_write(0x10, conf->event0_enable); + ec_write(0x11, conf->event1_enable); + ec_write(0x12, conf->event2_enable); + ec_write(0x13, conf->event3_enable); + ec_write(0x14, conf->event4_enable); + ec_write(0x15, conf->event5_enable); + ec_write(0x16, conf->event6_enable); + ec_write(0x17, conf->event7_enable); + ec_write(0x18, conf->event8_enable); + ec_write(0x19, conf->event9_enable); + ec_write(0x1a, conf->eventa_enable); + ec_write(0x1b, conf->eventb_enable); + ec_write(0x1c, conf->eventc_enable); + ec_write(0x1d, conf->eventd_enable); + ec_write(0x1e, conf->evente_enable); + ec_write(0x1f, conf->eventf_enable); + + h8_wlan_enable(conf->wlan_enable); + h8_trackpoint_enable(conf->trackpoint_enable); + +} + +struct chip_operations ec_lenovo_h8_ops = { + CHIP_NAME("Lenovo H8 EC") + .enable_dev = h8_enable +}; diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h new file mode 100644 index 0000000..cdb22ca --- /dev/null +++ b/src/ec/lenovo/h8/h8.h @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef EC_LENOVO_H8_H +#define EC_LENOVO_H8_H + +void h8_trackpoint_enable(int on); +void h8_wlan_enable(int on); +void h8_set_audio_mute(int on); +void h8_enable_event(int event); +void h8_disable_event(int event); + +/* EC registers */ +#define H8_CONFIG0 0x00 +#define H8_CONFIG0_EVENTS_ENABLE 0x02 +#define H8_CONFIG0_HOTKEY_ENABLE 0x04 +#define H8_CONFIG0_SMM_H8_ENABLE 0x20 +#define H8_CONFIG0_TC_ENABLE 0x80 + +#define H8_CONFIG1 0x01 +#define H8_CONFIG1_BKLT_LID 0x01 +#define H8_CONFIG1_UBAY_PWR 0x20 + +#define H8_CONFIG2 0x02 +#define H8_CONFIG2_USB_DOCK 0x01 +#define H8_CONFIG2_DOCK_SPEAKER_MUTE 0x02 +#define H8_CONFIG2_DOCK_SPEAKER_MUTE_POL 0x04 + +#define H8_CONFIG3 0x03 + +#define H8_SOUND_ENABLE0 0x04 +#define H8_SOUND_ENABLE1 0x05 +#define H8_SOUND_REG 0x06 +#define H8_SOUND_REPEAT 0x07 + +#define H8_TRACKPOINT_CTRL 0x0B +#define H8_TRACKPOINT_AUTO 0x01 +#define H8_TRACKPOINT_OFF 0x02 +#define H8_TRACKPOINT_ON 0x03 + +#define H8_LED_CONTROL 0x0c +#define H8_LED_CONTROL_OFF 0x00 +#define H8_LED_CONTROL_ON 0x80 +#define H8_LED_CONTROL_BLINK 0xc0 + +#define H8_LED_CONTROL_POWER_LED 0x00 +#define H8_LED_CONTROL_BAT0_LED 0x01 +#define H8_LED_CONTROL_BAT1_LED 0x02 +#define H8_LED_CONTROL_UBAY_LED 0x04 +#define H8_LED_CONTROL_SUSPEND_LED 0x07 +#define H8_LED_CONTROL_DOCK_LED1 0x08 +#define H8_LED_CONTROL_DOCK_LED2 0x09 + +/* Embedded controller events */ +#define H8_EVENT_FN_F1 0x10 +#define H8_EVENT_FN_F2 0x11 +#define H8_EVENT_FN_F3 0x12 +#define H8_EVENT_FN_F4 0x13 +#define H8_EVENT_FN_HOME 0x14 +#define H8_EVENT_FN_END 0x15 +#define H8_EVENT_FN_F7 0x16 +#define H8_EVENT_FN_F8 0x17 +#define H8_EVENT_FN_F9 0x18 +#define H8_EVENT_FN_THINKVANTAGE 0x19 +#define H8_EVENT_FN_F11 0x1a +#define H8_EVENT_FN_F12 0x1b +#define H8_EVENT_FN_1 0x1c +#define H8_EVENT_FN_2 0x1d +#define H8_EVENT_FN_PGUP 0x1f + +#define H8_EVENT_AC_ON 0x26 +#define H8_EVENT_AC_OFF 0x27 + +#define H8_EVENT_PWRSW_PRESS 0x28 +#define H8_EVENT_PWRSW_RELEASE 0x29 + +#define H8_EVENT_LIDSW_CLOSE 0x2a +#define H8_EVENT_LIDSW_PUSH 0x2b + +#define H8_EVENT_UBAY_UNLOCK 0x2c +#define H8_EVENT_UBAY_LOCK 0x2d + +#define H8_EVENT_KEYPRESS 0x33 + +#define H8_EVENT_FN_PRESS 0x39 + +#define H8_EVENT_BAT0 0x4a +#define H8_EVENT_BAT0_STATE 0x4b + +#define H8_EVENT_BAT1 0x4c +#define H8_EVENT_BAT1_STATE 0x4d + +#define H8_EVENT_FN_F5 0x64 +#define H8_EVENT_FN_F6 0x65 +#endif diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index a46e179..47573a9 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -56,6 +56,15 @@ void pmh7_register_write(int reg, int val) outb(val, EC_LENOVO_PMH7_DATA); } +void pmh7_backlight_enable(int on) +{ + if (on) + pmh7_register_set_bit(0x50, 5); + else + pmh7_register_clear_bit(0x50, 5); + +} + static void enable_dev(device_t dev) { struct resource *resource; diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h index a4a61cc..8f4f5ab 100644 --- a/src/ec/lenovo/pmh7/pmh7.h +++ b/src/ec/lenovo/pmh7/pmh7.h @@ -31,4 +31,5 @@ void pmh7_register_clear_bit(int reg, int bit); char pmh7_register_read(int reg); void pmh7_register_write(int reg, int val); +void pmh7_backlight_enable(int on); #endif diff --git a/src/mainboard/emulation/qemu b/src/mainboard/emulation/qemu new file mode 100644 index 0000000..d9275b5 --- /dev/null +++ b/src/mainboard/emulation/qemu @@ -0,0 +1,368 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dmi.h" + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#define OLD_ACPI 0 +#if OLD_ACPI +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset (gnvs, 0, sizeof(global_nvs_t)); + + gnvs->LIDS = 1; + gnvs->PWRS = 1; + + gnvs->ACTT = 0x37; + gnvs->PSVT = 0x4f; + + gnvs->TC1V = 0x00; + gnvs->TC2V = 0x0a; + gnvs->TSPV = 0x02; + + gnvs->CRTT = 0x77; + + gnvs->B0SC = 0x54; + gnvs->APIC = 0x01; + gnvs->MPEN = 0x01; + + gnvs->PPCM = 0x02; + gnvs->PCP0 = 0xbf; + gnvs->PCP1 = 0xbf; + + gnvs->CMAP = 0x01; + gnvs->CMBP = 0x01; + gnvs->LT0 = 0x01; + gnvs->FDCP = 0x01; + gnvs->CMCP = 0x01; + gnvs->CMDP = 0x01; + gnvs->P2M = 0x02; + + gnvs->IGDS = 0x01; + + gnvs->CADL = 0x09; + gnvs->PADL = 0x09; + + gnvs->NDID = 3; + gnvs->DID1 = 0x80000100; + gnvs->DID2 = 0x80000240; + gnvs->DID3 = 0x80000410; + gnvs->DID4 = 0x80000410; + gnvs->DID5 = 0x00000005; + + gnvs->ALAF = 0x64; + gnvs->LLOW = 0x2c; + gnvs->LHIH = 0x01; + + // tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c); + // oemb->topm = tolud; +} +#endif + +#include "southbridge/intel/i82801gx/nvs.h" +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +static void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ +#define HPET_ADDR 0xfed00000ULL + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = HPET_ADDR & 0xffffffff; + addr->addrh = HPET_ADDR >> 32; + + hpet->id = 0x8086a201; /* Intel */ + hpet->number = 0x00; + hpet->min_tick = 0x0080; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + +#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + void *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + /* Fix up global NVS region for SMI handler. The GNVS region lives + * in the (high) table area. The low memory map looks like this: + * + * 0x00000000 - 0x000003ff Real Mode IVT + * 0x00000020 - 0x0000019c Low MP Table (XXX conflict?) + * 0x00000400 - 0x000004ff BDA (somewhat unused) + * 0x00000500 - 0x0000052f Moved GDT + * 0x00000530 - 0x00000b64 coreboot table + * 0x0007c000 - 0x0007dfff OS boot sector (unused?) + * 0x0007e000 - 0x0007ffff free to use (so no good for acpi+smi) + * 0x00080000 - 0x0009fbff usable ram + * 0x0009fc00 - 0x0009ffff EBDA (unused?) + * 0x000a0000 - 0x000bffff VGA memory + * 0x000c0000 - 0x000cffff VGA option rom + * 0x000d0000 - 0x000dffff free for other option roms? + * 0x000e0000 - 0x000fffff SeaBIOS? (conflict with low tables:) + * 0x000f0000 - 0x000f03ff PIRQ table + * 0x000f0400 - 0x000f66?? ACPI tables + * 0x000f66?? - 0x000f???? DMI tables + */ + + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* Keep pointer around */ + gnvs = (void *)current; + + current += 0x100; + ALIGN_CURRENT; + + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, "COREBOOT"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + + printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); + memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); +#if CONFIG_WRITE_HIGH_TABLES == 1 + memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); + current += DMI_TABLE_SIZE; + ALIGN_CURRENT; +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + + /* Enable Dummy DCC ON# for DVI */ + printk(BIOS_DEBUG, "Laptop handling...\n"); + outb(inb(0x60f) & ~(1 << 5), 0x60f); + + return current; +} diff --git a/src/mainboard/emulation/qemu-x86/dmi.h b/src/mainboard/emulation/qemu-x86/dmi.h new file mode 100644 index 0000000..96b5873 --- /dev/null +++ b/src/mainboard/emulation/qemu-x86/dmi.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DMI_TABLE_SIZE 0x55 + +static u8 dmi_table[DMI_TABLE_SIZE] = { + 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, + 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, + 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, + 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, + 0x30, 0x30, 0x38, 0x00, 0x00 +}; diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index ebd2c1c..c4b2f63 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87392 select EC_LENOVO_PMH7 - select EC_ACPI + select EC_LENOVO_H8 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/x60/acpi/ac.asl b/src/mainboard/lenovo/x60/acpi/ac.asl deleted file mode 100644 index cbc84b2..0000000 --- a/src/mainboard/lenovo/x60/acpi/ac.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x46), - , 4, - HPAC, 1 -} - -Device(AC) -{ - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) - - Method(_PSR, 0, NotSerialized) - { - return (HPAC) - } - - Method(_STA, 0, NotSerialized) - { - Return (0x0f) - } -} diff --git a/src/mainboard/lenovo/x60/acpi/battery.asl b/src/mainboard/lenovo/x60/acpi/battery.asl deleted file mode 100644 index 7168581..0000000 --- a/src/mainboard/lenovo/x60/acpi/battery.asl +++ /dev/null @@ -1,296 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x38), - B0ST, 4, /* Battery 0 state */ - , 1, - B0CH, 1, /* Battery 0 charging */ - B0DI, 1, /* Battery 0 discharging */ - B0PR, 1, /* Battery 0 present */ - Offset (0x39), - B1ST, 4, /* Battery 1 state */ - , 1, - B1CH, 1, /* Battery 1 charging, */ - B1DI, 1, /* Battery 1 discharging,*/ - B1PR, 1 /* Battery 1 present */ -} - -/* EC Registers */ -/* PAGE == 0x00 */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BARC, 16, /* Battery remaining capacity */ - BAFC, 16, /* Battery full charge capacity */ - Offset(0xa8), - BAPR, 16, /* Battery present rate */ - BAVO, 16, /* Battery Voltage */ -} - -/* PAGE == 0x01 */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - , 15, - BAMA, 1, -} - -/* PAGE == 0x02 */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BADC, 16, /* Design Capacity */ - BADV, 16, /* Design voltage */ - , 16, - , 16, - , 16, - BASN, 16, -} - -/* PAGE == 0x04: Battery type */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BATY, 32 -} - - -/* PAGE == 0x05: Battery OEM information */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BAOE, 128 -} - -/* PAGE == 0x06: Battery name */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BANA, 128 -} - -/* Arg0: Battery - * Arg1: Battery Status Package - * Arg2: charging - * Arg3: discharging - */ -Method(BSTA, 4, NotSerialized) -{ - Acquire(ECLK, 0xffff) - Store(0, Local0) - Or(1, Arg0, PAGE) - Store(BAMA, Local1) - Store(Arg0, PAGE) /* Battery dynamic information */ - - Store(BAPR, Local2) - - if (Arg2) // charging - { - Or(2, Local0, Local0) - - If (LGreaterEqual (Local2, 0x8000)) { - Store(0, Local2) - } - } - - if (Arg3) // discharging - { - Or(1, Local0, Local0) - Subtract(0x10000, Local2, Local2) - } - - Store(Local0, Index(Arg1, 0x00)) - - if (Local1) { - Multiply (BARC, 10, Index(Arg1, 2)) - Multiply (Local2, BAVO, Local2) - Divide (Local2, 1000, Local3, Index(Arg1, 1)) - } else { - Store(BARC, Index(Arg1, 2)) - Store(Local2, Index(Arg1, 1)) - } - Store(BAVO, Index(Arg1, 3)) - Release(ECLK) - Return (Arg1) -} - -Method(BINF, 2, NotSerialized) -{ - Acquire(ECLK, 0xffff) - Or(1, Arg1, PAGE) /* Battery 0 static information */ - Xor(BAMA, 1, Index(Arg0, 0)) - Store(BAMA, Local0) - Store(Arg1, PAGE) - Store(BAFC, Local2) - Or(2, Arg1, PAGE) - Store(BADC, Local1) - - if (Local0) - { - Multiply (Local1, 10, Local1) - Multiply (Local2, 10, Local2) - } - - Store(Local1, Index(Arg0, 1)) // Design Capacity - Store(Local2, Index(Arg0, 2)) // Last full charge capacity - Store(BADV, Index(Arg0, 4)) // Design Voltage - Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity - - Store (BASN, Local0) - Name (SERN, Buffer (0x06) { " " }) - Store (4, Local1) - While (Local0) - { - Divide (Local0, 0x0A, Local2, Local0) - Add (Local2, 48, Index (SERN, Local1)) - Decrement (Local1) - } - Store (SERN, Index (Arg0, 10)) // Serial Number - - Or(4, Arg1, PAGE) - Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) - Store(BATY, TYPE) - Store(TYPE, Index (Arg0, 11)) // Battery type - Or(5, Arg1, PAGE) - Store(BAOE, Index (Arg0, 12)) // OEM information - Or(6, Arg1, PAGE) - Store(BANA, Index (Arg0, 9)) // Model number - Release(ECLK) - Return (Arg0) -} - -Device (BAT0) -{ - Name (_HID, EisaId ("PNP0C0A")) - Name (_UID, 0x00) - Name (_PCL, Package () { \_SB }) - - Name (BATS, Package () - { - 0x00, // 0: PowerUnit: Report in mWh - 0xFFFFFFFF, // 1: Design cap - 0xFFFFFFFF, // 2: Last full charge cap - 0x01, // 3: Battery Technology - 10800, // 4: Design Voltage (mV) - 0x00, // 5: Warning design capacity - 200, // 6: Low design capacity - 1, // 7: granularity1 - 1, // 8: granularity2 - "", // 9: Model number - "", // A: Serial number - "", // B: Battery Type - "" // C: OEM information - }) - - Method (_BIF, 0, NotSerialized) - { - Return (BINF(BATS, 0)) - } - - Name (BATI, Package () - { - 0, // Battery State - // Bit 0 - discharge - // Bit 1 - charge - // Bit 2 - critical state - 0, // Battery present Rate - 0, // Battery remaining capacity - 0 // Battery present voltage - }) - - Method (_BST, 0, NotSerialized) - { - if (B0PR) { - Return (BSTA(0, BATI, B0CH, B0DI)) - } else { - Return (BATS) - } - } - - Method (_STA, 0, NotSerialized) - { - if (B0PR) { - Return (0x1f) - } else { - Return (0x0f) - } - } -} - -Device (BAT1) -{ - Name (_HID, EisaId ("PNP0C0A")) - Name (_UID, 0x00) - Name (_PCL, Package () { \_SB }) - - Name (BATS, Package () - { - 0x00, // 0: PowerUnit: Report in mWh - 0xFFFFFFFF, // 1: Design cap - 0xFFFFFFFF, // 2: Last full charge cap - 0x01, // 3: Battery Technology - 10800, // 4: Design Voltage (mV) - 0x00, // 5: Warning design capacity - 200, // 6: Low design capacity - 1, // 7: granularity1 - 1, // 8: granularity2 - "", // 9: Model number - "", // A: Serial number - "", // B: Battery Type - "" // C: OEM information - }) - - Method (_BIF, 0, NotSerialized) - { - Return (BINF(BATS, 0x10)) - } - - Name (BATI, Package () - { - 0, // Battery State - // Bit 0 - discharge - // Bit 1 - charge - // Bit 2 - critical state - 0, // Battery present Rate - 0, // Battery remaining capacity - 0 // Battery present voltage - }) - - Method (_BST, 0, NotSerialized) - { - if (B1PR) { - Return (BSTA(0x10, BATI, B1CH, B1DI)) - } else { - Return (BATS) - } - } - - Method (_STA, 0, NotSerialized) - { - if (B1PR) { - Return (0x1f) - } else { - Return (0x0f) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi/beep.asl b/src/mainboard/lenovo/x60/acpi/beep.asl deleted file mode 100644 index 718f41b..0000000 --- a/src/mainboard/lenovo/x60/acpi/beep.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x06), - SNDS, 8 /* Write to this register to generate sound */ - -} - -Method(BEEP, 1, NotSerialized) -{ - Store (Arg0, SNDS) -} diff --git a/src/mainboard/lenovo/x60/acpi/dock.asl b/src/mainboard/lenovo/x60/acpi/dock.asl index db61e05..d393f44 100644 --- a/src/mainboard/lenovo/x60/acpi/dock.asl +++ b/src/mainboard/lenovo/x60/acpi/dock.asl @@ -21,35 +21,47 @@ #include "smi.h" -OperationRegion (DLPC, SystemIO, 0x164c, 1) -Field(DLPC, ByteAcc, NoLock, Preserve) +Scope (\_SB) { - , 3, - DSTA, 1, -} -Device(DOCK) -{ - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) + OperationRegion (DLPC, SystemIO, 0x164c, 1) + Field(DLPC, ByteAcc, NoLock, Preserve) + { + , 3, + DSTA, 1, + } - Method(_DCK, 1, NotSerialized) + Device(DOCK) { - if (Arg0) { - Sleep(250) - /* connect dock */ - TRAP(SMI_DOCK_CONNECT) - } else { - /* disconnect dock */ - TRAP(SMI_DOCK_DISCONNECT) + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + Sleep(250) + /* connect dock */ + TRAP(SMI_DOCK_CONNECT) + } else { + /* disconnect dock */ + TRAP(SMI_DOCK_DISCONNECT) + } + + Xor(Arg0, DSTA, Local0) + Return (Local0) } - Xor(Arg0, DSTA, Local0) - Return (Local0) + Method(_STA, 0, NotSerialized) + { + Return (DSTA) + } } +} - Method(_STA, 0, NotSerialized) +Scope(\_SB.PCI0.LPCB.EC) +{ + Method(_Q18, 0, NotSerialized) { - Return (DSTA) + Notify(\_SB.DOCK, 3) } } diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl index 85ea491..c3569e8 100644 --- a/src/mainboard/lenovo/x60/acpi/ec.asl +++ b/src/mainboard/lenovo/x60/acpi/ec.asl @@ -1,128 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include "smi.h" -Device(EC) -{ - Name (_HID, EISAID("PNP0C09")) - Name (_UID, 0) - - Name (_GPE, 28) - Mutex (ECLK, 0) - - OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) - Field (ERAM, ByteAcc, NoLock, Preserve) - { - Offset (0x05), - HSPA, 1, - Offset (0x0C), - LEDS, 8, /* LED state */ - Offset (0x3a), - AMUT, 1, /* Audio Mute */ - Offset (0x3B), - , 1, - KBLT, 1, /* Keyboard Light */ - Offset (0x4e), - WAKE, 16, - Offset (0x78), - TMP0, 8, /* Thermal Zone 0 temperature */ - TMP1, 8, /* Thermal Zone 1 temperature */ - Offset (0x81), - PAGE, 8 /* Information Page Selector */ - } - - Method (_CRS, 0) - { - Name (ECMD, ResourceTemplate() - { - IO (Decode16, 0x62, 0x62, 1, 1) - IO (Decode16, 0x66, 0x66, 1, 1) - }) - Return (ECMD) - } - - Method (LED, 1, NotSerialized) - { - Store(Arg0, LEDS) - } - - Method (_INI, 0, NotSerialized) - { - } - - Method (MUTE, 1, NotSerialized) - { - Store(Arg0, AMUT) - } - - /* Sleep Button pressed */ - Method(_Q13, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80) - } - - /* Brightness up GPE */ - Method(_Q14, 0, NotSerialized) - { - \DSPC.BRTU () - } - - /* Brightness down GPE */ - Method(_Q15, 0, NotSerialized) - { - \DSPC.BRTD() - } - - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) - } - - /* AC status change: present */ - Method(_Q26, 0, NotSerialized) - { - Notify (AC, 0x80) - } - - /* AC status change: not present */ - Method(_Q27, 0, NotSerialized) - { - Notify (AC, 0x80) - } - - Method(_Q2A, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) - } - - Method(_Q2B, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) - } - - -#include "ac.asl" -#include "battery.asl" -#include "sleepbutton.asl" -#include "lid.asl" -#include "beep.asl" -#include "dock.asl" -} +#include diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl index 64e8e31..3aa9615 100644 --- a/src/mainboard/lenovo/x60/acpi/gpe.asl +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -12,10 +12,10 @@ Scope (\_GPE) { if (GP13) { Or(GIV1, 0x20, GIV1) - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) + Notify(\_SB.DOCK, 3) } else { And(GIV1, 0xdf, GIV1) - Notify(\_SB.PCI0.LPCB.EC.DOCK, 0) + Notify(\_SB.DOCK, 0) } } } diff --git a/src/mainboard/lenovo/x60/acpi/lid.asl b/src/mainboard/lenovo/x60/acpi/lid.asl deleted file mode 100644 index 2dfa8d1..0000000 --- a/src/mainboard/lenovo/x60/acpi/lid.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x32), - , 2, - WKLD, 1, - Offset (0x46), - , 2, - LIDS, 1 -} - -Device(LID) -{ - Name(_HID, "PNP0C0D") - - Method(_LId, 0, NotSerialized) - { - return (LIDS) - } - - Method(_PRW, 0, NotSerialized) - { - Return (Package() { 0x18, 0x03 }) - } - - Method(_PSW, 1, NotSerialized) - { - if (Arg0) { - Store(1, WKLD) - } else { - Store(0, WKLD) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi/sleepbutton.asl b/src/mainboard/lenovo/x60/acpi/sleepbutton.asl deleted file mode 100644 index 09e88aa..0000000 --- a/src/mainboard/lenovo/x60/acpi/sleepbutton.asl +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x32), - , 4, - WKFN, 1, - Offset(0x83), - FNKY, 8 -} - -Device(SLPB) -{ - Name (_HID, EisaId ("PNP0C0E")) - Method(_PRW, 0, NotSerialized) - { - Return (Package() { 0x18, 0x03 }) - } - - Method(_PSW, 1, NotSerialized) - { - if (Arg0) { - Store(6, FNKY) /* Fn key acts as wake button */ - Store(1, WKFN) - } else { - Store(0, FNKY) /* Fn key normal operation */ - Store(0, WKFN) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi/systemstatus.asl b/src/mainboard/lenovo/x60/acpi/systemstatus.asl deleted file mode 100644 index 161be08..0000000 --- a/src/mainboard/lenovo/x60/acpi/systemstatus.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - - -Scope (\_SI) -{ - Method(_SST, 1, NotSerialized) - { - If (LEqual (Arg0, 0)) { - /* Indicator off */ - - /* power LED off */ - \_SB.PCI0.LPCB.EC.LED(0x00) - /* suspend LED off */ - \_SB.PCI0.LPCB.EC.LED(0x07) - } - - If (LEqual (Arg0, 1)) { - /* working state */ - - /* power LED on */ - \_SB.PCI0.LPCB.EC.LED(0x80) - /* suspend LED off */ - \_SB.PCI0.LPCB.EC.LED(0x07) - } - - If (LEqual (Arg0, 2)) { - /* waking state */ - - /* power LED om */ - \_SB.PCI0.LPCB.EC.LED(0x80) - /* suspend LED blinking */ - \_SB.PCI0.LPCB.EC.LED(0xc7) - } - - If (LEqual (Arg0, 3)) { - /* sleep state */ - - /* power LED off */ - \_SB.PCI0.LPCB.EC.LED(0x00) - /* suspend LED on */ - \_SB.PCI0.LPCB.EC.LED(0x87) - } - - - - } -} diff --git a/src/mainboard/lenovo/x60/acpi/thermal.asl b/src/mainboard/lenovo/x60/acpi/thermal.asl deleted file mode 100644 index 35b6f14..0000000 --- a/src/mainboard/lenovo/x60/acpi/thermal.asl +++ /dev/null @@ -1,41 +0,0 @@ -Scope(\_TZ) -{ - Method(C2K, 1, NotSerialized) - { - Multiply(Arg0, 10, Local0) - Add (Local0, 2732, Local0) - if (LLessEqual(Local0, 2732)) { - Return (3000) - } - - if (LGreater(Local0, 4012)) { - Return (3000) - } - Return (Local0) - } - - ThermalZone(THM0) - { - Method(_CRT, 0, NotSerialized) { - Return (C2K(127)) - } - Method(_TMP) { - Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) - } - } - - ThermalZone(THM1) - { - Method(_CRT, 0, NotSerialized) { - Return (C2K(99)) - } - - Method(_PSV, 0, NotSerialized) { - Return (C2K(94)) - } - - Method(_TMP) { - Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) - } - } -} diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 2817255..f47fdae 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -86,13 +86,29 @@ chip northbridge/intel/i945 device pnp ff.1 on # dummy end end - chip ec/acpi + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 io 0x62 = 0x66 io 0x64 = 0x1600 io 0x66 = 0x1604 end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0x05" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + + register "wlan_enable" = "0x01" + register "trackpoint_enable" = "0x03" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 3467a8b..905c94a 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -40,10 +40,6 @@ DefinitionBlock( // mainboard specific devices #include "acpi/mainboard.asl" - // Thermal Zone - #include "acpi/thermal.asl" - // System status indicators - #include "acpi/systemstatus.asl" Scope (\_SB) { Device (PCI0) { @@ -54,4 +50,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + + // Dock support code + #include "acpi/dock.asl" } diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index c2aaaa9..15ed808 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -32,78 +32,22 @@ #include #include #include +#include #include static void backlight_enable(void) { - pmh7_register_set_bit(0x50, 5); -} - -static void trackpoint_enable(void) -{ - ec_write(0x0b, 0x03); -} - -static void wlan_enable(void) -{ - ec_write(0x3a, 0x20); -} - -static void log_ec_version(void) -{ - unsigned char ecfw[9], c; - u16 fwvh, fwvl; - int i; - - for(i = 0; i < 8; i++) { - c = ec_read(0xf0 + i); - if (c < 0x20 || c > 0x7f) - break; - ecfw[i] = c; - } - ecfw[i] = '\0'; - - fwvh = ec_read(0xe9); - fwvl = ec_read(0xe8); - - printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, - fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); + pmh7_register_set_bit(0x50, 5); } static void mainboard_enable(device_t dev) { device_t dev0; - log_ec_version(); - backlight_enable(); - trackpoint_enable(); - - /* FIXME: this should be ACPI's task - * but for now, enable it here */ - wlan_enable(); - - /* enable ACPI events */ - ec_write(0x00, 0xa6); - ec_write(0x01, 0x05); - - ec_write(0x02, 0xa0); - ec_write(0x03, 0x05); - - /* set mask of enabled beeps */ - ec_write(0x04, 0xfe); - ec_write(0x05, 0x96); - - /* Unknown, but required for hotkeys - Maybe a mask for enabled keys? */ - - ec_write(0x12, 0xff); - ec_write(0x13, 0xff); - ec_write(0x14, 0xf4); - ec_write(0x15, 0x3c); /* enable Audio */ - ec_clr_bit(0x3a, 0); + h8_set_audio_mute(0); /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); -- 1.7.4.1 From anton.kochkov at gmail.com Sun Apr 10 22:25:01 2011 From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=) Date: Mon, 11 Apr 2011 00:25:01 +0400 Subject: [coreboot] Strange ITE IT8502e Message-ID: Hello! I'm reversed my Dell Vostro V13 board enable (ODM - Inventec) and read from it that my EC have 0x600/0x601 ports. See here: http://paste.flashrom.org/view.php?id=472 And here strange output if i use 0x600/0x601 pair in superiotool: http://paste.flashrom.org/view.php?id=473 Best regards, Anton Kochkov. From joe at settoplinux.org Mon Apr 11 00:08:29 2011 From: joe at settoplinux.org (Joseph Smith) Date: Sun, 10 Apr 2011 18:08:29 -0400 Subject: [coreboot] ask for ideas and suggestions about CBFS support on ARM In-Reply-To: <4DA1D9E0.1090501@georgi-clan.de> References: <4DA1D673.3060704@settoplinux.org> <4DA1D9E0.1090501@georgi-clan.de> Message-ID: <4DA22A5D.70907@settoplinux.org> On 04/10/2011 12:25 PM, Patrick Georgi wrote: > Am 10.04.2011 18:10, schrieb Joseph Smith: >> How about spitting up the code using pre-processing directives? One for >> arm and one for IA32? Just a thought. > AHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH > > please. not. more. compile. time. options. > > > sorry I guess that is not a good idea then... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From schramp at holmes.nl Mon Apr 11 08:52:56 2011 From: schramp at holmes.nl (Ruud Schramp (DT)) Date: Mon, 11 Apr 2011 08:52:56 +0200 Subject: [coreboot] PATCH: superiotool probe for ServerEngines chip In-Reply-To: <20110408230823.GA12287@coreboot.org> References: <20110408230823.GA12287@coreboot.org> Message-ID: Updated Signed-off-by: Ruud Schramp -----Original Message----- From: coreboot-bounces+schramp=holmes.nl at coreboot.org [mailto:coreboot-bounces+schramp=holmes.nl at coreboot.org] On Behalf Of Stefan Reinauer Sent: Saturday, April 09, 2011 1:08 AM To: Ruud Schramp (DT) Cc: coreboot at coreboot.org Subject: Re: [coreboot] PATCH: superiotool probe for ServerEngines chip * Ruud Schramp (DT) [110408 10:21]: > Hi guys, > > Do not know how to handle the unknown devices (LDN's) yet. For now I > dump all IO base registers etc for information purposed. > > I have identified two LDN's as Serial port; (LDN 0x01 and LDN 0x02) > > Best regards, > > Ruud > > > Signed-off-by: Ruud Schramp > diff -uNr superiotool_org/serverengine.c superiotool/serverengine.c > --- superiotool_org/serverengine.c 1970-01-01 01:00:00.000000000 +0100 > +++ superiotool/serverengine.c 2011-04-08 10:13:33.000000000 +0200 please rename to serverengines.c > @@ -0,0 +1,106 @@ > +/* > + * This file is part of the superiotool project. > + * > + * Copyright (C) 2007 Uwe Hermann Please add your copyright here > + > +static const struct superio_registers reg_table[] = { > + /* TODO: M5113 doesn't seem to have ID registers? */ Astray line from original code? Please delete > + {0x02c0, "Server Engine SE-SM 4210-P01", { Drop Server Engine here. > + /* TODO: Not documented/available on M512x (?) */ Left over comment? Stefan -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- A non-text attachment was scrubbed... Name: server_engines.patch Type: application/octet-stream Size: 4888 bytes Desc: server_engines.patch URL: From svn at coreboot.org Mon Apr 11 09:46:27 2011 From: svn at coreboot.org (repository service) Date: Mon, 11 Apr 2011 09:46:27 +0200 Subject: [coreboot] [commit] r6484 - trunk/util/superiotool Message-ID: Author: uwe Date: Mon Apr 11 09:46:27 2011 New Revision: 6484 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6484 Log: Add detection/dump support for ServerEngines SE-SM 4210-P01. Note that the registers and their defaults are mostly based on educated guessing, due to the lack of datasheet. Signed-off-by: Ruud Schramp Acked-by: Uwe Hermann Added: trunk/util/superiotool/serverengines.c Modified: trunk/util/superiotool/Makefile trunk/util/superiotool/superiotool.h Modified: trunk/util/superiotool/Makefile ============================================================================== --- trunk/util/superiotool/Makefile Sun Apr 10 09:41:56 2011 (r6483) +++ trunk/util/superiotool/Makefile Mon Apr 11 09:46:27 2011 (r6484) @@ -33,7 +33,8 @@ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) LDFLAGS += -lz -OBJS = superiotool.o ali.o fintek.o ite.o nsc.o nuvoton.o smsc.o winbond.o +OBJS = superiotool.o serverengines.o ali.o fintek.o ite.o nsc.o nuvoton.o \ + smsc.o winbond.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) Added: trunk/util/superiotool/serverengines.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/util/superiotool/serverengines.c Mon Apr 11 09:46:27 2011 (r6484) @@ -0,0 +1,113 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2011 Ruud Schramp + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "superiotool.h" + +#define DEVICE_ID_BYTE1_REG 0x20 +#define DEVICE_ID_BYTE2_REG 0x21 + +#define DEVICE_REV_REG 0x1f + +static const struct superio_registers reg_table[] = { + /* + * Note: These register defaults are based on educated guessing, + * take them with a grain of salt. + * + * TODO: Don't know the ID registers yet: 0x21 probably is not an ID + * register as it is being set in the BIOS. For now still use as there + * is no known alternative. + */ + {0x02c0, "SE-SM 4210-P01", { + {NOLDN, NULL, + {0x1f,0x20,0x21,0x22,0x23,0x2c,0x2d,0x2e,EOT}, + {NANA,0x02,0xc0,0x00,0x00,RSVD,RSVD,RSVD,EOT}}, + {0x0, "UNKNOWN", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x1, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x00,0x02,0xf8,0x03,0x00,0x00,0x0c,EOT}}, + {0x2, "COM1", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x00,0x03,0xf8,0x04,0x00,0x00,0x0c,EOT}}, + {0x3, "UNKNOWN", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x4, "UNKNOWN", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x5, "UNKNOWN", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x6, "UNKNOWN", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x7, "UNKNOWN", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, + {EOT} +}; + +static void enter_conf_mode_serverengines(uint16_t port) +{ + OUTB(0x5a, port); +} + +static void exit_conf_mode_serverengines(uint16_t port) +{ + OUTB(0xa5, port); +} + +void probe_idregs_serverengines(uint16_t port) +{ + uint16_t id; + uint8_t rev; + + probing_for("Server Engines", "", port); + + enter_conf_mode_serverengines(port); + + id = regval(port, DEVICE_ID_BYTE1_REG) << 8; + id |= regval(port, DEVICE_ID_BYTE2_REG); + + /* TODO: Not documented/available on ServerEngines. */ + rev = regval(port, DEVICE_REV_REG); + + if (superio_unknown(reg_table, id)) { + if (verbose) + printf(NOTFOUND "id=0x%04x, rev=0x%02x\n", id, rev); + exit_conf_mode_serverengines(port); + return; + } + + printf("Found Server Engines %s (id=0x%04x, rev=0x%02x) at 0x%x\n", + get_superio_name(reg_table, id), id, rev, port); + chip_found = 1; + + dump_superio("Server Engines", reg_table, port, id, LDN_SEL); + + exit_conf_mode_serverengines(port); +} + +void print_serverengines_chips(void) +{ + print_vendor_chips("Server Engines", reg_table); +} Modified: trunk/util/superiotool/superiotool.h ============================================================================== --- trunk/util/superiotool/superiotool.h Sun Apr 10 09:41:56 2011 (r6483) +++ trunk/util/superiotool/superiotool.h Mon Apr 11 09:46:27 2011 (r6484) @@ -182,6 +182,10 @@ void probe_idregs_ali(uint16_t port); void print_ali_chips(void); +/* serverengines.c */ +void probe_idregs_serverengines(uint16_t port); +void print_serverengines_chips(void); + /* fintek.c */ void probe_idregs_fintek(uint16_t port); void probe_idregs_fintek_alternative(uint16_t port); @@ -232,6 +236,7 @@ #ifdef PCI_SUPPORT {probe_idregs_via, {0x3f0, EOT}}, #endif + {probe_idregs_serverengines, {0x2e, EOT}}, }; /** Table of functions to print out supported Super I/O chips. */ @@ -248,6 +253,7 @@ #ifdef PCI_SUPPORT {print_via_chips}, #endif + {print_serverengines_chips}, }; #endif From uwe at hermann-uwe.de Mon Apr 11 09:48:08 2011 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 11 Apr 2011 09:48:08 +0200 Subject: [coreboot] PATCH: superiotool probe for ServerEngines chip In-Reply-To: References: <20110408230823.GA12287@coreboot.org> Message-ID: <20110411074808.GB28121@greenwood> On Mon, Apr 11, 2011 at 08:52:56AM +0200, Ruud Schramp (DT) wrote: > Updated > > Signed-off-by: Ruud Schramp Thanks, r6484 with some minor cosmetic changes. Can you post a full dump of all LDNs (0-15) using isadump? Maybe you can guess a few more LDN names at least, judging from the register contents... Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org From schramp at holmes.nl Mon Apr 11 12:50:11 2011 From: schramp at holmes.nl (Ruud Schramp (DT)) Date: Mon, 11 Apr 2011 12:50:11 +0200 Subject: [coreboot] PATCH: superiotool probe for ServerEngines chip In-Reply-To: <20110411074808.GB28121@greenwood> References: <20110408230823.GA12287@coreboot.org> <20110411074808.GB28121@greenwood> Message-ID: As requested: root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 1 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 02 f8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 03 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 2 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 03 f8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 04 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 3 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 4 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 5 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 05 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 6 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 7 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 07 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 8 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 0c a0 0c a1 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 9 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 09 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 0c a2 0c a3 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 10 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 11 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 0b 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 e4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 12 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 0c a8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 13 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 0d 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 14 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 0e 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 70 00 72 00 00 00 00 00 00 00 00 00 00 00 00 70: 08 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 15 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 0f 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 16 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 03 00 00 04 04 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 17 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 11 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 18 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 12 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 19 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 13 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 20 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 14 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 21 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 15 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 22 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 16 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 23 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 24 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 00 00 00 00 00 00 00 18 00 00 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root at Microknoppix:~# -----Original Message----- From: coreboot-bounces+schramp=holmes.nl at coreboot.org [mailto:coreboot-bounces+schramp=holmes.nl at coreboot.org] On Behalf Of Uwe Hermann Sent: Monday, April 11, 2011 9:48 AM To: Ruud Schramp (DT) Cc: coreboot at coreboot.org Subject: Re: [coreboot] PATCH: superiotool probe for ServerEngines chip On Mon, Apr 11, 2011 at 08:52:56AM +0200, Ruud Schramp (DT) wrote: > Updated > > Signed-off-by: Ruud Schramp Thanks, r6484 with some minor cosmetic changes. Can you post a full dump of all LDNs (0-15) using isadump? Maybe you can guess a few more LDN names at least, judging from the register contents... Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot From svn at coreboot.org Mon Apr 11 16:00:02 2011 From: svn at coreboot.org (coreboot tracker) Date: Mon, 11 Apr 2011 16:00:02 +0200 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From schramp at holmes.nl Mon Apr 11 16:00:22 2011 From: schramp at holmes.nl (Ruud Schramp (DT)) Date: Mon, 11 Apr 2011 16:00:22 +0200 Subject: [coreboot] IPMI Message-ID: Hello guys, I am looking in the sourcecode of the dl145_g3 and noticed IPMI initialisation there (commented out). It refers a ipmi.c Does anyone have this code around? Best regards, Ruud From hamo.by at gmail.com Mon Apr 11 16:52:56 2011 From: hamo.by at gmail.com (Hamo) Date: Mon, 11 Apr 2011 22:52:56 +0800 Subject: [coreboot] ask for ideas and suggestions about CBFS support on ARM In-Reply-To: <4DA1CF55.4050302@gmx.net> References: <4DA1CF55.4050302@gmx.net> Message-ID: On Sun, Apr 10, 2011 at 11:40 PM, Carl-Daniel Hailfinger wrote: > Hi Hamo, > > I wrote a CBFS design change proposal ~2 years ago which handled such issues > just fine, but IIRC nobody had time to comment. I can try to dig it up > again. > > Regards, > Carl-Daniel Can you send your change to me? Thanks. > > Am 10.04.2011 14:49 schrieb Hamo: >> >> Dear lists, >> I have be studying CBFS filesystem these days. Since coreboot only >> supports IA32 architecture now, the CBFS has hard-coded boot address >> and all the boot-related code and master header are located at around >> 0xFFFFFFF0. But as ARM read their first instruction at 0x0, we need >> change the CBFS filesystem but not destroy IA32 support. When porting >> to ARM, how should the rom be organized? I have 2 ideas: >> 1. Totally rewrite the CBFS structure on ARM according to that one on >> IA32 to meet the requirement of ARM architecture, including move the >> reset code and bootblock to the start of ROM(at address 0x0) and put >> all the other components follow them. In this way, we should rewrite >> the CBFStool and add a new option to CBFStool to tell it the >> architecture we are using. >> 2. Use the same structure on IA32 architecture but set the master >> header's offset to other value than 0x0 so that we can put boot code >> at the start of rom. >> Which one should I take or Do we have any better choice? >> Hope for your help. >> >> > > > -- > http://www.hailfinger.org/ > > -- ? ? """ ? ? Keep It Simple,Stupid. ? ? """ Chinese Name: ?? Nick Name: Hamo Homepage: http://hamobai.com/ GPG KEY ID: 0xA4691A33 Key fingerprint = 09D5 2D78 8E2B 0995 CF8E? 4331 33C4 3D24 A469 1A33 From stefan.reinauer at coreboot.org Mon Apr 11 19:16:55 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Mon, 11 Apr 2011 19:16:55 +0200 Subject: [coreboot] IPMI In-Reply-To: References: Message-ID: <20110411171655.GA18371@coreboot.org> * Ruud Schramp (DT) [110411 16:00]: > Hello guys, > > I am looking in the sourcecode of the dl145_g3 and noticed IPMI > initialisation there (commented out). It refers a ipmi.c Does anyone > have this code around? I suggest you get in contact with the original authors. Stefan From stefan.reinauer at coreboot.org Mon Apr 11 19:21:53 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Mon, 11 Apr 2011 19:21:53 +0200 Subject: [coreboot] [PATCH 1/2] EC: Add Lenovo H8 In-Reply-To: <1302462311-26590-2-git-send-email-svens@stackframe.org> References: <1302462311-26590-2-git-send-email-svens@stackframe.org> Message-ID: <20110411172153.GA20250@coreboot.org> * Sven Schnelle [110410 21:05]: > diff --git a/src/mainboard/emulation/qemu b/src/mainboard/emulation/qemu > new file mode 100644 > index 0000000..d9275b5 > --- /dev/null > +++ b/src/mainboard/emulation/qemu ... > +#include "southbridge/intel/i82801gx/nvs.h" ... > + printk(BIOS_INFO, "ACPI: done.\n"); > + > + /* Enable Dummy DCC ON# for DVI */ > + printk(BIOS_DEBUG, "Laptop handling...\n"); > + outb(inb(0x60f) & ~(1 << 5), 0x60f); It looks like some code that does not fit to Qemu sneaked into here. From svens at stackframe.org Mon Apr 11 21:08:47 2011 From: svens at stackframe.org (Sven Schnelle) Date: Mon, 11 Apr 2011 21:08:47 +0200 Subject: [coreboot] [PATCH 1/2] EC: Add Lenovo H8 In-Reply-To: <20110411172153.GA20250@coreboot.org> (Stefan Reinauer's message of "Mon\, 11 Apr 2011 19\:21\:53 +0200") References: <1302462311-26590-2-git-send-email-svens@stackframe.org> <20110411172153.GA20250@coreboot.org> Message-ID: <87bp0cppvk.fsf@begreifnix.stackframe.org> Stefan Reinauer writes: >> diff --git a/src/mainboard/emulation/qemu b/src/mainboard/emulation/qemu >> new file mode 100644 >> index 0000000..d9275b5 >> --- /dev/null >> +++ b/src/mainboard/emulation/qemu > ... >> +#include "southbridge/intel/i82801gx/nvs.h" > ... >> + printk(BIOS_INFO, "ACPI: done.\n"); >> + >> + /* Enable Dummy DCC ON# for DVI */ >> + printk(BIOS_DEBUG, "Laptop handling...\n"); >> + outb(inb(0x60f) & ~(1 << 5), 0x60f); > > > It looks like some code that does not fit to Qemu sneaked into here. Yes, that was a leftover from a previous test. I'll fix this, and resend the patch. Sven. From svens at stackframe.org Mon Apr 11 21:10:27 2011 From: svens at stackframe.org (Sven Schnelle) Date: Mon, 11 Apr 2011 21:10:27 +0200 Subject: [coreboot] [PATCH 2/2] PMH7: Add chip config In-Reply-To: <1302549027-7034-1-git-send-email-svens@stackframe.org> References: <1302549027-7034-1-git-send-email-svens@stackframe.org> Message-ID: <1302549027-7034-2-git-send-email-svens@stackframe.org> Signed-off-by: Sven Schnelle --- src/ec/lenovo/pmh7/chip.h | 9 +++++++++ src/ec/lenovo/pmh7/pmh7.c | 12 ++++++++++++ src/ec/lenovo/pmh7/pmh7.h | 1 + src/mainboard/lenovo/x60/devicetree.cb | 1 + src/mainboard/lenovo/x60/mainboard.c | 7 ------- 5 files changed, 23 insertions(+), 7 deletions(-) create mode 100644 src/ec/lenovo/pmh7/chip.h diff --git a/src/ec/lenovo/pmh7/chip.h b/src/ec/lenovo/pmh7/chip.h new file mode 100644 index 0000000..e11b772 --- /dev/null +++ b/src/ec/lenovo/pmh7/chip.h @@ -0,0 +1,9 @@ +#ifndef EC_LENOVO_PMH7_CHIP_H +#define EC_LENOVO_PMH7_CHIP_H + +extern struct chip_operations ec_lenovo_pmh7_ops; + +struct ec_lenovo_pmh7_config { + int backlight_enable:1; +}; +#endif diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index a46e179..ba37866 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -23,6 +23,15 @@ #include #include #include "pmh7.h" +#include "chip.h" + +void pmh7_backlight_enable(int onoff) +{ + if (onoff) + pmh7_register_set_bit(0x50, 5); + else + pmh7_register_clear_bit(0x50, 5); +} void pmh7_register_set_bit(int reg, int bit) { @@ -58,6 +67,7 @@ void pmh7_register_write(int reg, int val) static void enable_dev(device_t dev) { + struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); @@ -66,6 +76,8 @@ static void enable_dev(device_t dev) resource->size = 16; resource->align = 5; resource->gran = 5; + + pmh7_backlight_enable(conf->backlight_enable); } struct chip_operations ec_lenovo_pmh7_ops = { diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h index a4a61cc..a85d710 100644 --- a/src/ec/lenovo/pmh7/pmh7.h +++ b/src/ec/lenovo/pmh7/pmh7.h @@ -31,4 +31,5 @@ void pmh7_register_clear_bit(int reg, int bit); char pmh7_register_read(int reg); void pmh7_register_write(int reg, int val); +void pmh7_backlight_enable(int onoff); #endif diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index f47fdae..d5ba7d9 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -85,6 +85,7 @@ chip northbridge/intel/i945 chip ec/lenovo/pmh7 device pnp ff.1 on # dummy end + register "backlight_enable" = "0x01" end chip ec/lenovo/h8 device pnp ff.2 on # dummy diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 15ed808..b9416b5 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -35,17 +35,10 @@ #include #include -static void backlight_enable(void) -{ - pmh7_register_set_bit(0x50, 5); -} - static void mainboard_enable(device_t dev) { device_t dev0; - backlight_enable(); - /* enable Audio */ h8_set_audio_mute(0); -- 1.7.4.1 From svens at stackframe.org Mon Apr 11 21:10:26 2011 From: svens at stackframe.org (Sven Schnelle) Date: Mon, 11 Apr 2011 21:10:26 +0200 Subject: [coreboot] [PATCH 1/2] EC: Add Lenovo H8 Message-ID: <1302549027-7034-1-git-send-email-svens@stackframe.org> Move the EC support code from the X60 mainboard to a generic driver, as this EC is used in many thinkpads. Also move the ACPI code to this directory for this reason. This patch also adds a chip config, so that the initial setting for basic register can be specified in devicetree.cb Signed-off-by: Sven Schnelle --- src/ec/lenovo/Kconfig | 1 + src/ec/lenovo/Makefile.inc | 1 + src/ec/lenovo/h8/Kconfig | 3 + src/ec/lenovo/h8/Makefile.inc | 1 + src/ec/lenovo/h8/acpi/ac.asl | 44 ++++ src/ec/lenovo/h8/acpi/battery.asl | 296 ++++++++++++++++++++++++ src/ec/lenovo/h8/acpi/beep.asl | 32 +++ src/ec/lenovo/h8/acpi/ec.asl | 122 ++++++++++ src/ec/lenovo/h8/acpi/lid.asl | 54 +++++ src/ec/lenovo/h8/acpi/sleepbutton.asl | 49 ++++ src/ec/lenovo/h8/acpi/systemstatus.asl | 63 +++++ src/ec/lenovo/h8/acpi/thermal.asl | 41 ++++ src/ec/lenovo/h8/chip.h | 36 +++ src/ec/lenovo/h8/h8.c | 129 ++++++++++ src/ec/lenovo/h8/h8.h | 111 +++++++++ src/mainboard/lenovo/x60/Kconfig | 2 +- src/mainboard/lenovo/x60/acpi/ac.asl | 44 ---- src/mainboard/lenovo/x60/acpi/battery.asl | 296 ------------------------ src/mainboard/lenovo/x60/acpi/beep.asl | 32 --- src/mainboard/lenovo/x60/acpi/dock.asl | 56 +++-- src/mainboard/lenovo/x60/acpi/ec.asl | 129 +---------- src/mainboard/lenovo/x60/acpi/gpe.asl | 4 +- src/mainboard/lenovo/x60/acpi/lid.asl | 54 ----- src/mainboard/lenovo/x60/acpi/sleepbutton.asl | 49 ---- src/mainboard/lenovo/x60/acpi/systemstatus.asl | 66 ------ src/mainboard/lenovo/x60/acpi/thermal.asl | 41 ---- src/mainboard/lenovo/x60/devicetree.cb | 18 ++- src/mainboard/lenovo/x60/dsdt.asl | 7 +- src/mainboard/lenovo/x60/mainboard.c | 62 +----- 29 files changed, 1044 insertions(+), 799 deletions(-) create mode 100644 src/ec/lenovo/h8/Kconfig create mode 100644 src/ec/lenovo/h8/Makefile.inc create mode 100644 src/ec/lenovo/h8/acpi/ac.asl create mode 100644 src/ec/lenovo/h8/acpi/battery.asl create mode 100644 src/ec/lenovo/h8/acpi/beep.asl create mode 100644 src/ec/lenovo/h8/acpi/ec.asl create mode 100644 src/ec/lenovo/h8/acpi/lid.asl create mode 100644 src/ec/lenovo/h8/acpi/sleepbutton.asl create mode 100644 src/ec/lenovo/h8/acpi/systemstatus.asl create mode 100644 src/ec/lenovo/h8/acpi/thermal.asl create mode 100644 src/ec/lenovo/h8/chip.h create mode 100644 src/ec/lenovo/h8/h8.c create mode 100644 src/ec/lenovo/h8/h8.h delete mode 100644 src/mainboard/lenovo/x60/acpi/ac.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/battery.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/beep.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/lid.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/sleepbutton.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/systemstatus.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/thermal.asl diff --git a/src/ec/lenovo/Kconfig b/src/ec/lenovo/Kconfig index b564b62..73f11ca 100644 --- a/src/ec/lenovo/Kconfig +++ b/src/ec/lenovo/Kconfig @@ -1 +1,2 @@ +source src/ec/lenovo/h8/Kconfig source src/ec/lenovo/pmh7/Kconfig diff --git a/src/ec/lenovo/Makefile.inc b/src/ec/lenovo/Makefile.inc index f9a3feb..8865030 100644 --- a/src/ec/lenovo/Makefile.inc +++ b/src/ec/lenovo/Makefile.inc @@ -1 +1,2 @@ +subdirs-$(CONFIG_EC_LENOVO_H8) += h8 subdirs-$(CONFIG_EC_LENOVO_PMH7) += pmh7 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig new file mode 100644 index 0000000..07bdb11 --- /dev/null +++ b/src/ec/lenovo/h8/Kconfig @@ -0,0 +1,3 @@ +config EC_LENOVO_H8 + select EC_ACPI + bool diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc new file mode 100644 index 0000000..86bc663 --- /dev/null +++ b/src/ec/lenovo/h8/Makefile.inc @@ -0,0 +1 @@ +driver-y += h8.c diff --git a/src/ec/lenovo/h8/acpi/ac.asl b/src/ec/lenovo/h8/acpi/ac.asl new file mode 100644 index 0000000..cbc84b2 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/ac.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x46), + , 4, + HPAC, 1 +} + +Device(AC) +{ + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return (HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return (0x0f) + } +} diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl new file mode 100644 index 0000000..7168581 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -0,0 +1,296 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x38), + B0ST, 4, /* Battery 0 state */ + , 1, + B0CH, 1, /* Battery 0 charging */ + B0DI, 1, /* Battery 0 discharging */ + B0PR, 1, /* Battery 0 present */ + Offset (0x39), + B1ST, 4, /* Battery 1 state */ + , 1, + B1CH, 1, /* Battery 1 charging, */ + B1DI, 1, /* Battery 1 discharging,*/ + B1PR, 1 /* Battery 1 present */ +} + +/* EC Registers */ +/* PAGE == 0x00 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BARC, 16, /* Battery remaining capacity */ + BAFC, 16, /* Battery full charge capacity */ + Offset(0xa8), + BAPR, 16, /* Battery present rate */ + BAVO, 16, /* Battery Voltage */ +} + +/* PAGE == 0x01 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + , 15, + BAMA, 1, +} + +/* PAGE == 0x02 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BADC, 16, /* Design Capacity */ + BADV, 16, /* Design voltage */ + , 16, + , 16, + , 16, + BASN, 16, +} + +/* PAGE == 0x04: Battery type */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BATY, 32 +} + + +/* PAGE == 0x05: Battery OEM information */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BAOE, 128 +} + +/* PAGE == 0x06: Battery name */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BANA, 128 +} + +/* Arg0: Battery + * Arg1: Battery Status Package + * Arg2: charging + * Arg3: discharging + */ +Method(BSTA, 4, NotSerialized) +{ + Acquire(ECLK, 0xffff) + Store(0, Local0) + Or(1, Arg0, PAGE) + Store(BAMA, Local1) + Store(Arg0, PAGE) /* Battery dynamic information */ + + Store(BAPR, Local2) + + if (Arg2) // charging + { + Or(2, Local0, Local0) + + If (LGreaterEqual (Local2, 0x8000)) { + Store(0, Local2) + } + } + + if (Arg3) // discharging + { + Or(1, Local0, Local0) + Subtract(0x10000, Local2, Local2) + } + + Store(Local0, Index(Arg1, 0x00)) + + if (Local1) { + Multiply (BARC, 10, Index(Arg1, 2)) + Multiply (Local2, BAVO, Local2) + Divide (Local2, 1000, Local3, Index(Arg1, 1)) + } else { + Store(BARC, Index(Arg1, 2)) + Store(Local2, Index(Arg1, 1)) + } + Store(BAVO, Index(Arg1, 3)) + Release(ECLK) + Return (Arg1) +} + +Method(BINF, 2, NotSerialized) +{ + Acquire(ECLK, 0xffff) + Or(1, Arg1, PAGE) /* Battery 0 static information */ + Xor(BAMA, 1, Index(Arg0, 0)) + Store(BAMA, Local0) + Store(Arg1, PAGE) + Store(BAFC, Local2) + Or(2, Arg1, PAGE) + Store(BADC, Local1) + + if (Local0) + { + Multiply (Local1, 10, Local1) + Multiply (Local2, 10, Local2) + } + + Store(Local1, Index(Arg0, 1)) // Design Capacity + Store(Local2, Index(Arg0, 2)) // Last full charge capacity + Store(BADV, Index(Arg0, 4)) // Design Voltage + Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity + + Store (BASN, Local0) + Name (SERN, Buffer (0x06) { " " }) + Store (4, Local1) + While (Local0) + { + Divide (Local0, 0x0A, Local2, Local0) + Add (Local2, 48, Index (SERN, Local1)) + Decrement (Local1) + } + Store (SERN, Index (Arg0, 10)) // Serial Number + + Or(4, Arg1, PAGE) + Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) + Store(BATY, TYPE) + Store(TYPE, Index (Arg0, 11)) // Battery type + Or(5, Arg1, PAGE) + Store(BAOE, Index (Arg0, 12)) // OEM information + Or(6, Arg1, PAGE) + Store(BANA, Index (Arg0, 9)) // Model number + Release(ECLK) + Return (Arg0) +} + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 0x00) + Name (_PCL, Package () { \_SB }) + + Name (BATS, Package () + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage (mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 1, // 7: granularity1 + 1, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Method (_BIF, 0, NotSerialized) + { + Return (BINF(BATS, 0)) + } + + Name (BATI, Package () + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method (_BST, 0, NotSerialized) + { + if (B0PR) { + Return (BSTA(0, BATI, B0CH, B0DI)) + } else { + Return (BATS) + } + } + + Method (_STA, 0, NotSerialized) + { + if (B0PR) { + Return (0x1f) + } else { + Return (0x0f) + } + } +} + +Device (BAT1) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 0x00) + Name (_PCL, Package () { \_SB }) + + Name (BATS, Package () + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage (mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 1, // 7: granularity1 + 1, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Method (_BIF, 0, NotSerialized) + { + Return (BINF(BATS, 0x10)) + } + + Name (BATI, Package () + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method (_BST, 0, NotSerialized) + { + if (B1PR) { + Return (BSTA(0x10, BATI, B1CH, B1DI)) + } else { + Return (BATS) + } + } + + Method (_STA, 0, NotSerialized) + { + if (B1PR) { + Return (0x1f) + } else { + Return (0x0f) + } + } +} diff --git a/src/ec/lenovo/h8/acpi/beep.asl b/src/ec/lenovo/h8/acpi/beep.asl new file mode 100644 index 0000000..718f41b --- /dev/null +++ b/src/ec/lenovo/h8/acpi/beep.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x06), + SNDS, 8 /* Write to this register to generate sound */ + +} + +Method(BEEP, 1, NotSerialized) +{ + Store (Arg0, SNDS) +} diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl new file mode 100644 index 0000000..98abfc1 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "smi.h" +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, 28) + Mutex (ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x05), + HSPA, 1, + Offset (0x0C), + LEDS, 8, /* LED state */ + Offset (0x3a), + AMUT, 1, /* Audio Mute */ + Offset (0x3B), + , 1, + KBLT, 1, /* Keyboard Light */ + Offset (0x4e), + WAKE, 16, + Offset (0x78), + TMP0, 8, /* Thermal Zone 0 temperature */ + TMP1, 8, /* Thermal Zone 1 temperature */ + Offset (0x81), + PAGE, 8 /* Information Page Selector */ + } + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + Return (ECMD) + } + + Method (LED, 1, NotSerialized) + { + Store(Arg0, LEDS) + } + + Method (_INI, 0, NotSerialized) + { + } + + Method (MUTE, 1, NotSerialized) + { + Store(Arg0, AMUT) + } + + /* Sleep Button pressed */ + Method(_Q13, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80) + } + + /* Brightness up GPE */ + Method(_Q14, 0, NotSerialized) + { + \DSPC.BRTU () + } + + /* Brightness down GPE */ + Method(_Q15, 0, NotSerialized) + { + \DSPC.BRTD() + } + + /* AC status change: present */ + Method(_Q26, 0, NotSerialized) + { + Notify (AC, 0x80) + } + + /* AC status change: not present */ + Method(_Q27, 0, NotSerialized) + { + Notify (AC, 0x80) + } + + Method(_Q2A, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) + } + + Method(_Q2B, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) + } + + +#include "ac.asl" +#include "battery.asl" +#include "sleepbutton.asl" +#include "lid.asl" +#include "beep.asl" +} diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl new file mode 100644 index 0000000..2dfa8d1 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x32), + , 2, + WKLD, 1, + Offset (0x46), + , 2, + LIDS, 1 +} + +Device(LID) +{ + Name(_HID, "PNP0C0D") + + Method(_LId, 0, NotSerialized) + { + return (LIDS) + } + + Method(_PRW, 0, NotSerialized) + { + Return (Package() { 0x18, 0x03 }) + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + Store(1, WKLD) + } else { + Store(0, WKLD) + } + } +} diff --git a/src/ec/lenovo/h8/acpi/sleepbutton.asl b/src/ec/lenovo/h8/acpi/sleepbutton.asl new file mode 100644 index 0000000..09e88aa --- /dev/null +++ b/src/ec/lenovo/h8/acpi/sleepbutton.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x32), + , 4, + WKFN, 1, + Offset(0x83), + FNKY, 8 +} + +Device(SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Method(_PRW, 0, NotSerialized) + { + Return (Package() { 0x18, 0x03 }) + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + Store(6, FNKY) /* Fn key acts as wake button */ + Store(1, WKFN) + } else { + Store(0, FNKY) /* Fn key normal operation */ + Store(0, WKFN) + } + } +} diff --git a/src/ec/lenovo/h8/acpi/systemstatus.asl b/src/ec/lenovo/h8/acpi/systemstatus.asl new file mode 100644 index 0000000..17e8ba7 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/systemstatus.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +Scope (\_SI) +{ + Method(_SST, 1, NotSerialized) + { + If (LEqual (Arg0, 0)) { + /* Indicator off */ + + /* power LED off */ + \_SB.PCI0.LPCB.EC.LED(0x00) + /* suspend LED off */ + \_SB.PCI0.LPCB.EC.LED(0x07) + } + + If (LEqual (Arg0, 1)) { + /* working state */ + + /* power LED on */ + \_SB.PCI0.LPCB.EC.LED(0x80) + /* suspend LED off */ + \_SB.PCI0.LPCB.EC.LED(0x07) + } + + If (LEqual (Arg0, 2)) { + /* waking state */ + + /* power LED om */ + \_SB.PCI0.LPCB.EC.LED(0x80) + /* suspend LED blinking */ + \_SB.PCI0.LPCB.EC.LED(0xc7) + } + + If (LEqual (Arg0, 3)) { + /* sleep state */ + + /* power LED off */ + \_SB.PCI0.LPCB.EC.LED(0x00) + /* suspend LED on */ + \_SB.PCI0.LPCB.EC.LED(0x87) + } + } +} diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl new file mode 100644 index 0000000..35b6f14 --- /dev/null +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -0,0 +1,41 @@ +Scope(\_TZ) +{ + Method(C2K, 1, NotSerialized) + { + Multiply(Arg0, 10, Local0) + Add (Local0, 2732, Local0) + if (LLessEqual(Local0, 2732)) { + Return (3000) + } + + if (LGreater(Local0, 4012)) { + Return (3000) + } + Return (Local0) + } + + ThermalZone(THM0) + { + Method(_CRT, 0, NotSerialized) { + Return (C2K(127)) + } + Method(_TMP) { + Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) + } + } + + ThermalZone(THM1) + { + Method(_CRT, 0, NotSerialized) { + Return (C2K(99)) + } + + Method(_PSV, 0, NotSerialized) { + Return (C2K(94)) + } + + Method(_TMP) { + Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) + } + } +} diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h new file mode 100644 index 0000000..d504654 --- /dev/null +++ b/src/ec/lenovo/h8/chip.h @@ -0,0 +1,36 @@ +#ifndef EC_LENOVO_H8EC_CHIP_H +#define EC_LENOVO_H8EC_CHIP_H + +extern struct chip_operations ec_lenovo_h8_ops; +struct ec_lenovo_h8_config { + + u8 config0; + u8 config1; + u8 config2; + u8 config3; + + u8 beepmask0; + u8 beepmask1; + + u8 event0_enable; + u8 event1_enable; + u8 event2_enable; + u8 event3_enable; + u8 event4_enable; + u8 event5_enable; + u8 event6_enable; + u8 event7_enable; + u8 event8_enable; + u8 event9_enable; + u8 eventa_enable; + u8 eventb_enable; + u8 eventc_enable; + u8 eventd_enable; + u8 evente_enable; + u8 eventf_enable; + + u8 trackpoint_enable; + u8 wlan_enable; + u8 wwan_enable; +}; +#endif diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c new file mode 100644 index 0000000..bc0ddde --- /dev/null +++ b/src/ec/lenovo/h8/h8.c @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "h8.h" +#include "chip.h" + +void h8_trackpoint_enable(int on) +{ + ec_write(H8_TRACKPOINT_CTRL, + on ? H8_TRACKPOINT_ON : H8_TRACKPOINT_OFF); + +} + +void h8_wlan_enable(int on) +{ + if (on) + ec_set_bit(0x3a, 5); + else + ec_clr_bit(0x3a, 5); +} + +static void h8_log_ec_version(void) +{ + unsigned char ecfw[9], c; + u16 fwvh, fwvl; + int i; + + for(i = 0; i < 8; i++) { + c = ec_read(0xf0 + i); + if (c < 0x20 || c > 0x7f) + break; + ecfw[i] = c; + } + ecfw[i] = '\0'; + + fwvh = ec_read(0xe9); + fwvl = ec_read(0xe8); + + printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); +} + +void h8_set_audio_mute(int on) +{ + if (on) + ec_clr_bit(0x3a, 0); + else + ec_set_bit(0x3a, 1); +} + +void h8_enable_event(int event) +{ + if (event < 0 || event > 127) + return; + + ec_set_bit(0x10 + (event >> 3), event & 7); +} + +void h8_disable_event(int event) +{ + if (event < 0 || event > 127) + return; + + ec_clr_bit(0x10 + (event >> 3), event & 7); + +} + +static void h8_enable(device_t dev) +{ + struct ec_lenovo_h8_config *conf = dev->chip_info; + h8_log_ec_version(); + + ec_write(H8_CONFIG0, conf->config0); + ec_write(H8_CONFIG1, conf->config1); + ec_write(H8_CONFIG2, conf->config2); + ec_write(H8_CONFIG3, conf->config3); + + ec_write(H8_SOUND_ENABLE0, conf->beepmask0); + ec_write(H8_SOUND_ENABLE1, conf->beepmask1); + ec_write(H8_SOUND_REPEAT, 0x00); + + ec_write(0x10, conf->event0_enable); + ec_write(0x11, conf->event1_enable); + ec_write(0x12, conf->event2_enable); + ec_write(0x13, conf->event3_enable); + ec_write(0x14, conf->event4_enable); + ec_write(0x15, conf->event5_enable); + ec_write(0x16, conf->event6_enable); + ec_write(0x17, conf->event7_enable); + ec_write(0x18, conf->event8_enable); + ec_write(0x19, conf->event9_enable); + ec_write(0x1a, conf->eventa_enable); + ec_write(0x1b, conf->eventb_enable); + ec_write(0x1c, conf->eventc_enable); + ec_write(0x1d, conf->eventd_enable); + ec_write(0x1e, conf->evente_enable); + ec_write(0x1f, conf->eventf_enable); + + h8_wlan_enable(conf->wlan_enable); + h8_trackpoint_enable(conf->trackpoint_enable); + +} + +struct chip_operations ec_lenovo_h8_ops = { + CHIP_NAME("Lenovo H8 EC") + .enable_dev = h8_enable +}; diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h new file mode 100644 index 0000000..cdb22ca --- /dev/null +++ b/src/ec/lenovo/h8/h8.h @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef EC_LENOVO_H8_H +#define EC_LENOVO_H8_H + +void h8_trackpoint_enable(int on); +void h8_wlan_enable(int on); +void h8_set_audio_mute(int on); +void h8_enable_event(int event); +void h8_disable_event(int event); + +/* EC registers */ +#define H8_CONFIG0 0x00 +#define H8_CONFIG0_EVENTS_ENABLE 0x02 +#define H8_CONFIG0_HOTKEY_ENABLE 0x04 +#define H8_CONFIG0_SMM_H8_ENABLE 0x20 +#define H8_CONFIG0_TC_ENABLE 0x80 + +#define H8_CONFIG1 0x01 +#define H8_CONFIG1_BKLT_LID 0x01 +#define H8_CONFIG1_UBAY_PWR 0x20 + +#define H8_CONFIG2 0x02 +#define H8_CONFIG2_USB_DOCK 0x01 +#define H8_CONFIG2_DOCK_SPEAKER_MUTE 0x02 +#define H8_CONFIG2_DOCK_SPEAKER_MUTE_POL 0x04 + +#define H8_CONFIG3 0x03 + +#define H8_SOUND_ENABLE0 0x04 +#define H8_SOUND_ENABLE1 0x05 +#define H8_SOUND_REG 0x06 +#define H8_SOUND_REPEAT 0x07 + +#define H8_TRACKPOINT_CTRL 0x0B +#define H8_TRACKPOINT_AUTO 0x01 +#define H8_TRACKPOINT_OFF 0x02 +#define H8_TRACKPOINT_ON 0x03 + +#define H8_LED_CONTROL 0x0c +#define H8_LED_CONTROL_OFF 0x00 +#define H8_LED_CONTROL_ON 0x80 +#define H8_LED_CONTROL_BLINK 0xc0 + +#define H8_LED_CONTROL_POWER_LED 0x00 +#define H8_LED_CONTROL_BAT0_LED 0x01 +#define H8_LED_CONTROL_BAT1_LED 0x02 +#define H8_LED_CONTROL_UBAY_LED 0x04 +#define H8_LED_CONTROL_SUSPEND_LED 0x07 +#define H8_LED_CONTROL_DOCK_LED1 0x08 +#define H8_LED_CONTROL_DOCK_LED2 0x09 + +/* Embedded controller events */ +#define H8_EVENT_FN_F1 0x10 +#define H8_EVENT_FN_F2 0x11 +#define H8_EVENT_FN_F3 0x12 +#define H8_EVENT_FN_F4 0x13 +#define H8_EVENT_FN_HOME 0x14 +#define H8_EVENT_FN_END 0x15 +#define H8_EVENT_FN_F7 0x16 +#define H8_EVENT_FN_F8 0x17 +#define H8_EVENT_FN_F9 0x18 +#define H8_EVENT_FN_THINKVANTAGE 0x19 +#define H8_EVENT_FN_F11 0x1a +#define H8_EVENT_FN_F12 0x1b +#define H8_EVENT_FN_1 0x1c +#define H8_EVENT_FN_2 0x1d +#define H8_EVENT_FN_PGUP 0x1f + +#define H8_EVENT_AC_ON 0x26 +#define H8_EVENT_AC_OFF 0x27 + +#define H8_EVENT_PWRSW_PRESS 0x28 +#define H8_EVENT_PWRSW_RELEASE 0x29 + +#define H8_EVENT_LIDSW_CLOSE 0x2a +#define H8_EVENT_LIDSW_PUSH 0x2b + +#define H8_EVENT_UBAY_UNLOCK 0x2c +#define H8_EVENT_UBAY_LOCK 0x2d + +#define H8_EVENT_KEYPRESS 0x33 + +#define H8_EVENT_FN_PRESS 0x39 + +#define H8_EVENT_BAT0 0x4a +#define H8_EVENT_BAT0_STATE 0x4b + +#define H8_EVENT_BAT1 0x4c +#define H8_EVENT_BAT1_STATE 0x4d + +#define H8_EVENT_FN_F5 0x64 +#define H8_EVENT_FN_F6 0x65 +#endif diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index ebd2c1c..c4b2f63 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87392 select EC_LENOVO_PMH7 - select EC_ACPI + select EC_LENOVO_H8 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/x60/acpi/ac.asl b/src/mainboard/lenovo/x60/acpi/ac.asl deleted file mode 100644 index cbc84b2..0000000 --- a/src/mainboard/lenovo/x60/acpi/ac.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x46), - , 4, - HPAC, 1 -} - -Device(AC) -{ - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) - - Method(_PSR, 0, NotSerialized) - { - return (HPAC) - } - - Method(_STA, 0, NotSerialized) - { - Return (0x0f) - } -} diff --git a/src/mainboard/lenovo/x60/acpi/battery.asl b/src/mainboard/lenovo/x60/acpi/battery.asl deleted file mode 100644 index 7168581..0000000 --- a/src/mainboard/lenovo/x60/acpi/battery.asl +++ /dev/null @@ -1,296 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x38), - B0ST, 4, /* Battery 0 state */ - , 1, - B0CH, 1, /* Battery 0 charging */ - B0DI, 1, /* Battery 0 discharging */ - B0PR, 1, /* Battery 0 present */ - Offset (0x39), - B1ST, 4, /* Battery 1 state */ - , 1, - B1CH, 1, /* Battery 1 charging, */ - B1DI, 1, /* Battery 1 discharging,*/ - B1PR, 1 /* Battery 1 present */ -} - -/* EC Registers */ -/* PAGE == 0x00 */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BARC, 16, /* Battery remaining capacity */ - BAFC, 16, /* Battery full charge capacity */ - Offset(0xa8), - BAPR, 16, /* Battery present rate */ - BAVO, 16, /* Battery Voltage */ -} - -/* PAGE == 0x01 */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - , 15, - BAMA, 1, -} - -/* PAGE == 0x02 */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BADC, 16, /* Design Capacity */ - BADV, 16, /* Design voltage */ - , 16, - , 16, - , 16, - BASN, 16, -} - -/* PAGE == 0x04: Battery type */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BATY, 32 -} - - -/* PAGE == 0x05: Battery OEM information */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BAOE, 128 -} - -/* PAGE == 0x06: Battery name */ -Field (ERAM, ByteAcc, NoLock, Preserve) -{ - Offset(0xa0), - BANA, 128 -} - -/* Arg0: Battery - * Arg1: Battery Status Package - * Arg2: charging - * Arg3: discharging - */ -Method(BSTA, 4, NotSerialized) -{ - Acquire(ECLK, 0xffff) - Store(0, Local0) - Or(1, Arg0, PAGE) - Store(BAMA, Local1) - Store(Arg0, PAGE) /* Battery dynamic information */ - - Store(BAPR, Local2) - - if (Arg2) // charging - { - Or(2, Local0, Local0) - - If (LGreaterEqual (Local2, 0x8000)) { - Store(0, Local2) - } - } - - if (Arg3) // discharging - { - Or(1, Local0, Local0) - Subtract(0x10000, Local2, Local2) - } - - Store(Local0, Index(Arg1, 0x00)) - - if (Local1) { - Multiply (BARC, 10, Index(Arg1, 2)) - Multiply (Local2, BAVO, Local2) - Divide (Local2, 1000, Local3, Index(Arg1, 1)) - } else { - Store(BARC, Index(Arg1, 2)) - Store(Local2, Index(Arg1, 1)) - } - Store(BAVO, Index(Arg1, 3)) - Release(ECLK) - Return (Arg1) -} - -Method(BINF, 2, NotSerialized) -{ - Acquire(ECLK, 0xffff) - Or(1, Arg1, PAGE) /* Battery 0 static information */ - Xor(BAMA, 1, Index(Arg0, 0)) - Store(BAMA, Local0) - Store(Arg1, PAGE) - Store(BAFC, Local2) - Or(2, Arg1, PAGE) - Store(BADC, Local1) - - if (Local0) - { - Multiply (Local1, 10, Local1) - Multiply (Local2, 10, Local2) - } - - Store(Local1, Index(Arg0, 1)) // Design Capacity - Store(Local2, Index(Arg0, 2)) // Last full charge capacity - Store(BADV, Index(Arg0, 4)) // Design Voltage - Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity - - Store (BASN, Local0) - Name (SERN, Buffer (0x06) { " " }) - Store (4, Local1) - While (Local0) - { - Divide (Local0, 0x0A, Local2, Local0) - Add (Local2, 48, Index (SERN, Local1)) - Decrement (Local1) - } - Store (SERN, Index (Arg0, 10)) // Serial Number - - Or(4, Arg1, PAGE) - Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) - Store(BATY, TYPE) - Store(TYPE, Index (Arg0, 11)) // Battery type - Or(5, Arg1, PAGE) - Store(BAOE, Index (Arg0, 12)) // OEM information - Or(6, Arg1, PAGE) - Store(BANA, Index (Arg0, 9)) // Model number - Release(ECLK) - Return (Arg0) -} - -Device (BAT0) -{ - Name (_HID, EisaId ("PNP0C0A")) - Name (_UID, 0x00) - Name (_PCL, Package () { \_SB }) - - Name (BATS, Package () - { - 0x00, // 0: PowerUnit: Report in mWh - 0xFFFFFFFF, // 1: Design cap - 0xFFFFFFFF, // 2: Last full charge cap - 0x01, // 3: Battery Technology - 10800, // 4: Design Voltage (mV) - 0x00, // 5: Warning design capacity - 200, // 6: Low design capacity - 1, // 7: granularity1 - 1, // 8: granularity2 - "", // 9: Model number - "", // A: Serial number - "", // B: Battery Type - "" // C: OEM information - }) - - Method (_BIF, 0, NotSerialized) - { - Return (BINF(BATS, 0)) - } - - Name (BATI, Package () - { - 0, // Battery State - // Bit 0 - discharge - // Bit 1 - charge - // Bit 2 - critical state - 0, // Battery present Rate - 0, // Battery remaining capacity - 0 // Battery present voltage - }) - - Method (_BST, 0, NotSerialized) - { - if (B0PR) { - Return (BSTA(0, BATI, B0CH, B0DI)) - } else { - Return (BATS) - } - } - - Method (_STA, 0, NotSerialized) - { - if (B0PR) { - Return (0x1f) - } else { - Return (0x0f) - } - } -} - -Device (BAT1) -{ - Name (_HID, EisaId ("PNP0C0A")) - Name (_UID, 0x00) - Name (_PCL, Package () { \_SB }) - - Name (BATS, Package () - { - 0x00, // 0: PowerUnit: Report in mWh - 0xFFFFFFFF, // 1: Design cap - 0xFFFFFFFF, // 2: Last full charge cap - 0x01, // 3: Battery Technology - 10800, // 4: Design Voltage (mV) - 0x00, // 5: Warning design capacity - 200, // 6: Low design capacity - 1, // 7: granularity1 - 1, // 8: granularity2 - "", // 9: Model number - "", // A: Serial number - "", // B: Battery Type - "" // C: OEM information - }) - - Method (_BIF, 0, NotSerialized) - { - Return (BINF(BATS, 0x10)) - } - - Name (BATI, Package () - { - 0, // Battery State - // Bit 0 - discharge - // Bit 1 - charge - // Bit 2 - critical state - 0, // Battery present Rate - 0, // Battery remaining capacity - 0 // Battery present voltage - }) - - Method (_BST, 0, NotSerialized) - { - if (B1PR) { - Return (BSTA(0x10, BATI, B1CH, B1DI)) - } else { - Return (BATS) - } - } - - Method (_STA, 0, NotSerialized) - { - if (B1PR) { - Return (0x1f) - } else { - Return (0x0f) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi/beep.asl b/src/mainboard/lenovo/x60/acpi/beep.asl deleted file mode 100644 index 718f41b..0000000 --- a/src/mainboard/lenovo/x60/acpi/beep.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x06), - SNDS, 8 /* Write to this register to generate sound */ - -} - -Method(BEEP, 1, NotSerialized) -{ - Store (Arg0, SNDS) -} diff --git a/src/mainboard/lenovo/x60/acpi/dock.asl b/src/mainboard/lenovo/x60/acpi/dock.asl index db61e05..d393f44 100644 --- a/src/mainboard/lenovo/x60/acpi/dock.asl +++ b/src/mainboard/lenovo/x60/acpi/dock.asl @@ -21,35 +21,47 @@ #include "smi.h" -OperationRegion (DLPC, SystemIO, 0x164c, 1) -Field(DLPC, ByteAcc, NoLock, Preserve) +Scope (\_SB) { - , 3, - DSTA, 1, -} -Device(DOCK) -{ - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) + OperationRegion (DLPC, SystemIO, 0x164c, 1) + Field(DLPC, ByteAcc, NoLock, Preserve) + { + , 3, + DSTA, 1, + } - Method(_DCK, 1, NotSerialized) + Device(DOCK) { - if (Arg0) { - Sleep(250) - /* connect dock */ - TRAP(SMI_DOCK_CONNECT) - } else { - /* disconnect dock */ - TRAP(SMI_DOCK_DISCONNECT) + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + Sleep(250) + /* connect dock */ + TRAP(SMI_DOCK_CONNECT) + } else { + /* disconnect dock */ + TRAP(SMI_DOCK_DISCONNECT) + } + + Xor(Arg0, DSTA, Local0) + Return (Local0) } - Xor(Arg0, DSTA, Local0) - Return (Local0) + Method(_STA, 0, NotSerialized) + { + Return (DSTA) + } } +} - Method(_STA, 0, NotSerialized) +Scope(\_SB.PCI0.LPCB.EC) +{ + Method(_Q18, 0, NotSerialized) { - Return (DSTA) + Notify(\_SB.DOCK, 3) } } diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl index 85ea491..c3569e8 100644 --- a/src/mainboard/lenovo/x60/acpi/ec.asl +++ b/src/mainboard/lenovo/x60/acpi/ec.asl @@ -1,128 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include "smi.h" -Device(EC) -{ - Name (_HID, EISAID("PNP0C09")) - Name (_UID, 0) - - Name (_GPE, 28) - Mutex (ECLK, 0) - - OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) - Field (ERAM, ByteAcc, NoLock, Preserve) - { - Offset (0x05), - HSPA, 1, - Offset (0x0C), - LEDS, 8, /* LED state */ - Offset (0x3a), - AMUT, 1, /* Audio Mute */ - Offset (0x3B), - , 1, - KBLT, 1, /* Keyboard Light */ - Offset (0x4e), - WAKE, 16, - Offset (0x78), - TMP0, 8, /* Thermal Zone 0 temperature */ - TMP1, 8, /* Thermal Zone 1 temperature */ - Offset (0x81), - PAGE, 8 /* Information Page Selector */ - } - - Method (_CRS, 0) - { - Name (ECMD, ResourceTemplate() - { - IO (Decode16, 0x62, 0x62, 1, 1) - IO (Decode16, 0x66, 0x66, 1, 1) - }) - Return (ECMD) - } - - Method (LED, 1, NotSerialized) - { - Store(Arg0, LEDS) - } - - Method (_INI, 0, NotSerialized) - { - } - - Method (MUTE, 1, NotSerialized) - { - Store(Arg0, AMUT) - } - - /* Sleep Button pressed */ - Method(_Q13, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80) - } - - /* Brightness up GPE */ - Method(_Q14, 0, NotSerialized) - { - \DSPC.BRTU () - } - - /* Brightness down GPE */ - Method(_Q15, 0, NotSerialized) - { - \DSPC.BRTD() - } - - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) - } - - /* AC status change: present */ - Method(_Q26, 0, NotSerialized) - { - Notify (AC, 0x80) - } - - /* AC status change: not present */ - Method(_Q27, 0, NotSerialized) - { - Notify (AC, 0x80) - } - - Method(_Q2A, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) - } - - Method(_Q2B, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) - } - - -#include "ac.asl" -#include "battery.asl" -#include "sleepbutton.asl" -#include "lid.asl" -#include "beep.asl" -#include "dock.asl" -} +#include diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl index 64e8e31..3aa9615 100644 --- a/src/mainboard/lenovo/x60/acpi/gpe.asl +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -12,10 +12,10 @@ Scope (\_GPE) { if (GP13) { Or(GIV1, 0x20, GIV1) - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) + Notify(\_SB.DOCK, 3) } else { And(GIV1, 0xdf, GIV1) - Notify(\_SB.PCI0.LPCB.EC.DOCK, 0) + Notify(\_SB.DOCK, 0) } } } diff --git a/src/mainboard/lenovo/x60/acpi/lid.asl b/src/mainboard/lenovo/x60/acpi/lid.asl deleted file mode 100644 index 2dfa8d1..0000000 --- a/src/mainboard/lenovo/x60/acpi/lid.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x32), - , 2, - WKLD, 1, - Offset (0x46), - , 2, - LIDS, 1 -} - -Device(LID) -{ - Name(_HID, "PNP0C0D") - - Method(_LId, 0, NotSerialized) - { - return (LIDS) - } - - Method(_PRW, 0, NotSerialized) - { - Return (Package() { 0x18, 0x03 }) - } - - Method(_PSW, 1, NotSerialized) - { - if (Arg0) { - Store(1, WKLD) - } else { - Store(0, WKLD) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi/sleepbutton.asl b/src/mainboard/lenovo/x60/acpi/sleepbutton.asl deleted file mode 100644 index 09e88aa..0000000 --- a/src/mainboard/lenovo/x60/acpi/sleepbutton.asl +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Field(ERAM, ByteAcc, NoLock, Preserve) -{ - Offset (0x32), - , 4, - WKFN, 1, - Offset(0x83), - FNKY, 8 -} - -Device(SLPB) -{ - Name (_HID, EisaId ("PNP0C0E")) - Method(_PRW, 0, NotSerialized) - { - Return (Package() { 0x18, 0x03 }) - } - - Method(_PSW, 1, NotSerialized) - { - if (Arg0) { - Store(6, FNKY) /* Fn key acts as wake button */ - Store(1, WKFN) - } else { - Store(0, FNKY) /* Fn key normal operation */ - Store(0, WKFN) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi/systemstatus.asl b/src/mainboard/lenovo/x60/acpi/systemstatus.asl deleted file mode 100644 index 161be08..0000000 --- a/src/mainboard/lenovo/x60/acpi/systemstatus.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - - -Scope (\_SI) -{ - Method(_SST, 1, NotSerialized) - { - If (LEqual (Arg0, 0)) { - /* Indicator off */ - - /* power LED off */ - \_SB.PCI0.LPCB.EC.LED(0x00) - /* suspend LED off */ - \_SB.PCI0.LPCB.EC.LED(0x07) - } - - If (LEqual (Arg0, 1)) { - /* working state */ - - /* power LED on */ - \_SB.PCI0.LPCB.EC.LED(0x80) - /* suspend LED off */ - \_SB.PCI0.LPCB.EC.LED(0x07) - } - - If (LEqual (Arg0, 2)) { - /* waking state */ - - /* power LED om */ - \_SB.PCI0.LPCB.EC.LED(0x80) - /* suspend LED blinking */ - \_SB.PCI0.LPCB.EC.LED(0xc7) - } - - If (LEqual (Arg0, 3)) { - /* sleep state */ - - /* power LED off */ - \_SB.PCI0.LPCB.EC.LED(0x00) - /* suspend LED on */ - \_SB.PCI0.LPCB.EC.LED(0x87) - } - - - - } -} diff --git a/src/mainboard/lenovo/x60/acpi/thermal.asl b/src/mainboard/lenovo/x60/acpi/thermal.asl deleted file mode 100644 index 35b6f14..0000000 --- a/src/mainboard/lenovo/x60/acpi/thermal.asl +++ /dev/null @@ -1,41 +0,0 @@ -Scope(\_TZ) -{ - Method(C2K, 1, NotSerialized) - { - Multiply(Arg0, 10, Local0) - Add (Local0, 2732, Local0) - if (LLessEqual(Local0, 2732)) { - Return (3000) - } - - if (LGreater(Local0, 4012)) { - Return (3000) - } - Return (Local0) - } - - ThermalZone(THM0) - { - Method(_CRT, 0, NotSerialized) { - Return (C2K(127)) - } - Method(_TMP) { - Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) - } - } - - ThermalZone(THM1) - { - Method(_CRT, 0, NotSerialized) { - Return (C2K(99)) - } - - Method(_PSV, 0, NotSerialized) { - Return (C2K(94)) - } - - Method(_TMP) { - Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) - } - } -} diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 2817255..f47fdae 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -86,13 +86,29 @@ chip northbridge/intel/i945 device pnp ff.1 on # dummy end end - chip ec/acpi + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 io 0x62 = 0x66 io 0x64 = 0x1600 io 0x66 = 0x1604 end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0x05" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + + register "wlan_enable" = "0x01" + register "trackpoint_enable" = "0x03" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 3467a8b..905c94a 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -40,10 +40,6 @@ DefinitionBlock( // mainboard specific devices #include "acpi/mainboard.asl" - // Thermal Zone - #include "acpi/thermal.asl" - // System status indicators - #include "acpi/systemstatus.asl" Scope (\_SB) { Device (PCI0) { @@ -54,4 +50,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + + // Dock support code + #include "acpi/dock.asl" } diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index c2aaaa9..15ed808 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -32,78 +32,22 @@ #include #include #include +#include #include static void backlight_enable(void) { - pmh7_register_set_bit(0x50, 5); -} - -static void trackpoint_enable(void) -{ - ec_write(0x0b, 0x03); -} - -static void wlan_enable(void) -{ - ec_write(0x3a, 0x20); -} - -static void log_ec_version(void) -{ - unsigned char ecfw[9], c; - u16 fwvh, fwvl; - int i; - - for(i = 0; i < 8; i++) { - c = ec_read(0xf0 + i); - if (c < 0x20 || c > 0x7f) - break; - ecfw[i] = c; - } - ecfw[i] = '\0'; - - fwvh = ec_read(0xe9); - fwvl = ec_read(0xe8); - - printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, - fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); + pmh7_register_set_bit(0x50, 5); } static void mainboard_enable(device_t dev) { device_t dev0; - log_ec_version(); - backlight_enable(); - trackpoint_enable(); - - /* FIXME: this should be ACPI's task - * but for now, enable it here */ - wlan_enable(); - - /* enable ACPI events */ - ec_write(0x00, 0xa6); - ec_write(0x01, 0x05); - - ec_write(0x02, 0xa0); - ec_write(0x03, 0x05); - - /* set mask of enabled beeps */ - ec_write(0x04, 0xfe); - ec_write(0x05, 0x96); - - /* Unknown, but required for hotkeys - Maybe a mask for enabled keys? */ - - ec_write(0x12, 0xff); - ec_write(0x13, 0xff); - ec_write(0x14, 0xf4); - ec_write(0x15, 0x3c); /* enable Audio */ - ec_clr_bit(0x3a, 0); + h8_set_audio_mute(0); /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); -- 1.7.4.1 From peter at stuge.se Mon Apr 11 21:22:49 2011 From: peter at stuge.se (Peter Stuge) Date: Mon, 11 Apr 2011 21:22:49 +0200 Subject: [coreboot] [PATCH 1/2] EC: Add Lenovo H8 In-Reply-To: <1302549027-7034-1-git-send-email-svens@stackframe.org> References: <1302549027-7034-1-git-send-email-svens@stackframe.org> Message-ID: <20110411192249.29613.qmail@stuge.se> Sven Schnelle wrote: > Move the EC support code from the X60 mainboard to a generic > driver, as this EC is used in many thinkpads. Also move the > ACPI code to this directory for this reason. > > This patch also adds a chip config, so that the initial setting > for basic register can be specified in devicetree.cb > > Signed-off-by: Sven Schnelle Acked-by: Peter Stuge From peter at stuge.se Mon Apr 11 21:22:55 2011 From: peter at stuge.se (Peter Stuge) Date: Mon, 11 Apr 2011 21:22:55 +0200 Subject: [coreboot] [PATCH 2/2] PMH7: Add chip config In-Reply-To: <1302549027-7034-2-git-send-email-svens@stackframe.org> References: <1302549027-7034-1-git-send-email-svens@stackframe.org> <1302549027-7034-2-git-send-email-svens@stackframe.org> Message-ID: <20110411192255.29658.qmail@stuge.se> Sven Schnelle wrote: > Signed-off-by: Sven Schnelle Acked-by: Peter Stuge From bari at onelabs.com Mon Apr 11 21:29:24 2011 From: bari at onelabs.com (bari) Date: Mon, 11 Apr 2011 14:29:24 -0500 Subject: [coreboot] Could you please recommend an ARM board for the GSoC project? In-Reply-To: References: Message-ID: <4DA35694.8090800@onelabs.com> I have updated the coreboot site with some further ARM info: http://www.coreboot.org/ARM OpenRD-Ultimate http://www.globalscaletechnologies.com/t-openrdudetails.aspx has a PCIe slot right on the back panel. Maybe we should use this if this GSOC project gets approved. -Bari From svn at coreboot.org Mon Apr 11 21:43:33 2011 From: svn at coreboot.org (repository service) Date: Mon, 11 Apr 2011 21:43:33 +0200 Subject: [coreboot] [commit] r6485 - in trunk/src: ec/lenovo ec/lenovo/h8 ec/lenovo/h8/acpi mainboard/lenovo/x60 mainboard/lenovo/x60/acpi Message-ID: Author: svens Date: Mon Apr 11 21:43:32 2011 New Revision: 6485 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6485 Log: EC: Add Lenovo H8 Move the EC support code from the X60 mainboard to a generic driver, as this EC is used in many thinkpads. Also move the ACPI code to this directory for this reason. This patch also adds a chip config, so that the initial setting for basic register can be specified in devicetree.cb Signed-off-by: Sven Schnelle Acked-by: Peter Stuge Added: trunk/src/ec/lenovo/h8/ trunk/src/ec/lenovo/h8/Kconfig trunk/src/ec/lenovo/h8/Makefile.inc trunk/src/ec/lenovo/h8/acpi/ trunk/src/ec/lenovo/h8/acpi/ac.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/ac.asl trunk/src/ec/lenovo/h8/acpi/battery.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/battery.asl trunk/src/ec/lenovo/h8/acpi/beep.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/beep.asl trunk/src/ec/lenovo/h8/acpi/ec.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/ec.asl trunk/src/ec/lenovo/h8/acpi/lid.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/lid.asl trunk/src/ec/lenovo/h8/acpi/sleepbutton.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl trunk/src/ec/lenovo/h8/acpi/systemstatus.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl trunk/src/ec/lenovo/h8/acpi/thermal.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/thermal.asl trunk/src/ec/lenovo/h8/chip.h trunk/src/ec/lenovo/h8/h8.c trunk/src/ec/lenovo/h8/h8.h Deleted: trunk/src/mainboard/lenovo/x60/acpi/ac.asl trunk/src/mainboard/lenovo/x60/acpi/battery.asl trunk/src/mainboard/lenovo/x60/acpi/beep.asl trunk/src/mainboard/lenovo/x60/acpi/lid.asl trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl trunk/src/mainboard/lenovo/x60/acpi/thermal.asl Modified: trunk/src/ec/lenovo/Kconfig trunk/src/ec/lenovo/Makefile.inc trunk/src/mainboard/lenovo/x60/Kconfig trunk/src/mainboard/lenovo/x60/acpi/dock.asl trunk/src/mainboard/lenovo/x60/acpi/ec.asl trunk/src/mainboard/lenovo/x60/acpi/gpe.asl trunk/src/mainboard/lenovo/x60/devicetree.cb trunk/src/mainboard/lenovo/x60/dsdt.asl trunk/src/mainboard/lenovo/x60/mainboard.c Modified: trunk/src/ec/lenovo/Kconfig ============================================================================== --- trunk/src/ec/lenovo/Kconfig Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/ec/lenovo/Kconfig Mon Apr 11 21:43:32 2011 (r6485) @@ -1 +1,2 @@ +source src/ec/lenovo/h8/Kconfig source src/ec/lenovo/pmh7/Kconfig Modified: trunk/src/ec/lenovo/Makefile.inc ============================================================================== --- trunk/src/ec/lenovo/Makefile.inc Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/ec/lenovo/Makefile.inc Mon Apr 11 21:43:32 2011 (r6485) @@ -1 +1,2 @@ +subdirs-$(CONFIG_EC_LENOVO_H8) += h8 subdirs-$(CONFIG_EC_LENOVO_PMH7) += pmh7 Added: trunk/src/ec/lenovo/h8/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/h8/Kconfig Mon Apr 11 21:43:32 2011 (r6485) @@ -0,0 +1,3 @@ +config EC_LENOVO_H8 + select EC_ACPI + bool Added: trunk/src/ec/lenovo/h8/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/h8/Makefile.inc Mon Apr 11 21:43:32 2011 (r6485) @@ -0,0 +1 @@ +driver-y += h8.c Copied and modified: trunk/src/ec/lenovo/h8/acpi/ac.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/ac.asl) ============================================================================== Copied and modified: trunk/src/ec/lenovo/h8/acpi/battery.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/battery.asl) ============================================================================== Copied and modified: trunk/src/ec/lenovo/h8/acpi/beep.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/beep.asl) ============================================================================== Copied and modified: trunk/src/ec/lenovo/h8/acpi/ec.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/ec.asl) ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/ec.asl Sun Apr 10 09:41:56 2011 (r6483, copy source) +++ trunk/src/ec/lenovo/h8/acpi/ec.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -54,7 +54,7 @@ Name (ECMD, ResourceTemplate() { IO (Decode16, 0x62, 0x62, 1, 1) - IO (Decode16, 0x66, 0x66, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) }) Return (ECMD) } @@ -91,11 +91,6 @@ \DSPC.BRTD() } - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) - } - /* AC status change: present */ Method(_Q26, 0, NotSerialized) { @@ -124,5 +119,4 @@ #include "sleepbutton.asl" #include "lid.asl" #include "beep.asl" -#include "dock.asl" } Copied and modified: trunk/src/ec/lenovo/h8/acpi/lid.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/lid.asl) ============================================================================== Copied and modified: trunk/src/ec/lenovo/h8/acpi/sleepbutton.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl) ============================================================================== Copied and modified: trunk/src/ec/lenovo/h8/acpi/systemstatus.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl) ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl Sun Apr 10 09:41:56 2011 (r6483, copy source) +++ trunk/src/ec/lenovo/h8/acpi/systemstatus.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -59,8 +59,5 @@ /* suspend LED on */ \_SB.PCI0.LPCB.EC.LED(0x87) } - - - } } Copied and modified: trunk/src/ec/lenovo/h8/acpi/thermal.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/thermal.asl) ============================================================================== Added: trunk/src/ec/lenovo/h8/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/h8/chip.h Mon Apr 11 21:43:32 2011 (r6485) @@ -0,0 +1,36 @@ +#ifndef EC_LENOVO_H8EC_CHIP_H +#define EC_LENOVO_H8EC_CHIP_H + +extern struct chip_operations ec_lenovo_h8_ops; +struct ec_lenovo_h8_config { + + u8 config0; + u8 config1; + u8 config2; + u8 config3; + + u8 beepmask0; + u8 beepmask1; + + u8 event0_enable; + u8 event1_enable; + u8 event2_enable; + u8 event3_enable; + u8 event4_enable; + u8 event5_enable; + u8 event6_enable; + u8 event7_enable; + u8 event8_enable; + u8 event9_enable; + u8 eventa_enable; + u8 eventb_enable; + u8 eventc_enable; + u8 eventd_enable; + u8 evente_enable; + u8 eventf_enable; + + u8 trackpoint_enable; + u8 wlan_enable; + u8 wwan_enable; +}; +#endif Added: trunk/src/ec/lenovo/h8/h8.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/h8/h8.c Mon Apr 11 21:43:32 2011 (r6485) @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "h8.h" +#include "chip.h" + +void h8_trackpoint_enable(int on) +{ + ec_write(H8_TRACKPOINT_CTRL, + on ? H8_TRACKPOINT_ON : H8_TRACKPOINT_OFF); + +} + +void h8_wlan_enable(int on) +{ + if (on) + ec_set_bit(0x3a, 5); + else + ec_clr_bit(0x3a, 5); +} + +static void h8_log_ec_version(void) +{ + unsigned char ecfw[9], c; + u16 fwvh, fwvl; + int i; + + for(i = 0; i < 8; i++) { + c = ec_read(0xf0 + i); + if (c < 0x20 || c > 0x7f) + break; + ecfw[i] = c; + } + ecfw[i] = '\0'; + + fwvh = ec_read(0xe9); + fwvl = ec_read(0xe8); + + printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); +} + +void h8_set_audio_mute(int on) +{ + if (on) + ec_clr_bit(0x3a, 0); + else + ec_set_bit(0x3a, 1); +} + +void h8_enable_event(int event) +{ + if (event < 0 || event > 127) + return; + + ec_set_bit(0x10 + (event >> 3), event & 7); +} + +void h8_disable_event(int event) +{ + if (event < 0 || event > 127) + return; + + ec_clr_bit(0x10 + (event >> 3), event & 7); + +} + +static void h8_enable(device_t dev) +{ + struct ec_lenovo_h8_config *conf = dev->chip_info; + h8_log_ec_version(); + + ec_write(H8_CONFIG0, conf->config0); + ec_write(H8_CONFIG1, conf->config1); + ec_write(H8_CONFIG2, conf->config2); + ec_write(H8_CONFIG3, conf->config3); + + ec_write(H8_SOUND_ENABLE0, conf->beepmask0); + ec_write(H8_SOUND_ENABLE1, conf->beepmask1); + ec_write(H8_SOUND_REPEAT, 0x00); + + ec_write(0x10, conf->event0_enable); + ec_write(0x11, conf->event1_enable); + ec_write(0x12, conf->event2_enable); + ec_write(0x13, conf->event3_enable); + ec_write(0x14, conf->event4_enable); + ec_write(0x15, conf->event5_enable); + ec_write(0x16, conf->event6_enable); + ec_write(0x17, conf->event7_enable); + ec_write(0x18, conf->event8_enable); + ec_write(0x19, conf->event9_enable); + ec_write(0x1a, conf->eventa_enable); + ec_write(0x1b, conf->eventb_enable); + ec_write(0x1c, conf->eventc_enable); + ec_write(0x1d, conf->eventd_enable); + ec_write(0x1e, conf->evente_enable); + ec_write(0x1f, conf->eventf_enable); + + h8_wlan_enable(conf->wlan_enable); + h8_trackpoint_enable(conf->trackpoint_enable); + +} + +struct chip_operations ec_lenovo_h8_ops = { + CHIP_NAME("Lenovo H8 EC") + .enable_dev = h8_enable +}; Added: trunk/src/ec/lenovo/h8/h8.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/h8/h8.h Mon Apr 11 21:43:32 2011 (r6485) @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef EC_LENOVO_H8_H +#define EC_LENOVO_H8_H + +void h8_trackpoint_enable(int on); +void h8_wlan_enable(int on); +void h8_set_audio_mute(int on); +void h8_enable_event(int event); +void h8_disable_event(int event); + +/* EC registers */ +#define H8_CONFIG0 0x00 +#define H8_CONFIG0_EVENTS_ENABLE 0x02 +#define H8_CONFIG0_HOTKEY_ENABLE 0x04 +#define H8_CONFIG0_SMM_H8_ENABLE 0x20 +#define H8_CONFIG0_TC_ENABLE 0x80 + +#define H8_CONFIG1 0x01 +#define H8_CONFIG1_BKLT_LID 0x01 +#define H8_CONFIG1_UBAY_PWR 0x20 + +#define H8_CONFIG2 0x02 +#define H8_CONFIG2_USB_DOCK 0x01 +#define H8_CONFIG2_DOCK_SPEAKER_MUTE 0x02 +#define H8_CONFIG2_DOCK_SPEAKER_MUTE_POL 0x04 + +#define H8_CONFIG3 0x03 + +#define H8_SOUND_ENABLE0 0x04 +#define H8_SOUND_ENABLE1 0x05 +#define H8_SOUND_REG 0x06 +#define H8_SOUND_REPEAT 0x07 + +#define H8_TRACKPOINT_CTRL 0x0B +#define H8_TRACKPOINT_AUTO 0x01 +#define H8_TRACKPOINT_OFF 0x02 +#define H8_TRACKPOINT_ON 0x03 + +#define H8_LED_CONTROL 0x0c +#define H8_LED_CONTROL_OFF 0x00 +#define H8_LED_CONTROL_ON 0x80 +#define H8_LED_CONTROL_BLINK 0xc0 + +#define H8_LED_CONTROL_POWER_LED 0x00 +#define H8_LED_CONTROL_BAT0_LED 0x01 +#define H8_LED_CONTROL_BAT1_LED 0x02 +#define H8_LED_CONTROL_UBAY_LED 0x04 +#define H8_LED_CONTROL_SUSPEND_LED 0x07 +#define H8_LED_CONTROL_DOCK_LED1 0x08 +#define H8_LED_CONTROL_DOCK_LED2 0x09 + +/* Embedded controller events */ +#define H8_EVENT_FN_F1 0x10 +#define H8_EVENT_FN_F2 0x11 +#define H8_EVENT_FN_F3 0x12 +#define H8_EVENT_FN_F4 0x13 +#define H8_EVENT_FN_HOME 0x14 +#define H8_EVENT_FN_END 0x15 +#define H8_EVENT_FN_F7 0x16 +#define H8_EVENT_FN_F8 0x17 +#define H8_EVENT_FN_F9 0x18 +#define H8_EVENT_FN_THINKVANTAGE 0x19 +#define H8_EVENT_FN_F11 0x1a +#define H8_EVENT_FN_F12 0x1b +#define H8_EVENT_FN_1 0x1c +#define H8_EVENT_FN_2 0x1d +#define H8_EVENT_FN_PGUP 0x1f + +#define H8_EVENT_AC_ON 0x26 +#define H8_EVENT_AC_OFF 0x27 + +#define H8_EVENT_PWRSW_PRESS 0x28 +#define H8_EVENT_PWRSW_RELEASE 0x29 + +#define H8_EVENT_LIDSW_CLOSE 0x2a +#define H8_EVENT_LIDSW_PUSH 0x2b + +#define H8_EVENT_UBAY_UNLOCK 0x2c +#define H8_EVENT_UBAY_LOCK 0x2d + +#define H8_EVENT_KEYPRESS 0x33 + +#define H8_EVENT_FN_PRESS 0x39 + +#define H8_EVENT_BAT0 0x4a +#define H8_EVENT_BAT0_STATE 0x4b + +#define H8_EVENT_BAT1 0x4c +#define H8_EVENT_BAT1_STATE 0x4d + +#define H8_EVENT_FN_F5 0x64 +#define H8_EVENT_FN_F6 0x65 +#endif Modified: trunk/src/mainboard/lenovo/x60/Kconfig ============================================================================== --- trunk/src/mainboard/lenovo/x60/Kconfig Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/Kconfig Mon Apr 11 21:43:32 2011 (r6485) @@ -11,7 +11,7 @@ select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87392 select EC_LENOVO_PMH7 - select EC_ACPI + select EC_LENOVO_H8 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/lenovo/x60/acpi/dock.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/dock.asl Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/acpi/dock.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -21,35 +21,47 @@ #include "smi.h" -OperationRegion (DLPC, SystemIO, 0x164c, 1) -Field(DLPC, ByteAcc, NoLock, Preserve) +Scope (\_SB) { - , 3, - DSTA, 1, -} -Device(DOCK) -{ - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) + OperationRegion (DLPC, SystemIO, 0x164c, 1) + Field(DLPC, ByteAcc, NoLock, Preserve) + { + , 3, + DSTA, 1, + } - Method(_DCK, 1, NotSerialized) + Device(DOCK) { - if (Arg0) { - Sleep(250) - /* connect dock */ - TRAP(SMI_DOCK_CONNECT) - } else { - /* disconnect dock */ - TRAP(SMI_DOCK_DISCONNECT) + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + Sleep(250) + /* connect dock */ + TRAP(SMI_DOCK_CONNECT) + } else { + /* disconnect dock */ + TRAP(SMI_DOCK_DISCONNECT) + } + + Xor(Arg0, DSTA, Local0) + Return (Local0) } - Xor(Arg0, DSTA, Local0) - Return (Local0) + Method(_STA, 0, NotSerialized) + { + Return (DSTA) + } } +} - Method(_STA, 0, NotSerialized) +Scope(\_SB.PCI0.LPCB.EC) +{ + Method(_Q18, 0, NotSerialized) { - Return (DSTA) + Notify(\_SB.DOCK, 3) } } Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/ec.asl Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -1,128 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include "smi.h" -Device(EC) -{ - Name (_HID, EISAID("PNP0C09")) - Name (_UID, 0) - - Name (_GPE, 28) - Mutex (ECLK, 0) - - OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) - Field (ERAM, ByteAcc, NoLock, Preserve) - { - Offset (0x05), - HSPA, 1, - Offset (0x0C), - LEDS, 8, /* LED state */ - Offset (0x3a), - AMUT, 1, /* Audio Mute */ - Offset (0x3B), - , 1, - KBLT, 1, /* Keyboard Light */ - Offset (0x4e), - WAKE, 16, - Offset (0x78), - TMP0, 8, /* Thermal Zone 0 temperature */ - TMP1, 8, /* Thermal Zone 1 temperature */ - Offset (0x81), - PAGE, 8 /* Information Page Selector */ - } - - Method (_CRS, 0) - { - Name (ECMD, ResourceTemplate() - { - IO (Decode16, 0x62, 0x62, 1, 1) - IO (Decode16, 0x66, 0x66, 1, 1) - }) - Return (ECMD) - } - - Method (LED, 1, NotSerialized) - { - Store(Arg0, LEDS) - } - - Method (_INI, 0, NotSerialized) - { - } - - Method (MUTE, 1, NotSerialized) - { - Store(Arg0, AMUT) - } - - /* Sleep Button pressed */ - Method(_Q13, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80) - } - - /* Brightness up GPE */ - Method(_Q14, 0, NotSerialized) - { - \DSPC.BRTU () - } - - /* Brightness down GPE */ - Method(_Q15, 0, NotSerialized) - { - \DSPC.BRTD() - } - - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) - } - - /* AC status change: present */ - Method(_Q26, 0, NotSerialized) - { - Notify (AC, 0x80) - } - - /* AC status change: not present */ - Method(_Q27, 0, NotSerialized) - { - Notify (AC, 0x80) - } - - Method(_Q2A, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) - } - - Method(_Q2B, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) - } - - -#include "ac.asl" -#include "battery.asl" -#include "sleepbutton.asl" -#include "lid.asl" -#include "beep.asl" -#include "dock.asl" -} +#include Modified: trunk/src/mainboard/lenovo/x60/acpi/gpe.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/gpe.asl Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/acpi/gpe.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -12,10 +12,10 @@ { if (GP13) { Or(GIV1, 0x20, GIV1) - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) + Notify(\_SB.DOCK, 3) } else { And(GIV1, 0xdf, GIV1) - Notify(\_SB.PCI0.LPCB.EC.DOCK, 0) + Notify(\_SB.DOCK, 0) } } } Modified: trunk/src/mainboard/lenovo/x60/devicetree.cb ============================================================================== --- trunk/src/mainboard/lenovo/x60/devicetree.cb Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/devicetree.cb Mon Apr 11 21:43:32 2011 (r6485) @@ -86,13 +86,29 @@ device pnp ff.1 on # dummy end end - chip ec/acpi + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 io 0x62 = 0x66 io 0x64 = 0x1600 io 0x66 = 0x1604 end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0x05" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + + register "wlan_enable" = "0x01" + register "trackpoint_enable" = "0x03" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR Modified: trunk/src/mainboard/lenovo/x60/dsdt.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/dsdt.asl Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/dsdt.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -40,10 +40,6 @@ // mainboard specific devices #include "acpi/mainboard.asl" - // Thermal Zone - #include "acpi/thermal.asl" - // System status indicators - #include "acpi/systemstatus.asl" Scope (\_SB) { Device (PCI0) { @@ -54,4 +50,7 @@ /* Chipset specific sleep states */ #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + + // Dock support code + #include "acpi/dock.asl" } Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 11 21:43:32 2011 (r6485) @@ -32,78 +32,22 @@ #include #include #include +#include #include static void backlight_enable(void) { - pmh7_register_set_bit(0x50, 5); -} - -static void trackpoint_enable(void) -{ - ec_write(0x0b, 0x03); -} - -static void wlan_enable(void) -{ - ec_write(0x3a, 0x20); -} - -static void log_ec_version(void) -{ - unsigned char ecfw[9], c; - u16 fwvh, fwvl; - int i; - - for(i = 0; i < 8; i++) { - c = ec_read(0xf0 + i); - if (c < 0x20 || c > 0x7f) - break; - ecfw[i] = c; - } - ecfw[i] = '\0'; - - fwvh = ec_read(0xe9); - fwvl = ec_read(0xe8); - - printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, - fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); + pmh7_register_set_bit(0x50, 5); } static void mainboard_enable(device_t dev) { device_t dev0; - log_ec_version(); - backlight_enable(); - trackpoint_enable(); - - /* FIXME: this should be ACPI's task - * but for now, enable it here */ - wlan_enable(); - - /* enable ACPI events */ - ec_write(0x00, 0xa6); - ec_write(0x01, 0x05); - - ec_write(0x02, 0xa0); - ec_write(0x03, 0x05); - - /* set mask of enabled beeps */ - ec_write(0x04, 0xfe); - ec_write(0x05, 0x96); - - /* Unknown, but required for hotkeys - Maybe a mask for enabled keys? */ - - ec_write(0x12, 0xff); - ec_write(0x13, 0xff); - ec_write(0x14, 0xf4); - ec_write(0x15, 0x3c); /* enable Audio */ - ec_clr_bit(0x3a, 0); + h8_set_audio_mute(0); /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); From svn at coreboot.org Mon Apr 11 21:43:51 2011 From: svn at coreboot.org (repository service) Date: Mon, 11 Apr 2011 21:43:51 +0200 Subject: [coreboot] [commit] r6486 - in trunk/src: ec/lenovo/pmh7 mainboard/lenovo/x60 Message-ID: Author: svens Date: Mon Apr 11 21:43:50 2011 New Revision: 6486 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6486 Log: PMH7: Add chip config Signed-off-by: Sven Schnelle Acked-by: Peter Stuge Added: trunk/src/ec/lenovo/pmh7/chip.h Modified: trunk/src/ec/lenovo/pmh7/pmh7.c trunk/src/ec/lenovo/pmh7/pmh7.h trunk/src/mainboard/lenovo/x60/devicetree.cb trunk/src/mainboard/lenovo/x60/mainboard.c Added: trunk/src/ec/lenovo/pmh7/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/pmh7/chip.h Mon Apr 11 21:43:50 2011 (r6486) @@ -0,0 +1,9 @@ +#ifndef EC_LENOVO_PMH7_CHIP_H +#define EC_LENOVO_PMH7_CHIP_H + +extern struct chip_operations ec_lenovo_pmh7_ops; + +struct ec_lenovo_pmh7_config { + int backlight_enable:1; +}; +#endif Modified: trunk/src/ec/lenovo/pmh7/pmh7.c ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.c Mon Apr 11 21:43:32 2011 (r6485) +++ trunk/src/ec/lenovo/pmh7/pmh7.c Mon Apr 11 21:43:50 2011 (r6486) @@ -23,6 +23,15 @@ #include #include #include "pmh7.h" +#include "chip.h" + +void pmh7_backlight_enable(int onoff) +{ + if (onoff) + pmh7_register_set_bit(0x50, 5); + else + pmh7_register_clear_bit(0x50, 5); +} void pmh7_register_set_bit(int reg, int bit) { @@ -58,6 +67,7 @@ static void enable_dev(device_t dev) { + struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); @@ -66,6 +76,8 @@ resource->size = 16; resource->align = 5; resource->gran = 5; + + pmh7_backlight_enable(conf->backlight_enable); } struct chip_operations ec_lenovo_pmh7_ops = { Modified: trunk/src/ec/lenovo/pmh7/pmh7.h ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.h Mon Apr 11 21:43:32 2011 (r6485) +++ trunk/src/ec/lenovo/pmh7/pmh7.h Mon Apr 11 21:43:50 2011 (r6486) @@ -31,4 +31,5 @@ char pmh7_register_read(int reg); void pmh7_register_write(int reg, int val); +void pmh7_backlight_enable(int onoff); #endif Modified: trunk/src/mainboard/lenovo/x60/devicetree.cb ============================================================================== --- trunk/src/mainboard/lenovo/x60/devicetree.cb Mon Apr 11 21:43:32 2011 (r6485) +++ trunk/src/mainboard/lenovo/x60/devicetree.cb Mon Apr 11 21:43:50 2011 (r6486) @@ -85,6 +85,7 @@ chip ec/lenovo/pmh7 device pnp ff.1 on # dummy end + register "backlight_enable" = "0x01" end chip ec/lenovo/h8 device pnp ff.2 on # dummy Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 11 21:43:32 2011 (r6485) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 11 21:43:50 2011 (r6486) @@ -35,17 +35,10 @@ #include #include -static void backlight_enable(void) -{ - pmh7_register_set_bit(0x50, 5); -} - static void mainboard_enable(device_t dev) { device_t dev0; - backlight_enable(); - /* enable Audio */ h8_set_audio_mute(0); From svn at coreboot.org Mon Apr 11 22:17:23 2011 From: svn at coreboot.org (repository service) Date: Mon, 11 Apr 2011 22:17:23 +0200 Subject: [coreboot] [commit] r6487 - in trunk/src: arch/x86/init arch/x86/lib boot cpu/amd/model_gx2 cpu/amd/model_lx cpu/amd/sc520 cpu/intel/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/via/c... Message-ID: Author: stepan Date: Mon Apr 11 22:17:22 2011 New Revision: 6487 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6487 Log: Unify use of post_code Signed-off-by: Alexandru Gagniuc Acked-by: Stefan Reinauer Added: trunk/src/include/console/post_codes.h Modified: trunk/src/arch/x86/init/crt0_romcc_epilogue.inc trunk/src/arch/x86/init/prologue.inc trunk/src/arch/x86/lib/c_start.S trunk/src/boot/hardwaremain.c trunk/src/boot/selfboot.c trunk/src/cpu/amd/model_gx2/cache_as_ram.inc trunk/src/cpu/amd/model_lx/cache_as_ram.inc trunk/src/cpu/amd/sc520/raminit.c trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/cpu/x86/32bit/entry32.inc trunk/src/include/console/console.h trunk/src/include/cpu/amd/geode_post_code.h trunk/src/include/cpu/x86/post_code.h trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/lippert/hurricane-lx/romstage.c trunk/src/mainboard/lippert/literunner-lx/romstage.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/pcengines/alix2d/romstage.c trunk/src/mainboard/traverse/geos/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/mainboard/wyse/s50/romstage.c trunk/src/northbridge/amd/gx1/raminit.c trunk/src/northbridge/via/cx700/early_serial.c trunk/src/northbridge/via/vx800/early_serial.c trunk/src/southbridge/amd/cs5535/chipsetinit.c trunk/src/southbridge/amd/cs5536/cs5536.c trunk/src/southbridge/via/vt8231/early_serial.c Modified: trunk/src/arch/x86/init/crt0_romcc_epilogue.inc ============================================================================== --- trunk/src/arch/x86/init/crt0_romcc_epilogue.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/arch/x86/init/crt0_romcc_epilogue.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -5,11 +5,12 @@ * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of the License. */ +#include /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* clear direction flag */ movl %ebp, %esi @@ -20,7 +21,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/arch/x86/init/prologue.inc ============================================================================== --- trunk/src/arch/x86/init/prologue.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/arch/x86/init/prologue.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -25,5 +25,5 @@ /* This is the entry code. The code in the .reset section jumps here. */ - post_code(0x01) + post_code(POST_RESET_VECTOR_CORRECT) Modified: trunk/src/arch/x86/lib/c_start.S ============================================================================== --- trunk/src/arch/x86/lib/c_start.S Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/arch/x86/lib/c_start.S Mon Apr 11 22:17:22 2011 (r6487) @@ -14,7 +14,7 @@ movl %eax, %fs movl %eax, %gs - post_code(0x13) /* post 13 */ + post_code(POST_ENTRY_C_START) /* post 13 */ /** clear stack */ cld @@ -73,7 +73,7 @@ * bss is cleared. Now we call the main routine and * let it do the rest. */ - post_code(0xfe) /* post fe */ + post_code(POST_PRE_HARDWAREMAIN) /* post fe */ /* Restore the stack location */ movl %ebp, %esp @@ -82,7 +82,7 @@ call hardwaremain /* NOTREACHED */ .Lhlt: - post_code(0xee) /* post ee */ + post_code(POST_DEAD_CODE) /* post ee */ hlt jmp .Lhlt Modified: trunk/src/boot/hardwaremain.c ============================================================================== --- trunk/src/boot/hardwaremain.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/boot/hardwaremain.c Mon Apr 11 22:17:22 2011 (r6487) @@ -57,18 +57,18 @@ { struct lb_memory *lb_mem; - post_code(0x80); + post_code(POST_ENTRY_RAMSTAGE); /* console_init() MUST PRECEDE ALL printk()! */ console_init(); - post_code(0x39); + post_code(POST_CONSOLE_READY); printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", coreboot_version, coreboot_extra_version, coreboot_build, (boot_complete)?"rebooting":"booting"); - post_code(0x40); + post_code(POST_CONSOLE_BOOT_MSG); /* If we have already booted attempt a hard reboot */ if (boot_complete) { @@ -80,15 +80,15 @@ /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); - post_code(0x66); + post_code(POST_DEVICE_ENUMERATION_COMPLETE); /* Now compute and assign the bus resources. */ dev_configure(); - post_code(0x88); + post_code(POST_DEVICE_CONFIGURATION_COMPLETE); /* Now actually enable devices on the bus */ dev_enable(); /* And of course initialize devices on the bus */ dev_initialize(); - post_code(0x89); + post_code(POST_DEVICES_ENABLED); #if CONFIG_WRITE_HIGH_TABLES == 1 cbmem_initialize(); Modified: trunk/src/boot/selfboot.c ============================================================================== --- trunk/src/boot/selfboot.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/boot/selfboot.c Mon Apr 11 22:17:22 2011 (r6487) @@ -553,7 +553,7 @@ boot_successful(); printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry); - post_code(0xfe); + post_code(POST_ENTER_ELF_BOOT); /* Jump to kernel */ jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size); Modified: trunk/src/cpu/amd/model_gx2/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/model_gx2/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/amd/model_gx2/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -27,6 +27,7 @@ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #include +#include /*************************************************************************** /** /** DCacheSetup @@ -184,7 +185,7 @@ /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -201,7 +202,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/model_lx/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -26,6 +26,7 @@ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #include +#include /*************************************************************************** /** /** DCacheSetup @@ -210,7 +211,7 @@ /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -227,7 +228,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/amd/sc520/raminit.c ============================================================================== --- trunk/src/cpu/amd/sc520/raminit.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/amd/sc520/raminit.c Mon Apr 11 22:17:22 2011 (r6487) @@ -144,13 +144,13 @@ /* the 0x80 led should now be working*/ - outb(0xaa, 0x80); + post_code(0xaa); #if 0 - /* wtf are 680 leds ... */ + /* wtf are 680 leds ... *//* <-- WTF is this comment? */ par = (unsigned long *) 0xfffef0c4; *par = 0x28000680; /* well? */ - outb(0x55, 0x80); + post_code(0x55); #endif /* set the uart baud rate clocks to the normal 1.8432 MHz.*/ Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -24,6 +24,7 @@ #include #include #include +#include #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) @@ -364,7 +365,7 @@ /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -375,7 +376,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -20,6 +20,7 @@ #include #include +#include #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -229,7 +230,7 @@ /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -240,7 +241,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -20,6 +20,7 @@ #include #include +#include #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -229,7 +230,7 @@ /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -240,7 +241,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -20,6 +20,7 @@ #include #include +#include #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -243,7 +244,7 @@ /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -254,7 +255,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/via/car/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -27,6 +27,7 @@ #include #include +#include #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE @@ -261,7 +262,7 @@ /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -272,7 +273,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/x86/32bit/entry32.inc ============================================================================== --- trunk/src/cpu/x86/32bit/entry32.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/x86/32bit/entry32.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -1,6 +1,7 @@ /* For starting coreboot in protected mode */ #include +#include .code32 @@ -51,7 +52,7 @@ /* Save the BIST value */ movl %eax, %ebp - post_code(0x10) + post_code(POST_ENTER_PROTECTED_MODE) movw $ROM_DATA_SEG, %ax movw %ax, %ds Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/include/console/console.h Mon Apr 11 22:17:22 2011 (r6487) @@ -22,6 +22,7 @@ #include #include +#include #ifndef __PRE_RAM__ void console_tx_byte(unsigned char byte); Added: trunk/src/include/console/post_codes.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/console/post_codes.h Mon Apr 11 22:17:22 2011 (r6487) @@ -0,0 +1,351 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file post_codes.h + * + * This aims to be a central point for POST codes used throughout coreboot. + * All POST codes should be declared here as macros, and post_code() should + * be used with the macros instead of hardcoded values. This allows us to + * quicly reference POST codes when nothing is working + * + * The format for a POST code macro is + * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED + * Lets's keep it at POST_* instead of POST_CODE_* + * + * This file is also included by early assembly files. Only use #define s; + * no function prototypes allowed here + * + * DOCUMENTATION: + * Please document any and all post codes using Doxygen style comments. We + * want to be able to generate a verbose enough documentation that is useful + * during debugging. Failure to do so will result in your patch being rejected + * without any explanation or effort on part of the maintainers. + * + */ +#ifndef POST_CODES_H +#define POST_CODES_H + +/** + * \brief Entry into 'crt0.s'. reset code jumps to here + * + * First instruction that gets executed after the reset vector jumps. + * This indicates that the reset vector points to the correct code segment. + */ +#define POST_RESET_VECTOR_CORRECT 0x01 + +/** + * \brief Entry into protected mode + * + * Preparing to enter protected mode. This is POSTed right before changing to + * protected mode. + */ +#define POST_ENTER_PROTECTED_MODE 0x10 + +/** + * \brief Start copying coreboot to RAM with decompression if compressed + * + * POSTed before ramstage is about to be loaded into memory + */ +#define POST_PREPARE_RAMSTAGE 0x11 + +/** + * \brief Copy/decompression finished; jumping to RAM + * + * This is called after ramstage is loaded in memory, and before + * the code jumps there. This represents the end of romstage. + */ +#define POST_RAMSTAGE_IS_PREPARED 0x12 + + +/** + * \brief Entry into c_start + * + * c_start.S is the first code executing in ramstage. + */ +#define POST_ENTRY_C_START 0x13 + +/** + * \brief Entry into coreboot in hardwaremain (RAM) + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has succesfully loaded and started executing. + */ +#define POST_ENTRY_RAMSTAGE 0x80 + +/** + * \brief Console is initialized + * + * The console is initialized and is ready for usage + */ +#define POST_CONSOLE_READY 0x39 + +/** + * \brief Console boot message succeeded + * + * First console message has been succesfully sent through the console backend + * driver. + */ +#define POST_CONSOLE_BOOT_MSG 0x40 + +/** + * \brief Devices have been enumerated + * + * Bus scan, and device enumeration has completed. + */ +#define POST_DEVICE_ENUMERATION_COMPLETE 0x66 + +/** + * \brief Devices have been configured + * + * Device confgration has completed. + */ +#define POST_DEVICE_CONFIGURATION_COMPLETE 0x88 + +/** + * \brief Devices have been enabled + * + * Devices have been enabled. + */ +#define POST_DEVICES_ENABLED 0x89 + +/** + * \brief Entry into elf boot + * + * This POST code is called right before invoking jmp_to_elf_entry() + * jmp_to_elf_entry() invokes the payload, and should never return + */ +#define POST_ENTER_ELF_BOOT 0xf8 + +/** + * \brief Jumping to payload + * + * Called right before jumping to a payload. If the boot sequence stops with + * this code, chances are the payload freezes. + */ +#define POST_JUMPING_TO_PAYLOAD 0xf3 + +/** + * \brief Not supposed to get here + * + * A function that should not have returned, returned + * + * Check the console output for details. + */ +#define POST_DEAD_CODE 0xee + +/** + * \brief Pre call to hardwaremain() + * + * POSTed right before hardwaremain is called from c_start.S + * TODO: Change this code to a lower number + */ +#define POST_PRE_HARDWAREMAIN 0xfe + +/** + * \brief Elfload fail or die() called + * + * Coreboot was not able to load the payload, no payload was detected + * or die() was called. + * \n + * If this code appears before entering ramstage, then most likely + * ramstage is corrupted, and reflashing of the ROM chip is needed. + * \n + * If this code appears after ramstage, there is a problem with the payload + * If the payload was built out-of-tree, check that it was compiled as + * a coreboot payload + * \n + * Check the console output to see exactly where the failure occured. + */ +#define POST_DIE 0xff + + +/* + * The following POST codes are taken from src/include/cpu/amd/geode_post_code.h + * They overlap with previous codes, and most are not even used + * Some maiboards still require them, but they are deprecated. We want to consolidate + * our own POST code structure with the codes above. + * + * standard AMD post definitions for the AMD Geode + */ +#define POST_Output_Port (0x080) /* port to write post codes to*/ + +#define POST_preSioInit (0x000) +#define POST_clockInit (0x001) +#define POST_CPURegInit (0x002) +#define POST_UNREAL (0x003) +#define POST_CPUMemRegInit (0x004) +#define POST_CPUTest (0x005) +#define POST_memSetup (0x006) +#define POST_memSetUpStack (0x007) +#define POST_memTest (0x008) +#define POST_shadowRom (0x009) +#define POST_memRAMoptimize (0x00A) +#define POST_cacheInit (0x00B) +#define POST_northBridgeInit (0x00C) +#define POST_chipsetInit (0x00D) +#define POST_sioTest (0x00E) +#define POST_pcATjunk (0x00F) + +#define POST_intTable (0x010) +#define POST_memInfo (0x011) +#define POST_romCopy (0x012) +#define POST_PLLCheck (0x013) +#define POST_keyboardInit (0x014) +#define POST_cpuCacheOff (0x015) +#define POST_BDAInit (0x016) +#define POST_pciScan (0x017) +#define POST_optionRomInit (0x018) +#define POST_ResetLimits (0x019) +#define POST_summary_screen (0x01A) +#define POST_Boot (0x01B) +#define POST_SystemPreInit (0x01C) +#define POST_ClearRebootFlag (0x01D) +#define POST_GLIUInit (0x01E) +#define POST_BootFailed (0x01F) + +#define POST_CPU_ID (0x020) +#define POST_COUNTERBROKEN (0x021) +#define POST_DIFF_DIMMS (0x022) +#define POST_WIGGLE_MEM_LINES (0x023) +#define POST_NO_GLIU_DESC (0x024) +#define POST_CPU_LCD_CHECK (0x025) +#define POST_CPU_LCD_PASS (0x026) +#define POST_CPU_LCD_FAIL (0x027) +#define POST_CPU_STEPPING (0x028) +#define POST_CPU_DM_BIST_FAILURE (0x029) +#define POST_CPU_FLAGS (0x02A) +#define POST_CHIPSET_ID (0x02B) +#define POST_CHIPSET_ID_PASS (0x02C) +#define POST_CHIPSET_ID_FAIL (0x02D) +#define POST_CPU_ID_GOOD (0x02E) +#define POST_CPU_ID_FAIL (0x02F) + +/* PCI config*/ +#define P80_PCICFG (0x030) + +/* PCI io*/ +#define P80_PCIIO (0x040) + +/* PCI memory*/ +#define P80_PCIMEM (0x050) + +/* SIO*/ +#define P80_SIO (0x060) + +/* Memory Setp*/ +#define P80_MEM_SETUP (0x070) +#define POST_MEM_SETUP (0x070) +#define ERROR_32BIT_DIMMS (0x071) +#define POST_MEM_SETUP2 (0x072) +#define POST_MEM_SETUP3 (0x073) +#define POST_MEM_SETUP4 (0x074) +#define POST_MEM_SETUP5 (0x075) +#define POST_MEM_ENABLE (0x076) +#define ERROR_NO_DIMMS (0x077) +#define ERROR_DIFF_DIMMS (0x078) +#define ERROR_BAD_LATENCY (0x079) +#define ERROR_SET_PAGE (0x07A) +#define ERROR_DENSITY_DIMM (0x07B) +#define ERROR_UNSUPPORTED_DIMM (0x07C) +#define ERROR_BANK_SET (0x07D) +#define POST_MEM_SETUP_GOOD (0x07E) +#define POST_MEM_SETUP_FAIL (0x07F) + +#define POST_UserPreInit (0x080) +#define POST_UserPostInit (0x081) +#define POST_Equipment_check (0x082) +#define POST_InitNVRAMBX (0x083) +#define POST_NoPIRTable (0x084) +#define POST_ChipsetFingerPrintPass (0x085) +#define POST_ChipsetFingerPrintFail (0x086) +#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) +#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) +#define POST_CPU_FPU_BIST_FAILURE (0x089) +#define POST_CPU_BTB_BIST_FAILURE (0x08A) +#define POST_CPU_EX_BIST_FAILURE (0x08B) +#define POST_Chipset_PI_Test_Fail (0x08C) +#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D) +#define POST_BIT_CLK_Fail (0x08E) + +#define POST_STACK_SETUP (0x090) +#define POST_CPU_PF_BIST_FAILURE (0x091) +#define POST_CPU_L2_BIST_FAILURE (0x092) +#define POST_CPU_GLCP_BIST_FAILURE (0x093) +#define POST_CPU_DF_BIST_FAILURE (0x094) +#define POST_CPU_VG_BIST_FAILURE (0x095) +#define POST_CPU_VIP_BIST_FAILURE (0x096) +#define POST_STACK_SETUP_PASS (0x09E) +#define POST_STACK_SETUP_FAIL (0x09F) + +#define POST_PLL_INIT (0x0A0) +#define POST_PLL_MANUAL (0x0A1) +#define POST_PLL_STRAP (0x0A2) +#define POST_PLL_RESET_FAIL (0x0A3) +#define POST_PLL_PCI_FAIL (0x0A4) +#define POST_PLL_MEM_FAIL (0x0A5) +#define POST_PLL_CPU_VER_FAIL (0x0A6) + +#define POST_MEM_TESTMEM (0x0B0) +#define POST_MEM_TESTMEM1 (0x0B1) +#define POST_MEM_TESTMEM2 (0x0B2) +#define POST_MEM_TESTMEM3 (0x0B3) +#define POST_MEM_TESTMEM4 (0x0B4) +#define POST_MEM_TESTMEM_PASS (0x0BE) +#define POST_MEM_TESTMEM_FAIL (0x0BF) + +#define POST_SECUROM_SECBOOT_START (0x0C0) +#define POST_SECUROM_BOOTSRCSETUP (0x0C1) +#define POST_SECUROM_REMAP_FAIL (0x0C2) +#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) +#define POST_SECUROM_DCACHESETUP (0x0C4) +#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) +#define POST_SECUROM_ICACHESETUP (0x0C6) +#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) +#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) +#define POST_SECUROM_PLATFORMSETUP (0x0C9) +#define POST_SECUROM_SIGCHECKBIOS (0x0CA) +#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) +#define POST_SECUROM_PASS (0x0CC) +#define POST_SECUROM_FAIL (0x0CD) + +#define POST_RCONFInitError (0x0CE) +#define POST_CacheInitError (0x0CF) + +#define POST_ROM_PREUNCOMPRESS (0x0D0) +#define POST_ROM_UNCOMPRESS (0x0D1) +#define POST_ROM_SMM_INIT (0x0D2) +#define POST_ROM_VID_BIOS (0x0D3) +#define POST_ROM_LCDINIT (0x0D4) +#define POST_ROM_SPLASH (0x0D5) +#define POST_ROM_HDDINIT (0x0D6) +#define POST_ROM_SYS_INIT (0x0D7) +#define POST_ROM_DMM_INIT (0x0D8) +#define POST_ROM_TVINIT (0x0D9) +#define POST_ROM_POSTUNCOMPRESS (0x0DE) + +#define P80_CHIPSET_INIT (0x0E0) +#define POST_PreChipsetInit (0x0E1) +#define POST_LateChipsetInit (0x0E2) +#define POST_NORTHB_INIT (0x0E8) + +#define POST_INTR_SEG_JUMP (0x0F0) + +#endif /* THE_ALMIGHTY_POST_CODES_H */ Modified: trunk/src/include/cpu/amd/geode_post_code.h ============================================================================== --- trunk/src/include/cpu/amd/geode_post_code.h Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/include/cpu/amd/geode_post_code.h Mon Apr 11 22:17:22 2011 (r6487) @@ -1,182 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* standard AMD post definitions -- might as well use them. */ -#define POST_Output_Port (0x080) /* port to write post codes to*/ - -#define POST_preSioInit (0x000) -#define POST_clockInit (0x001) -#define POST_CPURegInit (0x002) -#define POST_UNREAL (0x003) -#define POST_CPUMemRegInit (0x004) -#define POST_CPUTest (0x005) -#define POST_memSetup (0x006) -#define POST_memSetUpStack (0x007) -#define POST_memTest (0x008) -#define POST_shadowRom (0x009) -#define POST_memRAMoptimize (0x00A) -#define POST_cacheInit (0x00B) -#define POST_northBridgeInit (0x00C) -#define POST_chipsetInit (0x00D) -#define POST_sioTest (0x00E) -#define POST_pcATjunk (0x00F) - -#define POST_intTable (0x010) -#define POST_memInfo (0x011) -#define POST_romCopy (0x012) -#define POST_PLLCheck (0x013) -#define POST_keyboardInit (0x014) -#define POST_cpuCacheOff (0x015) -#define POST_BDAInit (0x016) -#define POST_pciScan (0x017) -#define POST_optionRomInit (0x018) -#define POST_ResetLimits (0x019) -#define POST_summary_screen (0x01A) -#define POST_Boot (0x01B) -#define POST_SystemPreInit (0x01C) -#define POST_ClearRebootFlag (0x01D) -#define POST_GLIUInit (0x01E) -#define POST_BootFailed (0x01F) - -#define POST_CPU_ID (0x020) -#define POST_COUNTERBROKEN (0x021) -#define POST_DIFF_DIMMS (0x022) -#define POST_WIGGLE_MEM_LINES (0x023) -#define POST_NO_GLIU_DESC (0x024) -#define POST_CPU_LCD_CHECK (0x025) -#define POST_CPU_LCD_PASS (0x026) -#define POST_CPU_LCD_FAIL (0x027) -#define POST_CPU_STEPPING (0x028) -#define POST_CPU_DM_BIST_FAILURE (0x029) -#define POST_CPU_FLAGS (0x02A) -#define POST_CHIPSET_ID (0x02B) -#define POST_CHIPSET_ID_PASS (0x02C) -#define POST_CHIPSET_ID_FAIL (0x02D) -#define POST_CPU_ID_GOOD (0x02E) -#define POST_CPU_ID_FAIL (0x02F) - -/* PCI config*/ -#define P80_PCICFG (0x030) - -/* PCI io*/ -#define P80_PCIIO (0x040) - -/* PCI memory*/ -#define P80_PCIMEM (0x050) - -/* SIO*/ -#define P80_SIO (0x060) - -/* Memory Setp*/ -#define P80_MEM_SETUP (0x070) -#define POST_MEM_SETUP (0x070) -#define ERROR_32BIT_DIMMS (0x071) -#define POST_MEM_SETUP2 (0x072) -#define POST_MEM_SETUP3 (0x073) -#define POST_MEM_SETUP4 (0x074) -#define POST_MEM_SETUP5 (0x075) -#define POST_MEM_ENABLE (0x076) -#define ERROR_NO_DIMMS (0x077) -#define ERROR_DIFF_DIMMS (0x078) -#define ERROR_BAD_LATENCY (0x079) -#define ERROR_SET_PAGE (0x07A) -#define ERROR_DENSITY_DIMM (0x07B) -#define ERROR_UNSUPPORTED_DIMM (0x07C) -#define ERROR_BANK_SET (0x07D) -#define POST_MEM_SETUP_GOOD (0x07E) -#define POST_MEM_SETUP_FAIL (0x07F) - -#define POST_UserPreInit (0x080) -#define POST_UserPostInit (0x081) -#define POST_Equipment_check (0x082) -#define POST_InitNVRAMBX (0x083) -#define POST_NoPIRTable (0x084) -#define POST_ChipsetFingerPrintPass (0x085) -#define POST_ChipsetFingerPrintFail (0x086) -#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) -#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) -#define POST_CPU_FPU_BIST_FAILURE (0x089) -#define POST_CPU_BTB_BIST_FAILURE (0x08A) -#define POST_CPU_EX_BIST_FAILURE (0x08B) -#define POST_Chipset_PI_Test_Fail (0x08C) -#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D) -#define POST_BIT_CLK_Fail (0x08E) - -#define POST_STACK_SETUP (0x090) -#define POST_CPU_PF_BIST_FAILURE (0x091) -#define POST_CPU_L2_BIST_FAILURE (0x092) -#define POST_CPU_GLCP_BIST_FAILURE (0x093) -#define POST_CPU_DF_BIST_FAILURE (0x094) -#define POST_CPU_VG_BIST_FAILURE (0x095) -#define POST_CPU_VIP_BIST_FAILURE (0x096) -#define POST_STACK_SETUP_PASS (0x09E) -#define POST_STACK_SETUP_FAIL (0x09F) - -#define POST_PLL_INIT (0x0A0) -#define POST_PLL_MANUAL (0x0A1) -#define POST_PLL_STRAP (0x0A2) -#define POST_PLL_RESET_FAIL (0x0A3) -#define POST_PLL_PCI_FAIL (0x0A4) -#define POST_PLL_MEM_FAIL (0x0A5) -#define POST_PLL_CPU_VER_FAIL (0x0A6) - -#define POST_MEM_TESTMEM (0x0B0) -#define POST_MEM_TESTMEM1 (0x0B1) -#define POST_MEM_TESTMEM2 (0x0B2) -#define POST_MEM_TESTMEM3 (0x0B3) -#define POST_MEM_TESTMEM4 (0x0B4) -#define POST_MEM_TESTMEM_PASS (0x0BE) -#define POST_MEM_TESTMEM_FAIL (0x0BF) - -#define POST_SECUROM_SECBOOT_START (0x0C0) -#define POST_SECUROM_BOOTSRCSETUP (0x0C1) -#define POST_SECUROM_REMAP_FAIL (0x0C2) -#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) -#define POST_SECUROM_DCACHESETUP (0x0C4) -#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) -#define POST_SECUROM_ICACHESETUP (0x0C6) -#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) -#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) -#define POST_SECUROM_PLATFORMSETUP (0x0C9) -#define POST_SECUROM_SIGCHECKBIOS (0x0CA) -#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) -#define POST_SECUROM_PASS (0x0CC) -#define POST_SECUROM_FAIL (0x0CD) - -#define POST_RCONFInitError (0x0CE) -#define POST_CacheInitError (0x0CF) - -#define POST_ROM_PREUNCOMPRESS (0x0D0) -#define POST_ROM_UNCOMPRESS (0x0D1) -#define POST_ROM_SMM_INIT (0x0D2) -#define POST_ROM_VID_BIOS (0x0D3) -#define POST_ROM_LCDINIT (0x0D4) -#define POST_ROM_SPLASH (0x0D5) -#define POST_ROM_HDDINIT (0x0D6) -#define POST_ROM_SYS_INIT (0x0D7) -#define POST_ROM_DMM_INIT (0x0D8) -#define POST_ROM_TVINIT (0x0D9) -#define POST_ROM_POSTUNCOMPRESS (0x0DE) - -#define P80_CHIPSET_INIT (0x0E0) -#define POST_PreChipsetInit (0x0E1) -#define POST_LateChipsetInit (0x0E2) -#define POST_NORTHB_INIT (0x0E8) - -#define POST_INTR_SEG_JUMP (0x0F0) Modified: trunk/src/include/cpu/x86/post_code.h ============================================================================== --- trunk/src/include/cpu/x86/post_code.h Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/include/cpu/x86/post_code.h Mon Apr 11 22:17:22 2011 (r6487) @@ -1,4 +1,5 @@ +#include #define post_code(value) \ movb $value, %al; \ Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/amd/db800/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include #include "southbridge/amd/cs5536/early_smbus.c" @@ -56,7 +55,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/amd/norwich/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include #include "southbridge/amd/cs5536/early_smbus.c" @@ -53,7 +52,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/amd/rumba/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -8,7 +8,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -29,7 +29,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include "spd_table.h" #include @@ -68,7 +67,6 @@ void main(unsigned long bist) { - post_code(0x01); msr_t msr; static const struct mem_controller memctrl[] = { Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -9,7 +9,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include #include "southbridge/amd/cs5536/early_smbus.c" @@ -37,7 +36,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl [] = { {.channel0 = {DIMM0, DIMM1}} @@ -79,7 +77,6 @@ We use method 1 on Norwich. */ post_code(0x02); - print_err("POST 02\n"); __asm__("wbinvd\n"); print_err("Past wbinvd\n"); /* we are finding the return does not work on this board. Explicitly call the label that is Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include #include "southbridge/amd/cs5536/early_smbus.c" @@ -60,7 +59,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -9,7 +9,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5535/cs5535.h" #include "southbridge/amd/cs5535/early_smbus.c" #include "southbridge/amd/cs5535/early_setup.c" Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/hurricane-lx/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -31,7 +31,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include #include "southbridge/amd/cs5536/early_smbus.c" @@ -118,7 +117,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/literunner-lx/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/lippert/literunner-lx/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -32,7 +32,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" @@ -161,7 +160,6 @@ void main(unsigned long bist) { int err; - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -31,7 +31,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include #include "southbridge/amd/cs5536/early_smbus.c" @@ -93,7 +92,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -32,7 +32,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" @@ -158,7 +157,6 @@ void main(unsigned long bist) { int err; - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -30,7 +30,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -118,8 +117,6 @@ {.channel0 = {DIMM0}}, }; - post_code(0x01); - SystemPreInit(); msr_init(); Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/pcengines/alix2d/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -30,7 +30,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -142,8 +141,6 @@ {.channel0 = {DIMM0}}, }; - post_code(0x01); - SystemPreInit(); msr_init(); Modified: trunk/src/mainboard/traverse/geos/romstage.c ============================================================================== --- trunk/src/mainboard/traverse/geos/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/traverse/geos/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -29,7 +29,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include #include "southbridge/amd/cs5536/early_smbus.c" @@ -54,8 +53,6 @@ void main(unsigned long bist) { - post_code(0x01); - static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} }; Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/winent/pl6064/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -30,7 +30,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include "southbridge/amd/cs5536/cs5536.h" #include #include "southbridge/amd/cs5536/early_smbus.c" @@ -58,7 +57,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/wyse/s50/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -29,7 +29,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include -#include #include #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" Modified: trunk/src/northbridge/amd/gx1/raminit.c ============================================================================== --- trunk/src/northbridge/amd/gx1/raminit.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/northbridge/amd/gx1/raminit.c Mon Apr 11 22:17:22 2011 (r6487) @@ -46,12 +46,12 @@ { unsigned int tval, i; - outb(0x71, 0x80); + post_code(0x71); tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1); tval |= RFSHTST; for(i=0; i>NUM_REFRESH; i++) setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval); - outb(0x72, 0x80); + post_code(0x72); } @@ -59,7 +59,7 @@ { unsigned int tval, i; - outb(0x73, 0x80); + post_code(0x73); /* start SDCLCK's */ tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1); @@ -101,7 +101,7 @@ for(i=0; i<2000; i++) outb(0, 0xed); - outb(0x74, 0x80); + post_code(0x74); } static unsigned int size_dimm(int dimm_shift) @@ -321,7 +321,7 @@ unsigned int mem_config = 0x00700070; print_debug("Setting up default parameters for memory\n"); - outb(0x70, 0x80); + post_code(0x70); setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */ setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */ @@ -350,5 +350,5 @@ setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config); enable_dimm(); - outb(0x7e, 0x80); + post_code(0x7e); } Modified: trunk/src/northbridge/via/cx700/early_serial.c ============================================================================== --- trunk/src/northbridge/via/cx700/early_serial.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/northbridge/via/cx700/early_serial.c Mon Apr 11 22:17:22 2011 (r6487) @@ -47,7 +47,7 @@ static void enable_cx700_serial(void) { - outb(6, 0x80); + post_code(0x06); // WTH? outb(0x03, 0x22); @@ -98,5 +98,5 @@ // should be done. Dump a char for fun. cx700_writesiobyte(0x3f8, 48); - outb(7, 0x80); + post_code(0x07); } Modified: trunk/src/northbridge/via/vx800/early_serial.c ============================================================================== --- trunk/src/northbridge/via/vx800/early_serial.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/northbridge/via/vx800/early_serial.c Mon Apr 11 22:17:22 2011 (r6487) @@ -55,7 +55,7 @@ void enable_vx800_serial(void) { - outb(6, 0x80); + post_code(0x06); outb(0x03, 0x22); //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e); @@ -97,5 +97,5 @@ vx800_writesiobyte(0x3f9, 0xf); // should be done. Dump a char for fun. vx800_writesiobyte(0x3f8, 48); - outb(7, 0x80); + post_code(0x07); } Modified: trunk/src/southbridge/amd/cs5535/chipsetinit.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/chipsetinit.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/southbridge/amd/cs5535/chipsetinit.c Mon Apr 11 22:17:22 2011 (r6487) @@ -10,7 +10,6 @@ #include "chip.h" #include "northbridge/amd/gx2/northbridge.h" #include -#include #include #include #include "southbridge/amd/cs5535/cs5535.h" @@ -277,7 +276,7 @@ return; } - outb( P80_CHIPSET_INIT, 0x80); + post_code(P80_CHIPSET_INIT); ChipsetGeodeLinkInit(); #ifdef UNUSED_CODE Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Mon Apr 11 22:17:22 2011 (r6487) @@ -30,7 +30,6 @@ #include #include #include -#include #include #include "chip.h" #include "cs5536.h" Modified: trunk/src/southbridge/via/vt8231/early_serial.c ============================================================================== --- trunk/src/southbridge/via/vt8231/early_serial.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/southbridge/via/vt8231/early_serial.c Mon Apr 11 22:17:22 2011 (r6487) @@ -1,3 +1,4 @@ +#include /* * Enable the serial evices on the VIA */ @@ -33,11 +34,11 @@ { uint8_t c; device_t dev; - outb(6, 0x80); + post_code(0x06); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); if (dev == PCI_DEV_INVALID) { - outb(7, 0x80); + post_code(0x07); die("Serial controller not found\n"); } @@ -47,7 +48,7 @@ c = pci_read_config8(dev, 0x50); c |= 6; pci_write_config8(dev, 0x50, c); - outb(2, 0x80); + post_code(0x02); // now go ahead and set up com1. // set address vt8231_writesuper(0xf4, 0xfe); From joseph.czerniak at gmail.com Mon Apr 11 22:22:27 2011 From: joseph.czerniak at gmail.com (Joesph Czerniak) Date: Mon, 11 Apr 2011 16:22:27 -0400 Subject: [coreboot] Coreboot on Atom N550 Message-ID: Hi, I bought the HP 5103 netbook. I was wondering if coreboot would run on it. It has the following specs: Here are the quick specs (the more detailed specs are at the bottom): CPU: Intel Atom N550 with an integrated northbridge Southbridge: Intel N10/ICH 7 SuperIO: SMSC FDC37B72x So on your motherboard page, the closest motherboard I could find is the Intel D945GCLF. So I found the Kconfig file and thought a good way to start would be to modify it. It has: select CPU_INTEL_SOCKET_441 select NORTHBRIDGE_INTEL_I945GC select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_SMSC_LPC47M15X Should I start by modifying these four lines? Then compile and flash? The socket for the N550 is the Intel Socket 437. Does coreboot support that? The other question I had was about the northbridge. Since its integrated into the CPU, should I remove that line? Or can I keep it in? Thanks for your help! Joseph Per the FAQ, here's lspci -tvnn: -[0000:00]-+-00.0 Intel Corporation N10 Family DMI Bridge [8086:a010] +-02.0 Intel Corporation N10 Family Integrated Graphics Controller [8086:a011] +-02.1 Intel Corporation N10 Family Integrated Graphics Controller [8086:a012] +-1b.0 Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8] +-1c.0-[0000:01]----00.0 Broadcom Corporation Device [14e4:4727] +-1c.3-[0000:02]----00.0 Marvell Technology Group Ltd. Device [11ab:4381] +-1d.0 Intel Corporation N10/ICH7 Family USB UHCI Controller #1 [8086:27c8] +-1d.1 Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9] +-1d.2 Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca] +-1d.3 Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb] +-1d.7 Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc] +-1e.0-[0000:03]-- +-1f.0 Intel Corporation NM10 Family LPC Controller [8086:27bc] \-1f.2 Intel Corporation N10/ICH7 Family SATA AHCI Controller [8086:27c1] Here's superiotool -dV: Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Found SMSC FDC37B72x (id=0x4c, rev=0x01) at 0x2e Register dump: idx 03 20 21 22 23 24 26 27 28 2b 2c 2d 2e 2f val 00 4c 01 10 00 04 2e 00 00 00 00 00 00 00 def 03 4c 00 00 00 04 MM MM 00 NA NA NA NA NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 00 00 00 00 00 00 00 00 00 00 def 00 03 f0 06 02 0e 00 ff 00 00 LDN 0x03 (Parallel port) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 00 00 00 def 00 00 00 00 04 3c 00 LDN 0x04 (COM1) idx 30 60 61 70 f0 val 01 02 80 06 00 def 00 00 00 00 00 LDN 0x05 (COM2) idx 30 60 61 70 f0 f1 f2 val 00 00 00 00 00 00 00 def NA 00 00 00 00 02 03 LDN 0x07 (Keyboard) idx 30 70 72 f0 val 01 01 0c 00 def 00 00 00 00 LDN 0x08 (Aux I/O) idx 30 b0 b1 b2 b3 b8 c0 c1 c2 c3 c4 c5 c6 c8 ca cb cc d0 d1 d2 d3 d4 d5 d6 d7 e0 e1 e2 e3 e4 e5 e6 e7 ef f0 f1 f2 f3 f4 f6 f9 fa val 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 def 00 NA NA NA NA NA 00 01 NA NA NA 00 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 00 00 00 MM NA NA NA LDN 0x0a (ACPI) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 00 00 NA NA Here's flashrom -V: flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Mini 5103" DMI string system-version: " " DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "1608" DMI string baseboard-version: "KBC Version 92.04" DMI string chassis-type: "Notebook" Laptop detected via DMI ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. ======================================================================== Found chipset "Intel NM10", enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3020 0x00: 0x8004 (SPIS) 0x02: 0x4020 (SPIC) 0x04: 0x00000000 (SPIA) 0x08: 0x00412500 (SPID0) 0x0c: 0x00000000 (SPID0+4) 0x10: 0x00000000 (SPID1) 0x14: 0x00000000 (SPID1+4) 0x18: 0x00000000 (SPID2) 0x1c: 0x00000000 (SPID2+4) 0x20: 0x00000000 (SPID3) 0x24: 0x00000000 (SPID3+4) 0x28: 0x00000000 (SPID4) 0x2c: 0x00000000 (SPID4+4) 0x30: 0x00000000 (SPID5) 0x34: 0x00000000 (SPID5+4) 0x38: 0x00000000 (SPID6) 0x3c: 0x00000000 (SPID6+4) 0x40: 0x00000000 (SPID7) 0x44: 0x00000000 (SPID7+4) 0x50: 0x00000000 (BBAR) 0x54: 0x0606 (PREOP) 0x56: 0x7f48 (OPTYPE) 0x58: 0x0405039f (OPMENU) 0x5c: 0x0102d820 (OPMENU+4) 0x60: 0x80ff01c0 (PBR0) 0x64: 0x00000000 (PBR1) 0x68: 0x00000000 (PBR2) 0x6c: 0x00000000 (PBR3) WARNING: SPI Configuration Lockdown activated. Generating OPCODES... done SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: SPI. Calibrating delay loop... 738M loops per second, 100 myus = 211 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF041A, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF081, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF161, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF321, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF321A, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF641, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25F512B, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25FS010, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25FS040, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF041, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF081A, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF161, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF161A, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26F004, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT29C512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB011D, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB021D, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB041D, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB081D, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB161D, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB321C, 4224 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB321D, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB642D, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: RDID returned 0xbf 0x25 0x41 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L40PU, 512 KB: RDID returned 0xbf 0x25 0x41 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A29002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B05T, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B10, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B10T, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B20, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B20T, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B40, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B40T, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B80, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B80T, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B16T, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B32, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B32T, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B64, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B64T, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25D16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F05, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F10, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F20, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F40, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F80, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F32, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN29F010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L1005, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L2005, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L4005, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L1605, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L1635D, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L3205, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L3235D, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L6405, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L12805, 16384 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE20, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE40, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE80, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV010, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV016B, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV020, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV040, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV080B, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV512, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for Sanyo LF25FW203A, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Spansion S25FL016A, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST25VF016B, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Chip status register is 00 Chip status register: Block Protect Write Disable (BPL) is not set Chip status register: Auto Address Increment Programming (AAI) is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Resulting block protection : none Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000. Probing for SST SST25VF032B, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST25VF040.REMS, 512 KB: Invalid OPCODE 0x90 Probing for SST SST25VF040B, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST25VF040B.REMS, 512 KB: Invalid OPCODE 0x90 Probing for SST SST25VF080B, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST28SF040A, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P05.RES, 64 KB: RDID returned 0xbf 0x25 0x41. Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P10.RES, 128 KB: RDID returned 0xbf 0x25 0x41. Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P40, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P40-old, 512 KB: RDID returned 0xbf 0x25 0x41. Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P32, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P64, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P128, 16384 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M29F002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x20, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x40, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x80, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x32, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x64, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W29C011, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for Sanyo unknown Sanyo SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for Generic unknown SPI chip (RDID), 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for Generic unknown SPI chip (REMS), 0 KB: Not mapping flash chip, zero size at 0x00000000. Invalid OPCODE 0x90 Not unmapping zero size at (nil) === This flash part has status UNTESTED for operations: ERASE Please email a report to flashrom at flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.reinauer at coreboot.org Tue Apr 12 02:48:21 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Tue, 12 Apr 2011 02:48:21 +0200 Subject: [coreboot] Coreboot on Atom N550 In-Reply-To: References: Message-ID: <20110412004820.GA18842@coreboot.org> * Joesph Czerniak [110411 22:22]: > Hi, > I bought the HP 5103 netbook. I was wondering if coreboot would run on it. It > has the following specs: > > Here are the quick specs (the more detailed specs are at the bottom): > > CPU: Intel Atom N550 with an integrated northbridge > Southbridge: Intel N10/ICH 7 > SuperIO: SMSC FDC37B72x > > So on your motherboard page, the closest motherboard I could find is the Intel > D945GCLF. So I found the Kconfig file and thought a good way to start would be > to modify it. It has: > select CPU_INTEL_SOCKET_441 > select NORTHBRIDGE_INTEL_I945GC > select SOUTHBRIDGE_INTEL_I82801GX > select SUPERIO_SMSC_LPC47M15X > > Should I start by modifying these four lines? Then compile and flash? > > The socket for the N550 is the Intel Socket 437. Does coreboot support that? > > The other question I had was about the northbridge. Since its integrated into > the CPU, should I remove that line? Or can I keep it in? The N10/NM10 northbridge is unsupported by coreboot as of now. You will have to write support for that in order to get coreboot working on your system. Stefan From svn at coreboot.org Tue Apr 12 03:12:47 2011 From: svn at coreboot.org (repository service) Date: Tue, 12 Apr 2011 03:12:47 +0200 Subject: [coreboot] [commit] r6488 - trunk/src/southbridge/amd/rs780 Message-ID: Author: kerry Date: Tue Apr 12 03:12:46 2011 New Revision: 6488 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6488 Log: Use TOM2 for highest sysmem setting for northbound memory routing (DMA). This fixes 4GB memory issues. Signed-off-by: Marc Jones Acked-by: Kerry she Modified: trunk/src/southbridge/amd/rs780/gfx.c Modified: trunk/src/southbridge/amd/rs780/gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/gfx.c Mon Apr 11 22:17:22 2011 (r6487) +++ trunk/src/southbridge/amd/rs780/gfx.c Tue Apr 12 03:12:46 2011 (r6488) @@ -661,13 +661,15 @@ printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); - sysmem = rdmsr(0xc001001a); - printk(BIOS_DEBUG, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo); - /* The system top memory in 780. */ + sysmem = rdmsr(0xc001001a); + printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo); pci_write_config32(nb_dev, 0x90, sysmem.lo); - htiu_write_index(nb_dev, 0x30, 0); - htiu_write_index(nb_dev, 0x31, 0); + + sysmem = rdmsr(0xc001001D); + printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo); + htiu_write_index(nb_dev, 0x31, sysmem.hi); + htiu_write_index(nb_dev, 0x30, sysmem.lo | 1); /* Disable external GFX and enable internal GFX. */ l_dword = pci_read_config32(nb_dev, 0x8c); From Kerry.She at amd.com Tue Apr 12 03:09:18 2011 From: Kerry.She at amd.com (She, Kerry) Date: Tue, 12 Apr 2011 09:09:18 +0800 Subject: [coreboot] [patch] rs780 4GB memory issues In-Reply-To: References: <4D96454D.9070006@assembler.cz> Message-ID: Tested on the RS785E platform with Linux thanks Acked-by: Kerry she -- Best Regards Kerry -----Original Message----- From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Marc Jones Sent: Saturday, April 02, 2011 5:47 AM To: Rudolf Marek Cc: coreboot at coreboot.org Subject: Re: [coreboot] [patch] rs780 4GB memory issues On Fri, Apr 1, 2011 at 3:36 PM, Rudolf Marek wrote: > Hi, > > How the patch actually works? It looks like it only prints TOM2 not > using it. Argh, .. and half the change doesn't help... *sigh* Thanks for catching that! Marc -- http://se-eng.com From corey.osgood at gmail.com Tue Apr 12 04:27:37 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Mon, 11 Apr 2011 22:27:37 -0400 Subject: [coreboot] Coreboot on Atom N550 In-Reply-To: <20110412004820.GA18842@coreboot.org> References: <20110412004820.GA18842@coreboot.org> Message-ID: On Mon, Apr 11, 2011 at 8:48 PM, Stefan Reinauer wrote: > * Joesph Czerniak [110411 22:22]: >> Hi, >> I bought the HP 5103 netbook. I was wondering if coreboot would run on it. It >> has the following specs: >> >> Here are the quick specs (the more detailed specs are at the bottom): >> >> CPU: Intel Atom N550 with an integrated northbridge >> Southbridge: Intel N10/ICH 7 >> SuperIO: SMSC FDC37B72x >> >> So on your motherboard page, the closest motherboard I could find is the Intel >> D945GCLF. So I found the Kconfig file and thought a good way to start would be >> to modify it. It has: >> ? ? select CPU_INTEL_SOCKET_441 >> ? ? select NORTHBRIDGE_INTEL_I945GC >> ? ? select SOUTHBRIDGE_INTEL_I82801GX >> ? ? select SUPERIO_SMSC_LPC47M15X >> >> Should I start by modifying these four lines? Then compile and flash? >> >> The socket for the N550 is the Intel Socket 437. Does coreboot support that? >> >> The other question I had was about the northbridge. Since its integrated into >> the CPU, should I remove that line? Or can I keep it in? > > The N10/NM10 northbridge is unsupported by coreboot as of now. You will > have to write support for that in order to get coreboot working on your > system. > > Stefan The NM10 isn't the northbridge, it's the southbridge, and all it is is an ICH7 with one different PCI ID. The northbridge is integrated into the Atom CPU, and it's VERY different from the i945 (don't bother trying it, it won't work). Although public datasheets are available, the Bios Porting Guides for the Atom N500 and D400/500 series are covered under Intel NDA. -Corey From mlf.conv at gmail.com Tue Apr 12 14:26:58 2011 From: mlf.conv at gmail.com (Marek) Date: Tue, 12 Apr 2011 14:26:58 +0200 Subject: [coreboot] Gigabyte GA AMD E350N USB3 Board In-Reply-To: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> References: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> Message-ID: <7CA00DD3-FA50-4983-9E35-537CB9B3182B@gmail.com> Hi, I recently got a response from official GA support team and the chips used on this board are: MX25L1606EM2I-12G iTE8720 Marek On 1.4.2011, at 21:37, Marek wrote: > Hi, > > with regards to recent AMD patches, I'd like to ask whether it would be possible to install coreboot on Gigabyte GA AMD E350N USB3 board (AMD E350, chipset FCH A50 Hudson M1, iTE 8720). > > thanks > > Marek -------------- next part -------------- An HTML attachment was scrubbed... URL: From peter at stuge.se Tue Apr 12 15:08:05 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 12 Apr 2011 15:08:05 +0200 Subject: [coreboot] Gigabyte GA AMD E350N USB3 Board In-Reply-To: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> References: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> Message-ID: <20110412130805.12455.qmail@stuge.se> Marek wrote: > with regards to recent AMD patches, Note that the patches did not include support for your mainboard. > I'd like to ask whether it would be possible to install coreboot on > Gigabyte GA AMD E350N USB3 board > (AMD E350, chipset FCH A50 Hudson M1, iTE 8720). The answer is, as always, no it will not work unless you make it work. The final piece of the puzzle, mainboard support, is still missing, but all the other 4999 pieces have been put in place for you by AMD and the rest of the coreboot community. //Peter From mlf.conv at gmail.com Tue Apr 12 16:07:50 2011 From: mlf.conv at gmail.com (Marek) Date: Tue, 12 Apr 2011 16:07:50 +0200 Subject: [coreboot] Gigabyte GA AMD E350N USB3 Board In-Reply-To: <20110412130805.12455.qmail@stuge.se> References: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> <20110412130805.12455.qmail@stuge.se> Message-ID: Hi Peter, On 12.4.2011, at 15:08, Peter Stuge wrote: > Marek wrote: >> with regards to recent AMD patches, > > Note that the patches did not include support for your mainboard. > > >> I'd like to ask whether it would be possible to install coreboot on >> Gigabyte GA AMD E350N USB3 board >> (AMD E350, chipset FCH A50 Hudson M1, iTE 8720). > > The answer is, as always, no it will not work unless you make it work. > > The final piece of the puzzle, mainboard support, is still missing, > but all the other 4999 pieces have been put in place for you by AMD > and the rest of the coreboot community. thanks for your answer, I'm fully aware of the situation, my question was more directed to people (if there are any) who own that MB, perhaps work on coreboot support, or have considered it and abanonded it in the initial phase or even made progress but were unable to continue due to various circumstances. No answer most likely means that there isn't anyone who owns this board so far, so I just pushed all information I could find out without buying that board in case someone wants to buy one and add coreboot support for it. Marek > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From svn at coreboot.org Tue Apr 12 20:18:13 2011 From: svn at coreboot.org (repository service) Date: Tue, 12 Apr 2011 20:18:13 +0200 Subject: [coreboot] [commit] r6489 - trunk/src/superio/nsc/pc87384 Message-ID: Author: svens Date: Tue Apr 12 20:18:12 2011 New Revision: 6489 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6489 Log: PC87384: add GPIO defines Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/superio/nsc/pc87384/pc87384.h Modified: trunk/src/superio/nsc/pc87384/pc87384.h ============================================================================== --- trunk/src/superio/nsc/pc87384/pc87384.h Tue Apr 12 03:12:46 2011 (r6488) +++ trunk/src/superio/nsc/pc87384/pc87384.h Tue Apr 12 20:18:12 2011 (r6489) @@ -25,4 +25,15 @@ #define PC87384_SP2 0x02 #define PC87384_SP1 0x03 #define PC87384_GPIO 0x07 + +#define PC87384_GPIO_PIN_OE 0x01 +#define PC87384_GPIO_PIN_TYPE_PUSH_PULL 0x02 +#define PC87384_GPIO_PIN_PULLUP 0x04 +#define PC87384_GPIO_PIN_LOCK 0x08 +#define PC87384_GPIO_PIN_TRIG_LEVEL 0x10 +#define PC87384_GPIO_PIN_TRIG_LOW 0x20 +#define PC87384_GPIO_PIN_DEBOUNCE 0x40 + +#define PC87384_GPIO_PIN_TRIGGERS_IRQ 0x01 + #endif From svn at coreboot.org Tue Apr 12 20:18:24 2011 From: svn at coreboot.org (repository service) Date: Tue, 12 Apr 2011 20:18:24 +0200 Subject: [coreboot] [commit] r6490 - trunk/src/ec/lenovo/h8 Message-ID: Author: svens Date: Tue Apr 12 20:18:24 2011 New Revision: 6490 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6490 Log: Lenovo H8 EC: Set fancontrol to Automatic management My Notebook gets far to hot without fan, so just enable automatic fan control by default. Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/ec/lenovo/h8/h8.c trunk/src/ec/lenovo/h8/h8.h Modified: trunk/src/ec/lenovo/h8/h8.c ============================================================================== --- trunk/src/ec/lenovo/h8/h8.c Tue Apr 12 20:18:12 2011 (r6489) +++ trunk/src/ec/lenovo/h8/h8.c Tue Apr 12 20:18:24 2011 (r6490) @@ -118,6 +118,7 @@ ec_write(0x1e, conf->evente_enable); ec_write(0x1f, conf->eventf_enable); + ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); h8_wlan_enable(conf->wlan_enable); h8_trackpoint_enable(conf->trackpoint_enable); Modified: trunk/src/ec/lenovo/h8/h8.h ============================================================================== --- trunk/src/ec/lenovo/h8/h8.h Tue Apr 12 20:18:12 2011 (r6489) +++ trunk/src/ec/lenovo/h8/h8.h Tue Apr 12 20:18:24 2011 (r6490) @@ -67,6 +67,8 @@ #define H8_LED_CONTROL_DOCK_LED1 0x08 #define H8_LED_CONTROL_DOCK_LED2 0x09 +#define H8_FAN_CONTROL 0x2f +#define H8_FAN_CONTROL_AUTO 0x80 /* Embedded controller events */ #define H8_EVENT_FN_F1 0x10 #define H8_EVENT_FN_F2 0x11 From jakllsch at kollasch.net Tue Apr 12 23:06:42 2011 From: jakllsch at kollasch.net (Jonathan A. Kollasch) Date: Tue, 12 Apr 2011 21:06:42 +0000 Subject: [coreboot] SB850 SERR# routing (almost off-topic) Message-ID: <20110412210642.GJ23059@tarantulon.kollasch.net> Hi, My AM3/870/sb850 board doesn't seem to route SERR# on the conventional PCI bus to a NMI. I've adjusted the registers at port 61h and 70h, and ensured that the Core 0 LAPIC LINT1 is not masked and is routed to NMI. I've also enabled SERR handling in various parts of the chipset. I managed to get this to work on a 785/sb7xx board after adjusting port C14h, but that's not where I need to trigger a NMI. The sb850 board does not appear to have a decoded register at port C14h I don't know if this is because it's been hidden, or because it's moved somewhere else or where it may have moved to. Could anyone tell how I could make this work on the SB850 board? Jonathan Kollasch From stefan.reinauer at coreboot.org Tue Apr 12 23:10:12 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Tue, 12 Apr 2011 23:10:12 +0200 Subject: [coreboot] romcc segfault Message-ID: <20110412211012.GA4336@coreboot.org> Hi, just a heads up, I got romcc to segfault with the following sample program: --------------------- 8< snip 8< -------------------------------------- typedef unsigned int u32; #define DEFAULT_RCBA 0xfed1c000 #define GCS 0x3410 #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) void test(void) { RCBA32(GCS) &= (~0x04); } --------------------- >8 snip >8 -------------------------------------- I tried to simplify this further and this construct is still crashing romcc: --------------------- 8< snip 8< -------------------------------------- u32 *gcs = (u32 *)(DEFAULT_RCBA + GCS); *gcs &= (~0x04); --------------------- >8 snip >8 -------------------------------------- while this one is working --------------------- 8< snip 8< -------------------------------------- u32 *gcs = (u32 *)(DEFAULT_RCBA + GCS); u32 temp = *gcs; temp &= (~0x04); *gcs = temp; --------------------- >8 snip >8 -------------------------------------- Is that a construct that we just can't/don't want to support in romcc? Or is there a chance we can fix that? Stefan gdb back trace: $ gdb build/util/romcc/romcc GNU gdb (GDB) 7.2-gg8 Copyright (C) 2010 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later Type "show copying" and "show warranty" for licensing/warranty details. This GDB was configured as "x86_64-linux". Hey, I'm GDB 7.x. Check me out! http://wiki/Main/Gdb7x Reading symbols from /Users/stepan/svn/coreboot/build/util/romcc/romcc...done. (gdb) run test.c Starting program: /Users/stepan/svn/coreboot/build/util/romcc/romcc test.c Program received signal SIGSEGV, Segmentation fault. 0x0000000000402baa in use_triple (used=0x676860, user=0x676a50) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:1901 1901 if ((*ptr)->member == user) { (gdb) bt #0 0x0000000000402baa in use_triple (used=0x676860, user=0x676a50) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:1901 #1 0x00000000004120df in flatten_generic (state=0x7fffffff9c60, first=0x675d40, ptr=0x676a50, ignored=0) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:7847 #2 0x00000000004131a0 in flatten (state=0x7fffffff9c60, first=0x675d40, ptr=0x676a50) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:8042 #3 0x000000000041e1fb in expr_statement (state=0x7fffffff9c60, first=0x675d40) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:11662 #4 0x0000000000420479 in statement (state=0x7fffffff9c60, first=0x675d40) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:12361 #5 0x0000000000420248 in compound_statement (state=0x7fffffff9c60, first=0x675d40) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:12304 #6 0x0000000000422bb1 in function_definition (state=0x7fffffff9c60, type=0x675c60) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:13415 #7 0x0000000000422fa5 in decl (state=0x7fffffff9c60, first=0x675960) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:13507 #8 0x00000000004231b8 in decls (state=0x7fffffff9c60) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:13553 #9 0x000000000043f263 in compile (filename=0x7fffffffe389 "test.c", compiler=0x7fffffffdea0, arch=0x7fffffffdf00) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:25045 #10 0x000000000043f98b in main (argc=1, argv=0x7fffffffe020) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:25190 From joe at settoplinux.org Wed Apr 13 00:20:18 2011 From: joe at settoplinux.org (Joseph Smith) Date: Tue, 12 Apr 2011 18:20:18 -0400 Subject: [coreboot] romcc segfault In-Reply-To: <20110412211012.GA4336@coreboot.org> References: <20110412211012.GA4336@coreboot.org> Message-ID: <4DA4D022.4060106@settoplinux.org> On 04/12/2011 05:10 PM, Stefan Reinauer wrote: > Hi, > > just a heads up, I got romcc to segfault with the following sample program: > > D'oh! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From russ at ashlandhome.net Wed Apr 13 07:05:48 2011 From: russ at ashlandhome.net (Russell Whitaker) Date: Tue, 12 Apr 2011 22:05:48 -0700 (PDT) Subject: [coreboot] romcc segfault In-Reply-To: <20110412211012.GA4336@coreboot.org> References: <20110412211012.GA4336@coreboot.org> Message-ID: On Tue, 12 Apr 2011, Stefan Reinauer wrote: > Hi, > > just a heads up, I got romcc to segfault with the following sample program: > > > --------------------- 8< snip 8< -------------------------------------- > typedef unsigned int u32; > #define DEFAULT_RCBA 0xfed1c000 > #define GCS 0x3410 > #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) > > void test(void) > { > RCBA32(GCS) &= (~0x04); > } > --------------------- >8 snip >8 -------------------------------------- > > I tried to simplify this further and this construct is still crashing romcc: > > --------------------- 8< snip 8< -------------------------------------- > u32 *gcs = (u32 *)(DEFAULT_RCBA + GCS); > *gcs &= (~0x04); > --------------------- >8 snip >8 -------------------------------------- > > while this one is working > > --------------------- 8< snip 8< -------------------------------------- > u32 *gcs = (u32 *)(DEFAULT_RCBA + GCS); > u32 temp = *gcs; > temp &= (~0x04); > *gcs = temp; > --------------------- >8 snip >8 -------------------------------------- > > Is that a construct that we just can't/don't want to support in romcc? > Or is there a chance we can fix that? > > Stefan Just for comparison used gcc -S to compile the 3 snippets. The first compiled without error. 2nd: testc2.c:1:13: error: expected '=', ',', ';', 'asm' or '__attribute__' before '*' token testc2.c:2:14: error: expected '=', ',', ';', 'asm' or '__attribute__' before '&=' token 3rd: testc3.c:1:13: error: expected '=', ',', ';', 'asm' or '__attribute__' before '*' token testc3.c:2:13: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'temp' testc3.c:3:14: error: expected '=', ',', ';', 'asm' or '__attribute__' before '&=' token testc3.c:4:9: warning: data definition has no type or storage class testc3.c:4:16: error: 'temp' undeclared here (not in a function) testc3.c:5:13: error: expected '=', ',', ';', 'asm' or '__attribute__' before '*' token testc3.c:6:13: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'temp' testc3.c:7:14: error: expected '=', ',', ';', 'asm' or '__attribute__' before '&=' token testc3.c:8:9: warning: data definition has no type or storage class testc3.c:8:10: error: redefinition of 'gcs' testc3.c:4:10: note: previous definition of 'gcs' was here testc3.c:9:13: error: expected '=', ',', ';', 'asm' or '__attribute__' before '*' token testc3.c:10:13: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'temp' testc3.c:11:14: error: expected '=', ',', ';', 'asm' or '__attribute__' before '&=' token testc3.c:12:10: warning: data definition has no type or storage class testc3.c:12:11: error: redefinition of 'gcs' testc3.c:4:10: note: previous definition of 'gcs' was here Russ From stefan.reinauer at coreboot.org Wed Apr 13 07:57:06 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Tue, 12 Apr 2011 22:57:06 -0700 Subject: [coreboot] romcc segfault In-Reply-To: References: <20110412211012.GA4336@coreboot.org> Message-ID: <4DA53B32.8010404@coreboot.org> On 4/12/11 10:05 PM, Russell Whitaker wrote: > > > On Tue, 12 Apr 2011, Stefan Reinauer wrote: > >> Hi, >> >> just a heads up, I got romcc to segfault with the following sample >> program: >> >> >> --------------------- 8< snip 8< -------------------------------------- >> typedef unsigned int u32; >> #define DEFAULT_RCBA 0xfed1c000 >> #define GCS 0x3410 >> #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) >> >> void test(void) >> { >> RCBA32(GCS) &= (~0x04); >> } >> --------------------- >8 snip >8 -------------------------------------- >> >> I tried to simplify this further and this construct is still crashing >> romcc: >> >> --------------------- 8< snip 8< -------------------------------------- >> u32 *gcs = (u32 *)(DEFAULT_RCBA + GCS); >> *gcs &= (~0x04); >> --------------------- >8 snip >8 -------------------------------------- >> >> while this one is working >> >> --------------------- 8< snip 8< -------------------------------------- >> u32 *gcs = (u32 *)(DEFAULT_RCBA + GCS); >> u32 temp = *gcs; >> temp &= (~0x04); >> *gcs = temp; >> --------------------- >8 snip >8 -------------------------------------- >> >> Is that a construct that we just can't/don't want to support in romcc? >> Or is there a chance we can fix that? >> >> Stefan > > Just for comparison used gcc -S to compile the 3 snippets. > The first compiled without error. > [..] Russel, Not sure what you tried, but they all compile without error. You have to wrap example 2 and 3 with typedef unsigned int u32; #define DEFAULT_RCBA 0xfed1c000 #define GCS 0x3410 void test(void) { and } before actually running them through gcc. From svn at coreboot.org Wed Apr 13 11:23:46 2011 From: svn at coreboot.org (repository service) Date: Wed, 13 Apr 2011 11:23:46 +0200 Subject: [coreboot] [commit] r6491 - trunk/src/ec/lenovo/h8/acpi Message-ID: Author: svens Date: Wed Apr 13 11:23:45 2011 New Revision: 6491 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6491 Log: Lenovo H8 EC: add missing include for thermal.asl Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/ec/lenovo/h8/acpi/ec.asl Modified: trunk/src/ec/lenovo/h8/acpi/ec.asl ============================================================================== --- trunk/src/ec/lenovo/h8/acpi/ec.asl Tue Apr 12 20:18:24 2011 (r6490) +++ trunk/src/ec/lenovo/h8/acpi/ec.asl Wed Apr 13 11:23:45 2011 (r6491) @@ -119,4 +119,5 @@ #include "sleepbutton.asl" #include "lid.asl" #include "beep.asl" +#include "thermal.asl" } From cubicool at gmail.com Thu Apr 14 00:29:11 2011 From: cubicool at gmail.com (Jeremy Moles) Date: Wed, 13 Apr 2011 18:29:11 -0400 Subject: [coreboot] Super I/O: Winbond LPC Super I/O WPCN381U In-Reply-To: <20110407175251.18283.qmail@stuge.se> References: <1301958441.2587.11.camel@lv-426> <1302189374.2489.4.camel@lv-426> <20110407152156.1233.qmail@stuge.se> <20110407152744.1876.qmail@stuge.se> <1302190473.2489.9.camel@lv-426> <20110407153949.3424.qmail@stuge.se> <1302192439.2489.14.camel@lv-426> <1302197216.2489.21.camel@lv-426> <20110407175251.18283.qmail@stuge.se> Message-ID: <1302733751.2498.9.camel@lv-426> On Thu, 2011-04-07 at 19:52 +0200, Peter Stuge wrote: > Jeremy Moles wrote: > > It's not that the hardware specs are unvailable, it's simply that I > > lack the knowledge to be able to translate the information form the > > hardware vendor (i.e., their engineer telling me to simply ping > > GPIO-03 on the SuperI/O controller and the hardware lights up) into > > Linux code. :) In Windows, apparently, it's as easy as that... > > If anything I'd say it's more difficult in Windows. > > > > the GPIO registers I need are abstracted away in an LDN (7, in my > > case), and I think you need to inform the hardware of that FIRST > > before writing any bits. > > Correct. Looking at chapter 5 it's also clear that actual data for > GPIO pins is written using registers offset from an IO base address > configured in the logical device. So steps are: > > set gpio ldn: regwrite(7,7) > read io base address: regread(60h)<<8 | regread(61h) > read current GPIO-0 value: inb(base address) > set bit 3 in value (1<<3) > write new GPIO-0 value: outb(base,newval With this lists help and Tom Sylla's help, I was able to get the device working. :) If our contractors permit, I will release the code as OSS. At the very least I'm trying to authorize donations... Thanks a ton, a great resource here! > //Peter > From root at crankyadmin.net Thu Apr 14 14:00:20 2011 From: root at crankyadmin.net (Dave Houston) Date: Thu, 14 Apr 2011 13:00:20 +0100 Subject: [coreboot] ASUS M488t-m Message-ID: Afternoon all, I have an ASUS M488t-m which is very close to m4a785-m. I am currently making sure that I have a method to reflash should my build is bad ( which it most likely will be ) and I have been doing some digging regarding my Flash chip. The data sheet suggests that the current chip is 16Mb http://www.alldatasheet.com/datasheet-pdf/pdf/272751/EON/EN25F16.html. High resolution of mainboard: http://media.ldlc.com/ld/products/00/00/77/92/LD0000779214_2.jpg I have included all relevant output below. Is there any gotchas I should be aware of and is there a good flashing solution (I'm not adverse to buying a hardware solution ) ? Flashrom output > flashrom v0.9.1-r946 > No coreboot table found. > Found ITE Super I/O, id 8712 > Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK. > This chipset supports the following protocols: LPC,FWH,SPI. > Calibrating delay loop... OK. > Found chip "Eon EN25F16" (2048 KB, SPI) at physical address 0xffe00000. > === > This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE > Please email a report to flashrom at flashrom.org if any of the above operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, -rV, > -wV, -EV), and mention which mainboard or programmer you tested. > Thanks for your help! > === > No operations were specified. SuperIOTool -d output > Found ITE IT8712F (id=0x8712, rev=0x8) at 0x2e > Register dump: > idx 20 21 22 23 24 2b > val 87 12 08 00 00 00 > def 87 12 08 00 00 00 > LDN 0x00 (Floppy) > idx 30 60 61 70 74 f0 f1 > val 00 03 f0 06 02 00 00 > def 00 03 f0 06 02 00 00 > LDN 0x01 (COM1) > idx 30 60 61 70 f0 f1 f2 f3 > val 00 00 00 00 00 50 00 7f > def 00 03 f8 04 00 50 00 7f > LDN 0x02 (COM2) > idx 30 60 61 70 f0 f1 f2 f3 > val 00 02 f8 03 00 50 00 7f > def 00 02 f8 03 00 50 00 7f > LDN 0x03 (Parallel port) > idx 30 60 61 62 63 70 74 f0 > val 00 00 00 00 00 00 04 00 > def 00 03 78 07 78 07 03 03 > LDN 0x04 (Environment controller) > idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 > val 01 02 90 02 30 00 00 00 00 00 20 00 ff > def 00 02 90 02 30 09 00 00 00 00 00 NA NA > LDN 0x05 (Keyboard) > idx 30 60 61 62 63 70 71 f0 > val 01 00 60 00 64 01 02 04 > def 01 00 60 00 64 01 02 08 > LDN 0x06 (Mouse) > idx 30 70 71 f0 > val 01 0c 02 00 > def 00 0c 02 00 > LDN 0x07 (GPIO) > idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd > val c1 a0 00 00 80 01 1f 00 00 03 00 00 00 00 01 00 38 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 a0 00 00 00 40 a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1a 00 00 00 00 01 00 00 > def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 > LDN 0x08 (MIDI port) > idx 30 60 61 70 f0 > val 00 03 00 0a 00 > def 00 03 00 0a 00 > LDN 0x09 (Game port) > idx 30 60 61 > val 00 02 01 > def 00 02 01 > LDN 0x0a (Consumer IR) > idx 30 60 61 70 f0 > val 00 03 10 0b 06 > def 00 03 10 0b 00 > $ lspci -tvnn > -[0000:00]-+-00.0 Advanced Micro Devices [AMD] RS780 Host Bridge Alternate [1022:9601] > +-01.0-[0000:01]--+-05.0 ATI Technologies Inc Device [1002:9715] > | \-05.1 ATI Technologies Inc RS880 Audio Device [Radeon HD 4200] [1002:970f] > +-0a.0-[0000:02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] > +-11.0 ATI Technologies Inc SB700/SB800 SATA Controller [AHCI mode] [1002:4391] > +-12.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] > +-12.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] > +-12.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] > +-13.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] > +-13.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] > +-13.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] > +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] > +-14.1 ATI Technologies Inc SB700/SB800 IDE Controller [1002:439c] > +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] > +-14.3 ATI Technologies Inc SB700/SB800 LPC host controller [1002:439d] > +-14.4-[0000:03]-- > +-14.5 ATI Technologies Inc SB700/SB800 USB OHCI2 Controller [1002:4399] > +-18.0 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200] > +-18.1 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Address Map [1022:1201] > +-18.2 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202] > +-18.3 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203] > \-18.4 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Link Control [1022:1204] > Many thanks Dave -------------- next part -------------- An HTML attachment was scrubbed... URL: From chris.pn.west at gmail.com Thu Apr 14 20:21:40 2011 From: chris.pn.west at gmail.com (christopher west) Date: Thu, 14 Apr 2011 19:21:40 +0100 Subject: [coreboot] ASUS M4A79XTD EVO Message-ID: <1302805300.4248.52.camel@leela> Hello all, I've finally decided to bite the bullet and seriously look into putting coreboot on my Asus M4A79XTD EVO as I've getting bored of waiting for the BIOS to load. Buy my initial reckoning it looks as if everything is supported except the superio device. Could someone please confirm this as the specifications are as follows: Processor: AMD Phenom(tm) II X4 965 Processor, northbridge: RD790X Southbridge: SB750 SuperIO: IT8720F Rom Chip: Winbond W25x80 If I'm missing anything or you need more raw output please let me know. If my initial assumption is true then what could I do to support the superio as I'm not adverse to getting my hands dirty as I'm trying to get into embedded software and hardware design. Many thanks, Chris From svn at coreboot.org Thu Apr 14 21:52:04 2011 From: svn at coreboot.org (repository service) Date: Thu, 14 Apr 2011 21:52:04 +0200 Subject: [coreboot] [commit] r6492 - trunk/payloads/libpayload/drivers/usb Message-ID: Author: stepan Date: Thu Apr 14 21:52:04 2011 New Revision: 6492 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6492 Log: coding style cosmetics. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/payloads/libpayload/drivers/usb/ehci.c Modified: trunk/payloads/libpayload/drivers/usb/ehci.c ============================================================================== --- trunk/payloads/libpayload/drivers/usb/ehci.c Wed Apr 13 11:23:45 2011 (r6491) +++ trunk/payloads/libpayload/drivers/usb/ehci.c Thu Apr 14 21:52:04 2011 (r6492) @@ -31,7 +31,8 @@ #include "ehci.h" #include "ehci_private.h" -static void dump_td(u32 addr) { +static void dump_td(u32 addr) +{ qtd_t *td = phys_to_virt(addr); printf("td at phys(%x): active: %x, halted: %x, data_buf_err: %x\n babble: %x, xact_err: %x, missed_mframe: %x\n splitxstate: %x, perr: %x\n\n", addr, td->active, td->halted, td->data_buf_err, td->babble, td->xact_err, td->missed_mframe, td->splitxstate, td->perr); @@ -61,7 +62,8 @@ enum { EHCI_OUT=0, EHCI_IN=1, EHCI_SETUP=2 }; /* returns handled bytes */ -int fill_td(qtd_t *td, void* data, int datalen) { +int fill_td(qtd_t *td, void* data, int datalen) +{ u32 total_len = 0; u32 page_minus_1 = 0; @@ -99,7 +101,8 @@ } /* free up data structures */ -void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur) { +void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur) +{ qtd_t *next; while (cur) { next = (qtd_t*)phys_to_virt(cur->next_qtd & ~31); @@ -109,7 +112,8 @@ free(qh); } -int wait_for_tds(qtd_t *head) { +int wait_for_tds(qtd_t *head) +{ int result = 0; qtd_t *cur = head; while (1) { From reinauer at google.com Thu Apr 14 22:00:39 2011 From: reinauer at google.com (Stefan Reinauer) Date: Thu, 14 Apr 2011 22:00:39 +0200 Subject: [coreboot] [PATCH] libpayload OXPCIe 952 support Message-ID: <20110414200039.GA28147@coreboot.org> See patch. -------------- next part -------------- A non-text attachment was scrubbed... Name: libpayload-oxpcie.diff Type: text/x-patch Size: 4267 bytes Desc: not available URL: From svn at coreboot.org Thu Apr 14 22:06:31 2011 From: svn at coreboot.org (repository service) Date: Thu, 14 Apr 2011 22:06:31 +0200 Subject: [coreboot] [commit] r6493 - in trunk/src/cpu: amd/car intel/car intel/model_6ex intel/model_6fx Message-ID: Author: stepan Date: Thu Apr 14 22:06:30 2011 New Revision: 6493 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6493 Log: Use symbolic names for some MTRR bits instead of numbers in CAR code Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Thu Apr 14 21:52:04 2011 (r6492) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Thu Apr 14 22:06:30 2011 (r6493) @@ -77,7 +77,7 @@ /* Check if cpu_init_detected. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(1 << 11), %eax + andl $MTRRdefTypeEn, %eax movl %eax, %ebx /* We store the status. */ jmp_if_k8(CAR_FAM10_out_post_errata) @@ -306,7 +306,7 @@ jmp_if_k8(wbcache_post_fam10_setup) movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */ wbcache_post_fam10_setup: - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Thu Apr 14 21:52:04 2011 (r6492) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Thu Apr 14 22:06:30 2011 (r6493) @@ -254,7 +254,7 @@ movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -354,7 +354,7 @@ */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */ + movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr /* Enable cache. */ Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Thu Apr 14 21:52:04 2011 (r6492) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Thu Apr 14 22:06:30 2011 (r6493) @@ -63,14 +63,14 @@ /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx wrmsr /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr /* Enable L2 cache. */ @@ -118,7 +118,7 @@ movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -160,7 +160,7 @@ /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) @@ -201,7 +201,7 @@ xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx // 36bit address space wrmsr @@ -217,7 +217,7 @@ /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Thu Apr 14 21:52:04 2011 (r6492) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Thu Apr 14 22:06:30 2011 (r6493) @@ -70,14 +70,14 @@ /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx wrmsr /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr /* Enable L2 cache. */ @@ -125,7 +125,7 @@ movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -167,7 +167,7 @@ /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) @@ -208,7 +208,7 @@ xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx // 36bit address space wrmsr @@ -224,7 +224,7 @@ /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) From svn at coreboot.org Thu Apr 14 22:10:28 2011 From: svn at coreboot.org (repository service) Date: Thu, 14 Apr 2011 22:10:28 +0200 Subject: [coreboot] [commit] r6494 - trunk/src/southbridge/sis/sis966 Message-ID: Author: stepan Date: Thu Apr 14 22:10:27 2011 New Revision: 6494 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6494 Log: cosmetic cleanup of sis966 usb2 code Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/southbridge/sis/sis966/usb2.c Modified: trunk/src/southbridge/sis/sis966/usb2.c ============================================================================== --- trunk/src/southbridge/sis/sis966/usb2.c Thu Apr 14 22:06:30 2011 (r6493) +++ trunk/src/southbridge/sis/sis966/usb2.c Thu Apr 14 22:10:27 2011 (r6494) @@ -32,52 +32,50 @@ #include "sis966.h" #include -extern struct ehci_debug_info dbg_info; +static const u8 SiS_SiS7002_init[22][3]={ + {0x04, 0x00, 0x06}, + {0x0D, 0x00, 0x00}, + + {0x2C, 0xFF, 0x39}, + {0x2D, 0xFF, 0x10}, + {0x2E, 0xFF, 0x02}, + {0x2F, 0xFF, 0x70}, + + {0x74, 0x00, 0x00}, + {0x75, 0x00, 0x00}, + {0x76, 0x00, 0x00}, + {0x77, 0x00, 0x00}, + + {0x7A, 0x00, 0x00}, + {0x7B, 0x00, 0x00}, + + {0x40, 0x00, 0x20}, + {0x41, 0x00, 0x00}, + {0x42, 0x00, 0x00}, + {0x43, 0x00, 0x08}, + + {0x44, 0x00, 0x04}, + + {0x48, 0x00, 0x10}, + {0x49, 0x00, 0x80}, + {0x4A, 0x00, 0x07}, + {0x4B, 0x00, 0x00}, -u8 SiS_SiS7002_init[22][3]={ -{0x04, 0x00, 0x06}, -{0x0D, 0x00, 0x00}, - -{0x2C, 0xFF, 0x39}, -{0x2D, 0xFF, 0x10}, -{0x2E, 0xFF, 0x02}, -{0x2F, 0xFF, 0x70}, - -{0x74, 0x00, 0x00}, -{0x75, 0x00, 0x00}, -{0x76, 0x00, 0x00}, -{0x77, 0x00, 0x00}, - -{0x7A, 0x00, 0x00}, -{0x7B, 0x00, 0x00}, - -{0x40, 0x00, 0x20}, -{0x41, 0x00, 0x00}, -{0x42, 0x00, 0x00}, -{0x43, 0x00, 0x08}, - -{0x44, 0x00, 0x04}, - -{0x48, 0x00, 0x10}, -{0x49, 0x00, 0x80}, -{0x4A, 0x00, 0x07}, -{0x4B, 0x00, 0x00}, - -{0x00, 0x00, 0x00} //End of table + {0x00, 0x00, 0x00} //End of table }; static void usb2_init(struct device *dev) { u32 base; struct resource *res; + int i; + u8 temp8; print_debug("USB 2.0 INIT:---------->\n"); -//-------------- enable USB2.0 (SiS7002) ------------------------- -{ - u8 temp8; - int i=0; + //-------------- enable USB2.0 (SiS7002) ---------------------- + i = 0; while(SiS_SiS7002_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); @@ -86,7 +84,6 @@ pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); i++; }; -} res = find_resource(dev, 0x10); if(!res) @@ -95,12 +92,9 @@ base = res->base; printk(BIOS_DEBUG, "base = 0x%08x\n", base); write32(base+0x20, 0x2); -//----------------------------------------------------------- + //------------------------------------------------------------- #if DEBUG_USB2 -{ - int i; - print_debug("****** USB 2.0 PCI config ******"); print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); @@ -114,7 +108,6 @@ print_debug(" "); } print_debug("\n"); -} #endif print_debug("USB 2.0 INIT:<----------\n"); } @@ -139,7 +132,6 @@ set_ehci_base(base); report_resource_stored(dev, res, ""); #endif - } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -147,6 +139,7 @@ pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; From svn at coreboot.org Thu Apr 14 22:11:35 2011 From: svn at coreboot.org (repository service) Date: Thu, 14 Apr 2011 22:11:35 +0200 Subject: [coreboot] [commit] r6495 - trunk/src/southbridge/nvidia/mcp55 Message-ID: Author: stepan Date: Thu Apr 14 22:11:34 2011 New Revision: 6495 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6495 Log: nvidia mcp55: drop unused dbg_info Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/southbridge/nvidia/mcp55/usb2.c Modified: trunk/src/southbridge/nvidia/mcp55/usb2.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/usb2.c Thu Apr 14 22:10:27 2011 (r6494) +++ trunk/src/southbridge/nvidia/mcp55/usb2.c Thu Apr 14 22:11:34 2011 (r6495) @@ -29,8 +29,6 @@ #include "mcp55.h" #include -extern struct ehci_debug_info dbg_info; - static void usb2_init(struct device *dev) { u32 dword; From svn at coreboot.org Thu Apr 14 22:21:50 2011 From: svn at coreboot.org (repository service) Date: Thu, 14 Apr 2011 22:21:50 +0200 Subject: [coreboot] [commit] r6496 - in trunk/src: arch/x86 arch/x86/lib cpu/x86/16bit northbridge/via/vx800 southbridge/nvidia/ck804 southbridge/nvidia/mcp55 southbridge/sis/sis966 southbridge/via/k8t890 Message-ID: Author: stepan Date: Thu Apr 14 22:21:49 2011 New Revision: 6496 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6496 Log: drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/arch/x86/Kconfig trunk/src/arch/x86/lib/id.lds trunk/src/cpu/x86/16bit/reset16.lds trunk/src/northbridge/via/vx800/romstrap.lds trunk/src/southbridge/nvidia/ck804/romstrap.lds trunk/src/southbridge/nvidia/mcp55/romstrap.lds trunk/src/southbridge/sis/sis966/romstrap.lds trunk/src/southbridge/via/k8t890/romstrap.lds Modified: trunk/src/arch/x86/Kconfig ============================================================================== --- trunk/src/arch/x86/Kconfig Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/arch/x86/Kconfig Thu Apr 14 22:21:49 2011 (r6496) @@ -8,20 +8,10 @@ default n depends on ARCH_X86 -# This is the name of the respective architecture subdirectory in arch/. -config ARCH - string - default i386 - depends on ARCH_X86 - config ROMBASE hex default 0xffff0000 -config ROM_IMAGE_SIZE - hex - default 0x10000 - config RAMBASE hex default 0x100000 Modified: trunk/src/arch/x86/lib/id.lds ============================================================================== --- trunk/src/arch/x86/lib/id.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/arch/x86/lib/id.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -1,5 +1,5 @@ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start); + . = (0x100000000 - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start); .id (.): { *(.id) } Modified: trunk/src/cpu/x86/16bit/reset16.lds ============================================================================== --- trunk/src/cpu/x86/16bit/reset16.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/cpu/x86/16bit/reset16.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -5,7 +5,7 @@ SECTIONS { /* Trigger an error if I have an unuseable start address */ - _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease CONFIG_ROM_IMAGE_SIZE"); + _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please report."); _ROMTOP = 0xfffffff0; . = _ROMTOP; .reset . : { Modified: trunk/src/northbridge/via/vx800/romstrap.lds ============================================================================== --- trunk/src/northbridge/via/vx800/romstrap.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/northbridge/via/vx800/romstrap.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -19,7 +19,7 @@ */ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } Modified: trunk/src/southbridge/nvidia/ck804/romstrap.lds ============================================================================== --- trunk/src/southbridge/nvidia/ck804/romstrap.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/southbridge/nvidia/ck804/romstrap.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -19,7 +19,7 @@ */ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); + . = (0x100000000 - 0x10) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } Modified: trunk/src/southbridge/nvidia/mcp55/romstrap.lds ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/romstrap.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/southbridge/nvidia/mcp55/romstrap.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -20,7 +20,7 @@ */ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); + . = (0x100000000 - 0x10) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } Modified: trunk/src/southbridge/sis/sis966/romstrap.lds ============================================================================== --- trunk/src/southbridge/sis/sis966/romstrap.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/southbridge/sis/sis966/romstrap.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -20,7 +20,7 @@ */ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); + . = (0x100000000 - 0x10) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } Modified: trunk/src/southbridge/via/k8t890/romstrap.lds ============================================================================== --- trunk/src/southbridge/via/k8t890/romstrap.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/southbridge/via/k8t890/romstrap.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -22,7 +22,7 @@ /* Modified for K8T890 ROM strap by Rudolf Marek . */ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } From svn at coreboot.org Thu Apr 14 22:30:22 2011 From: svn at coreboot.org (repository service) Date: Thu, 14 Apr 2011 22:30:22 +0200 Subject: [coreboot] [commit] r6497 - in trunk/src/arch/x86: . init Message-ID: Author: stepan Date: Thu Apr 14 22:30:21 2011 New Revision: 6497 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6497 Log: - drop remaining CONFIG_ROM_IMAGE_SIZE - re-enable .data section check for bootblock. - rename ldscript_fallback_cbfs.lb to bootblock.ld Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Added: trunk/src/arch/x86/init/bootblock.ld - copied, changed from r6491, trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb Deleted: trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb Modified: trunk/src/arch/x86/Makefile.inc Modified: trunk/src/arch/x86/Makefile.inc ============================================================================== --- trunk/src/arch/x86/Makefile.inc Thu Apr 14 22:21:49 2011 (r6496) +++ trunk/src/arch/x86/Makefile.inc Thu Apr 14 22:30:21 2011 (r6497) @@ -165,7 +165,7 @@ crt0s = $(src)/arch/x86/init/prologue.inc ldscripts = -ldscripts += $(src)/arch/x86/init/ldscript_fallback_cbfs.lb +ldscripts += $(src)/arch/x86/init/bootblock.ld ifeq ($(CONFIG_BIG_BOOTBLOCK),y) crt0s += $(src)/cpu/x86/16bit/entry16.inc ldscripts += $(src)/cpu/x86/16bit/entry16.lds Copied and modified: trunk/src/arch/x86/init/bootblock.ld (from r6491, trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb) ============================================================================== --- trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb Wed Apr 13 11:23:45 2011 (r6491, copy source) +++ trunk/src/arch/x86/init/bootblock.ld Thu Apr 14 22:30:21 2011 (r6497) @@ -29,7 +29,7 @@ /* cut _start into last 64k*/ _x = .; - . = (_x < (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE) : _x; + . = (_x < CONFIG_ROMBASE) ? (CONFIG_ROMBASE) : _x; /* This section might be better named .setup */ .rom . : { @@ -49,6 +49,5 @@ *(.comment.*) *(.note.*) } -/* _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage"); */ - _bogus = ASSERT((SIZEOF(.bss)) == 0, "Do not use global variables in romstage"); + _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage"); } From svn at coreboot.org Thu Apr 14 22:33:54 2011 From: svn at coreboot.org (repository service) Date: Thu, 14 Apr 2011 22:33:54 +0200 Subject: [coreboot] [commit] r6498 - trunk/src/arch/x86/lib Message-ID: Author: stepan Date: Thu Apr 14 22:33:53 2011 New Revision: 6498 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6498 Log: add some comments to walkcbfs.S Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/arch/x86/lib/walkcbfs.S Modified: trunk/src/arch/x86/lib/walkcbfs.S ============================================================================== --- trunk/src/arch/x86/lib/walkcbfs.S Thu Apr 14 22:30:21 2011 (r6497) +++ trunk/src/arch/x86/lib/walkcbfs.S Thu Apr 14 22:33:53 2011 (r6498) @@ -16,11 +16,11 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) /* - input %esi: filename - input %esp: return address (not pointer to return address!) - output %eax: entry point - clobbers %ebx, %ecx, %edi -*/ + * input %esi: filename + * input %esp: return address (not pointer to return address!) + * output %eax: entry point + * clobbers %ebx, %ecx, %edi + */ walkcbfs_asm: cld @@ -28,10 +28,10 @@ mov CBFS_HEADER_ROMSIZE(%eax), %ecx bswap %ecx mov $0, %ebx - sub %ecx, %ebx + sub %ecx, %ebx /* rom base address in ebx */ mov CBFS_HEADER_OFFSET(%eax), %ecx bswap %ecx - add %ecx, %ebx + add %ecx, %ebx /* address where we start looking for LARCHIVEs */ /* determine filename length */ mov $0, %eax @@ -43,21 +43,22 @@ 2: add $1, %eax walker: - mov 0(%ebx), %edi + mov 0(%ebx), %edi /* Check for LARCHIVE header */ cmp %edi, filemagic jne searchfile mov 4(%ebx), %edi cmp %edi, filemagic+4 jne searchfile + /* LARCHIVE header found */ mov %ebx, %edi add $CBFS_FILE_STRUCTSIZE, %edi /* edi = address of first byte after struct cbfs_file */ mov %eax, %ecx repe cmpsb - # zero flag set if strings are equal + /* zero flag set if strings are equal */ jnz tryharder - # we found it! + /* we found it! */ mov CBFS_FILE_OFFSET(%ebx), %eax bswap %eax add %ebx, %eax From svn at coreboot.org Thu Apr 14 22:39:49 2011 From: svn at coreboot.org (repository service) Date: Thu, 14 Apr 2011 22:39:49 +0200 Subject: [coreboot] [commit] r6499 - trunk/src/cpu/x86/mtrr Message-ID: Author: stepan Date: Thu Apr 14 22:39:49 2011 New Revision: 6499 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6499 Log: earlymtrr.c: wipe some dead code, use names instead of numbers and some cosmetics. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c ============================================================================== --- trunk/src/cpu/x86/mtrr/earlymtrr.c Thu Apr 14 22:33:53 2011 (r6498) +++ trunk/src/cpu/x86/mtrr/earlymtrr.c Thu Apr 14 22:39:49 2011 (r6499) @@ -5,19 +5,6 @@ #include #include -#if 0 -static void disable_var_mtrr(unsigned reg) -{ - /* The invalid bit is kept in the mask so we simply - * clear the relevent mask register to disable a - * range. - */ - msr_t zero; - zero.lo = zero.hi = 0; - wrmsr(MTRRphysMask_MSR(reg), zero); -} -#endif - static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) @@ -28,33 +15,13 @@ basem.lo = base | type; basem.hi = 0; wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | 0x800; - maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1; + maskm.lo = ~(size - 1) | MTRRphysMaskValid; + maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; wrmsr(MTRRphysMask_MSR(reg), maskm); } -#if 0 -static void set_var_mtrr_x( - unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - msr_t basem, maskm; - basem.lo = (base_lo & 0xfffff000) | type; - basem.hi = base_hi & ((1<<(CONFIG_CPU_ADDR_BITS-32))-1); - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1; - if(size_lo) { - maskm.lo = ~(size_lo - 1) | 0x800; - } else { - maskm.lo = 0x800; - maskm.hi &= ~(size_hi - 1); - } - wrmsr(MTRRphysMask_MSR(reg), maskm); -} -#endif - -static inline void cache_lbmem(int type) +#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0) +static void cache_lbmem(int type) { /* Enable caching for 0 - 1MB using variable mtrr */ disable_cache(); @@ -62,7 +29,6 @@ enable_cache(); } -#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0) /* the fixed and variable MTTRs are power-up with random values, * clear them to MTRR_TYPE_UNCACHEABLE for safty. */ @@ -119,7 +85,6 @@ do_early_mtrr_init(mtrr_msrs); enable_cache(); } -#endif static inline int early_mtrr_init_detected(void) { @@ -131,7 +96,8 @@ * according to the documentation. */ msr = rdmsr(MTRRdefType_MSR); - return msr.lo & 0x00000800; + return msr.lo & MTRRdefTypeEn; } +#endif #endif /* EARLYMTRR_C */ From svn at coreboot.org Thu Apr 14 23:05:41 2011 From: svn at coreboot.org (repository service) Date: Thu, 14 Apr 2011 23:05:41 +0200 Subject: [coreboot] [commit] r6500 - trunk/src/arch/x86/boot Message-ID: Author: stepan Date: Thu Apr 14 23:05:41 2011 New Revision: 6500 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6500 Log: fix coreboot compilation without serial console enabled. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/arch/x86/boot/coreboot_table.c Modified: trunk/src/arch/x86/boot/coreboot_table.c ============================================================================== --- trunk/src/arch/x86/boot/coreboot_table.c Thu Apr 14 22:39:49 2011 (r6499) +++ trunk/src/arch/x86/boot/coreboot_table.c Thu Apr 14 23:05:41 2011 (r6500) @@ -116,7 +116,7 @@ serial->baud = CONFIG_TTYS0_BAUD; return serial; #else - return header; + return NULL; #endif } From peter at stuge.se Thu Apr 14 23:41:26 2011 From: peter at stuge.se (Peter Stuge) Date: Thu, 14 Apr 2011 23:41:26 +0200 Subject: [coreboot] [commit] r6497 - in trunk/src/arch/x86: . init In-Reply-To: References: Message-ID: <20110414214126.15081.qmail@stuge.se> repository service wrote: > Date: Thu Apr 14 22:30:21 2011 > Log: > - drop remaining CONFIG_ROM_IMAGE_SIZE Yeah!! I have been looking forward to this for a long long time! :) Well done! //Peter From svn at coreboot.org Thu Apr 14 23:45:11 2011 From: svn at coreboot.org (repository service) Date: Thu, 14 Apr 2011 23:45:11 +0200 Subject: [coreboot] build service results for r6496 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6496 to the coreboot repository. This caused the following changes: Change Log: drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=atc-6220&vendor=a-trend&num=2 Compilation of a-trend:atc-6240 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=atc-6240&vendor=a-trend&num=2 Compilation of abit:be6-ii_v2_0 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=be6-ii_v2_0&vendor=abit&num=2 Compilation of advantech:pcm-5820 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=pcm-5820&vendor=advantech&num=2 Compilation of amd:bimini_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=bimini_fam10&vendor=amd&num=2 Compilation of amd:db800 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=db800&vendor=amd&num=2 Compilation of amd:dbm690t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=dbm690t&vendor=amd&num=2 Compilation of amd:inagua has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=inagua&vendor=amd&num=2 Compilation of amd:mahogany has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=mahogany&vendor=amd&num=2 Compilation of amd:mahogany_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=mahogany_fam10&vendor=amd&num=2 Compilation of amd:norwich has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=norwich&vendor=amd&num=2 Compilation of amd:persimmon has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=persimmon&vendor=amd&num=2 Compilation of amd:pistachio has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=pistachio&vendor=amd&num=2 Compilation of amd:rumba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=rumba&vendor=amd&num=2 Compilation of amd:serengeti_cheetah has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=serengeti_cheetah&vendor=amd&num=2 Compilation of amd:serengeti_cheetah_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=serengeti_cheetah_fam10&vendor=amd&num=2 Compilation of amd:tilapia_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=tilapia_fam10&vendor=amd&num=2 Compilation of arima:hdama has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=hdama&vendor=arima&num=2 Compilation of artecgroup:dbe61 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=dbe61&vendor=artecgroup&num=2 Compilation of asi:mb_5blgp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=mb_5blgp&vendor=asi&num=2 Compilation of asi:mb_5blmp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=mb_5blmp&vendor=asi&num=2 Compilation of asrock:939a785gmh has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=939a785gmh&vendor=asrock&num=2 Compilation of asrock:e350m1 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=e350m1&vendor=asrock&num=2 Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=a8n_e&vendor=asus&num=2 Compilation of asus:a8v-e_deluxe has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=a8v-e_deluxe&vendor=asus&num=2 Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=a8v-e_se&vendor=asus&num=2 Compilation of asus:m2n-e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=m2n-e&vendor=asus&num=2 Compilation of asus:m2v has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=m2v&vendor=asus&num=2 Compilation of asus:m2v-mx_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=m2v-mx_se&vendor=asus&num=2 Compilation of asus:m4a78-em has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=m4a78-em&vendor=asus&num=2 Compilation of asus:m4a785-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=m4a785-m&vendor=asus&num=2 Compilation of asus:mew-am has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=mew-am&vendor=asus&num=2 Compilation of asus:mew-vm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=mew-vm&vendor=asus&num=2 Compilation of asus:p2b has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=p2b&vendor=asus&num=2 Compilation of asus:p2b-d has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=p2b-d&vendor=asus&num=2 Compilation of asus:p2b-ds has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=p2b-ds&vendor=asus&num=2 Compilation of asus:p2b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=p2b-f&vendor=asus&num=2 Compilation of asus:p2b-ls has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=p2b-ls&vendor=asus&num=2 Compilation of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=p3b-f&vendor=asus&num=2 Compilation of axus:tc320 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=tc320&vendor=axus&num=2 Compilation of azza:pt-6ibd has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=pt-6ibd&vendor=azza&num=2 Compilation of bcom:winnet100 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=winnet100&vendor=bcom&num=2 Compilation of bcom:winnetp680 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=winnetp680&vendor=bcom&num=2 Compilation of biostar:m6tba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=m6tba&vendor=biostar&num=2 Compilation of broadcom:blast has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=blast&vendor=broadcom&num=2 Compilation of compaq:deskpro_en_sff_p600 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=deskpro_en_sff_p600&vendor=compaq&num=2 Compilation of dell:s1850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s1850&vendor=dell&num=2 Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=adl855pc&vendor=digitallogic&num=2 Compilation of digitallogic:msm586seg has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=msm586seg&vendor=digitallogic&num=2 Compilation of digitallogic:msm800sev has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=msm800sev&vendor=digitallogic&num=2 Compilation of eaglelion:5bcm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=5bcm&vendor=eaglelion&num=2 Compilation of ecs:p6iwp-fe has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=p6iwp-fe&vendor=ecs&num=2 Compilation of emulation:qemu-x86 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=qemu-x86&vendor=emulation&num=2 Compilation of getac:p470 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=p470&vendor=getac&num=2 Compilation of gigabyte:ga-6bxc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ga-6bxc&vendor=gigabyte&num=2 Compilation of gigabyte:ga-6bxe has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ga-6bxe&vendor=gigabyte&num=2 Compilation of gigabyte:ga_2761gxdk has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ga_2761gxdk&vendor=gigabyte&num=2 Compilation of gigabyte:m57sli has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=m57sli&vendor=gigabyte&num=2 Compilation of gigabyte:ma785gmt has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ma785gmt&vendor=gigabyte&num=2 Compilation of gigabyte:ma78gm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ma78gm&vendor=gigabyte&num=2 Compilation of hp:dl145_g1 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=dl145_g1&vendor=hp&num=2 Compilation of hp:dl145_g3 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=dl145_g3&vendor=hp&num=2 Compilation of hp:dl165_g6_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=dl165_g6_fam10&vendor=hp&num=2 Compilation of hp:e_vectra_p2706t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=e_vectra_p2706t&vendor=hp&num=2 Compilation of ibase:mb899 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=mb899&vendor=ibase&num=2 Compilation of ibm:e325 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=e325&vendor=ibm&num=2 Compilation of ibm:e326 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=e326&vendor=ibm&num=2 Compilation of iei:juki-511p has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=juki-511p&vendor=iei&num=2 Compilation of iei:kino-780am2-fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=kino-780am2-fam10&vendor=iei&num=2 Compilation of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=nova4899r&vendor=iei&num=2 Compilation of iei:pcisa-lx-800-r10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=pcisa-lx-800-r10&vendor=iei&num=2 Compilation of intel:d810e2cb has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=d810e2cb&vendor=intel&num=2 Compilation of intel:d945gclf has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=d945gclf&vendor=intel&num=2 Compilation of intel:eagleheights has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=eagleheights&vendor=intel&num=2 Compilation of intel:jarrell has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=jarrell&vendor=intel&num=2 Compilation of intel:mtarvon has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=mtarvon&vendor=intel&num=2 Compilation of intel:truxton has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=truxton&vendor=intel&num=2 Compilation of intel:xe7501devkit has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=xe7501devkit&vendor=intel&num=2 Compilation of iwave:iWRainbowG6 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=iWRainbowG6&vendor=iwave&num=2 Compilation of iwill:dk8_htx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=dk8_htx&vendor=iwill&num=2 Compilation of iwill:dk8s2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=dk8s2&vendor=iwill&num=2 Compilation of iwill:dk8x has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=dk8x&vendor=iwill&num=2 Compilation of jetway:j7f24 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=j7f24&vendor=jetway&num=2 Compilation of jetway:pa78vm5 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=pa78vm5&vendor=jetway&num=2 Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=986lcd-m&vendor=kontron&num=2 Compilation of kontron:kt690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=kt690&vendor=kontron&num=2 Compilation of lanner:em8510 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=em8510&vendor=lanner&num=2 Compilation of lenovo:x60 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=x60&vendor=lenovo&num=2 Compilation of lippert:frontrunner has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=frontrunner&vendor=lippert&num=2 Compilation of lippert:hurricane-lx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=hurricane-lx&vendor=lippert&num=2 Compilation of lippert:literunner-lx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=literunner-lx&vendor=lippert&num=2 Compilation of lippert:roadrunner-lx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=roadrunner-lx&vendor=lippert&num=2 Compilation of lippert:spacerunner-lx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=spacerunner-lx&vendor=lippert&num=2 Compilation of mitac:6513wu has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=6513wu&vendor=mitac&num=2 Compilation of msi:ms6119 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ms6119&vendor=msi&num=2 Compilation of msi:ms6147 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ms6147&vendor=msi&num=2 Compilation of msi:ms6156 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ms6156&vendor=msi&num=2 Compilation of msi:ms6178 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ms6178&vendor=msi&num=2 Compilation of msi:ms7135 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ms7135&vendor=msi&num=2 Compilation of msi:ms7260 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ms7260&vendor=msi&num=2 Compilation of msi:ms9185 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ms9185&vendor=msi&num=2 Compilation of msi:ms9282 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ms9282&vendor=msi&num=2 Compilation of msi:ms9652_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ms9652_fam10&vendor=msi&num=2 Compilation of nec:powermate2000 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=powermate2000&vendor=nec&num=2 Compilation of newisys:khepri has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=khepri&vendor=newisys&num=2 Compilation of nokia:ip530 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ip530&vendor=nokia&num=2 Compilation of nvidia:l1_2pvv has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=l1_2pvv&vendor=nvidia&num=2 Compilation of pcengines:alix1c has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=alix1c&vendor=pcengines&num=2 Compilation of pcengines:alix2d has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=alix2d&vendor=pcengines&num=2 Compilation of rca:rm4100 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=rm4100&vendor=rca&num=2 Compilation of roda:rk886ex has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=rk886ex&vendor=roda&num=2 Compilation of soyo:sy-6ba-plus-iii has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=sy-6ba-plus-iii&vendor=soyo&num=2 Compilation of sunw:ultra40 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ultra40&vendor=sunw&num=2 Compilation of supermicro:h8dme has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=h8dme&vendor=supermicro&num=2 Compilation of supermicro:h8dmr has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=h8dmr&vendor=supermicro&num=2 Compilation of supermicro:h8dmr_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=h8dmr_fam10&vendor=supermicro&num=2 Compilation of supermicro:h8qme_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=h8qme_fam10&vendor=supermicro&num=2 Compilation of supermicro:h8scm_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=h8scm_fam10&vendor=supermicro&num=2 Compilation of supermicro:x6dai_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=x6dai_g&vendor=supermicro&num=2 Compilation of supermicro:x6dhe_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=x6dhe_g&vendor=supermicro&num=2 Compilation of supermicro:x6dhe_g2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=x6dhe_g2&vendor=supermicro&num=2 Compilation of supermicro:x6dhr_ig has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=x6dhr_ig&vendor=supermicro&num=2 Compilation of supermicro:x6dhr_ig2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=x6dhr_ig2&vendor=supermicro&num=2 Compilation of technexion:tim5690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=tim5690&vendor=technexion&num=2 Compilation of technexion:tim8690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=tim8690&vendor=technexion&num=2 Compilation of technologic:ts5300 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ts5300&vendor=technologic&num=2 Compilation of televideo:tc7020 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=tc7020&vendor=televideo&num=2 Compilation of thomson:ip1000 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=ip1000&vendor=thomson&num=2 Compilation of traverse:geos has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=geos&vendor=traverse&num=2 Compilation of tyan:s1846 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s1846&vendor=tyan&num=2 Compilation of tyan:s2735 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2735&vendor=tyan&num=2 Compilation of tyan:s2850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2850&vendor=tyan&num=2 Compilation of tyan:s2875 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2875&vendor=tyan&num=2 Compilation of tyan:s2880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2880&vendor=tyan&num=2 Compilation of tyan:s2881 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2881&vendor=tyan&num=2 Compilation of tyan:s2882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2882&vendor=tyan&num=2 Compilation of tyan:s2885 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2885&vendor=tyan&num=2 Compilation of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2891&vendor=tyan&num=2 Compilation of tyan:s2892 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2892&vendor=tyan&num=2 Compilation of tyan:s2895 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2895&vendor=tyan&num=2 Compilation of tyan:s2912 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2912&vendor=tyan&num=2 Compilation of tyan:s2912_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s2912_fam10&vendor=tyan&num=2 Compilation of tyan:s4880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s4880&vendor=tyan&num=2 Compilation of tyan:s4882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s4882&vendor=tyan&num=2 Compilation of via:epia has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=epia&vendor=via&num=2 Compilation of via:epia-cn has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=epia-cn&vendor=via&num=2 Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=epia-m&vendor=via&num=2 Compilation of via:epia-m700 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=epia-m700&vendor=via&num=2 Compilation of via:epia-n has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=epia-n&vendor=via&num=2 Compilation of via:pc2500e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=pc2500e&vendor=via&num=2 Compilation of via:vt8454c has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=vt8454c&vendor=via&num=2 Compilation of winent:pl6064 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=pl6064&vendor=winent&num=2 Compilation of wyse:s50 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=s50&vendor=wyse&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From stefan.reinauer at coreboot.org Thu Apr 14 23:46:16 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Thu, 14 Apr 2011 23:46:16 +0200 Subject: [coreboot] [PATCH] console/console.h cleanup Message-ID: <20110414214615.GA16484@coreboot.org> See patch -------------- next part -------------- A non-text attachment was scrubbed... Name: console_include_cleanup.diff Type: text/x-patch Size: 2039 bytes Desc: not available URL: From stefan.reinauer at coreboot.org Fri Apr 15 00:13:54 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Fri, 15 Apr 2011 00:13:54 +0200 Subject: [coreboot] [commit] r6497 - in trunk/src/arch/x86: . init In-Reply-To: <20110414214126.15081.qmail@stuge.se> References: <20110414214126.15081.qmail@stuge.se> Message-ID: <20110414221354.GA32710@coreboot.org> * Peter Stuge [110414 23:41]: > repository service wrote: > > Date: Thu Apr 14 22:30:21 2011 > > Log: > > - drop remaining CONFIG_ROM_IMAGE_SIZE > > Yeah!! I have been looking forward to this for a long long time! :) > > Well done! Thank you! I originally had a much more agressive patch removing even more questionable code, but it got kind of hairy with testing, so let's go one step after another. I encourage everyone to think about which config variables we can get rid of. "Make coreboot simpler" days! Stefan From peter at stuge.se Fri Apr 15 00:15:00 2011 From: peter at stuge.se (Peter Stuge) Date: Fri, 15 Apr 2011 00:15:00 +0200 Subject: [coreboot] [PATCH] console/console.h cleanup In-Reply-To: <20110414214615.GA16484@coreboot.org> References: <20110414214615.GA16484@coreboot.org> Message-ID: <20110414221500.18493.qmail@stuge.se> Stefan Reinauer wrote: > - include usbdebug.c where appropriate > - don't do ne2k_transmit()s without actual output > > Signed-off-by: Stefan Reinauer Acked-by: Peter Stuge From stefan.reinauer at coreboot.org Fri Apr 15 00:16:34 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Fri, 15 Apr 2011 00:16:34 +0200 Subject: [coreboot] build service results for r6496 In-Reply-To: References: Message-ID: <20110414221634.GB32710@coreboot.org> * repository service [110414 23:45]: > Dear coreboot readers! > > This is the automatic build system of coreboot. > > The developer "stepan" checked in revision 6496 to > the coreboot repository. This caused the following > changes: > > Change Log: > drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH > > Signed-off-by: Stefan Reinauer > Acked-by: Stefan Reinauer > > > > Build Log: > Compilation of a-trend:atc-6220 has been broken > See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6496&device=atc-6220&vendor=a-trend&num=2 [..] Sorry for this, should be fixed in 6497 From stefan.reinauer at coreboot.org Fri Apr 15 00:19:22 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Fri, 15 Apr 2011 00:19:22 +0200 Subject: [coreboot] [PATCH] drop init_uart8250() calls from superio drivers Message-ID: <20110414221921.GA9015@coreboot.org> See patch. With this in place I keep wondering if we couldn't get rid of all (non-early) code of most superio drivers -------------- next part -------------- A non-text attachment was scrubbed... Name: drop_baudrate_init.diff Type: text/x-patch Size: 33258 bytes Desc: not available URL: From svn at coreboot.org Fri Apr 15 00:28:01 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 00:28:01 +0200 Subject: [coreboot] [commit] r6501 - in trunk: . src/cpu/x86/smm src/lib Message-ID: Author: stepan Date: Fri Apr 15 00:28:00 2011 New Revision: 6501 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6501 Log: drop half an uart8250 implementation from smiutil and use the common code for that instead. This also allows using non-uart8250 consoles for smi debugging. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/Makefile.inc trunk/src/cpu/x86/smm/smiutil.c trunk/src/lib/Makefile.inc trunk/src/lib/uart8250.c Modified: trunk/Makefile.inc ============================================================================== --- trunk/Makefile.inc Thu Apr 14 23:05:41 2011 (r6500) +++ trunk/Makefile.inc Fri Apr 15 00:28:00 2011 (r6501) @@ -52,6 +52,8 @@ romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ +smm-c-ccopts:=-D__SMM__ +smm-S-ccopts:=-D__SMM__ ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) Modified: trunk/src/cpu/x86/smm/smiutil.c ============================================================================== --- trunk/src/cpu/x86/smm/smiutil.c Thu Apr 14 23:05:41 2011 (r6500) +++ trunk/src/cpu/x86/smm/smiutil.c Fri Apr 15 00:28:00 2011 (r6501) @@ -21,110 +21,52 @@ #include #include -#include #include #include -/* ********************* smi_util ************************* */ - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 +#include +#include +#if CONFIG_CONSOLE_SERIAL8250 +#include #endif - -#ifndef CONFIG_TTYS0_DIV -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#if CONFIG_USBDEBUG +#include #endif - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 +#if CONFIG_CONSOLE_NE2K +#include #endif -#define UART_LCS CONFIG_TTYS0_LCS - -static int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -static void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -static void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - void console_tx_flush(void) { - uart_wait_to_tx_byte(); + // the tx_byte functions take care of the flush. + // if not, this should be implemented. } void console_tx_byte(unsigned char byte) { if (byte == '\n') - uart_tx_byte('\r'); - uart_tx_byte(byte); -} + console_tx_byte('\r'); -#if CONFIG_DEBUG_SMI -static void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(byte); #endif +#if CONFIG_CONSOLE_NE2K + ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +} void console_init(void) { #if CONFIG_DEBUG_SMI console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +#if CONFIG_CONSOLE_SERIAL8250 uart_init(); +#endif #else console_loglevel = 1; #endif } -/* ********************* smi_util ************************* */ Modified: trunk/src/lib/Makefile.inc ============================================================================== --- trunk/src/lib/Makefile.inc Thu Apr 14 23:05:41 2011 (r6500) +++ trunk/src/lib/Makefile.inc Fri Apr 15 00:28:00 2011 (r6501) @@ -1,5 +1,18 @@ -ramstage-y += clog2.c -ramstage-y += uart8250.c + + +romstage-y += memset.c +romstage-y += memcpy.c +romstage-y += memcmp.c +romstage-y += cbfs.c +romstage-y += lzma.c +#romstage-y += lzmadecode.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c +romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c +romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c +romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c +romstage-$(CONFIG_USBDEBUG) += usbdebug.c + ramstage-y += memset.c ramstage-y += memcpy.c ramstage-y += memcmp.c @@ -13,27 +26,15 @@ ramstage-y += lzma.c #ramstage-y += lzmadecode.c ramstage-y += gcc.c +ramstage-y += clog2.c ramstage-y += cbmem.c - -romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c -romstage-y += uart8250.c -romstage-y += memset.c -romstage-y += memcpy.c -romstage-y += memcmp.c -romstage-y += cbfs.c -romstage-y += lzma.c -romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c -#romstage-y += lzmadecode.c -romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c -romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c - -driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c - -romstage-$(CONFIG_USBDEBUG) += usbdebug.c +ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c - ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c +driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c + smm-y += memcpy.c +smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c $(obj)/lib/version.ramstage.o : $(obj)/build.h Modified: trunk/src/lib/uart8250.c ============================================================================== --- trunk/src/lib/uart8250.c Thu Apr 14 23:05:41 2011 (r6500) +++ trunk/src/lib/uart8250.c Fri Apr 15 00:28:00 2011 (r6501) @@ -103,10 +103,10 @@ } #endif -#ifdef __PRE_RAM__ +#if defined(__PRE_RAM__) || defined(__SMM__) void uart_init(void) { -#if CONFIG_USE_OPTION_TABLE +#if CONFIG_USE_OPTION_TABLE && !defined(__SMM__) static const unsigned char divisor[] = { 1, 2, 3, 6, 12, 24, 48, 96 }; unsigned ttys0_div, ttys0_index; ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); From cubicool at gmail.com Fri Apr 15 01:13:24 2011 From: cubicool at gmail.com (Jeremy Moles) Date: Thu, 14 Apr 2011 19:13:24 -0400 Subject: [coreboot] SuperI/O Access (Kernelspace) Message-ID: <1302822804.2593.10.camel@lv-426> Hey guys, me again. :) So, my device is working great now that I can access the GPIO pins via userspace (using iotools w/ Tom Sylla's help) and can power on the device. However, I'd like to be able to toggle the power on via a kernel driver as well, but I'm having trouble accessing the same memory range from kernelspace. For example: iotools io_read8 0xA00 Will return the state of the first 5 GPIO pins. I see that iotools calls iopl() to be able to access this location from userspace. When I try to do the same thing in the kernel: unsigned short b; unsigned short* ptr = (unsigned short*)(0xA00); if(access_ok(VERIFY_READ, ptr, 8)) { get_user(b, ptr); ...I immediately get a segfault. From what I've read and seen in other example code, I believe I'm doing this right. However, I may be making some wrong assumptions. I was just curious if anyone would be able to shed some light on the subject--perhaps I'm missing some virtual memory offset functions or similar... From jeremy at emperorlinux.com Fri Apr 15 01:12:47 2011 From: jeremy at emperorlinux.com (Jeremy Moles) Date: Thu, 14 Apr 2011 19:12:47 -0400 Subject: [coreboot] SuperI/O Access (Kernelspace) Message-ID: <1302822767.2593.9.camel@lv-426> Hey guys, me again. :) So, my device is working great now that I can access the GPIO pins via userspace (using iotools w/ Tom Sylla's help) and can power on the device. However, I'd like to be able to toggle the power on via a kernel driver as well, but I'm having trouble accessing the same memory range from kernelspace. For example: iotools io_read8 0xA00 Will return the state of the first 5 GPIO pins. I see that iotools calls iopl() to be able to access this location from userspace. When I try to do the same thing in the kernel: unsigned short b; unsigned short* ptr = (unsigned short*)(0xA00); if(access_ok(VERIFY_READ, ptr, 8)) { get_user(b, ptr); ...I immediately get a segfault. From what I've read and seen in other example code, I believe I'm doing this right. However, I may be making some wrong assumptions. I was just curious if anyone would be able to shed some light on the subject--perhaps I'm missing some virtual memory offset functions or similar... From peter at stuge.se Fri Apr 15 02:07:11 2011 From: peter at stuge.se (Peter Stuge) Date: Fri, 15 Apr 2011 02:07:11 +0200 Subject: [coreboot] SuperI/O Access (Kernelspace) In-Reply-To: <1302822804.2593.10.camel@lv-426> References: <1302822804.2593.10.camel@lv-426> Message-ID: <20110415000711.29877.qmail@stuge.se> Jeremy Moles wrote: > working great now .. via userspace .. > However, I'd like to be able to toggle the power on via a kernel > driver as well, Why? > but I'm having trouble accessing the same memory range from > kernelspace. > > For example: > > iotools io_read8 0xA00 io_read8 is not a memory access, it is an I/O access. x86 has two different address spaces on the bus, and different instructions to access them. The superio is not memory mapped.. > When I try to do the same thing in the kernel: > > unsigned short b; > unsigned short* ptr = (unsigned short*)(0xA00); > > if(access_ok(VERIFY_READ, ptr, 8)) { > get_user(b, ptr); > > ...I immediately get a segfault. ..so that's not the way to reach it. Last time I did this I used inb() and outb(). Remember to use barriers as neccessary and also make sure that request_region() succeeds before you touch any hardware. The proper way to implement GPIO support is btw to write a gpio class driver for it. There are lots of gpio drivers already in the kernel. I would actually not be surprised if your chip is already supported by one of them, and if not one could probably be extended easily. The GPIO drivers are exposed to userspace via sysfs. Again; why does your other kernel driver need to deal with this GPIO? This smells like a questionable design decision was made somewhere in the chain. Better fix that sooner than later in that case.. //Peter From gregg.drwho8 at gmail.com Fri Apr 15 01:49:41 2011 From: gregg.drwho8 at gmail.com (Gregg Levine) Date: Thu, 14 Apr 2011 19:49:41 -0400 Subject: [coreboot] SuperI/O Access (Kernelspace) In-Reply-To: <1302822804.2593.10.camel@lv-426> References: <1302822804.2593.10.camel@lv-426> Message-ID: On Thu, Apr 14, 2011 at 7:13 PM, Jeremy Moles wrote: > Hey guys, me again. :) > > So, my device is working great now that I can access the GPIO pins via > userspace (using iotools w/ Tom Sylla's help) and can power on the > device. However, I'd like to be able to toggle the power on via a kernel > driver as well, but I'm having trouble accessing the same memory range > from kernelspace. > > For example: > > ? ? ? ?iotools io_read8 0xA00 > > Will return the state of the first 5 GPIO pins. I see that iotools calls > iopl() to be able to access this location from userspace. > > When I try to do the same thing in the kernel: > > ? ? ? ?unsigned short ?b; > ? ? ? ?unsigned short* ptr = (unsigned short*)(0xA00); > > ? ? ? ?if(access_ok(VERIFY_READ, ptr, 8)) { > ? ? ? ? ? ? ? ?get_user(b, ptr); > > ...I immediately get a segfault. From what I've read and seen in other > example code, I believe I'm doing this right. However, I may be making > some wrong assumptions. I was just curious if anyone would be able to > shed some light on the subject--perhaps I'm missing some virtual memory > offset functions or similar... > Hello! I'm not a C programmer, I just make use of its strengths and some of its weaknesses. That being stated, why don't you explain more about what you're trying to achieve without of course releasing anything considered a trade secret. For example are you using the uncommitted GPIO lines to access a feature on your device? And is your device returning something back to your board? Come to that, what is your device doing? That's the big thing I am curious about, again without doing that above. For what I do with Linux, I am interested in making use of your ideas, but again there is that limitation. Also is this being done on a board that was built by your shop, or did it start out life as a reference platform. ----- Gregg C Levine gregg.drwho8 at gmail.com "This signature fought the Time Wars, time and again." From scott at notabs.org Fri Apr 15 01:50:27 2011 From: scott at notabs.org (Scott Duplichan) Date: Thu, 14 Apr 2011 18:50:27 -0500 Subject: [coreboot] ASUS M488t-m In-Reply-To: References: Message-ID: Dave Houston wrote: ]Afternoon all, ] ]I have an ASUS M488t-m which is very close to m4a785-m. I am currently making ]sure that I have a method to reflash should my build is bad ( which it most ]likely will be ) and I have been doing some digging regarding my Flash chip. ]The data sheet suggests that the current chip is 16Mb ]http://www.alldatasheet.com/datasheet-pdf/pdf/272751/EON/EN25F16.html. I have a board with the same flash chip and use DediProg SF100 for programming. I use a clip similar to this to connect it to the DediProg: http://parts.digikey.com/1/parts-kws/8-pin-ic-dil-clip ]High resolution of mainboard: http://media.ldlc.com/ld/products/00/00/77/92/LD0000779214_2.jpg ] ]I have included all relevant output below. Is there any gotchas I should be ]aware of and is there a good flashing solution (I'm not adverse to buying a ]hardware solution ) ? As long as you can easily program the flash and also connect the serial port for logging then?progress is possible. I think you have to supply the serial port cable that connects to the motherboard com1 header. Thanks, Scott ]Many thanks ] ]Dave From tsylla at gmail.com Fri Apr 15 01:51:19 2011 From: tsylla at gmail.com (Tom Sylla) Date: Thu, 14 Apr 2011 16:51:19 -0700 Subject: [coreboot] SuperI/O Access (Kernelspace) In-Reply-To: <1302822767.2593.9.camel@lv-426> References: <1302822767.2593.9.camel@lv-426> Message-ID: Your address is in I/O address space, not memory address space. Take a look at io_rw.c in iotools, you need to be using inb/outb (not just reading/writing memory). Tom On Thu, Apr 14, 2011 at 4:12 PM, Jeremy Moles wrote: > Hey guys, me again. :) > > So, my device is working great now that I can access the GPIO pins via > userspace (using iotools w/ Tom Sylla's help) and can power on the > device. However, I'd like to be able to toggle the power on via a kernel > driver as well, but I'm having trouble accessing the same memory range > from kernelspace. > > For example: > > ? ? ? ?iotools io_read8 0xA00 > > Will return the state of the first 5 GPIO pins. I see that iotools calls > iopl() to be able to access this location from userspace. > > When I try to do the same thing in the kernel: > > ? ? ? ?unsigned short ?b; > ? ? ? ?unsigned short* ptr = (unsigned short*)(0xA00); > > ? ? ? ?if(access_ok(VERIFY_READ, ptr, 8)) { > ? ? ? ? ? ? ? ?get_user(b, ptr); > > ...I immediately get a segfault. From what I've read and seen in other > example code, I believe I'm doing this right. However, I may be making > some wrong assumptions. I was just curious if anyone would be able to > shed some light on the subject--perhaps I'm missing some virtual memory > offset functions or similar... > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From svn at coreboot.org Fri Apr 15 02:19:28 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 02:19:28 +0200 Subject: [coreboot] [commit] r6502 - in trunk/src/mainboard: digitallogic/adl855pc intel/eagleheights intel/mtarvon lanner/em8510 tyan/s2735 Message-ID: Author: stepan Date: Fri Apr 15 02:19:27 2011 New Revision: 6502 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6502 Log: fix mainboards that were including earlymtrr.c without actually using it. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/lanner/em8510/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Fri Apr 15 00:28:00 2011 (r6501) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Fri Apr 15 02:19:27 2011 (r6502) @@ -14,7 +14,6 @@ #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" #include "superio/winbond/w83627hf/early_serial.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Fri Apr 15 00:28:00 2011 (r6501) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Fri Apr 15 02:19:27 2011 (r6502) @@ -68,7 +68,6 @@ } #include "northbridge/intel/i3100/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "northbridge/intel/i3100/raminit.c" #include "lib/generic_sdram.c" Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Fri Apr 15 00:28:00 2011 (r6501) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Fri Apr 15 02:19:27 2011 (r6502) @@ -31,7 +31,6 @@ #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" #include "superio/intel/i3100/i3100.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "superio/intel/i3100/early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/lanner/em8510/romstage.c ============================================================================== --- trunk/src/mainboard/lanner/em8510/romstage.c Fri Apr 15 00:28:00 2011 (r6501) +++ trunk/src/mainboard/lanner/em8510/romstage.c Fri Apr 15 02:19:27 2011 (r6502) @@ -37,7 +37,6 @@ #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" #include "superio/winbond/w83627thg/early_serial.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Fri Apr 15 00:28:00 2011 (r6501) +++ trunk/src/mainboard/tyan/s2735/romstage.c Fri Apr 15 02:19:27 2011 (r6502) @@ -13,7 +13,6 @@ #include "northbridge/intel/e7501/raminit.h" #include "northbridge/intel/e7501/debug.c" #include "superio/winbond/w83627hf/early_serial.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) From svn at coreboot.org Fri Apr 15 02:26:31 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 02:26:31 +0200 Subject: [coreboot] build service results for r6501 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6501 to the coreboot repository. This caused the following changes: Change Log: drop half an uart8250 implementation from smiutil and use the common code for that instead. This also allows using non-uart8250 consoles for smi debugging. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=inagua&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=persimmon&vendor=amd&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=e350m1&vendor=asrock&num=2 Compilation of digitallogic:adl855pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=adl855pc&vendor=digitallogic&num=2 Compilation of intel:eagleheights is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=eagleheights&vendor=intel&num=2 Compilation of intel:mtarvon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=mtarvon&vendor=intel&num=2 Compilation of lanner:em8510 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=em8510&vendor=lanner&num=2 Compilation of tyan:s2735 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=s2735&vendor=tyan&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Fri Apr 15 02:56:40 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 02:56:40 +0200 Subject: [coreboot] build service results for r6502 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6502 to the coreboot repository. This caused the following changes: Change Log: fix mainboards that were including earlymtrr.c without actually using it. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6502&device=inagua&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6502&device=persimmon&vendor=amd&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6502&device=e350m1&vendor=asrock&num=2 Compilation of digitallogic:adl855pc has been fixed Compilation of intel:eagleheights has been fixed Compilation of intel:mtarvon has been fixed Compilation of lanner:em8510 has been fixed Compilation of tyan:s2735 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Fri Apr 15 03:27:17 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 03:27:17 +0200 Subject: [coreboot] build service results for r6499 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6499 to the coreboot repository. This caused the following changes: Change Log: earlymtrr.c: wipe some dead code, use names instead of numbers and some cosmetics. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=inagua&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=persimmon&vendor=amd&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=e350m1&vendor=asrock&num=2 Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=adl855pc&vendor=digitallogic&num=2 Compilation of intel:eagleheights has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=eagleheights&vendor=intel&num=2 Compilation of intel:mtarvon has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=mtarvon&vendor=intel&num=2 Compilation of lanner:em8510 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=em8510&vendor=lanner&num=2 Compilation of tyan:s2735 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=s2735&vendor=tyan&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Fri Apr 15 03:57:37 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 03:57:37 +0200 Subject: [coreboot] build service results for r6497 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6497 to the coreboot repository. This caused the following changes: Change Log: - drop remaining CONFIG_ROM_IMAGE_SIZE - re-enable .data section check for bootblock. - rename ldscript_fallback_cbfs.lb to bootblock.ld Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of a-trend:atc-6220 has been fixed Compilation of a-trend:atc-6240 has been fixed Compilation of abit:be6-ii_v2_0 has been fixed Compilation of advantech:pcm-5820 has been fixed Compilation of amd:bimini_fam10 has been fixed Compilation of amd:db800 has been fixed Compilation of amd:dbm690t has been fixed Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6497&device=inagua&vendor=amd&num=2 Compilation of amd:mahogany has been fixed Compilation of amd:mahogany_fam10 has been fixed Compilation of amd:norwich has been fixed Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6497&device=persimmon&vendor=amd&num=2 Compilation of amd:pistachio has been fixed Compilation of amd:rumba has been fixed Compilation of amd:serengeti_cheetah has been fixed Compilation of amd:serengeti_cheetah_fam10 has been fixed Compilation of amd:tilapia_fam10 has been fixed Compilation of arima:hdama has been fixed Compilation of artecgroup:dbe61 has been fixed Compilation of asi:mb_5blgp has been fixed Compilation of asi:mb_5blmp has been fixed Compilation of asrock:939a785gmh has been fixed Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6497&device=e350m1&vendor=asrock&num=2 Compilation of asus:a8n_e has been fixed Compilation of asus:a8v-e_deluxe has been fixed Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2n-e has been fixed Compilation of asus:m2v has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of asus:m4a78-em has been fixed Compilation of asus:m4a785-m has been fixed Compilation of asus:mew-am has been fixed Compilation of asus:mew-vm has been fixed Compilation of asus:p2b has been fixed Compilation of asus:p2b-d has been fixed Compilation of asus:p2b-ds has been fixed Compilation of asus:p2b-f has been fixed Compilation of asus:p2b-ls has been fixed Compilation of asus:p3b-f has been fixed Compilation of axus:tc320 has been fixed Compilation of azza:pt-6ibd has been fixed Compilation of bcom:winnet100 has been fixed Compilation of bcom:winnetp680 has been fixed Compilation of biostar:m6tba has been fixed Compilation of broadcom:blast has been fixed Compilation of compaq:deskpro_en_sff_p600 has been fixed Compilation of dell:s1850 has been fixed Compilation of digitallogic:adl855pc has been fixed Compilation of digitallogic:msm586seg has been fixed Compilation of digitallogic:msm800sev has been fixed Compilation of eaglelion:5bcm has been fixed Compilation of ecs:p6iwp-fe has been fixed Compilation of emulation:qemu-x86 has been fixed Compilation of getac:p470 has been fixed Compilation of gigabyte:ga-6bxc has been fixed Compilation of gigabyte:ga-6bxe has been fixed Compilation of gigabyte:ga_2761gxdk has been fixed Compilation of gigabyte:m57sli has been fixed Compilation of gigabyte:ma785gmt has been fixed Compilation of gigabyte:ma78gm has been fixed Compilation of hp:dl145_g1 has been fixed Compilation of hp:dl145_g3 has been fixed Compilation of hp:dl165_g6_fam10 has been fixed Compilation of hp:e_vectra_p2706t has been fixed Compilation of ibase:mb899 has been fixed Compilation of ibm:e325 has been fixed Compilation of ibm:e326 has been fixed Compilation of iei:juki-511p has been fixed Compilation of iei:kino-780am2-fam10 has been fixed Compilation of iei:nova4899r has been fixed Compilation of iei:pcisa-lx-800-r10 has been fixed Compilation of intel:d810e2cb has been fixed Compilation of intel:d945gclf has been fixed Compilation of intel:eagleheights has been fixed Compilation of intel:jarrell has been fixed Compilation of intel:mtarvon has been fixed Compilation of intel:truxton has been fixed Compilation of intel:xe7501devkit has been fixed Compilation of iwave:iWRainbowG6 has been fixed Compilation of iwill:dk8_htx has been fixed Compilation of iwill:dk8s2 has been fixed Compilation of iwill:dk8x has been fixed Compilation of jetway:j7f24 has been fixed Compilation of jetway:pa78vm5 has been fixed Compilation of kontron:986lcd-m has been fixed Compilation of kontron:kt690 has been fixed Compilation of lanner:em8510 has been fixed Compilation of lenovo:x60 has been fixed Compilation of lippert:frontrunner has been fixed Compilation of lippert:hurricane-lx has been fixed Compilation of lippert:literunner-lx has been fixed Compilation of lippert:roadrunner-lx has been fixed Compilation of lippert:spacerunner-lx has been fixed Compilation of mitac:6513wu has been fixed Compilation of msi:ms6119 has been fixed Compilation of msi:ms6147 has been fixed Compilation of msi:ms6156 has been fixed Compilation of msi:ms6178 has been fixed Compilation of msi:ms7135 has been fixed Compilation of msi:ms7260 has been fixed Compilation of msi:ms9185 has been fixed Compilation of msi:ms9282 has been fixed Compilation of msi:ms9652_fam10 has been fixed Compilation of nec:powermate2000 has been fixed Compilation of newisys:khepri has been fixed Compilation of nokia:ip530 has been fixed Compilation of nvidia:l1_2pvv has been fixed Compilation of pcengines:alix1c has been fixed Compilation of pcengines:alix2d has been fixed Compilation of rca:rm4100 has been fixed Compilation of roda:rk886ex has been fixed Compilation of soyo:sy-6ba-plus-iii has been fixed Compilation of sunw:ultra40 has been fixed Compilation of supermicro:h8dme has been fixed Compilation of supermicro:h8dmr has been fixed Compilation of supermicro:h8dmr_fam10 has been fixed Compilation of supermicro:h8qme_fam10 has been fixed Compilation of supermicro:h8scm_fam10 has been fixed Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed Compilation of technexion:tim5690 has been fixed Compilation of technexion:tim8690 has been fixed Compilation of technologic:ts5300 has been fixed Compilation of televideo:tc7020 has been fixed Compilation of thomson:ip1000 has been fixed Compilation of traverse:geos has been fixed Compilation of tyan:s1846 has been fixed Compilation of tyan:s2735 has been fixed Compilation of tyan:s2850 has been fixed Compilation of tyan:s2875 has been fixed Compilation of tyan:s2880 has been fixed Compilation of tyan:s2881 has been fixed Compilation of tyan:s2882 has been fixed Compilation of tyan:s2885 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed Compilation of tyan:s2912 has been fixed Compilation of tyan:s2912_fam10 has been fixed Compilation of tyan:s4880 has been fixed Compilation of tyan:s4882 has been fixed Compilation of via:epia has been fixed Compilation of via:epia-cn has been fixed Compilation of via:epia-m has been fixed Compilation of via:epia-m700 has been fixed Compilation of via:epia-n has been fixed Compilation of via:pc2500e has been fixed Compilation of via:vt8454c has been fixed Compilation of winent:pl6064 has been fixed Compilation of wyse:s50 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Fri Apr 15 05:30:04 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 05:30:04 +0200 Subject: [coreboot] [commit] r6503 - in trunk/src: . drivers drivers/ati drivers/ati/ragexl drivers/emulation drivers/emulation/qemu drivers/generic drivers/generic/debug drivers/i2c drivers/i2c/adm1026 drivers/i2c/ad... Message-ID: Author: stepan Date: Fri Apr 15 05:30:03 2011 New Revision: 6503 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6503 Log: Handle drivers/ equally to any other sub directory. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Added: trunk/src/drivers/ati/Kconfig trunk/src/drivers/ati/Makefile.inc trunk/src/drivers/ati/ragexl/Kconfig trunk/src/drivers/emulation/Kconfig trunk/src/drivers/emulation/Makefile.inc trunk/src/drivers/emulation/qemu/Kconfig trunk/src/drivers/emulation/qemu/Makefile.inc trunk/src/drivers/generic/Kconfig trunk/src/drivers/generic/Makefile.inc trunk/src/drivers/generic/debug/Kconfig trunk/src/drivers/i2c/Kconfig trunk/src/drivers/i2c/Makefile.inc trunk/src/drivers/i2c/adm1026/Kconfig trunk/src/drivers/i2c/adm1026/Makefile.inc trunk/src/drivers/i2c/adm1027/Kconfig trunk/src/drivers/i2c/adm1027/Makefile.inc trunk/src/drivers/i2c/adt7463/Kconfig trunk/src/drivers/i2c/adt7463/Makefile.inc trunk/src/drivers/i2c/i2cmux/Kconfig trunk/src/drivers/i2c/i2cmux/Makefile.inc trunk/src/drivers/i2c/i2cmux2/Kconfig trunk/src/drivers/i2c/i2cmux2/Makefile.inc trunk/src/drivers/i2c/lm63/Kconfig trunk/src/drivers/i2c/lm63/Makefile.inc trunk/src/drivers/sil/3114/Kconfig trunk/src/drivers/sil/Kconfig trunk/src/drivers/sil/Makefile.inc trunk/src/drivers/trident/Kconfig trunk/src/drivers/trident/Makefile.inc trunk/src/drivers/trident/blade3d/Kconfig trunk/src/drivers/trident/blade3d/Makefile.inc Modified: trunk/src/Kconfig trunk/src/drivers/Kconfig trunk/src/drivers/Makefile.inc Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Fri Apr 15 02:19:27 2011 (r6502) +++ trunk/src/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -157,9 +157,6 @@ bool default n -config ATI_RAGE_XL - bool - source src/console/Kconfig config HAVE_ACPI_RESUME Modified: trunk/src/drivers/Kconfig ============================================================================== --- trunk/src/drivers/Kconfig Fri Apr 15 02:19:27 2011 (r6502) +++ trunk/src/drivers/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -17,13 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config DRIVERS_SIL_3114 - bool "Silicon Image SIL3114" - default n - help - It sets PCI class to IDE compatible native mode, allowing - SeaBIOS, FILO etc... to boot from it. - - +source src/drivers/ati/Kconfig source src/drivers/dec/Kconfig +source src/drivers/emulation/Kconfig +source src/drivers/generic/Kconfig +source src/drivers/i2c/Kconfig +source src/drivers/sil/Kconfig +source src/drivers/trident/Kconfig Modified: trunk/src/drivers/Makefile.inc ============================================================================== --- trunk/src/drivers/Makefile.inc Fri Apr 15 02:19:27 2011 (r6502) +++ trunk/src/drivers/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -17,19 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +subdirs-y += ati subdirs-y += dec - -# should these be cleaned up to behave like all other subdirectories? - -subdirs-y += ati/ragexl -subdirs-y += emulation/qemu -subdirs-y += generic/debug -subdirs-y += i2c/adm1026 -subdirs-y += i2c/adm1027 -subdirs-y += i2c/adt7463 -subdirs-y += i2c/i2cmux -subdirs-y += i2c/i2cmux2 -subdirs-y += i2c/lm63 -subdirs-y += sil/3114 -subdirs-y += trident/blade3d +subdirs-y += emulation +subdirs-y += generic +subdirs-y += i2c +subdirs-y += sil +subdirs-y += trident Added: trunk/src/drivers/ati/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/ati/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +source src/drivers/ati/ragexl/Kconfig Added: trunk/src/drivers/ati/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/ati/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +subdirs-y += ragexl Added: trunk/src/drivers/ati/ragexl/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/ati/ragexl/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +config ATI_RAGE_XL + bool Added: trunk/src/drivers/emulation/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/emulation/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +source src/drivers/emulation/qemu/Kconfig + Added: trunk/src/drivers/emulation/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/emulation/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +subdirs-y += qemu Added: trunk/src/drivers/emulation/qemu/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/emulation/qemu/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +config DRIVERS_EMULATION_QEMU + bool Added: trunk/src/drivers/emulation/qemu/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/emulation/qemu/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_EMULATION_QEMU) += init.c Added: trunk/src/drivers/generic/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/generic/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +source src/drivers/generic/debug/Kconfig + Added: trunk/src/drivers/generic/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/generic/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +subdirs-y += debug Added: trunk/src/drivers/generic/debug/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/generic/debug/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +config DRIVERS_GENERIC_DEBUG + bool Added: trunk/src/drivers/i2c/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,6 @@ +source src/drivers/i2c/adm1026/Kconfig +source src/drivers/i2c/adm1027/Kconfig +source src/drivers/i2c/adt7463/Kconfig +source src/drivers/i2c/i2cmux/Kconfig +source src/drivers/i2c/i2cmux2/Kconfig +source src/drivers/i2c/lm63/Kconfig Added: trunk/src/drivers/i2c/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,6 @@ +subdirs-y += adm1026 +subdirs-y += adm1027 +subdirs-y += adt7463 +subdirs-y += i2cmux +subdirs-y += i2cmux2 +subdirs-y += lm63 Added: trunk/src/drivers/i2c/adm1026/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/adm1026/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +config DRIVERS_I2C_ADM1026 + bool Added: trunk/src/drivers/i2c/adm1026/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/adm1026/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_I2C_ADM1026) += adm1026.c Added: trunk/src/drivers/i2c/adm1027/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/adm1027/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +config DRIVERS_I2C_ADM1027 + bool Added: trunk/src/drivers/i2c/adm1027/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/adm1027/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_I2C_ADM1027) += adm1027.c Added: trunk/src/drivers/i2c/adt7463/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/adt7463/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +config DRIVERS_I2C_ADT7463 + bool Added: trunk/src/drivers/i2c/adt7463/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/adt7463/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_I2C_ADT7463) += adt7463.c Added: trunk/src/drivers/i2c/i2cmux/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/i2cmux/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +config DRIVERS_I2C_I2CMUX + bool Added: trunk/src/drivers/i2c/i2cmux/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/i2cmux/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_I2C_I2CMUX) += i2cmux.c Added: trunk/src/drivers/i2c/i2cmux2/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/i2cmux2/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +config DRIVERS_I2C_I2CMUX2 + bool Added: trunk/src/drivers/i2c/i2cmux2/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/i2cmux2/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_I2C_I2CMUX2) += i2cmux2.c Added: trunk/src/drivers/i2c/lm63/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/lm63/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +config DRIVERS_I2C_LM63 + bool Added: trunk/src/drivers/i2c/lm63/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/i2c/lm63/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_I2C_LM63) += lm63.c Added: trunk/src/drivers/sil/3114/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/sil/3114/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,8 @@ +config DRIVERS_SIL_3114 + bool "Silicon Image SIL3114" + default n + help + It sets PCI class to IDE compatible native mode, allowing + SeaBIOS, FILO etc... to boot from it. + + Added: trunk/src/drivers/sil/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/sil/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,8 @@ +config DRIVERS_SIL_3114 + bool "Silicon Image SIL3114" + default n + help + It sets PCI class to IDE compatible native mode, allowing + SeaBIOS, FILO etc... to boot from it. + + Added: trunk/src/drivers/sil/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/sil/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +subdirs-y += 3114 Added: trunk/src/drivers/trident/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/trident/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +source src/drivers/trident/blade3d/Kconfig + Added: trunk/src/drivers/trident/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/trident/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +subdirs-y += blade3d Added: trunk/src/drivers/trident/blade3d/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/trident/blade3d/Kconfig Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1,2 @@ +config DRIVERS_TRIDENT_BLADE3D + bool Added: trunk/src/drivers/trident/blade3d/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/trident/blade3d/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_TRIDENT_BLADE3D) += blade3d.c From svn at coreboot.org Fri Apr 15 05:34:06 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 05:34:06 +0200 Subject: [coreboot] [commit] r6504 - in trunk: payloads/external/FILO src src/arch/x86 Message-ID: Author: stepan Date: Fri Apr 15 05:34:05 2011 New Revision: 6504 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6504 Log: add FILO easy payload option Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Added: trunk/payloads/external/FILO/ trunk/payloads/external/FILO/Makefile.inc Modified: trunk/src/Kconfig trunk/src/arch/x86/Makefile.inc Added: trunk/payloads/external/FILO/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/payloads/external/FILO/Makefile.inc Fri Apr 15 05:34:05 2011 (r6504) @@ -0,0 +1,43 @@ +TAG-$(CONFIG_FILO_MASTER)= +NAME-$(CONFIG_FILO_MASTER)=HEAD +TAG-$(CONFIG_FILO_STABLE)=-r 139 +NAME-$(CONFIG_FILO_STABLE)=STABLE + +unexport KCONFIG_AUTOCONFIG + +all: filo + +checkout: + echo " SVN FILO $(NAME-y)" + test -d filo || \ + svn co svn://coreboot.org/filo/trunk/filo $(TAG-y) + cd filo; svn update $(TAG-y) + +config: libpayload + echo " CONFIG FILO $(NAME-y)" + $(MAKE) -C filo defconfig + echo "CONFIG_COREBOOT=y" >> filo/.config + echo "CONFIG_DEBUG_SERIAL=y" >> filo/.config + echo "CONFIG_COREBOOT_FLASH=y" >> filo/.config + echo "CONFIG_LZMA=y" >> filo/.config + echo "CONFIG_FLASH_FLOPPY=y" >> filo/.config + echo "CONFIG_VGAHOOKS=y" >> filo/.config + # This shows how to force a previously set .config option *off* + #echo "# CONFIG_SMBIOS is not set" >> filo/.config + +filo: config + echo " MAKE FILO $(NAME-y)" + $(MAKE) -C filo + +libpayload: checkout + cd ../../libpayload && $(MAKE) defconfig && \ + $(MAKE) && $(MAKE) DESTDIR=../external/FILO/filo/build install + +clean: + test -d filo && $(MAKE) -C filo clean || exit 0 + +distclean: + rm -rf filo + +.PHONY: checkout config filo clean distclean + Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Fri Apr 15 05:30:03 2011 (r6503) +++ trunk/src/Kconfig Fri Apr 15 05:34:05 2011 (r6504) @@ -358,6 +358,15 @@ See http://coreboot.org/Payloads for more information. +config PAYLOAD_FILO + bool "FILO" + help + Select this option if you want to build a coreboot image + with a FILO payload. If you don't know what this is + about, just leave it enabled. + + See http://coreboot.org/Payloads for more information. + endchoice choice @@ -375,6 +384,21 @@ Newest SeaBIOS version endchoice +choice + prompt "FILO version" + default FILO_STABLE + depends on PAYLOAD_FILO + +config FILO_STABLE + bool "0.6.0" + help + Stable FILO version +config FILO_MASTER + bool "HEAD" + help + Newest FILO version +endchoice + config PAYLOAD_FILE string "Payload path and filename" depends on PAYLOAD_ELF @@ -386,11 +410,15 @@ depends on PAYLOAD_SEABIOS default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +config PAYLOAD_FILE + depends on PAYLOAD_FILO + default "payloads/external/FILO/filo/build/filo.elf" + # TODO: Defined if no payload? Breaks build? config COMPRESSED_PAYLOAD_LZMA bool "Use LZMA compression for payloads" default y - depends on PAYLOAD_ELF || PAYLOAD_SEABIOS + depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO help In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm. Modified: trunk/src/arch/x86/Makefile.inc ============================================================================== --- trunk/src/arch/x86/Makefile.inc Fri Apr 15 05:30:03 2011 (r6503) +++ trunk/src/arch/x86/Makefile.inc Fri Apr 15 05:34:05 2011 (r6504) @@ -43,6 +43,9 @@ ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) COREBOOT_ROM_DEPENDENCIES+=seabios endif +ifeq ($(CONFIG_PAYLOAD_FILO),y) +COREBOOT_ROM_DEPENDENCIES+=filo +endif ifeq ($(CONFIG_AP_CODE_IN_CAR),y) COREBOOT_ROM_DEPENDENCIES+=$(obj)/coreboot_ap endif @@ -58,7 +61,7 @@ $(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); ) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL) +$(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $(prebuilt-files) $(CBFSTOOL) rm -f $@ $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock $(prebuild-files) @@ -86,6 +89,10 @@ @printf " PAYLOAD SeaBIOS (internal, compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" $(CBFSTOOL) $@.tmp add-payload $(CONFIG_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) endif +ifeq ($(CONFIG_PAYLOAD_FILO),y) + @printf " PAYLOAD FILO (internal, compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" + $(CBFSTOOL) $@.tmp add-payload $(CONFIG_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) +endif ifeq ($(CONFIG_GEODE_VSA_FILE),y) @printf " VSA $(CONFIG_VSA_FILENAME)\n" $(OBJCOPY) --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 $(CONFIG_VSA_FILENAME) $(obj)/vsa.o @@ -283,4 +290,11 @@ OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) +filo: + $(MAKE) -C payloads/external/FILO -f Makefile.inc \ + HOSTCC="$(HOSTCC)" \ + CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ + OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ + CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \ + CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) From svn at coreboot.org Fri Apr 15 05:58:17 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 05:58:17 +0200 Subject: [coreboot] build service results for r6503 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6503 to the coreboot repository. This caused the following changes: Change Log: Handle drivers/ equally to any other sub directory. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6503&device=inagua&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6503&device=persimmon&vendor=amd&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6503&device=e350m1&vendor=asrock&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Fri Apr 15 06:12:04 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 06:12:04 +0200 Subject: [coreboot] [commit] r6505 - trunk/src/arch/x86/init Message-ID: Author: stepan Date: Fri Apr 15 06:12:03 2011 New Revision: 6505 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6505 Log: comment cosmetics in bootblock.ld Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/arch/x86/init/bootblock.ld Modified: trunk/src/arch/x86/init/bootblock.ld ============================================================================== --- trunk/src/arch/x86/init/bootblock.ld Fri Apr 15 05:34:05 2011 (r6504) +++ trunk/src/arch/x86/init/bootblock.ld Fri Apr 15 06:12:03 2011 (r6505) @@ -27,7 +27,7 @@ { . = CONFIG_ROMBASE; - /* cut _start into last 64k*/ + /* cut _start into last 64k */ _x = .; . = (_x < CONFIG_ROMBASE) ? (CONFIG_ROMBASE) : _x; From stefan.reinauer at coreboot.org Fri Apr 15 06:14:27 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Thu, 14 Apr 2011 21:14:27 -0700 Subject: [coreboot] [PATCH] improve bootblock handling Message-ID: <4DA7C623.8050901@coreboot.org> See patch -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: cpu_bootblock.diff URL: From svn at coreboot.org Fri Apr 15 06:30:56 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 06:30:56 +0200 Subject: [coreboot] build service results for r6504 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6504 to the coreboot repository. This caused the following changes: Change Log: add FILO easy payload option Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:bimini_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=bimini_fam10&vendor=amd&num=2 Compilation of amd:dbm690t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=dbm690t&vendor=amd&num=2 Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=inagua&vendor=amd&num=2 Compilation of amd:mahogany has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=mahogany&vendor=amd&num=2 Compilation of amd:mahogany_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=mahogany_fam10&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=persimmon&vendor=amd&num=2 Compilation of amd:pistachio has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=pistachio&vendor=amd&num=2 Compilation of amd:serengeti_cheetah has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=serengeti_cheetah&vendor=amd&num=2 Compilation of amd:serengeti_cheetah_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=serengeti_cheetah_fam10&vendor=amd&num=2 Compilation of amd:tilapia_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=tilapia_fam10&vendor=amd&num=2 Compilation of arima:hdama has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=hdama&vendor=arima&num=2 Compilation of asrock:939a785gmh has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=939a785gmh&vendor=asrock&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=e350m1&vendor=asrock&num=2 Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=a8n_e&vendor=asus&num=2 Compilation of asus:a8v-e_deluxe has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=a8v-e_deluxe&vendor=asus&num=2 Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=a8v-e_se&vendor=asus&num=2 Compilation of asus:m2n-e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=m2n-e&vendor=asus&num=2 Compilation of asus:m2v has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=m2v&vendor=asus&num=2 Compilation of asus:m2v-mx_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=m2v-mx_se&vendor=asus&num=2 Compilation of asus:m4a78-em has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=m4a78-em&vendor=asus&num=2 Compilation of asus:m4a785-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=m4a785-m&vendor=asus&num=2 Compilation of asus:mew-vm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=mew-vm&vendor=asus&num=2 Compilation of bcom:winnetp680 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=winnetp680&vendor=bcom&num=2 Compilation of broadcom:blast has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=blast&vendor=broadcom&num=2 Compilation of dell:s1850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s1850&vendor=dell&num=2 Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=adl855pc&vendor=digitallogic&num=2 Compilation of digitallogic:msm586seg has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=msm586seg&vendor=digitallogic&num=2 Compilation of emulation:qemu-x86 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=qemu-x86&vendor=emulation&num=2 Compilation of getac:p470 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=p470&vendor=getac&num=2 Compilation of gigabyte:ga_2761gxdk has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=ga_2761gxdk&vendor=gigabyte&num=2 Compilation of gigabyte:m57sli has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=m57sli&vendor=gigabyte&num=2 Compilation of gigabyte:ma785gmt has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=ma785gmt&vendor=gigabyte&num=2 Compilation of gigabyte:ma78gm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=ma78gm&vendor=gigabyte&num=2 Compilation of hp:dl145_g1 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=dl145_g1&vendor=hp&num=2 Compilation of hp:dl145_g3 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=dl145_g3&vendor=hp&num=2 Compilation of hp:dl165_g6_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=dl165_g6_fam10&vendor=hp&num=2 Compilation of ibase:mb899 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=mb899&vendor=ibase&num=2 Compilation of ibm:e325 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=e325&vendor=ibm&num=2 Compilation of ibm:e326 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=e326&vendor=ibm&num=2 Compilation of iei:juki-511p has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=juki-511p&vendor=iei&num=2 Compilation of iei:kino-780am2-fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=kino-780am2-fam10&vendor=iei&num=2 Compilation of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=nova4899r&vendor=iei&num=2 Compilation of intel:d945gclf has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=d945gclf&vendor=intel&num=2 Compilation of intel:eagleheights has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=eagleheights&vendor=intel&num=2 Compilation of intel:jarrell has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=jarrell&vendor=intel&num=2 Compilation of iwill:dk8_htx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=dk8_htx&vendor=iwill&num=2 Compilation of iwill:dk8s2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=dk8s2&vendor=iwill&num=2 Compilation of iwill:dk8x has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=dk8x&vendor=iwill&num=2 Compilation of jetway:j7f24 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=j7f24&vendor=jetway&num=2 Compilation of jetway:pa78vm5 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=pa78vm5&vendor=jetway&num=2 Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=986lcd-m&vendor=kontron&num=2 Compilation of kontron:kt690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=kt690&vendor=kontron&num=2 Compilation of lanner:em8510 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=em8510&vendor=lanner&num=2 Compilation of lenovo:x60 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=x60&vendor=lenovo&num=2 Compilation of msi:ms7135 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=ms7135&vendor=msi&num=2 Compilation of msi:ms7260 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=ms7260&vendor=msi&num=2 Compilation of msi:ms9185 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=ms9185&vendor=msi&num=2 Compilation of msi:ms9282 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=ms9282&vendor=msi&num=2 Compilation of msi:ms9652_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=ms9652_fam10&vendor=msi&num=2 Compilation of newisys:khepri has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=khepri&vendor=newisys&num=2 Compilation of nvidia:l1_2pvv has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=l1_2pvv&vendor=nvidia&num=2 Compilation of roda:rk886ex has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=rk886ex&vendor=roda&num=2 Compilation of sunw:ultra40 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=ultra40&vendor=sunw&num=2 Compilation of supermicro:h8dme has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=h8dme&vendor=supermicro&num=2 Compilation of supermicro:h8dmr has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=h8dmr&vendor=supermicro&num=2 Compilation of supermicro:h8dmr_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=h8dmr_fam10&vendor=supermicro&num=2 Compilation of supermicro:h8qme_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=h8qme_fam10&vendor=supermicro&num=2 Compilation of supermicro:h8scm_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=h8scm_fam10&vendor=supermicro&num=2 Compilation of supermicro:x6dai_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=x6dai_g&vendor=supermicro&num=2 Compilation of supermicro:x6dhe_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=x6dhe_g&vendor=supermicro&num=2 Compilation of supermicro:x6dhe_g2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=x6dhe_g2&vendor=supermicro&num=2 Compilation of supermicro:x6dhr_ig has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=x6dhr_ig&vendor=supermicro&num=2 Compilation of supermicro:x6dhr_ig2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=x6dhr_ig2&vendor=supermicro&num=2 Compilation of technexion:tim5690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=tim5690&vendor=technexion&num=2 Compilation of technexion:tim8690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=tim8690&vendor=technexion&num=2 Compilation of technologic:ts5300 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=ts5300&vendor=technologic&num=2 Compilation of tyan:s2735 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2735&vendor=tyan&num=2 Compilation of tyan:s2850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2850&vendor=tyan&num=2 Compilation of tyan:s2875 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2875&vendor=tyan&num=2 Compilation of tyan:s2880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2880&vendor=tyan&num=2 Compilation of tyan:s2881 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2881&vendor=tyan&num=2 Compilation of tyan:s2882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2882&vendor=tyan&num=2 Compilation of tyan:s2885 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2885&vendor=tyan&num=2 Compilation of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2891&vendor=tyan&num=2 Compilation of tyan:s2892 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2892&vendor=tyan&num=2 Compilation of tyan:s2895 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2895&vendor=tyan&num=2 Compilation of tyan:s2912 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2912&vendor=tyan&num=2 Compilation of tyan:s2912_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s2912_fam10&vendor=tyan&num=2 Compilation of tyan:s4880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s4880&vendor=tyan&num=2 Compilation of tyan:s4882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=s4882&vendor=tyan&num=2 Compilation of via:epia has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=epia&vendor=via&num=2 Compilation of via:epia-cn has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=epia-cn&vendor=via&num=2 Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=epia-m&vendor=via&num=2 Compilation of via:epia-m700 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=epia-m700&vendor=via&num=2 Compilation of via:epia-n has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=epia-n&vendor=via&num=2 Compilation of via:pc2500e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=pc2500e&vendor=via&num=2 Compilation of via:vt8454c has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6504&device=vt8454c&vendor=via&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Fri Apr 15 06:58:12 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 06:58:12 +0200 Subject: [coreboot] build service results for r6505 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6505 to the coreboot repository. This caused the following changes: Change Log: comment cosmetics in bootblock.ld Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:bimini_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=bimini_fam10&vendor=amd&num=2 Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=dbm690t&vendor=amd&num=2 Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=inagua&vendor=amd&num=2 Compilation of amd:mahogany is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=mahogany&vendor=amd&num=2 Compilation of amd:mahogany_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=mahogany_fam10&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=persimmon&vendor=amd&num=2 Compilation of amd:pistachio is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=pistachio&vendor=amd&num=2 Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=serengeti_cheetah&vendor=amd&num=2 Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=serengeti_cheetah_fam10&vendor=amd&num=2 Compilation of amd:tilapia_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=tilapia_fam10&vendor=amd&num=2 Compilation of arima:hdama is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=hdama&vendor=arima&num=2 Compilation of asrock:939a785gmh is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=939a785gmh&vendor=asrock&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=e350m1&vendor=asrock&num=2 Compilation of asus:a8n_e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=a8n_e&vendor=asus&num=2 Compilation of asus:a8v-e_deluxe is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=a8v-e_deluxe&vendor=asus&num=2 Compilation of asus:a8v-e_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=a8v-e_se&vendor=asus&num=2 Compilation of asus:m2n-e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=m2n-e&vendor=asus&num=2 Compilation of asus:m2v is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=m2v&vendor=asus&num=2 Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=m2v-mx_se&vendor=asus&num=2 Compilation of asus:m4a78-em is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=m4a78-em&vendor=asus&num=2 Compilation of asus:m4a785-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=m4a785-m&vendor=asus&num=2 Compilation of asus:mew-vm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=mew-vm&vendor=asus&num=2 Compilation of bcom:winnetp680 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=winnetp680&vendor=bcom&num=2 Compilation of broadcom:blast is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=blast&vendor=broadcom&num=2 Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s1850&vendor=dell&num=2 Compilation of digitallogic:adl855pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=adl855pc&vendor=digitallogic&num=2 Compilation of digitallogic:msm586seg is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=msm586seg&vendor=digitallogic&num=2 Compilation of emulation:qemu-x86 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=qemu-x86&vendor=emulation&num=2 Compilation of getac:p470 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=p470&vendor=getac&num=2 Compilation of gigabyte:ga_2761gxdk is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=ga_2761gxdk&vendor=gigabyte&num=2 Compilation of gigabyte:m57sli is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=m57sli&vendor=gigabyte&num=2 Compilation of gigabyte:ma785gmt is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=ma785gmt&vendor=gigabyte&num=2 Compilation of gigabyte:ma78gm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=ma78gm&vendor=gigabyte&num=2 Compilation of hp:dl145_g1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=dl145_g1&vendor=hp&num=2 Compilation of hp:dl145_g3 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=dl145_g3&vendor=hp&num=2 Compilation of hp:dl165_g6_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=dl165_g6_fam10&vendor=hp&num=2 Compilation of ibase:mb899 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=mb899&vendor=ibase&num=2 Compilation of ibm:e325 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=e325&vendor=ibm&num=2 Compilation of ibm:e326 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=e326&vendor=ibm&num=2 Compilation of iei:juki-511p is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=juki-511p&vendor=iei&num=2 Compilation of iei:kino-780am2-fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=kino-780am2-fam10&vendor=iei&num=2 Compilation of iei:nova4899r is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=nova4899r&vendor=iei&num=2 Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=d945gclf&vendor=intel&num=2 Compilation of intel:eagleheights is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=eagleheights&vendor=intel&num=2 Compilation of intel:jarrell is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=jarrell&vendor=intel&num=2 Compilation of iwill:dk8_htx is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=dk8_htx&vendor=iwill&num=2 Compilation of iwill:dk8s2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=dk8s2&vendor=iwill&num=2 Compilation of iwill:dk8x is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=dk8x&vendor=iwill&num=2 Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=j7f24&vendor=jetway&num=2 Compilation of jetway:pa78vm5 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=pa78vm5&vendor=jetway&num=2 Compilation of kontron:986lcd-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=986lcd-m&vendor=kontron&num=2 Compilation of kontron:kt690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=kt690&vendor=kontron&num=2 Compilation of lanner:em8510 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=em8510&vendor=lanner&num=2 Compilation of lenovo:x60 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=x60&vendor=lenovo&num=2 Compilation of msi:ms7135 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=ms7135&vendor=msi&num=2 Compilation of msi:ms7260 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=ms7260&vendor=msi&num=2 Compilation of msi:ms9185 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=ms9185&vendor=msi&num=2 Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=ms9282&vendor=msi&num=2 Compilation of msi:ms9652_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=ms9652_fam10&vendor=msi&num=2 Compilation of newisys:khepri is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=khepri&vendor=newisys&num=2 Compilation of nvidia:l1_2pvv is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=l1_2pvv&vendor=nvidia&num=2 Compilation of roda:rk886ex is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=rk886ex&vendor=roda&num=2 Compilation of sunw:ultra40 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=ultra40&vendor=sunw&num=2 Compilation of supermicro:h8dme is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=h8dme&vendor=supermicro&num=2 Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=h8dmr&vendor=supermicro&num=2 Compilation of supermicro:h8dmr_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=h8dmr_fam10&vendor=supermicro&num=2 Compilation of supermicro:h8qme_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=h8qme_fam10&vendor=supermicro&num=2 Compilation of supermicro:h8scm_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=h8scm_fam10&vendor=supermicro&num=2 Compilation of supermicro:x6dai_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=x6dai_g&vendor=supermicro&num=2 Compilation of supermicro:x6dhe_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=x6dhe_g&vendor=supermicro&num=2 Compilation of supermicro:x6dhe_g2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=x6dhe_g2&vendor=supermicro&num=2 Compilation of supermicro:x6dhr_ig is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=x6dhr_ig&vendor=supermicro&num=2 Compilation of supermicro:x6dhr_ig2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=x6dhr_ig2&vendor=supermicro&num=2 Compilation of technexion:tim5690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=tim5690&vendor=technexion&num=2 Compilation of technexion:tim8690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=tim8690&vendor=technexion&num=2 Compilation of technologic:ts5300 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=ts5300&vendor=technologic&num=2 Compilation of tyan:s2735 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2735&vendor=tyan&num=2 Compilation of tyan:s2850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2850&vendor=tyan&num=2 Compilation of tyan:s2875 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2875&vendor=tyan&num=2 Compilation of tyan:s2880 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2880&vendor=tyan&num=2 Compilation of tyan:s2881 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2881&vendor=tyan&num=2 Compilation of tyan:s2882 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2882&vendor=tyan&num=2 Compilation of tyan:s2885 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2885&vendor=tyan&num=2 Compilation of tyan:s2891 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2891&vendor=tyan&num=2 Compilation of tyan:s2892 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2892&vendor=tyan&num=2 Compilation of tyan:s2895 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2895&vendor=tyan&num=2 Compilation of tyan:s2912 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2912&vendor=tyan&num=2 Compilation of tyan:s2912_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s2912_fam10&vendor=tyan&num=2 Compilation of tyan:s4880 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s4880&vendor=tyan&num=2 Compilation of tyan:s4882 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=s4882&vendor=tyan&num=2 Compilation of via:epia is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=epia&vendor=via&num=2 Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=epia-cn&vendor=via&num=2 Compilation of via:epia-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=epia-m&vendor=via&num=2 Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=epia-m700&vendor=via&num=2 Compilation of via:epia-n is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=epia-n&vendor=via&num=2 Compilation of via:pc2500e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=pc2500e&vendor=via&num=2 Compilation of via:vt8454c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6505&device=vt8454c&vendor=via&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Fri Apr 15 11:01:42 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 11:01:42 +0200 Subject: [coreboot] [commit] r6506 - trunk/src/arch/x86 Message-ID: Author: stepan Date: Fri Apr 15 11:01:42 2011 New Revision: 6506 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6506 Log: sorry for breaking the tree. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/arch/x86/Makefile.inc Modified: trunk/src/arch/x86/Makefile.inc ============================================================================== --- trunk/src/arch/x86/Makefile.inc Fri Apr 15 06:12:03 2011 (r6505) +++ trunk/src/arch/x86/Makefile.inc Fri Apr 15 11:01:42 2011 (r6506) @@ -61,7 +61,7 @@ $(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); ) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $(prebuilt-files) $(CBFSTOOL) +$(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL) rm -f $@ $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock $(prebuild-files) From svn at coreboot.org Fri Apr 15 11:31:55 2011 From: svn at coreboot.org (repository service) Date: Fri, 15 Apr 2011 11:31:55 +0200 Subject: [coreboot] build service results for r6506 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6506 to the coreboot repository. This caused the following changes: Change Log: sorry for breaking the tree. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:bimini_fam10 has been fixed Compilation of amd:dbm690t has been fixed Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6506&device=inagua&vendor=amd&num=2 Compilation of amd:mahogany has been fixed Compilation of amd:mahogany_fam10 has been fixed Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6506&device=persimmon&vendor=amd&num=2 Compilation of amd:pistachio has been fixed Compilation of amd:serengeti_cheetah has been fixed Compilation of amd:serengeti_cheetah_fam10 has been fixed Compilation of amd:tilapia_fam10 has been fixed Compilation of arima:hdama has been fixed Compilation of asrock:939a785gmh has been fixed Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6506&device=e350m1&vendor=asrock&num=2 Compilation of asus:a8n_e has been fixed Compilation of asus:a8v-e_deluxe has been fixed Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2n-e has been fixed Compilation of asus:m2v has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of asus:m4a78-em has been fixed Compilation of asus:m4a785-m has been fixed Compilation of asus:mew-vm has been fixed Compilation of bcom:winnetp680 has been fixed Compilation of broadcom:blast has been fixed Compilation of dell:s1850 has been fixed Compilation of digitallogic:adl855pc has been fixed Compilation of digitallogic:msm586seg has been fixed Compilation of emulation:qemu-x86 has been fixed Compilation of getac:p470 has been fixed Compilation of gigabyte:ga_2761gxdk has been fixed Compilation of gigabyte:m57sli has been fixed Compilation of gigabyte:ma785gmt has been fixed Compilation of gigabyte:ma78gm has been fixed Compilation of hp:dl145_g1 has been fixed Compilation of hp:dl145_g3 has been fixed Compilation of hp:dl165_g6_fam10 has been fixed Compilation of ibase:mb899 has been fixed Compilation of ibm:e325 has been fixed Compilation of ibm:e326 has been fixed Compilation of iei:juki-511p has been fixed Compilation of iei:kino-780am2-fam10 has been fixed Compilation of iei:nova4899r has been fixed Compilation of intel:d945gclf has been fixed Compilation of intel:eagleheights has been fixed Compilation of intel:jarrell has been fixed Compilation of iwill:dk8_htx has been fixed Compilation of iwill:dk8s2 has been fixed Compilation of iwill:dk8x has been fixed Compilation of jetway:j7f24 has been fixed Compilation of jetway:pa78vm5 has been fixed Compilation of kontron:986lcd-m has been fixed Compilation of kontron:kt690 has been fixed Compilation of lanner:em8510 has been fixed Compilation of lenovo:x60 has been fixed Compilation of msi:ms7135 has been fixed Compilation of msi:ms7260 has been fixed Compilation of msi:ms9185 has been fixed Compilation of msi:ms9282 has been fixed Compilation of msi:ms9652_fam10 has been fixed Compilation of newisys:khepri has been fixed Compilation of nvidia:l1_2pvv has been fixed Compilation of roda:rk886ex has been fixed Compilation of sunw:ultra40 has been fixed Compilation of supermicro:h8dme has been fixed Compilation of supermicro:h8dmr has been fixed Compilation of supermicro:h8dmr_fam10 has been fixed Compilation of supermicro:h8qme_fam10 has been fixed Compilation of supermicro:h8scm_fam10 has been fixed Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed Compilation of technexion:tim5690 has been fixed Compilation of technexion:tim8690 has been fixed Compilation of technologic:ts5300 has been fixed Compilation of tyan:s2735 has been fixed Compilation of tyan:s2850 has been fixed Compilation of tyan:s2875 has been fixed Compilation of tyan:s2880 has been fixed Compilation of tyan:s2881 has been fixed Compilation of tyan:s2882 has been fixed Compilation of tyan:s2885 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed Compilation of tyan:s2912 has been fixed Compilation of tyan:s2912_fam10 has been fixed Compilation of tyan:s4880 has been fixed Compilation of tyan:s4882 has been fixed Compilation of via:epia has been fixed Compilation of via:epia-cn has been fixed Compilation of via:epia-m has been fixed Compilation of via:epia-m700 has been fixed Compilation of via:epia-n has been fixed Compilation of via:pc2500e has been fixed Compilation of via:vt8454c has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From marcj303 at gmail.com Fri Apr 15 17:25:00 2011 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 15 Apr 2011 09:25:00 -0600 Subject: [coreboot] [PATCH] improve bootblock handling In-Reply-To: <4DA7C623.8050901@coreboot.org> References: <4DA7C623.8050901@coreboot.org> Message-ID: On Thu, Apr 14, 2011 at 10:14 PM, Stefan Reinauer wrote: > See patch > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Acked-by: Marc Jones -- http://se-eng.com From marcj303 at gmail.com Fri Apr 15 20:34:09 2011 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 15 Apr 2011 12:34:09 -0600 Subject: [coreboot] [PATCH] libpayload OXPCIe 952 support In-Reply-To: <20110414200039.GA28147@coreboot.org> References: <20110414200039.GA28147@coreboot.org> Message-ID: On Thu, Apr 14, 2011 at 2:00 PM, Stefan Reinauer wrote: > See patch. > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Acked-by: Marc Jones Can you put something about this card on the wiki. It would be handy for others that don't have a legacy serial port. Marc -- http://se-eng.com From svn at coreboot.org Sat Apr 16 02:09:54 2011 From: svn at coreboot.org (repository service) Date: Sat, 16 Apr 2011 02:09:54 +0200 Subject: [coreboot] [commit] r6507 - in trunk/src/arch/x86: include include/arch init Message-ID: Author: stepan Date: Sat Apr 16 02:09:53 2011 New Revision: 6507 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6507 Log: bootblock updates: - allow CPU to define bootblock code, too. - drop unneeded __PRE_RAM__ define - move CBFS specific code out of bootblock_common.h into cbfs.h Signed-off-by: Stefan Reinauer Acked-by: Marc Jones Added: trunk/src/arch/x86/include/arch/cbfs.h Modified: trunk/src/arch/x86/include/bootblock_common.h trunk/src/arch/x86/init/bootblock_normal.c trunk/src/arch/x86/init/bootblock_simple.c Added: trunk/src/arch/x86/include/arch/cbfs.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/x86/include/arch/cbfs.h Sat Apr 16 02:09:53 2011 (r6507) @@ -0,0 +1,26 @@ +static void *walkcbfs(char *target) +{ + void *entry; + asm volatile ( + "mov $1f, %%esp\n\t" + "jmp walkcbfs_asm\n\t" + "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp"); + return entry; +} + +/* just enough to support findstage. copied because the original version doesn't easily pass through romcc */ +struct cbfs_stage_restricted { + unsigned long compression; + unsigned long entry; // this is really 64bit, but properly endianized +}; + +static inline unsigned long findstage(char* target) +{ + return ((struct cbfs_stage_restricted *)walkcbfs(target))->entry; +} + +static inline void call(unsigned long addr, unsigned long bist) +{ + asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); +} + Modified: trunk/src/arch/x86/include/bootblock_common.h ============================================================================== --- trunk/src/arch/x86/include/bootblock_common.h Fri Apr 15 11:01:42 2011 (r6506) +++ trunk/src/arch/x86/include/bootblock_common.h Sat Apr 16 02:09:53 2011 (r6507) @@ -1,4 +1,3 @@ -#define __PRE_RAM__ #if CONFIG_LOGICAL_CPUS && \ (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT)) #include @@ -6,6 +5,11 @@ #define boot_cpu(x) 1 #endif +#ifdef CONFIG_BOOTBLOCK_CPU_INIT +#include CONFIG_BOOTBLOCK_CPU_INIT +#else +static void bootblock_cpu_init(void) { } +#endif #ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT #include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT #else @@ -17,31 +21,7 @@ static void bootblock_southbridge_init(void) { } #endif -static void *walkcbfs(char *target) -{ - void *entry; - asm volatile ( - "mov $1f, %%esp\n\t" - "jmp walkcbfs_asm\n\t" - "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp"); - return entry; -} - -/* just enough to support findstage. copied because the original version doesn't easily pass through romcc */ -struct cbfs_stage { - unsigned long compression; - unsigned long entry; // this is really 64bit, but properly endianized -}; - -static unsigned long findstage(char* target) -{ - return ((struct cbfs_stage*)walkcbfs(target))->entry; -} - -static void call(unsigned long addr, unsigned long bist) -{ - asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); -} +#include #if CONFIG_USE_OPTION_TABLE #include Modified: trunk/src/arch/x86/init/bootblock_normal.c ============================================================================== --- trunk/src/arch/x86/init/bootblock_normal.c Fri Apr 15 11:01:42 2011 (r6506) +++ trunk/src/arch/x86/init/bootblock_normal.c Sat Apr 16 02:09:53 2011 (r6507) @@ -6,6 +6,7 @@ if (boot_cpu()) { bootblock_northbridge_init(); bootblock_southbridge_init(); + bootblock_cpu_init(); } #if CONFIG_USE_OPTION_TABLE Modified: trunk/src/arch/x86/init/bootblock_simple.c ============================================================================== --- trunk/src/arch/x86/init/bootblock_simple.c Fri Apr 15 11:01:42 2011 (r6506) +++ trunk/src/arch/x86/init/bootblock_simple.c Sat Apr 16 02:09:53 2011 (r6507) @@ -5,6 +5,7 @@ if (boot_cpu()) { bootblock_northbridge_init(); bootblock_southbridge_init(); + bootblock_cpu_init(); } #if CONFIG_USE_OPTION_TABLE From stefan.reinauer at coreboot.org Sat Apr 16 02:11:54 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Sat, 16 Apr 2011 02:11:54 +0200 Subject: [coreboot] [PATCH] console/console.h cleanup In-Reply-To: <20110414214615.GA16484@coreboot.org> References: <20110414214615.GA16484@coreboot.org> Message-ID: <20110416001154.GA29678@coreboot.org> * Stefan Reinauer [110414 23:46]: > See patch > > - include usbdebug.c where appropriate > - don't do ne2k_transmit()s without actual output > > Signed-off-by: Stefan Reinauer Rudolf, you wrote some of the code initially. Can you please take a look? From svn at coreboot.org Sat Apr 16 02:13:18 2011 From: svn at coreboot.org (repository service) Date: Sat, 16 Apr 2011 02:13:18 +0200 Subject: [coreboot] [commit] r6508 - in trunk/payloads/libpayload: drivers include Message-ID: Author: stepan Date: Sat Apr 16 02:13:17 2011 New Revision: 6508 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6508 Log: Allow libpayload to use an OXPCIe 952 card on systems without onboard serial port Signed-off-by: Stefan Reinauer Acked-by: Marc Jones Modified: trunk/payloads/libpayload/drivers/serial.c trunk/payloads/libpayload/include/libpayload.h trunk/payloads/libpayload/include/sysinfo.h Modified: trunk/payloads/libpayload/drivers/serial.c ============================================================================== --- trunk/payloads/libpayload/drivers/serial.c Sat Apr 16 02:09:53 2011 (r6507) +++ trunk/payloads/libpayload/drivers/serial.c Sat Apr 16 02:13:17 2011 (r6508) @@ -32,9 +32,11 @@ #include #define IOBASE lib_sysinfo.ser_ioport +#define MEMBASE (phys_to_virt(lib_sysinfo.ser_base)) #define DIVISOR(x) (115200 / x) -void serial_hardware_init(int port, int speed, int word_bits, int parity, int stop_bits) +#ifdef CONFIG_SERIAL_SET_SPEED +static void serial_io_hardware_init(int port, int speed, int word_bits, int parity, int stop_bits) { unsigned char reg; @@ -58,6 +60,31 @@ outb(reg & ~0x80, port + 0x03); } +static void serial_mem_hardware_init(int port, int speed, int word_bits, int parity, int stop_bits) +{ + unsigned char reg; + + /* We will assume 8n1 for now. Does anyone use anything else these days? */ + + /* Disable interrupts. */ + writeb(0, MEMBASE + 0x01); + + /* Assert RTS and DTR. */ + writeb(3, MEMBASE + 0x04); + + /* Set the divisor latch. */ + reg = readb(MEMBASE + 0x03); + writeb(reg | 0x80, MEMBASE + 0x03); + + /* Write the divisor. */ + writeb(DIVISOR(speed) & 0xFF, MEMBASE); + writeb(DIVISOR(speed) >> 8 & 0xFF, MEMBASE + 1); + + /* Restore the previous value of the divisor. */ + writeb(reg & ~0x80, MEMBASE + 0x03); +} +#endif + static struct console_input_driver consin = { .havekey = serial_havechar, .getchar = serial_getchar @@ -69,31 +96,84 @@ void serial_init(void) { + pcidev_t oxpcie_dev; + if (pci_find_device(0x1415, 0xc158, &oxpcie_dev)) { + lib_sysinfo.ser_base = pci_read_resource(oxpcie_dev, 0) + 0x1000; + } else { + lib_sysinfo.ser_base = 0; + } + #ifdef CONFIG_SERIAL_SET_SPEED - serial_hardware_init(IOBASE, CONFIG_SERIAL_BAUD_RATE, 8, 0, 1); + if (lib_sysinfo.ser_base) + serial_mem_hardware_init(IOBASE, CONFIG_SERIAL_BAUD_RATE, 8, 0, 1); + else + serial_io_hardware_init(IOBASE, CONFIG_SERIAL_BAUD_RATE, 8, 0, 1); #endif console_add_input_driver(&consin); console_add_output_driver(&consout); } -void serial_putchar(unsigned int c) +static void serial_io_putchar(unsigned int c) { c &= 0xff; while ((inb(IOBASE + 0x05) & 0x20) == 0) ; outb(c, IOBASE); } -int serial_havechar(void) +static int serial_io_havechar(void) { return inb(IOBASE + 0x05) & 0x01; } -int serial_getchar(void) +static int serial_io_getchar(void) { - while (!serial_havechar()) ; + while (!serial_io_havechar()) ; return (int)inb(IOBASE); } +static void serial_mem_putchar(unsigned int c) +{ + c &= 0xff; + while ((readb(MEMBASE + 0x05) & 0x20) == 0) ; + writeb(c, MEMBASE); +} + +static int serial_mem_havechar(void) +{ + return readb(MEMBASE + 0x05) & 0x01; +} + +static int serial_mem_getchar(void) +{ + while (!serial_mem_havechar()) ; + return (int)readb(MEMBASE); +} + + +void serial_putchar(unsigned int c) +{ + if (lib_sysinfo.ser_base) + serial_mem_putchar(c); + else + serial_io_putchar(c); +} + +int serial_havechar(void) +{ + if (lib_sysinfo.ser_base) + return serial_mem_havechar(); + else + return serial_io_havechar(); +} + +int serial_getchar(void) +{ + if (lib_sysinfo.ser_base) + return serial_mem_getchar(); + else + return serial_io_getchar(); +} + /* These are thinly veiled vt100 functions used by curses */ #define VT100_CLEAR "\e[H\e[J" Modified: trunk/payloads/libpayload/include/libpayload.h ============================================================================== --- trunk/payloads/libpayload/include/libpayload.h Sat Apr 16 02:09:53 2011 (r6507) +++ trunk/payloads/libpayload/include/libpayload.h Sat Apr 16 02:13:17 2011 (r6508) @@ -153,7 +153,6 @@ * @{ */ void serial_init(void); -void serial_hardware_init(int port, int speed, int word_bits, int parity, int stop_bits); void serial_putchar(unsigned int c); int serial_havechar(void); int serial_getchar(void); Modified: trunk/payloads/libpayload/include/sysinfo.h ============================================================================== --- trunk/payloads/libpayload/include/sysinfo.h Sat Apr 16 02:09:53 2011 (r6507) +++ trunk/payloads/libpayload/include/sysinfo.h Sat Apr 16 02:13:17 2011 (r6508) @@ -36,6 +36,7 @@ struct sysinfo_t { unsigned int cpu_khz; unsigned short ser_ioport; + unsigned long ser_base; // for mmapped serial int n_memranges; From reinauer at google.com Sat Apr 16 02:15:19 2011 From: reinauer at google.com (Stefan Reinauer) Date: Sat, 16 Apr 2011 02:15:19 +0200 Subject: [coreboot] [PATCH] libpayload OXPCIe 952 support In-Reply-To: References: <20110414200039.GA28147@coreboot.org> Message-ID: <20110416001519.GB29678@coreboot.org> * Marc Jones [110415 20:34]: > Can you put something about this card on the wiki. It would be handy > for others that don't have a legacy serial port. will try to do so From svn at coreboot.org Sat Apr 16 02:38:09 2011 From: svn at coreboot.org (repository service) Date: Sat, 16 Apr 2011 02:38:09 +0200 Subject: [coreboot] build service results for r6507 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6507 to the coreboot repository. This caused the following changes: Change Log: bootblock updates: - allow CPU to define bootblock code, too. - drop unneeded __PRE_RAM__ define - move CBFS specific code out of bootblock_common.h into cbfs.h Signed-off-by: Stefan Reinauer Acked-by: Marc Jones Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6507&device=inagua&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6507&device=persimmon&vendor=amd&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6507&device=e350m1&vendor=asrock&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Sat Apr 16 03:10:41 2011 From: svn at coreboot.org (repository service) Date: Sat, 16 Apr 2011 03:10:41 +0200 Subject: [coreboot] build service results for r6508 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6508 to the coreboot repository. This caused the following changes: Change Log: Allow libpayload to use an OXPCIe 952 card on systems without onboard serial port Signed-off-by: Stefan Reinauer Acked-by: Marc Jones Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6508&device=inagua&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6508&device=persimmon&vendor=amd&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6508&device=e350m1&vendor=asrock&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From towardsoss at gmail.com Sat Apr 16 08:28:44 2011 From: towardsoss at gmail.com (Niklas Cholmkvist) Date: Sat, 16 Apr 2011 09:28:44 +0300 Subject: [coreboot] Gigabyte GA AMD E350N USB3 Board Message-ID: <4DA9371C.4040503@gmail.com> Hi Marek, did you have any luck in finding any other AMD USB3 motherboard? Are you mostly interested that it supports USB3? -- Niklas Cholmkvist Public GPG/PGP key block ID: 1024D/C09E670B Fingerprint: 8487 ECE3 8ED9 870B BB56 95E7 9AD2 946A C09E 670B Key download: https://sites.google.com/site/towardsfloss/main-page/NiklasCholmkvist.asc [Please, do not send my key to any keyserver] -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 262 bytes Desc: OpenPGP digital signature URL: From tsylla at gmail.com Sat Apr 16 11:12:26 2011 From: tsylla at gmail.com (Tom Sylla) Date: Sat, 16 Apr 2011 02:12:26 -0700 Subject: [coreboot] Gigabyte GA AMD E350N USB3 Board In-Reply-To: References: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> <20110412130805.12455.qmail@stuge.se> Message-ID: Hi Marek, I do own this board, and it is probably one of the more painful to get ported. There is no SPI header, no serial port, and it has the gigabyte dual-BIOS mechanism to deal with. I also have an MSI e350 mini-ITX board, without any of those problems, and maybe someday I will try to make a port for it. Tom On Tue, Apr 12, 2011 at 7:07 AM, Marek wrote: > Hi Peter, > > On 12.4.2011, at 15:08, Peter Stuge wrote: > >> Marek wrote: >>> with regards to recent AMD patches, >> >> Note that the patches did not include support for your mainboard. >> >> >>> I'd like to ask whether it would be possible to install coreboot on >>> Gigabyte GA AMD E350N USB3 board >>> (AMD E350, chipset FCH A50 Hudson M1, iTE 8720). >> >> The answer is, as always, no it will not work unless you make it work. >> >> The final piece of the puzzle, mainboard support, is still missing, >> but all the other 4999 pieces have been put in place for you by AMD >> and the rest of the coreboot community. > > thanks for your answer, I'm fully aware of the situation, my question was more directed to people (if there are any) who own that MB, perhaps work on coreboot support, or have considered it and abanonded it in the initial phase or even made progress but were unable to continue due to various circumstances. No answer most likely means that there isn't anyone who owns this board so far, so I just pushed all information I could find out without buying that board in case someone wants to buy one and add coreboot support for it. > > Marek > >> >> >> //Peter >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From hercares at gmail.com Sat Apr 16 12:29:17 2011 From: hercares at gmail.com (Julian Shulika) Date: Sat, 16 Apr 2011 13:29:17 +0300 Subject: [coreboot] Fwd: support for Asus L1N64 In-Reply-To: References: Message-ID: Hi,everyone. I have Asus L1N64WS/B with pair quad opteron Barcelona. I want to upgrade it for working with Shanghai core (an other owners too),but Asus engineers don't support this board more (last update was on 2009). It was one of a kind for AMD 4x4 platform based on pair of MCP55. (Tyan,Supermicro and Asus (other servers products) released new bioses for their MBs based on MCP55 for Shanghai and Istanbul cores) I wrote via email to support several times,no answer until,tried to chat with online helpers - no result.The base problem is update AGESA code. What is needed to do to add support for this MB in your project? I sent three files to subproject flashrom mailing list - dmidecode, flashrom verbose and lspci information, but any news yet. Have a nice day. http://www.asus.com/Motherboards/AMD_Socket_L1/L1N64SLI_WSB/ -------------- next part -------------- A non-text attachment was scrubbed... Name: verbose.log Type: application/octet-stream Size: 28245 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: dmi.report Type: application/octet-stream Size: 22860 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: lspci.report Type: application/octet-stream Size: 48875 bytes Desc: not available URL: From bh at udev.org Sun Apr 17 12:44:18 2011 From: bh at udev.org (Benjamin Henrion) Date: Sun, 17 Apr 2011 12:44:18 +0200 Subject: [coreboot] Recovering a bricked Alic1c with arduino+LPC? Message-ID: Hi, Does anybody has any experience with reflashing an Alix 1C with LPC? I am trying with an arduino in 3.3v and some LPC code written by Mike Stirling: http://www.zoobab.com/arduino-as-a-bios-lpc-flasher http://www.zoobab.com/alix-1c Any idea? Best, -- Benjamin Henrion FFII Brussels - +32-484-566109 - +32-2-4148403 "In July 2005, after several failed attempts to legalise software patents in Europe, the patent establishment changed its strategy. Instead of explicitly seeking to sanction the patentability of software, they are now seeking to create a central European patent court, which would establish and enforce patentability rules in their favor, without any possibility of correction by competing courts or democratically elected legislators." From svn at coreboot.org Sun Apr 17 14:54:33 2011 From: svn at coreboot.org (repository service) Date: Sun, 17 Apr 2011 14:54:33 +0200 Subject: [coreboot] [commit] r6509 - trunk/src/ec/lenovo/pmh7 Message-ID: Author: svens Date: Sun Apr 17 14:54:32 2011 New Revision: 6509 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6509 Log: PMH7: Add dock event control Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/ec/lenovo/pmh7/chip.h trunk/src/ec/lenovo/pmh7/pmh7.c trunk/src/ec/lenovo/pmh7/pmh7.h Modified: trunk/src/ec/lenovo/pmh7/chip.h ============================================================================== --- trunk/src/ec/lenovo/pmh7/chip.h Sat Apr 16 02:13:17 2011 (r6508) +++ trunk/src/ec/lenovo/pmh7/chip.h Sun Apr 17 14:54:32 2011 (r6509) @@ -5,5 +5,6 @@ struct ec_lenovo_pmh7_config { int backlight_enable:1; + int dock_event_enable:1; }; #endif Modified: trunk/src/ec/lenovo/pmh7/pmh7.c ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.c Sat Apr 16 02:13:17 2011 (r6508) +++ trunk/src/ec/lenovo/pmh7/pmh7.c Sun Apr 17 14:54:32 2011 (r6509) @@ -33,6 +33,14 @@ pmh7_register_clear_bit(0x50, 5); } +void pmh7_dock_event_enable(int onoff) +{ + if (onoff) + pmh7_register_set_bit(0x60, 3); + else + pmh7_register_clear_bit(0x60, 3); + +} void pmh7_register_set_bit(int reg, int bit) { char val; @@ -78,6 +86,7 @@ resource->gran = 5; pmh7_backlight_enable(conf->backlight_enable); + pmh7_dock_event_enable(conf->dock_event_enable); } struct chip_operations ec_lenovo_pmh7_ops = { Modified: trunk/src/ec/lenovo/pmh7/pmh7.h ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.h Sat Apr 16 02:13:17 2011 (r6508) +++ trunk/src/ec/lenovo/pmh7/pmh7.h Sun Apr 17 14:54:32 2011 (r6509) @@ -32,4 +32,5 @@ void pmh7_register_write(int reg, int val); void pmh7_backlight_enable(int onoff); +void pmh7_dock_event_enable(int onoff); #endif From svens at stackframe.org Sun Apr 17 15:07:45 2011 From: svens at stackframe.org (Sven Schnelle) Date: Sun, 17 Apr 2011 15:07:45 +0200 Subject: [coreboot] [PATCH] add ThinkPad T60 Message-ID: <871v1181r2.fsf@begreifnix.stackframe.org> Hi List, the attached patch adds support for the ThinkPad T60 to coreboot. it is diffed against the existing X60 port. Signed-off-by: Sven Schnelle -------------- next part -------------- A non-text attachment was scrubbed... Name: t60.diff Type: text/x-diff Size: 15173 bytes Desc: not available URL: From svn at coreboot.org Sun Apr 17 15:22:45 2011 From: svn at coreboot.org (repository service) Date: Sun, 17 Apr 2011 15:22:45 +0200 Subject: [coreboot] build service results for r6509 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "svens" checked in revision 6509 to the coreboot repository. This caused the following changes: Change Log: PMH7: Add dock event control Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6509&device=inagua&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6509&device=persimmon&vendor=amd&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6509&device=e350m1&vendor=asrock&num=2 If something broke during this checkin please be a pain in svens's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Sun Apr 17 16:55:21 2011 From: svn at coreboot.org (repository service) Date: Sun, 17 Apr 2011 16:55:21 +0200 Subject: [coreboot] [commit] r6510 - trunk/src/ec/lenovo/h8/acpi Message-ID: Author: svens Date: Sun Apr 17 16:55:21 2011 New Revision: 6510 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6510 Log: Lenovo H8 EC: add missing systemstatus.asl include Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/ec/lenovo/h8/acpi/ec.asl Modified: trunk/src/ec/lenovo/h8/acpi/ec.asl ============================================================================== --- trunk/src/ec/lenovo/h8/acpi/ec.asl Sun Apr 17 14:54:32 2011 (r6509) +++ trunk/src/ec/lenovo/h8/acpi/ec.asl Sun Apr 17 16:55:21 2011 (r6510) @@ -120,4 +120,5 @@ #include "lid.asl" #include "beep.asl" #include "thermal.asl" +#include "systemstatus.asl" } From svn at coreboot.org Sun Apr 17 17:22:50 2011 From: svn at coreboot.org (repository service) Date: Sun, 17 Apr 2011 17:22:50 +0200 Subject: [coreboot] build service results for r6510 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "svens" checked in revision 6510 to the coreboot repository. This caused the following changes: Change Log: Lenovo H8 EC: add missing systemstatus.asl include Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6510&device=inagua&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6510&device=persimmon&vendor=amd&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6510&device=e350m1&vendor=asrock&num=2 If something broke during this checkin please be a pain in svens's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From scott at notabs.org Sun Apr 17 23:37:12 2011 From: scott at notabs.org (Scott Duplichan) Date: Sun, 17 Apr 2011 16:37:12 -0500 Subject: [coreboot] [patch] allow new amd agesa code to skip check for globals in romstage In-Reply-To: <9D775EE5D2D9457EB887CB62A4F6FBFF@m3a78> References: <9D775EE5D2D9457EB887CB62A4F6FBFF@m3a78> Message-ID: Recently the 3 projects using the new AMD reference code have been failing the check for globals (or statics) in romstage. This causes ASRock E350M1, AMD Inagua, and AMD Persimmon builds to fail with the message "Do not use global variables in romstage". The message is working as intended. It is detecting data declared as 'static' when 'static const' was intended. The code executes correctly because it never tries to modify the data. To make reference code updates easy, it is probably best to avoid modifying the AMD provided code if possible. The following change bypasses the "Do not use global variables in romstage" check for the AMD reference code only. Signed-off-by: Scott Duplichan Index: src/arch/x86/init/bootblock.ld =================================================================== --- src/arch/x86/init/bootblock.ld (revision 6510) +++ src/arch/x86/init/bootblock.ld (working copy) @@ -48,6 +48,8 @@ *(.note) *(.comment.*) *(.note.*) - } - _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage"); + } + + CONFIG_AMD_AGESA = DEFINED(CONFIG_AMD_AGESA) ? CONFIG_AMD_AGESA : 0; + _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage"); } -------------- next part -------------- A non-text attachment was scrubbed... Name: agesa-waiver.patch Type: application/octet-stream Size: 570 bytes Desc: not available URL: From stefan.reinauer at coreboot.org Mon Apr 18 01:58:16 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Sun, 17 Apr 2011 16:58:16 -0700 Subject: [coreboot] [patch] allow new amd agesa code to skip check for globals in romstage In-Reply-To: References: <9D775EE5D2D9457EB887CB62A4F6FBFF@m3a78> Message-ID: <4DAB7E98.4030900@coreboot.org> On 4/17/11 2:37 PM, Scott Duplichan wrote: > Recently the 3 projects using the new AMD reference code have been > failing the check for globals (or statics) in romstage. This causes > ASRock E350M1, AMD Inagua, and AMD Persimmon builds to fail with the > message "Do not use global variables in romstage". The message is > working as intended. It is detecting data declared as 'static' when > 'static const' was intended. The code executes correctly because it > never tries to modify the data. > > To make reference code updates easy, it is probably best to avoid > modifying the AMD provided code if possible. The following change > bypasses the "Do not use global variables in romstage" check for > the AMD reference code only. > > Signed-off-by: Scott Duplichan I think AMD is working on a fix for this problem. However, until then: Acked-by: Stefan Reinauer From stefan.reinauer at coreboot.org Mon Apr 18 02:09:58 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Sun, 17 Apr 2011 17:09:58 -0700 Subject: [coreboot] [PATCH] add ThinkPad T60 In-Reply-To: <871v1181r2.fsf@begreifnix.stackframe.org> References: <871v1181r2.fsf@begreifnix.stackframe.org> Message-ID: <4DAB8156.4040200@coreboot.org> On 4/17/11 6:07 AM, Sven Schnelle wrote: > Hi List, > > the attached patch adds support for the ThinkPad T60 to > coreboot. it is diffed against the existing X60 port. > > Signed-off-by: Sven Schnelle > > Index: t60/Kconfig > =================================================================== > --- t60/Kconfig (revision 6509) > +++ t60/Kconfig (working copy) > > @@ -56,4 +56,28 @@ > int > default 1 > > +config TI_PCMCIA_CARDBUS_CMDR > + hex > + default 0x0107 > + > +config TI_PCMCIA_CARDBUS_CLSR > + hex > + default 0x00 > + > +config TI_PCMCIA_CARDBUS_CLTR > + hex > + default 0x40 > + > +config TI_PCMCIA_CARDBUS_BCR > + hex > + default 0x07C0 > + > +config TI_PCMCIA_CARDBUS_SCR > + hex > + default 0x08449060 > + > +config TI_PCMCIA_CARDBUS_MRR > + hex > + default 0x00007522 > + > endif Can you please put these in a .c or .h file in the mainboard directory? I don't think we should add configuration variables for single registers in Kconfig. > Index: t60/dock.c > =================================================================== > --- t60/dock.c (revision 6509) > +++ t60/dock.c (working copy) > @@ -26,8 +26,9 @@ > #include > #include > #include "dock.h" > +#include "superio/nsc/pc87384/pc87384.h" > +#include "ec/acpi/ec.h" > #include "southbridge/intel/i82801gx/i82801gx.h" > -#include "superio/nsc/pc87392/pc87392.h" > > static void dlpc_write_register(int reg, int value) > { > @@ -59,6 +60,7 @@ > dlpc_write_register(0xf1, mode); > } > > + drop new line? > + /* no GPIO events enabled for PORT0 */ > + outb(0x00, 0x1622); > + /* clear GPIO events on PORT0 */ > + outb(0xff, 0x1623); > + outb(0xff, 0x1624); > + /* no GPIO events enabled for PORT1 */ > + outb(0x00, 0x1626); Are you properly preventing the resource allocator from putting other resources on top of 0x16xx? > + outb(0x61, 0x15ec); > + return inb(0x15ee)& 1; > } > + ... and 0x15xx > Index: t60/mptable.c > =================================================================== > --- t60/mptable.c (revision 6509) > +++ t60/mptable.c (working copy) > @@ -62,9 +62,7 @@ > smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f<< 2) , 0x02, 0x17); /* LPC 0:1f.0 */ > smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f<< 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ > smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f<< 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ > - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00<< 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ > - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00<< 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ > - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00<< 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ > + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00<< 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ > > smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0); > smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1); In general it would be better to look for the appropriate devices in the system, because someone might plug in a device with a bridge on the lower buses, effectively rendering your mptable useless. MP table automation ftw! Looks great otherwise. Stefan -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Mon Apr 18 04:07:16 2011 From: svn at coreboot.org (repository service) Date: Mon, 18 Apr 2011 04:07:16 +0200 Subject: [coreboot] [commit] r6511 - trunk/util/kconfig Message-ID: Author: stepan Date: Mon Apr 18 04:07:16 2011 New Revision: 6511 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6511 Log: Emit unwritten symbols in Kconfig so we don't have to do constructs like #if defined(CONFIG_FOO) && CONFIG_FOO anymore. This was partially implemented but didn't work for symbols that were unset because of a missing dependency. Patch taken from SeaBIOS. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/util/kconfig/confdata.c Modified: trunk/util/kconfig/confdata.c ============================================================================== --- trunk/util/kconfig/confdata.c Sun Apr 17 16:55:21 2011 (r6510) +++ trunk/util/kconfig/confdata.c Mon Apr 18 04:07:16 2011 (r6511) @@ -721,8 +721,15 @@ for_all_symbols(i, sym) { sym_calc_value(sym); - if (!(sym->flags & SYMBOL_WRITE) || !sym->name) + if (!sym->name) continue; + if (!(sym->flags & SYMBOL_WRITE)) { + if (sym->type == S_BOOLEAN || sym->type == S_HEX + || sym->type == S_INT) + fprintf(out_h, "#define CONFIG_%s 0\n", + sym->name); + continue; + } switch (sym->type) { case S_BOOLEAN: case S_TRISTATE: From svn at coreboot.org Mon Apr 18 04:26:56 2011 From: svn at coreboot.org (repository service) Date: Mon, 18 Apr 2011 04:26:56 +0200 Subject: [coreboot] [commit] r6512 - trunk/src/lib Message-ID: Author: stepan Date: Mon Apr 18 04:26:56 2011 New Revision: 6512 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6512 Log: fix copy and paste errors in ne2k.c Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/lib/ne2k.c Modified: trunk/src/lib/ne2k.c ============================================================================== --- trunk/src/lib/ne2k.c Mon Apr 18 04:07:16 2011 (r6511) +++ trunk/src/lib/ne2k.c Mon Apr 18 04:26:56 2011 (r6512) @@ -444,8 +444,7 @@ return; } - -static struct device_operations si_sata_ops = { +static struct device_operations ne2k_ops = { .read_resources = read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -453,7 +452,7 @@ .scan_bus = 0, }; -static const struct pci_driver si_sata_driver __pci_driver = { +static const struct pci_driver ne2k_driver __pci_driver = { .ops = &si_sata_ops, .vendor = 0x10ec, .device = 0x8029, From svn at coreboot.org Mon Apr 18 04:34:22 2011 From: svn at coreboot.org (repository service) Date: Mon, 18 Apr 2011 04:34:22 +0200 Subject: [coreboot] build service results for r6511 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6511 to the coreboot repository. This caused the following changes: Change Log: Emit unwritten symbols in Kconfig so we don't have to do constructs like #if defined(CONFIG_FOO) && CONFIG_FOO anymore. This was partially implemented but didn't work for symbols that were unset because of a missing dependency. Patch taken from SeaBIOS. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:dbm690t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=dbm690t&vendor=amd&num=2 Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=inagua&vendor=amd&num=2 Compilation of amd:mahogany has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=mahogany&vendor=amd&num=2 Compilation of amd:mahogany_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=mahogany_fam10&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=persimmon&vendor=amd&num=2 Compilation of amd:pistachio has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=pistachio&vendor=amd&num=2 Compilation of amd:serengeti_cheetah has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=serengeti_cheetah&vendor=amd&num=2 Compilation of amd:tilapia_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=tilapia_fam10&vendor=amd&num=2 Compilation of arima:hdama has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=hdama&vendor=arima&num=2 Compilation of asrock:939a785gmh has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=939a785gmh&vendor=asrock&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=e350m1&vendor=asrock&num=2 Compilation of asus:a8v-e_deluxe has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=a8v-e_deluxe&vendor=asus&num=2 Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=a8v-e_se&vendor=asus&num=2 Compilation of asus:m2n-e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=m2n-e&vendor=asus&num=2 Compilation of asus:m2v has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=m2v&vendor=asus&num=2 Compilation of asus:m2v-mx_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=m2v-mx_se&vendor=asus&num=2 Compilation of asus:m4a78-em has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=m4a78-em&vendor=asus&num=2 Compilation of asus:m4a785-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=m4a785-m&vendor=asus&num=2 Compilation of broadcom:blast has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=blast&vendor=broadcom&num=2 Compilation of getac:p470 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=p470&vendor=getac&num=2 Compilation of gigabyte:ga_2761gxdk has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=ga_2761gxdk&vendor=gigabyte&num=2 Compilation of gigabyte:m57sli has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=m57sli&vendor=gigabyte&num=2 Compilation of gigabyte:ma785gmt has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=ma785gmt&vendor=gigabyte&num=2 Compilation of gigabyte:ma78gm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=ma78gm&vendor=gigabyte&num=2 Compilation of hp:dl145_g1 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=dl145_g1&vendor=hp&num=2 Compilation of hp:dl145_g3 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=dl145_g3&vendor=hp&num=2 Compilation of ibase:mb899 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=mb899&vendor=ibase&num=2 Compilation of ibm:e325 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=e325&vendor=ibm&num=2 Compilation of ibm:e326 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=e326&vendor=ibm&num=2 Compilation of iei:kino-780am2-fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=kino-780am2-fam10&vendor=iei&num=2 Compilation of intel:d945gclf has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=d945gclf&vendor=intel&num=2 Compilation of iwave:iWRainbowG6 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=iWRainbowG6&vendor=iwave&num=2 Compilation of iwill:dk8_htx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=dk8_htx&vendor=iwill&num=2 Compilation of iwill:dk8s2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=dk8s2&vendor=iwill&num=2 Compilation of iwill:dk8x has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=dk8x&vendor=iwill&num=2 Compilation of jetway:pa78vm5 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=pa78vm5&vendor=jetway&num=2 Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=986lcd-m&vendor=kontron&num=2 Compilation of kontron:kt690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=kt690&vendor=kontron&num=2 Compilation of lenovo:x60 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=x60&vendor=lenovo&num=2 Compilation of msi:ms7135 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=ms7135&vendor=msi&num=2 Compilation of msi:ms7260 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=ms7260&vendor=msi&num=2 Compilation of msi:ms9185 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=ms9185&vendor=msi&num=2 Compilation of msi:ms9282 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=ms9282&vendor=msi&num=2 Compilation of newisys:khepri has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=khepri&vendor=newisys&num=2 Compilation of nvidia:l1_2pvv has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=l1_2pvv&vendor=nvidia&num=2 Compilation of rca:rm4100 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=rm4100&vendor=rca&num=2 Compilation of roda:rk886ex has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=rk886ex&vendor=roda&num=2 Compilation of sunw:ultra40 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=ultra40&vendor=sunw&num=2 Compilation of supermicro:h8dme has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=h8dme&vendor=supermicro&num=2 Compilation of supermicro:h8dmr has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=h8dmr&vendor=supermicro&num=2 Compilation of technexion:tim5690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=tim5690&vendor=technexion&num=2 Compilation of technexion:tim8690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=tim8690&vendor=technexion&num=2 Compilation of thomson:ip1000 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=ip1000&vendor=thomson&num=2 Compilation of tyan:s2850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s2850&vendor=tyan&num=2 Compilation of tyan:s2875 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s2875&vendor=tyan&num=2 Compilation of tyan:s2880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s2880&vendor=tyan&num=2 Compilation of tyan:s2881 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s2881&vendor=tyan&num=2 Compilation of tyan:s2882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s2882&vendor=tyan&num=2 Compilation of tyan:s2885 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s2885&vendor=tyan&num=2 Compilation of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s2891&vendor=tyan&num=2 Compilation of tyan:s2892 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s2892&vendor=tyan&num=2 Compilation of tyan:s2895 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s2895&vendor=tyan&num=2 Compilation of tyan:s2912 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s2912&vendor=tyan&num=2 Compilation of tyan:s4880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s4880&vendor=tyan&num=2 Compilation of tyan:s4882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6511&device=s4882&vendor=tyan&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Mon Apr 18 05:03:16 2011 From: svn at coreboot.org (repository service) Date: Mon, 18 Apr 2011 05:03:16 +0200 Subject: [coreboot] build service results for r6512 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6512 to the coreboot repository. This caused the following changes: Change Log: fix copy and paste errors in ne2k.c Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=dbm690t&vendor=amd&num=2 Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=inagua&vendor=amd&num=2 Compilation of amd:mahogany is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=mahogany&vendor=amd&num=2 Compilation of amd:mahogany_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=mahogany_fam10&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=persimmon&vendor=amd&num=2 Compilation of amd:pistachio is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=pistachio&vendor=amd&num=2 Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=serengeti_cheetah&vendor=amd&num=2 Compilation of amd:tilapia_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=tilapia_fam10&vendor=amd&num=2 Compilation of arima:hdama is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=hdama&vendor=arima&num=2 Compilation of asrock:939a785gmh is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=939a785gmh&vendor=asrock&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=e350m1&vendor=asrock&num=2 Compilation of asus:a8v-e_deluxe is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=a8v-e_deluxe&vendor=asus&num=2 Compilation of asus:a8v-e_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=a8v-e_se&vendor=asus&num=2 Compilation of asus:m2n-e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=m2n-e&vendor=asus&num=2 Compilation of asus:m2v is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=m2v&vendor=asus&num=2 Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=m2v-mx_se&vendor=asus&num=2 Compilation of asus:m4a78-em is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=m4a78-em&vendor=asus&num=2 Compilation of asus:m4a785-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=m4a785-m&vendor=asus&num=2 Compilation of broadcom:blast is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=blast&vendor=broadcom&num=2 Compilation of getac:p470 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=p470&vendor=getac&num=2 Compilation of gigabyte:ga_2761gxdk is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=ga_2761gxdk&vendor=gigabyte&num=2 Compilation of gigabyte:m57sli is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=m57sli&vendor=gigabyte&num=2 Compilation of gigabyte:ma785gmt is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=ma785gmt&vendor=gigabyte&num=2 Compilation of gigabyte:ma78gm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=ma78gm&vendor=gigabyte&num=2 Compilation of hp:dl145_g1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=dl145_g1&vendor=hp&num=2 Compilation of hp:dl145_g3 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=dl145_g3&vendor=hp&num=2 Compilation of ibase:mb899 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=mb899&vendor=ibase&num=2 Compilation of ibm:e325 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=e325&vendor=ibm&num=2 Compilation of ibm:e326 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=e326&vendor=ibm&num=2 Compilation of iei:kino-780am2-fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=kino-780am2-fam10&vendor=iei&num=2 Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=d945gclf&vendor=intel&num=2 Compilation of iwave:iWRainbowG6 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=iWRainbowG6&vendor=iwave&num=2 Compilation of iwill:dk8_htx is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=dk8_htx&vendor=iwill&num=2 Compilation of iwill:dk8s2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=dk8s2&vendor=iwill&num=2 Compilation of iwill:dk8x is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=dk8x&vendor=iwill&num=2 Compilation of jetway:pa78vm5 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=pa78vm5&vendor=jetway&num=2 Compilation of kontron:986lcd-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=986lcd-m&vendor=kontron&num=2 Compilation of kontron:kt690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=kt690&vendor=kontron&num=2 Compilation of lenovo:x60 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=x60&vendor=lenovo&num=2 Compilation of msi:ms7135 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=ms7135&vendor=msi&num=2 Compilation of msi:ms7260 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=ms7260&vendor=msi&num=2 Compilation of msi:ms9185 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=ms9185&vendor=msi&num=2 Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=ms9282&vendor=msi&num=2 Compilation of newisys:khepri is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=khepri&vendor=newisys&num=2 Compilation of nvidia:l1_2pvv is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=l1_2pvv&vendor=nvidia&num=2 Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=rm4100&vendor=rca&num=2 Compilation of roda:rk886ex is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=rk886ex&vendor=roda&num=2 Compilation of sunw:ultra40 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=ultra40&vendor=sunw&num=2 Compilation of supermicro:h8dme is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=h8dme&vendor=supermicro&num=2 Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=h8dmr&vendor=supermicro&num=2 Compilation of technexion:tim5690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=tim5690&vendor=technexion&num=2 Compilation of technexion:tim8690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=tim8690&vendor=technexion&num=2 Compilation of thomson:ip1000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=ip1000&vendor=thomson&num=2 Compilation of tyan:s2850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s2850&vendor=tyan&num=2 Compilation of tyan:s2875 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s2875&vendor=tyan&num=2 Compilation of tyan:s2880 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s2880&vendor=tyan&num=2 Compilation of tyan:s2881 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s2881&vendor=tyan&num=2 Compilation of tyan:s2882 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s2882&vendor=tyan&num=2 Compilation of tyan:s2885 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s2885&vendor=tyan&num=2 Compilation of tyan:s2891 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s2891&vendor=tyan&num=2 Compilation of tyan:s2892 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s2892&vendor=tyan&num=2 Compilation of tyan:s2895 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s2895&vendor=tyan&num=2 Compilation of tyan:s2912 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s2912&vendor=tyan&num=2 Compilation of tyan:s4880 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s4880&vendor=tyan&num=2 Compilation of tyan:s4882 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6512&device=s4882&vendor=tyan&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From hamo.by at gmail.com Mon Apr 18 03:50:59 2011 From: hamo.by at gmail.com (Hamo) Date: Mon, 18 Apr 2011 09:50:59 +0800 Subject: [coreboot] [RFC][PATCH]Added architecture ARM and option for cross-compile Message-ID: This patch added a new architecture option in general setup menu, and after we choice the ARM architecture, we can define the cross-compiler-prefix. Since coreboot now depends on X86 architecture, we couldn't build an ARM coreboot now. Signed-off-by: Yang Bai diff --git a/Makefile b/Makefile index ac7115d..cae3870 100644 --- a/Makefile +++ b/Makefile @@ -101,6 +101,12 @@ else include $(HAVE_DOTCONFIG) +ifneq ($(CONFIG_ARCH_X86),y) +ifneq ($(CONFIG_COMPILER_LLVM_CLANG),y) +CC := $(CONFIG_CROSS_COMPILE)$(CC) +endif +endif + ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) CC:=clang -m32 diff --git a/src/Kconfig b/src/Kconfig index 05b4adb..abaa9a5 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -23,12 +23,37 @@ menu "General setup" config EXPERT bool "Expert mode" + default n help This allows you to select certain advanced configuration options. Warning: Only enable this option if you really know what you are doing! You have been warned! +choice + prompt "Architecture" + default ARCH_X86 + help + This option is used to set the architecture of Coreboot. + +config ARCH_X86 + bool "X86" +config ARCH_ARM + bool "ARM" + depends on EXPERT +endchoice + +config CROSS_COMPILE + string "Cross-compiler tool prefix" + default "" + depends on !ARCH_X86 + depends on COMPILER_GCC + help + Same as running 'make CROSS_COMPILE=prefix-' but stored for + default make runs in this kernel build directory. You don't + need to set this unless you want the configured kernel build + directory to select the cross-compiler automatically. + config LOCALVERSION string "Local version string" help @@ -102,12 +127,6 @@ endmenu source src/mainboard/Kconfig -# This option is used to set the architecture of a mainboard to X86. -# It is usually set in mainboard/*/Kconfig. -config ARCH_X86 - bool - default n - if ARCH_X86 source src/arch/x86/Kconfig endif From svens at stackframe.org Mon Apr 18 10:00:53 2011 From: svens at stackframe.org (Sven Schnelle) Date: Mon, 18 Apr 2011 10:00:53 +0200 Subject: [coreboot] [PATCH] add ThinkPad T60 In-Reply-To: <4DAB8156.4040200@coreboot.org> (Stefan Reinauer's message of "Sun\, 17 Apr 2011 17\:09\:58 -0700") References: <871v1181r2.fsf@begreifnix.stackframe.org> <4DAB8156.4040200@coreboot.org> Message-ID: <87tydw6lai.fsf@begreifnix.stackframe.org> Hi Stefan, Stefan Reinauer writes: > On 4/17/11 6:07 AM, Sven Schnelle wrote: > > Index: t60/Kconfig > =================================================================== > --- t60/Kconfig (revision 6509) > +++ t60/Kconfig (working copy) > > @@ -56,4 +56,28 @@ > int > default 1 > > +config TI_PCMCIA_CARDBUS_CMDR > + hex > + default 0x0107 > + > +config TI_PCMCIA_CARDBUS_CLSR > + hex > + default 0x00 > + > +config TI_PCMCIA_CARDBUS_CLTR > + hex > + default 0x40 > + > +config TI_PCMCIA_CARDBUS_BCR > + hex > + default 0x07C0 > + > +config TI_PCMCIA_CARDBUS_SCR > + hex > + default 0x08449060 > + > +config TI_PCMCIA_CARDBUS_MRR > + hex > + default 0x00007522 > + > endif > > Can you please put these in a .c or .h file in the mainboard > directory? I don't think we should add configuration variables > for single registers in Kconfig. Actually i've copied that from another Board using the pci1x2x cardbus controller, and was quite surprised that these settings are located in Kconfig. IMHO they should be configured in devicetree.cb via chip.h config. What do you think about this solution? Maybe we should do that in an extra patch, which moves those setting to chip config and converts all pci1x2x users? > Index: t60/dock.c > =================================================================== > --- t60/dock.c (revision 6509) > +++ t60/dock.c (working copy) > @@ -26,8 +26,9 @@ > #include > #include > #include "dock.h" > +#include "superio/nsc/pc87384/pc87384.h" > +#include "ec/acpi/ec.h" > #include "southbridge/intel/i82801gx/i82801gx.h" > -#include "superio/nsc/pc87392/pc87392.h" > > static void dlpc_write_register(int reg, int value) > { > @@ -59,6 +60,7 @@ > dlpc_write_register(0xf1, mode); > } > > + > > drop new line? Yes ;) > + /* no GPIO events enabled for PORT0 */ > + outb(0x00, 0x1622); > + /* clear GPIO events on PORT0 */ > + outb(0xff, 0x1623); > + outb(0xff, 0x1624); > + /* no GPIO events enabled for PORT1 */ > + outb(0x00, 0x1626); > > Are you properly preventing the resource allocator from putting other resources on top of 0x16xx? Yes, it's listed in devicetree.cb (which should prevent allocation). Debug log from boot: PNP: 002e.7 60 <- [0x0000001620 - 0x000000162f] size 0x00000010 gran 0x04 io > + outb(0x61, 0x15ec); > + return inb(0x15ee) & 1; > } > + > ... and 0x15xx same here, the 15e0 range is allocated in ec/lenovo/pmh7 (i'm not using the pmh7 function here because i don't want to have all the PMH7 code in SMM just for one register read) > > Index: t60/mptable.c > =================================================================== > --- t60/mptable.c (revision 6509) > +++ t60/mptable.c (working copy) > @@ -62,9 +62,7 @@ > smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ > smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ > smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ > - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ > - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ > - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ > + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ > > smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0); > smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1); > > In general it would be better to look for the appropriate devices in the system, because someone might plug in a device with a bridge on the > lower buses, effectively rendering your mptable useless. > > MP table automation ftw! Hmm, have to look how to do automatic generation of mptable. Thanks for the hint. Sven. From Zheng.Bao at amd.com Mon Apr 18 09:02:09 2011 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Mon, 18 Apr 2011 15:02:09 +0800 Subject: [coreboot] [patch] number of core of AMD fam10 Message-ID: The "temp" will be used later. So it has to be calculated correctly. ? Signed-off-by: Zheng Bao Index: src/northbridge/amd/amdht/h3ncmn.c =================================================================== --- src/northbridge/amd/amdht/h3ncmn.c?(revision 6512) +++ src/northbridge/amd/amdht/h3ncmn.c?(working copy) @@ -565,7 +565,8 @@ ? ??/* bits[15,13,12] specify the cores */ ??/* Support Downcoring */ -?cores = ((temp & 8) >> 1) + (temp & 3) + 1; +?temp = ((temp & 8) >> 1) + (temp & 3); +?cores = temp + 1; ??AmdPCIReadBits (MAKE_SBDFO(makePCISegmentFromNode(node), ??????makePCIBusFromNode(node), ??????makePCIDeviceFromNode(node), -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: fam10_number_of_core.patch URL: From mlf.conv at gmail.com Mon Apr 18 14:53:43 2011 From: mlf.conv at gmail.com (Marek) Date: Mon, 18 Apr 2011 14:53:43 +0200 Subject: [coreboot] Gigabyte GA AMD E350N USB3 Board In-Reply-To: References: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> <20110412130805.12455.qmail@stuge.se> Message-ID: <1E55BB5C-5EFF-45B1-AC90-0063B87EDD0B@gmail.com> Hi Tom and Niklas, What about the DB_PORT programming header? Is the dual BIOS stored on the MX25L1606EM2I-12G chip? I'm not interested in USB3 that much although it's a nice and useful feature but it seems to be a very good board in general. Marek On 16.4.2011, at 11:12, Tom Sylla wrote: > Hi Marek, > > I do own this board, and it is probably one of the more painful to get > ported. There is no SPI header, no serial port, and it has the > gigabyte dual-BIOS mechanism to deal with. I also have an MSI e350 > mini-ITX board, without any of those problems, and maybe someday I > will try to make a port for it. > > Tom > > On Tue, Apr 12, 2011 at 7:07 AM, Marek wrote: >> Hi Peter, >> >> On 12.4.2011, at 15:08, Peter Stuge wrote: >> >>> Marek wrote: >>>> with regards to recent AMD patches, >>> >>> Note that the patches did not include support for your mainboard. >>> >>> >>>> I'd like to ask whether it would be possible to install coreboot on >>>> Gigabyte GA AMD E350N USB3 board >>>> (AMD E350, chipset FCH A50 Hudson M1, iTE 8720). >>> >>> The answer is, as always, no it will not work unless you make it work. >>> >>> The final piece of the puzzle, mainboard support, is still missing, >>> but all the other 4999 pieces have been put in place for you by AMD >>> and the rest of the coreboot community. >> >> thanks for your answer, I'm fully aware of the situation, my question was more directed to people (if there are any) who own that MB, perhaps work on coreboot support, or have considered it and abanonded it in the initial phase or even made progress but were unable to continue due to various circumstances. No answer most likely means that there isn't anyone who owns this board so far, so I just pushed all information I could find out without buying that board in case someone wants to buy one and add coreboot support for it. >> >> Marek >> >>> >>> >>> //Peter >>> >>> -- >>> coreboot mailing list: coreboot at coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Mon Apr 18 16:00:02 2011 From: svn at coreboot.org (coreboot tracker) Date: Mon, 18 Apr 2011 16:00:02 +0200 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From peter at stuge.se Mon Apr 18 17:19:35 2011 From: peter at stuge.se (Peter Stuge) Date: Mon, 18 Apr 2011 17:19:35 +0200 Subject: [coreboot] Gigabyte GA AMD E350N USB3 Board In-Reply-To: <1E55BB5C-5EFF-45B1-AC90-0063B87EDD0B@gmail.com> References: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> <20110412130805.12455.qmail@stuge.se> <1E55BB5C-5EFF-45B1-AC90-0063B87EDD0B@gmail.com> Message-ID: <20110418151935.1367.qmail@stuge.se> Marek wrote: > What about the DB_PORT programming header? Maybe! Can you trace the connections from the port to the flash chips? > Is the dual BIOS stored on the MX25L1606EM2I-12G chip? GIGABYTE boards that actually implement DualBIOS should have two flash chips, close to each other. //Peter From vidwer at gmail.com Mon Apr 18 17:28:17 2011 From: vidwer at gmail.com (Idwer Vollering) Date: Mon, 18 Apr 2011 17:28:17 +0200 Subject: [coreboot] Gigabyte GA AMD E350N USB3 Board In-Reply-To: <20110418151935.1367.qmail@stuge.se> References: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> <20110412130805.12455.qmail@stuge.se> <1E55BB5C-5EFF-45B1-AC90-0063B87EDD0B@gmail.com> <20110418151935.1367.qmail@stuge.se> Message-ID: 2011/4/18 Peter Stuge : > Marek wrote: >> What about the DB_PORT programming header? http://hardforum.com/showthread.php?t=1598236 > > Maybe! Can you trace the connections from the port to the flash > chips? > > >> Is the dual BIOS stored on the MX25L1606EM2I-12G chip? > > GIGABYTE boards that actually implement DualBIOS should have two > flash chips, close to each other. > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From marcj303 at gmail.com Mon Apr 18 18:04:39 2011 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 18 Apr 2011 10:04:39 -0600 Subject: [coreboot] [RFC][PATCH]Added architecture ARM and option for cross-compile In-Reply-To: References: Message-ID: On Sun, Apr 17, 2011 at 7:50 PM, Hamo wrote: > This patch added a new architecture option in general setup menu, and > after we choice the > ARM architecture, we can define the cross-compiler-prefix. Since > coreboot now depends on > X86 architecture, we couldn't build an ARM coreboot now. > > Signed-off-by: Yang Bai > > > diff --git a/Makefile b/Makefile > index ac7115d..cae3870 100644 > --- a/Makefile > +++ b/Makefile > @@ -101,6 +101,12 @@ else > > ?include $(HAVE_DOTCONFIG) > > +ifneq ($(CONFIG_ARCH_X86),y) > +ifneq ($(CONFIG_COMPILER_LLVM_CLANG),y) > +CC := $(CONFIG_CROSS_COMPILE)$(CC) > +endif > +endif > + > ?ifneq ($(INNER_SCANBUILD),y) > ?ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) > ?CC:=clang -m32 > diff --git a/src/Kconfig b/src/Kconfig > index 05b4adb..abaa9a5 100644 > --- a/src/Kconfig > +++ b/src/Kconfig > @@ -23,12 +23,37 @@ menu "General setup" > > ?config EXPERT > ? ? ? ?bool "Expert mode" > + ? ? ? default n > ? ? ? ?help > ? ? ? ? ?This allows you to select certain advanced configuration options. > > ? ? ? ? ?Warning: Only enable this option if you really know what you are > ? ? ? ? ?doing! You have been warned! > > +choice > + ? ? ? prompt "Architecture" > + ? ? ? default ARCH_X86 > + ? ? ? help > + ? ? ? ? This option is used to set the architecture of Coreboot. > + > +config ARCH_X86 > + ? ? ? bool "X86" > +config ARCH_ARM > + ? ? ? bool "ARM" > + ? ? ? depends on EXPERT > +endchoice > + > +config CROSS_COMPILE > + ? ? ? string "Cross-compiler tool prefix" > + ? ? ? default "" > + ? ? ? depends on !ARCH_X86 > + ? ? ? depends on COMPILER_GCC > + ? ? ? help > + ? ? ? ? Same as running 'make CROSS_COMPILE=prefix-' but stored for > + ? ? ? ? default make runs in this kernel build directory. ?You don't > + ? ? ? ? need to set this unless you want the configured kernel build > + ? ? ? ? directory to select the cross-compiler automatically. > + > ?config LOCALVERSION > ? ? ? ?string "Local version string" > ? ? ? ?help > @@ -102,12 +127,6 @@ endmenu > > ?source src/mainboard/Kconfig > > -# This option is used to set the architecture of a mainboard to X86. > -# It is usually set in mainboard/*/Kconfig. > -config ARCH_X86 > - ? ? ? bool > - ? ? ? default n > - > ?if ARCH_X86 > ?source src/arch/x86/Kconfig > ?endif > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Hi Hamo, Thanks for the patch. It is a little early to add this without the actual ARM additions. Please maintain this patch until the ARM code is ready to be added. Have you considered how this will work with the existing coreboot cross compile, crosstools and xcompile? Marc -- http://se-eng.com From tsylla at gmail.com Mon Apr 18 17:54:21 2011 From: tsylla at gmail.com (Tom Sylla) Date: Mon, 18 Apr 2011 08:54:21 -0700 Subject: [coreboot] Gigabyte GA AMD E350N USB3 Board In-Reply-To: <1E55BB5C-5EFF-45B1-AC90-0063B87EDD0B@gmail.com> References: <7C145E6E-BDAA-4C4C-B0F1-51DB9A73BFC8@gmail.com> <20110412130805.12455.qmail@stuge.se> <1E55BB5C-5EFF-45B1-AC90-0063B87EDD0B@gmail.com> Message-ID: Hi Marek, When I first got the board, I checked the signals of the DB_PORT header with a meter, and found several connections going to the Super I/O instead of the flash chip. I was thinking it might be a serial port header of some non standard pinout instead of a SPI header. It would be good to double-check though. Tom On Mon, Apr 18, 2011 at 5:53 AM, Marek wrote: > Hi Tom and Niklas, > > What about the?DB_PORT?programming header? Is the dual BIOS stored on > the?MX25L1606EM2I-12G chip??I'm not interested in USB3 that much although > it's a nice and useful feature but it seems to be a very good board in > general. > Marek > On 16.4.2011, at 11:12, Tom Sylla wrote: > > Hi Marek, > > I do own this board, and it is probably one of the more painful to get > > ported. There is no SPI header, no serial port, and it has the > > gigabyte dual-BIOS mechanism to deal with. I also have an MSI e350 > > mini-ITX board, without any of those problems, and maybe someday I > > will try to make a port for it. > > Tom > > On Tue, Apr 12, 2011 at 7:07 AM, Marek wrote: > > Hi Peter, > > On 12.4.2011, at 15:08, Peter Stuge wrote: > > Marek wrote: > > with regards to recent AMD patches, > > Note that the patches did not include support for your mainboard. > > > I'd like to ask whether it would be possible to install coreboot on > > Gigabyte GA AMD E350N USB3 board > > (AMD E350, chipset FCH A50 Hudson M1, iTE 8720). > > The answer is, as always, no it will not work unless you make it work. > > The final piece of the puzzle, mainboard support, is still missing, > > but all the other 4999 pieces have been put in place for you by AMD > > and the rest of the coreboot community. > > thanks for your answer, I'm fully aware of the situation, my question was > more directed to people (if there are any) who own that MB, perhaps work on > coreboot support, or have considered it and abanonded it in the initial > phase or even made progress but were unable to continue due to various > circumstances. No answer most likely means that there isn't anyone who owns > this board so far, so I just pushed all information I could find out without > buying that board in case someone wants to buy one and add coreboot support > for it. > > Marek > > > > //Peter > > -- > > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > -- > > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > From marcj303 at gmail.com Mon Apr 18 20:26:19 2011 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 18 Apr 2011 12:26:19 -0600 Subject: [coreboot] [patch] number of core of AMD fam10 In-Reply-To: References: Message-ID: On Mon, Apr 18, 2011 at 1:02 AM, Bao, Zheng wrote: > The "temp" will be used later. So it has to be calculated correctly. > > Signed-off-by: Zheng Bao > > > > Index: src/northbridge/amd/amdht/h3ncmn.c > =================================================================== > --- src/northbridge/amd/amdht/h3ncmn.c?(revision 6512) > +++ src/northbridge/amd/amdht/h3ncmn.c?(working copy) > @@ -565,7 +565,8 @@ > > ??/* bits[15,13,12] specify the cores */ > ??/* Support Downcoring */ > -?cores = ((temp & 8) >> 1) + (temp & 3) + 1; > +?temp = ((temp & 8) >> 1) + (temp & 3); > +?cores = temp + 1; > ??AmdPCIReadBits (MAKE_SBDFO(makePCISegmentFromNode(node), > ??????makePCIBusFromNode(node), > ??????makePCIDeviceFromNode(node), Acked-by: Marc Jones -- http://se-eng.com From stefan.reinauer at coreboot.org Mon Apr 18 21:32:15 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Mon, 18 Apr 2011 21:32:15 +0200 Subject: [coreboot] [PATCH] add ThinkPad T60 In-Reply-To: <87tydw6lai.fsf@begreifnix.stackframe.org> References: <871v1181r2.fsf@begreifnix.stackframe.org> <4DAB8156.4040200@coreboot.org> <87tydw6lai.fsf@begreifnix.stackframe.org> Message-ID: <20110418193215.GA28141@coreboot.org> * Sven Schnelle [110418 10:00]: > Stefan Reinauer writes: > > Can you please put these in a .c or .h file in the mainboard > > directory? I don't think we should add configuration variables > > for single registers in Kconfig. > > Actually i've copied that from another Board using the pci1x2x cardbus > controller, and was quite surprised that these settings are located in > Kconfig. IMHO they should be configured in devicetree.cb via chip.h config. > What do you think about this solution? Maybe we should do that in an > extra patch, which moves those setting to chip config and converts all > pci1x2x users? Oh, that sounds like a much better thing to do. > > - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ > > - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ > > - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ > > + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ > > > > smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0); > > smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1); > > > > In general it would be better to look for the appropriate devices in the system, because someone might plug in a device with a bridge on the > > lower buses, effectively rendering your mptable useless. > > > > MP table automation ftw! > > Hmm, have to look how to do automatic generation of mptable. Thanks > for the hint. Well, there is this (unimplemented) idea of adding the IO Apics to the device tree (ie. let each southbridge create an extra device) and then create proper mp tables and pirq tables by walking the device tree. However, as a quick fix you can look at the kontron 986lcd-m. It probes for certain bridges and fixes up the bus numbers according to their subordinate buses. Anyways, with the pci1x2x fix in place, the code is Acked-by: Stefan Reinauer Everything else will possibly need another round of thoughts/patches. Stefan From jwangzju at gmail.com Mon Apr 18 23:38:49 2011 From: jwangzju at gmail.com (Jiang Wang) Date: Mon, 18 Apr 2011 17:38:49 -0400 Subject: [coreboot] rtc wake up does not work on ASUS M2V-MX SE Message-ID: Hi, I want to use the rtc wake up function on coreboot and Linux on ASUS M2V MX-SE. I used rtcwake command (ver 2.19) from ftp://ftp.kernel.org/pub/linux/utils/util-linux-ng/ to automatically wake up the machine after an S3 sleep. This works well on manufactured ASUS bios. But with coreboot, it reports an error, "open device /sys/class/rtc/rtc0/device/power/wakeup failed." It seems the command try to find /dev/rtc0 but failed. And I checked that device manually; it does not exist. Anyone knows why this happened and how to fix it? Thanks! Regards, Jiang From peter at stuge.se Tue Apr 19 01:06:07 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 19 Apr 2011 01:06:07 +0200 Subject: [coreboot] [patch] number of core of AMD fam10 In-Reply-To: References: Message-ID: <20110418230607.16884.qmail@stuge.se> Bao, Zheng wrote: > The "temp" will be used later. So it has to be calculated correctly. .. > +++ src/northbridge/amd/amdht/h3ncmn.c (working copy) > @@ -565,7 +565,8 @@ > > /* bits[15,13,12] specify the cores */ > /* Support Downcoring */ > - cores = ((temp & 8) >> 1) + (temp & 3) + 1; > + temp = ((temp & 8) >> 1) + (temp & 3); > + cores = temp + 1; The variable name "temp" unfortunately does not explain what the value is. The commit message also does not have hints. Hopefully in the future it's possible to also use a brief moment to improve the clarity of the code, while it is already being fixed for some other reason. Ie. fixing up variable names, writing particularly informative commit messages, or of course both at the same time! :) //Peter From stefan.reinauer at coreboot.org Tue Apr 19 01:06:49 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Tue, 19 Apr 2011 01:06:49 +0200 Subject: [coreboot] [PATCH] drop some per-board cruft Message-ID: <20110418230649.GA1275@coreboot.org> See patch. -------------- next part -------------- A non-text attachment was scrubbed... Name: drop_individual_usbdebug_init.diff Type: text/x-patch Size: 25682 bytes Desc: not available URL: From stefan.reinauer at coreboot.org Tue Apr 19 01:08:58 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Tue, 19 Apr 2011 01:08:58 +0200 Subject: [coreboot] rtc wake up does not work on ASUS M2V-MX SE In-Reply-To: References: Message-ID: <20110418230858.GA2822@coreboot.org> * Jiang Wang [110418 23:38]: > Hi, > > I want to use the rtc wake up function on coreboot and Linux on ASUS > M2V MX-SE. I used rtcwake command (ver 2.19) from > ftp://ftp.kernel.org/pub/linux/utils/util-linux-ng/ to automatically > wake up the machine after an S3 sleep. This works well on manufactured > ASUS bios. But with coreboot, it reports an error, "open device > /sys/class/rtc/rtc0/device/power/wakeup failed." It seems the command > try to find /dev/rtc0 but failed. And I checked that device manually; > it does not exist. Sounds like some node is missing in the DSDT? From peter at stuge.se Tue Apr 19 01:15:25 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 19 Apr 2011 01:15:25 +0200 Subject: [coreboot] [RFC][PATCH]Added architecture ARM and option for cross-compile In-Reply-To: References: Message-ID: <20110418231526.17996.qmail@stuge.se> Agree with Marc - well done everyone who is sending patches already! Please continue sending small patches like this, they are easy to review and comment on. Hamo wrote: > +choice > + prompt "Architecture" > + default ARCH_X86 > + help > + This option is used to set the architecture of Coreboot. > + > +config ARCH_X86 > + bool "X86" > +config ARCH_ARM > + bool "ARM" > + depends on EXPERT > +endchoice I don't think the above will work as-is. Consider the comment that was removed: > -# This option is used to set the architecture of a mainboard to X86. > -# It is usually set in mainboard/*/Kconfig. > -config ARCH_X86 > - bool > - default n This explains that ARCH_X86 is set by mainboards and not the user. Going forward the question is if a new step should be added to configuration, where the user can choose the architecture they are interested in, and that will limit the list of mainboards that can be selected. The alternative is that configuration continues to work like it does now, where all mainboards by all manufacturers are displayed, and the ARCH_* variable is set by the chosen mainboard. The approach to add a step will require much more work changing how coreboot Kconfig works. The latter approach will be simpler. I personally think that it would be fine to not have an extra step for the user to choose architecture, that this is implicit from the mainboard. Please also note that coreboot should always be written with all lowercase. //Peter From peter at stuge.se Tue Apr 19 01:17:47 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 19 Apr 2011 01:17:47 +0200 Subject: [coreboot] [PATCH] drop some per-board cruft In-Reply-To: <20110418230649.GA1275@coreboot.org> References: <20110418230649.GA1275@coreboot.org> Message-ID: <20110418231747.18261.qmail@stuge.se> Stefan Reinauer wrote: > * Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value > to unify calls to *_enable_usbdebug() > * rename *_enable_usbdebug() to enable_usbdebug() > * move enable_usbdebug() to generic romstage console init code > and drop it from the individual romstage.c files. > > Something similar should happen to the uart init: > * uart_init() can go into console.c right now > * superio init should go into a function local_uart_init() defined in > romstage.c and be called from console_init, too. > > Signed-off-by: Stefan Reinauer Acked-by: Peter Stuge From marcj303 at gmail.com Tue Apr 19 01:41:56 2011 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 18 Apr 2011 17:41:56 -0600 Subject: [coreboot] [RFC][PATCH]Added architecture ARM and option for cross-compile In-Reply-To: <20110418231526.17996.qmail@stuge.se> References: <20110418231526.17996.qmail@stuge.se> Message-ID: On Mon, Apr 18, 2011 at 5:15 PM, Peter Stuge wrote: > Agree with Marc - well done everyone who is sending patches already! > > Please continue sending small patches like this, they are easy to > review and comment on. > > > Hamo wrote: >> +choice >> + ? ? prompt "Architecture" >> + ? ? default ARCH_X86 >> + ? ? help >> + ? ? ? This option is used to set the architecture of Coreboot. >> + >> +config ARCH_X86 >> + ? ? bool "X86" >> +config ARCH_ARM >> + ? ? bool "ARM" >> + ? ? depends on EXPERT >> +endchoice > > I don't think the above will work as-is. Consider the comment that > was removed: > >> -# This option is used to set the architecture of a mainboard to X86. >> -# It is usually set in mainboard/*/Kconfig. >> -config ARCH_X86 >> - ? ? bool >> - ? ? default n > > This explains that ARCH_X86 is set by mainboards and not the user. > > > Going forward the question is if a new step should be added to > configuration, where the user can choose the architecture they are > interested in, and that will limit the list of mainboards that can be > selected. > > The alternative is that configuration continues to work like it does > now, where all mainboards by all manufacturers are displayed, and the > ARCH_* variable is set by the chosen mainboard. > > The approach to add a step will require much more work changing how > coreboot Kconfig works. The latter approach will be simpler. I > personally think that it would be fine to not have an extra step for > the user to choose architecture, that this is implicit from the > mainboard. Peter makes a very good point here. The architecture would be tied to the mainboard and by extension CPU kconfig. Marc -- http://se-eng.com From jwangzju at gmail.com Tue Apr 19 01:43:41 2011 From: jwangzju at gmail.com (Jiang Wang) Date: Mon, 18 Apr 2011 19:43:41 -0400 Subject: [coreboot] rtc wake up does not work on ASUS M2V-MX SE In-Reply-To: <20110418230858.GA2822@coreboot.org> References: <20110418230858.GA2822@coreboot.org> Message-ID: Hi Stefan, Do you have any suggestions about the specific name or keywords that I should look for in the DSDT? I think I can dump the DSDT of the manufactured BIOS with acpitool and compare it with the one of coreboot, right? But it is better to have a rough idea before doing the comparison. Thanks. Regards, Jiang On Mon, Apr 18, 2011 at 7:08 PM, Stefan Reinauer wrote: > * Jiang Wang [110418 23:38]: >> Hi, >> >> I want to use the rtc wake up function on coreboot and Linux on ASUS >> M2V MX-SE. I used rtcwake command (ver 2.19) ?from >> ftp://ftp.kernel.org/pub/linux/utils/util-linux-ng/ to automatically >> wake up the machine after an S3 sleep. This works well on manufactured >> ASUS bios. But with coreboot, it reports an error, "open device >> /sys/class/rtc/rtc0/device/power/wakeup failed." It seems the command >> try to find /dev/rtc0 but failed. And I checked that device manually; >> it does not exist. > > Sounds like some node is missing in the DSDT? > > > > From svn at coreboot.org Tue Apr 19 01:51:13 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 01:51:13 +0200 Subject: [coreboot] [commit] r6513 - in trunk/src: console mainboard/amd/bimini_fam10 mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/tilapia_fam10 mainb... Message-ID: Author: stepan Date: Tue Apr 19 01:51:12 2011 New Revision: 6513 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6513 Log: * Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer Acked-by: Peter Stuge Modified: trunk/src/console/console.c trunk/src/mainboard/amd/bimini_fam10/romstage.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/m2n-e/romstage.c trunk/src/mainboard/asus/m4a78-em/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/getac/p470/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/ibase/mb899/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/lenovo/x60/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/mainboard/supermicro/h8scm_fam10/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/southbridge/amd/sb600/Kconfig trunk/src/southbridge/amd/sb600/enable_usbdebug.c trunk/src/southbridge/amd/sb600/sb600.h trunk/src/southbridge/amd/sb700/enable_usbdebug.c trunk/src/southbridge/amd/sb700/sb700.h trunk/src/southbridge/amd/sb800/enable_usbdebug.c trunk/src/southbridge/amd/sb800/sb800.h trunk/src/southbridge/intel/i82801gx/Kconfig trunk/src/southbridge/intel/i82801gx/i82801gx.h trunk/src/southbridge/intel/i82801gx/usb_debug.c trunk/src/southbridge/intel/sch/usb_debug.c trunk/src/southbridge/nvidia/ck804/ck804.h trunk/src/southbridge/nvidia/ck804/enable_usbdebug.c trunk/src/southbridge/nvidia/mcp55/enable_usbdebug.c trunk/src/southbridge/nvidia/mcp55/mcp55.h trunk/src/southbridge/sis/sis966/enable_usbdebug.c trunk/src/southbridge/sis/sis966/sis966.h Modified: trunk/src/console/console.c ============================================================================== --- trunk/src/console/console.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/console/console.c Tue Apr 19 01:51:12 2011 (r6513) @@ -95,6 +95,10 @@ void console_init(void) { +#if CONFIG_USBDEBUG + enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); + early_usbdebug_init(); +#endif #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/amd/bimini_fam10/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -110,12 +110,7 @@ sb800_lpc_init(); uart_init(); -#if CONFIG_USBDEBUG - sb800_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -94,11 +94,6 @@ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb600_enable_usbdebug(0); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/amd/mahogany/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -93,11 +93,6 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -106,13 +106,7 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/amd/pistachio/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -91,11 +91,6 @@ * and it doesn't require any special setup. */ uart_init(); -#if CONFIG_USBDEBUG - sb600_enable_usbdebug(0); - early_usbdebug_init(); -#endif - console_init(); post_code(0x03); Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -105,13 +105,7 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -160,11 +160,6 @@ w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/asus/m2n-e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2n-e/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/asus/m2n-e/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -123,10 +123,6 @@ setup_mb_resource_map(); uart_init(); report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1); Modified: trunk/src/mainboard/asus/m4a78-em/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a78-em/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/asus/m4a78-em/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -106,13 +106,7 @@ it8712f_kill_watchdog(); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -106,13 +106,7 @@ it8712f_kill_watchdog(); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Modified: trunk/src/mainboard/getac/p470/romstage.c ============================================================================== --- trunk/src/mainboard/getac/p470/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/getac/p470/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -288,10 +288,6 @@ /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -147,10 +147,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - sis966_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -150,10 +150,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -102,11 +102,6 @@ it8718f_disable_reboot(); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); printk(BIOS_DEBUG, "\n"); Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -106,13 +106,7 @@ it8718f_disable_reboot(); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); Modified: trunk/src/mainboard/ibase/mb899/romstage.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/ibase/mb899/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -239,11 +239,6 @@ /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -107,13 +107,7 @@ f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -200,11 +200,6 @@ /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -112,13 +112,7 @@ f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -337,11 +337,6 @@ /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/kontron/kt690/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -96,11 +96,6 @@ w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb600_enable_usbdebug(0); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/lenovo/x60/romstage.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/lenovo/x60/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -242,11 +242,6 @@ uart_init(); } -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/msi/ms7260/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -139,10 +139,6 @@ setup_mb_resource_map(); uart_init(); report_bist_failure(bist); /* Halt upon BIST failure. */ -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -138,16 +138,10 @@ w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - printk(BIOS_DEBUG, "\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -140,10 +140,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -272,11 +272,6 @@ /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/supermicro/h8scm_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8scm_fam10/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/supermicro/h8scm_fam10/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -125,12 +125,7 @@ sb7xx_51xx_disable_wideio(0); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -100,11 +100,6 @@ it8712f_kill_watchdog(); uart_init(); -#if CONFIG_USBDEBUG - sb600_enable_usbdebug(0); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -95,11 +95,6 @@ it8712f_kill_watchdog(); uart_init(); -#if CONFIG_USBDEBUG - sb600_enable_usbdebug(0); - early_usbdebug_init(); -#endif - console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/tyan/s2912/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -136,10 +136,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Apr 19 01:51:12 2011 (r6513) @@ -138,16 +138,10 @@ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - printk(BIOS_DEBUG, "\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG - mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); Modified: trunk/src/southbridge/amd/sb600/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb600/Kconfig Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/amd/sb600/Kconfig Tue Apr 19 01:51:12 2011 (r6513) @@ -36,6 +36,10 @@ hex default 0xe0 +config USBDEBUG_DEFAULT_PORT + int + default 0 + choice prompt "SATA Mode" default SATA_MODE_IDE Modified: trunk/src/southbridge/amd/sb600/enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb600/enable_usbdebug.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/amd/sb600/enable_usbdebug.c Tue Apr 19 01:51:12 2011 (r6513) @@ -30,7 +30,7 @@ /* TODO: Allow changing the physical USB port used as Debug Port. */ } -void sb600_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ Modified: trunk/src/southbridge/amd/sb600/sb600.h ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600.h Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/amd/sb600/sb600.h Tue Apr 19 01:51:12 2011 (r6513) @@ -40,5 +40,5 @@ void sb600_lpc_port80(void); void sb600_pci_port80(void); -void sb600_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #endif /* SB600_H */ Modified: trunk/src/southbridge/amd/sb700/enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb700/enable_usbdebug.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/amd/sb700/enable_usbdebug.c Tue Apr 19 01:51:12 2011 (r6513) @@ -45,7 +45,7 @@ * This code currently only supports the first one, i.e., USB Debug devices * attached to physical USB ports belonging to the first EHCI device. */ -void sb7xx_51xx_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ Modified: trunk/src/southbridge/amd/sb700/sb700.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.h Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/amd/sb700/sb700.h Tue Apr 19 01:51:12 2011 (r6513) @@ -75,5 +75,5 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -void sb7xx_51xx_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #endif /* SB700_H */ Modified: trunk/src/southbridge/amd/sb800/enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb800/enable_usbdebug.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/amd/sb800/enable_usbdebug.c Tue Apr 19 01:51:12 2011 (r6513) @@ -43,7 +43,7 @@ } -void sb800_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5), EHCI_BAR_INDEX, CONFIG_EHCI_BAR); Modified: trunk/src/southbridge/amd/sb800/sb800.h ============================================================================== --- trunk/src/southbridge/amd/sb800/sb800.h Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/amd/sb800/sb800.h Tue Apr 19 01:51:12 2011 (r6513) @@ -58,7 +58,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -void sb800_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #else void sb800_enable(device_t dev); void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev); Modified: trunk/src/southbridge/intel/i82801gx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801gx/Kconfig Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/intel/i82801gx/Kconfig Tue Apr 19 01:51:12 2011 (r6513) @@ -24,11 +24,19 @@ select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT +if SOUTHBRIDGE_INTEL_I82801GX + config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX + default 0xfef00000 config EHCI_DEBUG_OFFSET hex - default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX + default 0xa0 + +config USBDEBUG_DEFAULT_PORT + int + default 1 + +endif Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx.h Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/intel/i82801gx/i82801gx.h Tue Apr 19 01:51:12 2011 (r6513) @@ -46,7 +46,7 @@ void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); #endif -void i82801gx_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #endif #define MAINBOARD_POWER_OFF 0 Modified: trunk/src/southbridge/intel/i82801gx/usb_debug.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/usb_debug.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/intel/i82801gx/usb_debug.c Tue Apr 19 01:51:12 2011 (r6513) @@ -31,7 +31,7 @@ /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } -void i82801gx_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { u32 dbgctl; device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ Modified: trunk/src/southbridge/intel/sch/usb_debug.c ============================================================================== --- trunk/src/southbridge/intel/sch/usb_debug.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/intel/sch/usb_debug.c Tue Apr 19 01:51:12 2011 (r6513) @@ -30,7 +30,7 @@ /* Not needed, the southbridges hardcode physical USB port 1. */ } -void sch_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { u32 dbgctl; device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ Modified: trunk/src/southbridge/nvidia/ck804/ck804.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804.h Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/nvidia/ck804/ck804.h Tue Apr 19 01:51:12 2011 (r6513) @@ -24,7 +24,7 @@ #include "chip.h" void ck804_enable(device_t dev); -void ck804_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); extern struct pci_operations ck804_pci_ops; Modified: trunk/src/southbridge/nvidia/ck804/enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/enable_usbdebug.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/nvidia/ck804/enable_usbdebug.c Tue Apr 19 01:51:12 2011 (r6513) @@ -46,7 +46,7 @@ pci_write_config32(dev, 0x74, dword); } -void ck804_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ Modified: trunk/src/southbridge/nvidia/mcp55/enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/enable_usbdebug.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/nvidia/mcp55/enable_usbdebug.c Tue Apr 19 01:51:12 2011 (r6513) @@ -40,7 +40,7 @@ pci_write_config32(dev, 0x74, dword); } -void mcp55_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ Modified: trunk/src/southbridge/nvidia/mcp55/mcp55.h ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55.h Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/nvidia/mcp55/mcp55.h Tue Apr 19 01:51:12 2011 (r6513) @@ -35,7 +35,7 @@ #else #if !defined(__ROMCC__) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -void mcp55_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #endif #endif Modified: trunk/src/southbridge/sis/sis966/enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/sis/sis966/enable_usbdebug.c Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/sis/sis966/enable_usbdebug.c Tue Apr 19 01:51:12 2011 (r6513) @@ -42,7 +42,7 @@ pci_write_config32(dev, 0x74, dword); } -void sis966_enable_usbdebug(unsigned int port) +void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ Modified: trunk/src/southbridge/sis/sis966/sis966.h ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966.h Mon Apr 18 04:26:56 2011 (r6512) +++ trunk/src/southbridge/sis/sis966/sis966.h Tue Apr 19 01:51:12 2011 (r6513) @@ -40,7 +40,7 @@ #endif #if defined(__PRE_RAM__) && !defined(__ROMCC__) -void sis966_enable_usbdebug(unsigned int port); +void enable_usbdebug(unsigned int port); #endif #endif /* SIS966_H */ From stefan.reinauer at coreboot.org Tue Apr 19 02:10:01 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Tue, 19 Apr 2011 02:10:01 +0200 Subject: [coreboot] [RFC][PATCH]Added architecture ARM and option for cross-compile In-Reply-To: <20110418231526.17996.qmail@stuge.se> References: <20110418231526.17996.qmail@stuge.se> Message-ID: <20110419001001.GA6753@coreboot.org> * Peter Stuge [110419 01:15]: > Going forward the question is if a new step should be added to > configuration, where the user can choose the architecture they are > interested in, and that will limit the list of mainboards that can be > selected. The advantage of this would be that a user (especially when compiling for non-x86) would be bothered with a significantly smaller choice of boards. The draw back is that the user has to know the architecture. :) That said, I kind of like the approach that each component "draws in" the other components it needs without the user having to make a choice. From svn at coreboot.org Tue Apr 19 02:19:00 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 02:19:00 +0200 Subject: [coreboot] build service results for r6513 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6513 to the coreboot repository. This caused the following changes: Change Log: * Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer Acked-by: Peter Stuge Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=dbm690t&vendor=amd&num=2 Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=inagua&vendor=amd&num=2 Compilation of amd:mahogany is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=mahogany&vendor=amd&num=2 Compilation of amd:mahogany_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=mahogany_fam10&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=persimmon&vendor=amd&num=2 Compilation of amd:pistachio is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=pistachio&vendor=amd&num=2 Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=serengeti_cheetah&vendor=amd&num=2 Compilation of amd:tilapia_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=tilapia_fam10&vendor=amd&num=2 Compilation of arima:hdama is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=hdama&vendor=arima&num=2 Compilation of asrock:939a785gmh is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=939a785gmh&vendor=asrock&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=e350m1&vendor=asrock&num=2 Compilation of asus:a8v-e_deluxe is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=a8v-e_deluxe&vendor=asus&num=2 Compilation of asus:a8v-e_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=a8v-e_se&vendor=asus&num=2 Compilation of asus:m2n-e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=m2n-e&vendor=asus&num=2 Compilation of asus:m2v is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=m2v&vendor=asus&num=2 Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=m2v-mx_se&vendor=asus&num=2 Compilation of asus:m4a78-em is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=m4a78-em&vendor=asus&num=2 Compilation of asus:m4a785-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=m4a785-m&vendor=asus&num=2 Compilation of broadcom:blast is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=blast&vendor=broadcom&num=2 Compilation of getac:p470 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=p470&vendor=getac&num=2 Compilation of gigabyte:ga_2761gxdk is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=ga_2761gxdk&vendor=gigabyte&num=2 Compilation of gigabyte:m57sli is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=m57sli&vendor=gigabyte&num=2 Compilation of gigabyte:ma785gmt is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=ma785gmt&vendor=gigabyte&num=2 Compilation of gigabyte:ma78gm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=ma78gm&vendor=gigabyte&num=2 Compilation of hp:dl145_g1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=dl145_g1&vendor=hp&num=2 Compilation of hp:dl145_g3 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=dl145_g3&vendor=hp&num=2 Compilation of ibase:mb899 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=mb899&vendor=ibase&num=2 Compilation of ibm:e325 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=e325&vendor=ibm&num=2 Compilation of ibm:e326 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=e326&vendor=ibm&num=2 Compilation of iei:kino-780am2-fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=kino-780am2-fam10&vendor=iei&num=2 Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=d945gclf&vendor=intel&num=2 Compilation of iwave:iWRainbowG6 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=iWRainbowG6&vendor=iwave&num=2 Compilation of iwill:dk8_htx is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=dk8_htx&vendor=iwill&num=2 Compilation of iwill:dk8s2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=dk8s2&vendor=iwill&num=2 Compilation of iwill:dk8x is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=dk8x&vendor=iwill&num=2 Compilation of jetway:pa78vm5 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=pa78vm5&vendor=jetway&num=2 Compilation of kontron:986lcd-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=986lcd-m&vendor=kontron&num=2 Compilation of kontron:kt690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=kt690&vendor=kontron&num=2 Compilation of lenovo:x60 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=x60&vendor=lenovo&num=2 Compilation of msi:ms7135 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=ms7135&vendor=msi&num=2 Compilation of msi:ms7260 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=ms7260&vendor=msi&num=2 Compilation of msi:ms9185 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=ms9185&vendor=msi&num=2 Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=ms9282&vendor=msi&num=2 Compilation of newisys:khepri is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=khepri&vendor=newisys&num=2 Compilation of nvidia:l1_2pvv is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=l1_2pvv&vendor=nvidia&num=2 Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=rm4100&vendor=rca&num=2 Compilation of roda:rk886ex is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=rk886ex&vendor=roda&num=2 Compilation of sunw:ultra40 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=ultra40&vendor=sunw&num=2 Compilation of supermicro:h8dme is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=h8dme&vendor=supermicro&num=2 Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=h8dmr&vendor=supermicro&num=2 Compilation of technexion:tim5690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=tim5690&vendor=technexion&num=2 Compilation of technexion:tim8690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=tim8690&vendor=technexion&num=2 Compilation of thomson:ip1000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=ip1000&vendor=thomson&num=2 Compilation of tyan:s2850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s2850&vendor=tyan&num=2 Compilation of tyan:s2875 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s2875&vendor=tyan&num=2 Compilation of tyan:s2880 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s2880&vendor=tyan&num=2 Compilation of tyan:s2881 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s2881&vendor=tyan&num=2 Compilation of tyan:s2882 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s2882&vendor=tyan&num=2 Compilation of tyan:s2885 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s2885&vendor=tyan&num=2 Compilation of tyan:s2891 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s2891&vendor=tyan&num=2 Compilation of tyan:s2892 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s2892&vendor=tyan&num=2 Compilation of tyan:s2895 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s2895&vendor=tyan&num=2 Compilation of tyan:s2912 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s2912&vendor=tyan&num=2 Compilation of tyan:s4880 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s4880&vendor=tyan&num=2 Compilation of tyan:s4882 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6513&device=s4882&vendor=tyan&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Tue Apr 19 02:36:39 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 02:36:39 +0200 Subject: [coreboot] [commit] r6514 - trunk/src/northbridge/amd/amdk8 Message-ID: Author: stepan Date: Tue Apr 19 02:36:39 2011 New Revision: 6514 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6514 Log: cleanup wrong use of defined() after exporting all variables in Kconfig Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c trunk/src/northbridge/amd/amdk8/raminit.c Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/incoherent_ht.c Tue Apr 19 01:51:12 2011 (r6513) +++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c Tue Apr 19 02:36:39 2011 (r6514) @@ -7,10 +7,6 @@ #include #include -#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT - #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 -#endif - // Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM #ifndef K8_ALLOCATE_MMIO_RANGE #define K8_ALLOCATE_MMIO_RANGE 0 @@ -568,7 +564,7 @@ return reset_needed; } -#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) // || defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) +#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55 static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) { uint32_t dword; Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Tue Apr 19 01:51:12 2011 (r6513) +++ trunk/src/northbridge/amd/amdk8/raminit.c Tue Apr 19 02:36:39 2011 (r6514) @@ -1165,7 +1165,7 @@ if (unbuffered) { if ((has_dualch) && (!is_cpu_pre_d0())) { dcl |= DCL_UnBuffDimm; -#if defined(CONFIG_CPU_AMD_SOCKET_939) && CONFIG_CPU_AMD_SOCKET_939 +#if CONFIG_CPU_AMD_SOCKET_939 if ((cpuid_eax(1) & 0x30) == 0x30) { /* CS[7:4] is copy of CS[3:0], should be set for 939 socket */ dcl |= DCL_UpperCSMap; @@ -1389,7 +1389,7 @@ [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ }; -#if defined(CONFIG_CPU_AMD_SOCKET_939) && CONFIG_CPU_AMD_SOCKET_939 +#if CONFIG_CPU_AMD_SOCKET_939 /* return the minimum cycle time and set 2T accordingly */ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { @@ -1511,14 +1511,14 @@ return dloading_cycle_time; } -#endif /* #if defined(CONFIG_CPU_AMD_SOCKET_939) */ +#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; unsigned min_cycle_time, min_latency, bios_cycle_time; -#if defined(CONFIG_CPU_AMD_SOCKET_939) +#if CONFIG_CPU_AMD_SOCKET_939 unsigned dloading_cycle_time; #endif int i; @@ -1674,7 +1674,7 @@ #endif #endif -#if defined(CONFIG_CPU_AMD_SOCKET_939) && CONFIG_CPU_AMD_SOCKET_939 +#if CONFIG_CPU_AMD_SOCKET_939 dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); if (dloading_cycle_time > min_cycle_time) { min_cycle_time = dloading_cycle_time; From svn at coreboot.org Tue Apr 19 03:04:41 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 03:04:41 +0200 Subject: [coreboot] build service results for r6514 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6514 to the coreboot repository. This caused the following changes: Change Log: cleanup wrong use of defined() after exporting all variables in Kconfig Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:dbm690t has been fixed Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=inagua&vendor=amd&num=2 Compilation of amd:mahogany is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=mahogany&vendor=amd&num=2 Compilation of amd:mahogany_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=mahogany_fam10&vendor=amd&num=2 Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=persimmon&vendor=amd&num=2 Compilation of amd:pistachio has been fixed Compilation of amd:serengeti_cheetah has been fixed Compilation of amd:tilapia_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=tilapia_fam10&vendor=amd&num=2 Compilation of arima:hdama has been fixed Compilation of asrock:939a785gmh is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=939a785gmh&vendor=asrock&num=2 Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=e350m1&vendor=asrock&num=2 Compilation of asus:a8v-e_deluxe has been fixed Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2n-e has been fixed Compilation of asus:m2v has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of asus:m4a78-em is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=m4a78-em&vendor=asus&num=2 Compilation of asus:m4a785-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=m4a785-m&vendor=asus&num=2 Compilation of broadcom:blast has been fixed Compilation of getac:p470 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=p470&vendor=getac&num=2 Compilation of gigabyte:ga_2761gxdk has been fixed Compilation of gigabyte:m57sli has been fixed Compilation of gigabyte:ma785gmt is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=ma785gmt&vendor=gigabyte&num=2 Compilation of gigabyte:ma78gm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=ma78gm&vendor=gigabyte&num=2 Compilation of hp:dl145_g1 has been fixed Compilation of hp:dl145_g3 has been fixed Compilation of ibase:mb899 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=mb899&vendor=ibase&num=2 Compilation of ibm:e325 has been fixed Compilation of ibm:e326 has been fixed Compilation of iei:kino-780am2-fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=kino-780am2-fam10&vendor=iei&num=2 Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=d945gclf&vendor=intel&num=2 Compilation of iwave:iWRainbowG6 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=iWRainbowG6&vendor=iwave&num=2 Compilation of iwill:dk8_htx has been fixed Compilation of iwill:dk8s2 has been fixed Compilation of iwill:dk8x has been fixed Compilation of jetway:pa78vm5 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=pa78vm5&vendor=jetway&num=2 Compilation of kontron:986lcd-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=986lcd-m&vendor=kontron&num=2 Compilation of kontron:kt690 has been fixed Compilation of lenovo:x60 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=x60&vendor=lenovo&num=2 Compilation of msi:ms7135 has been fixed Compilation of msi:ms7260 has been fixed Compilation of msi:ms9185 has been fixed Compilation of msi:ms9282 has been fixed Compilation of newisys:khepri has been fixed Compilation of nvidia:l1_2pvv has been fixed Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=rm4100&vendor=rca&num=2 Compilation of roda:rk886ex is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=rk886ex&vendor=roda&num=2 Compilation of sunw:ultra40 has been fixed Compilation of supermicro:h8dme has been fixed Compilation of supermicro:h8dmr has been fixed Compilation of technexion:tim5690 has been fixed Compilation of technexion:tim8690 has been fixed Compilation of thomson:ip1000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6514&device=ip1000&vendor=thomson&num=2 Compilation of tyan:s2850 has been fixed Compilation of tyan:s2875 has been fixed Compilation of tyan:s2880 has been fixed Compilation of tyan:s2881 has been fixed Compilation of tyan:s2882 has been fixed Compilation of tyan:s2885 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed Compilation of tyan:s2912 has been fixed Compilation of tyan:s4880 has been fixed Compilation of tyan:s4882 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Tue Apr 19 03:18:54 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 03:18:54 +0200 Subject: [coreboot] [commit] r6515 - in trunk/src: cpu/x86/smm southbridge/amd/sb700 Message-ID: Author: stepan Date: Tue Apr 19 03:18:54 2011 New Revision: 6515 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6515 Log: Fix some more misuses of ifdef/if defined Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/cpu/x86/smm/smmrelocate.S trunk/src/southbridge/amd/sb700/sb700.c Modified: trunk/src/cpu/x86/smm/smmrelocate.S ============================================================================== --- trunk/src/cpu/x86/smm/smmrelocate.S Tue Apr 19 02:36:39 2011 (r6514) +++ trunk/src/cpu/x86/smm/smmrelocate.S Tue Apr 19 03:18:54 2011 (r6515) @@ -22,17 +22,18 @@ // Make sure no stage 2 code is included: #define __PRE_RAM__ -#if !defined(CONFIG_NORTHBRIDGE_AMD_AMDK8) && !defined(CONFIG_NORTHBRIDGE_AMD_FAM10) +/* On AMD's platforms we can set SMBASE by writing an MSR */ +#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 // FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? // It's needed right now because we get our DEFAULT_PMBASE from // here. -#if defined(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG_SOUTHBRIDGE_INTEL_I82801GX #include "../../../southbridge/intel/i82801gx/i82801gx.h" -#elif defined(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) +#elif CONFIG_SOUTHBRIDGE_INTEL_I82801DX #include "../../../southbridge/intel/i82801dx/i82801dx.h" -#elif defined(CONFIG_SOUTHBRIDGE_INTEL_SCH) +#elif CONFIG_SOUTHBRIDGE_INTEL_SCH #include "../../../southbridge/intel/sch/sch.h" #else #error "Southbridge needs SMM handler support." @@ -152,7 +153,7 @@ /* End of southbridge specific section. */ -#if defined(CONFIG_DEBUG_SMM_RELOCATION) && CONFIG_DEBUG_SMM_RELOCATION +#if CONFIG_DEBUG_SMM_RELOCATION /* print [SMM-x] so we can determine if CPUx went to SMM */ movw $CONFIG_TTYS0_BASE, %dx mov $'[', %al Modified: trunk/src/southbridge/amd/sb700/sb700.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.c Tue Apr 19 02:36:39 2011 (r6514) +++ trunk/src/southbridge/amd/sb700/sb700.c Tue Apr 19 03:18:54 2011 (r6515) @@ -226,7 +226,7 @@ } } -#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SP5100 struct chip_operations southbridge_amd_sp5100_ops = { CHIP_NAME("ATI SP5100") .enable_dev = sb7xx_51xx_enable, From stefan.reinauer at coreboot.org Tue Apr 19 03:33:46 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Mon, 18 Apr 2011 18:33:46 -0700 Subject: [coreboot] potentially wrong uses of ifdef/if defined Message-ID: <4DACE67A.3030206@coreboot.org> Hi as you probably know, we are using a slightly modified Kconfig that emits #define CONFIG_FOO 0 for all unset bools in our Kconfig files in order to avoid nasty checks a la #if defined(CONFIG_FOO) && CONFIG_FOO However, this modification to Kconfig was incomplete, and so only some but not all config defines got set correctly. I fixed this bug in r6511 but unfortunately there is a whole lot of code that still uses the old method, sometimes assuming that a value has been set in Kconfig by checking #if defined(CONFIG_FOO) These cases will cause the preprocessor to make the wrong choice and compile the code in, even though the variable is not set in Kconfig. So I did a quick grep over the source code to determine our usage of ifdef, ifndef and if defined. All these occurences might need fixing, but certainly not all of them do. Can someone help with going through these and figuring out which ones need changing and which ones don't? Any help is highly appreciated. Example 1: #if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL can be written as #if CONFIG_PCI_OPTION_ROM_RUN_YABEL Example 2: #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL needs to be written as #if CONFIG_PCI_OPTION_ROM_RUN_YABEL Example 3: #ifndef CONFIG_TTYS0_BASE is not a bool value, and hence does not have to be changed. Here's the list: ./src/arch/x86/include/bootblock_common.h:#ifdef CONFIG_BOOTBLOCK_CPU_INIT ./src/arch/x86/include/bootblock_common.h:#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT ./src/arch/x86/include/bootblock_common.h:#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT ./src/devices/oprom/x86emu/debug.h:#ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVEL ./src/devices/oprom/yabel/compat/functions.c:#ifdef CONFIG_YABEL_VIRTMEM_LOCATION ./src/devices/oprom/yabel/device.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/device.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/device.h:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/device.h:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/io.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/io.c:#ifdef CONFIG_ARCH_X86 ./src/devices/oprom/yabel/io.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/io.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/mem.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/pciexp_device.c:#ifdef CONFIG_PCIE_TUNING ./src/devices/pciexp_device.c:#ifdef CONFIG_PCIE_TUNING ./src/drivers/ati/ragexl/atyfb.h:#ifdef CONFIG_PMAC_PBOOK ./src/lib/jpeg.c:#ifdef CONFIG_PPC ./src/northbridge/via/cn700/raminit.c:#ifdef CONFIG_DEBUG_RAM_SETUP ./src/northbridge/via/vx800/early_smbus.c:#ifdef CONFIG_DEBUG_SMBUS ./src/pc80/i8254.c:#ifdef CONFIG_UDELAY_TIMER2 ./src/southbridge/amd/sb700/early_setup.c:#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 ./src/southbridge/amd/sb700/early_setup.c:#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 ./src/southbridge/amd/sb700/early_setup.c:#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 ./src/southbridge/amd/sb700/early_setup.c:#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 ./src/southbridge/amd/sb700/lpc.c:#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 ./src/southbridge/amd/sb700/sata.c:#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 ./src/arch/x86/include/arch/pirq_routing.h:#ifndef CONFIG_IRQ_SLOT_COUNT ./src/boot/selfboot.c:#ifndef CONFIG_BIG_ENDIAN ./src/cpu/amd/model_gx2/syspreinit.c:#ifndef CONFIG_CACHE_AS_RAM ./src/cpu/amd/model_lx/syspreinit.c:#ifndef CONFIG_CACHE_AS_RAM ./src/cpu/x86/mtrr/mtrr.c:#ifndef CONFIG_VAR_MTRR_HOLE ./src/devices/oprom/yabel/device.c:#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/device.c:#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/device.c:#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/devices/oprom/yabel/device.c:#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/include/uart8250.h:#ifndef CONFIG_TTYS0_BASE ./src/include/uart8250.h:#ifndef CONFIG_TTYS0_BAUD ./src/include/uart8250.h:#ifndef CONFIG_TTYS0_DIV ./src/include/uart8250.h:#ifndef CONFIG_TTYS0_LCS ./src/lib/version.c:#ifndef CONFIG_MAINBOARD_VENDOR ./src/lib/version.c:#ifndef CONFIG_MAINBOARD_PART_NUMBER ./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT ./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED ./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef CONFIG_ENABLE_APIC_EXT_ID ./src/pc80/mc146818rtc_early.c:#ifndef CONFIG_MAX_REBOOT_CNT ./src/southbridge/amd/amd8111/acpi.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/amd/cimx_wrapper/sb800/bootblock.c:#ifndef CONFIG_TTYS0_DIV ./src/southbridge/amd/rs780/early_setup.c:#ifndef CONFIG_NORTHBRIDGE_AMD_AMDFAM10 ./src/southbridge/amd/sb600/sm.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/amd/sb700/sm.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/amd/sb800/sm.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/intel/esb6300/lpc.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/intel/i3100/lpc.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/intel/i82801cx/lpc.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/intel/i82801dx/i82801dx.h:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/intel/i82801ex/lpc.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/intel/i82801gx/i82801gx.h:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/nvidia/ck804/lpc.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/nvidia/mcp55/lpc.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/sis/sis966/lpc.c:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/southbridge/via/vt8237r/vt8237r.h:#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ./src/arch/x86/boot/coreboot_table.c:#if defined(CONFIG_BOOTSPLASH) && CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER ./src/arch/x86/include/arch/interrupt.h:#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE ./src/arch/x86/include/bootblock_common.h: (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT)) ./src/arch/x86/lib/exception.c:#if defined(CONFIG_GDB_STUB) && CONFIG_GDB_STUB == 1 ./src/arch/x86/lib/ioapic.c:#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT ./src/console/post.c:#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 ./src/cpu/amd/car/cache_as_ram.inc:#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) ./src/cpu/amd/car/cache_as_ram.inc:#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK ./src/cpu/intel/car/cache_as_ram.inc:#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) ./src/cpu/intel/car/cache_as_ram.inc:#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK ./src/cpu/intel/model_106cx/cache_as_ram.inc:#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) ./src/cpu/intel/model_106cx/cache_as_ram.inc:#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK ./src/cpu/intel/model_106cx/cache_as_ram.inc:#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) ./src/cpu/intel/model_6ex/cache_as_ram.inc:#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) ./src/cpu/intel/model_6ex/cache_as_ram.inc:#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK ./src/cpu/intel/model_6ex/cache_as_ram.inc:#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) ./src/cpu/intel/model_6fx/cache_as_ram.inc:#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) ./src/cpu/intel/model_6fx/cache_as_ram.inc:#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK ./src/cpu/intel/model_6fx/cache_as_ram.inc:#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) ./src/cpu/via/car/cache_as_ram.inc:#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK ./src/cpu/x86/lapic/lapic_cpu_init.c:#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) ./src/cpu/x86/lapic/lapic_cpu_init.c:#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) ./src/cpu/x86/mtrr/earlymtrr.c:#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0) ./src/cpu/x86/mtrr/earlymtrr.c:#if defined(CONFIG_XIP_ROM_SIZE) ./src/devices/oprom/x86.c:#if defined(CONFIG_GEODE_VSA) && CONFIG_GEODE_VSA ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_JMP) && CONFIG_X86EMU_DEBUG_JMP ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_TRACE) && CONFIG_X86EMU_DEBUG_TRACE ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_PNP) && CONFIG_X86EMU_DEBUG_PNP ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_DISK) && CONFIG_X86EMU_DEBUG_DISK ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_PMM) && CONFIG_X86EMU_DEBUG_PMM ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_VBE) && CONFIG_X86EMU_DEBUG_VBE ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_INT10) && CONFIG_X86EMU_DEBUG_INT10 ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_INTERRUPTS) && CONFIG_X86EMU_DEBUG_INTERRUPTS ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS) && CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_MEM) && CONFIG_X86EMU_DEBUG_MEM ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_IO) && CONFIG_X86EMU_DEBUG_IO ./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG ./src/devices/oprom/yabel/compat/functions.c:#if !defined(CONFIG_YABEL_DIRECTHW) || (!CONFIG_YABEL_DIRECTHW) ./src/devices/oprom/yabel/debug.h:#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG ./src/devices/oprom/yabel/device.c:#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG ./src/devices/oprom/yabel/device.c:#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG ./src/devices/oprom/yabel/device.c:#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG ./src/devices/oprom/yabel/interrupt.c:#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 ./src/devices/oprom/yabel/interrupt.c:#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 ./src/devices/oprom/yabel/io.c:#if defined(CONFIG_YABEL_DIRECTHW) && (CONFIG_YABEL_DIRECTHW == 1) ./src/devices/oprom/yabel/io.c:#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 ./src/devices/oprom/yabel/mem.c:#if !defined(CONFIG_YABEL_DIRECTHW) || (!CONFIG_YABEL_DIRECTHW) ./src/devices/pci_rom.c:#if defined(CONFIG_BOARD_EMULATION_QEMU_X86) && CONFIG_BOARD_EMULATION_QEMU_X86 ./src/include/assert.h:#if defined(__PRE_RAM__) && !CONFIG_CACHE_AS_RAM ./src/include/cpu/cpu.h:#if !defined(CONFIG_WAIT_BEFORE_CPUS_INIT) || CONFIG_WAIT_BEFORE_CPUS_INIT==0 ./src/include/cpu/x86/mtrr.h:#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE) ./src/include/cpu/x86/mtrr.h:#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE) ./src/include/cpu/x86/mtrr.h:#if !defined(CONFIG_RAMTOP) ./src/include/cpu/x86/mtrr.h:# error "CONFIG_RAMTOP not defined" ./src/include/cpu/x86/mtrr.h:#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) ./src/include/cpu/x86/mtrr.h:#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0) ./src/include/cpu/x86/mtrr.h:#if defined(CONFIG_XIP_ROM_SIZE) ./src/include/cpu/x86/mtrr.h:# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK ./src/include/lib.h:#if defined(CONFIG_CPU_AMD_LX) && CONFIG_CPU_AMD_LX ./src/lib/fallback_boot.c:#if defined(CONFIG_BOOTSPLASH) && CONFIG_BOOTSPLASH && !CONFIG_COREBOOT_KEEP_FRAMEBUFFER ./src/lib/uart8250.c:#if CONFIG_USE_OPTION_TABLE && !defined(__SMM__) ./src/lib/version.c:#error CONFIG_MAINBOARD_VENDOR not defined ./src/lib/version.c:#error CONFIG_MAINBOARD_PART_NUMBER not defined ./src/mainboard/kontron/986lcd-m/mainboard.c:#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/mainboard/kontron/986lcd-m/mainboard.c:#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/mainboard/kontron/986lcd-m/mainboard.c:#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/northbridge/amd/amdk8/f.h:#if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \ ./src/northbridge/amd/amdk8/f.h: ((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__)) ./src/northbridge/amd/amdk8/raminit.h:#if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO ./src/northbridge/amd/amdk8/raminit_f.c:#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || (CONFIG_INTERLEAVE_CHIP_SELECTS == 0) ./src/northbridge/amd/amdk8/raminit_f.c:#if defined(CONFIG_MAX_MEM_CLOCK) ./src/northbridge/amd/amdk8/raminit_f.c:#if defined(CONFIG_ECC_MEMORY) && (CONFIG_ECC_MEMORY == 0) ./src/northbridge/intel/i82830/smihandler.c:#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW ./src/northbridge/intel/i82830/vga.c:#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/northbridge/intel/i82830/vga.c:#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL ./src/northbridge/intel/i945/raminit.c:#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) ./src/northbridge/intel/i945/raminit.c:#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) ./src/northbridge/intel/i945/raminit.c:#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) ./src/northbridge/intel/i945/raminit.c:#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) ./src/northbridge/intel/i945/raminit.c:#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) ./src/northbridge/intel/i945/raminit.c:#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) ./src/northbridge/intel/i945/raminit.c:#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) ./src/northbridge/intel/i945/raminit.c:#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) ./src/northbridge/intel/i945/raminit.c:#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) ./src/southbridge/ti/pci1x2x/pci1x2x.c:#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \ ./src/southbridge/ti/pci1x2x/pci1x2x.c: !defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \ ./src/southbridge/ti/pci1x2x/pci1x2x.c: !defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \ ./src/southbridge/ti/pci1x2x/pci1x2x.c: !defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \ ./src/southbridge/ti/pci1x2x/pci1x2x.c: !defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \ ./src/southbridge/ti/pci1x2x/pci1x2x.c: !defined(CONFIG_TI_PCMCIA_CARDBUS_MRR)) ./src/southbridge/via/k8t890/early_car.c:#if defined(CONFIG_SOUTHBRIDGE_VIA_K8M800) ./src/southbridge/via/k8t890/early_car.c:#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) ./src/southbridge/via/k8t890/early_car.c:#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800PRO) ./src/southbridge/via/k8t890/early_car.c:#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8M890) ./src/southbridge/via/k8t890/early_car.c:#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T890) ./src/southbridge/via/vt8237r/lpc.c: #if defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) ./src/superio/ite/it8716f/it8716f.h:#if defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) && CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL ./src/superio/ite/it8716f/superio.c:#if !defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) || !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL From svn at coreboot.org Tue Apr 19 03:36:25 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 03:36:25 +0200 Subject: [coreboot] [commit] r6516 - trunk/src/arch/x86/init Message-ID: Author: stepan Date: Tue Apr 19 03:36:24 2011 New Revision: 6516 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6516 Log: Recently the 3 projects using the new AMD reference code have been failing the check for globals (or statics) in romstage. This causes ASRock E350M1, AMD Inagua, and AMD Persimmon builds to fail with the message "Do not use global variables in romstage". The message is working as intended. It is detecting data declared as 'static' when 'static const' was intended. The code executes correctly because it never tries to modify the data. To make reference code updates easy, it is probably best to avoid modifying the AMD provided code if possible. The following change bypasses the "Do not use global variables in romstage" check for the AMD reference code only. Signed-off-by: Scott Duplichan Acked-by: Stefan Reinauer Modified: trunk/src/arch/x86/init/bootblock.ld Modified: trunk/src/arch/x86/init/bootblock.ld ============================================================================== --- trunk/src/arch/x86/init/bootblock.ld Tue Apr 19 03:18:54 2011 (r6515) +++ trunk/src/arch/x86/init/bootblock.ld Tue Apr 19 03:36:24 2011 (r6516) @@ -49,5 +49,6 @@ *(.comment.*) *(.note.*) } - _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage"); + + _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage"); } From svn at coreboot.org Tue Apr 19 03:47:14 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 03:47:14 +0200 Subject: [coreboot] build service results for r6515 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6515 to the coreboot repository. This caused the following changes: Change Log: Fix some more misuses of ifdef/if defined Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6515&device=inagua&vendor=amd&num=2 Compilation of amd:mahogany has been fixed Compilation of amd:mahogany_fam10 has been fixed Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6515&device=persimmon&vendor=amd&num=2 Compilation of amd:tilapia_fam10 has been fixed Compilation of asrock:939a785gmh has been fixed Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6515&device=e350m1&vendor=asrock&num=2 Compilation of asus:m4a78-em has been fixed Compilation of asus:m4a785-m has been fixed Compilation of getac:p470 has been fixed Compilation of gigabyte:ma785gmt has been fixed Compilation of gigabyte:ma78gm has been fixed Compilation of ibase:mb899 has been fixed Compilation of iei:kino-780am2-fam10 has been fixed Compilation of intel:d945gclf has been fixed Compilation of iwave:iWRainbowG6 has been fixed Compilation of jetway:pa78vm5 has been fixed Compilation of kontron:986lcd-m has been fixed Compilation of lenovo:x60 has been fixed Compilation of rca:rm4100 has been fixed Compilation of roda:rk886ex has been fixed Compilation of thomson:ip1000 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Tue Apr 19 04:55:37 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 04:55:37 +0200 Subject: [coreboot] build service results for r6516 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6516 to the coreboot repository. This caused the following changes: Change Log: Recently the 3 projects using the new AMD reference code have been failing the check for globals (or statics) in romstage. This causes ASRock E350M1, AMD Inagua, and AMD Persimmon builds to fail with the message "Do not use global variables in romstage". The message is working as intended. It is detecting data declared as 'static' when 'static const' was intended. The code executes correctly because it never tries to modify the data. To make reference code updates easy, it is probably best to avoid modifying the AMD provided code if possible. The following change bypasses the "Do not use global variables in romstage" check for the AMD reference code only. Signed-off-by: Scott Duplichan Acked-by: Stefan Reinauer Build Log: Compilation of amd:inagua has been fixed Compilation of amd:persimmon has been fixed Compilation of asrock:e350m1 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Tue Apr 19 08:40:56 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 08:40:56 +0200 Subject: [coreboot] [commit] r6517 - trunk/src/northbridge/amd/amdht Message-ID: Author: zbao Date: Tue Apr 19 08:40:56 2011 New Revision: 6517 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6517 Log: The "temp" will be used later. So it has to be calculated correctly. Comment by Peter, The variable name "temp" unfortunately does not explain what the value is. The commit message also does not have hints. Hopefully in the future it's possible to also use a brief moment to improve the clarity of the code, while it is already being fixed for some other reason. Ie. fixing up variable names, writing particularly informative commit messages, or of course both at the same time! :) Signed-off-by: Zheng Bao Acked-by: Marc Jones Modified: trunk/src/northbridge/amd/amdht/h3ncmn.c Modified: trunk/src/northbridge/amd/amdht/h3ncmn.c ============================================================================== --- trunk/src/northbridge/amd/amdht/h3ncmn.c Tue Apr 19 03:36:24 2011 (r6516) +++ trunk/src/northbridge/amd/amdht/h3ncmn.c Tue Apr 19 08:40:56 2011 (r6517) @@ -565,7 +565,8 @@ /* bits[15,13,12] specify the cores */ /* Support Downcoring */ - cores = ((temp & 8) >> 1) + (temp & 3) + 1; + temp = ((temp & 8) >> 1) + (temp & 3); + cores = temp + 1; AmdPCIReadBits (MAKE_SBDFO(makePCISegmentFromNode(node), makePCIBusFromNode(node), makePCIDeviceFromNode(node), From mr.nuke.me at gmail.com Tue Apr 19 12:22:33 2011 From: mr.nuke.me at gmail.com (Alex G.) Date: Tue, 19 Apr 2011 13:22:33 +0300 Subject: [coreboot] potentially wrong uses of ifdef/if defined In-Reply-To: <4DACE67A.3030206@coreboot.org> References: <4DACE67A.3030206@coreboot.org> Message-ID: <4DAD6269.2020709@gmail.com> On 04/19/2011 04:33 AM, Stefan Reinauer wrote: > ./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT #ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif > ./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef > CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED #ifndef CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0 #endif > ./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef CONFIG_ENABLE_APIC_EXT_ID #ifndef CONFIG_ENABLE_APIC_EXT_ID #define CONFIG_ENABLE_APIC_EXT_ID 0 #endif These lines can just be deleted. Alex From cubicool at gmail.com Tue Apr 19 16:25:51 2011 From: cubicool at gmail.com (Jeremy Moles) Date: Tue, 19 Apr 2011 10:25:51 -0400 Subject: [coreboot] SuperI/O Access (Kernelspace) In-Reply-To: <20110415000711.29877.qmail@stuge.se> References: <1302822804.2593.10.camel@lv-426> <20110415000711.29877.qmail@stuge.se> Message-ID: <1303223151.21377.6.camel@lv-426> On Fri, 2011-04-15 at 02:07 +0200, Peter Stuge wrote: > Jeremy Moles wrote: > > working great now .. via userspace > .. > > However, I'd like to be able to toggle the power on via a kernel > > driver as well, > > Why? > > > > but I'm having trouble accessing the same memory range from > > kernelspace. > > > > For example: > > > > iotools io_read8 0xA00 > > io_read8 is not a memory access, it is an I/O access. x86 has two > different address spaces on the bus, and different instructions to > access them. > > The superio is not memory mapped.. > > > > When I try to do the same thing in the kernel: > > > > unsigned short b; > > unsigned short* ptr = (unsigned short*)(0xA00); > > > > if(access_ok(VERIFY_READ, ptr, 8)) { > > get_user(b, ptr); > > > > ...I immediately get a segfault. > > ..so that's not the way to reach it. Last time I did this I used > inb() and outb(). Remember to use barriers as neccessary and also > make sure that request_region() succeeds before you touch any > hardware. > > The proper way to implement GPIO support is btw to write a gpio class > driver for it. There are lots of gpio drivers already in the kernel. > I would actually not be surprised if your chip is already supported > by one of them, and if not one could probably be extended easily. The > GPIO drivers are exposed to userspace via sysfs. > > Again; why does your other kernel driver need to deal with this GPIO? > This smells like a questionable design decision was made somewhere in > the chain. Better fix that sooner than later in that case.. It's really just an exercise to see whether it can be done or not. I thought it might be interesting to continue to experiment with the hardware a bit more. The real code to control the device is just a bash script using iotools. However, using inb() doesn't change anything; it still panics the kernel immediately. There must be some kernel setup I'm mising... oh well. > //Peter > From r.marek at assembler.cz Tue Apr 19 20:24:35 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 19 Apr 2011 20:24:35 +0200 Subject: [coreboot] rtc wake up does not work on ASUS M2V-MX SE In-Reply-To: References: <20110418230858.GA2822@coreboot.org> Message-ID: <4DADD363.9070904@assembler.cz> Hi I think two things are missing: 1) Paste this into the dsdt table: Device(RTC0) { Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) }) } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ Now the RTC device should be visible. Second problem is that a wakeup event is not enabled. This can be fixed most likely here: Index: lpc.c =================================================================== --- lpc.c (revision 6474) +++ lpc.c (working copy) @@ -237,6 +237,9 @@ printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); #endif + /* enable power button wakeup and from RTC */ + outb(0x5, VT8237R_ACPI_IO_BASE + 0x3); + /* All SMI on, both IDE buses ON, PSON rising edge. */ outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c); Completely untested but might even work. Please let me know if it works for you, Thanks, Rudolf From support at plecavalier.com Tue Apr 19 20:22:13 2011 From: support at plecavalier.com (Philippe LeCavalier) Date: Tue, 19 Apr 2011 14:22:13 -0400 Subject: [coreboot] Dell Latitude D820 Message-ID: <1303235645-sup-3769@plc.intranet.plecavalier.com> Hi All. Just joined the list to find out your opinion on whether or not I should put coreboot on my laptop. First off, what do I gain? I read it's faster but I don't really think my BIOS is slow. OR is it? Perhaps seeing is believing... Second, I've created a small txt file for reference. Felt this mail might get kinda bulky otherwise. So whatever isn't answered below hopefully is in the file. Step 1: A very brief description of your system: board vendor, board name, CPU, northbridge, southbridge, and optionally other important details. Dell Latitude D820, Intel T2500(2.0GHz) CEntrino Duo, Intel 82801,Intel Mobile 945PM, Nvidia Go 7400 256MB, Intel Pro 3945 minipci, Broadcom gigabit nic PCIe Step 2: Linux "lspci -tvnn" output for your system, generated by booting Linux via the original BIOS and runnning lspci. See attached Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example "Winbond W83627HF" and/or run "superiotool -dV"). See attached Step 4: Type of BIOS device (see the question "How do I identify the BIOS chip on my mainboard?" below). Please send us the output of "flashrom -V" see attached Step 5: URL to the mainboard specifications page (optional). http://www.dell.com/downloads/global/products/latit/en/spec_latit_d820_en.pdf Step 6: Any other relevant information you can provide I'm running Deb Wheezy with GRUB2 -- Thanks, Phil -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: coreboot-nfo.txt URL: From svn at coreboot.org Tue Apr 19 21:21:27 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 21:21:27 +0200 Subject: [coreboot] [commit] r6518 - trunk/src/southbridge/intel/i82371eb Message-ID: Author: oxygene Date: Tue Apr 19 21:21:27 2011 New Revision: 6518 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6518 Log: Fix compilation of all i82371eb boards when ACPI tables aren't generated Signed-off-by: Idwer Vollering Acked-by: Stefan Reinauer Modified: trunk/src/southbridge/intel/i82371eb/Makefile.inc Modified: trunk/src/southbridge/intel/i82371eb/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82371eb/Makefile.inc Tue Apr 19 08:40:56 2011 (r6517) +++ trunk/src/southbridge/intel/i82371eb/Makefile.inc Tue Apr 19 21:21:27 2011 (r6518) @@ -24,8 +24,8 @@ driver-y += usb.c driver-y += smbus.c driver-y += reset.c -driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c +driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +driver-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c romstage-y += early_pm.c romstage-y += early_smbus.c From svn at coreboot.org Tue Apr 19 21:34:26 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 21:34:26 +0200 Subject: [coreboot] [commit] r6519 - in trunk/util/nvramtool: . cli Message-ID: Author: jakllsch Date: Tue Apr 19 21:34:25 2011 New Revision: 6519 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6519 Log: Cast arguments to ctype(3) functions through (int)(unsigned char). Signed-Off-By: Jonathan Kollasch Acked-By: Jonathan Kollasch Modified: trunk/util/nvramtool/cli/nvramtool.c trunk/util/nvramtool/cmos_ops.c Modified: trunk/util/nvramtool/cli/nvramtool.c ============================================================================== --- trunk/util/nvramtool/cli/nvramtool.c Tue Apr 19 21:21:27 2011 (r6518) +++ trunk/util/nvramtool/cli/nvramtool.c Tue Apr 19 21:34:25 2011 (r6519) @@ -800,7 +800,7 @@ case CMOS_ENTRY_STRING: w = (char *)(unsigned long)value; while (*w) { - if(!isprint(*w)) { + if(!isprint((int)(unsigned char)*w)) { if (show_name) printf("# Bad value -> %s\n", e->name); else @@ -846,7 +846,7 @@ uint16_t result; int negative; - for (p = value; isspace(*p); p++) ; + for (p = value; isspace((int)(unsigned char)*p); p++) ; negative = (*p == '-'); n = strtoul(value, (char **)&p, 0); Modified: trunk/util/nvramtool/cmos_ops.c ============================================================================== --- trunk/util/nvramtool/cmos_ops.c Tue Apr 19 21:21:27 2011 (r6518) +++ trunk/util/nvramtool/cmos_ops.c Tue Apr 19 21:34:25 2011 (r6519) @@ -125,7 +125,7 @@ /* See if the first character of 'value_str' (excluding * any initial whitespace) is a minus sign. */ - for (p = value_str; isspace(*p); p++) ; + for (p = value_str; isspace((int)(unsigned char)*p); p++) ; negative = (*p == '-'); out = strtoull(value_str, (char **)&p, 0); From patrick at georgi-clan.de Tue Apr 19 21:46:31 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Tue, 19 Apr 2011 21:46:31 +0200 Subject: [coreboot] [PATCH] drop init_uart8250() calls from superio drivers In-Reply-To: <20110414221921.GA9015@coreboot.org> References: <20110414221921.GA9015@coreboot.org> Message-ID: <4DADE697.5060000@georgi-clan.de> Am 15.04.2011 00:19, schrieb Stefan Reinauer: > See patch. Acked-by: Patrick Georgi From svens at stackframe.org Tue Apr 19 21:47:18 2011 From: svens at stackframe.org (Sven Schnelle) Date: Tue, 19 Apr 2011 21:47:18 +0200 Subject: [coreboot] [PATCH 4/4] pci1x2x: use cardbus_read_resources()/cardbus_enable_resources() In-Reply-To: <1303242438-13852-1-git-send-email-svens@stackframe.org> References: <1303242438-13852-1-git-send-email-svens@stackframe.org> Message-ID: <1303242438-13852-5-git-send-email-svens@stackframe.org> Signed-off-by: Sven Schnelle --- src/southbridge/ti/pci1x2x/pci1x2x.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index a3ec35c..bc4ee89 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include "chip.h" @@ -63,9 +64,9 @@ static struct pci_operations ti_pci1x2y_pci_ops = { }; struct device_operations southbridge_ti_pci1x2x_pciops = { - .read_resources = NULL, //pci_dev_read_resources, + .read_resources = cardbus_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = cardbus_enable_resources, .init = ti_pci1x2y_init, .scan_bus = 0, .ops_pci = &ti_pci1x2y_pci_ops, -- 1.7.4.1 From svens at stackframe.org Tue Apr 19 21:47:15 2011 From: svens at stackframe.org (Sven Schnelle) Date: Tue, 19 Apr 2011 21:47:15 +0200 Subject: [coreboot] [PATCH 1/4] pci1x2x: use devicetree register configuration In-Reply-To: <1303242438-13852-1-git-send-email-svens@stackframe.org> References: <1303242438-13852-1-git-send-email-svens@stackframe.org> Message-ID: <1303242438-13852-2-git-send-email-svens@stackframe.org> Signed-off-by: Sven Schnelle --- src/mainboard/nokia/ip530/Kconfig | 25 --------------------- src/mainboard/nokia/ip530/devicetree.cb | 9 +++++++ src/southbridge/ti/pci1x2x/pci1x2x.c | 36 +++++++++++++----------------- 3 files changed, 25 insertions(+), 45 deletions(-) diff --git a/src/mainboard/nokia/ip530/Kconfig b/src/mainboard/nokia/ip530/Kconfig index 0eac00a..b5abb89 100644 --- a/src/mainboard/nokia/ip530/Kconfig +++ b/src/mainboard/nokia/ip530/Kconfig @@ -45,29 +45,4 @@ config IRQ_SLOT_COUNT int default 22 -## Configuration for the PCMCIA-Cardbus controller. -config TI_PCMCIA_CARDBUS_CMDR - hex - default 0x0107 - -config TI_PCMCIA_CARDBUS_CLSR - hex - default 0x00 - -config TI_PCMCIA_CARDBUS_CLTR - hex - default 0x40 - -config TI_PCMCIA_CARDBUS_BCR - hex - default 0x07C0 - -config TI_PCMCIA_CARDBUS_SCR - hex - default 0x08449060 - -config TI_PCMCIA_CARDBUS_MRR - hex - default 0x00007522 - endif # BOARD_NOKIA_IP530 diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb index 3cfbc8f..54ebb1a 100644 --- a/src/mainboard/nokia/ip530/devicetree.cb +++ b/src/mainboard/nokia/ip530/devicetree.cb @@ -28,6 +28,15 @@ chip northbridge/intel/i440bx # Northbridge device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge + device pci f.0 on + chip southbridge/ti/pci1x2x + device pci 00.0 on + + end + register "scr" = "0x08449060" + register "mrr" = "0x00007522" + end + end device pci 7.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) device pnp 3f0.0 off end # Floppy (No connector) diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 63a0646..121b9ef 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -23,28 +23,20 @@ #include #include #include - -#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_MRR)) -#error "you must supply these values in your mainboard-specific Kconfig file" -#endif +#include "chip.h" static void ti_pci1x2y_init(struct device *dev) { + printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n"); + struct southbridge_ti_pci1x2x_config *conf = dev->chip_info; - /* Command (offset 04) */ - pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR); /* Cache Line Size (offset 0x0C) */ - pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR); + pci_write_config8(dev, 0x0C, conf->clsr); /* CardBus latency timer (offset 0x1B) */ - pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR); + pci_write_config8(dev, 0x1B, conf->cltr); /* Bridge control (offset 0x3E) */ - pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR); + pci_write_config16(dev, 0x3E, conf->bcr); /* * Enable change sub-vendor ID. Clear the bit 5 to enable to write * to the sub-vendor/device ids at 40 and 42. @@ -53,14 +45,14 @@ static void ti_pci1x2y_init(struct device *dev) pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA); /* Now write the correct value for SCR. */ /* System control (offset 0x80) */ - pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR); + pci_write_config32(dev, 0x80, conf->scr); /* Multifunction routing */ - pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR); + pci_write_config32(dev, 0x8C, conf->mrr); /* Set the device control register (0x92) accordingly. */ pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); } -static struct device_operations ti_pci1x2y_ops = { +struct device_operations southbridge_ti_pci1x2x_pciops = { .read_resources = NULL, //pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -69,19 +61,23 @@ static struct device_operations ti_pci1x2y_ops = { }; static const struct pci_driver ti_pci1225_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1225, }; static const struct pci_driver ti_pci1420_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1420, }; static const struct pci_driver ti_pci1520_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1520, }; + +struct chip_operations southbridge_ti_pci1x2x_ops = { + CHIP_NAME("TI PCI1x2x Cardbus controller") +}; -- 1.7.4.1 From svens at stackframe.org Tue Apr 19 21:47:16 2011 From: svens at stackframe.org (Sven Schnelle) Date: Tue, 19 Apr 2011 21:47:16 +0200 Subject: [coreboot] [PATCH 2/4] pci1x2x: add PCI1510 device IDs In-Reply-To: <1303242438-13852-1-git-send-email-svens@stackframe.org> References: <1303242438-13852-1-git-send-email-svens@stackframe.org> Message-ID: <1303242438-13852-3-git-send-email-svens@stackframe.org> Signed-off-by: Sven Schnelle --- src/include/device/pci_ids.h | 1 + src/southbridge/ti/pci1x2x/pci1x2x.c | 6 ++++++ 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6286cd6..03896c5 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -737,6 +737,7 @@ #define PCI_DEVICE_ID_TI_4451 0xac42 #define PCI_DEVICE_ID_TI_1420 0xac51 #define PCI_DEVICE_ID_TI_1520 0xac55 +#define PCI_DEVICE_ID_TI_1510 0xac56 #define PCI_VENDOR_ID_SONY 0x104d #define PCI_DEVICE_ID_SONY_CXD3222 0x8039 diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 121b9ef..0628f1f 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -72,6 +72,12 @@ static const struct pci_driver ti_pci1420_driver __pci_driver = { .device = PCI_DEVICE_ID_TI_1420, }; +static const struct pci_driver ti_pci1510_driver __pci_driver = { + .ops = &southbridge_ti_pci1x2x_pciops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1510, +}; + static const struct pci_driver ti_pci1520_driver __pci_driver = { .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, -- 1.7.4.1 From svens at stackframe.org Tue Apr 19 21:47:14 2011 From: svens at stackframe.org (Sven Schnelle) Date: Tue, 19 Apr 2011 21:47:14 +0200 Subject: [coreboot] [PATCH] southbridge/ti/pci1x2x cleanup Message-ID: <1303242438-13852-1-git-send-email-svens@stackframe.org> Hi List, this patch series is a generic cleanup of the pci1x2x driver. Basically it does: - move register config from Kconfig to devicetree.cb - use the generic pci/cardbus functions - add proper subsystemid configuration - remove latency. cacheline size, bridge control register settings, as such register should be configured by the pci/cardbus code. Sven. From svens at stackframe.org Tue Apr 19 21:47:17 2011 From: svens at stackframe.org (Sven Schnelle) Date: Tue, 19 Apr 2011 21:47:17 +0200 Subject: [coreboot] [PATCH 3/4] pci1x2x: use pci_ops set_subsystem instead of custom code In-Reply-To: <1303242438-13852-1-git-send-email-svens@stackframe.org> References: <1303242438-13852-1-git-send-email-svens@stackframe.org> Message-ID: <1303242438-13852-4-git-send-email-svens@stackframe.org> Signed-off-by: Sven Schnelle --- src/southbridge/ti/pci1x2x/pci1x2x.c | 25 ++++++++++++++++++------- 1 files changed, 18 insertions(+), 7 deletions(-) diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 0628f1f..a3ec35c 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "chip.h" static void ti_pci1x2y_init(struct device *dev) @@ -37,13 +38,6 @@ static void ti_pci1x2y_init(struct device *dev) pci_write_config8(dev, 0x1B, conf->cltr); /* Bridge control (offset 0x3E) */ pci_write_config16(dev, 0x3E, conf->bcr); - /* - * Enable change sub-vendor ID. Clear the bit 5 to enable to write - * to the sub-vendor/device ids at 40 and 42. - */ - pci_write_config32(dev, 0x80, 0x10); - pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA); - /* Now write the correct value for SCR. */ /* System control (offset 0x80) */ pci_write_config32(dev, 0x80, conf->scr); /* Multifunction routing */ @@ -52,12 +46,29 @@ static void ti_pci1x2y_init(struct device *dev) pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); } +static void ti_pci1x2y_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + /* + * Enable change sub-vendor ID. Clear the bit 5 to enable to write + * to the sub-vendor/device ids at 40 and 42. + */ + pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10); + pci_write_config16(dev, 0x40, vendor); + pci_write_config16(dev, 0x42, device); + pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10); +} + +static struct pci_operations ti_pci1x2y_pci_ops = { + .set_subsystem = ti_pci1x2y_set_subsystem, +}; + struct device_operations southbridge_ti_pci1x2x_pciops = { .read_resources = NULL, //pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ti_pci1x2y_init, .scan_bus = 0, + .ops_pci = &ti_pci1x2y_pci_ops, }; static const struct pci_driver ti_pci1225_driver __pci_driver = { -- 1.7.4.1 From svn at coreboot.org Tue Apr 19 21:57:27 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 21:57:27 +0200 Subject: [coreboot] [commit] r6520 - trunk/src/ec/lenovo/pmh7 Message-ID: Author: svens Date: Tue Apr 19 21:57:26 2011 New Revision: 6520 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6520 Log: Lenovo PMH7: add pmh7_touchpad_enable() Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/ec/lenovo/pmh7/pmh7.c trunk/src/ec/lenovo/pmh7/pmh7.h Modified: trunk/src/ec/lenovo/pmh7/pmh7.c ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.c Tue Apr 19 21:34:25 2011 (r6519) +++ trunk/src/ec/lenovo/pmh7/pmh7.c Tue Apr 19 21:57:26 2011 (r6520) @@ -41,6 +41,14 @@ pmh7_register_clear_bit(0x60, 3); } + +void pmh7_touchpad_enable(int onoff) +{ + if (onoff) + pmh7_register_clear_bit(0x51, 2); + else + pmh7_register_set_bit(0x51, 2); +} void pmh7_register_set_bit(int reg, int bit) { char val; Modified: trunk/src/ec/lenovo/pmh7/pmh7.h ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.h Tue Apr 19 21:34:25 2011 (r6519) +++ trunk/src/ec/lenovo/pmh7/pmh7.h Tue Apr 19 21:57:26 2011 (r6520) @@ -33,4 +33,5 @@ void pmh7_backlight_enable(int onoff); void pmh7_dock_event_enable(int onoff); +void pmh7_touchpad_enable(int onoff); #endif From r.marek at assembler.cz Tue Apr 19 22:28:13 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 19 Apr 2011 22:28:13 +0200 Subject: [coreboot] coreboot hackaton in Prague Message-ID: <4DADF05D.5010802@assembler.cz> Hi all, I think it is time to remind the coreboot hackaton in Prague which will take place last weekend at the end of May (27,28,29) There is still a http://doodle.com/2n4h3gcugwvs6c9k poll if others wants to join in. The even will take place in Prague, Czech Republic. Most likely at the university building in city centre. The accommodation could be arranged at the dormitory or in any other hotel/hostel. Now a bit to a programme and this is where you all can jump in! I think we could also do a short Prague sightseeing/social events too ;) Thanks, Rudolf From svn at coreboot.org Tue Apr 19 23:33:41 2011 From: svn at coreboot.org (repository service) Date: Tue, 19 Apr 2011 23:33:41 +0200 Subject: [coreboot] [commit] r6521 - in trunk/src: mainboard/digitallogic/adl855pc mainboard/digitallogic/msm586seg mainboard/eaglelion/5bcm mainboard/emulation/qemu-x86 mainboard/iei/juki-511p mainboard/iei/nova4899r... Message-ID: Author: stepan Date: Tue Apr 19 23:33:40 2011 New Revision: 6521 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6521 Log: Drop baud rate init to an arbitrary baud rate from Super I/O code. See discussion at http://www.mail-archive.com/coreboot at coreboot.org/msg29394.html config->com1, devicetree.cb cleanup and init_uart8250() removal will follow once this patch is comitted Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi Updated to drop com1, com2.... from config structure and devicetree.cb Modified: trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb trunk/src/mainboard/eaglelion/5bcm/devicetree.cb trunk/src/mainboard/emulation/qemu-x86/devicetree.cb trunk/src/mainboard/iei/juki-511p/devicetree.cb trunk/src/mainboard/iei/nova4899r/devicetree.cb trunk/src/mainboard/iwill/dk8s2/devicetree.cb trunk/src/mainboard/lanner/em8510/devicetree.cb trunk/src/mainboard/technologic/ts5300/devicetree.cb trunk/src/mainboard/via/epia/devicetree.cb trunk/src/superio/fintek/f71805f/chip.h trunk/src/superio/fintek/f71805f/superio.c trunk/src/superio/fintek/f71859/chip.h trunk/src/superio/fintek/f71859/superio.c trunk/src/superio/fintek/f71863fg/chip.h trunk/src/superio/fintek/f71863fg/superio.c trunk/src/superio/fintek/f71872/chip.h trunk/src/superio/fintek/f71872/superio.c trunk/src/superio/fintek/f71889/chip.h trunk/src/superio/fintek/f71889/superio.c trunk/src/superio/fintek/f81865f/chip.h trunk/src/superio/fintek/f81865f/superio.c trunk/src/superio/intel/i3100/chip.h trunk/src/superio/intel/i3100/superio.c trunk/src/superio/ite/it8661f/chip.h trunk/src/superio/ite/it8661f/superio.c trunk/src/superio/ite/it8671f/chip.h trunk/src/superio/ite/it8671f/superio.c trunk/src/superio/ite/it8673f/chip.h trunk/src/superio/ite/it8673f/superio.c trunk/src/superio/ite/it8705f/chip.h trunk/src/superio/ite/it8705f/superio.c trunk/src/superio/ite/it8712f/chip.h trunk/src/superio/ite/it8712f/superio.c trunk/src/superio/ite/it8716f/chip.h trunk/src/superio/ite/it8716f/superio.c trunk/src/superio/ite/it8718f/chip.h trunk/src/superio/ite/it8718f/superio.c trunk/src/superio/nsc/pc8374/chip.h trunk/src/superio/nsc/pc8374/superio.c trunk/src/superio/nsc/pc87309/chip.h trunk/src/superio/nsc/pc87309/superio.c trunk/src/superio/nsc/pc87351/chip.h trunk/src/superio/nsc/pc87351/superio.c trunk/src/superio/nsc/pc87360/chip.h trunk/src/superio/nsc/pc87360/superio.c trunk/src/superio/nsc/pc87366/chip.h trunk/src/superio/nsc/pc87366/superio.c trunk/src/superio/nsc/pc87382/chip.h trunk/src/superio/nsc/pc87382/superio.c trunk/src/superio/nsc/pc87384/chip.h trunk/src/superio/nsc/pc87384/superio.c trunk/src/superio/nsc/pc87392/chip.h trunk/src/superio/nsc/pc87392/superio.c trunk/src/superio/nsc/pc87417/chip.h trunk/src/superio/nsc/pc87417/superio.c trunk/src/superio/nsc/pc87427/chip.h trunk/src/superio/nsc/pc87427/superio.c trunk/src/superio/nsc/pc97307/chip.h trunk/src/superio/nsc/pc97307/superio.c trunk/src/superio/nsc/pc97317/chip.h trunk/src/superio/nsc/pc97317/superio.c trunk/src/superio/nuvoton/wpcm450/chip.h trunk/src/superio/nuvoton/wpcm450/superio.c trunk/src/superio/smsc/fdc37m60x/chip.h trunk/src/superio/smsc/fdc37m60x/superio.c trunk/src/superio/smsc/fdc37n972/chip.h trunk/src/superio/smsc/kbc1100/chip.h trunk/src/superio/smsc/lpc47b272/chip.h trunk/src/superio/smsc/lpc47b272/superio.c trunk/src/superio/smsc/lpc47b397/chip.h trunk/src/superio/smsc/lpc47b397/superio.c trunk/src/superio/smsc/lpc47m10x/chip.h trunk/src/superio/smsc/lpc47m10x/superio.c trunk/src/superio/smsc/lpc47m15x/chip.h trunk/src/superio/smsc/lpc47m15x/superio.c trunk/src/superio/smsc/lpc47n217/chip.h trunk/src/superio/smsc/lpc47n217/superio.c trunk/src/superio/smsc/lpc47n227/chip.h trunk/src/superio/smsc/lpc47n227/superio.c trunk/src/superio/smsc/sio10n268/chip.h trunk/src/superio/smsc/smscsuperio/chip.h trunk/src/superio/smsc/smscsuperio/superio.c trunk/src/superio/via/vt1211/chip.h trunk/src/superio/winbond/w83627dhg/chip.h trunk/src/superio/winbond/w83627dhg/superio.c trunk/src/superio/winbond/w83627ehg/chip.h trunk/src/superio/winbond/w83627ehg/superio.c trunk/src/superio/winbond/w83627hf/chip.h trunk/src/superio/winbond/w83627hf/superio.c trunk/src/superio/winbond/w83627thg/chip.h trunk/src/superio/winbond/w83627thg/superio.c trunk/src/superio/winbond/w83627uhg/chip.h trunk/src/superio/winbond/w83627uhg/superio.c trunk/src/superio/winbond/w83697hf/chip.h trunk/src/superio/winbond/w83697hf/superio.c trunk/src/superio/winbond/w83977f/chip.h trunk/src/superio/winbond/w83977f/superio.c trunk/src/superio/winbond/w83977tf/chip.h trunk/src/superio/winbond/w83977tf/superio.c Modified: trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb Tue Apr 19 23:33:40 2011 (r6521) @@ -45,9 +45,6 @@ device pnp 2e.b on # HW Monitor io 0x60 = 0x290 end - register "com1" = "{1}" - # register "com1" = "{1, 0, 0x3f8, 4}" - # register "lpt" = "{1}" end end end Modified: trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb Tue Apr 19 23:33:40 2011 (r6521) @@ -3,8 +3,5 @@ device pci 0.0 on end device pci 12.0 on end # enet device pci 14.0 on end # 69000 -# register "com1" = "{1}" -# register "com1" = "{1, 0, 0x3f8, 4}" end - end Modified: trunk/src/mainboard/eaglelion/5bcm/devicetree.cb ============================================================================== --- trunk/src/mainboard/eaglelion/5bcm/devicetree.cb Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/mainboard/eaglelion/5bcm/devicetree.cb Tue Apr 19 23:33:40 2011 (r6521) @@ -36,8 +36,6 @@ device pnp 2e.8 on # Power Management io 0x60 = 0xe800 end - register "com1" = "{115200}" - register "com2" = "{38400}" end device pci 12.1 off end # SMI device pci 12.2 on end # IDE Modified: trunk/src/mainboard/emulation/qemu-x86/devicetree.cb ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/devicetree.cb Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/mainboard/emulation/qemu-x86/devicetree.cb Tue Apr 19 23:33:40 2011 (r6521) @@ -9,7 +9,5 @@ register "ide1_enable" = "1" end -# register "com1" = "{1}" -# register "com1" = "{1, 0, 0x3f8, 4}" end end Modified: trunk/src/mainboard/iei/juki-511p/devicetree.cb ============================================================================== --- trunk/src/mainboard/iei/juki-511p/devicetree.cb Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/mainboard/iei/juki-511p/devicetree.cb Tue Apr 19 23:33:40 2011 (r6521) @@ -16,12 +16,10 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - register "com1" = "{115200}" device pnp 3f0.3 on # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - register "com2" = "{115200}" device pnp 3f0.4 on # RTC io 0x60 = 0x070 irq 0x70 = 8 Modified: trunk/src/mainboard/iei/nova4899r/devicetree.cb ============================================================================== --- trunk/src/mainboard/iei/nova4899r/devicetree.cb Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/mainboard/iei/nova4899r/devicetree.cb Tue Apr 19 23:33:40 2011 (r6521) @@ -19,12 +19,10 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - register "com1" = "{115200}" device pnp 2e.3 on # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - register "com2" = "{115200}" device pnp 2e.4 off # Reserved end device pnp 2e.5 on # Keyboard Modified: trunk/src/mainboard/iwill/dk8s2/devicetree.cb ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/devicetree.cb Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/mainboard/iwill/dk8s2/devicetree.cb Tue Apr 19 23:33:40 2011 (r6521) @@ -56,9 +56,6 @@ device pnp 2e.b on # HW Monitor io 0x60 = 0x290 end - register "com1" = "{1}" - # register "com1" = "{1, 0, 0x3f8, 4}" - # register "lpt" = "{1}" end end device pci 1.1 on end Modified: trunk/src/mainboard/lanner/em8510/devicetree.cb ============================================================================== --- trunk/src/mainboard/lanner/em8510/devicetree.cb Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/mainboard/lanner/em8510/devicetree.cb Tue Apr 19 23:33:40 2011 (r6521) @@ -44,9 +44,6 @@ device pnp 2e.b on # HW Monitor io 0x60 = 0x290 end - register "com1" = "{1}" - # register "com1" = "{1, 0, 0x3f8, 4}" - # register "lpt" = "{1}" end end end Modified: trunk/src/mainboard/technologic/ts5300/devicetree.cb ============================================================================== --- trunk/src/mainboard/technologic/ts5300/devicetree.cb Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/mainboard/technologic/ts5300/devicetree.cb Tue Apr 19 23:33:40 2011 (r6521) @@ -1,9 +1,6 @@ chip cpu/amd/sc520 device pci_domain 0 on device pci 0.0 on end - -# register "com1" = "{1}" -# register "com1" = "{1, 0, 0x3f8, 4}" end end Modified: trunk/src/mainboard/via/epia/devicetree.cb ============================================================================== --- trunk/src/mainboard/via/epia/devicetree.cb Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/mainboard/via/epia/devicetree.cb Tue Apr 19 23:33:40 2011 (r6521) @@ -33,7 +33,6 @@ irq 0x70 = 1 irq 0x72 = 12 end - register "com1" = "{CONFIG_TTYS0_BAUD}" end device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GAME_MIDI_GIPO1 Modified: trunk/src/superio/fintek/f71805f/chip.h ============================================================================== --- trunk/src/superio/fintek/f71805f/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f71805f/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ extern struct chip_operations superio_fintek_f71805f_ops; struct superio_fintek_f71805f_config { - struct uart8250 com1, com2; + }; #endif Modified: trunk/src/superio/fintek/f71805f/superio.c ============================================================================== --- trunk/src/superio/fintek/f71805f/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f71805f/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -40,23 +40,10 @@ static void f71805f_init(device_t dev) { - struct superio_fintek_f71805f_config *conf = dev->chip_info; - struct resource *res0; - if (!dev->enabled) return; - switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ - case F71805F_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case F71805F_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; - } } static void f71805f_pnp_set_resources(device_t dev) Modified: trunk/src/superio/fintek/f71859/chip.h ============================================================================== --- trunk/src/superio/fintek/f71859/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f71859/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ extern struct chip_operations superio_fintek_f71859_ops; struct superio_fintek_f71859_config { - struct uart8250 com1, com2; + }; #endif Modified: trunk/src/superio/fintek/f71859/superio.c ============================================================================== --- trunk/src/superio/fintek/f71859/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f71859/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -41,19 +41,10 @@ static void f71859_init(device_t dev) { - struct superio_fintek_f71859_config *conf = dev->chip_info; - struct resource *res0; - if (!dev->enabled) return; - switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ - case F71859_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - } } static void f71859_pnp_set_resources(device_t dev) Modified: trunk/src/superio/fintek/f71863fg/chip.h ============================================================================== --- trunk/src/superio/fintek/f71863fg/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f71863fg/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ extern struct chip_operations superio_fintek_f71863fg_ops; struct superio_fintek_f71863fg_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/fintek/f71863fg/superio.c ============================================================================== --- trunk/src/superio/fintek/f71863fg/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f71863fg/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -48,14 +48,6 @@ switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ - case F71863FG_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case F71863FG_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case F71863FG_KBC: res0 = find_resource(dev, PNP_IDX_IO0); pc_keyboard_init(&conf->keyboard); Modified: trunk/src/superio/fintek/f71872/chip.h ============================================================================== --- trunk/src/superio/fintek/f71872/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f71872/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ extern struct chip_operations superio_fintek_f71872_ops; struct superio_fintek_f71872_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/fintek/f71872/superio.c ============================================================================== --- trunk/src/superio/fintek/f71872/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f71872/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -40,21 +40,12 @@ static void f71872_init(device_t dev) { struct superio_fintek_f71872_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ - case F71872_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case F71872_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case F71872_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/fintek/f71889/chip.h ============================================================================== --- trunk/src/superio/fintek/f71889/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f71889/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ extern struct chip_operations superio_fintek_f71889_ops; struct superio_fintek_f71889_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/fintek/f71889/superio.c ============================================================================== --- trunk/src/superio/fintek/f71889/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f71889/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -41,21 +41,12 @@ static void f71889_init(device_t dev) { struct superio_fintek_f71889_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ - case F71889_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case F71889_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case F71889_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/fintek/f81865f/chip.h ============================================================================== --- trunk/src/superio/fintek/f81865f/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f81865f/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ extern struct chip_operations superio_fintek_f81865f_ops; struct superio_fintek_f81865f_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/fintek/f81865f/superio.c ============================================================================== --- trunk/src/superio/fintek/f81865f/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/fintek/f81865f/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -40,21 +40,12 @@ static void f81865f_init(device_t dev) { struct superio_fintek_f81865f_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ - case F81865F_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case F81865F_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case F81865F_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/intel/i3100/chip.h ============================================================================== --- trunk/src/superio/intel/i3100/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/intel/i3100/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,6 @@ extern struct chip_operations superio_intel_i3100_ops; struct superio_intel_i3100_config { - struct uart8250 com1, com2; }; #endif Modified: trunk/src/superio/intel/i3100/superio.c ============================================================================== --- trunk/src/superio/intel/i3100/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/intel/i3100/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -40,24 +40,8 @@ static void i3100_init(device_t dev) { - struct superio_intel_i3100_config *conf; - struct resource *res0; - if (!dev->enabled) return; - - conf = dev->chip_info; - - switch (dev->path.pnp.device) { - case I3100_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case I3100_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; - } } static void i3100_pnp_set_resources(device_t dev) Modified: trunk/src/superio/ite/it8661f/chip.h ============================================================================== --- trunk/src/superio/ite/it8661f/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8661f/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ extern struct chip_operations superio_ite_it8661f_ops; struct superio_ite_it8661f_config { - struct uart8250 com1, com2; + }; #endif Modified: trunk/src/superio/ite/it8661f/superio.c ============================================================================== --- trunk/src/superio/ite/it8661f/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8661f/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -29,23 +29,12 @@ static void init(device_t dev) { - struct superio_ite_it8661f_config *conf = dev->chip_info; - struct resource *res0; - if (!dev->enabled) return; switch (dev->path.pnp.device) { case IT8661F_FDC: /* TODO. */ break; - case IT8661F_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case IT8661F_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case IT8661F_PP: /* TODO. */ break; case IT8661F_IR: /* TODO. */ Modified: trunk/src/superio/ite/it8671f/chip.h ============================================================================== --- trunk/src/superio/ite/it8671f/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8671f/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ extern struct chip_operations superio_ite_it8671f_ops; struct superio_ite_it8671f_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/ite/it8671f/superio.c ============================================================================== --- trunk/src/superio/ite/it8671f/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8671f/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,6 @@ static void init(device_t dev) { struct superio_ite_it8671f_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; @@ -37,14 +36,6 @@ switch (dev->path.pnp.device) { case IT8671F_FDC: /* TODO. */ break; - case IT8671F_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case IT8671F_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case IT8671F_PP: /* TODO. */ break; case IT8671F_KBCK: Modified: trunk/src/superio/ite/it8673f/chip.h ============================================================================== --- trunk/src/superio/ite/it8673f/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8673f/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ extern struct chip_operations superio_ite_it8673f_ops; struct superio_ite_it8673f_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/ite/it8673f/superio.c ============================================================================== --- trunk/src/superio/ite/it8673f/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8673f/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,6 @@ static void init(device_t dev) { struct superio_ite_it8673f_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; @@ -37,14 +36,6 @@ switch (dev->path.pnp.device) { case IT8673F_FDC: /* TODO. */ break; - case IT8673F_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case IT8673F_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case IT8673F_PP: /* TODO. */ break; case IT8673F_FAN: /* TODO. */ Modified: trunk/src/superio/ite/it8705f/chip.h ============================================================================== --- trunk/src/superio/ite/it8705f/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8705f/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ extern struct chip_operations superio_ite_it8705f_ops; struct superio_ite_it8705f_config { - struct uart8250 com1, com2; + }; #endif Modified: trunk/src/superio/ite/it8705f/superio.c ============================================================================== --- trunk/src/superio/ite/it8705f/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8705f/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,6 @@ static void init(device_t dev) { struct superio_ite_it8705f_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; @@ -36,14 +35,6 @@ switch (dev->path.pnp.device) { case IT8705F_FDC: /* TODO. */ break; - case IT8705F_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case IT8705F_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case IT8705F_PP: /* TODO. */ break; case IT8705F_EC: /* TODO. */ Modified: trunk/src/superio/ite/it8712f/chip.h ============================================================================== --- trunk/src/superio/ite/it8712f/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8712f/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ extern struct chip_operations superio_ite_it8712f_ops; struct superio_ite_it8712f_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/ite/it8712f/superio.c ============================================================================== --- trunk/src/superio/ite/it8712f/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8712f/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -46,7 +46,6 @@ static void it8712f_init(device_t dev) { struct superio_ite_it8712f_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; @@ -54,14 +53,6 @@ switch (dev->path.pnp.device) { case IT8712F_FDC: /* TODO. */ break; - case IT8712F_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case IT8712F_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case IT8712F_PP: /* TODO. */ break; case IT8712F_EC: /* TODO. */ Modified: trunk/src/superio/ite/it8716f/chip.h ============================================================================== --- trunk/src/superio/ite/it8716f/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8716f/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ extern struct chip_operations superio_ite_it8716f_ops; struct superio_ite_it8716f_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/ite/it8716f/superio.c ============================================================================== --- trunk/src/superio/ite/it8716f/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8716f/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -85,14 +85,6 @@ /* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */ switch (dev->path.pnp.device) { - case IT8716F_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case IT8716F_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case IT8716F_EC: res0 = find_resource(dev, PNP_IDX_IO0); #define EC_INDEX_PORT 5 Modified: trunk/src/superio/ite/it8718f/chip.h ============================================================================== --- trunk/src/superio/ite/it8718f/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8718f/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ extern struct chip_operations superio_ite_it8718f_ops; struct superio_ite_it8718f_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/ite/it8718f/superio.c ============================================================================== --- trunk/src/superio/ite/it8718f/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/ite/it8718f/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,6 @@ static void init(device_t dev) { struct superio_ite_it8718f_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; @@ -37,14 +36,6 @@ switch (dev->path.pnp.device) { case IT8718F_FDC: /* TODO. */ break; - case IT8718F_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case IT8718F_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case IT8718F_PP: /* TODO. */ break; case IT8718F_EC: /* TODO. */ Modified: trunk/src/superio/nsc/pc8374/chip.h ============================================================================== --- trunk/src/superio/nsc/pc8374/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc8374/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ #include struct superio_nsc_pc8374_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/nsc/pc8374/superio.c ============================================================================== --- trunk/src/superio/nsc/pc8374/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc8374/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -34,20 +34,11 @@ static void init(device_t dev) { struct superio_nsc_pc8374_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case PC8374_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC8374_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case PC8374_KBCK: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/nsc/pc87309/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87309/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87309/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ extern struct chip_operations superio_nsc_pc87309_ops; struct superio_nsc_pc87309_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/nsc/pc87309/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87309/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87309/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -30,20 +30,11 @@ static void init(device_t dev) { struct superio_nsc_pc87309_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch (dev->path.pnp.device) { - case PC87309_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC87309_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case PC87309_KBCK: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/nsc/pc87351/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87351/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87351/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ #include struct superio_nsc_pc87351_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/nsc/pc87351/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87351/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87351/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -34,20 +34,11 @@ static void init(device_t dev) { struct superio_nsc_pc87351_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case PC87351_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC87351_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case PC87351_KBCK: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/nsc/pc87360/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87360/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87360/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ #include struct superio_nsc_pc87360_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/nsc/pc87360/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87360/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87360/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -34,20 +34,11 @@ static void init(device_t dev) { struct superio_nsc_pc87360_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case PC87360_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC87360_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case PC87360_KBCK: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/nsc/pc87366/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87366/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87366/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ #include struct superio_nsc_pc87366_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/nsc/pc87366/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87366/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87366/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -34,20 +34,11 @@ static void init(device_t dev) { struct superio_nsc_pc87366_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case PC87366_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC87366_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case PC87366_KBCK: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/nsc/pc87382/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87382/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87382/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -25,7 +25,7 @@ extern struct chip_operations superio_nsc_pc87382_ops; struct superio_nsc_pc87382_config { - struct uart8250 com1, com2; + }; #endif Modified: trunk/src/superio/nsc/pc87382/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87382/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87382/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -33,21 +33,11 @@ static void init(device_t dev) { struct superio_nsc_pc87382_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case PC87382_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC87382_IR: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; - case PC87382_DOCK: break; Modified: trunk/src/superio/nsc/pc87384/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87384/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87384/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -25,7 +25,7 @@ extern struct chip_operations superio_nsc_pc87384_ops; struct superio_nsc_pc87384_config { - struct uart8250 com1, com2; + }; #endif Modified: trunk/src/superio/nsc/pc87384/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87384/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87384/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -33,21 +33,11 @@ static void init(device_t dev) { struct superio_nsc_pc87384_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case PC87384_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC87384_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; - case PC87384_GPIO: break; } Modified: trunk/src/superio/nsc/pc87392/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87392/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87392/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -26,7 +26,7 @@ #include struct superio_nsc_pc87392_config { - struct uart8250 com1, com2; + }; #endif Modified: trunk/src/superio/nsc/pc87392/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87392/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87392/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -31,23 +31,8 @@ static void init(device_t dev) { - struct superio_nsc_pc87392_config *conf = dev->chip_info; - struct resource *res0; - if (!dev->enabled) return; - - switch(dev->path.pnp.device) { - case PC87392_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - - case PC87392_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; - } } static struct device_operations ops = { Modified: trunk/src/superio/nsc/pc87417/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87417/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87417/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ #include struct superio_nsc_pc87417_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/nsc/pc87417/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87417/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87417/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -35,20 +35,11 @@ static void init(device_t dev) { struct superio_nsc_pc87417_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case PC87417_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC87417_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case PC87417_KBCK: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/nsc/pc87427/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87427/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87427/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ #include struct superio_nsc_pc87427_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/nsc/pc87427/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87427/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc87427/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -32,20 +32,11 @@ static void init(device_t dev) { struct superio_nsc_pc87427_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case PC87427_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC87427_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case PC87427_KBCK: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/nsc/pc97307/chip.h ============================================================================== --- trunk/src/superio/nsc/pc97307/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc97307/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -34,7 +34,7 @@ #include struct superio_nsc_pc97307_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; #endif Modified: trunk/src/superio/nsc/pc97307/superio.c ============================================================================== --- trunk/src/superio/nsc/pc97307/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc97307/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -29,21 +29,12 @@ static void init(device_t dev) { struct superio_nsc_pc97307_config *conf = dev->chip_info; - struct resource *res0; u8 reg8; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case PC97307_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC97307_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case PC97307_KBCK: pnp_set_logical_device(dev); pnp_set_enable(dev, 0); /* Disable keyboard */ Modified: trunk/src/superio/nsc/pc97317/chip.h ============================================================================== --- trunk/src/superio/nsc/pc97317/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc97317/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -34,7 +34,7 @@ #include struct superio_nsc_pc97317_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/nsc/pc97317/superio.c ============================================================================== --- trunk/src/superio/nsc/pc97317/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nsc/pc97317/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -29,20 +29,11 @@ static void init(device_t dev) { struct superio_nsc_pc97317_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case PC97317_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case PC97317_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case PC97317_KBCK: pnp_set_logical_device(dev); pnp_set_enable(dev, 0); /* Disable keyboard */ Modified: trunk/src/superio/nuvoton/wpcm450/chip.h ============================================================================== --- trunk/src/superio/nuvoton/wpcm450/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nuvoton/wpcm450/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ #include struct superio_nuvoton_wpcm450_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/nuvoton/wpcm450/superio.c ============================================================================== --- trunk/src/superio/nuvoton/wpcm450/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/nuvoton/wpcm450/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -33,20 +33,11 @@ static void init(device_t dev) { struct superio_nuvoton_wpcm450_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case WPCM450_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case WPCM450_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case WPCM450_KBCK: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/smsc/fdc37m60x/chip.h ============================================================================== --- trunk/src/superio/smsc/fdc37m60x/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/fdc37m60x/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ extern struct chip_operations superio_smsc_fdc37m60x_ops; struct superio_smsc_fdc37m60x_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/smsc/fdc37m60x/superio.c ============================================================================== --- trunk/src/superio/smsc/fdc37m60x/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/fdc37m60x/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,6 @@ static void init(device_t dev) { struct superio_smsc_fdc37m60x_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; @@ -39,14 +38,6 @@ break; case FDC37M60X_PP: /* TODO. */ break; - case FDC37M60X_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case FDC37M60X_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case FDC37M60X_KBCK: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/smsc/fdc37n972/chip.h ============================================================================== --- trunk/src/superio/smsc/fdc37n972/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/fdc37n972/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ extern struct chip_operations superio_smsc_fdc37n972_ops; struct superio_smsc_fdc37n972_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/smsc/kbc1100/chip.h ============================================================================== --- trunk/src/superio/smsc/kbc1100/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/kbc1100/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ extern struct chip_operations superio_smsc_kbc1100_ops; struct superio_smsc_kbc1100_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/smsc/lpc47b272/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47b272/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47b272/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ #include struct superio_smsc_lpc47b272_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/smsc/lpc47b272/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b272/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47b272/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -120,20 +120,11 @@ static void lpc47b272_init(device_t dev) { struct superio_smsc_lpc47b272_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case LPC47B272_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case LPC47B272_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case LPC47B272_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/smsc/lpc47b397/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47b397/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47b397/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -30,7 +30,7 @@ #include struct superio_smsc_lpc47b397_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/smsc/lpc47b397/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b397/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47b397/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -68,20 +68,11 @@ static void lpc47b397_init(device_t dev) { struct superio_smsc_lpc47b397_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case LPC47B397_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case LPC47B397_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case LPC47B397_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/smsc/lpc47m10x/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47m10x/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -32,7 +32,7 @@ #include struct superio_smsc_lpc47m10x_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/smsc/lpc47m10x/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47m10x/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -118,20 +118,11 @@ static void lpc47m10x_init(device_t dev) { struct superio_smsc_lpc47m10x_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case LPC47M10X2_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case LPC47M10X2_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case LPC47M10X2_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/smsc/lpc47m15x/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47m15x/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47m15x/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ #include struct superio_smsc_lpc47m15x_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/smsc/lpc47m15x/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47m15x/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47m15x/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -94,20 +94,11 @@ static void lpc47m15x_init(device_t dev) { struct superio_smsc_lpc47m15x_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case LPC47M15X_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case LPC47M15X_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case LPC47M15X_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/smsc/lpc47n217/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47n217/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47n217/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ #include struct superio_smsc_lpc47n217_config { - struct uart8250 com1, com2; + }; #endif Modified: trunk/src/superio/smsc/lpc47n217/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47n217/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47n217/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -134,21 +134,9 @@ static void lpc47n217_init(device_t dev) { struct superio_smsc_lpc47n217_config* conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; - - switch(dev->path.pnp.device) { - case LPC47N217_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case LPC47N217_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; - } } static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) Modified: trunk/src/superio/smsc/lpc47n227/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47n227/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47n227/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ extern struct chip_operations superio_smsc_lpc47n227_ops; struct superio_smsc_lpc47n227_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/smsc/lpc47n227/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47n227/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/lpc47n227/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -131,20 +131,11 @@ static void lpc47n227_init(device_t dev) { struct superio_smsc_lpc47n227_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch (dev->path.pnp.device) { - case LPC47N227_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case LPC47N227_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case LPC47N227_KBDC: printk(BIOS_DEBUG, "LPC47N227: Initializing keyboard.\n"); pc_keyboard_init(&conf->keyboard); Modified: trunk/src/superio/smsc/sio10n268/chip.h ============================================================================== --- trunk/src/superio/smsc/sio10n268/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/sio10n268/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ extern struct chip_operations superio_smsc_sio10n268_ops; struct superio_smsc_sio10n268_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/smsc/smscsuperio/chip.h ============================================================================== --- trunk/src/superio/smsc/smscsuperio/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/smscsuperio/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ extern struct chip_operations superio_smsc_smscsuperio_ops; struct superio_smsc_smscsuperio_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/smsc/smscsuperio/superio.c ============================================================================== --- trunk/src/superio/smsc/smscsuperio/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/smsc/smscsuperio/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -205,7 +205,6 @@ static void smsc_init(device_t dev) { struct superio_smsc_smscsuperio_config *conf = dev->chip_info; - struct resource *res0; int i, ld; /* Do not initialize disabled devices. */ @@ -223,13 +222,7 @@ /* A Super I/O was found, so initialize the respective device. */ ld = dev->path.pnp.device; - if (ld == logical_device_table[i].devs[LD_SP1]) { - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - } else if (ld == logical_device_table[i].devs[LD_SP2]) { - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - } else if (ld == logical_device_table[i].devs[LD_KBC]) { + if (ld == logical_device_table[i].devs[LD_KBC]) { pc_keyboard_init(&conf->keyboard); } } Modified: trunk/src/superio/via/vt1211/chip.h ============================================================================== --- trunk/src/superio/via/vt1211/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/via/vt1211/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -26,7 +26,7 @@ extern struct chip_operations superio_via_vt1211_ops; struct superio_via_vt1211_config { - struct uart8250 com1, com2; + }; #endif Modified: trunk/src/superio/winbond/w83627dhg/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627dhg/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83627dhg/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ extern struct chip_operations superio_winbond_w83627dhg_ops; struct superio_winbond_w83627dhg_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/winbond/w83627dhg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627dhg/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83627dhg/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -40,20 +40,11 @@ static void w83627dhg_init(device_t dev) { struct superio_winbond_w83627dhg_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case W83627DHG_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case W83627DHG_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case W83627DHG_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/winbond/w83627ehg/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627ehg/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83627ehg/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -28,7 +28,7 @@ extern struct chip_operations superio_winbond_w83627ehg_ops; struct superio_winbond_w83627ehg_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/winbond/w83627ehg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627ehg/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83627ehg/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -114,14 +114,6 @@ return; switch(dev->path.pnp.device) { - case W83627EHG_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case W83627EHG_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case W83627EHG_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/winbond/w83627hf/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627hf/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83627hf/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ extern struct chip_operations superio_winbond_w83627hf_ops; struct superio_winbond_w83627hf_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/winbond/w83627hf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627hf/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83627hf/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -135,14 +135,6 @@ return; switch(dev->path.pnp.device) { - case W83627HF_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case W83627HF_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case W83627HF_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/winbond/w83627thg/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627thg/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83627thg/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ extern struct chip_operations superio_winbond_w83627thg_ops; struct superio_winbond_w83627thg_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/winbond/w83627thg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627thg/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83627thg/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -45,20 +45,11 @@ static void w83627thg_init(device_t dev) { struct superio_winbond_w83627thg_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case W83627THG_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case W83627THG_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case W83627THG_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/winbond/w83627uhg/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627uhg/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83627uhg/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ extern struct chip_operations superio_winbond_w83627uhg_ops; struct superio_winbond_w83627uhg_config { - struct uart8250 com1, com2, com3, com4, com5, com6; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/winbond/w83627uhg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627uhg/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83627uhg/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -73,41 +73,28 @@ static void w83627uhg_init(device_t dev) { struct superio_winbond_w83627uhg_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { case W83627UHG_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); /* set_uart_clock_source(dev, 0); */ - init_uart8250(res0->base, &conf->com1); break; case W83627UHG_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); /* set_uart_clock_source(dev, 0); */ - init_uart8250(res0->base, &conf->com2); break; case W83627UHG_SP3: - res0 = find_resource(dev, PNP_IDX_IO0); /* set_uart_clock_source(dev, 0); */ - init_uart8250(res0->base, &conf->com3); break; case W83627UHG_SP4: - res0 = find_resource(dev, PNP_IDX_IO0); /* set_uart_clock_source(dev, 0); */ - init_uart8250(res0->base, &conf->com4); break; case W83627UHG_SP5: - res0 = find_resource(dev, PNP_IDX_IO0); /* set_uart_clock_source(dev, 0); */ - init_uart8250(res0->base, &conf->com5); break; case W83627UHG_SP6: - res0 = find_resource(dev, PNP_IDX_IO0); /* set_uart_clock_source(dev, 0); */ - init_uart8250(res0->base, &conf->com6); break; case W83627UHG_KBC: pc_keyboard_init(&conf->keyboard); Modified: trunk/src/superio/winbond/w83697hf/chip.h ============================================================================== --- trunk/src/superio/winbond/w83697hf/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83697hf/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -26,7 +26,7 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - struct uart8250 com1, com2; + }; #endif Modified: trunk/src/superio/winbond/w83697hf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83697hf/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83697hf/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -43,22 +43,8 @@ static void w83697hf_init(device_t dev) { - struct superio_winbond_w83697hf_config *conf = dev->chip_info; - struct resource *res0; - if (!dev->enabled) return; - - switch(dev->path.pnp.device) { - case W83697HF_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case W83697HF_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; - } } static void w83697hf_pnp_set_resources(device_t dev) Modified: trunk/src/superio/winbond/w83977f/chip.h ============================================================================== --- trunk/src/superio/winbond/w83977f/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83977f/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -27,7 +27,7 @@ extern struct chip_operations superio_winbond_w83977f_ops; struct superio_winbond_w83977f_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/winbond/w83977f/superio.c ============================================================================== --- trunk/src/superio/winbond/w83977f/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83977f/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -44,20 +44,11 @@ static void w83977f_init(device_t dev) { struct superio_winbond_w83977f_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case W83977F_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case W83977F_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case W83977F_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/winbond/w83977tf/chip.h ============================================================================== --- trunk/src/superio/winbond/w83977tf/chip.h Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83977tf/chip.h Tue Apr 19 23:33:40 2011 (r6521) @@ -29,7 +29,7 @@ extern struct chip_operations superio_winbond_w83977tf_ops; struct superio_winbond_w83977tf_config { - struct uart8250 com1, com2; + struct pc_keyboard keyboard; }; Modified: trunk/src/superio/winbond/w83977tf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83977tf/superio.c Tue Apr 19 21:57:26 2011 (r6520) +++ trunk/src/superio/winbond/w83977tf/superio.c Tue Apr 19 23:33:40 2011 (r6521) @@ -46,20 +46,11 @@ static void w83977tf_init(device_t dev) { struct superio_winbond_w83977tf_config *conf = dev->chip_info; - struct resource *res0; if (!dev->enabled) return; switch(dev->path.pnp.device) { - case W83977TF_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case W83977TF_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case W83977TF_KBC: pc_keyboard_init(&conf->keyboard); break; From wmk587 at yahoo.com Tue Apr 19 23:31:22 2011 From: wmk587 at yahoo.com (Boris Shpoungin) Date: Tue, 19 Apr 2011 14:31:22 -0700 (PDT) Subject: [coreboot] Failed to launch windows 7 and two more questions ... Message-ID: <529603.59987.qm@web33008.mail.mud.yahoo.com> We are considering to use coreboot for our developing board. I downloaded latest version of coreboot + seabios and compiled it for emulation. I tried to launch windows 7 in qemu with coreboot bios and got the following error: "Windows failed to load because the firmware (BIOS) is not ACPI compatible" Status: 0xc0000225 Can anyone clarify why I get this error and what i did wrong? Two more questions: Could you recommend any manual which describe coreboot porting process to new not supported platform? Does it exist at all? Could you provide rough effort estimate to port coreboot to new unsupported platform? Thank you. From svn at coreboot.org Wed Apr 20 00:12:27 2011 From: svn at coreboot.org (repository service) Date: Wed, 20 Apr 2011 00:12:27 +0200 Subject: [coreboot] build service results for r6521 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6521 to the coreboot repository. This caused the following changes: Change Log: Drop baud rate init to an arbitrary baud rate from Super I/O code. See discussion at http://www.mail-archive.com/coreboot at coreboot.org/msg29394.html config->com1, devicetree.cb cleanup and init_uart8250() removal will follow once this patch is comitted Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi Updated to drop com1, com2.... from config structure and devicetree.cb Build Log: Compilation of lenovo:x60 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6521&device=x60&vendor=lenovo&num=2 Compilation of via:epia-cn has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6521&device=epia-cn&vendor=via&num=2 Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6521&device=epia-m&vendor=via&num=2 Compilation of via:vt8454c has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6521&device=vt8454c&vendor=via&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From peter at stuge.se Wed Apr 20 00:23:28 2011 From: peter at stuge.se (Peter Stuge) Date: Wed, 20 Apr 2011 00:23:28 +0200 Subject: [coreboot] Failed to launch windows 7 and two more questions ... In-Reply-To: <529603.59987.qm@web33008.mail.mud.yahoo.com> References: <529603.59987.qm@web33008.mail.mud.yahoo.com> Message-ID: <20110419222328.6561.qmail@stuge.se> Hi Boris, Boris Shpoungin wrote: > We are considering to use coreboot for our developing board. Sounds good! > I downloaded latest version of coreboot + seabios and compiled it > for emulation. I tried to launch windows 7 in qemu with coreboot > bios (Note coreboot is not a BIOS. SeaBIOS is the BIOS part.) > and got the following error: > > "Windows failed to load because the firmware (BIOS) is not ACPI > compatible" > Status: 0xc0000225 > > Can anyone clarify why I get this error and what i did wrong? You did nothing wrong. The qemu port of coreboot simply does not implement ACPI. > Could you recommend any manual which describe coreboot porting > process to new not supported platform? Does it exist at all? There's nothing really current, because the infrastructure in the coreboot sources has changed a fair amount since the last more comprehensive documentation was written. The best approach is to look at existing support in coreboot for hardware similar to yours, and together with firmware development documentation for the components the way ahead should already be somewhat clear. > Could you provide rough effort estimate to port coreboot to new > unsupported platform? Please define unsupported platform? If the significant components are already supported by coreboot then an experienced coreboot developer with prior knowledge of the components could accomplish a port in less than a week. If no components are supported then an experienced coreboot developer will spend a minimum of 8 months. An experienced firmware developer who knows C but is new to coreboot would most likely quickly find their way around coreboot. A developer with no prior experience from PC firmware development nor from general C development will spend a lot of time learning new things. //Peter From jwangzju at gmail.com Tue Apr 19 23:56:14 2011 From: jwangzju at gmail.com (Jiang Wang) Date: Tue, 19 Apr 2011 17:56:14 -0400 Subject: [coreboot] Intel 82541pi network card does not work on ASUS M2V-MX SE Message-ID: Hi, I tried to use an external PCI network card ( 8254pi) with m2v-mx se mother board. However, the booting process hangs. On the screen, it shows, "Chrome VGA textmode initialized", and stops there. The serial console output is attached. Is this the NIC option rom problem or coreboot problem? Any workarounds? I need to use a network card supported by e1000.ko on Linux. If I try to get a different model of NIC supported by e1000, does it help? Thanks! Regards, Jiang -------------- next part -------------- A non-text attachment was scrubbed... Name: nic-problem.log Type: application/octet-stream Size: 62366 bytes Desc: not available URL: From svn at coreboot.org Wed Apr 20 03:03:59 2011 From: svn at coreboot.org (repository service) Date: Wed, 20 Apr 2011 03:03:59 +0200 Subject: [coreboot] [commit] r6522 - in trunk/src/superio: nsc/pc87382 via/vt1211 Message-ID: Author: stepan Date: Wed Apr 20 03:03:58 2011 New Revision: 6522 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6522 Log: fix boards that still had some uart init remainders Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/superio/nsc/pc87382/superio.c trunk/src/superio/via/vt1211/vt1211.c Modified: trunk/src/superio/nsc/pc87382/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87382/superio.c Tue Apr 19 23:33:40 2011 (r6521) +++ trunk/src/superio/nsc/pc87382/superio.c Wed Apr 20 03:03:58 2011 (r6522) @@ -32,8 +32,6 @@ static void init(device_t dev) { - struct superio_nsc_pc87382_config *conf = dev->chip_info; - if (!dev->enabled) return; Modified: trunk/src/superio/via/vt1211/vt1211.c ============================================================================== --- trunk/src/superio/via/vt1211/vt1211.c Tue Apr 19 23:33:40 2011 (r6521) +++ trunk/src/superio/via/vt1211/vt1211.c Wed Apr 20 03:03:58 2011 (r6522) @@ -93,21 +93,12 @@ static void vt1211_init(struct device *dev) { - struct superio_via_vt1211_config *conf = dev->chip_info; struct resource *res0; if (!dev->enabled) return; switch (dev->path.pnp.device) { - case VT1211_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case VT1211_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case VT1211_HWM: res0 = find_resource(dev, PNP_IDX_IO0); init_hwm(res0->base); From svn at coreboot.org Wed Apr 20 03:08:27 2011 From: svn at coreboot.org (repository service) Date: Wed, 20 Apr 2011 03:08:27 +0200 Subject: [coreboot] [commit] r6523 - in trunk/src: include lib southbridge/via/vt82c686 Message-ID: Author: stepan Date: Wed Apr 20 03:08:25 2011 New Revision: 6523 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6523 Log: drop dead uart init code. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/include/uart8250.h trunk/src/lib/uart8250.c trunk/src/southbridge/via/vt82c686/chip.h Modified: trunk/src/include/uart8250.h ============================================================================== --- trunk/src/include/uart8250.h Wed Apr 20 03:03:58 2011 (r6522) +++ trunk/src/include/uart8250.h Wed Apr 20 03:08:25 2011 (r6523) @@ -131,11 +131,6 @@ #ifndef __ROMCC__ -// Can't we just drop this? It seems silly. -struct uart8250 { - unsigned int baud; -}; - unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); void uart8250_tx_byte(unsigned base_port, unsigned char data); @@ -144,7 +139,6 @@ * have three different sets of uart code, so it's an improvement. */ void uart8250_init(unsigned base_port, unsigned divisor); -void init_uart8250(unsigned base_port, struct uart8250 *uart); void uart_init(void); #endif Modified: trunk/src/lib/uart8250.c ============================================================================== --- trunk/src/lib/uart8250.c Wed Apr 20 03:03:58 2011 (r6522) +++ trunk/src/lib/uart8250.c Wed Apr 20 03:08:25 2011 (r6523) @@ -86,23 +86,6 @@ outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); } -#ifndef __ROMCC__ -/* Initialize a generic uart */ -void init_uart8250(unsigned base_port, struct uart8250 *uart) -{ - int divisor = uart->baud ? (115200/uart->baud) : 1; - - if (base_port == CONFIG_TTYS0_BASE) { - /* Don't reinitialize the console serial port, - * This is espeically nasty in SMP. - * NOTE: The first invocation thus always needs to be - */ - return; - } - uart8250_init(base_port, divisor); -} -#endif - #if