[coreboot] Patch merged into master: 0f196d4 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.

gerrit at coreboot.org gerrit at coreboot.org
Thu Aug 4 08:10:13 CEST 2011

the following patch was just integrated into master:
commit 0f196d4cf39e680389a2098e10739d8545397203
Author: Keith Hui <buurin at gmail.com>
Date:   Wed Jul 27 23:06:16 2011 -0400

    cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
    Bring from coreboot v1 support for initializing L2 cache on Slot 1
    Pentium II/III CPUs, code names Klamath, Deschutes and Katmai.
    Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with
    Pentium III 600MHz, Katmai core.
    Also add missing include of model_68x in slot_1, to address a
    similar problem fixed for model_6bx by r5945.
    Also change Deschutes CPU init sequence to match Katmai.
    Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257
    Signed-off-by: Keith Hui <buurin at gmail.com>

See http://review.coreboot.org/122 for details.


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