[coreboot] Patch set updated: ea7a21e AMD F14 southbridge update

perh52 at runbox.com perh52 at runbox.com
Sun Aug 7 21:40:26 CEST 2011

The proposed get_sb800_revision is incomplete. We know that at least SB810, SB820M
and SB850 exist, and that production ASIC revisions are A12, A13 (and perhaps later).
Since Frank is at AMD I guess he can obtain the full set easily.

The SB8xx device in the Asrock E350M1 has rev_id = 0x42 and so is _not_ covered by
the proposed patch. I guess it is an SB850 A12 or A13, but I have not removed the heatsink
to check.

+/* RPR 2.28 Get SB ASIC Revision.*/
+static u8 get_sb800_revision(void)
+	rev_id =  pci_read_config8(dev, 0x08);
+	if (rev_id == 0x40) {
+		rev = REV_SB800_A11;
+	} else if (rev_id == 0x41) {
+		rev = REV_SB800_A12;
+	} else {
+		die("It is not SB800 or SB810\r\n");
+	}
+	return rev;

Slightly OT, but still on the subject of device identification: The following code in
vendorcode/amd/cimx/sb800/SBPOR.c incorrectly turns off NbSbGen2 for the Asrock E350M1.
I don't know why it was put in or if it is correct for some other hardware.

     dbEfuse = MINOR_ID_EFUSE_LOC;
     getEfuseStatus (&dbEfuse);
     if ( dbEfuse == M1_MINOR_ID ) {
      // Limit ALink speed to 2.5G if Hudson-M1
      cimNbSbGen2 = 0;

So it would be nice to have a complete routine for identifying the SB8xx versions accurately.

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