[coreboot] Patch set updated: ea7a21e AMD F14 southbridge update

perh52 at runbox.com perh52 at runbox.com
Sun Aug 7 23:28:53 CEST 2011

Looking at src/southbridge/amd/cimx/sb800/late.c

 static void usb_init(struct device *dev)
+	printk(BIOS_DEBUG, "SB800 - Late.c - usb_init - Start.\n");
+	printk(BIOS_DEBUG, "SB800 - Late.c - usb_init - End.\n");

it is not correct to call usbInitAfterPciInit like this because usb_init is called for every
usb device, and usbInitAfterPciInit (re)initializes all the usb devices each time. This
problem predates the patch of course but while changing late.c let us get it right.

On a different part of the patch relating to
there is

+	sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
+	sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
+	sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
+	sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED;

Not sure why you want to set these, but all enabled is not always correct, and they
get reset in PreInitGppLink according to PortMask[lane_config]. Perhaps move
the PortMask logic into cfg.h/cfg.c ?

The sb900 cfg.c is much more complete than sb800. Leaving many values
undefined in sb_config seems like a bad idea. I found I needed to set SataPortPower.

+       sb_config->SataPortPower = 0; // 0=all enabled. Disable ports by setting bits 5:0.
+       sb_config->SataPortMode  = 0; // 0=all Gen3 (6Gb/s) -- 12 bits which select Gen1/2

and these need to be set correctly depending on the SB8xx version.

+       sb_config->NbSbGen2 = NBSB_GEN2;
+       sb_config->GppGen2 = GPP_GEN2;

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