From marcj303 at gmail.com  Thu Dec  1 04:48:15 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 30 Nov 2011 20:48:15 -0700
Subject: [coreboot] Persimmon LAN problem with coreboot
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E208C2C81649@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E208C2C81649@DATAKAMPONE.datakamp2008.local>
Message-ID: <CALrs_3gBrnM8yyesuBXF-jCggatdp5XPk84KtrfHLvmGdm8X_w@mail.gmail.com>

Hi Wolfgang,



On Wed, Nov 30, 2011 at 1:46 AM, Wolfgang Kamp - datakamp
<wmkamp at datakamp.de> wrote:
>
>
> Hi Marc,
>
>
>
> it looks that the PCI enumeration of the LAN chip works fine, but then the
> register access fails.
>
> So lspci -vvnn lists the Realtec LAN [10ec/8168] correct, but network test
> fails to access the register.
>
> It's not possible to read out the MAC address. 0xFF on all places will be
> returned.
>
> I have attached the coreboot log file.
>
> On line 375 PCI: 01:00.0 [10ec/8168] enabled shows the bus.
>
> On line 994 down I can see assertion fails on AmdInitLate process.
>
> What does this mean? Can you help?
>
>
>
> Thanks

I don't see anything that might be causing the MAC to be blanked, but
this has been reported in other places this week. I am working on a
patch for the cpulateinit assert, but I don't know if it will fix the
issue you are seeing. I think that there are some problems with the C0
release and we need to work through them. Please post what you find in
your debug.

Thanks,
Marc




-- 
http://se-eng.com


From gerrit at coreboot.org  Thu Dec  1 11:55:45 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 1 Dec 2011 11:55:45 +0100
Subject: [coreboot] Patch merged into coreboot/master: aadf4c5 X60/T60:
	reset baudrate loglevel to sane values
References: <Iaf5861e9db0a41a184da6d2e515e3b9afe0655d6+0@gerrit.coreboot.org>
Message-ID: <E1RW4Ir-0002aJ-4Z@ra.coresystems.de>

the following patch was just integrated into master:
commit aadf4c5effd7f31579d6105d82a7006d08eeab3e
Author: Sven Schnelle <svens at stackframe.org>
Date:   Mon Nov 28 21:12:11 2011 +0100

    X60/T60: reset baudrate loglevel to sane values
    
    Change-Id: Iaf5861e9db0a41a184da6d2e515e3b9afe0655d6
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Build-Tested: build bot (Jenkins) at Mon Nov 28 21:37:31 2011, giving +1
Reviewed-By: Sven Schnelle <svens at stackframe.org> at Thu Dec  1 11:55:43 2011, giving +2
See http://review.coreboot.org/459 for details.

-gerrit


From gerrit at coreboot.org  Thu Dec  1 16:01:31 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Thu, 1 Dec 2011 16:01:31 +0100
Subject: [coreboot] New patch to review for coreboot: 685f150 Change AMD
	vendorcode build
References: <I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0+0@gerrit.coreboot.org>
Message-ID: <I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0+1@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/468

-gerrit

commit 685f150a7e7e668965f6ca78025d71bff86b512d
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Thu Dec 1 16:24:20 2011 +0200

    Change AMD vendorcode build
    
    Apply the normal method of recursively including subdirectories
    for src/vendorcode. Remove redundant references under
    mainboard and northbridge.
    
    Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 Makefile.inc                                 |    3 ++-
 src/mainboard/amd/inagua/Makefile.inc        |    1 -
 src/mainboard/amd/persimmon/Makefile.inc     |    1 -
 src/mainboard/amd/south_station/Makefile.inc |    1 -
 src/mainboard/amd/torpedo/Makefile.inc       |    1 -
 src/mainboard/amd/union_station/Makefile.inc |    1 -
 src/mainboard/asrock/e350m1/Makefile.inc     |    1 -
 src/mainboard/supermicro/h8qgi/Makefile.inc  |    2 --
 src/northbridge/amd/Makefile.inc             |    3 ---
 src/vendorcode/Makefile.inc                  |    6 +-----
 src/vendorcode/amd/Makefile.inc              |    2 ++
 src/vendorcode/amd/agesa/Makefile.inc        |    3 +++
 src/vendorcode/amd/cimx/Makefile.inc         |    2 ++
 13 files changed, 10 insertions(+), 17 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 4c87bd2..e12cc92 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -38,7 +38,8 @@ PHONY+= clean-abuild coreboot
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/boot src/console src/devices src/ec src/southbridge src/northbridge src/superio src/drivers src/cpu
+subdirs-y := src/lib src/boot src/console src/devices src/ec src/southbridge
+subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode
 subdirs-y += util/cbfstool util/sconfig
 subdirs-y += src/arch/$(ARCHDIR-y)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
index 531a736..d9fc200 100755
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -31,4 +31,3 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += $(src)/vendorcode/amd/agesa/f14
\ No newline at end of file
diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc
index afad9ac..8a72727 100644
--- a/src/mainboard/amd/persimmon/Makefile.inc
+++ b/src/mainboard/amd/persimmon/Makefile.inc
@@ -38,4 +38,3 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc
index 1cb32b3..d9fc200 100644
--- a/src/mainboard/amd/south_station/Makefile.inc
+++ b/src/mainboard/amd/south_station/Makefile.inc
@@ -31,4 +31,3 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc
index 986d90d..ee44ade 100755
--- a/src/mainboard/amd/torpedo/Makefile.inc
+++ b/src/mainboard/amd/torpedo/Makefile.inc
@@ -47,4 +47,3 @@ ramstage-y += PlatformGnbPcie.c
 ramstage-y += reset.c
 ramstage-y += pmio.c
 
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += $(src)/vendorcode/amd/agesa/f12
diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc
index 1cb32b3..d9fc200 100644
--- a/src/mainboard/amd/union_station/Makefile.inc
+++ b/src/mainboard/amd/union_station/Makefile.inc
@@ -31,4 +31,3 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc
index 22d8373..d9fc200 100644
--- a/src/mainboard/asrock/e350m1/Makefile.inc
+++ b/src/mainboard/asrock/e350m1/Makefile.inc
@@ -31,4 +31,3 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 
-subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc
index 211387d..b09c5ca 100755
--- a/src/mainboard/supermicro/h8qgi/Makefile.inc
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@@ -29,5 +29,3 @@ ramstage-y += dimmSpd.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += platform_oem.c
 
-AGESA_ROOT ?= $(src)/vendorcode/amd/agesa/f10/
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += ../../../../$(AGESA_ROOT)
diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc
index 5299780..bf96b80 100644
--- a/src/northbridge/amd/Makefile.inc
+++ b/src/northbridge/amd/Makefile.inc
@@ -5,6 +5,3 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
 
 subdirs-$(CONFIG_AMD_AGESA) += agesa
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += ../../vendorcode/amd/agesa/f10
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += ../../vendorcode/amd/agesa/f12
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../vendorcode/amd/agesa/f14
diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc
index bd55573..16c0d68 100644
--- a/src/vendorcode/Makefile.inc
+++ b/src/vendorcode/Makefile.inc
@@ -1,6 +1,2 @@
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += $(src)/vendorcode/amd/agesa/f10
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += $(src)/vendorcode/amd/agesa/f12
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += $(src)/vendorcode/amd/agesa/f14
+subdirs-y += amd
 
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += $(src)/vendorcode/amd/cimx/sb800
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += $(src)/vendorcode/amd/cimx/sb900
diff --git a/src/vendorcode/amd/Makefile.inc b/src/vendorcode/amd/Makefile.inc
new file mode 100644
index 0000000..2897ff2
--- /dev/null
+++ b/src/vendorcode/amd/Makefile.inc
@@ -0,0 +1,2 @@
+subdirs-y += agesa
+subdirs-y += cimx
diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc
new file mode 100644
index 0000000..5516888
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Makefile.inc
@@ -0,0 +1,3 @@
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += f10
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
diff --git a/src/vendorcode/amd/cimx/Makefile.inc b/src/vendorcode/amd/cimx/Makefile.inc
new file mode 100644
index 0000000..bb9b78c
--- /dev/null
+++ b/src/vendorcode/amd/cimx/Makefile.inc
@@ -0,0 +1,2 @@
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900


From gerrit at coreboot.org  Thu Dec  1 16:50:45 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Thu, 1 Dec 2011 16:50:45 +0100
Subject: [coreboot] Patch set updated for coreboot: 6a8d16b Change AMD
	vendorcode build
References: <I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0+0@gerrit.coreboot.org>
Message-ID: <I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0+2@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/468

-gerrit

commit 6a8d16bdd456c70329cf46d03daf2a99bbff1e81
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Thu Dec 1 17:49:43 2011 +0200

    Change AMD vendorcode build
    
    Apply the normal method of recursively including subdirectories
    for src/vendorcode. Remove redundant references under
    mainboard and northbridge.
    
    Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 Makefile.inc                                 |    3 ++-
 src/mainboard/amd/inagua/Makefile.inc        |    1 -
 src/mainboard/amd/persimmon/Makefile.inc     |    1 -
 src/mainboard/amd/south_station/Makefile.inc |    1 -
 src/mainboard/amd/torpedo/Makefile.inc       |    1 -
 src/mainboard/amd/union_station/Makefile.inc |    1 -
 src/mainboard/asrock/e350m1/Makefile.inc     |    1 -
 src/mainboard/supermicro/h8qgi/Makefile.inc  |    2 --
 src/northbridge/amd/Makefile.inc             |    3 ---
 src/vendorcode/Makefile.inc                  |    6 +-----
 src/vendorcode/amd/Makefile.inc              |    2 ++
 src/vendorcode/amd/agesa/Makefile.inc        |    3 +++
 src/vendorcode/amd/agesa/f10/Makefile.inc    |    2 +-
 src/vendorcode/amd/cimx/Makefile.inc         |    2 ++
 14 files changed, 11 insertions(+), 18 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 4c87bd2..e12cc92 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -38,7 +38,8 @@ PHONY+= clean-abuild coreboot
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/boot src/console src/devices src/ec src/southbridge src/northbridge src/superio src/drivers src/cpu
+subdirs-y := src/lib src/boot src/console src/devices src/ec src/southbridge
+subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode
 subdirs-y += util/cbfstool util/sconfig
 subdirs-y += src/arch/$(ARCHDIR-y)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
index 531a736..d9fc200 100755
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -31,4 +31,3 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += $(src)/vendorcode/amd/agesa/f14
\ No newline at end of file
diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc
index afad9ac..8a72727 100644
--- a/src/mainboard/amd/persimmon/Makefile.inc
+++ b/src/mainboard/amd/persimmon/Makefile.inc
@@ -38,4 +38,3 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc
index 1cb32b3..d9fc200 100644
--- a/src/mainboard/amd/south_station/Makefile.inc
+++ b/src/mainboard/amd/south_station/Makefile.inc
@@ -31,4 +31,3 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc
index 986d90d..ee44ade 100755
--- a/src/mainboard/amd/torpedo/Makefile.inc
+++ b/src/mainboard/amd/torpedo/Makefile.inc
@@ -47,4 +47,3 @@ ramstage-y += PlatformGnbPcie.c
 ramstage-y += reset.c
 ramstage-y += pmio.c
 
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += $(src)/vendorcode/amd/agesa/f12
diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc
index 1cb32b3..d9fc200 100644
--- a/src/mainboard/amd/union_station/Makefile.inc
+++ b/src/mainboard/amd/union_station/Makefile.inc
@@ -31,4 +31,3 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc
index 22d8373..d9fc200 100644
--- a/src/mainboard/asrock/e350m1/Makefile.inc
+++ b/src/mainboard/asrock/e350m1/Makefile.inc
@@ -31,4 +31,3 @@ ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
 
-subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc
index 211387d..b09c5ca 100755
--- a/src/mainboard/supermicro/h8qgi/Makefile.inc
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@@ -29,5 +29,3 @@ ramstage-y += dimmSpd.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += platform_oem.c
 
-AGESA_ROOT ?= $(src)/vendorcode/amd/agesa/f10/
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += ../../../../$(AGESA_ROOT)
diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc
index 5299780..bf96b80 100644
--- a/src/northbridge/amd/Makefile.inc
+++ b/src/northbridge/amd/Makefile.inc
@@ -5,6 +5,3 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
 
 subdirs-$(CONFIG_AMD_AGESA) += agesa
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += ../../vendorcode/amd/agesa/f10
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += ../../vendorcode/amd/agesa/f12
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../vendorcode/amd/agesa/f14
diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc
index bd55573..16c0d68 100644
--- a/src/vendorcode/Makefile.inc
+++ b/src/vendorcode/Makefile.inc
@@ -1,6 +1,2 @@
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += $(src)/vendorcode/amd/agesa/f10
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += $(src)/vendorcode/amd/agesa/f12
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += $(src)/vendorcode/amd/agesa/f14
+subdirs-y += amd
 
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += $(src)/vendorcode/amd/cimx/sb800
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += $(src)/vendorcode/amd/cimx/sb900
diff --git a/src/vendorcode/amd/Makefile.inc b/src/vendorcode/amd/Makefile.inc
new file mode 100644
index 0000000..2897ff2
--- /dev/null
+++ b/src/vendorcode/amd/Makefile.inc
@@ -0,0 +1,2 @@
+subdirs-y += agesa
+subdirs-y += cimx
diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc
new file mode 100644
index 0000000..5516888
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Makefile.inc
@@ -0,0 +1,3 @@
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += f10
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc
index b212515..298eb95 100755
--- a/src/vendorcode/amd/agesa/f10/Makefile.inc
+++ b/src/vendorcode/amd/agesa/f10/Makefile.inc
@@ -18,7 +18,7 @@
 #
 
 ## ABSOLUTE AGESA V5 ROOT PATH ##
-AGESA_ROOT ?= $(PWD)
+AGESA_ROOT = src/vendorcode/amd/agesa/f10
 
 AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR)
 AGESA_INC += -I$(AGESA_ROOT)
diff --git a/src/vendorcode/amd/cimx/Makefile.inc b/src/vendorcode/amd/cimx/Makefile.inc
new file mode 100644
index 0000000..bb9b78c
--- /dev/null
+++ b/src/vendorcode/amd/cimx/Makefile.inc
@@ -0,0 +1,2 @@
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900


From towardsoss at gmail.com  Thu Dec  1 19:59:46 2011
From: towardsoss at gmail.com (Niklas Cholmkvist)
Date: Thu, 01 Dec 2011 20:59:46 +0200
Subject: [coreboot] Add password protection
Message-ID: <4ED7CEA2.4020607@gmail.com>

Hi Fred,

> Add password protection so you need password for boot the system.
> Add it to SeaBIOS too.
I don't know if it is already implemented. Will you help us implement it?
-- 
Niklas Cholmkvist

Public GPG/PGP key block
ID:           1024D/C09E670B
Fingerprint:  8487 ECE3 8ED9 870B BB56  95E7 9AD2 946A C09E 670B
Key download:
https://sites.google.com/site/towardsfloss/main-page/NiklasCholmkvist.asc
[For authenticity and privacy on the internet with prime number based
mathematics]

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From eldmannen at gmail.com  Thu Dec  1 22:59:56 2011
From: eldmannen at gmail.com (Fred .)
Date: Thu, 1 Dec 2011 22:59:56 +0100
Subject: [coreboot] Add password protection
In-Reply-To: <4ED7CEA2.4020607@gmail.com>
References: <4ED7CEA2.4020607@gmail.com>
Message-ID: <CAJgfmqXdCmO8Bm-t7Qu-tUoURrU5TOZ2VVpmEfi0xYo4j+e_nw@mail.gmail.com>

I do not know if it is implemented either. But I think it is not.

I am not much of a programmer.

But I guess coreboot and seabios use libpayload (not sure).

libpayload doesn't support many functions such as gets() so you will
have to use getc(), also then the password will be visible on the
screen, not cloaked.
- Show quoted text -

On Thu, Dec 1, 2011 at 7:59 PM, Niklas Cholmkvist <towardsoss at gmail.com> wrote:
> Hi Fred,
>
>> Add password protection so you need password for boot the system.
>> Add it to SeaBIOS too.
> I don't know if it is already implemented. Will you help us implement it?
> --
> Niklas Cholmkvist
>
> Public GPG/PGP key block
> ID: ? ? ? ? ? 1024D/C09E670B
> Fingerprint: ?8487 ECE3 8ED9 870B BB56 ?95E7 9AD2 946A C09E 670B
> Key download:
> https://sites.google.com/site/towardsfloss/main-page/NiklasCholmkvist.asc
> [For authenticity and privacy on the internet with prime number based
> mathematics]
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


From gerrit at coreboot.org  Fri Dec  2 08:59:27 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 08:59:27 +0100
Subject: [coreboot] Patch merged into coreboot/master: 6a8d16b Change AMD
	vendorcode build
References: <I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0+0@gerrit.coreboot.org>
Message-ID: <E1RWO1n-0004gU-QW@ra.coresystems.de>

the following patch was just integrated into master:
commit 6a8d16bdd456c70329cf46d03daf2a99bbff1e81
Author: Ky??sti M??lkki <kyosti.malkki at gmail.com>
Date:   Thu Dec 1 17:49:43 2011 +0200

    Change AMD vendorcode build
    
    Apply the normal method of recursively including subdirectories
    for src/vendorcode. Remove redundant references under
    mainboard and northbridge.
    
    Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
    Signed-off-by: Ky??sti M??lkki <kyosti.malkki at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Dec  2 08:59:26 2011, giving +2
See http://review.coreboot.org/468 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec  2 16:38:03 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Fri, 2 Dec 2011 16:38:03 +0100
Subject: [coreboot] New patch to review for coreboot: ed0ebd2 i3100: Add
	HAVE_HARD_RESET
References: <Id3669aaf99b96b4a7a965f4957e5de7c365acaa6+0@gerrit.coreboot.org>
Message-ID: <Id3669aaf99b96b4a7a965f4957e5de7c365acaa6+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/469

-gerrit

commit ed0ebd28ba3fcda086dad49b21cf34e97caba310
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:33:30 2011 +0100

    i3100: Add HAVE_HARD_RESET
    
    and remove it from mainboard/intel/mtarvon, as this function
    is implemented in the southbridge code.
    
    Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/intel/mtarvon/Kconfig |    1 -
 src/southbridge/intel/i3100/Kconfig |    1 +
 2 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig
index 76477b0..af40cad 100644
--- a/src/mainboard/intel/mtarvon/Kconfig
+++ b/src/mainboard/intel/mtarvon/Kconfig
@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_I3100
 	select SOUTHBRIDGE_INTEL_I3100
 	select SUPERIO_INTEL_I3100
-	select HAVE_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select UDELAY_TSC
diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig
index bcb282d..f2b7923 100644
--- a/src/southbridge/intel/i3100/Kconfig
+++ b/src/southbridge/intel/i3100/Kconfig
@@ -1,3 +1,4 @@
 config SOUTHBRIDGE_INTEL_I3100
 	bool
 	select IOAPIC
+	select HAVE_HARD_RESET


From gerrit at coreboot.org  Fri Dec  2 17:06:07 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Fri, 2 Dec 2011 17:06:07 +0100
Subject: [coreboot] New patch to review for coreboot: 41d6529 Remove
	obsolete TINY_BOOTBLOCK
References: <I0edc69dc5f95cc32ee648eb094c9e5387f80db47+0@gerrit.coreboot.org>
Message-ID: <I0edc69dc5f95cc32ee648eb094c9e5387f80db47+1@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/470

-gerrit

commit 41d65299b1359caddcf8944adc009cf33989febc
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Fri Dec 2 18:05:46 2011 +0200

    Remove obsolete TINY_BOOTBLOCK
    
    Change-Id: I0edc69dc5f95cc32ee648eb094c9e5387f80db47
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/mainboard/amd/south_station/Kconfig |    1 -
 src/mainboard/amd/union_station/Kconfig |    1 -
 src/mainboard/asus/m5a88-v/Kconfig      |    1 -
 3 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig
index 3828054..fb41cec 100644
--- a/src/mainboard/amd/south_station/Kconfig
+++ b/src/mainboard/amd/south_station/Kconfig
@@ -40,7 +40,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select AMDMCT
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_4096
-	select TINY_BOOTBLOCK
 	select GFXUMA
 	select UDELAY_LAPIC
 
diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig
index db0d1e4..194a39d 100644
--- a/src/mainboard/amd/union_station/Kconfig
+++ b/src/mainboard/amd/union_station/Kconfig
@@ -40,7 +40,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select AMDMCT
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_2048
-	select TINY_BOOTBLOCK
 	select GFXUMA
 	select UDELAY_LAPIC
 
diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig
index fdf2ba6..9cadcde 100644
--- a/src/mainboard/asus/m5a88-v/Kconfig
+++ b/src/mainboard/asus/m5a88-v/Kconfig
@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select RAMINIT_SYSINFO
 	select ENABLE_APIC_EXT_ID
-	select TINY_BOOTBLOCK
 	select GFXUMA
 	select HAVE_DEBUG_CAR
 	select SET_FIDVID


From gerrit at coreboot.org  Fri Dec  2 17:26:19 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 17:26:19 +0100
Subject: [coreboot] Patch merged into coreboot/master: 41d6529 Remove
	obsolete TINY_BOOTBLOCK
References: <I0edc69dc5f95cc32ee648eb094c9e5387f80db47+0@gerrit.coreboot.org>
Message-ID: <E1RWVwJ-0003p2-O9@ra.coresystems.de>

the following patch was just integrated into master:
commit 41d65299b1359caddcf8944adc009cf33989febc
Author: Ky??sti M??lkki <kyosti.malkki at gmail.com>
Date:   Fri Dec 2 18:05:46 2011 +0200

    Remove obsolete TINY_BOOTBLOCK
    
    Change-Id: I0edc69dc5f95cc32ee648eb094c9e5387f80db47
    Signed-off-by: Ky??sti M??lkki <kyosti.malkki at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Dec  2 17:26:18 2011, giving +2
See http://review.coreboot.org/470 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec  2 17:27:52 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 17:27:52 +0100
Subject: [coreboot] Patch merged into coreboot/master: 47e054a Add ASUS
	M4A785T-M mainboard support
References: <I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732+0@gerrit.coreboot.org>
Message-ID: <E1RWVxo-00049Z-NI@ra.coresystems.de>

the following patch was just integrated into master:
commit 47e054a1c4090e4a5a404de427634b260e4c4d13
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date:   Sun Nov 27 15:58:38 2011 +0100

    Add ASUS M4A785T-M mainboard support
    
    This mainboard is very similar to the M4A785-M, but it has
      DDR3 instead of DDR2.
    
    That's why most of the code was copied or included from
      the m4a785-m directory
    
    Notable changes between the two mainboards include:
     * the selection of the last microcode (mc_patch_010000b6.h)
       which made it pass the CPU init.
     * the selection of DDR3 which made it pass the ram init
    
    This change was tested with the Trisquel 5.0 GNU/Linux distribution
      which uses the linux-libre version 2.6.38-12-generic
    
    The mainboard boots fine, however some special care is required for
      the onboard sound CODEC, and the onboard video chip:
      * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue
        is the same than the ASUS M4A785-M mainboard:
        It causes a flood of interupts which prevents booting
      * The internal video chip currently requires pci=nocrs, else
        the graphics are frozen as soon as the radeon module loads,
        and dmesg would print the following(the card only has 256M,
        and the mainboard was equiped with 2G of RAM):
          [    3.674762] [drm] radeon: 3584M of VRAM memory ready
          [    3.679863] [drm] radeon: 512M of GTT memory ready.
        instead of :
          [   45.876088] [drm] radeon: 256M of VRAM memory ready
          [   45.876089] [drm] radeon: 512M of GTT memory ready.
      * The screen(both VGA and HDMI) flickers at high resolution
      * Sometimes the computer freeze while changing the resolution
        (even the serial console stops responding)
    
    The following peripherals were tested:
     * The ath9k PCI wireless card was tested
     * The SATA hard disk works fine
     * the USB keyboard and mouse work fine
     * htop see 2 cores
     * serial port works under coreboot and GNU/Linux
     * power off and reboot works
    
    CPU frequency cannot be changed yet, this is addressed
      in a new commit.
    
    More detail are available here:
      http://www.coreboot.org/ASUS_M4A785T-M
    
    dmesg is available here:
      http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html
    
    The mailing list thread on the graphic problem is here:
      http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html
    
    Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Dec  2 17:27:51 2011, giving +2
See http://review.coreboot.org/457 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec  2 17:28:02 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 17:28:02 +0100
Subject: [coreboot] Patch merged into coreboot/master: 4211f0c M4A785T-M:
	fix ACPI's P-States Table
References: <Ie00e4b11b2561356952d8ae28bd0a00523b6d85f+0@gerrit.coreboot.org>
Message-ID: <E1RWVxy-0004D3-Ka@ra.coresystems.de>

the following patch was just integrated into master:
commit 4211f0c5542743e251dbd022b023d0d34d8877c2
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date:   Sun Nov 27 22:04:02 2011 +0100

    M4A785T-M: fix ACPI's P-States Table
    
    Without that fix the linux kernel cannot change the frequency
      of the CPUs with cpufreq.
    
    Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Dec  2 17:27:13 2011, giving +2
See http://review.coreboot.org/458 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec  2 17:30:14 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 17:30:14 +0100
Subject: [coreboot] Patch merged into coreboot/master: 8bb1751 Mirror Fix
	coreinfo usage of cb_info
References: <I32f261e4be927555979eb833d0251fce2c6a5c47+0@gerrit.coreboot.org>
Message-ID: <E1RWW06-0001cR-1f@ra.coresystems.de>

the following patch was just integrated into master:
commit 8bb17510476ea1abaf941d443771fc95a2e849e3
Author: QingPei Wang <wangqingpei at gmail.com>
Date:   Tue Nov 22 15:24:12 2011 +0800

    Mirror Fix coreinfo usage of cb_info
    
    fix cb_info.serial.ioport to cb_info.serial.baseaddr
    
    Change-Id: I32f261e4be927555979eb833d0251fce2c6a5c47
    Signed-off-by: QingPei Wang <wangqingpei at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Dec  2 17:29:13 2011, giving +2
See http://review.coreboot.org/441 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec  2 18:10:53 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 18:10:53 +0100
Subject: [coreboot] Patch merged into coreboot/master: ed0ebd2 i3100: Add
	HAVE_HARD_RESET
References: <Id3669aaf99b96b4a7a965f4957e5de7c365acaa6+0@gerrit.coreboot.org>
Message-ID: <E1RWWdR-0003qJ-Ov@ra.coresystems.de>

the following patch was just integrated into master:
commit ed0ebd28ba3fcda086dad49b21cf34e97caba310
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:33:30 2011 +0100

    i3100: Add HAVE_HARD_RESET
    
    and remove it from mainboard/intel/mtarvon, as this function
    is implemented in the southbridge code.
    
    Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Dec  2 18:10:51 2011, giving +2
See http://review.coreboot.org/469 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec  2 23:06:21 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 23:06:21 +0100
Subject: [coreboot] Patch merged into coreboot/master: 2797390 implement
	usb2 termination and dpll delay setting for vt8237r
References: <I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769+0@gerrit.coreboot.org>
Message-ID: <E1RWbFN-0000nM-Ik@ra.coresystems.de>

the following patch was just integrated into master:
commit 2797390a25514005e59daa6a79b7acaf123f5946
Author: Florian Zumbiehl <florz at florz.de>
Date:   Tue Nov 1 20:19:35 2011 +0100

    implement usb2 termination and dpll delay setting for vt8237r
    
    Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769
    Signed-off-by: Florian Zumbiehl <florz at florz.de>

Build-Tested: build bot (Jenkins) at Wed Nov 23 19:56:27 2011, giving +1
Reviewed-By: Rudolf Marek <r.marek at assembler.cz> at Fri Dec  2 23:06:19 2011, giving +2
See http://review.coreboot.org/385 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec  2 23:12:31 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 23:12:31 +0100
Subject: [coreboot] Patch merged into coreboot/master: 3fc0235 some black
	magic for initializing the old version of the k8t800
References: <I1b5d23cee9f933aa090c9bd09890c7b335567e17+0@gerrit.coreboot.org>
Message-ID: <E1RWbLK-0007RB-4k@ra.coresystems.de>

the following patch was just integrated into master:
commit 3fc0235c1a85eb1bf977be201f5d174ce91a3196
Author: Florian Zumbiehl <florz at florz.de>
Date:   Tue Nov 1 20:19:38 2011 +0100

    some black magic for initializing the old version of the k8t800
    
    Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17
    Signed-off-by: Florian Zumbiehl <florz at florz.de>

Build-Tested: build bot (Jenkins) at Wed Nov 23 20:40:59 2011, giving +1
Reviewed-By: Rudolf Marek <r.marek at assembler.cz> at Fri Dec  2 23:11:55 2011, giving +2
See http://review.coreboot.org/388 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec  2 23:20:32 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 23:20:32 +0100
Subject: [coreboot] Patch merged into coreboot/master: 423d321 copied asus
	a8v-e_se to k8v-x
References: <Ib66e8c5102ad45e73977a06aea109ed9544f4d08+0@gerrit.coreboot.org>
Message-ID: <E1RWbT6-0001Av-UH@ra.coresystems.de>

the following patch was just integrated into master:
commit 423d3214899d68fb7e0c040b068c72517077fa4e
Author: Florian Zumbiehl <florz at florz.de>
Date:   Tue Nov 1 20:19:40 2011 +0100

    copied asus a8v-e_se to k8v-x
    
    Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08
    Signed-off-by: Florian Zumbiehl <florz at florz.de>

Build-Tested: build bot (Jenkins) at Wed Nov 23 20:31:22 2011, giving +1
Reviewed-By: Rudolf Marek <r.marek at assembler.cz> at Fri Dec  2 23:20:20 2011, giving +2
See http://review.coreboot.org/389 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec  2 23:24:42 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 23:24:42 +0100
Subject: [coreboot] Patch merged into coreboot/master: 80f52b7 make
	INT[EFGH]# of vt8237 configurable as gpio via devicetree
References: <I70202d81ddd1b0a00eddca4acabc621e5783e805+0@gerrit.coreboot.org>
Message-ID: <E1RWbX8-00037B-TV@ra.coresystems.de>

the following patch was just integrated into master:
commit 80f52b7bcd10a5c28ffa9a7ad3e64529df6f7085
Author: Florian Zumbiehl <florz at florz.de>
Date:   Mon Nov 21 03:10:47 2011 +0100

    make INT[EFGH]# of vt8237 configurable as gpio via devicetree
    
    Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805
    Signed-off-by: Florian Zumbiehl <florz at florz.de>

Build-Tested: build bot (Jenkins) at Wed Nov 23 19:45:59 2011, giving +1
Reviewed-By: Rudolf Marek <r.marek at assembler.cz> at Fri Dec  2 23:04:38 2011, giving +2
See http://review.coreboot.org/386 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec  2 23:26:00 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Dec 2011 23:26:00 +0100
Subject: [coreboot] Patch merged into coreboot/master: fd6fdfa make GPIOs
	and misc configurable via devicetree
References: <I9f70da76b5ea451f28a1ad9252c5d879fc4fe315+0@gerrit.coreboot.org>
Message-ID: <E1RWbYO-0005y6-PJ@ra.coresystems.de>

the following patch was just integrated into master:
commit fd6fdfa88c27551aa1169dac6616e0c7381edbb0
Author: Florian Zumbiehl <florz at florz.de>
Date:   Tue Nov 1 20:19:37 2011 +0100

    make GPIOs and misc configurable via devicetree
    
    Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315
    Signed-off-by: Florian Zumbiehl <florz at florz.de>

Build-Tested: build bot (Jenkins) at Wed Nov 23 19:34:51 2011, giving +1
Reviewed-By: Rudolf Marek <r.marek at assembler.cz> at Fri Dec  2 22:59:52 2011, giving +2
See http://review.coreboot.org/387 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec  3 00:54:00 2011
From: gerrit at coreboot.org (Florian Zumbiehl)
Date: Sat, 3 Dec 2011 00:54:00 +0100
Subject: [coreboot] Patch set updated for coreboot: 2796df7 adding support
	for the Asus K8V-X
References: <Ifb97714c2f009d688be0ca3c38ddc01599ffd799+0@gerrit.coreboot.org>
Message-ID: <Ifb97714c2f009d688be0ca3c38ddc01599ffd799+14@gerrit.coreboot.org>

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390

-gerrit

commit 2796df7bfeec1e1ca09fa23540198cd5056bc71a
Author: Florian Zumbiehl <florz at florz.de>
Date:   Tue Nov 1 20:19:41 2011 +0100

    adding support for the Asus K8V-X
    
    This pulls it all together and adds the real board-specific code.
    
    Confirmed to be working:
    - IDE
    - SATA
    - floppy
    - USB1.1
    - USB2.0
    - PS/2 keyboard
    - PS/2 mouse
    - serial
    - parport
    - sound
    - ethernet
    - PCI slots
    - AGP
    - powernow
    - fan speed monitoring
    - flashrom write
    
    Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
    Signed-off-by: Florian Zumbiehl <florz at florz.de>
---
 src/mainboard/asus/Kconfig             |    3 +
 src/mainboard/asus/k8v-x/Kconfig       |   20 ++++---
 src/mainboard/asus/k8v-x/acpi_tables.c |    2 +-
 src/mainboard/asus/k8v-x/devicetree.cb |   51 ++++++++++---------
 src/mainboard/asus/k8v-x/dsdt.asl      |   87 ++++---------------------------
 src/mainboard/asus/k8v-x/mainboard.c   |   38 +++++++++++++-
 src/mainboard/asus/k8v-x/mptable.c     |    2 +-
 src/mainboard/asus/k8v-x/romstage.c    |   69 +++++++++----------------
 8 files changed, 115 insertions(+), 157 deletions(-)

diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig
index 630e1ec..f7a3017 100644
--- a/src/mainboard/asus/Kconfig
+++ b/src/mainboard/asus/Kconfig
@@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE
 	bool "A8V-E SE"
 config BOARD_ASUS_A8V_E_DELUXE
 	bool "A8V-E Deluxe"
+config BOARD_ASUS_K8V_X
+	bool "K8V-X"
 config BOARD_ASUS_M2N_E
 	bool "M2N-E"
 config BOARD_ASUS_M2V
@@ -63,6 +65,7 @@ endchoice
 source "src/mainboard/asus/a8n_e/Kconfig"
 source "src/mainboard/asus/a8v-e_se/Kconfig"
 source "src/mainboard/asus/a8v-e_deluxe/Kconfig"
+source "src/mainboard/asus/k8v-x/Kconfig"
 source "src/mainboard/asus/m2n-e/Kconfig"
 source "src/mainboard/asus/m2v/Kconfig"
 source "src/mainboard/asus/m2v-mx_se/Kconfig"
diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig
index 4975cfa..d297143 100644
--- a/src/mainboard/asus/k8v-x/Kconfig
+++ b/src/mainboard/asus/k8v-x/Kconfig
@@ -1,26 +1,24 @@
-if BOARD_ASUS_A8V_E_SE
+if BOARD_ASUS_K8V_X
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_SOCKET_939
-	select K8_HT_FREQ_1G_SUPPORT
+	select CPU_AMD_SOCKET_754
 	select NORTHBRIDGE_AMD_AMDK8
 	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
 	select SOUTHBRIDGE_VIA_VT8237R
-	select SOUTHBRIDGE_VIA_K8T890
-	select SUPERIO_WINBOND_W83627EHG
+	select SOUTHBRIDGE_VIA_K8T800_OLD
+	select SUPERIO_WINBOND_W83697HF
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_TABLES
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
-	select QRANK_DIMM_SUPPORT
 	select SET_FIDVID
 
 config MAINBOARD_DIR
 	string
-	default asus/a8v-e_se
+	default asus/k8v-x
 
 config DCACHE_RAM_BASE
 	hex
@@ -44,7 +42,11 @@ config SB_HT_CHAIN_ON_BUS0
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "A8V-E SE"
+	default "K8V-X"
+
+config AGP_APERTURE_SIZE
+	hex
+	default 0x10000000
 
 config HW_MEM_HOLE_SIZEK
 	hex
@@ -70,4 +72,4 @@ config HT_CHAIN_UNITID_BASE
 	hex
 	default 0x0
 
-endif # BOARD_ASUS_A8V_E_SE
+endif # BOARD_ASUS_K8V_X
diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c
index 218f3bb..571d136 100644
--- a/src/mainboard/asus/k8v-x/acpi_tables.c
+++ b/src/mainboard/asus/k8v-x/acpi_tables.c
@@ -30,7 +30,7 @@
 #include <device/device.h>
 #include <device/pci_ids.h>
 #include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
+#include "southbridge/via/k8t890/k8x8xx.h"
 #include "northbridge/amd/amdk8/acpi.h"
 #include <cpu/amd/model_fxx_powernow.h>
 
diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb
index 3da93fe..61c5a2d 100644
--- a/src/mainboard/asus/k8v-x/devicetree.cb
+++ b/src/mainboard/asus/k8v-x/devicetree.cb
@@ -1,6 +1,6 @@
 chip northbridge/amd/amdk8/root_complex		# Root complex
   device lapic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_939			# CPU
+    chip cpu/amd/socket_754			# CPU
       device lapic 0 on end			# APIC
     end
   end
@@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
           register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
           register "fn_ctrl_lo" = "0"		# Enable SB functions
           register "fn_ctrl_hi" = "0xad"	# Enable SB functions
+          register "usb2_termination_set" = "1"
+          register "usb2_termination_a" = "8"
+          register "usb2_termination_b" = "8"
+          register "usb2_termination_c" = "6"
+          register "usb2_termination_d" = "6"
+          register "usb2_termination_e" = "6"
+          register "usb2_termination_f" = "6"
+          register "usb2_termination_g" = "6"
+          register "usb2_termination_h" = "6"
+          register "usb2_dpll_set" = "1"
+          register "usb2_dpll_delay" = "3"
+          register "int_efgh_as_gpio" = "1"
+          register "enable_gpo3" = "1"
+          register "disable_gpo26_gpo27" = "1"
+          register "enable_aol_2_smb_slave" = "1"
+          register "enable_gpo5" = "1"
+          register "gpio15_12_dir_output" = "1"
           device pci 0.0 on end			# HT
           device pci f.1 on end			# IDE
+          device pci 10.4 on end		# USB2
           device pci 11.0 on			# LPC
             chip drivers/generic/generic	# DIMM 0-0-0
               device i2c 50 on end
@@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
             chip drivers/generic/generic	# DIMM 0-1-0
               device i2c 52 on end
             end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            chip superio/winbond/w83627ehg	# Super I/O
+            chip superio/winbond/w83697hf	# Super I/O
+              register "hwmon_fan1_divisor" = "128"
+              register "hwmon_fan2_divisor" = "4"
               device pnp 2e.0 on		# Floppy
                 io 0x60 = 0x3f0
                 irq 0x70 = 6
@@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
                 irq 0x70 = 4
               end
               device pnp 2e.3 off		# Com2 (N/A on this board)
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 2e.5 off		# PS/2 keyboard & mouse (off)
-              end
-              device pnp 2e.106 off		# Serial flash interface (SFI)
-                io 0x60 = 0x100
               end
-              device pnp 2e.007 off		# GPIO 1
+              device pnp 2e.6 off		# CIR
               end
-              device pnp 2e.107 on		# Game port
-                io 0x60 = 0x201
+              device pnp 2e.7 off		# Game port/GPIO 1
               end
-              device pnp 2e.207 on		# MIDI
-                io 0x62 = 0x330
-                irq 0x70 = 0xa
+              device pnp 2e.8 off		# MIDI/GPIO 5
               end
-              device pnp 2e.307 off		# GPIO 6
-              end
-              device pnp 2e.8 off		# WDTO#, PLED
-              end
-              device pnp 2e.009 on		# GPIO 2
+              device pnp 2e.009 off		# GPIO 2
               end
               device pnp 2e.109 off		# GPIO 3
               end
               device pnp 2e.209 off		# GPIO 4
               end
-              device pnp 2e.309 on		# GPIO 5
-              end
               device pnp 2e.a off		# ACPI
               end
               device pnp 2e.b on		# Hardware monitor
diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl
index 16ad92c..25b7460 100644
--- a/src/mainboard/asus/k8v-x/dsdt.asl
+++ b/src/mainboard/asus/k8v-x/dsdt.asl
@@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
 
 			/* PCI Routing Table */
 			Name (_PRT, Package () {
+				Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */
+				Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
 				Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
 				Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
 				Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
@@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
 				Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
 				Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
 				Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
+				Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */
+				Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 },
+				Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 },
+				Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 },
+				Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */
+				Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 },
+				Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 },
+				Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 },
+				Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */
 				Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
 				Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
 				Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
 				Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
 				Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
-				Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
-				Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
-				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
-				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
-				Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
-				Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
-				Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
-				Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
-				Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
-				Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B }  /* IRQ43 */
+				Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }  /* AC97, MC97 */
 			})
 
-			Device (PEGG)
-			{
-				Name (_ADR, 0x00020000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x02)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
-				})
-			}
-
-			Device (PEX0)
-			{
-				Name (_ADR, 0x00030000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x03)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
-				})
-			}
-
-			Device (PEX1)
-			{
-				Name (_ADR, 0x00030001)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x04)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
-				})
-			}
-
-			Device (PEX2)
-			{
-				Name (_ADR, 0x00030002)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x05)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
-				})
-			}
-
-			Device (PEX3)
-			{
-				Name (_ADR, 0x00030003)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x06)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
-				})
-			}
-
 			Device (ISA) {
 				Name (_ADR, 0x00110000)
 
diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c
index b70f396..3e294b8 100644
--- a/src/mainboard/asus/k8v-x/mainboard.c
+++ b/src/mainboard/asus/k8v-x/mainboard.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot at tdiedrich.de>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,8 +22,43 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <arch/io.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
 #include "chip.h"
 
+u32 vt8237_ide_80pin_detect(struct device *dev)
+{
+	device_t lpc_dev;
+	u16 acpi_io_base;
+	u32 gpio_in;
+	u32 res;
+
+	lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
+	if (!lpc_dev)
+		return 0;
+
+	acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
+	if (!acpi_io_base)
+		return 0;
+
+	/* select function GPIO29 for pin AB9 */
+	pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08);
+
+	gpio_in = inl(acpi_io_base + 0x48);
+	/* bit 29 for primary port, clear if unconnected or 80-pin cable */
+	res  = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE;
+	/* bit 8 for secondary port, clear if unconnected or 80-pin cable */
+	res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE;
+
+	printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
+		res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
+	printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
+		res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
+
+	return res;
+}
+
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("ASUS A8V-E SE Mainboard")
+	CHIP_NAME("ASUS K8V-X Mainboard")
 };
diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c
index 999dd6c..673dfbe 100644
--- a/src/mainboard/asus/k8v-x/mptable.c
+++ b/src/mainboard/asus/k8v-x/mptable.c
@@ -22,7 +22,7 @@
 #include <arch/smp/mpspec.h>
 #include <arch/ioapic.h>
 #include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
+#include "southbridge/via/k8t890/k8x8xx.h"
 
 static void *smp_write_config_table(void *v)
 {
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 4e08859..014ce68 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
-#include "superio/winbond/w83627ehg/early_serial.c"
+#include "superio/winbond/w83697hf/early_serial.c"
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <spd.h>
 
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
-#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
+#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -105,52 +103,25 @@ static void sio_init(void)
 	u8 reg;
 
 	pnp_enter_ext_func_mode(SERIAL_DEV);
-	/* We have 24MHz input. */
 	reg = pnp_read_config(SERIAL_DEV, 0x24);
-	pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
-	/* We have GPIO for KB/MS pin. */
-	reg = pnp_read_config(SERIAL_DEV, 0x2a);
-	pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
-	/* We have all RESTOUT and even some reserved bits, too. */
-	reg = pnp_read_config(SERIAL_DEV, 0x2c);
-	pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
-	pnp_exit_ext_func_mode(SERIAL_DEV);
-
-	pnp_enter_ext_func_mode(ACPI_DEV);
-	pnp_set_logical_device(ACPI_DEV);
-	/*
-	 * Set the delay rising time from PWROK_LP to PWROK_ST to
-	 * 300 - 600ms, and 0 to vice versa.
-	 */
-	reg = pnp_read_config(ACPI_DEV, 0xe6);
-	pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
-	/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
-	reg = pnp_read_config(ACPI_DEV, 0xe4);
-	pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
-	pnp_exit_ext_func_mode(ACPI_DEV);
-
-	pnp_enter_ext_func_mode(GPIO_DEV);
-	pnp_set_logical_device(GPIO_DEV);
-	/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
-	pnp_write_config(GPIO_DEV, 0x30, 0x09);	/* Enable GPIO 2 & GPIO 5. */
-	pnp_write_config(GPIO_DEV, 0xe2, 0x00);	/* No inversion */
-	pnp_write_config(GPIO_DEV, 0xe5, 0x00);	/* No inversion */
-	pnp_write_config(GPIO_DEV, 0xe3, 0x03);	/* 0000 0011, 0=output 1=input */
-	pnp_write_config(GPIO_DEV, 0xe0, 0xde);	/* 1101 1110, 0=output 1=input */
-	pnp_write_config(GPIO_DEV, 0xe1, 0x01);	/* Set output val. */
-	pnp_write_config(GPIO_DEV, 0xe4, 0xb4);	/* Set output val (1011 0100). */
-	pnp_exit_ext_func_mode(GPIO_DEV);
+	/* 4 Mbit flash */
+	reg = (reg & ~0x30) | 0x20;
+	/* We have 24MHz input. */
+	reg &= ~0x40;
+	/* enable MEMW#, so flash can be written */
+	reg |= 0x08;
+	pnp_write_config(SERIAL_DEV, 0x24, reg);
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		DIMM0, DIMM2, 0, 0,
-		DIMM1, DIMM3, 0, 0,
+		DIMM0, DIMM1, DIMM2, 0,
+		0, 0, 0, 0,
 		// Node 1
-		DIMM4, DIMM6, 0, 0,
-		DIMM5, DIMM7, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
@@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	enable_rom_decode();
 
@@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	// FIXME why is this executed again? --->
 	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	enable_rom_decode();
 	// <--- FIXME why is this executed again?
@@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		soft_reset();
 	}
 
-	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
+	/* the HT settings needs to be OK, because link freq change may cause HT disconnect */
+	vt8237_sb_enable_fid_vid();
 	enable_fid_change();
 	init_fidvid_bsp(bsp_apicid);
 
@@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
 	enable_smbus();
+
+	/* this seems to be some GPIO on the SMBus--in any case, setting these
+	 * two bits reduces the pullup impedance of the bus lines and is required
+	 * in order to be able to read SPD info */
+	smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80);
+	smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10);
+
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
 }


From gerrit at coreboot.org  Sat Dec  3 10:34:14 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Sat, 3 Dec 2011 10:34:14 +0100
Subject: [coreboot] New patch to review for coreboot: cb4b944 Fix AMD 8132
	and 8151 southbridge builds
References: <I03acdfcc3f3440bd32e81a9a696159903bbbcb50+0@gerrit.coreboot.org>
Message-ID: <I03acdfcc3f3440bd32e81a9a696159903bbbcb50+1@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/471

-gerrit

commit cb4b9445f0cfa3089357b4ae7393352e962ddc31
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Sat Dec 3 11:30:26 2011 +0200

    Fix AMD 8132 and 8151 southbridge builds
    
    Untested, changes ramstage build for boards:
      supermicro/h8qme_fam10
      amd/serengeti_cheetah
      amd/serengeti_cheetah_fam10
    
    AMD 8132 was not built for any mainboard due to a typo.
    
    AMD Serengeti Cheetah:
      Chip 8151 is referenced in devicetree.cb but was not built.
    
    AMD Serengeti Cheetah Family10:
      There are indications the board has 8151, but it is not listed
      in the devicetree.cb. The 8151 chip is not added in the build.
    
    Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/mainboard/amd/serengeti_cheetah/Kconfig |    2 ++
 src/southbridge/amd/Makefile.inc            |    2 +-
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig
index f08fd6e..fcdeb49 100644
--- a/src/mainboard/amd/serengeti_cheetah/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah/Kconfig
@@ -3,6 +3,8 @@ if BOARD_AMD_SERENGETI_CHEETAH
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
+ 	select SOUTHBRIDGE_AMD_AMD8132
+ 	select SOUTHBRIDGE_AMD_AMD8151
 	select CPU_AMD_SOCKET_F
 	select DIMM_DDR2
 	select DIMM_REGISTERED
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index 7ec61f4..406a0b3 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -1,6 +1,6 @@
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8131) += amd8131
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8112) += amd8132
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8132) += amd8132
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8151) += amd8151
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS690) += rs690
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB600) += sb600


From gerrit at coreboot.org  Sat Dec  3 10:49:34 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 3 Dec 2011 10:49:34 +0100
Subject: [coreboot] Patch merged into coreboot/master: 82565a8 Fix Asus
	A8V-E SE DIMM slot mapping
References: <I8c49c4efb90a4297aaea0be2159435dadab9ac0a+0@gerrit.coreboot.org>
Message-ID: <E1RWmDu-0007bf-13@ra.coresystems.de>

the following patch was just integrated into master:
commit 82565a8f061bd46f0d8625a848ea49e97cba8751
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Wed Nov 23 00:23:43 2011 +0100

    Fix Asus A8V-E SE DIMM slot mapping
    
    Fix the DIMM mappings, channel 0 is "B" on board,
    and secondary channel is on 0x51,0x53
    
    Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Dec  3 10:49:20 2011, giving +2
See http://review.coreboot.org/449 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec  3 13:13:37 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 3 Dec 2011 13:13:37 +0100
Subject: [coreboot] Patch merged into coreboot/master: 2796df7 adding
	support for the Asus K8V-X
References: <Ifb97714c2f009d688be0ca3c38ddc01599ffd799+0@gerrit.coreboot.org>
Message-ID: <E1RWoTJ-0002Lz-I1@ra.coresystems.de>

the following patch was just integrated into master:
commit 2796df7bfeec1e1ca09fa23540198cd5056bc71a
Author: Florian Zumbiehl <florz at florz.de>
Date:   Tue Nov 1 20:19:41 2011 +0100

    adding support for the Asus K8V-X
    
    This pulls it all together and adds the real board-specific code.
    
    Confirmed to be working:
    - IDE
    - SATA
    - floppy
    - USB1.1
    - USB2.0
    - PS/2 keyboard
    - PS/2 mouse
    - serial
    - parport
    - sound
    - ethernet
    - PCI slots
    - AGP
    - powernow
    - fan speed monitoring
    - flashrom write
    
    Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
    Signed-off-by: Florian Zumbiehl <florz at florz.de>

Build-Tested: build bot (Jenkins) at Sat Dec  3 01:08:25 2011, giving +1
Reviewed-By: Rudolf Marek <r.marek at assembler.cz> at Sat Dec  3 00:56:36 2011, giving +2
See http://review.coreboot.org/390 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec  3 19:35:16 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Dec 2011 19:35:16 +0100
Subject: [coreboot] Patch set updated for coreboot: 80fbf23 i82801gx: Use
	CMOS variable if available for power-on on power failure
References: <Ib83aa07a3e55bed075150354a060317ebc9d5ba7+0@gerrit.coreboot.org>
Message-ID: <Ib83aa07a3e55bed075150354a060317ebc9d5ba7+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/443

-gerrit

commit 80fbf232709d8a95fda8f58de9aa3305600dd7b4
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Nov 22 10:28:46 2011 +0100

    i82801gx: Use CMOS variable if available for power-on on power failure
    
    We used a hard coded value for some reason. Don't do that, but use CMOS
    instead.
    
    Change-Id: Ib83aa07a3e55bed075150354a060317ebc9d5ba7
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/southbridge/intel/i82801gx/smihandler.c |   12 ++++++++----
 1 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 48375e4..5cc25e7 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -279,12 +279,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 	u8 reg8;
 	u32 reg32;
 	u8 slp_typ;
-	/* FIXME: the power state on boot should be read from
-	 * CMOS or even better from GNVS. Right now it's hard
-	 * coded at compile time.
-	 */
 	u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 
+	// save and recover RTC port values
+	u8 tmp70, tmp72;
+	tmp70 = inb(0x70);
+	tmp72 = inb(0x72);
+	get_option(&s5pwr, "power_on_after_fail");
+	outb(tmp70, 0x70);
+	outb(tmp72, 0x72);
+
 	/* First, disable further SMIs */
 	reg8 = inb(pmbase + SMI_EN);
 	reg8 &= ~SLP_SMI_EN;


From gerrit at coreboot.org  Sat Dec  3 19:35:17 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Dec 2011 19:35:17 +0100
Subject: [coreboot] Patch set updated for coreboot: cfcf2d3 i82801gx:
	Support power-on-after-power-fail better
References: <If1d88c1c34c3333b636ed3ec1e1fb9bea394e615+0@gerrit.coreboot.org>
Message-ID: <If1d88c1c34c3333b636ed3ec1e1fb9bea394e615+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/444

-gerrit

commit cfcf2d38858078e74ff6d0e34323f1da71a0fe1f
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Nov 22 10:52:43 2011 +0100

    i82801gx: Support power-on-after-power-fail better
    
    Changing CMOS value for power-on-after-power-fail was only honored
    after reboot, which is counter intuitive (set from "enable" to "disable",
    power-off, replug device -> device turns on; and similar cases).
    
    Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/southbridge/intel/i82801gx/smihandler.c |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 5cc25e7..401c9ad 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -316,16 +316,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 
 		outl(0, pmbase + GPE0_EN);
 
-		/* Should we keep the power state after a power loss?
-		 * In case the setting is "ON" or "OFF" we don't have
-		 * to do anything. But if it's "KEEP" we have to switch
-		 * to "OFF" before entering S5.
+		/* Always set the flag in case CMOS was changed on runtime. For
+		 * "KEEP", switch to "OFF" - KEEP is software emulated
 		 */
-		if (s5pwr == MAINBOARD_POWER_KEEP) {
-			reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+		reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+		if (s5pwr == MAINBOARD_POWER_ON) {
+			reg8 &= ~1;
+		} else {
 			reg8 |= 1;
-			pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
 		}
+		pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
 
 		/* also iterates over all bridges on bus 0 */
 		busmaster_disable_on_bus(0);


From gerrit at coreboot.org  Sun Dec  4 22:37:46 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Sun, 4 Dec 2011 22:37:46 +0100
Subject: [coreboot] New patch to review for coreboot: 72e5c9e Sconfig: parse
	Kconfig options from devicetree.cb
References: <I808d44af552dbc5e0565d6a0f4f72c7be9f5740e+0@gerrit.coreboot.org>
Message-ID: <I808d44af552dbc5e0565d6a0f4f72c7be9f5740e+1@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/472

-gerrit

commit 72e5c9ebb5c55dc44b54d7382a47d0fb60b25263
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Sun Dec 4 12:46:46 2011 +0200

    Sconfig: parse Kconfig options from devicetree.cb
    
    Mainboard and chip Kconfig files have several build options that
    are redundant with information in devicetree.cb. This patch enables
    sconfig to auto-generate equivalent configuration.
    
      sconfig -s
    
    Generates mainboard's static.c file, as before.
    
      sconfig -b
    
    This operation creates mainboard's bootblock init code. By default,
    for every chip listed in mainboard/devicetree.cb, if there is a
    chip/bootblock.c file, the init function is called.
    A mainboard/bootblock.c file can be added to override default
    behaviour.
    
      sconfig -k
    
    This operation generates select -options for component paths.
    
    Change-Id: I808d44af552dbc5e0565d6a0f4f72c7be9f5740e
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 util/sconfig/main.c |  166 +++++++++++++++++++++++++++++++++++++++-----------
 1 files changed, 129 insertions(+), 37 deletions(-)

diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index dab04db..960e6b2 100644
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -28,6 +28,7 @@ struct device *head, *lastdev;
 struct header headers;
 
 static int devcount = 0;
+static int scan_mode = 0;
 
 static struct device root;
 static struct device mainboard = {
@@ -116,21 +117,28 @@ void postprocess_devtree(void) {
 	}
 }
 
+void translate_name(char *str, int uppercase)
+{
+	char *c;
+	for (c = str; *c; c++) {
+		if (*c == '/') *c = '_';
+		if (*c == '-') *c = '_';
+		if (uppercase)
+			*c = toupper(*c);
+	}
+}
+
 struct device *new_chip(struct device *parent, struct device *bus, char *path) {
 	struct device *new_chip = new_dev(parent, bus);
 	new_chip->chiph_exists = 1;
 	new_chip->name = path;
 	new_chip->name_underscore = strdup(new_chip->name);
-	char *c;
-	for (c = new_chip->name_underscore; *c; c++) {
-		if (*c == '/') *c = '_';
-		if (*c == '-') *c = '_';
-	}
+	translate_name(new_chip->name_underscore, 0);
 	new_chip->type = chip;
 	new_chip->chip = new_chip;
 
 	struct stat st;
-	char *chip_h = malloc(strlen(path)+12);
+	char *chip_h = malloc(strlen(path)+18);
 	sprintf(chip_h, "src/%s", path);
 	if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) {
 		fprintf(stderr, "ERROR: Chip component %s does not exist.\n",
@@ -138,10 +146,16 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) {
 		exit(1);
 	}
 
-	sprintf(chip_h, "src/%s/chip.h", path);
-	if ((stat(chip_h, &st) == -1) && (errno == ENOENT))
-		new_chip->chiph_exists = 0;
+	if (scan_mode == 0)
+		sprintf(chip_h, "src/%s/chip.h", path);
+	else if (scan_mode == 1)
+		sprintf(chip_h, "src/%s/bootblock.c", path);
 
+	if ((scan_mode == 0) || (scan_mode == 1)) {
+		if ((stat(chip_h, &st) == -1) && (errno == ENOENT))
+			new_chip->chiph_exists = 0;
+	}
+	
 	if (parent->latestchild) {
 		parent->latestchild->next_sibling = new_chip;
 		parent->latestchild->sibling = new_chip;
@@ -153,7 +167,7 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) {
 }
 
 void add_header(struct device *dev) {
-	if (dev->chiph_exists) {
+	if ((dev->chiph_exists) || (scan_mode==2)){
 		int include_exists = 0;
 		struct header *h = &headers;
 		while (h->next) {
@@ -399,7 +413,8 @@ static void pass1(FILE *fil, struct device *ptr) {
 	}
 	if ((ptr->type == chip) && (ptr->chiph_exists)) {
 		if (ptr->reg) {
-			fprintf(fil, "struct %s_config %s_info_%d\t= {\n", ptr->name_underscore, ptr->name_underscore, ptr->id);
+			fprintf(fil, "struct %s_config %s_info_%d\t= {\n",
+				ptr->name_underscore, ptr->name_underscore, ptr->id);
 			struct reg *r = ptr->reg;
 			while (r) {
 				fprintf(fil, "\t.%s = %s,\n", r->key, r->value);
@@ -407,7 +422,8 @@ static void pass1(FILE *fil, struct device *ptr) {
 			}
 			fprintf(fil, "};\n\n");
 		} else {
-			fprintf(fil, "struct %s_config %s_info_%d;\n", ptr->name_underscore, ptr->name_underscore, ptr->id);
+			fprintf(fil, "struct %s_config %s_info_%d;\n",
+				ptr->name_underscore, ptr->name_underscore, ptr->id);
 		}
 	}
 }
@@ -441,23 +457,61 @@ static void inherit_subsystem_ids(FILE *file, struct device *dev)
 	}
 }
 
+static void usage(void)
+{
+	printf("usage: sconfig vendor/mainboard outputdir [-{s|b|k} outputfile]\n");
+	printf("\t-s file\tcreate ramstage static device map\n");
+	printf("\t-b file\tcreate bootblock init_mainboard()\n");
+	printf("\t-k file\tcreate Kconfig devicetree section\n");
+	printf("\nDefaults to \"-s static.c\" if no {s|b|k} specified.\n");
+	exit (1);
+}
+
+
 int main(int argc, char** argv) {
-	if (argc != 3) {
-		printf("usage: sconfig vendor/mainboard outputdir\n");
-		return 1;
-	}
+	if (argc < 3)
+		usage();
+
 	char *mainboard=argv[1];
 	char *outputdir=argv[2];
 	char *devtree=malloc(strlen(mainboard)+30);
-	char *outputc=malloc(strlen(outputdir)+10);
 	sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard);
-	sprintf(outputc, "%s/static.c", outputdir);
+	char *outputc;
+	
+	if (argc == 3) {
+		scan_mode = 0;
+		outputc=malloc(strlen(outputdir)+20);
+		sprintf(outputc, "%s/static.c", outputdir);
+	} else if ((argc == 5) && (argv[3][0] == '-') && (argv[3][2] == 0)) {
+
+		switch (argv[3][1]) {
+		case 's':
+			scan_mode = 0;
+			break;
+		case 'b':
+			scan_mode = 1;
+			break;
+		case 'k':
+			scan_mode = 2;
+			break;
+		default:
+			usage();
+			break;
+		}
+		char *outputfile=argv[4];
 
-	headers.next = malloc(sizeof(struct header));
-	headers.next->name = malloc(strlen(mainboard)+12);
-	headers.next->next = 0;
-	sprintf(headers.next->name, "mainboard/%s", mainboard);
+		outputc=malloc(strlen(outputdir)+strlen(outputfile)+2);
+		sprintf(outputc, "%s/%s", outputdir, outputfile);
+	}
 
+	headers.next = 0;
+	if (scan_mode == 0) {
+		headers.next = malloc(sizeof(struct header));
+		headers.next->name = malloc(strlen(mainboard)+12);
+		headers.next->next = 0;
+		sprintf(headers.next->name, "mainboard/%s", mainboard);
+	}
+	
 	FILE *filec = fopen(devtree, "r");
 	if (!filec) {
 		fprintf(stderr, "Could not open file '%s' for reading: ", devtree);
@@ -479,29 +533,67 @@ int main(int argc, char** argv) {
 		while (head->next != tmp) head = head->next;
 	}
 
-	FILE *staticc = fopen(outputc, "w");
-	if (!staticc) {
+	FILE *autogen = fopen(outputc, "w");
+	if (!autogen) {
 		fprintf(stderr, "Could not open file '%s' for writing: ", outputc);
 		perror(NULL);
 		exit(1);
 	}
 
-	fprintf(staticc, "#include <device/device.h>\n");
-	fprintf(staticc, "#include <device/pci.h>\n");
-	struct header *h = &headers;
-	while (h->next) {
-		h = h->next;
-		fprintf(staticc, "#include \"%s/chip.h\"\n", h->name);
-	}
+	struct header *h;
+	if (scan_mode == 0) {
+
+		fprintf(autogen, "#include <device/device.h>\n");
+		fprintf(autogen, "#include <device/pci.h>\n");
+		h = &headers;
+		while (h->next) {
+			h = h->next;
+			fprintf(autogen, "#include \"%s/chip.h\"\n", h->name);
+		}
+
+		walk_device_tree(autogen, &root, inherit_subsystem_ids, NULL);
+		fprintf(autogen, "\n/* pass 0 */\n");
+		walk_device_tree(autogen, &root, pass0, NULL);
+		fprintf(autogen, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\n"
+						"struct device *last_dev = &%s;\n", lastdev->name);
+		walk_device_tree(autogen, &root, pass1, NULL);
+
+	} else if (scan_mode == 1) {
+		h = &headers;
+		while (h->next) {
+			h = h->next;
+			fprintf(autogen, "#include \"%s/bootblock.c\"\n", h->name);
+		}
 
-	walk_device_tree(staticc, &root, inherit_subsystem_ids, NULL);
+		fprintf(autogen, "\n#if CONFIG_HAS_MAINBOARD_BOOTBLOCK\n");
+		fprintf(autogen, "#include \"mainboard/%s/bootblock.c\"\n", mainboard);
+		fprintf(autogen, "#else\n");
+		fprintf(autogen, "static unsigned long init_mainboard(int bsp_cpu)\n{\n");
+		fprintf(autogen, "\tif (! bsp_cpu) return 0;\n");
+		h = &headers;
+		while (h->next) {
+			h = h->next;
+			translate_name(h->name, 0);
+			fprintf(autogen, "\tinit_%s();\n", h->name);
+		}
+		
+		fprintf(autogen, "\treturn 0;\n}\n");
+		fprintf(autogen, "#endif\n");
 
-	fprintf(staticc, "\n/* pass 0 */\n");
-	walk_device_tree(staticc, &root, pass0, NULL);
-	fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device *last_dev = &%s;\n", lastdev->name);
-	walk_device_tree(staticc, &root, pass1, NULL);
+	} else if (scan_mode == 2) {
+		fprintf(autogen, "\nconfig MAINBOARD_DIR\n\tstring\n"); 
+		fprintf(autogen, "\tdefault %s\n", mainboard); 
+
+		fprintf(autogen, "\nconfig MAINBOARD_DEVTREE\n\tdef_bool y\n"); 
+		h = &headers;
+		while (h->next) {
+			h = h->next;
+			translate_name(h->name, 1);
+			fprintf(autogen, "\tselect %s\n", h->name);
+		}
+	}
 
-	fclose(staticc);
+	fclose(autogen);
 
 	return 0;
 }


From gerrit at coreboot.org  Sun Dec  4 22:37:46 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Sun, 4 Dec 2011 22:37:46 +0100
Subject: [coreboot] New patch to review for coreboot: 5500248 Auto-generate
	bootblock initialisation
References: <Ib1d101cdd68993530c9c7a653ac000a01de52ac2+0@gerrit.coreboot.org>
Message-ID: <Ib1d101cdd68993530c9c7a653ac000a01de52ac2+1@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/473

-gerrit

commit 5500248a5ce26e616a77e9632e469413604a382c
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Sun Dec 4 21:35:38 2011 +0200

    Auto-generate bootblock initialisation
    
    The following chip-specific functions were renamed to include
    chip name in the function:
      - bootblock_northbridge_init
      - bootblock_southbridge_init
    
    The following no-operation bootblock.c files were removed:
      - northbridge/amd/agesa/family10/bootblock.c
      - northbridge/amd/agesa/family12/bootblock.c
      - northbridge/amd/agesa/family14/bootblock.c
    
    A new init function called from bootblock is declared as:
      - unsigned long init_mainboard(int bsp_cpu)
    
    For BSP CPU bootblock calls init_mainboard(true). For AP CPUs bootblock
    calls init_mainboard(false). Usually AP CPU has nothing to do here.
    
    By default, build toolchain creates and includes an init_mainboard()
    function in file build/mainboard/x/x/bootblock_autogen.h that executes
    init functions from any bootblock.c files for all chips listed in
    mainboard/devtree.cb.
    
    Alternatively a mainboard/x/x/bootblock.c file is added in the
    bootblock build, if a Kconfig option HAS_MAINBOARD_BOOTBLOCK is set.
    One should copy the auto-generated init_mainboard() to this file,
    and optionally read various bootstrap signals or status bits from
    super-io and southbridge component to gain some control over the
    selection of romstage to boot via the return value.
    
    Samples of such (yet not implemented) controls for boot behaviour:
      - Reset CMOS to defaults on user request (jumper).
      - Use fallback prefix after power-button 4s override.
      - Refuse boot after intruder detection.
      - On remote wakeup, request network boot.
    
    Change-Id: Ib1d101cdd68993530c9c7a653ac000a01de52ac2
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/Kconfig                           |    7 +----
 src/arch/x86/Makefile.inc                      |    9 +++++-
 src/arch/x86/include/bootblock_common.h        |   17 +-------------
 src/arch/x86/init/bootblock_normal.c           |   12 +++++-----
 src/arch/x86/init/bootblock_simple.c           |   10 ++++----
 src/mainboard/hp/dl165_g6_fam10/Kconfig        |    5 +---
 src/mainboard/hp/dl165_g6_fam10/bootblock.c    |   10 +++++++-
 src/northbridge/amd/agesa/family10/Kconfig     |    3 --
 src/northbridge/amd/agesa/family10/bootblock.c |   29 ------------------------
 src/northbridge/amd/agesa/family12/Kconfig     |    4 ---
 src/northbridge/amd/agesa/family12/bootblock.c |   29 ------------------------
 src/northbridge/amd/agesa/family14/Kconfig     |    4 ---
 src/northbridge/amd/agesa/family14/bootblock.c |   29 ------------------------
 src/northbridge/amd/amdfam10/Kconfig           |    4 ---
 src/northbridge/amd/amdfam10/bootblock.c       |    2 +-
 src/northbridge/amd/amdk8/Kconfig              |    4 ---
 src/northbridge/amd/amdk8/bootblock.c          |    2 +-
 src/southbridge/amd/amd8111/Kconfig            |    4 ---
 src/southbridge/amd/amd8111/bootblock.c        |    2 +-
 src/southbridge/amd/cimx/sb800/Kconfig         |    3 --
 src/southbridge/amd/cimx/sb800/bootblock.c     |    2 +-
 src/southbridge/amd/cimx/sb900/Kconfig         |    3 --
 src/southbridge/amd/cimx/sb900/bootblock.c     |    2 +-
 src/southbridge/amd/sb600/Kconfig              |    3 --
 src/southbridge/amd/sb600/bootblock.c          |    2 +-
 src/southbridge/amd/sb700/Kconfig              |    5 ----
 src/southbridge/amd/sb700/bootblock.c          |    2 +-
 src/southbridge/amd/sb800/Kconfig              |    5 ----
 src/southbridge/amd/sb800/bootblock.c          |    2 +-
 src/southbridge/broadcom/bcm5785/Kconfig       |    4 ---
 src/southbridge/broadcom/bcm5785/bootblock.c   |    2 +-
 src/southbridge/intel/i82371eb/Kconfig         |    5 ----
 src/southbridge/intel/i82371eb/bootblock.c     |    2 +-
 src/southbridge/intel/i82801gx/Kconfig         |    5 ----
 src/southbridge/intel/i82801gx/bootblock.c     |    2 +-
 src/southbridge/nvidia/ck804/Kconfig           |    4 ---
 src/southbridge/nvidia/ck804/bootblock.c       |    2 +-
 src/southbridge/nvidia/mcp55/Kconfig           |    4 ---
 src/southbridge/nvidia/mcp55/bootblock.c       |    2 +-
 src/southbridge/sis/sis966/Kconfig             |    5 +---
 src/southbridge/sis/sis966/bootblock.c         |    2 +-
 src/southbridge/via/vt8237r/Kconfig            |    4 ---
 src/southbridge/via/vt8237r/bootblock.c        |    2 +-
 43 files changed, 47 insertions(+), 213 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index e71d0f3..07ad95f 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -67,8 +67,8 @@ config PC80_SYSTEM
 	bool
 	default y
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-	string
+config HAS_MAINBOARD_BOOTBLOCK
+	def_bool n
 
 config HAVE_CMOS_DEFAULT
 	def_bool n
@@ -77,9 +77,6 @@ config CMOS_DEFAULT_FILE
 	string
 	depends on HAVE_CMOS_DEFAULT
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-
 config BIG_ENDIAN
 	bool
 	default n
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7bba44e..2595595 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -331,11 +331,16 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@
 
-$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H)
+$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h $(objutil)/romcc/romcc $(OPTION_TABLE_H)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \
 		$< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d
-	$(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@
+	$(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) -I$(@D) $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig
+	@printf "    SCONFIG    $(subst $(src)/,,$(<)) (bootblock)\n"
+	mkdir -p $(@D)
+	$(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(@D) -b $(@F)
 
 $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h
index bd19682..69ab22c 100644
--- a/src/arch/x86/include/bootblock_common.h
+++ b/src/arch/x86/include/bootblock_common.h
@@ -1,22 +1,7 @@
 #include <cpu/x86/lapic/boot_cpu.c>
 
-#ifdef CONFIG_BOOTBLOCK_CPU_INIT
-#include CONFIG_BOOTBLOCK_CPU_INIT
-#else
-static void bootblock_cpu_init(void) { }
-#endif
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#else
-static void bootblock_northbridge_init(void) { }
-#endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#else
-static void bootblock_southbridge_init(void) { }
-#endif
-
 #include <arch/cbfs.h>
+#include "bootblock_autogen.h"
 
 #if CONFIG_USE_OPTION_TABLE
 #include <pc80/mc146818rtc.h>
diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c
index a0b7b37..48b4131 100644
--- a/src/arch/x86/init/bootblock_normal.c
+++ b/src/arch/x86/init/bootblock_normal.c
@@ -4,19 +4,19 @@
 static void main(unsigned long bist)
 {
 	unsigned long entry;
+	int bsp_cpu = boot_cpu();
 	int boot_mode;
-	
-	if (boot_cpu()) {
-		bootblock_northbridge_init();
-		bootblock_southbridge_init();
-		bootblock_cpu_init();
 
+	/* Mainboard-specific early init. */
+	init_mainboard(bsp_cpu);
+
+	if (bsp_cpu) {
 #if CONFIG_USE_OPTION_TABLE
 		sanitize_cmos();
 #endif
 		boot_mode = do_normal_boot();
 	} else {
-	
+
 		/* Questionable single byte read from CMOS.
 		 * Do not add any other CMOS access in the
 		 * bootblock for AP CPUs.
diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c
index 41f73b4..f4e4bbf 100644
--- a/src/arch/x86/init/bootblock_simple.c
+++ b/src/arch/x86/init/bootblock_simple.c
@@ -2,15 +2,15 @@
 
 static void main(unsigned long bist)
 {
-	if (boot_cpu()) {
-		bootblock_northbridge_init();
-		bootblock_southbridge_init();
-		bootblock_cpu_init();
+	int bsp_cpu = boot_cpu();
+
+	/* Mainboard-specific early init. */
+	init_mainboard(bsp_cpu);
 
 #if CONFIG_USE_OPTION_TABLE
+	if (bsp_cpu)
 		sanitize_cmos();
 #endif
-	}
 
 	const char* target1 = "fallback/romstage";
 	unsigned long entry;
diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig
index e3dbf6b..b8a25d8 100644
--- a/src/mainboard/hp/dl165_g6_fam10/Kconfig
+++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select HAVE_HARD_RESET
+	select HAS_MAINBOARD_BOOTBLOCK
 	select LIFT_BSP_APIC_ID
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
@@ -91,10 +92,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "mainboard/hp/dl165_g6_fam10/bootblock.c"
-
 config MMCONF_SUPPORT_DEFAULT
 	bool
 	default y
diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
index 2c56c4c..e7c0680 100644
--- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c
+++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
@@ -18,6 +18,9 @@ static inline void shc4307_exit_ext_func_mode(device_t dev)
 #define DBG_DEV  PNP_DEV(SCH4307_CONFIG_PORT, 0x3)
 #define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa)
 
+/* FIXME: This appears to be a super-io initialisation,
+ *        placed in the mainboard directory.
+ */
 void shc4307_init(void)
 {
 	shc4307_enter_ext_func_mode(CMOS_DEV);
@@ -43,6 +46,11 @@ void shc4307_init(void)
 	shc4307_exit_ext_func_mode(CMOS_DEV);
 }
 
-static void bootblock_southbridge_init(void) {
+static unsigned long init_mainboard(int bsp_cpu)
+{
+	if (!bsp_cpu) return 0;
+	init_northbridge_amd_amdfam10();
+	//init_southbridge_broadcom_bcm5785();
 	shc4307_init();
+	return 0;
 }
diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig
index 62a6cd4..0bb16d9 100755
--- a/src/northbridge/amd/agesa/family10/Kconfig
+++ b/src/northbridge/amd/agesa/family10/Kconfig
@@ -41,9 +41,6 @@ config MMCONF_BASE_ADDRESS
 config MMCONF_BUS_NUMBER
 	int
 	default 256
-config BOOTBLOCK_NORTHBRIDGE_INIT
-  string
-  default "northbridge/amd/agesa/family10/bootblock.c"
 endif #NORTHBRIDGE_AMD_AGESA_FAMILY10
 
 source "src/northbridge/amd/agesa/family10/root_complex/Kconfig"
diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c
deleted file mode 100644
index f6ae8be..0000000
--- a/src/northbridge/amd/agesa/family10/bootblock.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-
-static void bootblock_northbridge_init(void) {
-}
diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig
index fc3c436..8ab5de8 100755
--- a/src/northbridge/amd/agesa/family12/Kconfig
+++ b/src/northbridge/amd/agesa/family12/Kconfig
@@ -73,7 +73,3 @@ if DIMM_DDR3
 	endif
 endif
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-  string
-  default "northbridge/amd/agesa/family12/bootblock.c"
-	depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c
deleted file mode 100644
index f6ae8be..0000000
--- a/src/northbridge/amd/agesa/family12/bootblock.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-
-static void bootblock_northbridge_init(void) {
-}
diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig
index 44f93c1..e462153 100644
--- a/src/northbridge/amd/agesa/family14/Kconfig
+++ b/src/northbridge/amd/agesa/family14/Kconfig
@@ -39,8 +39,4 @@ config MMCONF_BUS_NUMBER
 	int
 	default 16
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-  string
-  default "northbridge/amd/agesa/family14/bootblock.c"
-
 endif
diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c
deleted file mode 100644
index f6ae8be..0000000
--- a/src/northbridge/amd/agesa/family14/bootblock.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-
-static void bootblock_northbridge_init(void) {
-}
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 74e0ff4..a1594ad 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -59,10 +59,6 @@ config MMCONF_BUS_NUMBER
 	int
 	default 256
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-        string
-        default "northbridge/amd/amdfam10/bootblock.c"
-
 config SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	bool
 	default n
diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c
index 612004a..328e9ad 100644
--- a/src/northbridge/amd/amdfam10/bootblock.c
+++ b/src/northbridge/amd/amdfam10/bootblock.c
@@ -3,7 +3,7 @@
 #include <device/pci_def.h>
 #include "northbridge/amd/amdfam10/early_ht.c"
 
-static void bootblock_northbridge_init(void) {
+static void init_northbridge_amd_amdfam10(void) {
 	/* Nothing special needs to be done to find bus 0 */
 	/* Allow the HT devices to be found */
 	/* mov bsp to bus 0xff when > 8 nodes */
diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig
index 858041a..418c734 100644
--- a/src/northbridge/amd/amdk8/Kconfig
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -45,10 +45,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-        string
-        default "northbridge/amd/amdk8/bootblock.c"
-
 config SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	bool
 	default n
diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c
index b5395bb..8afd507 100644
--- a/src/northbridge/amd/amdk8/bootblock.c
+++ b/src/northbridge/amd/amdk8/bootblock.c
@@ -3,6 +3,6 @@
 #include <device/pci_def.h>
 #include "northbridge/amd/amdk8/early_ht.c"
 
-static void bootblock_northbridge_init(void) {
+static void init_northbridge_amd_amdk8(void) {
 	enumerate_ht_chain();
 }
diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig
index 83fb8fc..4367017 100644
--- a/src/southbridge/amd/amd8111/Kconfig
+++ b/src/southbridge/amd/amd8111/Kconfig
@@ -21,7 +21,3 @@ config SOUTHBRIDGE_AMD_AMD8111
 	bool
 	select IOAPIC
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/amd8111/bootblock.c"
-	depends on SOUTHBRIDGE_AMD_AMD8111
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
index 3009c0b..d4660de 100644
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ b/src/southbridge/amd/amd8111/bootblock.c
@@ -41,7 +41,7 @@ static void amd8111_enable_rom(void)
 	pci_io_write_config8(dev, 0x43, byte);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_amd8111(void)
 {
 	amd8111_enable_rom();
 }
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 79624e0..fc15c42 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_CIMX_SB800
 	select AMD_SB_CIMX
 
 if SOUTHBRIDGE_AMD_CIMX_SB800
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-        string
-        default "southbridge/amd/cimx/sb800/bootblock.c"
 
 config ENABLE_IDE_COMBINED_MODE
 	bool "Enable SATA IDE combined mode"
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 0a339b0..9e00219 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -104,7 +104,7 @@ static void enable_clocks(void)
 	*acpi_mmio = reg32;
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_cimx_sb800(void)
 {
 	/* Setup the rom access for 2M */
 	enable_rom();
diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
index 253d73f..09edd1b 100755
--- a/src/southbridge/amd/cimx/sb900/Kconfig
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -49,8 +49,5 @@ config ACPI_SCI_IRQ
 	help
 		Set SCI IRQ to 9.
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-        string
-        default "southbridge/amd/cimx/sb900/bootblock.c"
 endif #SOUTHBRIDGE_AMD_CIMX_SB900
 
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index e84743b..f3b53d0 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -90,7 +90,7 @@ static void sb900_enable_rom(void)
   pci_io_write_config16(dev, 0x6c, word);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_cimx_sb900(void)
 {
   /* Setup the rom access for 2M */
   sb900_enable_rom();
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig
index 07028a0..79715d7 100644
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -23,9 +23,6 @@ config SOUTHBRIDGE_AMD_SB600
 	select HAVE_USBDEBUG
 
 if SOUTHBRIDGE_AMD_SB600
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/sb600/bootblock.c"
 
 config EHCI_BAR
 	hex
diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c
index 7007622..db9052e 100644
--- a/src/southbridge/amd/sb600/bootblock.c
+++ b/src/southbridge/amd/sb600/bootblock.c
@@ -64,7 +64,7 @@ static void sb600_enable_rom(void)
 	pci_write_config16(dev, 0x6e, 0xffff);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_sb600(void)
 {
 	sb600_enable_rom();
 }
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index 98b8e2a..02ffdca 100644
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -27,11 +27,6 @@ config SOUTHBRIDGE_AMD_SP5100
 	select IOAPIC
 	select HAVE_USBDEBUG
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/sb700/bootblock.c"
-	depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100)
-
 config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
 	bool
 	default n
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index 377bffc..a2a2653 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -64,7 +64,7 @@ static void sb700_enable_rom(void)
 	pci_write_config16(dev, 0x6e, 0xffff);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_sb700(void)
 {
 	sb700_enable_rom();
 }
diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig
index 67cb8ef..075e454 100644
--- a/src/southbridge/amd/sb800/Kconfig
+++ b/src/southbridge/amd/sb800/Kconfig
@@ -22,11 +22,6 @@ config SOUTHBRIDGE_AMD_SB800
 	select IOAPIC
 	select HAVE_USBDEBUG
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/sb800/bootblock.c"
-	depends on SOUTHBRIDGE_AMD_SB800
-
 config SOUTHBRIDGE_AMD_SB800_SKIP_ISA_DMA_INIT
 	bool
 	default n
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 18eae24..9f7c2c2 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -62,7 +62,7 @@ static void sb800_enable_rom(void)
 	pci_write_config16(dev, 0x6e, 0xffff);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_sb800(void)
 {
 	sb800_enable_rom();
 }
diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig
index d72afd8..286c19b 100644
--- a/src/southbridge/broadcom/bcm5785/Kconfig
+++ b/src/southbridge/broadcom/bcm5785/Kconfig
@@ -2,7 +2,3 @@ config SOUTHBRIDGE_BROADCOM_BCM5785
 	bool
 	select HAVE_HARD_RESET
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/broadcom/bcm5785/bootblock.c"
-	depends on SOUTHBRIDGE_BROADCOM_BCM5785
diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
index cadda53..e1e5f31 100644
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ b/src/southbridge/broadcom/bcm5785/bootblock.c
@@ -38,7 +38,7 @@ static void bcm5785_enable_rom(void)
 	pci_write_config8(dev, 0x41, byte);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_broadcom_bcm5785(void)
 {
 	bcm5785_enable_rom();
 }
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
index 7e5109a..a5c5eb8 100644
--- a/src/southbridge/intel/i82371eb/Kconfig
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -2,8 +2,3 @@ config SOUTHBRIDGE_INTEL_I82371EB
 	bool
 	select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/intel/i82371eb/bootblock.c"
-	depends on SOUTHBRIDGE_INTEL_I82371EB
-
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index 07fa0bc..a875723 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -48,7 +48,7 @@ static void i82371eb_enable_rom(void)
 	pci_write_config16(dev, XBCS, reg16);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_intel_i82371eb(void)
 {
 	i82371eb_enable_rom();
 }
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index a6bd202..f63c12f 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -38,10 +38,5 @@ config USBDEBUG_DEFAULT_PORT
 	int
 	default 1 
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-        string
-	default "southbridge/intel/i82801gx/bootblock.c"
-	depends on SOUTHBRIDGE_INTEL_I82801GX
-
 endif
 
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 39b0bd4..a0f73b3 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -33,7 +33,7 @@ static void enable_spi_prefetch(void)
         pci_write_config8(dev, 0xdc, reg8);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_intel_i82801gx(void)
 {
         enable_spi_prefetch();
 }
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 88ab7ff..01cff02 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -6,10 +6,6 @@ config SOUTHBRIDGE_NVIDIA_CK804
 
 if SOUTHBRIDGE_NVIDIA_CK804
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/nvidia/ck804/bootblock.c"
-
 config ID_SECTION_OFFSET
 	hex
 	default 0x80
diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c
index 29c10c8..3175606 100644
--- a/src/southbridge/nvidia/ck804/bootblock.c
+++ b/src/southbridge/nvidia/ck804/bootblock.c
@@ -42,7 +42,7 @@ static void ck804_enable_rom(void)
 	pci_write_config8(addr, 0x88, byte);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_nvidia_ck804(void)
 {
 	ck804_enable_rom();
 }
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index adca4bd..78a1f25 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -5,10 +5,6 @@ config SOUTHBRIDGE_NVIDIA_MCP55
 
 if SOUTHBRIDGE_NVIDIA_MCP55
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/nvidia/mcp55/bootblock.c"
-
 config ID_SECTION_OFFSET
 	hex
 	default 0x80
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c
index affb025..6fb6dbb 100644
--- a/src/southbridge/nvidia/mcp55/bootblock.c
+++ b/src/southbridge/nvidia/mcp55/bootblock.c
@@ -53,7 +53,7 @@ static void mcp55_enable_rom(void)
 	pci_write_config16(addr, 0x90, word);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_nvidia_mcp55(void)
 {
 	mcp55_enable_rom();
 }
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 909a741..da089d3 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -3,10 +3,6 @@ config SOUTHBRIDGE_SIS_SIS966
 	select IOAPIC
 	select HAVE_USBDEBUG
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
-
 config ID_SECTION_OFFSET
 	hex
 	default 0x80 if SOUTHBRIDGE_SIS_SIS966
@@ -18,3 +14,4 @@ config EHCI_BAR
 config EHCI_DEBUG_OFFSET
 	hex
 	default 0x98 if SOUTHBRIDGE_SIS_SIS966
+
diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c
index 1ff3cda..45ab81b 100644
--- a/src/southbridge/sis/sis966/bootblock.c
+++ b/src/southbridge/sis/sis966/bootblock.c
@@ -41,7 +41,7 @@ static void sis966_enable_rom(void)
 	pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_sis_sis966(void)
 {
 	sis966_enable_rom();
 }
diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig
index d0a6deb..9aa1b97 100644
--- a/src/southbridge/via/vt8237r/Kconfig
+++ b/src/southbridge/via/vt8237r/Kconfig
@@ -27,7 +27,3 @@ config EPIA_VT8237R_INIT
 	default n
 	depends on SOUTHBRIDGE_VIA_VT8237R
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/via/vt8237r/bootblock.c"
-	depends on SOUTHBRIDGE_VIA_VT8237R
diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c
index 8df37aa..0ca0533 100644
--- a/src/southbridge/via/vt8237r/bootblock.c
+++ b/src/southbridge/via/vt8237r/bootblock.c
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <device/pci_ids.h>
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_via_vt8237r(void)
 {
 	device_t dev;
 	/* don't walk other busses, HT is not enabled */


From gerrit at coreboot.org  Sun Dec  4 22:37:47 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Sun, 4 Dec 2011 22:37:47 +0100
Subject: [coreboot] Patch set updated for coreboot: fe83213 Only BSP CPU
	writes CMOS in bootblock code
References: <I29118e33c07c0080c94abb90f703e38312c72432+0@gerrit.coreboot.org>
Message-ID: <I29118e33c07c0080c94abb90f703e38312c72432+2@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/446

-gerrit

commit fe832132024c6f48b5c0ee4c71f13eb0996c228c
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Tue Nov 22 19:20:22 2011 +0200

    Only BSP CPU writes CMOS in bootblock code
    
    CMOS accesses are not safe for multi-processor and only the BSP CPU
    should count reboots and test CMOS sanity.
    
    A questionable single byte CMOS read access from AP CPUs remains.
    
    Change-Id: I29118e33c07c0080c94abb90f703e38312c72432
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/init/bootblock_normal.c |   18 ++++++++++++++----
 src/arch/x86/init/bootblock_simple.c |    4 ++--
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c
index db9d0f9..a0b7b37 100644
--- a/src/arch/x86/init/bootblock_normal.c
+++ b/src/arch/x86/init/bootblock_normal.c
@@ -3,18 +3,28 @@
 
 static void main(unsigned long bist)
 {
+	unsigned long entry;
+	int boot_mode;
+	
 	if (boot_cpu()) {
 		bootblock_northbridge_init();
 		bootblock_southbridge_init();
 		bootblock_cpu_init();
-	}
 
 #if CONFIG_USE_OPTION_TABLE
-	sanitize_cmos();
+		sanitize_cmos();
 #endif
+		boot_mode = do_normal_boot();
+	} else {
+	
+		/* Questionable single byte read from CMOS.
+		 * Do not add any other CMOS access in the
+		 * bootblock for AP CPUs.
+		 */
+		boot_mode = last_boot_normal();
+	}
 
-	unsigned long entry;
-	if (do_normal_boot())
+	if (boot_mode)
 		entry = findstage("normal/romstage");
 	else
 		entry = findstage("fallback/romstage");
diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c
index 5d7c611..41f73b4 100644
--- a/src/arch/x86/init/bootblock_simple.c
+++ b/src/arch/x86/init/bootblock_simple.c
@@ -6,11 +6,11 @@ static void main(unsigned long bist)
 		bootblock_northbridge_init();
 		bootblock_southbridge_init();
 		bootblock_cpu_init();
-	}
 
 #if CONFIG_USE_OPTION_TABLE
-	sanitize_cmos();
+		sanitize_cmos();
 #endif
+	}
 
 	const char* target1 = "fallback/romstage";
 	unsigned long entry;


From gerrit at coreboot.org  Sun Dec  4 22:37:47 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Sun, 4 Dec 2011 22:37:47 +0100
Subject: [coreboot] Patch set updated for coreboot: 1395308 Bootblock does
	not need a unique boot_cpu()
References: <I9187f954bb357ba1dbd459cfe11cc96cb7567968+0@gerrit.coreboot.org>
Message-ID: <I9187f954bb357ba1dbd459cfe11cc96cb7567968+2@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/447

-gerrit

commit 13953087baa0032722a55216e02ddb568e3821a0
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Tue Nov 22 19:44:45 2011 +0200

    Bootblock does not need a unique boot_cpu()
    
    Detection of a CPU being a BSP CPU is not dependent of the existence
    of northbridge and/or southbridge init code in the bootblock.
    
    Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP
    CPU of a hyper-threading CPU and needs to return actual BSP bit from
    MSR.
    
    Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/include/bootblock_common.h |    5 -----
 src/cpu/x86/lapic/boot_cpu.c            |    5 +++++
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h
index 4c4a092..bd19682 100644
--- a/src/arch/x86/include/bootblock_common.h
+++ b/src/arch/x86/include/bootblock_common.h
@@ -1,9 +1,4 @@
-#if CONFIG_LOGICAL_CPUS && \
- (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT))
 #include <cpu/x86/lapic/boot_cpu.c>
-#else
-#define boot_cpu(x) 1
-#endif
 
 #ifdef CONFIG_BOOTBLOCK_CPU_INIT
 #include CONFIG_BOOTBLOCK_CPU_INIT
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index bca73e1..87418d0 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,5 +1,6 @@
 #include <cpu/x86/msr.h>
 
+#if CONFIG_SMP
 static int boot_cpu(void)
 {
 	int bsp;
@@ -8,3 +9,7 @@ static int boot_cpu(void)
 	bsp = !!(msr.lo & (1 << 8));
 	return bsp;
 }
+#else
+#define boot_cpu(x) 1
+#endif
+


From gerrit at coreboot.org  Mon Dec  5 08:58:44 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 5 Dec 2011 08:58:44 +0100
Subject: [coreboot] Patch merged into coreboot/master: 5c8526e RS780: print
	the vgainfo
References: <I17c2a13ab52a0f78588f812d4f42f45f9a7b7524+0@gerrit.coreboot.org>
Message-ID: <E1RXTRk-0001Qc-Gt@ra.coresystems.de>

the following patch was just integrated into master:
commit 5c8526e3d32afb22644a92aa5abeb1b3a54eab1b
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date:   Sun Nov 27 13:43:16 2011 +0100

    RS780: print the vgainfo
    
    With this commit the vgainfo is printed and looks like that on the serial console:
    vgainfo:
      ulBootUpEngineClock:50000
      ulBootUpUMAClock:66700
      ulBootUpSidePortClock:0
      ulMinSidePortClock:0
      ulSystemConfig:0
      ulBootUpReqDisplayVector:0
      ulOtherDisplayMisc:0
      ulDDISlot1Config:0
      ulDDISlot2Config:0
      ucMemoryType:0
      ucUMAChannelNumber:1
      ucDockingPinBit:0
      ucDockingPinPolarity:0
      ulDockingPinCFGInfo:0
      ulCPUCapInfo: 2
      usNumberOfCyclesInPeriod:0
      usMaxNBVoltage:0
      usMinNBVoltage:0
      usBootUpNBVoltage:0
      ulHTLinkFreq:20000
      usMinHTLinkWidth:8
      usMaxHTLinkWidth:8
      usUMASyncStartDelay:100
      usUMADataReturnTime:300
      usLinkStatusZeroTime:600
      ulHighVoltageHTLinkFreq:20000
      ulLowVoltageHTLinkFreq:20000
      usMaxUpStreamHTLinkWidth:8
      usMaxDownStreamHTLinkWidth:8
      usMinUpStreamHTLinkWidth:8
      usMinDownStreamHTLinkWidth:8
    
    Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Mon Dec  5 08:58:42 2011, giving +2
See http://review.coreboot.org/456 for details.

-gerrit


From gerrit at coreboot.org  Mon Dec  5 12:20:45 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 5 Dec 2011 12:20:45 +0100
Subject: [coreboot] Patch merged into coreboot/master: 1395308 Bootblock
	does not need a unique boot_cpu()
References: <I9187f954bb357ba1dbd459cfe11cc96cb7567968+0@gerrit.coreboot.org>
Message-ID: <E1RXWbF-0002D3-2c@ra.coresystems.de>

the following patch was just integrated into master:
commit 13953087baa0032722a55216e02ddb568e3821a0
Author: Ky??sti M??lkki <kyosti.malkki at gmail.com>
Date:   Tue Nov 22 19:44:45 2011 +0200

    Bootblock does not need a unique boot_cpu()
    
    Detection of a CPU being a BSP CPU is not dependent of the existence
    of northbridge and/or southbridge init code in the bootblock.
    
    Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP
    CPU of a hyper-threading CPU and needs to return actual BSP bit from
    MSR.
    
    Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968
    Signed-off-by: Ky??sti M??lkki <kyosti.malkki at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Mon Dec  5 12:20:43 2011, giving +2
See http://review.coreboot.org/447 for details.

-gerrit


From svn at coreboot.org  Mon Dec  5 16:00:01 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 05 Dec 2011 16:00:01 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1RXa1R-0003d6-OS@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20111205/1153a41a/attachment.html>

From svn at coreboot.org  Mon Dec  5 19:03:19 2011
From: svn at coreboot.org (coreboot)
Date: Mon, 05 Dec 2011 18:03:19 -0000
Subject: [coreboot]  #182: superiotool installs man page with +x perms
Message-ID: <045.a89667f1b96e22af30939c7f4b444c60@coreboot.org>

#182: superiotool installs man page with +x perms
----------------------------+----------------------------------
    Reporter:  anonymous    |         Owner:  uwe@?
        Type:  defect       |        Status:  new
    Priority:  minor        |     Milestone:  Going mainstream
   Component:  superiotool  |      Keywords:
Dependencies:               |  Patch Status:  there is no patch
----------------------------+----------------------------------
 simple fix:

 {{{
 --- Makefile    (revision 6637)
 +++ Makefile    (working copy)
 @@ -71,7 +71,7 @@ install: $(PROGRAM)
         mkdir -p $(DESTDIR)$(PREFIX)/sbin
         $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin
         mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8
 -       $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8
 +       $(INSTALL) -m 644 $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8

  clean:
         rm -f $(PROGRAM) *.o
 }}}

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/182>
coreboot <http://www.coreboot.org/>


From gerrit at coreboot.org  Mon Dec  5 19:44:26 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Mon, 5 Dec 2011 19:44:26 +0100
Subject: [coreboot] Patch set updated for coreboot: c56b7fb Sconfig: parse
	Kconfig options from devicetree.cb
References: <I808d44af552dbc5e0565d6a0f4f72c7be9f5740e+0@gerrit.coreboot.org>
Message-ID: <I808d44af552dbc5e0565d6a0f4f72c7be9f5740e+2@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/472

-gerrit

commit c56b7fb47a0088292046d5cc2b6f4941273fb675
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Mon Dec 5 20:33:55 2011 +0200

    Sconfig: parse Kconfig options from devicetree.cb
    
    Mainboard and chip Kconfig files have several build options that
    are redundant with information in devicetree.cb. This patch enables
    sconfig to auto-generate equivalent configuration.
    
      sconfig -s
    
    Generates mainboard's static.c file, as before.
    
      sconfig -b
    
    This operation creates mainboard's bootblock init code. By default,
    for every chip listed in mainboard/devicetree.cb, if there is a
    chip/bootblock.c file, the init function is called.
    A mainboard/bootblock.c file can be added to override default
    behaviour.
    
      sconfig -k
    
    This operation generates select -options for component paths.
    
    Change-Id: I808d44af552dbc5e0565d6a0f4f72c7be9f5740e
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 util/sconfig/main.c |  173 ++++++++++++++++++++++++++++++++++++++++-----------
 1 files changed, 136 insertions(+), 37 deletions(-)

diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index dab04db..181be38 100644
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -29,6 +29,14 @@ struct header headers;
 
 static int devcount = 0;
 
+typedef enum {
+	STATIC_MODE,
+	BOOTBLOCK_MODE,
+	KCONFIG_MODE
+} scan_t;
+
+static scan_t scan_mode = STATIC_MODE;
+
 static struct device root;
 static struct device mainboard = {
 	.name = "mainboard",
@@ -116,21 +124,28 @@ void postprocess_devtree(void) {
 	}
 }
 
+void translate_name(char *str, int uppercase)
+{
+	char *c;
+	for (c = str; *c; c++) {
+		if (*c == '/') *c = '_';
+		if (*c == '-') *c = '_';
+		if (uppercase)
+			*c = toupper(*c);
+	}
+}
+
 struct device *new_chip(struct device *parent, struct device *bus, char *path) {
 	struct device *new_chip = new_dev(parent, bus);
 	new_chip->chiph_exists = 1;
 	new_chip->name = path;
 	new_chip->name_underscore = strdup(new_chip->name);
-	char *c;
-	for (c = new_chip->name_underscore; *c; c++) {
-		if (*c == '/') *c = '_';
-		if (*c == '-') *c = '_';
-	}
+	translate_name(new_chip->name_underscore, 0);
 	new_chip->type = chip;
 	new_chip->chip = new_chip;
 
 	struct stat st;
-	char *chip_h = malloc(strlen(path)+12);
+	char *chip_h = malloc(strlen(path)+18);
 	sprintf(chip_h, "src/%s", path);
 	if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) {
 		fprintf(stderr, "ERROR: Chip component %s does not exist.\n",
@@ -138,9 +153,15 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) {
 		exit(1);
 	}
 
-	sprintf(chip_h, "src/%s/chip.h", path);
-	if ((stat(chip_h, &st) == -1) && (errno == ENOENT))
-		new_chip->chiph_exists = 0;
+	if (scan_mode == STATIC_MODE)
+		sprintf(chip_h, "src/%s/chip.h", path);
+	else if (scan_mode == BOOTBLOCK_MODE)
+		sprintf(chip_h, "src/%s/bootblock.c", path);
+
+	if ((scan_mode == STATIC_MODE) || (scan_mode == BOOTBLOCK_MODE)) {
+		if ((stat(chip_h, &st) == -1) && (errno == ENOENT))
+			new_chip->chiph_exists = 0;
+	}
 
 	if (parent->latestchild) {
 		parent->latestchild->next_sibling = new_chip;
@@ -153,7 +174,7 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) {
 }
 
 void add_header(struct device *dev) {
-	if (dev->chiph_exists) {
+	if ((dev->chiph_exists) || (scan_mode == KCONFIG_MODE)){
 		int include_exists = 0;
 		struct header *h = &headers;
 		while (h->next) {
@@ -399,7 +420,8 @@ static void pass1(FILE *fil, struct device *ptr) {
 	}
 	if ((ptr->type == chip) && (ptr->chiph_exists)) {
 		if (ptr->reg) {
-			fprintf(fil, "struct %s_config %s_info_%d\t= {\n", ptr->name_underscore, ptr->name_underscore, ptr->id);
+			fprintf(fil, "struct %s_config %s_info_%d\t= {\n",
+				ptr->name_underscore, ptr->name_underscore, ptr->id);
 			struct reg *r = ptr->reg;
 			while (r) {
 				fprintf(fil, "\t.%s = %s,\n", r->key, r->value);
@@ -407,7 +429,8 @@ static void pass1(FILE *fil, struct device *ptr) {
 			}
 			fprintf(fil, "};\n\n");
 		} else {
-			fprintf(fil, "struct %s_config %s_info_%d;\n", ptr->name_underscore, ptr->name_underscore, ptr->id);
+			fprintf(fil, "struct %s_config %s_info_%d;\n",
+				ptr->name_underscore, ptr->name_underscore, ptr->id);
 		}
 	}
 }
@@ -441,22 +464,60 @@ static void inherit_subsystem_ids(FILE *file, struct device *dev)
 	}
 }
 
+static void usage(void)
+{
+	printf("usage: sconfig vendor/mainboard outputdir [-{s|b|k} outputfile]\n");
+	printf("\t-s file\tcreate ramstage static device map\n");
+	printf("\t-b file\tcreate bootblock init_mainboard()\n");
+	printf("\t-k file\tcreate Kconfig devicetree section\n");
+	printf("Defaults to \"-s static.c\" if no {s|b|k} specified.\n");
+	exit (1);
+}
+
+
 int main(int argc, char** argv) {
-	if (argc != 3) {
-		printf("usage: sconfig vendor/mainboard outputdir\n");
-		return 1;
-	}
+	if (argc < 3)
+		usage();
+
 	char *mainboard=argv[1];
 	char *outputdir=argv[2];
 	char *devtree=malloc(strlen(mainboard)+30);
-	char *outputc=malloc(strlen(outputdir)+10);
 	sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard);
-	sprintf(outputc, "%s/static.c", outputdir);
+	char *outputc;
 
-	headers.next = malloc(sizeof(struct header));
-	headers.next->name = malloc(strlen(mainboard)+12);
-	headers.next->next = 0;
-	sprintf(headers.next->name, "mainboard/%s", mainboard);
+	if (argc == 3) {
+		scan_mode = STATIC_MODE;
+		outputc=malloc(strlen(outputdir)+20);
+		sprintf(outputc, "%s/static.c", outputdir);
+	} else if ((argc == 5) && (argv[3][0] == '-') && (argv[3][2] == 0)) {
+
+		switch (argv[3][1]) {
+		case 's':
+			scan_mode = STATIC_MODE;
+			break;
+		case 'b':
+			scan_mode = BOOTBLOCK_MODE;
+			break;
+		case 'k':
+			scan_mode = KCONFIG_MODE;
+			break;
+		default:
+			usage();
+			break;
+		}
+		char *outputfile=argv[4];
+
+		outputc=malloc(strlen(outputdir)+strlen(outputfile)+2);
+		sprintf(outputc, "%s/%s", outputdir, outputfile);
+	}
+
+	headers.next = 0;
+	if (scan_mode == STATIC_MODE) {
+		headers.next = malloc(sizeof(struct header));
+		headers.next->name = malloc(strlen(mainboard)+12);
+		headers.next->next = 0;
+		sprintf(headers.next->name, "mainboard/%s", mainboard);
+	}
 
 	FILE *filec = fopen(devtree, "r");
 	if (!filec) {
@@ -479,29 +540,67 @@ int main(int argc, char** argv) {
 		while (head->next != tmp) head = head->next;
 	}
 
-	FILE *staticc = fopen(outputc, "w");
-	if (!staticc) {
+	FILE *autogen = fopen(outputc, "w");
+	if (!autogen) {
 		fprintf(stderr, "Could not open file '%s' for writing: ", outputc);
 		perror(NULL);
 		exit(1);
 	}
 
-	fprintf(staticc, "#include <device/device.h>\n");
-	fprintf(staticc, "#include <device/pci.h>\n");
-	struct header *h = &headers;
-	while (h->next) {
-		h = h->next;
-		fprintf(staticc, "#include \"%s/chip.h\"\n", h->name);
-	}
+	struct header *h;
+	if (scan_mode == STATIC_MODE) {
 
-	walk_device_tree(staticc, &root, inherit_subsystem_ids, NULL);
+		fprintf(autogen, "#include <device/device.h>\n");
+		fprintf(autogen, "#include <device/pci.h>\n");
+		h = &headers;
+		while (h->next) {
+			h = h->next;
+			fprintf(autogen, "#include \"%s/chip.h\"\n", h->name);
+		}
 
-	fprintf(staticc, "\n/* pass 0 */\n");
-	walk_device_tree(staticc, &root, pass0, NULL);
-	fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device *last_dev = &%s;\n", lastdev->name);
-	walk_device_tree(staticc, &root, pass1, NULL);
+		walk_device_tree(autogen, &root, inherit_subsystem_ids, NULL);
+		fprintf(autogen, "\n/* pass 0 */\n");
+		walk_device_tree(autogen, &root, pass0, NULL);
+		fprintf(autogen, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\n"
+						"struct device *last_dev = &%s;\n", lastdev->name);
+		walk_device_tree(autogen, &root, pass1, NULL);
+
+	} else if (scan_mode == BOOTBLOCK_MODE) {
+		h = &headers;
+		while (h->next) {
+			h = h->next;
+			fprintf(autogen, "#include \"%s/bootblock.c\"\n", h->name);
+		}
+
+		fprintf(autogen, "\n#if CONFIG_HAS_MAINBOARD_BOOTBLOCK\n");
+		fprintf(autogen, "#include \"mainboard/%s/bootblock.c\"\n", mainboard);
+		fprintf(autogen, "#else\n");
+		fprintf(autogen, "static unsigned long init_mainboard(int bsp_cpu)\n{\n");
+		fprintf(autogen, "\tif (! bsp_cpu) return 0;\n");
+		h = &headers;
+		while (h->next) {
+			h = h->next;
+			translate_name(h->name, 0);
+			fprintf(autogen, "\tinit_%s();\n", h->name);
+		}
+
+		fprintf(autogen, "\treturn 0;\n}\n");
+		fprintf(autogen, "#endif\n");
+
+	} else if (scan_mode == KCONFIG_MODE) {
+		fprintf(autogen, "\nconfig MAINBOARD_DIR\n\tstring\n");
+		fprintf(autogen, "\tdefault %s\n", mainboard);
+
+		fprintf(autogen, "\nconfig MAINBOARD_DEVTREE\n\tdef_bool y\n");
+		h = &headers;
+		while (h->next) {
+			h = h->next;
+			translate_name(h->name, 1);
+			fprintf(autogen, "\tselect %s\n", h->name);
+		}
+	}
 
-	fclose(staticc);
+	fclose(autogen);
 
 	return 0;
 }


From gerrit at coreboot.org  Mon Dec  5 19:44:27 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Mon, 5 Dec 2011 19:44:27 +0100
Subject: [coreboot] Patch set updated for coreboot: c5ffb4f Only BSP CPU
	writes CMOS in bootblock code
References: <I29118e33c07c0080c94abb90f703e38312c72432+0@gerrit.coreboot.org>
Message-ID: <I29118e33c07c0080c94abb90f703e38312c72432+3@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/446

-gerrit

commit c5ffb4f0fcb1bf57a6376234ecf411678080569c
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Mon Dec 5 20:17:17 2011 +0200

    Only BSP CPU writes CMOS in bootblock code
    
    CMOS accesses are not safe for multi-processor and only the BSP CPU
    should count reboots and test CMOS sanity.
    
    A questionable single byte CMOS read access from AP CPUs remains.
    AP CPUs should always select the same romstage prefix as BSP CPU.
    
    Change-Id: I29118e33c07c0080c94abb90f703e38312c72432
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/init/bootblock_normal.c |   18 ++++++++++++++----
 src/arch/x86/init/bootblock_simple.c |    4 ++--
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c
index db9d0f9..f8ae13b 100644
--- a/src/arch/x86/init/bootblock_normal.c
+++ b/src/arch/x86/init/bootblock_normal.c
@@ -3,18 +3,28 @@
 
 static void main(unsigned long bist)
 {
+	unsigned long entry;
+	int boot_mode;
+
 	if (boot_cpu()) {
 		bootblock_northbridge_init();
 		bootblock_southbridge_init();
 		bootblock_cpu_init();
-	}
 
 #if CONFIG_USE_OPTION_TABLE
-	sanitize_cmos();
+		sanitize_cmos();
 #endif
+		boot_mode = do_normal_boot();
+	} else {
 
-	unsigned long entry;
-	if (do_normal_boot())
+		/* Questionable single byte read from CMOS.
+		 * Do not add any other CMOS access in the
+		 * bootblock for AP CPUs.
+		 */
+		boot_mode = last_boot_normal();
+	}
+
+	if (boot_mode)
 		entry = findstage("normal/romstage");
 	else
 		entry = findstage("fallback/romstage");
diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c
index 5d7c611..41f73b4 100644
--- a/src/arch/x86/init/bootblock_simple.c
+++ b/src/arch/x86/init/bootblock_simple.c
@@ -6,11 +6,11 @@ static void main(unsigned long bist)
 		bootblock_northbridge_init();
 		bootblock_southbridge_init();
 		bootblock_cpu_init();
-	}
 
 #if CONFIG_USE_OPTION_TABLE
-	sanitize_cmos();
+		sanitize_cmos();
 #endif
+	}
 
 	const char* target1 = "fallback/romstage";
 	unsigned long entry;


From gerrit at coreboot.org  Mon Dec  5 19:44:28 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Mon, 5 Dec 2011 19:44:28 +0100
Subject: [coreboot] Patch set updated for coreboot: 8cd320c Auto-generate
	bootblock initialisation
References: <Ib1d101cdd68993530c9c7a653ac000a01de52ac2+0@gerrit.coreboot.org>
Message-ID: <Ib1d101cdd68993530c9c7a653ac000a01de52ac2+2@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/473

-gerrit

commit 8cd320ccc59e15d4a4a15a845668356f99a18fb5
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Sun Dec 4 21:35:38 2011 +0200

    Auto-generate bootblock initialisation
    
    The following chip-specific functions were renamed to include
    chip name in the function:
      - bootblock_northbridge_init
      - bootblock_southbridge_init
    
    The following no-operation bootblock.c files were removed:
      - northbridge/amd/agesa/family10/bootblock.c
      - northbridge/amd/agesa/family12/bootblock.c
      - northbridge/amd/agesa/family14/bootblock.c
    
    A new init function called from bootblock is declared as:
      - unsigned long init_mainboard(int bsp_cpu)
    
    For BSP CPU bootblock calls init_mainboard(true). For AP CPUs bootblock
    calls init_mainboard(false). Usually AP CPU has nothing to do here.
    
    By default, build toolchain creates and includes an init_mainboard()
    function in file build/mainboard/x/x/bootblock_autogen.h that executes
    init functions from any bootblock.c files for all chips listed in
    mainboard/devtree.cb.
    
    Alternatively a mainboard/x/x/bootblock.c file is added in the
    bootblock build, if a Kconfig option HAS_MAINBOARD_BOOTBLOCK is set.
    One should copy the auto-generated init_mainboard() to this file,
    and optionally read various bootstrap signals or status bits from
    super-io and southbridge component to gain some control over the
    selection of romstage to boot via the return value.
    
    Samples of such (yet not implemented) controls for boot behaviour:
      - Reset CMOS to defaults on user request (jumper).
      - Use fallback prefix after power-button 4s override.
      - Refuse boot after intruder detection.
      - On remote wakeup, request network boot.
    
    Change-Id: Ib1d101cdd68993530c9c7a653ac000a01de52ac2
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/Kconfig                           |    7 +----
 src/arch/x86/Makefile.inc                      |    9 +++++-
 src/arch/x86/include/bootblock_common.h        |   17 +-------------
 src/arch/x86/init/bootblock_normal.c           |    8 +++---
 src/arch/x86/init/bootblock_simple.c           |   10 ++++----
 src/mainboard/hp/dl165_g6_fam10/Kconfig        |    5 +---
 src/mainboard/hp/dl165_g6_fam10/bootblock.c    |   10 +++++++-
 src/northbridge/amd/agesa/family10/Kconfig     |    3 --
 src/northbridge/amd/agesa/family10/bootblock.c |   29 ------------------------
 src/northbridge/amd/agesa/family12/Kconfig     |    4 ---
 src/northbridge/amd/agesa/family12/bootblock.c |   29 ------------------------
 src/northbridge/amd/agesa/family14/Kconfig     |    4 ---
 src/northbridge/amd/agesa/family14/bootblock.c |   29 ------------------------
 src/northbridge/amd/amdfam10/Kconfig           |    4 ---
 src/northbridge/amd/amdfam10/bootblock.c       |    2 +-
 src/northbridge/amd/amdk8/Kconfig              |    4 ---
 src/northbridge/amd/amdk8/bootblock.c          |    2 +-
 src/southbridge/amd/amd8111/Kconfig            |    4 ---
 src/southbridge/amd/amd8111/bootblock.c        |    2 +-
 src/southbridge/amd/cimx/sb800/Kconfig         |    3 --
 src/southbridge/amd/cimx/sb800/bootblock.c     |    2 +-
 src/southbridge/amd/cimx/sb900/Kconfig         |    3 --
 src/southbridge/amd/cimx/sb900/bootblock.c     |    2 +-
 src/southbridge/amd/sb600/Kconfig              |    3 --
 src/southbridge/amd/sb600/bootblock.c          |    2 +-
 src/southbridge/amd/sb700/Kconfig              |    5 ----
 src/southbridge/amd/sb700/bootblock.c          |    2 +-
 src/southbridge/amd/sb800/Kconfig              |    5 ----
 src/southbridge/amd/sb800/bootblock.c          |    2 +-
 src/southbridge/broadcom/bcm5785/Kconfig       |    4 ---
 src/southbridge/broadcom/bcm5785/bootblock.c   |    2 +-
 src/southbridge/intel/i82371eb/Kconfig         |    5 ----
 src/southbridge/intel/i82371eb/bootblock.c     |    2 +-
 src/southbridge/intel/i82801gx/Kconfig         |    5 ----
 src/southbridge/intel/i82801gx/bootblock.c     |    2 +-
 src/southbridge/nvidia/ck804/Kconfig           |    4 ---
 src/southbridge/nvidia/ck804/bootblock.c       |    2 +-
 src/southbridge/nvidia/mcp55/Kconfig           |    4 ---
 src/southbridge/nvidia/mcp55/bootblock.c       |    2 +-
 src/southbridge/sis/sis966/Kconfig             |    5 +---
 src/southbridge/sis/sis966/bootblock.c         |    2 +-
 src/southbridge/via/vt8237r/Kconfig            |    4 ---
 src/southbridge/via/vt8237r/bootblock.c        |    2 +-
 43 files changed, 45 insertions(+), 211 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index e71d0f3..07ad95f 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -67,8 +67,8 @@ config PC80_SYSTEM
 	bool
 	default y
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-	string
+config HAS_MAINBOARD_BOOTBLOCK
+	def_bool n
 
 config HAVE_CMOS_DEFAULT
 	def_bool n
@@ -77,9 +77,6 @@ config CMOS_DEFAULT_FILE
 	string
 	depends on HAVE_CMOS_DEFAULT
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-
 config BIG_ENDIAN
 	bool
 	default n
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7bba44e..2595595 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -331,11 +331,16 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@
 
-$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H)
+$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h $(objutil)/romcc/romcc $(OPTION_TABLE_H)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \
 		$< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d
-	$(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@
+	$(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) -I$(@D) $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig
+	@printf "    SCONFIG    $(subst $(src)/,,$(<)) (bootblock)\n"
+	mkdir -p $(@D)
+	$(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(@D) -b $(@F)
 
 $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h
index bd19682..69ab22c 100644
--- a/src/arch/x86/include/bootblock_common.h
+++ b/src/arch/x86/include/bootblock_common.h
@@ -1,22 +1,7 @@
 #include <cpu/x86/lapic/boot_cpu.c>
 
-#ifdef CONFIG_BOOTBLOCK_CPU_INIT
-#include CONFIG_BOOTBLOCK_CPU_INIT
-#else
-static void bootblock_cpu_init(void) { }
-#endif
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#else
-static void bootblock_northbridge_init(void) { }
-#endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#else
-static void bootblock_southbridge_init(void) { }
-#endif
-
 #include <arch/cbfs.h>
+#include "bootblock_autogen.h"
 
 #if CONFIG_USE_OPTION_TABLE
 #include <pc80/mc146818rtc.h>
diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c
index f8ae13b..48b4131 100644
--- a/src/arch/x86/init/bootblock_normal.c
+++ b/src/arch/x86/init/bootblock_normal.c
@@ -4,13 +4,13 @@
 static void main(unsigned long bist)
 {
 	unsigned long entry;
+	int bsp_cpu = boot_cpu();
 	int boot_mode;
 
-	if (boot_cpu()) {
-		bootblock_northbridge_init();
-		bootblock_southbridge_init();
-		bootblock_cpu_init();
+	/* Mainboard-specific early init. */
+	init_mainboard(bsp_cpu);
 
+	if (bsp_cpu) {
 #if CONFIG_USE_OPTION_TABLE
 		sanitize_cmos();
 #endif
diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c
index 41f73b4..f4e4bbf 100644
--- a/src/arch/x86/init/bootblock_simple.c
+++ b/src/arch/x86/init/bootblock_simple.c
@@ -2,15 +2,15 @@
 
 static void main(unsigned long bist)
 {
-	if (boot_cpu()) {
-		bootblock_northbridge_init();
-		bootblock_southbridge_init();
-		bootblock_cpu_init();
+	int bsp_cpu = boot_cpu();
+
+	/* Mainboard-specific early init. */
+	init_mainboard(bsp_cpu);
 
 #if CONFIG_USE_OPTION_TABLE
+	if (bsp_cpu)
 		sanitize_cmos();
 #endif
-	}
 
 	const char* target1 = "fallback/romstage";
 	unsigned long entry;
diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig
index e3dbf6b..b8a25d8 100644
--- a/src/mainboard/hp/dl165_g6_fam10/Kconfig
+++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select HAVE_HARD_RESET
+	select HAS_MAINBOARD_BOOTBLOCK
 	select LIFT_BSP_APIC_ID
 	select BOARD_ROMSIZE_KB_1024
 	select RAMINIT_SYSINFO
@@ -91,10 +92,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "mainboard/hp/dl165_g6_fam10/bootblock.c"
-
 config MMCONF_SUPPORT_DEFAULT
 	bool
 	default y
diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
index 2c56c4c..e7c0680 100644
--- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c
+++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
@@ -18,6 +18,9 @@ static inline void shc4307_exit_ext_func_mode(device_t dev)
 #define DBG_DEV  PNP_DEV(SCH4307_CONFIG_PORT, 0x3)
 #define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa)
 
+/* FIXME: This appears to be a super-io initialisation,
+ *        placed in the mainboard directory.
+ */
 void shc4307_init(void)
 {
 	shc4307_enter_ext_func_mode(CMOS_DEV);
@@ -43,6 +46,11 @@ void shc4307_init(void)
 	shc4307_exit_ext_func_mode(CMOS_DEV);
 }
 
-static void bootblock_southbridge_init(void) {
+static unsigned long init_mainboard(int bsp_cpu)
+{
+	if (!bsp_cpu) return 0;
+	init_northbridge_amd_amdfam10();
+	//init_southbridge_broadcom_bcm5785();
 	shc4307_init();
+	return 0;
 }
diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig
index 62a6cd4..0bb16d9 100755
--- a/src/northbridge/amd/agesa/family10/Kconfig
+++ b/src/northbridge/amd/agesa/family10/Kconfig
@@ -41,9 +41,6 @@ config MMCONF_BASE_ADDRESS
 config MMCONF_BUS_NUMBER
 	int
 	default 256
-config BOOTBLOCK_NORTHBRIDGE_INIT
-  string
-  default "northbridge/amd/agesa/family10/bootblock.c"
 endif #NORTHBRIDGE_AMD_AGESA_FAMILY10
 
 source "src/northbridge/amd/agesa/family10/root_complex/Kconfig"
diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c
deleted file mode 100644
index f6ae8be..0000000
--- a/src/northbridge/amd/agesa/family10/bootblock.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-
-static void bootblock_northbridge_init(void) {
-}
diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig
index fc3c436..8ab5de8 100755
--- a/src/northbridge/amd/agesa/family12/Kconfig
+++ b/src/northbridge/amd/agesa/family12/Kconfig
@@ -73,7 +73,3 @@ if DIMM_DDR3
 	endif
 endif
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-  string
-  default "northbridge/amd/agesa/family12/bootblock.c"
-	depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c
deleted file mode 100644
index f6ae8be..0000000
--- a/src/northbridge/amd/agesa/family12/bootblock.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-
-static void bootblock_northbridge_init(void) {
-}
diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig
index 44f93c1..e462153 100644
--- a/src/northbridge/amd/agesa/family14/Kconfig
+++ b/src/northbridge/amd/agesa/family14/Kconfig
@@ -39,8 +39,4 @@ config MMCONF_BUS_NUMBER
 	int
 	default 16
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-  string
-  default "northbridge/amd/agesa/family14/bootblock.c"
-
 endif
diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c
deleted file mode 100644
index f6ae8be..0000000
--- a/src/northbridge/amd/agesa/family14/bootblock.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-
-static void bootblock_northbridge_init(void) {
-}
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 74e0ff4..a1594ad 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -59,10 +59,6 @@ config MMCONF_BUS_NUMBER
 	int
 	default 256
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-        string
-        default "northbridge/amd/amdfam10/bootblock.c"
-
 config SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	bool
 	default n
diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c
index 612004a..328e9ad 100644
--- a/src/northbridge/amd/amdfam10/bootblock.c
+++ b/src/northbridge/amd/amdfam10/bootblock.c
@@ -3,7 +3,7 @@
 #include <device/pci_def.h>
 #include "northbridge/amd/amdfam10/early_ht.c"
 
-static void bootblock_northbridge_init(void) {
+static void init_northbridge_amd_amdfam10(void) {
 	/* Nothing special needs to be done to find bus 0 */
 	/* Allow the HT devices to be found */
 	/* mov bsp to bus 0xff when > 8 nodes */
diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig
index 858041a..418c734 100644
--- a/src/northbridge/amd/amdk8/Kconfig
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -45,10 +45,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-        string
-        default "northbridge/amd/amdk8/bootblock.c"
-
 config SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	bool
 	default n
diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c
index b5395bb..8afd507 100644
--- a/src/northbridge/amd/amdk8/bootblock.c
+++ b/src/northbridge/amd/amdk8/bootblock.c
@@ -3,6 +3,6 @@
 #include <device/pci_def.h>
 #include "northbridge/amd/amdk8/early_ht.c"
 
-static void bootblock_northbridge_init(void) {
+static void init_northbridge_amd_amdk8(void) {
 	enumerate_ht_chain();
 }
diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig
index 83fb8fc..4367017 100644
--- a/src/southbridge/amd/amd8111/Kconfig
+++ b/src/southbridge/amd/amd8111/Kconfig
@@ -21,7 +21,3 @@ config SOUTHBRIDGE_AMD_AMD8111
 	bool
 	select IOAPIC
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/amd8111/bootblock.c"
-	depends on SOUTHBRIDGE_AMD_AMD8111
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
index 3009c0b..d4660de 100644
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ b/src/southbridge/amd/amd8111/bootblock.c
@@ -41,7 +41,7 @@ static void amd8111_enable_rom(void)
 	pci_io_write_config8(dev, 0x43, byte);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_amd8111(void)
 {
 	amd8111_enable_rom();
 }
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 79624e0..fc15c42 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_CIMX_SB800
 	select AMD_SB_CIMX
 
 if SOUTHBRIDGE_AMD_CIMX_SB800
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-        string
-        default "southbridge/amd/cimx/sb800/bootblock.c"
 
 config ENABLE_IDE_COMBINED_MODE
 	bool "Enable SATA IDE combined mode"
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 0a339b0..9e00219 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -104,7 +104,7 @@ static void enable_clocks(void)
 	*acpi_mmio = reg32;
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_cimx_sb800(void)
 {
 	/* Setup the rom access for 2M */
 	enable_rom();
diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
index 253d73f..09edd1b 100755
--- a/src/southbridge/amd/cimx/sb900/Kconfig
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -49,8 +49,5 @@ config ACPI_SCI_IRQ
 	help
 		Set SCI IRQ to 9.
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-        string
-        default "southbridge/amd/cimx/sb900/bootblock.c"
 endif #SOUTHBRIDGE_AMD_CIMX_SB900
 
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index e84743b..f3b53d0 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -90,7 +90,7 @@ static void sb900_enable_rom(void)
   pci_io_write_config16(dev, 0x6c, word);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_cimx_sb900(void)
 {
   /* Setup the rom access for 2M */
   sb900_enable_rom();
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig
index 07028a0..79715d7 100644
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -23,9 +23,6 @@ config SOUTHBRIDGE_AMD_SB600
 	select HAVE_USBDEBUG
 
 if SOUTHBRIDGE_AMD_SB600
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/sb600/bootblock.c"
 
 config EHCI_BAR
 	hex
diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c
index 7007622..db9052e 100644
--- a/src/southbridge/amd/sb600/bootblock.c
+++ b/src/southbridge/amd/sb600/bootblock.c
@@ -64,7 +64,7 @@ static void sb600_enable_rom(void)
 	pci_write_config16(dev, 0x6e, 0xffff);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_sb600(void)
 {
 	sb600_enable_rom();
 }
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index 98b8e2a..02ffdca 100644
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -27,11 +27,6 @@ config SOUTHBRIDGE_AMD_SP5100
 	select IOAPIC
 	select HAVE_USBDEBUG
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/sb700/bootblock.c"
-	depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100)
-
 config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
 	bool
 	default n
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index 377bffc..a2a2653 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -64,7 +64,7 @@ static void sb700_enable_rom(void)
 	pci_write_config16(dev, 0x6e, 0xffff);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_sb700(void)
 {
 	sb700_enable_rom();
 }
diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig
index 67cb8ef..075e454 100644
--- a/src/southbridge/amd/sb800/Kconfig
+++ b/src/southbridge/amd/sb800/Kconfig
@@ -22,11 +22,6 @@ config SOUTHBRIDGE_AMD_SB800
 	select IOAPIC
 	select HAVE_USBDEBUG
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/sb800/bootblock.c"
-	depends on SOUTHBRIDGE_AMD_SB800
-
 config SOUTHBRIDGE_AMD_SB800_SKIP_ISA_DMA_INIT
 	bool
 	default n
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 18eae24..9f7c2c2 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -62,7 +62,7 @@ static void sb800_enable_rom(void)
 	pci_write_config16(dev, 0x6e, 0xffff);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_sb800(void)
 {
 	sb800_enable_rom();
 }
diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig
index d72afd8..286c19b 100644
--- a/src/southbridge/broadcom/bcm5785/Kconfig
+++ b/src/southbridge/broadcom/bcm5785/Kconfig
@@ -2,7 +2,3 @@ config SOUTHBRIDGE_BROADCOM_BCM5785
 	bool
 	select HAVE_HARD_RESET
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/broadcom/bcm5785/bootblock.c"
-	depends on SOUTHBRIDGE_BROADCOM_BCM5785
diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
index cadda53..e1e5f31 100644
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ b/src/southbridge/broadcom/bcm5785/bootblock.c
@@ -38,7 +38,7 @@ static void bcm5785_enable_rom(void)
 	pci_write_config8(dev, 0x41, byte);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_broadcom_bcm5785(void)
 {
 	bcm5785_enable_rom();
 }
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
index 7e5109a..a5c5eb8 100644
--- a/src/southbridge/intel/i82371eb/Kconfig
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -2,8 +2,3 @@ config SOUTHBRIDGE_INTEL_I82371EB
 	bool
 	select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/intel/i82371eb/bootblock.c"
-	depends on SOUTHBRIDGE_INTEL_I82371EB
-
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index 07fa0bc..a875723 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -48,7 +48,7 @@ static void i82371eb_enable_rom(void)
 	pci_write_config16(dev, XBCS, reg16);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_intel_i82371eb(void)
 {
 	i82371eb_enable_rom();
 }
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index a6bd202..f63c12f 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -38,10 +38,5 @@ config USBDEBUG_DEFAULT_PORT
 	int
 	default 1 
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-        string
-	default "southbridge/intel/i82801gx/bootblock.c"
-	depends on SOUTHBRIDGE_INTEL_I82801GX
-
 endif
 
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 39b0bd4..a0f73b3 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -33,7 +33,7 @@ static void enable_spi_prefetch(void)
         pci_write_config8(dev, 0xdc, reg8);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_intel_i82801gx(void)
 {
         enable_spi_prefetch();
 }
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 88ab7ff..01cff02 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -6,10 +6,6 @@ config SOUTHBRIDGE_NVIDIA_CK804
 
 if SOUTHBRIDGE_NVIDIA_CK804
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/nvidia/ck804/bootblock.c"
-
 config ID_SECTION_OFFSET
 	hex
 	default 0x80
diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c
index 29c10c8..3175606 100644
--- a/src/southbridge/nvidia/ck804/bootblock.c
+++ b/src/southbridge/nvidia/ck804/bootblock.c
@@ -42,7 +42,7 @@ static void ck804_enable_rom(void)
 	pci_write_config8(addr, 0x88, byte);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_nvidia_ck804(void)
 {
 	ck804_enable_rom();
 }
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index adca4bd..78a1f25 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -5,10 +5,6 @@ config SOUTHBRIDGE_NVIDIA_MCP55
 
 if SOUTHBRIDGE_NVIDIA_MCP55
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/nvidia/mcp55/bootblock.c"
-
 config ID_SECTION_OFFSET
 	hex
 	default 0x80
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c
index affb025..6fb6dbb 100644
--- a/src/southbridge/nvidia/mcp55/bootblock.c
+++ b/src/southbridge/nvidia/mcp55/bootblock.c
@@ -53,7 +53,7 @@ static void mcp55_enable_rom(void)
 	pci_write_config16(addr, 0x90, word);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_nvidia_mcp55(void)
 {
 	mcp55_enable_rom();
 }
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 909a741..da089d3 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -3,10 +3,6 @@ config SOUTHBRIDGE_SIS_SIS966
 	select IOAPIC
 	select HAVE_USBDEBUG
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
-
 config ID_SECTION_OFFSET
 	hex
 	default 0x80 if SOUTHBRIDGE_SIS_SIS966
@@ -18,3 +14,4 @@ config EHCI_BAR
 config EHCI_DEBUG_OFFSET
 	hex
 	default 0x98 if SOUTHBRIDGE_SIS_SIS966
+
diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c
index 1ff3cda..45ab81b 100644
--- a/src/southbridge/sis/sis966/bootblock.c
+++ b/src/southbridge/sis/sis966/bootblock.c
@@ -41,7 +41,7 @@ static void sis966_enable_rom(void)
 	pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11);
 }
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_sis_sis966(void)
 {
 	sis966_enable_rom();
 }
diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig
index d0a6deb..9aa1b97 100644
--- a/src/southbridge/via/vt8237r/Kconfig
+++ b/src/southbridge/via/vt8237r/Kconfig
@@ -27,7 +27,3 @@ config EPIA_VT8237R_INIT
 	default n
 	depends on SOUTHBRIDGE_VIA_VT8237R
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/via/vt8237r/bootblock.c"
-	depends on SOUTHBRIDGE_VIA_VT8237R
diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c
index 8df37aa..0ca0533 100644
--- a/src/southbridge/via/vt8237r/bootblock.c
+++ b/src/southbridge/via/vt8237r/bootblock.c
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <device/pci_ids.h>
 
-static void bootblock_southbridge_init(void)
+static void init_southbridge_via_vt8237r(void)
 {
 	device_t dev;
 	/* don't walk other busses, HT is not enabled */


From eldmannen at gmail.com  Sat Dec  3 15:46:01 2011
From: eldmannen at gmail.com (Fred .)
Date: Sat, 3 Dec 2011 15:46:01 +0100
Subject: [coreboot] NIST BIOS Protection Guidelines
Message-ID: <CAJgfmqWEG92tsMJeVy1om4evUeyCakbgWxXo_9F6comN7xXSrw@mail.gmail.com>

http://csrc.nist.gov/publications/nistpubs/800-147/NIST-SP800-147-April2011.pdf


From gerrit at coreboot.org  Tue Dec  6 06:20:38 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 6 Dec 2011 06:20:38 +0100
Subject: [coreboot] Patch merged into coreboot/master: cb4b944 Fix AMD 8132
	and 8151 southbridge builds
References: <I03acdfcc3f3440bd32e81a9a696159903bbbcb50+0@gerrit.coreboot.org>
Message-ID: <E1RXnSI-0004Ou-29@ra.coresystems.de>

the following patch was just integrated into master:
commit cb4b9445f0cfa3089357b4ae7393352e962ddc31
Author: Ky??sti M??lkki <kyosti.malkki at gmail.com>
Date:   Sat Dec 3 11:30:26 2011 +0200

    Fix AMD 8132 and 8151 southbridge builds
    
    Untested, changes ramstage build for boards:
      supermicro/h8qme_fam10
      amd/serengeti_cheetah
      amd/serengeti_cheetah_fam10
    
    AMD 8132 was not built for any mainboard due to a typo.
    
    AMD Serengeti Cheetah:
      Chip 8151 is referenced in devicetree.cb but was not built.
    
    AMD Serengeti Cheetah Family10:
      There are indications the board has 8151, but it is not listed
      in the devicetree.cb. The 8151 chip is not added in the build.
    
    Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
    Signed-off-by: Ky??sti M??lkki <kyosti.malkki at gmail.com>

Build-Tested: build bot (Jenkins) at Sat Dec  3 10:44:09 2011, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Tue Dec  6 06:20:26 2011, giving +2
See http://review.coreboot.org/471 for details.

-gerrit


From gerrit at coreboot.org  Tue Dec  6 15:12:01 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Tue, 6 Dec 2011 15:12:01 +0100
Subject: [coreboot] Patch set updated for coreboot: 166bbb0 Add support for
	RAM-less multi-processor init
References: <I82e4edbf208c9ba863f51a64e50cd92871c528ef+0@gerrit.coreboot.org>
Message-ID: <I82e4edbf208c9ba863f51a64e50cd92871c528ef+2@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454

-gerrit

commit 166bbb0ae0b1b378b1a10b87c586f4bf4c007cfa
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Tue Dec 6 15:53:38 2011 +0200

    Add support for RAM-less multi-processor init
    
    For a hyper-threading processor, enabling cache requires that both the
    BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram
    implementation, partial multi-processor initialisation precedes
    raminit and AP CPUs' 16bit entry must be run from ROM.
    
    The AP CPU can only start execute real-mode code at a 4kB aligned
    address below 1MB. The protected mode entry code for AP is identical
    with the BSP code, which is already located at the top of bootblock.
    
    This patch takes the simplest approach and aligns the bootblock
    16 bit entry at highest possible 4kB boundary below 1MB.
    
    Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/init/ldscript_failover.lb |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb
index 83e5eb3..5340c0f 100644
--- a/src/arch/x86/init/ldscript_failover.lb
+++ b/src/arch/x86/init/ldscript_failover.lb
@@ -29,17 +29,18 @@ MEMORY {
 TARGET(binary)
 SECTIONS
 {
-	/* Align .rom to next 4 byte boundary so no pad byte appears
-	 * between _rom and _start.
+	/* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
+	 * with Startup IPI message without RAM.
 	 */
 	.bogus ROMLOC_MIN : {
-		. = ALIGN(4);
+		. = ALIGN(4096);
 		ROMLOC = .;
 	} >rom = 0xff
 
 	/* This section might be better named .setup */
 	.rom ROMLOC : {
 		_rom = .;
+		ap_sipi_vector = .;
 		*(.rom.text);
 		*(.rom.data);
 		*(.rom.data.*);
@@ -51,7 +52,7 @@ SECTIONS
 	 * may cause the total size of a section to change when the start
 	 * address gets applied.
 	 */
-	ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
+	ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096;
 
 	/DISCARD/ : {
 		*(.comment)


From gerrit at coreboot.org  Tue Dec  6 15:12:01 2011
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Tue, 6 Dec 2011 15:12:01 +0100
Subject: [coreboot] Patch set updated for coreboot: 9716e82 Fix ldscript for
	bootblock .rom section
References: <Ic2a43981836a0873b50abecfcad2def7b6586a5d+0@gerrit.coreboot.org>
Message-ID: <Ic2a43981836a0873b50abecfcad2def7b6586a5d+2@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/453

-gerrit

commit 9716e822a4a7442dcb781aa9b2fda2a35b1d531f
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Wed Nov 23 16:33:12 2011 +0200

    Fix ldscript for bootblock .rom section
    
    Allocation size for the section was miscalculated, so the section
    did not honour its upper-bound address.
    
    Also align the section start to 4 bytes, so it starts with code
    instead of pad bytes.
    
    Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/init/ldscript_failover.lb |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb
index 7e48dc1..83e5eb3 100644
--- a/src/arch/x86/init/ldscript_failover.lb
+++ b/src/arch/x86/init/ldscript_failover.lb
@@ -29,6 +29,14 @@ MEMORY {
 TARGET(binary)
 SECTIONS
 {
+	/* Align .rom to next 4 byte boundary so no pad byte appears
+	 * between _rom and _start.
+	 */
+	.bogus ROMLOC_MIN : {
+		. = ALIGN(4);
+		ROMLOC = .;
+	} >rom = 0xff
+
 	/* This section might be better named .setup */
 	.rom ROMLOC : {
 		_rom = .;
@@ -39,7 +47,11 @@ SECTIONS
 		_erom = .;
 	} >rom = 0xff
 
-	ROMLOC = 0xffffff00 - (_erom - _rom) + 1;
+	/* Allocation reserves extra 16 bytes here. Alignment requirements
+	 * may cause the total size of a section to change when the start
+	 * address gets applied.
+	 */
+	ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
 
 	/DISCARD/ : {
 		*(.comment)


From gerrit at coreboot.org  Wed Dec  7 08:59:26 2011
From: gerrit at coreboot.org (Alec Ari (neotheuser@ymail.com))
Date: Wed, 7 Dec 2011 08:59:26 +0100
Subject: [coreboot] New patch to review for coreboot: b434f9c Change DSDT
	Table ID for M4A785T-M board
References: <I43ee024222cf04d03685ffaee616971100cc9e6c+0@gerrit.coreboot.org>
Message-ID: <I43ee024222cf04d03685ffaee616971100cc9e6c+1@gerrit.coreboot.org>

Alec Ari (neotheuser at ymail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/474

-gerrit

commit b434f9ccda0c7756586ddb4a6acc22d598a071e9
Author: Alec Ari <neotheuser at ymail.com>
Date:   Wed Dec 7 01:50:52 2011 -0600

    Change DSDT Table ID for M4A785T-M board
    
    Change the DSDT Table ID for M4A785T-M
    from M4A785-M to M4A785T-M.
    
    This fixes a small copypasta.
    
    Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
    Signed-off-by: Alec Ari <neotheuser at ymail.com>
---
 src/mainboard/asus/m4a785t-m/dsdt.asl |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl
index 34ddd3a..0f06084 100644
--- a/src/mainboard/asus/m4a785t-m/dsdt.asl
+++ b/src/mainboard/asus/m4a785t-m/dsdt.asl
@@ -23,7 +23,7 @@ DefinitionBlock (
 	"DSDT",                 /* Signature */
 	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
 	"ASUS   ",               /* OEMID */
-	"M4A785-M ",	     /* TABLE ID */
+	"M4A785T-M ",	     /* TABLE ID */
 	0x00010001	/* OEM Revision */
 	)
 {	/* Start of ASL file */


From gerrit at coreboot.org  Wed Dec  7 23:36:35 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Wed, 7 Dec 2011 23:36:35 +0100
Subject: [coreboot] New patch to review for coreboot: c18ecfd Lenovo
	X60/T60: add first_battery setting
References: <Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8+0@gerrit.coreboot.org>
Message-ID: <Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/475

-gerrit

commit c18ecfd8b74b1a38bee90270e36630f9fad74b98
Author: Sven Schnelle <svens at stackframe.org>
Date:   Wed Dec 7 14:30:58 2011 -0800

    Lenovo X60/T60: add first_battery setting
    
    The EC allows to select the order in which batteries are (dis)charged.
    Make this setting available to the user.
    
    Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/ec/lenovo/h8/h8.c                |    9 ++++++++-
 src/mainboard/lenovo/t60/cmos.layout |    4 +++-
 src/mainboard/lenovo/x60/cmos.layout |    3 +++
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index f81a39c..f20cd38 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -104,7 +104,7 @@ int h8_ultrabay_device_present(void)
 static void h8_enable(device_t dev)
 {
 	struct ec_lenovo_h8_config *conf = dev->chip_info;
-	u8 val;
+	u8 val, tmp;
 
 	h8_log_ec_version();
 
@@ -142,6 +142,13 @@ static void h8_enable(device_t dev)
 	if (!get_option(&val, "volume"))
 		ec_write(H8_VOLUME_CONTROL, val);
 
+
+	if (!get_option(&val, "first_battery")) {
+		tmp = ec_read(H8_CONFIG3);
+		tmp &= ~(1 << 4);
+		tmp |= (val & 1)<< 4;
+		ec_write(H8_CONFIG3, tmp);
+	}
 	h8_set_audio_mute(0);
 }
 
diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout
index a946b4b..8d9dce4 100644
--- a/src/mainboard/lenovo/t60/cmos.layout
+++ b/src/mainboard/lenovo/t60/cmos.layout
@@ -109,6 +109,7 @@ entries
 
 1060         1       e       1        touchpad
 1064         8       h       0        volume
+1072         1       e       9        first_battery
 # -----------------------------------------------------------------
 
 enumerations
@@ -142,7 +143,8 @@ enumerations
 7     2     Keep
 8     0     No
 8     1     Yes
-
+9     0	    Secondary
+9     1	    Primary
 # -----------------------------------------------------------------
 checksums
 
diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout
index a157513..cae70cb 100644
--- a/src/mainboard/lenovo/x60/cmos.layout
+++ b/src/mainboard/lenovo/x60/cmos.layout
@@ -109,6 +109,7 @@ entries
 
 1064         8       h       0        volume
 1072         8       h       0        tft_brightness
+1080         1       e       9        first_battery
 # -----------------------------------------------------------------
 
 enumerations
@@ -142,6 +143,8 @@ enumerations
 7     2     Keep
 8     0     No
 8     1     Yes
+9     0	    Secondary
+9     1	    Primary
 
 # -----------------------------------------------------------------
 checksums


From gerrit at coreboot.org  Wed Dec  7 23:58:07 2011
From: gerrit at coreboot.org (Alec Ari (neotheuser@ymail.com))
Date: Wed, 7 Dec 2011 23:58:07 +0100
Subject: [coreboot] New patch to review for coreboot: 63a42ee Add support
	for MA785GM-US2H
References: <I58a7083a023ebf7373b6ded2e9f0adda7ab76dea+0@gerrit.coreboot.org>
Message-ID: <I58a7083a023ebf7373b6ded2e9f0adda7ab76dea+1@gerrit.coreboot.org>

Alec Ari (neotheuser at ymail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/476

-gerrit

commit 63a42eea39e797394f2b6bf391bfd2052749689e
Author: Alec Ari <neotheuser at ymail.com>
Date:   Wed Dec 7 16:20:03 2011 -0600

    Add support for MA785GM-US2H
    
    This patch adds coreboot support for the
    GIGABYTE MA785GM-US2H board.
    
    AHCI SATA controller does not work in SeaBIOS
    ACPI does not function properly.
    
    The issues with this board could be within SeaBIOS
    and not a direct issue with the coreboot port, as no other
    payloads have been tested, such as FILO.
    
    This patch has not been tested by myself in a long time,
    however a person with the same board had the problems I did.
    
    Change-Id: I58a7083a023ebf7373b6ded2e9f0adda7ab76dea
    Signed-off-by: Alec Ari <neotheuser at ymail.com>
---
 src/mainboard/gigabyte/Kconfig                  |    3 +
 src/mainboard/gigabyte/ma785gm/Kconfig          |   86 ++
 src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl |   75 +
 src/mainboard/gigabyte/ma785gm/acpi/ide.asl     |  244 +++
 src/mainboard/gigabyte/ma785gm/acpi/routing.asl |  300 ++++
 src/mainboard/gigabyte/ma785gm/acpi/sata.asl    |  149 ++
 src/mainboard/gigabyte/ma785gm/acpi/usb.asl     |  161 ++
 src/mainboard/gigabyte/ma785gm/acpi_tables.c    |  270 ++++
 src/mainboard/gigabyte/ma785gm/chip.h           |   23 +
 src/mainboard/gigabyte/ma785gm/cmos.layout      |   98 ++
 src/mainboard/gigabyte/ma785gm/devicetree.cb    |  115 ++
 src/mainboard/gigabyte/ma785gm/dsdt.asl         | 1850 +++++++++++++++++++++++
 src/mainboard/gigabyte/ma785gm/get_bus_conf.c   |  116 ++
 src/mainboard/gigabyte/ma785gm/irq_tables.c     |  112 ++
 src/mainboard/gigabyte/ma785gm/mainboard.c      |  317 ++++
 src/mainboard/gigabyte/ma785gm/mb_sysconf.h     |   45 +
 src/mainboard/gigabyte/ma785gm/mptable.c        |  171 +++
 src/mainboard/gigabyte/ma785gm/resourcemap.c    |  281 ++++
 src/mainboard/gigabyte/ma785gm/romstage.c       |  256 ++++
 19 files changed, 4672 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig
index 813acef..45de91a 100644
--- a/src/mainboard/gigabyte/Kconfig
+++ b/src/mainboard/gigabyte/Kconfig
@@ -31,6 +31,8 @@ config BOARD_GIGABYTE_M57SLI
 	bool "GA-M57SLI-S4"
 config BOARD_GIGABYTE_MA785GMT
 	bool "GA-MA785GMT-UD2H"
+config BOARD_GIGABYTE_MA785GM
+        bool "GA-MA785GM-US2H"
 config BOARD_GIGABYTE_MA78GM
 	bool "GA-MA78GM-US2H"
 
@@ -41,6 +43,7 @@ source "src/mainboard/gigabyte/ga-6bxc/Kconfig"
 source "src/mainboard/gigabyte/ga-6bxe/Kconfig"
 source "src/mainboard/gigabyte/m57sli/Kconfig"
 source "src/mainboard/gigabyte/ma785gmt/Kconfig"
+source "src/mainboard/gigabyte/ma785gm/Kconfig"
 source "src/mainboard/gigabyte/ma78gm/Kconfig"
 
 config MAINBOARD_VENDOR
diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig
new file mode 100644
index 0000000..1357104
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/Kconfig
@@ -0,0 +1,86 @@
+if BOARD_GIGABYTE_MA785GM
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_SOCKET_AM3
+	select DIMM_DDR2
+	select DIMM_REGISTERED
+	select NORTHBRIDGE_AMD_AMDFAM10
+	select SOUTHBRIDGE_AMD_RS780
+	select SOUTHBRIDGE_AMD_SB700
+	select SUPERIO_ITE_IT8718F
+	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_HARD_RESET
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select LIFT_BSP_APIC_ID
+	select SERIAL_CPU_INIT
+	select AMDMCT
+	select HAVE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_1024
+	select ENABLE_APIC_EXT_ID
+	select GFXUMA
+	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
+
+config MAINBOARD_DIR
+	string
+	default gigabyte/ma785gm
+
+config APIC_ID_OFFSET
+	hex
+	default 0x0
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "GA-MA785GM-US2H"
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+
+config MEM_TRAIN_SEQ
+	int
+	default 2
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x1
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config AMD_UCODE_PATCH_FILE
+	string
+	default "mc_patch_010000b6.h"
+
+config RAMTOP
+	hex
+	default 0x2000000
+
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+config RAMBASE
+	hex
+	default 0x200000
+
+endif # BOARD_GIGABYTE_MA785GM
diff --git a/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl b/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl
new file mode 100644
index 0000000..6a1b002
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+	}
+*/
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	/* Get from AMI BIOS. */
+	Name(_PSS, Package(){
+		Package ()
+		{
+		    0x00000AF0,
+		    0x0000BF81,
+		    0x00000002,
+		    0x00000002,
+		    0x00000000,
+		    0x00000000
+		},
+
+		Package ()
+		{
+		    0x00000578,
+		    0x000076F2,
+		    0x00000002,
+		    0x00000002,
+		    0x00000001,
+		    0x00000001
+		}
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}
diff --git a/src/mainboard/gigabyte/ma785gm/acpi/ide.asl b/src/mainboard/gigabyte/ma785gm/acpi/ide.asl
new file mode 100644
index 0000000..6ea2b09
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			#include "ide.asl"
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}
diff --git a/src/mainboard/gigabyte/ma785gm/acpi/routing.asl b/src/mainboard/gigabyte/ma785gm/acpi/routing.asl
new file mode 100644
index 0000000..ad51815
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi/routing.asl
@@ -0,0 +1,300 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "routing.asl"
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
+		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
+		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
+		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 1, INTA, 0 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
+		Package(){0x0012FFFF, 0, INTA, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+		Package(){0x0013FFFF, 0, INTA, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTA, 0 },
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Package(){0x0001FFFF, 0, 0, 18 }, */
+		/* package(){0x0001FFFF, 1, 0, 19 }, */
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		/* Package(){0x0002FFFF, 1, 0, 19 }, */
+		/* Package(){0x0002FFFF, 2, 0, 16 }, */
+		/* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		/* Package(){0x0004FFFF, 1, 0, 17 }, */
+		/* Package(){0x0004FFFF, 2, 0, 18 }, */
+		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, 0, 17 }, */
+		/* Package(){0x0005FFFF, 1, 0, 18 }, */
+		/* Package(){0x0005FFFF, 2, 0, 19 }, */
+		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		/* Package(){0x0006FFFF, 0, 0, 18 }, */
+		/* Package(){0x0006FFFF, 1, 0, 19 }, */
+		/* Package(){0x0006FFFF, 2, 0, 16 }, */
+		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		/* Package(){0x0007FFFF, 0, 0, 19 }, */
+		/* Package(){0x0007FFFF, 1, 0, 16 }, */
+		/* Package(){0x0007FFFF, 2, 0, 17 }, */
+		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+
+		/* Bus 0, Dev 9 - PCIe Bridge for network card */
+		Package(){0x0009FFFF, 0, 0, 17 },
+		/* Package(){0x0009FFFF, 1, 0, 16 }, */
+		/* Package(){0x0009FFFF, 2, 0, 17 }, */
+		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		/* Bus 0, Dev A - PCIe Bridge for network card */
+		Package(){0x000AFFFF, 0, 0, 18 },
+		/* Package(){0x000AFFFF, 1, 0, 16 }, */
+		/* Package(){0x000AFFFF, 2, 0, 17 }, */
+		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, 0, 22 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
+		Package(){0x0012FFFF, 0, 0, 16 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 19 },
+		Package(){0x0014FFFF, 0, 0, 16 },
+		/* Package(){0x00130004, 2, 0, 18 }, */
+		/* Package(){0x00130005, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Package(){0x00140004, 2, 0, 18 }, */
+		/* Package(){0x00140004, 3, 0, 19 }, */
+		/* Package(){0x00140005, 1, 0, 17 }, */
+		/* Package(){0x00140006, 1, 0, 17 }, */
+	})
+
+	Name(PR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, INTA, 0 },
+		Package(){0x0005FFFF, 1, INTB, 0 },
+		Package(){0x0005FFFF, 2, INTC, 0 },
+		Package(){0x0005FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, 0, 18 },
+		Package(){0x0005FFFF, 1, 0, 19 },
+		/* Package(){0x0005FFFF, 2, 0, 20 }, */
+		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+	Name(PS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+	Name(PSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+		Package(){0x0006FFFF, 0, 0, 0x15 },
+		Package(){0x0006FFFF, 1, 0, 0x16 },
+		Package(){0x0006FFFF, 2, 0, 0x17 },
+		Package(){0x0006FFFF, 3, 0, 0x14 },
+		Package(){0x0007FFFF, 0, 0, 0x16 },
+		Package(){0x0007FFFF, 1, 0, 0x17 },
+		Package(){0x0007FFFF, 2, 0, 0x14 },
+		Package(){0x0007FFFF, 3, 0, 0x15 },
+	})
+}
diff --git a/src/mainboard/gigabyte/ma785gm/acpi/sata.asl b/src/mainboard/gigabyte/ma785gm/acpi/sata.asl
new file mode 100644
index 0000000..b5e6fc5
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00110000)
+			#include "sata.asl"
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}
diff --git a/src/mainboard/gigabyte/ma785gm/acpi/usb.asl b/src/mainboard/gigabyte/ma785gm/acpi/usb.asl
new file mode 100644
index 0000000..203e0ad
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi/usb.asl
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "usb.asl"
+	}
+*/
+Method(UCOC, 0) {
+	Sleep(20)
+    	Store(0x13,CMTI)
+	Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+	Scope (\_GPE) {
+		Method (_L13) {
+			UCOC()
+			if(LEqual(GPB0,PLC0)) {
+				Not(PLC0,PLC0)
+				Store(PLC0, \_SB.PT0D)
+			}
+		}
+	}
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+	Scope (\_GPE) {
+		Method (_L14) {
+			UCOC()
+			if (LEqual(GPB1,PLC1)) {
+				Not(PLC1,PLC1)
+				Store(PLC1, \_SB.PT1D)
+			}
+		}
+	}
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+	Scope (\_GPE) {
+		Method (_L15) {
+			UCOC()
+			if (LEqual(GPB2,PLC2)) {
+				Not(PLC2,PLC2)
+				Store(PLC2, \_SB.PT2D)
+			}
+		}
+	}
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+	Scope (\_GPE) {
+		Method (_L16) {
+			UCOC()
+			if (LEqual(GPB3,PLC3)) {
+				Not(PLC3,PLC3)
+				Store(PLC3, \_SB.PT3D)
+			}
+		}
+	}
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+	Scope (\_GPE) {
+		Method (_L19) {
+			UCOC()
+			if (LEqual(GPB4,PLC4)) {
+				Not(PLC4,PLC4)
+				Store(PLC4, \_SB.PT4D)
+			}
+		}
+	}
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+	Scope (\_GPE) {
+		Method (_L1A) {
+			UCOC()
+			if (LEqual(GPB5,PLC5)) {
+				Not(PLC5,PLC5)
+				Store(PLC5, \_SB.PT5D)
+			}
+		}
+	}
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1C) { */
+		Method (_L06) {
+			UCOC()
+			if (LEqual(GPB6,PLC6)) {
+				Not(PLC6,PLC6)
+				Store(PLC6, \_SB.PT6D)
+			}
+		}
+	}
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ 	Scope (\_GPE) {
+		/* Method (_L1D) { */
+		Method (_L07) {
+			UCOC()
+			if (LEqual(GPB7,PLC7)) {
+				Not(PLC7,PLC7)
+				Store(PLC7, \_SB.PT7D)
+			}
+		}
+	}
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+	Scope (\_GPE) {
+		Method (_L17) {
+			if (LEqual(G8IS,PLC8)) {
+				Not(PLC8,PLC8)
+				Store(PLC8, \_SB.PT8D)
+			}
+		}
+	}
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+	Scope (\_GPE) {
+		Method (_L0E) {
+			if (LEqual(G9IS,0)) {
+			Store(1,\_SB.PT9D)
+			}
+		}
+	}
+}
diff --git a/src/mainboard/gigabyte/ma785gm/acpi_tables.c b/src/mainboard/gigabyte/ma785gm/acpi_tables.c
new file mode 100644
index 0000000..85de50b
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi_tables.c
@@ -0,0 +1,270 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+extern const unsigned char AmlCode_ssdt2[];
+extern const unsigned char AmlCode_ssdt3[];
+extern const unsigned char AmlCode_ssdt4[];
+extern const unsigned char AmlCode_ssdt5[];
+#endif
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB700 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+					   IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+	acpi_header_t *ssdtx;
+	void *p;
+	int i;
+#endif
+
+	get_bus_conf();	/* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+
+	/* SLIT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current += slit->header.length;
+	acpi_add_table(rsdp, slit);
+
+	/* SSDT */
+	current	  = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)current;
+	memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+	current += ssdt->length;
+	memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+	//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
+	update_ssdt((void*)ssdt);
+	/* recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	current = acpi_add_ssdt_pstates(rsdp, current);
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+
+	/* same htio, but different position? We may have to copy,
+	change HCIN, and recalculate the checknum and add_table */
+
+	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
+		if((sysconf.pci1234[i] & 1) != 1 ) continue;
+		u8 c;
+		if (i < 7) {
+			c = (u8) ('4' + i - 1);
+		} else {
+			c = (u8) ('A' + i - 1 - 6);
+		}
+		current	  = ( current + 0x07) & -0x08;
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
+		ssdtx = (acpi_header_t *)current;
+		switch (sysconf.hcid[i]) {
+		case 1:
+			p = &AmlCode_ssdt2;
+			break;
+		case 2:
+			p = &AmlCode_ssdt3;
+			break;
+		case 3:	/* 8131 */
+			p = &AmlCode_ssdt4;
+			break;
+		default:
+			/* HTX no io apic */
+			p = &AmlCode_ssdt5;
+			break;
+		}
+		memcpy(ssdtx, p, sizeof(acpi_header_t));
+		current += ssdtx->length;
+		memcpy(ssdtx, p, ssdtx->length);
+		update_ssdtx((void *)ssdtx, i);
+		ssdtx->checksum = 0;
+		ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
+		acpi_add_table(rsdp, ssdtx);
+	}
+#endif
+
+	/* DSDT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FADT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+#if DUMP_ACPI_TABLES == 1
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
+
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
+
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/gigabyte/ma785gm/chip.h b/src/mainboard/gigabyte/ma785gm/chip.h
new file mode 100644
index 0000000..70102aa
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/gigabyte/ma785gm/cmos.layout b/src/mainboard/gigabyte/ma785gm/cmos.layout
new file mode 100644
index 0000000..53fdef5
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/cmos.layout
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/gigabyte/ma785gm/devicetree.cb b/src/mainboard/gigabyte/ma785gm/devicetree.cb
new file mode 100644
index 0000000..55229ad
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/devicetree.cb
@@ -0,0 +1,115 @@
+# sample config for gigabyte/ma785gm
+chip northbridge/amd/amdfam10/root_complex
+	device lapic_cluster 0 on
+		chip cpu/amd/socket_AM3  #L1 and DDR2
+			 device lapic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
+		chip northbridge/amd/amdfam10
+			device pci 18.0 on #  northbridge
+				chip southbridge/amd/rs780
+					device pci 0.0 on end # HT  	0x9601
+					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
+					device pci 3.0 on end # PCIE P2P bridge	0x960b
+					device pci 4.0 on end # PCIE P2P bridge 0x9604
+					device pci 5.0 off end # PCIE P2P bridge 0x9605
+					device pci 6.0 off end # PCIE P2P bridge 0x9606
+					device pci 7.0 off end # PCIE P2P bridge 0x9607
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					device pci 9.0 off end #
+					device pci a.0 on end # PCIE P2P bridge 0x9609
+					register "gppsb_configuration" = "1"   # Configuration B
+					register "gpp_configuration" = "3"   # Configuration D default
+					register "port_enable" = "0x6fc"
+					register "gfx_dev2_dev3" = "1"
+					register "gfx_dual_slot" = "2"
+
+					register "gfx_lane_reversal" = "0"
+					register "gfx_tmds" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+				end
+				chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB
+					device pci 12.1 on end # USB
+					device pci 12.2 on end # USB
+					device pci 13.0 on end # USB
+					device pci 13.1 on end # USB
+					device pci 13.2 on end # USB
+	 				device pci 14.0 on # SM
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x439c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on # LPC	0x439d
+						chip superio/ite/it8718f
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.2 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.4 off end #  EC
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.6 on #  Mouse
+								irq 0x70 = 12
+							end
+							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
+							end
+							device pnp 2e.8 off #  MIDI
+								io 0x60 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.9 off #  GAME
+								io 0x60 = 0x220
+							end
+							device pnp 2e.a off end #  CIR
+						end	#superio/ite/it8718f
+					end		#LPC
+					device pci 14.4 on end # PCI 0x4384
+					device pci 14.5 on end # USB 2
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+				end	#southbridge/amd/sb700
+			end #  device pci 18.0
+
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+		end
+	end #pci_domain
+	#for node 32 to node 63
+end
diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl
new file mode 100644
index 0000000..32c04ec
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl
@@ -0,0 +1,1850 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",           /* Output filename */
+	"DSDT",                 /* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"GIGA  ",               /* OEMID */
+	"MA785GM-US2H",	     /* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include "../../../arch/x86/acpi/debug.asl" */		/* Include global debug methods if needed */
+
+	/* Data to be patched by the BIOS during POST */
+	/* FIXME the patching is not done yet! */
+	/* Memory related values */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+	/* USB overcurrent mapping pins.   */
+	Name(UOM0, 0)
+	Name(UOM1, 2)
+	Name(UOM2, 0)
+	Name(UOM3, 7)
+	Name(UOM4, 2)
+	Name(UOM5, 2)
+	Name(UOM6, 6)
+	Name(UOM7, 2)
+	Name(UOM8, 6)
+	Name(UOM9, 6)
+
+	/* Some global data */
+	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones)	/* Assume nothing */
+	Name(PMOD, One)	/* Assume APIC */
+
+	/*
+	 * Processor Object
+	 *
+	 */
+	Scope (\_PR) {		/* define processor scope */
+		Processor(
+			CPU0,		/* name space name */
+			0,		/* Unique number for this processor */
+			0x808,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU1,		/* name space name */
+			1,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU2,		/* name space name */
+			2,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU3,		/* name space name */
+			3,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+	} /* End _PR scope */
+
+	/* PIC IRQ mapping registers, C00h-C01h */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PINA, 0x00000008,	/* Index 0  */
+		PINB, 0x00000008,	/* Index 1 */
+		PINC, 0x00000008,	/* Index 2 */
+		PIND, 0x00000008,	/* Index 3 */
+		AINT, 0x00000008,	/* Index 4 */
+		SINT, 0x00000008,	/*  Index 5 */
+		, 0x00000008,	             /* Index 6 */
+		AAUD, 0x00000008,	/* Index 7 */
+		AMOD, 0x00000008,	/* Index 8 */
+		PINE, 0x00000008,	/* Index 9 */
+		PINF, 0x00000008,	/* Index A */
+		PING, 0x00000008,	/* Index B */
+		PINH, 0x00000008,	/* Index C */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,      8,
+		/* Client Management Data register */
+		G64E,   1,
+		G64O,      1,
+		G32O,      2,
+		,       2,
+		GPSL,     2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x00),	/* MiscControl */
+		, 1,
+		T1EE, 1,
+		T2EE, 1,
+		Offset(0x01),	/* MiscStatus */
+		, 1,
+		T1E, 1,
+		T2E, 1,
+		Offset(0x04),	/* SmiWakeUpEventEnable3 */
+		, 7,
+		SSEN, 1,
+		Offset(0x07),	/* SmiWakeUpEventStatus3 */
+		, 7,
+		CSSM, 1,
+		Offset(0x10),	/* AcpiEnable */
+		, 6,
+		PWDE, 1,
+		Offset(0x1C),	/* ProgramIoEnable */
+		, 3,
+		MKME, 1,
+		IO3E, 1,
+		IO2E, 1,
+		IO1E, 1,
+		IO0E, 1,
+		Offset(0x1D),	/* IOMonitorStatus */
+		, 3,
+		MKMS, 1,
+		IO3S, 1,
+		IO2S, 1,
+		IO1S, 1,
+		IO0S,1,
+		Offset(0x20),	/* AcpiPmEvtBlk */
+		APEB, 16,
+		Offset(0x36),	/* GEvtLevelConfig */
+		, 6,
+		ELC6, 1,
+		ELC7, 1,
+		Offset(0x37),	/* GPMLevelConfig0 */
+		, 3,
+		PLC0, 1,
+		PLC1, 1,
+		PLC2, 1,
+		PLC3, 1,
+		PLC8, 1,
+		Offset(0x38),	/* GPMLevelConfig1 */
+		, 1,
+		 PLC4, 1,
+		 PLC5, 1,
+		, 1,
+		 PLC6, 1,
+		 PLC7, 1,
+		Offset(0x3B),	/* PMEStatus1 */
+		GP0S, 1,
+		GM4S, 1,
+		GM5S, 1,
+		APS, 1,
+		GM6S, 1,
+		GM7S, 1,
+		GP2S, 1,
+		STSS, 1,
+		Offset(0x55),	/* SoftPciRst */
+		SPRE, 1,
+		, 1,
+		, 1,
+		PNAT, 1,
+		PWMK, 1,
+		PWNS, 1,
+
+		/* 	Offset(0x61), */	/*  Options_1 */
+		/* 		,7,  */
+		/* 		R617,1, */
+
+		Offset(0x65),	/* UsbPMControl */
+		, 4,
+		URRE, 1,
+		Offset(0x68),	/* MiscEnable68 */
+		, 3,
+		TMTE, 1,
+		, 1,
+		Offset(0x92),	/* GEVENTIN */
+		, 7,
+		E7IS, 1,
+		Offset(0x96),	/* GPM98IN */
+		G8IS, 1,
+		G9IS, 1,
+		Offset(0x9A),	/* EnhanceControl */
+		,7,
+		HPDE, 1,
+		Offset(0xA8),	/* PIO7654Enable */
+		IO4E, 1,
+		IO5E, 1,
+		IO6E, 1,
+		IO7E, 1,
+		Offset(0xA9),	/* PIO7654Status */
+		IO4S, 1,
+		IO5S, 1,
+		IO6S, 1,
+		IO7S, 1,
+	}
+
+	/* PM1 Event Block
+	* First word is PM1_Status, Second word is PM1_Enable
+	*/
+	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+		Field(P1EB, ByteAcc, NoLock, Preserve) {
+		TMST, 1,
+		,    3,
+		BMST,    1,
+		GBST,   1,
+		Offset(0x01),
+		PBST, 1,
+		, 1,
+		RTST, 1,
+		, 3,
+		PWST, 1,
+		SPWS, 1,
+		Offset(0x02),
+		TMEN, 1,
+		, 4,
+		GBEN, 1,
+		Offset(0x03),
+		PBEN, 1,
+		, 1,
+		RTEN, 1,
+		, 3,
+		PWDA, 1,
+	}
+
+	Scope(\_SB) {
+		/* PCIe Configuration Space for 16 busses */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+			Field(PCFG, ByteAcc, NoLock, Preserve) {
+			/* Byte offsets are computed using the following technique:
+			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+			*/
+			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+			STB5, 32,
+			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+			PT0D, 1,
+			PT1D, 1,
+			PT2D, 1,
+			PT3D, 1,
+			PT4D, 1,
+			PT5D, 1,
+			PT6D, 1,
+			PT7D, 1,
+			PT8D, 1,
+			PT9D, 1,
+			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
+			SBIE, 1,
+			SBME, 1,
+			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
+			SBRI, 8,
+			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
+			SBB1, 32,
+			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
+			,14,
+			P92E, 1,		/* Port92 decode enable */
+		}
+
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+			Field(SB5, AnyAcc, NoLock, Preserve){
+			/* Port 0 */
+			Offset(0x120),		/* Port 0 Task file status */
+			P0ER, 1,
+			, 2,
+			P0DQ, 1,
+			, 3,
+			P0BY, 1,
+			Offset(0x128),		/* Port 0 Serial ATA status */
+			P0DD, 4,
+			, 4,
+			P0IS, 4,
+			Offset(0x12C),		/* Port 0 Serial ATA control */
+			P0DI, 4,
+			Offset(0x130),		/* Port 0 Serial ATA error */
+			, 16,
+			P0PR, 1,
+
+			/* Port 1 */
+			offset(0x1A0),		/* Port 1 Task file status */
+			P1ER, 1,
+			, 2,
+			P1DQ, 1,
+			, 3,
+			P1BY, 1,
+			Offset(0x1A8),		/* Port 1 Serial ATA status */
+			P1DD, 4,
+			, 4,
+			P1IS, 4,
+			Offset(0x1AC),		/* Port 1 Serial ATA control */
+			P1DI, 4,
+			Offset(0x1B0),		/* Port 1 Serial ATA error */
+			, 16,
+			P1PR, 1,
+
+			/* Port 2 */
+			Offset(0x220),		/* Port 2 Task file status */
+			P2ER, 1,
+			, 2,
+			P2DQ, 1,
+			, 3,
+			P2BY, 1,
+			Offset(0x228),		/* Port 2 Serial ATA status */
+			P2DD, 4,
+			, 4,
+			P2IS, 4,
+			Offset(0x22C),		/* Port 2 Serial ATA control */
+			P2DI, 4,
+			Offset(0x230),		/* Port 2 Serial ATA error */
+			, 16,
+			P2PR, 1,
+
+			/* Port 3 */
+			Offset(0x2A0),		/* Port 3 Task file status */
+			P3ER, 1,
+			, 2,
+			P3DQ, 1,
+			, 3,
+			P3BY, 1,
+			Offset(0x2A8),		/* Port 3 Serial ATA status */
+			P3DD, 4,
+			, 4,
+			P3IS, 4,
+			Offset(0x2AC),		/* Port 3 Serial ATA control */
+			P3DI, 4,
+			Offset(0x2B0),		/* Port 3 Serial ATA error */
+			, 16,
+			P3PR, 1,
+		}
+	}
+
+
+	#include "acpi/routing.asl"
+
+	Scope(\_SB) {
+
+		Method(CkOT, 0){
+
+			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+			if(CondRefOf(\_OSI,Local1))
+			{
+				Store(1, OSTP)                /* Assume some form of XP */
+				if (\_OSI("Windows 2006"))      /* Vista */
+				{
+					Store(2, OSTP)
+				}
+			} else {
+				If(WCMP(\_OS,"Linux")) {
+					Store(3, OSTP)            /* Linux */
+				} Else {
+					Store(4, OSTP)            /* Gotta be WinCE */
+				}
+			}
+			Return(OSTP)
+		}
+
+		Method(_PIC, 0x01, NotSerialized)
+		{
+			If (Arg0)
+			{
+				\_SB.CIRQ()
+			}
+			Store(Arg0, PMOD)
+		}
+		Method(CIRQ, 0x00, NotSerialized){
+			Store(0, PINA)
+			Store(0, PINB)
+			Store(0, PINC)
+			Store(0, PIND)
+			Store(0, PINE)
+			Store(0, PINF)
+			Store(0, PING)
+			Store(0, PINH)
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+		})
+
+		Name(PITF, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){9}
+		})
+
+		Device(INTA) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 1)
+
+			Method(_STA, 0) {
+				if (PINA) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTA._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+				Store(0, PINA)
+			} /* End Method(_SB.INTA._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTA._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINA, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTA._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINA)
+			} /* End Method(_SB.INTA._SRS) */
+		} /* End Device(INTA) */
+
+		Device(INTB) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 2)
+
+			Method(_STA, 0) {
+				if (PINB) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTB._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+				Store(0, PINB)
+			} /* End Method(_SB.INTB._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTB._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINB, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTB._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINB)
+			} /* End Method(_SB.INTB._SRS) */
+		} /* End Device(INTB)  */
+
+		Device(INTC) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 3)
+
+			Method(_STA, 0) {
+				if (PINC) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTC._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+				Store(0, PINC)
+			} /* End Method(_SB.INTC._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTC._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINC, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTC._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINC)
+			} /* End Method(_SB.INTC._SRS) */
+		} /* End Device(INTC)  */
+
+		Device(INTD) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 4)
+
+			Method(_STA, 0) {
+				if (PIND) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTD._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+				Store(0, PIND)
+			} /* End Method(_SB.INTD._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTD._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIND, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTD._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIND)
+			} /* End Method(_SB.INTD._SRS) */
+		} /* End Device(INTD)  */
+
+		Device(INTE) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 5)
+
+			Method(_STA, 0) {
+				if (PINE) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTE._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+				Store(0, PINE)
+			} /* End Method(_SB.INTE._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTE._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINE, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTE._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINE)
+			} /* End Method(_SB.INTE._SRS) */
+		} /* End Device(INTE)  */
+
+		Device(INTF) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 6)
+
+			Method(_STA, 0) {
+				if (PINF) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTF._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+				Store(0, PINF)
+			} /* End Method(_SB.INTF._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+				Return(PITF)
+			} /* Method(_SB.INTF._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINF, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTF._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINF)
+			} /*  End Method(_SB.INTF._SRS) */
+		} /* End Device(INTF)  */
+
+		Device(INTG) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 7)
+
+			Method(_STA, 0) {
+				if (PING) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTG._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+				Store(0, PING)
+			} /* End Method(_SB.INTG._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PING, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PING)
+			} /* End Method(_SB.INTG._SRS)  */
+		} /* End Device(INTG)  */
+
+		Device(INTH) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 8)
+
+			Method(_STA, 0) {
+				if (PINH) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTH._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+				Store(0, PINH)
+			} /* End Method(_SB.INTH._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINH, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINH)
+			} /* End Method(_SB.INTH._SRS)  */
+		} /* End Device(INTH)   */
+
+	}   /* End Scope(_SB)  */
+
+
+	/* Supported sleep states: */
+	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+	If (LAnd(SSFG, 0x01)) {
+		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+	}
+	If (LAnd(SSFG, 0x02)) {
+		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x04)) {
+		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x08)) {
+		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+	}
+
+	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+	Name(CSMS, 0)			/* Current System State */
+
+	/* Wake status package */
+	Name(WKST,Package(){Zero, Zero})
+
+	/*
+	* \_PTS - Prepare to Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+	*
+	* Exit:
+	*		-none-
+	*
+	* The _PTS control method is executed at the beginning of the sleep process
+	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+	* control method may be executed a relatively long time before entering the
+	* sleep state and the OS may abort	the operation without notification to
+	* the ACPI driver.  This method cannot modify the configuration or power
+	* state of any device in the system.
+	*/
+	Method(\_PTS, 1) {
+		/* DBGO("\\_PTS\n") */
+		/* DBGO("From S0 to S") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+
+		/* Don't allow PCIRST# to reset USB */
+		if (LEqual(Arg0,3)){
+			Store(0,URRE)
+		}
+
+		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+		/*Store(One, CSSM)
+		Store(One, SSEN)*/
+
+		/* On older chips, clear PciExpWakeDisEn */
+		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+		*    	Store(0,\_SB.PWDE)
+		*}
+		*/
+
+		/* Clear wake status structure. */
+		Store(0, Index(WKST,0))
+		Store(0, Index(WKST,1))
+		\_SB.PCI0.SIOS (Arg0)
+	} /* End Method(\_PTS) */
+
+	/*
+	*  The following method results in a "not a valid reserved NameSeg"
+	*  warning so I have commented it out for the duration.  It isn't
+	*  used, so it could be removed.
+	*
+	*
+	*  	\_GTS OEM Going To Sleep method
+	*
+	*  	Entry:
+	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*  	Exit:
+	*  		-none-
+	*
+	*  Method(\_GTS, 1) {
+	*  DBGO("\\_GTS\n")
+	*  DBGO("From S0 to S")
+	*  DBGO(Arg0)
+	*  DBGO("\n")
+	*  }
+	*/
+
+	/*
+	*	\_BFS OEM Back From Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		-none-
+	*/
+	Method(\_BFS, 1) {
+		/* DBGO("\\_BFS\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+	}
+
+	/*
+	*  \_WAK System Wake method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		Return package of 2 DWords
+	*		Dword 1 - Status
+	*			0x00000000	wake succeeded
+	*			0x00000001	Wake was signaled but failed due to lack of power
+	*			0x00000002	Wake was signaled but failed due to thermal condition
+	*		Dword 2 - Power Supply state
+	*			if non-zero the effective S-state the power supply entered
+	*/
+	Method(\_WAK, 1) {
+		/* DBGO("\\_WAK\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+
+		/* Re-enable HPET */
+		Store(1,HPDE)
+
+		/* Restore PCIRST# so it resets USB */
+		if (LEqual(Arg0,3)){
+			Store(1,URRE)
+		}
+
+		/* Arbitrarily clear PciExpWakeStatus */
+		Store(PWST, PWST)
+
+		/* if(DeRefOf(Index(WKST,0))) {
+		*	Store(0, Index(WKST,1))
+		* } else {
+		*	Store(Arg0, Index(WKST,1))
+		* }
+		*/
+		\_SB.PCI0.SIOW (Arg0)
+		Return(WKST)
+	} /* End Method(\_WAK) */
+
+	Scope(\_GPE) {	/* Start Scope GPE */
+		/*  General event 0  */
+		/* Method(_L00) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 1  */
+		/* Method(_L01) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 2  */
+		/* Method(_L02) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 3  */
+		Method(_L03) {
+			/* DBGO("\\_GPE\\_L00\n") */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  General event 4  */
+		/* Method(_L04) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 5  */
+		/* Method(_L05) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* Method(_L06) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 7 - Used for GPM7, moved to USB.asl */
+		/* Method(_L07) {
+		*	DBGO("\\_GPE\\_L07\n")
+		* }
+		*/
+
+		/*  Legacy PM event  */
+		Method(_L08) {
+			/* DBGO("\\_GPE\\_L08\n") */
+		}
+
+		/*  Temp warning (TWarn) event  */
+		Method(_L09) {
+			/* DBGO("\\_GPE\\_L09\n") */
+			Notify (\_TZ.TZ00, 0x80)
+		}
+
+		/*  Reserved  */
+		/* Method(_L0A) {
+		*	DBGO("\\_GPE\\_L0A\n")
+		* }
+		*/
+
+		/*  USB controller PME#  */
+		Method(_L0B) {
+			/* DBGO("\\_GPE\\_L0B\n") */
+			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  AC97 controller PME#  */
+		/* Method(_L0C) {
+		*	DBGO("\\_GPE\\_L0C\n")
+		* }
+		*/
+
+		/*  OtherTherm PME#  */
+		/* Method(_L0D) {
+		*	DBGO("\\_GPE\\_L0D\n")
+		* }
+		*/
+
+		/*  GPM9 SCI event - Moved to USB.asl */
+		/* Method(_L0E) {
+		*	DBGO("\\_GPE\\_L0E\n")
+		* }
+		*/
+
+		/*  PCIe HotPlug event  */
+		/* Method(_L0F) {
+		* 	DBGO("\\_GPE\\_L0F\n")
+		* }
+		*/
+
+		/*  ExtEvent0 SCI event  */
+		Method(_L10) {
+			/* DBGO("\\_GPE\\_L10\n") */
+		}
+
+
+		/*  ExtEvent1 SCI event  */
+		Method(_L11) {
+			/* DBGO("\\_GPE\\_L11\n") */
+		}
+
+		/*  PCIe PME# event  */
+		/* Method(_L12) {
+		*	DBGO("\\_GPE\\_L12\n")
+		* }
+		*/
+
+		/*  GPM0 SCI event - Moved to USB.asl */
+		/* Method(_L13) {
+		* 	DBGO("\\_GPE\\_L13\n")
+		* }
+		*/
+
+		/*  GPM1 SCI event - Moved to USB.asl */
+		/* Method(_L14) {
+		* 	DBGO("\\_GPE\\_L14\n")
+		* }
+		*/
+
+		/*  GPM2 SCI event - Moved to USB.asl */
+		/* Method(_L15) {
+		* 	DBGO("\\_GPE\\_L15\n")
+		* }
+		*/
+
+		/*  GPM3 SCI event - Moved to USB.asl */
+		/* Method(_L16) {
+		*	DBGO("\\_GPE\\_L16\n")
+		* }
+		*/
+
+		/*  GPM8 SCI event - Moved to USB.asl */
+		/* Method(_L17) {
+		* 	DBGO("\\_GPE\\_L17\n")
+		* }
+		*/
+
+		/*  GPIO0 or GEvent8 event  */
+		Method(_L18) {
+			/* DBGO("\\_GPE\\_L18\n") */
+			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM4 SCI event - Moved to USB.asl */
+		/* Method(_L19) {
+		* 	DBGO("\\_GPE\\_L19\n")
+		* }
+		*/
+
+		/*  GPM5 SCI event - Moved to USB.asl */
+		/* Method(_L1A) {
+		*	DBGO("\\_GPE\\_L1A\n")
+		* }
+		*/
+
+		/*  Azalia SCI event  */
+		Method(_L1B) {
+			/* DBGO("\\_GPE\\_L1B\n") */
+			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM6 SCI event - Reassigned to _L06 */
+		/* Method(_L1C) {
+		*	DBGO("\\_GPE\\_L1C\n")
+		* }
+		*/
+
+		/*  GPM7 SCI event - Reassigned to _L07 */
+		/* Method(_L1D) {
+		*	DBGO("\\_GPE\\_L1D\n")
+		* }
+		*/
+
+		/*  GPIO2 or GPIO66 SCI event  */
+		/* Method(_L1E) {
+		* 	DBGO("\\_GPE\\_L1E\n")
+		* }
+		*/
+
+		/*  SATA SCI event - Moved to sata.asl */
+		/* Method(_L1F) {
+		*	 DBGO("\\_GPE\\_L1F\n")
+		* }
+		*/
+
+	} 	/* End Scope GPE */
+
+	#include "acpi/usb.asl"
+
+	/* South Bridge */
+	Scope(\_SB) { /* Start \_SB scope */
+		#include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+		/*  _SB.PCI0 */
+		/* Note: Only need HID on Primary Bus */
+		Device(PCI0) {
+			External (TOM1)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
+			Name(_HID, EISAID("PNP0A03"))
+			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			Method(_BBN, 0) { /* Bus number = 0 */
+				Return(0)
+			}
+			Method(_STA, 0) {
+				/* DBGO("\\_SB\\PCI0\\_STA\n") */
+				Return(0x0B)     /* Status is visible */
+			}
+
+			Method(_PRT,0) {
+				If(PMOD){ Return(APR0) }   /* APIC mode */
+				Return (PR0)                  /* PIC Mode */
+			} /* end _PRT */
+
+			/* Describe the Northbridge devices */
+			Device(AMRT) {
+				Name(_ADR, 0x00000000)
+			} /* end AMRT */
+
+			/* The internal GFX bridge */
+			Device(AGPB) {
+				Name(_ADR, 0x00010000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					Return (APR1)
+				}
+			}  /* end AGPB */
+
+			/* The external GFX bridge */
+			Device(PBR2) {
+				Name(_ADR, 0x00020000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS2) }   /* APIC mode */
+					Return (PS2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR2 */
+
+			/* Dev3 is also an external GFX bridge, not used in Herring */
+
+			Device(PBR4) {
+				Name(_ADR, 0x00040000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS4) }   /* APIC mode */
+					Return (PS4)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR4 */
+
+			Device(PBR5) {
+				Name(_ADR, 0x00050000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR5 */
+
+			Device(PBR6) {
+				Name(_ADR, 0x00060000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS6) }   /* APIC mode */
+					Return (PS6)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR6 */
+
+			/* The onboard EtherNet chip */
+			Device(PBR7) {
+				Name(_ADR, 0x00070000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS7) }   /* APIC mode */
+					Return (PS7)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR7 */
+
+			/* GPP */
+			Device(PBR9) {
+				Name(_ADR, 0x00090000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS9) }   /* APIC mode */
+					Return (PS9)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR9 */
+
+			Device(PBRa) {
+				Name(_ADR, 0x000A0000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APSa) }   /* APIC mode */
+					Return (PSa)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBRa */
+
+
+			/* PCI slot 1, 2, 3 */
+			Device(PIBR) {
+				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
+			}
+
+			/* Describe the Southbridge devices */
+			Device(STCR) {
+				Name(_ADR, 0x00110000)
+				#include "acpi/sata.asl"
+			} /* end STCR */
+
+			Device(UOH1) {
+				Name(_ADR, 0x00130000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH1 */
+
+			Device(UOH2) {
+				Name(_ADR, 0x00130001)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH2 */
+
+			Device(UOH3) {
+				Name(_ADR, 0x00130002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH3 */
+
+			Device(UOH4) {
+				Name(_ADR, 0x00130003)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH4 */
+
+			Device(UOH5) {
+				Name(_ADR, 0x00130004)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UEH1) {
+				Name(_ADR, 0x00130005)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UEH1 */
+
+			Device(SBUS) {
+				Name(_ADR, 0x00140000)
+			} /* end SBUS */
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				#include "acpi/ide.asl"
+			} /* end IDEC */
+
+			Device(AZHD) {
+				Name(_ADR, 0x00140002)
+				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+					Field(AZPD, AnyAcc, NoLock, Preserve) {
+					offset (0x42),
+					NSDI, 1,
+					NSDO, 1,
+					NSEN, 1,
+					offset (0x44),
+					IPCR, 4,
+					offset (0x54),
+					PWST, 2,
+					, 6,
+					PMEB, 1,
+					, 6,
+					PMST, 1,
+					offset (0x62),
+					MMCR, 1,
+					offset (0x64),
+					MMLA, 32,
+					offset (0x68),
+					MMHA, 32,
+					offset (0x6C),
+					MMDT, 16,
+				}
+
+				Method(_INI) {
+					If(LEqual(OSTP,3)){   /* If we are running Linux */
+						Store(zero, NSEN)
+						Store(one, NSDO)
+						Store(one, NSDI)
+					}
+				}
+			} /* end AZHD */
+
+			Device(LIBR) {
+				Name(_ADR, 0x00140003)
+				/* Method(_INI) {
+				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+				} */ /* End Method(_SB.SBRDG._INI) */
+
+				/* Real Time Clock Device */
+				Device(RTC0) {
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){8}
+						IO(Decode16,0x0070, 0x0070, 0, 2)
+						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+				Device(TMR) {	/* Timer */
+					Name(_HID,EISAID("PNP0100"))	/* System Timer */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){0}
+						IO(Decode16, 0x0040, 0x0040, 0, 4)
+						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+				Device(SPKR) {	/* Speaker */
+					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x0061, 0x0061, 0, 1)
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+				Device(PIC) {
+					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){2}
+						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IO(Decode16,0x00A0, 0x00A0, 0, 2)
+						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+				Device(MAD) { /* 8257 DMA */
+					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+					Name(_CRS, ResourceTemplate() {
+						DMA(Compatibility,BusMaster,Transfer8){4}
+						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+						IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+						IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+						IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+						IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+				Device(COPR) {
+					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+						IRQNoFlags(){13}
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+				Device(HPTM) {
+					Name(_HID,EISAID("PNP0103"))
+					Name(CRS,ResourceTemplate()	{
+						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
+					})
+					Method(_STA, 0) {
+						Return(0x0F) /* sata is visible */
+					}
+					Method(_CRS, 0)	{
+						CreateDwordField(CRS, ^HPT._BAS, HPBA)
+						Store(HPBA, HPBA)
+						Return(CRS)
+					}
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+			} /* end LIBR */
+
+			Device(HPBR) {
+				Name(_ADR, 0x00140004)
+			} /* end HostPciBr */
+
+			Device(ACAD) {
+				Name(_ADR, 0x00140005)
+			} /* end Ac97audio */
+
+			Device(ACMD) {
+				Name(_ADR, 0x00140006)
+			} /* end Ac97modem */
+
+			/* ITE8718 Support */
+			OperationRegion (IOID, SystemIO, 0x2E, 0x02)	/* sometimes it is 0x4E */
+				Field (IOID, ByteAcc, NoLock, Preserve)
+				{
+					SIOI,   8,    SIOD,   8		/* 0x2E and 0x2F */
+				}
+
+			IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+			{
+					Offset (0x07),
+				LDN,	8,	/* Logical Device Number */
+					Offset (0x20),
+				CID1,	8,	/* Chip ID Byte 1, 0x87 */
+				CID2,	8,	/* Chip ID Byte 2, 0x12 */
+					Offset (0x30),
+				ACTR,	8,	/* Function activate */
+					Offset (0xF0),
+				APC0,	8,	/* APC/PME Event Enable Register */
+				APC1,	8,	/* APC/PME Status Register */
+				APC2,	8,	/* APC/PME Control Register 1 */
+				APC3,	8,	/* Environment Controller Special Configuration Register */
+				APC4,	8	/* APC/PME Control Register 2 */
+			}
+
+			/* Enter the 8718 MB PnP Mode */
+			Method (EPNP)
+			{
+				Store(0x87, SIOI)
+				Store(0x01, SIOI)
+				Store(0x55, SIOI)
+				Store(0x55, SIOI) /* 8718 magic number */
+			}
+			/* Exit the 8718 MB PnP Mode */
+			Method (XPNP)
+			{
+				Store (0x02, SIOI)
+				Store (0x02, SIOD)
+			}
+			/*
+			 * Keyboard PME is routed to SB700 Gevent3. We can wake
+			 * up the system by pressing the key.
+			 */
+			Method (SIOS, 1)
+			{
+				/* We only enable KBD PME for S5. */
+				If (LLess (Arg0, 0x05))
+				{
+					EPNP()
+					/* DBGO("8718F\n") */
+
+					Store (0x4, LDN)
+					Store (One, ACTR)  /* Enable EC */
+					/*
+					Store (0x4, LDN)
+					Store (0x04, APC4)
+					*/  /* falling edge. which mode? Not sure. */
+
+					Store (0x4, LDN)
+					Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+					Store (0x4, LDN)
+					Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+					XPNP()
+				}
+			}
+			Method (SIOW, 1)
+			{
+				EPNP()
+				Store (0x4, LDN)
+				Store (Zero, APC0) /* disable keyboard PME */
+				Store (0x4, LDN)
+				Store (0xFF, APC1) /* clear keyboard PME status */
+				XPNP()
+			}
+
+			Name(CRES, ResourceTemplate() {
+				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0000,			/* range minimum */
+					0x0CF7,			/* range maximum */
+					0x0000,			/* translation */
+					0x0CF8			/* length */
+				)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0D00,			/* range minimum */
+					0xFFFF,			/* range maximum */
+					0x0000,			/* translation */
+					0xF300			/* length */
+				)
+
+				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
+
+				/* DRAM Memory from 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+
+				/* BIOS space just below 4GB */
+				DWORDMemory(
+					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00,			/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000001,		/* Max-Min, RLEN */
+					,,
+					PCBM
+				)
+
+				/* DRAM memory from 4GB to TopMem2 */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00000000,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000001,		/* Max-Min, RLEN */
+					,,
+					DMHI
+				)
+
+				/* BIOS space just below 16EB */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00000000,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000001,		/* Max-Min, RLEN */
+					,,
+					PEBM
+				)
+
+			}) /* End Name(_SB.PCI0.CRES) */
+
+			Method(_CRS, 0) {
+				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+
+				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+				CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				If(LGreater(LOMH, 0xC0000)){
+					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
+					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
+				}
+
+				/* Set size of memory from 1MB to TopMem */
+				Subtract(TOM1, 0x100000, DMLL)
+
+				/*
+				* If(LNotEqual(TOM2, 0x00000000)){
+				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
+				* }
+				*/
+
+				/* If there is no memory above 4GB, put the BIOS just below 4GB */
+				If(LEqual(TOM2, 0x00000000)){
+					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+					Store(PBLN,PBML)
+				}
+				Else {  /* Otherwise, put the BIOS just below 16EB */
+					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
+					Store(PBLN,EBML)
+				}
+
+				Return(CRES) /* note to change the Name buffer */
+			}  /* end of Method(_SB.PCI0._CRS) */
+
+			/*
+			*
+			*               FIRST METHOD CALLED UPON BOOT
+			*
+			*  1. If debugging, print current OS and ACPI interpreter.
+			*  2. Get PCI Interrupt routing from ACPI VSM, this
+			*     value is based on user choice in BIOS setup.
+			*/
+			Method(_INI, 0) {
+				/* DBGO("\\_SB\\_INI\n") */
+				/* DBGO("   DSDT.ASL code from ") */
+				/* DBGO(__DATE__) */
+				/* DBGO(" ") */
+				/* DBGO(__TIME__) */
+				/* DBGO("\n   Sleep states supported: ") */
+				/* DBGO("\n") */
+				/* DBGO("   \\_OS=") */
+				/* DBGO(\_OS) */
+				/* DBGO("\n   \\_REV=") */
+				/* DBGO(\_REV) */
+				/* DBGO("\n") */
+
+				/* Determine the OS we're running on */
+				CkOT()
+
+				/* On older chips, clear PciExpWakeDisEn */
+				/*if (LLessEqual(\SBRI, 0x13)) {
+				*    	Store(0,\PWDE)
+				* }
+				*/
+			} /* End Method(_SB._INI) */
+		} /* End Device(PCI0)  */
+
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
+	} /* End \_SB scope */
+
+	Scope(\_SI) {
+		Method(_SST, 1) {
+			/* DBGO("\\_SI\\_SST\n") */
+			/* DBGO("   New Indicator state: ") */
+			/* DBGO(Arg0) */
+			/* DBGO("\n") */
+		}
+	} /* End Scope SI */
+
+	/* SMBUS Support */
+	Mutex (SBX0, 0x00)
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+		Field (SMB0, ByteAcc, NoLock, Preserve) {
+			HSTS,   8, /* SMBUS status */
+			SSTS,   8,  /* SMBUS slave status */
+			HCNT,   8,  /* SMBUS control */
+			HCMD,   8,  /* SMBUS host cmd */
+			HADD,   8,  /* SMBUS address */
+			DAT0,   8,  /* SMBUS data0 */
+			DAT1,   8,  /* SMBUS data1 */
+			BLKD,   8,  /* SMBUS block data */
+			SCNT,   8,  /* SMBUS slave control */
+			SCMD,   8,  /* SMBUS shaow cmd */
+			SEVT,   8,  /* SMBUS slave event */
+			SDAT,   8  /* SMBUS slave data */
+	}
+
+	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+		Store (0x1E, HSTS)
+		Store (0xFA, Local0)
+		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+			Stall (0x64)
+			Decrement (Local0)
+		}
+
+		Return (Local0)
+	}
+
+	Method (SWTC, 1, NotSerialized) {
+		Store (Arg0, Local0)
+		Store (0x07, Local2)
+		Store (One, Local1)
+		While (LEqual (Local1, One)) {
+			Store (And (HSTS, 0x1E), Local3)
+			If (LNotEqual (Local3, Zero)) { /* read sucess */
+				If (LEqual (Local3, 0x02)) {
+					Store (Zero, Local2)
+				}
+
+				Store (Zero, Local1)
+			}
+			Else {
+				If (LLess (Local0, 0x0A)) { /* read failure */
+					Store (0x10, Local2)
+					Store (Zero, Local1)
+				}
+				Else {
+					Sleep (0x0A) /* 10 ms, try again */
+					Subtract (Local0, 0x0A, Local0)
+				}
+			}
+		}
+
+		Return (Local2)
+	}
+
+	Method (SMBR, 3, NotSerialized) {
+		Store (0x07, Local0)
+		If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+			Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+			If (LEqual (Local0, Zero)) {
+				Release (SBX0)
+				Return (0x0)
+			}
+
+			Store (0x1F, HSTS)
+			Store (Or (ShiftLeft (Arg1, One), One), HADD)
+			Store (Arg2, HCMD)
+			If (LEqual (Arg0, 0x07)) {
+				Store (0x48, HCNT) /* read byte */
+			}
+
+			Store (SWTC (0x03E8), Local1) /* 1000 ms */
+			If (LEqual (Local1, Zero)) {
+				If (LEqual (Arg0, 0x07)) {
+					Store (DAT0, Local0)
+				}
+			}
+			Else {
+				Store (Local1, Local0)
+			}
+
+			Release (SBX0)
+		}
+
+		/* DBGO("the value of SMBusData0 register ") */
+		/* DBGO(Arg2) */
+		/* DBGO(" is ") */
+		/* DBGO(Local0) */
+		/* DBGO("\n") */
+
+		Return (Local0)
+	}
+
+	/* THERMAL */
+	Scope(\_TZ) {
+		Name (KELV, 2732)
+		Name (THOT, 800)
+		Name (TCRT, 850)
+
+		ThermalZone(TZ00) {
+			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+				Return(Add(0, 2730))
+			}
+			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+				Return(Package() {\_TZ.TZ00.FAN0})
+			}
+			Device (FAN0) {
+				Name(_HID, EISAID("PNP0C0B"))
+				Name(_PR0, Package() {PFN0})
+			}
+
+			PowerResource(PFN0,0,0) {
+				Method(_STA) {
+					Store(0xF,Local0)
+					Return(Local0)
+				}
+				Method(_ON) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+				}
+				Method(_OFF) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+				}
+			}
+
+			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+				Return (Add (THOT, KELV))
+			}
+			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+				Return (Add (TCRT, KELV))
+			}
+			Method(_TMP,0) {	/* return current temp of this zone */
+				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+				If (LGreater (Local0, 0x10)) {
+					Store (Local0, Local1)
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400, KELV))
+				}
+
+				Store (SMBR (0x07, 0x4C, 0x01), Local0)
+				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+				If (LGreater (Local0, 0x10)) {
+					If (LGreater (Local0, Local1)) {
+						Store (Local0, Local1)
+					}
+
+					Multiply (Local1, 10, Local1)
+					Return (Add (Local1, KELV))
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400 , KELV))
+				}
+			} /* end of _TMP */
+		} /* end of TZ00 */
+	}
+}
+/* End of ASL file */
diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
new file mode 100644
index 0000000..b169775
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/multicore.h>
+#endif
+
+#include <cpu/amd/amdfam10_sysconf.h>
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+u8 bus_rs780[11];
+u8 bus_sb700[2];
+u32 apicid_sb700;
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+	0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+	0x20202020,
+};
+
+u32 sbdn_rs780;
+u32 sbdn_sb700;
+
+extern void get_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+	u32 apicid_base;
+	device_t dev;
+	int i;
+
+	if (get_bus_conf_done == 1)
+		return;		/* do it only once */
+	get_bus_conf_done = 1;
+
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+	for (i = 0; i < sysconf.hc_possible_num; i++) {
+		sysconf.pci1234[i] = pci1234x[i];
+		sysconf.hcdn[i] = hcdnx[i];
+	}
+
+	get_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
+	sbdn_rs780 = sysconf.sbdn;
+	sbdn_sb700 = 0;
+
+	for (i = 0; i < 2; i++) {
+		bus_sb700[i] = 0;
+	}
+	for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
+		bus_rs780[i] = 0;
+	}
+
+	bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sb700[0] = bus_rs780[0];
+
+	/* sb700 */
+	dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
+	if (dev) {
+		bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	}
+
+	/* rs780 */
+	for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
+		dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
+		if (dev) {
+			bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		}
+	}
+
+	/* I/O APICs:   APIC ID Version State   Address */
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+	apicid_sb700 = apicid_base + 0;
+}
diff --git a/src/mainboard/gigabyte/ma785gm/irq_tables.c b/src/mainboard/gigabyte/ma785gm/irq_tables.c
new file mode 100644
index 0000000..fc9e42c
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/irq_tables.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdfam10_sysconf.h>
+
+
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			    u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+extern u8 bus_rs780[8];
+extern u8 bus_sb700[2];
+extern unsigned long sbdn_sb700;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+	u8 *v;
+
+	u8 sum = 0;
+	int i;
+
+	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+	v = (u8 *) (addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = bus_sb700[0];
+	pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->checksum + 1);
+	slot_num = 0;
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+			0);
+	pirq_info++;
+	slot_num++;
+
+	pirq->size = 32 + 16 * slot_num;
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];
+
+	sum = pirq->checksum - sum;
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+	return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
new file mode 100644
index 0000000..eeddbfc
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -0,0 +1,317 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alec Ari <neotheuser at ymail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+#include "chip.h"
+
+#define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS     0x0C /* Alert Response Address */
+
+#define ADT7461_read_byte(address) \
+	do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ARA_read_byte(address) \
+	do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
+#define ADT7461_write_byte(address, val) \
+	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+
+uint64_t uma_memory_base, uma_memory_size;
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+int is_dev3_present(void);
+
+void set_pcie_dereset()
+{
+	u8 byte;
+	u16 word;
+	device_t sm_dev;
+	/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+	/* set 0 to bit2 :disable GPM8 as AZ_RST output */
+	byte = pm_ioread(0x8d);
+	byte &= ~((1 << 1) | (1 << 2));
+	pm_iowrite(0x8d, byte);
+
+	/* set the GPM8 and GPM9 output enable and the value to 1 */
+	byte = pm_ioread(0x94);
+	byte &= ~((1 << 2) | (1 << 3));
+	byte |=  ((1 << 0) | (1 << 1));
+	pm_iowrite(0x94, byte);
+
+	/* set the GPIO65 output enable and the value is 1 */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	word = pci_read_config16(sm_dev, 0x7e);
+	word |= (1 << 0);
+	word &= ~(1 << 4);
+	pci_write_config16(sm_dev, 0x7e, word);
+}
+
+void set_pcie_reset()
+{
+	u8 byte;
+	u16 word;
+	device_t sm_dev;
+
+	/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+	/* set 0 to bit2 :disable GPM8 as AZ_RST output */
+	byte = pm_ioread(0x8d);
+	byte &= ~((1 << 1) | (1 << 2));
+	pm_iowrite(0x8d, byte);
+
+	/* set the GPM8 and GPM9 output enable and the value to 0 */
+	byte = pm_ioread(0x94);
+	byte &= ~((1 << 2) | (1 << 3));
+	byte &= ~((1 << 0) | (1 << 1));
+	pm_iowrite(0x94, byte);
+
+	/* set the GPIO65 output enable and the value is 0 */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	word = pci_read_config16(sm_dev, 0x7e);
+	word &= ~(1 << 0);
+	word &= ~(1 << 4);
+	pci_write_config16(sm_dev, 0x7e, word);
+}
+
+/*
+ * justify the dev3 is exist or not
+ */
+int is_dev3_present(void)
+{
+	u16 word;
+	device_t sm_dev;
+
+	/* access the smbus extended register */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	/* put the GPIO68 output to tristate */
+	word = pci_read_config16(sm_dev, 0x7e);
+	word |= 1 << 6;
+	pci_write_config16(sm_dev, 0x7e,word);
+
+	/* read the GPIO68 input status */
+	word = pci_read_config16(sm_dev, 0x7e);
+
+	if(word & (1 << 10)){
+		/*not exist*/
+		return 0;
+	}else{
+		/*exist*/
+		return 1;
+	}
+}
+
+/*
+ * set gpio40 gfx
+ */
+static void set_gpio40_gfx(void)
+{
+	u8 byte;
+//	u16 word;
+	u32 dword;
+	device_t sm_dev;
+	/* disable the GPIO40 as CLKREQ2# function */
+	byte = pm_ioread(0xd3);
+	byte &= ~(1 << 7);
+	pm_iowrite(0xd3, byte);
+
+	/* disable the GPIO40 as CLKREQ3# function */
+	byte = pm_ioread(0xd4);
+	byte &= ~(1 << 0);
+	pm_iowrite(0xd4, byte);
+
+	/* enable pull up for GPIO68 */
+	byte = pm2_ioread(0xf1);
+	byte &=	~(1 << 4);
+	pm2_iowrite(0xf1, byte);
+
+	/* access the smbus extended register */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	/*if the dev3 is present, set the gfx to 2x8 lanes*/
+	/*otherwise set the gfx to 1x16 lanes*/
+	if(is_dev3_present()){
+
+		printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
+		/* when the gpio40 is configured as GPIO, this will enable the output */
+		pci_write_config32(sm_dev, 0xf8, 0x4);
+		dword = pci_read_config32(sm_dev, 0xfc);
+		dword &= ~(1 << 10);
+
+	        /* When the gpio40 is configured as GPIO, this will represent the output value*/
+		/* 1 :enable two x8  , 0 : master slot enable only */
+		dword |= (1 << 26);
+		pci_write_config32(sm_dev, 0xfc, dword);
+
+	}else{
+		printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
+		/* when the gpio40 is configured as GPIO, this will enable the output */
+		pci_write_config32(sm_dev, 0xf8, 0x4);
+		dword = pci_read_config32(sm_dev, 0xfc);
+		dword &= ~(1 << 10);
+
+        	/* When the gpio40 is configured as GPIO, this will represent the output value*/
+		/* 1 :enable two x8  , 0 : master slot enable only */
+		dword &=  ~(1 << 26);
+		pci_write_config32(sm_dev, 0xfc, dword);
+	}
+}
+
+/*
+ * set thermal config
+ */
+static void set_thermal_config(void)
+{
+	u8 byte;
+	u16 word;
+	device_t sm_dev;
+
+	/* set ADT 7461 */
+	ADT7461_write_byte(0x0B, 0x50);	/* Local Temperature Hight limit */
+	ADT7461_write_byte(0x0C, 0x00);	/* Local Temperature Low limit */
+	ADT7461_write_byte(0x0D, 0x50);	/* External Temperature Hight limit  High Byte */
+	ADT7461_write_byte(0x0E, 0x00);	/* External Temperature Low limit High Byte */
+
+	ADT7461_write_byte(0x19, 0x55);	/* External THERM limit */
+	ADT7461_write_byte(0x20, 0x55);	/* Local THERM limit */
+
+	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
+	ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
+	printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+
+	/* sb700 settings for thermal config */
+	/* set SB700 GPIO 64 to GPIO with pull-up */
+	byte = pm2_ioread(0x42);
+	byte &= 0x3f;
+	pm2_iowrite(0x42, byte);
+
+	/* set GPIO 64 to input */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	word = pci_read_config16(sm_dev, 0x56);
+	word |= 1 << 7;
+	pci_write_config16(sm_dev, 0x56, word);
+
+	/* set GPIO 64 internal pull-up */
+	byte = pm2_ioread(0xf0);
+	byte &= 0xee;
+	pm2_iowrite(0xf0, byte);
+
+	/* set Talert to be active low */
+	byte = pm_ioread(0x67);
+	byte &= ~(1 << 5);
+	pm_iowrite(0x67, byte);
+
+	/* set Talert to generate ACPI event */
+	byte = pm_ioread(0x3c);
+	byte &= 0xf3;
+	pm_iowrite(0x3c, byte);
+
+	/* THERMTRIP pin */
+	/* byte = pm_ioread(0x68);
+	 * byte |= 1 << 3;
+	 * pm_iowrite(0x68, byte);
+	 *
+	 * byte = pm_ioread(0x55);
+	 * byte |= 1 << 0;
+	 * pm_iowrite(0x55, byte);
+	 *
+	 * byte = pm_ioread(0x67);
+	 * byte &= ~( 1 << 6);
+	 * pm_iowrite(0x67, byte);
+	 */
+}
+
+/*************************************************
+* enable the dedicated function in ma785gm board.
+* This function called early than rs780_enable.
+*************************************************/
+static void ma785gm_enable(device_t dev)
+{
+	printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev);
+
+#if (CONFIG_GFXUMA == 1)
+	msr_t msr, msr2;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk(BIOS_INFO,
+	    "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk(BIOS_INFO,
+	    "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	     __func__, msr2.lo, msr2.hi);
+
+	switch (msr.lo) {
+	case 0x10000000:	/* 256M system memory */
+		uma_memory_size = 0x4000000;	/* 64M recommended UMA */
+		break;
+
+	case 0x20000000:	/* 512M system memory */
+		uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+		break;
+
+	default:		/* 1GB and above system memory */
+		uma_memory_size = 0x10000000;	/* 256M recommended UMA */
+		break;
+	}
+
+	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+		    __func__, uma_memory_size, uma_memory_base);
+
+	/* TODO: TOP_MEM2 */
+#else
+	uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+	uma_memory_base = 0x38000000;	/* 1GB  system memory supposed */
+#endif
+
+	set_pcie_dereset();
+	/* get_ide_dma66(); */
+	set_thermal_config();
+	set_gpio40_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	/* UMA is removed from system memory in the northbridge code, but
+	 * in some circumstances we want the memory mentioned as reserved.
+ 	 */
+#if (CONFIG_GFXUMA == 1)
+	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+		    uma_memory_base, uma_memory_size);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+			    uma_memory_size);
+#endif
+	return 0;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("GIGABYTE MA785GM-US2H   Mainboard")
+	.enable_dev = ma785gm_enable,
+};
diff --git a/src/mainboard/gigabyte/ma785gm/mb_sysconf.h b/src/mainboard/gigabyte/ma785gm/mb_sysconf.h
new file mode 100644
index 0000000..8827fb6
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/mb_sysconf.h
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+	u8 bus_isa;
+	u8 bus_8132_0;
+	u8 bus_8132_1;
+	u8 bus_8132_2;
+	u8 bus_8111_0;
+	u8 bus_8111_1;
+	u8 bus_8132a[31][3];
+	u8 bus_8151[31][2];
+
+	u32 apicid_8111;
+	u32 apicid_8132_1;
+	u32 apicid_8132_2;
+	u32 apicid_8132a[31][2];
+	u32 sbdn3;
+	u32 sbdn3a[31];
+	u32 sbdn5[31];
+ 	u32 bus_type[256];
+};
+
+#endif
+
diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c
new file mode 100644
index 0000000..4bf3480
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/mptable.c
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern u8 bus_rs780[11];
+extern u8 bus_sb700[2];
+
+extern u32 apicid_sb700;
+
+extern u32 sbdn_rs780;
+extern u32 sbdn_sb700;
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	int bus_isa;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LAPIC_ADDR);
+
+	smp_write_processors(mc);
+
+	get_bus_conf();
+
+	mptable_write_buses(mc, NULL, &bus_isa);
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	{
+		device_t dev;
+		u32 dword;
+		u8 byte;
+
+		dev =
+		    dev_find_slot(bus_sb700[0],
+				  PCI_DEVFN(sbdn_sb700 + 0x14, 0));
+		if (dev) {
+			dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+			smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+
+			/* Initialize interrupt mapping */
+			/* aza */
+			byte = pci_read_config8(dev, 0x63);
+			byte &= 0xf8;
+			byte |= 0;	/* 0: INTA, ...., 7: INTH */
+			pci_write_config8(dev, 0x63, byte);
+
+			/* SATA */
+			dword = pci_read_config32(dev, 0xac);
+			dword &= ~(7 << 26);
+			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
+			/* dword |= 1<<22; PIC and APIC co exists */
+			pci_write_config32(dev, 0xac, dword);
+
+			/*
+			 * 00:12.0: PROG SATA : INT F
+			 * 00:13.0: INTA USB_0
+			 * 00:13.1: INTB USB_1
+			 * 00:13.2: INTC USB_2
+			 * 00:13.3: INTD USB_3
+			 * 00:13.4: INTC USB_4
+			 * 00:13.5: INTD USB2
+			 * 00:14.1: INTA IDE
+			 * 00:14.2: Prog HDA : INT E
+			 * 00:14.5: INTB ACI
+			 * 00:14.6: INTB MCI
+			 */
+		}
+	}
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#if CONFIG_GENERATE_ACPI_TABLES == 0
+#define PCI_INT(bus, dev, fn, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
+
+	/* usb */
+	PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, 0x11);
+	PCI_INT(0x0, 0x13, 0x0, 0x12);
+	PCI_INT(0x0, 0x13, 0x1, 0x13);
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, 0x16);
+
+	/* HD Audio: b0:d20:f1:reg63 should be 0. */
+	/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
+
+	/* on board NIC & Slot PCIE.  */
+	/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
+/* 	PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
+	PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
+	/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
+	PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
+	/* configuration B doesnt need dev 5,6,7 */
+	/*
+	 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
+	 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
+	 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
+	 */
+	PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
+	PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c
new file mode 100644
index 0000000..7a3631b
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/resourcemap.c
@@ -0,0 +1,281 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration regin i
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+	};
+
+	int max;
+	max = ARRAY_SIZE(register_values);
+	setup_resource_map(register_values, max);
+}
+
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
new file mode 100644
index 0000000..4572169
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -0,0 +1,256 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+//#define SYSTEM_TYPE 0	/* SERVER */
+#define SYSTEM_TYPE 1	/* DESKTOP */
+//#define SYSTEM_TYPE 2	/* MOBILE */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <cpu/amd/model_10xxx_rev.h>
+#include "northbridge/amd/amdfam10/raminit.h"
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdfam10/reset_test.c"
+#include <console/loglevel.h>
+#include "cpu/x86/bist.h"
+#include "superio/ite/it8718f/early_serial.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
+#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+#include "northbridge/amd/amdfam10/debug.c"
+
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
+
+static int spd_read_byte(u32 device, u32 address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/pci.c"
+#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
+#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
+#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "northbridge/amd/amdfam10/early_ht.c"
+#include <spd.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
+	u32 bsp_apicid = 0, val;
+	msr_t msr;
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		/* mov bsp to bus 0xff when > 8 nodes */
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+		sb7xx_51xx_pci_port80();
+	}
+
+	post_code(0x30);
+
+	if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
+		/* All cores run this but the BSP(node0,core0) is the only core that returns. */
+	}
+
+	post_code(0x32);
+
+	enable_rs780_dev8();
+	sb7xx_51xx_lpc_init();
+
+	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+	it8718f_disable_reboot();
+	console_init();
+
+//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+	printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	/* Setup sysinfo defaults */
+	set_sysinfo_in_ram(0);
+
+#if CONFIG_UPDATE_CPU_MICROCODE
+	update_microcode(val);
+#endif
+	post_code(0x33);
+
+	cpuSetAMDMSR();
+	post_code(0x34);
+
+	amd_ht_init(sysinfo);
+	post_code(0x35);
+
+	/* Setup nodes PCI space and start core 0 AP init. */
+	finalize_node_setup(sysinfo);
+
+	/* Setup any mainboard PCI settings etc. */
+	setup_mb_resource_map();
+	post_code(0x36);
+
+	/* wait for all the APs core0 started by finalize_node_setup. */
+	/* FIXME: A bunch of cores are going to start output to serial at once.
+	   It would be nice to fixup prink spinlocks for ROM XIP mode.
+	   I think it could be done by putting the spinlock flag in the cache
+	   of the BSP located right after sysinfo.
+	 */
+	wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* Core0 on each node is configured. Now setup any additional cores. */
+	printk(BIOS_DEBUG, "start_other_cores()\n");
+	start_other_cores();
+	post_code(0x37);
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+
+	post_code(0x38);
+
+	/* run _early_setup before soft-reset. */
+	rs780_early_setup();
+	sb7xx_51xx_early_setup();
+
+#if CONFIG_SET_FIDVID
+	msr = rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+
+	/* FIXME: The sb fid change may survive the warm reset and only
+	   need to be done once.*/
+	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+	post_code(0x39);
+
+	if (!warm_reset_detect(0)) {			// BSP is node 0
+		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+	} else {
+		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
+	}
+
+	post_code(0x3A);
+
+	/* show final fid and vid */
+	msr=rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+#endif
+
+	rs780_htinit();
+
+	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+	if (!warm_reset_detect(0)) {
+		print_info("...WARM RESET...\n\n\n");
+		soft_reset();
+		die("After soft_reset_x - shouldn't see this message!!!\n");
+	}
+
+	post_code(0x3B);
+
+	/* It's the time to set ctrl in sysinfo now; */
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+	post_code(0x40);
+
+//	die("Die Before MCT init.");
+
+	printk(BIOS_DEBUG, "raminit_amdmct()\n");
+	raminit_amdmct(sysinfo);
+	post_code(0x41);
+
+/*
+	dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
+*/
+
+//	die("After MCT init before CAR disabled.");
+
+	rs780_before_pci_init();
+	sb7xx_51xx_before_pci_init();
+
+	post_code(0x42);
+	printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
+	post_code(0x43);	// Should never see this post code.
+}
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}


From gerrit at coreboot.org  Thu Dec  8 10:42:40 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 8 Dec 2011 10:42:40 +0100
Subject: [coreboot] Patch merged into coreboot/master: 9716e82 Fix ldscript
	for bootblock .rom section
References: <Ic2a43981836a0873b50abecfcad2def7b6586a5d+0@gerrit.coreboot.org>
Message-ID: <E1RYaUy-0007QI-UH@ra.coresystems.de>

the following patch was just integrated into master:
commit 9716e822a4a7442dcb781aa9b2fda2a35b1d531f
Author: Ky??sti M??lkki <kyosti.malkki at gmail.com>
Date:   Wed Nov 23 16:33:12 2011 +0200

    Fix ldscript for bootblock .rom section
    
    Allocation size for the section was miscalculated, so the section
    did not honour its upper-bound address.
    
    Also align the section start to 4 bytes, so it starts with code
    instead of pad bytes.
    
    Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d
    Signed-off-by: Ky??sti M??lkki <kyosti.malkki at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Thu Dec  8 10:42:39 2011, giving +2
See http://review.coreboot.org/453 for details.

-gerrit


From gerrit at coreboot.org  Thu Dec  8 15:39:39 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Thu, 8 Dec 2011 15:39:39 +0100
Subject: [coreboot] New patch to review for coreboot: 9f7c092 libpayload:
	remove uhci_reg_maskX
References: <Id0eb8327293831e54249d43fd06d50963c793699+0@gerrit.coreboot.org>
Message-ID: <Id0eb8327293831e54249d43fd06d50963c793699+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/477

-gerrit

commit 9f7c092cc6dc9101fcc3db20914b0efb69686e84
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Fri Nov 18 14:44:16 2011 +0100

    libpayload: remove uhci_reg_maskX
    
    Not that good an idea to start with.
    
    Coccinelle patch:
    @@
    @@
    -void
    (
    -uhci_reg_mask8
    |
    -uhci_reg_mask16
    |
    -uhci_reg_mask32
    )
    - (...) { ... }
    
    @@
    @@
    -void
    (
    -uhci_reg_mask8
    |
    -uhci_reg_mask16
    |
    -uhci_reg_mask32
    )
    - (...);
    
    @@
    expression ctrl, reg, ormask;
    @@
    -uhci_reg_mask32 (ctrl, reg, ~0, ormask)
    +uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) | ormask)
    
    @@
    expression ctrl, reg, ormask;
    @@
    -uhci_reg_mask16 (ctrl, reg, ~0, ormask)
    +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) | ormask)
    
    @@
    expression ctrl, reg, ormask;
    @@
    -uhci_reg_mask8 (ctrl, reg, ~0, ormask)
    +uhci_reg_write8 (ctrl, reg, uhci_reg_read8 (ctrl, reg) | ormask)
    
    @@
    expression ctrl, reg, andmask;
    @@
    -uhci_reg_mask32 (ctrl, reg, andmask, 0)
    +uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) & andmask)
    
    @@
    expression ctrl, reg, andmask;
    @@
    -uhci_reg_mask16 (ctrl, reg, andmask, 0)
    +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask)
    
    @@
    expression ctrl, reg, andmask;
    @@
    -uhci_reg_mask16 (ctrl, reg, andmask, 0)
    +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask)
    
    Change-Id: Id0eb8327293831e54249d43fd06d50963c793699
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 payloads/libpayload/drivers/usb/uhci.c         |   36 ++++++-----------------
 payloads/libpayload/drivers/usb/uhci_private.h |    3 --
 payloads/libpayload/drivers/usb/uhci_rh.c      |   18 ++++++++----
 3 files changed, 22 insertions(+), 35 deletions(-)

diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c
index 779098b..b964ee7 100644
--- a/payloads/libpayload/drivers/usb/uhci.c
+++ b/payloads/libpayload/drivers/usb/uhci.c
@@ -120,7 +120,8 @@ uhci_reset (hci_t *controller)
 	/* reset framelist index */
 	uhci_reg_write16 (controller, FRNUM, 0);
 
-	uhci_reg_mask16 (controller, USBCMD, ~0, 0xc0);	// max packets, configure flag
+	uhci_reg_write16(controller, USBCMD,
+			 uhci_reg_read16(controller, USBCMD) | 0xc0);	// max packets, configure flag
 
 	uhci_start (controller);
 }
@@ -240,7 +241,8 @@ uhci_shutdown (hci_t *controller)
 	detach_controller (controller);
 	UHCI_INST (controller)->roothub->destroy (UHCI_INST (controller)->
 						  roothub);
-	uhci_reg_mask16 (controller, USBCMD, 0, 0);	// stop work
+	uhci_reg_write16(controller, USBCMD,
+			 uhci_reg_read16(controller, USBCMD) & 0);	// stop work
 	free (UHCI_INST (controller)->framelistptr);
 	free (UHCI_INST (controller)->qh_prei);
 	free (UHCI_INST (controller)->qh_intr);
@@ -253,13 +255,15 @@ uhci_shutdown (hci_t *controller)
 static void
 uhci_start (hci_t *controller)
 {
-	uhci_reg_mask16 (controller, USBCMD, ~0, 1);	// start work on schedule
+	uhci_reg_write16(controller, USBCMD,
+			 uhci_reg_read16(controller, USBCMD) | 1);	// start work on schedule
 }
 
 static void
 uhci_stop (hci_t *controller)
 {
-	uhci_reg_mask16 (controller, USBCMD, ~1, 0);	// stop work on schedule
+	uhci_reg_write16(controller, USBCMD,
+			 uhci_reg_read16(controller, USBCMD) & ~1);	// stop work on schedule
 }
 
 #define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
@@ -274,7 +278,8 @@ wait_for_completed_qh (hci_t *controller, qh_t *qh)
 			current = GET_TD (qh->elementlinkptr.ptr);
 			timeout = 1000000;
 		}
-		uhci_reg_mask16 (controller, USBSTS, ~0, 0);	// clear resettable registers
+		uhci_reg_write16(controller, USBSTS,
+				 uhci_reg_read16(controller, USBSTS) | 0);	// clear resettable registers
 		udelay (30);
 	}
 	return (GET_TD (qh->elementlinkptr.ptr) ==
@@ -636,24 +641,3 @@ uhci_reg_read8 (hci_t *ctrl, usbreg reg)
 {
 	return inb (ctrl->reg_base + reg);
 }
-
-void
-uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask)
-{
-	uhci_reg_write32 (ctrl, reg,
-			  (uhci_reg_read32 (ctrl, reg) & andmask) | ormask);
-}
-
-void
-uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask)
-{
-	uhci_reg_write16 (ctrl, reg,
-			  (uhci_reg_read16 (ctrl, reg) & andmask) | ormask);
-}
-
-void
-uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask)
-{
-	uhci_reg_write8 (ctrl, reg,
-			 (uhci_reg_read8 (ctrl, reg) & andmask) | ormask);
-}
diff --git a/payloads/libpayload/drivers/usb/uhci_private.h b/payloads/libpayload/drivers/usb/uhci_private.h
index 877592a..adcd91c 100644
--- a/payloads/libpayload/drivers/usb/uhci_private.h
+++ b/payloads/libpayload/drivers/usb/uhci_private.h
@@ -104,9 +104,6 @@ typedef struct {
      u16 uhci_reg_read16 (hci_t *ctrl, usbreg reg);
      void uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value);
      u8 uhci_reg_read8 (hci_t *ctrl, usbreg reg);
-     void uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask);
-     void uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask);
-     void uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask);
 
      typedef struct uhci {
 	     flistp_t *framelistptr;
diff --git a/payloads/libpayload/drivers/usb/uhci_rh.c b/payloads/libpayload/drivers/usb/uhci_rh.c
index 53b32f6..5074099 100644
--- a/payloads/libpayload/drivers/usb/uhci_rh.c
+++ b/payloads/libpayload/drivers/usb/uhci_rh.c
@@ -53,14 +53,18 @@ uhci_rh_enable_port (usbdev_t *dev, int port)
 		return;
 	}
 
-	uhci_reg_mask16 (controller, port, ~(1 << 12), 0);	/* wakeup */
+	uhci_reg_write16(controller, port,
+			 uhci_reg_read16(controller, port) & ~(1 << 12));	/* wakeup */
 
-	uhci_reg_mask16 (controller, port, ~0, 1 << 9);	/* reset */
+	uhci_reg_write16(controller, port,
+			 uhci_reg_read16(controller, port) | 1 << 9);	/* reset */
 	mdelay (30);		// >10ms
-	uhci_reg_mask16 (controller, port, ~(1 << 9), 0);
+	uhci_reg_write16(controller, port,
+			 uhci_reg_read16(controller, port) & ~(1 << 9));
 	mdelay (1);		// >5.3us per spec, <3ms because some devices make trouble
 
-	uhci_reg_mask16 (controller, port, ~0, 1 << 2);	/* enable */
+	uhci_reg_write16(controller, port,
+			 uhci_reg_read16(controller, port) | 1 << 2);	/* enable */
 	do {
 		value = uhci_reg_read16 (controller, port);
 		mdelay (1);
@@ -75,7 +79,8 @@ uhci_rh_disable_port (usbdev_t *dev, int port)
 	port = PORTSC2;
 	if (port == 1)
 		port = PORTSC1;
-	uhci_reg_mask16 (controller, port, ~4, 0);
+	uhci_reg_write16(controller, port,
+			 uhci_reg_read16(controller, port) & ~4);
 	int value;
 	do {
 		value = uhci_reg_read16 (controller, port);
@@ -102,7 +107,8 @@ uhci_rh_scanport (usbdev_t *dev, int port)
 		usb_detach_device(dev->controller, devno);
 		RH_INST (dev)->port[offset] = -1;
 	}
-	uhci_reg_mask16 (dev->controller, portsc, ~0, (1 << 3) | (1 << 2));	// clear port state change, enable port
+	uhci_reg_write16(dev->controller, portsc,
+			 uhci_reg_read16(dev->controller, portsc) | (1 << 3) | (1 << 2));	// clear port state change, enable port
 
 	mdelay(100); // wait for signal to stabilize
 


From gerrit at coreboot.org  Thu Dec  8 15:39:40 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Thu, 8 Dec 2011 15:39:40 +0100
Subject: [coreboot] New patch to review for coreboot: c10f527 libpayload:
	Remove bitfield use from UHCI data structures
References: <I1b2bcda28c52ad10bbe9429e04d126b555f7828a+0@gerrit.coreboot.org>
Message-ID: <I1b2bcda28c52ad10bbe9429e04d126b555f7828a+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/478

-gerrit

commit c10f52730fcfd22693cea27d6cc0fbf66000d8e2
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Nov 24 11:55:46 2011 +0100

    libpayload: Remove bitfield use from UHCI data structures
    
    We agreed that bitfields are a Bad Idea[tm].
    
    Change-Id: I1b2bcda28c52ad10bbe9429e04d126b555f7828a
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 payloads/libpayload/drivers/usb/uhci.c         |  250 ++++++++++--------------
 payloads/libpayload/drivers/usb/uhci_private.h |   73 +++-----
 2 files changed, 133 insertions(+), 190 deletions(-)

diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c
index b964ee7..07a0742 100644
--- a/payloads/libpayload/drivers/usb/uhci.c
+++ b/payloads/libpayload/drivers/usb/uhci.c
@@ -66,7 +66,7 @@ td_dump (td_t *td)
 {
 	char td_value[3];
 	const char *td_type;
-	switch (td->pid) {
+	switch (td->token & TD_PID_MASK) {
 		case UHCI_SETUP:
 			td_type="SETUP";
 			break;
@@ -77,23 +77,24 @@ td_dump (td_t *td)
 			td_type="OUT";
 			break;
 		default:
-			sprintf(td_value, "%x", td->pid);
+			sprintf(td_value, "%x", td->token & TD_PID_MASK);
 			td_type=td_value;
 	}
 	debug ("%s packet (at %lx) to %x.%x failed\n", td_type,
-		virt_to_phys (td), td->dev_addr, td->endp);
-	debug ("td (counter at %x) returns: ", td->counter);
-	debug (" bitstuff err: %x, ", td->status_bitstuff_err);
-	debug (" CRC err: %x, ", td->status_crc_err);
-	debug (" NAK rcvd: %x, ", td->status_nakrcvd);
-	debug (" Babble: %x, ", td->status_babble);
-	debug (" Data Buffer err: %x, ", td->status_databuf_err);
-	debug (" Stalled: %x, ", td->status_stalled);
-	debug (" Active: %x\n", td->status_active);
-	if (td->status_babble)
+		virt_to_phys (td), (td->token & TD_DEVADDR_MASK) >> TD_DEVADDR_SHIFT,
+		(td->token & TD_EP_MASK) >> TD_EP_SHIFT);
+	debug ("td (counter at %x) returns: ", td->ctrlsts >> TD_COUNTER_SHIFT);
+	debug (" bitstuff err: %x, ", !!(td->ctrlsts & TD_STATUS_BITSTUFF_ERR));
+	debug (" CRC err: %x, ", !!(td->ctrlsts & TD_STATUS_CRC_ERR));
+	debug (" NAK rcvd: %x, ", !!(td->ctrlsts & TD_STATUS_NAK_RCVD));
+	debug (" Babble: %x, ", !!(td->ctrlsts & TD_STATUS_BABBLE));
+	debug (" Data Buffer err: %x, ", !!(td->ctrlsts & TD_STATUS_DATABUF_ERR));
+	debug (" Stalled: %x, ", !!(td->ctrlsts & TD_STATUS_STALLED));
+	debug (" Active: %x\n", !!(td->ctrlsts & TD_STATUS_ACTIVE));
+	if (td->ctrlsts & TD_STATUS_BABBLE)
 		debug (" Babble because of %s\n",
-			td->status_bitstuff_err ? "host" : "device");
-	if (td->status_active)
+			(td->ctrlsts & TD_STATUS_BITSTUFF_ERR) ? "host" : "device");
+	if (td->ctrlsts & TD_STATUS_ACTIVE)
 		debug (" still active - timeout?\n");
 }
 
@@ -197,34 +198,24 @@ uhci_init (pcidev_t addr)
 	    ! UHCI_INST (controller)->qh_last)
 		fatal("Not enough memory for USB controller queues.\n");
 
-	UHCI_INST (controller)->qh_prei->headlinkptr.ptr =
-		virt_to_phys (UHCI_INST (controller)->qh_intr);
-	UHCI_INST (controller)->qh_prei->headlinkptr.queue_head = 1;
-	UHCI_INST (controller)->qh_prei->elementlinkptr.ptr = 0;
-	UHCI_INST (controller)->qh_prei->elementlinkptr.terminate = 1;
-
-	UHCI_INST (controller)->qh_intr->headlinkptr.ptr =
-		virt_to_phys (UHCI_INST (controller)->qh_data);
-	UHCI_INST (controller)->qh_intr->headlinkptr.queue_head = 1;
-	UHCI_INST (controller)->qh_intr->elementlinkptr.ptr = 0;
-	UHCI_INST (controller)->qh_intr->elementlinkptr.terminate = 1;
-
-	UHCI_INST (controller)->qh_data->headlinkptr.ptr =
-		virt_to_phys (UHCI_INST (controller)->qh_last);
-	UHCI_INST (controller)->qh_data->headlinkptr.queue_head = 1;
-	UHCI_INST (controller)->qh_data->elementlinkptr.ptr = 0;
-	UHCI_INST (controller)->qh_data->elementlinkptr.terminate = 1;
-
-	UHCI_INST (controller)->qh_last->headlinkptr.ptr = virt_to_phys (UHCI_INST (controller)->qh_data);
-	UHCI_INST (controller)->qh_last->headlinkptr.terminate = 1;
-	UHCI_INST (controller)->qh_last->elementlinkptr.ptr = virt_to_phys (antiberserk);
-	UHCI_INST (controller)->qh_last->elementlinkptr.terminate = 1;
+	UHCI_INST (controller)->qh_prei->headlinkptr =
+		virt_to_phys (UHCI_INST (controller)->qh_intr) | FLISTP_QH;
+	UHCI_INST (controller)->qh_prei->elementlinkptr = 0 | FLISTP_TERMINATE;
+
+	UHCI_INST (controller)->qh_intr->headlinkptr =
+		virt_to_phys (UHCI_INST (controller)->qh_data) | FLISTP_QH;
+	UHCI_INST (controller)->qh_intr->elementlinkptr = 0 | FLISTP_TERMINATE;
+
+	UHCI_INST (controller)->qh_data->headlinkptr =
+		virt_to_phys (UHCI_INST (controller)->qh_last) | FLISTP_QH;
+	UHCI_INST (controller)->qh_data->elementlinkptr = 0 | FLISTP_TERMINATE;
+
+	UHCI_INST (controller)->qh_last->headlinkptr = virt_to_phys (UHCI_INST (controller)->qh_data) | FLISTP_TERMINATE;
+	UHCI_INST (controller)->qh_last->elementlinkptr = virt_to_phys (antiberserk) | FLISTP_TERMINATE;
 
 	for (i = 0; i < 1024; i++) {
-		UHCI_INST (controller)->framelistptr[i].ptr =
-			virt_to_phys (UHCI_INST (controller)->qh_prei);
-		UHCI_INST (controller)->framelistptr[i].terminate = 0;
-		UHCI_INST (controller)->framelistptr[i].queue_head = 1;
+		UHCI_INST (controller)->framelistptr[i] =
+			virt_to_phys (UHCI_INST (controller)->qh_prei) | FLISTP_QH;
 	}
 	controller->devices[0]->controller = controller;
 	controller->devices[0]->init = uhci_rh_init;
@@ -272,18 +263,18 @@ static td_t *
 wait_for_completed_qh (hci_t *controller, qh_t *qh)
 {
 	int timeout = 1000000;	/* max 30 ms. */
-	void *current = GET_TD (qh->elementlinkptr.ptr);
-	while ((qh->elementlinkptr.terminate == 0) && (timeout-- > 0)) {
-		if (current != GET_TD (qh->elementlinkptr.ptr)) {
-			current = GET_TD (qh->elementlinkptr.ptr);
+	void *current = GET_TD (qh->elementlinkptr);
+	while (((qh->elementlinkptr & FLISTP_TERMINATE) == 0) && (timeout-- > 0)) {
+		if (current != GET_TD (qh->elementlinkptr)) {
+			current = GET_TD (qh->elementlinkptr);
 			timeout = 1000000;
 		}
 		uhci_reg_write16(controller, USBSTS,
 				 uhci_reg_read16(controller, USBSTS) | 0);	// clear resettable registers
 		udelay (30);
 	}
-	return (GET_TD (qh->elementlinkptr.ptr) ==
-		0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr.ptr));
+	return (GET_TD (qh->elementlinkptr) ==
+		0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr));
 }
 
 static int
@@ -314,57 +305,51 @@ uhci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen
 	memset (tds, 0, sizeof (td_t) * count);
 	count--;		/* to compensate for 0-indexed array */
 	for (i = 0; i < count; i++) {
-		tds[i].ptr = virt_to_phys (&tds[i + 1]);
-		tds[i].depth_first = 1;
-		tds[i].terminate = 0;
+		tds[i].ptr = virt_to_phys (&tds[i + 1]) | TD_DEPTH_FIRST;
 	}
-	tds[count].ptr = 0;
-	tds[count].depth_first = 1;
-	tds[count].terminate = 1;
-
-	tds[0].pid = UHCI_SETUP;
-	tds[0].dev_addr = dev->address;
-	tds[0].endp = endp;
-	tds[0].maxlen = maxlen (drlen);
-	tds[0].counter = 3;
-	tds[0].data_toggle = 0;
-	tds[0].lowspeed = dev->speed;
+	tds[count].ptr = 0 | TD_DEPTH_FIRST | TD_TERMINATE;
+
+	tds[0].token = UHCI_SETUP |
+		dev->address << TD_DEVADDR_SHIFT |
+		endp << TD_EP_SHIFT |
+		TD_TOGGLE_DATA0 |
+		maxlen(drlen) << TD_MAXLEN_SHIFT;
 	tds[0].bufptr = virt_to_phys (devreq);
-	tds[0].status_active = 1;
+	tds[0].ctrlsts = (3 << TD_COUNTER_SHIFT) |
+		(dev->speed?TD_LOWSPEED:0) |
+		TD_STATUS_ACTIVE;
 
 	int toggle = 1;
 	for (i = 1; i < count; i++) {
 		switch (dir) {
-			case SETUP: tds[i].pid = UHCI_SETUP; break;
-			case IN:    tds[i].pid = UHCI_IN;    break;
-			case OUT:   tds[i].pid = UHCI_OUT;   break;
+			case SETUP: tds[i].token = UHCI_SETUP; break;
+			case IN:    tds[i].token = UHCI_IN;    break;
+			case OUT:   tds[i].token = UHCI_OUT;   break;
 		}
-		tds[i].dev_addr = dev->address;
-		tds[i].endp = endp;
-		tds[i].maxlen = maxlen (min (mlen, dalen));
-		tds[i].counter = 3;
-		tds[i].data_toggle = toggle;
-		tds[i].lowspeed = dev->speed;
+		tds[i].token |= dev->address << TD_DEVADDR_SHIFT |
+			endp << TD_EP_SHIFT |
+			maxlen (min (mlen, dalen)) << TD_MAXLEN_SHIFT |
+			toggle << TD_TOGGLE_SHIFT;
 		tds[i].bufptr = virt_to_phys (data);
-		tds[i].status_active = 1;
+		tds[i].ctrlsts = (3 << TD_COUNTER_SHIFT) |
+			(dev->speed?TD_LOWSPEED:0) |
+			TD_STATUS_ACTIVE;
 		toggle ^= 1;
 		dalen -= mlen;
 		data += mlen;
 	}
 
-	tds[count].pid = (dir == OUT) ? UHCI_IN : UHCI_OUT;
-	tds[count].dev_addr = dev->address;
-	tds[count].endp = endp;
-	tds[count].maxlen = maxlen (0);
-	tds[count].counter = 0;	/* as per linux 2.4.10 */
-	tds[count].data_toggle = 1;
-	tds[count].lowspeed = dev->speed;
+	tds[count].token = (dir == OUT) ? UHCI_IN : UHCI_OUT |
+		dev->address << TD_DEVADDR_SHIFT |
+		endp << TD_EP_SHIFT |
+		maxlen(0) << TD_MAXLEN_SHIFT |
+		TD_TOGGLE_DATA1;
 	tds[count].bufptr = 0;
-	tds[count].status_active = 1;
-	UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
-		virt_to_phys (tds);
-	UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
-	UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
+	tds[0].ctrlsts = (0 << TD_COUNTER_SHIFT) | /* as Linux 2.4.10 does */
+		(dev->speed?TD_LOWSPEED:0) |
+		TD_STATUS_ACTIVE;
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr =
+		virt_to_phys (tds) & ~(FLISTP_QH | FLISTP_TERMINATE);
 	td_t *td = wait_for_completed_qh (dev->controller,
 					  UHCI_INST (dev->controller)->
 					  qh_data);
@@ -389,15 +374,9 @@ create_schedule (int numpackets)
 	memset (tds, 0, sizeof (td_t) * numpackets);
 	int i;
 	for (i = 0; i < numpackets; i++) {
-		tds[i].ptr = virt_to_phys (&tds[i + 1]);
-		tds[i].terminate = 0;
-		tds[i].queue_head = 0;
-		tds[i].depth_first = 1;
+		tds[i].ptr = virt_to_phys (&tds[i + 1]) | TD_DEPTH_FIRST;
 	}
-	tds[numpackets - 1].ptr = 0;
-	tds[numpackets - 1].terminate = 1;
-	tds[numpackets - 1].queue_head = 0;
-	tds[numpackets - 1].depth_first = 0;
+	tds[numpackets - 1].ptr = 0 | TD_TERMINATE;
 	return tds;
 }
 
@@ -406,32 +385,26 @@ fill_schedule (td_t *td, endpoint_t *ep, int length, unsigned char *data,
 	       int *toggle)
 {
 	switch (ep->direction) {
-		case IN: td->pid = UHCI_IN; break;
-		case OUT: td->pid = UHCI_OUT; break;
-		case SETUP: td->pid = UHCI_SETUP; break;
+		case IN: td->token = UHCI_IN; break;
+		case OUT: td->token = UHCI_OUT; break;
+		case SETUP: td->token = UHCI_SETUP; break;
 	}
-	td->dev_addr = ep->dev->address;
-	td->endp = ep->endpoint & 0xf;
-	td->maxlen = maxlen (length);
-	if (ep->direction == SETUP)
-		td->counter = 3;
-	else
-		td->counter = 0;
-	td->data_toggle = *toggle & 1;
-	td->lowspeed = ep->dev->speed;
+	td->token |= ep->dev->address << TD_DEVADDR_SHIFT |
+		(ep->endpoint & 0xf) << TD_EP_SHIFT |
+		maxlen (length) << TD_MAXLEN_SHIFT |
+		(*toggle & 1) << TD_TOGGLE_SHIFT;
 	td->bufptr = virt_to_phys (data);
-
-	td->status_active = 1;
+	td->ctrlsts = ((ep->direction == SETUP?3:0) << TD_COUNTER_SHIFT) |
+		ep->dev->speed?TD_LOWSPEED:0 |
+		TD_STATUS_ACTIVE;
 	*toggle ^= 1;
 }
 
 static int
 run_schedule (usbdev_t *dev, td_t *td)
 {
-	UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
-		virt_to_phys (td);
-	UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
-	UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr =
+		virt_to_phys (td) | ~(FLISTP_QH | FLISTP_TERMINATE);
 	td = wait_for_completed_qh (dev->controller,
 				    UHCI_INST (dev->controller)->qh_data);
 	if (td == 0) {
@@ -493,9 +466,7 @@ uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming
 	if (!data || !tds || !qh)
 		fatal("Not enough memory to create USB intr queue prerequisites.\n");
 
-	qh->elementlinkptr.ptr = virt_to_phys(tds);
-	qh->elementlinkptr.queue_head = 0;
-	qh->elementlinkptr.terminate = 0;
+	qh->elementlinkptr = virt_to_phys(tds);
 
 	intr_q *q = malloc(sizeof(intr_q));
 	if (!q)
@@ -512,37 +483,28 @@ uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming
 	int i;
 	for (i = 0; i < reqcount; i++) {
 		tds[i].ptr = virt_to_phys (&tds[i + 1]);
-		tds[i].terminate = 0;
-		tds[i].queue_head = 0;
-		tds[i].depth_first = 0;
 
 		switch (ep->direction) {
-			case IN: tds[i].pid = UHCI_IN; break;
-			case OUT: tds[i].pid = UHCI_OUT; break;
-			case SETUP: tds[i].pid = UHCI_SETUP; break;
+			case IN: tds[i].token = UHCI_IN; break;
+			case OUT: tds[i].token = UHCI_OUT; break;
+			case SETUP: tds[i].token = UHCI_SETUP; break;
 		}
-		tds[i].dev_addr = ep->dev->address;
-		tds[i].endp = ep->endpoint & 0xf;
-		tds[i].maxlen = maxlen (reqsize);
-		tds[i].counter = 0;
-		tds[i].data_toggle = ep->toggle & 1;
-		tds[i].lowspeed = ep->dev->speed;
+		tds[i].token |= ep->dev->address << TD_DEVADDR_SHIFT |
+			(ep->endpoint & 0xf) << TD_EP_SHIFT |
+			maxlen (reqsize) << TD_MAXLEN_SHIFT |
+			(ep->toggle & 1) << TD_TOGGLE_SHIFT;
 		tds[i].bufptr = virt_to_phys (data);
-		tds[i].status_active = 1;
+		tds[i].ctrlsts = (0 << TD_COUNTER_SHIFT) |
+			ep->dev->speed?TD_LOWSPEED:0 |
+			TD_STATUS_ACTIVE;
 		ep->toggle ^= 1;
 		data += reqsize;
 	}
-	tds[reqcount - 1].ptr = 0;
-	tds[reqcount - 1].terminate = 1;
-	tds[reqcount - 1].queue_head = 0;
-	tds[reqcount - 1].depth_first = 0;
+	tds[reqcount - 1].ptr = 0 | TD_TERMINATE;
 	for (i = reqtiming; i < 1024; i += reqtiming) {
 		/* FIXME: wrap in another qh, one for each occurance of the qh in the framelist */
-		qh->headlinkptr.ptr = UHCI_INST (ep->dev->controller)->framelistptr[i].ptr;
-		qh->headlinkptr.terminate = 0;
-		UHCI_INST (ep->dev->controller)->framelistptr[i].ptr = virt_to_phys(qh);
-		UHCI_INST (ep->dev->controller)->framelistptr[i].terminate = 0;
-		UHCI_INST (ep->dev->controller)->framelistptr[i].queue_head = 1;
+		qh->headlinkptr = UHCI_INST (ep->dev->controller)->framelistptr[i] & ~FLISTP_TERMINATE;
+		UHCI_INST (ep->dev->controller)->framelistptr[i] = virt_to_phys(qh) | FLISTP_QH;
 	}
 	return q;
 }
@@ -557,15 +519,15 @@ uhci_destroy_intr_queue (endpoint_t *ep, void *q_)
 	int i;
 	for (i=0; i<1024; i++) {
 		u32 oldptr = 0;
-		u32 ptr = UHCI_INST (ep->dev->controller)->framelistptr[i].ptr;
+		u32 ptr = UHCI_INST (ep->dev->controller)->framelistptr[i];
 		while (ptr != end) {
-			if (((qh_t*)phys_to_virt(ptr))->elementlinkptr.ptr == val) {
-				((qh_t*)phys_to_virt(oldptr))->headlinkptr.ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr.ptr;
+			if (((qh_t*)phys_to_virt(ptr))->elementlinkptr == val) {
+				((qh_t*)phys_to_virt(oldptr))->headlinkptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr;
 				free(phys_to_virt(ptr));
 				break;
 			}
 			oldptr = ptr;
-			ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr.ptr;
+			ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr;
 		}
 	}
 	free(q->data);
@@ -582,7 +544,7 @@ static u8*
 uhci_poll_intr_queue (void *q_)
 {
 	intr_q *q = (intr_q*)q_;
-	if (q->tds[q->lastread].status_active == 0) {
+	if ((q->tds[q->lastread].ctrlsts & TD_STATUS_ACTIVE) == 0) {
 		/* FIXME: handle errors */
 		int current = q->lastread;
 		int previous;
@@ -591,15 +553,13 @@ uhci_poll_intr_queue (void *q_)
 		} else {
 			previous = q->lastread - 1;
 		}
-		q->tds[previous].status = 0;
-		q->tds[previous].ptr = 0;
-		q->tds[previous].terminate = 1;
+		q->tds[previous].ctrlsts &= ~TD_STATUS_MASK;
+		q->tds[previous].ptr = 0 | TD_TERMINATE;
 		if (q->last_td != &q->tds[previous]) {
-			q->last_td->ptr = virt_to_phys(&q->tds[previous]);
-			q->last_td->terminate = 0;
+			q->last_td->ptr = virt_to_phys(&q->tds[previous]) & ~TD_TERMINATE;
 			q->last_td = &q->tds[previous];
 		}
-		q->tds[previous].status_active = 1;
+		q->tds[previous].ctrlsts |= TD_STATUS_ACTIVE;
 		q->lastread = (q->lastread + 1) % q->total;
 		return &q->data[current*q->reqsize];
 	}
diff --git a/payloads/libpayload/drivers/usb/uhci_private.h b/payloads/libpayload/drivers/usb/uhci_private.h
index adcd91c..f650c4a 100644
--- a/payloads/libpayload/drivers/usb/uhci_private.h
+++ b/payloads/libpayload/drivers/usb/uhci_private.h
@@ -32,55 +32,38 @@
 
 typedef enum { UHCI_SETUP = 0x2d, UHCI_IN = 0x69, UHCI_OUT = 0xe1 } uhci_pid_t;
 
-typedef union {
-	struct {
-		unsigned long terminate:1;
-		unsigned long queue_head:1;
-		unsigned long:2;
-		unsigned long ptr_part:28;
-	};
-	u32 ptr;
-} __attribute__ ((packed)) flistp_t;
+typedef u32 flistp_t;
+#define FLISTP_TERMINATE 1
+#define FLISTP_QH 2
 
 typedef struct {
-	union {
-		struct {
-			unsigned long terminate:1;
-			unsigned long queue_head:1;
-			unsigned long depth_first:1;
-			unsigned long:29;
-		} __attribute__ ((packed));
-		u32 ptr;
-	} __attribute__ ((packed));
+	u32 ptr;
+#define TD_TERMINATE 1
+#define TD_QH 2
+#define TD_DEPTH_FIRST 4
 
-	volatile unsigned long actlen:11;
-	volatile unsigned long:5;
-	union {
-		struct {
-			unsigned long:1;	// bit 0
-			unsigned long status_bitstuff_err:1;
-			unsigned long status_crc_err:1;
-			unsigned long status_nakrcvd:1;
-			unsigned long status_babble:1;
-			unsigned long status_databuf_err:1;
-			unsigned long status_stalled:1;
-			unsigned long status_active:1;	// bit 7
-		} __attribute__ ((packed));
-		unsigned char status;
-	} __attribute__ ((packed));
-	volatile unsigned long ioc:1;	/* interrupt on complete */
-	volatile unsigned long isochronous:1;
-	volatile unsigned long lowspeed:1;
-	volatile unsigned long counter:2;
-	volatile unsigned long shortpck:1;
-	volatile unsigned long:2;
+	u32 ctrlsts;
+#define TD_STATUS_MASK (0xff << 16)
+#define TD_STATUS_BITSTUFF_ERR (1 << 17)
+#define TD_STATUS_CRC_ERR (1 << 18)
+#define TD_STATUS_NAK_RCVD (1 << 19)
+#define TD_STATUS_BABBLE (1 << 20)
+#define TD_STATUS_DATABUF_ERR (1 << 21)
+#define TD_STATUS_STALLED (1 << 22)
+#define TD_STATUS_ACTIVE (1 << 23)
+#define TD_LOWSPEED (1 << 26)
+#define TD_COUNTER_SHIFT 27
 
-	unsigned long pid:8;
-	unsigned long dev_addr:7;
-	unsigned long endp:4;
-	unsigned long data_toggle:1;
-	unsigned long:1;
-	unsigned long maxlen:11;
+	u32 token;
+#define TD_PID_MASK 0xff
+#define TD_DEVADDR_SHIFT 8
+#define TD_DEVADDR_MASK (((1<<7)-1) << TD_DEVADDR_SHIFT)
+#define TD_EP_SHIFT 15
+#define TD_EP_MASK (0xf << TD_EP_SHIFT)
+#define TD_TOGGLE_SHIFT 19
+#define TD_MAXLEN_SHIFT 21
+#define TD_TOGGLE_DATA0 0
+#define TD_TOGGLE_DATA1 (1 << TD_TOGGLE_SHIFT)
 
 	u32 bufptr;
 


From gerrit at coreboot.org  Thu Dec  8 15:39:46 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Thu, 8 Dec 2011 15:39:46 +0100
Subject: [coreboot] New patch to review for coreboot: 8f5c7b3 libpayload:
	Remove bitfield use from OHCI data structures
References: <Ic04f151091c359912835b8b3db488d2d41bd4bbb+0@gerrit.coreboot.org>
Message-ID: <Ic04f151091c359912835b8b3db488d2d41bd4bbb+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/479

-gerrit

commit 8f5c7b3a920532a36375705092ad1edd27599326
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Nov 24 09:12:11 2011 +0100

    libpayload: Remove bitfield use from OHCI data structures
    
    We agreed that bitfields are a Bad Idea[tm].
    
    Change-Id: Ic04f151091c359912835b8b3db488d2d41bd4bbb
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 payloads/libpayload/drivers/usb/ohci.c         |   83 +++++++++++-------------
 payloads/libpayload/drivers/usb/ohci_private.h |   62 ++++++++----------
 2 files changed, 65 insertions(+), 80 deletions(-)

diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c
index 60866d8..4095d69 100644
--- a/payloads/libpayload/drivers/usb/ohci.c
+++ b/payloads/libpayload/drivers/usb/ohci.c
@@ -188,7 +188,8 @@ dump_td(td_t *cur, int level)
 #ifdef USB_DEBUG
 	static const char *spaces="          ";
 	const char *spc=spaces+(10-level);
-	debug("%std at %x (%s), condition code: %s\n", spc, cur, direction[cur->direction], completion_codes[cur->condition_code & 0xf]);
+	debug("%std at %x (%s), condition code: %s\n", spc, cur, direction[(cur->config & TD_DIRECTION_MASK) >> TD_DIRECTION_SHIFT],
+		completion_codes[(cur->config & TD_CC_MASK) >> TD_CC_SHIFT]);
 	debug("%s toggle: %x\n", spc, cur->toggle);
 #endif
 }
@@ -201,7 +202,7 @@ wait_for_ed(usbdev_t *dev, ed_t *head)
 	/* wait for results */
 	while (((head->head_pointer & ~3) != head->tail_pointer) &&
 		!(head->head_pointer & 1) &&
-		((((td_t*)phys_to_virt(head->head_pointer & ~3))->condition_code & 0xf)>=0xe)) {
+		((((td_t*)phys_to_virt(head->head_pointer & ~3))->config & TD_CC_MASK) >= TD_CC_NOACCESS)) {
 		debug("intst: %x; ctrl: %x; cmdst: %x; head: %x -> %x, tail: %x, condition: %x\n",
 			OHCI_INST(dev->controller)->opreg->HcInterruptStatus,
 			OHCI_INST(dev->controller)->opreg->HcControl,
@@ -209,7 +210,7 @@ wait_for_ed(usbdev_t *dev, ed_t *head)
 			head->head_pointer,
 			((td_t*)phys_to_virt(head->head_pointer & ~3))->next_td,
 			head->tail_pointer,
-			((td_t*)phys_to_virt(head->head_pointer & ~3))->condition_code);
+			(((td_t*)phys_to_virt(head->head_pointer & ~3))->config & TD_CC_MASK) >> TD_CC_SHIFT);
 		mdelay(1);
 	}
 	mdelay(5);
@@ -266,12 +267,11 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen
 	}
 	tds[td_count + 3].next_td = 0;
 
-	tds[0].direction = OHCI_SETUP;
-	tds[0].toggle_from_td = 1;
-	tds[0].toggle = 0;
-	tds[0].error_count = 0;
-	tds[0].delay_interrupt = 7;
-	tds[0].condition_code = 0xf;
+	tds[0].config = TD_DIRECTION_SETUP |
+		TD_DELAY_INTERRUPT_NODELAY |
+		TD_TOGGLE_FROM_TD |
+		TD_TOGGLE_DATA0 |
+		TD_CC_NOACCESS;
 	tds[0].current_buffer_pointer = virt_to_phys(devreq);
 	tds[0].buffer_end = virt_to_phys(devreq + drlen - 1);
 
@@ -279,12 +279,10 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen
 
 	while (pages > 0) {
 		cur++;
-		cur->direction = (dir==IN)?OHCI_IN:OHCI_OUT;
-		cur->toggle_from_td = 0;
-		cur->toggle = 1;
-		cur->error_count = 0;
-		cur->delay_interrupt = 7;
-		cur->condition_code = 0xf;
+		cur->config = (dir==IN)?TD_DIRECTION_IN:TD_DIRECTION_OUT |
+			TD_DELAY_INTERRUPT_NODELAY |
+			TD_TOGGLE_FROM_ED |
+			TD_CC_NOACCESS;
 		cur->current_buffer_pointer = virt_to_phys(data);
 		pages--;
 		int consumed = (4096 - ((unsigned long)data % 4096));
@@ -308,12 +306,11 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen
 	}
 
 	cur++;
-	cur->direction = (dir==IN)?OHCI_OUT:OHCI_IN;
-	cur->toggle_from_td = 1;
-	cur->toggle = 1;
-	cur->error_count = 0;
-	cur->delay_interrupt = 7;
-	cur->condition_code = 0xf;
+	cur->config = (dir==IN)?TD_DIRECTION_OUT:TD_DIRECTION_IN |
+		TD_DELAY_INTERRUPT_NODELAY |
+		TD_TOGGLE_FROM_TD |
+		TD_TOGGLE_DATA1 |
+		TD_CC_NOACCESS;
 	cur->current_buffer_pointer = 0;
 	cur->buffer_end = 0;
 
@@ -323,18 +320,15 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen
 	/* Data structures */
 	ed_t *head = memalign(sizeof(ed_t), sizeof(ed_t));
 	memset((void*)head, 0, sizeof(*head));
-	head->function_address = dev->address;
-	head->endpoint_number = 0;
-	head->direction = OHCI_FROM_TD;
-	head->lowspeed = dev->speed;
-	head->format = 0;
-	head->maximum_packet_size = dev->endpoints[0].maxpacketsize;
+	head->config = (dev->address << ED_FUNC_SHIFT) |
+		(0 << ED_EP_SHIFT) |
+		(OHCI_FROM_TD << ED_DIR_SHIFT) |
+		(dev->speed?ED_LOWSPEED:0) |
+		(dev->endpoints[0].maxpacketsize << ED_MPS_SHIFT);
 	head->tail_pointer = virt_to_phys(cur);
 	head->head_pointer = virt_to_phys(tds);
-	head->halted = 0;
-	head->toggle = 0;
 
-	debug("doing control transfer with %x. first_td at %x\n", head->function_address, virt_to_phys(tds));
+	debug("doing control transfer with %x. first_td at %x\n", head->config & ED_FUNC_MASK, virt_to_phys(tds));
 
 	/* activate schedule */
 	OHCI_INST(dev->controller)->opreg->HcControlHeadED = virt_to_phys(head);
@@ -379,11 +373,10 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize)
 	}
 
 	for (cur = tds; cur->next_td != 0; cur++) {
-		cur->toggle_from_td = 0;
-		cur->error_count = 0;
-		cur->delay_interrupt = 7;
-		cur->condition_code = 0xf;
-		cur->direction = (ep->direction==IN)?OHCI_IN:OHCI_OUT;
+		cur->config =  (ep->direction==IN)?TD_DIRECTION_IN:TD_DIRECTION_OUT |
+                        TD_DELAY_INTERRUPT_NODELAY |
+                        TD_TOGGLE_FROM_ED |
+                        TD_CC_NOACCESS;
 		cur->current_buffer_pointer = virt_to_phys(data);
 		pages--;
 		if (dalen == 0) {
@@ -415,18 +408,16 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize)
 	/* Data structures */
 	ed_t *head = memalign(sizeof(ed_t), sizeof(ed_t));
 	memset((void*)head, 0, sizeof(*head));
-	head->function_address = ep->dev->address;
-	head->endpoint_number = ep->endpoint & 0xf;
-	head->direction = (ep->direction==IN)?OHCI_IN:OHCI_OUT;
-	head->lowspeed = ep->dev->speed;
-	head->format = 0;
-	head->maximum_packet_size = ep->maxpacketsize;
+	head->config = (ep->dev->address << ED_FUNC_SHIFT) |
+		((ep->endpoint & 0xf) << ED_EP_SHIFT) |
+		(((ep->direction==IN)?OHCI_IN:OHCI_OUT) << ED_DIR_SHIFT) |
+		(ep->dev->speed?ED_LOWSPEED:0) |
+		(ep->maxpacketsize << ED_MPS_SHIFT);
 	head->tail_pointer = virt_to_phys(cur);
-	head->head_pointer = virt_to_phys(tds);
-	head->halted = 0;
-	head->toggle = ep->toggle;
+	head->head_pointer = virt_to_phys(tds) | (ep->toggle?ED_TOGGLE:0);
 
-	debug("doing bulk transfer with %x(%x). first_td at %x, last %x\n", head->function_address, head->endpoint_number, virt_to_phys(tds), virt_to_phys(cur));
+	debug("doing bulk transfer with %x(%x). first_td at %x, last %x\n", head->config & ED_FUNC_MASK,
+		(head->config & ED_EP_MASK) >> ED_EP_SHIFT, virt_to_phys(tds), virt_to_phys(cur));
 
 	/* activate schedule */
 	OHCI_INST(ep->dev->controller)->opreg->HcBulkHeadED = virt_to_phys(head);
@@ -436,7 +427,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize)
 	int failure = wait_for_ed(ep->dev, head);
 	OHCI_INST(ep->dev->controller)->opreg->HcControl &= ~BulkListEnable;
 
-	ep->toggle = head->toggle;
+	ep->toggle = head->head_pointer & ED_TOGGLE;
 
 	/* free memory */
 	free((void*)tds);
diff --git a/payloads/libpayload/drivers/usb/ohci_private.h b/payloads/libpayload/drivers/usb/ohci_private.h
index a340be1..d0b8ffc 100644
--- a/payloads/libpayload/drivers/usb/ohci_private.h
+++ b/payloads/libpayload/drivers/usb/ohci_private.h
@@ -206,49 +206,43 @@
 	typedef enum { OHCI_SETUP=0, OHCI_OUT=1, OHCI_IN=2, OHCI_FROM_TD=3 } ohci_pid_t;
 
 	typedef volatile struct {
-		union {
-			u32 dword0;
-			struct {
-				unsigned long function_address:7;
-				unsigned long endpoint_number:4;
-				unsigned long direction:2;
-				unsigned long lowspeed:1;
-				unsigned long skip:1;
-				unsigned long format:1;
-				unsigned long maximum_packet_size:11;
-				unsigned long:5;
-			} __attribute__ ((packed));
-		};
+		u32 config;
 		u32 tail_pointer;
-		union {
-			u32 head_pointer;
-			struct {
-				unsigned long halted:1;
-				unsigned long toggle:1;
-				unsigned long:30;
-			} __attribute__ ((packed));
-		};
+		u32 head_pointer;
 		u32 next_ed;
 	} __attribute__ ((packed)) ed_t;
+#define ED_HALTED 1
+#define ED_TOGGLE 2
+
+#define ED_FUNC_SHIFT 0
+#define ED_FUNC_MASK MASK(7, 0)
+#define ED_EP_SHIFT 7
+#define ED_EP_MASK MASK(4, 7)
+#define ED_DIR_SHIFT 11
+#define ED_DIR_MASK MASK(2, 11)
+#define ED_LOWSPEED (1 << 13)
+#define ED_MPS_SHIFT 16
 
 	typedef volatile struct {
-		union {
-			u32 dword0;
-			struct {
-				unsigned long:18;
-				unsigned long buffer_rounding:1;
-				unsigned long direction:2;
-				unsigned long delay_interrupt:3;
-				unsigned long toggle:1;
-				unsigned long toggle_from_td:1;
-				unsigned long error_count:2;
-				unsigned long condition_code:4;
-			} __attribute__ ((packed));
-		};
+		u32 config;
 		u32 current_buffer_pointer;
 		u32 next_td;
 		u32 buffer_end;
 	} __attribute__ ((packed)) td_t;
+#define TD_DIRECTION_SHIFT 19
+#define TD_DIRECTION_MASK MASK(2, TD_DIRECTION_SHIFT)
+#define TD_DIRECTION_SETUP OHCI_SETUP << TD_DIRECTION_SHIFT
+#define TD_DIRECTION_IN OHCI_IN << TD_DIRECTION_SHIFT
+#define TD_DIRECTION_OUT OHCI_OUT << TD_DIRECTION_SHIFT
+#define TD_DELAY_INTERRUPT_NODELAY (7 << 21)
+#define TD_TOGGLE_DATA0 0
+#define TD_TOGGLE_DATA1 (1 << 24)
+#define TD_TOGGLE_FROM_ED 0
+#define TD_TOGGLE_FROM_TD (1 << 25)
+#define TD_CC_SHIFT 28
+#define TD_CC_MASK MASK(4, TD_CC_SHIFT)
+#define TD_CC_NOERR 0
+#define TD_CC_NOACCESS (14 << TD_CC_SHIFT) /* the lower of the two values, so "no access" can be tested with >= */
 
 #define OHCI_INST(controller) ((ohci_t*)((controller)->instance))
 


From gerrit at coreboot.org  Thu Dec  8 15:39:53 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Thu, 8 Dec 2011 15:39:53 +0100
Subject: [coreboot] New patch to review for coreboot: 340d640 libpayload:
	Remove bitfield use from EHCI data structures
References: <If4c4cb748af340e2721b89fea8e035da0632971f+0@gerrit.coreboot.org>
Message-ID: <If4c4cb748af340e2721b89fea8e035da0632971f+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/480

-gerrit

commit 340d64045cf4798d301d28664d24bc9ef78050e6
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Nov 24 13:19:57 2011 +0100

    libpayload: Remove bitfield use from EHCI data structures
    
    We agreed that bitfields are a Bad Idea[tm].
    
    Change-Id: If4c4cb748af340e2721b89fea8e035da0632971f
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 payloads/libpayload/drivers/usb/ehci.c         |  144 +++++++-------
 payloads/libpayload/drivers/usb/ehci_private.h |  249 ++++++------------------
 payloads/libpayload/drivers/usb/ehci_rh.c      |   41 ++---
 3 files changed, 139 insertions(+), 295 deletions(-)

diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c
index 71fbd7a..9500059 100644
--- a/payloads/libpayload/drivers/usb/ehci.c
+++ b/payloads/libpayload/drivers/usb/ehci.c
@@ -34,19 +34,19 @@
 static void dump_td(u32 addr)
 {
 	qtd_t *td = phys_to_virt(addr);
-	debug("td at phys(%x): active: %x, halted: %x, data_buf_err: %x\n    babble: %x, xact_err: %x, missed_mframe: %x\n    splitxstate: %x, perr: %x\n\n",
-		addr, td->active, td->halted, td->data_buf_err, td->babble, td->xact_err, td->missed_mframe, td->splitxstate, td->perr);
-	debug("-   cerr: %x, total_len: %x\n\n", td->cerr, td->total_len);
+	debug("td at phys(%x): status: %x\n\n", addr, td->token & QTD_STATUS_MASK);
+	debug("-   cerr: %x, total_len: %x\n\n", (td->token & QTD_CERR_MASK) >> QTD_CERR_SHIFT,
+		(td->token & QTD_TOTAL_LEN_MASK) >> QTD_TOTAL_LEN_SHIFT);
 }
 
 static void ehci_start (hci_t *controller)
 {
-	EHCI_INST(controller)->operation->rs = 1;
+	EHCI_INST(controller)->operation->usbcmd |= HC_OP_RS;
 }
 
 static void ehci_stop (hci_t *controller)
 {
-	EHCI_INST(controller)->operation->rs = 0;
+	EHCI_INST(controller)->operation->usbcmd &= ~HC_OP_RS;
 }
 
 static void ehci_reset (hci_t *controller)
@@ -61,20 +61,19 @@ static void ehci_shutdown (hci_t *controller)
 
 enum { EHCI_OUT=0, EHCI_IN=1, EHCI_SETUP=2 };
 
-/* returns handled bytes */
-int fill_td(qtd_t *td, void* data, int datalen)
+/* returns handled bytes. assumes that the fields it writes are empty on entry */
+static int fill_td(qtd_t *td, void* data, int datalen)
 {
 	u32 total_len = 0;
-	u32 page_minus_1 = 0;
+	u32 page_no = 0;
 
 	u32 start = virt_to_phys(data);
 	u32 page = start & ~4095;
 	u32 offset = start & 4095;
 	u32 page_len = 4096 - offset;
 
-	td->c_page = 0;
-	td->bufptr0 = page;
-	td->cur_off = offset;
+	td->token |= 0 << QTD_CPAGE_SHIFT;
+	td->bufptrs[page_no++] = start;
 
 	if (datalen <= page_len) {
 		total_len = datalen;
@@ -82,26 +81,25 @@ int fill_td(qtd_t *td, void* data, int datalen)
 		datalen -= page_len;
 		total_len += page_len;
 
-		do {
+		while (page_no < 5) {
 			/* we have a continguous mapping between virtual and physical memory */
 			page += 4096;
 
-			td->bufptrs[page_minus_1] = page;
+			td->bufptrs[page_no++] = page;
 			if (datalen <= 4096) {
 				total_len += datalen;
 				break;
 			}
-			page_minus_1++;
 			datalen -= 4096;
 			total_len += 4096;
-		} while (page_minus_1<4);
+		}
 	}
-	td->total_len = total_len;
+	td->token |= total_len << QTD_TOTAL_LEN_SHIFT;
 	return total_len;
 }
 
 /* free up data structures */
-void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur)
+static void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur)
 {
 	qtd_t *next;
 	while (cur) {
@@ -112,14 +110,14 @@ void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur)
 	free(qh);
 }
 
-int wait_for_tds(qtd_t *head)
+static int wait_for_tds(qtd_t *head)
 {
 	int result = 0;
 	qtd_t *cur = head;
 	while (1) {
 		if (0) dump_td(virt_to_phys(cur));
-		while (cur->active && !cur->halted) udelay(60);
-		if (cur->halted) {
+		while ((cur->token & QTD_ACTIVE) && !(cur->token & QTD_HALTED)) udelay(60);
+		if (cur->token & QTD_HALTED) {
 			printf("ERROR with packet\n");
 			dump_td(virt_to_phys(cur));
 			debug("-----------------\n");
@@ -146,17 +144,16 @@ static int ehci_bulk (endpoint_t *ep, int size, u8 *data, int finalize)
 	qtd_t *cur = head;
 	while (1) {
 		memset(cur, 0, sizeof(qtd_t));
-		cur->active = 1;
-		cur->pid = pid;
-		cur->cerr = 0;
+		cur->token = QTD_ACTIVE |
+			(pid << QTD_PID_SHIFT) |
+			(0 << QTD_CERR_SHIFT);
 		u32 chunk = fill_td(cur, data, size);
 		size -= chunk;
 		data += chunk;
 
-		cur->alt_terminate = 1;
+		cur->alt_next_qtd = QTD_TERMINATE;
 		if (size == 0) {
-			cur->next_qtd = virt_to_phys(0);
-			cur->terminate = 1;
+			cur->next_qtd = virt_to_phys(0) | QTD_TERMINATE;
 			break;
 		} else {
 			qtd_t *next = memalign(32, sizeof(qtd_t));
@@ -168,36 +165,35 @@ static int ehci_bulk (endpoint_t *ep, int size, u8 *data, int finalize)
 	/* create QH */
 	ehci_qh_t *qh = memalign(32, sizeof(ehci_qh_t));
 	memset(qh, 0, sizeof(ehci_qh_t));
-	qh->horiz_link_ptr = virt_to_phys(qh);
-	qh->type = 1; // FIXME: proper symbols for type. this is QH
-	qh->addr = ep->dev->address;
-	qh->ep = endp;
-	qh->eps = ep->dev->speed;
-	qh->dtc = 0;
-	qh->reclaim_head = 1;
-	qh->max_packet_len = ep->maxpacketsize;
-	qh->nak_cnt_reload = 0;
-	qh->pipe_multiplier = 3;
+	qh->horiz_link_ptr = virt_to_phys(qh) | QH_QH;
+	qh->epchar = ep->dev->address |
+		(endp << QH_EP_SHIFT) |
+		(ep->dev->speed << QH_EPS_SHIFT) |
+		(0 << QH_DTC_SHIFT) |
+		(1 << QH_RECLAIM_HEAD_SHIFT) |
+		(ep->maxpacketsize << QH_MPS_SHIFT) |
+		(0 << QH_NAK_CNT_SHIFT);
+	qh->epcaps = 3 << QH_PIPE_MULTIPLIER_SHIFT;
 
 	qh->td.next_qtd = virt_to_phys(head);
-	qh->td.dt = ep->toggle;
-	head->dt = ep->toggle;
+	qh->td.token |= (ep->toggle?QTD_TOGGLE_DATA1:0);
+	head->token |= (ep->toggle?QTD_TOGGLE_DATA1:0);
 
 	/* hook up QH */
 	EHCI_INST(ep->dev->controller)->operation->asynclistaddr = virt_to_phys(qh);
 
 	/* start async schedule */
-	EHCI_INST(ep->dev->controller)->operation->async_sched_enable = 1;
-	while (!EHCI_INST(ep->dev->controller)->operation->async_sched_status) ; /* wait */
+	EHCI_INST(ep->dev->controller)->operation->usbcmd |= HC_OP_ASYNC_SCHED_EN;
+	while (!(EHCI_INST(ep->dev->controller)->operation->usbsts & HC_OP_ASYNC_SCHED_STAT)) ; /* wait */
 
 	/* wait for result */
 	result = wait_for_tds(head);
 
 	/* disable async schedule */
-	EHCI_INST(ep->dev->controller)->operation->async_sched_enable = 0;
-	while (EHCI_INST(ep->dev->controller)->operation->async_sched_status) ; /* wait */
+	EHCI_INST(ep->dev->controller)->operation->usbcmd &= ~HC_OP_ASYNC_SCHED_EN;
+	while (EHCI_INST(ep->dev->controller)->operation->usbsts & HC_OP_ASYNC_SCHED_STAT) ; /* wait */
 
-	ep->toggle = cur->dt;
+	ep->toggle = (cur->token & QTD_TOGGLE_MASK) >> QTD_TOGGLE_SHIFT;
 
 	free_qh_and_tds(qh, head);
 	return result;
@@ -217,16 +213,16 @@ static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq
 	qtd_t *head = memalign(32, sizeof(qtd_t));
 	qtd_t *cur = head;
 	memset(cur, 0, sizeof(qtd_t));
-	cur->active = 1;
-	cur->dt = toggle;
-	cur->pid = EHCI_SETUP;
-	cur->cerr = 3;
+	cur->token = QTD_ACTIVE |
+		(toggle?QTD_TOGGLE_DATA1:0) |
+		(EHCI_SETUP << QTD_PID_SHIFT) |
+		(3 << QTD_CERR_SHIFT);
 	if (fill_td(cur, devreq, drlen) != drlen) {
 		printf("ERROR: couldn't send the entire device request\n");
 	}
 	qtd_t *next = memalign(32, sizeof(qtd_t));
 	cur->next_qtd = virt_to_phys(next);
-	cur->alt_terminate = 1;
+	cur->alt_next_qtd = QTD_TERMINATE;
 
 	/* FIXME: We're limited to 16-20K (depending on alignment) for payload for now.
 	 * Figure out, how toggle can be set sensibly in this scenario */
@@ -234,58 +230,56 @@ static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq
 		toggle ^= 1;
 		cur = next;
 		memset(cur, 0, sizeof(qtd_t));
-		cur->active = 1;
-		cur->dt = toggle;
-		cur->pid = (dir == OUT)?EHCI_OUT:EHCI_IN;
-		cur->cerr = 3;
+		cur->token = QTD_ACTIVE |
+			(toggle?QTD_TOGGLE_DATA1:0) |
+			(((dir == OUT)?EHCI_OUT:EHCI_IN) << QTD_PID_SHIFT) |
+			(3 << QTD_CERR_SHIFT);
 		if (fill_td(cur, data, dalen) != dalen) {
 			printf("ERROR: couldn't send the entire control payload\n");
 		}
 		next = memalign(32, sizeof(qtd_t));
 		cur->next_qtd = virt_to_phys(next);
-		cur->alt_terminate = 1;
+		cur->alt_next_qtd = QTD_TERMINATE;
 	}
 
 	toggle = 1;
 	cur = next;
 	memset(cur, 0, sizeof(qtd_t));
-	cur->active = 1;
-	cur->dt = toggle;
-	cur->pid = (dir == OUT)?EHCI_IN:EHCI_OUT;
-	cur->cerr = 0;
+	cur->token = QTD_ACTIVE |
+		(toggle?QTD_TOGGLE_DATA1:QTD_TOGGLE_DATA0) |
+		((dir == OUT)?EHCI_IN:EHCI_OUT) << QTD_PID_SHIFT |
+		(0 << QTD_CERR_SHIFT);
 	fill_td(cur, NULL, 0);
-	cur->next_qtd = virt_to_phys(0);
-	cur->terminate = 1;
-	cur->alt_terminate = 1;
+	cur->next_qtd = virt_to_phys(0) | QTD_TERMINATE;
+	cur->alt_next_qtd = QTD_TERMINATE;
 
 	/* create QH */
 	ehci_qh_t *qh = memalign(32, sizeof(ehci_qh_t));
 	memset(qh, 0, sizeof(ehci_qh_t));
-	qh->horiz_link_ptr = virt_to_phys(qh);
-	qh->type = 1; // FIXME: proper symbols for type. this is QH
-	qh->addr = dev->address;
-	qh->ep = endp;
-	qh->eps = dev->speed;
-	qh->dtc = 1; /* Take data toggle from TD, as control transfers are special */
-	qh->reclaim_head = 1;
-	qh->max_packet_len = mlen;
-	qh->non_hs_control_ep = 0; // no support for non-HS devices at this time
-	qh->nak_cnt_reload = 0;
-	qh->pipe_multiplier = 3;
+	qh->horiz_link_ptr = virt_to_phys(qh) | QH_QH;
+	qh->epchar = dev->address |
+		(endp << QH_EP_SHIFT) |
+		(dev->speed << QH_EPS_SHIFT) |
+		(1 << QH_DTC_SHIFT) | /* ctrl transfers are special: take toggle bit from TD */
+		(1 << QH_RECLAIM_HEAD_SHIFT) |
+		(mlen << QH_MPS_SHIFT) |
+		(0 << QH_NON_HS_CTRL_EP_SHIFT) | /* no non-HS device support yet */
+		(0 << QH_NAK_CNT_SHIFT);
+	qh->epcaps = 3 << QH_PIPE_MULTIPLIER_SHIFT;
 	qh->td.next_qtd = virt_to_phys(head);
 
 	/* hook up QH */
 	EHCI_INST(dev->controller)->operation->asynclistaddr = virt_to_phys(qh);
 
 	/* start async schedule */
-	EHCI_INST(dev->controller)->operation->async_sched_enable = 1;
-	while (!EHCI_INST(dev->controller)->operation->async_sched_status) ; /* wait */
+	EHCI_INST(dev->controller)->operation->usbcmd |= HC_OP_ASYNC_SCHED_EN;
+	while (!(EHCI_INST(dev->controller)->operation->usbsts & HC_OP_ASYNC_SCHED_STAT)) ; /* wait */
 
 	result = wait_for_tds(head);
 
 	/* disable async schedule */
-	EHCI_INST(dev->controller)->operation->async_sched_enable = 0;
-	while (EHCI_INST(dev->controller)->operation->async_sched_status) ; /* wait */
+	EHCI_INST(dev->controller)->operation->usbcmd &= ~HC_OP_ASYNC_SCHED_EN;
+	while (EHCI_INST(dev->controller)->operation->usbsts & HC_OP_ASYNC_SCHED_STAT) ; /* wait */
 
 	free_qh_and_tds(qh, head);
 	return result;
diff --git a/payloads/libpayload/drivers/usb/ehci_private.h b/payloads/libpayload/drivers/usb/ehci_private.h
index f4890cc..22fd7b2 100644
--- a/payloads/libpayload/drivers/usb/ehci_private.h
+++ b/payloads/libpayload/drivers/usb/ehci_private.h
@@ -37,134 +37,35 @@
 #define FLADJ 0x61
 #define FLADJ_framelength(x) (((x)-59488)/16)
 
-typedef volatile union {
-	u32 val;
-	volatile struct {
-		unsigned long current_conn_status:1;
-		unsigned long conn_status_change:1;
-		unsigned long port_enable:1;
-		unsigned long port_enable_change:1;
-		unsigned long overcurrent:1;
-		unsigned long overcurrent_change:1;
-		unsigned long force_port_resume:1;
-		unsigned long suspend:1;
-		unsigned long port_reset:1;
-		unsigned long:1;
-		unsigned long line_status:2;
-		unsigned long pp:1;
-		unsigned long port_owner:1;
-		unsigned long port_indicator_control:2;
-		unsigned long port_test_control:4;
-		unsigned long wake_on_connect_en:1;
-		unsigned long wake_on_disconnect_en:1;
-		unsigned long wake_on_overcurrent_en:1;
-		unsigned long:9;
-	} __attribute__ ((packed));
-} __attribute__ ((packed)) portsc_t;
+typedef volatile u32 portsc_t;
+#define P_CURR_CONN_STATUS (1 << 0)
+#define P_CONN_STATUS_CHANGE (1 << 1)
+#define P_PORT_ENABLE (1 << 2)
+#define P_PORT_RESET (1 << 8)
+#define P_LINE_STATUS (3 << 10)
+#define P_LINE_STATUS_LOWSPEED (1 << 10)
+#define P_PP (1 << 12)
+#define P_PORT_OWNER (1 << 13)
 
 typedef volatile struct {
+#define HCS_NPORTS_MASK 0xf
 	u8 caplength;
 	u8 res1;
 	u16 hciversion;
-	union {
-		u32 hcsparams;
-		struct {
-			unsigned long n_ports:4;
-			unsigned long ppc:1;
-			unsigned long:2;
-			unsigned long port_routing_rules:1;
-			unsigned long n_pcc:4;
-			unsigned long n_cc:4;
-			unsigned long p_indicator:1;
-			unsigned long:3;
-			unsigned long debug_port_number:4;
-			unsigned long:8;
-		} __attribute__ ((packed));
-	};
-	union {
-		u32 hccparams;
-		struct {
-			unsigned long cap_64b_addr:1;
-			unsigned long cap_prog_framelist_size:1;
-			unsigned long cap_async_park:1;
-			unsigned long:1;
-			unsigned long isoc_sched_threshold:4;
-			unsigned long eecp:8;
-			unsigned long:16;
-		} __attribute__ ((packed));
-	};
-	union {
-		u64 hcsp_portroute;
-		struct {
-			unsigned long portroute0:4;
-			unsigned long portroute1:4;
-			unsigned long portroute2:4;
-			unsigned long portroute3:4;
-			unsigned long portroute4:4;
-			unsigned long portroute5:4;
-			unsigned long portroute6:4;
-			unsigned long portroute7:4;
-			unsigned long portroute8:4;
-			unsigned long portroute9:4;
-			unsigned long portroute10:4;
-			unsigned long portroute11:4;
-			unsigned long portroute12:4;
-			unsigned long portroute13:4;
-			unsigned long portroute14:4;
-			unsigned long portroute15:4;
-			unsigned long:4;
-		} __attribute__ ((packed));
-	};
+	u32 hcsparams;
+	u32 hccparams;
+	u64 hcsp_portroute;
 } __attribute__ ((packed)) hc_cap_t;
 
 typedef volatile struct {
-	union {
-		u32 usbcmd;
-		volatile struct {
-			unsigned long rs:1;
-			unsigned long hcreset:1;
-			unsigned long frame_list_size:2;
-			unsigned long periodic_sched_enable:1;
-			unsigned long async_sched_enable:1;
-			unsigned long irq_on_async_advance_doorbell:1;
-			unsigned long light_hc_reset:1;
-			unsigned long async_sched_park_mode_count:2;
-			unsigned long:1;
-			unsigned long async_sched_park_mode_enable:1;
-			unsigned long:4;
-			unsigned long irq_threshold_count:8;
-			unsigned long:8;
-		} __attribute__ ((packed));
-	};
-	union {
-		u32 usbsts;
-		struct {
-			unsigned long usbint:1;
-			unsigned long usberrint:1;
-			unsigned long port_change_detect:1;
-			unsigned long frame_list_rollover:1;
-			unsigned long host_system_error:1;
-			unsigned long irq_on_async_advance:1;
-			unsigned long:6;
-			unsigned long hchalted:1;
-			unsigned long reclamation:1;
-			unsigned long periodic_sched_status:1;
-			unsigned long async_sched_status:1;
-			unsigned long:16;
-		} __attribute__ ((packed));
-	};
-	union {
-		u32 usbintr;
-		struct {
-			unsigned long en_usb_irq:1;
-			unsigned long en_usb_err_irq:1;
-			unsigned long en_port_change_irq:1;
-			unsigned long en_frame_list_rollover_irq:1;
-			unsigned long en_host_system_error_irq:1;
-			unsigned long en_irq_on_async_advance:1;
-			unsigned long:26;
-		} __attribute__ ((packed));
-	};
+	u32 usbcmd;
+#define HC_OP_RS 1
+#define HC_OP_ASYNC_SCHED_EN_SHIFT 5
+#define HC_OP_ASYNC_SCHED_EN (1 << HC_OP_ASYNC_SCHED_EN_SHIFT)
+	u32 usbsts;
+#define HC_OP_ASYNC_SCHED_STAT_SHIFT 15
+#define HC_OP_ASYNC_SCHED_STAT (1 << HC_OP_ASYNC_SCHED_STAT_SHIFT)
+	u32 usbintr;
 	u32 frindex;
 	u32 ctrldssegment;
 	u32 periodiclistbase;
@@ -175,82 +76,46 @@ typedef volatile struct {
 } hc_op_t;
 
 typedef volatile struct {
-	union {
-		u32 next_qtd;
-		struct {
-			unsigned long terminate:1;
-			unsigned long:4;
-			unsigned long:27;
-		} __attribute__ ((packed));
-	};
-	union {
-		u32 alt_next_qtd;
-		struct {
-			unsigned long alt_terminate:1;
-			unsigned long:4;
-			unsigned long:27;
-		} __attribute__ ((packed));
-	};
-	struct {
-		union {
-			volatile u8 status;
-			struct {
-				volatile unsigned long perr:1;
-				volatile unsigned long splitxstate:1;
-				volatile unsigned long missed_mframe:1;
-				volatile unsigned long xact_err:1;
-				volatile unsigned long babble:1;
-				volatile unsigned long data_buf_err:1;
-				volatile unsigned long halted:1;
-				volatile unsigned long active:1;
-			} __attribute__ ((packed));
-		};
-		unsigned long pid:2;
-		volatile unsigned long cerr:2;
-		volatile unsigned long c_page:3;
-		unsigned long ioc:1;
-		volatile unsigned long total_len:15;
-		volatile unsigned long dt:1;
-	} __attribute__ ((packed));
-	union {
-		u32 bufptr0;
-		struct {
-			volatile unsigned long cur_off:12;
-			unsigned long:20;
-		} __attribute__ ((packed));
-	};
-	u32 bufptrs[4];
+#define QTD_TERMINATE 1
+	u32 next_qtd;
+	u32 alt_next_qtd;
+	u32 token;
+#define QTD_STATUS_MASK 0xff
+#define QTD_HALTED (1 << 14)
+#define QTD_ACTIVE (1 << 15)
+#define QTD_PID_SHIFT 8
+#define QTD_PID_MASK (3 << QTD_PID_SHIFT)
+#define QTD_CERR_SHIFT 10
+#define QTD_CERR_MASK (3 << QTD_CERR_SHIFT)
+#define QTD_CPAGE_SHIFT 12
+#define QTD_CPAGE_MASK (7 << QTD_CPAGE_SHIFT)
+#define QTD_TOTAL_LEN_SHIFT 16
+#define QTD_TOTAL_LEN_MASK (((1<<15)-1) << QTD_TOTAL_LEN_SHIFT)
+#define QTD_TOGGLE_SHIFT 31
+#define QTD_TOGGLE_MASK (1 << 31)
+#define QTD_TOGGLE_DATA0 0
+#define QTD_TOGGLE_DATA1 (1 << QTD_TOGGLE_SHIFT)
+	u32 bufptrs[5];
 	u32 bufptrs64[5];
 } __attribute__ ((packed)) qtd_t;
 
 typedef volatile struct {
-	union {
-		u32 horiz_link_ptr;
-		struct {
-			unsigned long terminate:1;
-			unsigned long type:2;
-			unsigned long:1;
-			unsigned long:28;
-		} __attribute__ ((packed));
-	};
-	struct {
-		unsigned long addr:7;
-		unsigned long inactivate:1;
-		unsigned long ep:4;
-		unsigned long eps:2;
-		unsigned long dtc:1;
-		unsigned long reclaim_head:1;
-		unsigned long max_packet_len:11;
-		unsigned long non_hs_control_ep:1;
-		unsigned long nak_cnt_reload:4;
-	} __attribute__ ((packed));
-	struct {
-		unsigned long irq_sched_mask:8;
-		unsigned long split_compl_mask:8;
-		unsigned long hub_addr:7;
-		unsigned long port_num:7;
-		unsigned long pipe_multiplier:2;
-	} __attribute__ ((packed));
+	u32 horiz_link_ptr;
+#define QH_TERMINATE 1
+#define QH_iTD (0<<1)
+#define QH_QH (1<<1)
+#define QH_siTD (2<<1)
+#define QH_FSTN (3<<1)
+	u32 epchar;
+#define QH_EP_SHIFT 8
+#define QH_EPS_SHIFT 12
+#define QH_DTC_SHIFT 14
+#define QH_RECLAIM_HEAD_SHIFT 15
+#define QH_MPS_SHIFT 16
+#define QH_NON_HS_CTRL_EP_SHIFT 27
+#define QH_NAK_CNT_SHIFT 28
+	u32 epcaps;
+#define QH_PIPE_MULTIPLIER_SHIFT 30
 	volatile u32 current_td_ptr;
 	volatile qtd_t td;
 } ehci_qh_t;
diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c
index 22476c1..d9ba8e4 100644
--- a/payloads/libpayload/drivers/usb/ehci_rh.c
+++ b/payloads/libpayload/drivers/usb/ehci_rh.c
@@ -54,19 +54,14 @@ static void
 ehci_rh_hand_over_port (usbdev_t *dev, int port)
 {
 	volatile portsc_t *p = &(RH_INST(dev)->ports[port]);
-	volatile portsc_t tmp;
 
 	debug("giving up port %x, it's USB1\n", port+1);
 
 	/* Lowspeed device. Hand over to companion */
-	tmp = *p;
-	tmp.port_owner = 1;
-	*p = tmp;
-	do {} while (!p->conn_status_change);
+	*p |= P_PORT_OWNER;
+	do {} while (!(*p & P_CONN_STATUS_CHANGE));
 	/* RW/C register, so clear it by writing 1 */
-	tmp = *p;
-	tmp.conn_status_change = 1;
-	*p = tmp;
+	*p |= P_CONN_STATUS_CHANGE;
 	return;
 }
 
@@ -74,16 +69,15 @@ static void
 ehci_rh_scanport (usbdev_t *dev, int port)
 {
 	volatile portsc_t *p = &(RH_INST(dev)->ports[port]);
-	volatile portsc_t tmp;
 	if (RH_INST(dev)->devices[port]!=-1) {
 		debug("Unregister device at port %x\n", port+1);
 		usb_detach_device(dev->controller, RH_INST(dev)->devices[port]);
 		RH_INST(dev)->devices[port]=-1;
 	}
 	/* device connected, handle */
-	if (p->current_conn_status) {
+	if (*p & P_CURR_CONN_STATUS) {
 		mdelay(100);
-		if (p->line_status == 0x1) {
+		if ((*p & P_LINE_STATUS) == P_LINE_STATUS_LOWSPEED) {
 			ehci_rh_hand_over_port(dev, port);
 			return;
 		}
@@ -91,21 +85,17 @@ ehci_rh_scanport (usbdev_t *dev, int port)
 		/* Deassert enable, assert reset.  These must change
 		 * atomically.
 		 */
-		tmp = *p;
-		tmp.port_enable = 0;
-		tmp.port_reset = 1;
-		*p = tmp;
+		*p = (*p & ~P_PORT_ENABLE) | P_PORT_RESET;
 
 		/* Wait a bit while reset is active. */
 		mdelay(50);
 
 		/* Deassert reset. */
-		tmp.port_reset = 0;
-		*p = tmp;
+		*p &= ~P_PORT_RESET;
 
 		/* Wait for flag change to finish. The controller might take a while */
-		while (p->port_reset) ;
-		if (!p->port_enable) {
+		while (*p & P_PORT_RESET) ;
+		if (!(*p & P_PORT_ENABLE)) {
 			ehci_rh_hand_over_port(dev, port);
 			return;
 		}
@@ -113,9 +103,7 @@ ehci_rh_scanport (usbdev_t *dev, int port)
 		RH_INST(dev)->devices[port] = usb_attach_device(dev->controller, dev->address, port, 2);
 	}
 	/* RW/C register, so clear it by writing 1 */
-	tmp = *p;
-	tmp.conn_status_change = 1;
-	*p = tmp;
+	*p |= P_CONN_STATUS_CHANGE;
 }
 
 static int
@@ -123,7 +111,7 @@ ehci_rh_report_port_changes (usbdev_t *dev)
 {
 	int i;
 	for (i=0; i<RH_INST(dev)->n_ports; i++) {
-		if (RH_INST(dev)->ports[i].conn_status_change)
+		if (RH_INST(dev)->ports[i] & P_CONN_STATUS_CHANGE)
 			return i;
 	}
 	return -1;
@@ -143,14 +131,13 @@ ehci_rh_init (usbdev_t *dev)
 {
 	int i;
 	volatile portsc_t *p;
-	volatile portsc_t tmp;
 
 	dev->destroy = ehci_rh_destroy;
 	dev->poll = ehci_rh_poll;
 
 	dev->data = malloc(sizeof(rh_inst_t));
 
-	RH_INST(dev)->n_ports = EHCI_INST(dev->controller)->capabilities->n_ports;
+	RH_INST(dev)->n_ports = EHCI_INST(dev->controller)->capabilities->hcsparams & HCS_NPORTS_MASK;
 	RH_INST(dev)->ports = EHCI_INST(dev->controller)->operation->portsc;
 
 	debug("root hub has %x ports\n", RH_INST(dev)->n_ports);
@@ -159,9 +146,7 @@ ehci_rh_init (usbdev_t *dev)
 	for (i=0; i < RH_INST(dev)->n_ports; i++) {
 		p = &(RH_INST(dev)->ports[i]);
 		RH_INST(dev)->devices[i] = -1;
-		tmp = *p;
-		tmp.pp = 1;
-		*p = tmp;
+		*p |= P_PP;
 	}
 
 	dev->address = 0;


From gerrit at coreboot.org  Thu Dec  8 21:50:31 2011
From: gerrit at coreboot.org (Alec Ari (neotheuser@ymail.com))
Date: Thu, 8 Dec 2011 21:50:31 +0100
Subject: [coreboot] Patch set updated for coreboot: 7480cad Change DSDT
	Table ID for M4A785T-M board
References: <I43ee024222cf04d03685ffaee616971100cc9e6c+0@gerrit.coreboot.org>
Message-ID: <I43ee024222cf04d03685ffaee616971100cc9e6c+2@gerrit.coreboot.org>

Alec Ari (neotheuser at ymail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/474

-gerrit

commit 7480cad50c33e1cd8ca8f091318404468c48627f
Author: Alec Ari <neotheuser at ymail.com>
Date:   Wed Dec 7 01:50:52 2011 -0600

    Change DSDT Table ID for M4A785T-M board
    
    Change the DSDT Table ID for M4A785T-M
    from M4A785-M to M4A785T-M.
    
    This fixes a small copypasta.
    
    This is an updated patch set.
    
    Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
    Signed-off-by: Alec Ari <neotheuser at ymail.com>
---
 src/mainboard/asus/m4a785t-m/dsdt.asl |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl
index 34ddd3a..d6a4355 100644
--- a/src/mainboard/asus/m4a785t-m/dsdt.asl
+++ b/src/mainboard/asus/m4a785t-m/dsdt.asl
@@ -22,8 +22,8 @@ DefinitionBlock (
 	"DSDT.AML",           /* Output filename */
 	"DSDT",                 /* Signature */
 	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	"ASUS   ",               /* OEMID */
-	"M4A785-M ",	     /* TABLE ID */
+	"ASUS",               /* OEMID */
+	"M4A785T ",	     /* TABLE ID */
 	0x00010001	/* OEM Revision */
 	)
 {	/* Start of ASL file */


From gerrit at coreboot.org  Thu Dec  8 22:42:05 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 8 Dec 2011 22:42:05 +0100
Subject: [coreboot] Patch merged into coreboot/master: 7480cad Change DSDT
	Table ID for M4A785T-M board
References: <I43ee024222cf04d03685ffaee616971100cc9e6c+0@gerrit.coreboot.org>
Message-ID: <E1RYljB-0000Nb-KJ@ra.coresystems.de>

the following patch was just integrated into master:
commit 7480cad50c33e1cd8ca8f091318404468c48627f
Author: Alec Ari <neotheuser at ymail.com>
Date:   Wed Dec 7 01:50:52 2011 -0600

    Change DSDT Table ID for M4A785T-M board
    
    Change the DSDT Table ID for M4A785T-M
    from M4A785-M to M4A785T-M.
    
    This fixes a small copypasta.
    
    This is an updated patch set.
    
    Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
    Signed-off-by: Alec Ari <neotheuser at ymail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Thu Dec  8 22:42:03 2011, giving +2
See http://review.coreboot.org/474 for details.

-gerrit


From gerrit at coreboot.org  Thu Dec  8 22:57:30 2011
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Thu, 8 Dec 2011 22:57:30 +0100
Subject: [coreboot] Patch set updated for coreboot: 5763ba7 Use MMCONF for
	all AMD family 10 CPUs.
References: <I00a25bbf4e4152c89024f14a3c4c1c36b48d0128+0@gerrit.coreboot.org>
Message-ID: <I00a25bbf4e4152c89024f14a3c4c1c36b48d0128+3@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/455

-gerrit

commit 5763ba7b96d997412c6e014714edacf852910f57
Author: Marc Jones <marcj303 at gmail.com>
Date:   Wed Nov 23 17:49:19 2011 -0700

    Use MMCONF for all AMD family 10 CPUs.
    
    This fixes problems in AP init when multiple APs are trying to access
    PCI config space. All Fam10 CPUs setup and support MMCONF.
    
    Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/cpu/amd/model_10xxx/Kconfig |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 6aab30a..310f98d 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -48,8 +48,7 @@ config SET_FIDVID_CORE_RANGE
 	int
 	default 0
 
-endif
-endif
+endif	# SET_FIDVID
 
 config UPDATE_CPU_MICROCODE
 	bool
@@ -82,3 +81,7 @@ config UPDATE_CPU_MICROCODE
 	  Note that some operating system include these same microcode
 	  patches, so you may need to also disable microcode updates in
 	  your operating system in order for this option to matter.
+
+select MMCONF_SUPPORT_DEFAULT
+
+endif	# CPU_AMD_MODEL_10XXX


From gerrit at coreboot.org  Sat Dec 10 19:43:06 2011
From: gerrit at coreboot.org (Florian Zumbiehl)
Date: Sat, 10 Dec 2011 19:43:06 +0100
Subject: [coreboot] New patch to review for coreboot: 242cb03 k8: add
	CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
References: <Ia457f92f6fb7e287defb838db07f12d0f1766757+0@gerrit.coreboot.org>
Message-ID: <Ia457f92f6fb7e287defb838db07f12d0f1766757+1@gerrit.coreboot.org>

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/481

-gerrit

commit 242cb03ce02bde431666e5e6ac7d0eb1375eeba0
Author: Florian Zumbiehl <florz at florz.de>
Date:   Sat Dec 10 19:39:49 2011 +0100

    k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
    
    Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
    Signed-off-by: Florian Zumbiehl <florz at florz.de>
---
 src/mainboard/asus/k8v-x/Kconfig    |    1 +
 src/northbridge/amd/amdk8/Kconfig   |    6 ++++++
 src/northbridge/amd/amdk8/raminit.c |    4 ++--
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig
index d297143..114c609 100644
--- a/src/mainboard/asus/k8v-x/Kconfig
+++ b/src/mainboard/asus/k8v-x/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
 	select SET_FIDVID
+	select K8_FORCE_2T_DRAM_TIMING
 
 config MAINBOARD_DIR
 	string
diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig
index 858041a..70e75e9 100644
--- a/src/northbridge/amd/amdk8/Kconfig
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -37,6 +37,12 @@ config MEM_TRAIN_SEQ
 	int
 	default 0
 
+# Force 2T DRAM timing (vendor BIOS does it even for single DIMM setups and
+# single DIMM is indeed unreliable without it).
+config K8_FORCE_2T_DRAM_TIMING
+	bool
+	default n
+
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 98044d4..eb33a39 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -1477,7 +1477,7 @@ hw_error:
 	if (dloading != 0) {
 		/* we have valid combination check the restrictions */
 		dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-		dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0;
+		dcl |= ((dimm_loading_config[dpos][rpos] & DDR_2T) || CONFIG_K8_FORCE_2T_DRAM_TIMING) ? (DCL_En2T) : 0;
 		/* Set DuallDimm is second channel is completely empty (revD+) */
 		if (((cpuid_eax(1) & 0xfff0f) >= 0x10f00) && ((dpos & 0x5) == 0)) {
 			printk(BIOS_DEBUG, "Setting DualDIMMen\n");
@@ -1661,7 +1661,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 		goto hw_error;
 
 #if CONFIG_CPU_AMD_SOCKET_754
-	if (freq < max_freq_1t) {
+	if (freq < max_freq_1t || CONFIG_K8_FORCE_2T_DRAM_TIMING) {
 		pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW,
 			pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T);
 	}


From gerrit at coreboot.org  Sat Dec 10 19:43:48 2011
From: gerrit at coreboot.org (Florian Zumbiehl)
Date: Sat, 10 Dec 2011 19:43:48 +0100
Subject: [coreboot] New patch to review for coreboot: 6cd0925 asus k8v-x:
	explicitly set RAM and bus voltages
References: <I9426cafc252ee765d723af569c4a90e090d313d9+0@gerrit.coreboot.org>
Message-ID: <I9426cafc252ee765d723af569c4a90e090d313d9+1@gerrit.coreboot.org>

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/482

-gerrit

commit 6cd0925c8ba4a894ca053fa40477d79122cd6fba
Author: Florian Zumbiehl <florz at florz.de>
Date:   Tue Dec 6 10:31:10 2011 +0100

    asus k8v-x: explicitly set RAM and bus voltages
    
    Change-Id: I9426cafc252ee765d723af569c4a90e090d313d9
    Signed-off-by: Florian Zumbiehl <florz at florz.de>
---
 src/mainboard/asus/k8v-x/romstage.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 014ce68..f24c4d4 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -199,6 +199,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80);
 	smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10);
 
+	unsigned char mask;
+
+	mask = 0;
+//	mask |= 1 /* AGP voltage 1.7 V (not verified, just vendor BIOS value) */
+//	mask |= 2 /* V-Link voltage 2.6 V (not verified either) */
+	smbus_write_byte(0x4a, 0x00, (smbus_read_byte(0x4a, 0x00) & ~0x0f) | (0x0f ^ (mask << 2)));
+	smbus_write_byte(0x4a, 0x01, (smbus_read_byte(0x4a, 0x01) & ~0x03) | (0x03 ^ mask));
+
+	mask = 25; /* RAM voltage in decivolts, valid range from 25 to 28 */
+	mask = 3 - (mask - 25);
+	smbus_write_byte(0x4a, 0x02, 0x4f | (mask << 4));
+	smbus_write_byte(0x4a, 0x03, 0x04 | mask);
+
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
 }


From kevin at koconnor.net  Sat Dec 10 19:30:55 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 10 Dec 2011 13:30:55 -0500
Subject: [coreboot] [SeaBIOS] usb boot issue
In-Reply-To: <F53A09371FB723428826B442A4B20A4107BCC394@sbjgexmb1.amd.com>
References: <4738C8CE0A30FF47AACA9C624746E3E208AB0C7849@DATAKAMPONE.datakamp2008.local>
	<20111013231516.GA19387@morn.localdomain>
	<F53A09371FB723428826B442A4B20A4107BCC394@sbjgexmb1.amd.com>
Message-ID: <20111210183054.GA25512@morn.localdomain>

On Fri, Oct 14, 2011 at 12:25:45PM +0800, She, Kerry wrote:
> > > is there any solution for the usb boot issue of the AMD SB800
> Persimmon
> > platform
> > > with SeaBIOS 1.6.3 and actual Coreboot version?
> > 
> > I'm unfamiliar with the issue.  Can you post the SeaBIOS debug output
> > along with a description of the issue you are seeing?
> 
> I got the similar problem with seabios commit 8a161c9f5
> I'm using a EHCI CDROM drive, I have a simple test on sb700 and sb800
> platform.
> After boot to Linux OS, the Ehci CDROM drive can works fine.
> I suspect whether the seabios ehci driver is full support EHCI device?
> 
> Following text is the seabios log with log level 3.
> Thanks
> 
> SeaBIOS (version pre-0.6.3-20111014_111147-Debian-vg0)
[...]
> |7ffd0000| WARNING - Timeout at ehci_wait_qh:316!

There were several EHCI bug fixes committed to seabios git a few weeks
back.  There is a good chance these bugfixes may resolve your issue.
Can you retest?

-Kevin


From kevin at koconnor.net  Sat Dec 10 19:33:24 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 10 Dec 2011 13:33:24 -0500
Subject: [coreboot] [SeaBIOS] usb boot issue
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E208AB0C785C@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E208AB0C7849@DATAKAMPONE.datakamp2008.local>
	<20111013231516.GA19387@morn.localdomain>
	<4738C8CE0A30FF47AACA9C624746E3E208AB0C785C@DATAKAMPONE.datakamp2008.local>
Message-ID: <20111210183324.GB25512@morn.localdomain>

On Fri, Oct 14, 2011 at 05:49:39PM +0200, Wolfgang Kamp - datakamp wrote:
> Hi Kevin,
> 
> the problem occurs when I try to boot from USB Stick on AMD DBFT1 Persimmon board.
> I have tried a couple of sticks in different USB slots but it is always the same issue.
> If Ubuntu has booted from HD the stick will be recognized correctly.
> The log is attached. Tell me if you need more information.
[...]
> USB MSC vendor='' product='USB DISK 2.0' rev='PMAP' type=0 removable=1
> ehci_wait_td error - status=80d40
> ehci_send_bulk failed
> USB transmission failed
> Unable to configure USB MSC device.

There is a good chance this is now fixed due to several EHCI bug fixes
committed to seabios git a few weeks back.  Can you retest?

-Kevin


From mathias.krause at secunet.com  Mon Dec 12 10:25:47 2011
From: mathias.krause at secunet.com (Mathias Krause)
Date: Mon, 12 Dec 2011 10:25:47 +0100
Subject: [coreboot] [PATCH] kbd: wait longer for self-test on keyboard reset
Message-ID: <1323681947-4662-1-git-send-email-mathias.krause@secunet.com>

Some keyboards take pretty long to respond to a reset command, some even
delay the ACK to the command. To make the keyboard driver more robust,
increase the timeout for this special command. Also do an interface test
after the self-test to ensure the keyboard is functioning properly.

Another point is to reenable the keyboard *after* the scancode was set,
not before. We also set the system bit when enabling the keyboard
because this seems to be what older operating systems do expect.

One of the problematic keyboards, which will work with this patch
applied, is the DELL RT7D20. Without the patch an overly optimistic
operating system, read Linux 2.4, will not recognise the keyboard
because coreboot didn't fully initialize it.

Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
Since I was unable to download the git tree (why is it HTTP only, btw?) a
patch against a tarball snapshot.

diff -urp coreboot-403d2d6/src/pc80/keyboard.c coreboot-kbd_fix/src/pc80/keyboard.c
--- coreboot-403d2d6/src/pc80/keyboard.c	2011-12-08 22:42:04.000000000 +0100
+++ coreboot-kbd_fix/src/pc80/keyboard.c	2011-12-12 10:16:04.000000000 +0100
@@ -36,6 +36,7 @@
 #define KBC_CMD_READ_COMMAND	0x20 // Read command byte
 #define KBC_CMD_WRITE_COMMAND	0x60 // Write command byte
 #define KBC_CMD_SELF_TEST	0xAA // Controller self-test
+#define KBC_CMD_KBD_TEST	0xAB // Keyboard Interface test
 
 /* The Keyboard controller command byte
  *  BIT	| Description
@@ -136,6 +137,26 @@ static int kbc_self_test(void)
 		return 0;
 	}
 
+	/* ensure the buffers are empty */
+	kbc_cleanup_buffers();
+
+	/* keyboard interface test */
+	outb(KBC_CMD_KBD_TEST, KBD_COMMAND);
+
+	if (!kbc_output_buffer_full()) {
+		printk(BIOS_ERR, "Keyboard Interface test timed out.\n");
+		return 0;
+	}
+
+	/* read test result, 0x00 should be returned in case of no failures */
+	self_test = inb(KBD_DATA);
+
+	if (self_test != 0x00) {
+		printk(BIOS_ERR, "Keyboard Interface test failed: 0x%x\n",
+				self_test);
+		return 0;
+	}
+
 	return 1;
 }
 
@@ -147,6 +168,14 @@ static u8 send_keyboard(u8 command)
 	do {
 		if (!kbc_input_buffer_empty()) return 0;
 		outb(command, KBD_DATA);
+		/* the reset command takes much longer then normal commands and
+		 * even worse, some keyboards do send the ACK _after_ doing the
+		 * reset */
+		if (command == 0xFF) {
+			u8 retries;
+			for (retries = 9; retries && !kbc_output_buffer_full(); retries--)
+				;
+		}
 		if (!kbc_output_buffer_full()) {
 			printk(BIOS_ERR, "Could not send keyboard command %02x\n",
 					command);
@@ -161,6 +190,7 @@ static u8 send_keyboard(u8 command)
 
 void pc_keyboard_init(struct pc_keyboard *keyboard)
 {
+	u8 retries;
 	u8 regval;
 	if (!CONFIG_DRIVERS_PS2_KEYBOARD)
 		return;
@@ -192,10 +222,14 @@ void pc_keyboard_init(struct pc_keyboard
 	}
 
 	if (regval != KBD_REPLY_ACK) {
-		printk(BIOS_ERR, "Keyboard selftest failed ACK: 0x%x\n", regval);
+		printk(BIOS_ERR, "Keyboard reset failed ACK: 0x%x\n", regval);
 		return;
 	}
 
+	/* the reset command takes some time, so wait a little longer */
+	for (retries = 9; retries && !kbc_output_buffer_full(); retries--)
+		;
+
 	if (!kbc_output_buffer_full()) {
 		printk(BIOS_ERR, "Timeout waiting for keyboard after reset.\n");
 		return;
@@ -203,7 +237,7 @@ void pc_keyboard_init(struct pc_keyboard
 
 	regval = inb(KBD_DATA);
 	if (regval != 0xAA) {
-		printk(BIOS_ERR, "Keyboard selftest failed: 0x%x\n", regval);
+		printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", regval);
 		return;
 	}
 
@@ -232,20 +266,20 @@ void pc_keyboard_init(struct pc_keyboard
 		return;
 	}
 
-	/* enable the keyboard */
-	regval = send_keyboard(0xF4);
-	if (regval != KBD_REPLY_ACK) {
-		printk(BIOS_ERR, "Keyboard enable failed ACK: 0x%x\n", regval);
-		return;
-	}
-
 	/* All is well - enable keyboard interface */
 	if (!kbc_input_buffer_empty()) return;
 	outb(0x60, KBD_COMMAND);
 	if (!kbc_input_buffer_empty()) return;
-	outb(0x61, KBD_DATA);	/* send cmd: enable keyboard and IRQ 1 */
+	outb(0x65, KBD_DATA);	/* send cmd: enable keyboard and IRQ 1 */
 	if (!kbc_input_buffer_empty()) {
-		printk(BIOS_ERR, "Timeout during final keyboard enable\n");
+		printk(BIOS_ERR, "Timeout during keyboard enable\n");
+		return;
+	}
+
+	/* enable the keyboard */
+	regval = send_keyboard(0xF4);
+	if (regval != KBD_REPLY_ACK) {
+		printk(BIOS_ERR, "Keyboard enable failed ACK: 0x%x\n", regval);
 		return;
 	}
 }


From svn at coreboot.org  Mon Dec 12 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 12 Dec 2011 16:00:02 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1Ra7MI-0000Rl-1g@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20111212/eb287e44/attachment-0001.html>

From gerrit at coreboot.org  Tue Dec 13 01:58:37 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 13 Dec 2011 01:58:37 +0100
Subject: [coreboot] Patch merged into coreboot/master: 5763ba7 Use MMCONF
	for all AMD family 10 CPUs.
References: <I00a25bbf4e4152c89024f14a3c4c1c36b48d0128+0@gerrit.coreboot.org>
Message-ID: <E1RaGhZ-0004x8-N7@ra.coresystems.de>

the following patch was just integrated into master:
commit 5763ba7b96d997412c6e014714edacf852910f57
Author: Marc Jones <marcj303 at gmail.com>
Date:   Wed Nov 23 17:49:19 2011 -0700

    Use MMCONF for all AMD family 10 CPUs.
    
    This fixes problems in AP init when multiple APs are trying to access
    PCI config space. All Fam10 CPUs setup and support MMCONF.
    
    Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Thu Dec  8 23:15:22 2011, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Dec  9 21:46:13 2011, giving +2
See http://review.coreboot.org/455 for details.

-gerrit


From caracol at neuf.fr  Tue Dec 13 18:27:15 2011
From: caracol at neuf.fr (nap)
Date: Tue, 13 Dec 2011 18:27:15 +0100
Subject: [coreboot] Belkin Direct Connect USB 2.0
Message-ID: <4EE78AF3.9030609@neuf.fr>

on the  following two ASUS motherboard:
        P5QPL-AM (uATX, socket 755, G31)
        PZKPL-CM (uATX, socket 755, G41)
    To have a debug access, as the two MB have a serial port, this way
is available (not yet tested), but I wonder about the usability of the
following Belkin product "Direct Connect USB 2.0" ( marketed as a laptop
accessory) as a EHCI debug port device like the NET20DC, as new boxes
mostly don't have a serial port, even an Ethernet port for some
(wireless only), but at least a USB 2.0 port.
    I have not found any technical info on the web, including the Belkin
website.
    Anybody has some info about it, even a way to test it ?

caracol


From jakllsch at kollasch.net  Tue Dec 13 19:03:56 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 13 Dec 2011 18:03:56 +0000
Subject: [coreboot] Belkin Direct Connect USB 2.0
In-Reply-To: <4EE78AF3.9030609@neuf.fr>
References: <4EE78AF3.9030609@neuf.fr>
Message-ID: <20111213180356.GC16028@tazenda.kollasch.net>

On Tue, Dec 13, 2011 at 06:27:15PM +0100, nap wrote:
> on the  following two ASUS motherboard:
>         P5QPL-AM (uATX, socket 755, G31)
>         PZKPL-CM (uATX, socket 755, G41)
>     To have a debug access, as the two MB have a serial port, this way
> is available (not yet tested), but I wonder about the usability of the
> following Belkin product "Direct Connect USB 2.0" ( marketed as a laptop
> accessory) as a EHCI debug port device like the NET20DC, as new boxes
> mostly don't have a serial port, even an Ethernet port for some
> (wireless only), but at least a USB 2.0 port.
>     I have not found any technical info on the web, including the Belkin
> website.
>     Anybody has some info about it, even a way to test it ?

I've played with a Prolific PL-25A1 based data link cable, they almost
could work for a device similar to a debug class device that would have
to be supported by special drivers on the machine to be debugged. However,
the chip acts in a way that prevents it from actually being useful.

(The chip will reattach on one end when the other end is plugged in, and
sometimes manages to force the far end into non-high-speed mode long
enough to confuse things.)

	Jonathan Kollasch


From gerrit at coreboot.org  Tue Dec 13 23:10:21 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 13 Dec 2011 23:10:21 +0100
Subject: [coreboot] New patch to review for coreboot: 6f65e88 Fix console
	output in real mode int10 implementation.
References: <Id7f4d260b63024748ef771f949e8b60f934bacbc+0@gerrit.coreboot.org>
Message-ID: <Id7f4d260b63024748ef771f949e8b60f934bacbc+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/483

-gerrit

commit 6f65e8878ed0391c826404035e1d999ee09991d4
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Tue Dec 13 23:08:03 2011 +0100

    Fix console output in real mode int10 implementation.
    
    Checking RBIL, int10 AH=0x10 does never output a character.
    The two output functions are AH=0x09 and AH=0x0e.
    
    Change-Id: Id7f4d260b63024748ef771f949e8b60f934bacbc
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/oprom/x86_interrupts.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/devices/oprom/x86_interrupts.c b/src/devices/oprom/x86_interrupts.c
index 86d20d7..bada546 100644
--- a/src/devices/oprom/x86_interrupts.c
+++ b/src/devices/oprom/x86_interrupts.c
@@ -70,7 +70,7 @@ int int10_handler(struct eregs *regs)
 		res = 0;
 		break;
 	case 0x09: // Write Character and attribute
-	case 0x10: // Write Character
+	case 0x0e: // Write Character
 		printk(BIOS_INFO, "%c", regs->eax & 0xff);
 		res = 0;
 		break;


From gerrit at coreboot.org  Tue Dec 13 23:21:02 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 13 Dec 2011 23:21:02 +0100
Subject: [coreboot] Patch merged into coreboot/master: 47c17ed Fix CMOS
	handling for non-USE_OPTION_TABLE configuration
References: <I8d001f971681277a344b6788725746491546b607+0@gerrit.coreboot.org>
Message-ID: <E1Raaic-00022G-7A@ra.coresystems.de>

the following patch was just integrated into master:
commit 47c17ed4903029017a2e2cce390e549e3dce7f19
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Nov 22 10:27:24 2011 +0100

    Fix CMOS handling for non-USE_OPTION_TABLE configuration
    
    The read_option macro still emitted CMOS_VSTART_*/CMOS_VEND_* symbols,
    which fail without an option table (as no option_table.h defines them).
    
    Discard them by using a macro instead of a static inline function.
    
    Change-Id: I8d001f971681277a344b6788725746491546b607
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>


See http://review.coreboot.org/442 for details.

-gerrit


From gerrit at coreboot.org  Tue Dec 13 23:22:34 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 13 Dec 2011 23:22:34 +0100
Subject: [coreboot] Patch merged into coreboot/master: 38d51a3 libpayload:
	add set_option() function
References: <I4872fc27476923adafe13504126235b92b30de85+0@gerrit.coreboot.org>
Message-ID: <E1Raak6-0003xh-Ii@ra.coresystems.de>

the following patch was just integrated into master:
commit 38d51a3033e667fbde619793de3f8dc127669da6
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Nov 22 13:07:45 2011 +0100

    libpayload: add set_option() function
    
    It allows to change CMOS values from payloads
    
    Change-Id: I4872fc27476923adafe13504126235b92b30de85
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>


See http://review.coreboot.org/445 for details.

-gerrit


From gerrit at coreboot.org  Tue Dec 13 23:46:29 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 13 Dec 2011 23:46:29 +0100
Subject: [coreboot] Patch merged into coreboot/master: 6f65e88 Fix console
	output in real mode int10 implementation.
References: <Id7f4d260b63024748ef771f949e8b60f934bacbc+0@gerrit.coreboot.org>
Message-ID: <E1Rab7F-0007dn-Ny@ra.coresystems.de>

the following patch was just integrated into master:
commit 6f65e8878ed0391c826404035e1d999ee09991d4
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Tue Dec 13 23:08:03 2011 +0100

    Fix console output in real mode int10 implementation.
    
    Checking RBIL, int10 AH=0x10 does never output a character.
    The two output functions are AH=0x09 and AH=0x0e.
    
    Change-Id: Id7f4d260b63024748ef771f949e8b60f934bacbc
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

Build-Tested: build bot (Jenkins) at Tue Dec 13 23:36:01 2011, giving +1
Reviewed-By: Rudolf Marek <r.marek at assembler.cz> at Tue Dec 13 23:46:24 2011, giving +2
See http://review.coreboot.org/483 for details.

-gerrit


From gerrit at coreboot.org  Wed Dec 14 07:33:01 2011
From: gerrit at coreboot.org (Peter Stuge (peter@stuge.se))
Date: Wed, 14 Dec 2011 07:33:01 +0100
Subject: [coreboot] New patch to review for coreboot: cf5e777 .gitignore
	crossgcc ectool inteltool msrtool nvramtool and superiotool
References: <I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df+0@gerrit.coreboot.org>
Message-ID: <I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df+1@gerrit.coreboot.org>

Peter Stuge (peter at stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/484

-gerrit

commit cf5e777f569fb6fe66ade00a322e877a4ef81b30
Author: Peter Stuge <peter at stuge.se>
Date:   Wed Dec 14 07:32:15 2011 +0100

    .gitignore crossgcc ectool inteltool msrtool nvramtool and superiotool
    
    Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df
    Signed-off-by: Peter Stuge <peter at stuge.se>
---
 .gitignore |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/.gitignore b/.gitignore
index 6ea623e..98d0b81 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,19 @@ payloads/external/FILO/filo/
 payloads/external/SeaBIOS/seabios/
 util/crossgcc/tarballs/
 util/crossgcc/xgcc/
+util/crossgcc/acpica-unix-*/
+util/crossgcc/binutils-*/
+util/crossgcc/build-binutils/
+util/crossgcc/build-gcc/
+util/crossgcc/build-gmp/
+util/crossgcc/build-libelf/
+util/crossgcc/build-mpc/
+util/crossgcc/build-mpfr/
+util/crossgcc/gcc-*/
+util/crossgcc/gmp-*/
+util/crossgcc/libelf-*/
+util/crossgcc/mpc-*/
+util/crossgcc/mpfr-*/
 *.o
 *.elf
 *.debug
@@ -14,3 +27,12 @@ util/crossgcc/xgcc/
 *.\#
 *.swp
 *.bin
+util/ectool/ectool
+util/inteltool/.dependencies
+util/inteltool/inteltool
+util/msrtool/Makefile
+util/msrtool/Makefile.deps
+util/msrtool/msrtool
+util/nvramtool/.dependencies
+util/nvramtool/nvramtool
+util/superiotool/superiotool


From gerrit at coreboot.org  Wed Dec 14 07:37:45 2011
From: gerrit at coreboot.org (Peter Stuge (peter@stuge.se))
Date: Wed, 14 Dec 2011 07:37:45 +0100
Subject: [coreboot] Patch set updated for coreboot: 79e8a62 .gitignore
	util/crossgcc build-* and unpacked source directories
References: <I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df+0@gerrit.coreboot.org>
Message-ID: <I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df+2@gerrit.coreboot.org>

Peter Stuge (peter at stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/484

-gerrit

commit 79e8a6273de62857770852ab6a2ec8297f55b15c
Author: Peter Stuge <peter at stuge.se>
Date:   Wed Dec 14 07:32:15 2011 +0100

    .gitignore util/crossgcc build-* and unpacked source directories
    
    Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df
    Signed-off-by: Peter Stuge <peter at stuge.se>
---
 .gitignore |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/.gitignore b/.gitignore
index 6ea623e..0375ad5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,19 @@ payloads/external/FILO/filo/
 payloads/external/SeaBIOS/seabios/
 util/crossgcc/tarballs/
 util/crossgcc/xgcc/
+util/crossgcc/acpica-unix-*/
+util/crossgcc/binutils-*/
+util/crossgcc/build-binutils/
+util/crossgcc/build-gcc/
+util/crossgcc/build-gmp/
+util/crossgcc/build-libelf/
+util/crossgcc/build-mpc/
+util/crossgcc/build-mpfr/
+util/crossgcc/gcc-*/
+util/crossgcc/gmp-*/
+util/crossgcc/libelf-*/
+util/crossgcc/mpc-*/
+util/crossgcc/mpfr-*/
 *.o
 *.elf
 *.debug


From gerrit at coreboot.org  Wed Dec 14 07:41:29 2011
From: gerrit at coreboot.org (Peter Stuge (peter@stuge.se))
Date: Wed, 14 Dec 2011 07:41:29 +0100
Subject: [coreboot] New patch to review for coreboot: 5858275 .gitignore
	ectool, inteltool, msrtool, nvramtool and superiotool
References: <I06e69d97ef3646f79104ec316ce932cc53894c92+0@gerrit.coreboot.org>
Message-ID: <I06e69d97ef3646f79104ec316ce932cc53894c92+1@gerrit.coreboot.org>

Peter Stuge (peter at stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/485

-gerrit

commit 5858275c9f1bee5ee48cea5d614dcba15113e445
Author: Peter Stuge <peter at stuge.se>
Date:   Wed Dec 14 07:39:57 2011 +0100

    .gitignore ectool, inteltool, msrtool, nvramtool and superiotool
    
    Change-Id: I06e69d97ef3646f79104ec316ce932cc53894c92
    Signed-off-by: Peter Stuge <peter at stuge.se>
---
 .gitignore |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/.gitignore b/.gitignore
index 6ea623e..18ef6d6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -14,3 +14,12 @@ util/crossgcc/xgcc/
 *.\#
 *.swp
 *.bin
+util/ectool/ectool
+util/inteltool/.dependencies
+util/inteltool/inteltool
+util/msrtool/Makefile
+util/msrtool/Makefile.deps
+util/msrtool/msrtool
+util/nvramtool/.dependencies
+util/nvramtool/nvramtool
+util/superiotool/superiotool


From gerrit at coreboot.org  Wed Dec 14 07:43:19 2011
From: gerrit at coreboot.org (Peter Stuge (peter@stuge.se))
Date: Wed, 14 Dec 2011 07:43:19 +0100
Subject: [coreboot] Patch set updated for coreboot: ac891b4 .gitignore
	util/crossgcc build-* and unpacked source directories
References: <I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df+0@gerrit.coreboot.org>
Message-ID: <I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df+3@gerrit.coreboot.org>

Peter Stuge (peter at stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/484

-gerrit

commit ac891b40fbf5473c14e437795c56871d180d23fa
Author: Peter Stuge <peter at stuge.se>
Date:   Wed Dec 14 07:32:15 2011 +0100

    .gitignore util/crossgcc build-* and unpacked source directories
    
    Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df
    Signed-off-by: Peter Stuge <peter at stuge.se>
---
 .gitignore |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/.gitignore b/.gitignore
index 6ea623e..738f1e6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,22 @@ payloads/external/FILO/filo/
 payloads/external/SeaBIOS/seabios/
 util/crossgcc/tarballs/
 util/crossgcc/xgcc/
+util/crossgcc/acpica-unix-*/
+util/crossgcc/binutils-*/
+util/crossgcc/build-binutils/
+util/crossgcc/build-gcc/
+util/crossgcc/build-gdb/
+util/crossgcc/build-gmp/
+util/crossgcc/build-expat/
+util/crossgcc/build-libelf/
+util/crossgcc/build-mpc/
+util/crossgcc/build-mpfr/
+util/crossgcc/build-python/
+util/crossgcc/gcc-*/
+util/crossgcc/gmp-*/
+util/crossgcc/libelf-*/
+util/crossgcc/mpc-*/
+util/crossgcc/mpfr-*/
 *.o
 *.elf
 *.debug


From gerrit at coreboot.org  Wed Dec 14 07:49:00 2011
From: gerrit at coreboot.org (Peter Stuge (peter@stuge.se))
Date: Wed, 14 Dec 2011 07:49:00 +0100
Subject: [coreboot] Patch set updated for coreboot: e5c75f4 .gitignore
	util/crossgcc/build-* and unpacked source directories
References: <I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df+0@gerrit.coreboot.org>
Message-ID: <I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df+4@gerrit.coreboot.org>

Peter Stuge (peter at stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/484

-gerrit

commit e5c75f4c5fcd42f4d01deb2a9f4045df1d51e078
Author: Peter Stuge <peter at stuge.se>
Date:   Wed Dec 14 07:32:15 2011 +0100

    .gitignore util/crossgcc/build-* and unpacked source directories
    
    Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df
    Signed-off-by: Peter Stuge <peter at stuge.se>
---
 .gitignore |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/.gitignore b/.gitignore
index 6ea623e..a4bbacd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,27 @@ payloads/external/FILO/filo/
 payloads/external/SeaBIOS/seabios/
 util/crossgcc/tarballs/
 util/crossgcc/xgcc/
+util/crossgcc/Python-*/
+util/crossgcc/acpica-unix-*/
+util/crossgcc/binutils-*/
+util/crossgcc/build-binutils/
+util/crossgcc/build-gcc/
+util/crossgcc/build-gdb/
+util/crossgcc/build-gmp/
+util/crossgcc/build-expat/
+util/crossgcc/build-libelf/
+util/crossgcc/build-mpc/
+util/crossgcc/build-mpfr/
+util/crossgcc/build-python/
+util/crossgcc/expat-*/
+util/crossgcc/gcc-*/
+util/crossgcc/gdb-*/
+util/crossgcc/gmp-*/
+util/crossgcc/libelf-*/
+util/crossgcc/mingwrt-*/
+util/crossgcc/mpc-*/
+util/crossgcc/mpfr-*/
+util/crossgcc/w32api-*/
 *.o
 *.elf
 *.debug


From gerrit at coreboot.org  Wed Dec 14 08:42:06 2011
From: gerrit at coreboot.org (Peter Stuge (peter@stuge.se))
Date: Wed, 14 Dec 2011 08:42:06 +0100
Subject: [coreboot] New patch to review for coreboot: cc2e8ec kbd: wait
	longer for self-test on keyboard reset
References: <I28c8e05bdde61f71b7de084c96bc2447c1b9575e+0@gerrit.coreboot.org>
Message-ID: <I28c8e05bdde61f71b7de084c96bc2447c1b9575e+1@gerrit.coreboot.org>

Peter Stuge (peter at stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/486

-gerrit

commit cc2e8ec8e1da449915789fe13cc645f23b94669c
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Wed Dec 14 08:40:48 2011 +0100

    kbd: wait longer for self-test on keyboard reset
    
    Some keyboards take pretty long to respond to a reset command, some even
    delay the ACK to the command. To make the keyboard driver more robust,
    increase the timeout for this special command. Also do an interface test
    after the self-test to ensure the keyboard is functioning properly.
    
    Another point is to reenable the keyboard *after* the scancode was set,
    not before. We also set the system bit when enabling the keyboard
    because this seems to be what older operating systems do expect.
    
    One of the problematic keyboards, which will work with this patch
    applied, is the DELL RT7D20. Without the patch an overly optimistic
    operating system, read Linux 2.4, will not recognise the keyboard
    because coreboot didn't fully initialize it.
    
    Change-Id: I28c8e05bdde61f71b7de084c96bc2447c1b9575e
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 src/pc80/keyboard.c |   56 +++++++++++++++++++++++++++++++++++++++++----------
 1 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/src/pc80/keyboard.c b/src/pc80/keyboard.c
index 8552860..e0a6643 100644
--- a/src/pc80/keyboard.c
+++ b/src/pc80/keyboard.c
@@ -36,6 +36,7 @@
 #define KBC_CMD_READ_COMMAND	0x20 // Read command byte
 #define KBC_CMD_WRITE_COMMAND	0x60 // Write command byte
 #define KBC_CMD_SELF_TEST	0xAA // Controller self-test
+#define KBC_CMD_KBD_TEST	0xAB // Keyboard Interface test
 
 /* The Keyboard controller command byte
  *  BIT	| Description
@@ -136,6 +137,26 @@ static int kbc_self_test(void)
 		return 0;
 	}
 
+	/* ensure the buffers are empty */
+	kbc_cleanup_buffers();
+
+	/* keyboard interface test */
+	outb(KBC_CMD_KBD_TEST, KBD_COMMAND);
+
+	if (!kbc_output_buffer_full()) {
+		printk(BIOS_ERR, "Keyboard Interface test timed out.\n");
+		return 0;
+	}
+
+	/* read test result, 0x00 should be returned in case of no failures */
+	self_test = inb(KBD_DATA);
+
+	if (self_test != 0x00) {
+		printk(BIOS_ERR, "Keyboard Interface test failed: 0x%x\n",
+				self_test);
+		return 0;
+	}
+
 	return 1;
 }
 
@@ -147,6 +168,14 @@ static u8 send_keyboard(u8 command)
 	do {
 		if (!kbc_input_buffer_empty()) return 0;
 		outb(command, KBD_DATA);
+		/* the reset command takes much longer then normal commands and
+		 * even worse, some keyboards do send the ACK _after_ doing the
+		 * reset */
+		if (command == 0xFF) {
+			u8 retries;
+			for (retries = 9; retries && !kbc_output_buffer_full(); retries--)
+				;
+		}
 		if (!kbc_output_buffer_full()) {
 			printk(BIOS_ERR, "Could not send keyboard command %02x\n",
 					command);
@@ -161,6 +190,7 @@ static u8 send_keyboard(u8 command)
 
 void pc_keyboard_init(struct pc_keyboard *keyboard)
 {
+	u8 retries;
 	u8 regval;
 	if (!CONFIG_DRIVERS_PS2_KEYBOARD)
 		return;
@@ -192,10 +222,14 @@ void pc_keyboard_init(struct pc_keyboard *keyboard)
 	}
 
 	if (regval != KBD_REPLY_ACK) {
-		printk(BIOS_ERR, "Keyboard selftest failed ACK: 0x%x\n", regval);
+		printk(BIOS_ERR, "Keyboard reset failed ACK: 0x%x\n", regval);
 		return;
 	}
 
+	/* the reset command takes some time, so wait a little longer */
+	for (retries = 9; retries && !kbc_output_buffer_full(); retries--)
+		;
+
 	if (!kbc_output_buffer_full()) {
 		printk(BIOS_ERR, "Timeout waiting for keyboard after reset.\n");
 		return;
@@ -203,7 +237,7 @@ void pc_keyboard_init(struct pc_keyboard *keyboard)
 
 	regval = inb(KBD_DATA);
 	if (regval != 0xAA) {
-		printk(BIOS_ERR, "Keyboard selftest failed: 0x%x\n", regval);
+		printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", regval);
 		return;
 	}
 
@@ -232,20 +266,20 @@ void pc_keyboard_init(struct pc_keyboard *keyboard)
 		return;
 	}
 
-	/* enable the keyboard */
-	regval = send_keyboard(0xF4);
-	if (regval != KBD_REPLY_ACK) {
-		printk(BIOS_ERR, "Keyboard enable failed ACK: 0x%x\n", regval);
-		return;
-	}
-
 	/* All is well - enable keyboard interface */
 	if (!kbc_input_buffer_empty()) return;
 	outb(0x60, KBD_COMMAND);
 	if (!kbc_input_buffer_empty()) return;
-	outb(0x61, KBD_DATA);	/* send cmd: enable keyboard and IRQ 1 */
+	outb(0x65, KBD_DATA);	/* send cmd: enable keyboard and IRQ 1 */
 	if (!kbc_input_buffer_empty()) {
-		printk(BIOS_ERR, "Timeout during final keyboard enable\n");
+		printk(BIOS_ERR, "Timeout during keyboard enable\n");
+		return;
+	}
+
+	/* enable the keyboard */
+	regval = send_keyboard(0xF4);
+	if (regval != KBD_REPLY_ACK) {
+		printk(BIOS_ERR, "Keyboard enable failed ACK: 0x%x\n", regval);
 		return;
 	}
 }


From peter at stuge.se  Wed Dec 14 08:45:46 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 14 Dec 2011 08:45:46 +0100
Subject: [coreboot] [PATCH] kbd: wait longer for self-test on
	keyboard	reset
In-Reply-To: <1323681947-4662-1-git-send-email-mathias.krause@secunet.com>
References: <1323681947-4662-1-git-send-email-mathias.krause@secunet.com>
Message-ID: <20111214074546.14244.qmail@stuge.se>

Hi,

Mathias Krause wrote:
> Some keyboards take pretty long to respond to a reset command,

I've pushed this to Gerrit.


> Since I was unable to download the git tree (why is it HTTP only,
> btw?)

You can also access the Git repo using SSH. Please do that. You'll
need to create a user in Gerrit via the web interface, and upload
your public SSH key. Then you can push directly to Gerrit. You can't
count on someone else doing it for you, and there is a high risk that
patches get overlooked. :\


> a patch against a tarball snapshot.

Please always make a git commit and not only a patch. You can send an
email with the patch easily using git send-email, or you can format a
patch for attachment (as text/plain) using git format-patch, after
creating the commit.

I suggest using one branch per independent change, to not have any
dependencies in Gerrit, even though they are really only advisory.

The patch looks generally fine, but what about changing the 0x61 port
to 0x65? That was an error all along?


//Peter


From gerrit at coreboot.org  Wed Dec 14 08:51:00 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 14 Dec 2011 08:51:00 +0100
Subject: [coreboot] Patch merged into coreboot/master: 242cb03 k8: add
	CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
References: <Ia457f92f6fb7e287defb838db07f12d0f1766757+0@gerrit.coreboot.org>
Message-ID: <E1RajcC-0001G5-1i@ra.coresystems.de>

the following patch was just integrated into master:
commit 242cb03ce02bde431666e5e6ac7d0eb1375eeba0
Author: Florian Zumbiehl <florz at florz.de>
Date:   Sat Dec 10 19:39:49 2011 +0100

    k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
    
    Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
    Signed-off-by: Florian Zumbiehl <florz at florz.de>

Build-Tested: build bot (Jenkins) at Sat Dec 10 20:09:46 2011, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Wed Dec 14 08:50:45 2011, giving +2
See http://review.coreboot.org/481 for details.

-gerrit


From gerrit at coreboot.org  Wed Dec 14 08:52:00 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 14 Dec 2011 08:52:00 +0100
Subject: [coreboot] Patch merged into coreboot/master: 6cd0925 asus k8v-x:
	explicitly set RAM and bus voltages
References: <I9426cafc252ee765d723af569c4a90e090d313d9+0@gerrit.coreboot.org>
Message-ID: <E1RajdA-00039i-Dr@ra.coresystems.de>

the following patch was just integrated into master:
commit 6cd0925c8ba4a894ca053fa40477d79122cd6fba
Author: Florian Zumbiehl <florz at florz.de>
Date:   Tue Dec 6 10:31:10 2011 +0100

    asus k8v-x: explicitly set RAM and bus voltages
    
    Change-Id: I9426cafc252ee765d723af569c4a90e090d313d9
    Signed-off-by: Florian Zumbiehl <florz at florz.de>

Build-Tested: build bot (Jenkins) at Sat Dec 10 20:22:34 2011, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Wed Dec 14 08:51:58 2011, giving +2
See http://review.coreboot.org/482 for details.

-gerrit


From gerrit at coreboot.org  Wed Dec 14 09:41:48 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 14 Dec 2011 09:41:48 +0100
Subject: [coreboot] Patch merged into coreboot/master: c18ecfd Lenovo
	X60/T60: add first_battery setting
References: <Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8+0@gerrit.coreboot.org>
Message-ID: <E1RakPM-0005aI-3u@ra.coresystems.de>

the following patch was just integrated into master:
commit c18ecfd8b74b1a38bee90270e36630f9fad74b98
Author: Sven Schnelle <svens at stackframe.org>
Date:   Wed Dec 7 14:30:58 2011 -0800

    Lenovo X60/T60: add first_battery setting
    
    The EC allows to select the order in which batteries are (dis)charged.
    Make this setting available to the user.
    
    Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Build-Tested: build bot (Jenkins) at Wed Dec  7 23:53:28 2011, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Dec  9 21:47:10 2011, giving +2
Reviewed-By: Peter Stuge <peter at stuge.se> at Wed Dec 14 09:41:46 2011, giving +2
See http://review.coreboot.org/475 for details.

-gerrit


From gerrit at coreboot.org  Wed Dec 14 23:35:43 2011
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 14 Dec 2011 23:35:43 +0100
Subject: [coreboot] New patch to review for coreboot: 482f534 Fix Fam10
	MMCONF_SUPPORT_DEFAULT setting.
References: <If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234+0@gerrit.coreboot.org>
Message-ID: <If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/487

-gerrit

commit 482f5346ca1a49602cf0b3a3f69a22442a25dab1
Author: Marc Jones <marcj303 at gmail.com>
Date:   Wed Dec 14 15:33:33 2011 -0700

    Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.
    
    I misunderstood how kconfig select works. It needs to be selected with a config option. Moved the select to the correct location.
    
    Change-Id: If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/cpu/amd/model_10xxx/Kconfig |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 310f98d..221d044 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -2,6 +2,7 @@ config CPU_AMD_MODEL_10XXX
 	bool
 	select SSE
 	select SSE2
+	select MMCONF_SUPPORT_DEFAULT
 
 if CPU_AMD_MODEL_10XXX
 config CPU_ADDR_BITS
@@ -82,6 +83,4 @@ config UPDATE_CPU_MICROCODE
 	  patches, so you may need to also disable microcode updates in
 	  your operating system in order for this option to matter.
 
-select MMCONF_SUPPORT_DEFAULT
-
 endif	# CPU_AMD_MODEL_10XXX


From gerrit at coreboot.org  Thu Dec 15 00:02:26 2011
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Thu, 15 Dec 2011 00:02:26 +0100
Subject: [coreboot] New patch to review for coreboot: b4145dc Add RS780
	defaut graphics ID to AMD Mahogany mainboard.
References: <Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a+0@gerrit.coreboot.org>
Message-ID: <Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/488

-gerrit

commit b4145dcaed06d31ba8c85270e25b810448cd0ea1
Author: Marc Jones <marcj303 at gmail.com>
Date:   Wed Dec 14 15:59:02 2011 -0700

    Add RS780 defaut graphics ID to AMD Mahogany mainboard.
    
    Added the default ID to the mainboard Kconfig.
    
    Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/mahogany/Kconfig       |    4 ++++
 src/mainboard/amd/mahogany_fam10/Kconfig |    4 ++++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig
index 731002d..b0a46a4 100644
--- a/src/mainboard/amd/mahogany/Kconfig
+++ b/src/mainboard/amd/mahogany/Kconfig
@@ -73,4 +73,8 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
+config VGA_BIOS_ID
+	string
+	default "1002,9615"
+
 endif # BOARD_AMD_MAHOGANY
diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig
index 9c2e081..b8d46eb 100644
--- a/src/mainboard/amd/mahogany_fam10/Kconfig
+++ b/src/mainboard/amd/mahogany_fam10/Kconfig
@@ -83,4 +83,8 @@ config RAMBASE
 	hex
 	default 0x200000
 
+config VGA_BIOS_ID
+	string
+	default "1002,9615"
+
 endif # BOARD_AMD_MAHOGANY_FAM10


From mathias.krause at secunet.com  Thu Dec 15 08:28:39 2011
From: mathias.krause at secunet.com (Mathias Krause)
Date: Thu, 15 Dec 2011 08:28:39 +0100
Subject: [coreboot] [PATCH] kbd: wait longer for self-test on	keyboard
 reset
In-Reply-To: <20111214074546.14244.qmail@stuge.se>
References: <1323681947-4662-1-git-send-email-mathias.krause@secunet.com>
	<20111214074546.14244.qmail@stuge.se>
Message-ID: <4EE9A1A7.7010100@secunet.com>

Hi Peter,

On 14.12.2011 08:45, Peter Stuge wrote:
> Hi,
> 
> Mathias Krause wrote:
>> Some keyboards take pretty long to respond to a reset command,
> 
> I've pushed this to Gerrit.

thank you! I wasn't aware of that, but maybe the wiki[1] should be
updated to reflect that this is the preferred way to submit patches and
no longer the mailing list? It's even mentioning the usage of subversion
for the coreboot source, which is now obsolete, I guess.

>> Since I was unable to download the git tree (why is it HTTP only,
>> btw?)
> 
> You can also access the Git repo using SSH. Please do that. You'll
> need to create a user in Gerrit via the web interface, and upload
> your public SSH key. Then you can push directly to Gerrit. You can't
> count on someone else doing it for you, and there is a high risk that
> patches get overlooked. :\

I'll try to set it up for the next time. I already talked to Patrick why
the HTTP repo failed for me. Looks like my git version is to old and
that for lacks smart http support.

>> a patch against a tarball snapshot.
> 
> Please always make a git commit and not only a patch. You can send an
> email with the patch easily using git send-email, or you can format a
> patch for attachment (as text/plain) using git format-patch, after
> creating the commit.

Due to the lack of a git repo I was unable to do so. But, in fact, I
used git send-email to deliver the message. And the email should have
almost looked like as git format-patch generates them -- meaning it has
a subject describing the change, a commit message and the SOB signature.
Anything else missing?

> I suggest using one branch per independent change, to not have any
> dependencies in Gerrit, even though they are really only advisory.

> The patch looks generally fine, but what about changing the 0x61 port
> to 0x65? That was an error all along?

No, it was not. In fact, it's not the port that changed but the value
written. The additional bit is the "also set the system bit when
enabling the keyboard" part of the commit message.


Thanks,
Mathias

[1] http://www.coreboot.org/Development_Guidelines#How_to_contribute


From gerrit at coreboot.org  Thu Dec 15 11:50:56 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Thu, 15 Dec 2011 11:50:56 +0100
Subject: [coreboot] New patch to review for coreboot: 255321a Fix
	multipleVGA cards resource conflict
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
Message-ID: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/489

-gerrit

commit 255321a2d294747af779f24247db2a3583c5f48e
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Dec 15 19:30:50 2011 +0800

    Fix multipleVGA cards resource conflict
    
    If both graphic cards decode the IO 3B0-3DF and MEM A00000-BFFFF,
    Windows 7 complain a resource conflict, so only one VGA card can works
    at the same time.
    
    There is a discuss in coreboot mail list before,
    please reference thread: "how to prevent legacy resource conflictwith   multipleVGA cards"
    
    For the second graphic device, coreboot already disabled the
    IO and MEM decode in function set_vga_bridge_bits().
    But it will be enabled again in function pci_set_resource(),
    if the secondary graphic device take any IO/MEM resources.
    
    Following log printed by enable_resources() shows the problem:
    ...snip...
    PCI: 00:00.0 cmd <- 06
    PCI: 00:01.0 subsystem <- 1022/1410
    PCI: 00:01.0 cmd <- 07                <== The first graphic device
    PCI: 00:01.1 subsystem <- 1022/1410
    PCI: 00:01.1 cmd <- 02
    PCI: 00:02.0 bridge ctrl <- 0003
    PCI: 00:02.0 cmd <- 07
    ...snip...
    PCI: 01:00.0 cmd <- 03                <== The secondary graphic device
    PCI: 01:00.1 cmd <- 02
    PCI: 02:00.0 cmd <- 02
    PCI: 03:00.0 cmd <- 03
    done.
    ...snip...
    
    This patch tries to disable IO & MEM decode for the second graphic device,
    the resource conflict in windows7 resolved.
    
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d
---
 src/devices/pci_device.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 2ccb38a..5e4269d 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -494,6 +494,20 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
 			dev->command |= PCI_COMMAND_IO;
 		if (resource->flags & IORESOURCE_PCI_BRIDGE)
 			dev->command |= PCI_COMMAND_MASTER;
+
+		/* It isn't safe to enable other VGA cards,
+		 * otherwise windows will report resource conflict when
+		 * more than one graphic card in the system.
+		 */
+#if CONFIG_VGA_BRIDGE_SETUP == 1
+		extern device_t vga_pri;
+		if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
+			((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) {
+			if (dev != vga_pri) {
+				dev->command &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+			}
+		}
+#endif
 	}
 
 	/* Get the base address. */


From rockcui at viatech.com.cn  Wed Dec  7 06:18:32 2011
From: rockcui at viatech.com.cn (Rock Cui)
Date: Wed, 07 Dec 2011 13:18:32 +0800
Subject: [coreboot] About the boot steps of the coreboot-V4
Message-ID: <4EDEF728.7090100@viatech.com.cn>

Hi all,
I'm learnning the coreboot v4 source code. But when I read the file
entry32.inc, I don't know where the execution will jmp to after the
__protected_start.
I need help.

BRs,

Rock.


From n.owens at laposte.net  Wed Dec 14 01:59:58 2011
From: n.owens at laposte.net (Nathan OWENS)
Date: Tue, 13 Dec 2011 19:59:58 -0500
Subject: [coreboot] via pc2500e form factor and ROM protocol
Message-ID: <4EE7F50E.5070408@laposte.net>

Howdy All,

I've been playing with a Via PC2500e mainboard. It is listed as a
mini-ITX board on the supported boards page, but it is in fact a micro
ATX board (190mm x 228mm)

I'd also like to add the that it uses LPC as the ROM chip protocol. It
is currently listed as unknown.

No worky worky (technical term) with the SPI chips.

Keep up the good work. This is an excellent project.

Nathan Owens



From caracol at neuf.fr  Thu Dec 15 20:11:28 2011
From: caracol at neuf.fr (nap)
Date: Thu, 15 Dec 2011 20:11:28 +0100
Subject: [coreboot]  ASUS P5KPL-AM Let's play
Message-ID: <4EEA4660.60707@neuf.fr>

Let's play and contribute... Comments welcome.

The motherboard is a vanilla G31/ICH7 microATX with a LGA775 socket and
an accessible socketed DIP8.
See: http://www.asus.com/Motherboards/Intel_Socket_775/P5KPLAM/
The CPU is currently a Pentium E5300.

I have cloned the coreboot git tree and started to play with Kconfig and
read the code, to add the pieces for the support of the ASUS P5KLM-AM
board, if possible.

I have got the MB/CPU/NB/SB datasheets.

My immediate goal is to get some debug complaints from a coreboot image.

>From a first browsing of the supported motherboards, I have found the
LENOVO T60 laptop as the nearest from a CPU/chipset perspective
945GM/ICH7, but I suppose I will probably need to get pieces from an ATX MB.

I have put a renamed copy of the T60 in the motherboards/ASUS folder.

My current problems are, starting from the intel/model_f4x:
	what is a cpu_device_id (seems like a pci id) ?
	how to get the cpu_device_id(s) to put in cpu_table ?
	how is derived the cpu/intel/model name from them ?
	how to properly set the include and microcode list ?
	how to get the proper microcode ?
	how to name the 775 socket, maybe LGA775 ?
Enough for now.

nap


From gerrit at coreboot.org  Thu Dec 15 22:15:19 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 15 Dec 2011 22:15:19 +0100
Subject: [coreboot] Patch merged into coreboot/master: e5c75f4 .gitignore
	util/crossgcc/build-* and unpacked source directories
References: <I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df+0@gerrit.coreboot.org>
Message-ID: <E1RbIe7-0000o1-2q@ra.coresystems.de>

the following patch was just integrated into master:
commit e5c75f4c5fcd42f4d01deb2a9f4045df1d51e078
Author: Peter Stuge <peter at stuge.se>
Date:   Wed Dec 14 07:32:15 2011 +0100

    .gitignore util/crossgcc/build-* and unpacked source directories
    
    Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df
    Signed-off-by: Peter Stuge <peter at stuge.se>

Build-Tested: build bot (Jenkins) at Wed Dec 14 08:29:44 2011, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Thu Dec 15 22:15:16 2011, giving +2
See http://review.coreboot.org/484 for details.

-gerrit


From gerrit at coreboot.org  Fri Dec 16 04:20:17 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 16 Dec 2011 04:20:17 +0100
Subject: [coreboot] Patch set updated for coreboot: 23660d2 Fix multipleVGA
	cards resource conflict on Windows
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
Message-ID: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/489

-gerrit

commit 23660d2e26e4c63b8b2eca3c59d3bf756acadf5d
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Dec 16 11:58:47 2011 +0800

    Fix multipleVGA cards resource conflict on Windows
    
    If both legacy graphic cards decode the IO range 3B0-3DF and
    MEM range A00000-BFFFF, Windows 7 complain a resource conflict,
    so only one VGA card can works at the same time.
    
    There is a discuss in coreboot mail list before,
    please reference thread: "how to prevent legacy resource conflictwith   multipleVGA cards"
    
    Linux using VGA Arbiter module(vgaarb) to resolve this resource conflict,
    Please see the following linux dmesg log, more information can be found in
    Linux source dir Documentation/vgaarbiter.txt.
    But it seems that windows don't dealwith this conflict.
    ~# dmesg | grep -i vgaarb
    [    0.774076] vgaarb: device added: PCI:0000:00:01.0,decodes=io+mem,owns=io+mem
    [    0.776065] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,l
    [    0.780051] vgaarb: loaded
    [    0.784049] vgaarb: bridge control possible 0000:01:00.0
    [    0.788050] vgaarb: bridge control possible 0000:00:01.0
    
    For the second legacy graphic device, coreboot already disabled the
    IO and MEM decode in function set_vga_bridge_bits().
    But it will be enabled again in function pci_set_resource(),
    if the second legacy graphic device take any IO/MEM resources.
    
    Following log printed by enable_resources() shows the problem:
    ...snip...
    PCI: 00:00.0 cmd <- 06
    PCI: 00:01.0 subsystem <- 1022/1410
    PCI: 00:01.0 cmd <- 07                <== The first graphic device
    PCI: 00:01.1 subsystem <- 1022/1410
    PCI: 00:01.1 cmd <- 02
    PCI: 00:02.0 bridge ctrl <- 0003
    PCI: 00:02.0 cmd <- 07
    ...snip...
    PCI: 01:00.0 cmd <- 03                <== The second graphic device
    PCI: 01:00.1 cmd <- 02
    PCI: 02:00.0 cmd <- 02
    PCI: 03:00.0 cmd <- 03
    done.
    ...snip...
    
    This patch tries to disable IO & MEM decode for the second graphic device,
    the resource conflict in windows7 resolved.
    
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d
---
 src/devices/pci_device.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 2ccb38a..0d57977 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -494,6 +494,20 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
 			dev->command |= PCI_COMMAND_IO;
 		if (resource->flags & IORESOURCE_PCI_BRIDGE)
 			dev->command |= PCI_COMMAND_MASTER;
+
+		/* It isn't safe to enable other VGA cards,
+		 * otherwise windows will report resource conflict when
+		 * more than one legacy graphic card in the system.
+		 */
+#if CONFIG_VGA_BRIDGE_SETUP == 1
+		extern device_t vga_pri;
+		if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
+			((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) {
+			if (dev != vga_pri) {
+				dev->command &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+			}
+		}
+#endif
 	}
 
 	/* Get the base address. */


From Kerry.She at amd.com  Fri Dec 16 09:10:44 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Fri, 16 Dec 2011 16:10:44 +0800
Subject: [coreboot] About the boot steps of the coreboot-V4
In-Reply-To: <4EDEF728.7090100@viatech.com.cn>
References: <4EDEF728.7090100@viatech.com.cn>
Message-ID: <F53A09371FB723428826B442A4B20A41089821BA@sbjgexmb1.amd.com>

Hello, Rock

You may need to have a look at the crt0.S,
Take amd/persimmon as an example:
#include "config.h"
 #include "src/arch/x86/init/prologue.inc"
 #include "src/cpu/x86/32bit/entry32.inc"
 #include "src/cpu/x86/fpu_enable.inc"
 #include "src/cpu/amd/agesa/cache_as_ram.inc"
 #include "mainboard/amd/persimmon/romstage.inc"
~

"build/romstage/crt0.S"

But I think it's better to learn coreboot by playing with it
on a mainboard than just reading the code.
thanks

> -----Original Message-----
> From: coreboot-bounces+kerry.she=amd.com at coreboot.org
[mailto:coreboot-
> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Rock Cui
> Sent: Wednesday, December 07, 2011 1:19 PM
> To: coreboot at coreboot.org
> Subject: [coreboot] About the boot steps of the coreboot-V4
> 
> Hi all,
> I'm learnning the coreboot v4 source code. But when I read the file
> entry32.inc, I don't know where the execution will jmp to after the
> __protected_start.
> I need help.
> 
> BRs,
> 
> Rock.
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




From neverforget_2002 at 163.com  Fri Dec 16 10:04:07 2011
From: neverforget_2002 at 163.com (Cui Lei)
Date: Fri, 16 Dec 2011 17:04:07 +0800
Subject: [coreboot] About the boot steps of the coreboot-V4
In-Reply-To: <F53A09371FB723428826B442A4B20A41089821BA@sbjgexmb1.amd.com>
References: <4EDEF728.7090100@viatech.com.cn>
	<F53A09371FB723428826B442A4B20A41089821BA@sbjgexmb1.amd.com>
Message-ID: <4EEB0987.1000605@163.com>

Hi, Kerry

Thank you for your reply. I find after __protected_start the execution 
will go to the fpu_start (in the fpu_enable.inc), then go to the 
cache_as_ram. Now I have a new problem, on my mainboard , there are more 
than 2minutes delay between __protected_start and __fpu_start, but on 
another mainboard(I just change the romsip code in order to run), it is 
ok. If I move the fpu_start code to the entry32.inc, the delay will be 
after the __fpu_star

BRs,
Rock.

> Hello, Rock
>
> You may need to have a look at the crt0.S,
> Take amd/persimmon as an example:
> #include "config.h"
>   #include "src/arch/x86/init/prologue.inc"
>   #include "src/cpu/x86/32bit/entry32.inc"
>   #include "src/cpu/x86/fpu_enable.inc"
>   #include "src/cpu/amd/agesa/cache_as_ram.inc"
>   #include "mainboard/amd/persimmon/romstage.inc"
> ~
>
> "build/romstage/crt0.S"
>
> But I think it's better to learn coreboot by playing with it
> on a mainboard than just reading the code.
> thanks
>
>> -----Original Message-----
>> From: coreboot-bounces+kerry.she=amd.com at coreboot.org
> [mailto:coreboot-
>> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Rock Cui
>> Sent: Wednesday, December 07, 2011 1:19 PM
>> To: coreboot at coreboot.org
>> Subject: [coreboot] About the boot steps of the coreboot-V4
>>
>> Hi all,
>> I'm learnning the coreboot v4 source code. But when I read the file
>> entry32.inc, I don't know where the execution will jmp to after the
>> __protected_start.
>> I need help.
>>
>> BRs,
>>
>> Rock.
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>




From Kerry.She at amd.com  Fri Dec 16 10:48:39 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Fri, 16 Dec 2011 17:48:39 +0800
Subject: [coreboot] FW:  About the boot steps of the coreboot-V4
Message-ID: <F53A09371FB723428826B442A4B20A4108982375@sbjgexmb1.amd.com>

Hello, Rock

> -----Original Message-----
> From: Cui Lei [mailto:neverforget_2002 at 163.com]
> Sent: Friday, December 16, 2011 5:04 PM
> To: She, Kerry
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] About the boot steps of the coreboot-V4
> 
> Hi, Kerry
> 
> Thank you for your reply. I find after __protected_start the execution
> will go to the fpu_start (in the fpu_enable.inc), then go to the
> cache_as_ram. Now I have a new problem, on my mainboard , there are
more
> than 2minutes delay between __protected_start and __fpu_start, but on
> another mainboard(I just change the romsip code in order to run), it
is
> ok. If I move the fpu_start code to the entry32.inc, the delay will be
> after the __fpu_star
What platform do you use?
Can you provide some information about the mainboard, chipset and rom
chip,
With more information in detail, Maybe somebody else can assist.
thanks
 
> BRs,
> Rock.
> 
> > Hello, Rock
> >
> > You may need to have a look at the crt0.S,
> > Take amd/persimmon as an example:
> > #include "config.h"
> >   #include "src/arch/x86/init/prologue.inc"
> >   #include "src/cpu/x86/32bit/entry32.inc"
> >   #include "src/cpu/x86/fpu_enable.inc"
> >   #include "src/cpu/amd/agesa/cache_as_ram.inc"
> >   #include "mainboard/amd/persimmon/romstage.inc"
> > ~
> >
> > "build/romstage/crt0.S"
> >
> > But I think it's better to learn coreboot by playing with it
> > on a mainboard than just reading the code.
> > thanks
> >
> >> -----Original Message-----
> >> From: coreboot-bounces+kerry.she=amd.com at coreboot.org
> > [mailto:coreboot-
> >> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of Rock Cui
> >> Sent: Wednesday, December 07, 2011 1:19 PM
> >> To: coreboot at coreboot.org
> >> Subject: [coreboot] About the boot steps of the coreboot-V4
> >>
> >> Hi all,
> >> I'm learnning the coreboot v4 source code. But when I read the file
> >> entry32.inc, I don't know where the execution will jmp to after the
> >> __protected_start.
> >> I need help.
> >>
> >> BRs,
> >>
> >> Rock.
> >>
> >> --
> >> coreboot mailing list: coreboot at coreboot.org
> >> http://www.coreboot.org/mailman/listinfo/coreboot
> >
> 
> 




From gerrit at coreboot.org  Sat Dec 17 00:47:59 2011
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Sat, 17 Dec 2011 00:47:59 +0100
Subject: [coreboot] New patch to review for coreboot: b751de8 Persimmon
	audio codec verb patch.
References: <I067506871e92078d122cf79872363d8937d47e50+0@gerrit.coreboot.org>
Message-ID: <I067506871e92078d122cf79872363d8937d47e50+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/490

-gerrit

commit b751de894b1a7126b5182fefb9e048c5ffc45597
Author: Marc Jones <marcj303 at gmail.com>
Date:   Wed Dec 14 11:24:00 2011 -0700

    Persimmon audio codec verb patch.
    
    Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
    data is not required for mainboards that use G-Series HDMI. It is also a setting
    the may be boards specific. This fixes issues with Windows audio on Persimmon.
    
    Change-Id: I067506871e92078d122cf79872363d8937d47e50
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/persimmon/platform_cfg.h |   29 ++++++++++++++++++++++++++++
 src/southbridge/amd/cimx/sb800/cfg.c       |    5 ++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
index 66aab8b..97aa47e 100644
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -227,4 +227,33 @@
  */
 #define GEC_CONFIG			0
 
+const static CODECENTRY persimmon_codec_alc269[] =
+{
+	/* NID, PinConfig */
+	{0x12, 0x411111F0},
+	{0x14, 0x99130110},
+	{0x21, 0x0121401F},
+	{0x17, 0x411111F0},
+	{0x18, 0x01A19820},
+	{0x19, 0x411111F0},
+	{0x1A, 0x0181302F},
+	{0x1B, 0x411111F0},
+	{0x1D, 0x40069E05},
+	{0x1E, 0x411111F0},
+	{0x20, 0x0001FFFF},
+	{0xff, 0xffffffff} /* end of table */
+};
+
+const static CODECTBLLIST persimmon_codec_tablelist[] =
+{
+	{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
+	{0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL}
+};
+
+/**
+ * @def AZALIA_OEM_VERB_TABLE
+ *  Mainboard specific cocec verb table list
+ */
+#define AZALIA_OEM_VERB_TABLE		(&persimmon_codec_tablelist[0])
+
 #endif
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 2998fa2..a9e35bc 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -91,7 +91,12 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
 	sb_config->AzaliaController = AZALIA_CONTROLLER;
 	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
 	sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN;
+	/* Mainboard Specific Azalia Cocec Verb Table */
+#ifdef AZALIA_OEM_VERB_TABLE
+	sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = (CODECTBLLIST *)AZALIA_OEM_VERB_TABLE;
+#else
 	sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
+#endif
 
 	/* LPC */
 	/* SuperIO hardware monitor register access */


From gerrit at coreboot.org  Sat Dec 17 18:46:13 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sat, 17 Dec 2011 18:46:13 +0100
Subject: [coreboot] New patch to review for coreboot: 819d423 Add Intel
	i5000 Memory Controller Hub
References: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+0@gerrit.coreboot.org>
Message-ID: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/491

-gerrit

commit 819d423cf4af8ed40b184128f8f5c64f027f1205
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:21:01 2011 +0100

    Add Intel i5000 Memory Controller Hub
    
    Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/northbridge/intel/Kconfig             |    1 +
 src/northbridge/intel/Makefile.inc        |    1 +
 src/northbridge/intel/i5000/Kconfig       |   38 +
 src/northbridge/intel/i5000/Makefile.inc  |   21 +
 src/northbridge/intel/i5000/chip.h        |   23 +
 src/northbridge/intel/i5000/northbridge.c |  189 ++++
 src/northbridge/intel/i5000/raminit.c     | 1510 +++++++++++++++++++++++++++++
 src/northbridge/intel/i5000/raminit.h     |  326 +++++++
 src/northbridge/intel/i5000/udelay.c      |   85 ++
 9 files changed, 2194 insertions(+), 0 deletions(-)

diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig
index 1809d11..2b25ac4 100644
--- a/src/northbridge/intel/Kconfig
+++ b/src/northbridge/intel/Kconfig
@@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig
 source src/northbridge/intel/i855/Kconfig
 source src/northbridge/intel/i945/Kconfig
 source src/northbridge/intel/sch/Kconfig
+source src/northbridge/intel/i5000/Kconfig
\ No newline at end of file
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc
index 0d116d0..db59cf0 100644
--- a/src/northbridge/intel/Makefile.inc
+++ b/src/northbridge/intel/Makefile.inc
@@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
\ No newline at end of file
diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig
new file mode 100644
index 0000000..41c523d
--- /dev/null
+++ b/src/northbridge/intel/i5000/Kconfig
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_I5000
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+
+config NORTHBRIDGE_INTEL_I5000_MEMBIST
+	bool
+	prompt "Run Memory selfcheck (MEMBIST) during initialization"
+	default y
+	help
+		FBDIMM memory modules have a controller called 'Advanced Memory
+		Buffer' which allows to test the Memories used on that module.
+		Select yes to do a quick memory check after AMBs have been
+		initialized. This option can be used to check if the Memory
+		module has been correctly initialized, without depending on Northbridge
+		setup.
+
+config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	bool
+	prompt "Run ramcheck after RAM initialization"
diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc
new file mode 100644
index 0000000..a5623c0
--- /dev/null
+++ b/src/northbridge/intel/i5000/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
+romstage-y += raminit.c udelay.c
diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h
new file mode 100644
index 0000000..a23be90
--- /dev/null
+++ b/src/northbridge/intel/i5000/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_intel_i5000_config {
+};
+
+extern struct chip_operations northbridge_intel_i5000_ops;
diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c
new file mode 100644
index 0000000..4f20f78
--- /dev/null
+++ b/src/northbridge/intel/i5000/northbridge.c
@@ -0,0 +1,189 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "chip.h"
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x25d8,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+#include <cbmem.h>
+#endif
+
+static void pci_domain_set_resources(device_t dev)
+{
+	struct resource *resource;
+	uint32_t tolm;
+	uint32_t hecbase;
+	uint64_t ambase;
+//	uint64_t val;
+	uint32_t amsize;
+	int idx = 0;
+	device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));
+//	device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
+
+	tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;
+	hecbase = pci_read_config16(dev16_0, 0x64) >> 12;
+	hecbase &= 0xffff;
+
+	ambase = ((u64)pci_read_config32(dev16_0, 0x48) |
+		  (u64)pci_read_config32(dev16_0, 0x4c) << 32);
+
+	amsize = pci_read_config32(dev16_0, 0x50);
+	ambase &= 0x000000ffffff0000;
+
+	printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase);
+
+	/* Report the memory regions */
+	ram_resource(dev, idx++, 0, 640);
+	ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
+#if 0
+	if (tolm == 0xe0000000 && (val = pci_read_config16(dev16_1, 0x80)) > 0) {
+		val &= 0xfff0;
+		val <<= 34;
+		if (val > 4 * 1048576) {
+			val -= 4 * 1048576;
+			printk(BIOS_INFO, "memory above 4GB: %lldMB\n", val / 1024);
+			ram_resource(dev, idx++, 4096 * 1024, val);
+		}
+	}
+#endif
+	if (hecbase) {
+		printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28);
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)(uint64_t)hecbase << 28 ;
+		resource->size = (resource_t)256 * 1024 * 1024;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)(uint64_t)0xffe00000;
+	resource->size = (resource_t)0x200000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	if (ambase && amsize) {
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)ambase;
+		resource->size = (resource_t)amsize;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+			IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	/* add resource for 0xfe6xxxxx range. This range is used by i5000 for
+	   various fixed address registers (BOFL, SPAD, SPADS */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfe600000;
+	resource->size = (resource_t)0x00100000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	assign_resources(dev->link_list);
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = tolm - HIGH_MEMORY_SIZE;
+	high_tables_size = HIGH_MEMORY_SIZE;
+	printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size);
+#endif
+}
+
+static struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init             = NULL,
+	.scan_bus         = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+static void enable_dev(device_t dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_i5000_ops = {
+	CHIP_NAME("Intel i5000 Northbridge")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
new file mode 100644
index 0000000..d833563
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -0,0 +1,1510 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "raminit.h"
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <spd.h>
+#include <types.h>
+#include <southbridge/intel/i63xx/early_smbus.c>
+#include <string.h>
+#include <cbmem.h>
+#include <stdlib.h>
+#include <lib.h>
+#include <delay.h>
+
+static int i5000_for_each_channel(struct i5000_fbd_branch *branch,
+				  int (*cb)(struct i5000_fbd_channel *))
+{
+	struct i5000_fbd_channel *c;
+	int ret;
+
+	for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
+		if (c->used && (ret = cb(c)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_branch(struct i5000_fbd_setup *setup,
+				 int (*cb)(struct i5000_fbd_branch *))
+{
+	struct i5000_fbd_branch *b;
+	int ret;
+
+	for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
+		if (b->used && (ret = cb(b)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_dimm(struct i5000_fbd_setup *setup,
+			       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if ((ret = cb(d))) {
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup,
+				       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if (d->present && (ret = cb(d)))
+			return ret;
+	}
+	return 0;
+}
+
+static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)
+{
+	u16 status;
+	device_t dev = d->branch->branchdev;
+
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	while(count-- > 0) {
+		pci_write_config32(dev, cmdreg, 0xa8000000 |	\
+				   (d->num & 0x03) << 24 | addr++ << 16);
+
+		for(;;) {
+			status = pci_read_config16(dev,	stsreg);
+
+			if (status & I5000_SPD_SBE)
+				return -1;
+
+			if (status & I5000_SPD_BUSY)
+				continue;
+
+			if (status & I5000_SPD_RDO) {
+				*out = status & 0xff;
+				out++;
+				break;
+			}
+		}
+	}
+	return 0;
+}
+
+static void i5000_clear_fbd_errors(void)
+{
+	device_t dev16_1, dev16_2;
+
+	dev16_1 = PCI_ADDR(0, 16, 1, 0);
+	dev16_2 = PCI_ADDR(0, 16, 2, 0);
+
+	pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL));
+
+	pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL));
+}
+
+static int i5000_branch_reset(struct i5000_fbd_branch *b)
+{
+	device_t dev = b->branchdev;
+
+	pci_write_config8(dev, I5000_FBDRST, 0x00);
+
+	udelay(5000);
+
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	udelay(1);
+	pci_write_config8(dev, I5000_FBDRST, 0x04);
+	udelay(2);
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	pci_write_config8(dev, I5000_FBDRST, 0x07);
+	return 0;
+}
+
+static const int fsbdivs[] = {
+	[DDR_400MHZ] = 500,
+	[DDR_533MHZ] = 375,
+	[DDR_667MHZ] = 300,
+	[DDR_800MHZ] = 250,
+};
+
+static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)
+{
+	int ret = (del * 100) / fsbdivs[d->setup->ddr_speed];
+	return ret;
+}
+
+static int mtb2clks(struct i5000_fbdimm *d, int del)
+{
+	int ret = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * fsbdivs[d->setup->ddr_speed]);
+	if ((ret % 10) > 0)
+		ret += 10;
+	ret /= 10;
+	return ret;
+}
+
+static int i5000_read_spd_data(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr;
+	u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min;
+	u8 cmd2data_addr;
+	int t_ck_min;
+
+	s = d->setup;
+	if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) {
+		printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n",
+		       d->branch->num, d->channel->num, d->num);
+		return 0; // No FBDIMM present
+	}
+
+	if (val != 0x09)
+		return 0; // SDRAM type not FBDIMM
+
+	if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes))
+		return 0;
+
+	switch(d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_533;
+		break;
+
+	case DDR_667MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_667;
+		break;
+
+	case DDR_800MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_800;
+		break;
+	default:
+		printk(BIOS_ERR, "Unsupported FBDIMM clock\n");
+		return -1;
+	}
+
+	if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) ||
+	    spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) ||
+	    spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) ||
+	    spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) ||
+	    spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) ||
+	    spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) ||
+	    spd_read_byte(d, cmd2data_addr, 1, &d->cmd2datanxt) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) {
+		printk(BIOS_ERR, "failed to read data from SPD\n");
+		return 0;
+	}
+
+
+	t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor;
+	if (t_ck_min <= 250)
+		d->speed = DDR_800MHZ;
+	else if (t_ck_min <= 300)
+		d->speed = DDR_667MHZ;
+	else if (t_ck_min <= 375)
+		d->speed = DDR_533MHZ;
+	else if (t_ck_min <= 500)
+		d->speed = DDR_400MHZ;
+	else {
+		printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min);
+		return -1;
+	}
+
+	d->sdram_width = org & 0x07;
+	if (d->sdram_width > 1) {
+		printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width);
+		return 0;
+	}
+
+	s->ddr_speed = MIN(s->ddr_speed, d->speed);
+
+	d->banks = 4 << (addr & 0x03);
+	d->columns = 9 + ((addr >> 2) & 0x03);
+	d->rows = 12 + ((addr >> 5) & 0x03);
+	d->ranks = (org >> 3) & 0x03;
+	d->min_cas_latency = cas & 0x0f;
+
+	d->setup->bl &= bl;
+
+	if (!d->setup->bl) {
+		printk(BIOS_ERR, "no compatible burst length found\n");
+		return -1;
+	}
+
+	s->t_rc = MAX(s->t_rc, mtb2clks(d,
+				 t_rc | ((t_ras_rc_h & 0xf0) << 4)));
+	s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd));
+	s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc));
+	s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd));
+	s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min));
+	s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr));
+	s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp));
+	s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp));
+	s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr));
+	s->t_ras = MAX(s->t_ras, mtb2clks(d,
+				 t_ras | ((t_ras_rc_h & 0x0f) << 8)));
+	s->t_r2r = MAX(s->t_r2r, bb & 3);
+	s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3);
+	s->t_w2r = MAX(s->t_w2r, ((bb >> 2) & 3));
+
+	d->size = (1 << (d->banks + d->columns + d->rows + d->ranks)) >> 20;
+	d->branch->totalmem += d->size;
+	s->totalmem += d->size;
+
+	d->channel->columns = d->columns;
+	d->channel->rows = d->rows;
+	d->channel->ranks = d->ranks;
+	d->channel->banks = d->banks;
+	d->channel->width = d->sdram_width;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d %dMB: %d banks, "
+	       "%d columns, %d rows, %d ranks\n",
+	       d->branch->num, d->channel->num, d->num, d->size,
+	       d->banks, d->columns, d->rows, d->ranks);
+
+	d->present = 1;
+	d->branch->used |= 1;
+	d->channel->used |= 1;
+	d->channel->highest_amb = d->num;
+	return 0;
+}
+
+static int i5000_amb_smbus_write(struct i5000_fbdimm *d,  int byte1, int byte2)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16) | (byte2 << 8) | 1);
+
+	for(;;) {
+		status = pci_read_config16(dev,	stsreg);
+
+		if (status & I5000_SPD_BUSY)
+			continue;
+
+		if (status & I5000_SPD_SBE)
+			break;
+
+		if (status & I5000_SPD_WOD)
+			return 0;
+	}
+	printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",
+	       d->branch->num, d->channel->num, d->num, byte1, byte2, status);
+	return -1;
+
+}
+
+static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16));
+
+	for(;;) {
+		status = pci_read_config16(dev,	stsreg);
+
+		if (status & I5000_SPD_SBE)
+			break;
+
+		if (status & I5000_SPD_BUSY)
+			continue;
+
+		if (status & I5000_SPD_RDO) {
+			*out = status & 0xff;
+			return 0;
+		}
+	}
+	return -1;
+
+}
+
+static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d,
+					 int fn, int reg, u8 val)
+{
+	if (i5000_amb_smbus_write(d, 0x84, 00) ||
+	    i5000_amb_smbus_write(d, 0x04, fn) ||
+	    i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x04, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x44, val)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d,
+					  int fn, int reg, u16 val)
+{
+	if (i5000_amb_smbus_write(d, 0x88, 00) ||
+	    i5000_amb_smbus_write(d, 0x08, fn) ||
+	    i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x48, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d,
+					  int fn, int reg, u32 val)
+{
+	if (i5000_amb_smbus_write(d, 0x8c, 00) ||
+	    i5000_amb_smbus_write(d, 0x0c, fn) ||
+	    i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x4c, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
+					 int fn, int reg, u32 *val)
+{
+	u8 byte3, byte2, byte1, byte0;
+
+	if (i5000_amb_smbus_write(d, 0x80, 00) ||
+	    i5000_amb_smbus_write(d, 0x00, fn) ||
+	    i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x40, reg & 0xff) ||
+	    i5000_amb_smbus_read(d, 0x80, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte2) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte1) ||
+	    i5000_amb_smbus_read(d, 0x40, &byte0)) {
+		printk(BIOS_ERR, "AMB SMBUS read failed\n");
+		return 1;
+	}
+	*val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
+	return 0;
+}
+
+static void i5000_amb_write_config8(struct i5000_fbdimm *d,
+				    int fn, int reg, u32 val)
+{
+	write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config16(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config32(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
+				   int fn, int reg)
+{
+	return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
+}
+
+static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
+{
+	u32 drc, status;
+
+	printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...",
+		d->branch->num, d->channel->num, d->num, rank, command, addr);
+
+	drc = i5000_amb_read_config32(d, 3, AMB_DRC);
+	drc &= ~((3 << 9) | (1 << 12));
+	drc |= (rank << 9);
+
+	i5000_amb_write_config32(d, 3, AMB_DRC, drc);
+	i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr);
+	i5000_amb_write_config32(d, 4, AMB_DCALCSR,
+				 (rank << 21) | (command & 0x0f) | AMB_DCALCSR_START);
+
+	udelay(1000);
+	while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
+	      & (1 << 31));
+
+	if (status & (1 << 30)) {
+		printk(BIOS_SPEW, "failed (status 0x%08x)\n", status);
+		return -1;
+	} else {
+		printk(BIOS_SPEW, "done\n");
+	}
+	return 0;
+}
+
+static int i5000_ddr_calibration(struct i5000_fbdimm *d)
+{
+	u32 status;
+
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	if (ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||
+	    ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))
+		return -1;
+	return 0;
+}
+
+static int i5000_ddr_init(struct i5000_fbdimm *d)
+{
+
+	int rank;
+	u32 val;
+	u8 odt;
+
+	for(rank = 0; rank < d->ranks; rank++) {
+		printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,
+		       d->branch->num, d->channel->num, d->num, rank);
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_NOP))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		/* EMRS(2) */
+		if (ddr_command(d, 1 << rank,
+				2, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(3) */
+		if (ddr_command(d, 1 << rank,
+				3, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(1) */
+		if (ddr_command(d, 1 << rank,
+				1, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* MRS: DLL reset */
+		if (ddr_command(d, 1 << rank,
+				0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		udelay(200);
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		if (ddr_command(d, 1 << rank, 0,
+				AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		/* burst length + cas latency */
+		val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) |
+			(1 << 19) /* interleaved burst */ |
+			(d->setup->t_cl << 20) |
+			(((d->setup->t_wr - 1) & 7) << 25);
+
+		printk(BIOS_DEBUG, "MRS: 0x%08x\n", val);
+		if (ddr_command(d, 1 << rank,
+				val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* OCD calibration default */
+		if (ddr_command(d, 1 << rank, 0x03800001,
+				AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+
+		odt = d->odt;
+		if (rank)
+			odt >>= 4;
+
+		val = (d->setup->t_al << 19) |
+			((odt & 1) << 18) |
+		        ((odt & 2) << 21) | 1;
+
+		printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
+
+		/* ODT, OCD exit, additive latency */
+		if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_preinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+	u32 id, drc;
+
+	printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__,
+	       d->branch->num, d->channel->num, d->num);
+
+	i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]);
+	i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);
+
+	drc = (d->setup->t_al << 4) | (d->setup->t_cl);
+	printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc, d->cmd2datanxt);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, 0x20909);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651);
+	i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT, d->cmd2datanxt);
+	i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc);
+
+	if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) {
+		d->vendor = id & 0xffff;
+		d->device = id >> 16;
+	}
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);
+	return 0;
+}
+
+static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)
+{
+	device_t dev = b->branchdev;
+
+	printk(BIOS_DEBUG, "  FBD state branch %d: %02x, ", b->num, state);
+
+	pci_mmio_write_config8(dev, I5000_FBDHPC, state);
+
+	printk(BIOS_DEBUG, "waiting for new state...");
+	while(pci_mmio_read_config8(dev, I5000_FBDST) != state);
+	printk(BIOS_DEBUG, "done\n");
+}
+
+static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)
+{
+	int i = 10;
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
+
+	printk(BIOS_DEBUG, "      waiting for pattern recognition...");
+	while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0)
+		udelay(5000);
+
+	printk(BIOS_DEBUG, i ?  "done\n" : "failed\n");
+	return !i;
+}
+
+static const char *pattern_names[16] = {
+	"EI", "EI", "EI", "EI",
+	"EI", "EI", "EI", "EI",
+	"TS0", "TS1", "TS2", "TS3",
+	"RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones",
+};
+
+static int i5000_set_ambpresent(struct i5000_fbd_channel *c)
+{
+	int i;
+	device_t branchdev = c->branch->branchdev;
+	u16 ambpresent = 0x8000;
+
+	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+		if (c->dimm[i].present)
+			ambpresent |= (1 << i);
+	}
+
+	printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent);
+	pci_write_config16(branchdev,
+			   c->num ?
+			   I5000_AMBPRESENT1 :		\
+			   I5000_AMBPRESENT0, ambpresent);
+
+	return 0;
+}
+
+static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait)
+{
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
+
+	printk(BIOS_DEBUG, "    %d/%d  driving pattern %s to AMB%d (%02x)\n",
+	       c->branch->num, c->num,
+	       pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);
+	pci_mmio_write_config8(dev, 0, pattern);
+
+	if (!wait)
+		return 0;
+
+
+	return i5000_wait_pattern_recognized(c);
+}
+
+static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->num ? 0x100 : 0;
+	u32 portctl;
+	int i, cnt = 1000;
+
+
+	portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
+	portctl &= ~0x01000020;
+	if (mchpad)
+		portctl |= 0x00800000;
+	else
+		portctl &= ~0x00800000;
+	portctl &= ~0x01000020;
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
+
+	/* drive calibration patterns */
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))
+		return -1;
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))
+		return -1;
+
+	while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
+		udelay(1000);
+
+	if (!cnt) {
+		printk(BIOS_ERR, "IBIST timeout\n");
+		return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	for(i = 0; i < highest_amb; i++) {
+		if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))
+			return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	printk(BIOS_DEBUG, "Round trip latency: %d\n",
+	       pci_mmio_read_config8(branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1))
+		return -1;
+
+	if (i5000_set_ambpresent(c))
+		return -1;
+	return 0;
+}
+
+static int i5000_train_channel_idle(struct i5000_fbd_channel *c)
+{
+	return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1);
+}
+
+static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c)
+{
+	if (i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 0);
+}
+
+static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)
+{
+	if (i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 1);
+}
+
+static int i5000_setup_channel(struct i5000_fbd_channel *c)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->branch->num ? 0x100 : 0;
+	u32 val;
+
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
+
+	pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
+
+	/* unknown */
+	val = pci_mmio_read_config32(branchdev, off + 0x0164);
+	val &= 0xfffbcffc;
+	val |= 0x4004;
+	pci_mmio_write_config32(branchdev, off + 0x164, val);
+
+	pci_mmio_write_config32(branchdev, off + 0x15c, 0xff);
+	i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);
+	return 0;
+}
+
+static int i5000_link_training0(struct i5000_fbd_branch *b)
+{
+	device_t branchdev = b->branchdev;
+
+	pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
+
+	if (i5000_for_each_channel(b, i5000_setup_channel))
+		return -1;
+
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns0))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+static int i5000_link_training1(struct i5000_fbd_branch *b)
+{
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns1))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+
+static int i5000_amb_check(struct i5000_fbdimm *d)
+{
+	u32 id = i5000_amb_read_config32(d, 0, 0);
+	printk(BIOS_INFO, "AMB %d/%d/%d ID: %04x:%04x\n",
+	       d->branch->num, d->channel->num, d->num,
+	       id & 0xffff, id >> 16);
+
+	if ((id & 0xffff) != d->vendor || id >> 16 != d->device) {
+		printk(BIOS_ERR, "AMB mapping failed\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_postinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+
+	i5000_amb_write_config16(d, 4, 0xb6, p16[3]);
+	i5000_amb_write_config32(d, 4, 0xb8, p32[2]);
+	i5000_amb_write_config16(d, 4, 0xbc, p16[6]);
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
+
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, d->num ? 0x21b1b : 0x20b1b);
+	return 0;
+}
+
+static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u32 val, tref;
+	int refi;
+
+	s = d->setup;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n",
+	       d->branch->num, d->channel->num, d->num);
+
+	val = 0x44;
+	printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val);
+	i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val);
+
+	val = (0x0c << 24) | /* CLK control */
+		(1 << 18) | /* ODTZ enabled */
+		(((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */
+		((d->setup->t_al & 0x0f) << 4) | /* additive latency */
+		(d->setup->t_cl & 0x0f); /* CAS latency */
+
+	if (d->ranks > 1) {
+		val |= (0x03 << 9);
+	} else {
+		val |= (0x01 << 9);
+	}
+
+	printk(BIOS_DEBUG, "\tAMB_DRC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRC, val);
+
+	val = (d->sdram_width << 30) |
+		((d->ranks == 2 ? 1 : 0) << 29) |
+		((d->banks == 8 ? 1 : 0) << 28) |
+		((d->rows - 13) << 26) |
+		((d->columns - 10) << 24) |
+		(1 << 16) | /* Auto refresh exit */
+		(0x27 << 8) | /* t_xsnr */
+		(d->setup->t_rp << 4) |
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f);
+
+	printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, val);
+
+	tref = 15;
+	s->t_ref = tref;
+	switch(d->t_refi & 0x0f) {
+	case 0:
+		refi = 15625;
+		tref = 15;
+		break;
+	case 1:
+		refi = 3900;
+		tref = 3;
+		break;
+	case 2:
+		refi = 7800;
+		tref = 7;
+		break;
+	case 3:
+		refi = 31250;
+		break;
+	case 4:
+		refi = 62500;
+		break;
+	case 5:
+		refi = 125000;
+		break;
+	default:
+		printk(BIOS_ERR, "unsupported t_refi value: %d\n", d->t_refi & 0x0f);
+		refi = 7800;
+		break;
+	}
+
+	s->t_ref = MIN(s->t_ref, tref);
+	val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16);
+	printk(BIOS_INFO, "\tAMB_DAREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC, val);
+
+	u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) +
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor));
+	u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr;
+
+	val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) |
+		((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) |
+		((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) |
+		((s->t_rtp - 2) << 27);
+
+	switch(s->t_ras) {
+	default:
+		break;
+	case 15:
+		val |= (1 << 29);
+		break;
+	case 12:
+		val |= (2 << 29);
+		break;
+	}
+
+	printk(BIOS_INFO, "\tAMB_DRT: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRT, val);
+	return 0;
+}
+
+static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern)
+{
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n",
+	       d->branch->num, d->channel->num, d->num, rank, pattern);
+
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC,
+				 i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000);
+
+	i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678);
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8));
+	return 0;
+}
+
+static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank)
+{
+	int cnt = 1000;
+	u32 res;
+
+	while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
+		udelay(1000);
+
+	if (cnt && !(res & (1 << 30)))
+		return 0;
+
+	printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n",
+	       d->branch->num, d->channel->num, d->num, rank);
+	return -1;
+}
+
+static int i5000_amb_membist_random1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_random2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status1(struct i5000_fbdimm *d)
+{
+	if (i5000_do_amb_membist_status(d, 1))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status2(struct i5000_fbdimm *d)
+{
+	if (d->ranks < 2)
+		return 0;
+
+	if (i5000_do_amb_membist_status(d, 2))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_end(struct i5000_fbdimm *d)
+{
+	printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC));
+	return 0;
+}
+
+static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d)
+{
+	u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC);
+	tmp &= ~(1 << 16);
+	printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp);
+	return 0;
+}
+
+static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
+{
+	u32 val;
+
+	if (c->dimm[0].present || c->dimm[1].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 2) |
+		       (((c->ranks == 2) ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR0: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr, val);
+	}
+
+	if (c->dimm[2].present || c->dimm[3].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 4) |
+		       ((c->ranks ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR1: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr+2, val);
+	}
+}
+
+static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
+{
+	device_t dev16 = PCI_ADDR(0, 16, 1, 0);
+	device_t dev;
+	u32 tolm, mir, drta, drtb, mc, mca;
+	char ethrot;
+	int t_wrc, bl2, branch;
+
+	bl2 = (setup->bl & BL_BL8) ? 4 :2;
+	t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 +
+		 setup->t_wr + setup->t_rp;
+
+	drta = (setup->t_ref & 0x0f) |
+		((setup->t_rrd & 0x0f) << 4) |
+		((setup->t_rfc & 0xff) << 8) |
+		((setup->t_rc & 0x3f) << 16) |
+		((t_wrc & 0x3f) << 22) |
+		(setup->t_al & 0x07) << 28;
+
+	drtb = (bl2) |
+		(((1 + bl2 + setup->t_r2r) & 0x0f) << 4) |
+		(((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) |
+		(((2 + bl2 + setup->t_r2w) & 0x0f) << 12) |
+		 (((bl2 + setup->t_w2rdr) & 0x07) << 16);
+
+	switch(setup->ddr_speed) {
+	case DDR_400MHZ:
+	case DDR_533MHZ:
+		ethrot = 0;
+		break;
+	case DDR_667MHZ:
+		ethrot = 1;
+		break;
+	case DDR_800MHZ:
+		ethrot = 2;
+		break;
+	default:
+		ethrot = 3;
+		break;
+	}
+
+	mc = (1 << 30) | /* enable retry */
+		(3 << 25) | /* bad RAM threshold */
+		(1 << 21) | /* INITDONE */
+		(1 << 20) | /* FSB enable */
+		(ethrot << 18) | /* Electrical throttling: 20 clocks */
+		(1 << 8) | /* enhanced scrub mode */
+		(1 << 7) | /* enable patrol scrub */
+		(1 << 6) | /* enable demand scrubing */
+		(1 << 5); /* enable northbound error detection */
+
+	printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
+	pci_mmio_write_config32(dev16, I5000_DRTA, drta);
+	pci_mmio_write_config32(dev16, I5000_DRTB, drtb);
+	pci_mmio_write_config32(dev16, I5000_MC, mc);
+
+	mca = pci_mmio_read_config32(dev16, I5000_MCA);
+
+	mca |= (7 << 28);
+	if (setup->single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);
+	pci_mmio_write_config32(dev16, I5000_MCA, mca);
+
+	pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
+
+	i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);
+	i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1);
+
+	/* branch participation */
+	mir = (setup->totalmem >> 4) & 0xfff;
+
+	/* Rank2 = 2
+	 * Rank1 = 1
+	 * Rank0 = 3
+	 */
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		if (setup->branch[branch].used) {
+			dev = setup->branch[branch].branchdev;
+			mir |= 1 << branch;
+			pci_mmio_write_config32(dev, I5000_DMIR0, 0x20000);
+			pci_mmio_write_config32(dev, I5000_DMIR1, 0x20000);
+			pci_mmio_write_config32(dev, I5000_DMIR2, 0x20000);
+			pci_mmio_write_config32(dev, I5000_DMIR3, 0x20000);
+			pci_mmio_write_config32(dev, I5000_DMIR4, 0x20000);
+
+		}
+	}
+
+	printk(BIOS_DEBUG, "MIR: 0x%08x\n", mir);
+	pci_mmio_write_config16(dev16, I5000_MIR0, mir);
+
+	pci_mmio_write_config16(dev16, I5000_MIR1, mir & ~0x03);
+	pci_mmio_write_config16(dev16, I5000_MIR2, mir & ~0x03);
+
+	if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00)
+		tolm = 0xe00;
+
+	tolm <<= 4;
+	printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
+	pci_mmio_write_config16(dev16, I5000_TOLM, tolm);
+	return 0;
+}
+
+static void i5000_init_setup(struct i5000_fbd_setup *setup)
+{
+	int branch, channel, dimm, i = 0;
+	struct i5000_fbdimm *d;
+	struct i5000_fbd_channel *c;
+	struct i5000_fbd_branch *b;
+
+	setup->bl = 3;
+	/* default to highest memory frequency. If a module doesn't
+	   support it, it will decrease this setting */
+	setup->ddr_speed = DDR_800MHZ;
+
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		b = setup->branch + branch;
+		b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);
+		b->setup = setup;
+		b->num = branch;
+
+		for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
+			c = b->channel + channel;
+			c->branch = b;
+			c->setup = setup;
+			c->num = channel;
+
+			for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
+				d = c->dimm + dimm;
+				setup->dimms[i++] = d;
+				d->channel = c;
+				d->branch = b;
+				d->setup = setup;
+				d->num = dimm;
+				d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11);
+			}
+		}
+	}
+}
+
+static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
+{
+	/* register write captured from vendor BIOS, but undocument by Intel */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
+
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
+
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
+	pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
+
+	if (setup->branch[0].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[0].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
+
+	if (setup->branch[1].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[1].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
+}
+
+static int i5000_membist(struct i5000_fbd_setup *setup)
+{
+	return i5000_for_each_dimm_present(setup, i5000_amb_membist_random1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_random2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_end);
+}
+
+static void i5000_dump_error_registers(void)
+{
+	device_t dev = PCI_ADDR(0, 16, 1, 0);
+
+	printk(BIOS_ERR, "Dump of FBD error registers:\n"
+	       "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n"
+	       "FERR_NF_FBD:  0x%08x NERR_NF_FBD:  0x%08x\n"
+	       "EMASK_FBD:    0x%08x\n"
+	       "ERR0_FBD:     0x%08x\n"
+	       "ERR1_FBD:     0x%08x\n"
+	       "ERR2_FBD:     0x%08x\n"
+	       "MC_ERR_FBD:   0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_FERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_EMASK_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR0_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR1_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR2_FBD),
+	       pci_mmio_read_config32(dev, I5000_MCERR_FBD));
+
+	printk(BIOS_ERR, "Non recoverable error registers:\n"
+	       "NRECMEMA:     0x%08x NRECMEMB:    0x%08x\n"
+	       "NRECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECMEMA),
+	       pci_mmio_read_config32(dev, I5000_NRECMEMB),
+	       pci_mmio_read_config32(dev, I5000_NRECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "NRECFBDA: 0x%08x\n"
+	       "NRECFBDB: 0x%08x\n"
+	       "NRECFBDC: 0x%08x\n"
+	       "NRECFBDD: 0x%08x\n"
+	       "NRECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECFBDA),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDB),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDC),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDD),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDE));
+
+	printk(BIOS_ERR, "recoverable error registers:\n"
+	       "RECMEMA:     0x%08x RECMEMB:    0x%08x\n"
+	       "RECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECMEMA),
+	       pci_mmio_read_config32(dev, I5000_RECMEMB),
+	       pci_mmio_read_config32(dev, I5000_RECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "RECFBDA: 0x%08x\n"
+	       "RECFBDB: 0x%08x\n"
+	       "RECFBDC: 0x%08x\n"
+	       "RECFBDD: 0x%08x\n"
+	       "RECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECFBDA),
+	       pci_mmio_read_config32(dev, I5000_RECFBDB),
+	       pci_mmio_read_config32(dev, I5000_RECFBDC),
+	       pci_mmio_read_config32(dev, I5000_RECFBDD),
+	       pci_mmio_read_config32(dev, I5000_RECFBDE));
+
+}
+
+static void i5000_die(const char *msg)
+{
+	printk(BIOS_INFO, msg);
+	i5000_dump_error_registers();
+//	outb(0x06, 0xcf9);
+	asm volatile("hlt");
+}
+
+void i5000_fbdimm_init(void)
+{
+	struct i5000_fbd_setup setup;
+	u32 mca, mc;
+
+	udelay(10000);
+	memset(&setup, 0, sizeof(setup));
+
+	i5000_init_setup(&setup);
+
+	pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,
+			   pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
+
+	i5000_clear_fbd_errors();
+
+	if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) {
+		printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__);
+		return;
+	}
+
+	/* posted CAS requires t_AL = t_RCD - 1 */
+	setup.t_al = setup.t_rcd - 1;
+
+	printk(BIOS_DEBUG, "global timing parameters:\n"
+	       "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n"
+	       "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n",
+	       setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc,
+	       setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r,
+	       setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd,
+	       setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);
+
+	/* TODO: motherboard callback to set FBD clock */
+
+	setup.single_channel = (!(setup.branch[0].channel[1].used ||
+				  setup.branch[1].channel[0].used ||
+				  setup.branch[1].channel[1].used));
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
+
+	/* enable or disable single channel mode */
+	mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
+	if (setup.single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
+
+	/*
+	 * i5000 supports burst length 8 only in single channel mode
+	 * so strip BL_BL8 if we're operating in multichannel mode
+	 */
+
+	if (!setup.single_channel)
+		setup.bl &= ~BL_BL8;
+
+	if (!setup.bl)
+		die("No supported burst length found\n");
+
+	mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
+	/* disable error checking for training */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
+
+	while (i5000_for_each_branch(&setup, i5000_branch_reset) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_preinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training0) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_check) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_postinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training1) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) {
+		printk(BIOS_INFO, "Memory initialization failed\n");
+	}
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+	if (i5000_membist(&setup))
+		i5000_die("Memory selftest failed\n");
+#endif
+
+	if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh))
+		i5000_die("failed to enable auto refresh\n");
+
+	while (i5000_for_each_channel(&setup.branch[0], i5000_drive_test_patterns0) ||
+	    i5000_for_each_channel(&setup.branch[1], i5000_drive_test_patterns0))
+		printk(BIOS_INFO, "Channel training failed\n");
+
+	/* enable error checking */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
+
+	i5000_dram_timing_init(&setup);
+
+	i5000_reserved_register_init(&setup);
+
+	if (setup.branch[0].used)
+		i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE);
+
+	if (setup.branch[1].used)
+		i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	if (ram_check_nodie(0x000000, 0x0a0000) ||
+	    ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) {
+		i5000_die("RAM verification failed");
+	}
+#endif
+
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
+}
diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h
new file mode 100644
index 0000000..60fbaec
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.h
@@ -0,0 +1,326 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_I5000_RAMINIT_H
+#define NORTHBRIDGE_I5000_RAMINIT_H
+
+#include <types.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define I5000_MAX_BRANCH 2
+#define I5000_MAX_CHANNEL 2
+#define I5000_MAX_DIMM_PER_CHANNEL 4
+#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)
+
+#define I5000_FBDRST 0x53
+
+#define I5000_SPD_BUSY (1 << 12)
+#define I5000_SPD_SBE (1 << 13)
+#define I5000_SPD_WOD (1 << 14)
+#define I5000_SPD_RDO (1 << 15)
+
+#define I5000_SPD0 0x74
+#define I5000_SPD1 0x76
+
+#define I5000_SPDCMD0 0x78
+#define I5000_SPDCMD1 0x7c
+
+#define I5000_FBDHPC 0x4f
+#define I5000_FBDST  0x4b
+
+#define I5000_FBDHPC_STATE_RESET 0x00
+#define I5000_FBDHPC_STATE_INIT 0x10
+#define I5000_FBDHPC_STATE_READY 0x20
+#define I5000_FBDHPC_STATE_ACTIVE 0x30
+
+#define I5000_FBDISTS0 0x58
+#define I5000_FBDISTS1 0x5a
+
+#define I5000_FBDLVL0 0x44
+#define I5000_FBDLVL1 0x45
+
+#define I5000_FBDICMD0 0x46
+#define I5000_FBDICMD1 0x47
+
+#define I5000_FBDICMD_IDLE 0x00
+#define I5000_FBDICMD_TS0  0x80
+#define I5000_FBDICMD_TS1  0x90
+#define I5000_FBDICMD_TS2  0xa0
+#define I5000_FBDICMD_TS3  0xb0
+#define I5000_FBDICMD_TS2_MERGE 0xd0
+#define I5000_FBDICMD_TS2_NOMERGE 0xe0
+#define I5000_FBDICMD_ALL_ONES 0xf0
+
+#define I5000_AMBPRESENT0 0x64
+#define I5000_AMBPRESENT1 0x66
+
+#define I5000_FBDSBTXCFG0 0xc0
+#define I5000_FBDSBTXCFG1 0xc1
+
+#define I5000_PROCENABLE 0xf0
+#define I5000_FBD0IBPORTCTL 0x180
+#define I5000_FBD0IBTXPAT2EN 0x1a8
+#define I5000_FBD0IBRXPAT2EN 0x1ac
+
+#define I5000_FBD0IBTXMSK 0x18c
+#define I5000_FBD0IBRXMSK 0x190
+
+#define I5000_FBDPLLCTRL 0x1c0
+
+/* dev 16, function 1 registers */
+#define I5000_MC 0x40
+#define I5000_DRTA 0x48
+#define I5000_DRTB 0x4c
+#define I5000_ERRPERR 0x50
+#define I5000_MCA 0x58
+#define I5000_TOLM 0x6c
+#define I5000_MIR0 0x80
+#define I5000_MIR1 0x84
+#define I5000_MIR2 0x88
+#define I5000_AMIR0 0x8c
+#define I5000_AMIR1 0x90
+#define I5000_AMIR2 0x94
+
+#define I5000_FERR_FAT_FBD 0x98
+#define I5000_NERR_FAT_FBD 0x9c
+#define I5000_FERR_NF_FBD 0xa0
+#define I5000_NERR_NF_FBD 0xa4
+#define I5000_EMASK_FBD 0xa8
+#define I5000_ERR0_FBD 0xac
+#define I5000_ERR1_FBD 0xb0
+#define I5000_ERR2_FBD 0xb4
+#define I5000_MCERR_FBD 0xb8
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECMEMB 0xc0
+#define I5000_NRECFGLOG 0xc4
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECFBDA 0xc8
+#define I5000_NRECFBDB 0xcc
+#define I5000_NRECFBDC 0xd0
+#define I5000_NRECFBDD 0xd4
+#define I5000_NRECFBDE 0xd8
+
+#define I5000_REDMEMB 0x7c
+#define I5000_RECMEMA 0xe2
+#define I5000_RECMEMB 0xe4
+#define I5000_RECFGLOG 0xe8
+#define I5000_RECFBDA 0xec
+#define I5000_RECFBDB 0xf0
+#define I5000_RECFBDC 0xf4
+#define I5000_RECFBDD 0xf8
+#define I5000_RECFBDE 0xfc
+
+/* dev 16, function 2 registers */
+#define I5000_FERR_GLOBAL 0x40
+#define I5000_NERR_GLOBAL 0x44
+
+/* dev 21, function 0 registers */
+#define I5000_MTR0 0x80
+#define I5000_MTR1 0x84
+#define I5000_MTR2 0x88
+#define I5000_MTR3 0x8c
+#define I5000_DMIR0 0x90
+#define I5000_DMIR1 0x94
+#define I5000_DMIR2 0x98
+#define I5000_DMIR3 0x9c
+#define I5000_DMIR4 0xa0
+
+#define DEFAULT_AMBASE 0xfe000000
+
+/* AMB function 1 registers */
+#define AMB_FBDSBCFGNXT 0x58
+#define AMB_FBDLOCKTO 0x68
+#define AMB_CMD2DATANXT 0xe8
+
+/* AMB function 3 registers */
+#define AMB_DAREFTC 0x70
+#define AMB_DSREFTC 0x74
+#define AMB_DRT 0x78
+#define AMB_DRC 0x7c
+
+#define AMB_MBCSR 0x40
+#define AMB_MBADDR 0x44
+#define AMB_MBLFSRSED 0xa4
+
+/* AMB function 4 registers */
+#define AMB_DCALCSR  0x40
+#define AMB_DCALADDR 0x44
+#define AMB_DCALCSR_START (1 << 31)
+
+#define AMB_DCALCSR_OPCODE_NOP                0x00
+#define AMB_DCALCSR_OPCODE_REFRESH            0x01
+#define AMB_DCALCSR_OPCODE_PRECHARGE          0x02
+#define AMB_DCALCSR_OPCODE_MRS_EMRS           0x03
+#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL      0x05
+#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL    0x0c
+#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d
+
+#define AMB_DDR2ODTC 0xfc
+
+#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04
+#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07
+#define FBDIMM_SPD_FTB 0x08
+#define FBDIMM_SPD_MTB_DIVIDEND 0x09
+#define FBDIMM_SPD_MTB_DIVISOR 0x0a
+#define FBDIMM_SPD_MIN_TCK 0x0b
+#define FBDIMM_SPD_CAS_LATENCIES 0x0d
+#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e
+#define FBDIMM_SPD_T_WR 0x10
+#define FBDIMM_SPD_T_RCD 0x13
+#define FBDIMM_SPD_T_RRD 0x14
+#define FBDIMM_SPD_T_RP 0x15
+#define FBDIMM_SPD_T_RAS_RC_MSB 0x16
+#define FBDIMM_SPD_T_RAS 0x17
+#define FBDIMM_SPD_T_RC 0x18
+#define FBDIMM_SPD_T_RFC 0x19
+#define FBDIMM_SPD_T_WTR 0x1b
+#define FBDIMM_SPD_T_RTP 0x1c
+#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d
+#define FBDIMM_SPD_ODT 0x4f
+#define FBDIMM_SPD_T_REFI 0x20
+#define FBDIMM_SPD_T_BB 0x83
+#define FBDIMM_SPD_CMD2DATA_800 0x54
+#define FBDIMM_SPD_CMD2DATA_667 0x55
+#define FBDIMM_SPD_CMD2DATA_533 0x56
+
+void i5000_fbdimm_init(void);
+
+#define I5000_BURST4 0x01
+#define I5000_BURST8 0x02
+#define I5000_BURST_CHOP 0x80
+
+#define I5000_ODT_50 4
+#define I5000_ODT_75 2
+#define I5000_ODT_150 1
+
+enum ddr_speeds {
+	DDR_400MHZ,
+	DDR_533MHZ,
+	DDR_667MHZ,
+	DDR_800MHZ,
+};
+
+struct i5000_fbdimm {
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_channel *channel;
+	struct i5000_fbd_setup *setup;
+	enum ddr_speeds speed;
+	int num;
+	int present:1;
+	u32 ambase;
+
+	/* SPD data */
+	u8 amb_personality_bytes[14];
+	u8 banks;
+	u8 rows;
+	u8 columns;
+	u8 ranks;
+	u8 odt;
+	u8 sdram_width;
+	u8 mtb_divisor;
+	u8 mtb_dividend;
+	u8 t_ck_min;
+	u8 min_cas_latency;
+	u8 t_rrd;
+	u16 t_rfc;
+	u8 t_wtr;
+	u8 t_refi;
+	u8 cmd2datanxt;
+
+	u16 vendor;
+	u16 device;
+
+	/* memory size in MB */
+	int size;
+};
+
+struct i5000_fbd_channel {
+	struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_setup *setup;
+	int num;
+	int used;
+	int highest_amb;
+	int columns;
+	int rows;
+	int ranks;
+	int banks;
+	int width;
+	/* memory size in MB on this channel */
+	int totalmem;
+};
+
+struct i5000_fbd_branch {
+	struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];
+	struct i5000_fbd_setup *setup;
+	device_t branchdev;
+	int num;
+	int used;
+	/* memory size in MB on this branch */
+	int totalmem;
+};
+
+enum odt {
+	ODT_150OHM=1,
+	ODT_50OHM=4,
+	ODT_75OHM=2,
+};
+
+enum bl {
+	BL_BL4=1,
+	BL_BL8=2,
+};
+
+struct i5000_fbd_setup {
+	struct i5000_fbd_branch branch[I5000_MAX_BRANCH];
+	struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];
+	enum bl bl;
+	enum ddr_speeds ddr_speed;
+
+	int single_channel:1;
+	u32 tolm;
+
+	/* global SDRAM timing parameters */
+	u8 t_al;
+	u8 t_cl;
+	u8 t_ras;
+	u8 t_wrc;
+	u8 t_rc;
+	u8 t_rfc;
+	u8 t_rrd;
+	u8 t_ref;
+	u8 t_w2rdr;
+	u8 t_r2w;
+	u8 t_w2r;
+	u8 t_r2r;
+	u8 t_w2w;
+	u8 t_wtr;
+	u8 t_rcd;
+	u8 t_rp;
+	u8 t_wr;
+	u8 t_rtp;
+	/* memory size in MB */
+	int totalmem;
+};
+
+#define AMB_ADDR(base, fn, reg)	(base | ((fn & 7) << 8) | ((reg & 0xff)))
+#endif
diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c
new file mode 100644
index 0000000..26b3c49
--- /dev/null
+++ b/src/northbridge/intel/i5000/udelay.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+/**
+ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 0, divisor;
+	u32 d;			/* ticks per us */
+	u32 dn = 0x1000000 / 2;	/* how many us before we need to use hi */
+
+	msr = rdmsr(0xcd);
+	switch (msr.lo & 0x07) {
+	case 5:
+		fsb = 400;
+		break;
+	case 1:
+		fsb = 533;
+		break;
+	case 3:
+		fsb = 667;
+		break;
+	case 2:
+		fsb = 800;
+		break;
+	case 0:
+		fsb = 1067;
+		break;
+	case 4:
+		fsb = 1333;
+		break;
+	case 6:
+		fsb = 1600;
+		break;
+	}
+
+	msr = rdmsr(0x198);
+	divisor = (msr.hi >> 8) & 0x1f;
+
+	d = fsb * divisor;
+
+	tscd.hi = us / dn;
+	tscd.lo = (us - tscd.hi * dn) * d;
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	tsc = rdtsc();
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+
+}


From gerrit at coreboot.org  Sat Dec 17 19:42:33 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sat, 17 Dec 2011 19:42:33 +0100
Subject: [coreboot] New patch to review for coreboot: 3220062 Add Intel
	Socket LGA771
References: <Iee7d3ff2884d8c43ff1af498160589e551bc9cc8+0@gerrit.coreboot.org>
Message-ID: <Iee7d3ff2884d8c43ff1af498160589e551bc9cc8+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/492

-gerrit

commit 3220062a8c6312889c98688c6cee0ced13e31dbf
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:21:35 2011 +0100

    Add Intel Socket LGA771
    
    Change-Id: Iee7d3ff2884d8c43ff1af498160589e551bc9cc8
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/cpu/intel/Kconfig                       |    1 +
 src/cpu/intel/Makefile.inc                  |    1 +
 src/cpu/intel/socket_LGA771/Kconfig         |    7 +++++++
 src/cpu/intel/socket_LGA771/Makefile.inc    |   11 +++++++++++
 src/cpu/intel/socket_LGA771/chip.h          |    4 ++++
 src/cpu/intel/socket_LGA771/socket_LGA771.c |    7 +++++++
 6 files changed, 31 insertions(+), 0 deletions(-)

diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 8cf30c9..31c701c 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -28,3 +28,4 @@ source src/cpu/intel/socket_mPGA603/Kconfig
 source src/cpu/intel/socket_mPGA604/Kconfig
 source src/cpu/intel/socket_PGA370/Kconfig
 source src/cpu/intel/socket_441/Kconfig
+source src/cpu/intel/socket_LGA771/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 93ab7de..274c101 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -16,6 +16,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771
 
 #socket_mPGA604_533Mhz
 #socket_mPGA604_800Mhz
diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig
new file mode 100644
index 0000000..0821c3e
--- /dev/null
+++ b/src/cpu/intel/socket_LGA771/Kconfig
@@ -0,0 +1,7 @@
+config CPU_INTEL_SOCKET_LGA771
+	bool
+        select CPU_INTEL_MODEL_6FX
+        select CPU_INTEL_CORE2
+	select SSE2
+	select MMX
+	select AP_IN_SIPI_WAIT
diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc
new file mode 100644
index 0000000..319430f
--- /dev/null
+++ b/src/cpu/intel/socket_LGA771/Makefile.inc
@@ -0,0 +1,11 @@
+ramstage-y += socket_LGA771.c
+subdirs-y += ../model_6ex
+subdirs-y += ../model_6fx
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+
diff --git a/src/cpu/intel/socket_LGA771/chip.h b/src/cpu/intel/socket_LGA771/chip.h
new file mode 100644
index 0000000..d3f312e
--- /dev/null
+++ b/src/cpu/intel/socket_LGA771/chip.h
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_LGA771_ops;
+
+struct cpu_intel_socket_LGA771_config {
+};
diff --git a/src/cpu/intel/socket_LGA771/socket_LGA771.c b/src/cpu/intel/socket_LGA771/socket_LGA771.c
new file mode 100644
index 0000000..21a7dc9
--- /dev/null
+++ b/src/cpu/intel/socket_LGA771/socket_LGA771.c
@@ -0,0 +1,7 @@
+#include <device/device.h>
+#include "chip.h"
+
+
+struct chip_operations cpu_intel_socket_LGA771_ops = {
+	CHIP_NAME("Socket LGA771 CPU")
+};


From gerrit at coreboot.org  Sat Dec 17 19:42:34 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sat, 17 Dec 2011 19:42:34 +0100
Subject: [coreboot] New patch to review for coreboot: b21b8b8 Add Supermicro
	X7DB8 motherboard
References: <I5eaac32a8bafa69a05929cf08d869127b9464661+0@gerrit.coreboot.org>
Message-ID: <I5eaac32a8bafa69a05929cf08d869127b9464661+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/493

-gerrit

commit b21b8b87eb66058448e8803453bc2ccd51f1f6c2
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:22:44 2011 +0100

    Add Supermicro X7DB8 motherboard
    
    Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/supermicro/Kconfig             |    4 +
 src/mainboard/supermicro/x7db8/Kconfig       |   46 +++++++++++
 src/mainboard/supermicro/x7db8/chip.h        |   21 +++++
 src/mainboard/supermicro/x7db8/devicetree.cb |  111 ++++++++++++++++++++++++++
 src/mainboard/supermicro/x7db8/mainboard.c   |   41 ++++++++++
 src/mainboard/supermicro/x7db8/romstage.c    |   98 +++++++++++++++++++++++
 6 files changed, 321 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig
index 80ffd6a..794aead 100755
--- a/src/mainboard/supermicro/Kconfig
+++ b/src/mainboard/supermicro/Kconfig
@@ -25,6 +25,9 @@ config BOARD_SUPERMICRO_X6DHR_IG2
 	bool "X6DHR-iG2"
 config BOARD_SUPERMICRO_X6DHR_IG
 	bool "X6DHR-iG"
+config BOARD_SUPERMICRO_X7DB8
+	bool "X7DB8"
+
 
 endchoice
 
@@ -39,6 +42,7 @@ source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
 source "src/mainboard/supermicro/x6dhe_g/Kconfig"
 source "src/mainboard/supermicro/x6dhr_ig2/Kconfig"
 source "src/mainboard/supermicro/x6dhr_ig/Kconfig"
+source "src/mainboard/supermicro/x7db8/Kconfig"
 
 config MAINBOARD_VENDOR
 	string
diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig
new file mode 100644
index 0000000..56c616a
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/Kconfig
@@ -0,0 +1,46 @@
+if BOARD_SUPERMICRO_X7DB8
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_LGA771
+	select SOUTHBRIDGE_INTEL_I3100
+	select NORTHBRIDGE_INTEL_I5000
+	select SUPERIO_WINBOND_W83627HF
+	select MMCONF_SUPPORT
+	select HAVE_OPTION_TABLE
+	select BOARD_ROMSIZE_KB_512
+
+config MAINBOARD_DIR
+	string
+	default supermicro/x7db8
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Supermicro X7DB8"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xe0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+
+endif
diff --git a/src/mainboard/supermicro/x7db8/chip.h b/src/mainboard/supermicro/x7db8/chip.h
new file mode 100644
index 0000000..70f9bb4
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb
new file mode 100644
index 0000000..36e4aed
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/devicetree.cb
@@ -0,0 +1,111 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/i5000
+
+	device lapic_cluster 0 on
+		chip cpu/intel/socket_LGA771
+			device lapic 0 on end
+		end
+	end
+
+	device pci_domain 0 on
+		device pci 00.0 on # Host bridge
+			subsystemid 0x15d9 0x2017
+		end
+
+		device pci 02.0 on # PCIe bridge
+			device pci 00.0 on
+				device pci 00.0 on
+					device pci 00.0 on end
+					device pci 02.0 on end
+				end
+				device pci 02.0 on
+					device pci 00.0 on end
+					device pci 00.1 on end
+				end
+			end
+			device pci 00.3 on
+
+			end
+		end
+
+		device pci 03.0 on end
+		device pci 04.0 on end
+		device pci 05.0 on end
+		device pci 06.0 on end
+		device pci 07.0 on end
+		device pci 10.0 on end # FBD
+		device pci 10.1 on end # FBD
+		device pci 10.2 on end # FBD
+		device pci 11.0 on end # FBD reserved
+		device pci 13.0 on end # FBD reserved
+		device pci 15.0 on end # FBD
+		device pci 16.0 on end # FBD
+
+		chip southbridge/intel/i3100
+		device pci 1c.0 on end # PCIe bridge
+		device pci 1d.0 on end # USB UHCI
+		device pci 1d.1 on end # USB UHCI
+		device pci 1d.2 on end # USB UHCI
+		device pci 1d.3 on end # USB UHCI
+		device pci 1d.7 on end # USB2 EHCI
+		device pci 1e.0 on
+		       device pci 01.0 on
+		       end
+		end
+		device pci 1e.2 on end
+		device pci 1e.3 on end
+
+		device pci 1f.0 on # PCI-LPC bridge
+			subsystemid 0x15d9 0x2009
+			chip superio/winbond/w83627hf
+				device pnp 2e.0 off end # FDC
+				device pnp 2e.1 on # Parallel Port
+					io 0x60 = 0x378
+					irq 0x70 = 7
+				end
+				device pnp 2e.2 on # Serial Port 1
+					io 0x60 = 0x3f8
+					irq 0x70 = 4
+				end
+
+				device pnp 2e.3 off end
+				device pnp 2e.5 on # KBC
+				end
+
+				device pnp 2e.6 off end # CIR
+				device pnp 2e.7 off end # Game port / MIDI
+				device pnp 2e.8 off end # GPIO2
+				device pnp 2e.9 off end # GPIO3
+				device pnp 2e.a off end # ACPI
+				device pnp 2e.b off end # HWMON
+			end
+		end
+		device pci 1f.1 on end # IDE
+		device pci 1f.2 on end # IDE
+		device pci 1f.3 on # SMBUS
+			subsystemid 0x15d9 0x200f
+			end
+		end
+	end
+end
diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c
new file mode 100644
index 0000000..27a26f9
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/mainboard.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#include <arch/coreboot_tables.h>
+#include "chip.h"
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+static void mainboard_enable(device_t dev)
+{
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
+	.enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c
new file mode 100644
index 0000000..b4242a3
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/romstage.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <superio/winbond/w83627hf/early_serial.c>
+#include <southbridge/intel/i63xx/i63xx.h>
+#include <northbridge/intel/i5000/raminit.h>
+
+
+static void setup_gpio(void)
+{
+	pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1);
+	pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4));
+
+
+	outl(0xff0c79cf, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+	outl(0xe700ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+	outl(0x65bf0000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+	outl(0x0000718a, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+	outl(0x00000106, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
+	outl(0x00000301, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
+	outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */
+
+}
+
+static void i5000_lpc_config(void)
+{
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+}
+
+void main(unsigned long bist)
+{
+	if (bist == 0)
+		enable_lapic();
+
+	i5000_lpc_config();
+
+	w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);
+
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	setup_gpio();
+
+	enable_smbus();
+
+	/* setup PCIe MMCONF base address */
+	pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
+			   CONFIG_MMCONF_BASE_ADDRESS >> 16);
+
+	outb(0x07, 0x11b8);
+
+	/* These are smbus write captured with serialice. They
+	   seem to setup the clock generator */
+
+	if (smbus_write_byte(0x6f, 0x88, 0x1f) ||
+	    smbus_write_byte(0x6f, 0x81, 0xff) ||
+	    smbus_write_byte(0x6f, 0x82, 0xff) ||
+	    smbus_write_byte(0x6f, 0x80, 0x23))
+		printk(BIOS_ERR, "Clock generator setup failed\n");
+
+	outb(0x03, 0x11b8);
+	outb(0x01, 0x11b8);
+
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1);
+	i5000_fbdimm_init();
+	smbus_write_byte(0x69, 0x01, 0x01);
+}


From gerrit at coreboot.org  Sat Dec 17 22:00:56 2011
From: gerrit at coreboot.org (Christian Ruppert (idl0r@qasl.de))
Date: Sat, 17 Dec 2011 22:00:56 +0100
Subject: [coreboot] New patch to review for coreboot: 66ebaa9 Respect linker
	order
References: <I5a5b05e1cab8a2d88ce56c92d9b2f991ca1ee6c0+0@gerrit.coreboot.org>
Message-ID: <I5a5b05e1cab8a2d88ce56c92d9b2f991ca1ee6c0+1@gerrit.coreboot.org>

Christian Ruppert (idl0r at qasl.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/494

-gerrit

commit 66ebaa9f670438b7dd4efa80b65830b362729a9b
Author: Christian Ruppert <idl0r at qasl.de>
Date:   Sat Dec 17 21:56:05 2011 +0100

    Respect linker order
    
    Linking fails when using -Wl,--as-needed and/or esp. when forcing --as-needed
    through a compiler specs file.
    A proper compile/link command would look like: $(CC) $(CFLAGS) $(LDFLAGS) -o foo
    $(OBJS) $(LIBS). So the *FLAGS must be passed *before* the objects while the
    libraries/dependencies must be passed *after* the objects.
    For more details see: http://www.gentoo.org/proj/en/qa/asneeded.xml
    
    Change-Id: I5a5b05e1cab8a2d88ce56c92d9b2f991ca1ee6c0
    Signed-off-by: Christian Ruppert <idl0r at qasl.de>
---
 payloads/coreinfo/util/kconfig/Makefile   |    6 +++---
 payloads/libpayload/util/kconfig/Makefile |    6 +++---
 util/kconfig/Makefile                     |    4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/payloads/coreinfo/util/kconfig/Makefile b/payloads/coreinfo/util/kconfig/Makefile
index 9462aea..679ab92 100644
--- a/payloads/coreinfo/util/kconfig/Makefile
+++ b/payloads/coreinfo/util/kconfig/Makefile
@@ -298,7 +298,7 @@ $(objk)/qconf: $(patsubst %,$(objk)/%,$(qconf-cxxobjs)) \
 $(objk)/gconf: $(patsubst %,$(objk)/%,$(gconf-objs))
 	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^
 $(objk)/mconf: $(patsubst %,$(objk)/%,$(mconf-objs))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ $(HOST_LOADLIBES)
 $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs))
 	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^
 
@@ -330,8 +330,8 @@ $(objk)/zconf.tab.c: $(srck)/zconf.tab.c_shipped
 
 $(objk)/lxdialog/lxdialog: $(objk)/dochecklxdialog \
 			   $(patsubst %,$(objk)/lxdialog/%,$(lxdialog))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) \
-		$(patsubst %,$(objk)/lxdialog/%,$(lxdialog)) -o $@
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) \
+		$(patsubst %,$(objk)/lxdialog/%,$(lxdialog)) $(HOST_LOADLIBES) -o $@
 $(objk)/lxdialog/%.o: $(srck)/lxdialog/%.c
 	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ -c -o $@
 
diff --git a/payloads/libpayload/util/kconfig/Makefile b/payloads/libpayload/util/kconfig/Makefile
index f613a62..624233d 100644
--- a/payloads/libpayload/util/kconfig/Makefile
+++ b/payloads/libpayload/util/kconfig/Makefile
@@ -304,7 +304,7 @@ $(objk)/qconf: $(patsubst %,$(objk)/%,$(qconf-cxxobjs)) \
 $(objk)/gconf: $(patsubst %,$(objk)/%,$(gconf-objs))
 	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^
 $(objk)/mconf: $(patsubst %,$(objk)/%,$(mconf-objs))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ $(HOST_LOADLIBES)
 $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs))
 	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^
 
@@ -338,8 +338,8 @@ $(objk)/zconf.tab.c: $(srck)/zconf.tab.c_shipped
 
 $(objk)/lxdialog/lxdialog: $(objk)/dochecklxdialog \
 			   $(patsubst %,$(objk)/lxdialog/%,$(lxdialog))
-	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) \
-		$(patsubst %,$(objk)/lxdialog/%,$(lxdialog)) -o $@
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) \
+		$(patsubst %,$(objk)/lxdialog/%,$(lxdialog)) $(HOST_LOADLIBES) -o $@
 $(objk)/lxdialog/%.o: $(srck)/lxdialog/%.c
 	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ -c -o $@
 
diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile
index 477ff03..0e108a3 100644
--- a/util/kconfig/Makefile
+++ b/util/kconfig/Makefile
@@ -338,8 +338,8 @@ $(objk)/zconf.tab.c: $(srck)/zconf.tab.c_shipped
 
 $(objk)/lxdialog/lxdialog: $(objk)/dochecklxdialog \
 			   $(patsubst %,$(objk)/lxdialog/%,$(lxdialog))
-	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) \
-		$(patsubst %,$(objk)/lxdialog/%,$(lxdialog)) -o $@
+	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) \
+		$(patsubst %,$(objk)/lxdialog/%,$(lxdialog)) $(HOST_LOADLIBES) -o $@
 $(objk)/lxdialog/%.o: $(srck)/lxdialog/%.c
 	$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ -c -o $@
 


From caracol at neuf.fr  Sun Dec 18 10:04:16 2011
From: caracol at neuf.fr (nap)
Date: Sun, 18 Dec 2011 10:04:16 +0100
Subject: [coreboot] New patch to review for coreboot: 3220062 Add Intel
 Socket LGA771 - Model number
In-Reply-To: <Iee7d3ff2884d8c43ff1af498160589e551bc9cc8+1@gerrit.coreboot.org>
References: <Iee7d3ff2884d8c43ff1af498160589e551bc9cc8+0@gerrit.coreboot.org>
	<Iee7d3ff2884d8c43ff1af498160589e551bc9cc8+1@gerrit.coreboot.org>
Message-ID: <4EEDAC90.5060204@neuf.fr>

Repost to the list, apologies.

Thanks! that will be useful as a template for adding the LGA775 socket.

My CPUs are of the Pentium E5x00 kind, that is Pentium Dual Core based
on the Enhanced Core microarchitecture.

The problem is the family is 06 and model 17 (hexadecimals), not
directly compatible with the model_xx convention used so far. I don't
know how deep is going this convention into coreboot.

Looking at the latest Intel documentation (e.g.
64-ia-32-architectures-software-developer-vol-3b-part-2-manual, october
2011), the CPU microarchitecture main identification is a
DisplayFamilyDisplayModel string of the form xx_xxH, x being an
hexadecimal digit. I suggest to keep by that convention for the Intel
CPUs, something like model_xx_xxH and not model_xx. To make the switch
easy, just make model_xx a symlink to model_xx_xxH. Looking for info on
a given CPU in Intel doc would be easier.

Comments welcome.

nap

Le 17/12/2011 19:42, Sven Schnelle (svens at stackframe.org) a ?crit :
> Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/492
> 
> -gerrit
> 
> commit 3220062a8c6312889c98688c6cee0ced13e31dbf
> Author: Sven Schnelle <svens at stackframe.org>
> Date:   Fri Dec 2 16:21:35 2011 +0100
> 
>     Add Intel Socket LGA771
>     
>     Change-Id: Iee7d3ff2884d8c43ff1af498160589e551bc9cc8
>     Signed-off-by: Sven Schnelle <svens at stackframe.org>
> ---
>  src/cpu/intel/Kconfig                       |    1 +
>  src/cpu/intel/Makefile.inc                  |    1 +
>  src/cpu/intel/socket_LGA771/Kconfig         |    7 +++++++
>  src/cpu/intel/socket_LGA771/Makefile.inc    |   11 +++++++++++
>  src/cpu/intel/socket_LGA771/chip.h          |    4 ++++
>  src/cpu/intel/socket_LGA771/socket_LGA771.c |    7 +++++++
>  6 files changed, 31 insertions(+), 0 deletions(-)
> 
> diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
> index 8cf30c9..31c701c 100644
> --- a/src/cpu/intel/Kconfig
> +++ b/src/cpu/intel/Kconfig
> @@ -28,3 +28,4 @@ source src/cpu/intel/socket_mPGA603/Kconfig
>  source src/cpu/intel/socket_mPGA604/Kconfig
>  source src/cpu/intel/socket_PGA370/Kconfig
>  source src/cpu/intel/socket_441/Kconfig
> +source src/cpu/intel/socket_LGA771/Kconfig
> diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
> index 93ab7de..274c101 100644
> --- a/src/cpu/intel/Makefile.inc
> +++ b/src/cpu/intel/Makefile.inc
> @@ -16,6 +16,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
>  subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
>  subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
>  subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
> +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771
>  
>  #socket_mPGA604_533Mhz
>  #socket_mPGA604_800Mhz
> diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig
> new file mode 100644
> index 0000000..0821c3e
> --- /dev/null
> +++ b/src/cpu/intel/socket_LGA771/Kconfig
> @@ -0,0 +1,7 @@
> +config CPU_INTEL_SOCKET_LGA771
> +	bool
> +        select CPU_INTEL_MODEL_6FX
> +        select CPU_INTEL_CORE2
> +	select SSE2
> +	select MMX
> +	select AP_IN_SIPI_WAIT
> diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc


> new file mode 10064
> index 0000000..319430f
> --- /dev/null
> +++ b/src/cpu/intel/socket_LGA771/Makefile.inc
> @@ -0,0 +1,11 @@
> +ramstage-y += socket_LGA771.c
> +subdirs-y += ../model_6ex
> +subdirs-y += ../model_6fx
> +subdirs-y += ../../x86/tsc
> +subdirs-y += ../../x86/mtrr
> +subdirs-y += ../../x86/lapic
> +subdirs-y += ../../x86/cache
> +subdirs-y += ../../x86/smm
> +subdirs-y += ../microcode
> +subdirs-y += ../hyperthreading
> +
> diff --git a/src/cpu/intel/socket_LGA771/chip.h b/src/cpu/intel/socket_LGA771/chip.h
> new file mode 100644
> index 0000000..d3f312e
> --- /dev/null
> +++ b/src/cpu/intel/socket_LGA771/chip.h
> @@ -0,0 +1,4 @@
> +extern struct chip_operations cpu_intel_socket_LGA771_ops;
> +
> +struct cpu_intel_socket_LGA771_config {
> +};
> diff --git a/src/cpu/intel/socket_LGA771/socket_LGA771.c b/src/cpu/intel/socket_LGA771/socket_LGA771.c
> new file mode 100644
> index 0000000..21a7dc9
> --- /dev/null
> +++ b/src/cpu/intel/socket_LGA771/socket_LGA771.c
> @@ -0,0 +1,7 @@
> +#include <device/device.h>
> +#include "chip.h"
> +
> +
> +struct chip_operations cpu_intel_socket_LGA771_ops = {
> +	CHIP_NAME("Socket LGA771 CPU")
> +};
> 


From svn at coreboot.org  Sun Dec 18 18:15:53 2011
From: svn at coreboot.org (coreboot)
Date: Sun, 18 Dec 2011 17:15:53 -0000
Subject: [coreboot]  #183: SeaBIOS: test-gcc.sh executed multiple times,
 also during make clean
Message-ID: <069.1e6e87a2bb62f10b69a7ad36b1077247@coreboot.org>

#183: SeaBIOS: test-gcc.sh executed multiple times, also during make clean
--------------------------------------------+------------------------------
    Reporter:  Christian Ruppert <idl0r@?>  |         Owner:  stepan@?
        Type:  enhancement                  |        Status:  new
    Priority:  minor                        |     Milestone:
   Component:  coreboot                     |      Keywords:
Dependencies:                               |  Patch Status:  there is no
                                            |  patch
--------------------------------------------+------------------------------
 The test-gcc.sh script will be executed multiple times during "make" and
 at least once during "make clean". In "clean" there seems to be no $CC/$LD
 defined thus it leads to an error.
 So executing test-gcc.sh only once and only before compiling would fix
 both.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/183>
coreboot <http://www.coreboot.org/>


From rminnich at gmail.com  Sun Dec 18 18:02:57 2011
From: rminnich at gmail.com (ron minnich)
Date: Sun, 18 Dec 2011 09:02:57 -0800
Subject: [coreboot] New patch to review for coreboot: 3220062 Add Intel
 Socket LGA771 - Model number
In-Reply-To: <4EEDAC90.5060204@neuf.fr>
References: <Iee7d3ff2884d8c43ff1af498160589e551bc9cc8+0@gerrit.coreboot.org>
	<Iee7d3ff2884d8c43ff1af498160589e551bc9cc8+1@gerrit.coreboot.org>
	<4EEDAC90.5060204@neuf.fr>
Message-ID: <CAP6exYK0rdkAaV9CsskaGMojOHNRB6E9Xwj+qwepU-VLBqf-ZQ@mail.gmail.com>

On Sun, Dec 18, 2011 at 1:04 AM, nap <caracol at neuf.fr> wrote:

> The problem is the family is 06 and model 17 (hexadecimals), not
> directly compatible with the model_xx convention used so far. I don't
> know how deep is going this convention into coreboot.
>

it's a convention. If we can't take an arbitrary name then we've done
something wrong.

> just make model_xx a symlink to model_xx_xxH.

I don't see the need for a symlink. Just go with your proposed name.

thanks

ron


From scouter389 at gmail.com  Sun Dec 18 22:23:18 2011
From: scouter389 at gmail.com (James Wall)
Date: Sun, 18 Dec 2011 15:23:18 -0600
Subject: [coreboot] Dell Dimension 4700 Supported?
Message-ID: <CAPY5=CbSpXc84djd_LPUeag0gM96UQfC315gn5nvBF7KpaN3wg@mail.gmail.com>

I have a Dell Dimension 4700 that I would like to put coreboot on to help
improve performance and unmask CPU flags that the bios is masking. attached
is the output of dmidecode, lspci -tvnn, superiotool -dV, and flashrom -V.
I appreciate any suggestions to help get this project going.
James Wall
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flashrom v0.9.4-runknown on Linux 3.1.0-gentoo-r1 (x86_64), built with libpci 3.1.7, GCC 4.5.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 1 usecs, 1744M loops per second, 10 myus = 9 us, 100 myus = 94 us, 1000 myus = 937 us, 10000 myus = 9467 us, 4 myus = 4 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "Dell Inc.                "
DMI string system-product-name: "Dimension 4700               "
DMI string system-version: "Not Specified"
DMI string baseboard-manufacturer: "Dell Inc.          "
DMI string baseboard-product-name: "0M3918"
DMI string baseboard-version: "   "
DMI string chassis-type: "Mini Tower"
Found chipset "Intel ICH6/ICH6R" with PCI ID 8086:2640. Enabling flash write... 
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode disabled
0xffe00000/0xffa00000 FWH decode disabled
0xffd80000/0xff980000 FWH decode disabled
0xffd00000/0xff900000 FWH decode disabled
0xffc80000/0xff880000 FWH decode disabled
0xffc00000/0xff800000 FWH decode disabled
0xff700000/0xff300000 FWH decode disabled
0xff600000/0xff200000 FWH decode disabled
0xff500000/0xff100000 FWH decode disabled
0xff400000/0xff000000 FWH decode disabled
Maximum FWH chip size: 0x100000 bytes
BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2
WARNING: Setting 0xdc from 0x2 to 0x3 on ICH6/ICH6R failed. New value is 0x2.
FAILED!
This programmer supports the following protocols: FWH.
Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x1a, id2 0xc0, id1 is normal flash content, id2 is normal flash content
Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x1a, id2 0xc0, id1 is normal flash content, id2 is normal flash content
Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x1a, id2 0xc0, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x32, id2 0xed, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x1a, id2 0xc0, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x1a, id2 0xc0, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
Restoring PCI config space for 00:1f:0 reg 0xdc
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A non-text attachment was scrubbed...
Name: dmidecode.dump
Type: application/octet-stream
Size: 17854 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20111218/909ceadf/attachment-0001.obj>
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-[0000:00]-+-00.0  Intel Corporation 82915G/P/GV/GL/PL/910GL Memory Controller Hub [8086:2580]
           +-01.0-[01]--
           +-02.0  Intel Corporation 82915G/GV/910GL Integrated Graphics Controller [8086:2582]
           +-02.1  Intel Corporation 82915G Integrated Graphics Controller [8086:2782]
           +-1c.0-[02]--
           +-1d.0  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 [8086:2658]
           +-1d.1  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 [8086:2659]
           +-1d.2  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 [8086:265a]
           +-1d.3  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 [8086:265b]
           +-1d.7  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller [8086:265c]
           +-1e.0-[03]--+-01.0  Broadcom Corporation BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller [14e4:4318]
           |            \-08.0  Intel Corporation 82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller [8086:1064]
           +-1e.2  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller [8086:266e]
           +-1f.0  Intel Corporation 82801FB/FR (ICH6/ICH6R) LPC Interface Bridge [8086:2640]
           +-1f.1  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller [8086:266f]
           +-1f.2  Intel Corporation 82801FB/FW (ICH6/ICH6W) SATA Controller [8086:2651]
           \-1f.3  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller [8086:266a]
-------------- next part --------------
superiotool r
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0x0000, rev=0x00
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0x7601, rev=0x9
Probing for ITE Super I/O (init=it8502e) at 0x2e...
  Failed. Returned data: id=0x7601, rev=0x9
Probing for ITE Super I/O (init=it8761e) at 0x2e...
  Failed. Returned data: id=0x7601, rev=0x9
Probing for ITE Super I/O (init=it8228e) at 0x2e...
  Failed. Returned data: id=0x7601, rev=0x9
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0x7601, rev=0x9
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x164e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for Nuvoton Super I/O at 0x164e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x2e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x4e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
Found SMSC LPC47M584 (id=0x76, rev=0x01) at 0x2e
No dump available for this Super I/O
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Server Engines Super I/O at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xff

From idl0r at qasl.de  Sun Dec 18 23:03:50 2011
From: idl0r at qasl.de (Christian Ruppert)
Date: Sun, 18 Dec 2011 23:03:50 +0100
Subject: [coreboot] Asus M4A78LT-M status
Message-ID: <1468547.iUyCbOd7pl@odin>

Hi guys,

I currently try to get coreboot working on my "Asus M4A78LT-M".
Using the M4A785T-M [1] as template works fine so far as the hardware is almost 
equal but there are a few issues:

a)
My RAM sticks [2] (tried both separate) doesn't work (see serial-ram-
fail.txt).
It is present but not valid, it seems the CRC check fails in 
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c and I have no idea why...

My other RAM sticks [3] (only one tested) seem to work (see serial-ram-
works.txt)

Do you guys have any ideas why the other sticks do not work?

b) Neither the NVIDIA (ZOTAC GeForce 210 Synergy Edition 512MB) PCIe card nor 
the on-board ATI Radeon HD 3000 works.
I tried to extract the VGA bios of the on-board card by using the bios_extract 
script mentioned at [4] as well as Peter's shell command mentioned at [5].
bios_extract doesn't seem to find the VGA bios, at least the PCI IDs doesn't 
match.
I get amipci_1002_4392.rom, amipci_1002_FFF1.rom and amipci_1002_FFF2.rom but 
the PCI ID of the on-board ATI card is: 1002:9616.
So I tried Peter's command and that seems to work at least partially. I do get 
some strange stuff on the screen incl. a flashing cursor but that's it...

So I'd like to know how to get the PCIe card working at least (which is 
totally enough for me or resp. exactly what I want).
The on-board one would be only interesting for my Wiki article, so for others.

c)
Not sure if I just misunderstood something.. I have GRUB 1 / legacy installed 
on my disk and SeaBIOS tries to load GRUB but then it freezes. From what I've 
read only GRUB 2 is supported as *payload*. Does it also apply to GRUB on a 
disk?

d)
Using the microcode update stuff results into some strange boot issues (see 
serial-microcode_fail.txt, note the "rscp7u80S_eetAaMrDlyM_SsRe tup()") and 
freezes.
Is it a known issue? Any workarounds?
Even "Juhe" (the author of the M4A785T-M [1] article mentioned that..
In my case it is a AMD Athlon II X2 245e.


So as you can see in serial-ram-works.txt it's almost working. I guess it'll 
boot "fine" if you guys are able to help me with the issues above.
If you (like me) prefer IRC then just poke me (idl0r) and I'll post any 
successfully results either here or on the Wiki article later.

[1] http://www.coreboot.org/ASUS_M4A785T-M
[2] http://www.gskill.com/products.php?index=223
[3] http://www.gskill.com/products.php?index=243
[4] 
http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image
[5] 
http://www.coreboot.org/VGA_support#Extracting_from_the_system_.28if_everything_else_fails.29

-- 
Regards,
Christian Ruppert
-------------- next part --------------
coreboot-4.0-1914-g66ebaa9-dirty Sun Dec 18 18:20:39 CET 2011 starting...
BSP Family_Model: 00100f63 
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00 
cpu_init_detectedx = 00000000 
cpuSetAMDMSR  done
Enter amd_ht_init()
AMD_CB_EventNotify()
 event class: 02
 event: 2005
 data:  05  00  00  00  01 
AMD_CB_EventNotify()
 event class: 05
 event: 2006
 data:  04  00  00  ff 
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00 
  F3x80: e600e681 
  F3x84: 80e641e6 
  F3xD4: c8810f26 
  F3xD8: 03001016 
  F3xDC: 0000532e 
core0 started: 
start_other_cores()
init node: 00  cores: 01 
Start other core - nodeid: 00  cores: 01
started ap apicid:  corex:  --- { APICID = 01 NODEID = 00 COREID = 01} ---
on ApuPS e01tAMDMSR start edd
  e

init_fidvid_stage2 apicid: 01
rs780_early_setup()
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()

Begin FIDVID MSR 0xc0010071 0x30ba0083 0x44005c40 
End FIDVIDMSR 0xc0010071 0x30ba0083 0x4400200d 
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
         DIMMPresence: DIMMValid=0
         DIMMPresence: DIMMPresent=8
         DIMMPresence: RegDIMMPresent=0
         DIMMPresence: DimmECCPresent=0
         DIMMPresence: DimmPARPresent=0
         DIMMPresence: Dimmx4Present=0
         DIMMPresence: Dimmx8Present=8
         DIMMPresence: Dimmx16Present=0
         DIMMPresence: DimmPlPresent=0
         DIMMPresence: DimmDRPresent=8
         DIMMPresence: DimmQRPresent=0
         DIMMPresence: DATAload[0]=0
         DIMMPresence: MAload[0]=0
         DIMMPresence: MAdimms[0]=0
         DIMMPresence: DATAload[1]=2
         DIMMPresence: MAload[1]=10
         DIMMPresence: MAdimms[1]=1
         DIMMPresence: Status 1000
         DIMMPresence: ErrStatus 3
         DIMMPresence: ErrCode 2
         DIMMPresence: Done

No Nodes?!
mct_d: fatalexit
-------------- next part --------------


coreboot-4.0-1914-g66ebaa9-dirty Sun Dec 18 19:38:55 CET 2011 starting...
BSP Family_Model: 00100f63 
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00 
cpu_init_detectedx = 00000000 
cpuSetAMDMSR  done
Enter amd_ht_init()
AMD_CB_EventNotify()
 event class: 02
 event: 2005
 data:  05  00  00  00  01 
AMD_CB_EventNotify()
 event class: 05
 event: 2006
 data:  04  00  00  ff 
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00 
  F3x80: e600e681 
  F3x84: 80e641e6 
  F3xD4: c8810f24 
  F3xD8: 03001016 
  F3xDC: 0000532e 
core0 started: 
start_other_cores()
init node: 00  cores: 01 
Start other core - nodeid: 00  cores: 01
started ap apicid:  corex:  --- { APICID = 01 NODEID = 00 COREID = 01} ---
*cp uASPe 0t1AMDMSR start eddo
ne

init_fidvid_ap(stage1) apicid: 01
FrIDsV7I8D0 _oena rlAyP_:s e0t1up
()
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()

Begin FIDVID MSR 0xc0010071 0x30ba0083 0x48035c40 
FIDVID on BSP, APIC_id: 00
BSP fid = 10600
Wait for AP stage 1: ap_apicid = 1
	readback = 1010601
	common_fid(packed) = 10600
common_fid = 10600
FID Change Node:00, F3xD4: c8810f26 
End FIDVIDMSR 0xc0010071 0x30ba0083 0x44005c40 
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
...WARM RESET...




coreboot-4.0-1914-g66ebaa9-dirty Sun Dec 18 19:38:55 CET 2011 starting...
BSP Family_Model: 00100f63 
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00 
cpu_init_detectedx = 00000000 
cpuSetAMDMSR  done
Enter amd_ht_init()
AMD_CB_EventNotify()
 event class: 02
 event: 2005
 data:  05  00  00  00  01 
AMD_CB_EventNotify()
 event class: 05
 event: 2006
 data:  04  00  00  ff 
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00 
  F3x80: e600e681 
  F3x84: 80e641e6 
  F3xD4: c8810f26 
  F3xD8: 03001016 
  F3xDC: 0000532e 
core0 started: 
start_other_cores()
init node: 00  cores: 01 
Start other core - nodeid: 00  cores: 01
started ap apicid:  corex:  --- { APICID = 01 NODEID = 00 COREID = 01} ---
*cp uASPe t0A1MDMSR starte ddo
ne

init_fidvid_stage2 apicid: 01
rs780_early_setup()
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()

Begin FIDVID MSR 0xc0010071 0x30ba0083 0x44005c40 
End FIDVIDMSR 0xc0010071 0x30ba0083 0x4400200d 
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
MAX_NODES_SUPPORTED: 8
Trying to initilize node 0...
Node 0 is present...
	 DIMMPresence: DIMMValid=4
	 DIMMPresence: DIMMPresent=4
	 DIMMPresence: RegDIMMPresent=0
	 DIMMPresence: DimmECCPresent=0
	 DIMMPresence: DimmPARPresent=0
	 DIMMPresence: Dimmx4Present=0
	 DIMMPresence: Dimmx8Present=4
	 DIMMPresence: Dimmx16Present=0
	 DIMMPresence: DimmPlPresent=0
	 DIMMPresence: DimmDRPresent=4
	 DIMMPresence: DimmQRPresent=0
	 DIMMPresence: DATAload[0]=2
	 DIMMPresence: MAload[0]=10
	 DIMMPresence: MAdimms[0]=1
	 DIMMPresence: DATAload[1]=0
	 DIMMPresence: MAload[1]=0
	 DIMMPresence: MAdimms[1]=0
DEBUG: DIMMPresence: ErrCode 0
	 DIMMPresence: Status 1000
	 DIMMPresence: ErrStatus 0
	 DIMMPresence: ErrCode 0
	 DIMMPresence: Done

		DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
		DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 4
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 1000
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done

mct_AfterGetCLT
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

		DCTInit_D: AutoCycTiming_D Done
FOOOOO
SPDSetBanks: CSPresent c
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done

AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7fffff
StitchMemory: Status 1000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done

InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done

AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: 90092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 8010000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done

		DCTInit_D: AutoConfig_D Done
		DCTInit_D: PlatformSpec_D Done
		DCTInit_D: StartupDCT_D
Trying to initilize node 1...
Trying to initilize node 2...
Trying to initilize node 3...
Trying to initilize node 4...
Trying to initilize node 5...
Trying to initilize node 6...
Trying to initilize node 7...
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
 Node: 00  base: 00  limit: 7fffff  BottomIO: c00000
 Node: 00  base: 03  limit: 7fffff 
 Node: 01  base: 00  limit: 00 
 Node: 02  base: 00  limit: 00 
 Node: 03  base: 00  limit: 00 
 Node: 04  base: 00  limit: 00 
 Node: 05  base: 00  limit: 00 
 Node: 06  base: 00  limit: 00 
 Node: 07  base: 00  limit: 00 
mctAutoInitMCT_D: CPUMemTyping_D
	 CPUMemTyping: Cache32bTOP:800000
	 CPUMemTyping: Bottom32bIO:800000
	 CPUMemTyping: Bottom40bIO:0
mctAutoInitMCT_D: DQSTiming_D
TrainRcvrEn: Status 1000
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 1000
InterleaveNodes_D: ErrStatus 0
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done

InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done

mctAutoInitMCT_D: ECCInit_D
All Done
raminit_amdmct end:

*** Yes, the copy/decompress is taking a while, FIXME!
v_esp=000cbf28
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now 
Clearing initial memory region: Done
Loading image.
Searching for fallback/coreboot_ram
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x200000 (1245184 bytes), entry @ 0x200000
Stage: done loading.
Jumping to image.
coreboot-4.0-1914-g66ebaa9-dirty Sun Dec 18 19:38:55 CET 2011 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 0
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 0
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 0
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 1
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
Compare with tree...
Root Device: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:18.0: enabled 1
   PCI: 00:00.0: enabled 1
   PCI: 00:01.0: enabled 1
   PCI: 00:02.0: enabled 0
   PCI: 00:03.0: enabled 0
   PCI: 00:04.0: enabled 0
   PCI: 00:05.0: enabled 0
   PCI: 00:06.0: enabled 0
   PCI: 00:07.0: enabled 0
   PCI: 00:08.0: enabled 0
   PCI: 00:09.0: enabled 0
   PCI: 00:0a.0: enabled 1
   PCI: 00:11.0: enabled 1
   PCI: 00:12.0: enabled 1
   PCI: 00:12.1: enabled 1
   PCI: 00:12.2: enabled 1
   PCI: 00:13.0: enabled 1
   PCI: 00:13.1: enabled 1
   PCI: 00:13.2: enabled 1
   PCI: 00:14.0: enabled 1
    I2C: 00:50: enabled 1
    I2C: 00:51: enabled 1
    I2C: 00:52: enabled 1
    I2C: 00:53: enabled 1
   PCI: 00:14.1: enabled 1
   PCI: 00:14.2: enabled 1
   PCI: 00:14.3: enabled 1
    PNP: 002e.0: enabled 0
    PNP: 002e.1: enabled 1
    PNP: 002e.2: enabled 0
    PNP: 002e.3: enabled 0
    PNP: 002e.4: enabled 0
    PNP: 002e.5: enabled 1
    PNP: 002e.6: enabled 1
    PNP: 002e.7: enabled 0
    PNP: 002e.8: enabled 0
    PNP: 002e.9: enabled 0
    PNP: 002e.a: enabled 0
   PCI: 00:14.4: enabled 1
   PCI: 00:14.5: enabled 1
  PCI: 00:18.1: enabled 1
  PCI: 00:18.2: enabled 1
  PCI: 00:18.3: enabled 1
  PCI: 00:18.4: enabled 1
Mainboard enable. dev=0x00227dc4
m4a785m_enable, TOP MEM: msr.lo = 0x80000000, msr.hi = 0x00000000
m4a785m_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
m4a785m_enable: uma size 0x10000000, memory start 0x70000000
PCI: Using configuration type 1
Init adt7461 end , status 0x02 fd
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  PCI: 00:18.3 siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
rs780_enable: dev=00228258, VID_DID=0x96001022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
addr=e0000000,bus=0,devfn=40
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9600] ops
PCI: 00:00.0 [1022/9600] enabled
Capability: type 0x08 @ 0xc4
flags: 0x0181
PCI: pci_scan_bus for bus 00
PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
PCI: pci_scan_bus upper limit too big. Using 0xff.
rs780_enable: dev=00228258, VID_DID=0x96001022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9600] enabled
rs780_enable: dev=00228498, VID_DID=0x96021022
Bus-0, Dev-1, Fun-0.
GC is accessible from now on.
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
PCI: 00:01.0 [1022/9602] enabled
rs780_enable: dev=00228648, VID_DID=0x96031022
Bus-0, Dev-2,3, Fun-0. enable=0
rs780_enable: dev=00228768, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=0
rs780_enable: dev=002287f8, VID_DID=0x96041022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00228888, VID_DID=0x96051022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00228918, VID_DID=0x96061022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=002289a8, VID_DID=0x96071022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00228a38, VID_DID=0x960a1022
Bus-0, Dev-8, Fun-0. enable=0
rs780_enable: dev=00228ac8, VID_DID=0x96081022
Bus-0, Dev-9, 10, Fun-0. enable=0
rs780_enable: dev=00228b58, VID_DID=0x96091022
Bus-0, Dev-9, 10, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x50, port=0xa
PcieLinkTraining port=a:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=50
PcieTrainPort reg=0x10000
PcieTrainPort port=0xa result=1
disable_pcie_bar3()
rs780 unused GPP ports bitmap=0x2fc, force disabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1022/9609] enabled
sb7xx_51xx_enable()
PCI: 00:11.0 [1002/4390] ops
PCI: 00:11.0 [1002/4390] enabled
sb7xx_51xx_enable()
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:12.1 [1002/4398] ops
PCI: 00:12.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:13.1 [1002/4398] ops
PCI: 00:13.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:14.0 [1002/4385] bus ops
PCI: 00:14.0 [1002/4385] enabled
sb7xx_51xx_enable()
PCI: 00:14.1 [1002/439c] ops
PCI: 00:14.1 [1002/439c] enabled
sb7xx_51xx_enable()
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb7xx_51xx_enable()
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb7xx_51xx_enable()
PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb7xx_51xx_enable()
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: 01:05.0 [1002/9616] enabled
PCI: 01:05.1 [1002/960f] enabled
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [10ec/8168] enabled
PCI: pci_scan_bus returning with max=002
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
do_pci_scan_bridge returns max 2
scan_static_bus for PCI: 00:14.0
smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled
scan_static_bus for PCI: 00:14.0 done
scan_static_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 enabled
PNP: 002e.2 disabled
PNP: 002e.3 disabled
PNP: 002e.4 disabled
PNP: 002e.5 enabled
PNP: 002e.6 enabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
scan_static_bus for PCI: 00:14.3 done
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 03
PCI: 03:06.0 [1822/4e35] enabled
PCI: pci_scan_bus returning with max=003
do_pci_scan_bridge returns max 3
PCI: pci_scan_bus returning with max=003
PCI: pci_scan_bus returning with max=003
PCI_DOMAIN: 0000 passpw: enabled
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 01:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:00.0 register 1c(00000004), read-only ignoring it
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:0a.0 read_resources bus 2 link: 0
PCI: 00:0a.0 read_resources bus 2 link: 0 done
PCI: 00:14.0 read_resources bus 1 link: 0
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
PCI: 00:14.0 read_resources bus 1 link: 0 done
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 3 link: 0
PCI: 00:14.4 read_resources bus 3 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI: 00:18.0 read_resources bus 0 link: 3
PCI: 00:18.0 read_resources bus 0 link: 3 done
PCI: 00:18.0 read_resources bus 0 link: 4
PCI: 00:18.0 read_resources bus 0 link: 4 done
PCI: 00:18.0 read_resources bus 0 link: 5
PCI: 00:18.0 read_resources bus 0 link: 5 done
PCI: 00:18.0 read_resources bus 0 link: 6
PCI: 00:18.0 read_resources bus 0 link: 6 done
PCI: 00:18.0 read_resources bus 0 link: 7
PCI: 00:18.0 read_resources bus 0 link: 7 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: 01
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
   PCI: 00:18.0 child on link 0 PCI: 00:00.0
   PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0
    PCI: 00:00.0
    PCI: 00:01.0 child on link 0 PCI: 01:05.0
    PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit 1ffffff flags 80102 index 1c
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81202 index 24
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 01:05.0
     PCI: 01:05.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
     PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
     PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18
     PCI: 01:05.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 24
     PCI: 01:05.1
     PCI: 01:05.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
    PCI: 00:02.0
    PCI: 00:03.0
    PCI: 00:04.0
    PCI: 00:05.0
    PCI: 00:06.0
    PCI: 00:07.0
    PCI: 00:08.0
    PCI: 00:09.0
    PCI: 00:0a.0 child on link 0 PCI: 02:00.0
    PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 02:00.0
     PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
     PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
     PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
     PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
    PCI: 00:11.0
    PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
    PCI: 00:12.0
    PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:12.1
    PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:12.2
    PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
    PCI: 00:13.0
    PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:13.1
    PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:13.2
    PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
    PCI: 00:14.0 child on link 0 I2C: 01:50
    PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
    PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
    PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
     I2C: 01:50
     I2C: 01:51
     I2C: 01:52
     I2C: 01:53
    PCI: 00:14.1
    PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:14.2
    PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
    PCI: 00:14.3 child on link 0 PNP: 002e.0
    PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 200 index a0
    PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
    PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
     PNP: 002e.0
     PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.1
     PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
     PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.2
     PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
     PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.3
     PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60
     PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.4
     PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
     PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.5
     PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
     PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.6
     PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.7
     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
     PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
     PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.8
     PNP: 002e.8 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.9
     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
     PNP: 002e.a
     PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PCI: 00:14.4 child on link 0 PCI: 03:06.0
    PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
    PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
    PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 03:06.0
     PCI: 03:06.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 1200 index 10
    PCI: 00:14.5
    PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:18.0
    PCI: 00:18.1
    PCI: 00:18.2
    PCI: 00:18.3
    PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
    PCI: 00:18.4
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
   PCI: 00:18.4
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: 1ffffff
PCI: 01:05.0 14 *  [0x0 - 0xff] io
PCI: 00:01.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 02:00.0 10 *  [0x0 - 0xff] io
PCI: 00:0a.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c *  [0x0 - 0xfff] io
PCI: 00:0a.0 1c *  [0x1000 - 0x1fff] io
PCI: 00:11.0 20 *  [0x2000 - 0x200f] io
PCI: 00:14.1 20 *  [0x2010 - 0x201f] io
PCI: 00:11.0 10 *  [0x2020 - 0x2027] io
PCI: 00:11.0 18 *  [0x2028 - 0x202f] io
PCI: 00:14.1 10 *  [0x2030 - 0x2037] io
PCI: 00:14.1 18 *  [0x2038 - 0x203f] io
PCI: 00:11.0 14 *  [0x2040 - 0x2043] io
PCI: 00:11.0 1c *  [0x2044 - 0x2047] io
PCI: 00:14.1 14 *  [0x2048 - 0x204b] io
PCI: 00:14.1 1c *  [0x204c - 0x204f] io
PCI: 00:18.0 compute_resources_io: base: 2050 size: 3000 align: 12 gran: 12 limit: ffff done
PCI: 00:18.0 10d8 *  [0x0 - 0x2fff] io
PCI_DOMAIN: 0000 compute_resources_io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 01:05.0 10 *  [0x0 - 0xfffffff] prefmem
PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffff done
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 02:00.0 20 *  [0x0 - 0x3fff] prefmem
PCI: 02:00.0 18 *  [0x4000 - 0x4fff] prefmem
PCI: 00:0a.0 compute_resources_prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:06.0 10 *  [0x0 - 0xfff] prefmem
PCI: 00:14.4 compute_resources_prefmem: base: 1000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 24 *  [0x0 - 0xfffffff] prefmem
PCI: 00:0a.0 24 *  [0x10000000 - 0x100fffff] prefmem
PCI: 00:14.4 24 *  [0x10100000 - 0x101fffff] prefmem
PCI: 00:18.0 compute_resources_prefmem: base: 10200000 size: 10200000 align: 28 gran: 20 limit: ffffffff done
PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:05.0 24 *  [0x0 - 0xfffff] mem
PCI: 01:05.0 18 *  [0x100000 - 0x10ffff] mem
PCI: 01:05.1 10 *  [0x110000 - 0x113fff] mem
PCI: 00:01.0 compute_resources_mem: base: 114000 size: 200000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 30 *  [0x0 - 0xffff] mem
PCI: 00:0a.0 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:18.3 94 *  [0x0 - 0x3ffffff] mem
PCI: 00:01.0 20 *  [0x4000000 - 0x41fffff] mem
PCI: 00:0a.0 20 *  [0x4200000 - 0x42fffff] mem
PCI: 00:14.2 10 *  [0x4300000 - 0x4303fff] mem
PCI: 00:12.0 10 *  [0x4304000 - 0x4304fff] mem
PCI: 00:12.1 10 *  [0x4305000 - 0x4305fff] mem
PCI: 00:13.0 10 *  [0x4306000 - 0x4306fff] mem
PCI: 00:13.1 10 *  [0x4307000 - 0x4307fff] mem
PCI: 00:14.5 10 *  [0x4308000 - 0x4308fff] mem
PCI: 00:11.0 24 *  [0x4309000 - 0x43093ff] mem
PCI: 00:12.2 10 *  [0x4309400 - 0x43094ff] mem
PCI: 00:13.2 10 *  [0x4309500 - 0x43095ff] mem
PCI: 00:14.3 a0 *  [0x4309600 - 0x4309600] mem
PCI: 00:18.0 compute_resources_mem: base: 4309601 size: 4400000 align: 26 gran: 20 limit: ffffffff done
PCI: 00:18.0 10b8 *  [0x0 - 0x101fffff] prefmem
PCI: 00:18.0 10b0 *  [0x14000000 - 0x183fffff] mem
PCI: 00:18.3 94 *  [0x1c000000 - 0x1fffffff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 20000000 size: 20000000 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 01:05.0
constrain_resources: PCI: 01:05.1
constrain_resources: PCI: 00:0a.0
constrain_resources: PCI: 02:00.0
constrain_resources: PCI: 00:11.0
constrain_resources: PCI: 00:12.0
constrain_resources: PCI: 00:12.1
constrain_resources: PCI: 00:12.2
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:13.1
constrain_resources: PCI: 00:13.2
constrain_resources: PCI: 00:14.0
constrain_resources: I2C: 01:50
constrain_resources: I2C: 01:51
constrain_resources: I2C: 01:52
constrain_resources: I2C: 01:53
constrain_resources: PCI: 00:14.1
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PNP: 002e.1
constrain_resources: PNP: 002e.5
constrain_resources: PNP: 002e.6
constrain_resources: PCI: 00:14.4
constrain_resources: PCI: 03:06.0
constrain_resources: PCI: 00:14.5
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
	lim->base 00000000 lim->limit dfffffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:3000 align:12 gran:0 limit:ffff
Assigned: PCI: 00:18.0 10d8 *  [0x1000 - 0x3fff] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 4000 size: 3000 align: 12 gran: 0 done
PCI: 00:18.0 allocate_resources_io: base:1000 size:3000 align:12 gran:12 limit:ffff
Assigned: PCI: 00:01.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:0a.0 1c *  [0x2000 - 0x2fff] io
Assigned: PCI: 00:11.0 20 *  [0x3000 - 0x300f] io
Assigned: PCI: 00:14.1 20 *  [0x3010 - 0x301f] io
Assigned: PCI: 00:11.0 10 *  [0x3020 - 0x3027] io
Assigned: PCI: 00:11.0 18 *  [0x3028 - 0x302f] io
Assigned: PCI: 00:14.1 10 *  [0x3030 - 0x3037] io
Assigned: PCI: 00:14.1 18 *  [0x3038 - 0x303f] io
Assigned: PCI: 00:11.0 14 *  [0x3040 - 0x3043] io
Assigned: PCI: 00:11.0 1c *  [0x3044 - 0x3047] io
Assigned: PCI: 00:14.1 14 *  [0x3048 - 0x304b] io
Assigned: PCI: 00:14.1 1c *  [0x304c - 0x304f] io
PCI: 00:18.0 allocate_resources_io: next_base: 3050 size: 3000 align: 12 gran: 12 done
PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:05.0 14 *  [0x1000 - 0x10ff] io
PCI: 00:01.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
PCI: 00:0a.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 02:00.0 10 *  [0x2000 - 0x20ff] io
PCI: 00:0a.0 allocate_resources_io: next_base: 2100 size: 1000 align: 12 gran: 12 done
PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:20000000 align:28 gran:0 limit:dfffffff
Assigned: PCI: 00:18.0 10b8 *  [0xc0000000 - 0xd01fffff] prefmem
Assigned: PCI: 00:18.0 10b0 *  [0xd4000000 - 0xd83fffff] mem
Assigned: PCI: 00:18.3 94 *  [0xdc000000 - 0xdfffffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: e0000000 size: 20000000 align: 28 gran: 0 done
PCI: 00:18.0 allocate_resources_prefmem: base:c0000000 size:10200000 align:28 gran:20 limit:dfffffff
Assigned: PCI: 00:01.0 24 *  [0xc0000000 - 0xcfffffff] prefmem
Assigned: PCI: 00:0a.0 24 *  [0xd0000000 - 0xd00fffff] prefmem
Assigned: PCI: 00:14.4 24 *  [0xd0100000 - 0xd01fffff] prefmem
PCI: 00:18.0 allocate_resources_prefmem: next_base: d0200000 size: 10200000 align: 28 gran: 20 done
PCI: 00:01.0 allocate_resources_prefmem: base:c0000000 size:10000000 align:28 gran:20 limit:dfffffff
Assigned: PCI: 01:05.0 10 *  [0xc0000000 - 0xcfffffff] prefmem
PCI: 00:01.0 allocate_resources_prefmem: next_base: d0000000 size: 10000000 align: 28 gran: 20 done
PCI: 00:0a.0 allocate_resources_prefmem: base:d0000000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 02:00.0 20 *  [0xd0000000 - 0xd0003fff] prefmem
Assigned: PCI: 02:00.0 18 *  [0xd0004000 - 0xd0004fff] prefmem
PCI: 00:0a.0 allocate_resources_prefmem: next_base: d0005000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_prefmem: base:d0100000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 03:06.0 10 *  [0xd0100000 - 0xd0100fff] prefmem
PCI: 00:14.4 allocate_resources_prefmem: next_base: d0101000 size: 100000 align: 20 gran: 20 done
PCI: 00:18.0 allocate_resources_mem: base:d4000000 size:4400000 align:26 gran:20 limit:dfffffff
Assigned: PCI: 00:18.3 94 *  [0xd4000000 - 0xd7ffffff] mem
Assigned: PCI: 00:01.0 20 *  [0xd8000000 - 0xd81fffff] mem
Assigned: PCI: 00:0a.0 20 *  [0xd8200000 - 0xd82fffff] mem
Assigned: PCI: 00:14.2 10 *  [0xd8300000 - 0xd8303fff] mem
Assigned: PCI: 00:12.0 10 *  [0xd8304000 - 0xd8304fff] mem
Assigned: PCI: 00:12.1 10 *  [0xd8305000 - 0xd8305fff] mem
Assigned: PCI: 00:13.0 10 *  [0xd8306000 - 0xd8306fff] mem
Assigned: PCI: 00:13.1 10 *  [0xd8307000 - 0xd8307fff] mem
Assigned: PCI: 00:14.5 10 *  [0xd8308000 - 0xd8308fff] mem
Assigned: PCI: 00:11.0 24 *  [0xd8309000 - 0xd83093ff] mem
Assigned: PCI: 00:12.2 10 *  [0xd8309400 - 0xd83094ff] mem
Assigned: PCI: 00:13.2 10 *  [0xd8309500 - 0xd83095ff] mem
Assigned: PCI: 00:14.3 a0 *  [0xd8309600 - 0xd8309600] mem
PCI: 00:18.0 allocate_resources_mem: next_base: d8309601 size: 4400000 align: 26 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:d8000000 size:200000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 01:05.0 24 *  [0xd8000000 - 0xd80fffff] mem
Assigned: PCI: 01:05.0 18 *  [0xd8100000 - 0xd810ffff] mem
Assigned: PCI: 01:05.1 10 *  [0xd8110000 - 0xd8113fff] mem
PCI: 00:01.0 allocate_resources_mem: next_base: d8114000 size: 200000 align: 20 gran: 20 done
PCI: 00:0a.0 allocate_resources_mem: base:d8200000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 02:00.0 30 *  [0xd8200000 - 0xd820ffff] mem
PCI: 00:0a.0 allocate_resources_mem: next_base: d8210000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:14.4 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
0: mmio_basek=00300000, basek=00000300, limitk=00200000
Adding UMA memory area
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 10d8 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io <node 0 link 0>
PCI: 00:18.0 10b8 <- [0x00c0000000 - 0x00d01fffff] size 0x10200000 gran 0x14 prefmem <node 0 link 0>
PCI: 00:18.0 10b0 <- [0x00d4000000 - 0x00d83fffff] size 0x04400000 gran 0x14 mem <node 0 link 0>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00d8000000 - 0x00d81fffff] size 0x00200000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:05.0 10 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem
PCI: 01:05.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:05.0 18 <- [0x00d8100000 - 0x00d810ffff] size 0x00010000 gran 0x10 mem
PCI: 01:05.0 24 <- [0x00d8000000 - 0x00d80fffff] size 0x00100000 gran 0x14 mem
PCI: 01:05.1 10 <- [0x00d8110000 - 0x00d8113fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 02 io
PCI: 00:0a.0 24 <- [0x00d0000000 - 0x00d00fffff] size 0x00100000 gran 0x14 bus 02 prefmem
PCI: 00:0a.0 20 <- [0x00d8200000 - 0x00d82fffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:0a.0 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 02:00.0 18 <- [0x00d0004000 - 0x00d0004fff] size 0x00001000 gran 0x0c prefmem64
PCI: 02:00.0 20 <- [0x00d0000000 - 0x00d0003fff] size 0x00004000 gran 0x0e prefmem64
PCI: 02:00.0 30 <- [0x00d8200000 - 0x00d820ffff] size 0x00010000 gran 0x10 romem
PCI: 00:0a.0 assign_resources, bus 2 link: 0
PCI: 00:11.0 10 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000003040 - 0x0000003043] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000003028 - 0x000000302f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000003044 - 0x0000003047] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000003000 - 0x000000300f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00d8309000 - 0x00d83093ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00d8304000 - 0x00d8304fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.1 10 <- [0x00d8305000 - 0x00d8305fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00d8309400 - 0x00d83094ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00d8306000 - 0x00d8306fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.1 10 <- [0x00d8307000 - 0x00d8307fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00d8309500 - 0x00d83095ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.1 10 <- [0x0000003030 - 0x0000003037] size 0x00000008 gran 0x03 io
PCI: 00:14.1 14 <- [0x0000003048 - 0x000000304b] size 0x00000004 gran 0x02 io
PCI: 00:14.1 18 <- [0x0000003038 - 0x000000303f] size 0x00000008 gran 0x03 io
PCI: 00:14.1 1c <- [0x000000304c - 0x000000304f] size 0x00000004 gran 0x02 io
PCI: 00:14.1 20 <- [0x0000003010 - 0x000000301f] size 0x00000010 gran 0x04 io
PCI: 00:14.2 10 <- [0x00d8300000 - 0x00d8303fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 a0 <- [0x00d8309600 - 0x00d8309600] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PCI: 00:14.3 assign_resources, bus 0 link: 0
PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:14.4 24 <- [0x00d0100000 - 0x00d01fffff] size 0x00100000 gran 0x14 bus 03 prefmem
PCI: 00:14.4 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 03 mem
PCI: 00:14.4 assign_resources, bus 3 link: 0
PCI: 03:06.0 10 <- [0x00d0100000 - 0x00d0100fff] size 0x00001000 gran 0x0c prefmem
PCI: 00:14.4 assign_resources, bus 3 link: 0
PCI: 00:14.5 10 <- [0x00d8308000 - 0x00d8308fff] size 0x00001000 gran 0x0c mem
PCI: 00:18.3 94 <- [0x00d4000000 - 0x00d7ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.3 94 <- [0x00d4000000 - 0x00d7ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:18.3 94 <- [0x00dc000000 - 0x00dfffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.3 94 <- [0x00dc000000 - 0x00dfffffff] size 0x04000000 gran 0x1a mem <gart>
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: 01
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base c0000000 size 20000000 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
  PCI_DOMAIN: 0000 resource base c0000 size 6ff40000 align 0 gran 0 limit 0 flags e0004200 index 20
  PCI_DOMAIN: 0000 resource base 70000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 7
   PCI: 00:18.0 child on link 0 PCI: 00:00.0
   PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit ffff flags 60080100 index 10d8
   PCI: 00:18.0 resource base c0000000 size 10200000 align 28 gran 20 limit dfffffff flags 60081200 index 10b8
   PCI: 00:18.0 resource base d4000000 size 4400000 align 26 gran 20 limit dfffffff flags 60080200 index 10b0
    PCI: 00:00.0
    PCI: 00:01.0 child on link 0 PCI: 01:05.0
    PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:01.0 resource base c0000000 size 10000000 align 28 gran 20 limit dfffffff flags 60081202 index 24
    PCI: 00:01.0 resource base d8000000 size 200000 align 20 gran 20 limit dfffffff flags 60080202 index 20
     PCI: 01:05.0
     PCI: 01:05.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001200 index 10
     PCI: 01:05.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
     PCI: 01:05.0 resource base d8100000 size 10000 align 16 gran 16 limit dfffffff flags 60000200 index 18
     PCI: 01:05.0 resource base d8000000 size 100000 align 20 gran 20 limit dfffffff flags 60000200 index 24
     PCI: 01:05.1
     PCI: 01:05.1 resource base d8110000 size 4000 align 14 gran 14 limit dfffffff flags 60000200 index 10
    PCI: 00:02.0
    PCI: 00:03.0
    PCI: 00:04.0
    PCI: 00:05.0
    PCI: 00:06.0
    PCI: 00:07.0
    PCI: 00:08.0
    PCI: 00:09.0
    PCI: 00:0a.0 child on link 0 PCI: 02:00.0
    PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:0a.0 resource base d0000000 size 100000 align 20 gran 20 limit dfffffff flags 60081202 index 24
    PCI: 00:0a.0 resource base d8200000 size 100000 align 20 gran 20 limit dfffffff flags 60080202 index 20
     PCI: 02:00.0
     PCI: 02:00.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
     PCI: 02:00.0 resource base d0004000 size 1000 align 12 gran 12 limit dfffffff flags 60001201 index 18
     PCI: 02:00.0 resource base d0000000 size 4000 align 14 gran 14 limit dfffffff flags 60001201 index 20
     PCI: 02:00.0 resource base d8200000 size 10000 align 16 gran 16 limit dfffffff flags 60002200 index 30
    PCI: 00:11.0
    PCI: 00:11.0 resource base 3020 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
    PCI: 00:11.0 resource base 3040 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
    PCI: 00:11.0 resource base 3028 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
    PCI: 00:11.0 resource base 3044 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
    PCI: 00:11.0 resource base 3000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
    PCI: 00:11.0 resource base d8309000 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 24
    PCI: 00:12.0
    PCI: 00:12.0 resource base d8304000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10
    PCI: 00:12.1
    PCI: 00:12.1 resource base d8305000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10
    PCI: 00:12.2
    PCI: 00:12.2 resource base d8309400 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10
    PCI: 00:13.0
    PCI: 00:13.0 resource base d8306000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10
    PCI: 00:13.1
    PCI: 00:13.1 resource base d8307000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10
    PCI: 00:13.2
    PCI: 00:13.2 resource base d8309500 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10
    PCI: 00:14.0 child on link 0 I2C: 01:50
    PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
    PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
    PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
     I2C: 01:50
     I2C: 01:51
     I2C: 01:52
     I2C: 01:53
    PCI: 00:14.1
    PCI: 00:14.1 resource base 3030 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
    PCI: 00:14.1 resource base 3048 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
    PCI: 00:14.1 resource base 3038 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
    PCI: 00:14.1 resource base 304c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
    PCI: 00:14.1 resource base 3010 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
    PCI: 00:14.2
    PCI: 00:14.2 resource base d8300000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10
    PCI: 00:14.3 child on link 0 PNP: 002e.0
    PCI: 00:14.3 resource base d8309600 size 1 align 0 gran 0 limit dfffffff flags 60000200 index a0
    PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
    PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
     PNP: 002e.0
     PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.1
     PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
     PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.2
     PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
     PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.3
     PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60
     PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.4
     PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
     PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.5
     PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
     PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.6
     PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.7
     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
     PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
     PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.8
     PNP: 002e.8 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.9
     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
     PNP: 002e.a
     PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PCI: 00:14.4 child on link 0 PCI: 03:06.0
    PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:14.4 resource base d0100000 size 100000 align 20 gran 20 limit dfffffff flags 60081202 index 24
    PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20
     PCI: 03:06.0
     PCI: 03:06.0 resource base d0100000 size 1000 align 12 gran 12 limit dfffffff flags 60001200 index 10
    PCI: 00:14.5
    PCI: 00:14.5 resource base d8308000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10
    PCI: 00:18.0
    PCI: 00:18.1
    PCI: 00:18.2
    PCI: 00:18.3
    PCI: 00:18.3 resource base d4000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94
    PCI: 00:18.4
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.3 resource base dc000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94
   PCI: 00:18.4
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1043/83a2
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1043/83a2
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 subsystem <- 1043/83a2
PCI: 00:18.4 cmd <- 00
PCI: 00:00.0 subsystem <- 1043/83a2
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000b
PCI: 00:01.0 cmd <- 07
PCI: 00:0a.0 bridge ctrl <- 0003
PCI: 00:0a.0 cmd <- 07
PCI: 00:11.0 subsystem <- 1043/83a2
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1043/83a2
PCI: 00:12.0 cmd <- 02
PCI: 00:12.1 subsystem <- 1043/83a2
PCI: 00:12.1 cmd <- 02
PCI: 00:12.2 subsystem <- 1043/83a2
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1043/83a2
PCI: 00:13.0 cmd <- 02
PCI: 00:13.1 subsystem <- 1043/83a2
PCI: 00:13.1 cmd <- 02
PCI: 00:13.2 subsystem <- 1043/83a2
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1043/83a2
PCI: 00:14.0 cmd <- 403
PCI: 00:14.1 subsystem <- 1043/83a2
PCI: 00:14.1 cmd <- 01
PCI: 00:14.2 subsystem <- 1043/83a2
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1043/83a2
PCI: 00:14.3 cmd <- 0f
sb700 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff
sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 cmd <- 07
PCI: 00:14.5 subsystem <- 1043/83a2
PCI: 00:14.5 cmd <- 02
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 cmd <- 00
PCI: 01:05.0 cmd <- 03
PCI: 01:05.1 cmd <- 02
PCI: 02:00.0 cmd <- 03
PCI: 03:06.0 cmd <- 02
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x0000c000, offset=0x00200000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor AMD device 100f63
CPU: family 10, model 06, stepping 03
nodeid = 00, coreid = 00
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 1792MB, range:  256MB, type UC
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x00 done.
CPU model: AMD Athlon(tm) II X2 245e Processor
siblings = 01, CPU #0 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor AMD device 100f63
CPU: family 10, model 06, stepping 03
nodeid = 00, coreid = 01
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 1792MB, range:  256MB, type UC
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x01 done.
CPU model: AMD Athlon(tm) II X2 245e Processor
siblings = 01, CPU #1 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:18.1 init
Searching for pci1022,1201.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci1022,1201.rom'.
PCI: 00:18.2 init
Searching for pci1022,1202.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci1022,1202.rom'.
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:18.4 init
Searching for pci1022,1204.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci1022,1204.rom'.
PCI: 00:00.0 init
pcie_init in rs780_ht.c
PCI: 00:11.0 init
sata_bar0=3020
sata_bar1=3040
sata_bar2=3028
sata_bar3=3044
sata_bar4=3000
sata_bar5=d8309000
SATA port 0 status = 23
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=0, 0x7=50
drive no longer selected after 2450 ms, retrying init
drive detection done after 0 ms
Primary Master device is ready after 2 tries
SATA port 1 status = 0
No Primary Slave SATA drive on Slot1
SATA port 2 status = 13
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
Secondary Master device is not ready after 10 tries
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3
PCI: 00:12.0 init
PCI: 00:12.1 init
PCI: 00:12.2 init
usb2_bar0=0xd8309400
rpr 6.23, final dword=809e01c8
PCI: 00:13.0 init
PCI: 00:13.1 init
PCI: 00:13.2 init
usb2_bar0=0xd8309500
rpr 6.23, final dword=809e01c8
PCI: 00:14.0 init
sm_init().
IOAPIC: Clearing IOAPIC at 0xfec00000
IOAPIC: 23 interrupts
IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
set power off after power fail
++++++++++no set NMI+++++
RTC Init
sm_init() end
PCI: 00:14.1 init
Searching for pci1002,439c.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci1002,439c.rom'.
PCI: 00:14.2 init
base = 0xd8300000
codec_mask = 05
2(th) codec viddid: ffffffff
0(th) codec viddid: ffffffff
PCI: 00:14.3 init
Skipping isa_dma_init() to avoid getting stuck.
PCI: 00:14.4 init
PCI: 00:14.5 init
PCI: 00:18.0 init
PCI: 00:18.1 init
Searching for pci1022,1201.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci1022,1201.rom'.
PCI: 00:18.2 init
Searching for pci1022,1202.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci1022,1202.rom'.
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:18.4 init
Searching for pci1022,1204.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci1022,1204.rom'.
PCI: 01:05.0 init
Searching for pci1002,9616.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci1002,9616.rom'.
PCI: 01:05.1 init
Searching for pci1002,960f.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci1002,960f.rom'.
PCI: 02:00.0 init
Searching for pci10ec,8168.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci10ec,8168.rom'.
On card, ROM address for PCI: 02:00.0 = d8200000
PCI expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
Incorrect expansion ROM header signature 0000
PNP: 002e.1 init
PNP: 002e.5 init
Keyboard init...
No PS/2 keyboard detected.
PNP: 002e.6 init
PCI: 03:06.0 init
Searching for pci1822,4e35.rom
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check 
Could not find file 'pci1822,4e35.rom'.
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 0
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 0
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 01:50: enabled 1
I2C: 01:51: enabled 1
I2C: 01:52: enabled 1
I2C: 01:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 0
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 1
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
APIC: 01: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 01:05.0: enabled 1
PCI: 01:05.1: enabled 1
PCI: 02:00.0: enabled 1
PCI: 03:06.0: enabled 1
Initializing CBMEM area to 0x6fff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 6fff0200...ok
High Tables Base is 6fff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x6fff0400... done.
PIRQ table: 336 bytes.
Wrote the mp table end at: 000f0410 - 000f0514
Adding CBMEM entry as no. 3
Wrote the mp table end at: 6fff1410 - 6fff1514
MP table: 276 bytes.
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at 6fff2400...
ACPI:    * HPET at 6fff24c8
ACPI: added table 1/32, length now 40
ACPI:    * MADT at 6fff2500
ACPI: added table 2/32, length now 44
ACPI:    * SRAT at 6fff2560
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=001bfd00
ACPI: added table 3/32, length now 48
ACPI:   * SLIT at 6fff2600
ACPI: added table 4/32, length now 52
ACPI:    * SSDT at 6fff2630
ACPI: added table 5/32, length now 56
ACPI:    * SSDT for PState at 6fff2c65
ACPI:    * DSDT at 6fff2c68
ACPI:    * DSDT @ 6fff2c68 Length 298c
ACPI:	* FACS at 6fff55f8
ACPI:    * FADT at 6fff5638
pm_base: 0x0800
ACPI: added table 6/32, length now 60
ACPI: done.
ACPI tables: 13100 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: 6fffd800
Root Device (ASUS M4A785T-M Mainboard)
APIC_CLUSTER: 0 (AMD FAM10 Root Complex)
APIC: 00 (socket AM3)
PCI_DOMAIN: 0000 (AMD FAM10 Root Complex)
PCI: 00:18.0 (AMD FAM10 Northbridge)
PCI: 00:00.0 (ATI RS780)
PCI: 00:01.0 (ATI RS780)
PCI: 00:02.0 (ATI RS780)
PCI: 00:03.0 (ATI RS780)
PCI: 00:04.0 (ATI RS780)
PCI: 00:05.0 (ATI RS780)
PCI: 00:06.0 (ATI RS780)
PCI: 00:07.0 (ATI RS780)
PCI: 00:08.0 (ATI RS780)
PCI: 00:09.0 (ATI RS780)
PCI: 00:0a.0 (ATI RS780)
PCI: 00:11.0 (ATI SB700)
PCI: 00:12.0 (ATI SB700)
PCI: 00:12.1 (ATI SB700)
PCI: 00:12.2 (ATI SB700)
PCI: 00:13.0 (ATI SB700)
PCI: 00:13.1 (ATI SB700)
PCI: 00:13.2 (ATI SB700)
PCI: 00:14.0 (ATI SB700)
I2C: 01:50 ()
I2C: 01:51 ()
I2C: 01:52 ()
I2C: 01:53 ()
PCI: 00:14.1 (ATI SB700)
PCI: 00:14.2 (ATI SB700)
PCI: 00:14.3 (ATI SB700)
PNP: 002e.0 (ITE IT8712F Super I/O)
PNP: 002e.1 (ITE IT8712F Super I/O)
PNP: 002e.2 (ITE IT8712F Super I/O)
PNP: 002e.3 (ITE IT8712F Super I/O)
PNP: 002e.4 (ITE IT8712F Super I/O)
PNP: 002e.5 (ITE IT8712F Super I/O)
PNP: 002e.6 (ITE IT8712F Super I/O)
PNP: 002e.7 (ITE IT8712F Super I/O)
PNP: 002e.8 (ITE IT8712F Super I/O)
PNP: 002e.9 (ITE IT8712F Super I/O)
PNP: 002e.a (ITE IT8712F Super I/O)
PCI: 00:14.4 (ATI SB700)
PCI: 00:14.5 (ATI SB700)
PCI: 00:18.1 (AMD FAM10 Northbridge)
PCI: 00:18.2 (AMD FAM10 Northbridge)
PCI: 00:18.3 (AMD FAM10 Northbridge)
PCI: 00:18.4 (AMD FAM10 Northbridge)
APIC: 01 ()
PCI: 00:18.0 ()
PCI: 00:18.1 ()
PCI: 00:18.2 ()
PCI: 00:18.3 ()
PCI: 00:18.4 ()
PCI: 01:05.0 ()
PCI: 01:05.1 ()
PCI: 02:00.0 ()
PCI: 03:06.0 ()
SMBIOS tables: 282 bytes.
Adding CBMEM entry as no. 6
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum afde
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x6fffe000
rom_table_end = 0x6fffe000
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0x6fffe000 to 0x70000000 
Adding high table area
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000006ffeffff: RAM
 3. 000000006fff0000-000000006fffffff: CONFIGURATION TABLES
 4. 0000000070000000-000000007fffffff: RESERVED
 5. 00000000e0000000-00000000efffffff: RESERVED
 6. 00000000fec00000-00000000fec00fff: RESERVED
 7. 00000000fed00000-00000000fed003ff: RESERVED
Wrote coreboot table at: 6fffe000 - 6fffe208  checksum af8c
coreboot table: 520 bytes.
Multiboot Information structure has been written.
 0. FREE SPACE 70000000 00000000
 1. GDT        6fff0200 00000200
 2. IRQ TABLE  6fff0400 00001000
 3. SMP TABLE  6fff1400 00001000
 4. ACPI       6fff2400 0000b400
 5. SMBIOS     6fffd800 00000800
 6. COREBOOT   6fffe000 00002000
Searching for fallback/payload
Check cmos_layout.bin
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Got a payload
Loading segment from rom address 0xfff275f8
  data (compression=1)
  New segment dstaddr 0xe7e04 memsize 0x181fc srcaddr 0xfff27630 filesize 0xc1f9
  (cleaned up) New segment addr 0xe7e04 size 0x181fc offset 0xfff27630 filesize 0xc1f9
Loading segment from rom address 0xfff27614
  Entry Point 0x00000000
Loading Segment: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c1f9
lb: [0x0000000000200000, 0x0000000000330000)
Post relocation: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c1f9
using LZMA
[ 0x000e7e04, 00100000, 0x00100000) <- fff27630
dest 000e7e04, end 00100000, bouncebuffer 6fd90000
Loaded segments
Jumping to boot code at fc8c0
entry    = 0x000fc8c0
lb_start = 0x00200000
lb_size  = 0x00130000
adjust   = 0x6fcc0000
buffer   = 0x6fd90000
     elf_boot_notes = 0x00228dcc
adjusted_boot_notes = 0x6fee8dcc
Start bios (version 1.6.3-20111218_193902-odin)
Found mainboard ASUS M4A78LT-M
Found CBFS header at 0xfffffc90
Ram Size=0x6fff0000 (0x0000000000000000 high)
Relocating init from 0x000e8450 to 0x6ffd57a0 (size 42812)
CPU Mhz=2910
Found 25 PCI devices (max PCI bus is 03)
Found 2 cpu(s) max supported 2 cpu(s)
Copying PIR from 0x6fff0400 to 0x000fdaa0
Copying MPTABLE from 0x6fff1400/6fff1410 to 0x000fd980
Copying ACPI RSDP from 0x6fff2400 to 0x000fd960
Copying SMBIOS entry point from 0x6fffd800 to 0x000fd940
Scan for VGA option rom
EHCI init on dev 00:12.2 (regs=0xd8309420)
EHCI init on dev 00:13.2 (regs=0xd8309520)
OHCI init on dev 00:14.5 (regs=0xd8308000)
Found 0 lpt ports
Found 4 serial ports
ATA controller 1 at 3020/3040/0 (irq 0 dev 88)
ATA controller 2 at 3028/3044/0 (irq 0 dev 88)
ATA controller 3 at 1f0/3f4/0 (irq 14 dev a1)
ATA controller 4 at 170/374/0 (irq 15 dev a1)
OHCI init on dev 00:13.0 (regs=0xd8306000)
OHCI init on dev 00:13.1 (regs=0xd8307000)
ata0-0: WDC WD10EARS-00Y5B1 ATA-8 Hard-Disk (931 GiBytes)
Searching bootorder for: /pci at i0cf8/*@11/drive at 0/disk at 0
DVD/CD [ata0-1: TSSTcorpCD/DVDW SH-S183L ATAPI-0 DVD/CD]
Searching bootorder for: /pci at i0cf8/*@11/drive at 0/disk at 1
Got ps2 nak (status=51)
All threads complete.
Scan for option roms
Press F12 for boot menu.

drive 0x000fd8d0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1953525168
ebda moved from 9fc00 to 9f400
Returned 65536 bytes of ZoneHigh
e820 map has 8 items:
  0: 0000000000000000 - 000000000009f400 = 1 RAM
  1: 000000000009f400 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 000000006fff0000 = 1 RAM
  4: 000000006fff0000 - 0000000080000000 = 2 RESERVED
  5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED
  6: 00000000fec00000 - 00000000fec01000 = 2 RESERVED
  7: 00000000fed00000 - 00000000fed00400 = 2 RESERVED
enter handle_19:
  NULL
Booting from DVD/CD...
Device reports MEDIUM NOT PRESENT
atapi_is_ready returned -1
Boot failed: Could not read from CDROM (code 0003)
enter handle_18:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00
-------------- next part --------------
coreboot-4.0-1914-g66ebaa9-dirty Sun Dec 18 01:45:20 CET 2011 starting...
BSP Family_Model: 00100f63 
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00 
cpu_init_detectedx = 00000000 
microcode: equivalent rev id  = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6  success

cpuSetAMDMSR  done
Enter amd_ht_init()
AMD_CB_EventNotify()
 event class: 02
 event: 2005
 data:  05  00  00  00  01 
AMD_CB_EventNotify()
 event class: 05
 event: 2006
 data:  04  00  00  ff 
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00 
  F3x80: e600e681 
  F3x84: 80e641e6 
  F3xD4: c8810f26 
  F3xD8: 03001016 
  F3xDC: 0000532e 
core0 started: 
start_other_cores()
init node: 00  cores: 01 
Start other core - nodeid: 00  cores: 01
started ap apicid:  corex:  --- { APICID = 01 NODEID = 00 COREID = 01} ---
* AmPi cr0o1code: equivalent rev id  = 0x1043, current patch id = 0x00000000
otartmeidcr
 code: patch id to apply = 0x010000b6
m
 icrocode: updated to patch id = 0x010000b6  success

rscp7u80S_eetAaMrDlyM_SsRe tup()
fam10 d_oopntei
mization()
irnist78_0f_idpvoir_di_nstiatg
e2 apicid: 01
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From r.marek at assembler.cz  Mon Dec 19 00:12:12 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 19 Dec 2011 00:12:12 +0100
Subject: [coreboot] Asus M4A78LT-M status
In-Reply-To: <1468547.iUyCbOd7pl@odin>
References: <1468547.iUyCbOd7pl@odin>
Message-ID: <4EEE734C.6050205@assembler.cz>

Good night time. I only skimed though but if your PCIe cards are not working 
then PCIe resets are wrong. You need to find out what GPIO they are and fix 
mainboard.c functions.

There is AGESA callback for that so it could be read out from orig bios bootblock.

Try GPM8/9 as in mine asrock board (asrock/939....)

Thanks
Rudolf


From gerrit at coreboot.org  Mon Dec 19 05:32:09 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Mon, 19 Dec 2011 05:32:09 +0100
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix multipleVGA
	cards resource conflict on Windows
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
Message-ID: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/489

-gerrit

commit 6709bdd2da765178084de3e72ec7d8ce36f2ec37
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Mon Dec 19 13:13:34 2011 +0800

    Fix multipleVGA cards resource conflict on Windows
    
    If multiple VGA-compatible legacy graphic cards decode the IO range
    3B0-3DF and MEM range A00000-BFFFF, Windows 7 complain a resource conflict,
    so only one VGA card can works at the same time.
    
    By disable the IO & MEM decode of the second vga graphic device,
    this patch resolved the resource conflict in windows7, multiple
    vga-compatible graphic cards can work together in windows7.
    
    There is a discuss in coreboot mail list before,
    please reference thread: "how to prevent legacy resource conflictwith   multipleVGA cards"
    
    Linux using VGA Arbiter module(vgaarb) to resolve this resource conflict,
    Please see the following linux dmesg log, more information can be found in
    Linux source dir Documentation/vgaarbiter.txt.
    But it seems that windows don't dealwith this conflict.
    ~# dmesg | grep -i vgaarb
    [    0.774076] vgaarb: device added: PCI:0000:00:01.0,decodes=io+mem,owns=io+mem
    [    0.776065] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,l
    [    0.780051] vgaarb: loaded
    [    0.784049] vgaarb: bridge control possible 0000:01:00.0
    [    0.788050] vgaarb: bridge control possible 0000:00:01.0
    
    For the second legacy graphic device, coreboot already disabled the
    IO and MEM decode in function set_vga_bridge_bits().
    But it will be enabled again in function pci_set_resource(),
    if the second legacy vga-compatible graphic device take any IO/MEM resources.
    
    Following log printed by enable_resources() shows the problem:
    ...snip...
    PCI: 00:00.0 cmd <- 06
    PCI: 00:01.0 subsystem <- 1022/1410
    PCI: 00:01.0 cmd <- 07                <== The first graphic device
    PCI: 00:01.1 subsystem <- 1022/1410
    PCI: 00:01.1 cmd <- 02
    PCI: 00:02.0 bridge ctrl <- 0003
    PCI: 00:02.0 cmd <- 07
    ...snip...
    PCI: 01:00.0 cmd <- 03                <== The second graphic device
    PCI: 01:00.1 cmd <- 02
    PCI: 02:00.0 cmd <- 02
    PCI: 03:00.0 cmd <- 03
    done.
    ...snip...
    
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d
---
 src/devices/pci_device.c |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 2ccb38a..0ba7fd2 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -494,6 +494,21 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
 			dev->command |= PCI_COMMAND_IO;
 		if (resource->flags & IORESOURCE_PCI_BRIDGE)
 			dev->command |= PCI_COMMAND_MASTER;
+
+		/* It isn't safe to enable multiple VGA cards.
+		 * Windows will report resource conflict when more than one
+		 * VGA-compatible legacy graphic card in the system.
+		 */
+#if CONFIG_VGA_BRIDGE_SETUP == 1
+		extern device_t vga_pri;
+		if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
+			(dev != vga_pri)) {
+			if (((vga_pri->class >> 8) == PCI_CLASS_DISPLAY_VGA) &&
+				((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) {
+				dev->command &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+			}
+		}
+#endif
 	}
 
 	/* Get the base address. */


From rminnich at gmail.com  Mon Dec 19 06:06:42 2011
From: rminnich at gmail.com (ron minnich)
Date: Mon, 19 Dec 2011 00:06:42 -0500
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
 multipleVGA cards resource conflict on Windows
In-Reply-To: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
	<I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>
Message-ID: <CAP6exY+=rLiwFHqouSKLMAmM=3g+sbgP3MEQJCtWhdEXpN+A4A@mail.gmail.com>

> + ? ? ? ? ? ? ? /* It isn't safe to enable multiple VGA cards.
> + ? ? ? ? ? ? ? ?* Windows will report resource conflict when more than one
> + ? ? ? ? ? ? ? ?* VGA-compatible legacy graphic card in the system.
> + ? ? ? ? ? ? ? ?*/
> +#if CONFIG_VGA_BRIDGE_SETUP == 1
> + ? ? ? ? ? ? ? extern device_t vga_pri;
> + ? ? ? ? ? ? ? if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
> + ? ? ? ? ? ? ? ? ? ? ? (dev != vga_pri)) {
> + ? ? ? ? ? ? ? ? ? ? ? if (((vga_pri->class >> 8) == PCI_CLASS_DISPLAY_VGA) &&
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dev->command &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
> + ? ? ? ? ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? }
> +#endif

What do Linux or *BSD do in the same situation? Do they handle it cleanly?

thanks

ron


From Kerry.She at amd.com  Mon Dec 19 07:01:58 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Mon, 19 Dec 2011 14:01:58 +0800
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
	multipleVGA cards resource conflict on Windows
In-Reply-To: <CAP6exY+=rLiwFHqouSKLMAmM=3g+sbgP3MEQJCtWhdEXpN+A4A@mail.gmail.com>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org><I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>
	<CAP6exY+=rLiwFHqouSKLMAmM=3g+sbgP3MEQJCtWhdEXpN+A4A@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A4108982B85@sbjgexmb1.amd.com>

Hello, Ron

> -----Original Message-----
> From: coreboot-bounces+kerry.she=amd.com at coreboot.org [mailto:coreboot-
> bounces+kerry.she=amd.com at coreboot.org] On Behalf Of ron minnich
> Sent: Monday, December 19, 2011 1:07 PM
> To: Kerry Sheh
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] Patch set updated for coreboot: 6709bdd Fix
> multipleVGA cards resource conflict on Windows
> 
> > + ? ? ? ? ? ? ? /* It isn't safe to enable multiple VGA cards.
> > + ? ? ? ? ? ? ? ?* Windows will report resource conflict when more than
> one
> > + ? ? ? ? ? ? ? ?* VGA-compatible legacy graphic card in the system.
> > + ? ? ? ? ? ? ? ?*/
> > +#if CONFIG_VGA_BRIDGE_SETUP == 1
> > + ? ? ? ? ? ? ? extern device_t vga_pri;
> > + ? ? ? ? ? ? ? if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
> > + ? ? ? ? ? ? ? ? ? ? ? (dev != vga_pri)) {
> > + ? ? ? ? ? ? ? ? ? ? ? if (((vga_pri->class >> 8) ==
> PCI_CLASS_DISPLAY_VGA) &&
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ((dev->class >> 8) ==
> PCI_CLASS_DISPLAY_VGA)) {
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dev->command &= ~(PCI_COMMAND_IO |
> PCI_COMMAND_MEMORY);
> > + ? ? ? ? ? ? ? ? ? ? ? }
> > + ? ? ? ? ? ? ? }
> > +#endif
> 
> What do Linux or *BSD do in the same situation? Do they handle it cleanly?
Linux VGA Arbiter module(vgaarb) will handle this explicitly.
So dual vga card would works together, even coreboot not disable IO& MEM decoding on the second vga card.
thanks

 
> thanks
> 
> ron
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




From quest1914 at gmail.com  Mon Dec 19 08:20:31 2011
From: quest1914 at gmail.com (Anthony Crenshaw)
Date: Sun, 18 Dec 2011 23:20:31 -0800
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
 multipleVGA cards resource conflict on Windows
In-Reply-To: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
	<I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>
Message-ID: <CACABk8SpsG_wfw3QYgRMhgcD+GMVNCOCFqwGiCZxy63Cw_0Lyg@mail.gmail.com>

Hi

I'd like to ask you how long have you been making patch's
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From gregg.drwho8 at gmail.com  Mon Dec 19 09:13:59 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Mon, 19 Dec 2011 03:13:59 -0500
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
 multipleVGA cards resource conflict on Windows
In-Reply-To: <CACABk8SpsG_wfw3QYgRMhgcD+GMVNCOCFqwGiCZxy63Cw_0Lyg@mail.gmail.com>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
	<I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>
	<CACABk8SpsG_wfw3QYgRMhgcD+GMVNCOCFqwGiCZxy63Cw_0Lyg@mail.gmail.com>
Message-ID: <CAC5iaNHneFwo7FnzQfkpuZTRcCGyheQR_Gn9TTh5Gd2SuNKYeg@mail.gmail.com>

On Mon, Dec 19, 2011 at 2:20 AM, Anthony Crenshaw <quest1914 at gmail.com> wrote:
> Hi
>
> I'd like to ask you how long have you been making patch's

Hello!
An interesting question. Ron practically started the original project.
(Which is where I come in.) and Kerry started contributing to it,
fairly recently. Say about one to two years now?  What, say?

This series is fairly interesting, given the fact that the regular
BIOS that the majority of systems come with, have no clear idea as to
how to work with more then one video card.
-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."


From quest1914 at gmail.com  Mon Dec 19 11:03:57 2011
From: quest1914 at gmail.com (Anthony Crenshaw)
Date: Mon, 19 Dec 2011 02:03:57 -0800
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
 multipleVGA cards resource conflict on Windows
In-Reply-To: <CAC5iaNHneFwo7FnzQfkpuZTRcCGyheQR_Gn9TTh5Gd2SuNKYeg@mail.gmail.com>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
	<I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>
	<CACABk8SpsG_wfw3QYgRMhgcD+GMVNCOCFqwGiCZxy63Cw_0Lyg@mail.gmail.com>
	<CAC5iaNHneFwo7FnzQfkpuZTRcCGyheQR_Gn9TTh5Gd2SuNKYeg@mail.gmail.com>
Message-ID: <CACABk8SSYUhK+bVv04L93_ACs2q_we=rU5NcxdcSZDF-ukAmfg@mail.gmail.com>

Have you tried svga_HDMI.exe
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From Kerry.She at amd.com  Mon Dec 19 11:50:32 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Mon, 19 Dec 2011 18:50:32 +0800
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
	multipleVGA cards resource conflict on Windows
In-Reply-To: <CACABk8SSYUhK+bVv04L93_ACs2q_we=rU5NcxdcSZDF-ukAmfg@mail.gmail.com>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org><I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org><CACABk8SpsG_wfw3QYgRMhgcD+GMVNCOCFqwGiCZxy63Cw_0Lyg@mail.gmail.com><CAC5iaNHneFwo7FnzQfkpuZTRcCGyheQR_Gn9TTh5Gd2SuNKYeg@mail.gmail.com>
	<CACABk8SSYUhK+bVv04L93_ACs2q_we=rU5NcxdcSZDF-ukAmfg@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A4108A24EFA@sbjgexmb1.amd.com>

Hello, Anthony

 

From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Anthony Crenshaw
Sent: Monday, December 19, 2011 6:04 PM
To: Gregg Levine
Cc: coreboot
Subject: Re: [coreboot] Patch set updated for coreboot: 6709bdd Fix
multipleVGA cards resource conflict on Windows

 

Have you tried svga_HDMI.exe 

I don't think so.

I don't know what's "vga_HDMI.exe" is,  can you drop me some more
information?

thanks

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From Kerry.She at amd.com  Mon Dec 19 12:40:52 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Mon, 19 Dec 2011 19:40:52 +0800
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
	multipleVGA cards resource conflict on Windows
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org><I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org><CACABk8SpsG_wfw3QYgRMhgcD+GMVNCOCFqwGiCZxy63Cw_0Lyg@mail.gmail.com><CAC5iaNHneFwo7FnzQfkpuZTRcCGyheQR_Gn9TTh5Gd2SuNKYeg@mail.gmail.com>
	<CACABk8SSYUhK+bVv04L93_ACs2q_we=rU5NcxdcSZDF-ukAmfg@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A4108A24F23@sbjgexmb1.amd.com>

Hello, Anthony

 

From: She, Kerry 
Sent: Monday, December 19, 2011 6:51 PM
To: 'Anthony Crenshaw'; 'Gregg Levine'
Cc: 'coreboot'
Subject: Re: [coreboot] Patch set updated for coreboot: 6709bdd Fix
multipleVGA cards resource conflict on Windows

 

Hello, Anthony

 

From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Anthony Crenshaw
Sent: Monday, December 19, 2011 6:04 PM
To: Gregg Levine
Cc: coreboot
Subject: Re: [coreboot] Patch set updated for coreboot: 6709bdd Fix
multipleVGA cards resource conflict on Windows

 

Have you tried svga_HDMI.exe 

I don't think so.

I don't know what's "vga_HDMI.exe" is,  can you drop me some more
information?

Thanks

 

I have to mention that I only verified 2 amd graphic devices.

Hardware: 2 AMD graphic devices(one is an internal graphic device in the
APU chip, other one is external PCIE graphic card ).

OS: Debian 5(Lenny) and Windows 7.

2 graphic device works at the same time with no resource conflict,

Crossfire works as well with the ATI proprietary graphic driver
installed.

Thanks

Kerry

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From svn at coreboot.org  Mon Dec 19 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 19 Dec 2011 16:00:02 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1Rceh8-0001aE-76@ra.coresystems.de>

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From rminnich at gmail.com  Mon Dec 19 18:02:54 2011
From: rminnich at gmail.com (ron minnich)
Date: Mon, 19 Dec 2011 09:02:54 -0800
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
 multipleVGA cards resource conflict on Windows
In-Reply-To: <F53A09371FB723428826B442A4B20A4108982B85@sbjgexmb1.amd.com>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
	<I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>
	<CAP6exY+=rLiwFHqouSKLMAmM=3g+sbgP3MEQJCtWhdEXpN+A4A@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4108982B85@sbjgexmb1.amd.com>
Message-ID: <CAP6exYKRz0MRawXXPZjeG4rm-GXLM-E74p_+jwwL_+2S--ZLUQ@mail.gmail.com>

On Sun, Dec 18, 2011 at 10:01 PM, She, Kerry <Kerry.She at amd.com> wrote:
> Hello, Ron
>
>> I asked:
>> What do Linux or *BSD do in the same situation? Do they handle it cleanly?
> Linux VGA Arbiter module(vgaarb) will handle this explicitly.
> So dual vga card would works together, even coreboot not disable IO& MEM decoding on the second vga card.

OK, then,  my concern about this patch is that you are making a
compile-time decision in  coreboot to fix a problem with one operating
system (Windows) that will impact other operating systems that don't
have the problem.

I wonder if a better way to manage this is via a CMOS (aka NVRAM)
setting. I kind of hate to limit coreboot because Windows is limited.
But I'm a n00b in a sense, having just come back onto this project, so
I'm happy to be told I'm wrong :-)

ron
p.s. For those who don't know me, I've been out of coreboot for 2
years, having been heavily involved from 1999 (when I started
LinuxBIOS) to 2009. Changing circumstances mean I get to work on it
again, which is nice.


From idl0r at qasl.de  Mon Dec 19 18:31:10 2011
From: idl0r at qasl.de (Christian Ruppert)
Date: Mon, 19 Dec 2011 18:31:10 +0100
Subject: [coreboot] Asus M4A78LT-M status
In-Reply-To: <1468547.iUyCbOd7pl@odin>
References: <1468547.iUyCbOd7pl@odin>
Message-ID: <3913957.EPR7F00mhe@odin>

Ok, little status update...

On Sunday 18 December 2011 23:03:50 Christian Ruppert wrote:
> Hi guys,
> 
> I currently try to get coreboot working on my "Asus M4A78LT-M".
> Using the M4A785T-M [1] as template works fine so far as the hardware is
> almost equal but there are a few issues:
> 
> a)
> My RAM sticks [2] (tried both separate) doesn't work (see serial-ram-
> fail.txt).
> It is present but not valid, it seems the CRC check fails in
> src/northbridge/amd/amdmct/mct_ddr3/mct_d.c and I have no idea why...
> 
> My other RAM sticks [3] (only one tested) seem to work (see serial-ram-
> works.txt)
> 
> Do you guys have any ideas why the other sticks do not work?
> 
> b) Neither the NVIDIA (ZOTAC GeForce 210 Synergy Edition 512MB) PCIe card
> nor the on-board ATI Radeon HD 3000 works.
> I tried to extract the VGA bios of the on-board card by using the
> bios_extract script mentioned at [4] as well as Peter's shell command
> mentioned at [5]. bios_extract doesn't seem to find the VGA bios, at least
> the PCI IDs doesn't match.
> I get amipci_1002_4392.rom, amipci_1002_FFF1.rom and amipci_1002_FFF2.rom
> but the PCI ID of the on-board ATI card is: 1002:9616.
> So I tried Peter's command and that seems to work at least partially. I do
> get some strange stuff on the screen incl. a flashing cursor but that's
> it...
> 
> So I'd like to know how to get the PCIe card working at least (which is
> totally enough for me or resp. exactly what I want).
> The on-board one would be only interesting for my Wiki article, so for
> others.
> 

Now (thank GRUB2) that I am able to boot with coreboot/SeaBIOS I noticed that 
the NVIDIA PCIe card is *not* listed by lspci at all. The onboard card is 
listed.

> c)
> Not sure if I just misunderstood something.. I have GRUB 1 / legacy
> installed on my disk and SeaBIOS tries to load GRUB but then it freezes.
> From what I've read only GRUB 2 is supported as *payload*. Does it also
> apply to GRUB on a disk?
> 

So #c has been solved. Booting with GRUB2 works fine. :)

> d)
> Using the microcode update stuff results into some strange boot issues (see
> serial-microcode_fail.txt, note the "rscp7u80S_eetAaMrDlyM_SsRe tup()") and
> freezes.
> Is it a known issue? Any workarounds?
> Even "Juhe" (the author of the M4A785T-M [1] article mentioned that..
> In my case it is a AMD Athlon II X2 245e.
> 
> 
> So as you can see in serial-ram-works.txt it's almost working. I guess it'll
> boot "fine" if you guys are able to help me with the issues above. If you
> (like me) prefer IRC then just poke me (idl0r) and I'll post any
> successfully results either here or on the Wiki article later.
> 
> [1] http://www.coreboot.org/ASUS_M4A785T-M
> [2] http://www.gskill.com/products.php?index=223
> [3] http://www.gskill.com/products.php?index=243
> [4]
> http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor
> _bios_image [5]
> http://www.coreboot.org/VGA_support#Extracting_from_the_system_.28if_everyth
> ing_else_fails.29

Unfortunately there are other issues that I noticed during the first boot.

e)
The processor P-States are somewhat incomplete.
vendor BIOS:
# dmesg|grep power
[    1.901172] powernow-k8: Found 1 AMD Athlon(tm) II X2 245e Processor (2 cpu 
cores) (version 2.20.00)
[    1.911453] powernow-k8:    0 : pstate 0 (2900 MHz)
[    1.917517] powernow-k8:    1 : pstate 1 (2100 MHz)
[    1.923502] powernow-k8:    2 : pstate 2 (1500 MHz)
[    1.929473] powernow-k8:    3 : pstate 3 (800 MHz)

coreboot:
# grep powernow dmesg.coreboot
[    1.846464] powernow-k8: Found 1 AMD Athlon(tm) II X2 245e Processor (2 cpu 
cores) (version 2.20.00)
[    1.855605] powernow-k8:    0 : pstate 0 (2900 MHz)
[    1.860482] powernow-k8:    1 : pstate 1 (2100 MHz)

f)
As mentioned by "Juhe" the snd-hda-intel module crashes thus a kernel panic...
See attachment snd-hda-intel-panic.txt.

I also attached the dmesg and dmidecode output of the first *sucessfull* boot.

-- 
Regards,
Christian Ruppert
-------------- next part --------------
# modprobe snd-hda-intel
[  298.777045] BUG: unable to handle kernel NULL pointer dereference at 0000000000000128
[  298.778025] IP: [<ffffffffa02e4201>] snd_hda_queue_unsol_event+0x1/0x50 [snd_hda_codec]
[  298.790997] PGD 6c1db067 PUD 6c15f067 PMD 0 
[  298.790997] Oops: 0000 [#1] SMP 
[  298.790997] CPU 1 
[  298.790997] Modules linked in: snd_hda_intel(+) snd_hda_codec snd_hwdep snd_pcm snd_page_alloc snd_seq snd_timer snd_seq_device snd soundcore usbhid rc_imon_pad imon ir_lirc_codec lirc_dev ir_mce_kbd_decoder ir_sony_decoder ir_jvc_dec3
[  298.826866] 
[  298.826866] Pid: 0, comm: kworker/0:0 Tainted: P            3.1.5-gentoo #8 ASUS M4A78LT-M
[  298.826866] RIP: 0010:[<ffffffffa02e4201>]  [<ffffffffa02e4201>] snd_hda_queue_unsol_event+0x1/0x50 [snd_hda_codec]
[  298.826866] RSP: 0018:ffff88006fd03e38  EFLAGS: 00010002
[  298.826866] RAX: 0000000000000002 RBX: ffff88006cbc4000 RCX: ffff88006abd6800
[  298.826866] RDX: 0000000000000012 RSI: 00000000ffffffff RDI: 0000000000000000
[  298.826866] RBP: ffff88006fd03e68 R08: 0000000000000001 R09: 0000000000000008
[  298.826866] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000001
[  298.826866] R13: 0000000000000000 R14: 00000000c0000000 R15: 000000000000001c
[  298.826866] FS:  00007eff504f2700(0000) GS:ffff88006fd00000(0000) knlGS:0000000000000000
[  298.826866] CS:  0010 DS: 0000 ES: 0000 CR0: 000000008005003b
[  298.826866] CR2: 0000000000000128 CR3: 0000000061a8c000 CR4: 00000000000006e0
[  298.826866] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[  298.826866] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
[  298.826866] Process kworker/0:0 (pid: 0, threadinfo ffff88006d498000, task ffff88006d44c100)
[  298.826866] Stack:
[  298.826866]  ffff88006fd03e68 ffffffffa02f87fc 0000000000000286 ffff88006cbc7780
[  298.826866]  0000000000000008 ffff88006cbc4000 ffff88006fd03eb8 ffffffffa02f88f7
[  298.826866]  ffff88006cbc4218 ffff88006cbc4044 0000000000000000 ffff88006c344500
[  298.826866] Call Trace:
[  298.826866]  <IRQ> 
[  298.826866]  [<ffffffffa02f87fc>] ? azx_update_rirb+0xbc/0xe0 [snd_hda_intel]
[  298.826866]  [<ffffffffa02f88f7>] azx_interrupt+0xd7/0x190 [snd_hda_intel]
[  298.826866]  [<ffffffff81093d85>] handle_irq_event_percpu+0x55/0x1f0
[  298.826866]  [<ffffffff81093f57>] handle_irq_event+0x37/0x60
[  298.826866]  [<ffffffff81096514>] handle_fasteoi_irq+0x54/0xd0
[  298.826866]  [<ffffffff8100404d>] handle_irq+0x1d/0x30
[  298.826866]  [<ffffffff81003ce8>] do_IRQ+0x58/0xe0
[  298.826866]  [<ffffffff8142ea2b>] common_interrupt+0x6b/0x6b
[  298.826866]  <EOI> 
[  298.826866]  [<ffffffff8106fbd1>] ? tick_nohz_stop_sched_tick+0x281/0x3c0
[  298.826866]  [<ffffffff81000ac9>] cpu_idle+0x79/0x100
[  298.826866]  [<ffffffff8142770a>] start_secondary+0x23c/0x243
[  298.826866] Code: c4 48 8d 58 f0 74 18 0f 1f 00 48 89 df e8 a8 6c 00 00 48 8b 43 10 49 39 c4 48 8d 58 f0 75 eb 5b 31 c0 41 5c c9 c3 0f 1f 40 00 55 
[  298.826866]  8b 87 28 01 00 00 48 89 e5 48 85 c0 74 34 8b 88 04 02 00 00 
[  298.826866] RIP  [<ffffffffa02e4201>] snd_hda_queue_unsol_event+0x1/0x50 [snd_hda_codec]
[  298.826866]  RSP <ffff88006fd03e38>
[  298.826866] CR2: 0000000000000128
[  298.826866] ---[ end trace 9dd4667e4fe161ce ]---
[  298.826866] Kernel panic - not syncing: Fatal exception in interrupt
[  298.826866] Pid: 0, comm: kworker/0:0 Tainted: P      D     3.1.5-gentoo #8
[  298.826866] Call Trace:
[  298.826866]  <IRQ>  [<ffffffff8142bdd6>] panic+0x8c/0x193
[  298.826866]  [<ffffffff81005639>] oops_end+0x99/0xa0
[  298.826866]  [<ffffffff81024a30>] no_context+0xf0/0x260
[  298.826866]  [<ffffffff81024cbd>] __bad_area_nosemaphore+0x11d/0x200
[  298.826866]  [<ffffffff81024dae>] bad_area_nosemaphore+0xe/0x10
[  298.826866]  [<ffffffff810252dc>] do_page_fault+0x2ac/0x430
[  298.826866]  [<ffffffff81037429>] ? load_balance+0x99/0x780
[  298.826866]  [<ffffffff81065e7d>] ? sched_clock_local+0x1d/0x90
[  298.826866]  [<ffffffff8142ec2f>] page_fault+0x1f/0x30
[  298.826866]  [<ffffffffa02e4201>] ? snd_hda_queue_unsol_event+0x1/0x50 [snd_hda_codec]
[  298.826866]  [<ffffffffa02f87fc>] ? azx_update_rirb+0xbc/0xe0 [snd_hda_intel]
[  298.826866]  [<ffffffffa02f88f7>] azx_interrupt+0xd7/0x190 [snd_hda_intel]
[  298.826866]  [<ffffffff81093d85>] handle_irq_event_percpu+0x55/0x1f0
[  298.826866]  [<ffffffff81093f57>] handle_irq_event+0x37/0x60
[  298.826866]  [<ffffffff81096514>] handle_fasteoi_irq+0x54/0xd0
[  298.826866]  [<ffffffff8100404d>] handle_irq+0x1d/0x30
[  298.826866]  [<ffffffff81003ce8>] do_IRQ+0x58/0xe0
[  299.209351]  [<ffffffff8142ea2b>] common_interrupt+0x6b/0x6b
[  299.209351]  <EOI>  [<ffffffff8106fbd1>] ? tick_nohz_stop_sched_tick+0x281/0x3c0
[  299.209351]  [<ffffffff81000ac9>] cpu_idle+0x79/0x100
[  299.209351]  [<ffffffff8142770a>] start_secondary+0x23c/0x243
-------------- next part --------------
# dmidecode 2.10
SMBIOS 2.7 present.
6 structures occupying 250 bytes.
Table at 0x6FFFD820.

Handle 0x0000, DMI type 0, 24 bytes
BIOS Information
	Vendor: coreboot
	Version: 4.0-1914-g66ebaa9-dirty
	Release Date: 12/19/2011
	ROM Size: 1024 kB
	Characteristics:
		PCI is supported
		PC Card (PCMCIA) is supported
		BIOS is upgradeable
		Selectable boot is supported
		ACPI is supported
		Targeted content distribution is supported
	BIOS Revision: 4.0
	Firmware Revision: 0.0

Handle 0x0001, DMI type 1, 27 bytes
System Information
	Manufacturer: ASUS
	Product Name: M4A78LT-M
	Version: Not Specified
	Serial Number: Not Specified
	UUID: Not Settable
	Wake-up Type: Reserved
	SKU Number: Not Specified
	Family: Not Specified

Handle 0x0002, DMI type 3, 21 bytes
Chassis Information
	Manufacturer: ASUS
	Type: Desktop
	Lock: Not Present
	Version: Not Specified
	Serial Number: Not Specified
	Asset Tag: Not Specified
	Boot-up State: Safe
	Power Supply State: Safe
	Thermal State: Safe
	Security Status: None
	OEM Information: 0x00000000
	Height: Unspecified
	Number Of Power Cords: Unspecified
	Contained Elements: 0

Handle 0x0003, DMI type 4, 42 bytes
Processor Information
	Socket Designation: Not Specified
	Type: Central Processor
	Family: Pentium Pro
	Manufacturer: AuthenticAMD
	ID: 63 0F 10 00 FF FB 8B 17
	Signature: Type 0, Family 16, Model 6, Stepping 3
	Flags:
		FPU (Floating-point unit on-chip)
		VME (Virtual mode extension)
		DE (Debugging extension)
		PSE (Page size extension)
		TSC (Time stamp counter)
		MSR (Model specific registers)
		PAE (Physical address extension)
		MCE (Machine check exception)
		CX8 (CMPXCHG8 instruction supported)
		APIC (On-chip APIC hardware supported)
		SEP (Fast system call)
		MTRR (Memory type range registers)
		PGE (Page global enable)
		MCA (Machine check architecture)
		CMOV (Conditional move instruction supported)
		PAT (Page attribute table)
		PSE-36 (36-bit page size extension)
		CLFSH (CLFLUSH instruction supported)
		MMX (MMX technology supported)
		FXSR (Fast floating-point save and restore)
		SSE (Streaming SIMD extensions)
		SSE2 (Streaming SIMD extensions 2)
		HTT (Hyper-threading technology)
	Version: AMD Athlon(tm) II X2 245e Processor
	Voltage: Unknown
	External Clock: Unknown
	Max Speed: Unknown
	Current Speed: Unknown
	Status: Unpopulated
	Upgrade: Other
	L1 Cache Handle: Not Provided
	L2 Cache Handle: Not Provided
	L3 Cache Handle: Not Provided
	Serial Number: Not Specified
	Asset Tag: Not Specified
	Part Number: Not Specified
	Core Count: 2
	Characteristics: None

Handle 0x0004, DMI type 32, 11 bytes
System Boot Information
	Status: No errors detected

Handle 0x0005, DMI type 127, 4 bytes
End Of Table

-------------- next part --------------
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 3.1.5-gentoo (root at urd) (gcc version 4.5.3 (Gentoo 4.5.3-r1 p1.0, pie-0.4.5) ) #8 SMP Mon Dec 12 22:01:19 CET 2011
[    0.000000] Command line: BOOT_IMAGE=/kernel-3.1.5-gentoo root=/dev/sda3 ro video=uvesafb:1280x800-32,mtrr:3,ywrap console=ttyS0,115200 console=tty0
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009f000 (usable)
[    0.000000]  BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved)
[    0.000000]  BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
[    0.000000]  BIOS-e820: 0000000000100000 - 000000006fff0000 (usable)
[    0.000000]  BIOS-e820: 000000006fff0000 - 0000000080000000 (reserved)
[    0.000000]  BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved)
[    0.000000]  BIOS-e820: 00000000fec00000 - 00000000fec01000 (reserved)
[    0.000000]  BIOS-e820: 00000000fed00000 - 00000000fed00400 (reserved)
[    0.000000] NX (Execute Disable) protection: active
[    0.000000] DMI present.
[    0.000000] DMI: ASUS M4A78LT-M, BIOS 4.0-1914-g66ebaa9-dirty 12/19/2011
[    0.000000] e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved)
[    0.000000] e820 remove range: 00000000000a0000 - 0000000000100000 (usable)
[    0.000000] No AGP bridge found
[    0.000000] last_pfn = 0x6fff0 max_arch_pfn = 0x400000000
[    0.000000] MTRR default type: uncachable
[    0.000000] MTRR fixed ranges enabled:
[    0.000000]   00000-9FFFF write-back
[    0.000000]   A0000-BFFFF uncachable
[    0.000000]   C0000-FFFFF write-back
[    0.000000] MTRR variable ranges enabled:
[    0.000000]   0 base 000000000000 mask FFFF80000000 write-back
[    0.000000]   1 base 000070000000 mask FFFFF0000000 uncachable
[    0.000000]   2 disabled
[    0.000000]   3 disabled
[    0.000000]   4 disabled
[    0.000000]   5 disabled
[    0.000000]   6 disabled
[    0.000000]   7 disabled
[    0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
[    0.000000] initial memory mapped : 0 - 20000000
[    0.000000] Base memory trampoline at [ffff88000009a000] 9a000 size 20480
[    0.000000] Using GB pages for direct mapping
[    0.000000] init_memory_mapping: 0000000000000000-000000006fff0000
[    0.000000]  0000000000 - 0040000000 page 1G
[    0.000000]  0040000000 - 006fe00000 page 2M
[    0.000000]  006fe00000 - 006fff0000 page 4k
[    0.000000] kernel direct mapping tables up to 6fff0000 @ 1fffd000-20000000
[    0.000000] ACPI: RSDP 00000000000fd960 00014 (v00 CORE  )
[    0.000000] ACPI: RSDT 000000006fff2424 0003C (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: HPET 000000006fff24c8 00038 (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: APIC 000000006fff2500 0005C (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: SRAT 000000006fff2560 000A0 (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: SLIT 000000006fff2600 0002D (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: SSDT 000000006fff2630 00635 (v01 AMD-FA AMD-ACPI 06040000 INTL 20110922)
[    0.000000] ACPI: FACP 000000006fff5638 000F4 (v03 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: DSDT 000000006fff2c68 0298C (v02 ASUS   M4A78LT- 00010001 INTL 20110922)
[    0.000000] ACPI: FACS 000000006fff55f8 00040
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000]  [ffffea0000000000-ffffea0001bfffff] PMD -> [ffff88006da00000-ffff88006f5fffff] on node 0
[    0.000000] Zone PFN ranges:
[    0.000000]   DMA      0x00000010 -> 0x00001000
[    0.000000]   DMA32    0x00001000 -> 0x00100000
[    0.000000]   Normal   empty
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[2] active PFN ranges
[    0.000000]     0: 0x00000010 -> 0x0000009f
[    0.000000]     0: 0x00000100 -> 0x0006fff0
[    0.000000] On node 0 totalpages: 458623
[    0.000000]   DMA zone: 64 pages used for memmap
[    0.000000]   DMA zone: 5 pages reserved
[    0.000000]   DMA zone: 3914 pages, LIFO batch:0
[    0.000000]   DMA32 zone: 7104 pages used for memmap
[    0.000000]   DMA32 zone: 447536 pages, LIFO batch:31
[    0.000000] ACPI: PM-Timer IO Port: 0x818
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
[    0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
[    0.000000] IOAPIC[0]: apic_id 2, version 33, address 0xfec00000, GSI 0-23
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
[    0.000000] ACPI: IRQ0 used by override.
[    0.000000] ACPI: IRQ2 used by override.
[    0.000000] ACPI: IRQ9 used by override.
[    0.000000] Using ACPI (MADT) for SMP configuration information
[    0.000000] ACPI: HPET id: 0x102282a0 base: 0xfed00000
[    0.000000] SMP: Allowing 2 CPUs, 0 hotplug CPUs
[    0.000000] nr_irqs_gsi: 40
[    0.000000] Allocating PCI resources starting at 80000000 (gap: 80000000:60000000)
[    0.000000] setup_percpu: NR_CPUS:5 nr_cpumask_bits:5 nr_cpu_ids:2 nr_node_ids:1
[    0.000000] PERCPU: Embedded 25 pages/cpu @ffff88006fc00000 s73280 r8192 d20928 u1048576
[    0.000000] pcpu-alloc: s73280 r8192 d20928 u1048576 alloc=1*2097152
[    0.000000] pcpu-alloc: [0] 0 1 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 451450
[    0.000000] Kernel command line: BOOT_IMAGE=/kernel-3.1.5-gentoo root=/dev/sda3 ro video=uvesafb:1280x800-32,mtrr:3,ywrap console=ttyS0,115200 console=tty0
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.000000] Checking aperture...
[    0.000000] No AGP bridge found
[    0.000000] Node 0: aperture @ dc000000 size 64 MB
[    0.000000] Memory: 1794872k/1834944k available (4299k kernel code, 452k absent, 39620k reserved, 1909k data, 572k init)
[    0.000000] SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Hierarchical RCU implementation.
[    0.000000] NR_IRQS:416
[    0.000000] spurious 8259A interrupt: IRQ7.
[    0.000000] Console: colour dummy device 80x25
[    0.000000] console [tty0] enabled
[    0.000000] console [ttyS0] enabled
[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 2907.439 MHz processor.
[    0.003002] Calibrating delay loop (skipped), value calculated using timer frequency.. 5814.87 BogoMIPS (lpj=2907439)
[    0.005002] pid_max: default: 32768 minimum: 301
[    0.006041] Mount-cache hash table entries: 256
[    0.007124] Initializing cgroup subsys cpuacct
[    0.008007] Initializing cgroup subsys devices
[    0.009002] Initializing cgroup subsys freezer
[    0.010019] tseg: 0000000000
[    0.010026] CPU: Physical Processor ID: 0
[    0.011002] CPU: Processor Core ID: 0
[    0.012001] mce: CPU supports 6 MCE banks
[    0.013036] ACPI: Core revision 20110623
[    0.016172] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[    0.027168] CPU0: AMD Athlon(tm) II X2 245e Processor stepping 03
[    0.030997] Performance Events: AMD PMU driver.
[    0.031999] ... version:                0
[    0.032998] ... bit width:              48
[    0.033998] ... generic registers:      4
[    0.034998] ... value mask:             0000ffffffffffff
[    0.035998] ... max period:             00007fffffffffff
[    0.036998] ... fixed-purpose events:   0
[    0.037998] ... event mask:             000000000000000f
[    0.039095] MCE: In-kernel MCE decoding enabled.
[    0.040046] Booting Node   0, Processors  #1 Ok.
[    0.041799] smpboot cpu 1: start_ip = 9a000
[    0.112993] Brought up 2 CPUs
[    0.113991] Total of 2 processors activated (11629.04 BogoMIPS).
[    0.115340] RTC time: 17:38:02, date: 12/19/11
[    0.120023] NET: Registered protocol family 16
[    0.124018] node 0 link 0: io port [1000, 3fff]
[    0.124018] TOM: 0000000080000000 aka 2048M
[    0.128990] Fam 10h mmconf [e0000000, efffffff]
[    0.128992] node 0 link 0: mmio [d4000000, d83fffff]
[    0.128994] node 0 link 0: mmio [c0000000, d01fffff]
[    0.128996] bus: [00, 03] on node 0 link 0
[    0.128998] bus: 00 index 0 [io  0x0000-0xffff]
[    0.128999] bus: 00 index 1 [mem 0xd0200000-0xdfffffff]
[    0.129001] bus: 00 index 2 [mem 0x80000000-0xd01fffff]
[    0.129002] bus: 00 index 3 [mem 0xf0000000-0xfcffffffff]
[    0.129015] Extended Config Space enabled on 1 nodes
[    0.134015] ACPI: bus type pci registered
[    0.138013] PCI: Using configuration type 1 for base access
[    0.142989] PCI: Using configuration type 1 for extended access
[    0.148999] mtrr: your CPUs had inconsistent variable MTRR settings
[    0.154986] mtrr: probably your BIOS does not setup all CPUs.
[    0.160984] mtrr: corrected configuration.
[    0.167009] bio: create slab <bio-0> at 0
[    0.172004] ACPI: Added _OSI(Module Device)
[    0.172984] ACPI: Added _OSI(Processor Device)
[    0.173983] ACPI: Added _OSI(3.0 _SCP Extensions)
[    0.174983] ACPI: Added _OSI(Processor Aggregator Device)
[    0.177230] ACPI: EC: Look up EC in DSDT
[    0.177631] ACPI: Executed 2 blocks of module-level executable AML code
[    0.180569] ACPI: Interpreter enabled
[    0.180983] ACPI: (supports S0 S1 S2 S3 S5)
[    0.183266] ACPI: BIOS offers _BFS
[    0.183981] ACPI: If "acpi.bfs=1" improves resume, please notify linux-acpi at vger.kernel.org
[    0.184981] ACPI: Using IOAPIC for interrupt routing
[    0.191024] ACPI: Power Resource [PFN0] (on)
[    0.192031] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[    0.193057] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110623/psargs-359)
[    0.195980] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS] (Node ffff88006d430d70), AE_NOT_FOUND (20110623/psparse-536)
[    0.200982] [Firmware Bug]: ACPI: no secondary bus range in _CRS
[    0.201984] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
[    0.203025] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110623/psargs-359)
[    0.206978] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS] (Node ffff88006d430d70), AE_NOT_FOUND (20110623/psparse-536)
[    0.211997] pci 0000:00:00.0: [1022:9600] type 0 class 0x000600
[    0.212081] pci 0000:00:01.0: [1022:9602] type 1 class 0x000604
[    0.212993] pci 0000:00:0a.0: [1022:9609] type 1 class 0x000604
[    0.213044] pci 0000:00:0a.0: PME# supported from D0 D3hot D3cold
[    0.213047] pci 0000:00:0a.0: PME# disabled
[    0.213088] pci 0000:00:11.0: [1002:4390] type 0 class 0x000101
[    0.213115] pci 0000:00:11.0: reg 10: [io  0x3020-0x3027]
[    0.213128] pci 0000:00:11.0: reg 14: [io  0x3040-0x3043]
[    0.213141] pci 0000:00:11.0: reg 18: [io  0x3028-0x302f]
[    0.213154] pci 0000:00:11.0: reg 1c: [io  0x3044-0x3047]
[    0.213167] pci 0000:00:11.0: reg 20: [io  0x3000-0x300f]
[    0.213180] pci 0000:00:11.0: reg 24: [mem 0xd8309000-0xd83093ff]
[    0.213208] pci 0000:00:11.0: set SATA to AHCI mode
[    0.214028] pci 0000:00:12.0: [1002:4397] type 0 class 0x000c03
[    0.214046] pci 0000:00:12.0: reg 10: [mem 0xd8304000-0xd8304fff]
[    0.214133] pci 0000:00:12.1: [1002:4398] type 0 class 0x000c03
[    0.214151] pci 0000:00:12.1: reg 10: [mem 0xd8305000-0xd8305fff]
[    0.214247] pci 0000:00:12.2: [1002:4396] type 0 class 0x000c03
[    0.214273] pci 0000:00:12.2: reg 10: [mem 0xd8309400-0xd83094ff]
[    0.214372] pci 0000:00:12.2: supports D1 D2
[    0.214374] pci 0000:00:12.2: PME# supported from D0 D1 D2 D3hot
[    0.214378] pci 0000:00:12.2: PME# disabled
[    0.214406] pci 0000:00:13.0: [1002:4397] type 0 class 0x000c03
[    0.214424] pci 0000:00:13.0: reg 10: [mem 0xd8306000-0xd8306fff]
[    0.214512] pci 0000:00:13.1: [1002:4398] type 0 class 0x000c03
[    0.214530] pci 0000:00:13.1: reg 10: [mem 0xd8307000-0xd8307fff]
[    0.214625] pci 0000:00:13.2: [1002:4396] type 0 class 0x000c03
[    0.214651] pci 0000:00:13.2: reg 10: [mem 0xd8309500-0xd83095ff]
[    0.214750] pci 0000:00:13.2: supports D1 D2
[    0.214751] pci 0000:00:13.2: PME# supported from D0 D1 D2 D3hot
[    0.214756] pci 0000:00:13.2: PME# disabled
[    0.214788] pci 0000:00:14.0: [1002:4385] type 0 class 0x000c05
[    0.215014] pci 0000:00:14.1: [1002:439c] type 0 class 0x000101
[    0.215032] pci 0000:00:14.1: reg 10: [io  0x3030-0x3037]
[    0.215045] pci 0000:00:14.1: reg 14: [io  0x3048-0x304b]
[    0.215057] pci 0000:00:14.1: reg 18: [io  0x3038-0x303f]
[    0.215070] pci 0000:00:14.1: reg 1c: [io  0x304c-0x304f]
[    0.215083] pci 0000:00:14.1: reg 20: [io  0x3010-0x301f]
[    0.215133] pci 0000:00:14.2: [1002:4383] type 0 class 0x000403
[    0.215162] pci 0000:00:14.2: reg 10: [mem 0xd8300000-0xd8303fff 64bit]
[    0.215243] pci 0000:00:14.2: PME# supported from D0 D3hot D3cold
[    0.215248] pci 0000:00:14.2: PME# disabled
[    0.215264] pci 0000:00:14.3: [1002:439d] type 0 class 0x000601
[    0.215367] pci 0000:00:14.4: [1002:4384] type 1 class 0x000604
[    0.215422] pci 0000:00:14.5: [1002:4399] type 0 class 0x000c03
[    0.215440] pci 0000:00:14.5: reg 10: [mem 0xd8308000-0xd8308fff]
[    0.215531] pci 0000:00:18.0: [1022:1200] type 0 class 0x000600
[    0.215542] pci 0000:00:18.1: [1022:1201] type 0 class 0x000600
[    0.215552] pci 0000:00:18.2: [1022:1202] type 0 class 0x000600
[    0.215562] pci 0000:00:18.3: [1022:1203] type 0 class 0x000600
[    0.215575] pci 0000:00:18.4: [1022:1204] type 0 class 0x000600
[    0.215638] pci 0000:01:05.0: [1002:9616] type 0 class 0x000300
[    0.215654] pci 0000:01:05.0: reg 10: [mem 0xc0000000-0xcfffffff pref]
[    0.215663] pci 0000:01:05.0: reg 14: [io  0x1000-0x10ff]
[    0.215671] pci 0000:01:05.0: reg 18: [mem 0xd8100000-0xd810ffff]
[    0.215692] pci 0000:01:05.0: reg 24: [mem 0xd8000000-0xd80fffff]
[    0.215718] pci 0000:01:05.0: supports D1 D2
[    0.215737] pci 0000:01:05.1: [1002:960f] type 0 class 0x000403
[    0.215753] pci 0000:01:05.1: reg 10: [mem 0xd8110000-0xd8113fff]
[    0.215812] pci 0000:01:05.1: supports D1 D2
[    0.215868] pci 0000:00:01.0: PCI bridge to [bus 01-01]
[    0.215980] pci 0000:00:01.0:   bridge window [io  0x1000-0x1fff]
[    0.215984] pci 0000:00:01.0:   bridge window [mem 0xd8000000-0xd81fffff]
[    0.215989] pci 0000:00:01.0:   bridge window [mem 0xc0000000-0xcfffffff 64bit pref]
[    0.216053] pci 0000:02:00.0: [10ec:8168] type 0 class 0x000200
[    0.216071] pci 0000:02:00.0: reg 10: [io  0x2000-0x20ff]
[    0.216100] pci 0000:02:00.0: reg 18: [mem 0xd0004000-0xd0004fff 64bit pref]
[    0.216119] pci 0000:02:00.0: reg 20: [mem 0xd0000000-0xd0003fff 64bit pref]
[    0.216132] pci 0000:02:00.0: reg 30: [mem 0xd8200000-0xd820ffff pref]
[    0.216172] pci 0000:02:00.0: supports D1 D2
[    0.216174] pci 0000:02:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.216178] pci 0000:02:00.0: PME# disabled
[    0.217989] pci 0000:00:0a.0: PCI bridge to [bus 02-02]
[    0.218980] pci 0000:00:0a.0:   bridge window [io  0x2000-0x2fff]
[    0.218984] pci 0000:00:0a.0:   bridge window [mem 0xd8200000-0xd82fffff]
[    0.218989] pci 0000:00:0a.0:   bridge window [mem 0xd0000000-0xd00fffff 64bit pref]
[    0.219026] pci 0000:03:06.0: [1822:4e35] type 0 class 0x000480
[    0.219047] pci 0000:03:06.0: reg 10: [mem 0xd0100000-0xd0100fff pref]
[    0.219193] pci 0000:00:14.4: PCI bridge to [bus 03-03] (subtractive decode)
[    0.219986] pci 0000:00:14.4:   bridge window [mem 0xd0100000-0xd01fffff pref]
[    0.220003] pci_bus 0000:00: on NUMA node 0
[    0.220005] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
[    0.220052] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.AGPB._PRT]
[    0.220071] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PBRA._PRT]
[    0.220088] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT]
[    0.220141]  pci0000:00: Requesting ACPI _OSC control (0x1d)
[    0.220977]  pci0000:00: ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d
[    0.221976] ACPI _OSC control for PCIe not granted, disabling ASPM
[    0.226994] ACPI: PCI Interrupt Link [INTA] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
[    0.232002] ACPI: PCI Interrupt Link [INTB] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
[    0.237003] ACPI: PCI Interrupt Link [INTC] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
[    0.241999] ACPI: PCI Interrupt Link [INTD] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
[    0.247197] ACPI: PCI Interrupt Link [INTE] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
[    0.252195] ACPI: PCI Interrupt Link [INTF] (IRQs 9) *0, disabled.
[    0.255195] ACPI: PCI Interrupt Link [INTG] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
[    0.259191] ACPI: PCI Interrupt Link [INTH] (IRQs 3 4 5 7 10 11 12 15) *0, disabled.
[    0.263184] vgaarb: device added: PCI:0000:01:05.0,decodes=io+mem,owns=io+mem,locks=none
[    0.263971] vgaarb: loaded
[    0.264969] vgaarb: bridge control possible 0000:01:05.0
[    0.266016] SCSI subsystem initialized
[    0.266984] libata version 3.00 loaded.
[    0.266987] PCI: Using ACPI for IRQ routing
[    0.267974] PCI: pci_cache_line_size set to 64 bytes
[    0.267977] pci 0000:00:01.0: no compatible bridge window for [io  0x1000-0x1fff]
[    0.268969] pci 0000:00:01.0: no compatible bridge window for [mem 0xd8000000-0xd81fffff]
[    0.269969] pci 0000:00:01.0: no compatible bridge window for [mem 0xc0000000-0xcfffffff 64bit pref]
[    0.270969] pci 0000:00:0a.0: no compatible bridge window for [io  0x2000-0x2fff]
[    0.271969] pci 0000:00:0a.0: no compatible bridge window for [mem 0xd8200000-0xd82fffff]
[    0.272969] pci 0000:00:0a.0: no compatible bridge window for [mem 0xd0000000-0xd00fffff 64bit pref]
[    0.273968] pci 0000:00:14.4: no compatible bridge window for [mem 0xd0100000-0xd01fffff pref]
[    0.274975] pci 0000:00:11.0: no compatible bridge window for [io  0x3020-0x3027]
[    0.275975] pci 0000:00:11.0: no compatible bridge window for [io  0x3040-0x3043]
[    0.276968] pci 0000:00:11.0: no compatible bridge window for [io  0x3028-0x302f]
[    0.277968] pci 0000:00:11.0: no compatible bridge window for [io  0x3044-0x3047]
[    0.278967] pci 0000:00:11.0: no compatible bridge window for [io  0x3000-0x300f]
[    0.279968] pci 0000:00:11.0: no compatible bridge window for [mem 0xd8309000-0xd83093ff]
[    0.280970] pci 0000:00:12.0: no compatible bridge window for [mem 0xd8304000-0xd8304fff]
[    0.281970] pci 0000:00:12.1: no compatible bridge window for [mem 0xd8305000-0xd8305fff]
[    0.282969] pci 0000:00:12.2: no compatible bridge window for [mem 0xd8309400-0xd83094ff]
[    0.283969] pci 0000:00:13.0: no compatible bridge window for [mem 0xd8306000-0xd8306fff]
[    0.284969] pci 0000:00:13.1: no compatible bridge window for [mem 0xd8307000-0xd8307fff]
[    0.285969] pci 0000:00:13.2: no compatible bridge window for [mem 0xd8309500-0xd83095ff]
[    0.286970] pci 0000:00:14.1: no compatible bridge window for [io  0x01f0-0x01f7]
[    0.287966] pci 0000:00:14.1: no compatible bridge window for [io  0x03f6]
[    0.288966] pci 0000:00:14.1: no compatible bridge window for [io  0x0170-0x0177]
[    0.289966] pci 0000:00:14.1: no compatible bridge window for [io  0x0376]
[    0.290966] pci 0000:00:14.1: no compatible bridge window for [io  0x3010-0x301f]
[    0.291968] pci 0000:00:14.2: no compatible bridge window for [mem 0xd8300000-0xd8303fff 64bit]
[    0.292972] pci 0000:00:14.5: no compatible bridge window for [mem 0xd8308000-0xd8308fff]
[    0.293970] pci 0000:01:05.0: no compatible bridge window for [mem 0xc0000000-0xcfffffff pref]
[    0.294965] pci 0000:01:05.0: no compatible bridge window for [io  0x1000-0x10ff]
[    0.295965] pci 0000:01:05.0: no compatible bridge window for [mem 0xd8100000-0xd810ffff]
[    0.296965] pci 0000:01:05.0: no compatible bridge window for [mem 0xd8000000-0xd80fffff]
[    0.297966] pci 0000:01:05.1: no compatible bridge window for [mem 0xd8110000-0xd8113fff]
[    0.298966] pci 0000:02:00.0: no compatible bridge window for [io  0x2000-0x20ff]
[    0.299965] pci 0000:02:00.0: no compatible bridge window for [mem 0xd0004000-0xd0004fff 64bit pref]
[    0.300964] pci 0000:02:00.0: no compatible bridge window for [mem 0xd0000000-0xd0003fff 64bit pref]
[    0.301967] pci 0000:03:06.0: no compatible bridge window for [mem 0xd0100000-0xd0100fff pref]
[    0.303004] reserve RAM buffer: 000000000009f000 - 000000000009ffff 
[    0.303006] reserve RAM buffer: 000000006fff0000 - 000000006fffffff 
[    0.307003] pnp: PnP ACPI init
[    0.307987] ACPI: bus type pnp registered
[    0.309129] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110623/psargs-359)
[    0.312962] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS] (Node ffff88006d430d70), AE_NOT_FOUND (20110623/psparse-536)
[    0.317998] pnp 00:00: Plug and Play ACPI device, IDs PNP0a03 (active)
[    0.318052] pnp 00:01: [irq 8]
[    0.318053] pnp 00:01: [io  0x0070-0x0071]
[    0.318072] pnp 00:01: Plug and Play ACPI device, IDs PNP0b00 (active)
[    0.318072] pnp 00:02: [io  0x0061]
[    0.318072] pnp 00:02: Plug and Play ACPI device, IDs PNP0800 (active)
[    0.318072] pnp 00:03: [dma 4]
[    0.318072] pnp 00:03: [io  0x0000-0x000f]
[    0.318072] pnp 00:03: [io  0x0081-0x0083]
[    0.318072] pnp 00:03: [io  0x0087]
[    0.318072] pnp 00:03: [io  0x0089-0x008b]
[    0.318072] pnp 00:03: [io  0x008f]
[    0.318072] pnp 00:03: [io  0x00c0-0x00df]
[    0.318978] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active)
[    0.318984] pnp 00:04: [io  0x00f0-0x00ff]
[    0.318991] pnp 00:04: [irq 13]
[    0.319010] pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active)
[    0.319010] pnp 00:05: [mem 0xfed00000-0xfed003ff]
[    0.319010] pnp 00:05: Plug and Play ACPI device, IDs PNP0103 (active)
[    0.319010] pnp: PnP ACPI: found 6 devices
[    0.319968] ACPI: ACPI bus type pnp unregistered
[    0.326398] Switching to clocksource acpi_pm
[    0.326983] pci 0000:02:00.0: no compatible bridge window for [mem 0xd8200000-0xd820ffff pref]
[    0.327386] Switched to NOHz mode on CPU #1
[    0.339744] Switched to NOHz mode on CPU #0
[    0.343943] PCI: max bus depth: 1 pci_try_num: 2
[    0.343971] pci 0000:00:01.0: BAR 15: can't assign mem pref (size 0x10000000)
[    0.351096] pci 0000:00:01.0: BAR 14: can't assign mem (size 0x200000)
[    0.357613] pci 0000:00:0a.0: BAR 15: can't assign mem pref (size 0x100000)
[    0.364565] pci 0000:00:14.4: BAR 15: can't assign mem pref (size 0x100000)
[    0.371514] pci 0000:00:14.2: BAR 0: can't assign mem (size 0x4000)
[    0.377772] pci 0000:00:14.2: BAR 0: trying firmware assignment [mem 0xd8300000-0xd8303fff 64bit]
[    0.386625] pci 0000:00:14.2: BAR 0: assigned [mem 0xd8300000-0xd8303fff 64bit]
[    0.393935] pci 0000:00:14.2: BAR 0: set to [mem 0xd8300000-0xd8303fff 64bit] (PCI address [0xd8300000-0xd8303fff])
[    0.404344] pci 0000:00:01.0: BAR 13: can't assign io (size 0x1000)
[    0.410602] pci 0000:00:0a.0: BAR 13: can't assign io (size 0x1000)
[    0.416860] pci 0000:00:12.0: BAR 0: can't assign mem (size 0x1000)
[    0.423117] pci 0000:00:12.0: BAR 0: trying firmware assignment [mem 0xd8304000-0xd8304fff]
[    0.431451] pci 0000:00:12.0: BAR 0: assigned [mem 0xd8304000-0xd8304fff]
[    0.438233] pci 0000:00:12.0: BAR 0: set to [mem 0xd8304000-0xd8304fff] (PCI address [0xd8304000-0xd8304fff])
[    0.448128] pci 0000:00:12.1: BAR 0: can't assign mem (size 0x1000)
[    0.454385] pci 0000:00:12.1: BAR 0: trying firmware assignment [mem 0xd8305000-0xd8305fff]
[    0.462718] pci 0000:00:12.1: BAR 0: assigned [mem 0xd8305000-0xd8305fff]
[    0.469501] pci 0000:00:12.1: BAR 0: set to [mem 0xd8305000-0xd8305fff] (PCI address [0xd8305000-0xd8305fff])
[    0.479394] pci 0000:00:13.0: BAR 0: can't assign mem (size 0x1000)
[    0.485652] pci 0000:00:13.0: BAR 0: trying firmware assignment [mem 0xd8306000-0xd8306fff]
[    0.493986] pci 0000:00:13.0: BAR 0: assigned [mem 0xd8306000-0xd8306fff]
[    0.500765] pci 0000:00:13.0: BAR 0: set to [mem 0xd8306000-0xd8306fff] (PCI address [0xd8306000-0xd8306fff])
[    0.510662] pci 0000:00:13.1: BAR 0: can't assign mem (size 0x1000)
[    0.516919] pci 0000:00:13.1: BAR 0: trying firmware assignment [mem 0xd8307000-0xd8307fff]
[    0.525254] pci 0000:00:13.1: BAR 0: assigned [mem 0xd8307000-0xd8307fff]
[    0.532033] pci 0000:00:13.1: BAR 0: set to [mem 0xd8307000-0xd8307fff] (PCI address [0xd8307000-0xd8307fff])
[    0.541929] pci 0000:00:14.5: BAR 0: can't assign mem (size 0x1000)
[    0.548187] pci 0000:00:14.5: BAR 0: trying firmware assignment [mem 0xd8308000-0xd8308fff]
[    0.556519] pci 0000:00:14.5: BAR 0: assigned [mem 0xd8308000-0xd8308fff]
[    0.563300] pci 0000:00:14.5: BAR 0: set to [mem 0xd8308000-0xd8308fff] (PCI address [0xd8308000-0xd8308fff])
[    0.573193] pci 0000:00:11.0: BAR 5: can't assign mem (size 0x400)
[    0.579367] pci 0000:00:11.0: BAR 5: trying firmware assignment [mem 0xd8309000-0xd83093ff]
[    0.587700] pci 0000:00:11.0: BAR 5: assigned [mem 0xd8309000-0xd83093ff]
[    0.594482] pci 0000:00:11.0: BAR 5: set to [mem 0xd8309000-0xd83093ff] (PCI address [0xd8309000-0xd83093ff])
[    0.604375] pci 0000:00:12.2: BAR 0: can't assign mem (size 0x100)
[    0.610548] pci 0000:00:12.2: BAR 0: trying firmware assignment [mem 0xd8309400-0xd83094ff]
[    0.618880] pci 0000:00:12.2: BAR 0: assigned [mem 0xd8309400-0xd83094ff]
[    0.625660] pci 0000:00:12.2: BAR 0: set to [mem 0xd8309400-0xd83094ff] (PCI address [0xd8309400-0xd83094ff])
[    0.635554] pci 0000:00:13.2: BAR 0: can't assign mem (size 0x100)
[    0.641727] pci 0000:00:13.2: BAR 0: trying firmware assignment [mem 0xd8309500-0xd83095ff]
[    0.650060] pci 0000:00:13.2: BAR 0: assigned [mem 0xd8309500-0xd83095ff]
[    0.656842] pci 0000:00:13.2: BAR 0: set to [mem 0xd8309500-0xd83095ff] (PCI address [0xd8309500-0xd83095ff])
[    0.666736] pci 0000:00:11.0: BAR 4: can't assign io (size 0x10)
[    0.672737] pci 0000:00:11.0: BAR 4: trying firmware assignment [io  0x3000-0x300f]
[    0.680388] pci 0000:00:11.0: BAR 4: assigned [io  0x3000-0x300f]
[    0.686474] pci 0000:00:11.0: BAR 4: set to [io  0x3000-0x300f] (PCI address [0x3000-0x300f])
[    0.694985] pci 0000:00:14.1: BAR 4: can't assign io (size 0x10)
[    0.700986] pci 0000:00:14.1: BAR 4: trying firmware assignment [io  0x3010-0x301f]
[    0.708628] pci 0000:00:14.1: BAR 4: assigned [io  0x3010-0x301f]
[    0.714715] pci 0000:00:14.1: BAR 4: set to [io  0x3010-0x301f] (PCI address [0x3010-0x301f])
[    0.723219] pci 0000:00:11.0: BAR 0: can't assign io (size 0x8)
[    0.729132] pci 0000:00:11.0: BAR 0: trying firmware assignment [io  0x3020-0x3027]
[    0.736774] pci 0000:00:11.0: BAR 0: assigned [io  0x3020-0x3027]
[    0.742862] pci 0000:00:11.0: BAR 0: set to [io  0x3020-0x3027] (PCI address [0x3020-0x3027])
[    0.751375] pci 0000:00:11.0: BAR 2: can't assign io (size 0x8)
[    0.757285] pci 0000:00:11.0: BAR 2: trying firmware assignment [io  0x3028-0x302f]
[    0.764929] pci 0000:00:11.0: BAR 2: assigned [io  0x3028-0x302f]
[    0.771018] pci 0000:00:11.0: BAR 2: set to [io  0x3028-0x302f] (PCI address [0x3028-0x302f])
[    0.779530] pci 0000:00:11.0: BAR 1: can't assign io (size 0x4)
[    0.785441] pci 0000:00:11.0: BAR 1: trying firmware assignment [io  0x3040-0x3043]
[    0.793083] pci 0000:00:11.0: BAR 1: assigned [io  0x3040-0x3043]
[    0.799171] pci 0000:00:11.0: BAR 1: set to [io  0x3040-0x3043] (PCI address [0x3040-0x3043])
[    0.807674] pci 0000:00:11.0: BAR 3: can't assign io (size 0x4)
[    0.813588] pci 0000:00:11.0: BAR 3: trying firmware assignment [io  0x3044-0x3047]
[    0.821230] pci 0000:00:11.0: BAR 3: assigned [io  0x3044-0x3047]
[    0.827318] pci 0000:00:11.0: BAR 3: set to [io  0x3044-0x3047] (PCI address [0x3044-0x3047])
[    0.835832] pci 0000:01:05.0: BAR 0: can't assign mem pref (size 0x10000000)
[    0.842869] pci 0000:01:05.0: BAR 0: trying firmware assignment [mem 0xc0000000-0xcfffffff pref]
[    0.851632] pci 0000:01:05.0: BAR 0: assigned [mem 0xc0000000-0xcfffffff pref]
[    0.858845] pci 0000:01:05.0: BAR 0: set to [mem 0xc0000000-0xcfffffff pref] (PCI address [0xc0000000-0xcfffffff])
[    0.869171] pci 0000:01:05.0: BAR 5: can't assign mem (size 0x100000)
[    0.875606] pci 0000:01:05.0: BAR 5: trying firmware assignment [mem 0xd8000000-0xd80fffff]
[    0.883936] pci 0000:01:05.0: BAR 5: assigned [mem 0xd8000000-0xd80fffff]
[    0.890715] pci 0000:01:05.0: BAR 5: set to [mem 0xd8000000-0xd80fffff] (PCI address [0xd8000000-0xd80fffff])
[    0.900605] pci 0000:01:05.0: BAR 2: can't assign mem (size 0x10000)
[    0.906951] pci 0000:01:05.0: BAR 2: trying firmware assignment [mem 0xd8100000-0xd810ffff]
[    0.915290] pci 0000:01:05.0: BAR 2: assigned [mem 0xd8100000-0xd810ffff]
[    0.922069] pci 0000:01:05.0: BAR 2: set to [mem 0xd8100000-0xd810ffff] (PCI address [0xd8100000-0xd810ffff])
[    0.931958] pci 0000:01:05.1: BAR 0: can't assign mem (size 0x4000)
[    0.938218] pci 0000:01:05.1: BAR 0: trying firmware assignment [mem 0xd8110000-0xd8113fff]
[    0.946557] pci 0000:01:05.1: BAR 0: assigned [mem 0xd8110000-0xd8113fff]
[    0.953338] pci 0000:01:05.1: BAR 0: set to [mem 0xd8110000-0xd8113fff] (PCI address [0xd8110000-0xd8113fff])
[    0.963234] pci 0000:01:05.0: BAR 1: can't assign io (size 0x100)
[    0.969320] pci 0000:01:05.0: BAR 1: trying firmware assignment [io  0x1000-0x10ff]
[    0.976960] pci 0000:01:05.0: BAR 1: assigned [io  0x1000-0x10ff]
[    0.983049] pci 0000:01:05.0: BAR 1: set to [io  0x1000-0x10ff] (PCI address [0x1000-0x10ff])
[    0.991562] pci 0000:00:01.0: PCI bridge to [bus 01-01]
[    0.996791] pci 0000:02:00.0: BAR 6: can't assign mem pref (size 0x10000)
[    1.003571] pci 0000:02:00.0: BAR 4: can't assign mem pref (size 0x4000)
[    1.010271] pci 0000:02:00.0: BAR 4: trying firmware assignment [mem 0xd0000000-0xd0003fff 64bit pref]
[    1.019559] pci 0000:02:00.0: BAR 4: assigned [mem 0xd0000000-0xd0003fff 64bit pref]
[    1.027296] pci 0000:02:00.0: BAR 4: set to [mem 0xd0000000-0xd0003fff 64bit pref] (PCI address [0xd0000000-0xd0003fff])
[    1.038137] pci 0000:02:00.0: BAR 2: can't assign mem pref (size 0x1000)
[    1.044827] pci 0000:02:00.0: BAR 2: trying firmware assignment [mem 0xd0004000-0xd0004fff 64bit pref]
[    1.054114] pci 0000:02:00.0: BAR 2: assigned [mem 0xd0004000-0xd0004fff 64bit pref]
[    1.061847] pci 0000:02:00.0: BAR 2: set to [mem 0xd0004000-0xd0004fff 64bit pref] (PCI address [0xd0004000-0xd0004fff])
[    1.072689] pci 0000:02:00.0: BAR 0: can't assign io (size 0x100)
[    1.078774] pci 0000:02:00.0: BAR 0: trying firmware assignment [io  0x2000-0x20ff]
[    1.086415] pci 0000:02:00.0: BAR 0: assigned [io  0x2000-0x20ff]
[    1.092506] pci 0000:02:00.0: BAR 0: set to [io  0x2000-0x20ff] (PCI address [0x2000-0x20ff])
[    1.101018] pci 0000:00:0a.0: PCI bridge to [bus 02-02]
[    1.106247] pci 0000:03:06.0: BAR 0: can't assign mem pref (size 0x1000)
[    1.112939] pci 0000:03:06.0: BAR 0: trying firmware assignment [mem 0xd0100000-0xd0100fff pref]
[    1.121702] pci 0000:03:06.0: BAR 0: assigned [mem 0xd0100000-0xd0100fff pref]
[    1.128916] pci 0000:03:06.0: BAR 0: set to [mem 0xd0100000-0xd0100fff pref] (PCI address [0xd0100000-0xd0100fff])
[    1.139244] pci 0000:00:14.4: PCI bridge to [bus 03-03]
[    1.144487] pci 0000:00:0a.0: setting latency timer to 64
[    1.144525] NET: Registered protocol family 2
[    1.148922] IP route cache hash table entries: 65536 (order: 7, 524288 bytes)
[    1.156306] TCP established hash table entries: 262144 (order: 10, 4194304 bytes)
[    1.165050] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[    1.172085] TCP: Hash tables configured (established 262144 bind 65536)
[    1.178698] TCP reno registered
[    1.181846] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[    1.187853] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[    1.194353] NET: Registered protocol family 1
[    1.198718] pci 0000:00:01.0: MSI quirk detected; subordinate MSI disabled
[    1.205702] pci 0000:01:05.0: Boot video device
[    1.205712] PCI: CLS 64 bytes, default 64
[    1.207635] audit: initializing netlink socket (disabled)
[    1.213044] type=2000 audit(1324316282.212:1): initialized
[    1.222504] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[    1.233657] msgmni has been set to 3505
[    1.237959] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
[    1.245364] io scheduler noop registered
[    1.249303] io scheduler deadline registered
[    1.253662] io scheduler cfq registered (default)
[    1.258471] pcieport 0000:00:0a.0: setting latency timer to 64
[    1.258515] pcieport 0000:00:0a.0: irq 40 for MSI/MSI-X
[    1.258859] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    1.530157] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    1.593350] hpet_acpi_add: no address or irqs in _CRS
[    1.598467] Linux agpgart interface v0.103
[    1.603069] uvesafb: Getting VBE info block failed (eax=0x4f00, err=0)
[    1.609598] uvesafb: vbe_init() failed with -22
[    1.614129] uvesafb: probe of uvesafb.0 failed with error -22
[    1.619953] input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0
[    1.628117] ACPI: Power Button [PWRB]
[    1.631853] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
[    1.639243] ACPI: Power Button [PWRF]
[    1.643069] ACPI: Fan [FAN0] (on)
[    1.646441] ACPI: acpi_idle registered with cpuidle
[    1.667058] thermal LNXTHERM:00: registered as thermal_zone0
[    1.672724] ACPI: Thermal Zone [TZ00] (40 C)
[    1.679331] brd: module loaded
[    1.683619] loop: module loaded
[    1.687135] ahci 0000:00:11.0: version 3.0
[    1.687151] ahci 0000:00:11.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22
[    1.694036] ahci 0000:00:11.0: irq 41 for MSI/MSI-X
[    1.694136] ahci 0000:00:11.0: AHCI 0001.0100 32 slots 4 ports 3 Gbps 0xf impl SATA mode
[    1.702217] ahci 0000:00:11.0: flags: 64bit ncq sntf ilck pm led clo pmp pio slum part ccc 
[    1.711610] scsi0 : ahci
[    1.714329] scsi1 : ahci
[    1.717052] scsi2 : ahci
[    1.719739] scsi3 : ahci
[    1.722460] ata1: SATA max UDMA/133 abar m1024 at 0xd8309000 port 0xd8309100 irq 41
[    1.729846] ata2: SATA max UDMA/133 abar m1024 at 0xd8309000 port 0xd8309180 irq 41
[    1.737234] ata3: SATA max UDMA/133 abar m1024 at 0xd8309000 port 0xd8309200 irq 41
[    1.744618] ata4: SATA max UDMA/133 abar m1024 at 0xd8309000 port 0xd8309280 irq 41
[    1.752431] i8042: PNP: No PS/2 controller found. Probing ports directly.
[    1.759652] serio: i8042 KBD port at 0x60,0x64 irq 1
[    1.764624] serio: i8042 AUX port at 0x60,0x64 irq 12
[    1.769797] mousedev: PS/2 mouse device common for all mice
[    1.775618] rtc_cmos 00:01: RTC can wake from S4
[    1.780393] rtc_cmos 00:01: rtc core: registered rtc_cmos as rtc0
[    1.786517] rtc0: alarms up to one day, 114 bytes nvram
[    1.791787] i2c /dev entries driver
[    1.791930] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input2
[    1.804087] device-mapper: ioctl: 4.21.0-ioctl (2011-07-06) initialised: dm-devel at redhat.com
[    1.812649] cpuidle: using governor ladder
[    1.816750] cpuidle: using governor menu
[    1.820900] TCP cubic registered
[    1.824484] NET: Registered protocol family 10
[    1.829207] IPv6 over IPv4 tunneling driver
[    1.833780] NET: Registered protocol family 17
[    1.838423] registered taskstats version 1
[    1.842746]   Magic number: 7:848:643
[    1.846464] powernow-k8: Found 1 AMD Athlon(tm) II X2 245e Processor (2 cpu cores) (version 2.20.00)
[    1.855605] powernow-k8:    0 : pstate 0 (2900 MHz)
[    1.860482] powernow-k8:    1 : pstate 1 (2100 MHz)
[    2.067051] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[    2.073261] ata4: SATA link down (SStatus 0 SControl 300)
[    2.078703] ata2: SATA link down (SStatus 0 SControl 300)
[    2.084159] ata3: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[    2.090933] ata1.00: ATA-8: WDC WD10EARS-00Y5B1, 80.00A80, max UDMA/133
[    2.097548] ata1.00: 1953525168 sectors, multi 0: LBA48 NCQ (depth 31/32), AA
[    2.104700] ata3.00: ATAPI: TSSTcorpCD/DVDW SH-S183L, SB03, max UDMA/33
[    2.111306] ata3.00: applying bridge limits
[    2.117600] ata1.00: configured for UDMA/133
[    2.121883] ata3.00: configured for UDMA/33
[    2.121960] scsi 0:0:0:0: Direct-Access     ATA      WDC WD10EARS-00Y 80.0 PQ: 0 ANSI: 5
[    2.134396] sd 0:0:0:0: [sda] 1953525168 512-byte logical blocks: (1.00 TB/931 GiB)
[    2.142038] sd 0:0:0:0: Attached scsi generic sg0 type 0
[    2.142092] sd 0:0:0:0: [sda] Write Protect is off
[    2.142095] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[    2.142108] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    2.161181]  sda: sda1 sda2 sda3 sda4
[    2.165394] sd 0:0:0:0: [sda] Attached SCSI disk
[    2.165682] scsi 2:0:0:0: CD-ROM            TSSTcorp CD/DVDW SH-S183L SB03 PQ: 0 ANSI: 5
[    2.174083] sr0: scsi3-mmc drive: 48x/48x writer dvd-ram cd/rw xa/form2 cdda tray
[    2.174086] cdrom: Uniform CD-ROM driver Revision: 3.20
[    2.174201] sr 2:0:0:0: Attached scsi CD-ROM sr0
[    2.174275] sr 2:0:0:0: Attached scsi generic sg1 type 5
[    2.201794] EXT3-fs (sda3): error: couldn't mount because of unsupported optional features (240)
[    2.208053] Refined TSC clocksource calibration: 2907.446 MHz.
[    2.208057] Switching to clocksource tsc
[    2.224131] EXT4-fs (sda3): couldn't mount as ext2 due to feature incompatibilities
[    2.259299] EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: (null)
[    2.266951] VFS: Mounted root (ext4 filesystem) readonly on device 8:3.
[    2.274518] Freeing unused kernel memory: 572k freed
[    3.733179] udev[3812]: starting version 164
[    3.851917] fglrx: module license 'Proprietary. (C) 2002 - ATI Technologies, Starnberg, GERMANY' taints kernel.
[    3.851921] Disabling lock debugging due to kernel taint
[    3.875637] usbcore: registered new interface driver usbfs
[    3.875648] usbcore: registered new interface driver hub
[    3.881843] usbcore: registered new device driver usb
[    3.885042] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
[    3.885070] r8169 0000:02:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
[    3.885092] r8169 0000:02:00.0: (unregistered net_device): unknown MAC, using family default
[    3.895287] r8169 0000:02:00.0: setting latency timer to 64
[    3.895361] r8169 0000:02:00.0: irq 42 for MSI/MSI-X
[    3.896221] r8169 0000:02:00.0: eth0: RTL8168b/8111b at 0xffffc9000061c000, ff:ff:ff:ff:ff:ff, XID 9cf0f8ff IRQ 42
[    3.905050] IR NEC protocol handler initialized
[    3.914830] IR RC5(x) protocol handler initialized
[    3.918190] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    3.918225] ehci_hcd 0000:00:12.2: PCI INT B -> GSI 17 (level, low) -> IRQ 17
[    3.918245] ehci_hcd 0000:00:12.2: EHCI Host Controller
[    3.918252] ehci_hcd 0000:00:12.2: new USB bus registered, assigned bus number 1
[    3.918264] ehci_hcd 0000:00:12.2: applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround
[    3.918294] ehci_hcd 0000:00:12.2: debug port 1
[    3.918328] ehci_hcd 0000:00:12.2: irq 17, io mem 0xd8309400
[    3.920248] Mantis 0000:03:06.0: PCI INT A -> GSI 21 (level, low) -> IRQ 21
[    3.921382] DVB: registering new adapter (Mantis DVB adapter)
[    3.923183] IR RC6 protocol handler initialized
[    3.924028] ehci_hcd 0000:00:12.2: USB 2.0 started, EHCI 1.00
[    3.924053] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    3.924056] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.924058] usb usb1: Product: EHCI Host Controller
[    3.924060] usb usb1: Manufacturer: Linux 3.1.5-gentoo ehci_hcd
[    3.924062] usb usb1: SerialNumber: 0000:00:12.2
[    3.924144] hub 1-0:1.0: USB hub found
[    3.924148] hub 1-0:1.0: 6 ports detected
[    3.924235] ehci_hcd 0000:00:13.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19
[    3.924256] ehci_hcd 0000:00:13.2: EHCI Host Controller
[    3.924262] ehci_hcd 0000:00:13.2: new USB bus registered, assigned bus number 2
[    3.924273] ehci_hcd 0000:00:13.2: applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround
[    3.924300] ehci_hcd 0000:00:13.2: debug port 1
[    3.924335] ehci_hcd 0000:00:13.2: irq 19, io mem 0xd8309500
[    3.930015] ehci_hcd 0000:00:13.2: USB 2.0 started, EHCI 1.00
[    3.930145] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
[    3.930148] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.930151] usb usb2: Product: EHCI Host Controller
[    3.930153] usb usb2: Manufacturer: Linux 3.1.5-gentoo ehci_hcd
[    3.930155] usb usb2: SerialNumber: 0000:00:13.2
[    3.936309] hub 2-0:1.0: USB hub found
[    3.936315] hub 2-0:1.0: 6 ports detected
[    3.941542] [fglrx] Maximum main memory to use for locked dma buffers: 1638 MBytes.
[    3.941610] [fglrx]   vendor: 1002 device: 9616 count: 1
[    3.942075] [fglrx] ioport: bar 1, base 0x1000, size: 0x100
[    3.942097] pci 0000:01:05.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
[    3.942104] pci 0000:01:05.0: setting latency timer to 64
[    3.942527] [fglrx] Kernel PAT support is enabled
[    3.942545] [fglrx] module loaded - fglrx 8.88.7 [Jul 28 2011] with 1 minors
[    3.943460] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    3.943489] ohci_hcd 0000:00:12.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[    3.943510] ohci_hcd 0000:00:12.0: OHCI Host Controller
[    3.943517] ohci_hcd 0000:00:12.0: new USB bus registered, assigned bus number 3
[    3.943556] ohci_hcd 0000:00:12.0: irq 16, io mem 0xd8304000
[    3.998045] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
[    3.998049] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.998052] usb usb3: Product: OHCI Host Controller
[    3.998054] usb usb3: Manufacturer: Linux 3.1.5-gentoo ohci_hcd
[    3.998055] usb usb3: SerialNumber: 0000:00:12.0
[    3.998142] hub 3-0:1.0: USB hub found
[    3.998150] hub 3-0:1.0: 3 ports detected
[    3.998220] ohci_hcd 0000:00:12.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[    3.998245] ohci_hcd 0000:00:12.1: OHCI Host Controller
[    3.998250] ohci_hcd 0000:00:12.1: new USB bus registered, assigned bus number 4
[    3.998273] ohci_hcd 0000:00:12.1: irq 16, io mem 0xd8305000
[    4.053037] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
[    4.053040] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    4.053042] usb usb4: Product: OHCI Host Controller
[    4.053044] usb usb4: Manufacturer: Linux 3.1.5-gentoo ohci_hcd
[    4.053046] usb usb4: SerialNumber: 0000:00:12.1
[    4.053103] hub 4-0:1.0: USB hub found
[    4.053110] hub 4-0:1.0: 3 ports detected
[    4.053165] ohci_hcd 0000:00:13.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
[    4.053176] ohci_hcd 0000:00:13.0: OHCI Host Controller
[    4.053181] ohci_hcd 0000:00:13.0: new USB bus registered, assigned bus number 5
[    4.053212] ohci_hcd 0000:00:13.0: irq 18, io mem 0xd8306000
[    4.101710] IR JVC protocol handler initialized
[    4.108053] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
[    4.108056] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    4.108059] usb usb5: Product: OHCI Host Controller
[    4.108061] usb usb5: Manufacturer: Linux 3.1.5-gentoo ohci_hcd
[    4.108062] usb usb5: SerialNumber: 0000:00:13.0
[    4.108151] hub 5-0:1.0: USB hub found
[    4.108158] hub 5-0:1.0: 3 ports detected
[    4.108231] ohci_hcd 0000:00:13.1: PCI INT A -> GSI 18 (level, low) -> IRQ 18
[    4.108252] ohci_hcd 0000:00:13.1: OHCI Host Controller
[    4.108258] ohci_hcd 0000:00:13.1: new USB bus registered, assigned bus number 6
[    4.108280] ohci_hcd 0000:00:13.1: irq 18, io mem 0xd8307000
[    4.163040] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
[    4.163043] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    4.163045] usb usb6: Product: OHCI Host Controller
[    4.163047] usb usb6: Manufacturer: Linux 3.1.5-gentoo ohci_hcd
[    4.163049] usb usb6: SerialNumber: 0000:00:13.1
[    4.163111] hub 6-0:1.0: USB hub found
[    4.163118] hub 6-0:1.0: 3 ports detected
[    4.163177] ohci_hcd 0000:00:14.5: PCI INT C -> GSI 18 (level, low) -> IRQ 18
[    4.163188] ohci_hcd 0000:00:14.5: OHCI Host Controller
[    4.163193] ohci_hcd 0000:00:14.5: new USB bus registered, assigned bus number 7
[    4.163210] ohci_hcd 0000:00:14.5: irq 18, io mem 0xd8308000
[    4.218037] usb usb7: New USB device found, idVendor=1d6b, idProduct=0001
[    4.218040] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    4.218042] usb usb7: Product: OHCI Host Controller
[    4.218045] usb usb7: Manufacturer: Linux 3.1.5-gentoo ohci_hcd
[    4.218047] usb usb7: SerialNumber: 0000:00:14.5
[    4.218106] hub 7-0:1.0: USB hub found
[    4.218113] hub 7-0:1.0: 2 ports detected
[    4.245919] IR Sony protocol handler initialized
[    4.248212] IR MCE Keyboard/mouse protocol handler initialized
[    4.486008] usb 6-2: new low speed USB device number 2 using ohci_hcd
[    4.495977] lirc_dev: IR Remote Control driver registered, major 250 
[    4.496305] IR LIRC bridge handler initialized
[    4.630842] usb 6-2: New USB device found, idVendor=15c2, idProduct=0038
[    4.630845] usb 6-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    4.635303] input: iMON Panel, Knob and Mouse(15c2:0038) as /devices/pci0000:00/0000:00:13.1/usb6/6-2/6-2:1.0/input/input3
[    4.667006] Registered IR keymap rc-imon-pad
[    4.667089] input: iMON Remote (15c2:0038) as /devices/pci0000:00/0000:00:13.1/usb6/6-2/6-2:1.0/rc/rc0/input4
[    4.667121] rc0: iMON Remote (15c2:0038) as /devices/pci0000:00/0000:00:13.1/usb6/6-2/6-2:1.0/rc/rc0
[    4.672036] imon 6-2:1.0: iMON device (15c2:0038, intf0) on usb<6:2> initialized
[    4.672052] imon 6-2:1.1: iMON device (15c2:0038, intf1) on usb<6:2> initialized
[    4.672065] usbcore: registered new interface driver imon
[    4.672227] usbcore: registered new interface driver usbhid
[    4.672230] usbhid: USB HID core driver
[    4.779439] tda10021_attach: driver disabled by Kconfig
[    4.780649] DVB: registering adapter 0 frontend 0 (Philips TDA10023 DVB-C)...
[    6.910203] EXT4-fs (sda3): re-mounted. Opts: (null)
[    6.979135] EXT4-fs (sda1): mounting ext2 file system using the ext4 subsystem
[    6.982838] EXT4-fs (sda1): mounted filesystem without journal. Opts: (null)
[    7.007573] EXT4-fs (dm-0): mounted filesystem with ordered data mode. Opts: (null)
[    7.038870] EXT4-fs (dm-1): mounting ext2 file system using the ext4 subsystem
[    7.043705] EXT4-fs (dm-1): mounted filesystem without journal. Opts: (null)
[    7.062363] EXT4-fs (dm-2): mounting ext2 file system using the ext4 subsystem
[    7.067086] EXT4-fs (dm-2): mounted filesystem without journal. Opts: (null)
[    7.102780] EXT4-fs (dm-3): mounted filesystem with ordered data mode. Opts: (null)
[    7.125005] EXT4-fs (dm-4): mounting ext2 file system using the ext4 subsystem
[    7.129718] EXT4-fs (dm-4): mounted filesystem without journal. Opts: (null)
[    7.165591] EXT4-fs (dm-5): mounted filesystem with ordered data mode. Opts: (null)
[    7.465589] Adding 1048572k swap on /dev/sda2.  Priority:-1 extents:1 across:1048572k 
[    8.750766] syslog-ng (5061): Attempt to access syslog with CAP_SYS_ADMIN but no CAP_SYSLOG (deprecated).
[   23.555634] NVRM: No NVIDIA graphics adapter found!
[   28.171160] NVRM: No NVIDIA graphics adapter found!
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From Kerry.She at amd.com  Mon Dec 19 18:43:01 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Tue, 20 Dec 2011 01:43:01 +0800
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
	multipleVGA cards resource conflict on Windows
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org><I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org><CAP6exY+=rLiwFHqouSKLMAmM=3g+sbgP3MEQJCtWhdEXpN+A4A@mail.gmail.com><F53A09371FB723428826B442A4B20A4108982B85@sbjgexmb1.amd.com>
	<CAP6exYKRz0MRawXXPZjeG4rm-GXLM-E74p_+jwwL_+2S--ZLUQ@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A4105844413@sbjgexmb1.amd.com>




-----Original Message-----
From: ron minnich [mailto:rminnich at gmail.com]
Sent: Tue 12/20/2011 1:02 AM
To: She, Kerry
Cc: Kerry Sheh; coreboot at coreboot.org
Subject: Re: [coreboot] Patch set updated for coreboot: 6709bdd Fix multipleVGA cards resource conflict on Windows
 
On Sun, Dec 18, 2011 at 10:01 PM, She, Kerry <Kerry.She at amd.com> wrote:
>> Hello, Ron
>>
>>> I asked:
>>> What do Linux or *BSD do in the same situation? Do they handle it cleanly?
>> Linux VGA Arbiter module(vgaarb) will handle this explicitly.
>> So dual vga card would works together, even coreboot not disable IO& MEM decoding on the second vga card.

>OK, then,  my concern about this patch is that you are making a
>compile-time decision in  coreboot to fix a problem with one operating
>system (Windows) that will impact other operating systems that don't
>have the problem.
Yes, I agree.

>I wonder if a better way to manage this is via a CMOS (aka NVRAM)
>setting. I kind of hate to limit coreboot because Windows is limited.
>But I'm a n00b in a sense, having just come back onto this project, so
>I'm happy to be told I'm wrong :-)
I think CMOS option is a better choice for this case,
thanks for your advice.

>ron
>p.s. For those who don't know me, I've been out of coreboot for 2
>years, having been heavily involved from 1999 (when I started
>LinuxBIOS) to 2009. Changing circumstances mean I get to work on it
>again, which is nice.
That's great, I'm glad to hear that you are back to work on coreboot again:)

kerry
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From patrick at georgi-clan.de  Mon Dec 19 18:31:02 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 19 Dec 2011 18:31:02 +0100
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
 multipleVGA cards resource conflict on Windows
In-Reply-To: <CAP6exYKRz0MRawXXPZjeG4rm-GXLM-E74p_+jwwL_+2S--ZLUQ@mail.gmail.com>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>	<I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>	<CAP6exY+=rLiwFHqouSKLMAmM=3g+sbgP3MEQJCtWhdEXpN+A4A@mail.gmail.com>	<F53A09371FB723428826B442A4B20A4108982B85@sbjgexmb1.amd.com>
	<CAP6exYKRz0MRawXXPZjeG4rm-GXLM-E74p_+jwwL_+2S--ZLUQ@mail.gmail.com>
Message-ID: <4EEF74D6.3050202@georgi-clan.de>

Am 19.12.2011 18:02, schrieb ron minnich:
> I wonder if a better way to manage this is via a CMOS (aka NVRAM)
> setting. 
No user visible configuration if it can be avoided, please.

> I kind of hate to limit coreboot because Windows is limited.
> But I'm a n00b in a sense, having just come back onto this project, so
> I'm happy to be told I'm wrong :-)
It sounds just wrong to have IO/MEM decoding on the _same_ areas
activated for two devices.

vgaarb should still work with one of them having resources disabled by
default, I think.
Otherwise coreboot would be the _only_ chance for vgaarb to work, as all
other boot systems will support Windows even to the detriment of Linux
support.
Which means that vgaarb wouldn't exist, given their position towards
coreboot.

> Changing circumstances mean I get to work on it
> again, which is nice.
Yay!


Patrick


From Kerry.She at amd.com  Tue Dec 20 03:13:52 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Tue, 20 Dec 2011 10:13:52 +0800
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
	multipleVGA cards resource conflict on Windows
In-Reply-To: <4EEF74D6.3050202@georgi-clan.de>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>	<I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>	<CAP6exY+=rLiwFHqouSKLMAmM=3g+sbgP3MEQJCtWhdEXpN+A4A@mail.gmail.com>	<F53A09371FB723428826B442A4B20A4108982B85@sbjgexmb1.amd.com><CAP6exYKRz0MRawXXPZjeG4rm-GXLM-E74p_+jwwL_+2S--ZLUQ@mail.gmail.com>
	<4EEF74D6.3050202@georgi-clan.de>
Message-ID: <F53A09371FB723428826B442A4B20A4108A2513A@sbjgexmb1.amd.com>

Hello, Patrick

> -----Original Message-----
> From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Patrick Georgi
> Sent: Tuesday, December 20, 2011 1:31 AM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] Patch set updated for coreboot: 6709bdd Fix
> multipleVGA cards resource conflict on Windows
> 
> Am 19.12.2011 18:02, schrieb ron minnich:
> > I wonder if a better way to manage this is via a CMOS (aka NVRAM)
> > setting.
> No user visible configuration if it can be avoided, please.
> 
> > I kind of hate to limit coreboot because Windows is limited.
> > But I'm a n00b in a sense, having just come back onto this project,
so
> > I'm happy to be told I'm wrong :-)
> It sounds just wrong to have IO/MEM decoding on the _same_ areas
> activated for two devices.
Yes, exactly.
 
> vgaarb should still work with one of them having resources disabled by
> default, I think.
I have tested Linux vgaarb still works.
We just do a part of the vgaarb job in coreboot.

> Otherwise coreboot would be the _only_ chance for vgaarb to work, as
all
> other boot systems will support Windows even to the detriment of Linux
> support.
> Which means that vgaarb wouldn't exist, given their position towards
> coreboot.
It make sense on the OS lacking a mechanism like vgaarb.
Anyway, more test on different OS is needed.
Thanks

> 
> > Changing circumstances mean I get to work on it
> > again, which is nice.
> Yay!
> 
> 
> Patrick
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




From tsylla at gmail.com  Tue Dec 20 04:33:35 2011
From: tsylla at gmail.com (Tom Sylla)
Date: Mon, 19 Dec 2011 19:33:35 -0800
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
 multipleVGA cards resource conflict on Windows
In-Reply-To: <F53A09371FB723428826B442A4B20A4108A2513A@sbjgexmb1.amd.com>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
	<I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>
	<CAP6exY+=rLiwFHqouSKLMAmM=3g+sbgP3MEQJCtWhdEXpN+A4A@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4108982B85@sbjgexmb1.amd.com>
	<CAP6exYKRz0MRawXXPZjeG4rm-GXLM-E74p_+jwwL_+2S--ZLUQ@mail.gmail.com>
	<4EEF74D6.3050202@georgi-clan.de>
	<F53A09371FB723428826B442A4B20A4108A2513A@sbjgexmb1.amd.com>
Message-ID: <CAAxijvfdq-yq1ZoXGdLZJ4kh-M6RA41xzeYSgVSuvn+uxgCCUg@mail.gmail.com>

The open-graphics people had this question a while back, I think I
took a look at some different platforms and BIOSes:
http://lists.duskglow.com/open-graphics/2007-August/010402.html

Turning on the decoders for only one of each type of legacy device sounds right.

On Mon, Dec 19, 2011 at 6:13 PM, She, Kerry <Kerry.She at amd.com> wrote:
> Hello, Patrick
>
>> -----Original Message-----
>> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org]
>> On Behalf Of Patrick Georgi
>> Sent: Tuesday, December 20, 2011 1:31 AM
>> To: coreboot at coreboot.org
>> Subject: Re: [coreboot] Patch set updated for coreboot: 6709bdd Fix
>> multipleVGA cards resource conflict on Windows
>>
>> Am 19.12.2011 18:02, schrieb ron minnich:
>> > I wonder if a better way to manage this is via a CMOS (aka NVRAM)
>> > setting.
>> No user visible configuration if it can be avoided, please.
>>
>> > I kind of hate to limit coreboot because Windows is limited.
>> > But I'm a n00b in a sense, having just come back onto this project,
> so
>> > I'm happy to be told I'm wrong :-)
>> It sounds just wrong to have IO/MEM decoding on the _same_ areas
>> activated for two devices.
> Yes, exactly.
>
>> vgaarb should still work with one of them having resources disabled by
>> default, I think.
> I have tested Linux vgaarb still works.
> We just do a part of the vgaarb job in coreboot.
>
>> Otherwise coreboot would be the _only_ chance for vgaarb to work, as
> all
>> other boot systems will support Windows even to the detriment of Linux
>> support.
>> Which means that vgaarb wouldn't exist, given their position towards
>> coreboot.
> It make sense on the OS lacking a mechanism like vgaarb.
> Anyway, more test on different OS is needed.
> Thanks
>
>>
>> > Changing circumstances mean I get to work on it
>> > again, which is nice.
>> Yay!
>>
>>
>> Patrick
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


From marcj303 at gmail.com  Tue Dec 20 07:09:59 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 19 Dec 2011 23:09:59 -0700
Subject: [coreboot] Patch set updated for coreboot: 6709bdd Fix
 multipleVGA cards resource conflict on Windows
In-Reply-To: <CAAxijvfdq-yq1ZoXGdLZJ4kh-M6RA41xzeYSgVSuvn+uxgCCUg@mail.gmail.com>
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
	<I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+3@gerrit.coreboot.org>
	<CAP6exY+=rLiwFHqouSKLMAmM=3g+sbgP3MEQJCtWhdEXpN+A4A@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A4108982B85@sbjgexmb1.amd.com>
	<CAP6exYKRz0MRawXXPZjeG4rm-GXLM-E74p_+jwwL_+2S--ZLUQ@mail.gmail.com>
	<4EEF74D6.3050202@georgi-clan.de>
	<F53A09371FB723428826B442A4B20A4108A2513A@sbjgexmb1.amd.com>
	<CAAxijvfdq-yq1ZoXGdLZJ4kh-M6RA41xzeYSgVSuvn+uxgCCUg@mail.gmail.com>
Message-ID: <CALrs_3hbuCzd9V+wVkxMc9BfsMijzRYQKssU+s8TsCWovii6Ww@mail.gmail.com>

On Mon, Dec 19, 2011 at 8:33 PM, Tom Sylla <tsylla at gmail.com> wrote:
> The open-graphics people had this question a while back, I think I
> took a look at some different platforms and BIOSes:
> http://lists.duskglow.com/open-graphics/2007-August/010402.html
>
> Turning on the decoders for only one of each type of legacy device sounds right.

Right, the bridges need to be setup with the snoop etc, but only one
device can have the decode enabled.

Marc

-- 
http://se-eng.com


From paulepanter at users.sourceforge.net  Tue Dec 20 21:13:21 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Tue, 20 Dec 2011 21:13:21 +0100
Subject: [coreboot] [PATCH] superiotool.h: Add `EOT` to end of entry
Message-ID: <1324412001.4397.2.camel@mattotaupa>

Date: Mon, 19 Dec 2011 23:50:32 +0100

This is a fix up for commit 3d1d6bb4 which forgot to add `EOT` at the end.

        commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576
        Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
        Date:   Mon Nov 7 10:56:42 2011 -0600

            superiotool: add detection and dump of Infineon SLB9635 TPM

Carl-Daniel explained the continuous integration tool Jenkins did not
catch that, since this is a run time bug. It accesses uninitialized
memory until it crashes and writes random data to random I/O locations.

Reported-by (on IRC): Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 util/superiotool/superiotool.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h
index 5583ec5..94918b8 100644
--- a/util/superiotool/superiotool.h
+++ b/util/superiotool/superiotool.h
@@ -247,7 +247,7 @@ static const struct {
 	{probe_idregs_amd,	{0xaa, EOT}},
 #endif
 	{probe_idregs_serverengines,	{0x2e, EOT}},
-	{probe_idregs_infineon,	{0x2e, 0x4e}},
+	{probe_idregs_infineon,	{0x2e, 0x4e, EOT}},
 };
 
 /** Table of functions to print out supported Super I/O chips. */
-- 
1.7.7.3
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From paulepanter at users.sourceforge.net  Tue Dec 20 23:51:56 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Tue, 20 Dec 2011 23:51:56 +0100
Subject: [coreboot] [PATCH] superiotool.h: Add `EOT` to end of entry
In-Reply-To: <1324412001.4397.2.camel@mattotaupa>
References: <1324412001.4397.2.camel@mattotaupa>
Message-ID: <1324421516.4397.9.camel@mattotaupa>

Am Dienstag, den 20.12.2011, 21:13 +0100 schrieb Paul Menzel:
> Date: Mon, 19 Dec 2011 23:50:32 +0100
> 
> This is a fix up for commit 3d1d6bb4 which forgot to add `EOT` at the end.
> 
>         commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576
>         Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
>         Date:   Mon Nov 7 10:56:42 2011 -0600
> 
>             superiotool: add detection and dump of Infineon SLB9635 TPM
> 
> Carl-Daniel explained the continuous integration tool Jenkins did not
> catch that, since this is a run time bug. It accesses uninitialized
> memory until it crashes and writes random data to random I/O locations.
> 
> Reported-by (on IRC): Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
> ---

I have no OpenID account yet and therefore also no Gerrit account. Could
someone please push that patch to Gerrit for me please.

Save my original message as an mbox file.

        git checkout -b superiotool-EOT origin/master
        git am -s path/to/saved/mbox/file
        git push origin # see [1]


Thanks,

Paul


[1] http://www.coreboot.org/Git
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From gerrit at coreboot.org  Wed Dec 21 01:06:17 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 21 Dec 2011 01:06:17 +0100
Subject: [coreboot] Patch merged into coreboot/master: b751de8 Persimmon
	audio codec verb patch.
References: <I067506871e92078d122cf79872363d8937d47e50+0@gerrit.coreboot.org>
Message-ID: <E1Rd9hJ-0007SY-FE@ra.coresystems.de>

the following patch was just integrated into master:
commit b751de894b1a7126b5182fefb9e048c5ffc45597
Author: Marc Jones <marcj303 at gmail.com>
Date:   Wed Dec 14 11:24:00 2011 -0700

    Persimmon audio codec verb patch.
    
    Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
    data is not required for mainboards that use G-Series HDMI. It is also a setting
    the may be boards specific. This fixes issues with Windows audio on Persimmon.
    
    Change-Id: I067506871e92078d122cf79872363d8937d47e50
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Sat Dec 17 01:10:37 2011, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Dec 21 01:06:15 2011, giving +2
See http://review.coreboot.org/490 for details.

-gerrit


From marcj303 at gmail.com  Wed Dec 21 03:28:25 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 20 Dec 2011 19:28:25 -0700
Subject: [coreboot] gerrit/jenkis missing builds.
Message-ID: <CALrs_3i2Nh29QrfksfF95NYseLJYwk_dmi7joh4ZBUBh=M0X7Q@mail.gmail.com>

It looks like these patches didn't get built by jenkins.

http://review.coreboot.org/#change,487
http://review.coreboot.org/#change,488
http://review.coreboot.org/#change,409

Marc

-- 
http://se-eng.com


From patrick at georgi-clan.de  Wed Dec 21 08:26:13 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 21 Dec 2011 08:26:13 +0100
Subject: [coreboot] gerrit/jenkis missing builds.
In-Reply-To: <CALrs_3i2Nh29QrfksfF95NYseLJYwk_dmi7joh4ZBUBh=M0X7Q@mail.gmail.com>
References: <CALrs_3i2Nh29QrfksfF95NYseLJYwk_dmi7joh4ZBUBh=M0X7Q@mail.gmail.com>
Message-ID: <4EF18A15.6020803@georgi-clan.de>

Am 21.12.2011 03:28, schrieb Marc Jones:
> It looks like these patches didn't get built by jenkins.
Thanks for the notice.

> http://review.coreboot.org/#change,487
> http://review.coreboot.org/#change,488
I triggered these manually and will have to look into what happened
there originally.

> http://review.coreboot.org/#change,409
This one got tested, but it was found "unstable" by Jenkins, so it did a
-1 review, with no test result.


Patrick


From gerrit at coreboot.org  Wed Dec 21 12:21:48 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 21 Dec 2011 12:21:48 +0100
Subject: [coreboot] Patch set updated for coreboot: 14cd7a8 Fix multipleVGA
	cards resource conflict on Windows
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
Message-ID: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+4@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/489

-gerrit

commit 14cd7a8f8e165622cb9f537a6b6275d274e5e78e
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Dec 21 20:05:21 2011 +0800

    Fix multipleVGA cards resource conflict on Windows
    
    If multiple VGA-compatible legacy graphic cards decode the IO range
    3B0-3BB, 3C0-3DF and MEM range A00000-BFFFF.
    Windows 7 complain a resource conflict, so only one VGA card can
    works at the same time.
    
    By disable the IO & MEM decode of the second vga graphic device,
    this patch resolved the resource conflict in windows7, multiple
    vga-compatible graphic cards can work together in windows7.
    Please reference PCI spec. section 3.10 in detail.
    
    There is a discuss in coreboot mail list before,
    please reference thread: "how to prevent legacy resource conflictwith   multipleVGA cards"
    
    Linux using VGA Arbiter module(vgaarb) to resolve this resource conflict,
    Please see the following linux dmesg log, more information can be found in
    Linux source dir Documentation/vgaarbiter.txt.
    But it seems that windows don't dealwith this conflict.
    ~# dmesg | grep -i vgaarb
    [    0.774076] vgaarb: device added: PCI:0000:00:01.0,decodes=io+mem,owns=io+mem
    [    0.776065] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,l
    [    0.780051] vgaarb: loaded
    [    0.784049] vgaarb: bridge control possible 0000:01:00.0
    [    0.788050] vgaarb: bridge control possible 0000:00:01.0
    
    For the second legacy graphic device, coreboot already disabled the
    IO and MEM decode in function set_vga_bridge_bits().
    But it will be enabled again in function pci_set_resource(),
    if the second legacy vga-compatible graphic device take any IO/MEM resources.
    
    Following log printed by enable_resources() shows the problem:
    ...snip...
    PCI: 00:00.0 cmd <- 06
    PCI: 00:01.0 subsystem <- 1022/1410
    PCI: 00:01.0 cmd <- 07                <== The first graphic device
    PCI: 00:01.1 subsystem <- 1022/1410
    PCI: 00:01.1 cmd <- 02
    PCI: 00:02.0 bridge ctrl <- 0003
    PCI: 00:02.0 cmd <- 07
    ...snip...
    PCI: 01:00.0 cmd <- 03                <== The second graphic device
    PCI: 01:00.1 cmd <- 02
    PCI: 02:00.0 cmd <- 02
    PCI: 03:00.0 cmd <- 03
    done.
    ...snip...
    
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d
---
 src/devices/pci_device.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 2ccb38a..8270753 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -494,6 +494,26 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
 			dev->command |= PCI_COMMAND_IO;
 		if (resource->flags & IORESOURCE_PCI_BRIDGE)
 			dev->command |= PCI_COMMAND_MASTER;
+
+		/* It isn't safe to enable multiple VGA cards.
+		 * See PCI spec section 3.10.
+		 * The palette snoop bit will be set by the system firmware
+		 * when it detects both a VGA device and a graphics accelerator
+		 * device that are on separate add-in cards on the same bus or
+		 * on the same path but on different buses.
+		 * Either device can be set to snoop and the other will be set
+		 * to positively respond.
+		 */
+#if CONFIG_VGA_BRIDGE_SETUP == 1
+		extern device_t vga_pri;
+		if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
+			(dev != vga_pri)) {
+			if (((vga_pri->class >> 8) == PCI_CLASS_DISPLAY_VGA) &&
+				((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) {
+				dev->command &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+			}
+		}
+#endif
 	}
 
 	/* Get the base address. */


From gerrit at coreboot.org  Wed Dec 21 16:25:22 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 21 Dec 2011 16:25:22 +0100
Subject: [coreboot] Patch merged into coreboot/master: cc2e8ec kbd: wait
	longer for self-test on keyboard reset
References: <I28c8e05bdde61f71b7de084c96bc2447c1b9575e+0@gerrit.coreboot.org>
Message-ID: <E1RdO2k-0002sT-EN@ra.coresystems.de>

the following patch was just integrated into master:
commit cc2e8ec8e1da449915789fe13cc645f23b94669c
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Wed Dec 14 08:40:48 2011 +0100

    kbd: wait longer for self-test on keyboard reset
    
    Some keyboards take pretty long to respond to a reset command, some even
    delay the ACK to the command. To make the keyboard driver more robust,
    increase the timeout for this special command. Also do an interface test
    after the self-test to ensure the keyboard is functioning properly.
    
    Another point is to reenable the keyboard *after* the scancode was set,
    not before. We also set the system bit when enabling the keyboard
    because this seems to be what older operating systems do expect.
    
    One of the problematic keyboards, which will work with this patch
    applied, is the DELL RT7D20. Without the patch an overly optimistic
    operating system, read Linux 2.4, will not recognise the keyboard
    because coreboot didn't fully initialize it.
    
    Change-Id: I28c8e05bdde61f71b7de084c96bc2447c1b9575e
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Wed Dec 21 16:25:20 2011, giving +2
See http://review.coreboot.org/486 for details.

-gerrit


From gerrit at coreboot.org  Wed Dec 21 16:27:03 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 21 Dec 2011 16:27:03 +0100
Subject: [coreboot] Patch merged into coreboot/master: 66ebaa9 Respect
	linker order
References: <I5a5b05e1cab8a2d88ce56c92d9b2f991ca1ee6c0+0@gerrit.coreboot.org>
Message-ID: <E1RdO4N-0003F6-Cz@ra.coresystems.de>

the following patch was just integrated into master:
commit 66ebaa9f670438b7dd4efa80b65830b362729a9b
Author: Christian Ruppert <idl0r at qasl.de>
Date:   Sat Dec 17 21:56:05 2011 +0100

    Respect linker order
    
    Linking fails when using -Wl,--as-needed and/or esp. when forcing --as-needed
    through a compiler specs file.
    A proper compile/link command would look like: $(CC) $(CFLAGS) $(LDFLAGS) -o foo
    $(OBJS) $(LIBS). So the *FLAGS must be passed *before* the objects while the
    libraries/dependencies must be passed *after* the objects.
    For more details see: http://www.gentoo.org/proj/en/qa/asneeded.xml
    
    Change-Id: I5a5b05e1cab8a2d88ce56c92d9b2f991ca1ee6c0
    Signed-off-by: Christian Ruppert <idl0r at qasl.de>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Wed Dec 21 16:26:55 2011, giving +2
See http://review.coreboot.org/494 for details.

-gerrit


From marcj303 at gmail.com  Wed Dec 21 18:55:07 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 21 Dec 2011 10:55:07 -0700
Subject: [coreboot] gerrit/jenkis missing builds.
In-Reply-To: <4EF18A15.6020803@georgi-clan.de>
References: <CALrs_3i2Nh29QrfksfF95NYseLJYwk_dmi7joh4ZBUBh=M0X7Q@mail.gmail.com>
	<4EF18A15.6020803@georgi-clan.de>
Message-ID: <CALrs_3j4hDq3HKfyjYSFAVPQp7+GkZ0OvXSG7nbRiVX-_z2AiQ@mail.gmail.com>

On Wed, Dec 21, 2011 at 12:26 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 21.12.2011 03:28, schrieb Marc Jones:
>> It looks like these patches didn't get built by jenkins.
> Thanks for the notice.
>
>> http://review.coreboot.org/#change,487
>> http://review.coreboot.org/#change,488
> I triggered these manually and will have to look into what happened
> there originally.
>
>> http://review.coreboot.org/#change,409
> This one got tested, but it was found "unstable" by Jenkins, so it did a
> -1 review, with no test result.

Thanks Patrick,
What is a difference between Jenkis setting a -1 "unstable" vs a "red
x" in verified?


Marc
-- 
http://se-eng.com


From patrick at georgi-clan.de  Wed Dec 21 19:50:24 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 21 Dec 2011 19:50:24 +0100
Subject: [coreboot] gerrit/jenkis missing builds.
In-Reply-To: <CALrs_3j4hDq3HKfyjYSFAVPQp7+GkZ0OvXSG7nbRiVX-_z2AiQ@mail.gmail.com>
References: <CALrs_3i2Nh29QrfksfF95NYseLJYwk_dmi7joh4ZBUBh=M0X7Q@mail.gmail.com>
	<4EF18A15.6020803@georgi-clan.de>
	<CALrs_3j4hDq3HKfyjYSFAVPQp7+GkZ0OvXSG7nbRiVX-_z2AiQ@mail.gmail.com>
Message-ID: <4EF22A70.4010806@georgi-clan.de>

Am 21.12.2011 18:55, schrieb Marc Jones:
> What is a difference between Jenkis setting a -1 "unstable" vs a "red
> x" in verified?
"verified -1" is when any build fails
"unstable" is when the builds report success but the test harness
reports issues.

unstable will only happen for us when messing around with abuild and the
build system (such as with the patch in question).


Patrick


From gerrit at coreboot.org  Wed Dec 21 21:51:44 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Wed, 21 Dec 2011 21:51:44 +0100
Subject: [coreboot] New patch to review for coreboot: 9451dd1 Cleanup needed
	to make coreboot converge with linux driver
References: <Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a+0@gerrit.coreboot.org>
Message-ID: <Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/495

-gerrit

commit 9451dd17a684e5a8e438fb541f52775ade0f5a40
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Wed Dec 21 13:29:53 2011 -0700

    Cleanup needed to make coreboot converge with linux driver
    
    Having submitted changes upstream to add a linux kernel library for
    Coreboot, I was given a list of changes to make. While all good
    suggestions, they would have caused the linux version to diverge
    significantly with the original coreboot code from which it was
    cloned.
    
    Those changes are:
    
    * more use of inline functions rather than macros (they avoid
      typecasts);
    * convenience functions to access the motherboard vendor and part #
      from the parsed sysinfo.
    * use of void * for pointers to untyped memory;
    * eliminate unnecessary casts;
    * pass end-boundary of E820 memory region when parsing coreboot
      tables (in case of corruption);
    * add missing phys_to_virt() when handling FORWARD records;
    * save mainboard record pointer into sysinfo structure for later
      retrieval;
    * pass through return value from get_coreboot_info() in
      lib_get_sysinfo();
    
    Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |   12 ++--
 payloads/libpayload/arch/i386/coreboot.c      |   66 +++++++++++++++----------
 payloads/libpayload/arch/i386/sysinfo.c       |    8 ++-
 payloads/libpayload/include/coreboot_tables.h |   33 ++++++++----
 payloads/libpayload/include/libpayload.h      |    2 +-
 payloads/libpayload/include/sysinfo.h         |    3 +
 6 files changed, 77 insertions(+), 47 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index dd589ac..f298595 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <coreboot_tables.h>
 #include "coreinfo.h"
+#include <coreboot_tables.h>
 
 #ifdef CONFIG_MODULE_COREBOOT
 
@@ -112,9 +112,9 @@ int coreboot_module_redraw(WINDOW *win)
 		}
 
 		wprintw(win, "%16.16llx - %16.16llx",
-			UNPACK_CB64(cb_info.range[i].start),
-			UNPACK_CB64(cb_info.range[i].start) +
-			UNPACK_CB64(cb_info.range[i].size) - 1);
+			cb_unpack64(cb_info.range[i].start),
+			cb_unpack64(cb_info.range[i].start) +
+			cb_unpack64(cb_info.range[i].size) - 1);
 	}
 
 	return 0;
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31);
-	strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31);
+	strncpy(cb_info.vendor, (const char *)cb_mb_vendor_string(mb), 31);
+	strncpy(cb_info.part, (const char *)cb_mb_part_string(mb), 31);
 }
 
 static void parse_strings(unsigned char *ptr)
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 365445e..e49cba8 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -42,9 +42,9 @@
 /* === Parsing code === */
 /* This is the generic parsing code. */
 
-static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_memory(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_memory *mem = (struct cb_memory *)ptr;
+	struct cb_memory *mem = ptr;
 	int count = MEM_RANGE_COUNT(mem);
 	int i;
 
@@ -54,8 +54,7 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 	info->n_memranges = 0;
 
 	for (i = 0; i < count; i++) {
-		struct cb_memory_range *range =
-		    (struct cb_memory_range *)MEM_RANGE_PTR(mem, i);
+		struct cb_memory_range *range = MEM_RANGE_PTR(mem, i);
 
 #ifdef CONFIG_MEMMAP_RAM_ONLY
 		if (range->type != CB_MEM_RAM)
@@ -63,10 +62,10 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 #endif
 
 		info->memrange[info->n_memranges].base =
-		    UNPACK_CB64(range->start);
+		    cb_unpack64(range->start);
 
 		info->memrange[info->n_memranges].size =
-		    UNPACK_CB64(range->size);
+		    cb_unpack64(range->size);
 
 		info->memrange[info->n_memranges].type = range->type;
 
@@ -74,29 +73,29 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 	}
 }
 
-static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_serial(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_serial *ser = (struct cb_serial *)ptr;
+	struct cb_serial *ser = ptr;
 	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
 		return;
 	info->ser_ioport = ser->baseaddr;
 }
 
-static void cb_parse_version(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_version(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_string *ver = (struct cb_string *)ptr;
+	struct cb_string *ver = ptr;
 	info->cb_version = (char *)ver->string;
 }
 
 #ifdef CONFIG_NVRAM
-static void cb_parse_optiontable(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info)
 {
-	info->option_table = (struct cb_cmos_option_table *)ptr;
+	info->option_table = ptr;
 }
 
-static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_checksum(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_cmos_checksum *cmos_cksum = (struct cb_cmos_checksum *)ptr;
+	struct cb_cmos_checksum *cmos_cksum = ptr;
 	info->cmos_range_start = cmos_cksum->range_start;
 	info->cmos_range_end = cmos_cksum->range_end;
 	info->cmos_checksum_location = cmos_cksum->location;
@@ -104,39 +103,42 @@ static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
 #endif
 
 #ifdef CONFIG_COREBOOT_VIDEO_CONSOLE
-static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 {
-	info->framebuffer = (struct cb_framebuffer *)ptr;
+	info->framebuffer = ptr;
 }
 #endif
 
-static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
+static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 {
 	struct cb_header *header;
-	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr = addr;
+	void *forward;
 	int i;
 
-	for (i = 0; i < len; i += 16, ptr += 16) {
+	for (i = 0; (void *)ptr < end; i += 16, ptr += 16) {
 		header = (struct cb_header *)ptr;
 		if (!strncmp((const char *)header->signature, "LBIO", 4))
 			break;
 	}
 
 	/* We walked the entire space and didn't find anything. */
-	if (i >= len)
+	if ((void *)ptr >= end)
 		return -1;
 
 	if (!header->table_bytes)
 		return 0;
 
 	/* Make sure the checksums match. */
-	if (ipchksum((u16 *) header, sizeof(*header)) != 0)
+	if (cb_checksum(header, sizeof(*header)) != 0)
 		return -1;
 
-	if (ipchksum((u16 *) (ptr + sizeof(*header)),
+	if (cb_checksum((ptr + sizeof(*header)),
 		     header->table_bytes) != header->table_checksum)
 		return -1;
 
+	info->header = header;
+
 	/* Now, walk the tables. */
 	ptr += header->header_bytes;
 
@@ -146,8 +148,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		/* We only care about a few tags here (maybe more later). */
 		switch (rec->tag) {
 		case CB_TAG_FORWARD:
-			return cb_parse_header((void *)(unsigned long)((struct cb_forward *)rec)->forward, len, info);
-			continue;
+			forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward);
+			return cb_parse_header(forward, forward + 0x1000, info);
 		case CB_TAG_MEMORY:
 			cb_parse_memory(ptr, info);
 			break;
@@ -172,9 +174,16 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 			cb_parse_framebuffer(ptr, info);
 			break;
 #endif
+
+		case CB_TAG_MAINBOARD:
+			info->mainboard = (struct cb_mainboard *)ptr;
+			break;
 		}
 
 		ptr += rec->size;
+
+		if ((void *)ptr >= end)
+			return -1;
 	}
 
 	return 1;
@@ -185,10 +194,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 
 int get_coreboot_info(struct sysinfo_t *info)
 {
-	int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
+	void *base = phys_to_virt(0x00000000);
+	int ret = cb_parse_header(base, base + 0x1000, info);
 
-	if (ret != 1)
-		ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
+	if (ret != 1) {
+		base = phys_to_virt(0x000f0000);
+		ret = cb_parse_header(base, base + 0x1000, info);
+	}
 
 	return (ret == 1) ? 0 : -1;
 }
diff --git a/payloads/libpayload/arch/i386/sysinfo.c b/payloads/libpayload/arch/i386/sysinfo.c
index 599a811..6c1ef3f 100644
--- a/payloads/libpayload/arch/i386/sysinfo.c
+++ b/payloads/libpayload/arch/i386/sysinfo.c
@@ -45,8 +45,10 @@ struct sysinfo_t lib_sysinfo = {
 #endif
 };
 
-void lib_get_sysinfo(void)
+int lib_get_sysinfo(void)
 {
+	int ret;
+
 	/* Get the CPU speed (for delays). */
 	lib_sysinfo.cpu_khz = get_cpu_speed();
 
@@ -59,7 +61,7 @@ void lib_get_sysinfo(void)
 	/* Get information from the coreboot tables,
 	 * if they exist */
 
-	get_coreboot_info(&lib_sysinfo);
+	ret = get_coreboot_info(&lib_sysinfo);
 
 	if (!lib_sysinfo.n_memranges) {
 		/* If we can't get a good memory range, use the default. */
@@ -73,4 +75,6 @@ void lib_get_sysinfo(void)
 		lib_sysinfo.memrange[1].size = 31 * 1024 * 1024;
 		lib_sysinfo.memrange[1].type = CB_MEM_RAM;
 	}
+
+	return ret;
 }
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index d342c99..706e714 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -216,22 +216,33 @@ struct	cb_cmos_checksum {
 	u32 type;
 };
 
+static inline u16 cb_checksum(const void *ptr, unsigned len)
+{
+	return ipchksum(ptr, len);
+}
+
+static inline const u8 *cb_mb_vendor_string(const struct cb_mainboard *cbm)
+{
+	return cbm->strings + cbm->vendor_idx;
+}
+
+static inline const u8 *cb_mb_part_string(const struct cb_mainboard *cbm)
+{
+	return cbm->strings + cbm->part_number_idx;
+}
+
+static inline u64 cb_unpack64(struct cbuint64 val)
+{
+	return (((u64) val.hi) << 32) | val.lo;
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
 	(((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
 
 #define MEM_RANGE_PTR(_rec, _idx) \
-	(((u8 *) (_rec)) + sizeof(*(_rec)) \
-	+ (sizeof((_rec)->map[0]) * (_idx)))
-
-#define MB_VENDOR_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
-
-#define MB_PART_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
-
-#define UNPACK_CB64(_in) \
-	( (((u64) _in.hi) << 32) | _in.lo )
+	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
+		 + (sizeof((_rec)->map[0]) * (_idx)))
 
 #endif
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 8c8abc4..d9f7d21 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -369,7 +369,7 @@ int sysinfo_have_multiboot(unsigned long *addr);
 int get_coreboot_info(struct sysinfo_t *info);
 int get_multiboot_info(struct sysinfo_t *info);
 
-void lib_get_sysinfo(void);
+int lib_get_sysinfo(void);
 
 /* Timer functions - defined by each architecture. */
 unsigned int get_cpu_speed(void);
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c1d2002..778dfe9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -56,6 +56,9 @@ struct sysinfo_t {
 	struct cb_framebuffer *framebuffer;
 
 	unsigned long *mbtable; /** Pointer to the multiboot table */
+
+	struct cb_header *header;
+	struct cb_mainboard *mainboard;
 };
 
 extern struct sysinfo_t lib_sysinfo;


From gerrit at coreboot.org  Wed Dec 21 22:11:51 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 21 Dec 2011 22:11:51 +0100
Subject: [coreboot] Patch merged into coreboot/master: b4145dc Add RS780
	defaut graphics ID to AMD Mahogany mainboard.
References: <Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a+0@gerrit.coreboot.org>
Message-ID: <E1RdTS3-0003Tn-QE@ra.coresystems.de>

the following patch was just integrated into master:
commit b4145dcaed06d31ba8c85270e25b810448cd0ea1
Author: Marc Jones <marcj303 at gmail.com>
Date:   Wed Dec 14 15:59:02 2011 -0700

    Add RS780 defaut graphics ID to AMD Mahogany mainboard.
    
    Added the default ID to the mainboard Kconfig.
    
    Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Dec 21 08:51:51 2011, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Dec 21 01:06:42 2011, giving +2
See http://review.coreboot.org/488 for details.

-gerrit


From gerrit at coreboot.org  Wed Dec 21 22:28:51 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Wed, 21 Dec 2011 22:28:51 +0100
Subject: [coreboot] Patch set updated for coreboot: ebfafa0 Cleanup needed
	to make coreboot converge with linux driver
References: <Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a+0@gerrit.coreboot.org>
Message-ID: <Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a+2@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/495

-gerrit

commit ebfafa07bc5c92d4c14b890e245e57124d1b7edb
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Wed Dec 21 13:29:53 2011 -0700

    Cleanup needed to make coreboot converge with linux driver
    
    Having submitted changes upstream to add a linux kernel library for
    Coreboot, I was given a list of changes to make. While all good
    suggestions, they would have caused the linux version to diverge
    significantly with the original coreboot code from which it was
    cloned.
    
    Those changes are:
    
    * more use of inline functions rather than macros (they avoid
      typecasts);
    * convenience functions to access the motherboard vendor and part #
      from the parsed sysinfo.
    * use of void * for pointers to untyped memory;
    * eliminate unnecessary casts;
    * pass end-boundary of E820 memory region when parsing coreboot
      tables (in case of corruption);
    * add missing phys_to_virt() when handling FORWARD records;
    * save mainboard record pointer into sysinfo structure for later
      retrieval;
    * pass through return value from get_coreboot_info() in
      lib_get_sysinfo();
    
    The fifth change merits some more detail: on some of the systems I
    develop on the CB table gets indirected to by a CB_FORWARD record.
    When the final table (and not the initial stub containing the
    CB_FORWARD) is found, it is tucked up in the last bytes of the
    E820 region. Passing 0x1000 as the length might not always be
    correct if the table begins at less than 0x1000 bytes from the end
    of that region.  Explicitly passing in the region's end is a more
    accurate semantic.
    
    Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |   12 ++--
 payloads/libpayload/arch/i386/coreboot.c      |   66 +++++++++++++++----------
 payloads/libpayload/arch/i386/sysinfo.c       |    8 ++-
 payloads/libpayload/include/coreboot_tables.h |   33 ++++++++----
 payloads/libpayload/include/libpayload.h      |    2 +-
 payloads/libpayload/include/sysinfo.h         |    3 +
 6 files changed, 77 insertions(+), 47 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index dd589ac..f298595 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <coreboot_tables.h>
 #include "coreinfo.h"
+#include <coreboot_tables.h>
 
 #ifdef CONFIG_MODULE_COREBOOT
 
@@ -112,9 +112,9 @@ int coreboot_module_redraw(WINDOW *win)
 		}
 
 		wprintw(win, "%16.16llx - %16.16llx",
-			UNPACK_CB64(cb_info.range[i].start),
-			UNPACK_CB64(cb_info.range[i].start) +
-			UNPACK_CB64(cb_info.range[i].size) - 1);
+			cb_unpack64(cb_info.range[i].start),
+			cb_unpack64(cb_info.range[i].start) +
+			cb_unpack64(cb_info.range[i].size) - 1);
 	}
 
 	return 0;
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31);
-	strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31);
+	strncpy(cb_info.vendor, (const char *)cb_mb_vendor_string(mb), 31);
+	strncpy(cb_info.part, (const char *)cb_mb_part_string(mb), 31);
 }
 
 static void parse_strings(unsigned char *ptr)
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 365445e..e49cba8 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -42,9 +42,9 @@
 /* === Parsing code === */
 /* This is the generic parsing code. */
 
-static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_memory(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_memory *mem = (struct cb_memory *)ptr;
+	struct cb_memory *mem = ptr;
 	int count = MEM_RANGE_COUNT(mem);
 	int i;
 
@@ -54,8 +54,7 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 	info->n_memranges = 0;
 
 	for (i = 0; i < count; i++) {
-		struct cb_memory_range *range =
-		    (struct cb_memory_range *)MEM_RANGE_PTR(mem, i);
+		struct cb_memory_range *range = MEM_RANGE_PTR(mem, i);
 
 #ifdef CONFIG_MEMMAP_RAM_ONLY
 		if (range->type != CB_MEM_RAM)
@@ -63,10 +62,10 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 #endif
 
 		info->memrange[info->n_memranges].base =
-		    UNPACK_CB64(range->start);
+		    cb_unpack64(range->start);
 
 		info->memrange[info->n_memranges].size =
-		    UNPACK_CB64(range->size);
+		    cb_unpack64(range->size);
 
 		info->memrange[info->n_memranges].type = range->type;
 
@@ -74,29 +73,29 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 	}
 }
 
-static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_serial(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_serial *ser = (struct cb_serial *)ptr;
+	struct cb_serial *ser = ptr;
 	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
 		return;
 	info->ser_ioport = ser->baseaddr;
 }
 
-static void cb_parse_version(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_version(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_string *ver = (struct cb_string *)ptr;
+	struct cb_string *ver = ptr;
 	info->cb_version = (char *)ver->string;
 }
 
 #ifdef CONFIG_NVRAM
-static void cb_parse_optiontable(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info)
 {
-	info->option_table = (struct cb_cmos_option_table *)ptr;
+	info->option_table = ptr;
 }
 
-static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_checksum(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_cmos_checksum *cmos_cksum = (struct cb_cmos_checksum *)ptr;
+	struct cb_cmos_checksum *cmos_cksum = ptr;
 	info->cmos_range_start = cmos_cksum->range_start;
 	info->cmos_range_end = cmos_cksum->range_end;
 	info->cmos_checksum_location = cmos_cksum->location;
@@ -104,39 +103,42 @@ static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
 #endif
 
 #ifdef CONFIG_COREBOOT_VIDEO_CONSOLE
-static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 {
-	info->framebuffer = (struct cb_framebuffer *)ptr;
+	info->framebuffer = ptr;
 }
 #endif
 
-static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
+static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 {
 	struct cb_header *header;
-	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr = addr;
+	void *forward;
 	int i;
 
-	for (i = 0; i < len; i += 16, ptr += 16) {
+	for (i = 0; (void *)ptr < end; i += 16, ptr += 16) {
 		header = (struct cb_header *)ptr;
 		if (!strncmp((const char *)header->signature, "LBIO", 4))
 			break;
 	}
 
 	/* We walked the entire space and didn't find anything. */
-	if (i >= len)
+	if ((void *)ptr >= end)
 		return -1;
 
 	if (!header->table_bytes)
 		return 0;
 
 	/* Make sure the checksums match. */
-	if (ipchksum((u16 *) header, sizeof(*header)) != 0)
+	if (cb_checksum(header, sizeof(*header)) != 0)
 		return -1;
 
-	if (ipchksum((u16 *) (ptr + sizeof(*header)),
+	if (cb_checksum((ptr + sizeof(*header)),
 		     header->table_bytes) != header->table_checksum)
 		return -1;
 
+	info->header = header;
+
 	/* Now, walk the tables. */
 	ptr += header->header_bytes;
 
@@ -146,8 +148,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		/* We only care about a few tags here (maybe more later). */
 		switch (rec->tag) {
 		case CB_TAG_FORWARD:
-			return cb_parse_header((void *)(unsigned long)((struct cb_forward *)rec)->forward, len, info);
-			continue;
+			forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward);
+			return cb_parse_header(forward, forward + 0x1000, info);
 		case CB_TAG_MEMORY:
 			cb_parse_memory(ptr, info);
 			break;
@@ -172,9 +174,16 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 			cb_parse_framebuffer(ptr, info);
 			break;
 #endif
+
+		case CB_TAG_MAINBOARD:
+			info->mainboard = (struct cb_mainboard *)ptr;
+			break;
 		}
 
 		ptr += rec->size;
+
+		if ((void *)ptr >= end)
+			return -1;
 	}
 
 	return 1;
@@ -185,10 +194,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 
 int get_coreboot_info(struct sysinfo_t *info)
 {
-	int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
+	void *base = phys_to_virt(0x00000000);
+	int ret = cb_parse_header(base, base + 0x1000, info);
 
-	if (ret != 1)
-		ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
+	if (ret != 1) {
+		base = phys_to_virt(0x000f0000);
+		ret = cb_parse_header(base, base + 0x1000, info);
+	}
 
 	return (ret == 1) ? 0 : -1;
 }
diff --git a/payloads/libpayload/arch/i386/sysinfo.c b/payloads/libpayload/arch/i386/sysinfo.c
index 599a811..6c1ef3f 100644
--- a/payloads/libpayload/arch/i386/sysinfo.c
+++ b/payloads/libpayload/arch/i386/sysinfo.c
@@ -45,8 +45,10 @@ struct sysinfo_t lib_sysinfo = {
 #endif
 };
 
-void lib_get_sysinfo(void)
+int lib_get_sysinfo(void)
 {
+	int ret;
+
 	/* Get the CPU speed (for delays). */
 	lib_sysinfo.cpu_khz = get_cpu_speed();
 
@@ -59,7 +61,7 @@ void lib_get_sysinfo(void)
 	/* Get information from the coreboot tables,
 	 * if they exist */
 
-	get_coreboot_info(&lib_sysinfo);
+	ret = get_coreboot_info(&lib_sysinfo);
 
 	if (!lib_sysinfo.n_memranges) {
 		/* If we can't get a good memory range, use the default. */
@@ -73,4 +75,6 @@ void lib_get_sysinfo(void)
 		lib_sysinfo.memrange[1].size = 31 * 1024 * 1024;
 		lib_sysinfo.memrange[1].type = CB_MEM_RAM;
 	}
+
+	return ret;
 }
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index d342c99..706e714 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -216,22 +216,33 @@ struct	cb_cmos_checksum {
 	u32 type;
 };
 
+static inline u16 cb_checksum(const void *ptr, unsigned len)
+{
+	return ipchksum(ptr, len);
+}
+
+static inline const u8 *cb_mb_vendor_string(const struct cb_mainboard *cbm)
+{
+	return cbm->strings + cbm->vendor_idx;
+}
+
+static inline const u8 *cb_mb_part_string(const struct cb_mainboard *cbm)
+{
+	return cbm->strings + cbm->part_number_idx;
+}
+
+static inline u64 cb_unpack64(struct cbuint64 val)
+{
+	return (((u64) val.hi) << 32) | val.lo;
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
 	(((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
 
 #define MEM_RANGE_PTR(_rec, _idx) \
-	(((u8 *) (_rec)) + sizeof(*(_rec)) \
-	+ (sizeof((_rec)->map[0]) * (_idx)))
-
-#define MB_VENDOR_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
-
-#define MB_PART_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
-
-#define UNPACK_CB64(_in) \
-	( (((u64) _in.hi) << 32) | _in.lo )
+	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
+		 + (sizeof((_rec)->map[0]) * (_idx)))
 
 #endif
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 8c8abc4..d9f7d21 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -369,7 +369,7 @@ int sysinfo_have_multiboot(unsigned long *addr);
 int get_coreboot_info(struct sysinfo_t *info);
 int get_multiboot_info(struct sysinfo_t *info);
 
-void lib_get_sysinfo(void);
+int lib_get_sysinfo(void);
 
 /* Timer functions - defined by each architecture. */
 unsigned int get_cpu_speed(void);
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c1d2002..778dfe9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -56,6 +56,9 @@ struct sysinfo_t {
 	struct cb_framebuffer *framebuffer;
 
 	unsigned long *mbtable; /** Pointer to the multiboot table */
+
+	struct cb_header *header;
+	struct cb_mainboard *mainboard;
 };
 
 extern struct sysinfo_t lib_sysinfo;


From gerrit at coreboot.org  Thu Dec 22 00:56:36 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 22 Dec 2011 00:56:36 +0100
Subject: [coreboot] Patch merged into coreboot/master: 7b5f093
	south_station: Enable GNB hd audio
References: <I013c2c15ee56a7b134d980da1aa1856778a1eb4c+0@gerrit.coreboot.org>
Message-ID: <E1RdW1U-0006Td-AG@ra.coresystems.de>

the following patch was just integrated into master:
commit 7b5f093920dc0918eb620bac184588333e7ef7cc
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Nov 23 15:04:13 2011 +0800

    south_station: Enable GNB hd audio
    
    Enable HD audio over HDMI.
    Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed.
    
    Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>

Build-Tested: build bot (Jenkins) at Wed Nov 23 07:43:19 2011, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Tue Dec 20 07:28:39 2011, giving +2
See http://review.coreboot.org/450 for details.

-gerrit


From gerrit at coreboot.org  Thu Dec 22 04:34:03 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Thu, 22 Dec 2011 04:34:03 +0100
Subject: [coreboot] Patch set updated for coreboot: 42bde27 F14 mainboard:
	update acpi interrupt routing in pic and apic mode
References: <I4b6e0fce8d34637c03de8ebfdadea008c98e193b+0@gerrit.coreboot.org>
Message-ID: <I4b6e0fce8d34637c03de8ebfdadea008c98e193b+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/452

-gerrit

commit 42bde27e1474bd45ef0d727ef7a874f1eebfd3ab
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Dec 22 12:18:37 2011 +0800

    F14 mainboard: update acpi interrupt routing in pic and apic mode
    
    Add interrupt routing for APU GNB internal Graphic and HD audio device, and
    other pcie bridge device in GNB.
    
    south_station, union_station, inagua, persimmon and e350m1 mainboard
    are included herein.
    
    Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/acpi/routing.asl        |   59 ++++++++++++---------
 src/mainboard/amd/persimmon/acpi/routing.asl     |   59 ++++++++++++---------
 src/mainboard/amd/south_station/acpi/routing.asl |   59 ++++++++++++---------
 src/mainboard/amd/union_station/acpi/routing.asl |   59 ++++++++++++---------
 src/mainboard/asrock/e350m1/acpi/routing.asl     |   59 ++++++++++++---------
 5 files changed, 170 insertions(+), 125 deletions(-)

diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl
index cb50394..d7e4687 100644
--- a/src/mainboard/amd/inagua/acpi/routing.asl
+++ b/src/mainboard/amd/inagua/acpi/routing.asl
@@ -31,22 +31,28 @@ Scope(\_SB) {
 		/* NB devices */
 		/* Bus 0, Dev 0 - RS780 Host Controller */
 		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, INTC, 0 },
+		Package(){0x0001FFFF, 1, INTD, 0 },
 		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
 		Package(){0x0002FFFF, 0, INTC, 0 },
 		Package(){0x0002FFFF, 1, INTD, 0 },
 		Package(){0x0002FFFF, 2, INTA, 0 },
 		Package(){0x0002FFFF, 3, INTB, 0 },
 		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, INTD, 0 },
+		Package(){0x0003FFFF, 1, INTA, 0 },
+		Package(){0x0003FFFF, 2, INTB, 0 },
+		Package(){0x0003FFFF, 3, INTC, 0 },
 		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
 		Package(){0x0004FFFF, 0, INTA, 0 },
 		Package(){0x0004FFFF, 1, INTB, 0 },
 		Package(){0x0004FFFF, 2, INTC, 0 },
 		Package(){0x0004FFFF, 3, INTD, 0 },
 		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
-		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
-		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
-		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		Package(){0x0005FFFF, 0, INTB, 0 },
+		Package(){0x0005FFFF, 1, INTC, 0 },
+		Package(){0x0005FFFF, 2, INTD, 0 },
+		Package(){0x0005FFFF, 3, INTA, 0 },
 		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
 		Package(){0x0006FFFF, 0, INTC, 0 },
 		Package(){0x0006FFFF, 1, INTD, 0 },
@@ -126,41 +132,44 @@ Scope(\_SB) {
 
 		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
 		Package(){0x0003FFFF, 0, 0, 19 },
+		Package(){0x0003FFFF, 1, 0, 16 },
+		Package(){0x0003FFFF, 2, 0, 17 },
+		Package(){0x0003FFFF, 3, 0, 18 },
 
 		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
 		Package(){0x0004FFFF, 0, 0, 16 },
-		/* Package(){0x0004FFFF, 1, 0, 17 }, */
-		/* Package(){0x0004FFFF, 2, 0, 18 }, */
-		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+		Package(){0x0004FFFF, 1, 0, 17 },
+		Package(){0x0004FFFF, 2, 0, 18 },
+		Package(){0x0004FFFF, 3, 0, 19 },
 
 		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, 0, 17 }, */
-		/* Package(){0x0005FFFF, 1, 0, 18 }, */
-		/* Package(){0x0005FFFF, 2, 0, 19 }, */
-		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+		Package(){0x0005FFFF, 0, 0, 17 },
+		Package(){0x0005FFFF, 1, 0, 18 },
+		Package(){0x0005FFFF, 2, 0, 19 },
+		Package(){0x0005FFFF, 3, 0, 16 },
 
 		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		/* Package(){0x0006FFFF, 0, 0, 18 }, */
-		/* Package(){0x0006FFFF, 1, 0, 19 }, */
-		/* Package(){0x0006FFFF, 2, 0, 16 }, */
-		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+		Package(){0x0006FFFF, 0, 0, 18 },
+		Package(){0x0006FFFF, 1, 0, 19 },
+		Package(){0x0006FFFF, 2, 0, 16 },
+		Package(){0x0006FFFF, 3, 0, 17 },
 
 		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		/* Package(){0x0007FFFF, 0, 0, 19 }, */
-		/* Package(){0x0007FFFF, 1, 0, 16 }, */
-		/* Package(){0x0007FFFF, 2, 0, 17 }, */
-		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+		Package(){0x0007FFFF, 0, 0, 19 },
+		Package(){0x0007FFFF, 1, 0, 16 },
+		Package(){0x0007FFFF, 2, 0, 17 },
+		Package(){0x0007FFFF, 3, 0, 18 },
 
 		/* Bus 0, Dev 9 - PCIe Bridge for network card */
 		Package(){0x0009FFFF, 0, 0, 17 },
-		/* Package(){0x0009FFFF, 1, 0, 16 }, */
-		/* Package(){0x0009FFFF, 2, 0, 17 }, */
-		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		Package(){0x0009FFFF, 1, 0, 16 },
+		Package(){0x0009FFFF, 2, 0, 17 },
+		Package(){0x0009FFFF, 3, 0, 18 },
 		/* Bus 0, Dev A - PCIe Bridge for network card */
 		Package(){0x000AFFFF, 0, 0, 18 },
-		/* Package(){0x000AFFFF, 1, 0, 16 }, */
-		/* Package(){0x000AFFFF, 2, 0, 17 }, */
-		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		Package(){0x000AFFFF, 1, 0, 16 },
+		Package(){0x000AFFFF, 2, 0, 17 },
+		Package(){0x000AFFFF, 3, 0, 18 },
 		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
 
 		/* SB devices in APIC mode */
diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl
index cb50394..d7e4687 100644
--- a/src/mainboard/amd/persimmon/acpi/routing.asl
+++ b/src/mainboard/amd/persimmon/acpi/routing.asl
@@ -31,22 +31,28 @@ Scope(\_SB) {
 		/* NB devices */
 		/* Bus 0, Dev 0 - RS780 Host Controller */
 		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, INTC, 0 },
+		Package(){0x0001FFFF, 1, INTD, 0 },
 		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
 		Package(){0x0002FFFF, 0, INTC, 0 },
 		Package(){0x0002FFFF, 1, INTD, 0 },
 		Package(){0x0002FFFF, 2, INTA, 0 },
 		Package(){0x0002FFFF, 3, INTB, 0 },
 		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, INTD, 0 },
+		Package(){0x0003FFFF, 1, INTA, 0 },
+		Package(){0x0003FFFF, 2, INTB, 0 },
+		Package(){0x0003FFFF, 3, INTC, 0 },
 		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
 		Package(){0x0004FFFF, 0, INTA, 0 },
 		Package(){0x0004FFFF, 1, INTB, 0 },
 		Package(){0x0004FFFF, 2, INTC, 0 },
 		Package(){0x0004FFFF, 3, INTD, 0 },
 		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
-		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
-		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
-		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		Package(){0x0005FFFF, 0, INTB, 0 },
+		Package(){0x0005FFFF, 1, INTC, 0 },
+		Package(){0x0005FFFF, 2, INTD, 0 },
+		Package(){0x0005FFFF, 3, INTA, 0 },
 		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
 		Package(){0x0006FFFF, 0, INTC, 0 },
 		Package(){0x0006FFFF, 1, INTD, 0 },
@@ -126,41 +132,44 @@ Scope(\_SB) {
 
 		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
 		Package(){0x0003FFFF, 0, 0, 19 },
+		Package(){0x0003FFFF, 1, 0, 16 },
+		Package(){0x0003FFFF, 2, 0, 17 },
+		Package(){0x0003FFFF, 3, 0, 18 },
 
 		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
 		Package(){0x0004FFFF, 0, 0, 16 },
-		/* Package(){0x0004FFFF, 1, 0, 17 }, */
-		/* Package(){0x0004FFFF, 2, 0, 18 }, */
-		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+		Package(){0x0004FFFF, 1, 0, 17 },
+		Package(){0x0004FFFF, 2, 0, 18 },
+		Package(){0x0004FFFF, 3, 0, 19 },
 
 		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, 0, 17 }, */
-		/* Package(){0x0005FFFF, 1, 0, 18 }, */
-		/* Package(){0x0005FFFF, 2, 0, 19 }, */
-		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+		Package(){0x0005FFFF, 0, 0, 17 },
+		Package(){0x0005FFFF, 1, 0, 18 },
+		Package(){0x0005FFFF, 2, 0, 19 },
+		Package(){0x0005FFFF, 3, 0, 16 },
 
 		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		/* Package(){0x0006FFFF, 0, 0, 18 }, */
-		/* Package(){0x0006FFFF, 1, 0, 19 }, */
-		/* Package(){0x0006FFFF, 2, 0, 16 }, */
-		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+		Package(){0x0006FFFF, 0, 0, 18 },
+		Package(){0x0006FFFF, 1, 0, 19 },
+		Package(){0x0006FFFF, 2, 0, 16 },
+		Package(){0x0006FFFF, 3, 0, 17 },
 
 		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		/* Package(){0x0007FFFF, 0, 0, 19 }, */
-		/* Package(){0x0007FFFF, 1, 0, 16 }, */
-		/* Package(){0x0007FFFF, 2, 0, 17 }, */
-		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+		Package(){0x0007FFFF, 0, 0, 19 },
+		Package(){0x0007FFFF, 1, 0, 16 },
+		Package(){0x0007FFFF, 2, 0, 17 },
+		Package(){0x0007FFFF, 3, 0, 18 },
 
 		/* Bus 0, Dev 9 - PCIe Bridge for network card */
 		Package(){0x0009FFFF, 0, 0, 17 },
-		/* Package(){0x0009FFFF, 1, 0, 16 }, */
-		/* Package(){0x0009FFFF, 2, 0, 17 }, */
-		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		Package(){0x0009FFFF, 1, 0, 16 },
+		Package(){0x0009FFFF, 2, 0, 17 },
+		Package(){0x0009FFFF, 3, 0, 18 },
 		/* Bus 0, Dev A - PCIe Bridge for network card */
 		Package(){0x000AFFFF, 0, 0, 18 },
-		/* Package(){0x000AFFFF, 1, 0, 16 }, */
-		/* Package(){0x000AFFFF, 2, 0, 17 }, */
-		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		Package(){0x000AFFFF, 1, 0, 16 },
+		Package(){0x000AFFFF, 2, 0, 17 },
+		Package(){0x000AFFFF, 3, 0, 18 },
 		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
 
 		/* SB devices in APIC mode */
diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl
index cb50394..d7e4687 100644
--- a/src/mainboard/amd/south_station/acpi/routing.asl
+++ b/src/mainboard/amd/south_station/acpi/routing.asl
@@ -31,22 +31,28 @@ Scope(\_SB) {
 		/* NB devices */
 		/* Bus 0, Dev 0 - RS780 Host Controller */
 		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, INTC, 0 },
+		Package(){0x0001FFFF, 1, INTD, 0 },
 		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
 		Package(){0x0002FFFF, 0, INTC, 0 },
 		Package(){0x0002FFFF, 1, INTD, 0 },
 		Package(){0x0002FFFF, 2, INTA, 0 },
 		Package(){0x0002FFFF, 3, INTB, 0 },
 		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, INTD, 0 },
+		Package(){0x0003FFFF, 1, INTA, 0 },
+		Package(){0x0003FFFF, 2, INTB, 0 },
+		Package(){0x0003FFFF, 3, INTC, 0 },
 		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
 		Package(){0x0004FFFF, 0, INTA, 0 },
 		Package(){0x0004FFFF, 1, INTB, 0 },
 		Package(){0x0004FFFF, 2, INTC, 0 },
 		Package(){0x0004FFFF, 3, INTD, 0 },
 		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
-		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
-		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
-		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		Package(){0x0005FFFF, 0, INTB, 0 },
+		Package(){0x0005FFFF, 1, INTC, 0 },
+		Package(){0x0005FFFF, 2, INTD, 0 },
+		Package(){0x0005FFFF, 3, INTA, 0 },
 		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
 		Package(){0x0006FFFF, 0, INTC, 0 },
 		Package(){0x0006FFFF, 1, INTD, 0 },
@@ -126,41 +132,44 @@ Scope(\_SB) {
 
 		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
 		Package(){0x0003FFFF, 0, 0, 19 },
+		Package(){0x0003FFFF, 1, 0, 16 },
+		Package(){0x0003FFFF, 2, 0, 17 },
+		Package(){0x0003FFFF, 3, 0, 18 },
 
 		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
 		Package(){0x0004FFFF, 0, 0, 16 },
-		/* Package(){0x0004FFFF, 1, 0, 17 }, */
-		/* Package(){0x0004FFFF, 2, 0, 18 }, */
-		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+		Package(){0x0004FFFF, 1, 0, 17 },
+		Package(){0x0004FFFF, 2, 0, 18 },
+		Package(){0x0004FFFF, 3, 0, 19 },
 
 		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, 0, 17 }, */
-		/* Package(){0x0005FFFF, 1, 0, 18 }, */
-		/* Package(){0x0005FFFF, 2, 0, 19 }, */
-		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+		Package(){0x0005FFFF, 0, 0, 17 },
+		Package(){0x0005FFFF, 1, 0, 18 },
+		Package(){0x0005FFFF, 2, 0, 19 },
+		Package(){0x0005FFFF, 3, 0, 16 },
 
 		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		/* Package(){0x0006FFFF, 0, 0, 18 }, */
-		/* Package(){0x0006FFFF, 1, 0, 19 }, */
-		/* Package(){0x0006FFFF, 2, 0, 16 }, */
-		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+		Package(){0x0006FFFF, 0, 0, 18 },
+		Package(){0x0006FFFF, 1, 0, 19 },
+		Package(){0x0006FFFF, 2, 0, 16 },
+		Package(){0x0006FFFF, 3, 0, 17 },
 
 		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		/* Package(){0x0007FFFF, 0, 0, 19 }, */
-		/* Package(){0x0007FFFF, 1, 0, 16 }, */
-		/* Package(){0x0007FFFF, 2, 0, 17 }, */
-		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+		Package(){0x0007FFFF, 0, 0, 19 },
+		Package(){0x0007FFFF, 1, 0, 16 },
+		Package(){0x0007FFFF, 2, 0, 17 },
+		Package(){0x0007FFFF, 3, 0, 18 },
 
 		/* Bus 0, Dev 9 - PCIe Bridge for network card */
 		Package(){0x0009FFFF, 0, 0, 17 },
-		/* Package(){0x0009FFFF, 1, 0, 16 }, */
-		/* Package(){0x0009FFFF, 2, 0, 17 }, */
-		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		Package(){0x0009FFFF, 1, 0, 16 },
+		Package(){0x0009FFFF, 2, 0, 17 },
+		Package(){0x0009FFFF, 3, 0, 18 },
 		/* Bus 0, Dev A - PCIe Bridge for network card */
 		Package(){0x000AFFFF, 0, 0, 18 },
-		/* Package(){0x000AFFFF, 1, 0, 16 }, */
-		/* Package(){0x000AFFFF, 2, 0, 17 }, */
-		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		Package(){0x000AFFFF, 1, 0, 16 },
+		Package(){0x000AFFFF, 2, 0, 17 },
+		Package(){0x000AFFFF, 3, 0, 18 },
 		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
 
 		/* SB devices in APIC mode */
diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl
index cb50394..d7e4687 100644
--- a/src/mainboard/amd/union_station/acpi/routing.asl
+++ b/src/mainboard/amd/union_station/acpi/routing.asl
@@ -31,22 +31,28 @@ Scope(\_SB) {
 		/* NB devices */
 		/* Bus 0, Dev 0 - RS780 Host Controller */
 		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, INTC, 0 },
+		Package(){0x0001FFFF, 1, INTD, 0 },
 		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
 		Package(){0x0002FFFF, 0, INTC, 0 },
 		Package(){0x0002FFFF, 1, INTD, 0 },
 		Package(){0x0002FFFF, 2, INTA, 0 },
 		Package(){0x0002FFFF, 3, INTB, 0 },
 		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, INTD, 0 },
+		Package(){0x0003FFFF, 1, INTA, 0 },
+		Package(){0x0003FFFF, 2, INTB, 0 },
+		Package(){0x0003FFFF, 3, INTC, 0 },
 		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
 		Package(){0x0004FFFF, 0, INTA, 0 },
 		Package(){0x0004FFFF, 1, INTB, 0 },
 		Package(){0x0004FFFF, 2, INTC, 0 },
 		Package(){0x0004FFFF, 3, INTD, 0 },
 		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
-		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
-		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
-		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		Package(){0x0005FFFF, 0, INTB, 0 },
+		Package(){0x0005FFFF, 1, INTC, 0 },
+		Package(){0x0005FFFF, 2, INTD, 0 },
+		Package(){0x0005FFFF, 3, INTA, 0 },
 		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
 		Package(){0x0006FFFF, 0, INTC, 0 },
 		Package(){0x0006FFFF, 1, INTD, 0 },
@@ -126,41 +132,44 @@ Scope(\_SB) {
 
 		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
 		Package(){0x0003FFFF, 0, 0, 19 },
+		Package(){0x0003FFFF, 1, 0, 16 },
+		Package(){0x0003FFFF, 2, 0, 17 },
+		Package(){0x0003FFFF, 3, 0, 18 },
 
 		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
 		Package(){0x0004FFFF, 0, 0, 16 },
-		/* Package(){0x0004FFFF, 1, 0, 17 }, */
-		/* Package(){0x0004FFFF, 2, 0, 18 }, */
-		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+		Package(){0x0004FFFF, 1, 0, 17 },
+		Package(){0x0004FFFF, 2, 0, 18 },
+		Package(){0x0004FFFF, 3, 0, 19 },
 
 		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, 0, 17 }, */
-		/* Package(){0x0005FFFF, 1, 0, 18 }, */
-		/* Package(){0x0005FFFF, 2, 0, 19 }, */
-		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+		Package(){0x0005FFFF, 0, 0, 17 },
+		Package(){0x0005FFFF, 1, 0, 18 },
+		Package(){0x0005FFFF, 2, 0, 19 },
+		Package(){0x0005FFFF, 3, 0, 16 },
 
 		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		/* Package(){0x0006FFFF, 0, 0, 18 }, */
-		/* Package(){0x0006FFFF, 1, 0, 19 }, */
-		/* Package(){0x0006FFFF, 2, 0, 16 }, */
-		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+		Package(){0x0006FFFF, 0, 0, 18 },
+		Package(){0x0006FFFF, 1, 0, 19 },
+		Package(){0x0006FFFF, 2, 0, 16 },
+		Package(){0x0006FFFF, 3, 0, 17 },
 
 		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		/* Package(){0x0007FFFF, 0, 0, 19 }, */
-		/* Package(){0x0007FFFF, 1, 0, 16 }, */
-		/* Package(){0x0007FFFF, 2, 0, 17 }, */
-		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+		Package(){0x0007FFFF, 0, 0, 19 },
+		Package(){0x0007FFFF, 1, 0, 16 },
+		Package(){0x0007FFFF, 2, 0, 17 },
+		Package(){0x0007FFFF, 3, 0, 18 },
 
 		/* Bus 0, Dev 9 - PCIe Bridge for network card */
 		Package(){0x0009FFFF, 0, 0, 17 },
-		/* Package(){0x0009FFFF, 1, 0, 16 }, */
-		/* Package(){0x0009FFFF, 2, 0, 17 }, */
-		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		Package(){0x0009FFFF, 1, 0, 16 },
+		Package(){0x0009FFFF, 2, 0, 17 },
+		Package(){0x0009FFFF, 3, 0, 18 },
 		/* Bus 0, Dev A - PCIe Bridge for network card */
 		Package(){0x000AFFFF, 0, 0, 18 },
-		/* Package(){0x000AFFFF, 1, 0, 16 }, */
-		/* Package(){0x000AFFFF, 2, 0, 17 }, */
-		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		Package(){0x000AFFFF, 1, 0, 16 },
+		Package(){0x000AFFFF, 2, 0, 17 },
+		Package(){0x000AFFFF, 3, 0, 18 },
 		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
 
 		/* SB devices in APIC mode */
diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl
index cb50394..d7e4687 100644
--- a/src/mainboard/asrock/e350m1/acpi/routing.asl
+++ b/src/mainboard/asrock/e350m1/acpi/routing.asl
@@ -31,22 +31,28 @@ Scope(\_SB) {
 		/* NB devices */
 		/* Bus 0, Dev 0 - RS780 Host Controller */
 		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, INTC, 0 },
+		Package(){0x0001FFFF, 1, INTD, 0 },
 		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
 		Package(){0x0002FFFF, 0, INTC, 0 },
 		Package(){0x0002FFFF, 1, INTD, 0 },
 		Package(){0x0002FFFF, 2, INTA, 0 },
 		Package(){0x0002FFFF, 3, INTB, 0 },
 		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, INTD, 0 },
+		Package(){0x0003FFFF, 1, INTA, 0 },
+		Package(){0x0003FFFF, 2, INTB, 0 },
+		Package(){0x0003FFFF, 3, INTC, 0 },
 		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
 		Package(){0x0004FFFF, 0, INTA, 0 },
 		Package(){0x0004FFFF, 1, INTB, 0 },
 		Package(){0x0004FFFF, 2, INTC, 0 },
 		Package(){0x0004FFFF, 3, INTD, 0 },
 		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
-		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
-		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
-		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		Package(){0x0005FFFF, 0, INTB, 0 },
+		Package(){0x0005FFFF, 1, INTC, 0 },
+		Package(){0x0005FFFF, 2, INTD, 0 },
+		Package(){0x0005FFFF, 3, INTA, 0 },
 		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
 		Package(){0x0006FFFF, 0, INTC, 0 },
 		Package(){0x0006FFFF, 1, INTD, 0 },
@@ -126,41 +132,44 @@ Scope(\_SB) {
 
 		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
 		Package(){0x0003FFFF, 0, 0, 19 },
+		Package(){0x0003FFFF, 1, 0, 16 },
+		Package(){0x0003FFFF, 2, 0, 17 },
+		Package(){0x0003FFFF, 3, 0, 18 },
 
 		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
 		Package(){0x0004FFFF, 0, 0, 16 },
-		/* Package(){0x0004FFFF, 1, 0, 17 }, */
-		/* Package(){0x0004FFFF, 2, 0, 18 }, */
-		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+		Package(){0x0004FFFF, 1, 0, 17 },
+		Package(){0x0004FFFF, 2, 0, 18 },
+		Package(){0x0004FFFF, 3, 0, 19 },
 
 		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, 0, 17 }, */
-		/* Package(){0x0005FFFF, 1, 0, 18 }, */
-		/* Package(){0x0005FFFF, 2, 0, 19 }, */
-		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+		Package(){0x0005FFFF, 0, 0, 17 },
+		Package(){0x0005FFFF, 1, 0, 18 },
+		Package(){0x0005FFFF, 2, 0, 19 },
+		Package(){0x0005FFFF, 3, 0, 16 },
 
 		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		/* Package(){0x0006FFFF, 0, 0, 18 }, */
-		/* Package(){0x0006FFFF, 1, 0, 19 }, */
-		/* Package(){0x0006FFFF, 2, 0, 16 }, */
-		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+		Package(){0x0006FFFF, 0, 0, 18 },
+		Package(){0x0006FFFF, 1, 0, 19 },
+		Package(){0x0006FFFF, 2, 0, 16 },
+		Package(){0x0006FFFF, 3, 0, 17 },
 
 		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		/* Package(){0x0007FFFF, 0, 0, 19 }, */
-		/* Package(){0x0007FFFF, 1, 0, 16 }, */
-		/* Package(){0x0007FFFF, 2, 0, 17 }, */
-		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+		Package(){0x0007FFFF, 0, 0, 19 },
+		Package(){0x0007FFFF, 1, 0, 16 },
+		Package(){0x0007FFFF, 2, 0, 17 },
+		Package(){0x0007FFFF, 3, 0, 18 },
 
 		/* Bus 0, Dev 9 - PCIe Bridge for network card */
 		Package(){0x0009FFFF, 0, 0, 17 },
-		/* Package(){0x0009FFFF, 1, 0, 16 }, */
-		/* Package(){0x0009FFFF, 2, 0, 17 }, */
-		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		Package(){0x0009FFFF, 1, 0, 16 },
+		Package(){0x0009FFFF, 2, 0, 17 },
+		Package(){0x0009FFFF, 3, 0, 18 },
 		/* Bus 0, Dev A - PCIe Bridge for network card */
 		Package(){0x000AFFFF, 0, 0, 18 },
-		/* Package(){0x000AFFFF, 1, 0, 16 }, */
-		/* Package(){0x000AFFFF, 2, 0, 17 }, */
-		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		Package(){0x000AFFFF, 1, 0, 16 },
+		Package(){0x000AFFFF, 2, 0, 17 },
+		Package(){0x000AFFFF, 3, 0, 18 },
 		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
 
 		/* SB devices in APIC mode */


From gerrit at coreboot.org  Thu Dec 22 04:34:04 2011
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Thu, 22 Dec 2011 04:34:04 +0100
Subject: [coreboot] Patch set updated for coreboot: 1ba80c2 F14 mainboard:
	mptable update
References: <Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59+0@gerrit.coreboot.org>
Message-ID: <Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/451

-gerrit

commit 1ba80c2a084e3403fc7ce06c487e0a97316b668e
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Dec 22 12:18:26 2011 +0800

    F14 mainboard: mptable update
    
    Add GNB internal graphic interrupt,
    correct southbridge hd audio device interrupt. and remove the
    dead code already commented out.
    
    south_station, union_station, inagua, persimmon and e350m1 mainboard
    are included herein.
    
    Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/mptable.c        |   10 +++++++---
 src/mainboard/amd/persimmon/mptable.c     |    8 +++++---
 src/mainboard/amd/south_station/mptable.c |    8 +++++---
 src/mainboard/amd/union_station/mptable.c |    8 +++++---
 src/mainboard/asrock/e350m1/mptable.c     |    8 +++++---
 5 files changed, 27 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 7278936..73d946c 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -166,11 +166,15 @@ static void *smp_write_config_table(void *v)
 #define PCI_INT(bus, dev, int_sign, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
 
+  /* APU Internal Graphic Device*/
+  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
   /* SMBUS */
   PCI_INT(0x0, 0x14, 0x0, 0x10);
 
-  /* HD Audio */
-  PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+  /* Southbridge HD Audio */
+  PCI_INT(0x0, 0x14, 0x2, intr_data[0x13]);
 
   /* USB */
   PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
@@ -179,7 +183,7 @@ static void *smp_write_config_table(void *v)
   PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
   PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
   PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-  PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+  PCI_INT(0x0, 0x14, 0x5, intr_data[0x36]);
 
   /* sata */
   PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 92c842f..18a7707 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v)
 #define PCI_INT(bus, dev, fn, pin)
 #endif
 
+	/* APU Internal Graphic Device*/
+	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
 	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
 	PCI_INT(0x0, 0x14, 0x0, 0x10);
-	/* HD Audio: */
+	/* Southbridge HD Audio: */
 	PCI_INT(0x0, 0x14, 0x2, 0x12);
 
 	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
@@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v)
 	/* sata */
 	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
-	/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
-
 	/* on board NIC & Slot PCIE.	*/
 
 	/* PCI slots */
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index a3b4b5c..5c8ae5a 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v)
 #define PCI_INT(bus, dev, fn, pin)
 #endif
 
+  /* APU Internal Graphic Device*/
+  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
   //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
   PCI_INT(0x0, 0x14, 0x0, 0x10);
-  /* HD Audio: */
+  /* Southbridge HD Audio: */
   PCI_INT(0x0, 0x14, 0x2, 0x12);
 
   PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
@@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v)
   /* sata */
   PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
-  /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
-
   /* on board NIC & Slot PCIE.  */
   
   /* PCI slots */
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index a3b4b5c..5c8ae5a 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v)
 #define PCI_INT(bus, dev, fn, pin)
 #endif
 
+  /* APU Internal Graphic Device*/
+  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
   //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
   PCI_INT(0x0, 0x14, 0x0, 0x10);
-  /* HD Audio: */
+  /* Southbridge HD Audio: */
   PCI_INT(0x0, 0x14, 0x2, 0x12);
 
   PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
@@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v)
   /* sata */
   PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
-  /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
-
   /* on board NIC & Slot PCIE.  */
   
   /* PCI slots */
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 960c2c8..de9d7f4 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v)
 #define PCI_INT(bus, dev, fn, pin)
 #endif
 
+  /* APU Internal Graphic Device*/
+  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
   //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
   PCI_INT(0x0, 0x14, 0x0, 0x10);
-  /* HD Audio: */
+  /* Southbridge HD Audio: */
   PCI_INT(0x0, 0x14, 0x2, 0x12);
 
   PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
@@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v)
   /* sata */
   PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
-  /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
-
   /* on board NIC & Slot PCIE.  */
 
   /* PCI slots */


From gerrit at coreboot.org  Fri Dec 23 11:27:19 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Fri, 23 Dec 2011 11:27:19 +0100
Subject: [coreboot] New patch to review for coreboot: 3ff84d3 ACPI: remove
	empty get_cst_entries()
References: <I4bc0168aee110171faeaa081f217dfd1536bb821+0@gerrit.coreboot.org>
Message-ID: <I4bc0168aee110171faeaa081f217dfd1536bb821+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/496

-gerrit

commit 3ff84d326ee881a4ec2f3995744363d75710cf14
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 23 10:29:09 2011 +0100

    ACPI: remove empty get_cst_entries()
    
    This function prevents the linker from choosing the right
    get_cst_entries(), preventing writing the _CST tables.
    
    Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/cpu/intel/speedstep/acpi.c |    7 +------
 1 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 8f32e4f..c7ad4f6 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -62,11 +62,6 @@ static int get_fsb(void)
 	return 200;
 }
 
-int get_cst_entries(struct cst_entry **entries __attribute__((unused)))
-{
-	return 0;
-}
-
 void generate_cpu_entries(void)
 {
 	int len_pr, len_ps;
@@ -89,7 +84,7 @@ void generate_cpu_entries(void)
 		len_pr = acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen);
 			len_pr += acpigen_write_empty_PCT();
 			len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
-			if ((count = get_cst_entries(&cst_entries)) > 0)
+			if (get_cst_entries && (count = get_cst_entries(&cst_entries)) > 0)
 				len_pr += acpigen_write_CST_package(cst_entries, count);
 			len_pr += acpigen_write_name("_PSS");
 


From gerrit at coreboot.org  Sat Dec 24 01:13:17 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 01:13:17 +0100
Subject: [coreboot] Patch set updated for coreboot: db8120b Replace
	UNPACK_CB64 macro with inline
References: <Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a+0@gerrit.coreboot.org>
Message-ID: <Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a+3@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/495

-gerrit

commit db8120b11aa3b9610f31ace9bbba61b6e5fa4046
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:09:02 2011 -0700

    Replace UNPACK_CB64 macro with inline
    
    Having submitted a module based on coreboot to LKML for acceptance,
    it was requested that fewer macros and more inlines be used (because
    of their superior type-checking when performing pointer casts, etc).
    
    This is the first of several changes to make the relevant parts of
    coreboot comply to linux code standards.
    
    Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    6 +++---
 payloads/libpayload/arch/i386/coreboot.c      |    4 ++--
 payloads/libpayload/include/coreboot_tables.h |   10 +++++++---
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index dd589ac..5d13128 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -112,9 +112,9 @@ int coreboot_module_redraw(WINDOW *win)
 		}
 
 		wprintw(win, "%16.16llx - %16.16llx",
-			UNPACK_CB64(cb_info.range[i].start),
-			UNPACK_CB64(cb_info.range[i].start) +
-			UNPACK_CB64(cb_info.range[i].size) - 1);
+			cb_unpack64(cb_info.range[i].start),
+			cb_unpack64(cb_info.range[i].start) +
+			cb_unpack64(cb_info.range[i].size) - 1);
 	}
 
 	return 0;
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 365445e..a77144b 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -63,10 +63,10 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 #endif
 
 		info->memrange[info->n_memranges].base =
-		    UNPACK_CB64(range->start);
+		    cb_unpack64(range->start);
 
 		info->memrange[info->n_memranges].size =
-		    UNPACK_CB64(range->size);
+		    cb_unpack64(range->size);
 
 		info->memrange[info->n_memranges].type = range->type;
 
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index d342c99..3b3b7d2 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -216,6 +216,13 @@ struct	cb_cmos_checksum {
 	u32 type;
 };
 
+/* Helpful inlines */
+
+static inline u64 cb_unpack64(struct cbuint64 val)
+{
+	return (((u64) val.hi) << 32) | val.lo;
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
@@ -231,7 +238,4 @@ struct	cb_cmos_checksum {
 #define MB_PART_STRING(_mb) \
 	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
 
-#define UNPACK_CB64(_in) \
-	( (((u64) _in.hi) << 32) | _in.lo )
-
 #endif


From gerrit at coreboot.org  Sat Dec 24 01:24:26 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 01:24:26 +0100
Subject: [coreboot] New patch to review for coreboot: 76ee7c3 Use
	convenience function to checksum
References: <I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370+0@gerrit.coreboot.org>
Message-ID: <I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/497

-gerrit

commit 76ee7c3f8e68eae1df5fcb43bcfb54dcdf489cad
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:22:05 2011 -0700

    Use convenience function to checksum
    
    That coreboot uses the IP checksum is an artifact, not a deliberate
    requirement to be compatible with the Internet Protocole suite. Use
    a wrapper to abstract the computation of coreboot's checksum.
    
    Change-Id: I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    6 +++---
 payloads/libpayload/include/coreboot_tables.h |    5 +++++
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index 5d13128..7289366 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <coreboot_tables.h>
 #include "coreinfo.h"
+#include <coreboot_tables.h>
 
 #ifdef CONFIG_MODULE_COREBOOT
 
@@ -189,10 +189,10 @@ static int parse_header(void *addr, int len)
 
 	/* FIXME: Check the checksum. */
 
-	if (ipchksum((uint16_t *) header, sizeof(*header)))
+	if (cb_checksum(header, sizeof(*header)))
 		return -1;
 
-	if (ipchksum((uint16_t *) (ptr + sizeof(*header)), header->table_bytes)
+	if (cb_checksum((ptr + sizeof(*header)), header->table_bytes)
 	    != header->table_checksum)
 		return -1;
 
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 3b3b7d2..574469a 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -223,6 +223,11 @@ static inline u64 cb_unpack64(struct cbuint64 val)
 	return (((u64) val.hi) << 32) | val.lo;
 }
 
+static inline u16 cb_checksum(const void *ptr, unsigned len)
+{
+	return ipchksum(ptr, len);
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \


From gerrit at coreboot.org  Sat Dec 24 01:30:49 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 01:30:49 +0100
Subject: [coreboot] New patch to review for coreboot: 545d7a5 Use void
	pointers for untyped memory
References: <I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3+0@gerrit.coreboot.org>
Message-ID: <I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/498

-gerrit

commit 545d7a5bea6e06a97eb11e248ea1b06942358e1a
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:28:59 2011 -0700

    Use void pointers for untyped memory
    
    To avoid unnecessary casts, we can use untyped pointers when accessing
    individual records.
    
    Change-Id: I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/libpayload/arch/i386/coreboot.c |   29 ++++++++++++++---------------
 1 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index a77144b..3c99c4f 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -42,9 +42,9 @@
 /* === Parsing code === */
 /* This is the generic parsing code. */
 
-static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_memory(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_memory *mem = (struct cb_memory *)ptr;
+	struct cb_memory *mem = ptr;
 	int count = MEM_RANGE_COUNT(mem);
 	int i;
 
@@ -54,8 +54,7 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 	info->n_memranges = 0;
 
 	for (i = 0; i < count; i++) {
-		struct cb_memory_range *range =
-		    (struct cb_memory_range *)MEM_RANGE_PTR(mem, i);
+		struct cb_memory_range *range = MEM_RANGE_PTR(mem, i);
 
 #ifdef CONFIG_MEMMAP_RAM_ONLY
 		if (range->type != CB_MEM_RAM)
@@ -74,29 +73,29 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 	}
 }
 
-static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_serial(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_serial *ser = (struct cb_serial *)ptr;
+	struct cb_serial *ser = ptr;
 	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
 		return;
 	info->ser_ioport = ser->baseaddr;
 }
 
-static void cb_parse_version(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_version(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_string *ver = (struct cb_string *)ptr;
+	struct cb_string *ver = ptr;
 	info->cb_version = (char *)ver->string;
 }
 
 #ifdef CONFIG_NVRAM
-static void cb_parse_optiontable(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info)
 {
-	info->option_table = (struct cb_cmos_option_table *)ptr;
+	info->option_table = ptr;
 }
 
-static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_checksum(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_cmos_checksum *cmos_cksum = (struct cb_cmos_checksum *)ptr;
+	struct cb_cmos_checksum *cmos_cksum = ptr;
 	info->cmos_range_start = cmos_cksum->range_start;
 	info->cmos_range_end = cmos_cksum->range_end;
 	info->cmos_checksum_location = cmos_cksum->location;
@@ -104,16 +103,16 @@ static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
 #endif
 
 #ifdef CONFIG_COREBOOT_VIDEO_CONSOLE
-static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 {
-	info->framebuffer = (struct cb_framebuffer *)ptr;
+	info->framebuffer = ptr;
 }
 #endif
 
 static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 {
 	struct cb_header *header;
-	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr = addr;
 	int i;
 
 	for (i = 0; i < len; i += 16, ptr += 16) {


From gerrit at coreboot.org  Sat Dec 24 01:45:41 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 01:45:41 +0100
Subject: [coreboot] New patch to review for coreboot: db051bf Fix missing VM
	mapping
References: <I35ef637fbec7886d4cfeac5fd650a17eae8d555a+0@gerrit.coreboot.org>
Message-ID: <I35ef637fbec7886d4cfeac5fd650a17eae8d555a+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/499

-gerrit

commit db051bf5228810b95952960bdc66fb37f004c09f
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:36:09 2011 -0700

    Fix missing VM mapping
    
    When processing FORWARD records, we weren't accounting for the pointer
    being in the physical address space and not the virtual space instead.
    
    Change-Id: I35ef637fbec7886d4cfeac5fd650a17eae8d555a
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/libpayload/arch/i386/coreboot.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 3c99c4f..709f8ae 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -113,6 +113,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 {
 	struct cb_header *header;
 	unsigned char *ptr = addr;
+	void *forward;
 	int i;
 
 	for (i = 0; i < len; i += 16, ptr += 16) {
@@ -145,7 +146,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		/* We only care about a few tags here (maybe more later). */
 		switch (rec->tag) {
 		case CB_TAG_FORWARD:
-			return cb_parse_header((void *)(unsigned long)((struct cb_forward *)rec)->forward, len, info);
+			forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward);
+			return cb_parse_header(forward, len, info);
 			continue;
 		case CB_TAG_MEMORY:
 			cb_parse_memory(ptr, info);


From gerrit at coreboot.org  Sat Dec 24 01:45:54 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 01:45:54 +0100
Subject: [coreboot] Patch set updated for coreboot: 250f8aa Replace
	UNPACK_CB64 macro with inline
References: <Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a+0@gerrit.coreboot.org>
Message-ID: <Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a+4@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/495

-gerrit

commit 250f8aa63a19efbeecca74d4330dd5c483c741d3
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:09:02 2011 -0700

    Replace UNPACK_CB64 macro with inline
    
    Having submitted a module based on coreboot to LKML for acceptance,
    it was requested that fewer macros and more inlines be used (because
    of their superior type-checking when performing pointer casts, etc).
    
    This is the first of several changes to make the relevant parts of
    coreboot comply to linux code standards.
    
    Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    6 +++---
 payloads/libpayload/arch/i386/coreboot.c      |    4 ++--
 payloads/libpayload/include/coreboot_tables.h |   10 +++++++---
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index dd589ac..5d13128 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -112,9 +112,9 @@ int coreboot_module_redraw(WINDOW *win)
 		}
 
 		wprintw(win, "%16.16llx - %16.16llx",
-			UNPACK_CB64(cb_info.range[i].start),
-			UNPACK_CB64(cb_info.range[i].start) +
-			UNPACK_CB64(cb_info.range[i].size) - 1);
+			cb_unpack64(cb_info.range[i].start),
+			cb_unpack64(cb_info.range[i].start) +
+			cb_unpack64(cb_info.range[i].size) - 1);
 	}
 
 	return 0;
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 365445e..a77144b 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -63,10 +63,10 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 #endif
 
 		info->memrange[info->n_memranges].base =
-		    UNPACK_CB64(range->start);
+		    cb_unpack64(range->start);
 
 		info->memrange[info->n_memranges].size =
-		    UNPACK_CB64(range->size);
+		    cb_unpack64(range->size);
 
 		info->memrange[info->n_memranges].type = range->type;
 
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index d342c99..3b3b7d2 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -216,6 +216,13 @@ struct	cb_cmos_checksum {
 	u32 type;
 };
 
+/* Helpful inlines */
+
+static inline u64 cb_unpack64(struct cbuint64 val)
+{
+	return (((u64) val.hi) << 32) | val.lo;
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
@@ -231,7 +238,4 @@ struct	cb_cmos_checksum {
 #define MB_PART_STRING(_mb) \
 	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
 
-#define UNPACK_CB64(_in) \
-	( (((u64) _in.hi) << 32) | _in.lo )
-
 #endif


From gerrit at coreboot.org  Sat Dec 24 01:46:07 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 01:46:07 +0100
Subject: [coreboot] Patch set updated for coreboot: bde7653 Use convenience
	function to checksum
References: <I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370+0@gerrit.coreboot.org>
Message-ID: <I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370+2@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/497

-gerrit

commit bde765381d216bb9144b3950aa101d6e987ebc07
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:22:05 2011 -0700

    Use convenience function to checksum
    
    That coreboot uses the IP checksum is an artifact, not a deliberate
    requirement to be compatible with the Internet Protocole suite. Use
    a wrapper to abstract the computation of coreboot's checksum.
    
    Change-Id: I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    6 +++---
 payloads/libpayload/include/coreboot_tables.h |    5 +++++
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index 5d13128..7289366 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <coreboot_tables.h>
 #include "coreinfo.h"
+#include <coreboot_tables.h>
 
 #ifdef CONFIG_MODULE_COREBOOT
 
@@ -189,10 +189,10 @@ static int parse_header(void *addr, int len)
 
 	/* FIXME: Check the checksum. */
 
-	if (ipchksum((uint16_t *) header, sizeof(*header)))
+	if (cb_checksum(header, sizeof(*header)))
 		return -1;
 
-	if (ipchksum((uint16_t *) (ptr + sizeof(*header)), header->table_bytes)
+	if (cb_checksum((ptr + sizeof(*header)), header->table_bytes)
 	    != header->table_checksum)
 		return -1;
 
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 3b3b7d2..574469a 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -223,6 +223,11 @@ static inline u64 cb_unpack64(struct cbuint64 val)
 	return (((u64) val.hi) << 32) | val.lo;
 }
 
+static inline u16 cb_checksum(const void *ptr, unsigned len)
+{
+	return ipchksum(ptr, len);
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \


From gerrit at coreboot.org  Sat Dec 24 01:46:08 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 01:46:08 +0100
Subject: [coreboot] Patch set updated for coreboot: 956c9c2 Use void
	pointers for untyped memory
References: <I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3+0@gerrit.coreboot.org>
Message-ID: <I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3+2@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/498

-gerrit

commit 956c9c27504107109f11ef7113efa6448acea6df
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:28:59 2011 -0700

    Use void pointers for untyped memory
    
    To avoid unnecessary casts, we can use untyped pointers when accessing
    individual records.
    
    Change-Id: I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/libpayload/arch/i386/coreboot.c |   29 ++++++++++++++---------------
 1 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index a77144b..3c99c4f 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -42,9 +42,9 @@
 /* === Parsing code === */
 /* This is the generic parsing code. */
 
-static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_memory(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_memory *mem = (struct cb_memory *)ptr;
+	struct cb_memory *mem = ptr;
 	int count = MEM_RANGE_COUNT(mem);
 	int i;
 
@@ -54,8 +54,7 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 	info->n_memranges = 0;
 
 	for (i = 0; i < count; i++) {
-		struct cb_memory_range *range =
-		    (struct cb_memory_range *)MEM_RANGE_PTR(mem, i);
+		struct cb_memory_range *range = MEM_RANGE_PTR(mem, i);
 
 #ifdef CONFIG_MEMMAP_RAM_ONLY
 		if (range->type != CB_MEM_RAM)
@@ -74,29 +73,29 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
 	}
 }
 
-static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_serial(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_serial *ser = (struct cb_serial *)ptr;
+	struct cb_serial *ser = ptr;
 	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
 		return;
 	info->ser_ioport = ser->baseaddr;
 }
 
-static void cb_parse_version(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_version(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_string *ver = (struct cb_string *)ptr;
+	struct cb_string *ver = ptr;
 	info->cb_version = (char *)ver->string;
 }
 
 #ifdef CONFIG_NVRAM
-static void cb_parse_optiontable(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info)
 {
-	info->option_table = (struct cb_cmos_option_table *)ptr;
+	info->option_table = ptr;
 }
 
-static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_checksum(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_cmos_checksum *cmos_cksum = (struct cb_cmos_checksum *)ptr;
+	struct cb_cmos_checksum *cmos_cksum = ptr;
 	info->cmos_range_start = cmos_cksum->range_start;
 	info->cmos_range_end = cmos_cksum->range_end;
 	info->cmos_checksum_location = cmos_cksum->location;
@@ -104,16 +103,16 @@ static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
 #endif
 
 #ifdef CONFIG_COREBOOT_VIDEO_CONSOLE
-static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info)
+static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 {
-	info->framebuffer = (struct cb_framebuffer *)ptr;
+	info->framebuffer = ptr;
 }
 #endif
 
 static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 {
 	struct cb_header *header;
-	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr = addr;
 	int i;
 
 	for (i = 0; i < len; i += 16, ptr += 16) {


From gerrit at coreboot.org  Sat Dec 24 01:54:17 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 01:54:17 +0100
Subject: [coreboot] New patch to review for coreboot: 98cd3c8 Fix missing
	cast back to void *
References: <I0ec64ad7bdb136d5e1a999bff3df6fa66eb29bf1+0@gerrit.coreboot.org>
Message-ID: <I0ec64ad7bdb136d5e1a999bff3df6fa66eb29bf1+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/500

-gerrit

commit 98cd3c8d5b16d4369e25ddca6a313d59f2a0bf4a
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:53:26 2011 -0700

    Fix missing cast back to void *
    
    MEM_RANGE_PTR() also needs to return a pointer to untyped memory.
    
    Change-Id: I0ec64ad7bdb136d5e1a999bff3df6fa66eb29bf1
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/libpayload/include/coreboot_tables.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 574469a..e362d06 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -234,8 +234,8 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	(((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
 
 #define MEM_RANGE_PTR(_rec, _idx) \
-	(((u8 *) (_rec)) + sizeof(*(_rec)) \
-	+ (sizeof((_rec)->map[0]) * (_idx)))
+	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
+		+ (sizeof((_rec)->map[0]) * (_idx)))
 
 #define MB_VENDOR_STRING(_mb) \
 	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)


From gerrit at coreboot.org  Sat Dec 24 02:12:03 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 02:12:03 +0100
Subject: [coreboot] New patch to review for coreboot: 3aa126f
	cb_parse_header() should not assume table in 4K of contiguous memory
References: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+0@gerrit.coreboot.org>
Message-ID: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/501

-gerrit

commit 3aa126fcf9ced443618b7600069376b0202edaee
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:09:25 2011 -0700

    cb_parse_header() should not assume table in 4K of contiguous memory
    
    If we have the CB table in E820 memory, we might not have an entire 4K
    (0x1000) bytes of memory to scan through. Instead, a better strategy
    is to pass in a pointer to the end of the region or the start + 4K
    (which ever is lower). This change prepares the cb_parse_header()
    calling convention for that change.
    
    Change-Id: I9257726c6a7065b5596d4c32ab451edd0a3cdc10
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/libpayload/arch/i386/coreboot.c |   22 ++++++++++++++--------
 1 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 709f8ae..135c59c 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -109,21 +109,21 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 }
 #endif
 
-static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
+static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 {
 	struct cb_header *header;
-	unsigned char *ptr = addr;
+	unsigned char *ptr;
 	void *forward;
 	int i;
 
-	for (i = 0; i < len; i += 16, ptr += 16) {
+	for (ptr = addr; (void *)ptr < end; ptr += 16) {
 		header = (struct cb_header *)ptr;
 		if (!strncmp((const char *)header->signature, "LBIO", 4))
 			break;
 	}
 
 	/* We walked the entire space and didn't find anything. */
-	if (i >= len)
+	if ((void *)ptr >= end)
 		return -1;
 
 	if (!header->table_bytes)
@@ -147,7 +147,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		switch (rec->tag) {
 		case CB_TAG_FORWARD:
 			forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward);
-			return cb_parse_header(forward, len, info);
+			return cb_parse_header(forward, forward + 0x1000, info);
 			continue;
 		case CB_TAG_MEMORY:
 			cb_parse_memory(ptr, info);
@@ -176,6 +176,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		}
 
 		ptr += rec->size;
+
+		if ((void *)ptr >= end)
+			return -1;
 	}
 
 	return 1;
@@ -186,10 +189,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 
 int get_coreboot_info(struct sysinfo_t *info)
 {
-	int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
+	void *base = phys_to_virt(0x00000000);
+	int ret = cb_parse_header(base, base + 0x1000, info);
 
-	if (ret != 1)
-		ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
+	if (ret != 1) {
+		base = phys_to_virt(0x000f0000);
+		ret = cb_parse_header(base, base + 0x1000, info);
+	}
 
 	return (ret == 1) ? 0 : -1;
 }


From gerrit at coreboot.org  Sat Dec 24 02:34:45 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 02:34:45 +0100
Subject: [coreboot] New patch to review for coreboot: 089323a Cleanup access
	to vendor/part # info
References: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+0@gerrit.coreboot.org>
Message-ID: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502

-gerrit

commit 089323aaad415077205d38edf7f787fa1152dfb5
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:28:24 2011 -0700

    Cleanup access to vendor/part # info
    
    Instead of macros to access MAINBOARD record, use convenience functions.
    
    Store pointers to MAINBOARD and HEADER for use outside of CB code.
    
    Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    4 ++--
 payloads/libpayload/arch/i386/coreboot.c      |    5 +++++
 payloads/libpayload/include/coreboot_tables.h |   16 ++++++++++------
 payloads/libpayload/include/sysinfo.h         |    3 +++
 4 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index 7289366..d33ea9e 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31);
-	strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31);
+	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31);
+	strncpy(cb_info.part, cb_mb_part_string(mb), 31);
 }
 
 static void parse_strings(unsigned char *ptr)
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 135c59c..7fe286e 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 		     header->table_bytes) != header->table_checksum)
 		return -1;
 
+	info->header = header;
+
 	/* Now, walk the tables. */
 	ptr += header->header_bytes;
 
@@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 			cb_parse_framebuffer(ptr, info);
 			break;
 #endif
+		case CB_TAG_MAINBOARD:
+			info->mainboard = (struct cb_mainboard *)ptr;
+			break;
 		}
 
 		ptr += rec->size;
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index e362d06..c68ccc9 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	return ipchksum(ptr, len);
 }
 
+static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->vendor_idx);
+}
+
+static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->part_number_idx);
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
@@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
 		+ (sizeof((_rec)->map[0]) * (_idx)))
 
-#define MB_VENDOR_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
-
-#define MB_PART_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
-
 #endif
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c1d2002..778dfe9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -56,6 +56,9 @@ struct sysinfo_t {
 	struct cb_framebuffer *framebuffer;
 
 	unsigned long *mbtable; /** Pointer to the multiboot table */
+
+	struct cb_header *header;
+	struct cb_mainboard *mainboard;
 };
 
 extern struct sysinfo_t lib_sysinfo;


From gerrit at coreboot.org  Sat Dec 24 02:34:48 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 02:34:48 +0100
Subject: [coreboot] New patch to review for coreboot: e11cec9 Let
	lib_get_sysinfo() pass through the success of get_coreboot_info()
References: <I0176c93ee92c9dff733112026ee50f2ca797bdff+0@gerrit.coreboot.org>
Message-ID: <I0176c93ee92c9dff733112026ee50f2ca797bdff+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/503

-gerrit

commit e11cec94e22b2a6c4086656006a0667ec648e0d5
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:33:05 2011 -0700

    Let lib_get_sysinfo() pass through the success of get_coreboot_info()
    
    The return status of get_coreboot_info() might be handy to a platform
    driver calling lib_get_sysinfo() to test for the presence of coreboot.
    
    Change-Id: I0176c93ee92c9dff733112026ee50f2ca797bdff
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/libpayload/arch/i386/sysinfo.c    |    8 ++++++--
 payloads/libpayload/arch/powerpc/sysinfo.c |    8 ++++++--
 payloads/libpayload/include/libpayload.h   |    2 +-
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/payloads/libpayload/arch/i386/sysinfo.c b/payloads/libpayload/arch/i386/sysinfo.c
index 599a811..6c1ef3f 100644
--- a/payloads/libpayload/arch/i386/sysinfo.c
+++ b/payloads/libpayload/arch/i386/sysinfo.c
@@ -45,8 +45,10 @@ struct sysinfo_t lib_sysinfo = {
 #endif
 };
 
-void lib_get_sysinfo(void)
+int lib_get_sysinfo(void)
 {
+	int ret;
+
 	/* Get the CPU speed (for delays). */
 	lib_sysinfo.cpu_khz = get_cpu_speed();
 
@@ -59,7 +61,7 @@ void lib_get_sysinfo(void)
 	/* Get information from the coreboot tables,
 	 * if they exist */
 
-	get_coreboot_info(&lib_sysinfo);
+	ret = get_coreboot_info(&lib_sysinfo);
 
 	if (!lib_sysinfo.n_memranges) {
 		/* If we can't get a good memory range, use the default. */
@@ -73,4 +75,6 @@ void lib_get_sysinfo(void)
 		lib_sysinfo.memrange[1].size = 31 * 1024 * 1024;
 		lib_sysinfo.memrange[1].type = CB_MEM_RAM;
 	}
+
+	return ret;
 }
diff --git a/payloads/libpayload/arch/powerpc/sysinfo.c b/payloads/libpayload/arch/powerpc/sysinfo.c
index 599a811..6c1ef3f 100644
--- a/payloads/libpayload/arch/powerpc/sysinfo.c
+++ b/payloads/libpayload/arch/powerpc/sysinfo.c
@@ -45,8 +45,10 @@ struct sysinfo_t lib_sysinfo = {
 #endif
 };
 
-void lib_get_sysinfo(void)
+int lib_get_sysinfo(void)
 {
+	int ret;
+
 	/* Get the CPU speed (for delays). */
 	lib_sysinfo.cpu_khz = get_cpu_speed();
 
@@ -59,7 +61,7 @@ void lib_get_sysinfo(void)
 	/* Get information from the coreboot tables,
 	 * if they exist */
 
-	get_coreboot_info(&lib_sysinfo);
+	ret = get_coreboot_info(&lib_sysinfo);
 
 	if (!lib_sysinfo.n_memranges) {
 		/* If we can't get a good memory range, use the default. */
@@ -73,4 +75,6 @@ void lib_get_sysinfo(void)
 		lib_sysinfo.memrange[1].size = 31 * 1024 * 1024;
 		lib_sysinfo.memrange[1].type = CB_MEM_RAM;
 	}
+
+	return ret;
 }
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 8c8abc4..d9f7d21 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -369,7 +369,7 @@ int sysinfo_have_multiboot(unsigned long *addr);
 int get_coreboot_info(struct sysinfo_t *info);
 int get_multiboot_info(struct sysinfo_t *info);
 
-void lib_get_sysinfo(void);
+int lib_get_sysinfo(void);
 
 /* Timer functions - defined by each architecture. */
 unsigned int get_cpu_speed(void);


From gerrit at coreboot.org  Sat Dec 24 02:46:14 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sat, 24 Dec 2011 02:46:14 +0100
Subject: [coreboot] New patch to review for coreboot: 0ab8e97 Eliminate
	magic numbers
References: <I2b7e0e4a8df6448d027cc61867382f161eb990d3+0@gerrit.coreboot.org>
Message-ID: <I2b7e0e4a8df6448d027cc61867382f161eb990d3+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/504

-gerrit

commit 0ab8e97acc036c78c7c9e49995be94d275f91ef6
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:45:33 2011 -0700

    Eliminate magic numbers
    
    Use sizeof() on vendor and part# rather than explicit memory length.
    
    Change-Id: I2b7e0e4a8df6448d027cc61867382f161eb990d3
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index d33ea9e..77a4bb2 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31);
-	strncpy(cb_info.part, cb_mb_part_string(mb), 31);
+	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), sizeof(cb_info.vendor) - 1);
+	strncpy(cb_info.part, cb_mb_part_string(mb), sizeof(cb_info.part) - 1);
 }
 
 static void parse_strings(unsigned char *ptr)


From rminnich at gmail.com  Sat Dec 24 05:16:55 2011
From: rminnich at gmail.com (ron minnich)
Date: Fri, 23 Dec 2011 20:16:55 -0800
Subject: [coreboot] New patch to review for coreboot: db051bf Fix
 missing VM mapping
In-Reply-To: <I35ef637fbec7886d4cfeac5fd650a17eae8d555a+1@gerrit.coreboot.org>
References: <I35ef637fbec7886d4cfeac5fd650a17eae8d555a+0@gerrit.coreboot.org>
	<I35ef637fbec7886d4cfeac5fd650a17eae8d555a+1@gerrit.coreboot.org>
Message-ID: <CAP6exYKYTPuxh0k-UUTAebq4VLTtJCKk_sTAOpcY7pa0irym4g@mail.gmail.com>

I'm just getting back to coreboot. Is libpayload used verbatim in the
kernel? The phys/virt map in coreboot is 1:1 by design. The mapping
seems unnecessary to me. Just wondering.

ron


From philipp_subx at redfish-solutions.com  Sat Dec 24 07:20:21 2011
From: philipp_subx at redfish-solutions.com (Philip Prindeville)
Date: Fri, 23 Dec 2011 23:20:21 -0700
Subject: [coreboot] New patch to review for coreboot: db051bf Fix
 missing VM mapping
In-Reply-To: <CAP6exYKYTPuxh0k-UUTAebq4VLTtJCKk_sTAOpcY7pa0irym4g@mail.gmail.com>
References: <I35ef637fbec7886d4cfeac5fd650a17eae8d555a+0@gerrit.coreboot.org>
	<I35ef637fbec7886d4cfeac5fd650a17eae8d555a+1@gerrit.coreboot.org>
	<CAP6exYKYTPuxh0k-UUTAebq4VLTtJCKk_sTAOpcY7pa0irym4g@mail.gmail.com>
Message-ID: <4EF56F25.6070206@redfish-solutions.com>

On 12/23/11 9:16 PM, ron minnich wrote:
> I'm just getting back to coreboot. Is libpayload used verbatim in the
> kernel? The phys/virt map in coreboot is 1:1 by design. The mapping
> seems unnecessary to me. Just wondering.
> 
> ron
> 

The code is being borrowed to use in linux as well to help parse the coreboot tables for platform drivers that need to determine they're running on the correct model/part # of the motherboard.



From kevin at koconnor.net  Sat Dec 24 07:34:16 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 24 Dec 2011 01:34:16 -0500
Subject: [coreboot] Asus M4A78LT-M status
In-Reply-To: <1468547.iUyCbOd7pl@odin>
References: <1468547.iUyCbOd7pl@odin>
Message-ID: <20111224063416.GA17129@morn.localdomain>

On Sun, Dec 18, 2011 at 11:03:50PM +0100, Christian Ruppert wrote:
> c)
> Not sure if I just misunderstood something.. I have GRUB 1 / legacy installed 
> on my disk and SeaBIOS tries to load GRUB but then it freezes. From what I've 
> read only GRUB 2 is supported as *payload*. Does it also apply to GRUB on a 
> disk?

SeaBIOS should be able to boot grub 1.

Looking through your logs, it appears you have both coreboot and
seabios set to execute option roms - this can confuse the hardware -
when using seabios, only seabios should execute the option roms.  I
can't say if this is the cause of your issue.

-Kevin


From patrick at georgi-clan.de  Sat Dec 24 08:51:01 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 24 Dec 2011 08:51:01 +0100
Subject: [coreboot] New patch to review for coreboot: db051bf Fix
 missing VM mapping
In-Reply-To: <CAP6exYKYTPuxh0k-UUTAebq4VLTtJCKk_sTAOpcY7pa0irym4g@mail.gmail.com>
References: <I35ef637fbec7886d4cfeac5fd650a17eae8d555a+0@gerrit.coreboot.org>	<I35ef637fbec7886d4cfeac5fd650a17eae8d555a+1@gerrit.coreboot.org>
	<CAP6exYKYTPuxh0k-UUTAebq4VLTtJCKk_sTAOpcY7pa0irym4g@mail.gmail.com>
Message-ID: <4EF58465.2090603@georgi-clan.de>

Am 24.12.2011 05:16, schrieb ron minnich:
> I'm just getting back to coreboot. Is libpayload used verbatim in the
> kernel? The phys/virt map in coreboot is 1:1 by design. The mapping
> seems unnecessary to me. Just wondering.
libpayload provides phys/virt mapping because FILO relocates itself to
high memory.

Side note:
At some point, I'd like to see generic relocation support in libpayload
as most payloads can benefit from being moved to top-of-ram, to make
space for OS kernels.


Patrick


From gerrit at coreboot.org  Sat Dec 24 11:50:09 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 24 Dec 2011 11:50:09 +0100
Subject: [coreboot] Patch merged into coreboot/master: 250f8aa Replace
	UNPACK_CB64 macro with inline
References: <Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a+0@gerrit.coreboot.org>
Message-ID: <E1RePB3-0003xh-Nh@ra.coresystems.de>

the following patch was just integrated into master:
commit 250f8aa63a19efbeecca74d4330dd5c483c741d3
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:09:02 2011 -0700

    Replace UNPACK_CB64 macro with inline
    
    Having submitted a module based on coreboot to LKML for acceptance,
    it was requested that fewer macros and more inlines be used (because
    of their superior type-checking when performing pointer casts, etc).
    
    This is the first of several changes to make the relevant parts of
    coreboot comply to linux code standards.
    
    Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Dec 24 11:50:07 2011, giving +2
See http://review.coreboot.org/495 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec 24 11:51:16 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 24 Dec 2011 11:51:16 +0100
Subject: [coreboot] Patch merged into coreboot/master: bde7653 Use
	convenience function to checksum
References: <I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370+0@gerrit.coreboot.org>
Message-ID: <E1RePC8-0004EX-RK@ra.coresystems.de>

the following patch was just integrated into master:
commit bde765381d216bb9144b3950aa101d6e987ebc07
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:22:05 2011 -0700

    Use convenience function to checksum
    
    That coreboot uses the IP checksum is an artifact, not a deliberate
    requirement to be compatible with the Internet Protocole suite. Use
    a wrapper to abstract the computation of coreboot's checksum.
    
    Change-Id: I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Dec 24 11:51:13 2011, giving +2
See http://review.coreboot.org/497 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec 24 11:52:17 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 24 Dec 2011 11:52:17 +0100
Subject: [coreboot] Patch merged into coreboot/master: 956c9c2 Use void
	pointers for untyped memory
References: <I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3+0@gerrit.coreboot.org>
Message-ID: <E1RePD7-0004SO-NI@ra.coresystems.de>

the following patch was just integrated into master:
commit 956c9c27504107109f11ef7113efa6448acea6df
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:28:59 2011 -0700

    Use void pointers for untyped memory
    
    To avoid unnecessary casts, we can use untyped pointers when accessing
    individual records.
    
    Change-Id: I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Dec 24 11:52:15 2011, giving +2
See http://review.coreboot.org/498 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec 24 11:56:15 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 24 Dec 2011 11:56:15 +0100
Subject: [coreboot] Patch merged into coreboot/master: db051bf Fix missing
	VM mapping
References: <I35ef637fbec7886d4cfeac5fd650a17eae8d555a+0@gerrit.coreboot.org>
Message-ID: <E1RePGx-0005lZ-Lb@ra.coresystems.de>

the following patch was just integrated into master:
commit db051bf5228810b95952960bdc66fb37f004c09f
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:36:09 2011 -0700

    Fix missing VM mapping
    
    When processing FORWARD records, we weren't accounting for the pointer
    being in the physical address space and not the virtual space instead.
    
    Change-Id: I35ef637fbec7886d4cfeac5fd650a17eae8d555a
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Dec 24 11:53:34 2011, giving +2
See http://review.coreboot.org/499 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec 24 11:56:55 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 24 Dec 2011 11:56:55 +0100
Subject: [coreboot] Patch merged into coreboot/master: 98cd3c8 Fix missing
	cast back to void *
References: <I0ec64ad7bdb136d5e1a999bff3df6fa66eb29bf1+0@gerrit.coreboot.org>
Message-ID: <E1RePHb-00079F-2n@ra.coresystems.de>

the following patch was just integrated into master:
commit 98cd3c8d5b16d4369e25ddca6a313d59f2a0bf4a
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 17:53:26 2011 -0700

    Fix missing cast back to void *
    
    MEM_RANGE_PTR() also needs to return a pointer to untyped memory.
    
    Change-Id: I0ec64ad7bdb136d5e1a999bff3df6fa66eb29bf1
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Dec 24 11:56:51 2011, giving +2
See http://review.coreboot.org/500 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec 24 12:02:22 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 24 Dec 2011 12:02:22 +0100
Subject: [coreboot] Patch merged into coreboot/master: e11cec9 Let
	lib_get_sysinfo() pass through the success of get_coreboot_info()
References: <I0176c93ee92c9dff733112026ee50f2ca797bdff+0@gerrit.coreboot.org>
Message-ID: <E1RePMs-0002Tg-Sb@ra.coresystems.de>

the following patch was just integrated into master:
commit e11cec94e22b2a6c4086656006a0667ec648e0d5
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:33:05 2011 -0700

    Let lib_get_sysinfo() pass through the success of get_coreboot_info()
    
    The return status of get_coreboot_info() might be handy to a platform
    driver calling lib_get_sysinfo() to test for the presence of coreboot.
    
    Change-Id: I0176c93ee92c9dff733112026ee50f2ca797bdff
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Dec 24 12:02:12 2011, giving +2
See http://review.coreboot.org/503 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec 24 12:07:53 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 24 Dec 2011 12:07:53 +0100
Subject: [coreboot] Patch merged into coreboot/master: 9f7c092 libpayload:
	remove uhci_reg_maskX
References: <Id0eb8327293831e54249d43fd06d50963c793699+0@gerrit.coreboot.org>
Message-ID: <E1RePSD-0006BX-FI@ra.coresystems.de>

the following patch was just integrated into master:
commit 9f7c092cc6dc9101fcc3db20914b0efb69686e84
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Fri Nov 18 14:44:16 2011 +0100

    libpayload: remove uhci_reg_maskX
    
    Not that good an idea to start with.
    
    Coccinelle patch:
    @@
    @@
    -void
    (
    -uhci_reg_mask8
    |
    -uhci_reg_mask16
    |
    -uhci_reg_mask32
    )
    - (...) { ... }
    
    @@
    @@
    -void
    (
    -uhci_reg_mask8
    |
    -uhci_reg_mask16
    |
    -uhci_reg_mask32
    )
    - (...);
    
    @@
    expression ctrl, reg, ormask;
    @@
    -uhci_reg_mask32 (ctrl, reg, ~0, ormask)
    +uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) | ormask)
    
    @@
    expression ctrl, reg, ormask;
    @@
    -uhci_reg_mask16 (ctrl, reg, ~0, ormask)
    +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) | ormask)
    
    @@
    expression ctrl, reg, ormask;
    @@
    -uhci_reg_mask8 (ctrl, reg, ~0, ormask)
    +uhci_reg_write8 (ctrl, reg, uhci_reg_read8 (ctrl, reg) | ormask)
    
    @@
    expression ctrl, reg, andmask;
    @@
    -uhci_reg_mask32 (ctrl, reg, andmask, 0)
    +uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) & andmask)
    
    @@
    expression ctrl, reg, andmask;
    @@
    -uhci_reg_mask16 (ctrl, reg, andmask, 0)
    +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask)
    
    @@
    expression ctrl, reg, andmask;
    @@
    -uhci_reg_mask16 (ctrl, reg, andmask, 0)
    +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask)
    
    Change-Id: Id0eb8327293831e54249d43fd06d50963c793699
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>


See http://review.coreboot.org/477 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec 24 12:10:16 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 24 Dec 2011 12:10:16 +0100
Subject: [coreboot] Patch merged into coreboot/master: c5ffb4f Only BSP CPU
	writes CMOS in bootblock code
References: <I29118e33c07c0080c94abb90f703e38312c72432+0@gerrit.coreboot.org>
Message-ID: <E1RePUW-0003HE-Bh@ra.coresystems.de>

the following patch was just integrated into master:
commit c5ffb4f0fcb1bf57a6376234ecf411678080569c
Author: Ky??sti M??lkki <kyosti.malkki at gmail.com>
Date:   Mon Dec 5 20:17:17 2011 +0200

    Only BSP CPU writes CMOS in bootblock code
    
    CMOS accesses are not safe for multi-processor and only the BSP CPU
    should count reboots and test CMOS sanity.
    
    A questionable single byte CMOS read access from AP CPUs remains.
    AP CPUs should always select the same romstage prefix as BSP CPU.
    
    Change-Id: I29118e33c07c0080c94abb90f703e38312c72432
    Signed-off-by: Ky??sti M??lkki <kyosti.malkki at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Dec 24 12:10:01 2011, giving +2
See http://review.coreboot.org/446 for details.

-gerrit


From gerrit at coreboot.org  Sat Dec 24 12:25:23 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 24 Dec 2011 12:25:23 +0100
Subject: [coreboot] Patch merged into coreboot/master: c56b7fb Sconfig:
	parse Kconfig options from devicetree.cb
References: <I808d44af552dbc5e0565d6a0f4f72c7be9f5740e+0@gerrit.coreboot.org>
Message-ID: <E1RePj9-000401-FQ@ra.coresystems.de>

the following patch was just integrated into master:
commit c56b7fb47a0088292046d5cc2b6f4941273fb675
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Mon Dec 5 20:33:55 2011 +0200

    Sconfig: parse Kconfig options from devicetree.cb
    
    Mainboard and chip Kconfig files have several build options that
    are redundant with information in devicetree.cb. This patch enables
    sconfig to auto-generate equivalent configuration.
    
      sconfig -s
    
    Generates mainboard's static.c file, as before.
    
      sconfig -b
    
    This operation creates mainboard's bootblock init code. By default,
    for every chip listed in mainboard/devicetree.cb, if there is a
    chip/bootblock.c file, the init function is called.
    A mainboard/bootblock.c file can be added to override default
    behaviour.
    
      sconfig -k
    
    This operation generates select -options for component paths.
    
    Change-Id: I808d44af552dbc5e0565d6a0f4f72c7be9f5740e
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Dec 24 12:25:09 2011, giving +2
See http://review.coreboot.org/472 for details.

-gerrit


From c-d.hailfinger.devel.2006 at gmx.net  Sun Dec 25 00:18:53 2011
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 25 Dec 2011 00:18:53 +0100
Subject: [coreboot] [PATCH] superiotool: add EOT for Infineon ports
In-Reply-To: <4EC95E01.6070405@gmail.com>
References: <4EC95E01.6070405@gmail.com>
Message-ID: <4EF65DDD.3010801@gmx.net>

Am 20.11.2011 21:07 schrieb Joshua Roys:
> This patch prevents a long loop through memory until superiotool finds
> an EOT.
>
> Signed-off-by: Joshua Roys <roysjosh at gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/



From c-d.hailfinger.devel.2006 at gmx.net  Sun Dec 25 00:19:24 2011
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 25 Dec 2011 00:19:24 +0100
Subject: [coreboot] [PATCH] superiotool.h: Add `EOT` to end of entry
In-Reply-To: <1324412001.4397.2.camel@mattotaupa>
References: <1324412001.4397.2.camel@mattotaupa>
Message-ID: <4EF65DFC.4050009@gmx.net>

Am 20.12.2011 21:13 schrieb Paul Menzel:
> Date: Mon, 19 Dec 2011 23:50:32 +0100
>
> This is a fix up for commit 3d1d6bb4 which forgot to add `EOT` at the end.
>
>         commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576
>         Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
>         Date:   Mon Nov 7 10:56:42 2011 -0600
>
>             superiotool: add detection and dump of Infineon SLB9635 TPM
>
> Carl-Daniel explained the continuous integration tool Jenkins did not
> catch that, since this is a run time bug. It accesses uninitialized
> memory until it crashes and writes random data to random I/O locations.
>
> Reported-by (on IRC): Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/



From gerrit at coreboot.org  Sun Dec 25 06:16:24 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sun, 25 Dec 2011 06:16:24 +0100
Subject: [coreboot] Patch set updated for coreboot: a97069d
	cb_parse_header() should not assume table in 4K of contiguous memory
References: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+0@gerrit.coreboot.org>
Message-ID: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+2@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/501

-gerrit

commit a97069d0d5ab55d2eb250c7870c1422b007e61ae
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:09:25 2011 -0700

    cb_parse_header() should not assume table in 4K of contiguous memory
    
    If we have the CB table in E820 memory, we might not have an entire 4K
    (0x1000) bytes of memory to scan through. Instead, a better strategy
    is to pass in a pointer to the end of the region or the start + 4K
    (which ever is lower). This change prepares the cb_parse_header()
    calling convention for that change.
    
    Change-Id: I9257726c6a7065b5596d4c32ab451edd0a3cdc10
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/libpayload/arch/i386/coreboot.c |   22 ++++++++++++++--------
 1 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 709f8ae..135c59c 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -109,21 +109,21 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 }
 #endif
 
-static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
+static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 {
 	struct cb_header *header;
-	unsigned char *ptr = addr;
+	unsigned char *ptr;
 	void *forward;
 	int i;
 
-	for (i = 0; i < len; i += 16, ptr += 16) {
+	for (ptr = addr; (void *)ptr < end; ptr += 16) {
 		header = (struct cb_header *)ptr;
 		if (!strncmp((const char *)header->signature, "LBIO", 4))
 			break;
 	}
 
 	/* We walked the entire space and didn't find anything. */
-	if (i >= len)
+	if ((void *)ptr >= end)
 		return -1;
 
 	if (!header->table_bytes)
@@ -147,7 +147,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		switch (rec->tag) {
 		case CB_TAG_FORWARD:
 			forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward);
-			return cb_parse_header(forward, len, info);
+			return cb_parse_header(forward, forward + 0x1000, info);
 			continue;
 		case CB_TAG_MEMORY:
 			cb_parse_memory(ptr, info);
@@ -176,6 +176,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		}
 
 		ptr += rec->size;
+
+		if ((void *)ptr >= end)
+			return -1;
 	}
 
 	return 1;
@@ -186,10 +189,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 
 int get_coreboot_info(struct sysinfo_t *info)
 {
-	int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
+	void *base = phys_to_virt(0x00000000);
+	int ret = cb_parse_header(base, base + 0x1000, info);
 
-	if (ret != 1)
-		ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
+	if (ret != 1) {
+		base = phys_to_virt(0x000f0000);
+		ret = cb_parse_header(base, base + 0x1000, info);
+	}
 
 	return (ret == 1) ? 0 : -1;
 }


From gerrit at coreboot.org  Sun Dec 25 06:16:25 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sun, 25 Dec 2011 06:16:25 +0100
Subject: [coreboot] Patch set updated for coreboot: 257dc76 Cleanup access
	to vendor/part # info
References: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+0@gerrit.coreboot.org>
Message-ID: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+2@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502

-gerrit

commit 257dc761876550715f9969ce6042b4b50f27b005
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sat Dec 24 22:12:37 2011 -0700

    Cleanup access to vendor/part # info
    
    Instead of macros to access MAINBOARD record, use convenience functions.
    
    Store pointers to MAINBOARD and HEADER for use outside of CB code.
    
    Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    4 ++--
 payloads/libpayload/arch/i386/coreboot.c      |    5 +++++
 payloads/libpayload/include/coreboot_tables.h |   16 ++++++++++------
 payloads/libpayload/include/sysinfo.h         |    3 +++
 4 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index 7289366..d33ea9e 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31);
-	strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31);
+	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31);
+	strncpy(cb_info.part, cb_mb_part_string(mb), 31);
 }
 
 static void parse_strings(unsigned char *ptr)
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 135c59c..7fe286e 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 		     header->table_bytes) != header->table_checksum)
 		return -1;
 
+	info->header = header;
+
 	/* Now, walk the tables. */
 	ptr += header->header_bytes;
 
@@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 			cb_parse_framebuffer(ptr, info);
 			break;
 #endif
+		case CB_TAG_MAINBOARD:
+			info->mainboard = (struct cb_mainboard *)ptr;
+			break;
 		}
 
 		ptr += rec->size;
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index e362d06..c68ccc9 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	return ipchksum(ptr, len);
 }
 
+static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->vendor_idx);
+}
+
+static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->part_number_idx);
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
@@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
 		+ (sizeof((_rec)->map[0]) * (_idx)))
 
-#define MB_VENDOR_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
-
-#define MB_PART_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
-
 #endif
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c1d2002..778dfe9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -56,6 +56,9 @@ struct sysinfo_t {
 	struct cb_framebuffer *framebuffer;
 
 	unsigned long *mbtable; /** Pointer to the multiboot table */
+
+	struct cb_header *header;
+	struct cb_mainboard *mainboard;
 };
 
 extern struct sysinfo_t lib_sysinfo;


From gerrit at coreboot.org  Sun Dec 25 21:50:56 2011
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Sun, 25 Dec 2011 21:50:56 +0100
Subject: [coreboot] New patch to review for coreboot: 1818697 trivial:change
	the value type of POST_PORT in Kconfig from int to hex
References: <Ib6bb4ccfabaa3af18b48a23a51a576b872d807a8+0@gerrit.coreboot.org>
Message-ID: <Ib6bb4ccfabaa3af18b48a23a51a576b872d807a8+1@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/505

-gerrit

commit 181869715598f0ad7cc665027d98671d013908ca
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Mon Dec 26 02:08:44 2011 +0530

    trivial:change the value type of POST_PORT in Kconfig from int to hex
    
    trivial change in src/console/Kconfig
    
    Change-Id: Ib6bb4ccfabaa3af18b48a23a51a576b872d807a8
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/console/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/console/Kconfig b/src/console/Kconfig
index 8382695..dbd11f6 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -334,7 +334,7 @@ config NO_POST
 	default n
 
 config POST_PORT
-	int
+	hex
 	default 0x80
 
 config CONSOLE_POST


From gerrit at coreboot.org  Mon Dec 26 08:52:08 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 26 Dec 2011 08:52:08 +0100
Subject: [coreboot] Patch merged into coreboot/master: 1818697
	trivial:change the value type of POST_PORT in Kconfig from
	int to hex
References: <Ib6bb4ccfabaa3af18b48a23a51a576b872d807a8+0@gerrit.coreboot.org>
Message-ID: <E1Rf5Ls-0008N5-NO@ra.coresystems.de>

the following patch was just integrated into master:
commit 181869715598f0ad7cc665027d98671d013908ca
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Mon Dec 26 02:08:44 2011 +0530

    trivial:change the value type of POST_PORT in Kconfig from int to hex
    
    trivial change in src/console/Kconfig
    
    Change-Id: Ib6bb4ccfabaa3af18b48a23a51a576b872d807a8
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Mon Dec 26 08:52:06 2011, giving +2
See http://review.coreboot.org/505 for details.

-gerrit


From gerrit at coreboot.org  Mon Dec 26 08:53:04 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 26 Dec 2011 08:53:04 +0100
Subject: [coreboot] Patch merged into coreboot/master: 482f534 Fix Fam10
	MMCONF_SUPPORT_DEFAULT setting.
References: <If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234+0@gerrit.coreboot.org>
Message-ID: <E1Rf5Mm-0000AA-Mu@ra.coresystems.de>

the following patch was just integrated into master:
commit 482f5346ca1a49602cf0b3a3f69a22442a25dab1
Author: Marc Jones <marcj303 at gmail.com>
Date:   Wed Dec 14 15:33:33 2011 -0700

    Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.
    
    I misunderstood how kconfig select works. It needs to be selected with a config option. Moved the select to the correct location.
    
    Change-Id: If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Mon Dec 26 08:53:00 2011, giving +2
See http://review.coreboot.org/487 for details.

-gerrit


From svn at coreboot.org  Mon Dec 26 16:00:01 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 26 Dec 2011 16:00:01 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1RfC1x-0002k6-FB@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20111226/c0c5110a/attachment-0001.html>

From gerrit at coreboot.org  Mon Dec 26 18:27:23 2011
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Mon, 26 Dec 2011 18:27:23 +0100
Subject: [coreboot] New patch to review for coreboot: e267d74 Indentation:
	Various indentation fixes
References: <I5b396e5753544aff13ac5d16afc59e193a6b1da1+0@gerrit.coreboot.org>
Message-ID: <I5b396e5753544aff13ac5d16afc59e193a6b1da1+1@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/506

-gerrit

commit e267d74eb35f6df29e9463faf6c75b3f7989af07
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Mon Dec 26 22:52:01 2011 +0530

    Indentation: Various indentation fixes
    
    Fixed indentation using indent tool in the src/drivers/i2c tree
    
    Change-Id: I5b396e5753544aff13ac5d16afc59e193a6b1da1
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/drivers/i2c/adm1026/adm1026.c |   38 ++++++++++++++++++------------------
 src/drivers/i2c/adm1027/adm1027.c |    9 +++----
 src/drivers/i2c/adt7463/adt7463.c |    8 +++---
 src/drivers/i2c/i2cmux/i2cmux.c   |   26 +++++++++++-------------
 src/drivers/i2c/i2cmux2/i2cmux2.c |   24 ++++++++++------------
 src/drivers/i2c/lm63/lm63.c       |   24 ++++++++++------------
 6 files changed, 61 insertions(+), 68 deletions(-)

diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c
index 14b07aa..1aaae52 100644
--- a/src/drivers/i2c/adm1026/adm1026.c
+++ b/src/drivers/i2c/adm1026/adm1026.c
@@ -7,7 +7,7 @@
 #include <cpu/x86/msr.h>
 #include "chip.h"
 
-#define ADM1026_DEVICE 0x2d /* Either 0x2c or 0x2d or 0x2e */
+#define ADM1026_DEVICE 0x2d	/* Either 0x2c or 0x2d or 0x2e */
 #define ADM1026_REG_CONFIG1 0x00
 #define CFG1_MONITOR     0x01
 #define CFG1_INT_ENABLE  0x02
@@ -24,38 +24,38 @@ static void adm1026_enable_monitoring(device_t dev);
 
 static void adm1026_init(device_t dev)
 {
-	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
-	{
-		if(ops_smbus_bus(get_pbus_smbus(dev))) {
-			if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux
+	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) {
+		if (ops_smbus_bus(get_pbus_smbus(dev))) {
+			if (dev->bus->dev->path.type == DEVICE_PATH_I2C)
+				smbus_set_link(dev);	// it is under mux
 			adm1026_enable_monitoring(dev);
 		}
-
 	}
-
 }
+
 static void adm1026_enable_monitoring(device_t dev)
 {
-        int result;
-        result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
+	int result;
+	result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
 
-        result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET);
-        result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result);
+	result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET);
+	result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result);
 
-        result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
-        if (!(result & CFG1_MONITOR)) {
-                printk(BIOS_DEBUG, "ADM1026: monitoring would not enable");
-        }
+	result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
+	if (!(result & CFG1_MONITOR)) {
+		printk(BIOS_DEBUG, "ADM1026: monitoring would not enable");
+	}
 }
+
 static void adm1026_noop(device_t dummy)
 {
 }
 
 static struct device_operations adm1026_operations = {
-        .read_resources   = adm1026_noop,
-        .set_resources    = adm1026_noop,
-        .enable_resources = adm1026_noop,
-        .init             = adm1026_init,
+	.read_resources = adm1026_noop,
+	.set_resources = adm1026_noop,
+	.enable_resources = adm1026_noop,
+	.init = adm1026_init,
 };
 
 static void enable_dev(struct device *dev)
diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c
index bca2c0d..516a889 100644
--- a/src/drivers/i2c/adm1027/adm1027.c
+++ b/src/drivers/i2c/adm1027/adm1027.c
@@ -47,7 +47,6 @@ static void adm1027_init(device_t dev)
 				smbus_set_link(dev);	// it is under mux
 			adm1027_enable_monitoring(dev);
 		}
-
 	}
 }
 
@@ -56,10 +55,10 @@ static void adm1027_noop(device_t dummy)
 }
 
 static struct device_operations adm1027_operations = {
-	.read_resources		= adm1027_noop,
-	.set_resources		= adm1027_noop,
-	.enable_resources	= adm1027_noop,
-	.init			= adm1027_init,
+	.read_resources = adm1027_noop,
+	.set_resources = adm1027_noop,
+	.enable_resources = adm1027_noop,
+	.init = adm1027_init,
 };
 
 static void enable_dev(struct device *dev)
diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c
index 25a65c8..3967bf7 100644
--- a/src/drivers/i2c/adt7463/adt7463.c
+++ b/src/drivers/i2c/adt7463/adt7463.c
@@ -91,10 +91,10 @@ static void adt7463_noop(device_t dummy)
 }
 
 static struct device_operations adt7463_operations = {
-	.read_resources		= adt7463_noop,
-	.set_resources		= adt7463_noop,
-	.enable_resources	= adt7463_noop,
-	.init			= adt7463_init,
+	.read_resources = adt7463_noop,
+	.set_resources = adt7463_noop,
+	.enable_resources = adt7463_noop,
+	.init = adt7463_init,
 };
 
 static void enable_dev(struct device *dev)
diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c
index 14c52cc..44bf390 100644
--- a/src/drivers/i2c/i2cmux/i2cmux.c
+++ b/src/drivers/i2c/i2cmux/i2cmux.c
@@ -9,32 +9,30 @@
 
 static void i2cmux_set_link(device_t dev, unsigned int link)
 {
-	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
-	{
-		if(ops_smbus_bus(get_pbus_smbus(dev))) {
-			smbus_write_byte(dev, 0x01, 1<<link); // output value
-			smbus_write_byte(dev, 0x03, 0); // all output
+	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) {
+		if (ops_smbus_bus(get_pbus_smbus(dev))) {
+			smbus_write_byte(dev, 0x01, 1 << link);	// output value
+			smbus_write_byte(dev, 0x03, 0);	// all output
 		}
-
 	}
-
 }
+
 static void i2cmux_noop(device_t dummy)
 {
 }
 
 static struct device_operations i2cmux_operations = {
-        .read_resources   = i2cmux_noop,
-        .set_resources    = i2cmux_noop,
-        .enable_resources = i2cmux_noop,
-        .init             = i2cmux_noop,
-	.scan_bus         = scan_static_bus,
-	.set_link	  = i2cmux_set_link,
+	.read_resources = i2cmux_noop,
+	.set_resources = i2cmux_noop,
+	.enable_resources = i2cmux_noop,
+	.init = i2cmux_noop,
+	.scan_bus = scan_static_bus,
+	.set_link = i2cmux_set_link,
 };
 
 static void enable_dev(struct device *dev)
 {
-	if(dev->link_list != NULL)
+	if (dev->link_list != NULL)
 		dev->ops = &i2cmux_operations;
 }
 
diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c
index c0f8e70..dc8ec25 100644
--- a/src/drivers/i2c/i2cmux2/i2cmux2.c
+++ b/src/drivers/i2c/i2cmux2/i2cmux2.c
@@ -9,31 +9,29 @@
 
 static void i2cmux2_set_link(device_t dev, unsigned int link)
 {
-	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
-	{
-		if(ops_smbus_bus(get_pbus_smbus(dev))) {
-			smbus_send_byte(dev, link); // output value
+	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) {
+		if (ops_smbus_bus(get_pbus_smbus(dev))) {
+			smbus_send_byte(dev, link);	// output value
 		}
-
 	}
-
 }
+
 static void i2cmux2_noop(device_t dummy)
 {
 }
 
 static struct device_operations i2cmux2_operations = {
-        .read_resources   = i2cmux2_noop,
-        .set_resources    = i2cmux2_noop,
-        .enable_resources = i2cmux2_noop,
-        .init             = i2cmux2_noop,
-	.scan_bus         = scan_static_bus,
-	.set_link	  = i2cmux2_set_link,
+	.read_resources = i2cmux2_noop,
+	.set_resources = i2cmux2_noop,
+	.enable_resources = i2cmux2_noop,
+	.init = i2cmux2_noop,
+	.scan_bus = scan_static_bus,
+	.set_link = i2cmux2_set_link,
 };
 
 static void enable_dev(struct device *dev)
 {
-	if(dev->link_list != NULL)
+	if (dev->link_list != NULL)
 		dev->ops = &i2cmux2_operations;
 }
 
diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c
index 05302a6..d98a245 100644
--- a/src/drivers/i2c/lm63/lm63.c
+++ b/src/drivers/i2c/lm63/lm63.c
@@ -7,32 +7,30 @@
 #include <cpu/x86/msr.h>
 #include "chip.h"
 
-
 static void lm63_init(device_t dev)
 {
 	int result;
-	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
-	{
-		if(ops_smbus_bus(get_pbus_smbus(dev))) {
-			if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux
+	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) {
+		if (ops_smbus_bus(get_pbus_smbus(dev))) {
+			if (dev->bus->dev->path.type == DEVICE_PATH_I2C)
+				smbus_set_link(dev);	// it is under mux
 			result = smbus_read_byte(dev, 0x03);
-//			result &= ~0x04;
+//                      result &= ~0x04;
 			result |= 0x04;
-			smbus_write_byte(dev, 0x03, result & 0xff); // config lm63
+			smbus_write_byte(dev, 0x03, result & 0xff);	// config lm63
 		}
-
 	}
-
 }
+
 static void lm63_noop(device_t dummy)
 {
 }
 
 static struct device_operations lm63_operations = {
-        .read_resources   = lm63_noop,
-        .set_resources    = lm63_noop,
-        .enable_resources = lm63_noop,
-        .init             = lm63_init,
+	.read_resources = lm63_noop,
+	.set_resources = lm63_noop,
+	.enable_resources = lm63_noop,
+	.init = lm63_init,
 };
 
 static void enable_dev(struct device *dev)


From gerrit at coreboot.org  Mon Dec 26 19:09:07 2011
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Mon, 26 Dec 2011 19:09:07 +0100
Subject: [coreboot] New patch to review for coreboot: 05634a9 APIC: Fixed
	reading MSR_FSB_FREQ register
References: <I6bf93bac1ee9123af78c003f5a0728f8f0801958+0@gerrit.coreboot.org>
Message-ID: <I6bf93bac1ee9123af78c003f5a0728f8f0801958+1@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/507

-gerrit

commit 05634a9703cb7c52a882a67669800e79a5101e99
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Mon Dec 26 23:30:23 2011 +0530

    APIC: Fixed reading MSR_FSB_FREQ register
    
    According to Intel's manual, bits 0:2 of MSR 0xCDh gives the FSB
    frequency. But the code had a right shift of 4 which will always
    give 267 MHz, as the valid bits are shifted to right.
    Also, fixed the indentations.
    
    Change-Id: I6bf93bac1ee9123af78c003f5a0728f8f0801958
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/cpu/x86/lapic/apic_timer.c |   31 +++++++++++++++++++++----------
 1 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 826f5b6..312951a 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -27,9 +27,10 @@
  * memory init.
  */
 
-#define FSB_CLOCK_STS 0xcd
+#define FSB_CLOCK_STS 0xCD
+#define FSB_FREQ_MASK 0x07
 
-static u32 timer_fsb = 200; // default to 200MHz
+static u32 timer_fsb = 200;	// default to 200MHz
 
 void init_timer(void)
 {
@@ -42,16 +43,26 @@ void init_timer(void)
 	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
 
 	/* Set the initial counter to 0xffffffff */
-	lapic_write(LAPIC_TMICT, 0xffffffff);
+	lapic_write(LAPIC_TMICT, ~0UL);
 
 	/* Set FSB frequency to a reasonable value */
 	fsb_clock_sts = rdmsr(FSB_CLOCK_STS);
-	switch ((fsb_clock_sts.lo >> 4) & 0x07) {
-	case 0: timer_fsb = 266; break;
-	case 1: timer_fsb = 133; break;
-	case 2: timer_fsb = 200; break;
-	case 3: timer_fsb = 166; break;
-	case 5: timer_fsb = 100; break;
+	switch (fsb_clock_sts.lo & FSB_FREQ_MASK) {
+	case 0:
+		timer_fsb = 266;
+		break;
+	case 1:
+		timer_fsb = 133;
+		break;
+	case 2:
+		timer_fsb = 200;
+		break;
+	case 3:
+		timer_fsb = 166;
+		break;
+	case 5:
+		timer_fsb = 100;
+		break;
 	}
 }
 
@@ -63,5 +74,5 @@ void udelay(u32 usecs)
 	start = lapic_read(LAPIC_TMCCT);
 	do {
 		value = lapic_read(LAPIC_TMCCT);
-	} while((start - value) < ticks);
+	} while ((start - value) < ticks);
 }


From peter at stuge.se  Tue Dec 27 02:53:34 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 27 Dec 2011 02:53:34 +0100
Subject: [coreboot] coreboot dinner in Berlin today Tuesday 27/12 at 1800 CET
Message-ID: <20111227015334.12691.qmail@stuge.se>

Hi all!

During the 28th Chaos Communication Congress [1] which starts today
there is an unusually high concentration of coreboot developers and
enthusiasts in Berlin, so this is a nice opportunity to have dinner
together, and perhaps chat a bit or two about firmware!

After reviewing the schedule of presentations (fahrplan [2]) it seems
that Day 1 may be the best suited for doing a dinner together, since
we may want to spend a little bit more time than the scheduled dinner
break in the evening.

The particular venue is as yet undecided. If I haven't made it to
dolores [3] for lunch I would be happy to go there. The food is
amazing. So far I know of roughly 7 persons who might join, and
although dolores is not optimal for a group of 7 sitting around and
chatting, we will be able to fit easily, especially since we are
starting a little bit earlier than the scheduled dinner break.

Other options include a few nice nearby restaurants, or possibly even
going on a slightly longer excursion eastbound to the Friedrichshain
area where there are plenty of nice restaurants.

Let's meet at 1800 CET somewhere around the wardrobe/exit in the bcc
building.

Please don't hesitate to follow up with your suggestions or wishes
for a particular restaurant, and in any case I hope you see you
tomorrow evening!


Kind regards (and sorry for the short notice!)

//Peter


From peter at stuge.se  Tue Dec 27 03:24:54 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 27 Dec 2011 03:24:54 +0100
Subject: [coreboot] coreboot dinner in Berlin today Tuesday 27/12
	at	1800 CET
In-Reply-To: <20111227015334.12691.qmail@stuge.se>
References: <20111227015334.12691.qmail@stuge.se>
Message-ID: <20111227022454.16752.qmail@stuge.se>

Peter Stuge wrote:
> 28th Chaos Communication Congress [1]
> fahrplan [2]
> dolores [3]

[1] http://events.ccc.de/congress/2011/wiki/Welcome
[2] http://events.ccc.de/congress/2011/Fahrplan/
[3] http://www.dolores-online.de/index_mitte.html


//Peter


From ruchi.chopra at stericsson.com  Tue Dec 27 04:35:04 2011
From: ruchi.chopra at stericsson.com (Ruchi CHOPRA)
Date: Tue, 27 Dec 2011 04:35:04 +0100
Subject: [coreboot]  New bie to coreboot development
In-Reply-To: <I6bf93bac1ee9123af78c003f5a0728f8f0801958+1@gerrit.coreboot.org>
References: <I6bf93bac1ee9123af78c003f5a0728f8f0801958+0@gerrit.coreboot.org>
	<I6bf93bac1ee9123af78c003f5a0728f8f0801958+1@gerrit.coreboot.org>
Message-ID: <2E48302EED53D048A7BA72B0A307FB511CF4F6E7E7@EXDCVYMBSTM005.EQ1STM.local>

Hi Friends,
   I am a new bie to coreboot.
I want to start learning coreboot and then finally wants to port it to some hardware which is not yet supported.

Can you please indicate me how can I learn about coreboot architecture and implementation.
If it has to be done only through understanding the code, is there any flow diagram or something similar which helps in understanding the code easily and fastly.

Thanks in advance for your response!!

Best Regards,
Ruchi



From njacobs8 at adsltotaal.nl  Tue Dec 27 23:21:00 2011
From: njacobs8 at adsltotaal.nl (Nils)
Date: Tue, 27 Dec 2011 23:21:00 +0100
Subject: [coreboot]  tiny bootblock problem
Message-ID: <1325024460.2022.13.camel@Debian.lan>

Hi all,
I was updating some old patches to get them ready for inclusion and
tested latest coreboot trunk. (first time with tiny bootblock)

My geode GX2 target does boot, but it takes 30 seconds to load
fallback/coreboot_ram .

Is that a caching problem introduced by tiny bootblock?
What is needed to get it right?

Thanks, Nils.
 



From gerrit at coreboot.org  Wed Dec 28 23:23:41 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 28 Dec 2011 23:23:41 +0100
Subject: [coreboot] Patch set updated for coreboot: 1c7c31d Eliminate magic
	numbers
References: <I2b7e0e4a8df6448d027cc61867382f161eb990d3+0@gerrit.coreboot.org>
Message-ID: <I2b7e0e4a8df6448d027cc61867382f161eb990d3+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/504

-gerrit

commit 1c7c31d5bf4243fdddb86f0d2a1a315c54703140
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:45:33 2011 -0700

    Eliminate magic numbers
    
    Use sizeof() on vendor and part# rather than explicit memory length.
    
    Change-Id: I2b7e0e4a8df6448d027cc61867382f161eb990d3
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index d33ea9e..77a4bb2 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31);
-	strncpy(cb_info.part, cb_mb_part_string(mb), 31);
+	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), sizeof(cb_info.vendor) - 1);
+	strncpy(cb_info.part, cb_mb_part_string(mb), sizeof(cb_info.part) - 1);
 }
 
 static void parse_strings(unsigned char *ptr)


From gerrit at coreboot.org  Wed Dec 28 23:23:42 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 28 Dec 2011 23:23:42 +0100
Subject: [coreboot] Patch set updated for coreboot: afc57f7 Cleanup access
	to vendor/part # info
References: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+0@gerrit.coreboot.org>
Message-ID: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502

-gerrit

commit afc57f7ce4bbfcae1257108fd549d33cdfd7c151
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sat Dec 24 22:12:37 2011 -0700

    Cleanup access to vendor/part # info
    
    Instead of macros to access MAINBOARD record, use convenience functions.
    
    Store pointers to MAINBOARD and HEADER for use outside of CB code.
    
    Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    4 ++--
 payloads/libpayload/arch/i386/coreboot.c      |    5 +++++
 payloads/libpayload/include/coreboot_tables.h |   16 ++++++++++------
 payloads/libpayload/include/sysinfo.h         |    3 +++
 4 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index 7289366..d33ea9e 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31);
-	strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31);
+	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31);
+	strncpy(cb_info.part, cb_mb_part_string(mb), 31);
 }
 
 static void parse_strings(unsigned char *ptr)
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 709f8ae..06acc17 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		     header->table_bytes) != header->table_checksum)
 		return -1;
 
+	info->header = header;
+
 	/* Now, walk the tables. */
 	ptr += header->header_bytes;
 
@@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 			cb_parse_framebuffer(ptr, info);
 			break;
 #endif
+		case CB_TAG_MAINBOARD:
+			info->mainboard = (struct cb_mainboard *)ptr;
+			break;
 		}
 
 		ptr += rec->size;
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index e362d06..c68ccc9 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	return ipchksum(ptr, len);
 }
 
+static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->vendor_idx);
+}
+
+static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->part_number_idx);
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
@@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
 		+ (sizeof((_rec)->map[0]) * (_idx)))
 
-#define MB_VENDOR_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
-
-#define MB_PART_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
-
 #endif
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c1d2002..778dfe9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -56,6 +56,9 @@ struct sysinfo_t {
 	struct cb_framebuffer *framebuffer;
 
 	unsigned long *mbtable; /** Pointer to the multiboot table */
+
+	struct cb_header *header;
+	struct cb_mainboard *mainboard;
 };
 
 extern struct sysinfo_t lib_sysinfo;


From gerrit at coreboot.org  Thu Dec 29 00:35:24 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Thu, 29 Dec 2011 00:35:24 +0100
Subject: [coreboot] Patch set updated for coreboot: 24ace2e
	cb_parse_header() should not assume table in 4K of contiguous memory
References: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+0@gerrit.coreboot.org>
Message-ID: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+3@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/501

-gerrit

commit 24ace2ea7da2db5c5f08f813ee6ce8c6147464cb
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:09:25 2011 -0700

    cb_parse_header() should not assume table in 4K of contiguous memory
    
    If we have the CB table in E820 memory, we might not have an entire 4K
    (0x1000) bytes of memory to scan through. Instead, a better strategy
    is to pass in a pointer to the end of the region or the start + 4K
    (which ever is lower). This change prepares the cb_parse_header()
    calling convention for that change.
    
    Change-Id: I9257726c6a7065b5596d4c32ab451edd0a3cdc10
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/libpayload/arch/i386/coreboot.c |   22 ++++++++++++++--------
 1 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 709f8ae..135c59c 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -109,21 +109,21 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 }
 #endif
 
-static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
+static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 {
 	struct cb_header *header;
-	unsigned char *ptr = addr;
+	unsigned char *ptr;
 	void *forward;
 	int i;
 
-	for (i = 0; i < len; i += 16, ptr += 16) {
+	for (ptr = addr; (void *)ptr < end; ptr += 16) {
 		header = (struct cb_header *)ptr;
 		if (!strncmp((const char *)header->signature, "LBIO", 4))
 			break;
 	}
 
 	/* We walked the entire space and didn't find anything. */
-	if (i >= len)
+	if ((void *)ptr >= end)
 		return -1;
 
 	if (!header->table_bytes)
@@ -147,7 +147,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		switch (rec->tag) {
 		case CB_TAG_FORWARD:
 			forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward);
-			return cb_parse_header(forward, len, info);
+			return cb_parse_header(forward, forward + 0x1000, info);
 			continue;
 		case CB_TAG_MEMORY:
 			cb_parse_memory(ptr, info);
@@ -176,6 +176,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		}
 
 		ptr += rec->size;
+
+		if ((void *)ptr >= end)
+			return -1;
 	}
 
 	return 1;
@@ -186,10 +189,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 
 int get_coreboot_info(struct sysinfo_t *info)
 {
-	int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
+	void *base = phys_to_virt(0x00000000);
+	int ret = cb_parse_header(base, base + 0x1000, info);
 
-	if (ret != 1)
-		ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
+	if (ret != 1) {
+		base = phys_to_virt(0x000f0000);
+		ret = cb_parse_header(base, base + 0x1000, info);
+	}
 
 	return (ret == 1) ? 0 : -1;
 }


From gerrit at coreboot.org  Thu Dec 29 00:35:24 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Thu, 29 Dec 2011 00:35:24 +0100
Subject: [coreboot] Patch set updated for coreboot: a1ce169 Cleanup access
	to vendor/part # info
References: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+0@gerrit.coreboot.org>
Message-ID: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+4@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502

-gerrit

commit a1ce169728cbae26db404959bc35f4779604d7ad
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sat Dec 24 22:12:37 2011 -0700

    Cleanup access to vendor/part # info
    
    Instead of macros to access MAINBOARD record, use convenience functions.
    
    Store pointers to MAINBOARD and HEADER for use outside of CB code.
    
    Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    4 ++--
 payloads/libpayload/arch/i386/coreboot.c      |    5 +++++
 payloads/libpayload/include/coreboot_tables.h |   16 ++++++++++------
 payloads/libpayload/include/sysinfo.h         |    3 +++
 4 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index 7289366..d33ea9e 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31);
-	strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31);
+	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31);
+	strncpy(cb_info.part, cb_mb_part_string(mb), 31);
 }
 
 static void parse_strings(unsigned char *ptr)
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 135c59c..7fe286e 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 		     header->table_bytes) != header->table_checksum)
 		return -1;
 
+	info->header = header;
+
 	/* Now, walk the tables. */
 	ptr += header->header_bytes;
 
@@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 			cb_parse_framebuffer(ptr, info);
 			break;
 #endif
+		case CB_TAG_MAINBOARD:
+			info->mainboard = (struct cb_mainboard *)ptr;
+			break;
 		}
 
 		ptr += rec->size;
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index e362d06..c68ccc9 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	return ipchksum(ptr, len);
 }
 
+static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->vendor_idx);
+}
+
+static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->part_number_idx);
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
@@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
 		+ (sizeof((_rec)->map[0]) * (_idx)))
 
-#define MB_VENDOR_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
-
-#define MB_PART_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
-
 #endif
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c1d2002..778dfe9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -56,6 +56,9 @@ struct sysinfo_t {
 	struct cb_framebuffer *framebuffer;
 
 	unsigned long *mbtable; /** Pointer to the multiboot table */
+
+	struct cb_header *header;
+	struct cb_mainboard *mainboard;
 };
 
 extern struct sysinfo_t lib_sysinfo;


From philipp_subx at redfish-solutions.com  Thu Dec 29 03:22:06 2011
From: philipp_subx at redfish-solutions.com (Philip Prindeville)
Date: Wed, 28 Dec 2011 19:22:06 -0700
Subject: [coreboot] Bricked 6F2
Message-ID: <4EFBCECE.40805@redfish-solutions.com>

Ok, I build coreboot's trunk and selected the target Alix2D, but managed to brick the device:

coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting...
MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:0000182e
Configuring PLL.


coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting...
MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:07de002e
PLL configured.
Castle 2.0 BTM periodic sync period.
Enable Quack for fewer re-RAS on the MC
 GLIU port active enable
Set the Delay Control in GLCP
spd_read_byte dev 50 addr 0d returns 08
spd_read_byte dev 50 addr 05 returns 01
spd_read_byte dev 51 returns 0xff
Enable RSDC
FPU imprecise exceptions bit
Enable Suspend on HLT & PAUSE instructions
Enable SUSP and allow TSC to run in Suspend
Setup throttling delays to proper mode
Done cpuRegInit
Ram1.00
Ram2.00
 * sdram_set_spd_register
spd_read_byte dev 50 addr 15 returns ff
 * Check DIMM 0
 * Check DIMM 1
spd_read_byte dev 51 returns 0xff
 * Check DDR MAX
spd_read_byte dev 50 addr 09 returns 0a
spd_read_byte dev 51 returns 0xff
 * AUTOSIZE DIMM 0
 * Check present
spd_read_byte dev 50 addr 02 returns 07
 * MODBANKS
spd_read_byte dev 50 addr 05 returns 01
 * FIELDBANKS
spd_read_byte dev 50 addr 11 returns 04
 * SPDNUMROWS
spd_read_byte dev 50 addr 03 returns 03
spd_read_byte dev 50 addr 04 returns 0a
 * SPDBANKDENSITY
spd_read_byte dev 50 addr 1f returns 40
 * DIMMSIZE
 * BEFORT CTZ
 * TEST DIMM SIZE>8
 * PAGESIZE
spd_read_byte dev 50 addr 04 returns 0a
 * MAXCOLADDR
 * >12address test
 * RDMSR CF07
 * WRMSR CF07
 * ALL DONE
 * AUTOSIZE DIMM 1
 * Check present
spd_read_byte dev 51 returns 0xff
 * set cas latency
spd_read_byte dev 50 addr 12 returns 10
spd_read_byte dev 50 addr 17 returns 3c
spd_read_byte dev 50 addr 19 returns 4b
spd_read_byte dev 51 returns 0xff
 * set all latency
spd_read_byte dev 50 addr 1e returns 28
spd_read_byte dev 51 returns 0xff
spd_read_byte dev 50 addr 1b returns 0f
spd_read_byte dev 51 returns 0xff
spd_read_byte dev 50 addr 1d returns 0f
spd_read_byte dev 51 returns 0xff
spd_read_byte dev 50 addr 1c returns 0a
spd_read_byte dev 51 returns 0xff
spd_read_byte dev 50 addr 2a returns 46
spd_read_byte dev 51 returns 0xff
 * set emrs
spd_read_byte dev 50 addr 16 returns ff
spd_read_byte dev 51 returns 0xff
 * set ref rate
spd_read_byte dev 50 addr 0c returns 3a
spd_read_byte dev 51 returns 0xff
Ram3
 * DRAM controller init done.

RAM DLL lock
Ram4
POST 02
Past wbinvd
Loading image.
Searching for fallback/coreboot_ram
Check fallback/romstage
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 booting...
clocks_per_usec: 499
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:0f.0: enabled 1
PCI: 00:0f.1: enabled 1
PCI: 00:0f.2: enabled 1
PCI: 00:0f.4: enabled 1
PCI: 00:0f.5: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
Compare with tree...
Root Device: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:01.1: enabled 1
  PCI: 00:0f.0: enabled 1
  PCI: 00:0f.1: enabled 1
  PCI: 00:0f.2: enabled 1
  PCI: 00:0f.4: enabled 1
  PCI: 00:0f.5: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
scan_static_bus for Root Device
>> Entering northbridge.c: enable_dev with path 6
>> Entering northbridge.c: pci_domain_enable
Enter northbridge_init_early
writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80
writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0
sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
sizeram: sizem 0x100MB
SysmemInit: enable for 256MBytes
usable RAM: 268304383 bytes
SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100
sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
sizeram: sizem 0x100MB
SMMGL0Init: 268304384 bytes
SMMGL0Init: offset is 0x80400000
SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0
writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003
writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80
writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0
sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
sizeram: sizem 0x100MB
SysmemInit: enable for 256MBytes
usable RAM: 268304383 bytes
SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100
SMMGL1Init:
SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0
writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001
writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0
CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00
CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000
L2 cache enabled
Enabling cache
GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000
GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000
Exit northbridge_init_early
Done cpubug fixes
Not Doing ChipsetFlashSetup()
Preparing for VSA...
VSA: Real mode stub @00000600: 862 bytes
Searching for vsa
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'vsa'.
Failed to load VSA.
Graphics init...
VRC_VG value: 0xffff
Finding PCI configuration type.
PCI: Sanity check failed
pci_check_direct failed



[hang]

What am I missing?  There doesn't seem to be a default VSA payload for the out-of-the-box default SeaBIOS build, which seems curious...

I burned BIOS by doing the following:

* boot the box up in linux
* scp'd the coreboot.rom file over from my build box
* flashrom -w coreboot.rom

Those were hopefully the correct steps.

-Philip


From bh at udev.org  Thu Dec 29 12:30:04 2011
From: bh at udev.org (Benjamin Henrion)
Date: Thu, 29 Dec 2011 12:30:04 +0100
Subject: [coreboot] Bricked 6F2
In-Reply-To: <4EFBCECE.40805@redfish-solutions.com>
References: <4EFBCECE.40805@redfish-solutions.com>
Message-ID: <CANjd3ndVNLsH7=SxaxkOH6PggGrU9rm78X+rYhDOfid2GZVyvA@mail.gmail.com>

On Thu, Dec 29, 2011 at 3:22 AM, Philip Prindeville
<philipp_subx at redfish-solutions.com> wrote:
> Ok, I build coreboot's trunk and selected the target Alix2D, but managed to brick the device:
>
> coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting...
> MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:0000182e
> Configuring PLL.
>
>
> coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting...
> MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:07de002e
> PLL configured.
> Castle 2.0 BTM periodic sync period.
> Enable Quack for fewer re-RAS on the MC
> ?GLIU port active enable
> Set the Delay Control in GLCP
> spd_read_byte dev 50 addr 0d returns 08
> spd_read_byte dev 50 addr 05 returns 01
> spd_read_byte dev 51 returns 0xff
> Enable RSDC
> FPU imprecise exceptions bit
> Enable Suspend on HLT & PAUSE instructions
> Enable SUSP and allow TSC to run in Suspend
> Setup throttling delays to proper mode
> Done cpuRegInit
> Ram1.00
> Ram2.00
> ?* sdram_set_spd_register
> spd_read_byte dev 50 addr 15 returns ff
> ?* Check DIMM 0
> ?* Check DIMM 1
> spd_read_byte dev 51 returns 0xff
> ?* Check DDR MAX
> spd_read_byte dev 50 addr 09 returns 0a
> spd_read_byte dev 51 returns 0xff
> ?* AUTOSIZE DIMM 0
> ?* Check present
> spd_read_byte dev 50 addr 02 returns 07
> ?* MODBANKS
> spd_read_byte dev 50 addr 05 returns 01
> ?* FIELDBANKS
> spd_read_byte dev 50 addr 11 returns 04
> ?* SPDNUMROWS
> spd_read_byte dev 50 addr 03 returns 03
> spd_read_byte dev 50 addr 04 returns 0a
> ?* SPDBANKDENSITY
> spd_read_byte dev 50 addr 1f returns 40
> ?* DIMMSIZE
> ?* BEFORT CTZ
> ?* TEST DIMM SIZE>8
> ?* PAGESIZE
> spd_read_byte dev 50 addr 04 returns 0a
> ?* MAXCOLADDR
> ?* >12address test
> ?* RDMSR CF07
> ?* WRMSR CF07
> ?* ALL DONE
> ?* AUTOSIZE DIMM 1
> ?* Check present
> spd_read_byte dev 51 returns 0xff
> ?* set cas latency
> spd_read_byte dev 50 addr 12 returns 10
> spd_read_byte dev 50 addr 17 returns 3c
> spd_read_byte dev 50 addr 19 returns 4b
> spd_read_byte dev 51 returns 0xff
> ?* set all latency
> spd_read_byte dev 50 addr 1e returns 28
> spd_read_byte dev 51 returns 0xff
> spd_read_byte dev 50 addr 1b returns 0f
> spd_read_byte dev 51 returns 0xff
> spd_read_byte dev 50 addr 1d returns 0f
> spd_read_byte dev 51 returns 0xff
> spd_read_byte dev 50 addr 1c returns 0a
> spd_read_byte dev 51 returns 0xff
> spd_read_byte dev 50 addr 2a returns 46
> spd_read_byte dev 51 returns 0xff
> ?* set emrs
> spd_read_byte dev 50 addr 16 returns ff
> spd_read_byte dev 51 returns 0xff
> ?* set ref rate
> spd_read_byte dev 50 addr 0c returns 3a
> spd_read_byte dev 51 returns 0xff
> Ram3
> ?* DRAM controller init done.
>
> RAM DLL lock
> Ram4
> POST 02
> Past wbinvd
> Loading image.
> Searching for fallback/coreboot_ram
> Check fallback/romstage
> Check fallback/coreboot_ram
> Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000
> Stage: done loading.
> Jumping to image.
> coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 booting...
> clocks_per_usec: 499
> Enumerating buses...
> Show all devs...Before device enumeration.
> Root Device: enabled 1
> PCI_DOMAIN: 0000: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:01.1: enabled 1
> PCI: 00:0f.0: enabled 1
> PCI: 00:0f.1: enabled 1
> PCI: 00:0f.2: enabled 1
> PCI: 00:0f.4: enabled 1
> PCI: 00:0f.5: enabled 1
> APIC_CLUSTER: 0: enabled 1
> APIC: 00: enabled 1
> Compare with tree...
> Root Device: enabled 1
> ?PCI_DOMAIN: 0000: enabled 1
> ?PCI: 00:01.0: enabled 1
> ?PCI: 00:01.1: enabled 1
> ?PCI: 00:0f.0: enabled 1
> ?PCI: 00:0f.1: enabled 1
> ?PCI: 00:0f.2: enabled 1
> ?PCI: 00:0f.4: enabled 1
> ?PCI: 00:0f.5: enabled 1
> ?APIC_CLUSTER: 0: enabled 1
> ?APIC: 00: enabled 1
> scan_static_bus for Root Device
>>> Entering northbridge.c: enable_dev with path 6
>>> Entering northbridge.c: pci_domain_enable
> Enter northbridge_init_early
> writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80
> writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0
> sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
> sizeram: sizem 0x100MB
> SysmemInit: enable for 256MBytes
> usable RAM: 268304383 bytes
> SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100
> sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
> sizeram: sizem 0x100MB
> SMMGL0Init: 268304384 bytes
> SMMGL0Init: offset is 0x80400000
> SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0
> writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003
> writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80
> writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0
> sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
> sizeram: sizem 0x100MB
> SysmemInit: enable for 256MBytes
> usable RAM: 268304383 bytes
> SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100
> SMMGL1Init:
> SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0
> writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001
> writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0
> CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00
> CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000
> L2 cache enabled
> Enabling cache
> GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000
> GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000
> Exit northbridge_init_early
> Done cpubug fixes
> Not Doing ChipsetFlashSetup()
> Preparing for VSA...
> VSA: Real mode stub @00000600: 862 bytes
> Searching for vsa
> Check fallback/romstage
> Check fallback/coreboot_ram
> Check fallback/payload
> Check config
> Check
> ERROR: No file header found at fffffd40, attempting to recover by searching for header
> Could not find file 'vsa'.
> Failed to load VSA.
> Graphics init...
> VRC_VG value: 0xffff
> Finding PCI configuration type.
> PCI: Sanity check failed
> pci_check_direct failed
>
>
>
> [hang]
>
> What am I missing? ?There doesn't seem to be a default VSA payload for the out-of-the-box default SeaBIOS build, which seems curious...
>
> I burned BIOS by doing the following:
>
> * boot the box up in linux
> * scp'd the coreboot.rom file over from my build box
> * flashrom -w coreboot.rom
>
> Those were hopefully the correct steps.

You need to add the seabios thing in the .rom file.

It seems you have hit the same problem as I had:

http://www.zoobab.com/alix-1c#toc4

I have the plan to recover it with an LPC+arduinomega that I bought
recently, but have to find the time.

--
Benjamin Henrion <bhenrion at ffii.org>
FFII Brussels - +32-484-566109 - +32-2-4148403
"In July 2005, after several failed attempts to legalise software
patents in Europe, the patent establishment changed its strategy.
Instead of explicitly seeking to sanction the patentability of
software, they are now seeking to create a central European patent
court, which would establish and enforce patentability rules in their
favor, without any possibility of correction by competing courts or
democratically elected legislators."


From philipp_subx at redfish-solutions.com  Thu Dec 29 19:03:09 2011
From: philipp_subx at redfish-solutions.com (Philip Prindeville)
Date: Thu, 29 Dec 2011 11:03:09 -0700
Subject: [coreboot] Bricked 6F2
In-Reply-To: <CANjd3ndVNLsH7=SxaxkOH6PggGrU9rm78X+rYhDOfid2GZVyvA@mail.gmail.com>
References: <4EFBCECE.40805@redfish-solutions.com>
	<CANjd3ndVNLsH7=SxaxkOH6PggGrU9rm78X+rYhDOfid2GZVyvA@mail.gmail.com>
Message-ID: <4EFCAB5D.60609@redfish-solutions.com>

On 12/29/11 4:30 AM, Benjamin Henrion wrote:
> On Thu, Dec 29, 2011 at 3:22 AM, Philip Prindeville
> <philipp_subx at redfish-solutions.com> wrote:
>> Ok, I build coreboot's trunk and selected the target Alix2D, but managed to brick the device:
>>
>> coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting...
>> MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:0000182e
>> Configuring PLL.
>>
>>
>> coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting...
>> MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:07de002e
>> PLL configured.
>> Castle 2.0 BTM periodic sync period.
>> Enable Quack for fewer re-RAS on the MC
>>  GLIU port active enable
>> Set the Delay Control in GLCP
>> spd_read_byte dev 50 addr 0d returns 08
>> spd_read_byte dev 50 addr 05 returns 01
>> spd_read_byte dev 51 returns 0xff
>> Enable RSDC
>> FPU imprecise exceptions bit
>> Enable Suspend on HLT & PAUSE instructions
>> Enable SUSP and allow TSC to run in Suspend
>> Setup throttling delays to proper mode
>> Done cpuRegInit
>> Ram1.00
>> Ram2.00
>>  * sdram_set_spd_register
>> spd_read_byte dev 50 addr 15 returns ff
>>  * Check DIMM 0
>>  * Check DIMM 1
>> spd_read_byte dev 51 returns 0xff
>>  * Check DDR MAX
>> spd_read_byte dev 50 addr 09 returns 0a
>> spd_read_byte dev 51 returns 0xff
>>  * AUTOSIZE DIMM 0
>>  * Check present
>> spd_read_byte dev 50 addr 02 returns 07
>>  * MODBANKS
>> spd_read_byte dev 50 addr 05 returns 01
>>  * FIELDBANKS
>> spd_read_byte dev 50 addr 11 returns 04
>>  * SPDNUMROWS
>> spd_read_byte dev 50 addr 03 returns 03
>> spd_read_byte dev 50 addr 04 returns 0a
>>  * SPDBANKDENSITY
>> spd_read_byte dev 50 addr 1f returns 40
>>  * DIMMSIZE
>>  * BEFORT CTZ
>>  * TEST DIMM SIZE>8
>>  * PAGESIZE
>> spd_read_byte dev 50 addr 04 returns 0a
>>  * MAXCOLADDR
>>  * >12address test
>>  * RDMSR CF07
>>  * WRMSR CF07
>>  * ALL DONE
>>  * AUTOSIZE DIMM 1
>>  * Check present
>> spd_read_byte dev 51 returns 0xff
>>  * set cas latency
>> spd_read_byte dev 50 addr 12 returns 10
>> spd_read_byte dev 50 addr 17 returns 3c
>> spd_read_byte dev 50 addr 19 returns 4b
>> spd_read_byte dev 51 returns 0xff
>>  * set all latency
>> spd_read_byte dev 50 addr 1e returns 28
>> spd_read_byte dev 51 returns 0xff
>> spd_read_byte dev 50 addr 1b returns 0f
>> spd_read_byte dev 51 returns 0xff
>> spd_read_byte dev 50 addr 1d returns 0f
>> spd_read_byte dev 51 returns 0xff
>> spd_read_byte dev 50 addr 1c returns 0a
>> spd_read_byte dev 51 returns 0xff
>> spd_read_byte dev 50 addr 2a returns 46
>> spd_read_byte dev 51 returns 0xff
>>  * set emrs
>> spd_read_byte dev 50 addr 16 returns ff
>> spd_read_byte dev 51 returns 0xff
>>  * set ref rate
>> spd_read_byte dev 50 addr 0c returns 3a
>> spd_read_byte dev 51 returns 0xff
>> Ram3
>>  * DRAM controller init done.
>>
>> RAM DLL lock
>> Ram4
>> POST 02
>> Past wbinvd
>> Loading image.
>> Searching for fallback/coreboot_ram
>> Check fallback/romstage
>> Check fallback/coreboot_ram
>> Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000
>> Stage: done loading.
>> Jumping to image.
>> coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 booting...
>> clocks_per_usec: 499
>> Enumerating buses...
>> Show all devs...Before device enumeration.
>> Root Device: enabled 1
>> PCI_DOMAIN: 0000: enabled 1
>> PCI: 00:01.0: enabled 1
>> PCI: 00:01.1: enabled 1
>> PCI: 00:0f.0: enabled 1
>> PCI: 00:0f.1: enabled 1
>> PCI: 00:0f.2: enabled 1
>> PCI: 00:0f.4: enabled 1
>> PCI: 00:0f.5: enabled 1
>> APIC_CLUSTER: 0: enabled 1
>> APIC: 00: enabled 1
>> Compare with tree...
>> Root Device: enabled 1
>>  PCI_DOMAIN: 0000: enabled 1
>>  PCI: 00:01.0: enabled 1
>>  PCI: 00:01.1: enabled 1
>>  PCI: 00:0f.0: enabled 1
>>  PCI: 00:0f.1: enabled 1
>>  PCI: 00:0f.2: enabled 1
>>  PCI: 00:0f.4: enabled 1
>>  PCI: 00:0f.5: enabled 1
>>  APIC_CLUSTER: 0: enabled 1
>>  APIC: 00: enabled 1
>> scan_static_bus for Root Device
>>>> Entering northbridge.c: enable_dev with path 6
>>>> Entering northbridge.c: pci_domain_enable
>> Enter northbridge_init_early
>> writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80
>> writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0
>> sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
>> sizeram: sizem 0x100MB
>> SysmemInit: enable for 256MBytes
>> usable RAM: 268304383 bytes
>> SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100
>> sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
>> sizeram: sizem 0x100MB
>> SMMGL0Init: 268304384 bytes
>> SMMGL0Init: offset is 0x80400000
>> SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0
>> writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003
>> writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80
>> writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0
>> sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
>> sizeram: sizem 0x100MB
>> SysmemInit: enable for 256MBytes
>> usable RAM: 268304383 bytes
>> SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100
>> SMMGL1Init:
>> SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0
>> writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001
>> writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0
>> CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00
>> CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000
>> L2 cache enabled
>> Enabling cache
>> GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000
>> GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000
>> Exit northbridge_init_early
>> Done cpubug fixes
>> Not Doing ChipsetFlashSetup()
>> Preparing for VSA...
>> VSA: Real mode stub @00000600: 862 bytes
>> Searching for vsa
>> Check fallback/romstage
>> Check fallback/coreboot_ram
>> Check fallback/payload
>> Check config
>> Check
>> ERROR: No file header found at fffffd40, attempting to recover by searching for header
>> Could not find file 'vsa'.
>> Failed to load VSA.
>> Graphics init...
>> VRC_VG value: 0xffff
>> Finding PCI configuration type.
>> PCI: Sanity check failed
>> pci_check_direct failed
>>
>>
>>
>> [hang]
>>
>> What am I missing?  There doesn't seem to be a default VSA payload for the out-of-the-box default SeaBIOS build, which seems curious...
>>
>> I burned BIOS by doing the following:
>>
>> * boot the box up in linux
>> * scp'd the coreboot.rom file over from my build box
>> * flashrom -w coreboot.rom
>>
>> Those were hopefully the correct steps.
> 
> You need to add the seabios thing in the .rom file.
> 
> It seems you have hit the same problem as I had:
> 
> http://www.zoobab.com/alix-1c#toc4
> 
> I have the plan to recover it with an LPC+arduinomega that I bought
> recently, but have to find the time.

What's the difference between that VSA file and the amd_vsa_lx.bin that's in:

svn://coreboot.org/vsa/trunk/gplvsa2

-Philip


From invertedrat at gmail.com  Fri Dec 23 03:24:44 2011
From: invertedrat at gmail.com (jacob scott)
Date: Thu, 22 Dec 2011 18:24:44 -0800
Subject: [coreboot] Will coreboot work on my machine?
Message-ID: <CABDPA_gx=vaOjG_W0oc5gdMgPYq5LVF+AkT9Zu=51YbsLvd0RQ@mail.gmail.com>

As I understand, this is where to send my motherboard specs, my apologies
if it isn't.

ASUS M4A88T-V EVO/USB3
AMD 880G/SB710
AMD Athlon II x4 640

More specs:
http://usa.asus.com/Motherboards/AMD_AM3/M4A88TV_EVOUSB3/#specifications

*lspci -tvnn *output:

~$ lspci -tvnn
-[0000:00]-+-00.0  Advanced Micro Devices [AMD] RS880 Host Bridge
[1022:9601]
           +-02.0-[01]--+-00.0  ATI Technologies Inc Redwood [Radeon HD
5670] [1002:68d8]
           |            \-00.1  ATI Technologies Inc Redwood HDMI Audio
[Radeon HD 5600 Series] [1002:aa60]
           +-09.0-[02]----00.0  Realtek Semiconductor Co., Ltd.
RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168]
           +-0a.0-[03]----00.0  NEC Corporation uPD720200 USB 3.0 Host
Controller [1033:0194]
           +-11.0  ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA Controller
[IDE mode] [1002:4390]
           +-12.0  ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0
Controller [1002:4397]
           +-12.1  ATI Technologies Inc SB7x0 USB OHCI1 Controller
[1002:4398]
           +-12.2  ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI
Controller [1002:4396]
           +-13.0  ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0
Controller [1002:4397]
           +-13.1  ATI Technologies Inc SB7x0 USB OHCI1 Controller
[1002:4398]
           +-13.2  ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI
Controller [1002:4396]
           +-14.0  ATI Technologies Inc SBx00 SMBus Controller [1002:4385]
           +-14.1  ATI Technologies Inc SB7x0/SB8x0/SB9x0 IDE Controller
[1002:439c]
           +-14.2  ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383]
           +-14.3  ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host
controller [1002:439d]
           +-14.4-[04]--+-05.0  Ralink corp. RT2760 Wireless 802.11n 1T/2R
Cardbus [1814:0701]
           |            \-08.0  VIA Technologies, Inc. VT6306/7/8 [Fire
II(M)] IEEE 1394 OHCI Controller [1106:3044]
           +-14.5  ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI2
Controller [1002:4399]
           +-18.0  Advanced Micro Devices [AMD] Family 10h Processor
HyperTransport Configuration [1022:1200]
           +-18.1  Advanced Micro Devices [AMD] Family 10h Processor
Address Map [1022:1201]
           +-18.2  Advanced Micro Devices [AMD] Family 10h Processor DRAM
Controller [1022:1202]
           +-18.3  Advanced Micro Devices [AMD] Family 10h Processor
Miscellaneous Control [1022:1203]
           \-18.4  Advanced Micro Devices [AMD] Family 10h Processor Link
Control [1022:1204]
~$

*superistool -dV *output:
~# superiotool -dV
superiotool r6637
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x2e...
Found ITE IT8721F (id=0x8721, rev=0x3) at 0x2e
No dump available for this Super I/O
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x164e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for Nuvoton Super I/O at 0x164e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x2e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x4e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for VIA Super I/O at 0x3f0...
  PCI device 1106:0686 not found.
Probing for Server Engines Super I/O at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xff
~#

*flashrom -V *output:
~# flashrom -V
flashrom v0.9.4-r1394 on Linux 3.0.0-14-generic (x86_64), built with libpci
3.1.7, GCC 4.6.1, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 1 usecs, 1907M loops per
second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 997 us, 10000 myus =
9984 us, 4 myus = 14 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "System manufacturer"
DMI string system-product-name: "System Product Name"
DMI string system-version: "System Version"
DMI string baseboard-manufacturer: "ASUSTeK Computer INC."
DMI string baseboard-product-name: "M4A88T-V EVO/USB3"
DMI string baseboard-version: "Rev X.0x"
DMI string chassis-type: "Desktop"
Found ITE Super I/O, ID 0x8721 on port 0x2e
Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d. Enabling
flash write... SPI base address is at 0xfec10000
AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0
PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1
SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4,
SpiBridgeDisable=1, DropOneClkOnRd=0
NormSpeed is 33 MHz
GPIO11 used for SPI_DO
GPIO12 used for SPI_DI
GPIO31 used for SPI_HOLD
GPIO32 used for SPI_CS
GPIO47 used for SPI_CLK
SB700 IMC is not active.
ROM strap override is not active
OK.
This chipset supports the following protocols: LPC, FWH, SPI.
Super I/O ID 0x8721 is not on the list of flash capable controllers.
Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x03, id2 0x99,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115
Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115
Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Chip status register is 00
Found Eon flash chip "EN25F16" (2048 kB, SPI) at physical address
0xffe00000.
Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x03, id2 0x99, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1
0x1c, id2 0x3115
Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xd8, id2 0xb1,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x03, id2 0x99,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0x1c, id2 0x14
Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0x1c, id2 0x14
Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x14, id2 0x14
Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0x1c, id2 0x14
Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xd8, id2
0xb1, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x74, id2
0xd9, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x03, id2
0x99, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x03, id2 0x99, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xd8, id2 0xb1,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xd8, id2
0xb1, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x03, id2 0x99,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x03, id2
0x99, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115
Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID.
Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID.
Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115
Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115
Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID.
Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115
Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115
Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115
Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115
Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x03, id2 0x99, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x03, id2 0x99, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xd8, id2 0xb1, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x03, id2 0x99, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2
0x3115
Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x03, id2
0x99, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x03, id2
0x99, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x03, id2
0x99, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x03, id2
0x99, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x03, id2
0x99, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x03, id2
0x99, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xd8, id2
0xb1, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xd8, id2
0xb1, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1
0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1
0x1c, id2 0x3115
Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1
0x1c, id2 0x3115
Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1
0x1c, id2 0x3115
Probing for Macronix unknown Macronix SPI chip, 0 kB:
probe_spi_rdid_generic: id1 0x1c, id2 0x3115
Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1
0x1c, id2 0x3115
Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1
0x1c, id2 0x3115
Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c,
id2 0x3115
Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1
0x1c, id2 0x3115
Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic:
id1 0x1c, id2 0x3115
Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1
0x1c, id2 0x14
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
The test status of this chip may have been updated in the latest development
version of flashrom. If you are running the latest development version,
please email a report to flashrom at flashrom.org if any of the above
operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -Vr,
-Vw, -VE), and mention which mainboard or programmer you tested.
Please mention your board in the subject line. Thanks for your help!
No operations were specified.
~#
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From gerrit at coreboot.org  Thu Dec 29 20:23:13 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Thu, 29 Dec 2011 20:23:13 +0100
Subject: [coreboot] New patch to review for coreboot: 5fd4844 Set default
	baudrate on Alix2d to be compatible with factory default
References: <Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0+0@gerrit.coreboot.org>
Message-ID: <Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/508

-gerrit

commit 5fd4844dce2b414565ad512cbaa930159d00cd5d
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Wed Dec 28 16:32:44 2011 -0700

    Set default baudrate on Alix2d to be compatible with factory default
    
    Boards shipping from PC Engines with the factory BIOS (tinyBios 0.99)
    boot up at 38400. In keeping with the principle of least astonishment,
    boards reflashed with SeaBIOS should probably try to keep compatible
    with this setting.
    
    Change-Id: Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/pcengines/alix2d/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index 264f5d9..ea02adf 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
 	select POWER_BUTTON_FORCE_DISABLE
+	select CONSOLE_SERIAL_38400
 
 config MAINBOARD_DIR
 	string


From gerrit at coreboot.org  Thu Dec 29 20:23:14 2011
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Thu, 29 Dec 2011 20:23:14 +0100
Subject: [coreboot] New patch to review for coreboot: b95f3f3 Add rules to
	pull down and uncompress gpl_vsa_lx_102.bin
References: <I81528dddb47b0cfe4acd33456680f8d3211fabd7+0@gerrit.coreboot.org>
Message-ID: <I81528dddb47b0cfe4acd33456680f8d3211fabd7+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/509

-gerrit

commit b95f3f353cf61b21bc079566edc100a355757771
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Thu Dec 29 12:21:39 2011 -0700

    Add rules to pull down and uncompress gpl_vsa_lx_102.bin
    
    These steps are in the Wiki, but they should be automated.
    
    Change-Id: I81528dddb47b0cfe4acd33456680f8d3211fabd7
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/arch/x86/Makefile.inc |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7bba44e..a95fd62 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -396,3 +396,8 @@ filo:
 			CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \
 			CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE)
 
+gpl_vsa_lx_102.bin.gz:
+	@wget -q http://marcjonesconsulting.com/gplvsa/gpl_vsa_lx_102.bin.gz
+
+gpl_vsa_lx_102.bin: gpl_vsa_lx_102.bin.gz
+	@gunzip $^


From rminnich at gmail.com  Thu Dec 29 23:25:20 2011
From: rminnich at gmail.com (ron minnich)
Date: Thu, 29 Dec 2011 14:25:20 -0800
Subject: [coreboot] Bricked 6F2
In-Reply-To: <4EFCAB5D.60609@redfish-solutions.com>
References: <4EFBCECE.40805@redfish-solutions.com>
	<CANjd3ndVNLsH7=SxaxkOH6PggGrU9rm78X+rYhDOfid2GZVyvA@mail.gmail.com>
	<4EFCAB5D.60609@redfish-solutions.com>
Message-ID: <CAP6exYKuqe-ZDz1Y0XTKRQsL9w7S8Dp0NYq+NZuwgFA68+SBtQ@mail.gmail.com>

On Thu, Dec 29, 2011 at 10:03 AM, Philip Prindeville
<philipp_subx at redfish-solutions.com> wrote:

> What's the difference between that VSA file and the amd_vsa_lx.bin that's in:
>
> svn://coreboot.org/vsa/trunk/gplvsa2

probably not much. It's been years since I did geode work.

You need to add the vsa to the image by hand, at least you used to
have to on v2/v4.

Let me know if this is not enough info.

ron


From gerrit at coreboot.org  Fri Dec 30 14:29:54 2011
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Fri, 30 Dec 2011 14:29:54 +0100
Subject: [coreboot] New patch to review for coreboot: fde05ff build_opt_tbl:
	cosmetic changes
References: <I9cb8d2c311d2791f6da8a3e0a65806270bb53b41+0@gerrit.coreboot.org>
Message-ID: <I9cb8d2c311d2791f6da8a3e0a65806270bb53b41+1@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/510

-gerrit

commit fde05ff876063bb18d50f1d771990e17a31a3c7b
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Fri Dec 30 18:54:21 2011 +0530

    build_opt_tbl: cosmetic changes
    
    Replaced the switch-cases in is_ident_digit and is_ident_nondigit
    with if-else construct. Also made the functions inline.
    
    Change-Id: I9cb8d2c311d2791f6da8a3e0a65806270bb53b41
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 util/options/build_opt_tbl.c |   48 ++++++++---------------------------------
 1 files changed, 10 insertions(+), 38 deletions(-)

diff --git a/util/options/build_opt_tbl.c b/util/options/build_opt_tbl.c
index b89bb4f..515d6ea 100644
--- a/util/options/build_opt_tbl.c
+++ b/util/options/build_opt_tbl.c
@@ -174,48 +174,20 @@ static unsigned long get_number(char *line, char **ptr, int base)
 	return value;
 }
 
-static int is_ident_digit(int c)
+static inline int is_ident_digit(int c)
 {
-	int result;
-	switch(c) {
-	case '0':	case '1':	case '2':	case '3':
-	case '4':	case '5':	case '6':	case '7':
-	case '8':	case '9':
-		result = 1;
-		break;
-	default:
-		result = 0;
-		break;
-	}
-	return result;
+	if(c >= '0' && c <= '9')
+		return 1;
+	else
+		return 0;
 }
 
-static int is_ident_nondigit(int c)
+static inline int is_ident_nondigit(int c)
 {
-	int result;
-	switch(c) {
-	case 'A':	case 'B':	case 'C':	case 'D':
-	case 'E':	case 'F':	case 'G':	case 'H':
-	case 'I':	case 'J':	case 'K':	case 'L':
-	case 'M':	case 'N':	case 'O':	case 'P':
-	case 'Q':	case 'R':	case 'S':	case 'T':
-	case 'U':	case 'V':	case 'W':	case 'X':
-	case 'Y':	case 'Z':
-	case 'a':	case 'b':	case 'c':	case 'd':
-	case 'e':	case 'f':	case 'g':	case 'h':
-	case 'i':	case 'j':	case 'k':	case 'l':
-	case 'm':	case 'n':	case 'o':	case 'p':
-	case 'q':	case 'r':	case 's':	case 't':
-	case 'u':	case 'v':	case 'w':	case 'x':
-	case 'y':	case 'z':
-	case '_':
-		result = 1;
-		break;
-	default:
-		result = 0;
-		break;
-	}
-	return result;
+	if((c >= 'A' && c <= 'Z') || (c == '_') || (c >= 'a' && c <= 'z'))
+		return 1;
+	else
+		return 0;
 }
 
 static int is_ident(char *str)


From prakash at punnoor.de  Fri Dec 30 16:00:40 2011
From: prakash at punnoor.de (Prakash Punnoor)
Date: Fri, 30 Dec 2011 16:00:40 +0100
Subject: [coreboot] Trouble building coreboot/SeaBios
Message-ID: <2338194.f4GqbpMnWv@graviton>

Hi,

I am trying to build coreboot with SeaBios (for a new mainboard I am trying to 
port). Initially the build system complained about a broken LD, so I built 
make crossgcc -j1 (iasl compile fails in parallel mode, btw) and rm .xcompile 
as written in the wiki. Now make -j1 goes further and dies on building 
seabios:

Compilation complete. 0 Errors, 31 Warnings, 0 Remarks, 3 Optimizations
  Compiling whole program out/ccode32flat.o
  Compiling whole program out/code32seg.o
  Building ld scripts (version "pre-1.6.4-20111230_155214-graviton")
  File "./tools/layoutrom.py", line 75
    print "Error: Fixed section %s has non-zero alignment (%d)" % (

I tried stable and master but both give this error. Any idea?

Regards,

Prakash
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From vidwer at gmail.com  Fri Dec 30 16:46:15 2011
From: vidwer at gmail.com (Idwer Vollering)
Date: Fri, 30 Dec 2011 16:46:15 +0100
Subject: [coreboot] Trouble building coreboot/SeaBios
In-Reply-To: <2338194.f4GqbpMnWv@graviton>
References: <2338194.f4GqbpMnWv@graviton>
Message-ID: <CAPp9OrmjBMTsXjwGQ1AiF7CypqouwTBMkdFUF5owvPwb6i_KNQ@mail.gmail.com>

2011/12/30 Prakash Punnoor <prakash at punnoor.de>:
> Hi,
>
>
>
> I am trying to build coreboot with SeaBios (for a new mainboard I am trying
> to port). Initially the build system complained about a broken LD, so I
> built make crossgcc -j1 (iasl compile fails in parallel mode, btw)

 Oh? Wasn't that fixed..
http://review.coreboot.org/gitweb?p=coreboot.git&a=search&h=HEAD&st=commit&s=iasl

> and rm .xcompile as written in the wiki. Now make -j1 goes further and dies on
> building seabios:
>
>
>
> Compilation complete. 0 Errors, 31 Warnings, 0 Remarks, 3 Optimizations
>
> Compiling whole program out/ccode32flat.o
>
> Compiling whole program out/code32seg.o
>
> Building ld scripts (version "pre-1.6.4-20111230_155214-graviton")
>
> File "./tools/layoutrom.py", line 75
>
> print "Error: Fixed section %s has non-zero alignment (%d)" % (
>
>
>
> I tried stable and master but both give this error. Any idea?

Installing python 2.x will probably solve this.

>
>
>
> Regards,
>
>
>
> Prakash
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


From gerrit at coreboot.org  Fri Dec 30 22:57:59 2011
From: gerrit at coreboot.org (Nils Jacobs (njacobs8@adsltotaal.nl))
Date: Fri, 30 Dec 2011 22:57:59 +0100
Subject: [coreboot] New patch to review for coreboot: b0a31b4 White space
	and coding style fixes.
References: <I14f39b5666fc18e8183723ec78a40a849d337736+0@gerrit.coreboot.org>
Message-ID: <I14f39b5666fc18e8183723ec78a40a849d337736+1@gerrit.coreboot.org>

Nils Jacobs (njacobs8 at adsltotaal.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/511

-gerrit

commit b0a31b460822364e72bdf87c25e6b60946da120a
Author: Nils Jacobs <njacobs8 at adsltotaal.nl>
Date:   Fri Dec 30 22:30:27 2011 +0100

    White space and coding style fixes.
    
    Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736
    Signed-off-by: Nils Jacobs <njacobs8 at adsltotaal.nl>
---
 src/northbridge/amd/gx2/northbridgeinit.c |  161 ++++++++++++++---------------
 1 files changed, 80 insertions(+), 81 deletions(-)

diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index e4aaa8b..f52eaf2 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -23,29 +23,27 @@ struct gliutable
 };
 
 struct gliutable gliu0table[] = {
-	{.desc_name=GLIU0_P2D_BM_0,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=  0x0FFF80},			/* 0-7FFFF to MC */
-	{.desc_name=GLIU0_P2D_BM_1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},	/* 80000-9ffff to Mc */
-	{.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=  0x03},		/* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
-	{.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=GLIU0_P2D_BMO_1,    .desc_type= BMO_DMM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=GLIU0_P2D_BMO_0,    .desc_type= BMO_SMM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
-	{.desc_name=GL_END,           .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+	{.desc_name=GLIU0_P2D_BM_0,	.desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80},		/* 0-7FFFF to MC */
+	{.desc_name=GLIU0_P2D_BM_1,	.desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},	/* 80000-9ffff to Mc */
+	{.desc_name=GLIU0_P2D_SC_0,	.desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03},		/* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
+	{.desc_name=GLIU0_P2D_R_0,	.desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU0_P2D_BMO_0,	.desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU0_GLD_MSR_COH,	.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
+	{.desc_name=GL_END,		.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };
 
 struct gliutable gliu1table[] = {
-	{.desc_name=GLIU1_P2D_BM_0,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},		/* 0-7FFFF to MC */
-	{.desc_name=GLIU1_P2D_BM_1,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},	/* 80000-9ffff to Mc */
-	{.desc_name=GLIU1_P2D_SC_0,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03},		/* C0000-Fffff split to MC and PCI (sub decode) */
-	{.desc_name=GLIU1_P2D_R_0,.desc_type=  R_SYSMEM,.hi=  MSR_GL0,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=GLIU1_P2D_BM_4,.desc_type=  BM_DMM,.hi=  MSR_GL0,.lo=  0x0},				/* Catch and fix dynamicly. */
-	{.desc_name=GLIU1_P2D_BM_3,.desc_type=  BM_SMM,.hi=  MSR_GL0,.lo=  0x0},				/* Catch and fix dynamicly. */
-	{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
-	{.desc_name=GLIU1_IOD_SC_0,.desc_type=  SCIO,.hi=  (GL1_GLCP << 29) + 0x0,.lo=  0x033000F0}, /* FooGlue FPU 0xF0 */
-	{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+	{.desc_name=GLIU1_P2D_BM_0,	.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80},		/* 0-7FFFF to MC */
+	{.desc_name=GLIU1_P2D_BM_1,	.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
+	{.desc_name=GLIU1_P2D_SC_0,	.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03},		/* C0000-Fffff split to MC and PCI (sub decode) */
+	{.desc_name=GLIU1_P2D_R_0,	.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU1_P2D_BM_3,	.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU1_GLD_MSR_COH,	.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
+	{.desc_name=GLIU1_IOD_SC_0,	.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0},	/* FooGlue FPU 0xF0 */
+	{.desc_name=GL_END,		.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };
 
-struct gliutable *gliutables[]  = {gliu0table, gliu1table, 0};
+struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
 
 struct msrinit
 {
@@ -53,7 +51,7 @@ struct msrinit
 	msr_t msr;
 };
 
-struct msrinit ClockGatingDefault [] = {
+struct msrinit ClockGatingDefault[] = {
 	{GLIU0_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
 	/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */
 	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},
@@ -91,7 +89,7 @@ struct msrinit ClockGatingPerformance[] = {
 };
 
 /* SET GeodeLink PRIORITY */
-struct msrinit GeodeLinkPriorityTable [] = {
+struct msrinit GeodeLinkPriorityTable[] = {
 	{CPU_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0220}},		/* CPU Priority. */
 	{DF_GLD_MSR_MASTER_CONF,	{.hi=0x00,.lo=0x0000}},		/* DF Priority. */
 	{VG_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0720}},		/* VG Primary and Secondary Priority. */
@@ -145,7 +143,7 @@ static void SysmemInit(struct gliutable *gl)
 	printk(BIOS_DEBUG, "%s: enable for %dm bytes\n", __func__, sizembytes);
 	sizebytes = sizembytes << 20;
 
-	sizebytes -= SMM_SIZE*1024 +1;
+	sizebytes -= SMM_SIZE * 1024 + 1;
 
 	if (havedmi)
 		sizebytes -= DMM_SIZE * 1024 + 1;
@@ -216,10 +214,10 @@ static void DMMGL1Init(struct gliutable *gl)
 static void SMMGL0Init(struct gliutable *gl)
 {
 	msr_t msr;
-	int sizebytes = sizeram()<<20;
+	int sizebytes = sizeram() << 20;
 	long offset;
 
-	sizebytes -= SMM_SIZE*1024;
+	sizebytes -= SMM_SIZE * 1024;
 
 	if (havedmi)
 		sizebytes -= DMM_SIZE * 1024;
@@ -231,10 +229,10 @@ static void SMMGL0Init(struct gliutable *gl)
 	offset >>= 12;
 
 	msr.hi = offset << 8;
-	msr.hi |= SMM_OFFSET>>24;
+	msr.hi |= SMM_OFFSET >> 24;
 
 	msr.lo = SMM_OFFSET << 8;
-	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
+	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
 	msr = rdmsr(gl->desc_name);
@@ -251,7 +249,7 @@ static void SMMGL1Init(struct gliutable *gl)
 	msr.hi &= 0xffffff00;
 	msr.hi |= (SMM_OFFSET >> 24);
 	msr.lo = SMM_OFFSET << 8;
-	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
+	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
 	msr = rdmsr(gl->desc_name);
@@ -260,8 +258,8 @@ static void SMMGL1Init(struct gliutable *gl)
 
 static void GLIUInit(struct gliutable *gl)
 {
-	while (gl->desc_type != GL_END){
-		switch(gl->desc_type){
+	while (gl->desc_type != GL_END) {
+		switch (gl->desc_type) {
 		default:
 			/* For Unknown types: Write then read MSR */
 			writeglmsr(gl);
@@ -277,15 +275,15 @@ static void GLIUInit(struct gliutable *gl)
 			DMMGL0Init(gl);
 			break;
 
-		case BM_DMM	: /* check for a DMM entry */
+		case BM_DMM: /* check for a DMM entry */
 			DMMGL1Init(gl);
 			break;
 
-		case BMO_SMM	: /* check for a SMM entry */
+		case BMO_SMM: /* check for a SMM entry */
 			SMMGL0Init(gl);
 			break;
 
-		case BM_SMM	: /* check for a SMM entry */
+		case BM_SMM: /* check for a SMM entry */
 			SMMGL1Init(gl);
 			break;
 		}
@@ -311,13 +309,13 @@ static void GLPCIInit(void)
 	/* R0 - GLPCI settings for Conventional Memory space. */
 	msr.hi =  (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;	/* 640 */
 	msr.lo =  0;						/* 0 */
-	msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
+	msr.lo |= GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
 	msrnum = GLPCI_RC0;
 	wrmsr(msrnum, msr);
 
 	/* R1 - GLPCI settings for SysMem space. */
 	/* Get systop from GLIU0 SYSTOP Descriptor */
-	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
+	for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
 		if (gliu0table[i].desc_type == R_SYSMEM) {
 			gl = &gliu0table[i];
 			break;
@@ -328,8 +326,8 @@ static void GLPCIInit(void)
 		msrnum = gl->desc_name;
 		msr = rdmsr(msrnum);
 		/* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00
-                 * translates to a base of 0x00100000 and top of 0xffbf0000
-                 * base of 1M and top of around 256M
+		 * translates to a base of 0x00100000 and top of 0xffbf0000
+		 * base of 1M and top of around 256M
 		 */
 		/* we have to create a page-aligned (4KB page) address for base and top
 		 * so we need a high page aligned addresss (pah) and low page aligned address (pal)
@@ -341,8 +339,8 @@ static void GLPCIInit(void)
 		pah <<= 12;
 
 		pal = msr.lo << 12;
-		msr.hi =  pah;
-		msr.lo =  pal;
+		msr.hi = pah;
+		msr.lo = pal;
 		msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
 		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
@@ -350,16 +348,16 @@ static void GLPCIInit(void)
 	}
 
 	/* R2 - GLPCI settings for SMM space. */
-	msr.hi =  ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
-	msr.lo =  (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
+	msr.hi = ((SMM_OFFSET + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
+	msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
 	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
 	msrnum = GLPCI_RC2;
 	wrmsr(msrnum, msr);
 
 	/* this is done elsewhere already, but it does no harm to do it more than once */
-	/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */
-	msr.lo =  0x021212121;		/* cache disabled and write serialized */
-	msr.hi =  0x021212121;		/* cache disabled and write serialized */
+	/* write serialize memory hole to PCI. Need to unWS when something is shadowed regardless of cachablility. */
+	msr.lo = 0x021212121;	/* cache disabled and write serialized */
+	msr.hi = 0x021212121;	/* cache disabled and write serialized */
 
 	msrnum = CPU_RCONF_A0_BF;
 	wrmsr(msrnum, msr);
@@ -372,24 +370,24 @@ static void GLPCIInit(void)
 
 	/* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */
 	msrnum = GLPCI_A0_BF;
-	msr.hi =  0x35353535;
-	msr.lo =  0x35353535;
+	msr.hi = 0x35353535;
+	msr.lo = 0x35353535;
 	wrmsr(msrnum, msr);
 
 	msrnum = GLPCI_C0_DF;
-	msr.hi =  0x35353535;
-	msr.lo =  0x35353535;
+	msr.hi = 0x35353535;
+	msr.lo = 0x35353535;
 	wrmsr(msrnum, msr);
 
 	msrnum = GLPCI_E0_FF;
-	msr.hi =  0x35353535;
-	msr.lo =  0x35353535;
+	msr.hi = 0x35353535;
+	msr.lo = 0x35353535;
 	wrmsr(msrnum, msr);
 
 	/* Set WSREQ */
 	msrnum = CPU_DM_CONFIG0;
 	msr = rdmsr(msrnum);
-	msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
+	msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
 	msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT	;	/* reduce to 1 for safe mode. */
 	wrmsr(msrnum, msr);
 
@@ -398,54 +396,54 @@ static void GLPCIInit(void)
 	/* 5535 NB Init */
 	msrnum = GLPCI_ARB;
 	msr = rdmsr(msrnum);
-	msr.hi |=  GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
-	msr.lo |=  GLPCI_ARB_LOWER_IIE_SET;
+	msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
+	msr.lo |= GLPCI_ARB_LOWER_IIE_SET;
 	wrmsr(msrnum, msr);
 
 	msrnum = GLPCI_CTRL;
 	msr = rdmsr(msrnum);
 
-	msr.lo |=  GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; 	/* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
-	msr.lo |=  GLPCI_CTRL_LOWER_LDE_SET;
+	msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; 	/* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
+	msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
 
-	msr.lo &=  ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
-	msr.lo |=  0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
+	msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
+	msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
 
-	msr.lo &=  ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
-	msr.lo |=  0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
+	msr.lo &= ~(0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
+	msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
 
-	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
-	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
+	msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
+	msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
 
-	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
-	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
+	msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
+	msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
 
-	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
-	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
+	msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
+	msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
 
-	msr.hi &=  ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
-	msr.hi |=  0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
+	msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
+	msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
 
-	msr.hi &=  ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
-	msr.hi |=  0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
+	msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
+	msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
 	wrmsr(msrnum, msr);
 
 	/* Set GLPCI Latency Timer. */
 	msrnum = GLPCI_CTRL;
 	msr = rdmsr(msrnum);
-	msr.hi |=  0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; 	/* Change once 1.x is gone. */
+	msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; 	/* Change once 1.x is gone. */
 	wrmsr(msrnum, msr);
 
 	/* GLPCI_SPARE */
 	msrnum = GLPCI_SPARE;
 	msr = rdmsr(msrnum);
-	msr.lo &=  ~ 0x7;
-	msr.lo |=  GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
+	msr.lo &= ~0x7;
+	msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
 	wrmsr(msrnum, msr);
 }
 
 /* Enable Clock Gating. */
-static void ClockGatingInit (void)
+static void ClockGatingInit(void)
 {
 	msr_t msr;
 	struct msrinit *gating = ClockGatingDefault;
@@ -479,7 +477,7 @@ performance:
 		printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to  0x%08x:0x%08x\n", __func__,
 			gating->msrnum, msr.hi, msr.lo);
 		wrmsr(gating->msrnum, msr);	/* MSR - See the table above */
-		gating +=1;
+		gating += 1;
 	}
 }
 
@@ -489,7 +487,7 @@ static void GeodeLinkPriority(void)
 	struct msrinit *prio = GeodeLinkPriorityTable;
 	int i;
 
-	for(i = 0; prio->msrnum != 0xffffffff; i++) {
+	for (i = 0; prio->msrnum != 0xffffffff; i++) {
 		msr = rdmsr(prio->msrnum);
 		printk(BIOS_DEBUG, "%s: MSR 0x%08lx is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
 		msr.hi |= prio->msr.hi;
@@ -498,7 +496,7 @@ static void GeodeLinkPriority(void)
 		printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
 			prio->msrnum, msr.hi, msr.lo);
 		wrmsr(prio->msrnum, msr);	/* MSR - See the table above */
-		prio +=1;
+		prio += 1;
 	}
 }
 
@@ -510,6 +508,7 @@ static void GeodeLinkPriority(void)
 static uint64_t getShadow(void)
 {
 	msr_t msr;
+
 	msr = rdmsr(GLIU0_P2D_SC_0);
 	return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
 }
@@ -538,7 +537,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
 	}
 
 	/* load up C000 settings in eax. */
-	for ( ; bit; bit--) {
+	for (; bit; bit--) {
 		msr.lo <<= 8;
 		msr.lo |= 1;			/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
@@ -558,7 +557,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
 	}
 
 	/* load up E000 settings in eax. */
-	for ( ; bit; bit--) {
+	for (; bit; bit--) {
 		msr.lo <<= 8;
 		msr.lo |= 1;			/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
@@ -579,7 +578,7 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
 	/* Set the Enable Register. */
 	msr = rdmsr(GLPCI_REN);
 	msr.lo &= 0xFFFF00FF;
-	msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8);
+	msr.lo |= ((shadowLo & 0xFFFF0000) >> 8);
 	wrmsr(GLPCI_REN, msr);
 }
 
@@ -591,7 +590,7 @@ static void setShadow(uint64_t shadowSettings)
 {
 	int i;
 	msr_t msr;
-	struct gliutable* pTable;
+	struct gliutable *pTable;
 	uint32_t shadowLo, shadowHi;
 
 	shadowLo = (uint32_t) shadowSettings;
@@ -600,7 +599,7 @@ static void setShadow(uint64_t shadowSettings)
 	setShadowRCONF(shadowHi, shadowLo);
 	setShadowGLPCI(shadowHi, shadowLo);
 
-	for(i = 0; gliutables[i]; i++) {
+	for (i = 0; gliutables[i]; i++) {
 		for (pTable = gliutables[i]; pTable->desc_type != GL_END; pTable++) {
 			if (pTable->desc_type == SC_SHADOW) {
 
@@ -646,7 +645,7 @@ static void RCONFInit(void)
 	uint8_t SysMemCacheProp;
 
 	/* Locate SYSMEM entry in GLIU0table */
-	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
+	for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
 		if (gliu0table[i].desc_type == R_SYSMEM) {
 			gl = &gliu0table[i];
 			break;
@@ -724,7 +723,7 @@ void northbridge_init_early(void)
 	int i;
 	printk(BIOS_DEBUG, "Enter %s\n", __func__);
 
-	for(i = 0; gliutables[i]; i++)
+	for (i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
 
 	GeodeLinkPriority();


From gerrit at coreboot.org  Fri Dec 30 23:24:32 2011
From: gerrit at coreboot.org (Nils Jacobs (njacobs8@adsltotaal.nl))
Date: Fri, 30 Dec 2011 23:24:32 +0100
Subject: [coreboot] New patch to review for coreboot: a96e8b2 Update geode
	GX2 tree to match LX.
References: <I5b99c531e44ea09990b9da0b97213fb7945f34ee+0@gerrit.coreboot.org>
Message-ID: <I5b99c531e44ea09990b9da0b97213fb7945f34ee+1@gerrit.coreboot.org>

Nils Jacobs (njacobs8 at adsltotaal.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/512

-gerrit

commit a96e8b2fffb58aa393ad0455f29df8737e2adbcf
Author: Nils Jacobs <njacobs8 at adsltotaal.nl>
Date:   Fri Dec 30 23:00:11 2011 +0100

    Update geode GX2 tree to match LX.
    
    Change-Id: I5b99c531e44ea09990b9da0b97213fb7945f34ee
    Signed-off-by: Nils Jacobs <njacobs8 at adsltotaal.nl>
---
 src/mainboard/amd/rumba/devicetree.cb           |    1 -
 src/mainboard/lippert/frontrunner/devicetree.cb |    1 -
 src/mainboard/wyse/s50/devicetree.cb            |   36 ++--
 src/northbridge/amd/gx2/chip.h                  |   21 ++-
 src/northbridge/amd/gx2/northbridge.c           |   87 ---------
 src/northbridge/amd/gx2/northbridgeinit.c       |  236 ++++++++---------------
 6 files changed, 118 insertions(+), 264 deletions(-)

diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb
index fc49cbe..40490e1 100644
--- a/src/mainboard/amd/rumba/devicetree.cb
+++ b/src/mainboard/amd/rumba/devicetree.cb
@@ -1,5 +1,4 @@
 chip northbridge/amd/gx2
-  	#register "irqmap" = "0xaa5b"
 	device lapic_cluster 0 on
 		chip cpu/amd/model_gx2
 			device lapic 0 on end
diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb
index 9c18076..fa7c6e7 100644
--- a/src/mainboard/lippert/frontrunner/devicetree.cb
+++ b/src/mainboard/lippert/frontrunner/devicetree.cb
@@ -5,7 +5,6 @@ chip northbridge/amd/gx2
     end
   end
 
-  #register "irqmap" = "0xaa5b"
   device pci_domain 0 on
     device pci 0.0 on end
       chip southbridge/amd/cs5535
diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb
index 504a5de..e7cf0c2 100644
--- a/src/mainboard/wyse/s50/devicetree.cb
+++ b/src/mainboard/wyse/s50/devicetree.cb
@@ -20,18 +20,10 @@
 ##
 
 chip northbridge/amd/gx2
-	register "irqmap" = "0xaa5b"
-
-	device lapic_cluster 0 on
-		chip cpu/amd/model_gx2
-			device lapic 0 on end
-		end
-	end
-  	device pci_domain 0 on 
-		subsystemid 102d 0 inherit
-    		device pci 1.0 on end
-		device pci 1.1 on end
-      		chip southbridge/amd/cs5536
+	device pci_domain 0 on 
+		device pci 1.0 on end	# Geode GX2 Host Bridge
+		device pci 1.1 on end	# Geode GX2 Graphics Processor
+		chip southbridge/amd/cs5536
 			register "enable_gpio_int_route" = "0x0D0C0700"
 			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
 			register "enable_USBP4_device" = "0"	#0: host, 1:device
@@ -42,13 +34,19 @@ chip northbridge/amd/gx2
 			register "com2_enable" = "0"
 			register "com2_address" = "0x2F8"
 			register "com2_irq" = "3"
-        		device pci e.0 on end	# Realtek 8139 LAN
-        		device pci f.0 on end	# ISA Bridge
-        		device pci f.2 on end	# IDE Controller
-        		device pci f.3 on end 	# Audio
-        		device pci f.4 on end	# OHCI
+			device pci e.0 on end	# Realtek 8139 LAN
+			device pci f.0 on end	# ISA Bridge
+			device pci f.2 on end	# IDE Controller
+			device pci f.3 on end 	# Audio
+			device pci f.4 on end	# OHCI
 			device pci f.5 on end	# EHCI
-      		end
-    	end
+		end
+	end
+	# APIC cluster is late CPU init.
+	device lapic_cluster 0 on
+		chip cpu/amd/model_gx2
+			device lapic 0 on end
+		end
+	end
 end
 
diff --git a/src/northbridge/amd/gx2/chip.h b/src/northbridge/amd/gx2/chip.h
index 60b5691..34021ba 100644
--- a/src/northbridge/amd/gx2/chip.h
+++ b/src/northbridge/amd/gx2/chip.h
@@ -1,6 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 struct northbridge_amd_gx2_config
 {
- 	uint16_t irqmap;
+
 };
 
 extern struct chip_operations northbridge_amd_gx2_ops;
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 200ecfe..f567766 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -215,92 +215,6 @@ int sizeram(void)
 	return sizem;
 }
 
-/* these are the 8-bit attributes for controlling RCONF registers */
-#define CACHE_DISABLE (1<<0)
-#define WRITE_ALLOCATE (1<<1)
-#define WRITE_PROTECT (1<<2)
-#define WRITE_THROUGH (1<<3)
-#define WRITE_COMBINE (1<<4)
-#define WRITE_SERIALIZE (1<<5)
-
-/* ram has none of this stuff */
-#define RAM_PROPERTIES (0)
-#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
-#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
-
-/* setup_gx2_cache
- *
- * Returns the amount of memory (in KB) available to the system.  This is the
- * total amount of memory less the amount of memory reserved for SMM use.
- */
-static int setup_gx2_cache(void)
-{
-	msr_t msr;
-	unsigned long long val;
-	int sizekbytes, sizereg;
-
-	sizekbytes = sizeram() * 1024;
-	printk(BIOS_DEBUG, "setup_gx2_cache: enable for %d KB\n", sizekbytes);
-	/* build up the rconf word. */
-	/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
-	/* set romrp */
-	val = ((unsigned long long) ROM_PROPERTIES) << 56;
-	/* make rom base useful for 1M roms */
-	/* Flash base address -- sized for 1M for now */
-	val |= ((unsigned long long) 0xfff00)<<36;
-	/* set the devrp properties */
-	val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
-	/* Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */
-	/* yank off memory for the SMM handler */
-	sizekbytes -= SMM_SIZE;
-	sizereg = sizekbytes;
-	sizereg *= 1024;	/* convert to bytes */
-	sizereg >>= 12;
-	sizereg <<= 8;
-	val |= sizereg;
-	val |= RAM_PROPERTIES;
-	msr.lo = val;
-	msr.hi = (val >> 32);
-	printk(BIOS_DEBUG, "msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
-	wrmsr(CPU_RCONF_DEFAULT, msr);
-
-	enable_cache();
-	wbinvd();
-	return sizekbytes;
-}
-
-/* we have to do this here. We have not found a nicer way to do it */
-static void setup_gx2(void)
-{
-	unsigned long tmp, tmp2;
-	msr_t msr;
-	unsigned long size_kb, membytes;
-
-	size_kb = setup_gx2_cache();
-
-	membytes = size_kb * 1024;
-	/* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST!
-	 * so it is safe to use. You should NOT at this point call
-	 * sizeram() directly.
-	 */
-
-	/* fixme: SMM MSR 0x10000026 and 0x400000023 */
-	/* calculate the OFFSET field */
-	tmp = membytes - SMM_OFFSET;
-	tmp >>= 12;
-	tmp <<= 8;
-	tmp |= 0x20000000;
-	tmp |= (SMM_OFFSET >> 24);
-
-	/* calculate the PBASE and PMASK fields */
-	tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20  == left 8 */
-	tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
-	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%lx:0x%lx\n", 0x10000026, tmp, tmp2);
-	msr.hi = tmp;
-	msr.lo = tmp2;
-	wrmsr(0x10000026, msr);
-}
-
 static void enable_shadow(device_t dev)
 {
 
@@ -398,7 +312,6 @@ static void pci_domain_enable(device_t dev)
 	northbridge_init_early();
 	cpubug();
 	chipsetinit();
-	setup_gx2();
 	print_conf();
 	do_vsmbios();
 	graphics_init();
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index f52eaf2..e55efcb 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <arch/io.h>
 #include <stdint.h>
@@ -13,8 +33,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cache.h>
 
-/* put this here for now, we are not sure where it belongs */
-
 struct gliutable
 {
 	unsigned long desc_name;
@@ -100,9 +118,6 @@ struct msrinit GeodeLinkPriorityTable[] = {
 	{0x0FFFFFFFF, 			{0x0FFFFFFFF, 0x0FFFFFFFF}},	/* END */
 };
 
-/* do we have dmi or not? assume NO per AMD */
-int havedmi = 0;
-
 static void writeglmsr(struct gliutable *gl)
 {
 	msr_t msr;
@@ -110,10 +125,7 @@ static void writeglmsr(struct gliutable *gl)
 	msr.lo = gl->lo;
 	msr.hi = gl->hi;
 	wrmsr(gl->desc_name, msr);	/* MSR - see table above */
-	printk(BIOS_DEBUG, "%s: write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
-	/* they do this, so we do this */
-	msr = rdmsr(gl->desc_name);
-	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
 static void ShadowInit(struct gliutable *gl)
@@ -127,133 +139,71 @@ static void ShadowInit(struct gliutable *gl)
 	}
 }
 
-/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here.
- * CLEAN ME UP
- */
-/* yes, this duplicates later code, but it seems that is how they want it done. */
 static void SysmemInit(struct gliutable *gl)
 {
 	msr_t msr;
 	int sizembytes, sizebytes;
 
 	/* Figure out how much RAM is in the machine and alocate all to the
-	 * system. We will adjust for SMM and DMM now and Frame Buffer later.
+	 * system. We will adjust for SMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
-	printk(BIOS_DEBUG, "%s: enable for %dm bytes\n", __func__, sizembytes);
+	printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);
 	sizebytes = sizembytes << 20;
 
-	sizebytes -= SMM_SIZE * 1024 + 1;
-
-	if (havedmi)
-		sizebytes -= DMM_SIZE * 1024 + 1;
+	sizebytes -= ((SMM_SIZE * 1024) + 1);
 
-	sizebytes -= 1;
+	/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
+	   The top 8 bits go into 0-7 of msr.hi. */
+	sizebytes --;
 	msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
-	/* set up sizebytes to fit into msr.lo */
-	sizebytes <<= 8; /* what? well, we want bits 23:12 in bits 31:20. */
+	sizebytes <<= 8;	/* move bits 23:12 in bits 31:20. */
 	sizebytes &= 0xfff00000;
-	sizebytes |= 0x100;
+	sizebytes |= 0x100;	/* start at 1MB */
 	msr.lo = sizebytes;
 	wrmsr(gl->desc_name, msr);	/* MSR - see table above */
-	msr = rdmsr(gl->desc_name);
-	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 				gl->desc_name, msr.hi, msr.lo);
 }
 
-static void DMMGL0Init(struct gliutable *gl)
-{
-	msr_t msr;
-	int sizebytes = sizeram()<<20;
-	long offset;
-
-	if (! havedmi)
-		return;
-
-	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
-
-	sizebytes -= DMM_SIZE*1024;
-	offset = sizebytes - DMM_OFFSET;
-	printk(BIOS_DEBUG, "%s: offset is 0x%08lx\n", __func__, offset);
-	offset >>= 12;
-	msr.hi = (gl->hi) | (offset << 8);
-	/* I don't think this is needed */
-	msr.hi &= 0xffffff00;
-	msr.hi |= (DMM_OFFSET >> 24);
-	msr.lo = DMM_OFFSET << 8;
-	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
-
-	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
-	msr = rdmsr(gl->desc_name);
-	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
-}
-
-static void DMMGL1Init(struct gliutable *gl)
-{
-	msr_t msr;
-
-	if (! havedmi)
-		return;
-
-	printk(BIOS_DEBUG, "%s:\n", __func__ );
-
-	msr.hi = gl->hi;
-	/* I don't think this is needed */
-	msr.hi &= 0xffffff00;
-	msr.hi |= (DMM_OFFSET >> 24);
-	msr.lo = DMM_OFFSET << 8;
-	/* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */
-	printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
-	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
-
-	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
-	msr = rdmsr(gl->desc_name);
-	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
-}
-
 static void SMMGL0Init(struct gliutable *gl)
 {
 	msr_t msr;
 	int sizebytes = sizeram() << 20;
 	long offset;
 
-	sizebytes -= SMM_SIZE * 1024;
-
-	if (havedmi)
-		sizebytes -= DMM_SIZE * 1024;
+	sizebytes -= (SMM_SIZE * 1024);
 
 	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	offset = sizebytes - SMM_OFFSET;
-	printk(BIOS_DEBUG, "%s: offset is 0x%08lx\n", __func__, offset);
-	offset >>= 12;
+	offset = (offset >> 12) & 0x000fffff;
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
 
-	msr.hi = offset << 8;
+	msr.hi = offset << 8 | gl->hi;
 	msr.hi |= SMM_OFFSET >> 24;
 
 	msr.lo = SMM_OFFSET << 8;
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
-	msr = rdmsr(gl->desc_name);
-	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
 static void SMMGL1Init(struct gliutable *gl)
 {
 	msr_t msr;
-	printk(BIOS_DEBUG, "%s:\n", __func__ );
+	printk(BIOS_DEBUG, "%s:\n", __func__);
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
 	msr.hi &= 0xffffff00;
 	msr.hi |= (SMM_OFFSET >> 24);
-	msr.lo = SMM_OFFSET << 8;
+	msr.lo = (SMM_OFFSET << 8) & 0xfff00000;
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
-	msr = rdmsr(gl->desc_name);
-	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
 static void GLIUInit(struct gliutable *gl)
@@ -261,7 +211,6 @@ static void GLIUInit(struct gliutable *gl)
 	while (gl->desc_type != GL_END) {
 		switch (gl->desc_type) {
 		default:
-			/* For Unknown types: Write then read MSR */
 			writeglmsr(gl);
 		case SC_SHADOW: /* Check for a Shadow entry */
 			ShadowInit(gl);
@@ -271,14 +220,6 @@ static void GLIUInit(struct gliutable *gl)
 			SysmemInit(gl);
 			break;
 
-		case BMO_DMM: /* check for a DMM entry */
-			DMMGL0Init(gl);
-			break;
-
-		case BM_DMM: /* check for a DMM entry */
-			DMMGL1Init(gl);
-			break;
-
 		case BMO_SMM: /* check for a SMM entry */
 			SMMGL0Init(gl);
 			break;
@@ -333,8 +274,7 @@ static void GLPCIInit(void)
 		 * so we need a high page aligned addresss (pah) and low page aligned address (pal)
 		 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
 		 */
-		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
-		pah = ((msr.hi &0xff) << 12) | ((msr.lo >> 20) & 0xfff);
+		pah = ((msr.hi & 0xff) << 12) | ((msr.lo >> 20) & 0xfff);
 		/* we have the page address. Now make it a page-aligned address */
 		pah <<= 12;
 
@@ -342,7 +282,7 @@ static void GLPCIInit(void)
 		msr.hi = pah;
 		msr.lo = pal;
 		msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
-		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
 		wrmsr(msrnum, msr);
 	}
@@ -351,6 +291,7 @@ static void GLPCIInit(void)
 	msr.hi = ((SMM_OFFSET + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
 	msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
 	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
+	printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
 	msrnum = GLPCI_RC2;
 	wrmsr(msrnum, msr);
 
@@ -393,7 +334,9 @@ static void GLPCIInit(void)
 
 	/* we are ignoring the 5530 case for now, and perhaps forever. */
 
-	/* 5535 NB Init */
+	/* 553X NB Init */
+	
+	/* Arbiter setup */
 	msrnum = GLPCI_ARB;
 	msr = rdmsr(msrnum);
 	msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
@@ -449,33 +392,10 @@ static void ClockGatingInit(void)
 	struct msrinit *gating = ClockGatingDefault;
 	int i;
 
-#if 0
-	mov	cx, TOKEN_CLK_GATE
-	NOSTACK	bx, GetNVRAMValueBX
-	cmp	al, TVALUE_CG_OFF
-	je	gatingdone
-
-	cmp	al, TVALUE_CG_DEFAULT
-	jb	allon
-	ja	performance
-	lea	si, ClockGatingDefault
-	jmp	nextdevice
-
-allon:
-	lea	si, ClockGatingAllOn
-	jmp	nextdevice
-
-performance:
-	lea	si, ClockGatingPerformance
-#endif
-
-	for(i = 0; gating->msrnum != 0xffffffff; i++) {
+	for (i = 0; gating->msrnum != 0xffffffff; i++) {
 		msr = rdmsr(gating->msrnum);
-		printk(BIOS_DEBUG, "%s: MSR 0x%08lx is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo);
 		msr.hi |= gating->msr.hi;
 		msr.lo |= gating->msr.lo;
-		printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to  0x%08x:0x%08x\n", __func__,
-			gating->msrnum, msr.hi, msr.lo);
 		wrmsr(gating->msrnum, msr);	/* MSR - See the table above */
 		gating += 1;
 	}
@@ -484,17 +404,15 @@ performance:
 static void GeodeLinkPriority(void)
 {
 	msr_t msr = { 0, 0 };
+	
 	struct msrinit *prio = GeodeLinkPriorityTable;
 	int i;
 
 	for (i = 0; prio->msrnum != 0xffffffff; i++) {
 		msr = rdmsr(prio->msrnum);
-		printk(BIOS_DEBUG, "%s: MSR 0x%08lx is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
 		msr.hi |= prio->msr.hi;
 		msr.lo &= ~0xfff;
 		msr.lo |= prio->msr.lo;
-		printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
-			prio->msrnum, msr.hi, msr.lo);
 		wrmsr(prio->msrnum, msr);	/* MSR - See the table above */
 		prio += 1;
 	}
@@ -507,8 +425,8 @@ static void GeodeLinkPriority(void)
  */
 static uint64_t getShadow(void)
 {
-	msr_t msr;
-
+	msr_t msr = { 0, 0 };
+	
 	msr = rdmsr(GLIU0_P2D_SC_0);
 	return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
 }
@@ -614,8 +532,7 @@ static void setShadow(uint64_t shadowSettings)
 	}
 }
 
-/* Set up a stack for ease of further testing. */
-static void shadowRom(void)
+static void rom_shadow_settings(void)
 {
 	uint64_t shadowSettings = getShadow();
 	shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL;	/* Disable read & writes */
@@ -637,7 +554,7 @@ static void shadowRom(void)
 #define ROMBASE_RCONF_DEFAULT 0xFFFC0000
 #define ROMRC_RCONF_DEFAULT 0x25
 
-static void RCONFInit(void)
+static void enable_L_cache(void)
 {
 	struct gliutable *gl = 0;
 	int i;
@@ -657,7 +574,6 @@ static void RCONFInit(void)
 	}
 
 /* sysdescfound: */
-	/* found the descriptor... get its contents */
 	msr = rdmsr(gl->desc_name);
 
 	/* 20 bit address -  The bottom 12 bits go into bits 20-31 in eax, the
@@ -668,10 +584,10 @@ static void RCONFInit(void)
 	msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT;	/* 8 */
 
 	/* Set Default SYSMEM region properties */
-	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	/* 8 (or ~8) */
+	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	/* NOT writethrough == writeback 8 (or ~8) */
 
 	/* Set PCI space cache properties */
-	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);	/* only need the bottom bits and lets clean the rest of edx */
+	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);	/* setting is split betwwen hi and lo... */
 	msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
 
 	/* Set the ROMBASE. This is usually FFFC0000h */
@@ -682,14 +598,33 @@ static void RCONFInit(void)
 
 	/* now program RCONF_DEFAULT */
 	wrmsr(CPU_RCONF_DEFAULT, msr);
+	printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi, msr.lo);
 
-	/* RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. */
+	/* RCONF_BYPASS: Cache tablewalk properties and SMM header access properties. */
 	/* Set to match system memory cache properties. */
 	msr = rdmsr(CPU_RCONF_DEFAULT);
 	SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
 	msr = rdmsr(CPU_RCONF_BYPASS);
 	msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
 	wrmsr(CPU_RCONF_BYPASS, msr);
+	printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, msr.lo);
+}
+
+static void setup_gx2_cache(void)
+{
+	msr_t msr;
+
+	enable_L_cache();
+
+	/* Make sure all INVD instructions are treated as WBINVD.  We do this
+	 * because we've found some programs which require this behavior.
+	 */
+	msr = rdmsr(CPU_DM_CONFIG0);
+	msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
+	wrmsr(CPU_DM_CONFIG0, msr);
+
+	x86_enable_cache();
+	wbinvd();
 }
 
 uint32_t get_systop(void)
@@ -719,36 +654,27 @@ uint32_t get_systop(void)
 /* Core Logic initialization: Host bridge. */
 void northbridge_init_early(void)
 {
-	msr_t msr;
 	int i;
 	printk(BIOS_DEBUG, "Enter %s\n", __func__);
 
 	for (i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
 
-	GeodeLinkPriority();
-
-	shadowRom();
-
-	RCONFInit();
-
-	/* The cacheInit function in GeodeROM tests cache and, among other things,
-	 * makes sure all INVD instructions are treated as WBINVD.  We do this
-	 * because we've found some programs which require this behavior.
-	 * That subset of cacheInit() is implemented here:
-	 */
-	msr = rdmsr(CPU_DM_CONFIG0);
-	msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
-	wrmsr(CPU_DM_CONFIG0, msr);
-
 	/* Now that the descriptor to memory is set up. */
 	/* The memory controller needs one read to synch its lines before it can be used. */
 	i = *(int *) 0;
 
+	GeodeLinkPriority();
+
+	setup_gx2_cache();
+
+	rom_shadow_settings();
+
 	GLPCIInit();
+
 	ClockGatingInit();
-	__asm__("FINIT\n");
-	/* CPUBugsFix -- called elsewhere */
+
+	__asm__ __volatile__("FINIT\n");
 	printk(BIOS_DEBUG, "Exit %s\n", __func__);
 }
 


From hagigatali at gmail.com  Sat Dec 31 14:00:20 2011
From: hagigatali at gmail.com (ali hagigat)
Date: Sat, 31 Dec 2011 16:30:20 +0330
Subject: [coreboot] xgcc folder is not made!
Message-ID: <CAKKWdtftxKJ80VZbiSY+ySCU3v8d5Df3+jwWGRNa-T1DYbvowg@mail.gmail.com>

I downloaded the coreboot version 4 for a Ubuntu system. When i want to execute
util/crossgcc/make

It stops complaining that there is an error building GDB!
If i want to make without GDB like by buildgcc, it stops , the error
is that it can not find one h file in xgcc and iasl can not be made!

xgcc folder is not filled! What is the problem?

Regards

(PS. Besides when i want to compile the source code of coreboot by its
makefile, it stops and complains that one symbol has two contradict
types. Should i run `buildgcc`? before making the Coreboot source
code? )


From gerrit at coreboot.org  Sat Dec 31 14:56:37 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 31 Dec 2011 14:56:37 +0100
Subject: [coreboot] Patch merged into coreboot/master: b0a31b4 White space
	and coding style fixes.
References: <I14f39b5666fc18e8183723ec78a40a849d337736+0@gerrit.coreboot.org>
Message-ID: <E1RgzQL-0008KV-9X@ra.coresystems.de>

the following patch was just integrated into master:
commit b0a31b460822364e72bdf87c25e6b60946da120a
Author: Nils Jacobs <njacobs8 at adsltotaal.nl>
Date:   Fri Dec 30 22:30:27 2011 +0100

    White space and coding style fixes.
    
    Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736
    Signed-off-by: Nils Jacobs <njacobs8 at adsltotaal.nl>

Build-Tested: build bot (Jenkins) at Fri Dec 30 23:21:57 2011, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Sat Dec 31 14:56:35 2011, giving +2
See http://review.coreboot.org/511 for details.

-gerrit


From stefan.reinauer at coreboot.org  Sat Dec 31 19:48:38 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 31 Dec 2011 10:48:38 -0800
Subject: [coreboot] xgcc folder is not made!
In-Reply-To: <CAKKWdtftxKJ80VZbiSY+ySCU3v8d5Df3+jwWGRNa-T1DYbvowg@mail.gmail.com>
References: <CAKKWdtftxKJ80VZbiSY+ySCU3v8d5Df3+jwWGRNa-T1DYbvowg@mail.gmail.com>
Message-ID: <4EFF5906.3080700@coreboot.org>

On 12/31/11 5:00 AM, ali hagigat wrote:
> I downloaded the coreboot version 4 for a Ubuntu system. When i want to execute
> util/crossgcc/make
>
> It stops complaining that there is an error building GDB!
> If i want to make without GDB like by buildgcc, it stops , the error
> is that it can not find one h file in xgcc and iasl can not be made!
>
> xgcc folder is not filled! What is the problem?
>
> Regards
>
> (PS. Besides when i want to compile the source code of coreboot by its
> makefile, it stops and complains that one symbol has two contradict
> types.
An error log would be helpful.

> Should i run `buildgcc`  before making the Coreboot source
> code? )
yes.
>
Please update your coreboot checkout to the latest version. GDB is no 
longer built per default due to problems with some Linux distributions.


From prakashp at arcor.de  Fri Dec 30 16:06:54 2011
From: prakashp at arcor.de (Prakash Punnoor)
Date: Fri, 30 Dec 2011 16:06:54 +0100
Subject: [coreboot] Trouble building coreboot/SeaBios
Message-ID: <1454405.AelLYuJe3i@graviton>

Hi,
 
I am trying to build coreboot with SeaBios (for a new mainboard I am trying to 
port). Initially the build system complained about a broken LD, so I built 
make crossgcc -j1 (iasl compile fails in parallel mode, btw) and rm .xcompile 
as written in the wiki. Now make -j1 goes further and dies on building 
seabios:
 
Compilation complete. 0 Errors, 31 Warnings, 0 Remarks, 3 Optimizations
Compiling whole program out/ccode32flat.o
Compiling whole program out/code32seg.o
Building ld scripts (version "pre-1.6.4-20111230_155214-graviton")
File "./tools/layoutrom.py", line 75
print "Error: Fixed section %s has non-zero alignment (%d)" % (
 
I tried stable and master but both give this error. Any idea?
 
Regards,
 
Prakash
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From prakashp at arcor.de  Fri Dec 30 17:58:39 2011
From: prakashp at arcor.de (Prakash Punnoor)
Date: Fri, 30 Dec 2011 17:58:39 +0100
Subject: [coreboot] Trouble building coreboot/SeaBios
In-Reply-To: <CAPp9OrmjBMTsXjwGQ1AiF7CypqouwTBMkdFUF5owvPwb6i_KNQ@mail.gmail.com>
References: <2338194.f4GqbpMnWv@graviton>
	<CAPp9OrmjBMTsXjwGQ1AiF7CypqouwTBMkdFUF5owvPwb6i_KNQ@mail.gmail.com>
Message-ID: <3362532.UlYKD0VCHT@graviton>

On Friday 30 December 2011 16:46:15 Idwer Vollering wrote:
> 2011/12/30 Prakash Punnoor <prakash at punnoor.de>:
> > print "Error: Fixed section %s has non-zero alignment (%d)" % (
> > 
> > I tried stable and master but both give this error. Any idea?
> 
> Installing python 2.x will probably solve this.

Thanks, that solved it!

Cheers,

Prakash
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