[coreboot] New patch to review for coreboot: b21b8b8 Add Supermicro X7DB8 motherboard

Sven Schnelle (svens@stackframe.org) gerrit at coreboot.org
Sat Dec 17 19:42:34 CET 2011


Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/493

-gerrit

commit b21b8b87eb66058448e8803453bc2ccd51f1f6c2
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:22:44 2011 +0100

    Add Supermicro X7DB8 motherboard
    
    Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/supermicro/Kconfig             |    4 +
 src/mainboard/supermicro/x7db8/Kconfig       |   46 +++++++++++
 src/mainboard/supermicro/x7db8/chip.h        |   21 +++++
 src/mainboard/supermicro/x7db8/devicetree.cb |  111 ++++++++++++++++++++++++++
 src/mainboard/supermicro/x7db8/mainboard.c   |   41 ++++++++++
 src/mainboard/supermicro/x7db8/romstage.c    |   98 +++++++++++++++++++++++
 6 files changed, 321 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig
index 80ffd6a..794aead 100755
--- a/src/mainboard/supermicro/Kconfig
+++ b/src/mainboard/supermicro/Kconfig
@@ -25,6 +25,9 @@ config BOARD_SUPERMICRO_X6DHR_IG2
 	bool "X6DHR-iG2"
 config BOARD_SUPERMICRO_X6DHR_IG
 	bool "X6DHR-iG"
+config BOARD_SUPERMICRO_X7DB8
+	bool "X7DB8"
+
 
 endchoice
 
@@ -39,6 +42,7 @@ source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
 source "src/mainboard/supermicro/x6dhe_g/Kconfig"
 source "src/mainboard/supermicro/x6dhr_ig2/Kconfig"
 source "src/mainboard/supermicro/x6dhr_ig/Kconfig"
+source "src/mainboard/supermicro/x7db8/Kconfig"
 
 config MAINBOARD_VENDOR
 	string
diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig
new file mode 100644
index 0000000..56c616a
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/Kconfig
@@ -0,0 +1,46 @@
+if BOARD_SUPERMICRO_X7DB8
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_LGA771
+	select SOUTHBRIDGE_INTEL_I3100
+	select NORTHBRIDGE_INTEL_I5000
+	select SUPERIO_WINBOND_W83627HF
+	select MMCONF_SUPPORT
+	select HAVE_OPTION_TABLE
+	select BOARD_ROMSIZE_KB_512
+
+config MAINBOARD_DIR
+	string
+	default supermicro/x7db8
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Supermicro X7DB8"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xe0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+
+endif
diff --git a/src/mainboard/supermicro/x7db8/chip.h b/src/mainboard/supermicro/x7db8/chip.h
new file mode 100644
index 0000000..70f9bb4
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb
new file mode 100644
index 0000000..36e4aed
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/devicetree.cb
@@ -0,0 +1,111 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/i5000
+
+	device lapic_cluster 0 on
+		chip cpu/intel/socket_LGA771
+			device lapic 0 on end
+		end
+	end
+
+	device pci_domain 0 on
+		device pci 00.0 on # Host bridge
+			subsystemid 0x15d9 0x2017
+		end
+
+		device pci 02.0 on # PCIe bridge
+			device pci 00.0 on
+				device pci 00.0 on
+					device pci 00.0 on end
+					device pci 02.0 on end
+				end
+				device pci 02.0 on
+					device pci 00.0 on end
+					device pci 00.1 on end
+				end
+			end
+			device pci 00.3 on
+
+			end
+		end
+
+		device pci 03.0 on end
+		device pci 04.0 on end
+		device pci 05.0 on end
+		device pci 06.0 on end
+		device pci 07.0 on end
+		device pci 10.0 on end # FBD
+		device pci 10.1 on end # FBD
+		device pci 10.2 on end # FBD
+		device pci 11.0 on end # FBD reserved
+		device pci 13.0 on end # FBD reserved
+		device pci 15.0 on end # FBD
+		device pci 16.0 on end # FBD
+
+		chip southbridge/intel/i3100
+		device pci 1c.0 on end # PCIe bridge
+		device pci 1d.0 on end # USB UHCI
+		device pci 1d.1 on end # USB UHCI
+		device pci 1d.2 on end # USB UHCI
+		device pci 1d.3 on end # USB UHCI
+		device pci 1d.7 on end # USB2 EHCI
+		device pci 1e.0 on
+		       device pci 01.0 on
+		       end
+		end
+		device pci 1e.2 on end
+		device pci 1e.3 on end
+
+		device pci 1f.0 on # PCI-LPC bridge
+			subsystemid 0x15d9 0x2009
+			chip superio/winbond/w83627hf
+				device pnp 2e.0 off end # FDC
+				device pnp 2e.1 on # Parallel Port
+					io 0x60 = 0x378
+					irq 0x70 = 7
+				end
+				device pnp 2e.2 on # Serial Port 1
+					io 0x60 = 0x3f8
+					irq 0x70 = 4
+				end
+
+				device pnp 2e.3 off end
+				device pnp 2e.5 on # KBC
+				end
+
+				device pnp 2e.6 off end # CIR
+				device pnp 2e.7 off end # Game port / MIDI
+				device pnp 2e.8 off end # GPIO2
+				device pnp 2e.9 off end # GPIO3
+				device pnp 2e.a off end # ACPI
+				device pnp 2e.b off end # HWMON
+			end
+		end
+		device pci 1f.1 on end # IDE
+		device pci 1f.2 on end # IDE
+		device pci 1f.3 on # SMBUS
+			subsystemid 0x15d9 0x200f
+			end
+		end
+	end
+end
diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c
new file mode 100644
index 0000000..27a26f9
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/mainboard.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#include <arch/coreboot_tables.h>
+#include "chip.h"
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+static void mainboard_enable(device_t dev)
+{
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
+	.enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c
new file mode 100644
index 0000000..b4242a3
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/romstage.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <superio/winbond/w83627hf/early_serial.c>
+#include <southbridge/intel/i63xx/i63xx.h>
+#include <northbridge/intel/i5000/raminit.h>
+
+
+static void setup_gpio(void)
+{
+	pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1);
+	pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4));
+
+
+	outl(0xff0c79cf, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+	outl(0xe700ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+	outl(0x65bf0000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+	outl(0x0000718a, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+	outl(0x00000106, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
+	outl(0x00000301, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
+	outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */
+
+}
+
+static void i5000_lpc_config(void)
+{
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+}
+
+void main(unsigned long bist)
+{
+	if (bist == 0)
+		enable_lapic();
+
+	i5000_lpc_config();
+
+	w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);
+
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	setup_gpio();
+
+	enable_smbus();
+
+	/* setup PCIe MMCONF base address */
+	pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
+			   CONFIG_MMCONF_BASE_ADDRESS >> 16);
+
+	outb(0x07, 0x11b8);
+
+	/* These are smbus write captured with serialice. They
+	   seem to setup the clock generator */
+
+	if (smbus_write_byte(0x6f, 0x88, 0x1f) ||
+	    smbus_write_byte(0x6f, 0x81, 0xff) ||
+	    smbus_write_byte(0x6f, 0x82, 0xff) ||
+	    smbus_write_byte(0x6f, 0x80, 0x23))
+		printk(BIOS_ERR, "Clock generator setup failed\n");
+
+	outb(0x03, 0x11b8);
+	outb(0x01, 0x11b8);
+
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1);
+	i5000_fbdimm_init();
+	smbus_write_byte(0x69, 0x01, 0x01);
+}




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