[coreboot] Patch set updated for coreboot: 14cd7a8 Fix multipleVGA cards resource conflict on Windows

Kerry Sheh (shekairui@gmail.com) gerrit at coreboot.org
Wed Dec 21 12:21:48 CET 2011


Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/489

-gerrit

commit 14cd7a8f8e165622cb9f537a6b6275d274e5e78e
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Dec 21 20:05:21 2011 +0800

    Fix multipleVGA cards resource conflict on Windows
    
    If multiple VGA-compatible legacy graphic cards decode the IO range
    3B0-3BB, 3C0-3DF and MEM range A00000-BFFFF.
    Windows 7 complain a resource conflict, so only one VGA card can
    works at the same time.
    
    By disable the IO & MEM decode of the second vga graphic device,
    this patch resolved the resource conflict in windows7, multiple
    vga-compatible graphic cards can work together in windows7.
    Please reference PCI spec. section 3.10 in detail.
    
    There is a discuss in coreboot mail list before,
    please reference thread: "how to prevent legacy resource conflictwith   multipleVGA cards"
    
    Linux using VGA Arbiter module(vgaarb) to resolve this resource conflict,
    Please see the following linux dmesg log, more information can be found in
    Linux source dir Documentation/vgaarbiter.txt.
    But it seems that windows don't dealwith this conflict.
    ~# dmesg | grep -i vgaarb
    [    0.774076] vgaarb: device added: PCI:0000:00:01.0,decodes=io+mem,owns=io+mem
    [    0.776065] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,l
    [    0.780051] vgaarb: loaded
    [    0.784049] vgaarb: bridge control possible 0000:01:00.0
    [    0.788050] vgaarb: bridge control possible 0000:00:01.0
    
    For the second legacy graphic device, coreboot already disabled the
    IO and MEM decode in function set_vga_bridge_bits().
    But it will be enabled again in function pci_set_resource(),
    if the second legacy vga-compatible graphic device take any IO/MEM resources.
    
    Following log printed by enable_resources() shows the problem:
    ...snip...
    PCI: 00:00.0 cmd <- 06
    PCI: 00:01.0 subsystem <- 1022/1410
    PCI: 00:01.0 cmd <- 07                <== The first graphic device
    PCI: 00:01.1 subsystem <- 1022/1410
    PCI: 00:01.1 cmd <- 02
    PCI: 00:02.0 bridge ctrl <- 0003
    PCI: 00:02.0 cmd <- 07
    ...snip...
    PCI: 01:00.0 cmd <- 03                <== The second graphic device
    PCI: 01:00.1 cmd <- 02
    PCI: 02:00.0 cmd <- 02
    PCI: 03:00.0 cmd <- 03
    done.
    ...snip...
    
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d
---
 src/devices/pci_device.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 2ccb38a..8270753 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -494,6 +494,26 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
 			dev->command |= PCI_COMMAND_IO;
 		if (resource->flags & IORESOURCE_PCI_BRIDGE)
 			dev->command |= PCI_COMMAND_MASTER;
+
+		/* It isn't safe to enable multiple VGA cards.
+		 * See PCI spec section 3.10.
+		 * The palette snoop bit will be set by the system firmware
+		 * when it detects both a VGA device and a graphics accelerator
+		 * device that are on separate add-in cards on the same bus or
+		 * on the same path but on different buses.
+		 * Either device can be set to snoop and the other will be set
+		 * to positively respond.
+		 */
+#if CONFIG_VGA_BRIDGE_SETUP == 1
+		extern device_t vga_pri;
+		if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
+			(dev != vga_pri)) {
+			if (((vga_pri->class >> 8) == PCI_CLASS_DISPLAY_VGA) &&
+				((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) {
+				dev->command &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+			}
+		}
+#endif
 	}
 
 	/* Get the base address. */




More information about the coreboot mailing list