From mr.nuke.me at gmail.com  Tue Feb  1 01:18:25 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Tue, 01 Feb 2011 02:18:25 +0200
Subject: [coreboot] [PATCH] Add support for VIA K8T800 northbridge
Message-ID: <4D475151.9030909@gmail.com>

See patch for details.

I have an ASUS K8V-X SE with the named NB, and this patch is sufficient
to get the HT link working properly, and to get a working V-Link with
the southbridge.
The modifications in the vt8237r directory allow the respective SB to
find the K8T800 and K8M800 NBs.

I will need someone with a K8T890 to test this patch to make sure it
doesn't break anything on the K8T890 side.

Alex

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From scouter389 at gmail.com  Tue Feb  1 00:50:27 2011
From: scouter389 at gmail.com (James Wall)
Date: Mon, 31 Jan 2011 17:50:27 -0600
Subject: [coreboot] 848P-A7 supported?
Message-ID: <4D474AC3.8040209@gmail.com>

Hello all,
I have a ECS 848P-A7 that I was wondering if it could be supported since
all the chipset chips were already listed as being supported. The
motherboard specification page address is

http://www.ecsusa.com/ECSWebSite/Product/Product_Detail.aspx?CategoryID=1&DetailID=475&DetailName=Feature&MenuID=24&LanID=9#fragment-SPEC


and I have attached the lspci dump as well as the superiotool and
flashrom dump. I noticed that the bios chip was listed as untested on
the write and erase options which I tested and appear to work because I
was able to erase and reimage the bios onto the chip.
Thanks in advance,
 James Wall
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From vidwer at gmail.com  Tue Feb  1 01:35:54 2011
From: vidwer at gmail.com (Idwer Vollering)
Date: Tue, 1 Feb 2011 01:35:54 +0100
Subject: [coreboot] 848P-A7 supported?
In-Reply-To: <4D474AC3.8040209@gmail.com>
References: <4D474AC3.8040209@gmail.com>
Message-ID: <AANLkTinCd_SM66An0m6FQOqLJhhpf-pQPjbSbmre044r@mail.gmail.com>

2011/2/1 James Wall <scouter389 at gmail.com>

> Hello all,
> I have a ECS 848P-A7 that I was wondering if it could be supported since
> all the chipset chips were already listed as being supported.


No, the Intel 848P currently isn't supported but the datasheet can be found
here: http://www.intel.com/design/chipsets/datashts/253575.htm

Looking at the output from lspci tells that the northbridge is i865 ?
In that case: http://www.intel.com/design/chipsets/datashts/252514.htm

I've planned to continue with working on ram init for the i865 next week or
so.


> The
> motherboard specification page address is
>
>
> http://www.ecsusa.com/ECSWebSite/Product/Product_Detail.aspx?CategoryID=1&DetailID=475&DetailName=Feature&MenuID=24&LanID=9#fragment-SPEC
>
>
> and I have attached the lspci dump as well as the superiotool and
> flashrom dump. I noticed that the bios chip was listed as untested on
> the write and erase options which I tested and appear to work because I
> was able to erase and reimage the bios onto the chip.
> Thanks in advance,
>  James Wall
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From svens at stackframe.org  Tue Feb  1 09:08:38 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Feb 2011 09:08:38 +0100
Subject: [coreboot] Add Lenovo PMH7
Message-ID: <878vy0p46x.fsf@begreifnix.stackframe.org>

Hi List,

this patch adds support for the Lenovo PMH7 (Power Management Hardware
Hub) found in most recent (starting with X60/T60 AFAIK) Lenovo/IBM
Laptops.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
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From svens at stackframe.org  Tue Feb  1 09:08:38 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Feb 2011 09:08:38 +0100
Subject: [coreboot] [PATCH v2] Add Lenovo PMH7
Message-ID: <87k4hknkhr.fsf@begreifnix.stackframe.org>

Hi List,

this patch adds support for the Lenovo PMH7 (Power Management Hardware
Hub) found in most recent (starting with X60/T60 AFAIK) Lenovo/IBM
Laptops. Please ignore the previous version, as it missed the
src/ec/Kconfig file.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
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From mathias.krause at secunet.com  Tue Feb  1 11:18:36 2011
From: mathias.krause at secunet.com (Mathias Krause)
Date: Tue, 01 Feb 2011 11:18:36 +0100
Subject: [coreboot] [PATCH] Fix abuild's config argument
Message-ID: <4D47DDFC.1000705@secunet.com>

The undocumented config argument for the -t option implicitly assumes
the config file is within the mainboard directory but fails to honor
this assumption when it comes to copying the file.

Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
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From svn at coreboot.org  Tue Feb  1 11:42:52 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Feb 2011 11:42:52 +0100
Subject: [coreboot] [commit] r6324 - trunk/util/abuild
Message-ID: <E1PkDhE-0001vv-WF@ra.coresystems.de>

Author: oxygene
Date: Tue Feb  1 11:42:52 2011
New Revision: 6324
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6324

Log:
Fix using custom build configs in abuild

The undocumented config argument for the -t option implicitly assumes
the config file is within the mainboard directory but fails to honor
this assumption when it comes to copying the file.

Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/util/abuild/abuild

Modified: trunk/util/abuild/abuild
==============================================================================
--- trunk/util/abuild/abuild	Mon Jan 31 22:16:48 2011	(r6323)
+++ trunk/util/abuild/abuild	Tue Feb  1 11:42:52 2011	(r6324)
@@ -161,7 +161,7 @@
 	if [ "$CONFIG" != "" ]; then
 		printf "  Using existing configuration $CONFIG ... "
 		xml "  <config>$CONFIG</config>"
-		cp $CONFIG ${build_dir}/config.build
+		cp src/mainboard/$VENDOR/$MAINBOARD/$CONFIG ${build_dir}/config.build
 	else
 		printf "  Creating config file... "
 		xml "  <config>autogenerated</config>"



From svn at coreboot.org  Tue Feb  1 11:44:26 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Feb 2011 11:44:26 +0100
Subject: [coreboot] [commit] r6325 - in trunk/src/ec: . lenovo lenovo/pmh7
Message-ID: <E1PkDik-0003Fo-P7@ra.coresystems.de>

Author: oxygene
Date: Tue Feb  1 11:44:26 2011
New Revision: 6325
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6325

Log:
Add support for the Lenovo PMH7 embedded controller

Lenovo PMH7 (Power Management Hardware Hub) is found in
most recent (starting with X60/T60 AFAIK) Lenovo/IBM Laptops.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Added:
   trunk/src/ec/lenovo/
   trunk/src/ec/lenovo/Kconfig
   trunk/src/ec/lenovo/Makefile.inc
   trunk/src/ec/lenovo/pmh7/
   trunk/src/ec/lenovo/pmh7/Kconfig
   trunk/src/ec/lenovo/pmh7/Makefile.inc
   trunk/src/ec/lenovo/pmh7/pmh7.c
   trunk/src/ec/lenovo/pmh7/pmh7.h
Modified:
   trunk/src/ec/Kconfig

Modified: trunk/src/ec/Kconfig
==============================================================================
--- trunk/src/ec/Kconfig	Tue Feb  1 11:42:52 2011	(r6324)
+++ trunk/src/ec/Kconfig	Tue Feb  1 11:44:26 2011	(r6325)
@@ -1 +1,2 @@
 source src/ec/acpi/Kconfig
+source src/ec/lenovo/Kconfig

Added: trunk/src/ec/lenovo/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/ec/lenovo/Kconfig	Tue Feb  1 11:44:26 2011	(r6325)
@@ -0,0 +1 @@
+source src/ec/lenovo/pmh7/Kconfig

Added: trunk/src/ec/lenovo/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/ec/lenovo/Makefile.inc	Tue Feb  1 11:44:26 2011	(r6325)
@@ -0,0 +1 @@
+subdirs-$(CONFIG_EC_LENOVO_PMH7) += pmh7

Added: trunk/src/ec/lenovo/pmh7/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/ec/lenovo/pmh7/Kconfig	Tue Feb  1 11:44:26 2011	(r6325)
@@ -0,0 +1,2 @@
+config EC_LENOVO_PMH7
+	bool

Added: trunk/src/ec/lenovo/pmh7/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/ec/lenovo/pmh7/Makefile.inc	Tue Feb  1 11:44:26 2011	(r6325)
@@ -0,0 +1 @@
+driver-y += pmh7.c

Added: trunk/src/ec/lenovo/pmh7/pmh7.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/ec/lenovo/pmh7/pmh7.c	Tue Feb  1 11:44:26 2011	(r6325)
@@ -0,0 +1,56 @@
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <stdlib.h>
+
+#include "pmh7.h"
+
+void pmh7_register_set_bit(int reg, int bit)
+{
+	char val;
+
+	outb(reg, EC_LENOVO_PMH7_ADDR);
+	val = inb(EC_LENOVO_PMH7_DATA);
+	outb(reg, EC_LENOVO_PMH7_ADDR);
+	outb(val | (1 << bit), EC_LENOVO_PMH7_DATA);
+}
+
+void pmh7_register_clear_bit(int reg, int bit)
+{
+	char val;
+
+	outb(reg, EC_LENOVO_PMH7_ADDR);
+	val = inb(EC_LENOVO_PMH7_DATA);
+	outb(reg, EC_LENOVO_PMH7_ADDR);
+	outb(val &= ~(1 << bit), EC_LENOVO_PMH7_DATA);
+}
+
+char pmh7_register_read(int reg)
+{
+	outb(reg, EC_LENOVO_PMH7_ADDR);
+	return inb(EC_LENOVO_PMH7_DATA);
+}
+
+void pmh7_register_write(int reg, int val)
+{
+	outb(reg, EC_LENOVO_PMH7_ADDR);
+	outb(val, EC_LENOVO_PMH7_DATA);
+}
+
+static void enable_dev(device_t dev)
+{
+	struct resource *resource;
+	resource = new_resource(dev, EC_LENOVO_PMH7_INDEX);
+	resource->flags = IORESOURCE_IO | IORESOURCE_FIXED;
+	resource->base = EC_LENOVO_PMH7_BASE;
+	resource->size = 16;
+	resource->align = 5;
+	resource->gran = 5;
+
+}
+
+struct chip_operations ec_lenovo_pmh7_ops = {
+	CHIP_NAME("Lenovo Power Management Hardware Hub 7")
+	.enable_dev = enable_dev,
+};

Added: trunk/src/ec/lenovo/pmh7/pmh7.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/ec/lenovo/pmh7/pmh7.h	Tue Feb  1 11:44:26 2011	(r6325)
@@ -0,0 +1,15 @@
+#ifndef EC_LENOVO_PMH7_H
+#define EC_LENOVO_PMH7_H
+
+#define EC_LENOVO_PMH7_INDEX 0x77
+
+#define EC_LENOVO_PMH7_BASE 0x15e0
+#define EC_LENOVO_PMH7_ADDR (EC_LENOVO_PMH7_BASE + 0x0c)
+#define EC_LENOVO_PMH7_DATA (EC_LENOVO_PMH7_BASE + 0x0e)
+
+void pmh7_register_set_bit(int reg, int bit);
+void pmh7_register_clear_bit(int reg, int bit);
+char pmh7_register_read(int reg);
+void pmh7_register_write(int reg, int val);
+
+#endif



From Patrick.Georgi at secunet.com  Tue Feb  1 11:47:02 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Tue, 1 Feb 2011 11:47:02 +0100
Subject: [coreboot] [PATCH] Fix abuild's config argument
In-Reply-To: <4D47DDFC.1000705@secunet.com>
References: <4D47DDFC.1000705@secunet.com>
Message-ID: <1296557222.6489.64.camel@linux-0a8x.site>

Am Dienstag, den 01.02.2011, 11:18 +0100 schrieb Mathias Krause:
> The undocumented config argument for the -t option implicitly assumes
> the config file is within the mainboard directory but fails to honor
> this assumption when it comes to copying the file.
Good catch. Thank you!

> Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>
and committed as r6324


Patrick
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From Patrick.Georgi at secunet.com  Tue Feb  1 11:47:37 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Tue, 1 Feb 2011 11:47:37 +0100
Subject: [coreboot] [PATCH v2] Add Lenovo PMH7
In-Reply-To: <87k4hknkhr.fsf@begreifnix.stackframe.org>
References: <87k4hknkhr.fsf@begreifnix.stackframe.org>
Message-ID: <1296557257.6489.65.camel@linux-0a8x.site>

Am Dienstag, den 01.02.2011, 09:08 +0100 schrieb Sven Schnelle:
> this patch adds support for the Lenovo PMH7 (Power Management Hardware
> Hub) found in most recent (starting with X60/T60 AFAIK) Lenovo/IBM
> Laptops. Please ignore the previous version, as it missed the
> src/ec/Kconfig file.
> 
> Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>
and committed as r6325


Patrick
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From svens at stackframe.org  Tue Feb  1 11:58:04 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Feb 2011 11:58:04 +0100
Subject: [coreboot] [PATCH] add PC87382 to superiotool
Message-ID: <87ei7snhs3.fsf@begreifnix.stackframe.org>

Hi List,

this patch adds the NSC PC87382 to superiotool. It is a rather small
'superio' device, containing one Serial Port, one Infrared Port, GPIO
and a Docking LPC switch. It is used in various Thinkpads.

It adds 0x164e/0x16ef to the list of probed port for NSC chipsets, as
Thinkpads are using this address pair.

Signed-off-by: Sven Schnelle <svens at stackframe.org>

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From juhe at iki.fi  Tue Feb  1 12:05:24 2011
From: juhe at iki.fi (Juhana Helovuo)
Date: Tue, 01 Feb 2011 13:05:24 +0200
Subject: [coreboot] QA contribution
In-Reply-To: <20110130111604.4440.qmail@stuge.se>
References: <AANLkTimaLyGgk2ZNQ7QhOWGxgUDPkyCJ=N3M8c9DnPLE@mail.gmail.com>	<20110130060515.GB19798@coreboot.org>	<AANLkTikwBeK=z-hAHN8yu3beX8jhdJzZvzSaoq8B0PBs@mail.gmail.com>
	<20110130111604.4440.qmail@stuge.se>
Message-ID: <4D47E8F4.3090403@iki.fi>

30.1.2011 13:16, Peter Stuge kirjoitti:

> Personally I believe that development is what is missing to get
> corebot testing going to a greater extent. As you will see in the
> documentation there are fairly many requirements for an individual
> mainboard to actually be hooked up to the test system. It's fully
> automated once it runs, but it's too complicated to get there.
>
> I think this needs to be optimized and to some degree productized,
> into an easy to buy and fairly affordable (<100$) unit that can
> administer testing of one or even better several mainboards. I have
> plenty of design and implementation ideas if you'd like to go into
> that.

Hello all,

I started building a tester device to hook up a mainboard into an 
automated test host.

The basic plan is as follows: The host computer is connected to tester 
device via USB. The tester is connected to the target mainboard so that 
it can take control of the BIOS ROM and reprogram it regardless of the 
state of the target mainbaord.

The tester device can also connect to the serial port of the target 
mainboard, so it can act as a serial-over-USB-device. This is because 
otherwise controlling the test of N mainboards would require N serial 
ports in the host.

The tester also has two FET switches for controlling the reset and ATX 
power buttons on the target mainboard.

The actual AC power control of the target mainboard is not included and 
should be done by another device, such as this:
http://www.gembird.nl/default.aspx?op=products&op2=item&id=3234

So far there is support only for SPI ROMs, but the design could be 
modified to support LPC and FWH also.

The tester device is basically an Atmel Atmega microcontroller, which 
can talk USB, RS232, SPI, and generic digital I/O.

Here are some images of my first (incomplete) prototype:

http://alpskari.asiantuntijat.org/~juhe/spi-flasher-piirilevyt/

The images were originally taken just to illustrate the PCB making 
experiment via the toner transfer method, but you can also see what the 
device looks like. The smaller board is specific to SPI ROMs and 
attaches to the SPI ROM socket on the mainbaord. The larger PCB is a 
microcontroller, which connects all the parts together.

Both the software and hardware are incomplete. Hardware is missing some 
parts and work.

The software is not yet done, except a prototype microcontroller program 
that can read and program SPI ROMs. It is controlled by "flashrom" from 
Linux host. It can communicate via serial port using the "serial 
programmer" protocol. Flashrom program was modified by adding a 
"serprog-spi"-module, which is modified from "serprog", mainly by 
adapting it to suit SPI.


Best regards,
Juhana Helovuo



From hagigatali at gmail.com  Tue Feb  1 12:46:25 2011
From: hagigatali at gmail.com (ali hagigat)
Date: Tue, 1 Feb 2011 15:16:25 +0330
Subject: [coreboot] a question about reset16.lds
Message-ID: <AANLkTikkEg62XVUj65zDeGa3+BjxP8FHSYPVVh4b=jLg@mail.gmail.com>

SECTIONS {
	/* Trigger an error if I have an unuseable start address */
	_bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please
decrease CONFIG_ROM_IMAGE_SIZE");
	_ROMTOP = 0xfffffff0;
	. = _ROMTOP;
	.reset . : {
		*(.reset)
		. = 15 ;
		BYTE(0x00);
	}
}
------------------------------------------------------------------
What does (.=15;) mean? It seems a mistake! and can be: . = .+1;



From joe at settoplinux.org  Tue Feb  1 13:19:03 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 01 Feb 2011 07:19:03 -0500
Subject: [coreboot] QA contribution
In-Reply-To: <4D47E8F4.3090403@iki.fi>
References: <AANLkTimaLyGgk2ZNQ7QhOWGxgUDPkyCJ=N3M8c9DnPLE@mail.gmail.com>	<20110130060515.GB19798@coreboot.org>	<AANLkTikwBeK=z-hAHN8yu3beX8jhdJzZvzSaoq8B0PBs@mail.gmail.com>
	<20110130111604.4440.qmail@stuge.se> <4D47E8F4.3090403@iki.fi>
Message-ID: <6dc2684092219b6bddf4bc13835b2433@imap.1and1.com>



On Tue, 01 Feb 2011 13:05:24 +0200, Juhana Helovuo <juhe at iki.fi> wrote:
> 30.1.2011 13:16, Peter Stuge kirjoitti:
> 
>> Personally I believe that development is what is missing to get
>> corebot testing going to a greater extent. As you will see in the
>> documentation there are fairly many requirements for an individual
>> mainboard to actually be hooked up to the test system. It's fully
>> automated once it runs, but it's too complicated to get there.
>>
>> I think this needs to be optimized and to some degree productized,
>> into an easy to buy and fairly affordable (<100$) unit that can
>> administer testing of one or even better several mainboards. I have
>> plenty of design and implementation ideas if you'd like to go into
>> that.
> 
> Hello all,
> 
> I started building a tester device to hook up a mainboard into an
> automated test host.
> 
> The basic plan is as follows: The host computer is connected to tester
> device via USB. The tester is connected to the target mainboard so that
> it can take control of the BIOS ROM and reprogram it regardless of the
> state of the target mainbaord.
> 
> The tester device can also connect to the serial port of the target
> mainboard, so it can act as a serial-over-USB-device. This is because
> otherwise controlling the test of N mainboards would require N serial
> ports in the host.
> 
> The tester also has two FET switches for controlling the reset and ATX
> power buttons on the target mainboard.
> 
> The actual AC power control of the target mainboard is not included and
> should be done by another device, such as this:
> http://www.gembird.nl/default.aspx?op=products&op2=item&id=3234
> 
> So far there is support only for SPI ROMs, but the design could be
> modified to support LPC and FWH also.
> 
> The tester device is basically an Atmel Atmega microcontroller, which
> can talk USB, RS232, SPI, and generic digital I/O.
> 
> Here are some images of my first (incomplete) prototype:
> 
> http://alpskari.asiantuntijat.org/~juhe/spi-flasher-piirilevyt/
> 
> The images were originally taken just to illustrate the PCB making
> experiment via the toner transfer method, but you can also see what the
> device looks like. The smaller board is specific to SPI ROMs and
> attaches to the SPI ROM socket on the mainbaord. The larger PCB is a
> microcontroller, which connects all the parts together.
> 
> Both the software and hardware are incomplete. Hardware is missing some
> parts and work.
> 
> The software is not yet done, except a prototype microcontroller program
> that can read and program SPI ROMs. It is controlled by "flashrom" from
> Linux host. It can communicate via serial port using the "serial
> programmer" protocol. Flashrom program was modified by adding a
> "serprog-spi"-module, which is modified from "serprog", mainly by
> adapting it to suit SPI.
> 
> 
> Best regards,
> Juhana Helovuo

Wow! that is really cool! I hope it works out as planned :-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From peter at stuge.se  Tue Feb  1 13:58:28 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 1 Feb 2011 13:58:28 +0100
Subject: [coreboot] Tester devices [was: QA contribution]
In-Reply-To: <4D47E8F4.3090403@iki.fi>
References: <AANLkTimaLyGgk2ZNQ7QhOWGxgUDPkyCJ=N3M8c9DnPLE@mail.gmail.com>
	<20110130060515.GB19798@coreboot.org>
	<AANLkTikwBeK=z-hAHN8yu3beX8jhdJzZvzSaoq8B0PBs@mail.gmail.com>
	<20110130111604.4440.qmail@stuge.se> <4D47E8F4.3090403@iki.fi>
Message-ID: <20110201125829.18404.qmail@stuge.se>

Juhana Helovuo wrote:
>> unit that can administer testing of one or even better several
>> mainboards. I have plenty of design and implementation ideas if
>> you'd like to go into that.
>
> I started building a tester device to hook up a mainboard into an
> automated test host.

Nice.


> The basic plan is as follows:
> The host computer is connected to tester device via USB.

This certainly makes the device itself simpler. But it requires
*another* system to be monitoring all these devices.. I can't seem to
let go of the thought that I would prefer a tester device to be
connected directly to the internet, and work autonomously. Ethernet
is simple enough with something like an LM3S6965 ARM. WiFi would be a
nice option, but will also increase the unit cost..


> The tester is connected to the target mainboard so that it can take
> control of the BIOS ROM and reprogram it regardless of the state of
> the target mainbaord.

Yes. A flash emulator would of course be ideal, but also requires
some programmable logic, ie. either one more component, or a larger
component. In some cases board size is critical, e.g. to fit a tester
inside a tight case.


> The tester device can also connect to the serial port of the target
> mainboard, so it can act as a serial-over-USB-device.

Right. Either the tester just has a UART, or if it is networked then
it will itself do the checkpointing. As for the USB device, it's
fairly important to use a generic USB hardware. The ATmega U chips
would work fine I believe. The key is to have multiple interfaces,
ie. at least one bulk IN endpoint for the serial port, and one bulk
OUT endpoint for downloading flash data, but it might be a good idea
to make both of them bidirectional, which then needs four bulk
endpoints. And it's important to be able to provide custom
descriptors, which the ATmega U and many other micros with USB
allows.


> The tester also has two FET switches for controlling the reset and
> ATX power buttons on the target mainboard.

Yep. I've also been thinking that the power good signal could be
used. One problem with FETs is that they must be plugged in to the
mainboard the right way. It would be significantly simpler to use the
device if it had a solid state switch instead, but that's also more
expensive.


> The actual AC power control of the target mainboard is not included
> and should be done by another device, such as this:
> http://www.gembird.nl/default.aspx?op=products&op2=item&id=3234

Do you know where these units can be purchased, with the various
voltage ratings and power plugs that are needed around the world?


> Here are some images of my first (incomplete) prototype:
>
> http://alpskari.asiantuntijat.org/~juhe/spi-flasher-piirilevyt/

Looks like a great start!


> The software is not yet done, except a prototype microcontroller
> program that can read and program SPI ROMs. It is controlled by
> "flashrom" from Linux host. It can communicate via serial port
> using the "serial programmer" protocol.

With USB connectivity I think it is important to really take
advantage of the simplicity and efficiency of USB, rather than
emulating a serial port on top of it. Also, having a serial port over
USB both for target connectivity, *and* for flash programming, is IMO
unneccssarily confusing. For the flashing we will simply implement
the serprog protocol properly using native USB concepts. It should be
very easy.


> Flashrom program was modified by adding a "serprog-spi"-module,
> which is modified from "serprog", mainly by adapting it to suit
> SPI.

Hm, ok. Yeah maybe some hacking will be needed in flashrom. I've
tried to get a design discussion going with Carl-Daniel for a data
model that can describe any SPI programming algorithm, but he's very
busy. I believe that data model is really what is needed to make the
programming really fast. But of course, serprog works right now!


You're doing really nice work! :)


//Peter



From Patrick.Georgi at secunet.com  Tue Feb  1 11:50:17 2011
From: Patrick.Georgi at secunet.com (Patrick Georgi)
Date: Tue, 1 Feb 2011 11:50:17 +0100
Subject: [coreboot] [PATCH] Move cmos.default handling to bootblock
Message-ID: <1296566674.6489.78.camel@linux-0a8x.site>


The cmos.default code wasn't actually used so far, due to an oversight
when forward-porting this feature from an old branch.

- Extend walkcbfs' use by factoring out the stage handling into C code.
- New sanitize_cmos() function that looks if CMOS data is invalid and
  cmos.default exists and if so overwrites CMOS with cmos.default data.
- Use sanitize_cmos() in both bootblock implementations.
- Drop the need to reboot after writing CMOS: CMOS wasn't used so far,
  so we can go on without a reboot.
- Remove the restriction that cmos.default only works on CAR boards.
- Always build in cmos.default support on boards that USE_OPTION_TABLE.

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

It's abuild tested and boot tested with emulation/qemu-x86.

With this patch CMOS recovery only works on bootblock enabled boards/chipsets.
Consider this an incentive to implement bootblock support where necessary :-)
---
 src/arch/x86/Kconfig                    |    6 -----
 src/arch/x86/Makefile.bootblock.inc     |    2 +-
 src/arch/x86/include/bootblock_common.h |   34 ++++++++++++++++++++++++++++--
 src/arch/x86/init/bootblock_normal.c    |    4 +++
 src/arch/x86/init/bootblock_simple.c    |    5 ++++
 src/arch/x86/lib/walkcbfs.S             |   10 +--------
 src/pc80/mc146818rtc_early.c            |   28 -------------------------
 7 files changed, 42 insertions(+), 47 deletions(-)

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From mr.nuke.me at gmail.com  Tue Feb  1 14:50:02 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Tue, 01 Feb 2011 15:50:02 +0200
Subject: [coreboot] [PATCH] add PC87382 to superiotool
In-Reply-To: <87ei7snhs3.fsf@begreifnix.stackframe.org>
References: <87ei7snhs3.fsf@begreifnix.stackframe.org>
Message-ID: <4D480F8A.7060305@gmail.com>

On 02/01/2011 12:58 PM, Sven Schnelle wrote:
> Hi List,
>
> this patch adds the NSC PC87382 to superiotool. It is a rather small
> 'superio' device, containing one Serial Port, one Infrared Port, GPIO
> and a Docking LPC switch. It is used in various Thinkpads.
>
> It adds 0x164e/0x16ef to the list of probed port for NSC chipsets, as
> Thinkpads are using this address pair.
>
> Signed-off-by: Sven Schnelle <svens at stackframe.org>
>
Acked-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>



From juhe at iki.fi  Tue Feb  1 14:54:39 2011
From: juhe at iki.fi (Juhana Helovuo)
Date: Tue, 01 Feb 2011 15:54:39 +0200
Subject: [coreboot] Tester devices [was: QA contribution]
In-Reply-To: <20110201125829.18404.qmail@stuge.se>
References: <AANLkTimaLyGgk2ZNQ7QhOWGxgUDPkyCJ=N3M8c9DnPLE@mail.gmail.com>	<20110130060515.GB19798@coreboot.org>	<AANLkTikwBeK=z-hAHN8yu3beX8jhdJzZvzSaoq8B0PBs@mail.gmail.com>	<20110130111604.4440.qmail@stuge.se>
	<4D47E8F4.3090403@iki.fi> <20110201125829.18404.qmail@stuge.se>
Message-ID: <4D48109F.6090604@iki.fi>

1.2.2011 14:58, Peter Stuge kirjoitti:
> Juhana Helovuo wrote:
>>> unit that can administer testing of one or even better several
>>> mainboards. I have plenty of design and implementation ideas if
>>> you'd like to go into that.
>>
>> I started building a tester device to hook up a mainboard into an
>> automated test host.
>
> Nice.

Thanks for your supportive comments. I think I was a bit unclear on some 
points, so you misunderstood some details.


>> The basic plan is as follows:
>> The host computer is connected to tester device via USB.
>
> This certainly makes the device itself simpler. But it requires
> *another* system to be monitoring all these devices.. I can't seem to
> let go of the thought that I would prefer a tester device to be
> connected directly to the internet, and work autonomously. Ethernet
> is simple enough with something like an LM3S6965 ARM. WiFi would be a
> nice option, but will also increase the unit cost..

That would be another design strategy. However, I wanted to make the 
tester device to be just a simple interface between USB and the target 
mainboard. That makes it easier to design and fabricate with hobbyist 
methods and budget.

A design constraint for me is e.g. using only components that I can 
solder into a self-designed, self-made PCB. Using small pitch SMD 
devices or a components requiring reflow soldering seems a bit too much 
right now.

Also the tester device firmware will be simpler this way. I discovered 
that flashrom utility alone is quite a complicated piece.


>> The tester is connected to the target mainboard so that it can take
>> control of the BIOS ROM and reprogram it regardless of the state of
>> the target mainbaord.
>
> Yes. A flash emulator would of course be ideal, but also requires
> some programmable logic, ie. either one more component, or a larger
> component. In some cases board size is critical, e.g. to fit a tester
> inside a tight case.

Flash emulator would be nice, but emulating a SPI flash ROM would 
require single clock cycle response times for ordinary read commands. 
There is very little time for the ROM from receiving the last address 
bit to start transmitting the data. I do not have a document at hand, 
but I recall that for the AMD SB7x0 this should be done at 16...33 MHz 
clock rate. Some SPI controllers could do it even faster, since many ROM 
chips are rated to operate up to 60 MHz or more.


>> The tester device can also connect to the serial port of the target
>> mainboard, so it can act as a serial-over-USB-device.
>
> Right. Either the tester just has a UART, or if it is networked then
> it will itself do the checkpointing. As for the USB device, it's
> fairly important to use a generic USB hardware. The ATmega U chips

I am currently working with AT90USB162. The choice was also influenced 
by easy availability and ease of soldering.


>> The tester also has two FET switches for controlling the reset and
>> ATX power buttons on the target mainboard.
>
> Yep. I've also been thinking that the power good signal could be
> used. One problem with FETs is that they must be plugged in to the
> mainboard the right way. It would be significantly simpler to use the
> device if it had a solid state switch instead, but that's also more
> expensive.

The FET switch device I am using is this:
http://focus.ti.com/docs/prod/folders/print/sn74cbt3306.html

I believe it should work with the terminals plugged either way around. 
It should also work regardless of the voltage used in the mainboard 
switch sensing pins. E.g. in my test mainbaord the reset and atx power 
switch pins have different operating voltages (5V and 3.3V).

>> The actual AC power control of the target mainboard is not included
>> and should be done by another device, such as this:
>> http://www.gembird.nl/default.aspx?op=products&op2=item&id=3234
>
> Do you know where these units can be purchased, with the various
> voltage ratings and power plugs that are needed around the world?

I haven't tried internationally. In Finland, Jimm's PC claims to have 
them in stock a total of 4 pcs.

http://www.jimms.fi/tuote/SIS-PMS

No idea about different plug types, but I believe this one would work at 
least in Finland, Sweden, and Germany.


> With USB connectivity I think it is important to really take
> advantage of the simplicity and efficiency of USB, rather than
> emulating a serial port on top of it. Also, having a serial port over
> USB both for target connectivity, *and* for flash programming, is IMO
> unneccssarily confusing. For the flashing we will simply implement
> the serprog protocol properly using native USB concepts. It should be
> very easy.

Yes, communication from flashrom program to SPI ROM should go over 
native USB, no serial emulation needed.

I used serial port only for testing that I can actually talk to the SPI 
ROM from the microcontroller. The test setup was based on Arduino Uno, 
which can do only serial-over-USB.


Best regards,
Juhana Helovuo




From peter at stuge.se  Tue Feb  1 15:56:26 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 1 Feb 2011 15:56:26 +0100
Subject: [coreboot] Tester devices [was: QA contribution]
In-Reply-To: <4D48109F.6090604@iki.fi>
References: <AANLkTimaLyGgk2ZNQ7QhOWGxgUDPkyCJ=N3M8c9DnPLE@mail.gmail.com>
	<20110130060515.GB19798@coreboot.org>
	<AANLkTikwBeK=z-hAHN8yu3beX8jhdJzZvzSaoq8B0PBs@mail.gmail.com>
	<20110130111604.4440.qmail@stuge.se> <4D47E8F4.3090403@iki.fi>
	<20110201125829.18404.qmail@stuge.se> <4D48109F.6090604@iki.fi>
Message-ID: <20110201145626.16399.qmail@stuge.se>

Juhana Helovuo wrote:
> Thanks for your supportive comments. I think I was a bit unclear on
> some points, so you misunderstood some details.

I just have a few different design ideas. :)


>> I can't seem to let go of the thought that I would prefer a tester
>> device to be connected directly to the internet
>
> That would be another design strategy.

Yes certainly.


> However, I wanted to make the tester device to be just a simple
> interface between USB and the target mainboard. That makes it
> easier to design and fabricate with hobbyist methods and budget.

Yes indeed! I think both approaches are equally useful. Some will
prefer to buy a device, and some, who have the ability, may prefer
to build their own.


> A design constraint for me is e.g. using only components that I can
> solder into a self-designed, self-made PCB. Using small pitch SMD
> devices or a components requiring reflow soldering seems a bit too
> much right now.

I understand. One thing that makes this design constraint a bit
tricky is that everyone has different equipment and ability here, but
I agree that no smaller than SO components would make the build very
accessible.


> Also the tester device firmware will be simpler this way.

Even if the device is doing a bit more the task is pretty simple, so
firmware would in any case be manageable I think.


> I discovered that flashrom utility alone is quite a complicated piece.

Ok. I haven't followed it for a good while.


> Flash emulator would be nice, but emulating a SPI flash ROM would
> require single clock cycle response times for ordinary read
> commands. There is very little time for the ROM from receiving the
> last address bit to start transmitting the data.

Yep, an emulator should be SRAM backed.


> I do not have a document at hand, but I recall that for the AMD
> SB7x0 this should be done at 16...33 MHz clock rate. Some SPI
> controllers could do it even faster, since many ROM chips are rated
> to operate up to 60 MHz or more.

I think in practise not much more than 16MHz is used, even though
some chips go up to 75 or 90.


>> ATmega U chips
>
> I am currently working with AT90USB162.

All right. With QFP on the table there's suddenly a whole lot more
possibilities for the design.


> The choice was also influenced by easy availability and ease of
> soldering.

Right. I've understood that Atmel are having some difficulties
shipping the U series.


>> One problem with FETs is that they must be plugged in to the
>> mainboard the right way.
..
>> significantly simpler to use .. if it had a solid state switch
>> instead,
>
> The FET switch device I am using is this:
> http://focus.ti.com/docs/prod/folders/print/sn74cbt3306.html
>
> I believe it should work with the terminals plugged either way
> around. It should also work regardless of the voltage used in the
> mainboard switch sensing pins. E.g. in my test mainbaord the reset
> and atx power switch pins have different operating voltages (5V and
> 3.3V).

A switch like that should indeed work perfectly, and the price is
right. Sorry, I was thinking of a discrete FET.


>>> http://www.gembird.nl/default.aspx?op=products&op2=item&id=3234
>>
>> Do you know where these units can be purchased, with the various
>> voltage ratings and power plugs that are needed around the world?
>
> I haven't tried internationally. In Finland, Jimm's PC claims to
> have them in stock a total of 4 pcs.
>
> http://www.jimms.fi/tuote/SIS-PMS
>
> No idea about different plug types, but I believe this one would
> work at least in Finland, Sweden, and Germany.

Since coreboot is very much an international project I think we'll
have to spend some effort on supporting various types of these power
switches.


>> we will simply implement the serprog protocol properly using
>> native USB concepts. It should be very easy.
>
> Yes, communication from flashrom program to SPI ROM should go over
> native USB, no serial emulation needed.

Let's look at designing that protocol. Are you on IRC?


> I used serial port only for testing that I can actually talk to the
> SPI ROM from the microcontroller.

Yup.


> The test setup was based on Arduino Uno, which can do only
> serial-over-USB.

Actually the Uno has an ATmega U for the USB interface, with firmware
released, specifically so that it can be reprogrammed with different
descriptors and make better use of USB. It requires a standalone AVR
programmer though, and is beyond the level of many Arduino users, so
it hasn't really taken off..


OK, so.. Do you like svn or git? Let's set up a repository or two
for this work.


//Peter



From svens at stackframe.org  Tue Feb  1 16:20:51 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Feb 2011 16:20:51 +0100
Subject: [coreboot] [PATCH] Add PC87382 support
Message-ID: <87aaifok6k.fsf@begreifnix.stackframe.org>

Hi List,

this patch adds support for NSC PC87382 Super I/O. IT is
used in many Lenovo Notebooks as Docking LPC Switch.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
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From svens at stackframe.org  Tue Feb  1 16:23:24 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Feb 2011 16:23:24 +0100
Subject: [coreboot] [PATCH] Add PC87392 support
Message-ID: <8762t3ok2b.fsf@begreifnix.stackframe.org>

Hi List,

this patch adds support for the NSC PC87392 Super I/O. It is
used in Lenovo Docking Stations as Super I/O chip.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
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From svens at stackframe.org  Tue Feb  1 16:28:52 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Feb 2011 16:28:52 +0100
Subject: [coreboot] [PATCH] Add missing Makefile.inc change for Lenovo PMH7
Message-ID: <871v3rojt7.fsf@begreifnix.stackframe.org>

Hi List,

my commit in r6325 missed a src/ec/Makefile.inc change.
Lets add it and make the buildsystem happy.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
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From patrick at georgi-clan.de  Tue Feb  1 17:45:03 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 01 Feb 2011 17:45:03 +0100
Subject: [coreboot] a question about reset16.lds
In-Reply-To: <AANLkTikkEg62XVUj65zDeGa3+BjxP8FHSYPVVh4b=jLg@mail.gmail.com>
References: <AANLkTikkEg62XVUj65zDeGa3+BjxP8FHSYPVVh4b=jLg@mail.gmail.com>
Message-ID: <4D48388F.3020006@georgi-clan.de>

Am 01.02.2011 12:46, schrieb ali hagigat:
> SECTIONS {
> 	/* Trigger an error if I have an unuseable start address */
> 	_bogus = ASSERT(_start>= 0xffff0000, "_start too low. Please
> decrease CONFIG_ROM_IMAGE_SIZE");
> 	_ROMTOP = 0xfffffff0;
> 	. = _ROMTOP;
> 	.reset . : {
> 		*(.reset)
> 		. = 15 ;
> 		BYTE(0x00);
> 	}
> }
> ------------------------------------------------------------------
> What does (.=15;) mean? It seems a mistake! and can be: . = .+1;
. = 15; means "set the location pointer to 15". With the byte that's 
written right after that, this means that .reset is exactly 16 bytes.
If it's less, ". = 15" pads the section to be larger, if it would have 
to be larger, ". = 15" makes the linker fail (because the location 
pointer must not go backwards).

I guess that also answers why ". = .+1" is no adequate substitute.


Patrick



From svn at coreboot.org  Tue Feb  1 20:19:54 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Feb 2011 20:19:54 +0100
Subject: [coreboot] [commit] r6326 - trunk/src/ec
Message-ID: <E1PkLla-00043M-5Q@ra.coresystems.de>

Author: oxygene
Date: Tue Feb  1 20:19:53 2011
New Revision: 6326
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6326

Log:
Properly add Lenovo EC to build

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/src/ec/Makefile.inc

Modified: trunk/src/ec/Makefile.inc
==============================================================================
--- trunk/src/ec/Makefile.inc	Tue Feb  1 11:44:26 2011	(r6325)
+++ trunk/src/ec/Makefile.inc	Tue Feb  1 20:19:53 2011	(r6326)
@@ -1 +1,2 @@
 subdirs-$(CONFIG_EC_ACPI) += acpi
+subdirs-y += lenovo



From svens at stackframe.org  Tue Feb  1 16:20:51 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Feb 2011 16:20:51 +0100
Subject: [coreboot] [PATCH v2] Add PC87382 support
Message-ID: <86aaif1mzy.fsf@stackframe.org>

Hi List,

this patch adds support for NSC PC87382 Super I/O. It is
used in many Lenovo Notebooks as Docking LPC Switch.

v2 because of:

- The patch added some empty files
- missing newlines in Kconfig and Makefile.inc
- chip.h missed uart8250.h include
- add the Kconfig option in sorted order

Thanks to idler on irc for pointing that out.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
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From svens at stackframe.org  Tue Feb  1 16:23:24 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Feb 2011 16:23:24 +0100
Subject: [coreboot] [PATCH v2] Add PC87392 support
Message-ID: <867hdj1mw7.fsf@stackframe.org>

Hi List,

this patch adds support for the NSC PC87392 Super I/O. It is
used in Lenovo Docking Stations as Super I/O chip.

v2 because of:

- The patch added some empty files
- missing newlines in Kconfig and Makefile.inc
- add the Kconfig option in sorted order

Thanks to idwer on irc for pointing that out.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
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From juhe at iki.fi  Wed Feb  2 09:25:52 2011
From: juhe at iki.fi (Juhana Helovuo)
Date: Wed, 02 Feb 2011 10:25:52 +0200
Subject: [coreboot] Tester devices [was: QA contribution]
In-Reply-To: <4D48109F.6090604@iki.fi>
References: <AANLkTimaLyGgk2ZNQ7QhOWGxgUDPkyCJ=N3M8c9DnPLE@mail.gmail.com>	<20110130060515.GB19798@coreboot.org>	<AANLkTikwBeK=z-hAHN8yu3beX8jhdJzZvzSaoq8B0PBs@mail.gmail.com>	<20110130111604.4440.qmail@stuge.se>	<4D47E8F4.3090403@iki.fi>
	<20110201125829.18404.qmail@stuge.se> <4D48109F.6090604@iki.fi>
Message-ID: <4D491510.1010801@iki.fi>

[ Note: There seems to be something wrong with mailing list delivery. I 
did not receive this Peter's latest message at all, but found it in the 
mailing list archive instead. Other coreboot lists messages have arrived 
to my inbox after that. ]

Peter Stuge wrote:

>> Flash emulator would be nice, but emulating a SPI flash ROM would
>> require single clock cycle response times for ordinary read
>> commands. There is very little time for the ROM from receiving the
>> last address bit to start transmitting the data.
>
> Yep, an emulator should be SRAM backed.

True, and additionally the controller between SPI and SRAM has to be 
able to react very quickly, which would mean using an FPGA or similar.

A microcontroller would have to have quite a high frequency to be able 
to react to a command within 1 cycle, even at 16 MHz.


> All right. With QFP on the table there's suddenly a whole lot more
> possibilities for the design.

Actully I was surprised myself how good the result with QFP-32 package 
was. However, that is already quite near the limit of my current skills 
and tools.


> OK, so.. Do you like svn or git? Let's set up a repository or two
> for this work.

Good idea! I suppose git would do better for this job, since I expect 
that the development is quite decentralized. Right now I have only the 
prototype board schematics and layout, but I suppose that is already 
better than nothing. Do have a good home for a git repository available?


Best regards,
Juhana Helovuo




From Joseph.Kellermann at heitec.de  Wed Feb  2 13:08:36 2011
From: Joseph.Kellermann at heitec.de (Joseph Kellermann)
Date: Wed, 2 Feb 2011 12:08:36 +0000
Subject: [coreboot] Moved 'pci_set_subsystem' to a weak function:
	Support for Siemens Mainboard
In-Reply-To: <1295960041.2414.47.camel@linux-0a8x.site>
References: <ADF72474DB94FA47B566A9574D0ECA26038ACD4D@MX1.heitec.net> ,
	<1295954189.2414.23.camel@linux-0a8x.site><ADF72474DB94FA47B566A9574D0ECA26038ACDC6@MX1.heitec.net>
	<1295958299.2414.39.camel@linux-0a8x.site>,
	<1295960041.2414.47.camel@linux-0a8x.site>
Message-ID: <ADF72474DB94FA47B566A9574D0ECA260FC880AE@MX1.heitec.net>

Patrick,

could you commit this patch ?

Regards,
Joseph

________________________________________
Von: Georgi, Patrick [Patrick.Georgi at secunet.com]
Gesendet: Dienstag, 25. Januar 2011 13:54
Bis: Joseph Kellermann
Cc: coreboot at coreboot.org
Betreff: Re: [coreboot] Moved 'pci_set_subsystem' to a weak function: Support for Siemens Mainboard

Am Dienstag, den 25.01.2011, 13:24 +0100 schrieb Georgi, Patrick:
> I'm not quite sure if using weak functions to wrap the subsystem
> CONFIG_* values is actually the right approach, I'll work on a patch to
> discuss.
Here it is.
I tested it by providing a mainboard_pci_subsystem_vendor_id for my
board in its mainboard.c which returned a different constant value -
this was picked up by properly and reported on boot.
mainboard_pci_subsystem_device_id will work just the same.

Joseph, will this suffice to help you implement your requirement?

Everyone, any opinion on the design?
My main issue is that other code can still use the CONFIG_* values
directly. Maybe our lint mechanism should look for that?
Any other issues you have with this?

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>


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From seppk at arcor.de  Wed Feb  2 18:39:07 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Wed, 02 Feb 2011 18:39:07 +0100
Subject: [coreboot] errata#89 patch for Family 0Fh Prozessors
Message-ID: <4D4996BB.7080105@arcor.de>

This patch fixes a potential system hang.
Don't know why this patch isn't included if 'CONFIG_K8_REV_F_SUPPORT == 1'.

Signed-off-by: Josef Kellermann  <mailto://seppk at arcor.de><seppk at arcor.de>  <mailto://seppk at arcor.de>

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From svn at coreboot.org  Wed Feb  2 19:32:47 2011
From: svn at coreboot.org (coreboot)
Date: Wed, 02 Feb 2011 18:32:47 -0000
Subject: [coreboot] #174: Unable to boot from qemu-kvm -- seems to be a cbfs
 problem
Message-ID: <060.648700c6f1026614c71f90e09c54f4b1@coreboot.org>

#174: Unable to boot from qemu-kvm -- seems to be a cbfs problem
-------------------------------------+-------------------------------------
    Reporter:  czw[+]660[+]@?        |         Owner:  stepan@?
        Type:  defect                |        Status:  new
    Priority:  major                 |     Milestone:
   Component:  coreboot              |      Keywords:
Dependencies:                        |  Patch Status:  there is no patch
-------------------------------------+-------------------------------------
 Hello,

 I was the opener of ticket 173, so I'm still using gcc 4.4.3, and now
 testing with qemu-kvm version 0.12.5, with (about) the following command:

 [[BR]]
 {{{
 /usr/local/bin/qemu-system-x86_64 -monitor stdio -smp
 1,cores=1,threads=1,sockets=1 -cpu phenom -soundhw ac97 -k it -kvm-shadow-
 memory 1 -m 512 -no-fd-bootchk -show-cursor -drive
 file="/mnt/pdc_a0p1/qemu/disk0",if=scsi,bus=0,unit=0,media=disk -drive
 file="/mnt/pdc_a0p1/qemu/disk1",if=scsi,bus=1,unit=0,media=disk -drive
 file="/mnt/pdc_a0p1/qemu/disk2",if=scsi,bus=2,unit=0,media=disk -net none
 -usb -usbdevice tablet -startdate 2009-01-20T14:30:00 -name "test" -cdrom
 path/to/image.iso -fda /mnt/pdc_a0p1/qemu/fd -hda /mnt/pdc_a0p1/qemu/ide
 -L /mnt/pdc_a0p1/qemu/bios -bios coreboot_version-seabios_version.bin
 -boot order=adc,menu=on -vga cirrus -serial file:path/to/coreboot_version-
 seabios_version.log
 }}}

 (configured from aqemu)

 [[BR]]
 path/to/image.iso is a bootable dvd image with freedos or /dev/cdrom (I
 get similar results with a win xp setup disk/image) - this is also the
 only bootable emulated drive; path/to/coreboot_version-seabios_version.log
 is a log of the serial output of coreboot (see attached files).

 The above works fine with both qemu's bios.bin and pre-built coreboot v2
 r4917 + seabios 9eebe66a9978165cfa91f2266c97fa5d0aa6ef2e, 2009-11-04, as
 retrieved from
 [http://www.coreboot.org/images/6/6a/Qemu_coreboot_seabios.zip] which
 works with both qemu's provided vgabios-cirrus.bin and your patched
 version - from [http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip] -
 excluding a seabios or qemu-kvm specific problem.

 I can also exclude any problem related to my build environment (as well as
 my qemu-kvm) because I've been able to download, build and boot coreboot
 r4917 + the above seabios version with a correctly modified src/config.h,
 as per

 [[BR]]
 {{{
 #define CONFIG_COREBOOT 1
 #define CONFIG_DEBUG_SERIAL 1
 #define CONFIG_COREBOOT_FLASH 1
 #define CONFIG_OPTIONROMS_DEPLOYED 0
 #define CONFIG_VGAHOOKS 1
 }}}

 [[BR]]
 Now to the core of the problem: when runnig qemu-kvm it hangs after
 displaying a vga specific message (see attached jpeg), and serial log
 files show a message like the following:

 [[BR]]
 {{{
 CBFS:  Could not find file fallback/payload
 Boot failed.
 }}}

 (last message - see attached file for full log)

 [[BR]]
 Of course, fallback/payload is therein (see attached coreboot-layout.txt
 for a cbfstool print result)

 I'm testing both the stable trunk (pre-6321 but correcting the issue from
 ticket 173) and revision 6325 of coreboot, both with latest stable seabios
 (0.6.1.3) and the old one used in your qemu test (v2) build, added as
 external elf payload, with or without lzma compression, all the rest with
 default configuration values (see attached files for full details).

 Regards

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/174>
coreboot <http://www.coreboot.org/>


From mr.nuke.me at gmail.com  Wed Feb  2 20:11:08 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Feb 2011 21:11:08 +0200
Subject: [coreboot] errata#89 patch for Family 0Fh Prozessors
In-Reply-To: <4D4996BB.7080105@arcor.de>
References: <4D4996BB.7080105@arcor.de>
Message-ID: <4D49AC4C.9030009@gmail.com>

Erratum 89 is already handled on line 390:

if (!is_cpu_pre_b3()) {

    /* Erratum 89 ... */
    msr = rdmsr(NB_CFG_MSR);
    msr.lo |= 1 << 3;

If this is also needed when CONFIG_K8_REV_F_SUPPORT == 1, then we should
move the existing one out of the
#if CONFIG_K8_REV_F_SUPPORT == 0
so it gets executed in both cases, as opposed to duplicating it.

Alex

On 02/02/2011 07:39 PM, Josef Kellermann wrote:
> This patch fixes a potential system hang.
> Don't know why this patch isn't included if 'CONFIG_K8_REV_F_SUPPORT == 1'.
> 
> Signed-off-by: Josef Kellermann  <mailto://seppk at arcor.de><seppk at arcor.de> <mailto://seppk at arcor.de>
> 




From mr.nuke.me at gmail.com  Wed Feb  2 20:23:46 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Feb 2011 21:23:46 +0200
Subject: [coreboot] [PATCH] Add license headers for AMD family Fh
Message-ID: <4D49AF42.6060503@gmail.com>

See patch.

Alex
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From stefan.reinauer at coreboot.org  Wed Feb  2 20:36:03 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 2 Feb 2011 20:36:03 +0100
Subject: [coreboot] [PATCH] Add license headers for AMD family Fh
In-Reply-To: <4D49AF42.6060503@gmail.com>
References: <4D49AF42.6060503@gmail.com>
Message-ID: <20110202193603.GA21924@coreboot.org>

* Alex G. <mr.nuke.me at gmail.com> [110202 20:23]:
> Add GPL license headers to all files in src/cpu/amd/model_fxx
> (except microcode).
 
> Signed-off-by Alexandru Gagniuc <mr.nuke.me at gmail.com>
> Acked-by Alexandru Gagniuc <mr.nuke.me at gmail.com> Trivial

Not trivial at all, but legally kind of troublesome. Got to NACK this,
sorry.

> +# Copyright (C) The coreboot project

We can not accept generic copyright to the coreboot project, as it is
not a legal entity.

> +# This program is free software; you can redistribute it and/or modify
> +# it under the terms of the GNU General Public License as published by
> +# the Free Software Foundation; either version 2 of the License, or
> +# (at your option) any later version.

coreboot is GPLv2, not GPLv2+

Stefan





From seppk at arcor.de  Wed Feb  2 20:06:25 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Wed, 02 Feb 2011 20:06:25 +0100
Subject: [coreboot] Different register numbers to program subsystem ids
Message-ID: <4D49AB31.7030007@arcor.de>

The default 'pci_set_subsystem' sets the subvendor/device id register #0x2c. In fact for a few devices in the RS690 the register is 0x4c respectively 0x50. Moved the default set_subsystem implementation to chipset specific.


Signed-off-by: Josef Kellermann<seppk at arcor.de>  <mailto://seppk at arcor.de>




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From mr.nuke.me at gmail.com  Wed Feb  2 20:39:27 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Feb 2011 21:39:27 +0200
Subject: [coreboot] [PATCH] Add license headers for AMD family Fh
In-Reply-To: <20110202193603.GA21924@coreboot.org>
References: <4D49AF42.6060503@gmail.com> <20110202193603.GA21924@coreboot.org>
Message-ID: <4D49B2EF.9030602@gmail.com>

> Not trivial at all, but legally kind of troublesome. Got to NACK this,
> sorry.
> 
No problem


> coreboot is GPLv2, not GPLv2+
> 

http://www.coreboot.org/Development_Guidelines says GPLv2+.
So which is the correct license?

Alex



From patrick at georgi-clan.de  Wed Feb  2 20:50:47 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 02 Feb 2011 20:50:47 +0100
Subject: [coreboot] [PATCH] Add license headers for AMD family Fh
In-Reply-To: <4D49B2EF.9030602@gmail.com>
References: <4D49AF42.6060503@gmail.com> <20110202193603.GA21924@coreboot.org>
	<4D49B2EF.9030602@gmail.com>
Message-ID: <4D49B597.4090303@georgi-clan.de>

Am 02.02.2011 20:39, schrieb Alex G.:
>> coreboot is GPLv2, not GPLv2+
> http://www.coreboot.org/Development_Guidelines says GPLv2+.
> So which is the correct license?
We have some GPLv2 and some GPLv2+ files, so the combined work is GPLv2.
As for the files that you added licensing information to, the licensing
is really a matter of the authors.
The only license we can safely apply is the GPLv2.


Patrick



From mr.nuke.me at gmail.com  Wed Feb  2 20:51:52 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Feb 2011 21:51:52 +0200
Subject: [coreboot] [PATCH] Add license headers for AMD family Fh
In-Reply-To: <4D49B597.4090303@georgi-clan.de>
References: <4D49AF42.6060503@gmail.com>
	<20110202193603.GA21924@coreboot.org>	<4D49B2EF.9030602@gmail.com>
	<4D49B597.4090303@georgi-clan.de>
Message-ID: <4D49B5D8.4050006@gmail.com>

On 02/02/2011 09:50 PM, Patrick Georgi wrote:
> Am 02.02.2011 20:39, schrieb Alex G.:
>>> coreboot is GPLv2, not GPLv2+
>> http://www.coreboot.org/Development_Guidelines says GPLv2+.
>> So which is the correct license?
> We have some GPLv2 and some GPLv2+ files, so the combined work is GPLv2.
> As for the files that you added licensing information to, the licensing
> is really a matter of the authors.
> The only license we can safely apply is the GPLv2.
> 
Thanks! That sheds some light on the matter. :)

Alex



From seppk at arcor.de  Wed Feb  2 21:17:20 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Wed, 02 Feb 2011 21:17:20 +0100
Subject: [coreboot] errata#89 patch for Family 0Fh Prozessors
In-Reply-To: <4D49AC4C.9030009@gmail.com>
References: <4D4996BB.7080105@arcor.de> <4D49AC4C.9030009@gmail.com>
Message-ID: <4D49BBD0.1040202@arcor.de>

Am 02.02.2011 20:11, schrieb Alex G.:
> Erratum 89 is already handled on line 390:
>
> if (!is_cpu_pre_b3()) {
>
>      /* Erratum 89 ... */
>      msr = rdmsr(NB_CFG_MSR);
>      msr.lo |= 1<<  3;
>
> If this is also needed when CONFIG_K8_REV_F_SUPPORT == 1, then we should
> move the existing one out of the
> #if CONFIG_K8_REV_F_SUPPORT == 0
> so it gets executed in both cases, as opposed to duplicating it.
>
> Alex
>
> On 02/02/2011 07:39 PM, Josef Kellermann wrote:
>> This patch fixes a potential system hang.
>> Don't know why this patch isn't included if 'CONFIG_K8_REV_F_SUPPORT == 1'.
>>
>> Signed-off-by: Josef Kellermann<mailto://seppk at arcor.de><seppk at arcor.de>  <mailto://seppk at arcor.de>
>>
>
Ok,
now it gets executed in both cases.

Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>
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From r.marek at assembler.cz  Wed Feb  2 22:20:28 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 02 Feb 2011 22:20:28 +0100
Subject: [coreboot] errata#89 patch for Family 0Fh Prozessors
In-Reply-To: <4D49AC4C.9030009@gmail.com>
References: <4D4996BB.7080105@arcor.de> <4D49AC4C.9030009@gmail.com>
Message-ID: <4D49CA9C.8000402@assembler.cz>

While we are at it. I'm attaching some very old patch (r2978 ;)
which contains some errata fixes too, if you have some spare time please try to 
check if it is correct.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>


Thanks,
Rudolf

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From mr.nuke.me at gmail.com  Wed Feb  2 22:55:43 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Feb 2011 23:55:43 +0200
Subject: [coreboot] errata#89 patch for Family 0Fh Prozessors
In-Reply-To: <4D49BBD0.1040202@arcor.de>
References: <4D4996BB.7080105@arcor.de> <4D49AC4C.9030009@gmail.com>
	<4D49BBD0.1040202@arcor.de>
Message-ID: <4D49D2DF.6040902@gmail.com>

That looks way better. :)

Acked-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>

On 02/02/2011 10:17 PM, Josef Kellermann wrote:
> Am 02.02.2011 20:11, schrieb Alex G.:
>> Erratum 89 is already handled on line 390:
>>
>> if (!is_cpu_pre_b3()) {
>>
>>     /* Erratum 89 ... */
>>     msr = rdmsr(NB_CFG_MSR);
>>     msr.lo |= 1 << 3;
>>
>> If this is also needed when CONFIG_K8_REV_F_SUPPORT == 1, then we should
>> move the existing one out of the
>> #if CONFIG_K8_REV_F_SUPPORT == 0
>> so it gets executed in both cases, as opposed to duplicating it.
>>
>> Alex
>>
>> On 02/02/2011 07:39 PM, Josef Kellermann wrote:
>>> This patch fixes a potential system hang.
>>> Don't know why this patch isn't included if 'CONFIG_K8_REV_F_SUPPORT == 1'.
>>>
>>> Signed-off-by: Josef Kellermann  <mailto://seppk at arcor.de><seppk at arcor.de> <mailto://seppk at arcor.de>
>>>
>>
> Ok,
> now it gets executed in both cases.
> 
> Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>
> 




From mr.nuke.me at gmail.com  Wed Feb  2 23:02:05 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 03 Feb 2011 00:02:05 +0200
Subject: [coreboot] errata#89 patch for Family 0Fh Prozessors
In-Reply-To: <4D49CA9C.8000402@assembler.cz>
References: <4D4996BB.7080105@arcor.de> <4D49AC4C.9030009@gmail.com>
	<4D49CA9C.8000402@assembler.cz>
Message-ID: <4D49D45D.8080907@gmail.com>

src/northbridge/amd/amdk8/coherent_ht_car.c was renamed to someting else
since then (I wasn't around then), and the patch can no longer be applied.

Can you please check this?

Alex

On 02/02/2011 11:20 PM, Rudolf Marek wrote:
> While we are at it. I'm attaching some very old patch (r2978 ;)
> which contains some errata fixes too, if you have some spare time please
> try to check if it is correct.
> 
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
> 
> 
> Thanks,
> Rudolf
> 




From svn at coreboot.org  Thu Feb  3 00:49:42 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Feb 2011 00:49:42 +0100
Subject: [coreboot] [commit] r6327 - trunk/util/superiotool
Message-ID: <E1PkmSE-0006ic-6q@ra.coresystems.de>

Author: uwe
Date: Thu Feb  3 00:49:41 2011
New Revision: 6327
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6327

Log:
Add detection/dump support for the NSC PC87382.

It is a rather small 'Super I/O' device, containing a serial port, IR,
GPIO, and a Docking LPC switch. It is used in various Thinkpads.

Add 0x164e/0x16ef to the list of probed ports for NSC chips, as
Thinkpads are using this address pair.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/util/superiotool/nsc.c
   trunk/util/superiotool/superiotool.h

Modified: trunk/util/superiotool/nsc.c
==============================================================================
--- trunk/util/superiotool/nsc.c	Tue Feb  1 20:19:53 2011	(r6326)
+++ trunk/util/superiotool/nsc.c	Thu Feb  3 00:49:41 2011	(r6327)
@@ -305,7 +305,25 @@
 			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT},
 			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}},
 		{EOT}}},
-
+	{0xf4, "PC87382", {
+		{NOLDN, NULL,
+			{0x20,0x21,0x22,0x26,0x27,0x29,EOT},
+			{0xf4,0x11,0x63,0x00,0x00,0x00,EOT}},
+		{0x02, "IR",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}},
+		{0x03, "COM1",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}},
+		{0x07, "GPIO",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,
+			 0xf2,EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,MISC,
+			 0x01,EOT}},
+		{0x19, "Docking LPC switch",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT},
+			{0x00,0x00,0x00,0x00,0x00,0x04,0x04,EOT}},
+		{EOT}}},
 	/* SID[7..0]: family, SRID[7..5]: ID, SRID[4..0]: rev. */
 	{0xea, "PC8739x", {
 		{NOLDN, NULL,

Modified: trunk/util/superiotool/superiotool.h
==============================================================================
--- trunk/util/superiotool/superiotool.h	Tue Feb  1 20:19:53 2011	(r6326)
+++ trunk/util/superiotool/superiotool.h	Thu Feb  3 00:49:41 2011	(r6327)
@@ -223,7 +223,7 @@
 	{probe_idregs_fintek_alternative,	{0x2e, 0x4e, EOT}},
 	/* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */
 	{probe_idregs_ite,	{0x25e, 0x2e, 0x4e, 0x370, EOT}},
-	{probe_idregs_nsc,	{0x2e, 0x4e, 0x15c, EOT}},
+	{probe_idregs_nsc,	{0x2e, 0x4e, 0x15c, 0x164e, EOT}},
 	/* I/O pairs on Nuvoton EC chips can be configured by firmware in
 	 * addition to the following hardware strapping options. */
 	{probe_idregs_nuvoton, {0x164e, 0x2e, EOT}},



From uwe at hermann-uwe.de  Thu Feb  3 00:51:16 2011
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 3 Feb 2011 00:51:16 +0100
Subject: [coreboot] [PATCH] add PC87382 to superiotool
In-Reply-To: <87ei7snhs3.fsf@begreifnix.stackframe.org>
References: <87ei7snhs3.fsf@begreifnix.stackframe.org>
Message-ID: <20110202235116.GE9074@greenwood>

Hi,

On Tue, Feb 01, 2011 at 11:58:04AM +0100, Sven Schnelle wrote:
> this patch adds the NSC PC87382 to superiotool. It is a rather small
> 'superio' device, containing one Serial Port, one Infrared Port, GPIO
> and a Docking LPC switch. It is used in various Thinkpads.
> 
> It adds 0x164e/0x16ef to the list of probed port for NSC chipsets, as
> Thinkpads are using this address pair.
> 
> Signed-off-by: Sven Schnelle <svens at stackframe.org>

Thanks, committed as r6327 with minor whitespace and consistency
changes.


> +	{0xf4, "PC87382", {
> +		{ NOLDN, NULL,
> +			{ 0x20, 0x21, 0x22, 0x26, 0x27, 0x29, EOT },
> +			{ 0xf2, 0x11, 0x63, 0x00, 0x00, 0x00, EOT }},

I also changed the 0xf2 value for register 0x20 (chip ID) to 0xf4, that
was probably a typo.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Thu Feb  3 00:56:16 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Feb 2011 00:56:16 +0100
Subject: [coreboot] [commit] r6328 - trunk/src/ec/lenovo/pmh7
Message-ID: <E1PkmYa-0001iD-Hz@ra.coresystems.de>

Author: uwe
Date: Thu Feb  3 00:56:15 2011
New Revision: 6328
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6328

Log:
pmh7.[ch]: Add missing license headers.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/ec/lenovo/pmh7/pmh7.c
   trunk/src/ec/lenovo/pmh7/pmh7.h

Modified: trunk/src/ec/lenovo/pmh7/pmh7.c
==============================================================================
--- trunk/src/ec/lenovo/pmh7/pmh7.c	Thu Feb  3 00:49:41 2011	(r6327)
+++ trunk/src/ec/lenovo/pmh7/pmh7.c	Thu Feb  3 00:56:15 2011	(r6328)
@@ -1,9 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pnp.h>
 #include <stdlib.h>
-
 #include "pmh7.h"
 
 void pmh7_register_set_bit(int reg, int bit)
@@ -41,13 +59,13 @@
 static void enable_dev(device_t dev)
 {
 	struct resource *resource;
+
 	resource = new_resource(dev, EC_LENOVO_PMH7_INDEX);
 	resource->flags = IORESOURCE_IO | IORESOURCE_FIXED;
 	resource->base = EC_LENOVO_PMH7_BASE;
 	resource->size = 16;
 	resource->align = 5;
 	resource->gran = 5;
-
 }
 
 struct chip_operations ec_lenovo_pmh7_ops = {

Modified: trunk/src/ec/lenovo/pmh7/pmh7.h
==============================================================================
--- trunk/src/ec/lenovo/pmh7/pmh7.h	Thu Feb  3 00:49:41 2011	(r6327)
+++ trunk/src/ec/lenovo/pmh7/pmh7.h	Thu Feb  3 00:56:15 2011	(r6328)
@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #ifndef EC_LENOVO_PMH7_H
 #define EC_LENOVO_PMH7_H
 



From uwe at hermann-uwe.de  Thu Feb  3 00:58:27 2011
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 3 Feb 2011 00:58:27 +0100
Subject: [coreboot] [PATCH v2] Add Lenovo PMH7
In-Reply-To: <87k4hknkhr.fsf@begreifnix.stackframe.org>
References: <87k4hknkhr.fsf@begreifnix.stackframe.org>
Message-ID: <20110202235827.GF9074@greenwood>

On Tue, Feb 01, 2011 at 09:08:38AM +0100, Sven Schnelle wrote:
> this patch adds support for the Lenovo PMH7 (Power Management Hardware
> Hub) found in most recent (starting with X60/T60 AFAIK) Lenovo/IBM
> Laptops. Please ignore the previous version, as it missed the
> src/ec/Kconfig file.
> 
> Signed-off-by: Sven Schnelle <svens at stackframe.org>

Nice stuff (and already committed)! Please don't forget to add the usual
license header to all new source files though, thanks! I added some
for pmh7.[ch].


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Thu Feb  3 01:31:16 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Feb 2011 01:31:16 +0100
Subject: [coreboot] build service results for r6328
Message-ID: <E1Pkn6S-0000l2-5v@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "uwe" checked in revision 6328 to
the coreboot repository. This caused the following 
changes:

Change Log:
pmh7.[ch]: Add missing license headers.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of a-trend:atc-6220 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 has been broken
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Compilation of abit:be6-ii_v2_0 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:bimini_fam10 has been broken
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Compilation of amd:db800 has been broken
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Compilation of amd:dbm690t has been broken
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Compilation of amd:mahogany has been broken
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Compilation of amd:mahogany_fam10 has been broken
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Compilation of amd:norwich has been broken
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Compilation of amd:pistachio has been broken
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Compilation of amd:rumba has been broken
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Compilation of amd:serengeti_cheetah has been broken
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Compilation of amd:serengeti_cheetah_fam10 has been broken
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Compilation of amd:tilapia_fam10 has been broken
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Compilation of arima:hdama has been broken
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Compilation of artecgroup:dbe61 has been broken
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Compilation of asi:mb_5blgp has been broken
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Compilation of asi:mb_5blmp has been broken
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Compilation of asrock:939a785gmh has been broken
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Compilation of asus:a8n_e has been broken
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Compilation of asus:a8v-e_deluxe has been broken
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Compilation of asus:a8v-e_se has been broken
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Compilation of asus:m2n-e has been broken
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Compilation of asus:m2v has been broken
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Compilation of asus:m2v-mx_se has been broken
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Compilation of asus:m4a78-em has been broken
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Compilation of asus:m4a785-m has been broken
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Compilation of asus:mew-am has been broken
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Compilation of asus:mew-vm has been broken
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Compilation of asus:p2b has been broken
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Compilation of asus:p2b-d has been broken
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Compilation of asus:p2b-ds has been broken
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Compilation of asus:p2b-f has been broken
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Compilation of asus:p2b-ls has been broken
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Compilation of asus:p3b-f has been broken
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Compilation of axus:tc320 has been broken
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Compilation of azza:pt-6ibd has been broken
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Compilation of bcom:winnet100 has been broken
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Compilation of bcom:winnetp680 has been broken
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Compilation of biostar:m6tba has been broken
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Compilation of broadcom:blast has been broken
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Compilation of compaq:deskpro_en_sff_p600 has been broken
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Compilation of dell:s1850 has been broken
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Compilation of digitallogic:adl855pc has been broken
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Compilation of digitallogic:msm586seg has been broken
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Compilation of digitallogic:msm800sev has been broken
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Compilation of eaglelion:5bcm has been broken
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Compilation of ecs:p6iwp-fe has been broken
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Compilation of emulation:qemu-x86 has been broken
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Compilation of getac:p470 has been broken
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Compilation of gigabyte:ga-6bxc has been broken
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Compilation of gigabyte:ga-6bxe has been broken
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Compilation of gigabyte:ga_2761gxdk has been broken
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Compilation of gigabyte:m57sli has been broken
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Compilation of gigabyte:ma785gmt has been broken
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Compilation of gigabyte:ma78gm has been broken
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Compilation of hp:dl145_g1 has been broken
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Compilation of hp:dl145_g3 has been broken
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Compilation of hp:dl165_g6_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=dl165_g6_fam10&vendor=hp&num=2
Compilation of hp:e_vectra_p2706t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=e_vectra_p2706t&vendor=hp&num=2
Compilation of ibase:mb899 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=mb899&vendor=ibase&num=2
Compilation of ibm:e325 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=e325&vendor=ibm&num=2
Compilation of ibm:e326 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=e326&vendor=ibm&num=2
Compilation of iei:juki-511p has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=juki-511p&vendor=iei&num=2
Compilation of iei:kino-780am2-fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=kino-780am2-fam10&vendor=iei&num=2
Compilation of iei:nova4899r has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=nova4899r&vendor=iei&num=2
Compilation of iei:pcisa-lx-800-r10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=pcisa-lx-800-r10&vendor=iei&num=2
Compilation of intel:d810e2cb has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=d810e2cb&vendor=intel&num=2
Compilation of intel:d945gclf has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=d945gclf&vendor=intel&num=2
Compilation of intel:eagleheights has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=eagleheights&vendor=intel&num=2
Compilation of intel:jarrell has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=jarrell&vendor=intel&num=2
Compilation of intel:mtarvon has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=mtarvon&vendor=intel&num=2
Compilation of intel:truxton has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=truxton&vendor=intel&num=2
Compilation of intel:xe7501devkit has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=xe7501devkit&vendor=intel&num=2
Compilation of iwave:iWRainbowG6 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=iWRainbowG6&vendor=iwave&num=2
Compilation of iwill:dk8_htx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=dk8_htx&vendor=iwill&num=2
Compilation of iwill:dk8s2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=dk8s2&vendor=iwill&num=2
Compilation of iwill:dk8x has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=dk8x&vendor=iwill&num=2
Compilation of jetway:j7f24 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=j7f24&vendor=jetway&num=2
Compilation of jetway:pa78vm5 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=pa78vm5&vendor=jetway&num=2
Compilation of kontron:986lcd-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=986lcd-m&vendor=kontron&num=2
Compilation of kontron:kt690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=kt690&vendor=kontron&num=2
Compilation of lanner:em8510 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=em8510&vendor=lanner&num=2
Compilation of lippert:frontrunner has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=frontrunner&vendor=lippert&num=2
Compilation of lippert:hurricane-lx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=hurricane-lx&vendor=lippert&num=2
Compilation of lippert:literunner-lx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=literunner-lx&vendor=lippert&num=2
Compilation of lippert:roadrunner-lx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=roadrunner-lx&vendor=lippert&num=2
Compilation of lippert:spacerunner-lx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=spacerunner-lx&vendor=lippert&num=2
Compilation of mitac:6513wu has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=6513wu&vendor=mitac&num=2
Compilation of msi:ms6119 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6156 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ms6156&vendor=msi&num=2
Compilation of msi:ms6178 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ms6178&vendor=msi&num=2
Compilation of msi:ms7135 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ms7135&vendor=msi&num=2
Compilation of msi:ms7260 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ms7260&vendor=msi&num=2
Compilation of msi:ms9185 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ms9185&vendor=msi&num=2
Compilation of msi:ms9282 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ms9282&vendor=msi&num=2
Compilation of msi:ms9652_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ms9652_fam10&vendor=msi&num=2
Compilation of nec:powermate2000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=powermate2000&vendor=nec&num=2
Compilation of newisys:khepri has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=khepri&vendor=newisys&num=2
Compilation of nokia:ip530 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ip530&vendor=nokia&num=2
Compilation of nvidia:l1_2pvv has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=l1_2pvv&vendor=nvidia&num=2
Compilation of pcengines:alix1c has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=alix1c&vendor=pcengines&num=2
Compilation of pcengines:alix2d has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=alix2d&vendor=pcengines&num=2
Compilation of rca:rm4100 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=rm4100&vendor=rca&num=2
Compilation of roda:rk886ex has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=rk886ex&vendor=roda&num=2
Compilation of soyo:sy-6ba-plus-iii has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=sy-6ba-plus-iii&vendor=soyo&num=2
Compilation of sunw:ultra40 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ultra40&vendor=sunw&num=2
Compilation of supermicro:h8dme has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=h8dme&vendor=supermicro&num=2
Compilation of supermicro:h8dmr has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=h8dmr&vendor=supermicro&num=2
Compilation of supermicro:h8dmr_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=h8dmr_fam10&vendor=supermicro&num=2
Compilation of supermicro:h8qme_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=h8qme_fam10&vendor=supermicro&num=2
Compilation of supermicro:x6dai_g has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=x6dai_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=x6dhe_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=x6dhe_g2&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=x6dhr_ig&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=x6dhr_ig2&vendor=supermicro&num=2
Compilation of technexion:tim5690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=tim5690&vendor=technexion&num=2
Compilation of technexion:tim8690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=tim8690&vendor=technexion&num=2
Compilation of technologic:ts5300 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=tc7020&vendor=televideo&num=2
Compilation of thomson:ip1000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=ip1000&vendor=thomson&num=2
Compilation of traverse:geos has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=geos&vendor=traverse&num=2
Compilation of tyan:s1846 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s1846&vendor=tyan&num=2
Compilation of tyan:s2735 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2735&vendor=tyan&num=2
Compilation of tyan:s2850 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2850&vendor=tyan&num=2
Compilation of tyan:s2875 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2875&vendor=tyan&num=2
Compilation of tyan:s2880 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2880&vendor=tyan&num=2
Compilation of tyan:s2881 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2881&vendor=tyan&num=2
Compilation of tyan:s2882 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2882&vendor=tyan&num=2
Compilation of tyan:s2885 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2885&vendor=tyan&num=2
Compilation of tyan:s2891 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2891&vendor=tyan&num=2
Compilation of tyan:s2892 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2892&vendor=tyan&num=2
Compilation of tyan:s2895 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2895&vendor=tyan&num=2
Compilation of tyan:s2912 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2912&vendor=tyan&num=2
Compilation of tyan:s2912_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s2912_fam10&vendor=tyan&num=2
Compilation of tyan:s4880 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s4880&vendor=tyan&num=2
Compilation of tyan:s4882 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s4882&vendor=tyan&num=2
Compilation of via:epia has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=epia&vendor=via&num=2
Compilation of via:epia-cn has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=epia-cn&vendor=via&num=2
Compilation of via:epia-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=epia-m&vendor=via&num=2
Compilation of via:epia-m700 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=epia-m700&vendor=via&num=2
Compilation of via:epia-n has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=epia-n&vendor=via&num=2
Compilation of via:pc2500e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=pc2500e&vendor=via&num=2
Compilation of via:vt8454c has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=vt8454c&vendor=via&num=2
Compilation of winent:pl6064 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=pl6064&vendor=winent&num=2
Compilation of wyse:s50 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=s50&vendor=wyse&num=2


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From uwe at hermann-uwe.de  Thu Feb  3 02:23:40 2011
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 3 Feb 2011 02:23:40 +0100
Subject: [coreboot] build service results for r6328
In-Reply-To: <E1Pkn6S-0000l2-5v@ra.coresystems.de>
References: <E1Pkn6S-0000l2-5v@ra.coresystems.de>
Message-ID: <20110203012340.GG9074@greenwood>

On Thu, Feb 03, 2011 at 01:31:16AM +0100, repository service wrote:
> Change Log:
> pmh7.[ch]: Add missing license headers.
[...] 
> Build Log:
> Compilation of a-trend:atc-6220 has been broken
> See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6328&device=atc-6220&vendor=a-trend&num=2

I think/hope this is unrelated to my patch.

    CC         coreboot_ram
  Prepping out/bios.bin
Error!  Code does not end at 0x100000 (got 0xff700)
make[2]: *** [out/bios.bin] Error 1
make[1]: *** [seabios] Error 2
make: *** [seabios] Error 2


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Thu Feb  3 05:46:43 2011
From: svn at coreboot.org (coreboot)
Date: Thu, 03 Feb 2011 04:46:43 -0000
Subject: [coreboot] #174: Unable to boot from qemu-kvm -- seems to be a
 cbfs problem
In-Reply-To: <060.648700c6f1026614c71f90e09c54f4b1@coreboot.org>
References: <060.648700c6f1026614c71f90e09c54f4b1@coreboot.org>
Message-ID: <075.25202cbfabce334caf039bf8b977eae4@coreboot.org>

#174: Unable to boot from qemu-kvm -- seems to be a cbfs problem
-------------------------------------+-------------------------------------
    Reporter:  czw[+]660[+]@?        |         Owner:  stepan@?
        Type:  defect                |        Status:  new
    Priority:  major                 |     Milestone:
   Component:  coreboot              |    Resolution:
    Keywords:                        |  Dependencies:
Patch Status:  there is no patch     |
-------------------------------------+-------------------------------------

Comment (by czw[+]660[+]@?):

 I've noticed, through freedos, that the (apparently) working coreboot v2
 fails recognizing and granting access to any emulated floppy, accessible
 via qemu's bios.bin, perhaps you'll find some hints in the logs I've
 posted, in the boot parts with handle failures and registry data
 (qemu_coreboot_seabios.log). It seems it could be a 'target' related
 problem, because I've tried to change (in qemu) the target machine,
 setting it to a 'standard pc for qemu 0.11', and the resulting log for the
 other, newer versions of coreboot I was testing, shows an apparently
 booting machine, though with no visual output (it seems to fail loading
 the vga option rom, the log misses the lines "Running option rom at
 c000:0003
 " and "Turning on vga console" after "Scan for VGA option rom" ).
 Attaching file 'qemu_0.11_test.log' as serial output for coreboot r6325
 with seabios stable version.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/174#comment:1>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Thu Feb  3 06:04:39 2011
From: svn at coreboot.org (coreboot)
Date: Thu, 03 Feb 2011 05:04:39 -0000
Subject: [coreboot] #174: Unable to boot from qemu-kvm -- seems to be a
 cbfs problem
In-Reply-To: <060.648700c6f1026614c71f90e09c54f4b1@coreboot.org>
References: <060.648700c6f1026614c71f90e09c54f4b1@coreboot.org>
Message-ID: <075.0eed0341805bae58e9befd57beb1e460@coreboot.org>

#174: Unable to boot from qemu-kvm -- seems to be a cbfs problem
-------------------------------------+-------------------------------------
    Reporter:  czw[+]660[+]@?        |         Owner:  stepan@?
        Type:  defect                |        Status:  new
    Priority:  major                 |     Milestone:
   Component:  coreboot              |    Resolution:
    Keywords:                        |  Dependencies:
Patch Status:  there is no patch     |
-------------------------------------+-------------------------------------

Comment (by czw[+]660[+]@?):

 Coreboot v2 (r4917) allows grants access, anyway, to emulated ide, and
 freedos works fine for the rest (as far as I've tested it). (just to
 clarify)

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/174#comment:2>
coreboot <http://www.coreboot.org/>


From svens at stackframe.org  Thu Feb  3 09:07:25 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Thu, 03 Feb 2011 09:07:25 +0100
Subject: [coreboot] [PATCH] add PC87382 to superiotool
In-Reply-To: <20110202235116.GE9074@greenwood> (Uwe Hermann's message of "Thu\,
	3 Feb 2011 00\:51\:16 +0100")
References: <87ei7snhs3.fsf@begreifnix.stackframe.org>
	<20110202235116.GE9074@greenwood>
Message-ID: <87lj1xmthe.fsf@begreifnix.stackframe.org>

Uwe Hermann <uwe at hermann-uwe.de> writes:

> Thanks, committed as r6327 with minor whitespace and consistency
> changes.
>
>
>> +	{0xf4, "PC87382", {
>> +		{ NOLDN, NULL,
>> +			{ 0x20, 0x21, 0x22, 0x26, 0x27, 0x29, EOT },
>> +			{ 0xf2, 0x11, 0x63, 0x00, 0x00, 0x00, EOT }},
>
> I also changed the 0xf2 value for register 0x20 (chip ID) to 0xf4, that
> was probably a typo.

Yes, indeed a typo. Sorry.

Thanks,

Sven
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From seppk at arcor.de  Thu Feb  3 09:17:40 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Thu, 03 Feb 2011 09:17:40 +0100
Subject: [coreboot] errata#89 patch for Family 0Fh Prozessors
In-Reply-To: <4D49CA9C.8000402@assembler.cz>
References: <4D4996BB.7080105@arcor.de> <4D49AC4C.9030009@gmail.com>
	<4D49CA9C.8000402@assembler.cz>
Message-ID: <4D4A64A4.4060805@arcor.de>

Am 02.02.2011 22:20, schrieb Rudolf Marek:
> While we are at it. I'm attaching some very old patch (r2978 ;)
> which contains some errata fixes too, if you have some spare time 
> please try to check if it is correct.
>
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
>
>
> Thanks,
> Rudolf
>
Hi,
are you sure ?

-#if K8_REV_F_SUPPORT == 1
-        /* Erratum 131... */
+        /* Erratum 131 is fixed together with erratum 169 */
          msr = rdmsr(NB_CFG_MSR);
-        msr.lo |= 1<<  20;
+        msr.lo |= 1<<  32;<=======================
          wrmsr(NB_CFG_MSR, msr);

Josef



From svn at coreboot.org  Thu Feb  3 10:14:40 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Feb 2011 10:14:40 +0100
Subject: [coreboot] [commit] r6329 - in trunk/src: devices include/device
	southbridge/intel/i82801gx
Message-ID: <E1PkvGy-0000M8-Dh@ra.coresystems.de>

Author: oxygene
Date: Thu Feb  3 10:14:40 2011
New Revision: 6329
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6329

Log:
Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functions

This is so that boards can determine them on runtime based on hardware
properties, if so desired.


Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Joseph Kellermann <Joseph.Kellermann at heitec.de>

Modified:
   trunk/src/devices/pci_device.c
   trunk/src/include/device/pci.h
   trunk/src/southbridge/intel/i82801gx/pci.c

Modified: trunk/src/devices/pci_device.c
==============================================================================
--- trunk/src/devices/pci_device.c	Thu Feb  3 00:56:15 2011	(r6328)
+++ trunk/src/devices/pci_device.c	Thu Feb  3 10:14:40 2011	(r6329)
@@ -586,6 +586,16 @@
 	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 }
 
+unsigned __attribute__((weak)) mainboard_pci_subsystem_vendor_id(__attribute__((unused)) struct device *dev)
+{
+		return CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID;
+}
+
+unsigned __attribute__((weak)) mainboard_pci_subsystem_device_id(__attribute__((unused)) struct device *dev)
+{
+		return CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID;
+}
+
 void pci_dev_enable_resources(struct device *dev)
 {
 	const struct pci_operations *ops;
@@ -595,11 +605,11 @@
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
 		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", dev_path(dev),
-		       CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-		       CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+		       mainboard_pci_subsystem_vendor_id(dev),
+		       mainboard_pci_subsystem_device_id(dev));
 		ops->set_subsystem(dev,
-				   CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-				   CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+				   mainboard_pci_subsystem_vendor_id(dev),
+				   mainboard_pci_subsystem_device_id(dev));
 	}
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;

Modified: trunk/src/include/device/pci.h
==============================================================================
--- trunk/src/include/device/pci.h	Thu Feb  3 00:56:15 2011	(r6328)
+++ trunk/src/include/device/pci.h	Thu Feb  3 10:14:40 2011	(r6329)
@@ -103,4 +103,7 @@
 	return bops;
 }
 
+unsigned mainboard_pci_subsystem_vendor_id(struct device *dev);
+unsigned mainboard_pci_subsystem_device_id(struct device *dev);
+
 #endif /* PCI_H */

Modified: trunk/src/southbridge/intel/i82801gx/pci.c
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/pci.c	Thu Feb  3 00:56:15 2011	(r6328)
+++ trunk/src/southbridge/intel/i82801gx/pci.c	Thu Feb  3 10:14:40 2011	(r6329)
@@ -73,11 +73,11 @@
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
 		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
 			dev_path(dev),
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+			mainboard_pci_subsystem_vendor_id(dev),
+			mainboard_pci_subsystem_device_id(dev));
 		ops->set_subsystem(dev,
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+			mainboard_pci_subsystem_vendor_id(dev),
+			mainboard_pci_subsystem_device_id(dev));
 	}
 
 	command = pci_read_config16(dev, PCI_COMMAND);



From mr.nuke.me at gmail.com  Thu Feb  3 10:14:22 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 03 Feb 2011 11:14:22 +0200
Subject: [coreboot] errata#89 patch for Family 0Fh Prozessors
In-Reply-To: <4D4A64A4.4060805@arcor.de>
References: <4D4996BB.7080105@arcor.de>
	<4D49AC4C.9030009@gmail.com>	<4D49CA9C.8000402@assembler.cz>
	<4D4A64A4.4060805@arcor.de>
Message-ID: <4D4A71EE.90508@gmail.com>

On 02/03/2011 10:17 AM, Josef Kellermann wrote:
>> e are at it. I'm attaching some very old patch (r2978 ;)
>> which contains some errata fixes too, if you have some spare time
>> please try to check if it is correct.
>>
>> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
>>
>>
>> Thanks,
>> Rudolf
>>
> Hi,
> are you sure ?

You're right:

AMD Publication #33610, page34

"[Regarding erratum #131]
Systems implementing the workaround for erratum #169 should not apply
this workaround."

So it seems AMD recommends either or, but not both.

Page 59:
"[Regarding erratum #169]
The workaround for this erratum supersedes the workaround for erratum
#131. When implementing
this workaround, the workaround for erratum #131 should not be applied."

So we better implement only 169, and explain in the comments why 131 is
left out.

Alex




From psybertao at gmail.com  Thu Feb  3 10:02:01 2011
From: psybertao at gmail.com (Craig Magee)
Date: Thu, 3 Feb 2011 22:02:01 +1300
Subject: [coreboot] (no subject)
Message-ID: <AANLkTikgeUVATUoHS6Uz+v2rH62A64Ynu00-H6kcwYsi@mail.gmail.com>





From svn at coreboot.org  Thu Feb  3 10:29:58 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Feb 2011 10:29:58 +0100
Subject: [coreboot] [commit] r6330 - trunk/src/southbridge/amd/rs690
Message-ID: <E1PkvVm-0001Zq-I1@ra.coresystems.de>

Author: oxygene
Date: Thu Feb  3 10:29:57 2011
New Revision: 6330
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6330

Log:
Fix subvendor/subdevice programming on RS690

Some RS690 devices require subvendor/subdevice IDs to
be programmed at locations other than default 0x2c.


Signed-off-by: Josef Kellermann <seppk at arcor.de>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/src/southbridge/amd/rs690/gfx.c
   trunk/src/southbridge/amd/rs690/ht.c

Modified: trunk/src/southbridge/amd/rs690/gfx.c
==============================================================================
--- trunk/src/southbridge/amd/rs690/gfx.c	Thu Feb  3 10:14:40 2011	(r6329)
+++ trunk/src/southbridge/amd/rs690/gfx.c	Thu Feb  3 10:29:57 2011	(r6330)
@@ -193,8 +193,13 @@
 	/* TODO: the optimization of voltage and frequency */
 }
 
+static void gfx_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x4c,  ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
 static struct pci_operations lops_pci = {
-	.set_subsystem = pci_dev_set_subsystem,
+	.set_subsystem = gfx_dev_set_subsystem,
 };
 
 static struct device_operations pcie_ops = {

Modified: trunk/src/southbridge/amd/rs690/ht.c
==============================================================================
--- trunk/src/southbridge/amd/rs690/ht.c	Thu Feb  3 10:14:40 2011	(r6329)
+++ trunk/src/southbridge/amd/rs690/ht.c	Thu Feb  3 10:29:57 2011	(r6330)
@@ -70,8 +70,13 @@
 	pci_write_config32(dev, 0x4C, dword);
 }
 
+static void ht_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x50,  ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
 static struct pci_operations lops_pci = {
-	.set_subsystem = pci_dev_set_subsystem,
+	.set_subsystem = ht_dev_set_subsystem,
 };
 
 static struct device_operations ht_ops = {



From svn at coreboot.org  Thu Feb  3 10:32:27 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Feb 2011 10:32:27 +0100
Subject: [coreboot] build service results for r6329
Message-ID: <E1PkvYB-000673-6K@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 6329 to
the coreboot repository. This caused the following 
changes:

Change Log:
Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functions

This is so that boards can determine them on runtime based on hardware
properties, if so desired.


Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Joseph Kellermann <Joseph.Kellermann at heitec.de>


Build Log:
Compilation of a-trend:atc-6220 has been fixed
Compilation of a-trend:atc-6240 has been fixed
Compilation of abit:be6-ii_v2_0 has been fixed
Compilation of advantech:pcm-5820 has been fixed
Compilation of amd:bimini_fam10 has been fixed
Compilation of amd:db800 has been fixed
Compilation of amd:dbm690t has been fixed
Compilation of amd:mahogany has been fixed
Compilation of amd:mahogany_fam10 has been fixed
Compilation of amd:norwich has been fixed
Compilation of amd:pistachio has been fixed
Compilation of amd:rumba has been fixed
Compilation of amd:serengeti_cheetah has been fixed
Compilation of amd:serengeti_cheetah_fam10 has been fixed
Compilation of amd:tilapia_fam10 has been fixed
Compilation of arima:hdama has been fixed
Compilation of artecgroup:dbe61 has been fixed
Compilation of asi:mb_5blgp has been fixed
Compilation of asi:mb_5blmp has been fixed
Compilation of asrock:939a785gmh has been fixed
Compilation of asus:a8n_e has been fixed
Compilation of asus:a8v-e_deluxe has been fixed
Compilation of asus:a8v-e_se has been fixed
Compilation of asus:m2n-e has been fixed
Compilation of asus:m2v has been fixed
Compilation of asus:m2v-mx_se has been fixed
Compilation of asus:m4a78-em has been fixed
Compilation of asus:m4a785-m has been fixed
Compilation of asus:mew-am has been fixed
Compilation of asus:mew-vm has been fixed
Compilation of asus:p2b has been fixed
Compilation of asus:p2b-d has been fixed
Compilation of asus:p2b-ds has been fixed
Compilation of asus:p2b-f has been fixed
Compilation of asus:p2b-ls has been fixed
Compilation of asus:p3b-f has been fixed
Compilation of axus:tc320 has been fixed
Compilation of azza:pt-6ibd has been fixed
Compilation of bcom:winnet100 has been fixed
Compilation of bcom:winnetp680 has been fixed
Compilation of biostar:m6tba has been fixed
Compilation of broadcom:blast has been fixed
Compilation of compaq:deskpro_en_sff_p600 has been fixed
Compilation of dell:s1850 has been fixed
Compilation of digitallogic:adl855pc has been fixed
Compilation of digitallogic:msm586seg has been fixed
Compilation of digitallogic:msm800sev has been fixed
Compilation of eaglelion:5bcm has been fixed
Compilation of ecs:p6iwp-fe has been fixed
Compilation of emulation:qemu-x86 has been fixed
Compilation of getac:p470 has been fixed
Compilation of gigabyte:ga-6bxc has been fixed
Compilation of gigabyte:ga-6bxe has been fixed
Compilation of gigabyte:ga_2761gxdk has been fixed
Compilation of gigabyte:m57sli has been fixed
Compilation of gigabyte:ma785gmt has been fixed
Compilation of gigabyte:ma78gm has been fixed
Compilation of hp:dl145_g1 has been fixed
Compilation of hp:dl145_g3 has been fixed
Compilation of hp:dl165_g6_fam10 has been fixed
Compilation of hp:e_vectra_p2706t has been fixed
Compilation of ibase:mb899 has been fixed
Compilation of ibm:e325 has been fixed
Compilation of ibm:e326 has been fixed
Compilation of iei:juki-511p has been fixed
Compilation of iei:kino-780am2-fam10 has been fixed
Compilation of iei:nova4899r has been fixed
Compilation of iei:pcisa-lx-800-r10 has been fixed
Compilation of intel:d810e2cb has been fixed
Compilation of intel:d945gclf has been fixed
Compilation of intel:eagleheights has been fixed
Compilation of intel:jarrell has been fixed
Compilation of intel:mtarvon has been fixed
Compilation of intel:truxton has been fixed
Compilation of intel:xe7501devkit has been fixed
Compilation of iwave:iWRainbowG6 has been fixed
Compilation of iwill:dk8_htx has been fixed
Compilation of iwill:dk8s2 has been fixed
Compilation of iwill:dk8x has been fixed
Compilation of jetway:j7f24 has been fixed
Compilation of jetway:pa78vm5 has been fixed
Compilation of kontron:986lcd-m has been fixed
Compilation of kontron:kt690 has been fixed
Compilation of lanner:em8510 has been fixed
Compilation of lippert:frontrunner has been fixed
Compilation of lippert:hurricane-lx has been fixed
Compilation of lippert:literunner-lx has been fixed
Compilation of lippert:roadrunner-lx has been fixed
Compilation of lippert:spacerunner-lx has been fixed
Compilation of mitac:6513wu has been fixed
Compilation of msi:ms6119 has been fixed
Compilation of msi:ms6147 has been fixed
Compilation of msi:ms6156 has been fixed
Compilation of msi:ms6178 has been fixed
Compilation of msi:ms7135 has been fixed
Compilation of msi:ms7260 has been fixed
Compilation of msi:ms9185 has been fixed
Compilation of msi:ms9282 has been fixed
Compilation of msi:ms9652_fam10 has been fixed
Compilation of nec:powermate2000 has been fixed
Compilation of newisys:khepri has been fixed
Compilation of nokia:ip530 has been fixed
Compilation of nvidia:l1_2pvv has been fixed
Compilation of pcengines:alix1c has been fixed
Compilation of pcengines:alix2d has been fixed
Compilation of rca:rm4100 has been fixed
Compilation of roda:rk886ex has been fixed
Compilation of soyo:sy-6ba-plus-iii has been fixed
Compilation of sunw:ultra40 has been fixed
Compilation of supermicro:h8dme has been fixed
Compilation of supermicro:h8dmr has been fixed
Compilation of supermicro:h8dmr_fam10 has been fixed
Compilation of supermicro:h8qme_fam10 has been fixed
Compilation of supermicro:x6dai_g has been fixed
Compilation of supermicro:x6dhe_g has been fixed
Compilation of supermicro:x6dhe_g2 has been fixed
Compilation of supermicro:x6dhr_ig has been fixed
Compilation of supermicro:x6dhr_ig2 has been fixed
Compilation of technexion:tim5690 has been fixed
Compilation of technexion:tim8690 has been fixed
Compilation of technologic:ts5300 has been fixed
Compilation of televideo:tc7020 has been fixed
Compilation of thomson:ip1000 has been fixed
Compilation of traverse:geos has been fixed
Compilation of tyan:s1846 has been fixed
Compilation of tyan:s2735 has been fixed
Compilation of tyan:s2850 has been fixed
Compilation of tyan:s2875 has been fixed
Compilation of tyan:s2880 has been fixed
Compilation of tyan:s2881 has been fixed
Compilation of tyan:s2882 has been fixed
Compilation of tyan:s2885 has been fixed
Compilation of tyan:s2891 has been fixed
Compilation of tyan:s2892 has been fixed
Compilation of tyan:s2895 has been fixed
Compilation of tyan:s2912 has been fixed
Compilation of tyan:s2912_fam10 has been fixed
Compilation of tyan:s4880 has been fixed
Compilation of tyan:s4882 has been fixed
Compilation of via:epia has been fixed
Compilation of via:epia-cn has been fixed
Compilation of via:epia-m has been fixed
Compilation of via:epia-m700 has been fixed
Compilation of via:epia-n has been fixed
Compilation of via:pc2500e has been fixed
Compilation of via:vt8454c has been fixed
Compilation of winent:pl6064 has been fixed
Compilation of wyse:s50 has been fixed


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Thu Feb  3 10:56:55 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Feb 2011 10:56:55 +0100
Subject: [coreboot] build service results for r6330
Message-ID: <E1Pkvvr-0003j2-Nh@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 6330 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix subvendor/subdevice programming on RS690

Some RS690 devices require subvendor/subdevice IDs to
be programmed at locations other than default 0x2c.


Signed-off-by: Josef Kellermann <seppk at arcor.de>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>


Build Log:
Compilation of a-trend:atc-6220 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6330&device=atc-6220&vendor=a-trend&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From seppk at arcor.de  Thu Feb  3 11:26:53 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Thu, 03 Feb 2011 11:26:53 +0100
Subject: [coreboot] errata#89 patch for Family 0Fh Prozessors
In-Reply-To: <4D4A71EE.90508@gmail.com>
References: <4D4996BB.7080105@arcor.de>	<4D49AC4C.9030009@gmail.com>	<4D49CA9C.8000402@assembler.cz>	<4D4A64A4.4060805@arcor.de>
	<4D4A71EE.90508@gmail.com>
Message-ID: <4D4A82ED.2030900@arcor.de>

Am 03.02.2011 10:14, schrieb Alex G.:
> On 02/03/2011 10:17 AM, Josef Kellermann wrote:
>>> e are at it. I'm attaching some very old patch (r2978 ;)
>>> which contains some errata fixes too, if you have some spare time
>>> please try to check if it is correct.
>>>
>>> Signed-off-by: Rudolf Marek<r.marek at assembler.cz>
>>>
>>>
>>> Thanks,
>>> Rudolf
>>>
>> Hi,
>> are you sure ?
> You're right:
>
> AMD Publication #33610, page34
>
> "[Regarding erratum #131]
> Systems implementing the workaround for erratum #169 should not apply
> this workaround."
>
> So it seems AMD recommends either or, but not both.
>
> Page 59:
> "[Regarding erratum #169]
> The workaround for this erratum supersedes the workaround for erratum
> #131. When implementing
> this workaround, the workaround for erratum #131 should not be applied."
>
> So we better implement only 169, and explain in the comments why 131 is
> left out.
>
> Alex
>
>
Hi,
sorry for the misunderstanding.
Setting bit 32 in msr should be ->  'msr.hi |= (1<<  0)', no?

Josef



From mr.nuke.me at gmail.com  Thu Feb  3 12:35:00 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 03 Feb 2011 13:35:00 +0200
Subject: [coreboot] errata#89 patch for Family 0Fh Prozessors
In-Reply-To: <4D4A82ED.2030900@arcor.de>
References: <4D4996BB.7080105@arcor.de>	<4D49AC4C.9030009@gmail.com>	<4D49CA9C.8000402@assembler.cz>	<4D4A64A4.4060805@arcor.de>	<4D4A71EE.90508@gmail.com>
	<4D4A82ED.2030900@arcor.de>
Message-ID: <4D4A92E4.1030300@gmail.com>

> Hi,
> sorry for the misunderstanding.
> Setting bit 32 in msr should be ->  'msr.hi |= (1<<  0)', no?
LOL! Nice catch.

This is what happens when you're still up at 6AM, obsessive drawing
lines on a Google Earth printscreen in order to finish a project due in
a few hours. :P

It's funny to see those logic mistakes made with so much ease. As for
#169, we should set 'msr.hi |= (1<<  0)' :P, "set
F0x68[22:21](DsNpReqLmt0) to 01b," and drop #131 altogether.

I'm assuming the second part means 0:18.0, register 0x6b-0x68[22:21], or
Rx6a[6-5].

reg = pci_read_config8(0:18.0, 0x6a);
reg |= 0x20;
pci_write_config8(0:18.0, 0x6a, reg);

Alex




From seppk at arcor.de  Thu Feb  3 16:09:40 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Thu, 03 Feb 2011 16:09:40 +0100
Subject: [coreboot] cmos recovery feature
Message-ID: <4D4AC534.90109@arcor.de>

Patrick,

having made a 'svn up' I'm getting a build error:

make: *** Keine Regel vorhanden, um das Target ?cmos.default?,
   ben?tigt von ?build/coreboot.pre1?, zu erstellen.  Schluss.

I've added this to my mainboards Makefile.inc:

cbfs-files-y += cmos.default
cmos.default-name = cmos.default
cmos.default-type = 0xaa

cmos.default also exists in mainboard dir.

I've also tried with:
cmos.default-file = cmos.default

Any idea ?

Regards,
Joseph



From svn at coreboot.org  Thu Feb  3 17:00:29 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Feb 2011 17:00:29 +0100
Subject: [coreboot] [commit] r6331 - trunk/util/superiotool
Message-ID: <E1Pl1bh-0000GN-58@ra.coresystems.de>

Author: jakllsch
Date: Thu Feb  3 17:00:28 2011
New Revision: 6331
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6331

Log:
Add support for the IT8720F Super I/O

Signed-off-by: Christian Ruppert <idl0r at gentoo.org>
Acked-by: Stefan Reinauer <stepan at coreboot.org>

Modified:
   trunk/util/superiotool/ite.c

Modified: trunk/util/superiotool/ite.c
==============================================================================
--- trunk/util/superiotool/ite.c	Thu Feb  3 10:29:57 2011	(r6330)
+++ trunk/util/superiotool/ite.c	Thu Feb  3 17:00:28 2011	(r6331)
@@ -603,7 +603,51 @@
 			{0x30,0x60,0x61,0x70,0xf0,EOT},
 			{0x00,0x03,0x10,0x0b,0x00,EOT}},
 		{EOT}}},
-	{0x8720, "IT8720F", {	/* From sensors-detect */
+	{0x8720, "IT8720F", {
+		{NOLDN, NULL,
+			{0x20,0x21,0x22,0x23,0x24,0x2b,EOT},
+			{0x87,0x20,0x05,0x00,0x00,0x00,EOT}},
+		{0x0, "Floppy",
+			{0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT},
+			{0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}},
+		{0x1, "COM1",
+			{0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
+			{0x00,0x03,0xf8,0x04,0x00,0x50,EOT}},
+		{0x2, "COM2",
+			{0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
+			{0x00,0x02,0xf8,0x03,0x00,0x50,EOT}},
+		{0x3, "Parallel port",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT},
+			{0x00,0x03,0x78,0x07,0x78,0x07,0x03,0x03,EOT}},
+		{0x4, "Environment controller",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,
+			 0xf4,0xf5,0xf6,EOT},
+			{0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,0x00,
+			 0x00,NANA,NANA,EOT}},
+		{0x5, "Keyboard",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT},
+			{0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x48,EOT}},
+		{0x6, "Mouse",
+			{0x30,0x70,0x71,0xf0,EOT},
+			{0x00,0x0c,0x02,0x00,EOT}},
+		{0x7, "GPIO",
+			{0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x60,0x61,0x62,
+			 0x63,0x64,0x65,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1,
+			 0xb2,0xb3,0xb4,0xb5,0xb8,0xb9,0xba,0xbb,0xbc,0xbd,
+			 0xc0,0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc,
+			 0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xf0,
+			 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,
+			 0xfb,0xfc,0xfd,0xfe,0xff,EOT},
+			{0x00,0xff,0x00,0x40,0x00,0x00,0x03,0x00,0x00,0x00,
+			 0x00,0x00,0x00,0x00,0x00,NANA,0x38,0x00,0x00,0x00,
+			 0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,
+			 0x01,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x40,0x00,
+			 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,0x00,
+			 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+			 0x00,NANA,0x00,0x00,0x00,EOT}},
+		{0xa, "Consumer IR",
+			{0x30,0x60,0x61,0x70,0xf0,EOT},
+			{0x00,0x03,0x10,0x0b,0x06,EOT}},
 		{EOT}}},
 	{0x8721, "IT8721F", {
 		{EOT}}},



From svn at coreboot.org  Thu Feb  3 17:16:50 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Feb 2011 17:16:50 +0100
Subject: [coreboot] build service results for r6331
Message-ID: <E1Pl1rW-0005el-TQ@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "jakllsch" checked in revision 6331 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add support for the IT8720F Super I/O

Signed-off-by: Christian Ruppert <idl0r at gentoo.org>
Acked-by: Stefan Reinauer <stepan at coreboot.org>


Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6331&device=atc-6220&vendor=a-trend&num=2


If something broke during this checkin please be a pain 
in jakllsch's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From stefan.reinauer at coreboot.org  Thu Feb  3 22:33:05 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Thu, 3 Feb 2011 22:33:05 +0100
Subject: [coreboot] Reliably build any Kconfig-based SeaBIOS revision
In-Reply-To: <20110129202608.10621.qmail@stuge.se>
References: <20110129202608.10621.qmail@stuge.se>
Message-ID: <20110203213305.GB28701@coreboot.org>

* Peter Stuge <peter at stuge.se> [110129 21:26]:
> See patch.
> 
> The new TAG-stable points to the very latest commit in seabios.git,
> which may not be quite right, but both stable and master must be
> using Kconfig.
> 
> 
> //Peter

slightly reworked to get rid of the perl calls (and to work with the
latest HEAD version with options that are hidden during defconfig so a
perl call would not replace them.


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From seppk at arcor.de  Fri Feb  4 12:03:10 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Fri, 04 Feb 2011 12:03:10 +0100
Subject: [coreboot] rs690 mmconfig access
Message-ID: <4D4BDCEE.7010108@arcor.de>

attached is a patch to enable mmconf access on RS690.
This patch is required for the upcoming Siemens sitemp mainboard.

1. Overwrite read resources in src/southbridge/amd/rs690/ht.c
    a. disable and hide BAR3 so pci_get_resource() doesn't touch.
    b. add an mmconf resource

2. Overwrite set_resources so that it:
    a. writes the mmconf resource base to the BAR3
    b. disable writes and hide BAR3
    c. find a not assigned resource in the K8 mmio and
       setup base and limit with flag nonposted
3. Add the resource as reserved in add_mainboard_resources()
4. in the mainboard's acpi_tables.c
    a. pass the mmconf base to the dsdt.
    b. create a ACPI mcfg table

I've testet with Linux 2.6.12, Linux 2.6.26 and Windows XP SP3 + ATI X1200 driver,
Linux 2.6.26 comes up with the following messages:
[    0.232014] PCI: MCFG configuration 0: base e0000000 segment 0 buses 0 - 31
[    0.232014] PCI: MCFG area at e0000000 reserved in E820
[    0.232014] PCI: Using MMCONFIG at e0000000 - e1ffffff
[    0.232014] PCI: Using configuration type 1 for base access

lspci -xxxx shows me 4Kb ext config space for some devices.

Can somebody please comment on the patch ? Would be nice !

Signed-off-by: Josef Kellermann<seppk at arcor.de>  <mailto://seppk at arcor.de>

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From hagigatali at gmail.com  Sat Feb  5 05:55:35 2011
From: hagigatali at gmail.com (ali hagigat)
Date: Sat, 5 Feb 2011 08:25:35 +0330
Subject: [coreboot] a question about reset16.lds
In-Reply-To: <4D48388F.3020006@georgi-clan.de>
References: <AANLkTikkEg62XVUj65zDeGa3+BjxP8FHSYPVVh4b=jLg@mail.gmail.com>
	<4D48388F.3020006@georgi-clan.de>
Message-ID: <AANLkTim_2DdNQD6A7=w=V37BJt0nSGeRQ_iUPdgOa6Nn@mail.gmail.com>

Thank you for the reply.

Lets consider the lines of that linker script again! First the
location counter is set to 0xfffffff0 and the output .reset section
starts from VMA=0xfffffff0. I think we both agree on that so far.
But after .reset section, .=15 forces the location counter to be 15!!
It means the location counter suddenly jumps from the top of memory to
some where in the bottom! and then linker asks for storing 0x00 in the
address of 15! or at the beginning of memory.
.=15 does not set the size of .reset as you wrote.
My suggestion was .=.+1 instead of .=15, or set VMA to one byte after
the final .reset and then ask for writing 0x00 at the address of
0xffffffff.
We are using . in the linker script file, it means VMA (virtual memory
address)    .....


On Tue, Feb 1, 2011 at 8:15 PM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 01.02.2011 12:46, schrieb ali hagigat:
>>
>> SECTIONS {
>> ? ? ? ?/* Trigger an error if I have an unuseable start address */
>> ? ? ? ?_bogus = ASSERT(_start>= 0xffff0000, "_start too low. Please
>> decrease CONFIG_ROM_IMAGE_SIZE");
>> ? ? ? ?_ROMTOP = 0xfffffff0;
>> ? ? ? ?. = _ROMTOP;
>> ? ? ? ?.reset . : {
>> ? ? ? ? ? ? ? ?*(.reset)
>> ? ? ? ? ? ? ? ?. = 15 ;
>> ? ? ? ? ? ? ? ?BYTE(0x00);
>> ? ? ? ?}
>> }
>> ------------------------------------------------------------------
>> What does (.=15;) mean? It seems a mistake! and can be: . = .+1;
>
> . = 15; means "set the location pointer to 15". With the byte that's written
> right after that, this means that .reset is exactly 16 bytes.
> If it's less, ". = 15" pads the section to be larger, if it would have to be
> larger, ". = 15" makes the linker fail (because the location pointer must
> not go backwards).
>
> I guess that also answers why ". = .+1" is no adequate substitute.
>
>
> Patrick
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From patrick at georgi-clan.de  Sat Feb  5 09:44:30 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 05 Feb 2011 09:44:30 +0100
Subject: [coreboot] a question about reset16.lds
In-Reply-To: <AANLkTim_2DdNQD6A7=w=V37BJt0nSGeRQ_iUPdgOa6Nn@mail.gmail.com>
References: <AANLkTikkEg62XVUj65zDeGa3+BjxP8FHSYPVVh4b=jLg@mail.gmail.com>	<4D48388F.3020006@georgi-clan.de>
	<AANLkTim_2DdNQD6A7=w=V37BJt0nSGeRQ_iUPdgOa6Nn@mail.gmail.com>
Message-ID: <4D4D0DEE.8090105@georgi-clan.de>

Am 05.02.2011 05:55, schrieb ali hagigat:
> Lets consider the lines of that linker script again! First the
> location counter is set to 0xfffffff0 and the output .reset section
> starts from VMA=0xfffffff0. I think we both agree on that so far.
> But after .reset section, .=15 forces the location counter to be 15!!
Inside a section definition, the location pointer is relative to the
start of the section. The section's location isn't always known
beforehand (but you're right that it is in our case).

> It means the location counter suddenly jumps from the top of memory to
> some where in the bottom! and then linker asks for storing 0x00 in the
> address of 15! or at the beginning of memory.
That would lead to a linker error. If you try ". = 0" at the place, the
linker will fail: cannot move location counter backwards (from fffffffd
to fffffff0)

> .=15 does not set the size of .reset as you wrote.
> My suggestion was .=.+1 instead of .=15, or set VMA to one byte after
> the final .reset and then ask for writing 0x00 at the address of
> 0xffffffff.
This relies on knowledge that *(.reset) yields 15 bytes of data, and
might break on runtime if it's less, or on build time if it's more.
With ". = 15" you get deterministic behaviour on build time.


Patrick



From svn at coreboot.org  Sat Feb  5 13:20:23 2011
From: svn at coreboot.org (repository service)
Date: Sat, 05 Feb 2011 13:20:23 +0100
Subject: [coreboot] [commit] r6332 - in trunk/src/superio/nsc: . pc87382
Message-ID: <E1Plh7n-00063d-NM@ra.coresystems.de>

Author: stuge
Date: Sat Feb  5 13:20:23 2011
New Revision: 6332
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6332

Log:
Add PC87382 support

This patch adds support for NSC PC87382 Super I/O. It is used in many
Lenovo Notebooks as Docking LPC Switch.

v2 because of:

- Skip some empty files
- Fix newlines in Kconfig and Makefile.inc
- chip.h missed uart8250.h include
- add the Kconfig option in sorted order

Thanks to idwer on irc for pointing that out.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>

Added:
   trunk/src/superio/nsc/pc87382/
   trunk/src/superio/nsc/pc87382/Makefile.inc
   trunk/src/superio/nsc/pc87382/chip.h
   trunk/src/superio/nsc/pc87382/pc87382.h
   trunk/src/superio/nsc/pc87382/superio.c
Modified:
   trunk/src/superio/nsc/Makefile.inc

Modified: trunk/src/superio/nsc/Makefile.inc
==============================================================================
--- trunk/src/superio/nsc/Makefile.inc	Thu Feb  3 17:00:28 2011	(r6331)
+++ trunk/src/superio/nsc/Makefile.inc	Sat Feb  5 13:20:23 2011	(r6332)
@@ -22,6 +22,7 @@
 subdirs-y += pc87351
 subdirs-y += pc87360
 subdirs-y += pc87366
+subdirs-y += pc87382
 subdirs-y += pc87417
 subdirs-y += pc87427
 subdirs-y += pc97307

Added: trunk/src/superio/nsc/pc87382/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87382/Makefile.inc	Sat Feb  5 13:20:23 2011	(r6332)
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_NSC_PC87382) += superio.c
+

Added: trunk/src/superio/nsc/pc87382/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87382/chip.h	Sat Feb  5 13:20:23 2011	(r6332)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_NSC_PC87382_CHIP_H
+#define SUPERIO_NSC_PC87382_CHIP_H
+
+#include <uart8250.h>
+extern struct chip_operations superio_nsc_pc87382_ops;
+
+struct superio_nsc_pc87382_config {
+	struct uart8250 com1, com2;
+};
+
+#endif

Added: trunk/src/superio/nsc/pc87382/pc87382.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87382/pc87382.h	Sat Feb  5 13:20:23 2011	(r6332)
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_NSC_PC87382_H
+#define SUPERIO_NSC_PC87382_H
+
+#define PC87382_IR   0x02
+#define PC87382_SP1  0x03
+#define PC87382_GPIO 0x07
+#define PC87382_DOCK 0x19
+#endif

Added: trunk/src/superio/nsc/pc87382/superio.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87382/superio.c	Sat Feb  5 13:20:23 2011	(r6332)
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "pc87382.h"
+
+static void init(device_t dev)
+{
+	struct superio_nsc_pc87382_config *conf = dev->chip_info;
+	struct resource *res0;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.pnp.device) {
+	case PC87382_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case PC87382_IR:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+
+	case PC87382_DOCK:
+		break;
+
+	case PC87382_GPIO:
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, PC87382_IR,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x07f8, 0 } },
+	{ &ops, PC87382_SP1,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } },
+	{ &ops, PC87382_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } },
+	{ &ops, PC87382_DOCK, PNP_IO0 | PNP_IRQ0, { 0xfffe, 0 } },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nsc_pc87382_ops = {
+	CHIP_NAME("NSC PC87382 Docking LPC Switch")
+	.enable_dev = enable_dev,
+};



From peter at stuge.se  Sat Feb  5 13:20:51 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 5 Feb 2011 13:20:51 +0100
Subject: [coreboot] [PATCH v2] Add PC87382 support
In-Reply-To: <86aaif1mzy.fsf@stackframe.org>
References: <86aaif1mzy.fsf@stackframe.org>
Message-ID: <20110205122051.27584.qmail@stuge.se>

Sven Schnelle wrote:
> this patch adds support for NSC PC87382 Super I/O. It is
> used in many Lenovo Notebooks as Docking LPC Switch.
> 
> v2 because of:
> 
> - The patch added some empty files
> - missing newlines in Kconfig and Makefile.inc
> - chip.h missed uart8250.h include
> - add the Kconfig option in sorted order
> 
> Thanks to idler on irc for pointing that out.
> 
> Signed-off-by: Sven Schnelle <svens at stackframe.org>

Acked-by: Peter Stuge <peter at stuge.se>

r6332
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From svn at coreboot.org  Sat Feb  5 13:26:08 2011
From: svn at coreboot.org (repository service)
Date: Sat, 05 Feb 2011 13:26:08 +0100
Subject: [coreboot] [commit] r6333 - in trunk/src/superio/nsc: . pc87392
Message-ID: <E1PlhDM-0000EB-KP@ra.coresystems.de>

Author: stuge
Date: Sat Feb  5 13:26:07 2011
New Revision: 6333
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6333

Log:
Add PC87392 support

This adds support for the NSC PC87392 Super I/O. It is used in Lenovo
Docking Stations as Super I/O chip.

v2 because of:

- skip some empty files
- missing newlines in Kconfig and Makefile.inc
- add the Kconfig option in sorted order

Thanks to idwer on irc for pointing that out.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>

Added:
   trunk/src/superio/nsc/pc87392/
   trunk/src/superio/nsc/pc87392/Makefile.inc
   trunk/src/superio/nsc/pc87392/chip.h
   trunk/src/superio/nsc/pc87392/early_serial.c
   trunk/src/superio/nsc/pc87392/pc87392.h
   trunk/src/superio/nsc/pc87392/superio.c
Modified:
   trunk/src/superio/nsc/Kconfig
   trunk/src/superio/nsc/Makefile.inc

Modified: trunk/src/superio/nsc/Kconfig
==============================================================================
--- trunk/src/superio/nsc/Kconfig	Sat Feb  5 13:20:23 2011	(r6332)
+++ trunk/src/superio/nsc/Kconfig	Sat Feb  5 13:26:07 2011	(r6333)
@@ -28,6 +28,8 @@
 	bool
 config SUPERIO_NSC_PC87366
 	bool
+config SUPERIO_NSC_PC87392
+	bool
 config SUPERIO_NSC_PC87417
 	bool
 config SUPERIO_NSC_PC87427

Modified: trunk/src/superio/nsc/Makefile.inc
==============================================================================
--- trunk/src/superio/nsc/Makefile.inc	Sat Feb  5 13:20:23 2011	(r6332)
+++ trunk/src/superio/nsc/Makefile.inc	Sat Feb  5 13:26:07 2011	(r6333)
@@ -23,6 +23,7 @@
 subdirs-y += pc87360
 subdirs-y += pc87366
 subdirs-y += pc87382
+subdirs-y += pc87392
 subdirs-y += pc87417
 subdirs-y += pc87427
 subdirs-y += pc97307

Added: trunk/src/superio/nsc/pc87392/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87392/Makefile.inc	Sat Feb  5 13:26:07 2011	(r6333)
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_NSC_PC87392) += superio.c
+

Added: trunk/src/superio/nsc/pc87392/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87392/chip.h	Sat Feb  5 13:26:07 2011	(r6333)
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_NSC_PC87392_CHIP_H
+#define SUPERIO_NSC_PC87392_CHIP_H
+
+extern struct chip_operations superio_nsc_pc87392_ops;
+
+#include <uart8250.h>
+
+struct superio_nsc_pc87392_config {
+	struct uart8250 com1, com2;
+};
+
+#endif

Added: trunk/src/superio/nsc/pc87392/early_serial.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87392/early_serial.c	Sat Feb  5 13:26:07 2011	(r6333)
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "pc87392.h"
+
+static void pc87392_enable_serial(device_t dev, u16 iobase)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+}

Added: trunk/src/superio/nsc/pc87392/pc87392.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87392/pc87392.h	Sat Feb  5 13:26:07 2011	(r6333)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_NSC_PC87392_H
+#define SUPERIO_NSC_PC87392_H
+
+#define PC87392_FDC  0x00
+#define PC87392_PP   0x01
+#define PC87392_SP2  0x02
+#define PC87392_SP1  0x03
+#define PC87392_GPIO 0x07
+#define PC87392_WDT  0x0A
+
+#endif

Added: trunk/src/superio/nsc/pc87392/superio.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87392/superio.c	Sat Feb  5 13:26:07 2011	(r6333)
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "pc87392.h"
+
+static void init(device_t dev)
+{
+	struct superio_nsc_pc87392_config *conf = dev->chip_info;
+	struct resource *res0;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.pnp.device) {
+	case PC87392_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+
+	case PC87392_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, PC87392_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0} },
+	{ &ops, PC87392_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0} },
+	{ &ops, PC87392_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0} },
+	{ &ops, PC87392_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0} },
+	{ &ops, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0} },
+	{ &ops, PC87392_WDT,  PNP_IO0 | PNP_IRQ0, {0xfffc, 0} },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nsc_pc87392_ops = {
+	CHIP_NAME("NSC PC87392 Super I/O")
+	.enable_dev = enable_dev,
+};



From peter at stuge.se  Sat Feb  5 13:26:31 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 5 Feb 2011 13:26:31 +0100
Subject: [coreboot] [PATCH v2] Add PC87392 support
In-Reply-To: <867hdj1mw7.fsf@stackframe.org>
References: <867hdj1mw7.fsf@stackframe.org>
Message-ID: <20110205122631.28469.qmail@stuge.se>

Sven Schnelle wrote:
> this patch adds support for the NSC PC87392 Super I/O. It is
> used in Lenovo Docking Stations as Super I/O chip.
> 
> v2 because of:
> 
> - The patch added some empty files
> - missing newlines in Kconfig and Makefile.inc
> - add the Kconfig option in sorted order
> 
> Thanks to idwer on irc for pointing that out.
> 
> Signed-off-by: Sven Schnelle <svens at stackframe.org>

Acked-by: Peter Stuge <peter at stuge.se>

r6333
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From svn at coreboot.org  Sat Feb  5 13:36:50 2011
From: svn at coreboot.org (repository service)
Date: Sat, 05 Feb 2011 13:36:50 +0100
Subject: [coreboot] build service results for r6332
Message-ID: <E1PlhNi-0003Rc-Ac@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stuge" checked in revision 6332 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add PC87382 support

This patch adds support for NSC PC87382 Super I/O. It is used in many
Lenovo Notebooks as Docking LPC Switch.

v2 because of:

- Skip some empty files
- Fix newlines in Kconfig and Makefile.inc
- chip.h missed uart8250.h include
- add the Kconfig option in sorted order

Thanks to idwer on irc for pointing that out.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Compilation of a-trend:atc-6220 has been fixed


If something broke during this checkin please be a pain 
in stuge's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sat Feb  5 14:32:57 2011
From: svn at coreboot.org (repository service)
Date: Sat, 05 Feb 2011 14:32:57 +0100
Subject: [coreboot] [commit] r6334 - trunk/src/superio/nsc
Message-ID: <E1PliG1-0005jQ-6r@ra.coresystems.de>

Author: stuge
Date: Sat Feb  5 14:32:56 2011
New Revision: 6334
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6334

Log:
Actually add PC87382 into Kconfig, missing from r6332

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/superio/nsc/Kconfig

Modified: trunk/src/superio/nsc/Kconfig
==============================================================================
--- trunk/src/superio/nsc/Kconfig	Sat Feb  5 13:26:07 2011	(r6333)
+++ trunk/src/superio/nsc/Kconfig	Sat Feb  5 14:32:56 2011	(r6334)
@@ -28,6 +28,8 @@
 	bool
 config SUPERIO_NSC_PC87366
 	bool
+config SUPERIO_NSC_PC87382
+	bool
 config SUPERIO_NSC_PC87392
 	bool
 config SUPERIO_NSC_PC87417



From svn at coreboot.org  Sat Feb  5 14:48:56 2011
From: svn at coreboot.org (repository service)
Date: Sat, 05 Feb 2011 14:48:56 +0100
Subject: [coreboot] build service results for r6334
Message-ID: <E1PliVU-0002OT-1b@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stuge" checked in revision 6334 to
the coreboot repository. This caused the following 
changes:

Change Log:
Actually add PC87382 into Kconfig, missing from r6332

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Compilation of a-trend:atc-6220 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6334&device=atc-6220&vendor=a-trend&num=2


If something broke during this checkin please be a pain 
in stuge's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sat Feb  5 17:51:55 2011
From: svn at coreboot.org (coreboot)
Date: Sat, 05 Feb 2011 16:51:55 -0000
Subject: [coreboot] #174: Unable to boot from qemu-kvm -- seems to be a
 cbfs problem
In-Reply-To: <060.648700c6f1026614c71f90e09c54f4b1@coreboot.org>
References: <060.648700c6f1026614c71f90e09c54f4b1@coreboot.org>
Message-ID: <075.ed7c6fa644e90e98e7a3e15b2bcdcb58@coreboot.org>

#174: Unable to boot from qemu-kvm -- seems to be a cbfs problem
-------------------------------------+-------------------------------------
    Reporter:  czw[+]660[+]@?        |         Owner:  stepan@?
        Type:  defect                |        Status:  new
    Priority:  major                 |     Milestone:
   Component:  coreboot              |    Resolution:
    Keywords:                        |  Dependencies:
Patch Status:  there is no patch     |
-------------------------------------+-------------------------------------

Comment (by anonymous):

 Ok, I've managed to boot with both r6325 and r6331, using both seabios
 stable and latest master version
 (d7137a30635b504203ae97510e8609bb350ee0f7), by enabling yabel emulation.
 Still getting the same error - 'Could not find fallback/payload' - if
 'YABEL_DIRECTHW' is set, though, so it would seem a problem related to the
 way coreboot interfaces with qemu-kvm 0.12.5 emulated hw, or the way the
 vga rom is loaded/run (that's the same for both qemu's and your patched
 version).

 Yet no floppies (neither emulated by qemu, nor embedded into coreboot). In
 any case (even with qemu's bios.bin), freedos gets some troubles to
 recognize the geometry of emulated cdrom (option -cdrom) and ide disk
 (option -hda), but it can read from them with stable seabios, whereas it
 fails with the newer version I've tested (it blocks). Also, the newer
 seabios causes a kvm problem on reboot (hitting Ctrl+Alt+Del kvm exits
 with error "unhandled exit ffffffff").

 The latter problems would seem seabios-related, though I can't tell, at
 this stage, if that's a real seabios pitfall or whether seabios changes
 hit another problem in coreboot, or in qemu, or if that's a combination of
 problems/diverging design choices of those three.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/174#comment:3>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Sat Feb  5 20:21:13 2011
From: svn at coreboot.org (coreboot)
Date: Sat, 05 Feb 2011 19:21:13 -0000
Subject: [coreboot] #174: Unable to boot from qemu-kvm -- seems to be a
 cbfs problem
In-Reply-To: <060.648700c6f1026614c71f90e09c54f4b1@coreboot.org>
References: <060.648700c6f1026614c71f90e09c54f4b1@coreboot.org>
Message-ID: <075.bb56c476f8ad519934ff0062c01a781f@coreboot.org>

#174: Unable to boot from qemu-kvm -- seems to be a cbfs problem
-------------------------------------+-------------------------------------
    Reporter:  czw[+]660[+]@?        |         Owner:  stepan@?
        Type:  defect                |        Status:  new
    Priority:  major                 |     Milestone:
   Component:  coreboot              |    Resolution:
    Keywords:                        |  Dependencies:
Patch Status:  there is no patch     |
-------------------------------------+-------------------------------------

Comment (by anonymous):

 Mmm, it seems a kvm-related issue. Without loaded kvm modules (thus,
 without kvm support) I've been able to boot with 'native' execution of
 option roms in both kvm-qemu 0.12.5 and 0.13.0, both seabios stable and
 master (the aforementioned commit).

 Still no floppies. Still unable to reboot with master seabios, vm just
 blocks and last lines in my serial log: 'Attempting a hard reboot
 ', 'i8042_wait_write'

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/174#comment:4>
coreboot <http://www.coreboot.org/>


From mr.nuke.me at gmail.com  Sat Feb  5 20:50:00 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Sat, 05 Feb 2011 21:50:00 +0200
Subject: [coreboot] [PATCH] Fix issue with Winbond W83627EHG MIDI driver
Message-ID: <4D4DA9E8.9060008@gmail.com>

(See Patch)

This fixes the
"ERROR: device PNP: 002e.207 index 98 has no mask."
that I have been getting on the W83627EHG.

Alex





From mr.nuke.me at gmail.com  Sat Feb  5 20:54:49 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Sat, 05 Feb 2011 21:54:49 +0200
Subject: [coreboot] [PATCH] Fix issue with Winbond W83627EHG MIDI driver
In-Reply-To: <4D4DA9E8.9060008@gmail.com>
References: <4D4DA9E8.9060008@gmail.com>
Message-ID: <4D4DAB09.3080606@gmail.com>

Sorry about forgetting to attach the patch.

Alex

On 02/05/2011 09:50 PM, Alex G. wrote:
> (See Patch)
> 
> This fixes the
> "ERROR: device PNP: 002e.207 index 98 has no mask."
> that I have been getting on the W83627EHG.
> 
> Alex
> 
> 

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From mr.nuke.me at gmail.com  Sat Feb  5 21:04:47 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Sat, 05 Feb 2011 22:04:47 +0200
Subject: [coreboot] [PATCH]  errata#89 patch for Family 0Fh Prozessors
In-Reply-To: <4D49D2DF.6040902@gmail.com>
References: <4D4996BB.7080105@arcor.de> <4D49AC4C.9030009@gmail.com>
	<4D49BBD0.1040202@arcor.de> <4D49D2DF.6040902@gmail.com>
Message-ID: <4D4DAD5F.10907@gmail.com>

Can someone with commit access please commit this patch, or NACK it?

Alex

On 02/02/2011 11:55 PM, Alex G. wrote:
> That looks way better. :)
> 
> Acked-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
> 
> On 02/02/2011 10:17 PM, Josef Kellermann wrote:
>> Am 02.02.2011 20:11, schrieb Alex G.:
>>> Erratum 89 is already handled on line 390:
>>>
>>> if (!is_cpu_pre_b3()) {
>>>
>>>     /* Erratum 89 ... */
>>>     msr = rdmsr(NB_CFG_MSR);
>>>     msr.lo |= 1 << 3;
>>>
>>> If this is also needed when CONFIG_K8_REV_F_SUPPORT == 1, then we should
>>> move the existing one out of the
>>> #if CONFIG_K8_REV_F_SUPPORT == 0
>>> so it gets executed in both cases, as opposed to duplicating it.
>>>
>>> Alex
>>>
>>> On 02/02/2011 07:39 PM, Josef Kellermann wrote:
>>>> This patch fixes a potential system hang.
>>>> Don't know why this patch isn't included if 'CONFIG_K8_REV_F_SUPPORT == 1'.
>>>>
>>>> Signed-off-by: Josef Kellermann  <mailto://seppk at arcor.de><seppk at arcor.de> <mailto://seppk at arcor.de>
>>>>
>>>
>> Ok,
>> now it gets executed in both cases.
>>
>> Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>
>>
> 

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From hagigatali at gmail.com  Sun Feb  6 14:25:03 2011
From: hagigatali at gmail.com (ali hagigat)
Date: Sun, 6 Feb 2011 16:55:03 +0330
Subject: [coreboot] how Coreboot keeps the right offsets of the sections
Message-ID: <AANLkTinX0ju8=eU+TcAZ-ehapTs0d5npD6FHbM8WZ9p7@mail.gmail.com>

Coreboot starts by compiling and linking some C-Assembly files as
bootblock core and then compile and link them by some linker script
files. the result is bootblock.elf but then it executes:
objcopy -O binary bootblock.elf coreboot.bootblock
The elf file probably has some headers which specify the VMA-LMA
addresses of the sections but after objcopy command all these headers
are removed.
So how cbfstool can write those sections in a correct relative
position? While all the information of the addresses have been deleted
by objcopy?(how .reset section is written from 0xfffffff0)
My another question is that the top content of ROM, like 0xffffff00 is
probably written from the beginning of coreboot.rom so does flash
utility writes coreboot.rom from 0xffffffff or the end of BIOS EEPROM?



From seppk at arcor.de  Sun Feb  6 20:40:54 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Sun, 06 Feb 2011 20:40:54 +0100
Subject: [coreboot] Support for siemens sitemp_g1p1 mainboard
Message-ID: <4D4EF946.3040200@arcor.de>

Added support for the Siemens 'sitemp_g1p1' mainboard.
The board is similar to the AMD dbm690t. I adapt the code from dbm690t 
according to customer requirement specification.
I have been testing Linux as well as Windows XP booting on this board.

Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>

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From stefan.reinauer at coreboot.org  Mon Feb  7 00:03:29 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 7 Feb 2011 00:03:29 +0100
Subject: [coreboot] Reliably build any Kconfig-based SeaBIOS revision
In-Reply-To: <20110203213305.GB28701@coreboot.org>
References: <20110129202608.10621.qmail@stuge.se>
	<20110203213305.GB28701@coreboot.org>
Message-ID: <20110206230329.GA12147@coreboot.org>

* Stefan Reinauer <stefan.reinauer at coreboot.org> [110203 22:33]:
> * Peter Stuge <peter at stuge.se> [110129 21:26]:
> > See patch.
> > 
> > The new TAG-stable points to the very latest commit in seabios.git,
> > which may not be quite right, but both stable and master must be
> > using Kconfig.
> > 
> > 
> > //Peter
> 
> slightly reworked to get rid of the perl calls (and to work with the
> latest HEAD version with options that are hidden during defconfig so a
> perl call would not replace them.
> 
> Reliably build arbitrary Kconfig-based revisions of SeaBIOS
>
> The reliability is accomplished by checking out the user's desired SeaBIOS
> tag into a branch named 'coreboot' in the local SeaBIOS git repository.
> Thanks to the use of a branch TAG-$(CONFIG_SEABIOS_..) can refer to any
> commitish at all in the SeaBIOS git repo.
>
> Configuration is done by make defconfig followed by enabling of several
> coreboot-specific Kconfig options for SeaBIOS using perl.
>
> Signed-off-by: Peter Stuge <peter at stuge.se>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Unless there's a reason not to, please commit the revised version (plus
the one line change to src/arch/x86/Makefile.inc which I forgot to diff)

Stefan



From hagigatali at gmail.com  Mon Feb  7 14:04:01 2011
From: hagigatali at gmail.com (ali hagigat)
Date: Mon, 7 Feb 2011 16:34:01 +0330
Subject: [coreboot] gcc in coreboot
Message-ID: <AANLkTik9WNodYSojTCRLyh=tYM0LshEqBvAP0xKBAYDy@mail.gmail.com>

If I want to run gcc, ld , as from elf32-i386 toolchain, should i
change the file .xcompile in the root directory of Coreboot?
and change the following line:
CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none
to:
CC:=util/crossgcc/xgcc/i386-elf/bin/gcc -Wa,--divide
-fno-stack-protector -Wl,--build-id=none

Will that be enough? (no need to change the system header files paths?
or other thing?)
Sorry to take up the time of people of the mailing list and thank you
all in advance.



From patrick at georgi-clan.de  Mon Feb  7 14:51:57 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 07 Feb 2011 14:51:57 +0100
Subject: [coreboot] gcc in coreboot
In-Reply-To: <AANLkTik9WNodYSojTCRLyh=tYM0LshEqBvAP0xKBAYDy@mail.gmail.com>
References: <AANLkTik9WNodYSojTCRLyh=tYM0LshEqBvAP0xKBAYDy@mail.gmail.com>
Message-ID: <mailman.4214.1355071865.16123.coreboot@coreboot.org>

Am Montag, 7. Februar 2011, um 16:34:01 schrieb ali hagigat:
> Will that be enough? (no need to change the system header files paths?
> or other thing?)
Simply remove .xcompile - it's regenerated by the util/xcompile/xcompile tool 
before next build, and it should find the cross compiler automatically.


Patrick



From svn at coreboot.org  Mon Feb  7 16:00:01 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 07 Feb 2011 16:00:01 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1PmSZN-0001C6-U5@ra.coresystems.de>

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From ivaylo at e-valkov.org  Mon Feb  7 17:24:01 2011
From: ivaylo at e-valkov.org (Ivaylo Valkov)
Date: Mon, 07 Feb 2011 18:24:01 +0200
Subject: [coreboot] [PATCH] RS690 code booting RS740 with ECS A740GM-M
In-Reply-To: <87hbcyw1vp.fsf@e-valkov.org> (Ivaylo Valkov's message of "Mon,
	24 Jan 2011 21:14:02 +0200")
References: <87bp3cy4d6.fsf@e-valkov.org> <20110123064253.1276.qmail@stuge.se>
	<87hbcyw1vp.fsf@e-valkov.org>
Message-ID: <87k4hb95jy.fsf@e-valkov.org>

Ivaylo Valkov writes:

> Peter Stuge writes:
>
>> Ivaylo Valkov wrote:
>>> Adds RS740 HT and internal graphics PCI ids. 
>>> Adds support for RS740 in RS690 code (some of the fam10 code from RS780).
>>> Adds support for ECS A740GM-M.
>>> 
>>> This definitely needs more patches and fine-tuning. 
>>> Only tested on RS740.
>>
>> Please keep working on this and keep sending patches! I think in
>> particular splitting this up into individual patches will be
>> neccessary to get anyone to really take a look at it.
>
> In that case I will split it like this:
> * patch for PCI IDs
> * patch for RS690 code (gfx, ht, early_setup)
> * patch for ECS A740GM-M with files from multiple boards sources and modifications
> * patch for ECS A740GM-M with directly copied files from other boards

Hello, all

I am trying to test my patches against trunk. Unfortunately I am unable
to build on my main system using the development release of
Trisquel. I've tested with r6275 where everything used to work. The
build process breaks there as well:

    CC         cpu/amd/mtrr/amd_mtrr.ramstage.o
    CC         cpu/amd/microcode/microcode.ramstage.o
    CC         cpu/x86/lapic/lapic.ramstage.o
    CC         cpu/x86/lapic/lapic_cpu_init.ramstage.o
    CC         cpu/x86/lapic/secondary.ramstage.o
    CC         cpu/x86/cache/cache.ramstage.o
    CC         cpu/x86/pae/pgtbl.ramstage.o
    CC         cpu/x86/mtrr/mtrr.ramstage.o
    AR         coreboot.a
    CC         coreboot_ram.o
    CC         coreboot_ram
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards (from 0000000000140000 to 0000000000004000)
collect2: ld returned 1 exit status
make: *** [build/coreboot_ram] Error 1

The specified line is the last in the file. Recently I've upgraded to
the development release of Trisquel. This probably changed the ldd
version. There are no changes to coreboot_ram.ld in trunk since December
2010, so it must be ldd. I am able to build in gNewSense both trunk and
r6275.

Version of ldd in Trisquel 4.5 Slaine (develpomnet release), based on Ubuntu
10.10:
$ ldd --version
ldd (Ubuntu EGLIBC 2.12.1-0ubuntu10.2) 2.12.1

Version of ldd in gNewSense 3.0 MetaD, based on Debian lenny:
$ ldd --version
ldd (GNU libc) 2.7

Any suggestions?



From svn at coreboot.org  Mon Feb  7 21:16:40 2011
From: svn at coreboot.org (repository service)
Date: Mon, 07 Feb 2011 21:16:40 +0100
Subject: [coreboot] [commit] r6335 - in trunk: payloads/external/SeaBIOS
	src/arch/x86
Message-ID: <E1PmXVo-0001SY-JV@ra.coresystems.de>

Author: stuge
Date: Mon Feb  7 21:16:40 2011
New Revision: 6335
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6335

Log:
Reliably build arbitrary Kconfig-based revisions of SeaBIOS

Reliability is accomplished by checking out the desired SeaBIOS commitish
into a branch named 'coreboot' in the local SeaBIOS git repository. Using
a branch allows TAG-$(CONFIG_SEABIOS_..) to refer to any commitish in the
SeaBIOS git repo, not just branches and tags.

Configuration is done with make defconfig followed by enabling and
disabling of the relevant coreboot-specific SeaBIOS options by appending
to .config using echo. This works, because later entries in .config will
overwrite earlier ones.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/payloads/external/SeaBIOS/Makefile.inc
   trunk/src/arch/x86/Makefile.inc

Modified: trunk/payloads/external/SeaBIOS/Makefile.inc
==============================================================================
--- trunk/payloads/external/SeaBIOS/Makefile.inc	Sat Feb  5 14:32:56 2011	(r6334)
+++ trunk/payloads/external/SeaBIOS/Makefile.inc	Mon Feb  7 21:16:40 2011	(r6335)
@@ -1,31 +1,38 @@
 
 
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=rel-0.6.1.3
+TAG-$(CONFIG_SEABIOS_STABLE)=1efb10b9ea30c45a8c9c6230234fefa10d2886ed
 
-all: seabios
-
-seabios: patch
-	cd seabios; $(MAKE)
+unexport KCONFIG_AUTOCONFIG
 
-patch: checkout
-	test -r seabios/.patched || \
-	perl -pi -e "s,#define CONFIG_COREBOOT 0,#define CONFIG_COREBOOT 1,;" \
-		 -e "s,#define CONFIG_DEBUG_SERIAL 0,#define CONFIG_DEBUG_SERIAL 1,;" \
-		 -e "s,#define CONFIG_VGAHOOKS 0,#define CONFIG_VGAHOOKS 1,;" \
-		 seabios/src/config.h
-	touch seabios/.patched
+all: seabios
 
 checkout:
-	echo "Checking out SeaBIOS $(TAG-y)"
+	echo "    GIT        SeaBIOS $(TAG-y)"
 	test -d seabios && ( cd seabios; git fetch ) || \
-	git clone git://git.linuxtogo.org/home/kevin/seabios.git seabios
-	cd seabios; git checkout -m $(TAG-y)
+		git clone git://git.linuxtogo.org/home/kevin/seabios.git
+	cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)
+
+config: checkout
+	echo "    CONFIG     SeaBIOS $(TAG-y)"
+	$(MAKE) -C seabios defconfig
+	echo "CONFIG_COREBOOT=y" >> seabios/.config
+	echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config
+	echo "CONFIG_COREBOOT_FLASH=y" >> seabios/.config
+	echo "CONFIG_LZMA=y" >> seabios/.config
+	echo "CONFIG_FLASH_FLOPPY=y" >> seabios/.config
+	echo "CONFIG_VGAHOOKS=y" >> seabios/.config
+	# This shows how to force a previously set .config option *off*
+	#echo "# CONFIG_SMBIOS is not set" >> seabios/.config
+
+seabios: config
+	echo "    MAKE       SeaBIOS $(TAG-y)"
+	$(MAKE) -C seabios
 
 clean:
-	test -d seabios && (cd seabios; $(MAKE) clean) || exit 0
+	test -d seabios && $(MAKE) -C seabios clean || exit 0
 
 distclean:
 	rm -rf seabios
 
-.PHONY: seabios
+.PHONY: checkout config seabios clean distclean

Modified: trunk/src/arch/x86/Makefile.inc
==============================================================================
--- trunk/src/arch/x86/Makefile.inc	Sat Feb  5 14:32:56 2011	(r6334)
+++ trunk/src/arch/x86/Makefile.inc	Mon Feb  7 21:16:40 2011	(r6335)
@@ -278,6 +278,7 @@
 
 seabios:
 	$(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \
+			HOSTCC="$(HOSTCC)" \
 			CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \
 			OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \
 			CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \



From peter at stuge.se  Mon Feb  7 21:17:04 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 7 Feb 2011 21:17:04 +0100
Subject: [coreboot] Reliably build any Kconfig-based SeaBIOS revision
In-Reply-To: <20110206230329.GA12147@coreboot.org>
References: <20110129202608.10621.qmail@stuge.se>
	<20110203213305.GB28701@coreboot.org>
	<20110206230329.GA12147@coreboot.org>
Message-ID: <20110207201705.18300.qmail@stuge.se>

Stefan Reinauer wrote:
> > slightly reworked to get rid of the perl calls (and to work with the
> 
> Unless there's a reason not to, please commit the revised version (plus
> the one line change to src/arch/x86/Makefile.inc which I forgot to diff)

r6335


//Peter



From svn at coreboot.org  Mon Feb  7 21:44:38 2011
From: svn at coreboot.org (repository service)
Date: Mon, 07 Feb 2011 21:44:38 +0100
Subject: [coreboot] build service results for r6335
Message-ID: <E1PmXws-0001Ro-4d@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stuge" checked in revision 6335 to
the coreboot repository. This caused the following 
changes:

Change Log:
Reliably build arbitrary Kconfig-based revisions of SeaBIOS

Reliability is accomplished by checking out the desired SeaBIOS commitish
into a branch named 'coreboot' in the local SeaBIOS git repository. Using
a branch allows TAG-$(CONFIG_SEABIOS_..) to refer to any commitish in the
SeaBIOS git repo, not just branches and tags.

Configuration is done with make defconfig followed by enabling and
disabling of the relevant coreboot-specific SeaBIOS options by appending
to .config using echo. This works, because later entries in .config will
overwrite earlier ones.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


Build Log:
Compilation of a-trend:atc-6220 has been fixed


If something broke during this checkin please be a pain 
in stuge's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From jakllsch at kollasch.net  Mon Feb  7 22:15:36 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Mon, 7 Feb 2011 21:15:36 +0000
Subject: [coreboot] [patch] nvramtool hardware access on NetBSD
Message-ID: <20110207211536.GA8516@tarantulon.kollasch.net>

Add NetBSD support to nvramtool.

Signed-off-by: <jakllsch at kollasch.net>
-------------- next part --------------
Index: util/nvramtool/accessors/cmos-hw-unix.c
===================================================================
--- util/nvramtool/accessors/cmos-hw-unix.c	(revision 6334)
+++ util/nvramtool/accessors/cmos-hw-unix.c	(working copy)
@@ -17,6 +17,53 @@
 #if (defined(__MACH__) && defined(__APPLE__))
 #include <DirectIO/darwinio.h>
 #endif
+#if defined(__NetBSD__)
+#if defined(__i386__) || defined(__x86_64__) 
+#include <machine/sysarch.h>
+
+static inline void outb(uint8_t value, uint16_t port)
+{
+	asm volatile ("outb %b0,%w1": :"a" (value), "Nd" (port));
+}
+
+static inline uint8_t inb(uint16_t port)
+{
+	uint8_t value;
+	asm volatile ("inb %w1,%0":"=a" (value):"Nd" (port));
+	return value;
+}
+
+static inline void outw(uint16_t value, uint16_t port)
+{
+	asm volatile ("outw %w0,%w1": :"a" (value), "Nd" (port));
+}
+
+static inline uint16_t inw(uint16_t port)
+{
+	uint16_t value;
+	asm volatile ("inw %w1,%0":"=a" (value):"Nd" (port));
+	return value;
+}
+
+static inline void outl(uint32_t value, uint16_t port)
+{
+	asm volatile ("outl %0,%w1": :"a" (value), "Nd" (port));
+}
+
+static inline uint32_t inl(uint16_t port)
+{
+	uint32_t value;
+	asm volatile ("inl %1,%0":"=a" (value):"Nd" (port));
+	return value;
+}
+#endif
+#ifdef __x86_64__
+#define iopl x86_64_iopl
+#endif
+#ifdef __i386__
+#define iopl i386_iopl
+#endif
+#endif
 #define OUTB outb
 #define OUTW outw
 #define OUTL outl
Index: util/nvramtool/Makefile
===================================================================
--- util/nvramtool/Makefile	(revision 6334)
+++ util/nvramtool/Makefile	(working copy)
@@ -39,6 +39,9 @@
 ifeq ($(OS_ARCH), Darwin)
 LDFLAGS = -framework DirectIO
 endif
+ifeq ($(OS_ARCH), NetBSD)
+LDFLAGS = -l$(shell uname -p)
+endif
 
 all: dep $(PROGRAM)
 

From jakllsch at kollasch.net  Tue Feb  8 02:38:20 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 8 Feb 2011 01:38:20 +0000
Subject: [coreboot] what was 'set' in struct io_info for?
Message-ID: <20110208013820.GC8516@tarantulon.kollasch.net>

Hi,

I noticed that, other than initialization in almost every superio, the
'set' member of struct io_info doesn't seem to be referenced by the pnp
code.  Worth the removing?

	Jonathan Kollasch



From jakllsch at kollasch.net  Tue Feb  8 02:41:43 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 8 Feb 2011 01:41:43 +0000
Subject: [coreboot] [PATCH] Fix issue with Winbond W83627EHG MIDI driver
In-Reply-To: <4D4DAB09.3080606@gmail.com>
References: <4D4DA9E8.9060008@gmail.com>
 <4D4DAB09.3080606@gmail.com>
Message-ID: <20110208014143.GD8516@tarantulon.kollasch.net>

On Sat, Feb 05, 2011 at 09:54:49PM +0200, Alex G. wrote:
> Sorry about forgetting to attach the patch.
> 
> Alex
> 
> On 02/05/2011 09:50 PM, Alex G. wrote:
> > (See Patch)
> > 
> > This fixes the
> > "ERROR: device PNP: 002e.207 index 98 has no mask."
> > that I have been getting on the W83627EHG.
> > 
> > Alex
> > 
> > 
> 

> Fixes a problem with the W8327EHG driver, where the midi device
> could get initialised with no mask.
> 
> Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
> 
> Index: src/superio/winbond/w83627ehg/superio.c
> ===================================================================
> --- src/superio/winbond/w83627ehg/superio.c	(revision 6323)
> +++ src/superio/winbond/w83627ehg/superio.c	(working copy)
> @@ -189,7 +189,7 @@
>  	{ &ops, W83627EHG_HWM,  PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
>  
>  	{ &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, },
> -	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07fe, 4}, },
> +	{ &ops, W83627EHG_MIDI, PNP_IO0 | PNP_IRQ0, {0x07fe, 4}, },
>  	{ &ops, W83627EHG_GPIO1, },
>  	{ &ops, W83627EHG_GPIO2, },
>  	{ &ops, W83627EHG_GPIO3, },

I don't think this is the right fix.
The datasheet says the MIDI BAR is at 62h, 63h.
Hence the mask needs to be in the second position, not the first.

Maybe try something like: 
{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, }

	Jonathan Kollasch



From mr.nuke.me at gmail.com  Tue Feb  8 02:48:44 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Tue, 08 Feb 2011 03:48:44 +0200
Subject: [coreboot] [PATCH] Fix issue with Winbond W83627EHG MIDI driver
In-Reply-To: <20110208014143.GD8516@tarantulon.kollasch.net>
References: <4D4DA9E8.9060008@gmail.com> <4D4DAB09.3080606@gmail.com>
	<20110208014143.GD8516@tarantulon.kollasch.net>
Message-ID: <4D50A0FC.3090108@gmail.com>

>> Index: src/superio/winbond/w83627ehg/superio.c
>> ===================================================================
>> --- src/superio/winbond/w83627ehg/superio.c	(revision 6323)
>> +++ src/superio/winbond/w83627ehg/superio.c	(working copy)
>> @@ -189,7 +189,7 @@
>>  	{ &ops, W83627EHG_HWM,  PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
>>  
>>  	{ &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, },
>> -	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07fe, 4}, },
>> +	{ &ops, W83627EHG_MIDI, PNP_IO0 | PNP_IRQ0, {0x07fe, 4}, },
>>  	{ &ops, W83627EHG_GPIO1, },
>>  	{ &ops, W83627EHG_GPIO2, },
>>  	{ &ops, W83627EHG_GPIO3, },
> 
> I don't think this is the right fix.
> The datasheet says the MIDI BAR is at 62h, 63h.
> Hence the mask needs to be in the second position, not the first.
> 
> Maybe try something like: 
> { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, }
> 
> 	Jonathan Kollasch

Thanks. Find attached the updated micropatch.

Alex
-------------- next part --------------
A non-text attachment was scrubbed...
Name: W83627ehg_MIDI_fix.patch
Type: text/x-patch
Size: 813 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110208/3b7f82ff/attachment.patch>

From jakllsch at kollasch.net  Tue Feb  8 03:29:47 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 8 Feb 2011 02:29:47 +0000
Subject: [coreboot] [PATCH] Fix issue with Winbond W83627EHG MIDI driver
In-Reply-To: <4D50A0FC.3090108@gmail.com>
References: <4D4DA9E8.9060008@gmail.com> <4D4DAB09.3080606@gmail.com>
	<20110208014143.GD8516@tarantulon.kollasch.net>
	<4D50A0FC.3090108@gmail.com>
Message-ID: <20110208022947.GE8516@tarantulon.kollasch.net>

On Tue, Feb 08, 2011 at 03:48:44AM +0200, Alex G. wrote:
> > Maybe try something like: 
> > { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, }
> > 
> > 	Jonathan Kollasch
> 
> Thanks. Find attached the updated micropatch.
> 
> Alex

> Fixes a problem with the W8327EHG driver, where the midi device
> could get initialised with no mask.
> 
> Based on input from Jonathan Kollasch <jakllsch at kollasch.net>
> 
> Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
> 
> 
> Index: src/superio/winbond/w83627ehg/superio.c
> ===================================================================
> --- src/superio/winbond/w83627ehg/superio.c	(revision 6323)
> +++ src/superio/winbond/w83627ehg/superio.c	(working copy)
> @@ -189,7 +189,7 @@
>  	{ &ops, W83627EHG_HWM,  PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
>  
>  	{ &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, },
> -	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07fe, 4}, },
> +	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, },
>  	{ &ops, W83627EHG_GPIO1, },
>  	{ &ops, W83627EHG_GPIO2, },
>  	{ &ops, W83627EHG_GPIO3, },

Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>



From svn at coreboot.org  Tue Feb  8 03:36:39 2011
From: svn at coreboot.org (repository service)
Date: Tue, 08 Feb 2011 03:36:39 +0100
Subject: [coreboot] [commit] r6336 - trunk/src/superio/winbond/w83627ehg
Message-ID: <E1PmdRX-00071F-Fp@ra.coresystems.de>

Author: jakllsch
Date: Tue Feb  8 03:36:39 2011
New Revision: 6336
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6336

Log:
Place the W83627EHG MIDI base address mask in the correct position.
Corrects "index 98 has no mask" error at runtime.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>

Modified:
   trunk/src/superio/winbond/w83627ehg/superio.c

Modified: trunk/src/superio/winbond/w83627ehg/superio.c
==============================================================================
--- trunk/src/superio/winbond/w83627ehg/superio.c	Mon Feb  7 21:16:40 2011	(r6335)
+++ trunk/src/superio/winbond/w83627ehg/superio.c	Tue Feb  8 03:36:39 2011	(r6336)
@@ -189,7 +189,7 @@
 	{ &ops, W83627EHG_HWM,  PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
 
 	{ &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, },
-	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07fe, 4}, },
+	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, },
 	{ &ops, W83627EHG_GPIO1, },
 	{ &ops, W83627EHG_GPIO2, },
 	{ &ops, W83627EHG_GPIO3, },



From jakllsch at kollasch.net  Tue Feb  8 03:37:41 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 8 Feb 2011 02:37:41 +0000
Subject: [coreboot] [PATCH] Fix issue with Winbond W83627EHG MIDI driver
In-Reply-To: <20110208022947.GE8516@tarantulon.kollasch.net>
References: <4D4DA9E8.9060008@gmail.com> <4D4DAB09.3080606@gmail.com>
	<20110208014143.GD8516@tarantulon.kollasch.net>
	<4D50A0FC.3090108@gmail.com>
	<20110208022947.GE8516@tarantulon.kollasch.net>
Message-ID: <20110208023741.GF8516@tarantulon.kollasch.net>

On Tue, Feb 08, 2011 at 02:29:47AM +0000, Jonathan A. Kollasch wrote:
> On Tue, Feb 08, 2011 at 03:48:44AM +0200, Alex G. wrote:
> > > Maybe try something like: 
> > > { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, }
> > > 
> > > 	Jonathan Kollasch
> > 
> > Thanks. Find attached the updated micropatch.
> > 
> > Alex
> 
> > Fixes a problem with the W8327EHG driver, where the midi device
> > could get initialised with no mask.
> > 
> > Based on input from Jonathan Kollasch <jakllsch at kollasch.net>
> > 
> > Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
> > 
> > 
> > Index: src/superio/winbond/w83627ehg/superio.c
> > ===================================================================
> > --- src/superio/winbond/w83627ehg/superio.c	(revision 6323)
> > +++ src/superio/winbond/w83627ehg/superio.c	(working copy)
> > @@ -189,7 +189,7 @@
> >  	{ &ops, W83627EHG_HWM,  PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
> >  
> >  	{ &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, },
> > -	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07fe, 4}, },
> > +	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, },
> >  	{ &ops, W83627EHG_GPIO1, },
> >  	{ &ops, W83627EHG_GPIO2, },
> >  	{ &ops, W83627EHG_GPIO3, },
> 
> Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>
 
Committed in r6336.



From svn at coreboot.org  Tue Feb  8 09:37:47 2011
From: svn at coreboot.org (repository service)
Date: Tue, 08 Feb 2011 09:37:47 +0100
Subject: [coreboot] [commit] r6337 - trunk
Message-ID: <E1Pmj51-0004pm-MP@ra.coresystems.de>

Author: oxygene
Date: Tue Feb  8 09:37:47 2011
New Revision: 6337
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6337

Log:
Fix cmos-files-y for relative paths

Thanks to Josef Kellermann <seppk at arcor.de> for reporting the issue.
Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/Makefile

Modified: trunk/Makefile
==============================================================================
--- trunk/Makefile	Tue Feb  8 03:36:39 2011	(r6336)
+++ trunk/Makefile	Tue Feb  8 09:37:47 2011	(r6337)
@@ -208,10 +208,10 @@
 			$$(subst $(top)/,, \
 			$$(abspath $$(addprefix $(dir $(1)),$$($(type)-y)))))) \
 	$(foreach file,$(cbfs-files-y), \
-		$(if $(wildcard $(dir $(1))$$($(file)-file)), \
-			$(eval tmp-cbfs-file:= $(wildcard $(dir $(1))$$($(file)-file))), \
-			$(eval tmp-cbfs-file:= $$($(file)-file))) \
-		$(eval cbfs-files += $(tmp-cbfs-file)|$(file)|$$($(file)-type)|$$($(file)-position)) \
+		$(if $(wildcard $(dir $(1))$($(file)-file)), \
+			$(eval tmp-cbfs-file:= $(wildcard $(dir $(1))$($(file)-file))), \
+			$(eval tmp-cbfs-file:= $($(file)-file))) \
+		$(eval cbfs-files += $(tmp-cbfs-file)|$(file)|$($(file)-type)|$($(file)-position)) \
 		$(eval $(file)-name:=) \
 		$(eval $(file)-type:=) \
 		$(eval $(file)-position:=)) \



From Patrick.Georgi at secunet.com  Tue Feb  8 09:41:57 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Tue, 8 Feb 2011 09:41:57 +0100
Subject: [coreboot] cmos recovery feature
In-Reply-To: <4D4AC534.90109@arcor.de>
References: <4D4AC534.90109@arcor.de>
Message-ID: <1297154517.2438.16.camel@linux-0a8x.site>

Am Donnerstag, den 03.02.2011, 16:09 +0100 schrieb Josef Kellermann:
> I've added this to my mainboards Makefile.inc:
> 
> cbfs-files-y += cmos.default
> cmos.default-name = cmos.default
> cmos.default-type = 0xaa
> 
> cmos.default also exists in mainboard dir.
> 
> I've also tried with:
> cmos.default-file = cmos.default
> 
> Any idea ?
Fixed in r6337.


Thanks,
Patrick
-- 
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
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From Patrick.Georgi at secunet.com  Tue Feb  8 11:26:00 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Tue, 8 Feb 2011 11:26:00 +0100
Subject: [coreboot] [patch] nvramtool hardware access on NetBSD
In-Reply-To: <20110207211536.GA8516@tarantulon.kollasch.net>
References: <20110207211536.GA8516@tarantulon.kollasch.net>
Message-ID: <1297160760.9475.2.camel@linux-0a8x.site>

Am Montag, den 07.02.2011, 21:15 +0000 schrieb Jonathan A. Kollasch:
> Add NetBSD support to nvramtool.
> 
> Signed-off-by: <jakllsch at kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

More general question (shouldn't stop anyone from committing this
patch): Should we move hardware access code to directio and use its API
on all platforms (not just Darwin, and - in theory - win32)?
Though in that case, we might want to import directio to the coreboot
tree.

Patrick
-- 
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
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From peter at stuge.se  Tue Feb  8 12:31:18 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 8 Feb 2011 12:31:18 +0100
Subject: [coreboot] [patch] nvramtool hardware access on NetBSD
In-Reply-To: <20110207211536.GA8516@tarantulon.kollasch.net>
References: <20110207211536.GA8516@tarantulon.kollasch.net>
Message-ID: <20110208113118.13563.qmail@stuge.se>

Jonathan A. Kollasch wrote:
> Add NetBSD support to nvramtool.
> 
> Signed-off-by: <jakllsch at kollasch.net>

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Tue Feb  8 17:07:50 2011
From: svn at coreboot.org (repository service)
Date: Tue, 08 Feb 2011 17:07:50 +0100
Subject: [coreboot] [commit] r6338 - in trunk/util/nvramtool: . accessors
Message-ID: <E1Pmq6Y-0003ia-3D@ra.coresystems.de>

Author: jakllsch
Date: Tue Feb  8 17:07:49 2011
New Revision: 6338
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6338

Log:
Add NetBSD support to nvramtool.

Signed-off-by: <jakllsch at kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/util/nvramtool/Makefile
   trunk/util/nvramtool/accessors/cmos-hw-unix.c

Modified: trunk/util/nvramtool/Makefile
==============================================================================
--- trunk/util/nvramtool/Makefile	Tue Feb  8 09:37:47 2011	(r6337)
+++ trunk/util/nvramtool/Makefile	Tue Feb  8 17:07:49 2011	(r6338)
@@ -39,6 +39,9 @@
 ifeq ($(OS_ARCH), Darwin)
 LDFLAGS = -framework DirectIO
 endif
+ifeq ($(OS_ARCH), NetBSD)
+LDFLAGS = -l$(shell uname -p)
+endif
 
 all: dep $(PROGRAM)
 

Modified: trunk/util/nvramtool/accessors/cmos-hw-unix.c
==============================================================================
--- trunk/util/nvramtool/accessors/cmos-hw-unix.c	Tue Feb  8 09:37:47 2011	(r6337)
+++ trunk/util/nvramtool/accessors/cmos-hw-unix.c	Tue Feb  8 17:07:49 2011	(r6338)
@@ -17,6 +17,53 @@
 #if (defined(__MACH__) && defined(__APPLE__))
 #include <DirectIO/darwinio.h>
 #endif
+#if defined(__NetBSD__)
+#if defined(__i386__) || defined(__x86_64__) 
+#include <machine/sysarch.h>
+
+static inline void outb(uint8_t value, uint16_t port)
+{
+	asm volatile ("outb %b0,%w1": :"a" (value), "Nd" (port));
+}
+
+static inline uint8_t inb(uint16_t port)
+{
+	uint8_t value;
+	asm volatile ("inb %w1,%0":"=a" (value):"Nd" (port));
+	return value;
+}
+
+static inline void outw(uint16_t value, uint16_t port)
+{
+	asm volatile ("outw %w0,%w1": :"a" (value), "Nd" (port));
+}
+
+static inline uint16_t inw(uint16_t port)
+{
+	uint16_t value;
+	asm volatile ("inw %w1,%0":"=a" (value):"Nd" (port));
+	return value;
+}
+
+static inline void outl(uint32_t value, uint16_t port)
+{
+	asm volatile ("outl %0,%w1": :"a" (value), "Nd" (port));
+}
+
+static inline uint32_t inl(uint16_t port)
+{
+	uint32_t value;
+	asm volatile ("inl %1,%0":"=a" (value):"Nd" (port));
+	return value;
+}
+#endif
+#ifdef __x86_64__
+#define iopl x86_64_iopl
+#endif
+#ifdef __i386__
+#define iopl i386_iopl
+#endif
+#endif
 #define OUTB outb
 #define OUTW outw
 #define OUTL outl



From jakllsch at kollasch.net  Tue Feb  8 17:08:21 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 8 Feb 2011 16:08:21 +0000
Subject: [coreboot] [patch] nvramtool hardware access on NetBSD
In-Reply-To: <20110207211536.GA8516@tarantulon.kollasch.net>
References: <20110207211536.GA8516@tarantulon.kollasch.net>
Message-ID: <20110208160821.GI8516@tarantulon.kollasch.net>

r6338.



From SVotier at drs-ds.com  Tue Feb  8 21:15:49 2011
From: SVotier at drs-ds.com (Votier, Sean (DS-1))
Date: Tue, 8 Feb 2011 15:15:49 -0500
Subject: [coreboot] Help with RX serial interrupts?
Message-ID: <26AF4B58BBCBEE4686FEBEF7B6B8081F13DD03@DSHERNMAIL.herndon.drs-ds.master>

Designation: Non-SSA/Finmeccanica 

Hi all.

I would like to apologise for being a lurker on this list and only
popping up when I need help. But I need help...........

I've run into an issue that has been stumping my for the last couple of
weeks. 

I'm developing bios code for a GE CR-11 Compact PCI board.

The chips I'm working with are:

1.06 Mhz Pentium M

E7520 Northbridge

6300ESB Southbridge

I'm initialising the SIU in the Southbridge. I have the port configured.
I can see data transmitted and received from and to the serial port
using a scope on the serial cable and also on my emulator but I can't
seem to get the receive side to generate an interrupt. Does anyone have
experience with serial interrupts on this hardware? Can you run through
the steps involved for a very simple rx interrupt config just in case I
missed something in the Intel docs. Know of an pitfalls?

 

    Thanks in advance for the help.

                  Sean 

 

 

3.1.1001

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From mr.nuke.me at gmail.com  Tue Feb  8 22:15:03 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Tue, 08 Feb 2011 23:15:03 +0200
Subject: [coreboot] Help with RX serial interrupts?
In-Reply-To: <26AF4B58BBCBEE4686FEBEF7B6B8081F13DD03@DSHERNMAIL.herndon.drs-ds.master>
References: <26AF4B58BBCBEE4686FEBEF7B6B8081F13DD03@DSHERNMAIL.herndon.drs-ds.master>
Message-ID: <4D51B257.3080705@gmail.com>

Are you sure it's not just a bad PIC/APIC config?

Alex

On 02/08/2011 10:15 PM, Votier, Sean (DS-1) wrote:
> Designation: Non-SSA/Finmeccanica
> 
> Hi all.
> 
> I would like to apologise for being a lurker on this list and only
> popping up when I need help. But I need help???..
> 
> I?ve run into an issue that has been stumping my for the last couple of
> weeks.
> 
> I?m developing bios code for a GE CR-11 Compact PCI board.
> 
> The chips I?m working with are:
> 
> 1.06 Mhz Pentium M
> 
> E7520 Northbridge
> 
> 6300ESB Southbridge
> 
> I?m initialising the SIU in the Southbridge. I have the port configured.
> I can see data transmitted and received from and to the serial port
> using a scope on the serial cable and also on my emulator but I can?t
> seem to get the receive side to generate an interrupt. Does anyone have
> experience with serial interrupts on this hardware? Can you run through
> the steps involved for a very simple rx interrupt config just in case I
> missed something in the Intel docs. Know of an pitfalls?



From mr.nuke.me at gmail.com  Tue Feb  8 22:37:38 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Tue, 08 Feb 2011 23:37:38 +0200
Subject: [coreboot] [PATCH] Fix some errata for AMD Family F processors
Message-ID: <4D51B7A2.1000702@gmail.com>

See patch for detailed description.

Alex



From mr.nuke.me at gmail.com  Tue Feb  8 22:40:06 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Tue, 08 Feb 2011 23:40:06 +0200
Subject: [coreboot] [PATCH] Fix some errata for AMD Family F processors
In-Reply-To: <4D51B7A2.1000702@gmail.com>
References: <4D51B7A2.1000702@gmail.com>
Message-ID: <4D51B836.9070700@gmail.com>

On 02/08/2011 11:37 PM, Alex G. wrote:
> See patch for detailed description.
> 
> Alex

I should really attach the patch first before writing anything. Sorry
about that. Here's the patch.

Alex
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From mr.nuke.me at gmail.com  Tue Feb  8 23:22:00 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 09 Feb 2011 00:22:00 +0200
Subject: [coreboot] Help with RX serial interrupts?
In-Reply-To: <26AF4B58BBCBEE4686FEBEF7B6B8081F13DD14@DSHERNMAIL.herndon.drs-ds.master>
References: <26AF4B58BBCBEE4686FEBEF7B6B8081F13DD03@DSHERNMAIL.herndon.drs-ds.master>
	<4D51B257.3080705@gmail.com>
	<26AF4B58BBCBEE4686FEBEF7B6B8081F13DD14@DSHERNMAIL.herndon.drs-ds.master>
Message-ID: <4D51C208.207@gmail.com>

On 02/08/2011 11:32 PM, Votier, Sean (DS-1) wrote:
> Designation:  Non-SSA/Finmeccanica  
> 
> 
> Thanks for the reply Alex.

I'll do my best to help as much as I can. Though make sure next time you
hit the "reply all" or "reply list" button, as your message didn't make
it to the list.

> No, I'm not totally sure. I've looked through the docs and picked the
> values for the registers that seem appropriate. 
There's the problem right there. There is a big difference between
"seems" and "are".
I'm working on a K8T800 board, the southbridge containing the IOAPIC is
already supported, and yet it still doesn't work. Try to rip off as much
data as you can from the mfg BIOS.
That's all I can tell you, I'm not an expert in the field.

> I looked though the core
> boot code to see what was in there but their IRQ scheme it's much more
> complicated than I need and it didn't lend itself well to my particular
> situation. The problem with IRQ's is that they are a bitch to
> troubleshoot, particularly when the signals are all on the silicon so
> you can't put a scope on them :(
> 
Coreboot's scheme is fairly straightforward. To my understanding, it
sets up the IOAPICs as virtual-wire, compliant with the Intel MP spec
(which I read last night :P ). To software, this looks (should look)
just like PIC mode.

Alex
> 
>    Sean
> 
> 
> -----Original Message-----
> From: coreboot-bounces+svotier=drs-ds.com at coreboot.org
> [mailto:coreboot-bounces+svotier=drs-ds.com at coreboot.org] On Behalf Of
> Alex G.
> Sent: Tuesday, February 08, 2011 4:15 PM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] Help with RX serial interrupts?
> 
> Are you sure it's not just a bad PIC/APIC config?
> 
> Alex
> 
> On 02/08/2011 10:15 PM, Votier, Sean (DS-1) wrote:
>> Designation: Non-SSA/Finmeccanica
>>
>> Hi all.
>>
>> I would like to apologise for being a lurker on this list and only 
>> popping up when I need help. But I need help...........
>>
>> I've run into an issue that has been stumping my for the last couple 
>> of weeks.
>>
>> I'm developing bios code for a GE CR-11 Compact PCI board.
>>
>> The chips I'm working with are:
>>
>> 1.06 Mhz Pentium M
>>
>> E7520 Northbridge
>>
>> 6300ESB Southbridge
>>
>> I'm initialising the SIU in the Southbridge. I have the port
> configured.
>> I can see data transmitted and received from and to the serial port 
>> using a scope on the serial cable and also on my emulator but I can't 
>> seem to get the receive side to generate an interrupt. Does anyone 
>> have experience with serial interrupts on this hardware? Can you run 
>> through the steps involved for a very simple rx interrupt config just 
>> in case I missed something in the Intel docs. Know of an pitfalls?
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 
> 3.1.1001




From r.marek at assembler.cz  Tue Feb  8 23:32:29 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 08 Feb 2011 23:32:29 +0100
Subject: [coreboot] Help with RX serial interrupts?
In-Reply-To: <26AF4B58BBCBEE4686FEBEF7B6B8081F13DD03@DSHERNMAIL.herndon.drs-ds.master>
References: <26AF4B58BBCBEE4686FEBEF7B6B8081F13DD03@DSHERNMAIL.herndon.drs-ds.master>
Message-ID: <4D51C47D.7070001@assembler.cz>

Looks like a RX pin multiplexing is wrong, therefore no IRQ is generated?


Rudolf

PS: I go for a holiday so don't expect much answers from me.





From stefan.reinauer at coreboot.org  Wed Feb  9 00:38:04 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 9 Feb 2011 00:38:04 +0100
Subject: [coreboot] [patch] nvramtool hardware access on NetBSD
In-Reply-To: <1297160760.9475.2.camel@linux-0a8x.site>
References: <20110207211536.GA8516@tarantulon.kollasch.net>
	<1297160760.9475.2.camel@linux-0a8x.site>
Message-ID: <20110208233803.GA920@coreboot.org>

* Georgi, Patrick <Patrick.Georgi at secunet.com> [110208 11:26]:
> More general question (shouldn't stop anyone from committing this
> patch): Should we move hardware access code to directio and use its API
> on all platforms (not just Darwin, and - in theory - win32)?
> Though in that case, we might want to import directio to the coreboot
> tree.

+1




From hagigatali at gmail.com  Wed Feb  9 14:35:54 2011
From: hagigatali at gmail.com (ali hagigat)
Date: Wed, 9 Feb 2011 17:05:54 +0330
Subject: [coreboot] coreboot.rom
Message-ID: <AANLkTikJynd_cKisASA_9-pBnNBNZSSCHxifcqoq1XDA@mail.gmail.com>

How the file coreboot.rom is written on BIOS chip logically? Suppose
our BIOS chip is 1 mega bytes. We should read first byte from the
beginning of the file and write it to the address zero of BIOS chip
and continue this way?

I checked the content of build/coreboot.rom and the last byte was
0x0a!! Which is written probably on the top of our EEPROM. Right?
but src/arch/i386/init/ldscript.ld specifies the last byte as 0x00!!
SECTIONS {
	_ROMTOP = 0xfffffff0;
	. = _ROMTOP;
	.resetvector . : {
		*(.reset)
                . = 15 ;
                BYTE(0x00);
	}
}

Please help me with this puzzle. Thank you.



From peter at stuge.se  Wed Feb  9 20:25:57 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 9 Feb 2011 20:25:57 +0100
Subject: [coreboot] what was 'set' in struct io_info for?
In-Reply-To: <20110208013820.GC8516@tarantulon.kollasch.net>
References: <20110208013820.GC8516@tarantulon.kollasch.net>
Message-ID: <20110209192557.30453.qmail@stuge.se>

Jonathan A. Kollasch wrote:
> I noticed that, other than initialization in almost every superio, the
> 'set' member of struct io_info doesn't seem to be referenced by the pnp
> code.  Worth the removing?

What would it be used for? How does the patch to remove it look?


//Peter



From peter at stuge.se  Wed Feb  9 20:44:33 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 9 Feb 2011 20:44:33 +0100
Subject: [coreboot] how Coreboot keeps the right offsets of the sections
In-Reply-To: <AANLkTikJynd_cKisASA_9-pBnNBNZSSCHxifcqoq1XDA@mail.gmail.com>
	<AANLkTinX0ju8=eU+TcAZ-ehapTs0d5npD6FHbM8WZ9p7@mail.gmail.com>
References: <AANLkTikJynd_cKisASA_9-pBnNBNZSSCHxifcqoq1XDA@mail.gmail.com>
	<AANLkTinX0ju8=eU+TcAZ-ehapTs0d5npD6FHbM8WZ9p7@mail.gmail.com>
Message-ID: <20110209194433.745.qmail@stuge.se>

ali hagigat wrote:
> the top content of ROM, like 0xffffff00 is probably written from
> the beginning of coreboot.rom

No.


ali hagigat wrote:
> How the file coreboot.rom is written on BIOS chip logically?

Exactly the same way all other firmware images are written to flash
chips on PCs, and all other machines.

I'd expect you to already know this, with your experience from
firmware development on the PC.


> Suppose our BIOS chip is 1 mega bytes. We should read first byte
> from the beginning of the file and write it to the address zero of
> BIOS chip and continue this way?

Yes, coreboot.rom is a 1:1 representation of the flash chip contents.

This is fairly clear from the size of the file, and the fact that you
must select a flash chip size during configuration.


> I checked the content of build/coreboot.rom and the last byte was
> 0x0a!! Which is written probably on the top of our EEPROM. Right?

If it is written properly or not depends on what tool you use to
write to the flash chip.


> but src/arch/i386/init/ldscript.ld specifies the last byte as 0x00!!
> SECTIONS {
> 	_ROMTOP = 0xfffffff0;
> 	. = _ROMTOP;
> 	.resetvector . : {
> 		*(.reset)
>                 . = 15 ;
>                 BYTE(0x00);
> 	}
> }
> 
> Please help me with this puzzle. Thank you.

What is the concrete problem? You should not rule out that there are
binutils bugs. Just be happy that the reset vector has the right
opcodes.


//Peter



From svn at coreboot.org  Thu Feb 10 08:48:07 2011
From: svn at coreboot.org (repository service)
Date: Thu, 10 Feb 2011 08:48:07 +0100
Subject: [coreboot] [commit] r6339 - trunk/src/cpu/amd/model_fxx
Message-ID: <E1PnRG3-0007iw-Nb@ra.coresystems.de>

Author: oxygene
Date: Thu Feb 10 08:48:07 2011
New Revision: 6339
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6339

Log:
Fix a potential system hang by handling AMD Model F Erratum 89
a bit later.

Signed-off-by: Josef Kellermann <seppk at arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>

Modified:
   trunk/src/cpu/amd/model_fxx/model_fxx_init.c

Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/model_fxx_init.c	Tue Feb  8 17:07:49 2011	(r6338)
+++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c	Thu Feb 10 08:48:07 2011	(r6339)
@@ -384,23 +384,6 @@
 		wrmsr_amd(DC_CFG_MSR, msr);
 
 	}
-	/* I can't touch this msr on early buggy cpus */
-	if (!is_cpu_pre_b3()) {
-
-		/* Erratum 89 ... */
-		msr = rdmsr(NB_CFG_MSR);
-		msr.lo |= 1 << 3;
-
-		if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
-			/* D0 later don't need it */
-			/* Erratum 86 Disable data masking on C0 and
-			 * later processor revs.
-			 * FIXME this is only needed if ECC is enabled.
-			 */
-			msr.hi |= 1 << (36 - 32);
-		}
-		wrmsr(NB_CFG_MSR, msr);
-	}
 
 	/* Erratum 97 ... */
 	if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
@@ -445,7 +428,28 @@
 		msr.hi |= 1;
 		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 	}
+	
+#if CONFIG_K8_REV_F_SUPPORT == 0
+		/* I can't touch this msr on early buggy cpus */
+	if (!is_cpu_pre_b3())
+#endif
+	{
 
+		/* Erratum 89 ... */
+		msr = rdmsr(NB_CFG_MSR);
+		msr.lo |= 1 << 3;
+#if CONFIG_K8_REV_F_SUPPORT == 0
+		if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
+			/* D0 later don't need it */
+			/* Erratum 86 Disable data masking on C0 and
+			 * later processor revs.
+			 * FIXME this is only needed if ECC is enabled.
+			 */
+			msr.hi |= 1 << (36 - 32);
+		}
+#endif
+		wrmsr(NB_CFG_MSR, msr);
+	}
 	/* Erratum 122 */
 	msr = rdmsr(HWCR_MSR);
 	msr.lo |= 1 << 6;



From svn at coreboot.org  Thu Feb 10 08:51:52 2011
From: svn at coreboot.org (repository service)
Date: Thu, 10 Feb 2011 08:51:52 +0100
Subject: [coreboot] [commit] r6340 - in trunk/src: cpu/amd/model_fxx
	northbridge/amd/amdk8
Message-ID: <E1PnRJg-00044R-GY@ra.coresystems.de>

Author: oxygene
Date: Thu Feb 10 08:51:51 2011
New Revision: 6340
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6340

Log:
Implemented workaround for erratum 169, obsoleting erratum 131.
Workaround for 131 removed.
Changed workaround for erratum 110 to only include pre-revision-F
processors.

For details, check AMD publications:
#25759 (Errata for Fam F pre-revision F processors)
#33610 (Errata for Fam F revision F and later processor)

Based on work and previous patches by:
Rudolf Marek <r.marek at assembler.cz> 
Josef Kellermann <seppk at arcor.de>

Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/src/cpu/amd/model_fxx/model_fxx_init.c
   trunk/src/northbridge/amd/amdk8/coherent_ht.c

Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/model_fxx_init.c	Thu Feb 10 08:48:07 2011	(r6339)
+++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c	Thu Feb 10 08:51:51 2011	(r6340)
@@ -411,33 +411,35 @@
 	msr.hi |= 1 << (43 - 32);
 	wrmsr_amd(BU_CFG_MSR, msr);
 
+	/* Erratum 110 */
+	/* This erratum applies to D0 thru E6 revisions
+	 * Revision F and later are unaffected. There are two fixes
+	 * depending on processor revision.
+	 */
 	if (is_cpu_d0()) {
 		/* Erratum 110 ... */
 		msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
 		msr.hi |= 1;
 		wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
 	}
-#endif
 
-#if CONFIG_K8_REV_F_SUPPORT == 0
 	if (!is_cpu_pre_e0())
-#endif
 	{
 		/* Erratum 110 ... */
 		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
 		msr.hi |= 1;
 		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 	}
-	
+#endif
+
+
 #if CONFIG_K8_REV_F_SUPPORT == 0
-		/* I can't touch this msr on early buggy cpus */
+	/* I can't touch this msr on early buggy cpus */
 	if (!is_cpu_pre_b3())
 #endif
 	{
-
-		/* Erratum 89 ... */
 		msr = rdmsr(NB_CFG_MSR);
-		msr.lo |= 1 << 3;
+		
 #if CONFIG_K8_REV_F_SUPPORT == 0
 		if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
 			/* D0 later don't need it */
@@ -448,6 +450,18 @@
 			msr.hi |= 1 << (36 - 32);
 		}
 #endif
+		/* Erratum 89 ... */
+		/* Erratum 89 is mistakenly labeled as 88 in AMD pub #25759
+		 * It is correctly labeled as 89 on page 49 of the document
+		 * and in AMD pub#33610
+		 */
+		msr.lo |= 1 << 3;
+		/* Erratum 169 */
+		/* This supersedes erratum 131; 131 should not be applied with 169 
+		 * We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/
+		 */
+		msr.hi |= 1;
+		
 		wrmsr(NB_CFG_MSR, msr);
 	}
 	/* Erratum 122 */
@@ -455,12 +469,6 @@
 	msr.lo |= 1 << 6;
 	wrmsr(HWCR_MSR, msr);
 
-#if CONFIG_K8_REV_F_SUPPORT == 1
-	/* Erratum 131... */
-	msr = rdmsr(NB_CFG_MSR);
-	msr.lo |= 1 << 20;
-	wrmsr(NB_CFG_MSR, msr);
-#endif
 
 }
 

Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/coherent_ht.c	Thu Feb 10 08:48:07 2011	(r6339)
+++ trunk/src/northbridge/amd/amdk8/coherent_ht.c	Thu Feb 10 08:51:51 2011	(r6340)
@@ -1662,10 +1662,10 @@
 	unsigned node;
 	int needs_reset = 0;
 	for(node = 0; node < nodes; node++) {
-#if CONFIG_K8_REV_F_SUPPORT == 0
 		device_t dev;
 		uint32_t cmd;
 		dev = NODE_MC(node);
+#if CONFIG_K8_REV_F_SUPPORT == 0
 		if (is_cpu_pre_c0()) {
 
 			/* Errata 66
@@ -1708,6 +1708,20 @@
 			}
 		}
 #endif
+
+		
+#if CONFIG_K8_REV_F_SUPPORT == 0
+		/* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
+		if (!is_cpu_pre_b3())
+#endif
+		{
+			/* Errata 169 */
+			/* We also need to set some bits in NB_CFG_MSR, which is handled in src/cpu/amd/model_fxx/ */
+			cmd = pci_read_config32(dev, 0x68);
+			cmd &= ~(1 << 22);
+			cmd |= (1 << 21);
+			pci_write_config32(dev, 0x68, cmd);
+		}
 	}
 	return needs_reset;
 }



From svn at coreboot.org  Thu Feb 10 09:49:58 2011
From: svn at coreboot.org (repository service)
Date: Thu, 10 Feb 2011 09:49:58 +0100
Subject: [coreboot] [commit] r6341 - trunk/src/southbridge/amd/rs690
Message-ID: <E1PnSDu-0001FQ-EE@ra.coresystems.de>

Author: oxygene
Date: Thu Feb 10 09:49:57 2011
New Revision: 6341
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6341

Log:
RS690: Provide support for MMCONF.

If enabled, set up 0xe0000000..0xf0000000 as MMCONF
area. Must still be configured in per-board ACPI for
the OS to pick it up, so it's disabled by default.

Signed-off-by: Josef Kellermann<seppk at arcor.de>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/src/southbridge/amd/rs690/Kconfig
   trunk/src/southbridge/amd/rs690/ht.c

Modified: trunk/src/southbridge/amd/rs690/Kconfig
==============================================================================
--- trunk/src/southbridge/amd/rs690/Kconfig	Thu Feb 10 08:51:51 2011	(r6340)
+++ trunk/src/southbridge/amd/rs690/Kconfig	Thu Feb 10 09:49:57 2011	(r6341)
@@ -20,3 +20,10 @@
 config SOUTHBRIDGE_AMD_RS690
 	bool
 
+if SOUTHBRIDGE_AMD_RS690
+config EXT_CONF_SUPPORT
+	def_bool n
+	help
+	  Select if RS690 should be setup to support MMCONF.
+
+endif

Modified: trunk/src/southbridge/amd/rs690/ht.c
==============================================================================
--- trunk/src/southbridge/amd/rs690/ht.c	Thu Feb 10 08:51:51 2011	(r6340)
+++ trunk/src/southbridge/amd/rs690/ht.c	Thu Feb 10 09:49:57 2011	(r6341)
@@ -22,8 +22,93 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <lib.h>
 #include "rs690.h"
 
+static void ht_dev_set_resources(device_t dev)
+{
+#if CONFIG_EXT_CONF_SUPPORT == 1
+	unsigned reg;		
+	device_t k8_f1;
+	resource_t rbase, rend;
+	u32 base, limit;
+	struct resource *resource;
+	
+	printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
+	
+	resource = probe_resource(dev, 0x1C);
+	if (resource) {
+		set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible	
+		set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 1 << 30);	/* Enables writes to the BAR3 register. */
+		set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses 
+		pci_write_config32(dev, 0x1C, resource->base);
+		/* Enable MMCONFIG decoding. */
+		set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28);	/* PCIEMiscInit */
+		set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3 register. */
+		set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3
+		
+		// setup resource nonposted in k8 mmio
+		/* Get the base address */
+		rbase = resource->base;
+		/* Get the limit (rounded up) */
+		rend  = resource_end(resource);
+		printk(BIOS_DEBUG,"%s: %s[0x1C] base = %0llx limit = %0llx\n", __func__, dev_path(dev), rbase, rend);
+		k8_f1 = dev_find_slot(0,PCI_DEVFN(0x18,1));
+		// find a not assigned resource
+		for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
+			base = pci_read_config32(k8_f1,reg);
+			limit = pci_read_config32(k8_f1,reg+4);
+			if( !(base & 3) ) break; // found a not assigned resource
+		}
+		if( !(base & 3) ) {
+			u32 sblk;
+			device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+			/* Remember this resource has been stored. */
+			resource->flags |= IORESOURCE_STORED;
+			report_resource_stored(dev, resource, " <mmconfig>");
+			/* Get SBLink value (HyperTransport I/O Hub Link ID). */
+			sblk = (pci_read_config32(k8_f0, 0x64) >> 8) & 0x3;
+			base  &= 0x000000f0;
+			base  |= ((rbase >> 8) & 0xffffff00);
+			base  |= 3;
+			limit &= 0x00000048;
+			limit |= ((rend >> 8) & 0xffffff00);
+			limit |= (sblk << 4);
+			limit |= (1 << 7); 
+			printk(BIOS_INFO, "%s <- index %x base %04x limit %04x\n", dev_path(k8_f1), reg, base, limit);
+			pci_write_config32(k8_f1, reg+4, limit); 
+			pci_write_config32(k8_f1, reg, base);
+		}
+	}
+#endif
+	pci_dev_set_resources(dev);
+}
+
+static void ht_dev_read_resources(device_t dev)
+{
+#if CONFIG_EXT_CONF_SUPPORT == 1
+	struct resource *res;
+	
+	printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);	
+	set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3	
+#endif
+
+	pci_dev_read_resources(dev);
+	
+#if CONFIG_EXT_CONF_SUPPORT == 1
+	/* Add an MMCONFIG resource. */
+	res = new_resource(dev, 0x1C);
+	res->base = EXT_CONF_BASE_ADDRESS;
+	res->size = 256 * 1024 * 1024; // 256 busses, 1MB memory space each
+	res->align = log2(res->size);
+	res->gran = log2(res->size);
+	res->limit = 0xffffffffffffffffULL;	/* 64bit */
+	res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED;
+	
+	compact_resources(dev);
+#endif	
+}
+
 /* for UMA internal graphics */
 void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)
 {
@@ -80,8 +165,8 @@
 };
 
 static struct device_operations ht_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
+	.read_resources = ht_dev_read_resources,
+	.set_resources = ht_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init = pcie_init,
 	.scan_bus = 0,



From mark.marshall at csr.com  Thu Feb 10 11:52:37 2011
From: mark.marshall at csr.com (Mark Marshall)
Date: Thu, 10 Feb 2011 10:52:37 +0000
Subject: [coreboot] what was 'set' in struct io_info for?
In-Reply-To: <20110208013820.GC8516@tarantulon.kollasch.net>
References: <20110208013820.GC8516@tarantulon.kollasch.net>
Message-ID: <ij0g1l$32k$1@dough.gmane.org>

On 08/02/2011 01:38, Jonathan A. Kollasch wrote:
> Hi,
>
> I noticed that, other than initialization in almost every superio, the
> 'set' member of struct io_info doesn't seem to be referenced by the pnp
> code.  Worth the removing?
>
> 	Jonathan Kollasch
>

I found the same thing as you a while ago.  The io_info structure in 
pnp.h is never referenced by the code, and it's purpose is never really 
defined anywhere.  If you change the name to something else (just in the 
header file) the code still all compiles, so I'd say remove it.

I also asked about it on the news group, but got no reply.

MM




From jelledejong at powercraft.nl  Thu Feb 10 16:09:18 2011
From: jelledejong at powercraft.nl (Jelle de Jong)
Date: Thu, 10 Feb 2011 16:09:18 +0100
Subject: [coreboot] searching volunteer to install coreboot on asus m4a78 pro
Message-ID: <4D53FF9E.2020100@powercraft.nl>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hello everybody,

I would like to start with thanking all volunteers on the coreboot
project! At FOSDEM 2011 I had dinner with two of the volunteers. I have
been watching the coreboot for the past years, as something that I love
to have running on my motherboards but never found the time/resources to
made a first step.

I would like to get coreboot on this system[1]. I would like the
coreboot to be installed by a volunteer. I can provide ssh access (both
ipv4 and ipv6) and a root passwd to the machine, and standby to help
over IRC.

[1] http://debian.pastebin.com/mqphUf5U # details ASUSTeK M4A78 PRO

Features I would like:
* Serial Console Redirection
* AMD Athlon II X4 615e support
* ECC Memory support
* Readout volt,temp,rpm sensors
* Boot 2.6 kernel support
* Grub 2 (lvm, mdadm, ext4) support

I got two M4A78 PRO motherboards that I would like to give new life by
getting coreboot on them.

With kind regards,

Jelle de Jong
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)

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=x6PR
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From scott at notabs.org  Thu Feb 10 20:32:31 2011
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 10 Feb 2011 13:32:31 -0600
Subject: [coreboot] [PATCH] cache type for BIOS flash memory should be
	WP-MMIO, not WB-MMIO
Message-ID: <46BB7DA45F6A4D8F85B38E0F7EC230A1@m3a78>

According to AMD documentation, cache type WP should be used for
execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem for a jtag debugger. The attached
patch changes AMD cache as ram setting for flash execution from
WB to WP.

Signed-off-by: Scott Duplichan <scott at notabs.org>

Index: src/cpu/amd/car/cache_as_ram.inc
===================================================================
--- src/cpu/amd/car/cache_as_ram.inc	(revision 6341)
+++ src/cpu/amd/car/cache_as_ram.inc	(working copy)
@@ -294,11 +294,11 @@
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The two lines below can _not_ be written like this:
-	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
 	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
-	orl	$MTRR_TYPE_WRBACK, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
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From marcj303 at gmail.com  Thu Feb 10 21:22:08 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 10 Feb 2011 13:22:08 -0700
Subject: [coreboot] [PATCH] cache type for BIOS flash memory should be
 WP-MMIO, not WB-MMIO
In-Reply-To: <46BB7DA45F6A4D8F85B38E0F7EC230A1@m3a78>
References: <46BB7DA45F6A4D8F85B38E0F7EC230A1@m3a78>
Message-ID: <AANLkTinC2-wM_z+bM4YCJvBA88Sx+coMEK7JGwQfXa5b@mail.gmail.com>

On Thu, Feb 10, 2011 at 12:32 PM, Scott Duplichan <scott at notabs.org> wrote:
> According to AMD documentation, cache type WP should be used for
> execution from flash memory. Coreboot uses WB. While there is no
> noticeable performance difference between the two settings, use
> of WB can cause a problem for a jtag debugger. The attached
> patch changes AMD cache as ram setting for flash execution from
> WB to WP.
>
> Signed-off-by: Scott Duplichan <scott at notabs.org>
>
> Index: src/cpu/amd/car/cache_as_ram.inc
> ===================================================================
> --- src/cpu/amd/car/cache_as_ram.inc ? ?(revision 6341)
> +++ src/cpu/amd/car/cache_as_ram.inc ? ?(working copy)
> @@ -294,11 +294,11 @@
> ? ? ? ?xorl ? ?%edx, %edx
> ? ? ? ?/*
> ? ? ? ? * IMPORTANT: The two lines below can _not_ be written like this:
> - ? ? ? ?* ? movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
> + ? ? ? ?* ? movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
> ? ? ? ? * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
> ? ? ? ? */
> ? ? ? ?movl ? ?$REAL_XIP_ROM_BASE, %eax
> - ? ? ? orl ? ? $MTRR_TYPE_WRBACK, %eax
> + ? ? ? orl ? ? $MTRR_TYPE_WRPROT, %eax
> ? ? ? ?wrmsr
>
> ? ? ? ?movl ? ?$MTRRphysMask_MSR(1), %ecx
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Acked-by: Marc Jones <marcj303 at gmail.com>

-- 
http://se-eng.com



From svn at coreboot.org  Thu Feb 10 21:49:57 2011
From: svn at coreboot.org (repository service)
Date: Thu, 10 Feb 2011 21:49:57 +0100
Subject: [coreboot] [commit] r6342 - trunk/src/cpu/amd/car
Message-ID: <E1PndSf-0002Jh-Ai@ra.coresystems.de>

Author: sduplichan
Date: Thu Feb 10 21:49:56 2011
New Revision: 6342
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6342

Log:
According to AMD documentation, cache type WP should be used for
execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem for a jtag debugger. The attached
patch changes AMD cache as ram setting for flash execution from
WB to WP.

Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/cpu/amd/car/cache_as_ram.inc

Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc	Thu Feb 10 09:49:57 2011	(r6341)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc	Thu Feb 10 21:49:56 2011	(r6342)
@@ -294,11 +294,11 @@
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The two lines below can _not_ be written like this:
-	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
 	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
-	orl	$MTRR_TYPE_WRBACK, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx



From anton.kochkov at gmail.com  Fri Feb 11 00:30:05 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Fri, 11 Feb 2011 02:30:05 +0300
Subject: [coreboot] inteltool: first preview for machine-readable output
Message-ID: <AANLkTin43TvnFrz+HkqLChtWhDi9q-jWM=sNGZ8adOw1@mail.gmail.com>

inteltool: first preview for machine-readable output
Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
---

This is only for preview and discussion, it's still ugly and dont safe/clear.
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From stefan.reinauer at coreboot.org  Fri Feb 11 01:51:25 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Fri, 11 Feb 2011 01:51:25 +0100
Subject: [coreboot] what was 'set' in struct io_info for?
In-Reply-To: <ij0g1l$32k$1@dough.gmane.org>
References: <20110208013820.GC8516@tarantulon.kollasch.net>
	<ij0g1l$32k$1@dough.gmane.org>
Message-ID: <20110211005125.GA5352@coreboot.org>

* Mark Marshall <mark.marshall at csr.com> [110210 11:52]:
> I found the same thing as you a while ago.  The io_info structure in
> pnp.h is never referenced by the code, and it's purpose is never
> really defined anywhere.  If you change the name to something else
> (just in the header file) the code still all compiles, so I'd say
> remove it.
> 
> I also asked about it on the news group, but got no reply.

Oh, we have a news group? 

 



From stefan.reinauer at coreboot.org  Fri Feb 11 02:36:56 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Fri, 11 Feb 2011 02:36:56 +0100
Subject: [coreboot] how Coreboot keeps the right offsets of the sections
In-Reply-To: <20110209194433.745.qmail@stuge.se>
References: <AANLkTikJynd_cKisASA_9-pBnNBNZSSCHxifcqoq1XDA@mail.gmail.com>
	<AANLkTinX0ju8=eU+TcAZ-ehapTs0d5npD6FHbM8WZ9p7@mail.gmail.com>
	<20110209194433.745.qmail@stuge.se>
Message-ID: <20110211013655.GA18817@coreboot.org>

* Peter Stuge <peter at stuge.se> [110209 20:44]:
> > I checked the content of build/coreboot.rom and the last byte was
> > 0x0a!! Which is written probably on the top of our EEPROM. Right?
> 
> > but src/arch/i386/init/ldscript.ld specifies the last byte as 0x00!!
> > SECTIONS {
> > 	_ROMTOP = 0xfffffff0;
> > 	. = _ROMTOP;
> > 	.resetvector . : {
> > 		*(.reset)
> >                 . = 15 ;
> >                 BYTE(0x00);
> > 	}
> > }
> > 
> > Please help me with this puzzle. Thank you.
> 
> What is the concrete problem? You should not rule out that there are
> binutils bugs. Just be happy that the reset vector has the right
> opcodes.

cbfstool updates those memory regions.




From anton.kochkov at gmail.com  Fri Feb 11 02:32:55 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Fri, 11 Feb 2011 04:32:55 +0300
Subject: [coreboot] Fwd: inteltool: first preview for machine-readable output
In-Reply-To: <AANLkTin43TvnFrz+HkqLChtWhDi9q-jWM=sNGZ8adOw1@mail.gmail.com>
References: <AANLkTin43TvnFrz+HkqLChtWhDi9q-jWM=sNGZ8adOw1@mail.gmail.com>
Message-ID: <AANLkTin=3aK7aPVq4cAJJBj7rOEe_eFT1LEMxhCuBQC4@mail.gmail.com>

inteltool: first preview for machine-readable output
Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
---

This is only for preview and discussion, it's still ugly and dont safe/clear.
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From anton.kochkov at gmail.com  Fri Feb 11 03:31:59 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Fri, 11 Feb 2011 05:31:59 +0300
Subject: [coreboot] inteltool: first preview for machine-readable output,
	fixes
Message-ID: <AANLkTi=3J5m9oBG1MVs1jvwA4RNfC5LGgdE8wCbJcFtf@mail.gmail.com>

inteltool: first preview for machine-readable output, fixes
Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
---

This is only for preview and discussion, it's still ugly and dont safe/clear.
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From mr.nuke.me at gmail.com  Fri Feb 11 14:09:22 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Fri, 11 Feb 2011 15:09:22 +0200
Subject: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
Message-ID: <4D553502.50904@gmail.com>

Find attached a new version of my previous patch for the K8T800. In my
previous patch, I was worried that the .tblpointer could contain
incorrect values. I have hexdumped the image for the A8V-E SE (K8T8900
chipset), and it contains the correct values. The same applies to the
board I'm porting (with K8T800 chipset).

I remember someone on IRC asking about the previous patch for the
K8T800. I've added the PCI ID for the K8M800 VGA controller to the
K8M890 driver, so the VGA might work (TM) on the K8M800.

The code for the K8T800 works. The reason I'm not also putting up a
patch for the ASUS K8V-X SE is that IRQs are not (yet) working well for
this board.

Alex

*These northbridges have not been tested.
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From svens at stackframe.org  Fri Feb 11 15:38:26 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Fri, 11 Feb 2011 15:38:26 +0100
Subject: [coreboot] Fwd: inteltool: first preview for machine-readable
	output
In-Reply-To: <AANLkTin=3aK7aPVq4cAJJBj7rOEe_eFT1LEMxhCuBQC4@mail.gmail.com>
	(=?utf-8?B?ItCQ0L3RgtC+0L0g0JrQvtGH0LrQvtCyIidz?= message of "Fri\,
	11 Feb 2011 04\:32\:55 +0300")
References: <AANLkTin43TvnFrz+HkqLChtWhDi9q-jWM=sNGZ8adOw1@mail.gmail.com>
	<AANLkTin=3aK7aPVq4cAJJBj7rOEe_eFT1LEMxhCuBQC4@mail.gmail.com>
Message-ID: <87wrl6iql9.fsf@begreifnix.stackframe.org>

Hi,

????? ?????? <anton.kochkov at gmail.com> writes:

At first, can you please give us a few use cases for this patch?

> inteltool: first preview for machine-readable output
> Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
> ---
>
> This is only for preview and discussion, it's still ugly and dont safe/clear.

> void machine_readable_printf(reg_t *reg) {
>
> #ifdef XML
> 	printf("<register domain='%s' base='0x%x' offset='0x%x' size='%d' value='0x%x' name='%s' description='%s' />\n",
> 		reg->domain, reg->base_addr, reg->offset, reg->size, reg->value, reg->name, reg->desc);
> #endif

That should probably be an #else, and it should be switchable during
runtime instead of compile time.

> #ifndef XML
> 	printf("domain: %s\n", reg->domain);
> 	printf("base addr: 0x%x\n", reg->base_addr);
> 	printf("offset: 0x%x\n", reg->offset);
> 	printf("size: %d\n", reg->size);
> 	printf("value: 0x%x\n", reg->value);
> 	printf("name: %s\n", reg->name);
> 	printf("description: %s\n", reg->desc);
> #endif
> }



From Patrick.Georgi at secunet.com  Fri Feb 11 10:38:58 2011
From: Patrick.Georgi at secunet.com (Patrick Georgi)
Date: Fri, 11 Feb 2011 10:38:58 +0100
Subject: [coreboot] [PATCH 2/4] libpayload: Less noisy lpgcc
Message-ID: <1297436253.7802.1.camel@linux-0a8x.site>

lpgcc was too noisy in some cases

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 payloads/libpayload/bin/lpgcc |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc
index 826e498..57015d5 100755
--- a/payloads/libpayload/bin/lpgcc
+++ b/payloads/libpayload/bin/lpgcc
@@ -30,12 +30,14 @@
 # let's not recurse.
 # This is a hack, I know, but it makes sure that really simple user errors
 # don't fork-bomb your machine.
-echo "CC = $CC"
+# echo "CC = $CC"
 
+if [ -n "$CC" ]; then
 b=`basename $CC`
 if [ "$b" = "lpgcc" ]; then
 CC=""
 fi
+fi
 
 
 
-- 
1.7.1




From Patrick.Georgi at secunet.com  Fri Feb 11 10:36:41 2011
From: Patrick.Georgi at secunet.com (Patrick Georgi)
Date: Fri, 11 Feb 2011 10:36:41 +0100
Subject: [coreboot] [PATCH 1/4] libpayload: Some more POSIX compatibility
Message-ID: <1297436253.7802.0.camel@linux-0a8x.site>

- Add assert.h
- Add arpa/inet.h
- Add assert-macro

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 payloads/libpayload/include/arpa/inet.h |   36 ++++++++++++++++++++++++++++
 payloads/libpayload/include/assert.h    |   39 +++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+), 0 deletions(-)
 create mode 100644 payloads/libpayload/include/arpa/inet.h
 create mode 100644 payloads/libpayload/include/assert.h

diff --git a/payloads/libpayload/include/arpa/inet.h b/payloads/libpayload/include/arpa/inet.h
new file mode 100644
index 0000000..4fc8a89
--- /dev/null
+++ b/payloads/libpayload/include/arpa/inet.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2011 secunet Security Networks AG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARPA_INET_H
+#define _ARPA_INET_H
+
+// arch/endian.h already provides ?to?[lwb]
+#include <arch/endian.h>
+
+#endif
diff --git a/payloads/libpayload/include/assert.h b/payloads/libpayload/include/assert.h
new file mode 100644
index 0000000..fda4bc0
--- /dev/null
+++ b/payloads/libpayload/include/assert.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2011 secunet Security Networks AG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+
+// assert's existence depends on NDEBUG state on _last_ inclusion of assert.h,
+// so don't guard this against double-includes.
+#ifdef NDEBUG
+// Heisenbugs appear if statement has side-effects. This could be worked around but does the standard allow for that?
+#define assert(statement)
+#else
+#define assert(statement) if ((statement) == 0) { printf("assertion failed in file %s, function %s(), line %s\n", __FILE__, __FUNCTION__, __LINE__); abort(); }
+#endif
-- 
1.7.1




From Patrick.Georgi at secunet.com  Fri Feb 11 10:57:16 2011
From: Patrick.Georgi at secunet.com (Patrick Georgi)
Date: Fri, 11 Feb 2011 10:57:16 +0100
Subject: [coreboot] [PATCH 3/4] libpayload: Stub out FILE*,
 stdout/stdin/stderr and implement fprintf on these
Message-ID: <1297436253.7802.2.camel@linux-0a8x.site>

- Add FILE*
- Add stdout, stdin, stderr stubs
- Add fprintf that redirects to printf for stdout and stderr and fails
  otherwise

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 payloads/libpayload/include/stdio.h |   11 ++++++++++-
 payloads/libpayload/libc/printf.c   |   14 ++++++++++++++
 2 files changed, 24 insertions(+), 1 deletions(-)

diff --git a/payloads/libpayload/include/stdio.h b/payloads/libpayload/include/stdio.h
index 73af2d1..fb40a0d 100644
--- a/payloads/libpayload/include/stdio.h
+++ b/payloads/libpayload/include/stdio.h
@@ -32,6 +32,15 @@
 
 #include <stddef.h>
 
+struct _FILE {
+} _stdout, _stdin, _stderr;
+
+typedef struct _FILE FILE;
+
+FILE *stdout = &_stdout;
+FILE *stdin = &_stdin;
+FILE *stderr = &_stderr;
+
 /**
  * @defgroup printf Print functions
  * @{
@@ -39,6 +48,7 @@
 int snprintf(char *str, size_t size, const char *fmt, ...);
 int sprintf(char *str, const char *fmt, ...);
 int printf(const char *fmt, ...);
+int fprintf(FILE *file, const char *fmt, ...);
 /** @} */
 
 void perror(const char *s);
@@ -47,5 +57,4 @@ void perror(const char *s);
 #define SEEK_CUR 1 /**< The seek offset is against the current position. */
 #define SEEK_END 2 /**< The seek offset is against the end of the file. */
 
-
 #endif
diff --git a/payloads/libpayload/libc/printf.c b/payloads/libpayload/libc/printf.c
index 04d3931..a1ebb14 100644
--- a/payloads/libpayload/libc/printf.c
+++ b/payloads/libpayload/libc/printf.c
@@ -723,6 +723,20 @@ int sprintf(char *str, const char *fmt, ...)
 	return ret;
 }
 
+int fprintf(FILE *file, const char *fmt, ...)
+{
+	int ret;
+	if ((file == stdout) || (file == stderr)) {
+		va_list args;
+		va_start(args, fmt);
+		ret = vprintf(fmt, args);
+		va_end(args);
+
+		return ret;
+	}
+	return -1;
+}
+
 struct vsnprintf_data {
 	size_t size;		/* Total space for string */
 	size_t len;		/* Count of currently used characters */
-- 
1.7.1




From Patrick.Georgi at secunet.com  Fri Feb 11 11:00:09 2011
From: Patrick.Georgi at secunet.com (Patrick Georgi)
Date: Fri, 11 Feb 2011 11:00:09 +0100
Subject: [coreboot] [PATCH 4/4] libpayload: Use fprintf(stderr,
	...) in library
Message-ID: <1297436253.7802.3.camel@linux-0a8x.site>

If we have it, why not use it?

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 payloads/libpayload/include/assert.h |    3 ++-
 payloads/libpayload/libc/lib.c       |    2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/include/assert.h b/payloads/libpayload/include/assert.h
index fda4bc0..9968504 100644
--- a/payloads/libpayload/include/assert.h
+++ b/payloads/libpayload/include/assert.h
@@ -28,6 +28,7 @@
  */
 
 #include <stdlib.h>
+#include <stdio.h>
 
 // assert's existence depends on NDEBUG state on _last_ inclusion of assert.h,
 // so don't guard this against double-includes.
@@ -35,5 +36,5 @@
 // Heisenbugs appear if statement has side-effects. This could be worked around but does the standard allow for that?
 #define assert(statement)
 #else
-#define assert(statement) if ((statement) == 0) { printf("assertion failed in file %s, function %s(), line %s\n", __FILE__, __FUNCTION__, __LINE__); abort(); }
+#define assert(statement) if ((statement) == 0) { fprintf(stderr, "assertion failed in file %s, function %s(), line %s\n", __FILE__, __FUNCTION__, __LINE__); abort(); }
 #endif
diff --git a/payloads/libpayload/libc/lib.c b/payloads/libpayload/libc/lib.c
index baccc07..c8539cb 100644
--- a/payloads/libpayload/libc/lib.c
+++ b/payloads/libpayload/libc/lib.c
@@ -109,7 +109,7 @@ u8 hex2bin(u8 h)
  */
 void fatal(const char *msg)
 {
-	printf("%s",msg);
+	fprintf(stderr, "%s",msg);
 	halt();
 }
 
-- 
1.7.1



From stefan.reinauer at coresystems.de  Fri Feb 11 19:03:22 2011
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 11 Feb 2011 10:03:22 -0800
Subject: [coreboot] [PATCH 2/4] libpayload: Less noisy lpgcc
In-Reply-To: <1297436253.7802.1.camel@linux-0a8x.site>
References: <1297436253.7802.1.camel@linux-0a8x.site>
Message-ID: <9B57A5AD-D882-489F-9454-9747A6AD183C@coresystems.de>

On 11.02.2011, at 01:38, Patrick Georgi <Patrick.Georgi at secunet.com> wrote:

> lpgcc was too noisy in some cases
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org> 


> ---
> payloads/libpayload/bin/lpgcc |    4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
> 
> diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc
> index 826e498..57015d5 100755
> --- a/payloads/libpayload/bin/lpgcc
> +++ b/payloads/libpayload/bin/lpgcc
> @@ -30,12 +30,14 @@
> # let's not recurse.
> # This is a hack, I know, but it makes sure that really simple user errors
> # don't fork-bomb your machine.
> -echo "CC = $CC"
> +# echo "CC = $CC"
> 
> +if [ -n "$CC" ]; then
> b=`basename $CC`
> if [ "$b" = "lpgcc" ]; then
> CC=""
> fi
> +fi
> 
> 
> 
> -- 
> 1.7.1
> 
> 
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 



From stefan.reinauer at coresystems.de  Fri Feb 11 19:03:46 2011
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 11 Feb 2011 10:03:46 -0800
Subject: [coreboot] [PATCH 1/4] libpayload: Some more POSIX compatibility
In-Reply-To: <1297436253.7802.0.camel@linux-0a8x.site>
References: <1297436253.7802.0.camel@linux-0a8x.site>
Message-ID: <C837B9B5-357A-49B2-B320-EBA5A2EA45D3@coresystems.de>


On 11.02.2011, at 01:36, Patrick Georgi <Patrick.Georgi at secunet.com> wrote:

> - Add assert.h
> - Add arpa/inet.h
> - Add assert-macro
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org> 


> ---
> payloads/libpayload/include/arpa/inet.h |   36 ++++++++++++++++++++++++++++
> payloads/libpayload/include/assert.h    |   39 +++++++++++++++++++++++++++++++
> 2 files changed, 75 insertions(+), 0 deletions(-)
> create mode 100644 payloads/libpayload/include/arpa/inet.h
> create mode 100644 payloads/libpayload/include/assert.h
> 
> diff --git a/payloads/libpayload/include/arpa/inet.h b/payloads/libpayload/include/arpa/inet.h
> new file mode 100644
> index 0000000..4fc8a89
> --- /dev/null
> +++ b/payloads/libpayload/include/arpa/inet.h
> @@ -0,0 +1,36 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2011 secunet Security Networks AG
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#ifndef _ARPA_INET_H
> +#define _ARPA_INET_H
> +
> +// arch/endian.h already provides ?to?[lwb]
> +#include <arch/endian.h>
> +
> +#endif
> diff --git a/payloads/libpayload/include/assert.h b/payloads/libpayload/include/assert.h
> new file mode 100644
> index 0000000..fda4bc0
> --- /dev/null
> +++ b/payloads/libpayload/include/assert.h
> @@ -0,0 +1,39 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2011 secunet Security Networks AG
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include <stdlib.h>
> +
> +// assert's existence depends on NDEBUG state on _last_ inclusion of assert.h,
> +// so don't guard this against double-includes.
> +#ifdef NDEBUG
> +// Heisenbugs appear if statement has side-effects. This could be worked around but does the standard allow for that?
> +#define assert(statement)
> +#else
> +#define assert(statement) if ((statement) == 0) { printf("assertion failed in file %s, function %s(), line %s\n", __FILE__, __FUNCTION__, __LINE__); abort(); }
> +#endif
> -- 
> 1.7.1
> 
> 
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 



From stefan.reinauer at coresystems.de  Fri Feb 11 19:04:15 2011
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 11 Feb 2011 10:04:15 -0800
Subject: [coreboot] [PATCH 3/4] libpayload: Stub out FILE*,
	stdout/stdin/stderr and implement fprintf on these
In-Reply-To: <1297436253.7802.2.camel@linux-0a8x.site>
References: <1297436253.7802.2.camel@linux-0a8x.site>
Message-ID: <841DB28E-B6BF-4CD8-B0B1-EDAC53702DEA@coresystems.de>

On 11.02.2011, at 01:57, Patrick Georgi <Patrick.Georgi at secunet.com> wrote:

> - Add FILE*
> - Add stdout, stdin, stderr stubs
> - Add fprintf that redirects to printf for stdout and stderr and fails
>  otherwise
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org> 

> ---
> payloads/libpayload/include/stdio.h |   11 ++++++++++-
> payloads/libpayload/libc/printf.c   |   14 ++++++++++++++
> 2 files changed, 24 insertions(+), 1 deletions(-)
> 
> diff --git a/payloads/libpayload/include/stdio.h b/payloads/libpayload/include/stdio.h
> index 73af2d1..fb40a0d 100644
> --- a/payloads/libpayload/include/stdio.h
> +++ b/payloads/libpayload/include/stdio.h
> @@ -32,6 +32,15 @@
> 
> #include <stddef.h>
> 
> +struct _FILE {
> +} _stdout, _stdin, _stderr;
> +
> +typedef struct _FILE FILE;
> +
> +FILE *stdout = &_stdout;
> +FILE *stdin = &_stdin;
> +FILE *stderr = &_stderr;
> +
> /**
>  * @defgroup printf Print functions
>  * @{
> @@ -39,6 +48,7 @@
> int snprintf(char *str, size_t size, const char *fmt, ...);
> int sprintf(char *str, const char *fmt, ...);
> int printf(const char *fmt, ...);
> +int fprintf(FILE *file, const char *fmt, ...);
> /** @} */
> 
> void perror(const char *s);
> @@ -47,5 +57,4 @@ void perror(const char *s);
> #define SEEK_CUR 1 /**< The seek offset is against the current position. */
> #define SEEK_END 2 /**< The seek offset is against the end of the file. */
> 
> -
> #endif
> diff --git a/payloads/libpayload/libc/printf.c b/payloads/libpayload/libc/printf.c
> index 04d3931..a1ebb14 100644
> --- a/payloads/libpayload/libc/printf.c
> +++ b/payloads/libpayload/libc/printf.c
> @@ -723,6 +723,20 @@ int sprintf(char *str, const char *fmt, ...)
>    return ret;
> }
> 
> +int fprintf(FILE *file, const char *fmt, ...)
> +{
> +    int ret;
> +    if ((file == stdout) || (file == stderr)) {
> +        va_list args;
> +        va_start(args, fmt);
> +        ret = vprintf(fmt, args);
> +        va_end(args);
> +
> +        return ret;
> +    }
> +    return -1;
> +}
> +
> struct vsnprintf_data {
>    size_t size;        /* Total space for string */
>    size_t len;        /* Count of currently used characters */
> -- 
> 1.7.1
> 
> 
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 



From stefan.reinauer at coresystems.de  Fri Feb 11 19:04:39 2011
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 11 Feb 2011 10:04:39 -0800
Subject: [coreboot] [PATCH 4/4] libpayload: Use fprintf(stderr,
	...) in library
In-Reply-To: <1297436253.7802.3.camel@linux-0a8x.site>
References: <1297436253.7802.3.camel@linux-0a8x.site>
Message-ID: <FC18CEA3-B098-4507-9F5F-AFE08D849D21@coresystems.de>

On 11.02.2011, at 02:00, Patrick Georgi <Patrick.Georgi at secunet.com> wrote:

> If we have it, why not use it?
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org> 


> ---
> payloads/libpayload/include/assert.h |    3 ++-
> payloads/libpayload/libc/lib.c       |    2 +-
> 2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/payloads/libpayload/include/assert.h b/payloads/libpayload/include/assert.h
> index fda4bc0..9968504 100644
> --- a/payloads/libpayload/include/assert.h
> +++ b/payloads/libpayload/include/assert.h
> @@ -28,6 +28,7 @@
>  */
> 
> #include <stdlib.h>
> +#include <stdio.h>
> 
> // assert's existence depends on NDEBUG state on _last_ inclusion of assert.h,
> // so don't guard this against double-includes.
> @@ -35,5 +36,5 @@
> // Heisenbugs appear if statement has side-effects. This could be worked around but does the standard allow for that?
> #define assert(statement)
> #else
> -#define assert(statement) if ((statement) == 0) { printf("assertion failed in file %s, function %s(), line %s\n", __FILE__, __FUNCTION__, __LINE__); abort(); }
> +#define assert(statement) if ((statement) == 0) { fprintf(stderr, "assertion failed in file %s, function %s(), line %s\n", __FILE__, __FUNCTION__, __LINE__); abort(); }
> #endif
> diff --git a/payloads/libpayload/libc/lib.c b/payloads/libpayload/libc/lib.c
> index baccc07..c8539cb 100644
> --- a/payloads/libpayload/libc/lib.c
> +++ b/payloads/libpayload/libc/lib.c
> @@ -109,7 +109,7 @@ u8 hex2bin(u8 h)
>  */
> void fatal(const char *msg)
> {
> -    printf("%s",msg);
> +    fprintf(stderr, "%s",msg);
>    halt();
> }
> 
> -- 
> 1.7.1
> 
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 



From anton.kochkov at gmail.com  Sat Feb 12 00:01:50 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Sat, 12 Feb 2011 02:01:50 +0300
Subject: [coreboot] msrtool: add support for Intel
Message-ID: <AANLkTinGSB-7Zg6MN1Cp=L7CrLi2BgmOdKfxbfGoX+j6@mail.gmail.com>

msrtool: add support for Intel
Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
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From marcj303 at gmail.com  Sat Feb 12 00:20:53 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 11 Feb 2011 16:20:53 -0700
Subject: [coreboot] coreboot.rom
In-Reply-To: <AANLkTikJynd_cKisASA_9-pBnNBNZSSCHxifcqoq1XDA@mail.gmail.com>
References: <AANLkTikJynd_cKisASA_9-pBnNBNZSSCHxifcqoq1XDA@mail.gmail.com>
Message-ID: <AANLkTim+s8-nUCb62A2YYEg03U=9UM0aTAnaJ04ecPwW@mail.gmail.com>

On Wed, Feb 9, 2011 at 6:35 AM, ali hagigat <hagigatali at gmail.com> wrote:
> How the file coreboot.rom is written on BIOS chip logically? Suppose
> our BIOS chip is 1 mega bytes. We should read first byte from the
> beginning of the file and write it to the address zero of BIOS chip
> and continue this way?
>
> I checked the content of build/coreboot.rom and the last byte was
> 0x0a!! Which is written probably on the top of our EEPROM. Right?
> but src/arch/i386/init/ldscript.ld specifies the last byte as 0x00!!
> SECTIONS {
> ? ? ? ?_ROMTOP = 0xfffffff0;
> ? ? ? ?. = _ROMTOP;
> ? ? ? ?.resetvector . : {
> ? ? ? ? ? ? ? ?*(.reset)
> ? ? ? ? ? ? ? ?. = 15 ;
> ? ? ? ? ? ? ? ?BYTE(0x00);
> ? ? ? ?}
> }

x86 systems start executing 0xFFFFFFF0, the reset vector.

http://en.wikipedia.org/wiki/Reset_vector

The first instruction is a far jump down to the stackless init code.

This wiki is for V3, but all the details are there:
http://www.coreboot.org/Coreboot_v3#How_coreboot_starts_after_Reset

Marc



-- 
http://se-eng.com



From marcj303 at gmail.com  Sat Feb 12 01:04:29 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 11 Feb 2011 17:04:29 -0700
Subject: [coreboot] searching volunteer to install coreboot on asus
	m4a78 pro
In-Reply-To: <4D53FF9E.2020100@powercraft.nl>
References: <4D53FF9E.2020100@powercraft.nl>
Message-ID: <AANLkTikd7R1FxeW3VGQe0KcXQdZJypShokD1-2t94tzj@mail.gmail.com>

On Thu, Feb 10, 2011 at 8:09 AM, Jelle de Jong
<jelledejong at powercraft.nl> wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Hello everybody,
>
> I would like to start with thanking all volunteers on the coreboot
> project! At FOSDEM 2011 I had dinner with two of the volunteers. I have
> been watching the coreboot for the past years, as something that I love
> to have running on my motherboards but never found the time/resources to
> made a first step.
>
> I would like to get coreboot on this system[1]. I would like the
> coreboot to be installed by a volunteer. I can provide ssh access (both
> ipv4 and ipv6) and a root passwd to the machine, and standby to help
> over IRC.
>
> [1] http://debian.pastebin.com/mqphUf5U # details ASUSTeK M4A78 PRO
>
> Features I would like:
> * Serial Console Redirection
> * AMD Athlon II X4 615e support
> * ECC Memory support
> * Readout volt,temp,rpm sensors
> * Boot 2.6 kernel support
> * Grub 2 (lvm, mdadm, ext4) support
>
> I got two M4A78 PRO motherboards that I would like to give new life by
> getting coreboot on them.
>
> With kind regards,
>
> Jelle de Jong

Welcome,

Your platform is a good candidate for coreboot support, but the best
way to get coreboot on your system is for you to develop it. You may
want to look at the AMD Mahogany platform as a place to start. You
need to find out what your flash device is. Flashrom didn't ID it.
Mistakes will be made along the way, so make sure that you have a way
to recover from a bad flash. Your board may have a SPI header for
reprogramming.

Marc




-- 
http://se-eng.com



From gregg.drwho8 at gmail.com  Sat Feb 12 01:34:23 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Fri, 11 Feb 2011 19:34:23 -0500
Subject: [coreboot] SVN service down?
Message-ID: <AANLkTikQS3TtEqeFqBzCHqrTHD+wjwAeXQ2QTJYH98Tz@mail.gmail.com>

Hello!
I've been trying to update my checked out coreboot code drop since
just ten minutes ago. In fact I would bring up a console and enter at
the appropriate directory, "svn update" (without quotes) and wait. It
would seem to be hanging. Network monitors would only indicate that my
SSH shell is the only thing running on the host.

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From dhendrix at google.com  Sat Feb 12 02:41:43 2011
From: dhendrix at google.com (David Hendricks)
Date: Fri, 11 Feb 2011 17:41:43 -0800
Subject: [coreboot] SVN service down?
In-Reply-To: <AANLkTikQS3TtEqeFqBzCHqrTHD+wjwAeXQ2QTJYH98Tz@mail.gmail.com>
References: <AANLkTikQS3TtEqeFqBzCHqrTHD+wjwAeXQ2QTJYH98Tz@mail.gmail.com>
Message-ID: <AANLkTika_NsGdS5ha27jmeYB5C7gLLvqgRyCpgQnf6qr@mail.gmail.com>

On Fri, Feb 11, 2011 at 4:34 PM, Gregg Levine <gregg.drwho8 at gmail.com>wrote:

> Hello!
> I've been trying to update my checked out coreboot code drop since
> just ten minutes ago. In fact I would bring up a console and enter at
> the appropriate directory, "svn update" (without quotes) and wait. It
> would seem to be hanging. Network monitors would only indicate that my
> SSH shell is the only thing running on the host.
>

fwiw, svn update works fine for me right now.

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From svn at coreboot.org  Sat Feb 12 03:01:45 2011
From: svn at coreboot.org (repository service)
Date: Sat, 12 Feb 2011 03:01:45 +0100
Subject: [coreboot] [FILO] r140 - trunk/filo/fs
Message-ID: <E1Po4nx-0008Q2-C1@ra.coresystems.de>

Author: stepan
Date: Sat Feb 12 03:01:44 2011
New Revision: 140
URL: http://tracker.coreboot.org/trac/filo/changeset/140

Log:
Allow FILO to boot off EXT4 partitions.

Using adapted http://grub4ext4.googlecode.com/svn/trunk/ext4-support

Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/filo/fs/fsys_ext2fs.c

Modified: trunk/filo/fs/fsys_ext2fs.c
==============================================================================
--- trunk/filo/fs/fsys_ext2fs.c	Fri Dec 10 05:09:57 2010	(r139)
+++ trunk/filo/fs/fsys_ext2fs.c	Sat Feb 12 03:01:44 2011	(r140)
@@ -38,6 +38,7 @@
 typedef unsigned short __u16;
 typedef __signed__ int __s32;
 typedef unsigned int __u32;
+typedef unsigned long long __u64;
 
 /*
  * Constants relative to the data blocks, from ext2_fs.h
@@ -48,7 +49,7 @@
 #define EXT2_TIND_BLOCK                 (EXT2_DIND_BLOCK + 1)
 #define EXT2_N_BLOCKS                   (EXT2_TIND_BLOCK + 1)
 
-/* include/linux/ext2_fs.h */
+/* lib/ext2fs/ext2_fs.h from e2fsprogs */
 struct ext2_super_block
   {
     __u32 s_inodes_count;	/* Inodes count */
@@ -58,9 +59,9 @@
     __u32 s_free_inodes_count;	/* Free inodes count */
     __u32 s_first_data_block;	/* First Data Block */
     __u32 s_log_block_size;	/* Block size */
-    __s32 s_log_frag_size;	/* Fragment size */
+    __s32 s_obso_log_frag_size;	/* Obsoleted Fragment size */
     __u32 s_blocks_per_group;	/* # Blocks per group */
-    __u32 s_frags_per_group;	/* # Fragments per group */
+    __u32 s_obso_frags_per_group;	/* Obsoleted Fragments per group */
     __u32 s_inodes_per_group;	/* # Inodes per group */
     __u32 s_mtime;		/* Mount time */
     __u32 s_wtime;		/* Write time */
@@ -69,7 +70,7 @@
     __u16 s_magic;		/* Magic signature */
     __u16 s_state;		/* File system state */
     __u16 s_errors;		/* Behaviour when detecting errors */
-    __u16 s_pad;
+    __u16 s_minor_rev_level;	/* minor revision level */
     __u32 s_lastcheck;		/* time of last check */
     __u32 s_checkinterval;	/* max. time between checks */
     __u32 s_creator_os;		/* OS */
@@ -105,7 +106,7 @@
 	 */
 	__u8	s_prealloc_blocks;	/* Nr of blocks to try to preallocate*/
 	__u8	s_prealloc_dir_blocks;	/* Nr to preallocate for dirs */
-	__u16	s_padding1;
+	__u16	s_reserved_gdt_blocks;  /* Per group desc for online growth */
 	/*
 	 * Journaling support valid if EXT3_FEATURE_COMPAT_HAS_JOURNAL set.
 	 */
@@ -115,14 +116,30 @@
 	__u32	s_last_orphan;		/* start of list of inodes to delete */
 	__u32	s_hash_seed[4];		/* HTREE hash seed */
 	__u8	s_def_hash_version;	/* Default hash version to use */
-	__u8	s_reserved_char_pad;
-	__u16	s_reserved_word_pad;
+	__u8	s_jnl_backup_type;	/* Default type of journal backup */
+	__u16	s_desc_size;	/* size of group descriptor */
 	__u32	s_default_mount_opts;
  	__u32	s_first_meta_bg; 	/* First metablock block group */
-	__u32	s_reserved[190];	/* Padding to the end of the block */
+	__u32	s_mkfs_time;	/* When the filesystem was created */
+	__u32	s_jnl_blocks[17];	/* Backup of journal inode */
+	/* 64bit desc support valid if EXT4_FEATURE_INCOMPAT_64BIT */
+	__u32	s_blocks_count_hi;	/* Blocks count */
+	__u32	s_r_blocks_count_hi;/* Reserved blocks count */
+	__u32	s_free_blocks_count_hi;	/* Free blocks count */
+	__u16	s_min_extra_isize;	/* All inodes have at least # bytes */
+	__u16	s_max_extra_isize;	/* New inodes should reverve # bytes */
+	__u32	s_flags;	/* Miscellaneous flags */
+	__u16	s_raid_stride;		/* Raid stride */
+	__u16	s_mmp_interval;		/* # seconds to wait MMP checking */
+	__u64	s_mmp_block;		/* Block for multi-mount protection */
+	__u32	s_raid_stripe_width;	/* Blocks on all data disks (N*stride)*/
+	__u8	s_log_groups_per_flex;	/* FLEX_BG group size*/
+	__u8	s_reserved_char_pad;
+	__u16	s_reserved_pad;
+	__u32	s_reserved[162];	/* Padding to the end of the block */
   };
 
-struct ext2_group_desc
+struct ext4_group_desc
   {
     __u32 bg_block_bitmap;	/* Blocks bitmap block */
     __u32 bg_inode_bitmap;	/* Inodes bitmap block */
@@ -130,8 +147,18 @@
     __u16 bg_free_blocks_count;	/* Free blocks count */
     __u16 bg_free_inodes_count;	/* Free inodes count */
     __u16 bg_used_dirs_count;	/* Directories count */
-    __u16 bg_pad;
-    __u32 bg_reserved[3];
+    __u16 bg_flags;		/* EXT4_BG_flags (INODE_UNINIT, etc) */
+    __u32 bg_reserved[2];		/* Likely block/inode bitmap checksum */
+    __u16 bg_itable_unused;	/* Unused inodes count */
+    __u16 bg_checksum;		/* crc16(sb_uuid+group+desc) */
+    __u32 bg_block_bitmap_hi;	/* Blocks bitmap block MSB */
+    __u32 bg_inode_bitmap_hi;	/* Inodes bitmap block MSB */
+    __u32 bg_inode_table_hi;	/* Inodes table block MSB */
+    __u16 bg_free_blocks_count_hi;/* Free blocks count MSB */
+    __u16 bg_free_inodes_count_hi;/* Free inodes count MSB */
+    __u16 bg_used_dirs_count_hi;	/* Directories count MSB */
+    __u16 bg_itable_unused_hi;	/* Unused inodes count MSB */
+    __u32 bg_reserved2[3];
   };
 
 struct ext2_inode
@@ -169,22 +196,22 @@
     __u32 i_block[EXT2_N_BLOCKS];	/* 40: Pointers to blocks */
     __u32 i_version;		/* File version (for NFS) */
     __u32 i_file_acl;		/* File ACL */
-    __u32 i_dir_acl;		/* Directory ACL */
-    __u32 i_faddr;		/* Fragment address */
+    __u32 i_size_high;
+    __u32 i_obso_faddr;		/* Obsoleted fragment address */
     union
       {
 	struct
 	  {
-	    __u8 l_i_frag;	/* Fragment number */
-	    __u8 l_i_fsize;	/* Fragment size */
-	    __u16 i_pad1;
-	    __u32 l_i_reserved2[2];
+		__u16	l_i_blocks_high; /* were l_i_reserved1 */
+		__u16	l_i_file_acl_high;
+		__u16	l_i_uid_high;	/* these 2 fields */
+		__u16	l_i_gid_high;	/* were reserved2[0] */
+		__u32	l_i_reserved2;
 	  }
 	linux2;
 	struct
 	  {
-	    __u8 h_i_frag;	/* Fragment number */
-	    __u8 h_i_fsize;	/* Fragment size */
+		__u16	h_i_reserved1;	/* Obsoleted fragment number/size which are removed in ext4 */
 	    __u16 h_i_mode_high;
 	    __u16 h_i_uid_high;
 	    __u16 h_i_gid_high;
@@ -193,16 +220,36 @@
 	hurd2;
 	struct
 	  {
-	    __u8 m_i_frag;	/* Fragment number */
-	    __u8 m_i_fsize;	/* Fragment size */
-	    __u16 m_pad1;
+		__u16	h_i_reserved1;	/* Obsoleted fragment number/size which are removed in ext4 */
+		__u16	m_i_file_acl_high;
 	    __u32 m_i_reserved2[2];
 	  }
 	masix2;
       }
     osd2;			/* OS dependent 2 */
+	__u16	i_extra_isize;
+	__u16	i_pad1;
+	__u32  i_ctime_extra;  /* extra Change time      (nsec << 2 | epoch) */
+	__u32  i_mtime_extra;  /* extra Modification time(nsec << 2 | epoch) */
+	__u32  i_atime_extra;  /* extra Access time      (nsec << 2 | epoch) */
+	__u32  i_crtime;       /* File Creation time */
+	__u32  i_crtime_extra; /* extra FileCreationtime (nsec << 2 | epoch) */
+	__u32  i_version_hi;	/* high 32 bits for 64-bit version */
   };
 
+#define EXT4_FEATURE_INCOMPAT_EXTENTS		0x0040 /* extents support */
+#define EXT4_FEATURE_INCOMPAT_64BIT			0x0080 /* bergwolf:grub not supported*/
+#define EXT4_FEATURE_INCOMPAT_MMP           0x0100
+#define EXT4_FEATURE_INCOMPAT_FLEX_BG		0x0200
+
+#define EXT4_HAS_INCOMPAT_FEATURE(sb,mask)			\
+	( sb->s_feature_incompat & mask )
+
+#define EXT4_EXTENTS_FL		0x00080000 /* Inode uses extents */
+#define EXT4_HUGE_FILE_FL	0x00040000 /* Set to each huge file */
+
+#define EXT4_MIN_DESC_SIZE			32
+
 /* linux/limits.h */
 #define NAME_MAX         255	/* # chars in a file name */
 
@@ -220,6 +267,57 @@
     char name[EXT2_NAME_LEN];	/* File name */
   };
 
+/* linux/ext4_fs_extents.h */ 
+/* This is the extent on-disk structure.
+ * It's used at the bottom of the tree.
+ */
+struct ext4_extent 
+  {
+	__u32  ee_block;   /* first logical block extent covers */
+	__u16  ee_len;     /* number of blocks covered by extent */
+	__u16  ee_start_hi;    /* high 16 bits of physical block */
+	__u32  ee_start_lo;    /* low 32 bits of physical block */
+  };
+
+/*
+ * This is index on-disk structure.
+ * It's used at all the levels except the bottom.
+ */
+struct ext4_extent_idx 
+  {
+    __u32  ei_block;   /* index covers logical blocks from 'block' */
+    __u32  ei_leaf_lo; /* pointer to the physical block of the next *
+	                     * level. leaf or next index could be there */
+    __u16  ei_leaf_hi; /* high 16 bits of physical block */
+    __u16  ei_unused;
+  };
+
+/*
+ * Each block (leaves and indexes), even inode-stored has header.
+ */
+struct ext4_extent_header 
+  {
+    __u16  eh_magic;   /* probably will support different formats */
+    __u16  eh_entries; /* number of valid entries */
+    __u16  eh_max;     /* capacity of store in entries */
+    __u16  eh_depth;   /* has tree real underlying blocks? */
+    __u32  eh_generation;  /* generation of the tree */
+  };
+
+#define EXT4_EXT_MAGIC      (0xf30a)
+#define EXT_FIRST_EXTENT(__hdr__) \
+    ((struct ext4_extent *) (((char *) (__hdr__)) +     \
+                 sizeof(struct ext4_extent_header)))
+#define EXT_FIRST_INDEX(__hdr__) \
+    ((struct ext4_extent_idx *) (((char *) (__hdr__)) + \
+                 sizeof(struct ext4_extent_header)))
+#define EXT_LAST_EXTENT(__hdr__) \
+    (EXT_FIRST_EXTENT((__hdr__)) + (__u16)((__hdr__)->eh_entries) - 1)
+#define EXT_LAST_INDEX(__hdr__) \
+    (EXT_FIRST_INDEX((__hdr__)) + (__u16)((__hdr__)->eh_entries) - 1)
+
+
+
 /* linux/ext2fs.h */
 /*
  * EXT2_DIR_PAD defines the directory entries boundaries
@@ -270,8 +368,17 @@
 /* kind of from ext2/super.c */
 #define EXT2_BLOCK_SIZE(s)	(1 << EXT2_BLOCK_SIZE_BITS(s))
 /* linux/ext2fs.h */
+/* bergwolf: sizeof(struct ext2_group_desc) is changed in ext4 
+ * in kernel code, ext2/3 uses sizeof(struct ext2_group_desc) to calculate 
+ * number of desc per block, while ext4 uses superblock->s_desc_size in stead
+ * superblock->s_desc_size is not available in ext2/3
+ * */
+#define EXT2_DESC_SIZE(s) \
+	(EXT4_HAS_INCOMPAT_FEATURE(s,EXT4_FEATURE_INCOMPAT_64BIT)? \
+	s->s_desc_size : EXT4_MIN_DESC_SIZE)
 #define EXT2_DESC_PER_BLOCK(s) \
-     (EXT2_BLOCK_SIZE(s) / sizeof (struct ext2_group_desc))
+	(EXT2_BLOCK_SIZE(s) / EXT2_DESC_SIZE(s))
+
 /* linux/stat.h */
 #define S_IFMT  00170000
 #define S_IFLNK  0120000
@@ -475,6 +582,123 @@
     [logical_block & (EXT2_ADDR_PER_BLOCK (SUPERBLOCK) - 1)]);
 }
 
+/* extent binary search index
+ * find closest index in the current level extent tree
+ * kind of from ext4_ext_binsearch_idx in ext4/extents.c
+ */
+static struct ext4_extent_idx*
+ext4_ext_binsearch_idx(struct ext4_extent_header* eh, int logical_block)
+{
+  struct ext4_extent_idx *r, *l, *m;
+  l = EXT_FIRST_INDEX(eh) + 1;
+  r = EXT_LAST_INDEX(eh);
+  while (l <= r) 
+    {
+	  m = l + (r - l) / 2;
+	  if (logical_block < m->ei_block)
+		  r = m - 1;
+	  else
+		  l = m + 1;
+	}
+  return (struct ext4_extent_idx*)(l - 1);
+}
+
+/* extent binary search 
+ * find closest extent in the leaf level 
+ * kind of from ext4_ext_binsearch in ext4/extents.c
+ */
+static struct ext4_extent*
+ext4_ext_binsearch(struct ext4_extent_header* eh, int logical_block)
+{
+  struct ext4_extent *r, *l, *m;
+  l = EXT_FIRST_EXTENT(eh) + 1;
+  r = EXT_LAST_EXTENT(eh);
+  while (l <= r) 
+    {
+	  m = l + (r - l) / 2;
+	  if (logical_block < m->ee_block)
+		  r = m - 1;
+	  else
+		  l = m + 1;
+	}
+  return (struct ext4_extent*)(l - 1);
+}
+
+/* Maps extents enabled logical block into physical block via an inode. 
+ * EXT4_HUGE_FILE_FL should be checked before calling this.
+ */
+static int
+ext4fs_block_map (int logical_block)
+{
+  struct ext4_extent_header *eh;
+  struct ext4_extent *ex, *extent;
+  struct ext4_extent_idx *ei, *index;
+  int depth;
+  int i;
+
+#ifdef E2DEBUG
+  unsigned char *i;
+  for (i = (unsigned char *) INODE;
+       i < ((unsigned char *) INODE + sizeof (struct ext2_inode));
+       i++)
+    {
+      printf ("%c", "0123456789abcdef"[*i >> 4]);
+      printf ("%c", "0123456789abcdef"[*i % 16]);
+      if (!((i + 1 - (unsigned char *) INODE) % 16))
+	{
+	  printf ("\n");
+	}
+      else
+	{
+	  printf (" ");
+	}
+    }
+  printf ("logical block %d\n", logical_block);
+#endif /* E2DEBUG */
+  eh = (struct ext4_extent_header*)INODE->i_block;
+  if (eh->eh_magic != EXT4_EXT_MAGIC)
+  {
+          errnum = ERR_FSYS_CORRUPT;
+          return -1;
+  }
+  while((depth = eh->eh_depth) != 0)
+  	{ /* extent index */
+	  if (eh->eh_magic != EXT4_EXT_MAGIC)
+	  {
+	          errnum = ERR_FSYS_CORRUPT;
+		  return -1;
+	  }
+	  ei = ext4_ext_binsearch_idx(eh, logical_block);
+	  if (ei->ei_leaf_hi)
+	{/* 64bit physical block number not supported */
+	  errnum = ERR_FILELENGTH;
+	  return -1;
+	}
+	  if (!ext2_rdfsb(ei->ei_leaf_lo, DATABLOCK1))
+	{
+	  errnum = ERR_FSYS_CORRUPT;
+	  return -1;
+	}
+	  printf("next level\n");
+	  eh = (struct ext4_extent_header*)DATABLOCK1;
+  	}
+
+  /* depth==0, we come to the leaf */
+  ex = ext4_ext_binsearch(eh, logical_block);
+  if (ex->ee_start_hi) 
+	{/* 64bit physical block number not supported */
+	  errnum = ERR_FILELENGTH;
+	  return -1;
+	}
+  if ((ex->ee_block + ex->ee_len) < logical_block)
+	{
+	  errnum = ERR_FSYS_CORRUPT;
+	  return -1;
+	}
+  return ex->ee_start_lo + logical_block - ex->ee_block;
+
+}
+
 /* preconditions: all preconds of ext2fs_block_map */
 int
 ext2fs_read (char *buf, int len)
@@ -495,7 +719,12 @@
       /* find the (logical) block component of our location */
       logical_block = filepos >> EXT2_BLOCK_SIZE_BITS (SUPERBLOCK);
       offset = filepos & (EXT2_BLOCK_SIZE (SUPERBLOCK) - 1);
-      map = ext2fs_block_map (logical_block);
+      /* map logical block of an extents enabled file into a physical block on the disk */
+      if (EXT4_HAS_INCOMPAT_FEATURE(SUPERBLOCK,EXT4_FEATURE_INCOMPAT_EXTENTS) 
+                    && INODE->i_flags & EXT4_EXTENTS_FL)
+          map = ext4fs_block_map (logical_block);
+      else
+          map = ext2fs_block_map (logical_block);
 #ifdef E2DEBUG
       printf ("map=%d\n", map);
 #endif /* E2DEBUG */
@@ -579,7 +808,7 @@
   int desc;			/* index within that group */
   int ino_blk;			/* fs pointer of the inode's information */
   int str_chk = 0;		/* used to hold the results of a string compare */
-  struct ext2_group_desc *gdp;
+  struct ext4_group_desc *ext4_gdp;
   struct ext2_inode *raw_inode;	/* inode info corresponding to current_ino */
 
   char linkbuf[PATH_MAX];	/* buffer for following symbolic links */
@@ -632,8 +861,15 @@
       dump_group_desc(GROUP_DESC);
 #endif /* E2DEBUG */	
 
-      gdp = GROUP_DESC;
-      ino_blk = le32_to_cpu(gdp[desc].bg_inode_table) +
+      ext4_gdp = (struct ext4_group_desc *)( (__u8*)GROUP_DESC +
+		      desc * EXT2_DESC_SIZE(SUPERBLOCK));
+      if (EXT4_HAS_INCOMPAT_FEATURE(SUPERBLOCK, EXT4_FEATURE_INCOMPAT_64BIT)
+		      && (! ext4_gdp->bg_inode_table_hi))
+        {/* 64bit itable not supported */
+	  errnum = ERR_FILELENGTH;
+	  return -1;
+        }
+      ino_blk = ext4_gdp->bg_inode_table + 
 	(((current_ino - 1) % le32_to_cpu(SUPERBLOCK->s_inodes_per_group))
 	 >> log2 (EXT2_INODES_PER_BLOCK (SUPERBLOCK)));
 #ifdef E2DEBUG
@@ -704,7 +940,10 @@
 	    }
 	  linkbuf[filemax + len] = '\0';
 
-	  /* Read the symlink data. */
+	  /* Read the symlink data. 
+	   * Slow symlink is extents enabled
+	   * But since grub_read invokes ext2fs_read, nothing to change here
+	   * */
 	  if (! ext2_is_fast_symlink ())
 	    {
 	      /* Read the necessary blocks, and reset the file pointer. */
@@ -715,7 +954,9 @@
 	    }
 	  else
 	    {
-	      /* Copy the data directly from the inode. */
+	      /* Copy the data directly from the inode. 
+		   * Fast symlink is not extents enabled
+		   * */
 	      len = filemax;
 	      memmove (linkbuf, (char *) INODE->i_block, len);
 	    }
@@ -749,6 +990,13 @@
 	      errnum = ERR_BAD_FILETYPE;
 	      return 0;
 	    }
+	  /* if file is too large, just stop and report an error*/
+	  if ( (INODE->i_flags & EXT4_HUGE_FILE_FL) && !(INODE->i_size_high))
+	    {
+		  /* file too large, stop reading */
+		  errnum = ERR_FILELENGTH;
+		  return 0;
+	    }
 
 	  filemax = le32_to_cpu(INODE->i_size);
 	  return 1;
@@ -803,17 +1051,28 @@
 	    }
 
 	  /* else, find the (logical) block component of our location */
+	  /* ext4 logical block number the same as ext2/3 */
 	  blk = loc >> EXT2_BLOCK_SIZE_BITS (SUPERBLOCK);
 
 	  /* we know which logical block of the directory entry we are looking
 	     for, now we have to translate that to the physical (fs) block on
 	     the disk */
-	  map = ext2fs_block_map (blk);
+	  /* map logical block of an extents enabled file into a physical block on the disk */
+	  if (EXT4_HAS_INCOMPAT_FEATURE(SUPERBLOCK,EXT4_FEATURE_INCOMPAT_EXTENTS)
+			  && INODE->i_flags & EXT4_EXTENTS_FL)
+	       map = ext4fs_block_map (blk);
+	  else
+	       map = ext2fs_block_map (blk);
 #ifdef E2DEBUG
 	  printf ("ext2fs_dir: fs block=%d\n", map);
 #endif /* E2DEBUG */
 	  mapblock2 = -1;
-	  if ((map < 0) || !ext2_rdfsb (map, DATABLOCK2))
+	  if (map < 0) 
+	    {
+	      *rest = ch;
+	      return 0;
+	    }
+	  if (!ext2_rdfsb (map, DATABLOCK2))
 	    {
 	      errnum = ERR_FSYS_CORRUPT;
 	      *rest = ch;



From gregg.drwho8 at gmail.com  Sat Feb 12 04:23:53 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Fri, 11 Feb 2011 22:23:53 -0500
Subject: [coreboot] SVN service down?
In-Reply-To: <AANLkTika_NsGdS5ha27jmeYB5C7gLLvqgRyCpgQnf6qr@mail.gmail.com>
References: <AANLkTikQS3TtEqeFqBzCHqrTHD+wjwAeXQ2QTJYH98Tz@mail.gmail.com>
	<AANLkTika_NsGdS5ha27jmeYB5C7gLLvqgRyCpgQnf6qr@mail.gmail.com>
Message-ID: <AANLkTikspdJWY6K+s4xcc1YzbxxGHLghYm=BFViiqEET@mail.gmail.com>

On Fri, Feb 11, 2011 at 8:41 PM, David Hendricks <dhendrix at google.com> wrote:
> On Fri, Feb 11, 2011 at 4:34 PM, Gregg Levine <gregg.drwho8 at gmail.com>
> wrote:
>>
>> Hello!
>> I've been trying to update my checked out coreboot code drop since
>> just ten minutes ago. In fact I would bring up a console and enter at
>> the appropriate directory, "svn update" (without quotes) and wait. It
>> would seem to be hanging. Network monitors would only indicate that my
>> SSH shell is the only thing running on the host.
>
> fwiw, svn update works fine for me right now.
> --
> David Hendricks (dhendrix)
> Systems Software Engineer, Google Inc.
>

Hello!
Well at the moment I've got an open ticket with my ISP. They are going
to crawl around and check to see what is going on. Meanwhile when I
tried to use the WebDav approach there was some reference to the
certificate used by the server, and it seems to be not a nice one as
far as my setup is concerned. Probably age of my system here.

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From xdrudis at tinet.cat  Sat Feb 12 08:03:11 2011
From: xdrudis at tinet.cat (xdrudis)
Date: Sat, 12 Feb 2011 08:03:11 +0100
Subject: [coreboot] searching volunteer to install coreboot on asus
 m4a78 pro
In-Reply-To: <4D53FF9E.2020100@powercraft.nl>
References: <4D53FF9E.2020100@powercraft.nl>
Message-ID: <20110212070310.GA7274@ideafix.casa.ct>


My setup  is similar to yours, I bought it trying to get easy coreboot
support (easy, not immediate, and also some features), I've spent
some 6 months trying to "install coreboot" and it still does not
boot. But I'm not experienced in low level programming and I don't
have that much spare time to experiment. So don't count on me 
as a volunteer. It's also not something I'd like to do on ssh.
You have to do a lot of trying and exchange one chip for another,
and it's already slighty tiresome if you're there physically, let alone
having to wait for someone on IRC... There's also some risk of breaking something
that I wouldn't like to take.
   
On Thu, Feb 10, 2011 at 04:09:18PM +0100, Jelle de Jong wrote:
> 
> [1] http://debian.pastebin.com/mqphUf5U # details ASUSTeK M4A78 PRO
> 
> Features I would like:
> * Serial Console Redirection

Does your board have a serial port (RS232)?
The photos look a lot like my board. Mine has one but I don't see it in yours

http://www.mail-archive.com/coreboot at coreboot.org/msg24572.html

Try to see the marking on the EPROM chip.
I bet is the small chip on a  
300MIL 8-PDIP socket 
between the red connectors (IDE and SATA ?)
follow that thread in case it is the same chip, 
I finally bought the winbond chips from digikey in June 2010 

Idx  Box Ordered   Cancelled Shipped              Item Number/Description             Back  Unit Price Amount
                                                                                      Order  Euro       Euro
   1   1         3         0         3 W25Q80BVDAIG-ND                                        2.38000     7.14
                                       SPI FLASH 8MBIT 8-DIP
                                       SCHED B: 854232       ECCN: EAR99
                                       LEAD: LEAD FREE                    ROHS: ROHS COMP
                                       COUNTRY/ORIGIN: TAIWAN

And have worked perfectly with flashrom for me all these months.


> * AMD Athlon II X4 615e support

I have a Phenom II X4 910e 
Looks quite similar. Yours is revision RB_C3 also, I think?

I found fidvid.c did not suppport this version and coreboot 
hanged while setting frequency and voltage of the CPU. 
I've apparently fixed it but I have a 1600 lines patch, 
and I really should see how to break it up in chunks that
can be reasonably reviewed . In fact for fidvid.c itself 
the patch is bigger than the file. I hope I can do something 
this weekend to break into decent patches...

My board still doesn't boot though. It currently gets to 
ram stage and hangs while enabling pci devices. It's similar
to a problem I found in romstage and I worked around it with 
a patch that wasn't probably the right approach (it wasn't commited).
This time I'll have to see what's causing it (likely that I have
an RX781, not an RS780, it's more or less the same without 
graphics, but I may have to tweak something somehow). 

> * ECC Memory support

Not sure this works

> * Readout volt,temp,rpm sensors
> * Boot 2.6 kernel support
> * Grub 2 (lvm, mdadm, ext4) support
>

I think this will work 

> I got two M4A78 PRO motherboards that I would like to give new life by
> getting coreboot on them.
> 

New life ? They are not so old as to have died yet...
There're similar boards already that might work:
src/mainboard/asus/m4a785-m
src/mainboard/asus/m4a78-em 






From anton.kochkov at gmail.com  Sat Feb 12 10:24:42 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Sat, 12 Feb 2011 12:24:42 +0300
Subject: [coreboot] msrtool code-generation from xml definitions file.
	Preliminary release.
Message-ID: <AANLkTimZkbf3GDA6WyK06x6utPEVwMm6AYemQWwQNyZT@mail.gmail.com>

See example. Write bugs and suggestions
-- 
Best regards,
Anton Kochkov
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From jelledejong at powercraft.nl  Sat Feb 12 13:26:19 2011
From: jelledejong at powercraft.nl (Jelle de Jong)
Date: Sat, 12 Feb 2011 13:26:19 +0100
Subject: [coreboot] searching volunteer to install coreboot on asus
 m4a78 pro
In-Reply-To: <20110212070310.GA7274@ideafix.casa.ct>
References: <4D53FF9E.2020100@powercraft.nl>
	<20110212070310.GA7274@ideafix.casa.ct>
Message-ID: <4D567C6B.7050303@powercraft.nl>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 12-02-11 08:03, xdrudis wrote:
> My setup  is similar to yours, I bought it trying to get easy coreboot
> support (easy, not immediate, and also some features), I've spent
> some 6 months trying to "install coreboot" and it still does not
> boot. But I'm not experienced in low level programming and I don't
> have that much spare time to experiment. So don't count on me 
> as a volunteer. It's also not something I'd like to do on ssh.
> You have to do a lot of trying and exchange one chip for another,
> and it's already slighty tiresome if you're there physically, let alone
> having to wait for someone on IRC... There's also some risk of breaking something
> that I wouldn't like to take.

This ain?t good news :( Will a bounty of 100 Euro help to get the
coreboot working with the needed features on this motherboard in less
then 3 months?

> Does your board have a serial port (RS232)?
> The photos look a lot like my board. Mine has one but I don't see it in yours

Yes, there is a COM1 header for the serial port.

> Try to see the marking on the EPROM chip.

(see attachment) (imagebin was down)
Winbond 25X80AVA17
0903

> My board still doesn't boot though. It currently gets to 
> ram stage and hangs while enabling pci devices. It's similar
> to a problem I found in romstage and I worked around it with 
> a patch that wasn't probably the right approach (it wasn't commited).
> This time I'll have to see what's causing it (likely that I have
> an RX781, not an RS780, it's more or less the same without 
> graphics, but I may have to tweak something somehow). 

>> * ECC Memory support
> Not sure this works

Does somebody know if ECC DDR2 and DDR3 works with coreboot? It's
essential for my systems to countermeasure bitflips issues.

>> I got two M4A78 PRO motherboards that I would like to give new life by
>> getting coreboot on them.
> New life ? They are not so old as to have died yet...
> There're similar boards already that might work:
> src/mainboard/asus/m4a785-m
> src/mainboard/asus/m4a78-em 

The M4A78 PRO are not being soled any-more, I switched to expensive
server motherboards from intel and supermicro to have serial console
redirection. I use alix motherboards for all network appliances (I will
add coreboot to the alix systems soon)

For my customer-grade server motherboards I'm now using:
Gigabyte GA-890GPA-UD3H [1]
Asus M4A89GTD PRO [2]
[1] http://www.asus.com/product.aspx?P_ID=Gdf0vtpVf72LTYgs
[2] http://www.gigabyte.com/products/product-page.aspx?pid=3516#sp

If it is better to donate one of these motherboards to an coreboot
developer please tell me where to send one and what would be a
reasonable ETA (in months) for a working coreboot system?

Thanks in advance,

With kind regards,

Jelle de Jong
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From svn at coreboot.org  Sat Feb 12 17:24:49 2011
From: svn at coreboot.org (repository service)
Date: Sat, 12 Feb 2011 17:24:49 +0100
Subject: [coreboot] [commit] r6343 - in trunk/src/southbridge/amd: sb600
	sb800
Message-ID: <E1PoIHB-0004jv-A0@ra.coresystems.de>

Author: ruik
Date: Sat Feb 12 17:24:48 2011
New Revision: 6343
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6343

Log:
Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC. 
Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...

Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.

While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz> 
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/southbridge/amd/sb600/early_setup.c
   trunk/src/southbridge/amd/sb600/lpc.c
   trunk/src/southbridge/amd/sb800/early_setup.c
   trunk/src/southbridge/amd/sb800/lpc.c

Modified: trunk/src/southbridge/amd/sb600/early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/sb600/early_setup.c	Thu Feb 10 21:49:56 2011	(r6342)
+++ trunk/src/southbridge/amd/sb600/early_setup.c	Sat Feb 12 17:24:48 2011	(r6343)
@@ -364,26 +364,8 @@
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
 	/* DMA enable */
 	pci_write_config8(dev, 0x40, 0x04);
-
-	/* IO Port Decode Enable */
-	pci_write_config8(dev, 0x44, 0xFF);
-	pci_write_config8(dev, 0x45, 0xFF);
-	pci_write_config8(dev, 0x46, 0xC3);
-	pci_write_config8(dev, 0x47, 0xFF);
-
-	// TODO: This has already been done(?)
-	/* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
-	 *  Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
-	 * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65). */
-	byte = pci_read_config8(dev, 0x48);
-	byte |= (1 << 1) | (1 << 0);	/* enable Super IO config port 2e-2h, 4e-4f */
-	byte |= 1 << 6;		/* enable for RTC I/O range */
-	pci_write_config8(dev, 0x48, byte);
+	/* LPC Sync Timeout */
 	pci_write_config8(dev, 0x49, 0xFF);
-	/* Enable 0x480-0x4bf, 0x4700-0x470B */
-	byte = pci_read_config8(dev, 0x4A);
-	byte |= ((1 << 1) + (1 << 6));	/*0x42, save the configuraion for port 0x80. */
-	pci_write_config8(dev, 0x4A, byte);
 
 	/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
 	pci_write_config8(dev, 0x7C, 0x05);

Modified: trunk/src/southbridge/amd/sb600/lpc.c
==============================================================================
--- trunk/src/southbridge/amd/sb600/lpc.c	Thu Feb 10 21:49:56 2011	(r6342)
+++ trunk/src/southbridge/amd/sb600/lpc.c	Sat Feb 12 17:24:48 2011	(r6343)
@@ -103,7 +103,8 @@
 	struct bus *link;
 	u32 reg, reg_x;
 	int var_num = 0;
-	u16 reg_var[3];
+	u16 reg_var[3] = {0x0, 0x0, 0x0};
+	u8 wiosize = pci_read_config8(dev, 0x74);
 
 	reg = pci_read_config32(dev, 0x44);
 	reg_x = pci_read_config32(dev, 0x48);
@@ -134,13 +135,14 @@
 					case 0x2f8:	/*  COM2 */
 						reg |= (1 << 7);
 						break;
-					case 0x378:	/*  Parallal 1 */
+					case 0x378:	/*  Parallel 1 */
 						reg |= (1 << 0);
+						reg |= (1 << 1); /* + 0x778 for ECP */
 						break;
 					case 0x3f0:	/*  FD0 */
 						reg |= (1 << 26);
 						break;
-					case 0x220:	/*  Aduio 0 */
+					case 0x220:	/*  Audio 0 */
 						reg |= (1 << 8);
 						break;
 					case 0x300:	/*  Midi 0 */
@@ -170,12 +172,19 @@
 						switch (var_num) {
 						case 0:
 							reg_x |= (1 << 2);
+							if ((end - base) < 16)
+								wiosize |= (1 << 0);
 							break;
 						case 1:
 							reg_x |= (1 << 24);
+							if ((end - base) < 16)
+								wiosize |= (1 << 2);
 							break;
 						case 2:
 							reg_x |= (1 << 25);
+							reg_x |= (1 << 24);
+							if ((end - base) < 16)
+								wiosize |= (1 << 3);
 							break;
 						}
 						reg_var[var_num++] =
@@ -197,6 +206,7 @@
 		pci_write_config16(dev, 0x64, reg_var[0]);
 		break;
 	}
+	pci_write_config8(dev, 0x74, wiosize);
 }
 
 static void sb600_lpc_enable_resources(device_t dev)

Modified: trunk/src/southbridge/amd/sb800/early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/sb800/early_setup.c	Thu Feb 10 21:49:56 2011	(r6342)
+++ trunk/src/southbridge/amd/sb800/early_setup.c	Sat Feb 12 17:24:48 2011	(r6343)
@@ -450,26 +450,8 @@
 	/* DMA enable */
 	pci_write_config8(dev, 0x40, 0x04);
 
-	/* IO Port Decode Enable */
-	pci_write_config8(dev, 0x44, 0xFF);
-	pci_write_config8(dev, 0x45, 0xFF);
-	pci_write_config8(dev, 0x46, 0xC3);
-	pci_write_config8(dev, 0x47, 0xFF);
-
-	/* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
-	 *  Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
-	 * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
-	 * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
-	byte = pci_read_config8(dev, 0x48);
-	byte |= (1 << 1) | (1 << 0);	/* enable Super IO config port 2e-2h, 4e-4f */
-	byte |= (1 << 3) | (1 << 4);	/* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
-	byte |= 1 << 6;		/* enable for RTC I/O range */
-	pci_write_config8(dev, 0x48, byte);
+	/* LPC Sync Timeout */
 	pci_write_config8(dev, 0x49, 0xFF);
-	/* Enable 0x480-0x4bf, 0x4700-0x470B */
-	byte = pci_read_config8(dev, 0x4A);
-	byte |= ((1 << 1) + (1 << 6));	/*0x42, save the configuraion for port 0x80. */
-	pci_write_config8(dev, 0x4A, byte);
 
 	/* Set LPC ROM size, it has been done in sb800_lpc_init().
 	 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;

Modified: trunk/src/southbridge/amd/sb800/lpc.c
==============================================================================
--- trunk/src/southbridge/amd/sb800/lpc.c	Thu Feb 10 21:49:56 2011	(r6342)
+++ trunk/src/southbridge/amd/sb800/lpc.c	Sat Feb 12 17:24:48 2011	(r6343)
@@ -122,7 +122,8 @@
 	struct bus *link;
 	u32 reg, reg_x;
 	int var_num = 0;
-	u16 reg_var[3];
+	u16 reg_var[3] = {0x0, 0x0, 0x0};
+	u8 wiosize = pci_read_config8(dev, 0x74);
 
 	reg = pci_read_config32(dev, 0x44);
 	reg_x = pci_read_config32(dev, 0x48);
@@ -153,13 +154,14 @@
 					case 0x2f8:	/*  COM2 */
 						reg |= (1 << 7);
 						break;
-					case 0x378:	/*  Parallal 1 */
+					case 0x378:	/*  Parallel 1 */
 						reg |= (1 << 0);
+						reg |= (1 << 1); /* + 0x778 for ECP */
 						break;
 					case 0x3f0:	/*  FD0 */
 						reg |= (1 << 26);
 						break;
-					case 0x220:	/*  Aduio 0 */
+					case 0x220:	/*  Audio 0 */
 						reg |= (1 << 8);
 						break;
 					case 0x300:	/*  Midi 0 */
@@ -189,12 +191,19 @@
 						switch (var_num) {
 						case 0:
 							reg_x |= (1 << 2);
+							if ((end - base) < 16)
+								wiosize |= (1 << 0);
 							break;
 						case 1:
 							reg_x |= (1 << 24);
+							if ((end - base) < 16)
+								wiosize |= (1 << 2);
 							break;
 						case 2:
 							reg_x |= (1 << 25);
+							reg_x |= (1 << 24);
+							if ((end - base) < 16)
+								wiosize |= (1 << 3);
 							break;
 						}
 						reg_var[var_num++] =
@@ -216,6 +225,7 @@
 		pci_write_config16(dev, 0x64, reg_var[0]);
 		break;
 	}
+	pci_write_config8(dev, 0x74, wiosize);
 }
 
 static void sb800_lpc_enable_resources(device_t dev)



From xdrudis at tinet.cat  Sat Feb 12 17:56:41 2011
From: xdrudis at tinet.cat (xdrudis)
Date: Sat, 12 Feb 2011 17:56:41 +0100
Subject: [coreboot] searching volunteer to install coreboot on asus
 m4a78 pro
In-Reply-To: <20110212163343.GB4445@ideafix.casa.ct>
References: <4D53FF9E.2020100@powercraft.nl>
	<20110212070310.GA7274@ideafix.casa.ct>
	<4D567C6B.7050303@powercraft.nl>
	<20110212163343.GB4445@ideafix.casa.ct>
Message-ID: <20110212165641.GA4935@ideafix.casa.ct>

On Sat, Feb 12, 2011 at 05:33:44PM +0100, xdrudis wrote:
 > http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=W25Q80BVDAIG-ND
>

Forgot to say: this is the one I bought (thanks to Rudolf Marek for
the advice) and it's working here with flashrom. The original chip in
my board was not yours, it was by Macronix, but yours seems even more
similar, to my limited knowledge.




From r.marek at assembler.cz  Sat Feb 12 18:31:29 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 12 Feb 2011 18:31:29 +0100
Subject: [coreboot] [PATCH] Fix superio enable calls
In-Reply-To: <4D3F3995.40206@assembler.cz>
References: <4D3F3995.40206@assembler.cz>
Message-ID: <4D56C3F1.3020702@assembler.cz>

Hi all,

Can please someone take a look into this?
Thanks,

Rudolf




From marcj303 at gmail.com  Sat Feb 12 18:33:37 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Sat, 12 Feb 2011 10:33:37 -0700
Subject: [coreboot] [FILO] r140 - trunk/filo/fs
In-Reply-To: <E1Po4nx-0008Q2-C1@ra.coresystems.de>
References: <E1Po4nx-0008Q2-C1@ra.coresystems.de>
Message-ID: <AANLkTi=JNBaFTE1Rrci-zBA-neO5Kw4FOj5h1rK4CbOE@mail.gmail.com>

On Fri, Feb 11, 2011 at 7:01 PM, repository service <svn at coreboot.org> wrote:
> Author: stepan
> Date: Sat Feb 12 03:01:44 2011
> New Revision: 140
> URL: http://tracker.coreboot.org/trac/filo/changeset/140
>
> Log:
> Allow FILO to boot off EXT4 partitions.

nice!

-- 
http://se-eng.com



From peter at stuge.se  Sat Feb 12 18:35:07 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 12 Feb 2011 18:35:07 +0100
Subject: [coreboot] [PATCH] Fix superio enable calls
In-Reply-To: <4D3F3995.40206@assembler.cz>
References: <4D3F3995.40206@assembler.cz>
Message-ID: <20110212173507.18189.qmail@stuge.se>

Rudolf Marek wrote:
> Hello,
>
> While hunting yet another bug, I noticed that part of my serial log is 
> missing. Especially I missed the Allocating & Setting resources.
>
> It turns out that the code which enables specific LDN is somewhat buggy:
>
>
>
>  static void w83627dhg_pnp_enable(device_t dev)
>  {
> -	if (!dev->enabled)
> -		return;
> -
>  	pnp_enter_ext_func_mode(dev);
>  	pnp_set_logical_device(dev);
> -	pnp_set_enable(dev, 0);
>  	pnp_exit_ext_func_mode(dev);
>  }
>
>
> So instead of enable the device the device gets disabled. However after 
> some time the serial line gets back, most likely some "enable resources" 
> might fix it.
>
> I'm attaching patch which somewhat fixes the problem and changes the 
> function to look same in all superio code. Some boards even did not convert 
> the dev->enabled to 0,1 values.
>
> Also makes me wonder some sio call pnp_enable directly, which has yet 
> another semantics, it wont enable already enabled devices just disable 
> those which declared not enabled. And no PnP enter conf magic is called 
> (maybe this is the reason).
>
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Acked-by: Peter Stuge <peter at stuge.se>



From peter at stuge.se  Sat Feb 12 18:35:34 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 12 Feb 2011 18:35:34 +0100
Subject: [coreboot] [PATCH] Fix superio enable calls
In-Reply-To: <4D56C3F1.3020702@assembler.cz>
References: <4D3F3995.40206@assembler.cz> <4D56C3F1.3020702@assembler.cz>
Message-ID: <20110212173535.18251.qmail@stuge.se>

Rudolf Marek wrote:
> Can please someone take a look into this?

Thanks for the ping. Good fix. Go for it!


//Peter



From marcj303 at gmail.com  Sat Feb 12 18:32:54 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Sat, 12 Feb 2011 10:32:54 -0700
Subject: [coreboot] searching volunteer to install coreboot on asus
	m4a78 pro
In-Reply-To: <20110212070310.GA7274@ideafix.casa.ct>
References: <4D53FF9E.2020100@powercraft.nl>
	<20110212070310.GA7274@ideafix.casa.ct>
Message-ID: <AANLkTikNkYjEEtAjZ=XSz2osyM7eQi9DAFgXdPk2dmGe@mail.gmail.com>

On Sat, Feb 12, 2011 at 12:03 AM, xdrudis <xdrudis at tinet.cat> wrote:
;;;

>> * AMD Athlon II X4 615e support
>
> I have a Phenom II X4 910e
> Looks quite similar. Yours is revision RB_C3 also, I think?
>
> I found fidvid.c did not suppport this version and coreboot
> hanged while setting frequency and voltage of the CPU.
> I've apparently fixed it but I have a 1600 lines patch,
> and I really should see how to break it up in chunks that
> can be reasonably reviewed . In fact for fidvid.c itself
> the patch is bigger than the file. I hope I can do something
> this weekend to break into decent patches...

It would be good to see this. The AMD BKDG has changed with regard to
the VID setup since the code was added. I think that dual PVI works
well, but SVI is suspect in my recent review of it. They two are not
as different as once indicated.

The fid shouldn't require too much change. There are some features
that are not supported, but nothing that should prevent booting at
maxfid.


> My board still doesn't boot though. It currently gets to
> ram stage and hangs while enabling pci devices. It's similar
> to a problem I found in romstage and I worked around it with
> a patch that wasn't probably the right approach (it wasn't commited).
> This time I'll have to see what's causing it (likely that I have
> an RX781, not an RS780, it's more or less the same without
> graphics, but I may have to tweak something somehow).

This should be a matter of getting your lspci and the devicetree to
match up. If there is no graphics, you will need to remove that and
also look for any uma stuff that might be left around.


>> * ECC Memory support
>
> Not sure this works

I think this works, but Zheng may be able to confirm when he is back
from holiday.


Marc

-- 
http://se-eng.com



From anton.kochkov at gmail.com  Sat Feb 12 19:19:01 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Sat, 12 Feb 2011 21:19:01 +0300
Subject: [coreboot] msrtool: add support for code generation from xml files
Message-ID: <AANLkTi=4nNWw6i-DVA8YjAEeyjCeEE4Gs=iLoPdXKNk5@mail.gmail.com>

msrtool: add support for Intel
Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
---
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From anton.kochkov at gmail.com  Sat Feb 12 19:27:38 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Sat, 12 Feb 2011 21:27:38 +0300
Subject: [coreboot] msrtool: add support for code generation from xml files
In-Reply-To: <AANLkTi=4nNWw6i-DVA8YjAEeyjCeEE4Gs=iLoPdXKNk5@mail.gmail.com>
References: <AANLkTi=4nNWw6i-DVA8YjAEeyjCeEE4Gs=iLoPdXKNk5@mail.gmail.com>
Message-ID: <AANLkTi=ug11Yb+UpHkirwY=jEX6r3z5o4j8BMiJYXJUw@mail.gmail.com>

msrtool: add support for code generation from xml files
Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
---

Sorry, was type error. Now it works out of the box
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From xdrudis at tinet.cat  Sat Feb 12 19:53:49 2011
From: xdrudis at tinet.cat (xdrudis)
Date: Sat, 12 Feb 2011 19:53:49 +0100
Subject: [coreboot] searching volunteer to install coreboot on asus
 m4a78 pro
In-Reply-To: <AANLkTikNkYjEEtAjZ=XSz2osyM7eQi9DAFgXdPk2dmGe@mail.gmail.com>
References: <4D53FF9E.2020100@powercraft.nl>
	<20110212070310.GA7274@ideafix.casa.ct>
	<AANLkTikNkYjEEtAjZ=XSz2osyM7eQi9DAFgXdPk2dmGe@mail.gmail.com>
Message-ID: <20110212185349.GA7933@ideafix.casa.ct>

On Sat, Feb 12, 2011 at 10:32:54AM -0700, Marc Jones wrote:
> On Sat, Feb 12, 2011 at 12:03 AM, xdrudis <xdrudis at tinet.cat> wrote:
> ;;;
> 
> >> * AMD Athlon II X4 615e support
> >
> > I have a Phenom II X4 910e
> > Looks quite similar. Yours is revision RB_C3 also, I think?
> >
> > I found fidvid.c did not suppport this version and coreboot
> > hanged while setting frequency and voltage of the CPU.
> > I've apparently fixed it but I have a 1600 lines patch,
> > and I really should see how to break it up in chunks that
> > can be reasonably reviewed . In fact for fidvid.c itself
> > the patch is bigger than the file. I hope I can do something
> > this weekend to break into decent patches...
> 
> It would be good to see this. The AMD BKDG has changed with regard to
> the VID setup since the code was added. I think that dual PVI works
> well, but SVI is suspect in my recent review of it. They two are not
> as different as once indicated.
>

My board is SVI, and I've tried to bring it to comply a little 
more with Fam10 Bios and Kernel Development Guide #31116, 
rev 3.48, April 22, 2010 . I hope it's the correct version.
 
There are still lots of FIXMEs, some paranoid checks and 
possibly some errors for any other hardware but mine. I even
removed (with #if 0) a little code I couldn't make any sense with the 
documentation, I hope it doesn't break much.

> The fid shouldn't require too much change. There are some features
> that are not supported, but nothing that should prevent booting at
> maxfid.
>

I basically found it only worked for revision B, but now I don't 
remember whether it was fid or vid. One of the hangs seemed to be
the CPU refusing to go into a pstate out of limits and coreboot
waiting infinetely for the CPU to get to that pstate.

I also don't know how much of what I've changed was really necessary,
at a certain point I just got tired of random changes and decided
to implement as much of the BKDG as I could and try again. Maybe 
some thing are in BKDG but are not really necessary for booting.
 
I'm attaching the monster. But I'm splitting it into many smaller
patches, so it may be easier to read. So you may want to wait.

> 
> > My board still doesn't boot though. It currently gets to
> > ram stage and hangs while enabling pci devices. It's similar
> > to a problem I found in romstage and I worked around it with
> > a patch that wasn't probably the right approach (it wasn't commited).
> > This time I'll have to see what's causing it (likely that I have
> > an RX781, not an RS780, it's more or less the same without
> > graphics, but I may have to tweak something somehow).
> 
> This should be a matter of getting your lspci and the devicetree to
> match up. If there is no graphics, you will need to remove that and
> also look for any uma stuff that might be left around.
>

I tried to match lspci and devicetree.cb, but I may have got it wrong.
 I didn't know that uma could hang a pci read. It basically works 
for pci devices, but once it gets to where the external graphics card
should be (00:02.0) it hangs there. 

src/southbridge/amd/rs780/rs780.c
 static u32 get_vid_did(device_t dev)

I haven't looked much into it. I wanted to send the fidvid changes
before I forget (more).
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From svn at coreboot.org  Sat Feb 12 19:54:24 2011
From: svn at coreboot.org (coreboot)
Date: Sat, 12 Feb 2011 18:54:24 -0000
Subject: [coreboot] #173: Build faiulre with gcc 4.4.3 because of
 src/pc80/mc146818rtc_early.c unused variable
In-Reply-To: <045.944f1ade890e41b7449c412e40d82c99@coreboot.org>
References: <045.944f1ade890e41b7449c412e40d82c99@coreboot.org>
Message-ID: <060.651b69ad37b87a7c6f0878bc7061cf6c@coreboot.org>

#173: Build faiulre with gcc 4.4.3 because of src/pc80/mc146818rtc_early.c unused
variable
----------------------------------+--------------------------------------
    Reporter:  anonymous          |         Owner:  stepan@?
        Type:  defect             |        Status:  closed
    Priority:  major              |     Milestone:
   Component:  coreboot           |    Resolution:  fixed
    Keywords:                     |  Dependencies:
Patch Status:  there is no patch  |
----------------------------------+--------------------------------------

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-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/173#comment:2>
coreboot <http://www.coreboot.org/>


From juhe at iki.fi  Sat Feb 12 19:55:08 2011
From: juhe at iki.fi (Juhana Helovuo)
Date: Sat, 12 Feb 2011 20:55:08 +0200
Subject: [coreboot] Tester devices [was: QA contribution]
In-Reply-To: <20110201125829.18404.qmail@stuge.se>
References: <AANLkTimaLyGgk2ZNQ7QhOWGxgUDPkyCJ=N3M8c9DnPLE@mail.gmail.com>	<20110130060515.GB19798@coreboot.org>	<AANLkTikwBeK=z-hAHN8yu3beX8jhdJzZvzSaoq8B0PBs@mail.gmail.com>	<20110130111604.4440.qmail@stuge.se>
	<4D47E8F4.3090403@iki.fi> <20110201125829.18404.qmail@stuge.se>
Message-ID: <4D56D78C.5010409@iki.fi>

Peter Stuge wrote:
> Juhana Helovuo wrote:
>> Here are some images of my first (incomplete) prototype:
>>
>> http://alpskari.asiantuntijat.org/~juhe/spi-flasher-piirilevyt/
> 
> Looks like a great start!

Now there is more progress. After some building, coding, and debugging I 
have the tester sort-of-working.

The first version of the hardware works.

In this image you can see the tester plugged into an Asus mainboard:

http://alpskari.asiantuntijat.org/~juhe/in-system-flasher/DSC08430.jpg

Today I successfully used this setup to reflash the mainboard from the 
host PC via flashrom.

The USB cable goes to a host computer, which is running a modified 
flashrom program. The flashrom is extended with a serprog_spi module, 
which can transfer SPI over the serprog protocol, and additionally 
toggle SPI bus multiplexer between the MCU and mainboard at the 
beginning and end of programming.

Target reset switch is still operated manually, but there is hardware 
support for operating also that from the tester board. Reset pins on the 
mainboard need to be connected to pin header in the corner of the bigger 
PCB, and flashrom needs to be extended to send also the reset command to 
the tester. The ATX power button can be operated in the same fashion.


The tester hardware has the following features:

* Single USB connection to host PC, tester is USB powered.
* RS-232 serial port to collect boot log from the target mainboard. 
Tested to work at 115200 bps.
* Two software-controllable switches for controlling mainboard 
pushbutton inputs. Button-sensing voltage on mainboard need not be the 
same as Vcc on tester.
* Small PCB mounted to mainboard can be powered by tester PCB or mainboard.
* Mainboard can operate normally even when tester has no power.
* Tester can access the ROM also when disconnected from the target 
mainboard.
* Two software-controllable LEDs to impress people.



The work is still quite incomplete:

* The first PCB had two layout errors (corrected by jumper wires), so it 
needs some rework.

* Some host-side software is missing. Flashrom extension or a separate 
program is needed to control the pushbutton inputs.

* The PCB could be extended to include a software-controlled isolated 
switch to control a relay, which can switch mains power of the target 
mainboard on or off. I am still uncertain whether I want to have 
self-hacked devices with 230 VAC parts in my house.

* Currently there is no tester firmware that could operate both the SPI 
and RS-232. The main problem is that the AT90USB162 microcontroller 
supports only up to five USB endpoints (including default control EP). I 
do not know if it is possible to implement two USB CDC class virtual 
serial ports with less than seven EPs. With two serial ports, one could 
represent the RS-232 interface, and other be used to control the 
programmer without writing any custom USB drivers.

This could be solved either in software by writing a custom USB driver 
for both the tester and the host, or in hardware by replacing the 
microcontroller with a more capable model. If anyone on the list can 
suggest any easier solutions, I'd be glad to hear about them.

* The handling of SPI ROM is horribly slow. Programming and verifying 1 
MByte ROM takes about half an hour. The main suspect is nonexistent USB 
data buffering in the tester firmware.


Best regards,
Juhana Helovuo



From anton.kochkov at gmail.com  Sat Feb 12 21:23:37 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Sat, 12 Feb 2011 23:23:37 +0300
Subject: [coreboot] msrtool: add support for code generation from xml files.
	step 2
Message-ID: <AANLkTinE4VEYzQD4WFceBwuAwyUMx=0C8fc5F0wW+rzL@mail.gmail.com>

msrtool: add support for code generation from xml files
Search all *.msr.xml files in directory, creating *.c files from them,
produce *.patch for msrtool.c and msrtool.h
Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
---
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From anton.kochkov at gmail.com  Sun Feb 13 03:37:57 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Sun, 13 Feb 2011 05:37:57 +0300
Subject: [coreboot] pygen: code generation from xml files. step 1: msrtool
	module
Message-ID: <AANLkTi=_RRTsOqQ+Gn4cQ0AuJ3iRj2rkY4ZXyKKQJ1pw@mail.gmail.com>

msrtool: add support for code generation from xml files
Search all *.msr.xml files in directory, creating *.c files from them,
produce *.patch for msrtool.c and msrtool.h
Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
---

Next will be superiotool module and gui interface
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From buurin at gmail.com  Sun Feb 13 06:59:12 2011
From: buurin at gmail.com (Keith Hui)
Date: Sun, 13 Feb 2011 00:59:12 -0500
Subject: [coreboot] Now that I swapped in my other P2B-LS,
	I finally found out a few things
Message-ID: <AANLkTikazL=V0rstxhcbWjW+nE7he2ES_kgqyYGk4sL5@mail.gmail.com>

I have two P2B-LS mainboards. I have been doing development on a newer
rev 1.04 "Dot" board while my desktop runs a rev 1.03 board heavily
modified by myself [1]. It's my "Trophy" at my high times in modding
things.

Tonight I swapped my two P2B-LS boards so I can try coreboot on Trophy.

I know 1.04. has Winbond 83977EF for superio. Found out 1.03 has W83977TF.

The reason why SCSI isn't enabled properly is because my 1.04.
actually has broken Ultra2 SCSI hardware. I have to put my drives on
the single-ended ultra-wide port for them to be detected at all. And I
don't think it's a termination problem. Is it possible that my
previous attempts at getting the SCSI bios to load fry the hardware?

Now I need to bring in serialice to find out how the onboard
termination is controlled.

Once I figured out how to control this termination, where should I put
code to control this? A driver like Sil3114 or add to the board level
romstage?

I should update the wiki with my findings.



From anton.kochkov at gmail.com  Sun Feb 13 08:40:28 2011
From: anton.kochkov at gmail.com (=?UTF-8?B?0JDQvdGC0L7QvSDQmtC+0YfQutC+0LI=?=)
Date: Sun, 13 Feb 2011 10:40:28 +0300
Subject: [coreboot] pygen: code generation from xml files. step 1: msrtool
	module - fixes
Message-ID: <AANLkTikShYnp2rRVYT9O=dmTYiWevD8BUYZae_489JdN@mail.gmail.com>

msrtool: add support for code generation from xml files
Search all *.msr.xml files in directory, creating *.c files from them,
produce *.patch for msrtool.c and msrtool.h
Signed-off-by: Anton Kochkov <anton.kochkov at gmail.com>
---
Small fixes, included export_msr.c file, which produce *.msr.xml files
from existing code
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From marcj303 at gmail.com  Sun Feb 13 18:11:51 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Sun, 13 Feb 2011 10:11:51 -0700
Subject: [coreboot] searching volunteer to install coreboot on asus
	m4a78 pro
In-Reply-To: <20110212185349.GA7933@ideafix.casa.ct>
References: <4D53FF9E.2020100@powercraft.nl>
	<20110212070310.GA7274@ideafix.casa.ct>
	<AANLkTikNkYjEEtAjZ=XSz2osyM7eQi9DAFgXdPk2dmGe@mail.gmail.com>
	<20110212185349.GA7933@ideafix.casa.ct>
Message-ID: <AANLkTimBKdhn-a9ZFJFez+Z=usFHXkH0NYCzfQFKHFuS@mail.gmail.com>

On Sat, Feb 12, 2011 at 11:53 AM, xdrudis <xdrudis at tinet.cat> wrote:
> On Sat, Feb 12, 2011 at 10:32:54AM -0700, Marc Jones wrote:
>> On Sat, Feb 12, 2011 at 12:03 AM, xdrudis <xdrudis at tinet.cat> wrote:
>> ;;;
>>
>> >> * AMD Athlon II X4 615e support
>> >
>> > I have a Phenom II X4 910e
>> > Looks quite similar. Yours is revision RB_C3 also, I think?
>> >
>> > I found fidvid.c did not suppport this version and coreboot
>> > hanged while setting frequency and voltage of the CPU.
>> > I've apparently fixed it but I have a 1600 lines patch,
>> > and I really should see how to break it up in chunks that
>> > can be reasonably reviewed . In fact for fidvid.c itself
>> > the patch is bigger than the file. I hope I can do something
>> > this weekend to break into decent patches...
>>
>> It would be good to see this. The AMD BKDG has changed with regard to
>> the VID setup since the code was added. I think that dual PVI works
>> well, but SVI is suspect in my recent review of it. They two are not
>> as different as once indicated.
>>
>
> My board is SVI, and I've tried to bring it to comply a little
> more with Fam10 Bios and Kernel Development Guide #31116,
> rev 3.48, April 22, 2010 . I hope it's the correct version.
>
> There are still lots of FIXMEs, some paranoid checks and
> possibly some errors for any other hardware but mine. I even
> removed (with #if 0) a little code I couldn't make any sense with the
> documentation, I hope it doesn't break much.
>
>> The fid shouldn't require too much change. There are some features
>> that are not supported, but nothing that should prevent booting at
>> maxfid.
>>
>
> I basically found it only worked for revision B, but now I don't
> remember whether it was fid or vid. One of the hangs seemed to be
> the CPU refusing to go into a pstate out of limits and coreboot
> waiting infinetely for the CPU to get to that pstate.
>
> I also don't know how much of what I've changed was really necessary,
> at a certain point I just got tired of random changes and decided
> to implement as much of the BKDG as I could and try again. Maybe
> some thing are in BKDG but are not really necessary for booting.
>
> I'm attaching the monster. But I'm splitting it into many smaller
> patches, so it may be easier to read. So you may want to wait.
>

This is great. I see several key changes that should help SVI. I'll
look for the smaller patches. They will be easier to work through.


>>
>> > My board still doesn't boot though. It currently gets to
>> > ram stage and hangs while enabling pci devices. It's similar
>> > to a problem I found in romstage and I worked around it with
>> > a patch that wasn't probably the right approach (it wasn't commited).
>> > This time I'll have to see what's causing it (likely that I have
>> > an RX781, not an RS780, it's more or less the same without
>> > graphics, but I may have to tweak something somehow).
>>
>> This should be a matter of getting your lspci and the devicetree to
>> match up. If there is no graphics, you will need to remove that and
>> also look for any uma stuff that might be left around.
>>
>
> I tried to match lspci and devicetree.cb, but I may have got it wrong.
> ?I didn't know that uma could hang a pci read. It basically works
> for pci devices, but once it gets to where the external graphics card
> should be (00:02.0) it hangs there.

This may be a 780 PCIe config issue. It can be set to a number of
different configurations for links and lanes. You'll want to take a
look at the 780 RPR section 5.5 to start. Settings from the vendor
BIOS should also help you understand how it is connected.

Marc


-- 
http://se-eng.com



From namedylan at gmail.com  Sun Feb 13 21:17:48 2011
From: namedylan at gmail.com (Fengwei Zhang)
Date: Sun, 13 Feb 2011 15:17:48 -0500
Subject: [coreboot] question: Is it possible for OS to initialize the memory
Message-ID: <4D583C6C.9020903@gmail.com>

Hi all,

recently, I am using coreboot for my project. I have two DIMM slots on 
my board and I installed two memory modules on it(each DIMM slot has a 
memory module). Currently, I let coreboot initialize one of them. After 
loading operating system, I would like to use OS to initialize another 
memory module. my question is: Is it feasible for OS to initialize the 
another memory module?
I looked at the BKDG of my board, I didn't see any documented words 
saying I can do or cannot do this. I would appreciate it if anyone could 
give me some hints or direction of what documents I need to look at.

Thanks,
Fengwei




From mr.nuke.me at gmail.com  Sun Feb 13 23:43:38 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Mon, 14 Feb 2011 00:43:38 +0200
Subject: [coreboot] question: Is it possible for OS to initialize the
 memory
In-Reply-To: <4D583C6C.9020903@gmail.com>
References: <4D583C6C.9020903@gmail.com>
Message-ID: <4D585E9A.50600@gmail.com>

AFAIK, the controller needs to initialise all channels at once. Worse
yet, if you only have two slots, chances are those are on the same
channel, so commands intended for the first dimm will unavoidably reach
the second dimm. You would need to stop the MC for this to happen. You
lose all the tables left by the BIOS in the memory.

That, and there's no reason you'd want to do this. If you had a board
with several sockets, you could theoretically initialize MCs on
application processors independently, but it's too much unnecessary work
IMO.

It's unfeasible and impractical, but if you still want information on
this, the BKDG is your bible.

Alex

On 02/13/2011 10:17 PM, Fengwei Zhang wrote:
> Hi all,
> 
> recently, I am using coreboot for my project. I have two DIMM slots on
> my board and I installed two memory modules on it(each DIMM slot has a
> memory module). Currently, I let coreboot initialize one of them. After
> loading operating system, I would like to use OS to initialize another
> memory module. my question is: Is it feasible for OS to initialize the
> another memory module?
> I looked at the BKDG of my board, I didn't see any documented words
> saying I can do or cannot do this. I would appreciate it if anyone could
> give me some hints or direction of what documents I need to look at.
> 
> Thanks,
> Fengwei
> 
> 




From scott at notabs.org  Mon Feb 14 00:36:16 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 13 Feb 2011 17:36:16 -0600
Subject: [coreboot] Unused files
In-Reply-To: <20110112225225.GA2193@coreboot.org>
References: <20110112193923.GA9235@coreboot.org>
	<AANLkTi=Ow9RJbz-Yzwot3uXrjf35cnMs-rgexYnt7xEN@mail.gmail.com>
	<81402CC9560B4EB197647EABEADFCCEC@m3a78>
	<20110112225225.GA2193@coreboot.org>
Message-ID: <D3E7DA44D78C4AC1B1FE49989F395FE9@m3a78>

]* Scott Duplichan <scott at notabs.org> [110112 23:35]:
]> On Wed, Jan 12, 2011 at 12:39 PM, Stefan Reinauer <stepan at coreboot.org> wrote:
]> > These include files are unused, they are never included
]> >
]> > src/cpu/amd/model_10xxx/mc_patch_01000020.h
]> > src/cpu/amd/model_10xxx/mc_patch_01000083.h
]> > src/cpu/amd/model_10xxx/mc_patch_01000084.h
]> > src/cpu/intel/model_f1x/multiplier.h
]> > src/cpu/intel/model_f0x/multiplier.h
]> > src/southbridge/amd/cs5536/smbus2.h
]> >
]> > I vote for dropping them.
]> >
]> > Stefan
]> 
]> ]I agree, the patch files have been replaced by newer version.
]> ]
]> ]Marc
]> ]-- 
]> ]http://se-eng.com
]> 
]> All the AMD family 10h patches are quite old. The first 4 bytes show dates of:
]> mc_patch_010000B6   07/31/2009
]> mc_patch_0100009F   12/17/2008
]> mc_patch_01000086   05/01/2008
]> mc_patch_01000095   11/04/2008
]> mc_patch_01000096   11/05/2008
]> 
]> The AMI BIOS in my Asustek m3A78 family 10h motherboard has 2010 patches.
] 
]Where can we get newer microcode patches from? AMD anyone?
]
]Stefan

Today's patch from AMD contains these family 10h patches:

01000085
010000c6
010000c7
010000c8
010000c4
010000c5
010000bf

Thanks,
Scott




From scott at notabs.org  Mon Feb 14 00:22:33 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 13 Feb 2011 17:22:33 -0600
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code.  Patch 1 of 8.
In-Reply-To: <276EC11373289744A112A8FE66755067019CFD642A@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE66755067019CFD642A@SAUSEXMBP01.amd.com>
Message-ID: <5E7963AF22104D9EBB0D681052B1B826@m3a78>

]From: coreboot-bounces+scott=notabs.org at coreboot.org [mailto:coreboot-]bounces+scott=notabs.org at coreboot.org] On Behalf Of Vibrans,
Frank
]Sent: Sunday, February 13, 2011 03:43 PM
]To: coreboot at coreboot.org
]Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.
]
]Add AMD Agesa and AMD CIMx SB800 code.  Patch 1 of 8.
]
]This code currently generates many warnings that are functionally benign.  These are
]being addressed, but the wheels of bureaucracy turn slowly.  This drop supports AMD
]cpu families 10h and 14h.  Only Family 14h is used as an example in this set of
]patches.  Other cpu families are supported by the infrastructure, but their specific
]support is not included herein.  This patch is functionally independent of the other
]patches in this set.
]
]Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
]
]--
]
]This patch is compressed because when it expands, it is 11.3 MB or so.


Wow, thanks a lot Frank and AMD folks. I will be satisfied to suppress
the warnings for this part of the build, knowing the code is already
well proven.

This is quite a milestone for coreboot. Now half of the major processor
vendors support coreboot for their current products.

Thanks,
Scott




From nathan at traverse.com.au  Mon Feb 14 04:20:26 2011
From: nathan at traverse.com.au (Nathan Williams)
Date: Mon, 14 Feb 2011 14:20:26 +1100
Subject: [coreboot] [FILO] r140 - trunk/filo/fs
In-Reply-To: <E1Po4nx-0008Q2-C1@ra.coresystems.de>
References: <E1Po4nx-0008Q2-C1@ra.coresystems.de>
Message-ID: <1297653626.12484.6.camel@dualcore.traverse>

On Sat, 2011-02-12 at 03:01 +0100, repository service wrote:
> Author: stepan
> Date: Sat Feb 12 03:01:44 2011
> New Revision: 140
> URL: http://tracker.coreboot.org/trac/filo/changeset/140
> 
> Log:
> Allow FILO to boot off EXT4 partitions.
> 
> Using adapted http://grub4ext4.googlecode.com/svn/trunk/ext4-support
> 
> Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
> 
> Modified:
>    trunk/filo/fs/fsys_ext2fs.c
> 

This doesn't compile with CONFIG_DEBUG_FSYS_EXT2FS=y

Regards,
Nathan

Found Libpayload /home/nathan/coreboot/payloads/filo/build/libpayload/lib/libpayload.a.
  CC      build/i386/context.o
  CC      build/i386/segment.o
  CC      build/i386/timer.o
  CC      build/i386/sys_info.o
  CC      build/i386/linux_load.o
  CC      build/main/filo.o
  CC      build/main/strtox.o
  CC      build/main/elfload.o
  CC      build/main/ipchecksum.o
  CC      build/fs/blockdev.o
  CC      build/fs/vfs.o
  CC      build/fs/fsys_ext2fs.o
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:411: warning: ?struct ext2_group_desc? declared inside parameter list
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:411: warning: its scope is only this definition or declaration, which is probably not what you want
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function ?dump_group_desc?:
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:414: error: dereferencing pointer to incomplete type
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:415: error: dereferencing pointer to incomplete type
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:416: error: dereferencing pointer to incomplete type
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:417: error: dereferencing pointer to incomplete type
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:418: error: dereferencing pointer to incomplete type
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:419: error: dereferencing pointer to incomplete type
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function ?ext4fs_block_map?:
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:640: error: conflicting types for ?i?
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:637: note: previous declaration of ?i? was here
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function ?ext2fs_dir?:
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:861: warning: passing argument 1 of ?dump_group_desc? from incompatible pointer type
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:411: note: expected ?struct ext2_group_desc *? but argument is of type ?struct ext2_group_desc *?
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:877: error: ?gdp? undeclared (first use in this function)
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:877: error: (Each undeclared identifier is reported only once
/home/nathan/coreboot/payloads/filo/fs/fsys_ext2fs.c:877: error: for each function it appears in.)
make: *** [/home/nathan/coreboot/payloads/filo/build/fs/fsys_ext2fs.o] Error 1




From svens at stackframe.org  Mon Feb 14 10:57:24 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Mon, 14 Feb 2011 10:57:24 +0100
Subject: [coreboot] [PATCH v3] Lenovo X60s Support
Message-ID: <87pqqvhraz.fsf@begreifnix.stackframe.org>

Hi List,

this patch adds support for Lenovo X60s (Model 1703)
Thinkpads. It is a basic Patch without SMI and ACPI,
as this makes it probably easier to review. I'll send
SMI and ACPI Patches as soon as the patch is commited.

Signed-off-by: Sven Schnelle <svens at stackframe.org>

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From svens at stackframe.org  Mon Feb 14 11:54:22 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Mon, 14 Feb 2011 11:54:22 +0100
Subject: [coreboot] [PATCH v4] Lenovo X60s support
Message-ID: <87lj1ij38h.fsf@begreifnix.stackframe.org>

Hi List,

next version of my patch because:

- re-add old Copyright to copied files
- add small GPIO description (not proven to be correct,
  and the actual register values are still taken from vendors
  settings)

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From svn at coreboot.org  Mon Feb 14 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 14 Feb 2011 16:00:02 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1PozuE-0005ze-8C@ra.coresystems.de>

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From seppk at arcor.de  Mon Feb 14 16:17:43 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Mon, 14 Feb 2011 16:17:43 +0100
Subject: [coreboot] patch for errata#169
Message-ID: <4D594797.80003@arcor.de>

this patch should be applied to k8_f0 (NODE_HT(x)), not k8_f3 (NODE_MC(x)).
see patch for details.

Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>
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From seppk at arcor.de  Mon Feb 14 17:07:51 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Mon, 14 Feb 2011 17:07:51 +0100
Subject: [coreboot] amd/rs690/gfx.c cleanup
Message-ID: <4D595357.50302@arcor.de>

removed /* LPC DMA Deadlock workaround? */ ...

setting bit#21 in k8_f0#68 is part of the errata#169 which is handled in 
amdk8/coherent.c

see patch for details.

Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>

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Name: rs690_gfx.diff
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110214/d62a4f65/attachment.ksh>

From mr.nuke.me at gmail.com  Mon Feb 14 17:10:10 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Mon, 14 Feb 2011 18:10:10 +0200
Subject: [coreboot] amd/rs690/gfx.c cleanup
In-Reply-To: <4D595357.50302@arcor.de>
References: <4D595357.50302@arcor.de>
Message-ID: <4D5953E2.6070306@gmail.com>

On 02/14/2011 06:07 PM, Josef Kellermann wrote:
> removed /* LPC DMA Deadlock workaround? */ ...
> 
> setting bit#21 in k8_f0#68 is part of the errata#169 which is handled in
> amdk8/coherent.c
> 
> see patch for details.
> 
> Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>
> 
WOW! Nice catch!

Acked-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>



From mr.nuke.me at gmail.com  Mon Feb 14 17:07:10 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Mon, 14 Feb 2011 18:07:10 +0200
Subject: [coreboot] patch for errata#169
In-Reply-To: <4D594797.80003@arcor.de>
References: <4D594797.80003@arcor.de>
Message-ID: <4D59532E.3000404@gmail.com>

On 02/14/2011 05:17 PM, Josef Kellermann wrote:
> this patch should be applied to k8_f0 (NODE_HT(x)), not k8_f3 (NODE_MC(x)).
> see patch for details.
> 
> Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>
> 
You are correct. This is what happens when writing patches at 2AM.
I'm glad you caught that :) .

Acked-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>



From marcj303 at gmail.com  Mon Feb 14 18:09:59 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 10:09:59 -0700
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.
In-Reply-To: <276EC11373289744A112A8FE66755067019CFD642A@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE66755067019CFD642A@SAUSEXMBP01.amd.com>
Message-ID: <AANLkTikvt9nQNW==Udrg43gojXhaLaor=GbTpAxc9-cS@mail.gmail.com>

On Sun, Feb 13, 2011 at 2:43 PM, Vibrans, Frank <Frank.Vibrans at amd.com> wrote:
> Add AMD Agesa and AMD CIMx SB800 code. ?Patch 1 of 8.
>
> This code currently generates many warnings that are functionally benign. ?These are
> being addressed, but the wheels of bureaucracy turn slowly. ?This drop supports AMD
> cpu families 10h and 14h. ?Only Family 14h is used as an example in this set of
> patches. ?Other cpu families are supported by the infrastructure, but their specific
> support is not included herein. ?This patch is functionally independent of the other
> patches in this set.
>
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>

Well done Frank. We need to recognize a group of people at AMD that
have put a lot of effort into making this happen. This has been a more
than a years effort to get through business, legal, and technical
issues.

Frank Vibrans
Gary Simpson
Kenneth Zheng
Kerry She
Kevin Tanguay
Michael Xie
Mike Materazzi
Zheng (Joe) Bao


As always, the coreboot guys have been very supportive through this as
well. Thanks to Ron, Stefan, David, Patrick and others that I am
forgetting.

I know that there were many other behind the scenes and I apologize if
I left anyone out.

Thank You Everyone Involved!

Marc

-- 
http://se-eng.com



From stefan.reinauer at coreboot.org  Mon Feb 14 19:06:50 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 14 Feb 2011 19:06:50 +0100
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.
In-Reply-To: <AANLkTikvt9nQNW==Udrg43gojXhaLaor=GbTpAxc9-cS@mail.gmail.com>
References: <276EC11373289744A112A8FE66755067019CFD642A@SAUSEXMBP01.amd.com>
	<AANLkTikvt9nQNW==Udrg43gojXhaLaor=GbTpAxc9-cS@mail.gmail.com>
Message-ID: <20110214180650.GA29618@coreboot.org>

Hi!

Thank you very much, Frank, Gary, Kenneth, Kerry, Kevin, Michael, Mike
and Zheng! And of course all the others that were involved! This is
great moment for coreboot, and we are all incredibly excited about this!

Those among the coreboot community that have done hardware ports before can
estimate how much excellent work has been put into this port, both on
the technical as well as on the legal side. Awesome job!

Apart from the actual port, we are also seeing infrastructure coming in
place that allows coreboot to support AMD processors and chipsets much
sooner and even better than in previous releases.

May AMD systems boot fast and numerously out there!

Thanks,

Stefan




From stefan.reinauer at coreboot.org  Mon Feb 14 19:07:16 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 14 Feb 2011 19:07:16 +0100
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code.  Patch 1 of 8.
In-Reply-To: <276EC11373289744A112A8FE66755067019CFD642A@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE66755067019CFD642A@SAUSEXMBP01.amd.com>
Message-ID: <20110214180716.GB29618@coreboot.org>

* Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:43]:
> Add AMD Agesa and AMD CIMx SB800 code.  Patch 1 of 8.
> 
> This code currently generates many warnings that are functionally benign.  These are
> being addressed, but the wheels of bureaucracy turn slowly.  This drop supports AMD
> cpu families 10h and 14h.  Only Family 14h is used as an example in this set of
> patches.  Other cpu families are supported by the infrastructure, but their specific
> support is not included herein.  This patch is functionally independent of the other
> patches in this set.
> 
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>




From stefan.reinauer at coreboot.org  Mon Feb 14 19:07:39 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 14 Feb 2011 19:07:39 +0100
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code.  Patch 2 of 8
In-Reply-To: <276EC11373289744A112A8FE66755067019CFD642B@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE66755067019CFD642B@SAUSEXMBP01.amd.com>
Message-ID: <20110214180738.GC29618@coreboot.org>

* Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:47]:
> Add AMD Agesa northbridge wrapper code.  Patch 2 of 8.
> 
> This code provides cpu northbridge initialization for Family 14h cpus.  It is
> dependent on the AMD Agesa code.
> 
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>





From stefan.reinauer at coreboot.org  Mon Feb 14 19:07:53 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 14 Feb 2011 19:07:53 +0100
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code.  Patch 3 of 8.
In-Reply-To: <276EC11373289744A112A8FE66755067019CFD642C@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE66755067019CFD642C@SAUSEXMBP01.amd.com>
Message-ID: <20110214180753.GD29618@coreboot.org>

* Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:49]:
> Add AMD CIMx SB800 wrapper code.  Patch 3 of 8.
> 
> This code provides southbridge initialization for SB800 south bridges.  It is
> dependent on the AMD CIMx/SB800 code.
> 
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>




From stefan.reinauer at coreboot.org  Mon Feb 14 19:08:11 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 14 Feb 2011 19:08:11 +0100
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code.  Patch 4 of 8.
In-Reply-To: <276EC11373289744A112A8FE66755067019CFD642D@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE66755067019CFD642D@SAUSEXMBP01.amd.com>
Message-ID: <20110214180811.GE29618@coreboot.org>

* Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:50]:
> Add AMD cpu wrapper code.  Patch 4 of 8.
> 
> This code provides cpu early initialization for Family 14h cpus.  It is
> dependent on the AMD Agesa code.
> 
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
> 

> Add AMD cpu wrapper code.  Patch 4 of 8.
> 
> This code provides cpu early initialization for Family 14h cpus.  It is
> dependent on the AMD Agesa code.
> 
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>




From stefan.reinauer at coreboot.org  Mon Feb 14 19:08:22 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 14 Feb 2011 19:08:22 +0100
Subject: [coreboot] (no subject)
In-Reply-To: <276EC11373289744A112A8FE66755067019CFD642E@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE66755067019CFD642E@SAUSEXMBP01.amd.com>
Message-ID: <20110214180822.GF29618@coreboot.org>

* Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:52]:
> Add support for AMD Agesa wrapper code.  Patch 5 of 8.
> 
> This code fixes a number of build issues related to the AMD Agesa code.
> The particular issues are global variables existing in romstage and the
> use of GCC intrinsics in the build.  The former issue will be addressed
> shortly, and the latter issue requires community assistance.  This code
> is dependent on the AMD Family 14h mainboard code.
> 
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>




From stefan.reinauer at coreboot.org  Mon Feb 14 19:08:39 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 14 Feb 2011 19:08:39 +0100
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code.  Patch 6 of 8.
In-Reply-To: <276EC11373289744A112A8FE66755067019CFD642F@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE66755067019CFD642F@SAUSEXMBP01.amd.com>
Message-ID: <20110214180839.GG29618@coreboot.org>

* Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:53]:
> Add Fintek f81865f superio code.  Patch 6 of 8.
> 
> This code provides support for the superio chip on the IBASE Technology
> DB-FT1 (AMD code name Persimmon) platform.  It is independent of the AMD
> code.
> 
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>




From stefan.reinauer at coreboot.org  Mon Feb 14 19:08:55 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 14 Feb 2011 19:08:55 +0100
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code.  Patch 7 of 8.
In-Reply-To: <276EC11373289744A112A8FE66755067019CFD6430@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE66755067019CFD6430@SAUSEXMBP01.amd.com>
Message-ID: <20110214180855.GH29618@coreboot.org>

* Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:55]:
> Add SMSC KBC 1100 superio code.  Patch 7 of 8.
> 
> This code provides support for the superio chip on the AMD Inagua
> platform (not commercially available).  It is independent of the AMD
> code.
> 
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>




From stefan.reinauer at coreboot.org  Mon Feb 14 19:09:09 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 14 Feb 2011 19:09:09 +0100
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code.  Patch 8 of 8.
In-Reply-To: <276EC11373289744A112A8FE66755067019CFD6431@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE66755067019CFD6431@SAUSEXMBP01.amd.com>
Message-ID: <20110214180909.GI29618@coreboot.org>

* Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:55]:
> Add IBASE DB-FT1 and AMD Inagua motherboards.  Patch 8 of 8.
> 
> This code provides support for IBASE Technology DB-FT1 (AMD code
> name Persimmon) and AMD Inagua platforms.  It is dependent on all
> other patches in this set.
> 
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>




From marcj303 at gmail.com  Mon Feb 14 19:32:01 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 11:32:01 -0700
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.
In-Reply-To: <20110214180716.GB29618@coreboot.org>
References: <276EC11373289744A112A8FE66755067019CFD642A@SAUSEXMBP01.amd.com>
	<20110214180716.GB29618@coreboot.org>
Message-ID: <AANLkTikMnRJZhvVO0Rp0+w+SweYtr++rrxMGoHMGyaR=@mail.gmail.com>

On Mon, Feb 14, 2011 at 11:07 AM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:43]:
>> Add AMD Agesa and AMD CIMx SB800 code. ?Patch 1 of 8.
>>
>> This code currently generates many warnings that are functionally benign. ?These are
>> being addressed, but the wheels of bureaucracy turn slowly. ?This drop supports AMD
>> cpu families 10h and 14h. ?Only Family 14h is used as an example in this set of
>> patches. ?Other cpu families are supported by the infrastructure, but their specific
>> support is not included herein. ?This patch is functionally independent of the other
>> patches in this set.
>>
>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Acked-by: Marc Jones <marcj303 at gmail.com>

Thanks Frank!

r6344

-- 
http://se-eng.com



From svn at coreboot.org  Mon Feb 14 19:35:17 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Feb 2011 19:35:17 +0100
Subject: [coreboot] [commit] r6345 - in trunk/src/northbridge/amd: .
	agesa_wrapper agesa_wrapper/family14
	agesa_wrapper/family14/root_complex
Message-ID: <E1Pp3GX-0005AI-3y@ra.coresystems.de>

Author: mjones
Date: Mon Feb 14 19:35:15 2011
New Revision: 6345
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6345

Log:
This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code.

Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Added:
   trunk/src/northbridge/amd/agesa_wrapper/
   trunk/src/northbridge/amd/agesa_wrapper/Kconfig
   trunk/src/northbridge/amd/agesa_wrapper/Makefile.inc
   trunk/src/northbridge/amd/agesa_wrapper/family14/
   trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig
   trunk/src/northbridge/amd/agesa_wrapper/family14/Makefile.inc
   trunk/src/northbridge/amd/agesa_wrapper/family14/amdfam14_conf.c
   trunk/src/northbridge/amd/agesa_wrapper/family14/bootblock.c
   trunk/src/northbridge/amd/agesa_wrapper/family14/chip.h
   trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c
   trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.h
   trunk/src/northbridge/amd/agesa_wrapper/family14/root_complex/
   trunk/src/northbridge/amd/agesa_wrapper/family14/root_complex/Kconfig
   trunk/src/northbridge/amd/agesa_wrapper/family14/root_complex/chip.h
   trunk/src/northbridge/amd/agesa_wrapper/family14/ssdt.asl
Modified:
   trunk/src/northbridge/amd/Kconfig
   trunk/src/northbridge/amd/Makefile.inc

Modified: trunk/src/northbridge/amd/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/Kconfig	Mon Feb 14 19:30:54 2011	(r6344)
+++ trunk/src/northbridge/amd/Kconfig	Mon Feb 14 19:35:15 2011	(r6345)
@@ -3,6 +3,7 @@
 source src/northbridge/amd/gx2/Kconfig
 source src/northbridge/amd/amdfam10/Kconfig
 source src/northbridge/amd/lx/Kconfig
+source src/northbridge/amd/agesa_wrapper/Kconfig
 menu "HyperTransport setup"
 	#could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8)
 	depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT

Modified: trunk/src/northbridge/amd/Makefile.inc
==============================================================================
--- trunk/src/northbridge/amd/Makefile.inc	Mon Feb 14 19:30:54 2011	(r6344)
+++ trunk/src/northbridge/amd/Makefile.inc	Mon Feb 14 19:35:15 2011	(r6345)
@@ -4,3 +4,5 @@
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
 
+subdirs-$(CONFIG_AMD_AGESA) += agesa_wrapper
+subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa

Added: trunk/src/northbridge/amd/agesa_wrapper/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/Kconfig	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+source src/northbridge/amd/agesa_wrapper/family14/Kconfig
+

Added: trunk/src/northbridge/amd/agesa_wrapper/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/Makefile.inc	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,19 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14) += family14

Added: trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,79 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+config NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+	select HAVE_DEBUG_SMBUS
+	select HYPERTRANSPORT_PLUGIN_SUPPORT
+	select MMCONF_SUPPORT
+	select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
+
+config HT3_SUPPORT
+	bool
+	default y
+	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xe0000000
+  depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+
+config MMCONF_BUS_NUMBER
+	int
+	default 256
+	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+
+config DIMM_DDR3
+	bool
+	default n
+	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+
+config DIMM_REGISTERED
+	bool
+	default n
+	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+
+if !DIMM_REGISTERED
+	config DIMM_SUPPORT
+		hex
+		default 0x0004
+endif
+
+if DIMM_DDR3
+	if DIMM_REGISTERED
+	  config DIMM_SUPPORT
+		  hex
+		  default 0x0005
+	endif
+endif
+
+config BOOTBLOCK_NORTHBRIDGE_INIT
+  string
+  default "northbridge/amd/agesa_wrapper/family14/bootblock.c"
+	depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14

Added: trunk/src/northbridge/amd/agesa_wrapper/family14/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/Makefile.inc	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+ 
+driver-y += northbridge.c
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
\ No newline at end of file

Added: trunk/src/northbridge/amd/agesa_wrapper/family14/amdfam14_conf.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/amdfam14_conf.c	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,305 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * No includes in this file because it is included into northbridge.c.
+ */
+
+struct dram_base_mask_t {
+	u32 base; //[47:27] at [28:8]
+	u32 mask; //[47:27] at [28:8] and enable at bit 0
+};
+
+static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
+{
+	device_t dev;
+	struct dram_base_mask_t d;
+#if defined(__PRE_RAM__)
+	dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
+#else
+	dev = __f1_dev[0];
+#endif	// defined(__PRE_RAM__)
+
+	u32 temp;
+	temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16]
+	d.mask = (temp & 0xffff0000); // mask out  DramMask [26:24] too
+
+	temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16]
+	d.mask |= (temp & 1); // read enable bit
+
+	d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too
+
+	return d;
+}
+
+#if CONFIG_EXT_CONF_SUPPORT
+static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
+						u32 busn_min, u32 busn_max,
+						u32 type)
+{
+	device_t dev;
+	u32 i;
+	u32 tempreg;
+	u32 index_min, index_max;
+	u32 dest_min, dest_max;
+	index_min = busn_min>>2; dest_min = busn_min - (index_min<<2);
+	index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
+
+	// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
+#if defined(__PRE_RAM__)
+	dev = NODE_PCI(nodeid, 1);
+#else
+	dev = __f1_dev[nodeid];
+#endif	// defined(__PRE_RAM__)
+	if(index_min== index_max) {
+		pci_write_config32(dev, 0x110, index_min | (type<<28));
+		tempreg = pci_read_config32(dev, 0x114);
+		for(i=dest_min; i<=dest_max; i++) {
+			tempreg &= ~(0xff<<(i*8));
+			tempreg |= (cfg_map_dest<<(i*8));
+		}
+		pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
+		pci_write_config32(dev, 0x114, tempreg);
+	} else if(index_min<index_max) {
+		pci_write_config32(dev, 0x110, index_min | (type<<28));
+		tempreg = pci_read_config32(dev, 0x114);
+		for(i=dest_min; i<=3; i++) {
+			tempreg &= ~(0xff<<(i*8));
+			tempreg |= (cfg_map_dest<<(i*8));
+		}
+		pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
+		pci_write_config32(dev, 0x114, tempreg);
+
+		pci_write_config32(dev, 0x110, index_max | (type<<28));
+		tempreg = pci_read_config32(dev, 0x114);
+		for(i=0; i<=dest_max; i++) {
+			tempreg &= ~(0xff<<(i*8));
+			tempreg |= (cfg_map_dest<<(i*8));
+		}
+		pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again
+		pci_write_config32(dev, 0x114, tempreg);
+		if((index_max-index_min)>1) {
+			tempreg = 0;
+			for(i=0; i<=3; i++) {
+				tempreg &= ~(0xff<<(i*8));
+				tempreg |= (cfg_map_dest<<(i*8));
+			}
+			for(i=index_min+1; i<index_max;i++) {
+				pci_write_config32(dev, 0x110, i | (type<<28));
+				pci_write_config32(dev, 0x114, tempreg);
+			}
+		}
+	}
+}
+#endif	// CONFIG_EXT_CONF_SUPPORT
+
+#if defined(__PRE_RAM__)
+static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
+					u32 io_min, u32 io_max, u32 nodes)
+{
+	u32 i;
+	u32 tempreg;
+	device_t dev;
+
+#if CONFIG_EXT_CONF_SUPPORT
+	if(ht_c_index<4) {
+#endif
+		/* io range allocation */
+		tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
+		for(i=0; i<nodes; i++) {
+			dev = NODE_PCI(i, 1);
+			pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
+		}
+		tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	     //base :ISA and VGA ?
+		for(i=0; i<nodes; i++){
+			dev = NODE_PCI(i, 1);
+			pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
+		}
+#if CONFIG_EXT_CONF_SUPPORT
+		return;
+	}
+
+	u32 cfg_map_dest;
+	u32 j;
+
+	// if ht_c_index > 3, We should use extend space
+
+	if(io_min>io_max) return;
+
+	// for nodeid at first
+	cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
+
+	set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
+
+	// all other nodes
+	cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
+	for(j = 0; j< nodes; j++) {
+		if(j== nodeid) continue;
+		set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
+	}
+#endif	// CONFIG_EXT_CONF_SUPPORT
+}
+
+
+static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
+					u32 io_min, u32 io_max, u32 nodes)
+{
+	u32 i;
+	device_t dev;
+#if CONFIG_EXT_CONF_SUPPORT
+	if(ht_c_index<4) {
+#endif
+		 /* io range allocation */
+		for(i=0; i<nodes; i++) {
+			dev = NODE_PCI(i, 1);
+			pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
+			pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
+		}
+#if CONFIG_EXT_CONF_SUPPORT
+		return;
+	}
+	// : if hc_c_index > 3, We should use io_min, io_max to clear extend space
+	u32 cfg_map_dest;
+	u32 j;
+
+
+	// all nodes
+	cfg_map_dest = 0;
+	for(j = 0; j< nodes; j++) {
+		set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
+	}
+#endif
+}
+#endif // defined(__PRE_RAM__)
+
+#if !defined(__PRE_RAM__)
+static u32 get_io_addr_index(u32 nodeid, u32 linkn)
+{
+#if 0
+	u32 index;
+
+	for(index=0; index<256; index++) {
+		if((sysconf.conf_io_addrx[index+4] == 0)){
+			sysconf.conf_io_addr[index+4] =  (nodeid & 0x3f)  ;
+			sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
+			return index;
+		 }
+	 }
+#endif
+	 return	 0;
+}
+
+static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
+{
+#if 0
+	u32 index;
+
+	for(index=0; index<64; index++) {
+		if((sysconf.conf_mmio_addrx[index+8] == 0)){
+			sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
+			sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
+			return index;
+		}
+	}
+#endif
+
+	return	 0;
+}
+
+static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
+				u32 io_min, u32 io_max)
+{
+
+	u32 tempreg;
+#if CONFIG_EXT_CONF_SUPPORT
+	if(reg!=0x110) {
+#endif
+		/* io range allocation */
+		tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
+		pci_write_config32(__f1_dev[0], reg+4, tempreg);
+
+		tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
+#if 0
+		// FIXME: can we use VGA reg instead?
+		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+			printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
+				__func__, dev_path(dev), link);
+			tempreg |= PCI_IO_BASE_VGA_EN;
+		}
+		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
+			tempreg |= PCI_IO_BASE_NO_ISA;
+		}
+#endif
+		pci_write_config32(__f1_dev[0], reg, tempreg);
+#if CONFIG_EXT_CONF_SUPPORT
+		return;
+	}
+
+	u32 cfg_map_dest;
+	u32 j;
+	// if ht_c_index > 3, We should use extend space
+	if(io_min>io_max) return;
+	// for nodeid at first
+	cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
+
+	set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
+#endif // CONFIG_EXT_CONF_SUPPORT
+}
+
+
+static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
+{
+
+	u32 tempreg;
+#if CONFIG_EXT_CONF_SUPPORT
+	if(reg!=0x110) {
+#endif
+		/* io range allocation */
+		tempreg = (nodeid&0xf) | (linkn<<4) |	 (mmio_max&0xffffff00); //limit
+		pci_write_config32(__f1_dev[0], reg+4, tempreg);
+		tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
+		pci_write_config32(__f1_dev[0], reg, tempreg);
+#if CONFIG_EXT_CONF_SUPPORT
+		return;
+	}
+
+	device_t dev;
+	u32 j;
+	// if ht_c_index > 3, We should use extend space
+	// for nodeid at first
+	u32 enable;
+
+	if(mmio_min>mmio_max) {
+		return;
+	}
+
+	enable = 1;
+
+	dev = __f1_dev[nodeid];
+	tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0);
+	pci_write_config32(dev, 0x110, index | (2<<28));
+	pci_write_config32(dev, 0x114, tempreg);
+
+	tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
+	pci_write_config32(dev, 0x110, index | (3<<28));
+	pci_write_config32(dev, 0x114, tempreg);
+#endif	// CONFIG_EXT_CONF_SUPPORT
+}
+
+#endif // !defined(__PRE_RAM__)

Added: trunk/src/northbridge/amd/agesa_wrapper/family14/bootblock.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/bootblock.c	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,29 @@
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+ 
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+
+static void bootblock_northbridge_init(void) {
+}

Added: trunk/src/northbridge/amd/agesa_wrapper/family14/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/chip.h	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_amd_agesa_wrapper_family14_config
+{
+};
+
+extern struct chip_operations northbridge_amd_agesa_wrapper_family14_ops;

Added: trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.c	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,856 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+
+#include <cpu/x86/lapic.h>
+
+#include "chip.h"
+#include "northbridge.h"
+
+
+//#define FX_DEVS NODE_NUMS
+#define FX_DEVS 1
+
+static device_t __f0_dev[FX_DEVS];
+static device_t __f1_dev[FX_DEVS];
+static device_t __f2_dev[FX_DEVS];
+static device_t __f4_dev[FX_DEVS];
+static unsigned fx_devs=0;
+
+
+device_t get_node_pci(u32 nodeid, u32 fn)
+{
+    return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+}
+
+
+static void get_fx_devs(void)
+{
+    int i;
+    for(i = 0; i < FX_DEVS; i++) {
+        __f0_dev[i] = get_node_pci(i, 0);
+        __f1_dev[i] = get_node_pci(i, 1);
+        __f2_dev[i] = get_node_pci(i, 2);
+        __f4_dev[i] = get_node_pci(i, 4);
+        if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
+            fx_devs = i+1;
+    }
+    if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
+        die("Cannot find 0:0x18.[0|1]\n");
+    }
+}
+
+
+static u32 f1_read_config32(unsigned reg)
+{
+    if (fx_devs == 0)
+        get_fx_devs();
+    return pci_read_config32(__f1_dev[0], reg);
+}
+
+
+static void f1_write_config32(unsigned reg, u32 value)
+{
+    int i;
+    if (fx_devs == 0)
+        get_fx_devs();
+    for(i = 0; i < fx_devs; i++) {
+        device_t dev;
+        dev = __f1_dev[i];
+        if (dev && dev->enabled) {
+            pci_write_config32(dev, reg, value);
+        }
+    }
+}
+
+
+static u32 amdfam14_nodeid(device_t dev)
+{
+    return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
+}
+
+
+#include "amdfam14_conf.c"
+
+
+static void northbridge_init(device_t dev)
+{
+  printk(BIOS_DEBUG, "Northbridge init\n");
+}
+
+
+static void set_vga_enable_reg(u32 nodeid, u32 linkn)
+{
+    u32 val;
+
+    val =  1 | (nodeid<<4) | (linkn<<12);
+    /* it will routing (1)mmio  0xa0000:0xbffff (2) io 0x3b0:0x3bb,
+     0x3c0:0x3df */
+    f1_write_config32(0xf4, val);
+
+}
+
+
+static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
+            unsigned goal_link)
+{
+    struct resource *res;
+    unsigned nodeid, link = 0;
+    int result;
+    res = 0;
+    for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
+        device_t dev;
+        dev = __f0_dev[nodeid];
+        if (!dev)
+            continue;
+        for(link = 0; !res && (link < 8); link++) {
+            res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
+        }
+    }
+    result = 2;
+    if (res) {
+        result = 0;
+        if (    (goal_link == (link - 1)) &&
+            (goal_nodeid == (nodeid - 1)) &&
+            (res->flags <= 1)) {
+            result = 1;
+        }
+    }
+    return result;
+}
+
+static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, unsigned link)
+{
+    struct resource *resource;
+    u32 result, reg;
+    resource = 0;
+    reg = 0;
+        result = reg_useable(0xc0, dev, nodeid, link);
+        if (result >= 1) {
+            /* I have been allocated this one */
+            reg = 0xc0;
+    }
+
+    //Ext conf space
+    if(!reg) {
+        //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range
+        u32 index = get_io_addr_index(nodeid, link);
+        reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255
+    }
+
+        resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
+
+    return resource;
+}
+
+static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, u32 link)
+{
+    struct resource *resource;
+    u32 free_reg, reg;
+    resource = 0;
+    free_reg = 0;
+    for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
+        int result;
+        result = reg_useable(reg, dev, nodeid, link);
+        if (result == 1) {
+            /* I have been allocated this one */
+            break;
+        }
+        else if (result > 1) {
+            /* I have a free register pair */
+            free_reg = reg;
+        }
+    }
+    if (reg > 0xb8) {
+        reg = free_reg;
+    }
+
+    //Ext conf space
+    if(!reg) {
+        //because of Extend conf space, we will never run out of reg,
+        // but we need one index to differ them. so same node and
+        // same link can have multi range
+        u32 index = get_mmio_addr_index(nodeid, link);
+        reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63
+
+    }
+    resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
+    return resource;
+}
+
+
+static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
+{
+    struct resource *resource;
+
+    /* Initialize the io space constraints on the current bus */
+    resource = amdfam14_find_iopair(dev, nodeid, link);
+    if (resource) {
+        u32 align;
+#if CONFIG_EXT_CONF_SUPPORT == 1
+        if((resource->index & 0x1fff) == 0x1110) { // ext
+            align = 8;
+        }
+        else
+#endif
+            align = log2(HT_IO_HOST_ALIGN);
+        resource->base  = 0;
+        resource->size  = 0;
+        resource->align = align;
+        resource->gran  = align;
+        resource->limit = 0xffffUL;
+        resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
+    }
+
+    /* Initialize the prefetchable memory constraints on the current bus */
+    resource = amdfam14_find_mempair(dev, nodeid, link);
+    if (resource) {
+        resource->base = 0;
+        resource->size = 0;
+        resource->align = log2(HT_MEM_HOST_ALIGN);
+        resource->gran = log2(HT_MEM_HOST_ALIGN);
+        resource->limit = 0xffffffffffULL;
+        resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+        resource->flags |= IORESOURCE_BRIDGE;
+
+#if CONFIG_EXT_CONF_SUPPORT == 1
+        if((resource->index & 0x1fff) == 0x1110) { // ext
+            normalize_resource(resource);
+        }
+#endif
+
+    }
+
+    /* Initialize the memory constraints on the current bus */
+    resource = amdfam14_find_mempair(dev, nodeid, link);
+    if (resource) {
+        resource->base = 0;
+        resource->size = 0;
+        resource->align = log2(HT_MEM_HOST_ALIGN);
+        resource->gran = log2(HT_MEM_HOST_ALIGN);
+        resource->limit = 0xffffffffffULL;
+        resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
+#if CONFIG_EXT_CONF_SUPPORT == 1
+        if((resource->index & 0x1fff) == 0x1110) { // ext
+            normalize_resource(resource);
+        }
+#endif
+    }
+}
+
+static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
+{
+    struct resource *min;
+    min = 0;
+    search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+    if (min && tolm > min->base) {
+        tolm = min->base;
+    }
+    return tolm;
+}
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+
+struct hw_mem_hole_info {
+    unsigned hole_startk;
+    int node_id;
+};
+
+static struct hw_mem_hole_info get_hw_mem_hole_info(void)
+{
+        struct hw_mem_hole_info mem_hole;
+        int i;
+
+        mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
+        mem_hole.node_id = -1;
+
+        struct dram_base_mask_t d;
+        u32 hole;
+        d = get_dram_base_mask(0);
+        if(d.mask & 1) {
+            hole = pci_read_config32(__f1_dev[0], 0xf0);
+            if(hole & 1) { // we find the hole
+                mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
+                mem_hole.node_id = 0; // record the node No with hole
+            }
+        }
+
+#if 0
+        // We need to double check if there is speical set on base reg and limit reg 
+            // are not continous instead of hole, it will find out it's hole_startk
+        if(mem_hole.node_id==-1) {
+            resource_t limitk_pri = 0;
+            struct dram_base_mask_t d;
+            resource_t base_k, limit_k;
+            d = get_dram_base_mask(0);
+            if(d.base & 1) {
+                base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
+                if(base_k <= 4 *1024 * 1024) {
+                    if(limitk_pri != base_k) { // we find the hole
+                        mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G
+                        mem_hole.node_id = 0;
+                    }
+                }
+
+                limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
+                limitk_pri = limit_k;
+            }
+        }
+#endif
+        
+        return mem_hole;
+}
+#endif
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
+#if CONFIG_GFXUMA == 1
+extern uint64_t uma_memory_base, uma_memory_size;
+
+static void add_uma_resource(struct device *dev, int index)
+{
+    struct resource *resource;
+
+    printk(BIOS_DEBUG, "\nFam14h - Adding UMA memory.\n");
+
+    resource = new_resource(dev, index);
+    resource->base = (resource_t) uma_memory_base;
+    resource->size = (resource_t) uma_memory_size;
+    resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+        IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+#endif
+
+static void read_resources(device_t dev)
+{
+    u32 nodeid;
+    struct bus *link;
+
+    printk(BIOS_DEBUG, "\nFam14h - read_resources.\n");
+
+    nodeid = amdfam14_nodeid(dev);
+    for(link = dev->link_list; link; link = link->next) {
+        if (link->children) {
+            amdfam14_link_read_bases(dev, nodeid, link->link_num);
+        }
+    }
+}
+
+
+static void set_resource(device_t dev, struct resource *resource,
+                u32 nodeid)
+{
+    resource_t rbase, rend;
+    unsigned reg, link_num;
+    char buf[50];
+
+    printk(BIOS_DEBUG, "\nFam14h - set_resource.\n");
+
+    /* Make certain the resource has actually been set */
+    if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+        return;
+    }
+
+    /* If I have already stored this resource don't worry about it */
+    if (resource->flags & IORESOURCE_STORED) {
+        return;
+    }
+
+    /* Only handle PCI memory and IO resources */
+    if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
+        return;
+
+    /* Ensure I am actually looking at a resource of function 1 */
+    if ((resource->index & 0xffff) < 0x1000) {
+        return;
+    }
+    /* Get the base address */
+    rbase = resource->base;
+
+    /* Get the limit (rounded up) */
+    rend  = resource_end(resource);
+
+    /* Get the register and link */
+    reg  = resource->index & 0xfff; // 4k
+    link_num = IOINDEX_LINK(resource->index);
+
+    if (resource->flags & IORESOURCE_IO) {
+        set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
+    }
+    else if (resource->flags & IORESOURCE_MEM) {
+        set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1) ;// [39:8]
+    }
+    resource->flags |= IORESOURCE_STORED;
+    sprintf(buf, " <node %x link %x>",
+        nodeid, link_num);
+    report_resource_stored(dev, resource, buf);
+}
+
+
+#if CONFIG_CONSOLE_VGA_MULTI == 1
+extern device_t vga_pri;    // the primary vga device, defined in device.c
+#endif
+
+static void create_vga_resource(device_t dev, unsigned nodeid)
+{
+    struct bus *link;
+
+    printk(BIOS_DEBUG, "\nFam14h - create_vga_resource.\n");
+
+    /* find out which link the VGA card is connected,
+     * we only deal with the 'first' vga card */
+    for (link = dev->link_list; link; link = link->next) {
+        if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+#if CONFIG_CONSOLE_VGA_MULTI == 1
+            printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
+                link->secondary,link->subordinate);
+            /* We need to make sure the vga_pri is under the link */
+            if((vga_pri->bus->secondary >= link->secondary ) &&
+                (vga_pri->bus->secondary <= link->subordinate )
+            )
+#endif
+            break;
+        }
+    }
+
+    /* no VGA card installed */
+    if (link == NULL)
+        return;
+
+    printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
+    set_vga_enable_reg(nodeid, link->link_num);
+}
+
+
+static void set_resources(device_t dev)
+{
+    unsigned nodeid;
+    struct bus *bus;
+    struct resource *res;
+
+    printk(BIOS_DEBUG, "\nFam14h - set_resources.\n");
+ 
+    /* Find the nodeid */
+    nodeid = amdfam14_nodeid(dev);
+
+    create_vga_resource(dev, nodeid);
+
+    /* Set each resource we have found */
+    for(res = dev->resource_list; res; res = res->next) {
+        set_resource(dev, res, nodeid);
+    }
+
+    for(bus = dev->link_list; bus; bus = bus->next) {
+        if (bus->children) {
+            assign_resources(bus);
+        }
+    }
+}
+
+
+/* Domain/Root Complex related code */
+
+static void domain_read_resources(device_t dev)
+{
+    unsigned reg;
+
+    printk(BIOS_DEBUG, "\nFam14h - domain_read_resources.\n");
+
+    /* Find the already assigned resource pairs */
+    get_fx_devs();
+    for(reg = 0x80; reg <= 0xc0; reg+= 0x08) {
+        u32 base, limit;
+        base  = f1_read_config32(reg);
+        limit = f1_read_config32(reg + 0x04);
+        /* Is this register allocated? */
+        if ((base & 3) != 0) {
+            unsigned nodeid, reg_link;
+            device_t reg_dev;
+            if(reg<0xc0) { // mmio
+                nodeid = (limit & 0xf) + (base&0x30);
+            } else { // io
+                nodeid =  (limit & 0xf) + ((base>>4)&0x30);
+            }
+            reg_link = (limit >> 4) & 7;
+            reg_dev = __f0_dev[nodeid];
+            if (reg_dev) {
+                /* Reserve the resource  */
+                struct resource *res;
+                res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
+                if (res) {
+                    res->flags = 1;
+                }
+            }
+        }
+    }
+    /* FIXME: do we need to check extend conf space?
+       I don't believe that much preset value */
+
+#if CONFIG_PCI_64BIT_PREF_MEM == 0
+    pci_domain_read_resources(dev);
+#else
+    struct bus *link;
+    struct resource *resource;
+    for(link=dev->link_list; link; link = link->next) {
+        /* Initialize the system wide io space constraints */
+        resource = new_resource(dev, 0|(link->link_num<<2));
+        resource->base  = 0x400;
+        resource->limit = 0xffffUL;
+        resource->flags = IORESOURCE_IO;
+
+        /* Initialize the system wide prefetchable memory resources constraints */
+        resource = new_resource(dev, 1|(link->link_num<<2));
+        resource->limit = 0xfcffffffffULL;
+        resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+
+        /* Initialize the system wide memory resources constraints */
+        resource = new_resource(dev, 2|(link->link_num<<2));
+        resource->limit = 0xfcffffffffULL;
+        resource->flags = IORESOURCE_MEM;
+    }
+#endif
+}
+
+
+static void domain_set_resources(device_t dev)
+{
+    printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n");
+    printk(BIOS_DEBUG, "  amsr - incoming dev = %08lx\n",dev);
+
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+    struct resource *io, *mem1, *mem2;
+    struct resource *res;
+#endif
+    unsigned long mmio_basek;
+    u32 pci_tolm;
+    int i, idx;
+    struct bus *link;
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+    struct hw_mem_hole_info mem_hole;
+    u32 reset_memhole = 1;
+#endif
+
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+
+printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
+    for(link = dev->link_list; link; link = link->next) {
+        /* Now reallocate the pci resources memory with the
+         * highest addresses I can manage.
+         */
+        mem1 = find_resource(dev, 1|(link->link_num<<2));
+        mem2 = find_resource(dev, 2|(link->link_num<<2));
+
+        printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+            mem1->base, mem1->limit, mem1->size, mem1->align);
+        printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+            mem2->base, mem2->limit, mem2->size, mem2->align);
+
+        /* See if both resources have roughly the same limits */
+        if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
+            ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
+        {
+            /* If so place the one with the most stringent alignment first
+             */
+            if (mem2->align > mem1->align) {
+                struct resource *tmp;
+                tmp = mem1;
+                mem1 = mem2;
+                mem2 = tmp;
+            }
+            /* Now place the memory as high up as it will go */
+            mem2->base = resource_max(mem2);
+            mem1->limit = mem2->base - 1;
+            mem1->base = resource_max(mem1);
+        }
+        else {
+            /* Place the resources as high up as they will go */
+            mem2->base = resource_max(mem2);
+            mem1->base = resource_max(mem1);
+        }
+
+        printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+            mem1->base, mem1->limit, mem1->size, mem1->align);
+        printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+            mem2->base, mem2->limit, mem2->size, mem2->align);
+    }
+
+    for(res = &dev->resource_list; res; res = res->next)
+    {
+        res->flags |= IORESOURCE_ASSIGNED;
+        res->flags |= IORESOURCE_STORED;
+        report_resource_stored(dev, res, "");
+    }
+#endif
+
+    pci_tolm = 0xffffffffUL;
+    for(link = dev->link_list; link; link = link->next) {
+        pci_tolm = my_find_pci_tolm(link, pci_tolm);
+    }
+
+    // FIXME handle interleaved nodes. If you fix this here, please fix
+    // amdk8, too.
+    mmio_basek = pci_tolm >> 10;
+    /* Round mmio_basek to something the processor can support */
+    mmio_basek &= ~((1 << 6) -1);
+
+    // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
+    // MMIO hole. If you fix this here, please fix amdk8, too.
+    /* Round the mmio hole to 64M */
+    mmio_basek &= ~((64*1024) - 1);
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+/* if the hw mem hole is already set in raminit stage, here we will compare
+ * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
+ * use hole_basek as mmio_basek and we don't need to reset hole.
+ * otherwise We reset the hole to the mmio_basek
+ */
+
+    mem_hole = get_hw_mem_hole_info();
+
+    // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
+    if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) {
+        mmio_basek = mem_hole.hole_startk;
+        reset_memhole = 0;
+    }
+#endif
+
+    idx = 0x10;
+
+    struct dram_base_mask_t d;
+    resource_t basek, limitk, sizek; // 4 1T
+
+    d = get_dram_base_mask(0);
+
+    if (d.mask & 1) {
+        basek = ((resource_t)(d.base)) << 8;
+        limitk = (resource_t)((d.mask << 8) | 0xFFFFFF);
+printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk);
+
+        /* Convert these values to multiples of 1K for ease of math. */
+        basek >>= 10;
+        limitk >>= 10;
+        sizek = limitk - basek + 1;
+
+printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek);
+
+        /* see if we need a hole from 0xa0000 to 0xbffff */
+        if ((basek < 640) && (sizek > 768)) {
+printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
+            ram_resource(dev, (idx | 0), basek, 640 - basek);
+            idx += 0x10;
+            basek = 768;
+            sizek = limitk - 768;
+        }
+
+
+printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n",  mmio_basek, basek, limitk);
+
+        /* split the region to accomodate pci memory space */
+        if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
+            if (basek <= mmio_basek) {
+                unsigned pre_sizek;
+                pre_sizek = mmio_basek - basek;
+                if(pre_sizek>0) {
+                    ram_resource(dev, idx, basek, pre_sizek);
+                    idx += 0x10;
+                    sizek -= pre_sizek;
+#if CONFIG_WRITE_HIGH_TABLES==1
+                    if (high_tables_base==0) {
+                    /* Leave some space for ACPI, PIRQ and MP tables */
+#if CONFIG_GFXUMA == 1
+                        high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
+#else
+                        high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
+#endif
+                        high_tables_size = HIGH_TABLES_SIZE * 1024;
+                        printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
+                                 high_tables_base);
+                    }
+#endif
+                }
+
+                basek = mmio_basek;
+            }
+            if ((basek + sizek) <= 4*1024*1024) {
+                sizek = 0;
+            }
+            else {
+                basek = 4*1024*1024;
+                sizek -= (4*1024*1024 - mmio_basek);
+            }
+        }
+
+        ram_resource(dev, (idx | 0), basek, sizek);
+        idx += 0x10;
+#if CONFIG_WRITE_HIGH_TABLES==1
+        printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
+                 0, mmio_basek, basek, limitk);
+        if (high_tables_base==0) {
+        /* Leave some space for ACPI, PIRQ and MP tables */
+#if CONFIG_GFXUMA == 1
+            high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
+            printk(BIOS_DEBUG, "  adsr - uma_memory_base = %x.\n",uma_memory_base);
+#else
+            high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
+#endif
+            high_tables_size = HIGH_TABLES_SIZE * 1024;
+        }
+#endif
+    }
+printk(BIOS_DEBUG, "  adsr - mmio_basek = %x.\n",mmio_basek);
+printk(BIOS_DEBUG, "  adsr - high_tables_size = %x.\n",high_tables_size);
+
+#if CONFIG_GFXUMA == 1
+    printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
+    add_uma_resource(dev, 7);
+#endif
+
+    for(link = dev->link_list; link; link = link->next) {
+        if (link->children) {
+            assign_resources(link);
+        }
+    }
+printk(BIOS_DEBUG, "  adsr - leaving this lovely routine.\n");
+}
+
+
+static void domain_enable_resources(device_t dev)
+{
+  u32 val;
+  /* Must be called after PCI enumeration and resource allocation */
+  printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n");
+  val = agesawrapper_amdinitmid (); 
+  if(val) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
+  }
+  
+  printk(BIOS_DEBUG, "  ader - leaving domain_enable_resources.\n");
+}
+
+
+/* Bus related code */
+
+
+static void cpu_bus_read_resources(device_t dev)
+{
+    printk(BIOS_DEBUG, "\nFam14h - cpu_bus_read_resources.\n");
+
+#if CONFIG_MMCONF_SUPPORT
+    struct resource *resource = new_resource(dev, 0xc0010058);
+    resource->base = CONFIG_MMCONF_BASE_ADDRESS;
+    resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+    resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+        IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
+#endif
+}
+
+static void cpu_bus_set_resources(device_t dev)
+{
+    struct resource *resource = find_resource(dev, 0xc0010058);
+
+    printk(BIOS_DEBUG, "\nFam14h - cpu_bus_set_resources.\n");
+
+    if (resource) {
+        report_resource_stored(dev, resource, " <mmconfig>");
+    }
+    pci_dev_set_resources(dev);
+}
+ 
+static void cpu_bus_init(device_t dev)
+{
+    initialize_cpus(dev->link_list);
+}
+
+
+/* North Bridge Structures */
+
+static struct device_operations northbridge_operations = {
+    .read_resources   = read_resources,
+    .set_resources    = set_resources,
+  .enable_resources = pci_dev_enable_resources,
+  .init             = northbridge_init,
+  .enable           = 0,
+  .ops_pci          = 0,
+};
+
+
+static const struct pci_driver northbridge_driver __pci_driver = {
+    .ops = &northbridge_operations,
+    .vendor = PCI_VENDOR_ID_AMD,
+    .device = 0x1510,
+};
+
+
+struct chip_operations northbridge_amd_agesa_wrapper_family14_ops = {
+    CHIP_NAME("AMD Family 14h Northbridge")
+    .enable_dev = 0,
+};
+
+
+/* Root Complex Structures */
+
+
+static struct device_operations pci_domain_ops = {
+    .read_resources   = domain_read_resources,
+    .set_resources    = domain_set_resources,
+    .enable_resources = domain_enable_resources,
+    .init             = NULL,
+    .scan_bus         = pci_domain_scan_bus,
+};
+
+
+static struct device_operations cpu_bus_ops = {
+    .read_resources   = cpu_bus_read_resources,
+    .set_resources    = cpu_bus_set_resources,
+    .enable_resources = NULL,
+    .init             = cpu_bus_init,
+    .scan_bus         = 0,
+};
+
+
+static void root_complex_enable_dev(struct device *dev)
+{
+    /* Set the operations if it is a special bus type */
+    if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+        dev->ops = &pci_domain_ops;
+    }
+    else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+        dev->ops = &cpu_bus_ops;
+    }
+}
+
+
+struct chip_operations northbridge_amd_agesa_wrapper_family14_root_complex_ops = {
+    CHIP_NAME("AMD Family 14h Root Complex")
+    .enable_dev = root_complex_enable_dev,
+};

Added: trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/northbridge.h	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_AMD_AGESA_WRAPPER_FAM14H_H
+#define NORTHBRIDGE_AMD_AGESA_WRAPPER_FAM14H_H
+
+static struct device_operations pci_domain_ops;
+static struct device_operations cpu_bus_ops;
+
+#endif /* NORTHBRIDGE_AMD_AGESA_WRAPPER_FAM14H_H */

Added: trunk/src/northbridge/amd/agesa_wrapper/family14/root_complex/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/root_complex/Kconfig	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,2 @@
+config NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
+	bool

Added: trunk/src/northbridge/amd/agesa_wrapper/family14/root_complex/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/root_complex/chip.h	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_amd_agesa_wrapper_family14_root_complex_config
+{
+};
+
+extern struct chip_operations northbridge_amd_agesa_wrapper_family14_root_complex_ops;

Added: trunk/src/northbridge/amd/agesa_wrapper/family14/ssdt.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/northbridge/amd/agesa_wrapper/family14/ssdt.asl	Mon Feb 14 19:35:15 2011	(r6345)
@@ -0,0 +1,346 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file
+ */
+
+DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM14H", "AMD-ACPI", 0x1000)
+{
+	/*
+	 * These objects were referenced but not defined in this table
+	 */
+	External (\_SB_.PCI0, DeviceObj)
+
+	Scope (\_SB.PCI0)
+	{
+		Name (BUSN, Package (0x20) /* HC_NUMS */
+		{
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x10101010,
+			0x11111111,
+			0x12121212,
+			0x13131313,
+			0x14141414,
+			0x15151515,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc
+		})
+		Name (MMIO, Package (0x80) /* HC_NUMS * 4 */
+		{
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x11111111,
+			0x22222222,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x11111111,
+			0x22222222,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x11111111,
+			0x22222222,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x11111111,
+			0x22222222,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x11111111,
+			0x22222222,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888
+		})
+		Name (PCIO, Package (0x40) /* HC_NUMS * 2 */
+		{
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444
+		})
+		Name (SBLK, 0x11)
+		Name (TOM1, 0xaaaaaaaa)
+		Name (SBDN, 0xbbbbbbbb)
+		Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */
+		{
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888
+		})
+		Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */
+		{
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888
+		})
+		Name (CBB, 0x99)
+		Name (CBST, 0x88)
+		Name (CBB2, 0x77)
+		Name (CBS2, 0x66)
+
+	}
+}
+



From marcj303 at gmail.com  Mon Feb 14 19:35:41 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 11:35:41 -0700
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 2 of 8
In-Reply-To: <20110214180738.GC29618@coreboot.org>
References: <276EC11373289744A112A8FE66755067019CFD642B@SAUSEXMBP01.amd.com>
	<20110214180738.GC29618@coreboot.org>
Message-ID: <AANLkTimuNUL5e3B1_W8PoDK7juxrnF-TkSyj-+KvNiuK@mail.gmail.com>

On Mon, Feb 14, 2011 at 11:07 AM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:47]:
>> Add AMD Agesa northbridge wrapper code. ?Patch 2 of 8.
>>
>> This code provides cpu northbridge initialization for Family 14h cpus. ?It is
>> dependent on the AMD Agesa code.
>>
>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Acked-by: Marc Jones <marcj303 at gmail.com>

Thanks Frank!

r6345


-- 
http://se-eng.com



From svn at coreboot.org  Mon Feb 14 19:38:15 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Feb 2011 19:38:15 +0100
Subject: [coreboot] [commit] r6346 - in trunk/src/southbridge/amd: .
	cimx_wrapper cimx_wrapper/sb800
Message-ID: <E1Pp3JP-00015G-Nw@ra.coresystems.de>

Author: mjones
Date: Mon Feb 14 19:38:14 2011
New Revision: 6346
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6346

Log:
This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code.

Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Added:
   trunk/src/southbridge/amd/cimx_wrapper/
   trunk/src/southbridge/amd/cimx_wrapper/Kconfig
   trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc
   trunk/src/southbridge/amd/cimx_wrapper/sb800/
   trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/AmdSbLib.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig
   trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc
   trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
   trunk/src/southbridge/amd/cimx_wrapper/sb800/cbtypes.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c
   trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/chip.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c
   trunk/src/southbridge/amd/cimx_wrapper/sb800/early.c
   trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
   trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.c
   trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.c
   trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.h
Modified:
   trunk/src/southbridge/amd/Kconfig
   trunk/src/southbridge/amd/Makefile.inc

Modified: trunk/src/southbridge/amd/Kconfig
==============================================================================
--- trunk/src/southbridge/amd/Kconfig	Mon Feb 14 19:35:15 2011	(r6345)
+++ trunk/src/southbridge/amd/Kconfig	Mon Feb 14 19:38:14 2011	(r6346)
@@ -11,3 +11,4 @@
 source src/southbridge/amd/rs780/Kconfig
 source src/southbridge/amd/sb700/Kconfig
 source src/southbridge/amd/sb800/Kconfig
+source src/southbridge/amd/cimx_wrapper/Kconfig

Modified: trunk/src/southbridge/amd/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/Makefile.inc	Mon Feb 14 19:35:15 2011	(r6345)
+++ trunk/src/southbridge/amd/Makefile.inc	Mon Feb 14 19:38:14 2011	(r6346)
@@ -10,4 +10,5 @@
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
+subdirs-$(CONFIG_AMD_CIMX_SB800) += cimx_wrapper
 

Added: trunk/src/southbridge/amd/cimx_wrapper/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/Kconfig	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+source src/southbridge/amd/cimx_wrapper/sb800/Kconfig

Added: trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,19 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800) += sb800

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,382 @@
+/*****************************************************************************
+ * AMD Generic Encapsulated Software Architecture                            */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA/CIMx core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision:$   @e \$Date:$
+ */
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+// AGESA Types and Definitions
+#ifndef NULL
+  #define NULL 0
+#endif
+
+#define LAST_ENTRY 0xFFFFFFFF
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+#define IN
+#define OUT
+
+#ifndef Int16FromChar
+#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
+#endif
+#ifndef Int32FromChar
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+#endif
+
+#define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
+
+typedef unsigned int AGESA_STATUS;
+
+#define AGESA_SUCCESS       ((AGESA_STATUS) 0x0)
+#define AGESA_ALERT         ((AGESA_STATUS) 0x40000000)
+#define AGESA_WARNING       ((AGESA_STATUS) 0x40000001)
+#define AGESA_UNSUPPORTED   ((AGESA_STATUS) 0x80000003)
+#define AGESA_ERROR         ((AGESA_STATUS) 0xC0000001)
+#define AGESA_CRITICAL      ((AGESA_STATUS) 0xC0000002)
+#define AGESA_FATAL         ((AGESA_STATUS) 0xC0000003)
+
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr);
+typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+  PreMemHeap = 0,                                           ///< Create heap in cache.
+  PostMemDram,                                              ///< Create heap in memory.
+  ByHost                                                    ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
+  AccessWidth16,                                            ///< Access width is 16 bits.
+  AccessWidth32,                                            ///< Access width is 32 bits.
+  AccessWidth64,                                            ///< Access width is 64 bits.
+
+  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
+  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
+  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
+  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+typedef struct _AMD_CONFIG_PARAMS {
+  IN       unsigned int          ImageBasePtr;     ///< The AGESA Image base address.
+  IN       unsigned int          Func;             ///< The service desired, @sa dispatch.h.
+  IN       unsigned int          AltImageBasePtr;  ///< Alternate Image location
+  IN       unsigned int          PcieBasePtr;      ///< PCIe MMIO Base address, if configured.
+  union {                                    ///< Callback pointer
+    IN       unsigned long long          PlaceHolder;    ///< Place holder
+    IN       CALLOUT_ENTRY   CalloutPtr;     ///< For Callout from AGESA
+  } CALLBACK;
+  IN OUT   unsigned int          Reserved[2];      ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// AGESA Binary module header structure
+typedef struct _AMD_IMAGE_HEADER {
+  IN       unsigned int  Signature;                          ///< Binary Signature
+  IN       signed char   CreatorID[8];                       ///< 8 characters ID
+  IN       signed char   Version[12];                        ///< 12 characters version
+  IN       unsigned int  ModuleInfoOffset;                   ///< Offset of module
+  IN       unsigned int  EntryPointAddress;                  ///< Entry address
+  IN       unsigned int  ImageBase;                          ///< Image base
+  IN       unsigned int  RelocTableOffset;                   ///< Relocate Table offset
+  IN       unsigned int  ImageSize;                          ///< Size
+  IN       unsigned short  Checksum;                           ///< Checksum
+  IN       unsigned char   ImageType;                          ///< Type
+  IN       unsigned char   V_Reserved;                         ///< Reserved
+} AMD_IMAGE_HEADER;
+
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+  IN       unsigned int          ModuleHeaderSignature;      ///< Module signature
+  IN       signed char           ModuleIdentifier[8];        ///< 8 characters ID
+  IN       signed char           ModuleVersion[12];          ///< 12 characters version
+  IN       MODULE_ENTRY    ModuleDispatcherPtr;        ///< A pointer point to dispatcher
+  IN       struct _AMD_MODULE_HEADER  *NextBlockPtr;    ///< Next module header link
+} AMD_MODULE_HEADER;
+
+#define FUNC_0    0   // bit-placed for PCI address creation
+#define FUNC_1    1
+#define FUNC_2    2
+#define FUNC_3    3
+#define FUNC_4    4
+#define FUNC_5    5
+#define FUNC_6    6
+#define FUNC_7    7
+
+//   SBDFO - Segment Bus Device Function Offset
+//   31:28   Segment (4-bits)
+//   27:20   Bus     (8-bits)
+//   19:15   Device  (5-bits)
+//   14:12   Function (3-bits)
+//   11:00   Offset  (12-bits)
+
+#if 0
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \
+                   (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
+#endif
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/// CPUID data received registers format
+typedef struct _SB_CPUID_DATA {
+  IN OUT   unsigned int          EAX_Reg;                ///< CPUID instruction result in EAX
+  IN OUT   unsigned int          EBX_Reg;                ///< CPUID instruction result in EBX
+  IN OUT   unsigned int          ECX_Reg;                ///< CPUID instruction result in ECX
+  IN OUT   unsigned int          EDX_Reg;                ///< CPUID instruction result in EDX
+} SB_CPUID_DATA;
+
+#define WARM_RESET 1
+#define COLD_RESET 2      // Cold reset
+#define RESET_CPU  4      // Triggers a CPU reset
+
+/// HT frequency for external callbacks
+typedef enum {
+  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
+  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
+  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
+  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
+  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
+  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
+  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
+  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
+  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
+  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
+  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
+  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
+  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
+  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
+  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
+  HT_FREQUENCY_3200M         = 19                 ///< HT speed 3200 for external callbacks
+} HT_FREQUENCIES;
+
+#ifndef BIT0
+  #define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+  #define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+  #define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+  #define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+  #define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+  #define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+  #define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+  #define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+  #define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+  #define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+  #define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+  #define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+  #define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+  #define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+  #define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+  #define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+  #define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+  #define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+  #define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+  #define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+  #define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+  #define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+  #define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+  #define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+  #define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+  #define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+  #define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+  #define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+  #define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+  #define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+  #define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+  #define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+  #define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+  #define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+  #define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+  #define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+  #define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+  #define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+  #define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+  #define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+  #define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+  #define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+  #define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+  #define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+  #define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+  #define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+  #define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+  #define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+  #define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+  #define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+  #define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+  #define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+  #define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+  #define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+  #define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+  #define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+  #define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+  #define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+  #define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+  #define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+  #define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+  #define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+  #define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+  #define BIT63       0x8000000000000000ull
+#endif
+#endif

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/AmdSbLib.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/AmdSbLib.h	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,175 @@
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _AMD_SB_LIB_H_
+#define _AMD_SB_LIB_H_
+
+typedef signed char  *va_list;
+#ifndef _INTSIZEOF
+  #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) )
+#endif
+
+// Also support coding convention rules for var arg macros
+#ifndef va_start
+  #define va_start(ap, v)  ( ap = (va_list)&(v) + _INTSIZEOF (v) )
+#endif
+#define va_arg(ap, t)    ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) )
+#define va_end(ap)      ( ap = (va_list)0 )
+
+
+#pragma pack (push, 1)
+
+#define IMAGE_ALIGN          32*1024
+#define NUM_IMAGE_LOCATION   32
+
+//Entry Point Call
+typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);
+
+//Hook Call
+
+typedef struct _CIMFILEHEADER
+{
+  unsigned int  AMDLogo;
+  unsigned long long  CreatorID;
+  unsigned int  Version1;
+  unsigned int  Version2;
+  unsigned int  Version3;
+  unsigned int  ModuleInfoOffset;
+  unsigned int  EntryPoint;
+  unsigned int  ImageBase;
+  unsigned int  RelocTableOffset;
+  unsigned int  ImageSize;
+  unsigned short  CheckSum;
+  unsigned char ImageType;
+  unsigned char Reserved2;
+} CIMFILEHEADER;
+
+#ifndef BIT0
+  #define BIT0 (1 << 0)
+#endif
+#ifndef BIT1
+  #define BIT1 (1 << 1)
+#endif
+#ifndef BIT2
+  #define BIT2 (1 << 2)
+#endif
+#ifndef BIT3
+  #define BIT3 (1 << 3)
+#endif
+#ifndef BIT4
+  #define BIT4 (1 << 4)
+#endif
+#ifndef BIT5
+  #define BIT5 (1 << 5)
+#endif
+#ifndef BIT6
+  #define BIT6 (1 << 6)
+#endif
+#ifndef BIT7
+  #define BIT7 (1 << 7)
+#endif
+#ifndef BIT8
+  #define BIT8 (1 << 8)
+#endif
+#ifndef BIT9
+  #define BIT9 (1 << 9)
+#endif
+#ifndef BIT10
+  #define BIT10 (1 << 10)
+#endif
+#ifndef BIT11
+  #define BIT11 (1 << 11)
+#endif
+#ifndef BIT12
+  #define BIT12 (1 << 12)
+#endif
+#ifndef BIT13
+  #define BIT13 (1 << 13)
+#endif
+#ifndef BIT14
+  #define BIT14 (1 << 14)
+#endif
+#ifndef BIT15
+  #define BIT15 (1 << 15)
+#endif
+#ifndef BIT16
+  #define BIT16 (1 << 16)
+#endif
+#ifndef BIT17
+  #define BIT17 (1 << 17)
+#endif
+#ifndef BIT18
+  #define BIT18 (1 << 18)
+#endif
+#ifndef BIT19
+  #define BIT19 (1 << 19)
+#endif
+#ifndef BIT20
+  #define BIT20 (1 << 20)
+#endif
+#ifndef BIT21
+  #define BIT21 (1 << 21)
+#endif
+#ifndef BIT22
+  #define BIT22 (1 << 22)
+#endif
+#ifndef BIT23
+  #define BIT23 (1 << 23)
+#endif
+#ifndef  BIT24
+  #define BIT24 (1 << 24)
+#endif
+#ifndef BIT25
+  #define BIT25 (1 << 25)
+#endif
+#ifndef BIT26
+  #define BIT26 (1 << 26)
+#endif
+#ifndef BIT27
+  #define BIT27 (1 << 27)
+#endif
+#ifndef BIT28
+  #define BIT28 (1 << 28)
+#endif
+#ifndef BIT29
+  #define BIT29 (1 << 29)
+#endif
+#ifndef BIT30
+  #define BIT30 (1 << 30)
+#endif
+#ifndef BIT31
+  #define BIT31 (1 << 31)
+#endif
+
+#pragma pack (pop)
+
+typedef enum
+{
+  AccWidthUint8 = 0,
+  AccWidthUint16,
+  AccWidthUint32,
+} ACC_WIDTH;
+
+#define S3_SAVE  0x80
+
+#endif

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,29 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+	bool
+	select IOAPIC
+
+if SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+        string
+        default "southbridge/amd/cimx_wrapper/sb800/bootblock.c"
+endif #SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,34 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+subdirs-$(CONFIG_AMD_CIMX_SB800) += ../../../../../src/vendorcode/amd/cimx/sb800
+
+# SB800 Platform Files
+
+romstage-y += cfg.c
+romstage-y += early.c
+romstage-y += smbus.c
+
+ramstage-y += cfg.c
+ramstage-y += late.c
+
+driver-y   += smbus.c
+driver-y   += lpc.c
+
+

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,155 @@
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+ 
+#ifndef  _AMD_SBPLATFORM_H_
+#define  _AMD_SBPLATFORM_H_
+
+//#include "cbtypes.h"
+#ifdef NULL
+  #undef NULL
+#endif
+#define NULL            0
+
+typedef unsigned long long PLACEHOLDER;
+
+#ifndef SBOEM_ACPI_RESTORE_SWSMI
+  #define SBOEM_BEFORE_PCI_RESTORE_SWSMI    0xD3
+  #define SBOEM_AFTER_PCI_RESTORE_SWSMI     0xD4
+#endif
+
+#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
+
+/*
+/// Extended PCI Address
+typedef struct _EXT_PCI_ADDR {
+  UINT32                  Reg :16; ///< / PCI Register
+  UINT32                  Func:3;  ///< / PCI Function
+  UINT32                  Dev :5;  ///< / PCI Device
+  UINT32                  Bus :8;  ///< / PCI Address
+} EXT_PCI_ADDR;
+
+/// PCI Address
+typedef union _PCI_ADDR {
+  UINT32                  ADDR; ///< / 32 bit Address
+  EXT_PCI_ADDR            Addr; ///< / Extended PCI Address
+} PCI_ADDR;
+*/
+#endif
+#define FIXUP_PTR(ptr)  ptr
+
+#include "AmdSbLib.h"
+#include "Amd.h"
+#include "SB800.h"
+#include "SBTYPE.h"
+#include "ACPILIB.h"
+#include "SBDEF.h"
+#include "AMDSBLIB.h"
+#include "SBSUBFUN.h"
+#include "OEM.h"
+#include "AMD.h"
+
+
+//------------------------------------------------------------------------------------------------------------------------//
+/**
+ * SB_CIMx_PARAMETER                0                1                   2            Defult Value When CIMx Take over
+ *  SpreadSpectrum         CIMx take over   User (Setup Option) User (Setup Option)               Enable
+ * SpreadSpectrumType      CIMx take over   User (Setup Option) User (Setup Option)               Normal
+ *     HpetTimer           CIMx take over   User (Setup Option) User (Setup Option)               Enable
+ *     HpetMsiDis          CIMx take over   User (Setup Option) User (Setup Option)               Enable (0x00)
+ *      IrConfig           CIMx take over   User (Setup Option) User (Setup Option)               Disable (0x00)
+ * SpiFastReadEnable       CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ * SpiFastReadSpeed        CIMx take over   User (Setup Option) User (Setup Option)               Disable (NULL)
+ *     NbSbGen2            CIMx take over   User (Setup Option) User (Setup Option)               Enable
+ * AlinkPhyPllPowerDown    CIMx take over   User (Setup Option) User (Setup Option)               Enable
+ * ResetCpuOnSyncFlood     CIMx take over   User (Setup Option) User (Setup Option)               Enable
+ *     GppGen2             CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *  GppMemWrImprove        CIMx take over   User (Setup Option) User (Setup Option)               Enable
+ *    GppPortAspm          CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *  GppLaneReversal        CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *  GppPhyPllPowerDown     CIMx take over   User (Setup Option) User (Setup Option)               Enable
+ *  UsbPhyPowerDown        CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *  SBGecDebugBus          CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *     SBGecPwr            CIMx take over   User (Setup Option) User (Setup Option)               Nerver Power down (0x11)
+ *   SataSetMaxGen2        CIMx take over   User (Setup Option) User (Setup Option)               Max Gen3 (0x00)
+ *   SataClkMode           CIMx take over   User (Setup Option) User (Setup Option)               0x90   int. 100Mhz
+ *  SataAggrLinkPmCap      CIMx take over   User (Setup Option) User (Setup Option)               Enable
+ *  SataPortMultCap        CIMx take over   User (Setup Option) User (Setup Option)               Enable
+ *   SataPscCap            CIMx take over   User (Setup Option) User (Setup Option)               Enable (0x00)
+ *   SataSscCap            CIMx take over   User (Setup Option) User (Setup Option)               Enable (0x00)
+ * SataFisBasedSwitching   CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *   SataCccSupport        CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *   SataMsiCapability     CIMx take over   User (Setup Option) User (Setup Option)               Enable
+ *   SataClkAutoOff        CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *    AcDcMsg              CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *   TimerTickTrack        CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *  ClockInterruptTag      CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *  OhciTrafficHanding     CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *  EhciTrafficHanding     CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *  FusionMsgCMultiCore    CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ *   FusionMsgCStage       CIMx take over   User (Setup Option) User (Setup Option)               Disable
+ */
+#define SB_CIMx_PARAMETER  0x02
+
+// Generic 
+#define cimSpreadSpectrumDefault        TRUE
+#define cimSpreadSpectrumTypeDefault	0x00      // Normal
+#define cimHpetTimerDefault             TRUE
+#define cimHpetMsiDisDefault            FALSE     // Enable
+#define cimIrConfigDefault              0x00      // Disable
+#define cimSpiFastReadEnableDefault     0x00      // Disable
+#define cimSpiFastReadSpeedDefault      0x00      // NULL
+// GPP/AB Controller 
+#define cimNbSbGen2Default              TRUE
+#define cimAlinkPhyPllPowerDownDefault  TRUE
+#define cimResetCpuOnSyncFloodDefault   TRUE
+#define cimGppGen2Default               FALSE
+#define cimGppMemWrImproveDefault       TRUE
+#define cimGppPortAspmDefault           FALSE
+#define cimGppLaneReversalDefault       FALSE
+#define cimGppPhyPllPowerDownDefault    TRUE 
+// USB Controller
+#define cimUsbPhyPowerDownDefault       FALSE
+// GEC Controller
+#define cimSBGecDebugBusDefault         FALSE
+#define cimSBGecPwrDefault              0x03
+// Sata Controller 
+#define cimSataSetMaxGen2Default        0x00
+#define cimSATARefClkSelDefault         0x10
+#define cimSATARefDivSelDefault         0x80
+#define cimSataAggrLinkPmCapDefault     TRUE
+#define cimSataPortMultCapDefault       TRUE
+#define cimSataPscCapDefault            0x00      // Enable
+#define cimSataSscCapDefault            0x00      // Enable
+#define cimSataFisBasedSwitchingDefault FALSE 
+#define cimSataCccSupportDefault        FALSE
+#define cimSataClkAutoOffDefault        FALSE
+#define cimNativepciesupportDefault     FALSE
+// Fusion Related 
+#define cimAcDcMsgDefault               FALSE
+#define cimTimerTickTrackDefault        FALSE
+#define cimClockInterruptTagDefault     FALSE
+#define cimOhciTrafficHandingDefault    FALSE
+#define cimEhciTrafficHandingDefault    FALSE
+#define cimFusionMsgCMultiCoreDefault   FALSE
+#define cimFusionMsgCStageDefault       FALSE
+#endif // _AMD_SBPLATFORM_H_

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _CIMX_SB_EARLY_H_
+#define _CIMX_SB_EARLY_H_
+
+/**
+ * @brief Get SouthBridge device number, called by finalize_node_setup()
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus);
+
+/**
+ * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper.
+ */
+void sb_poweron_init(void);
+//void sb_before_pci_init(void);
+
+#endif

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+
+#if CONFIG_SERIAL_POST == 1
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+#ifndef CONFIG_TTYS0_DIV
+#if ((115200%CONFIG_TTYS0_BAUD) != 0)
+#error Bad ttys0 baud rate
+#endif
+#define CONFIG_TTYS0_DIV	(115200/CONFIG_TTYS0_BAUD)
+#endif // CONFIG_TTYS0_DIV
+
+#define UART_LCS	CONFIG_TTYS0_LCS
+
+#endif // CONFIG_SERIAL_POST == 1
+
+
+static void sb800_enable_rom(void)
+{
+  u32 word;
+  u32 dword;
+  device_t dev;
+
+  dev = PCI_DEV(0, 0x14, 0x03);
+  /* SB800 LPC Bridge 0:20:3:44h.
+   * BIT6: Port Enable for serial port 0x3f8-0x3ff
+   * BIT29: Port Enable for KBC port 0x60 and 0x64
+   * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
+   */
+  dword = pci_io_read_config32(dev, 0x44);
+  //dword |= (1<<6) | (1<<29) | (1<<30) ;
+  /*Turn on all of LPC IO Port decode enable */
+  dword = 0xffffffff;
+  pci_io_write_config32(dev, 0x44, dword);
+
+  /* SB800 LPC Bridge 0:20:3:48h.
+   * BIT0: Port Enable for SuperIO 0x2E-0x2F 
+   * BIT1: Port Enable for SuperIO 0x4E-0x4F 
+   * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
+   * BIT6: Port Enable for RTC IO 0x70-0x73
+   * BIT21: Port Enable for Port 0x80
+   */
+  dword = pci_io_read_config32(dev, 0x48);
+  dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
+  pci_io_write_config32(dev, 0x48, dword);
+
+  /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+  /* Set the 4MB enable bits */
+  word = pci_io_read_config16(dev, 0x6c);
+  word = 0xFFC0; 
+  pci_io_write_config16(dev, 0x6c, word);
+}
+
+static void bootblock_southbridge_init(void)
+{
+  /* Setup the rom access for 2M */
+  sb800_enable_rom();
+}

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/cbtypes.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cbtypes.h	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _CBTYPES_H_
+#define _CBTYPES_H_
+
+//#include <stdint.h>
+
+typedef signed long long __int64;
+typedef void VOID;
+typedef unsigned int UINTN;
+typedef signed char CHAR8;
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned long long UINT64;
+
+#ifndef TRUE
+#define TRUE  1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+typedef unsigned char BOOLEAN;
+
+#ifndef VOLATILE
+#define VOLATILE volatile
+#endif
+
+#ifndef IN
+#define IN
+#endif
+#ifndef OUT
+#define OUT
+#endif
+
+#endif

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include "SBPLATFORM.h"
+#include "cfg.h"
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void sb800_cimx_config(AMDSBCFG *sb_config)
+{
+	if (!sb_config) {
+		return;
+	}
+	//memset(sb_config, 0, sizeof(AMDSBCFG));
+
+	/* header */
+	sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;
+
+	/* static Build Parameters */
+	sb_config->BuildParameters.BiosSize = BIOS_SIZE;
+	sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
+	sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
+	sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
+	sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
+	sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
+	sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
+	sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS;
+	sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
+	sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
+	sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
+	sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
+	sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
+	sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
+	sb_config->BuildParameters.OhciSsid = OHCI_SSID;
+	sb_config->BuildParameters.EhciSsid = EHCI_SSID;
+	sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
+	sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
+	sb_config->BuildParameters.IdeSsid = IDE_SSID;
+	sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
+	sb_config->BuildParameters.LpcSsid = LPC_SSID;
+	sb_config->BuildParameters.PCIBSsid = PCIB_SSID;
+	sb_config->BuildParameters.SpreadSpectrumType = Spread_Spectrum_Type;
+	sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
+
+	/* General */
+	sb_config->SpreadSpectrum = SPREAD_SPECTRUM;
+	sb_config->PciClks = PCI_CLOCK_CTRL;
+	sb_config->HpetTimer = HPET_TIMER;
+
+	/* USB */
+	sb_config->USBMODE.UsbModeReg = USB_CINFIG;
+  	sb_config->SbUsbPll = 0;
+
+	/* SATA */
+	sb_config->SataClass = SATA_MODE;
+	sb_config->SataIdeMode = SATA_IDE_MODE;
+	sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED;
+  	sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
+	sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
+								//TODO: set to secondary not take effect.
+	sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
+	sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
+
+  	/* Azalia HDA */
+	sb_config->AzaliaController = AZALIA_CONTROLLER;
+	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
+	sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN;
+	sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
+
+	/*
+	 * GPP. default configure only enable port0 with 4 lanes,
+	 * configure in devicetree.cb would overwrite the default configuration
+	 */
+	sb_config->GppFunctionEnable = GPP_CONTROLLER;
+	sb_config->GppLinkConfig = GPP_CFGMODE;
+	//sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
+	sb_config->PORTCONFIG[0].PortCfg.PortPresent = ENABLED;
+	sb_config->PORTCONFIG[1].PortCfg.PortPresent = ENABLED;
+	sb_config->PORTCONFIG[2].PortCfg.PortPresent = ENABLED;
+	sb_config->PORTCONFIG[3].PortCfg.PortPresent = ENABLED;
+	sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
+	//sb_config->NbSbGen2 = TRUE;
+	//sb_config->GppGen2 = TRUE;
+
+	//cimx BTS fix
+	sb_config->GppMemWrImprove = TRUE;
+	sb_config->SbPcieOrderRule = TRUE;
+	sb_config->AlinkPhyPllPowerDown = TRUE;
+	sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving
+	sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06, PLATFORM.H default define 0x11 was wrong
+	sb_config->GecConfig = 0; //ENABLE GEC controller
+
+#ifndef __PRE_RAM__
+	/* ramstage cimx config here */
+	if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
+		sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
+	}
+
+	//sb_config->
+#endif //!__PRE_RAM__
+}
+

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,240 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _SB800_CFG_H_
+#define _SB800_CFG_H_
+
+#include <stdint.h>
+
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M			0
+#define BIOS_SIZE_2M			1
+#define BIOS_SIZE_4M			3
+#define BIOS_SIZE_8M			7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#ifndef BIOS_SIZE
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+  #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+  #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+  #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+  #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ *  0 - Disable Spread Spectrum function
+ *  1 - Enable  Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM			0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ *  0 - Disable hpet
+ *  1 - Enable  hpet
+ */
+#define HPET_TIMER			1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ *   0 - Disable
+ *   1 - Enable
+ *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CINFIG		0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ *   0 - disable
+ *   1 - enable
+ *  PCI SLOT 0 define at BIT0
+ *  PCI SLOT 1 define at BIT1
+ *  PCI SLOT 2 define at BIT2
+ *  PCI SLOT 3 define at BIT3
+ *  PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL			0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#ifndef SATA_CONTROLLER
+  #define SATA_CONTROLLER		ENABLED
+#endif
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#ifndef SATA_MODE
+  #define SATA_MODE			NATIVE_IDE_MODE
+#endif
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE			0
+#define IDE_NATIVE_MODE			1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#ifndef SATA_IDE_MODE
+  #define SATA_IDE_MODE			IDE_LEGACY_MODE
+#endif
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ *  PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK		0x00
+#define INTERNAL_CLOCK		0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED	1
+
+
+/**
+ * @def   AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def   AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def   AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO			0
+#define AZALIA_DISABLE			1
+#define AZALIA_ENABLE			2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#ifndef AZALIA_CONTROLLER
+  #define AZALIA_CONTROLLER		AZALIA_AUTO
+#endif
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ *  0 - disable
+ *  1 - enable
+ */
+#ifndef AZALIA_PIN_CONFIG
+  #define AZALIA_PIN_CONFIG		1
+#endif
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ *  SDIN0 is define at BIT0 & BIT1
+ *   00 - GPIO PIN
+ *   01 - Reserved
+ *   10 - As a Azalia SDIN pin
+ *  SDIN1 is define at BIT2 & BIT3
+ *  SDIN2 is define at BIT4 & BIT5
+ *  SDIN3 is define at BIT6 & BIT7
+ */
+#ifndef AZALIA_SDIN_PIN
+  //#define AZALIA_SDIN_PIN		0xAA
+  #define AZALIA_SDIN_PIN		0x2A
+#endif
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#ifndef GPP_CONTROLLER
+  #define GPP_CONTROLLER		ENABLED
+#endif
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ *  GPP_CFGMODE_X4000
+ *  GPP_CFGMODE_X2200
+ *  GPP_CFGMODE_X2110
+ *  GPP_CFGMODE_X1111
+ */
+#ifndef GPP_CFGMODE
+  #define GPP_CFGMODE			GPP_CFGMODE_X1111
+#endif
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ */
+void sb800_cimx_config(AMDSBCFG *sb_cfg);
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func    Southbridge CIMx Function ID.
+ * @param[in] data    Southbridge Input Data.
+ * @param[in] sb_cfg  Southbridge configuration structure pointer.
+ *
+ */
+u32 sb800_callout_entry(u32 func, u32 data, void* sb_cfg);
+
+#endif

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/chip.h	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _CIMX_WRAPPER_SB800_CHIP_H_
+#define _CIMX_WRAPPER_SB800_CHIP_H_
+
+extern struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops;
+
+/*
+ * configuration set in mainboard/devicetree.cb
+ *  boot_switch_sata_ide:
+ *   0 -set SATA as primary, PATA(IDE) as secondary.
+ *   1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
+ *  gpp_configuration - The configuration of General Purpose Port A/B/C/D
+ *   0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
+ *   2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
+ *   3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
+ *   4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
+ */
+struct southbridge_amd_cimx_wrapper_sb800_config
+{
+	u32 boot_switch_sata_ide : 1;
+	u8  gpp_configuration;
+};
+
+#endif /* _CIMX_WRAPPER_SB800_CHIP_H_ */

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {
+	CHIP_NAME("AMD South Bridge  SB800")
+};

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/early.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/early.c	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+//#include <config.h>
+#include <stdint.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>		/* inl, outl */
+#include <arch/romcc_io.h>	/* device_t */
+#include "SBPLATFORM.h"
+#include "SbEarly.h"
+#include "cfg.h"		/*sb800_cimx_config*/
+
+
+/**
+ * @brief Get SouthBridge device number
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus)
+{
+	device_t dev;
+
+	//dev = PCI_DEV(bus, 0x14, 0);
+	dev = pci_locate_device_on_bus(
+			PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM),
+			bus);
+
+	return (dev >> 15) & 0x1f;
+}
+
+
+/**
+ * @brief South Bridge CIMx romstage entry,
+ *        wrapper of sbPowerOnInit entry point.
+ */
+void sb_poweron_init(void)
+{
+	AMDSBCFG sb_early_cfg;
+
+	sb800_cimx_config(&sb_early_cfg);
+	//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
+	//AmdSbDispatcher(&sb_early_cfg);
+	//TODO
+	//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
+	// VerifyImage() will fail, LocateImage() take minitues to find the image.
+	sbPowerOnInit(&sb_early_cfg);
+}

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,436 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <device/device.h>	/* device_t */
+#include <device/pci.h>		/* device_operations */
+#include <device/pci_ids.h>
+#include <device/smbus.h>	/* smbus_bus_operations */
+#include <console/console.h>	/* printk */
+#include "lpc.h"		/* lpc_read_resources */
+#include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
+#include "cfg.h"		/* sb800 Cimx configuration */
+#include "chip.h" 		/* struct southbridge_amd_cimx_wrapper_sb800_config */
+
+
+/*implement in mainboard.c*/
+//void set_pcie_assert(void);
+//void set_pcie_deassert(void);
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+
+#ifndef _RAMSTAGE_
+#define _RAMSTAGE_
+#endif
+static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
+static AMDSBCFG *sb_config = &sb_late_cfg;
+
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func      Southbridge CIMx Function ID.
+ * @param[in] data      Southbridge Input Data.
+ * @param[in] sb_config Southbridge configuration structure pointer.
+ *
+ */
+u32 sb800_callout_entry(u32 func, u32 data, void* config)
+{
+	u32 ret = 0;
+
+	switch (func) {
+	case CB_SBGPP_RESET_ASSERT:
+		//set_pcie_assert();
+		set_pcie_reset();
+		break;
+
+	case CB_SBGPP_RESET_DEASSERT:
+		//set_pcie_deassert();
+		set_pcie_dereset();
+		break;
+
+	case IMC_FIRMWARE_FAIL:
+		break;
+
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static void lpc_enable_resources(device_t dev)
+{
+
+	pci_dev_enable_resources(dev);
+	//lpc_enable_childrens_resources(dev);
+}
+
+static void lpc_init(device_t dev)
+{
+	/* SB Configure HPET base and enable bit */
+	hpetInit(sb_config, &(sb_config->BuildParameters));
+}
+
+static struct device_operations lpc_ops = {
+        .read_resources = lpc_read_resources,
+        .set_resources = lpc_set_resources,
+        .enable_resources = lpc_enable_resources,
+        .init = lpc_init,
+        .scan_bus = scan_static_bus,
+        .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+        .ops = &lpc_ops,
+        .vendor = PCI_VENDOR_ID_ATI,
+        .device = PCI_DEVICE_ID_ATI_SB800_LPC,
+};
+
+
+static void sata_enable_resources(struct device *dev)
+{
+	sataInitAfterPciEnum(sb_config);
+	pci_dev_enable_resources(dev);
+}
+
+static void sata_init(struct device *dev)
+{
+	sb_config->StdHeader.Func = SB_MID_POST_INIT;
+	AmdSbDispatcher(sb_config); //sataInitMidPost only
+	commonInitLateBoot(sb_config);
+	sataInitLatePost(sb_config);
+}
+
+static struct device_operations sata_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = sata_enable_resources, //pci_dev_enable_resources,
+	.init = sata_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver sata_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode 4390
+};
+
+
+#if CONFIG_USBDEBUG
+static void usb_set_resources(struct device *dev)
+{
+	struct resource *res;
+	u32 base;
+	u32 old_debug;
+
+	old_debug = get_ehci_debug();
+	set_ehci_debug(0);
+
+	pci_dev_set_resources(dev);
+
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(old_debug);
+	if (!res)
+		return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+}
+#endif
+
+static void usb_init(struct device *dev)
+{
+	usbInitAfterPciInit(sb_config);
+	commonInitLateBoot(sb_config);
+}
+
+static struct device_operations usb_ops = {
+	.read_resources = pci_dev_read_resources,
+#if CONFIG_USBDEBUG
+	.set_resources = usb_set_resources,
+#else
+	.set_resources = pci_dev_set_resources,
+#endif
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+/*
+ * The pci id of usb ctrl 0 and 1 are the same.
+ */
+static const struct pci_driver usb_ohci123_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
+};
+
+static const struct pci_driver usb_ehci123_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
+};
+
+static const struct pci_driver usb_ohci4_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
+};
+
+
+static void azalia_init(struct device *dev)
+{
+	azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
+}
+
+static struct device_operations azalia_ops = {
+        .read_resources = pci_dev_read_resources,
+        .set_resources = pci_dev_set_resources,
+        .enable_resources = pci_dev_enable_resources,
+        .init = azalia_init,
+        .scan_bus = 0,
+        .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver azalia_driver __pci_driver = {
+        .ops = &azalia_ops,
+        .vendor = PCI_VENDOR_ID_ATI,
+        .device = PCI_DEVICE_ID_ATI_SB800_HDA,
+};
+
+
+static void gec_init(struct device *dev)
+{
+	gecInitAfterPciEnum(sb_config);
+	gecInitLatePost(sb_config);
+	printk(BIOS_DEBUG, "gec hda enabled\n");
+}
+
+static struct device_operations gec_ops = {
+        .read_resources = pci_dev_read_resources,
+        .set_resources = pci_dev_set_resources,
+        .enable_resources = pci_dev_enable_resources,
+        .init = gec_init,
+        .scan_bus = 0,
+        .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver gec_driver __pci_driver = {
+        .ops = &gec_ops,
+        .vendor = PCI_VENDOR_ID_ATI,
+        .device = PCI_DEVICE_ID_ATI_SB800_GEC,
+};
+
+
+static void pcie_init(device_t dev)
+{
+	sbPcieGppLateInit(sb_config);
+}
+
+static struct device_operations pci_ops = {
+        .read_resources = pci_bus_read_resources,
+        .set_resources = pci_dev_set_resources,
+        .enable_resources = pci_bus_enable_resources,
+        .init = pcie_init,
+        .scan_bus = pci_scan_bridge,
+        .reset_bus = pci_bus_reset,
+        .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+        .ops = &pci_ops,
+        .vendor = PCI_VENDOR_ID_ATI,
+        .device = PCI_DEVICE_ID_ATI_SB800_PCI,
+};
+
+
+struct device_operations bridge_ops = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pcie_init,
+	.scan_bus         = pci_scan_bridge,
+	.enable           = 0,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = &lops_pci,
+};
+
+/* 0:15:0 PCIe PortA */
+static const struct pci_driver PORTA_driver __pci_driver = {
+        .ops = &bridge_ops,
+        .vendor = PCI_VENDOR_ID_ATI,
+        .device = PCI_DEVICE_ID_ATI_SB800_PCIEA,
+};
+
+/* 0:15:1 PCIe PortB */
+static const struct pci_driver PORTB_driver __pci_driver = {
+        .ops = &bridge_ops,
+        .vendor = PCI_VENDOR_ID_ATI,
+        .device = PCI_DEVICE_ID_ATI_SB800_PCIEB,
+};
+
+/* 0:15:2 PCIe PortC */
+static const struct pci_driver PORTC_driver __pci_driver = {
+        .ops = &bridge_ops,
+        .vendor = PCI_VENDOR_ID_ATI,
+        .device = PCI_DEVICE_ID_ATI_SB800_PCIEC,
+};
+
+/* 0:15:3 PCIe PortD */
+static const struct pci_driver PORTD_driver __pci_driver = {
+        .ops = &bridge_ops,
+        .vendor = PCI_VENDOR_ID_ATI,
+        .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
+};
+
+
+/**
+ * @brief SB Cimx entry point sbBeforePciInit wrapper
+ */
+static void sb800_enable(device_t dev)
+{
+	u8 gpp_port = 0;
+	struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
+		(struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
+
+	sb800_cimx_config(sb_config);
+	printk(BIOS_DEBUG, "sb800_enable() ");
+
+	/* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
+	commonInitEarlyBoot(sb_config);
+	commonInitEarlyPost(sb_config);
+
+	switch (dev->path.pci.devfn) {
+	case (0x11 << 3) | 0: /* 0:11.0  SATA */
+		if (dev->enabled) {
+  			sb_config->SATAMODE.SataMode.SataController = ENABLED;
+			if (1 == sb_chip->boot_switch_sata_ide)
+				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
+			else if (0 == sb_chip->boot_switch_sata_ide)
+				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
+		} else {
+  			sb_config->SATAMODE.SataMode.SataController = DISABLED;
+		}
+
+		sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
+		break;
+
+	case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
+	case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
+	case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
+	case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
+	case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
+	case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
+	case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
+		usbInitBeforePciEnum(sb_config);  // USB POST TIME Only
+		break;
+
+	case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
+		break;
+
+	case (0x14 << 3) | 1: /* 0:14:1 IDE */
+		if (dev->enabled) {
+			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
+		} else {
+  			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
+		}
+		sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
+		break;
+
+	case (0x14 << 3) | 2: /* 0:14:2 HDA */
+		if (dev->enabled) {
+  			if (AZALIA_DISABLE == sb_config->AzaliaController) {
+  				sb_config->AzaliaController = AZALIA_AUTO;
+			}
+			printk(BIOS_DEBUG, "hda enabled\n");
+		} else {
+  			sb_config->AzaliaController = AZALIA_DISABLE;
+			printk(BIOS_DEBUG, "hda disabled\n");
+		}
+  		azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
+		break;
+
+
+	case (0x14 << 3) | 3: /* 0:14:3 LPC */
+		break;
+
+	case (0x14 << 3) | 4: /* 0:14:4 PCI */
+		break;
+
+	case (0x14 << 3) | 6: /* 0:14:6 GEC */
+		if (dev->enabled) {
+			sb_config->GecConfig = 0;
+			printk(BIOS_DEBUG, "gec enabled\n");
+		} else {
+			sb_config->GecConfig = 1;
+			printk(BIOS_DEBUG, "gec disabled\n");
+		}
+  		gecInitBeforePciEnum(sb_config); // Init GEC
+		break;
+
+	case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
+	case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
+	case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
+	case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
+		gpp_port = (dev->path.pci.devfn) & 0x03;
+		if (dev->enabled) {
+			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
+		} else {
+			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
+		}
+
+		/*
+		 * GPP_CFGMODE_X4000: PortA Lanes[3:0]
+		 * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
+		 * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
+		 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
+		 */
+		if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
+			sb_config->GppLinkConfig = sb_chip->gpp_configuration;
+		}
+
+		sbPcieGppEarlyInit(sb_config);
+		break;
+
+	default:
+		break;
+	}
+
+	/* Special setting ABCFG registers before PCI emulation. */
+	abSpecialSetBeforePciEnum(sb_config);
+  	usbDesertPll(sb_config);
+	//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
+	//AmdSbDispatcher(sb_config);
+}
+
+struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {
+	CHIP_NAME("ATI SB800")
+	.enable_dev = sb800_enable,
+};

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.c	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,173 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/pci.h>
+#include "lpc.h"
+
+
+void lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
+
+	pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	compact_resources(dev);
+}
+
+void lpc_set_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_dev_set_resources(dev);
+
+	/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
+	res = find_resource(dev, SPIROM_BASE_ADDRESS);
+	pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
+
+}
+
+/**
+ * @brief Enable resources for children devices
+ *
+ * @param dev the device whos children's resources are to be enabled
+ *
+ */
+void lpc_enable_childrens_resources(device_t dev)
+{
+	struct bus *link;
+	u32 reg, reg_x;
+	int var_num = 0;
+	u16 reg_var[3];
+
+	reg = pci_read_config32(dev, 0x44);
+	reg_x = pci_read_config32(dev, 0x48);
+
+	for (link = dev->link_list; link; link = link->next) {
+		device_t child;
+		for (child = link->children; child;
+		     child = child->sibling) {
+			if (child->enabled
+			    && (child->path.type == DEVICE_PATH_PNP)) {
+				struct resource *res;
+				for (res = child->resource_list; res; res = res->next) {
+					u32 base, end;	/*  don't need long long */
+					if (!(res->flags & IORESOURCE_IO))
+						continue;
+					base = res->base;
+					end = resource_end(res);
+/*
+					printk(BIOS_DEBUG, "sb800 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+					     dev_path(child), base, end);
+*/
+					switch (base) {
+					case 0x60:	/*  KB */
+					case 0x64:	/*  MS */
+						reg |= (1 << 29);
+						break;
+					case 0x3f8:	/*  COM1 */
+						reg |= (1 << 6);
+						break;
+					case 0x2f8:	/*  COM2 */
+						reg |= (1 << 7);
+						break;
+					case 0x378:	/*  Parallal 1 */
+						reg |= (1 << 0);
+						break;
+					case 0x3f0:	/*  FD0 */
+						reg |= (1 << 26);
+						break;
+					case 0x220:	/*  Aduio 0 */
+						reg |= (1 << 8);
+						break;
+					case 0x300:	/*  Midi 0 */
+						reg |= (1 << 18);
+						break;
+					case 0x400:
+						reg_x |= (1 << 16);
+						break;
+					case 0x480:
+						reg_x |= (1 << 17);
+						break;
+					case 0x500:
+						reg_x |= (1 << 18);
+						break;
+					case 0x580:
+						reg_x |= (1 << 19);
+						break;
+					case 0x4700:
+						reg_x |= (1 << 22);
+						break;
+					case 0xfd60:
+						reg_x |= (1 << 23);
+						break;
+					default:
+						if (var_num >= 3)
+							continue;	/* only 3 var ; compact them ? */
+						switch (var_num) {
+						case 0:
+							reg_x |= (1 << 2);
+							break;
+						case 1:
+							reg_x |= (1 << 24);
+							break;
+						case 2:
+							reg_x |= (1 << 25);
+							break;
+						}
+						reg_var[var_num++] =
+						    base & 0xffff;
+					}
+				}
+			}
+		}
+	}
+	pci_write_config32(dev, 0x44, reg);
+	pci_write_config32(dev, 0x48, reg_x);
+	/* Set WideIO for as many IOs found (fall through is on purpose) */
+	switch (var_num) {
+	case 2:
+		pci_write_config16(dev, 0x90, reg_var[2]);
+	case 1:
+		pci_write_config16(dev, 0x66, reg_var[1]);
+	case 0:
+		//pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
+		break;
+	}
+}

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.h	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SB800_LPC_H_
+#define _SB800_LPC_H_
+
+
+#define SPIROM_BASE_ADDRESS	0xA0 /* SPI ROM base address */
+
+void lpc_read_resources(device_t dev);
+void lpc_set_resources(device_t dev);
+void lpc_enable_childrens_resources(device_t dev);
+
+#endif

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.c	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,251 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include "smbus.h"
+
+static inline void smbus_delay(void)
+{
+	outb(inb(0x80), 0x80);
+}
+
+static int smbus_wait_until_ready(u32 smbus_io_base)
+{
+	u32 loops;
+
+	loops = SMBUS_TIMEOUT;
+	do {
+		u8 val;
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;
+		if (val == 0) {	/* ready now */
+			return 0;
+		}
+		outb(val, smbus_io_base + SMBHSTSTAT);
+	} while (--loops);
+
+	return -2;		/* time out */
+}
+
+static int smbus_wait_until_done(u32 smbus_io_base)
+{
+	u32 loops;
+
+	loops = SMBUS_TIMEOUT;
+	do {
+		u8 val;
+
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;	/* mask off reserved bits */
+		if (val & 0x1c) {
+			return -5;	/* error */
+		}
+		if (val == 0x02) {
+			outb(val, smbus_io_base + SMBHSTSTAT);	/* clear status */
+			return 0;
+		}
+	} while (--loops);
+
+	return -3;		/* timeout */
+}
+
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTCMD);
+
+	return byte;
+}
+
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	/* set the command... */
+	outb(val, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	return 0;
+}
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+
+	return byte;
+}
+
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+	/* output value */
+	outb(val, smbus_io_base + SMBHSTDAT0);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	return 0;
+}
+
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
+	tmp = inl(AB_DATA);
+	/* rpr 4.2
+	 * For certain revisions of the chip, the ABCFG registers,
+	 * with an address of 0x100NN (where 'N' is any hexadecimal
+	 * number), require an extra programming step.*/
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
+	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+}
+
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
+	tmp = inl(AB_DATA);
+	/* rpr 4.2
+	 * For certain revisions of the chip, the ABCFG registers,
+	 * with an address of 0x100NN (where 'N' is any hexadecimal
+	 * number), require an extra programming step.*/
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
+	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+}
+
+/* space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	/* read axindc to tmp */
+	outl(space << 29 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(0, AB_INDX);
+	outl(space << 29 | space << 3 | 0x34, AB_INDX);
+	tmp = inl(AB_DATA);
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* write tmp */
+	outl(space << 29 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(0, AB_INDX);
+	outl(space << 29 | space << 3 | 0x34, AB_INDX);
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+}
+

Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.h	Mon Feb 14 19:38:14 2011	(r6346)
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SB800_SMBUS_H_
+#define _SB800_SMBUS_H_
+
+//#include <stdint.h>
+
+#define SMBUS_IO_BASE	SMBUS0_BASE_ADDRESS
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD  0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+/*//SB00.H
+#define AX_INDXC  0
+#define AX_INDXP  2
+#define AXCFG     4
+#define ABCFG     6
+#define RC_INDXC  1
+#define RC_INDXP  3
+*/
+
+#define AB_INDX   0xCD8
+#define AB_DATA   (AB_INDX+4)
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define abcfg_reg(reg, mask, val)	\
+	alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val)	\
+	alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val)	\
+	alink_ax_indx((AX_INDXC), (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val)		\
+	alink_ax_indx((AX_INDXP), (reg), (mask), (val))
+#define rcindxc_reg(reg, port, mask, val)	\
+	alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
+#define rcindxp_reg(reg, port, mask, val)	\
+	alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
+
+#endif



From marcj303 at gmail.com  Mon Feb 14 19:38:32 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 11:38:32 -0700
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 3 of 8.
In-Reply-To: <20110214180753.GD29618@coreboot.org>
References: <276EC11373289744A112A8FE66755067019CFD642C@SAUSEXMBP01.amd.com>
	<20110214180753.GD29618@coreboot.org>
Message-ID: <AANLkTi=j5WnoKzeQzqd94jtR8JmEnYH5u3hobE6EdvOb@mail.gmail.com>

On Mon, Feb 14, 2011 at 11:07 AM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:49]:
>> Add AMD CIMx SB800 wrapper code. ?Patch 3 of 8.
>>
>> This code provides southbridge initialization for SB800 south bridges. ?It is
>> dependent on the AMD CIMx/SB800 code.
>>
>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Acked-by: Marc Jones <marcj303 at gmail.com>

Thanks Frank!
r6346

-- 
http://se-eng.com



From svn at coreboot.org  Mon Feb 14 19:42:12 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Feb 2011 19:42:12 +0100
Subject: [coreboot] [commit] r6347 - in trunk/src/cpu/amd: . agesa_wrapper
	agesa_wrapper/family14
Message-ID: <E1Pp3NE-0007DH-US@ra.coresystems.de>

Author: mjones
Date: Mon Feb 14 19:42:12 2011
New Revision: 6347
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6347

Log:
Add AMD cpu wrapper code. Patch 4 of 8.

This code provides cpu early initialization for Family 14h cpus. It is dependent on the AMD Agesa code.

Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Added:
   trunk/src/cpu/amd/agesa_wrapper/
   trunk/src/cpu/amd/agesa_wrapper/Kconfig
   trunk/src/cpu/amd/agesa_wrapper/Makefile.inc
   trunk/src/cpu/amd/agesa_wrapper/family14/
   trunk/src/cpu/amd/agesa_wrapper/family14/Kconfig
   trunk/src/cpu/amd/agesa_wrapper/family14/Makefile.inc
   trunk/src/cpu/amd/agesa_wrapper/family14/apic_timer.c
   trunk/src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc
   trunk/src/cpu/amd/agesa_wrapper/family14/chip.h
   trunk/src/cpu/amd/agesa_wrapper/family14/chip_name.c
   trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c
Modified:
   trunk/src/cpu/amd/Kconfig
   trunk/src/cpu/amd/Makefile.inc

Modified: trunk/src/cpu/amd/Kconfig
==============================================================================
--- trunk/src/cpu/amd/Kconfig	Mon Feb 14 19:38:14 2011	(r6346)
+++ trunk/src/cpu/amd/Kconfig	Mon Feb 14 19:42:12 2011	(r6347)
@@ -20,3 +20,5 @@
 source src/cpu/amd/model_lx/Kconfig
 
 source src/cpu/amd/sc520/Kconfig
+
+source src/cpu/amd/agesa_wrapper/Kconfig

Modified: trunk/src/cpu/amd/Makefile.inc
==============================================================================
--- trunk/src/cpu/amd/Makefile.inc	Mon Feb 14 19:38:14 2011	(r6346)
+++ trunk/src/cpu/amd/Makefile.inc	Mon Feb 14 19:42:12 2011	(r6347)
@@ -12,3 +12,6 @@
 subdirs-$(CONFIG_CPU_AMD_LX) += model_lx
 subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
+
+subdirs-$(CONFIG_AMD_AGESA) += agesa_wrapper
+subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa

Added: trunk/src/cpu/amd/agesa_wrapper/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/cpu/amd/agesa_wrapper/Kconfig	Mon Feb 14 19:42:12 2011	(r6347)
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+source src/cpu/amd/agesa_wrapper/family14/Kconfig

Added: trunk/src/cpu/amd/agesa_wrapper/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/cpu/amd/agesa_wrapper/Makefile.inc	Mon Feb 14 19:42:12 2011	(r6347)
@@ -0,0 +1,19 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+subdirs-$(CONFIG_CPU_AMD_AGESA_WRAPPER_FAMILY14) += family14

Added: trunk/src/cpu/amd/agesa_wrapper/family14/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/Kconfig	Mon Feb 14 19:42:12 2011	(r6347)
@@ -0,0 +1,74 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+config CPU_AMD_AGESA_WRAPPER_FAMILY14
+	bool
+	select PCI_IO_CFG_EXT
+
+config CPU_ADDR_BITS
+	int
+	default 36
+	depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+
+config CPU_SOCKET_TYPE
+	hex
+	default 0x10
+	depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+
+# DDR2 and REG
+config DIMM_SUPPORT
+	hex
+	default 0x0104
+	depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+
+config EXT_RT_TBL_SUPPORT
+	bool
+	default n
+	depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+
+config EXT_CONF_SUPPORT
+	bool
+	default n
+	depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+
+config CBB
+	hex
+	default 0x0
+	depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+
+config CDB
+	hex
+	default 0x18
+	depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+
+config XIP_ROM_BASE
+	hex
+	default 0xfff80000
+	depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+
+config XIP_ROM_SIZE
+	hex
+	default 0x80000
+	depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+	
+config HAVE_INIT_TIMER
+	bool
+	default y
+	depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 
+		

Added: trunk/src/cpu/amd/agesa_wrapper/family14/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/Makefile.inc	Mon Feb 14 19:42:12 2011	(r6347)
@@ -0,0 +1,285 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+ 
+ramstage-y += chip_name.c
+driver-y += model_14_init.c
+
+AGESA_ROOT = ../../../../vendorcode/amd/agesa
+
+agesa_lib_src  = $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtPost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14IoCstate.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnprotoon.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B_Unenc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A_Unenc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000025_Unenc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbSmu.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtEnv.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtPost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Feature/NbLclkDpm.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Feature/NbFuseTable.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Pstate.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14C6State.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnmcton.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam14/htNbUtilitiesFam14.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnflowon.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtPost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c
+agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnidendimmon.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Utilities.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxStrapsInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEarly.c
+agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnoton.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mndcton.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxGmcInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Dmi.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnregon.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtEnvPost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c
+agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpson3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PciTables.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtLatePost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam14/htNbFam14.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxConfigData.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/ON/mmflowon.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14MsrTables.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtLatePost.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxRegisterAcc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtReset.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
+agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
+agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnon.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnphyon.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14BrandId.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbConfigData.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ON/mauon3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ON/mason3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnS3on.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieLateInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortLateInit.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieMiscLib.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbSmuLib.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEnv.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbServices.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxLib.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbPowerMgmt.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/HT/htInitReset.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c
+
+romstage-y += $(agesa_lib_src)
+ramstage-y += $(agesa_lib_src)
+
+subdirs-y += ../../mtrr
+subdirs-y += ../../../x86/tsc
+subdirs-y += ../../../x86/lapic
+subdirs-y += ../../../x86/cache
+subdirs-y += ../../../x86/mtrr
+subdirs-y += ../../../x86/pae
+subdirs-y += ../../../x86/smm
+
+ramstage-y += apic_timer.c
+cpu_incs += $(src)/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc

Added: trunk/src/cpu/amd/agesa_wrapper/family14/apic_timer.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/apic_timer.c	Mon Feb 14 19:42:12 2011	(r6347)
@@ -0,0 +1,58 @@
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+#include <stdint.h>
+#include <delay.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+
+/* NOTE: We use the APIC TIMER register is to hold flags for AP init during
+ * pre-memory init (__PRE_RAM__). Don't use init_timer() and  udelay is
+ * redirected to udelay_tsc().
+ */
+
+
+void init_timer(void)
+{
+  /* Set the apic timer to no interrupts and periodic mode */
+  lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
+
+  /* Set the divider to 1, no divider */
+  lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
+
+  /* Set the initial counter to 0xffffffff */
+  lapic_write(LAPIC_TMICT, 0xffffffff);
+}
+
+
+void udelay(u32 usecs)
+{
+  u32 start, value, ticks;
+  /* Calculate the number of ticks to run, our FSB runs a 200Mhz */
+  ticks = usecs * 200;
+  start = lapic_read(LAPIC_TMCCT);
+  do {
+    value = lapic_read(LAPIC_TMCCT);
+  } while((start - value) < ticks);
+
+}

Added: trunk/src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc	Mon Feb 14 19:42:12 2011	(r6347)
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+ 
+/******************************************************************************
+ * AMD Generic Encapsulated Software Architecture
+ *
+ * $Workfile:: cache_as_ram.inc
+ *
+ * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
+ *
+ ******************************************************************************
+ */ 
+ 
+#include "gcccar.inc"
+
+/*
+ * XMM map:
+ *   xmm0: BIST
+ *   xmm1: backup ebx -- cpu_init_detected
+ */
+
+.code32
+.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
+
+cache_as_ram_setup:
+  
+  post_code(0xa0)
+  
+  /* enable SSE2 128bit instructions */ 
+  /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
+  
+  movl %cr4, %eax
+  orl $(3<<9), %eax
+  movl %eax, %cr4 
+  
+  /* Get the cpu_init_detected */
+  mov $1, %eax
+  cpuid
+  shr $24, %ebx
+        
+  /* Save the BIST result */
+  cvtsi2sd  %ebp, %xmm0
+  
+  /* for normal part %ebx already contain cpu_init_detected from fallback call */
+  
+  /* Save the cpu_init_detected */
+  cvtsi2sd  %ebx, %xmm1
+      
+  post_code(0xa1)
+  AMD_ENABLE_STACK
+  
+  post_code(0xa1)
+  
+  /* Restore the BIST result */
+  cvtsd2si  %xmm0, %edx
+  
+  /* Restore the  cpu_init_detected */
+  cvtsd2si  %xmm1, %ebx
+  
+  pushl %ebx  /* init detected */
+  pushl %edx  /* bist */
+  call  cache_as_ram_main
+  
+  /* Should never see this postcode */ 
+  post_code(0xaf)     
+stop:
+  jmp stop
+
+disable_cache_as_ram:
+  /* Save return stack */
+  cvtsi2sd  %esp, %xmm0
+  
+  AMD_DISABLE_STACK
+  
+  /* Restore the return stack */
+  cvtsd2si  %xmm0, %esp
+ 
+  ret
+    
+cache_as_ram_setup_out:
+
+

Added: trunk/src/cpu/amd/agesa_wrapper/family14/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/chip.h	Mon Feb 14 19:42:12 2011	(r6347)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_amd_agesa_wrapper_family14_ops;
+
+struct cpu_amd_agesa_wrapper_family14_config {
+};

Added: trunk/src/cpu/amd/agesa_wrapper/family14/chip_name.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/chip_name.c	Mon Feb 14 19:42:12 2011	(r6347)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_amd_agesa_wrapper_family14_ops = {
+	CHIP_NAME("AMD CPU Family 14h")
+};

Added: trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c	Mon Feb 14 19:42:12 2011	(r6347)
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/pae.h>
+#include <pc80/mc146818rtc.h>
+#include <cpu/x86/lapic.h>
+
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/multicore.h>
+#include <cpu/amd/amdfam14.h>
+
+#define MCI_STATUS 0x401
+
+msr_t rdmsr_amd(u32 index)
+{
+  msr_t result;
+  __asm__ __volatile__(
+    "rdmsr"
+    :"=a"(result.lo), "=d"(result.hi)
+    :"c"(index), "D"(0x9c5a203a)
+  );
+  return result;
+}
+
+void wrmsr_amd(u32 index, msr_t msr)
+{
+  __asm__ __volatile__(
+    "wrmsr"
+    : /* No outputs */
+    :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
+  );
+}
+
+static void model_14_init(device_t dev)
+{
+  printk(BIOS_DEBUG, "Model 14 Init - a no-op.\n");
+
+  u8 i;
+  msr_t msr;
+  struct node_core_id id;
+#if CONFIG_LOGICAL_CPUS == 1
+  u32 siblings;
+#endif
+
+//  id = get_node_core_id(read_nb_cfg_54());  /* nb_cfg_54 can not be set */
+//  printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
+
+  /* Turn on caching if we haven't already */
+  x86_enable_cache();
+  amd_setup_mtrrs();
+  x86_mtrr_check();
+
+  disable_cache();
+
+  /* zero the machine check error status registers */
+  msr.lo = 0;
+  msr.hi = 0;
+  for (i = 0; i < 5; i++) {
+    wrmsr(MCI_STATUS + (i * 4), msr);
+  }
+
+  enable_cache();
+
+  /* Enable the local cpu apics */
+  setup_lapic();
+
+  /* Set the processor name string */
+//  init_processor_name();
+
+
+#if CONFIG_LOGICAL_CPUS == 1
+  siblings = cpuid_ecx(0x80000008) & 0xff;
+
+  if (siblings > 0) {
+    msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+    msr.lo |= 1 << 28;
+    wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+
+    msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+    msr.hi |= 1 << (33 - 32);
+    wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+  }
+  printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
+#endif
+
+  /* DisableCf8ExtCfg */
+  msr = rdmsr(NB_CFG_MSR);
+  msr.hi &= ~(1 << (46 - 32));
+  wrmsr(NB_CFG_MSR, msr);
+
+
+  /* Write protect SMM space with SMMLOCK. */
+  msr = rdmsr(HWCR_MSR);
+  msr.lo |= (1 << 0);
+  wrmsr(HWCR_MSR, msr);
+}
+
+static struct device_operations cpu_dev_ops = {
+  .init = model_14_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+  { X86_VENDOR_AMD, 0x500f00 },   /* ON-A0 */
+  { X86_VENDOR_AMD, 0x500f01 },   /* ON-A1 */
+  { X86_VENDOR_AMD, 0x500f10 },   /* ON-B0 */
+  { 0, 0 },
+};
+
+static const struct cpu_driver model_14 __cpu_driver = {
+  .ops      = &cpu_dev_ops,
+  .id_table = cpu_table,
+};



From marcj303 at gmail.com  Mon Feb 14 19:42:31 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 11:42:31 -0700
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 4 of 8.
In-Reply-To: <20110214180811.GE29618@coreboot.org>
References: <276EC11373289744A112A8FE66755067019CFD642D@SAUSEXMBP01.amd.com>
	<20110214180811.GE29618@coreboot.org>
Message-ID: <AANLkTimtU0C6veO6bVDLP5n8acHYhOCfQ2CQFyO0cRYj@mail.gmail.com>

On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:50]:
>> Add AMD cpu wrapper code. ?Patch 4 of 8.
>>
>> This code provides cpu early initialization for Family 14h cpus. ?It is
>> dependent on the AMD Agesa code.
>>
>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>>
>
>> Add AMD cpu wrapper code. ?Patch 4 of 8.
>>
>> This code provides cpu early initialization for Family 14h cpus. ?It is
>> dependent on the AMD Agesa code.
>>
>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Acked-by: Marc Jones <marcj303 at gmail.com>

Thanks Frank!
r6347

-- 
http://se-eng.com



From svn at coreboot.org  Mon Feb 14 19:47:38 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Feb 2011 19:47:38 +0100
Subject: [coreboot] [commit] r6348 - in trunk: . src/arch/x86/init
Message-ID: <E1Pp3SU-0007ZX-1l@ra.coresystems.de>

Author: mjones
Date: Mon Feb 14 19:47:37 2011
New Revision: 6348
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6348

Log:
This code fixes a number of build issues related to the AMD Agesa code. The particular issues are global variables existing in romstage and the use of GCC intrinsics in the build. The former issue will be addressed shortly, and the latter issue requires community assistance. This code is dependent on the AMD Family 14h mainboard code.

Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/Makefile
   trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb

Modified: trunk/Makefile
==============================================================================
--- trunk/Makefile	Mon Feb 14 19:42:12 2011	(r6347)
+++ trunk/Makefile	Mon Feb 14 19:47:37 2011	(r6348)
@@ -300,13 +300,16 @@
 # abspath is a workaround for romcc
 INCLUDES += -include $(abspath $(obj)/config.h)
 
-CFLAGS = $(INCLUDES) -Os -nostdinc -pipe -g
+CFLAGS = $(INCLUDES) -Os -pipe -g
 CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
 CFLAGS += -Wstrict-aliasing -Wshadow
 ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y)
 CFLAGS += -Werror
 endif
+ifneq ($(CONFIG_AMD_AGESA),y)
+CFLAGS += -nostdinc 
+endif
 CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 
 CBFS_COMPRESS_FLAG:=l

Modified: trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb
==============================================================================
--- trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb	Mon Feb 14 19:42:12 2011	(r6347)
+++ trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb	Mon Feb 14 19:47:37 2011	(r6348)
@@ -49,5 +49,6 @@
 		*(.comment.*)
 		*(.note.*)
 	}
-	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage");
+/*	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage"); */
+	_bogus = ASSERT((SIZEOF(.bss)) == 0, "Do not use global variables in romstage"); 
 }



From marcj303 at gmail.com  Mon Feb 14 19:48:12 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 11:48:12 -0700
Subject: [coreboot] (no subject)
In-Reply-To: <20110214180822.GF29618@coreboot.org>
References: <276EC11373289744A112A8FE66755067019CFD642E@SAUSEXMBP01.amd.com>
	<20110214180822.GF29618@coreboot.org>
Message-ID: <AANLkTi=cYp89ZeqKMbXxAO4LJV4-QvHEtP_EB_OXZDPS@mail.gmail.com>

On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:52]:
>> Add support for AMD Agesa wrapper code. ?Patch 5 of 8.
>>
>> This code fixes a number of build issues related to the AMD Agesa code.
>> The particular issues are global variables existing in romstage and the
>> use of GCC intrinsics in the build. ?The former issue will be addressed
>> shortly, and the latter issue requires community assistance. ?This code
>> is dependent on the AMD Family 14h mainboard code.
>>
>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Acked-by: Marc Jones <marcj303 at gmail.com>

We are accepting this patch, but we recognize the the .data area link
stage check needs to be addressed ASAP.

r6348

-- 
http://se-eng.com



From svn at coreboot.org  Mon Feb 14 19:52:16 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Feb 2011 19:52:16 +0100
Subject: [coreboot] [commit] r6349 - in trunk/src/superio/fintek: . f81865f
Message-ID: <E1Pp3Wy-0006KX-BP@ra.coresystems.de>

Author: mjones
Date: Mon Feb 14 19:52:15 2011
New Revision: 6349
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6349

Log:
This code provides support for the superio chip on the IBASE Technology DB-FT1 (AMD code name Persimmon) platform. It is independent of the  AMD code.

Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Added:
   trunk/src/superio/fintek/f81865f/
   trunk/src/superio/fintek/f81865f/Makefile.inc
   trunk/src/superio/fintek/f81865f/chip.h
   trunk/src/superio/fintek/f81865f/f81865f.h
   trunk/src/superio/fintek/f81865f/f81865f_early_serial.c
   trunk/src/superio/fintek/f81865f/superio.c
Modified:
   trunk/src/superio/fintek/Kconfig
   trunk/src/superio/fintek/Makefile.inc

Modified: trunk/src/superio/fintek/Kconfig
==============================================================================
--- trunk/src/superio/fintek/Kconfig	Mon Feb 14 19:47:37 2011	(r6348)
+++ trunk/src/superio/fintek/Kconfig	Mon Feb 14 19:52:15 2011	(r6349)
@@ -27,3 +27,5 @@
 	bool
 config SUPERIO_FINTEK_F71889
 	bool
+config SUPERIO_FINTEK_F81865F
+	bool

Modified: trunk/src/superio/fintek/Makefile.inc
==============================================================================
--- trunk/src/superio/fintek/Makefile.inc	Mon Feb 14 19:47:37 2011	(r6348)
+++ trunk/src/superio/fintek/Makefile.inc	Mon Feb 14 19:52:15 2011	(r6349)
@@ -22,3 +22,4 @@
 subdirs-y += f71863fg
 subdirs-y += f71872
 subdirs-y += f71889
+subdirs-y += f81865f

Added: trunk/src/superio/fintek/f81865f/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/fintek/f81865f/Makefile.inc	Mon Feb 14 19:52:15 2011	(r6349)
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += superio.c

Added: trunk/src/superio/fintek/f81865f/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/fintek/f81865f/chip.h	Mon Feb 14 19:52:15 2011	(r6349)
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_FINTEK_F81865_CHIP_H
+#define SUPERIO_FINTEK_F81865_CHIP_H
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+/* This chip doesn't have keyboard and mouse support. */
+
+extern struct chip_operations superio_fintek_f81865f_ops;
+
+struct superio_fintek_f81865f_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif

Added: trunk/src/superio/fintek/f81865f/f81865f.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/fintek/f81865f/f81865f.h	Mon Feb 14 19:52:15 2011	(r6349)
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * Datasheet:
+ *  - Name: F81865F/F-I
+ */
+#ifndef SUPERIO_FINTEK_F81865_F81865_H
+#define SUPERIO_FINTEK_F81865_F81865_H
+
+/* Logical Device Numbers (LDN). */
+#define	F81865F_FDC	0x00	/* Floppy */
+#define	F81865F_SP1	0x10	/* UART1 */
+#define	F81865F_SP2	0x11	/* UART2 */
+#define	F81865F_PP	0x03	/* Parallel Port */
+#define	F81865F_HWM	0x04	/* Hardware Monitor */
+#define	F81865F_KBC	0x05	/* Keyboard/Mouse */
+#define	F81865F_GPIO	0x06	/* General Purpose I/O (GPIO) */
+#define	F81865F_PME	0x0a	/* Power Management Events (PME) */
+
+#endif

Added: trunk/src/superio/fintek/f81865f/f81865f_early_serial.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/fintek/f81865f/f81865f_early_serial.c	Mon Feb 14 19:52:15 2011	(r6349)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include "f81865f.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0x87, port);
+	outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0xaa, port);
+}
+
+static void f81865f_enable_serial(device_t dev, u16 iobase)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}

Added: trunk/src/superio/fintek/f81865f/superio.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/fintek/f81865f/superio.c	Mon Feb 14 19:52:15 2011	(r6349)
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "f81865f.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+	outb(0x87, dev->path.pnp.port);
+	outb(0x87, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	outb(0xaa, dev->path.pnp.port);
+}
+
+static void f81865f_init(device_t dev)
+{
+	struct superio_fintek_f81865f_config *conf = dev->chip_info;
+	struct resource *res0;
+
+	if (!dev->enabled)
+		return;
+
+	switch (dev->path.pnp.device) {
+	/* TODO: Might potentially need code for HWM or FDC etc. */
+	case F81865F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case F81865F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case F81865F_KBC:
+		pc_keyboard_init(&conf->keyboard);
+		break;
+	}
+}
+
+static void f81865f_pnp_set_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void f81865f_pnp_enable_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_enable_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void f81865f_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	(dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+	pnp_exit_conf_state(dev);
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = f81865f_pnp_set_resources,
+	.enable_resources = f81865f_pnp_enable_resources,
+	.enable           = f81865f_pnp_enable,
+	.init             = f81865f_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	/* TODO: Some of the 0x7f8 etc. values may not be correct. */
+	{ &ops, F81865F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, F81865F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, F81865F_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, F81865F_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0}, },
+	{ &ops, F81865F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, F81865F_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
+	{ &ops, F81865F_GPIO, PNP_IRQ0, },
+	{ &ops, F81865F_PME, },
+};
+
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_fintek_f81865f_ops = {
+	CHIP_NAME("Fintek F81865F Super I/O")
+	.enable_dev = enable_dev
+};



From marcj303 at gmail.com  Mon Feb 14 19:52:35 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 11:52:35 -0700
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 6 of 8.
In-Reply-To: <20110214180839.GG29618@coreboot.org>
References: <276EC11373289744A112A8FE66755067019CFD642F@SAUSEXMBP01.amd.com>
	<20110214180839.GG29618@coreboot.org>
Message-ID: <AANLkTi==VQ+5icA0iSKrb-xM_ZWWAS3xLNknxUoOdfXE@mail.gmail.com>

On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:53]:
>> Add Fintek f81865f superio code. ?Patch 6 of 8.
>>
>> This code provides support for the superio chip on the IBASE Technology
>> DB-FT1 (AMD code name Persimmon) platform. ?It is independent of the AMD
>> code.
>>
>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Acked-by: Marc Jones <marcj303 at gmail.com>

r6394

-- 
http://se-eng.com



From svn at coreboot.org  Mon Feb 14 19:56:10 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Feb 2011 19:56:10 +0100
Subject: [coreboot] [commit] r6350 - trunk/src/include/cpu/amd
Message-ID: <E1Pp3ak-0003fz-VQ@ra.coresystems.de>

Author: mjones
Date: Mon Feb 14 19:56:10 2011
New Revision: 6350
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6350

Log:
I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347.

Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com

Added:
   trunk/src/include/cpu/amd/amdfam14.h

Added: trunk/src/include/cpu/amd/amdfam14.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/include/cpu/amd/amdfam14.h	Mon Feb 14 19:56:10 2011	(r6350)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef CPU_AMD_FAM14_H
+#define CPU_AMD_FAM14_H
+
+#include <cpu/x86/msr.h>
+
+#define HWCR_MSR			0xC0010015
+#define NB_CFG_MSR			0xC001001f
+#define LS_CFG_MSR			0xC0011020
+#define IC_CFG_MSR			0xC0011021
+#define DC_CFG_MSR			0xC0011022
+#define BU_CFG_MSR			0xC0011023
+#define BU_CFG2_MSR			0xC001102A
+
+#define CPU_ID_FEATURES_MSR		0xC0011004
+#define CPU_ID_EXT_FEATURES_MSR	0xC0011005
+
+msr_t rdmsr_amd(u32 index);
+void wrmsr_amd(u32 index, msr_t msr);
+
+//#if defined(__GNUC__)
+//// it can be used to get unitid and coreid it running only
+//struct node_core_id get_node_core_id(u32 nb_cfg_54);
+//struct node_core_id get_node_core_id_x(void);
+//#endif
+
+#if defined(__PRE_RAM__)
+void wait_all_core0_started(void);
+void wait_all_other_cores_started(u32 bsp_apicid);
+void wait_all_aps_started(u32 bsp_apicid);
+void allow_all_aps_stop(u32 bsp_apicid);
+#endif
+u32 get_initial_apicid(void);
+
+#endif /* CPU_AMD_FAM14_H */



From marcj303 at gmail.com  Mon Feb 14 19:56:22 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 11:56:22 -0700
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 4 of 8.
In-Reply-To: <AANLkTimtU0C6veO6bVDLP5n8acHYhOCfQ2CQFyO0cRYj@mail.gmail.com>
References: <276EC11373289744A112A8FE66755067019CFD642D@SAUSEXMBP01.amd.com>
	<20110214180811.GE29618@coreboot.org>
	<AANLkTimtU0C6veO6bVDLP5n8acHYhOCfQ2CQFyO0cRYj@mail.gmail.com>
Message-ID: <AANLkTikXYbmSy5n+KsbpPm_4=k7+jKg1dhB7F4iW9Ad6@mail.gmail.com>

On Mon, Feb 14, 2011 at 11:42 AM, Marc Jones <marcj303 at gmail.com> wrote:
> On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer
> <stefan.reinauer at coreboot.org> wrote:
>> * Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:50]:
>>> Add AMD cpu wrapper code. ?Patch 4 of 8.
>>>
>>> This code provides cpu early initialization for Family 14h cpus. ?It is
>>> dependent on the AMD Agesa code.
>>>
>>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>>>
>>
>>> Add AMD cpu wrapper code. ?Patch 4 of 8.
>>>
>>> This code provides cpu early initialization for Family 14h cpus. ?It is
>>> dependent on the AMD Agesa code.
>>>
>>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>>
>> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
>
> Acked-by: Marc Jones <marcj303 at gmail.com>
>
> Thanks Frank!
> r6347

I missed a file, also  r6350


-- 
http://se-eng.com



From marcj303 at gmail.com  Mon Feb 14 19:57:17 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 11:57:17 -0700
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 6 of 8.
In-Reply-To: <AANLkTi==VQ+5icA0iSKrb-xM_ZWWAS3xLNknxUoOdfXE@mail.gmail.com>
References: <276EC11373289744A112A8FE66755067019CFD642F@SAUSEXMBP01.amd.com>
	<20110214180839.GG29618@coreboot.org>
	<AANLkTi==VQ+5icA0iSKrb-xM_ZWWAS3xLNknxUoOdfXE@mail.gmail.com>
Message-ID: <AANLkTinV=U6P910BNOPq+XaFhBQzuOZwAyHL7ioQyiex@mail.gmail.com>

On Mon, Feb 14, 2011 at 11:52 AM, Marc Jones <marcj303 at gmail.com> wrote:
> On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer
> <stefan.reinauer at coreboot.org> wrote:
>> * Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:53]:
>>> Add Fintek f81865f superio code. ?Patch 6 of 8.
>>>
>>> This code provides support for the superio chip on the IBASE Technology
>>> DB-FT1 (AMD code name Persimmon) platform. ?It is independent of the AMD
>>> code.
>>>
>>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>>
>> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
>
> Acked-by: Marc Jones <marcj303 at gmail.com>
>
> r6394

oops typo

r6349



-- 
http://se-eng.com



From svn at coreboot.org  Mon Feb 14 20:00:14 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Feb 2011 20:00:14 +0100
Subject: [coreboot] [commit] r6351 - in trunk/src/superio/smsc: . kbc1100
Message-ID: <E1Pp3eg-0001Za-4f@ra.coresystems.de>

Author: mjones
Date: Mon Feb 14 20:00:13 2011
New Revision: 6351
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6351

Log:
This code provides support for the superio chip on the AMD Inagua platform (not commercially available). It is independent of the AMD>code.

Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Added:
   trunk/src/superio/smsc/kbc1100/
   trunk/src/superio/smsc/kbc1100/Makefile.inc
   trunk/src/superio/smsc/kbc1100/chip.h
   trunk/src/superio/smsc/kbc1100/kbc1100.h
   trunk/src/superio/smsc/kbc1100/kbc1100_early_init.c
   trunk/src/superio/smsc/kbc1100/superio.c
Modified:
   trunk/src/superio/smsc/Kconfig
   trunk/src/superio/smsc/Makefile.inc

Modified: trunk/src/superio/smsc/Kconfig
==============================================================================
--- trunk/src/superio/smsc/Kconfig	Mon Feb 14 19:56:10 2011	(r6350)
+++ trunk/src/superio/smsc/Kconfig	Mon Feb 14 20:00:13 2011	(r6351)
@@ -35,5 +35,7 @@
 	bool
 config SUPERIO_SMSC_SIO10N268
 	bool
+config SUPERIO_SMSC_KBC1100
+	bool
 config SUPERIO_SMSC_SMSCSUPERIO
 	bool

Modified: trunk/src/superio/smsc/Makefile.inc
==============================================================================
--- trunk/src/superio/smsc/Makefile.inc	Mon Feb 14 19:56:10 2011	(r6350)
+++ trunk/src/superio/smsc/Makefile.inc	Mon Feb 14 20:00:13 2011	(r6351)
@@ -26,4 +26,5 @@
 subdirs-y += lpc47n217
 subdirs-y += lpc47n227
 subdirs-y += sio10n268
+subdirs-y += kbc1100
 subdirs-y += smscsuperio

Added: trunk/src/superio/smsc/kbc1100/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/smsc/kbc1100/Makefile.inc	Mon Feb 14 20:00:13 2011	(r6351)
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+ramstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += superio.c

Added: trunk/src/superio/smsc/kbc1100/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/smsc/kbc1100/chip.h	Mon Feb 14 20:00:13 2011	(r6351)
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_SMSC_KBC1100_CHIP_H
+#define SUPERIO_SMSC_KBC1100_CHIP_H
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct chip_operations;
+extern struct chip_operations superio_smsc_kbc1100_ops;
+
+struct superio_smsc_kbc1100_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif
\ No newline at end of file

Added: trunk/src/superio/smsc/kbc1100/kbc1100.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/smsc/kbc1100/kbc1100.h	Mon Feb 14 20:00:13 2011	(r6351)
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define KBC1100_PM1              1            /* PM1 */
+#define SMSCSUPERIO_SP1          4            /* Com1 */
+#define SMSCSUPERIO_SP2          5            /* Com2 */
+#define KBC1100_KBC              7            /* Keyboard */
+#define KBC1100_EC0              8            /* EC Channel 0 */
+#define KBC1100_MAILBOX          9            /* Mail Box */
+#define KBC1100_GPIO             0x0A         /* GPIO */
+#define KBC1100_SPI              0x0B         /* Share flash interface */
+
+#define KBC1100_EC1              0x0D         /* EC Channel 1 */
+#define KBC1100_EC2              0x0E         /* EC Channel 2 */
+
+

Added: trunk/src/superio/smsc/kbc1100/kbc1100_early_init.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/smsc/kbc1100/kbc1100_early_init.c	Mon Feb 14 20:00:13 2011	(r6351)
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
+
+#include <arch/romcc_io.h>
+#include "kbc1100.h"
+
+static inline void pnp_enter_conf_state(device_t dev)
+{
+  unsigned port = dev>>8;
+  outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+  unsigned port = dev>>8;
+  outb(0xaa, port);
+}
+
+static inline void kbc1100_early_init(unsigned port)
+{
+  device_t dev;
+  dev = PNP_DEV (port, KBC1100_KBC);
+
+  pnp_enter_conf_state(dev);
+  
+  /* Serial IRQ enabled */
+  outb(0x25, port);
+  outb(0x04, port + 1);
+  
+  /* Enable SMSC UART 0 */
+  dev = PNP_DEV (port, SMSCSUPERIO_SP1);
+  pnp_set_logical_device(dev);
+  pnp_set_enable(dev, 0);
+  pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
+  pnp_set_enable(dev, 1);
+
+  /* Enable keyboard */
+  dev = PNP_DEV (port, KBC1100_KBC);
+  pnp_set_logical_device(dev);
+  pnp_set_enable(dev, 0);
+  pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
+  pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
+  pnp_set_irq(dev, 0x70, 1);   /* IRQ 1 */
+  pnp_set_irq(dev, 0x72, 12);   /* IRQ 12 */
+  pnp_set_enable(dev, 1);
+
+  /* Enable EC Channel 0 */
+  dev = PNP_DEV (port, KBC1100_EC0);
+  pnp_set_logical_device(dev);
+  pnp_set_enable(dev, 1);
+
+  pnp_exit_conf_state(dev);
+
+  /* disable the 1s timer */
+  outb(0xE7, 0x64);  
+}
+

Added: trunk/src/superio/smsc/kbc1100/superio.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/smsc/kbc1100/superio.c	Mon Feb 14 20:00:13 2011	(r6351)
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* RAM driver for the SMSC KBC1100 Super I/O chip */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "kbc1100.h"
+
+/* Forward declarations */
+static void enable_dev(device_t dev);
+static void kbc1100_pnp_set_resources(device_t dev);
+static void kbc1100_pnp_enable_resources(device_t dev);
+static void kbc1100_pnp_enable(device_t dev);
+static void kbc1100_init(device_t dev);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+
+struct chip_operations superio_smsc_kbc1100_ops = {
+  CHIP_NAME("SMSC KBC1100 Super I/O")
+  .enable_dev = enable_dev
+};
+
+static struct device_operations ops = {
+  .read_resources   = pnp_read_resources,
+  .set_resources    = kbc1100_pnp_set_resources,
+  .enable_resources = kbc1100_pnp_enable_resources,
+  .enable           = kbc1100_pnp_enable,
+  .init             = kbc1100_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+  { &ops, KBC1100_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+};
+
+static void enable_dev(device_t dev)
+{
+  pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+static void kbc1100_pnp_set_resources(device_t dev)
+{
+  pnp_enter_conf_state(dev);
+  pnp_set_resources(dev);
+  pnp_exit_conf_state(dev);
+}
+
+static void kbc1100_pnp_enable_resources(device_t dev)
+{
+  pnp_enter_conf_state(dev);
+  pnp_enable_resources(dev);
+  pnp_exit_conf_state(dev);
+}
+
+static void kbc1100_pnp_enable(device_t dev)
+{
+  pnp_enter_conf_state(dev);
+  pnp_set_logical_device(dev);
+
+  if(dev->enabled) {
+    pnp_set_enable(dev, 1);
+  }
+  else {
+    pnp_set_enable(dev, 0);
+  }
+  pnp_exit_conf_state(dev);
+}
+
+static void kbc1100_init(device_t dev)
+{
+  struct superio_smsc_kbc1100_config *conf = dev->chip_info;
+  struct resource *res0, *res1;
+
+  
+   
+  if (!dev->enabled) {
+    return;
+  }
+
+  switch(dev->path.pnp.device) {
+  
+  case KBC1100_KBC:
+    res0 = find_resource(dev, PNP_IDX_IO0);
+    res1 = find_resource(dev, PNP_IDX_IO1);
+    pc_keyboard_init(&conf->keyboard);
+    break;
+  }
+}
+
+static void pnp_enter_conf_state(device_t dev)
+{
+  outb(0x55, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+  outb(0xaa, dev->path.pnp.port);
+}



From marcj303 at gmail.com  Mon Feb 14 20:00:29 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 12:00:29 -0700
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 7 of 8.
In-Reply-To: <20110214180855.GH29618@coreboot.org>
References: <276EC11373289744A112A8FE66755067019CFD6430@SAUSEXMBP01.amd.com>
	<20110214180855.GH29618@coreboot.org>
Message-ID: <AANLkTim3rb9Dhu0Y7fa1TSNDzv+4avLuqAY6ohW_XYKU@mail.gmail.com>

On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:55]:
>> Add SMSC KBC 1100 superio code. ?Patch 7 of 8.
>>
>> This code provides support for the superio chip on the AMD Inagua
>> platform (not commercially available). ?It is independent of the AMD
>> code.
>>
>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Acked-by: Marc Jones <marcj303 at gmail.com>

r6351

-- 
http://se-eng.com



From marcj303 at gmail.com  Mon Feb 14 20:05:10 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 14 Feb 2011 12:05:10 -0700
Subject: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 8 of 8.
In-Reply-To: <20110214180909.GI29618@coreboot.org>
References: <276EC11373289744A112A8FE66755067019CFD6431@SAUSEXMBP01.amd.com>
	<20110214180909.GI29618@coreboot.org>
Message-ID: <AANLkTinVhG5hSrKNJ5qMPCF75=ToeZ_-b5+cNLgWEV2O@mail.gmail.com>

On Mon, Feb 14, 2011 at 11:09 AM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * Vibrans, Frank <Frank.Vibrans at amd.com> [110213 22:55]:
>> Add IBASE DB-FT1 and AMD Inagua motherboards. ?Patch 8 of 8.
>>
>> This code provides support for IBASE Technology DB-FT1 (AMD code
>> name Persimmon) and AMD Inagua platforms. ?It is dependent on all
>> other patches in this set.
>>
>> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Acked-by: Marc Jones <marcj303 at gmail.com>

r6352

-- 
http://se-eng.com



From svn at coreboot.org  Mon Feb 14 20:15:37 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Feb 2011 20:15:37 +0100
Subject: [coreboot] [commit] r6353 - trunk/src/mainboard/amd/inagua
Message-ID: <E1Pp3tZ-0006Fh-B0@ra.coresystems.de>

Author: oxygene
Date: Mon Feb 14 20:15:36 2011
New Revision: 6353
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6353

Log:
Fix Typo. (and why is that file, and some of its siblings per-board?)

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/src/mainboard/amd/inagua/agesawrapper.c

Modified: trunk/src/mainboard/amd/inagua/agesawrapper.c
==============================================================================
--- trunk/src/mainboard/amd/inagua/agesawrapper.c	Mon Feb 14 20:04:45 2011	(r6352)
+++ trunk/src/mainboard/amd/inagua/agesawrapper.c	Mon Feb 14 20:15:36 2011	(r6353)
@@ -402,7 +402,7 @@
       return AcpiWheaCmc;
     case PICK_ALIB:
       return AcpiAlib;
-    defaut:
+    default:
       return NULL;
   }
 }



From svn at coreboot.org  Mon Feb 14 19:30:56 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Feb 2011 19:30:56 +0100
Subject: [coreboot] [commit] r6344 - in trunk/src/vendorcode: . amd
	amd/agesa amd/agesa/Include amd/agesa/Legacy
	amd/agesa/Legacy/Proc amd/agesa/Lib amd/agesa/Lib/IA32
	amd/agesa/Lib/x64 amd/agesa/Proc amd/agesa/Proc/C...
Message-ID: <E1Pp3CK-0008Tm-K3@ra.coresystems.de>

Author: mjones
Date: Mon Feb 14 19:30:54 2011
New Revision: 6344
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6344

Log:
Add AMD Agesa and AMD CIMx SB800 code.  Patch 1 of 8.

This code currently generates many warnings that are functionally benign.  These are being addressed, but the wheels of bureaucracy turn slowly.  This drop supports AMD cpu families 10h and 14h.  Only Family 14h is used as an example in this set of patches.  Other cpu families are supported by the infrastructure, but their specific support is not included herein.  This patch is functionally independent of the other patches in this set.

Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Marc Jones <marcj303 at gmail.com>

Added:
   trunk/src/vendorcode/
   trunk/src/vendorcode/Makefile.inc
   trunk/src/vendorcode/amd/
   trunk/src/vendorcode/amd/agesa/
   trunk/src/vendorcode/amd/agesa/AGESA.h
   trunk/src/vendorcode/amd/agesa/AMD.h
   trunk/src/vendorcode/amd/agesa/Dispatcher.h
   trunk/src/vendorcode/amd/agesa/Include/
   trunk/src/vendorcode/amd/agesa/Include/AdvancedApi.h
   trunk/src/vendorcode/amd/agesa/Include/BrazosInstall.h
   trunk/src/vendorcode/amd/agesa/Include/CommonReturns.h
   trunk/src/vendorcode/amd/agesa/Include/DanNiInstall.h
   trunk/src/vendorcode/amd/agesa/Include/DanubeInstall.h
   trunk/src/vendorcode/amd/agesa/Include/DevTestInstall.h
   trunk/src/vendorcode/amd/agesa/Include/DragonInstall.h
   trunk/src/vendorcode/amd/agesa/Include/Filecode.h
   trunk/src/vendorcode/amd/agesa/Include/GeneralServices.h
   trunk/src/vendorcode/amd/agesa/Include/GnbInterface.h
   trunk/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h
   trunk/src/vendorcode/amd/agesa/Include/Ids.h
   trunk/src/vendorcode/amd/agesa/Include/IdsHt.h
   trunk/src/vendorcode/amd/agesa/Include/LynxInstall.h
   trunk/src/vendorcode/amd/agesa/Include/MaranelloInstall.h
   trunk/src/vendorcode/amd/agesa/Include/NileInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionC6Install.h
   trunk/src/vendorcode/amd/agesa/Include/OptionCpbInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionCpuCacheFlushOnHaltInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionCpuCoreLevelingInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionCpuFamiliesInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionCpuFeaturesInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionDmi.h
   trunk/src/vendorcode/amd/agesa/Include/OptionDmiInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionFamily10hInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionFamily12hEarlySample.h
   trunk/src/vendorcode/amd/agesa/Include/OptionFamily12hInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionFamily14hEarlySample.h
   trunk/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionGfxRecovery.h
   trunk/src/vendorcode/amd/agesa/Include/OptionGfxRecoveryInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionGnb.h
   trunk/src/vendorcode/amd/agesa/Include/OptionGnbInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionHtAssistInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionHtInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionHwC1eInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionIdsInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionMemory.h
   trunk/src/vendorcode/amd/agesa/Include/OptionMemoryInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h
   trunk/src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionMultiSocket.h
   trunk/src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionPstate.h
   trunk/src/vendorcode/amd/agesa/Include/OptionPstateInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionSlit.h
   trunk/src/vendorcode/amd/agesa/Include/OptionSlitInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionSrat.h
   trunk/src/vendorcode/amd/agesa/Include/OptionSratInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionSwC1eInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionWhea.h
   trunk/src/vendorcode/amd/agesa/Include/OptionWheaInstall.h
   trunk/src/vendorcode/amd/agesa/Include/Options.h
   trunk/src/vendorcode/amd/agesa/Include/OptionsHt.h
   trunk/src/vendorcode/amd/agesa/Include/OptionsPage.h
   trunk/src/vendorcode/amd/agesa/Include/PlatformInstall.h
   trunk/src/vendorcode/amd/agesa/Include/PlatformMemoryConfiguration.h
   trunk/src/vendorcode/amd/agesa/Include/SabineInstall.h
   trunk/src/vendorcode/amd/agesa/Include/SanMarinoInstall.h
   trunk/src/vendorcode/amd/agesa/Include/ScorpiusInstall.h
   trunk/src/vendorcode/amd/agesa/Include/TigrisInstall.h
   trunk/src/vendorcode/amd/agesa/Include/Topology.h
   trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h
   trunk/src/vendorcode/amd/agesa/Legacy/
   trunk/src/vendorcode/amd/agesa/Legacy/PlatformMemoryConfiguration.inc
   trunk/src/vendorcode/amd/agesa/Legacy/Proc/
   trunk/src/vendorcode/amd/agesa/Legacy/Proc/Dispatcher.c
   trunk/src/vendorcode/amd/agesa/Legacy/Proc/Legacy.bat
   trunk/src/vendorcode/amd/agesa/Legacy/Proc/agesaCallouts.c
   trunk/src/vendorcode/amd/agesa/Legacy/Proc/arch2008.asm
   trunk/src/vendorcode/amd/agesa/Legacy/Proc/hobTransfer.c
   trunk/src/vendorcode/amd/agesa/Legacy/agesa.inc
   trunk/src/vendorcode/amd/agesa/Legacy/amd.inc
   trunk/src/vendorcode/amd/agesa/Legacy/bridge32.inc
   trunk/src/vendorcode/amd/agesa/Lib/
   trunk/src/vendorcode/amd/agesa/Lib/IA32/
   trunk/src/vendorcode/amd/agesa/Lib/IA32/amdlib32.asm
   trunk/src/vendorcode/amd/agesa/Lib/IA32/ms_shift.asm
   trunk/src/vendorcode/amd/agesa/Lib/IA32/msmemcpy.asm
   trunk/src/vendorcode/amd/agesa/Lib/amdlib.c
   trunk/src/vendorcode/amd/agesa/Lib/amdlib.h
   trunk/src/vendorcode/amd/agesa/Lib/helper.c
   trunk/src/vendorcode/amd/agesa/Lib/x64/
   trunk/src/vendorcode/amd/agesa/Lib/x64/amdlib64.asm
   trunk/src/vendorcode/amd/agesa/MainPage.h
   trunk/src/vendorcode/amd/agesa/Makefile.inc
   trunk/src/vendorcode/amd/agesa/Porting.h
   trunk/src/vendorcode/amd/agesa/Proc/
   trunk/src/vendorcode/amd/agesa/Proc/CPU/
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10InitEarlyTable.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10IoCstate.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PackageType.h
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
   trunk/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
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   trunk/src/vendorcode/amd/agesa/Proc/Recovery/GNB/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GfxRecovery.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GfxRecovery.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GnbRecovery.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/GNB/NbInitRecovery.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/GNB/NbInitRecovery.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/HT/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/HT/htInitRecovery.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/HT/htInitReset.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnc32.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnc32.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnda.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnda.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnmctda.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrndr.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrndr.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrndcthy.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnhy.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnhy.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/NI/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/NI/mrnNi.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/NI/mrnNi.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrndcton.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnmcton.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnon.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnon.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/PH/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/PH/mrnPh.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/PH/mrnPh.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/RB/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/RB/mrnRb.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/RB/mrnRb.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrn.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrndct.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrnmct.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrntrain3.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrp.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplribt.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplrnlr.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplrnpr.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpmr0.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpodtpat.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprc10opspd.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprc2ibt.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprtt.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpsao.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrtthrc.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrttpos.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrttsrc.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrdef.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrinit.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrm.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrport.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrt3.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.asm
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.h
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mruc.c
   trunk/src/vendorcode/amd/agesa/Proc/Recovery/recoveryPage.h
   trunk/src/vendorcode/amd/agesa/cpcar.inc
   trunk/src/vendorcode/amd/agesa/cpcarmac.inc
   trunk/src/vendorcode/amd/agesa/errno.h
   trunk/src/vendorcode/amd/agesa/gcccar.inc
   trunk/src/vendorcode/amd/cimx/
   trunk/src/vendorcode/amd/cimx/sb800/
   trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c
   trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.h
   trunk/src/vendorcode/amd/cimx/sb800/AMDLIB.c
   trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
   trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
   trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c
   trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
   trunk/src/vendorcode/amd/cimx/sb800/EC.c
   trunk/src/vendorcode/amd/cimx/sb800/ECLIB.c
   trunk/src/vendorcode/amd/cimx/sb800/ECfan.h
   trunk/src/vendorcode/amd/cimx/sb800/ECfanLIB.c
   trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c
   trunk/src/vendorcode/amd/cimx/sb800/GEC.c
   trunk/src/vendorcode/amd/cimx/sb800/Gpp.c
   trunk/src/vendorcode/amd/cimx/sb800/IOLIB.c
   trunk/src/vendorcode/amd/cimx/sb800/LEGACY.c
   trunk/src/vendorcode/amd/cimx/sb800/MEMLIB.c
   trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc
   trunk/src/vendorcode/amd/cimx/sb800/OEM.h
   trunk/src/vendorcode/amd/cimx/sb800/PCILIB.c
   trunk/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c
   trunk/src/vendorcode/amd/cimx/sb800/PMIOLIB.c
   trunk/src/vendorcode/amd/cimx/sb800/SATA.c
   trunk/src/vendorcode/amd/cimx/sb800/SB800.h
   trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c
   trunk/src/vendorcode/amd/cimx/sb800/SBDEF.h
   trunk/src/vendorcode/amd/cimx/sb800/SBMAIN.c
   trunk/src/vendorcode/amd/cimx/sb800/SBPELIB.c
   trunk/src/vendorcode/amd/cimx/sb800/SBPOR.c
   trunk/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
   trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h
   trunk/src/vendorcode/amd/cimx/sb800/SMM.c
   trunk/src/vendorcode/amd/cimx/sb800/SbModInf.c
   trunk/src/vendorcode/amd/cimx/sb800/USB.c

Added: trunk/src/vendorcode/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/Makefile.inc	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1 @@
+subdirs-y += amd

Added: trunk/src/vendorcode/amd/agesa/AGESA.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/AGESA.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,3022 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 41504 $   @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+
+#ifndef _AGESA_H_
+#define _AGESA_H_
+
+#include  "Porting.h"
+#include  "AMD.h"
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+
+// AGESA BASIC CALLOUTS
+#define AGESA_MEM_RELEASE              0x00028000
+
+// AGESA ADVANCED CALLOUTS, Processor
+#define AGESA_CHECK_UMA                0x00028100
+#define AGESA_DO_RESET                 0x00028101
+#define AGESA_ALLOCATE_BUFFER          0x00028102
+#define AGESA_DEALLOCATE_BUFFER        0x00028103
+#define AGESA_LOCATE_BUFFER            0x00028104
+#define AGESA_RUNFUNC_ONAP             0x00028105
+
+// AGESA ADVANCED CALLOUTS, HyperTransport
+
+// AGESA ADVANCED CALLOUTS, Memory
+#define AGESA_READ_SPD                 0x00028140
+#define AGESA_HOOKBEFORE_DRAM_INIT     0x00028141
+#define AGESA_HOOKBEFORE_DQS_TRAINING  0x00028142
+#define AGESA_READ_SPD_RECOVERY        0x00028143
+#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144
+#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY     0x00028145
+
+// AGESA IDS CALLOUTS
+#define AGESA_GET_IDS_INIT_DATA       0x00028200
+
+// AGESA GNB CALLOUTS
+#define AGESA_GNB_PCIE_SLOT_RESET      0x00028301
+
+//------------------------------------------------------------------------
+//
+// HyperTransport Interface
+
+
+
+//-----------------------------------------------------------------------------
+//                         HT DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+
+// Width equates for call backs
+#define HT_WIDTH_8_BITS              8                          ///< Specifies 8 bit, or up to 8 bit widths.
+#define HT_WIDTH_16_BITS             16                         ///< Specifies 16 bit, or up to 16 bit widths.
+#define HT_WIDTH_4_BITS              4
+#define HT_WIDTH_2_BITS              2
+#define HT_WIDTH_NO_LIMIT            HT_WIDTH_16_BITS
+
+// Frequency Limit equates for call backs which take a frequency supported mask.
+#define HT_FREQUENCY_LIMIT_200M      1                           ///< Specifies a limit of no more than 200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_400M      7                           ///< Specifies a limit of no more than 400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_600M      0x1F                        ///< Specifies a limit of no more than 600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_800M      0x3F                        ///< Specifies a limit of no more than 800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1000M     0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_HT1_ONLY  0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1200M     0xFF                        ///< Specifies a limit of no more than 1200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1400M     0x1FF                       ///< Specifies a limit of no more than 1400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1600M     0x3FF                       ///< Specifies a limit of no more than 1600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1800M     0x7FF                       ///< Specifies a limit of no more than 1800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2000M     0xFFF                       ///< Specifies a limit of no more than 2000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2200M     0x1FFF                      ///< Specifies a limit of no more than 2200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2400M     0x3FFF                      ///< Specifies a limit of no more than 2400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2600M     0x7FFF                      ///< Specifies a limit of no more than 2600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2800M     0x27FFF                     ///< Specifies a limit of no more than 2800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3000M     0x67FFF                     ///< Specifies a limit of no more than 3000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3200M     0xE7FFF                     ///< Specifies a limit of no more than 3200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3600M     0x1E7FFF
+#define HT_FREQUENCY_LIMIT_MAX       HT_FREQUENCY_LIMIT_3600M
+#define HT_FREQUENCY_NO_LIMIT        0xFFFFFFFF                  ///< Specifies a no limit of HT frequency.
+
+// Unit ID Clumping special values
+#define HT_CLUMPING_DISABLE          0x00000000
+#define HT_CLUMPING_NO_LIMIT         0xFFFFFFFF
+
+#define HT_LIST_TERMINAL             0xFF             ///< End of list.
+#define HT_LIST_MATCH_ANY            0xFE             ///< Match Any value, used for Sockets, Links, IO Chain Depth.
+#define HT_LIST_MATCH_INTERNAL_LINK  0xFD             ///< Match all of the internal links.
+
+// Event Notify definitions
+
+// Event definitions.
+
+// Coherent subfunction events
+#define HT_EVENT_COH_EVENTS             0x10001000
+#define HT_EVENT_COH_NO_TOPOLOGY        0x10011000    ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
+#define HT_EVENT_COH_OBSOLETE000        0x10021000    //   No longer used.
+#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000    ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
+#define HT_EVENT_COH_NODE_DISCOVERED    0x10041000    ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
+#define HT_EVENT_COH_MPCAP_MISMATCH     0x10051000    ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
+
+// Non-coherent subfunction events
+#define HT_EVENT_NCOH_EVENTS         0x10002000
+#define HT_EVENT_NCOH_BUID_EXCEED    0x10012000       ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
+#define HT_EVENT_NCOH_OBSOLETE000    0x10022000       //   No longer used.
+#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000       ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
+#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000       ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
+#define HT_EVENT_NCOH_DEVICE_FAILED  0x10052000       ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
+#define HT_EVENT_NCOH_AUTO_DEPTH     0x10062000       ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
+
+// Optimization subfunction events
+#define HT_EVENT_OPT_EVENTS               0x10003000
+#define HT_EVENT_OPT_REQUIRED_CAP_RETRY   0x10013000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_REQUIRED_CAP_GEN3    0x10023000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_UNUSED_LINKS         0x10033000  ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
+#define HT_EVENT_OPT_LINK_PAIR_EXCEED     0x10043000  ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
+
+// HW Fault events
+#define HT_EVENT_HW_EVENTS           0x10004000
+#define HT_EVENT_HW_SYNCFLOOD        0x10014000       ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
+#define HT_EVENT_HW_HTCRC            0x10024000       ///< See ::HT_EVENT_DATA_HW_HT_CRC.
+
+// The Recovery HT component uses 0x10005000 for events.
+// For consistency, we avoid that range here.
+
+#define HT_MAX_NC_BUIDS 32
+//----------------------------------------------------------------------------
+//                         HT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// Specify the state redundant links are to be left in after match.
+///
+/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone,
+/// or powered off.
+
+typedef enum {
+  MATCHED,                               ///< The link matches the requested customization.
+                                         ///< When used with IGNORE_LINK,
+                                         ///< this will generally require other software to initialize the link.
+                                         ///< When used with SKIP_REGANG,
+                                         ///< the two unganged links will be available for distribution.
+
+  POWERED_OFF,                           ///< Power the link off.  Support may vary based on processor model.
+                                         ///< Power Off is only supported for coherent links.
+                                         ///< Link power off may occur at a warm reset rather than immediately.
+                                         ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link.
+
+  UNMATCHED,                             ///< The link should be processed according to normal defaults.
+                                         ///< Effectively, the link does not match the requested customization.
+                                         ///< This can be used to exclude links from a following match any.
+
+  MaxFinalLinkState                      ///< Not a final link state, use for limit checking.
+} FINAL_LINK_STATE;
+
+/// Swap a device from its current id to a new one.
+
+typedef struct {
+  IN       UINT8 FromId;                 ///< The device responding to FromId,
+  IN       UINT8 ToId;                   ///< will be moved to ToId.
+} BUID_SWAP_ITEM;
+
+
+/// Each Non-coherent chain may have a list of device swaps.  After performing the swaps,
+/// the final in order list of device ids is provided. (There can be more swaps than devices.)
+/// The unused entries in both are filled with 0xFF.
+
+typedef struct {
+  IN       BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform
+  IN       UINT8 FinalIds[HT_MAX_NC_BUIDS];       ///< The ordered final BUIDs, resulting from the swaps
+} BUID_SWAP_LIST;
+
+
+/// Control Manual Initialization of Non-Coherent Chains
+///
+/// This interface is checked every time a non-coherent chain is
+/// processed.  BUID assignment may be controlled explicitly on a
+/// non-coherent chain. Provide a swap list.  Swaps controls the
+/// BUID assignment and FinalIds provides the device to device
+/// Linking.  Device orientation can be detected automatically, or
+/// explicitly.  See interface documentation for more details.
+///
+/// If a manual swap list is not supplied,
+/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+/// based on each device's unit count.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                       ///< The Socket on which this chain is located
+  IN       UINT8 Link;                         ///< The Link on the host for this chain
+  // Override fields
+  IN       BUID_SWAP_LIST SwapList;            ///< The swap list
+} MANUAL_BUID_SWAP_LIST;
+
+
+/// Override options for DEVICE_CAP_OVERRIDE.
+///
+/// Specify which override actions should be performed.  For Checks, 1 means to check the item
+/// and 0 means to skip the check.  For the override options, 1 means to apply the override and
+/// 0 means to ignore the override.
+
+typedef struct {
+  IN       UINT32  IsCheckDevVenId:1;     ///< Check Match on Device/Vendor id
+  IN       UINT32  IsCheckRevision:1;     ///< Check Match on device Revision
+  IN       UINT32  IsOverrideWidthIn:1;   ///< Override Width In
+  IN       UINT32  IsOverrideWidthOut:1;  ///< Override Width Out
+  IN       UINT32  IsOverrideFreq:1;      ///< Override Frequency
+  IN       UINT32  IsOverrideClumping:1;  ///< Override Clumping
+  IN       UINT32  IsDoCallout:1;         ///< Make the optional callout
+} DEVICE_CAP_OVERRIDE_OPTIONS;
+
+/// Override capabilities of a device.
+///
+/// This interface is checked once for every Link on every IO device.
+/// Provide the width and frequency capability if needed for this device.
+/// This is used along with device capabilities, the limit interfaces, and northbridge
+/// limits to compute the default settings.  The components of the device's PCI config
+/// address are provided, so its settings can be consulted if need be.
+/// The optional callout is a catch all.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
+  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
+  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
+  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
+  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
+  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
+  IN       DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override.
+  // Override fields
+  IN       UINT8 LinkWidthIn;          ///< modify to change the Link Width In.
+  IN       UINT8 LinkWidthOut;         ///< modify to change the Link Width Out.
+  IN       UINT32 FreqCap;             ///< modify to change the Link's frequency capability.
+  IN       UINT32 Clumping;            ///< modify to change Unit ID clumping support.
+  IN       CALLOUT_ENTRY Callout;      ///< optional call for really complex cases, or NULL.
+} DEVICE_CAP_OVERRIDE;
+
+/// Callout param struct for override capabilities of a device.
+///
+/// If the optional callout is implemented this param struct is passed to it.
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+  // Match fields
+  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
+  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
+  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
+  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
+  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
+  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
+  IN       PCI_ADDR PciAddress;        ///< The Device's PCI Address.
+  // Override fields
+     OUT   UINT8 *LinkWidthIn;          ///< modify to change the Link Width In.
+     OUT   UINT8 *LinkWidthOut;         ///< modify to change the Link Width Out.
+     OUT   UINT32 *FreqCap;             ///< modify to change the Link's frequency capability.
+     OUT   UINT32 *Clumping;            ///< modify to change Unit ID clumping support.
+} DEVICE_CAP_CALLOUT_PARAMS;
+
+///  Limits for CPU to CPU Links.
+///
+///  For each coherent connection this interface is checked once.
+///  Provide the frequency and width if needed for this Link (usually based on board
+///  restriction).  This is used with CPU device capabilities and northbridge limits
+///  to compute the default settings.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
+  IN       UINT8 LinkA;                  ///< The Link on this Node
+  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
+  IN       UINT8 LinkB;                  ///< The Link on that Node
+  // Limit fields
+  IN       UINT8 ABLinkWidthLimit;       ///< modify to change the Link Width A->B
+  IN       UINT8 BALinkWidthLimit;       ///< modify to change the Link Width B-<A
+  IN       UINT32 PcbFreqCap;            ///< modify to change the Link's frequency capability
+} CPU_TO_CPU_PCB_LIMITS;
+
+///  Get limits for non-coherent Links.
+///
+/// For each non-coherent connection this interface is checked once.
+/// Provide the frequency and width if needed for this Link (usually based on board
+/// restriction).  This is used with device capabilities, device overrides, and northbridge limits
+/// to compute the default settings.
+///
+typedef struct {
+  // Match fields
+  IN       UINT8 HostSocket;               ///< The Socket on which this Link is located
+  IN       UINT8 HostLink;                 ///< The Link about to be initialized
+  IN       UINT8 Depth;                    ///< The Depth in the I/O chain from the Host
+  // Limit fields
+  IN       UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor
+  IN       UINT8 UpstreamLinkWidthLimit;   ///< modify to change the Link Width moving toward processor
+  IN       UINT32 PcbFreqCap;              ///< modify to change the Link's frequency capability
+} IO_PCB_LIMITS;
+
+///  Manually control bus number assignment.
+///
+/// This interface is checked every time a non-coherent chain is processed.
+/// If a system can not use the auto Bus numbering feature for non-coherent chain bus
+/// assignments, this interface can provide explicit control.  For each chain, provide
+/// the bus number range to use.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                 ///< The Socket on which this chain is located
+  IN       UINT8 Link;                   ///< The Link on the host for this chain
+  // Override fields
+  IN       UINT8 SecBus;                 ///< Secondary Bus number for this non-coherent chain
+  IN       UINT8 SubBus;                 ///< Subordinate Bus number
+} OVERRIDE_BUS_NUMBERS;
+
+
+///  Ignore a Link.
+///
+///  This interface is checked every time a coherent Link is found and then every
+///  time a non-coherent Link from a CPU is found.
+///  Any coherent or non-coherent Link from a CPU can be ignored and not used
+///  for discovery or initialization.  Useful for connection based systems.
+///  (Note: not checked for IO device to IO Device Links.)
+///  (Note: not usable for internal links (MCM processors).)
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                 ///< The Socket on which this Link is located
+  IN       UINT8 Link;                   ///< The Link about to be initialized
+  // Customization fields
+  IN       FINAL_LINK_STATE LinkState;   ///< The link may be left unitialized, or powered off.
+} IGNORE_LINK;
+
+
+///  Skip reganging of subLinks.
+///
+///  This interface is checked whenever two subLinks are both connected to the same CPUs.
+///  Normally, unganged sublinks between the same two CPUs are reganged.
+///  Provide a matching structure to leave the Links unganged.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
+  IN       UINT8 LinkA;                  ///< The Link on this Node
+  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
+  IN       UINT8 LinkB;                  ///< The Link on that Node
+  // Customization fields
+  IN       FINAL_LINK_STATE LinkState;   ///< The paired sublink may be active, or powered off.
+} SKIP_REGANG;
+
+///  The System Socket layout, which sockets are physically connected.
+///
+///  The hardware method for Socket naming is preferred.  Use this software method only
+///  if required.
+
+typedef struct {
+  IN       UINT8 CurrentSocket;    ///< The socket from which this connection originates.
+  IN       UINT8 CurrentLink;      ///< The Link from the source socket connects to another socket.
+  IN       UINT8 TargetSocket;     ///< The target socket which is connected on that link.
+} SYSTEM_PHYSICAL_SOCKET_MAP;
+
+//----------------------------------------------------------------------------
+///
+/// This is the input structure for AmdHtInitialize.
+///
+typedef struct {
+  // Basic level customization
+  IN       UINT8 AutoBusStart;           ///< For automatic bus number assignment, starting bus number - usually zero.
+                                         ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM}
+  IN       UINT8 AutoBusMax;             ///< For automatic bus number assignment, do not assign above max.
+                                         ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM}
+  IN       UINT8 AutoBusIncrement;       ///< For automatic bus number assignment, each chain gets this many busses.
+                                         ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUMS}
+
+  // Advanced Level Customization
+  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;     ///< Provide Manual Swap List, if any.
+                                                          ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+  IN       DEVICE_CAP_OVERRIDE *DeviceCapOverrideList;    ///< Provide Device Overrides, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST}
+  IN       CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList;   ///< Provide CPU PCB Limits, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}.
+                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+  IN       IO_PCB_LIMITS *IoPcbLimitsList;                ///< Provide IO PCB Limits, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}.
+                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+  IN       OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList;  ///< Provide manual Bus Number assignment, if any.
+                                                          ///< Use either auto bus numbering or override bus
+                                                          ///< numbers, not both.
+                                                          ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST}
+
+  IN       IGNORE_LINK *IgnoreLinkList;                   ///< Provide links to ignore, if any.
+                                                          ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST}
+  IN       SKIP_REGANG *SkipRegangList;                   ///< Provide links to remain unganged, if any.
+                                                          ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST}
+                                                          ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization".
+
+  // Expert Level Customization
+  IN       UINT8 **Topolist;                         ///< Use this topology list in addition to the built in, if not NULL.
+                                                     ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST}
+  IN       SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap;
+                                                     ///< The hardware socket naming method is preferred,
+                                                     ///<  If it can't be used, this provides a software method.
+                                                     ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP}
+} AMD_HT_INTERFACE;
+
+//-----------------------------------------------------------------------------
+//
+// HT Recovery Interface
+//
+
+
+/*-----------------------------------------------------------------------------
+ *              HT Recovery DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+// BBHT subfunction events
+#define HT_EVENT_BB_EVENTS         0x10005000
+#define HT_EVENT_BB_BUID_EXCEED    0x10015000
+#define HT_EVENT_BB_DEVICE_FAILED  0x10055000
+#define HT_EVENT_BB_AUTO_DEPTH     0x10065000
+
+/*----------------------------------------------------------------------------
+ *                      HT Recovery   TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/// The Interface structure to Recovery HT.
+
+typedef struct {
+  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;  ///< Option to manually control SB link init
+                                                       ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+     OUT   UINT32 Depth;           ///< If auto init was used this is set to the depth of the chain,
+                                   ///< else, for manual init unmodified.
+} AMD_HT_RESET_INTERFACE;
+
+/*----------------------------------------------------------------------------
+ *   CPU Feature related info
+ *----------------------------------------------------------------------------
+ */
+
+/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
+typedef enum {
+  C1eModeDisabled                   = 0,   ///< Disabled
+  C1eModeHardware                   = 1,   ///< Hardware method
+  C1eModeMsgBased                   = 2,   ///< Message-based method
+  C1eModeSoftwareDeprecated         = 3,   ///< Deprecated software SMI method.
+                                           ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for
+                                           ///< example host BIOS SMM Handler implementation
+  C1eModeHardwareSoftwareDeprecated = 4,   ///< Hardware or deprecated software SMI method
+  MaxC1eMode                        = 5    ///< Not a valid value, used for verifying input
+} PLATFORM_C1E_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+typedef enum {
+  CStateModeDisabled = 0,           ///< Disabled
+  CStateModeC6       = 1,           ///< C6 State
+  MaxCStateMode      = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_CSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
+typedef enum {
+  CpbModeAuto     = 0,           ///< Auto
+  CpbModeDisabled = 1,           ///< Disabled
+  MaxCpbMode      = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_CPB_MODES;
+
+/*----------------------------------------------------------------------------
+ *   GNB PCIe configuration info
+ *----------------------------------------------------------------------------
+ */
+
+// Event definitions
+
+
+#define GNB_EVENT_INVALID_CONFIGURATION               0x20010000   // User configuration invalid
+#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001   // Requested lane allocation for PCIe port can not be supported
+#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION     0x20010002   // Requested incorrect PCIe port device address
+#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION      0x20010003   // Incorrect parameter in DDI link configuration
+#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION    0x20010004   // Invalid with for PCIe port or DDI link
+#define GNB_EVENT_INVALID_LANES_CONFIGURATION         0x20010005   // Lane double subscribe lanes
+#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION  0x20010006   // Requested lane allocation for DDI link(s) can not be supported
+#define GNB_EVENT_LINK_TRAINING_FAIL                  0x20020000   // PCIe Link training fail
+#define GNB_EVENT_BROKEN_LANE_RECOVERY                0x20030000   // Broken lane workaround applied to recover link training
+#define GNB_EVENT_GEN2_SUPPORT_RECOVERY               0x20040000   // Scale back to GEN1 to recover link training
+
+
+#define DESCRIPTOR_TERMINATE_LIST           0x80000000ull
+
+/// PCIe port misc extended controls
+typedef struct  {
+  IN      UINT8                     LinkComplianceMode :1;  ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
+  IN      UINT8                     LinkSafeMode       :2;  /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
+                                                             *  @li @b 0 - port can advertize muximum supported capability
+                                                             *  @li @b 1 - port limit advertized capability and speed to PCIe Gen1
+                                                             */
+} PCIe_PORT_MISC_CONTROL;
+
+
+/// PCIe port configuration data
+typedef struct  {
+  IN       UINT8                   PortPresent;              ///< Enable PCIe port for initialization.
+  IN       UINT8                   ChannelType;              /**< Channel type.
+                                                               *  @li @b 0 - "lowLoss",
+                                                               *  @li @b 1 - "highLoss",
+                                                               *  @li @b 2 - "mob0db",
+                                                               *  @li @b 3 - "mob3db",
+                                                               *  @li @b 4 - "extnd6db"
+                                                               *  @li @b 5 - "extnd8db"
+                                                               */
+  IN       UINT8                   DeviceNumber;             /**< PCI Device number for port.
+                                                               *   @li @b 0 - Native port device number
+                                                               *   @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12",  @ref F14LaneConfigurations "Family 0x14")
+                                                               */
+  IN       UINT8                   FunctionNumber;           ///< Reserved for future use
+  IN       UINT8                   LinkSpeedCapability;      /**< PCIe link speed/
+                                                               *  @li @b 0 - Maximum supported by silicon
+                                                               *  @li @b 1 - Gen1
+                                                               *  @li @b 2 - Gen2
+                                                               *  @li @b 3 - Gen3
+                                                               */
+  IN       UINT8                   LinkAspm;                 /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
+                                                               *  @li @b 0 - Disabled
+                                                               *  @li @b 1 - L0s only
+                                                               *  @li @b 2 - L1 only
+                                                               *  @li @b 3 - L0s and L1
+                                                               */
+  IN       UINT8                   LinkHotplug;              /**< Hotplug control.
+                                                               *  @li @b 0 - Disabled
+                                                               *  @li @b 1 - Basic
+                                                               *  @li @b 2 - Server
+                                                               *  @li @b 3 - Enhanced
+                                                               */
+  IN       UINT8                   ResetId;                  /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
+                                                               *   identification which control reset for given port.
+                                                               *   Each port with unique GPIO should have unique ResetId assigned.
+                                                               *   All ports use same GPIO to control reset should have same ResetId assigned.
+                                                               *   see AgesaPcieSlotResetContol.
+                                                               */
+  IN       PCIe_PORT_MISC_CONTROL  MiscControls;             ///< Misc extended controls
+} PCIe_PORT_DATA;
+
+/// DDI channel lane mapping
+typedef struct {                                          ///< Structure that discribe lane mapping
+  IN      UINT8              Lane0   :2;                  /**< Lane 0 mapping
+                                                           *  @li @b 0 - Map to lane 0
+                                                           *  @li @b 1 - Map to lane 1
+                                                           *  @li @b 2 - Map to lane 2
+                                                           *  @li @b 2 - Map to lane 3
+                                                           */
+  IN      UINT8              Lane1   :2;                  ///< Lane 1 mapping (see "Lane 0 mapping")
+  IN      UINT8              Lane2   :2;                  ///< Lane 2 mapping (see "Lane 0 mapping")
+  IN      UINT8              Lane3   :2;                  ///< Lane 3 mapping (see "Lane 0 mapping")
+} CHANNEL_MAPPING;                                        ///< Lane mapping
+
+/// Common Channel Mapping
+typedef union {
+  IN      UINT8                ChannelMappingValue;       ///< Raw lane mapping
+  IN      CHANNEL_MAPPING      ChannelMapping;            ///< Channel mapping
+} CONN_CHANNEL_MAPPING;
+
+/// DDI Configuration data
+typedef struct  {
+  IN       UINT8                ConnectorType;            /**< Display Connector Type
+                                                            *  @li @b 0 - DP
+                                                            *  @li @b 1 - eDP
+                                                            *  @li @b 2 - Single Link DVI-D
+                                                            *  @li @b 3 - Dual  Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description")
+                                                            *  @li @b 4 - HDMI
+                                                            *  @li @b 5 - Travis DP-to-VGA
+                                                            *  @li @b 6 - Travis DP-to-LVDS
+                                                            *  @li @b 7 - Hudson-2 NutMeg DP-to-VGA
+                                                            *  @li @b 8 - Single Link DVI-I
+                                                            *  @li @b 9 - Native CRT (Family 0x14)
+                                                            *  @li @b 10 - Native LVDS (Family 0x14)
+                                                            *  @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS
+                                                            *              The auto detection method only support panel with EDID.
+                                                            */
+  IN       UINT8                AuxIndex;                 /**< Indicates which AUX or DDC Line is used
+                                                            *  @li @b 0 - AUX1
+                                                            *  @li @b 1 - AUX2
+                                                            *  @li @b 2 - AUX3
+                                                            *  @li @b 3 - AUX4
+                                                            *  @li @b 4 - AUX5
+                                                            *  @li @b 5 - AUX6
+                                                            */
+  IN       UINT8                HdpIndex;                 /**< Indicates which HDP pin is used
+                                                            *  @li @b 0 - HDP1
+                                                            *  @li @b 1 - HDP2
+                                                            *  @li @b 2 - HDP3
+                                                            *  @li @b 3 - HDP4
+                                                            *  @li @b 4 - HDP5
+                                                            *  @li @b 5 - HDP6
+                                                            */
+  IN       CONN_CHANNEL_MAPPING Mapping[2];               /**< Set specific mapping of lanes to connector pins
+                                                            *  @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
+                                                            *  @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
+                                                            *  if Mapping[x] set to 0 than default mapping assumed
+                                                            */
+} PCIe_DDI_DATA;
+
+/// Engine Configuration
+typedef struct {
+  IN       UINT8                EngineType;               /**< Engine type
+                                                           *  @li @b 0 -  Ignore engine configuration
+                                                           *  @li @b 1 -  PCIe port
+                                                           *  @li @b 2 -  DDI
+                                                           */
+  IN       UINT16               StartLane;                /**< Start Lane ID (in reversed configuration StartLane > EndLane)
+                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12"
+                                                           * @ref F14PcieLaneDescription "Family 0x14".
+                                                           * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
+                                                           * @ref F14LaneConfigurations "Family 0x14".
+                                                           */
+  IN       UINT16               EndLane;                  /**< End lane ID (in reversed configuration StartLane > EndLane)
+                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12",
+                                                           * @ref F14PcieLaneDescription "Family 0x14".
+                                                           * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
+                                                           * @ref F14LaneConfigurations "Family 0x14".
+                                                           */
+
+} PCIe_ENGINE_DATA;
+
+/// PCIe port descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in complex
+                                                           */
+  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
+  IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
+} PCIe_PORT_DESCRIPTOR;
+
+/// DDI descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in complex
+                                                           */
+  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
+  IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
+} PCIe_DDI_DESCRIPTOR;
+
+/// PCIe Complex descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in topology
+                                                           */
+  IN       UINT32               SocketId;                 ///< Socket Id
+  IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       VOID                 *Reserved;                ///< Reserved for future use
+} PCIe_COMPLEX_DESCRIPTOR;
+
+/// Action to control PCIe slot reset
+typedef enum {
+  AssertSlotReset,                                        ///< Assert slot reset
+  DeassertSlotReset                                       ///< Deassert slot reset
+} PCIE_RESET_CONTROL;
+
+///Slot Reset Info
+typedef struct {
+  IN      AMD_CONFIG_PARAMS     StdHeader;                ///< Standard configuration header
+  IN      UINT8                 ResetId;                  ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+  IN      UINT8                 ResetControl;             ///< Reset control as in PCIE_RESET_CONTROL
+} PCIe_SLOT_RESET_INFO;
+
+/// Engine descriptor type
+typedef enum {
+  PcieUnusedEngine = 0,                                   ///< Unused descriptor
+  PciePortEngine = 1,                                     ///< PCIe port
+  PcieDdiEngine = 2,                                      ///< DDI
+  MaxPcieEngine                                           ///< Max engine type for boundary check.
+} PCIE_ENGINE_TYPE;
+
+/// PCIe link capability/speed
+typedef enum  {
+  PcieGenMaxSupported,                                    ///< Maximum supported
+  PcieGen1 = 1,                                           ///< Gen1
+  PcieGen2,                                               ///< Gen2
+  MaxPcieGen                                              ///< Max Gen for boundary check
+} PCIE_LINK_SPEED_CAP;
+
+/// PCIe PSPP Power policy
+typedef enum  {
+  PsppDisabled,                                           ///< PSPP disabled
+  PsppPerformance = 1,                                    ///< Performance
+  PsppBalanceHigh,                                        ///< Balance-High
+  PsppBalanceLow,                                         ///< Balance-Low
+  PsppPowerSaving,                                        ///< Power Saving
+  MaxPspp                                                 ///< Max Pspp for boundary check
+} PCIE_PSPP_POLICY;
+
+/// DDI display connector type
+typedef enum {
+  ConnectorTypeDP,                                        ///< DP
+  ConnectorTypeEDP,                                       ///< eDP
+  ConnectorTypeSingleLinkDVI,                             ///< Single Link DVI-D
+  ConnectorTypeDualLinkDVI,                               ///< Dual  Link DVI-D
+  ConnectorTypeHDMI,                                      ///< HDMI
+  ConnectorTypeTravisDpToVga,                             ///< Travis DP-to-VGA
+  ConnectorTypeTravisDpToLvds,                            ///< Travis DP-to-LVDS
+  ConnectorTypeNutmegDpToVga,                             ///< Hudson-2 NutMeg DP-to-VGA
+  ConnectorTypeSingleLinkDviI,                            ///< Single Link DVI-I
+  ConnectorTypeCrt,                                       ///< CRT (VGA)
+  ConnectorTypeLvds,                                      ///< LVDS
+  ConnectorTypeAutoDetect,                                ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS)
+  MaxConnectorType                                        ///< Not valid value, used to verify input
+} PCIE_CONNECTOR_TYPE;
+
+/// PCIe link channel type
+typedef enum {
+  ChannelTypeLowLoss,                                     ///< Low Loss
+  ChannelTypeHighLoss,                                    ///< High Loss
+  ChannelTypeMob0db,                                      ///< Mobile 0dB
+  ChannelTypeMob3db,                                      ///< Mobile 3dB
+  ChannelTypeExt6db,                                      ///< Extended 6dB
+  ChannelTypeExt8db,                                      ///< Extended 8dB
+  MaxChannelType                                          ///< Not valid value, used to verify input
+} PCIE_CHANNEL_TYPE;
+
+/// PCIe link ASPM
+typedef enum {
+  AspmDisabled,                                           ///< Disabled
+  AspmL0s,                                                ///< PCIe L0s link state
+  AspmL1,                                                 ///< PCIe L1 link state
+  AspmL0sL1,                                              ///< PCIe L0s & L1 link state
+  MaxAspm                                                 ///< Not valid value, used to verify input
+} PCIE_ASPM_TYPE;
+
+/// PCIe link hotplug support
+typedef enum {
+  HotplugDisabled,                                        ///< Hotplug disable
+  HotplugBasic,                                           ///< Basic Hotplug
+  HotplugServer,                                          ///< Server Hotplug
+  HotplugEnhanced,                                        ///< Enhanced
+  HotplugInboard,                                         ///< Inboard
+  MaxHotplug                                              ///< Not valid value, used to verify input
+} PCIE_HOTPLUG_TYPE;
+
+/// PCIe link initialization
+typedef enum {
+  PortDisabled,                                           ///< Disable
+  PortEnabled                                             ///< Enable
+} PCIE_PORT_ENABLE;
+
+/// DDI Aux channel
+typedef enum {
+  Aux1,                                                   ///< Aux1
+  Aux2,                                                   ///< Aux2
+  Aux3,                                                   ///< Aux3
+  Aux4,                                                   ///< Aux4
+  Aux5,                                                   ///< Aux5
+  Aux6,                                                   ///< Aux6
+  MaxAux                                                  ///< Not valid value, used to verify input
+} PCIE_AUX_TYPE;
+
+/// DDI Hdp Index
+typedef enum {
+  Hdp1,                                                   ///< Hdp1
+  Hdp2,                                                   ///< Hdp2
+  Hdp3,                                                   ///< Hdp3
+  Hdp4,                                                   ///< Hdp4
+  Hdp5,                                                   ///< Hdp5
+  Hdp6,                                                   ///< Hdp6
+  MaxHdp                                                  ///< Not valid value, used to verify input
+} PCIE_HDP_TYPE;
+
+// Macro for statically initialization of various structures
+#define  PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
+#define  PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
+{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} }
+#define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
+{mConnectorType, mAuxIndex, mHpdIndex, {0, 0}}
+#define  PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}}
+
+
+/*----------------------------------------------------------------------------
+ *   GNB configuration info
+ *----------------------------------------------------------------------------
+ */
+/// Configuration settings for GNB.
+typedef struct {
+  IN  UINT8     Gnb3dStereoPinIndex;      ///< 3D Stereo Pin ID.
+                                          ///< @li 0 = Stereo 3D is disabled (default).
+                                          ///< @li 1 = Use processor pin HPD1.
+                                          ///< @li 2 = Use processor pin HPD2
+                                          ///< @li 3 = Use processor pin HPD3
+                                          ///< @li 4 = Use processor pin HPD4
+                                          ///< @li 5 = Use processor pin HPD5
+                                          ///< @li 6 = Use processor pin HPD6
+                                          ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
+  IN  UINT16     LvdsSpreadSpectrum;      ///< Spread spectrum value in 0.01 %
+                                          ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+  IN  UINT16     LvdsSpreadSpectrumRate;  ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+                                          ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+} GNB_ENV_CONFIGURATION;
+
+/// GNB configuration info
+typedef struct {
+  IN       PCIe_COMPLEX_DESCRIPTOR  *PcieComplexList;  /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
+                                                        * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST
+                                                        * Example of topology definition for single socket system:
+                                                        * @code
+                                                        *  PCIe_PORT_DESCRIPTOR PortList [] = {
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    },
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    },
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+                                                        *    {
+                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    }
+                                                        *  };
+                                                        *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+                                                        *    },
+                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
+                                                        *    {
+                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+                                                        *    }
+                                                        *  };
+                                                        * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
+                                                        *   DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate complexes list
+                                                        *   0,  //Socket ID
+                                                        *   &PortList[0],
+                                                        *   &DdiList[0],
+                                                        * }
+                                                        * @endcode
+                                                        */
+  IN       UINT8                    PsppPolicy;         /**< PSPP (PCIe Speed Power Policy)
+                                                         *  @li @b 0 - Disabled
+                                                         *  @li @b 1 - Performance
+                                                         *  @li @b 2 - Balance-High
+                                                         *  @li @b 3 - Balance-Low
+                                                         *  @li @b 4 - Power Saving
+                                                         */
+
+} GNB_CONFIGURATION;
+//
+//  MEMORY-SPECIFIC DATA STRUCTURES
+//
+//
+//
+//
+// AGESA MAXIMIUM VALUES
+//
+//   These Max values are used to define array sizes and associated loop
+//   counts in the code.  They reflect the maximum values that AGESA
+//   currently supports and does not necessarily reflect the hardware
+//   capabilities of configuration.
+//
+
+#define MAX_SOCKETS_SUPPORTED   8   ///< Max number of sockets in system
+#define MAX_CHANNELS_PER_SOCKET 4   ///< Max Channels per sockets
+#define MAX_DIMMS_PER_CHANNEL   4   ///< Max DIMMs on a memory channel (independent of platform)
+#define NUMBER_OF_DELAY_TABLES  9   ///< Number of tables defined in CH_DEF_STRUCT.
+                                    ///< Eg: UINT16  *RcvEnDlys;
+                                    ///<     UINT8   *WrDqsDlys;
+                                    ///<     UINT8   *RdDqsDlys;
+                                    ///<     UINT8   *WrDatDlys;
+                                    ///<     UINT8   *RdDqsMinDlys;
+                                    ///<     UINT8   *RdDqsMaxDlys;
+                                    ///<     UINT8   *WrDatMinDlys;
+                                    ///<     UINT8   *WrDatMaxDlys;
+#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
+
+#define MAX_PLATFORM_TYPES     16   ///< Platform types per system
+
+#define MCT_TRNG_KEEPOUT_START  0x00004000    ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_END    0x00007FFF    ///< base [39:8]
+
+#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000   ///< Uma Region is interleaved
+#define UMA_ATTRIBUTE_ON_DCT0    0x40000000   ///< UMA resides on memory that belongs to DCT0
+#define UMA_ATTRIBUTE_ON_DCT1    0x20000000   ///< UMA resides on memory that belongs to DCT1
+
+typedef UINT8 PSO_TABLE;            ///< Platform Configuration Table
+
+//        AGESA DEFINITIONS
+//
+//        Many of these are derived from the platform and hardware specific definitions
+
+/// EccSymbolSize override value
+#define ECCSYMBOLSIZE_USE_BKDG      0   ///< Use BKDG Recommended Value
+#define ECCSYMBOLSIZE_FORCE_X4      4   ///< Force to x4
+#define ECCSYMBOLSIZE_FORCE_X8      8   ///< Force to x8
+/// CPU Package Type
+#define PT_L1       0                 ///< L1 Package type
+#define PT_M2       1                 ///< AM Package type
+#define PT_S1       2                 ///< S1 Package type
+
+/// Structures use to pass system Logical CPU-ID
+typedef struct {
+  IN OUT   UINT64 Family;             ///< Indicates logical ID Family
+  IN OUT   UINT64 Revision;           ///< Indicates logical ID Family
+} CPU_LOGICAL_ID;
+
+/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+typedef enum {
+  AMD_PLATFORM_SERVER = 0x8000,     ///< Server
+  AMD_PLATFORM_DESKTOP = 0x10000,   ///< Desktop
+  AMD_PLATFORM_MOBILE = 0x20000,    ///< Mobile
+} AMD_PLATFORM_TYPE;
+
+/// Dram technology type
+typedef enum {
+  DDR2_TECHNOLOGY,      ///< DDR2 technology
+  DDR3_TECHNOLOGY       ///< DDR3 technology
+} TECHNOLOGY_TYPE;
+
+/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+typedef enum {
+  DDR400_FREQUENCY = 200,     ///< DDR 400
+  DDR533_FREQUENCY = 266,     ///< DDR 533
+  DDR667_FREQUENCY = 333,     ///< DDR 667
+  DDR800_FREQUENCY = 400,     ///< DDR 800
+  DDR1066_FREQUENCY = 533,    ///< DDR 1066
+  DDR1333_FREQUENCY = 667,    ///< DDR 1333
+  DDR1600_FREQUENCY = 800,    ///< DDR 1600
+  DDR1866_FREQUENCY = 933,    ///< DDR 1866
+  UNSUPPORTED_DDR_FREQUENCY   ///< Highest limit of DDR frequency
+} MEMORY_BUS_SPEED;
+
+/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+typedef enum {
+  QUADRANK_REGISTERED,        ///< Quadrank registered DIMM
+  QUADRANK_UNBUFFERED         ///< Quadrank unbuffered DIMM
+} QUANDRANK_TYPE;
+
+/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+typedef enum {
+  TIMING_MODE_AUTO,           ///< Use best rate possible
+  TIMING_MODE_LIMITED,        ///< Set user top limit
+  TIMING_MODE_SPECIFIC        ///< Set user specified speed
+} USER_MEMORY_TIMING_MODE;
+
+/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
+typedef enum {
+  POWER_DOWN_BY_CHANNEL,      ///< Channel power down mode
+  POWER_DOWN_BY_CHIP_SELECT,  ///< Chip select power down mode
+  POWER_DOWN_MODE_AUTO        ///< AGESA to select power down mode
+} POWER_DOWN_MODE;
+
+/// Low voltage support
+typedef enum {
+  VOLT1_5,                   ///< 1.5 Volt
+  VOLT1_35,                  ///< 1.35 Volt
+  VOLT1_25,                  ///< 1.25 Volt
+  VOLT_UNSUPPORTED = 0xFF    ///< No common voltage found
+} DIMM_VOLTAGE;
+
+/// UMA Mode
+typedef enum {
+  UMA_NONE = 0,              ///< UMA None
+  UMA_SPECIFIED = 1,         ///< UMA Specified
+  UMA_AUTO = 2               ///< UMA Auto
+} UMA_MODE;
+
+/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
+typedef enum {
+  NO_UMA_ALIGNED = 0x00FFFFFF,           ///< NO UMA aligned
+  UMA_128MB_ALIGNED = 0x00FFF800,        ///< UMA 128MB aligned
+  UMA_256MB_ALIGNED = 0x00FFF000,        ///< UMA 256MB aligned
+  UMA_512MB_ALIGNED = 0x00FFE000,        ///< UMA 512MB aligned
+} UMA_ALIGNMENT;
+
+///
+///   Global MCT Configuration Status Word (GStatus)
+///
+typedef enum {
+  GsbMTRRshort,              ///< Ran out of MTRRs while mapping memory
+  GsbAllECCDimms,            ///< All banks of all Nodes are ECC capable
+  GsbDramECCDis,             ///< Dram ECC requested but not enabled.
+  GsbSoftHole,               ///< A Node Base gap was created
+  GsbHWHole,                 ///< A HW dram remap was created
+  GsbNodeIntlv,              ///< Node Memory interleaving was enabled
+  GsbSpIntRemapHole,         ///< Special condition for Node Interleave and HW remapping
+  GsbEnDIMMSpareNW,          ///< Indicates that DIMM Spare can be used without a warm reset
+
+  GsbEOL                     ///< End of list
+} GLOBAL_STATUS_FIELD;
+
+///
+///   Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+///
+typedef enum {
+  EsbNoDimms,                  ///< No DIMMs
+  EsbSpdChkSum,                ///< SPD Checksum fail
+  EsbDimmMismatchM,            ///< dimm module type(buffer) mismatch
+  EsbDimmMismatchT,            ///< dimm CL/T mismatch
+  EsbDimmMismatchO,            ///< dimm organization mismatch (128-bit)
+  EsbNoTrcTrfc,                ///< SPD missing Trc or Trfc info
+  EsbNoCycTime,                ///< SPD missing byte 23 or 25
+  EsbBkIntDis,                 ///< Bank interleave requested but not enabled
+  EsbDramECCDis,               ///< Dram ECC requested but not enabled
+  EsbSpareDis,                 ///< Online spare requested but not enabled
+  EsbMinimumMode,              ///< Running in Minimum Mode
+  EsbNoRcvrEn,                 ///< No DQS Receiver Enable pass window found
+  EsbSmallRcvr,                ///< DQS Rcvr En pass window too small (far right of dynamic range)
+  EsbNoDqsPos,                 ///< No DQS-DQ passing positions
+  EsbSmallDqs,                 ///< DQS-DQ passing window too small
+  EsbDCBKScrubDis,             ///< DCache scrub requested but not enabled
+
+  EsbEMPNotSupported,          ///< Processor is not capable for EMP.
+  EsbEMPConflict,               ///< EMP requested but cannot be enabled since
+                               ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
+  EsbEMPDis,                   ///< EMP requested but cannot be enabled since
+                               ///< memory size of each DCT is not a power of two.
+
+  EsbEOL                       ///< End of list
+} ERROR_STATUS_FIELD;
+
+///
+///  Local Configuration Status (DIE_STRUCT.Status[31:0])
+///
+typedef enum {
+  SbRegistered,                ///< All DIMMs are Registered
+  SbEccDimms,                  ///< All banks ECC capable
+  SbParDimms,                  ///< All banks Addr/CMD Parity capable
+  SbDiagClks,                  ///< Jedec ALL slots clock enable diag mode
+  Sb128bitmode,                ///< DCT in 128-bit mode operation
+  Sb64MuxedMode,               ///< DCT in 64-bit mux'ed mode.
+  Sb2TMode,                    ///< 2T CMD timing mode is enabled.
+  SbSWNodeHole,                ///< Remapping of Node Base on this Node to create a gap.
+  SbHWHole,                    ///< Memory Hole created on this Node using HW remapping.
+  SbOver400Mhz,                ///< DCT freq greater than or equal to 400MHz flag
+  SbDQSPosPass2,               ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+  SbDQSRcvLimit,               ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
+  SbExtConfig,                 ///< Indicate the default setting for extended PCI configuration support
+  SbLrdimms,                   ///< All DIMMs are LRDIMMs
+
+  SbEOL                        ///< End of list
+} LOCAL_STATUS_FIELD;
+
+
+///< CPU MSR Register definitions ------------------------------------------
+#define SYS_CFG     0xC0010010
+#define TOP_MEM     0xC001001A
+#define TOP_MEM2    0xC001001D
+#define HWCR        0xC0010015
+#define NB_CFG      0xC001001F
+
+#define FS_BASE     0xC0000100
+#define IORR0_BASE  0xC0010016
+#define IORR0_MASK  0xC0010017
+#define BU_CFG      0xC0011023
+#define BU_CFG2     0xC001102A
+#define COFVID_STAT 0xC0010071
+#define TSC         0x10
+
+//-----------------------------------------------------------------------------
+///
+/// SPD Data for each DIMM.
+///
+typedef struct _SPD_DEF_STRUCT {
+  IN BOOLEAN DimmPresent;       ///< Indicates that the DIMM is present and Data is valid
+  IN UINT8 Data[256];           ///< Buffer for 256 Bytes of SPD data from DIMM
+} SPD_DEF_STRUCT;
+
+///
+/// Channel Definition Structure.
+/// This data structure defines entries that are specific to the channel initialization
+///
+typedef struct _CH_DEF_STRUCT {
+  OUT UINT8   ChannelID;         ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+  OUT TECHNOLOGY_TYPE TechType;  ///< Technology type of this channel
+  OUT UINT8   ChDimmPresent;     ///< For each bit n 0..7, 1 = DIMM n is present.
+                                 ///<  DIMM#  Select Signal
+                                 ///<  0      MA0_CS_L[0, 1]
+                                 ///<  1      MB0_CS_L[0, 1]
+                                 ///<  2      MA1_CS_L[0, 1]
+                                 ///<  3      MB1_CS_L[0, 1]
+                                 ///<  4      MA2_CS_L[0, 1]
+                                 ///<  5      MB2_CS_L[0, 1]
+                                 ///<  6      MA3_CS_L[0, 1]
+                                 ///<  7      MB3_CS_L[0, 1]
+
+  OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
+  OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
+  OUT SPD_DEF_STRUCT *SpdPtr;    ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
+  OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
+                                 ///<   SPD Data for each Dimm. (Setup by Tech Block Constructor)
+  OUT UINT8   ChDimmValid;       ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
+                                 ///<
+  OUT UINT8   RegDimmPresent;    ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
+  OUT UINT8   LrDimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
+  OUT UINT8   SODimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
+  OUT UINT8   Loads;             ///< Number of devices loading bus
+  OUT UINT8   Dimms;             ///< Number of DIMMs loading Channel
+  OUT UINT8   Ranks;             ///< Number of ranks loading Channel DATA
+  OUT BOOLEAN SlowMode;          ///< 1T or 2T CMD mode (slow access mode)
+                                 ///< FALSE = 1T
+                                 ///< TRUE = 2T
+  ///< The following pointers will be pointed to dynamically allocated buffers.
+  ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+  ///< Example: If DIMM and Byte based training, then
+  ///< XX is a value in Hex
+  ///<                        BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+  ///<  Row1 -  Logical DIMM0    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  ///<  Row2 -  Logical DIMM1    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  OUT UINT16  *RcvEnDlys;       ///< DQS Receiver Enable Delays
+  OUT UINT8   *WrDqsDlys;       ///< Write DQS delays (only valid for DDR3)
+  OUT UINT8   *RdDqsDlys;       ///< Read Dqs delays
+  OUT UINT8   *WrDatDlys;       ///< Write Data delays
+  OUT UINT8   *RdDqsMinDlys;    ///< Minimum Window for Read DQS
+  OUT UINT8   *RdDqsMaxDlys;    ///< Maximum Window for Read DQS
+  OUT UINT8   *WrDatMinDlys;    ///< Minimum Window for Write data
+  OUT UINT8   *WrDatMaxDlys;    ///< Maximum Window for Write data
+  OUT UINT8   RowCount;         ///< Number of rows of the allocated buffer.
+  OUT UINT8   ColumnCount;      ///< Number of columns of the allocated buffer.
+  OUT UINT8   *FailingBitMask;    ///< Table of masks to Track Failing bits
+  OUT UINT32  DctOdcCtl;          ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+  OUT UINT32  DctAddrTmg;         ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+  OUT UINT32  PhyRODTCSLow;       ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
+  OUT UINT32  PhyRODTCSHigh;      ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
+  OUT UINT32  PhyWODTCSLow;       ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
+  OUT UINT32  PhyWODTCSHigh;      ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
+  OUT UINT8   PhyWLODT[4];        ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+  OUT UINT16  DctEccDqsLike;      ///< DCT DQS ECC UINT8 like...
+  OUT UINT8   DctEccDqsScale;     ///< DCT DQS ECC UINT8 scale
+  OUT UINT16  PtrPatternBufA;     ///< Ptr on stack to aligned DQS testing pattern
+  OUT UINT16  PtrPatternBufB;     ///< Ptr on stack to aligned DQS testing pattern
+  OUT UINT8   ByteLane;           ///< Current UINT8 Lane (0..7)
+  OUT UINT8   Direction;          ///< Current DQS-DQ training write direction (0=read, 1=write)
+  OUT UINT8   Pattern;            ///< Current pattern
+  OUT UINT8   DqsDelay;           ///< Current DQS delay value
+  OUT UINT16  HostBiosSrvc1;      ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+  OUT UINT32  HostBiosSrvc2;      ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+  OUT UINT16  DctMaxRdLat;        ///< Max Read Latency (ns) for the DCT
+  OUT UINT8   DIMMValidCh;        ///< DIMM# in CH
+  OUT UINT8   MaxCh;              ///< Max number of CH in system
+  OUT UINT8   Dct;                ///< Dct pointer
+  OUT UINT8   WrDatGrossH;        ///< Write Data Gross delay high value
+  OUT UINT8   DqsRcvEnGrossL;     ///< DQS Receive Enable Gross Delay low
+
+  OUT UINT8   TrwtWB;             ///<  Non-SPD timing value for TrwtWB
+  OUT UINT8   CurrRcvrDctADelay;  ///< for keep current RcvrEnDly
+  OUT UINT16  T1000;              ///< get the T1000 figure (cycle time (ns) * 1K)
+  OUT UINT8   DqsRcvEnPass;       ///< for TrainRcvrEn UINT8 lane pass flag
+  OUT UINT8   DqsRcvEnSaved;      ///< for TrainRcvrEn UINT8 lane saved flag
+  OUT UINT8   SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
+
+  OUT UINT8   ClToNbFlag;         ///< is used to restore ClLinesToNbDis bit after memory
+  OUT UINT32  NodeSysBase;        ///< for channel interleave usage
+  OUT UINT8   RefRawCard[MAX_DIMMS_PER_CHANNEL];   ///< Array of rawcards detected
+  OUT UINT8   CtrlWrd02[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 2 values per DIMM
+  OUT UINT8   CtrlWrd03[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 3 values per DIMM
+  OUT UINT8   CtrlWrd04[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 4 values per DIMM
+  OUT UINT8   CtrlWrd05[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 5 values per DIMM
+  OUT UINT8   CtrlWrd08[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 8 values per DIMM
+
+  OUT UINT16  CsPresentDCT;       ///< For each bit n 0..7, 1 = Chip-select n is present
+  OUT UINT8   DimmMirrorPresent;  ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
+  OUT UINT8   DimmSpdCse;         ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
+  OUT UINT8   DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+  OUT UINT8   DimmYr06;           ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+  OUT UINT8   DimmWk2406;         ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+  OUT UINT8   DimmPlPresent;      ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+  OUT UINT8   DimmQrPresent;      ///< QuadRank DIMM present?
+  OUT UINT8   DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present
+  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present
+  OUT UINT8   Dimmx4Present;      ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
+  OUT UINT8   Dimmx8Present;      ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
+  OUT UINT8   Dimmx16Present;     ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
+  OUT UINT8   LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
+  OUT UINT8   LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
+  OUT UINT8   LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
+
+  OUT UINT8   *MemClkDisMap;      ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+                                  ///<  base on this array to disable unused MemClk to save power.
+                                  ///<
+                                  ///<  The array must have 8 entries. Each entry, which associates with
+                                  ///<  one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+                                  ///<    Example:
+                                  ///<    BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
+                                  ///<    is like below:
+                                  ///<         Bit AM3/S1g3 pin name
+                                  ///<         0   M[B,A]_CLK_H/L[0]
+                                  ///<         1   M[B,A]_CLK_H/L[1]
+                                  ///<         2   M[B,A]_CLK_H/L[2]
+                                  ///<         3   M[B,A]_CLK_H/L[3]
+                                  ///<         4   M[B,A]_CLK_H/L[4]
+                                  ///<         5   M[B,A]_CLK_H/L[5]
+                                  ///<         6   M[B,A]_CLK_H/L[6]
+                                  ///<         7   M[B,A]_CLK_H/L[7]
+                                  ///<    And platform has the following routing:
+                                  ///<         CS0   M[B,A]_CLK_H/L[4]
+                                  ///<         CS1   M[B,A]_CLK_H/L[2]
+                                  ///<         CS2   M[B,A]_CLK_H/L[3]
+                                  ///<         CS3   M[B,A]_CLK_H/L[5]
+                                  ///<    Then MemClkDisMap should be pointed to the following array:
+                                  ///<               CLK_2 CLK_3 CLK_4 CLK_5
+                                  ///<    0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
+                                  ///<  Each entry of the array is the bitmask of 8 chip selects.
+
+  OUT UINT8   *CKETriMap;         ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of CKE pins to the DIMMs' ranks.
+                                  ///<  The array must have 2 entries. Each entry, which associates with
+                                  ///<  one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+                                  ///<  AGESA will base on this array to disable unused CKE pins to save power.
+
+  OUT UINT8   *ODTTriMap;         ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of ODT pins to the DIMMs' ranks.
+                                  ///<  The array must have 4 entries. Each entry, which associates with
+                                  ///<  one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+                                  ///<  AGESA will base on this array to disable unused ODT pins to save power.
+
+  OUT UINT8   *ChipSelTriMap;     ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of chip select pins to the DIMMs' ranks.
+                                  ///<  The array must have 8 entries. Each entry is a bitmap of 8 CS.
+                                  ///<  AGESA will base on this array to disable unused Chip select pins to save power.
+
+  OUT BOOLEAN   ExtendTmp;        ///<  If extended temperature is supported on all dimms on a channel.
+
+  OUT UINT8   Reserved[100];      ///< Reserved
+} CH_DEF_STRUCT;
+
+///
+/// DCT Channel Timing Parameters.
+/// This data structure sets timings that are specific to the channel.
+///
+typedef struct _CH_TIMING_STRUCT {
+  OUT UINT16  DctDimmValid;       ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
+  OUT UINT16  DimmMirrorPresent;  ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
+  OUT UINT16  DimmSpdCse;         ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
+  OUT UINT16  DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+  OUT UINT16  CsPresent;          ///< For each bit n 0..7, 1=Chip-select n is present
+  OUT UINT16  CsEnabled;          ///< For each bit n 0..7, 1=Chip-select n is enabled
+  OUT UINT16  CsTestFail;         ///< For each bit n 0..7, 1=Chip-select n is present but disabled
+  OUT UINT16  CsTrainFail;        ///< Bitmap showing which chipselects failed training
+  OUT UINT16  DIMM1KPage;         ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
+  OUT UINT16  DimmQrPresent;      ///< QuadRank DIMM present?
+  OUT UINT16  DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
+  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
+  OUT UINT16  Dimmx4Present;      ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
+  OUT UINT16  Dimmx8Present;      ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
+  OUT UINT16  Dimmx16Present;     ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
+
+  OUT UINT16  DIMMTrcd;           ///< Minimax Trcd*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrp;            ///< Minimax Trp*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrtp;           ///< Minimax Trtp*40 (ns) of DIMMs
+  OUT UINT16  DIMMTras;           ///< Minimax Tras*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrc;            ///< Minimax Trc*40 (ns) of DIMMs
+  OUT UINT16  DIMMTwr;            ///< Minimax Twr*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrrd;           ///< Minimax Trrd*40 (ns) of DIMMs
+  OUT UINT16  DIMMTwtr;           ///< Minimax Twtr*40 (ns) of DIMMs
+  OUT UINT16  DIMMTfaw;           ///< Minimax Tfaw*40 (ns) of DIMMs
+  OUT UINT16  TargetSpeed;        ///< Target DRAM bus speed in MHz
+  OUT UINT16  Speed;              ///< DRAM bus speed in MHz
+                                  ///<  400 (MHz)
+                                  ///<  533 (MHz)
+                                  ///<  667 (MHz)
+                                  ///<  800 (MHz)
+                                  ///<  and so on...
+  OUT UINT8   CasL;               ///< CAS latency DCT setting (busclocks)
+  OUT UINT8   Trcd;               ///< DCT Trcd (busclocks)
+  OUT UINT8   Trp;                ///< DCT Trp (busclocks)
+  OUT UINT8   Trtp;               ///< DCT Trtp (busclocks)
+  OUT UINT8   Tras;               ///< DCT Tras (busclocks)
+  OUT UINT8   Trc;                ///< DCT Trc (busclocks)
+  OUT UINT8   Twr;                ///< DCT Twr (busclocks)
+  OUT UINT8   Trrd;               ///< DCT Trrd (busclocks)
+  OUT UINT8   Twtr;               ///< DCT Twtr (busclocks)
+  OUT UINT8   Tfaw;               ///< DCT Tfaw (busclocks)
+  OUT UINT8   Trfc0;              ///< DCT Logical DIMM0 Trfc
+                                  ///<  0 = 75ns (for 256Mb devs)
+                                  ///<  1 = 105ns (for 512Mb devs)
+                                  ///<  2 = 127.5ns (for 1Gb devs)
+                                  ///<  3 = 195ns (for 2Gb devs)
+                                  ///<  4 = 327.5ns (for 4Gb devs)
+  OUT UINT8   Trfc1;              ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
+  OUT UINT8   Trfc2;              ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
+  OUT UINT8   Trfc3;              ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
+  OUT UINT32  DctMemSize;         ///< Base[47:16], total DRAM size controlled by this DCT.
+                                  ///<
+  OUT BOOLEAN SlowMode;           ///< 1T or 2T CMD mode (slow access mode)
+                                  ///< FALSE = 1T
+                                  ///< TRUE = 2T
+  OUT UINT8   TrwtTO;             ///< DCT TrwtTO (busclocks)
+  OUT UINT8   Twrrd;              ///< DCT Twrrd (busclocks)
+  OUT UINT8   Twrwr;              ///< DCT Twrwr (busclocks)
+  OUT UINT8   Trdrd;              ///< DCT Trdrd (busclocks)
+  OUT UINT8   TrwtWB;             ///< DCT TrwtWB (busclocks)
+  OUT UINT8   TrdrdSD;            ///< DCT TrdrdSD (busclocks)
+  OUT UINT8   TwrwrSD;            ///< DCT TwrwrSD (busclocks)
+  OUT UINT8   TwrrdSD;            ///< DCT TwrrdSD (busclocks)
+  OUT UINT16  MaxRdLat;           ///< Max Read Latency
+  OUT UINT8   WrDatGrossH;        ///< Temporary variables must be removed
+  OUT UINT8   DqsRcvEnGrossL;     ///< Temporary variables must be removed
+} CH_TIMING_STRUCT;
+
+///
+/// Data for each DCT.
+/// This data structure defines data used to configure each DRAM controller.
+///
+typedef struct _DCT_STRUCT {
+  OUT UINT8   Dct;                ///< Current Dct
+  OUT CH_TIMING_STRUCT Timings;   ///< Channel Timing structure
+  OUT CH_DEF_STRUCT    *ChData;   ///< Pointed to a dynamically allocated array of Channel structures
+  OUT UINT8   ChannelCount;       ///< Number of channel per this DCT
+} DCT_STRUCT;
+
+
+///
+/// Data Structure defining each Die.
+/// This data structure contains information that is used to configure each Die.
+///
+typedef struct _DIE_STRUCT {
+
+  /// Advanced:
+
+  OUT UINT8   NodeId;              ///< Node ID of current controller
+  OUT UINT8   SocketId;            ///< Socket ID of this Die
+  OUT UINT8   DieId;               ///< ID of this die relative to the socket
+  OUT PCI_ADDR      PciAddr;       ///< Pci bus and device number of this controller.
+  OUT AGESA_STATUS  ErrCode;       ///< Current error condition of Node
+                                   ///<  0x0 = AGESA_SUCCESS
+                                   ///<  0x1 = AGESA_UNSUPPORTED
+                                   ///<  0x2 = AGESA_BOUNDS_CHK
+                                   ///<  0x3 = AGESA_ALERT
+                                   ///<  0x4 = AGESA_WARNING
+                                   ///<  0x5 = AGESA_ERROR
+                                   ///<  0x6 = AGESA_CRITICAL
+                                   ///<  0x7 = AGESA_FATAL
+                                   ///<
+  OUT BOOLEAN ErrStatus[EsbEOL];   ///< Error Status bit Field
+                                   ///<
+  OUT BOOLEAN Status[SbEOL];       ///< Status bit Field
+                                   ///<
+  OUT UINT32  NodeMemSize;         ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+                                   ///<
+  OUT UINT32  NodeSysBase;         ///< Base[47:16] (system address) DRAM base address of this Node.
+                                   ///<
+  OUT UINT32  NodeHoleBase;        ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping.  Dram hole exists on this Node
+                                   ///<
+  OUT UINT32  NodeSysLimit;        ///< Base[47:16] (system address) DRAM limit address of this Node.
+                                   ///<
+  OUT UINT32  DimmPresent;         ///< For each bit n 0..7, 1 = DIMM n is present.
+                                   ///<   DIMM#  Select Signal
+                                   ///<   0      MA0_CS_L[0, 1]
+                                   ///<   1      MB0_CS_L[0, 1]
+                                   ///<   2      MA1_CS_L[0, 1]
+                                   ///<   3      MB1_CS_L[0, 1]
+                                   ///<   4      MA2_CS_L[0, 1]
+                                   ///<   5      MB2_CS_L[0, 1]
+                                   ///<   6      MA3_CS_L[0, 1]
+                                   ///<   7      MB3_CS_L[0, 1]
+                                   ///<
+  OUT UINT32  DimmValid;           ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+  OUT UINT32  RegDimmPresent;      ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
+  OUT UINT32  LrDimmPresent;       ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
+  OUT UINT32  DimmEccPresent;      ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
+  OUT UINT32  DimmParPresent;      ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+                                   ///<
+  OUT UINT16  DimmTrainFail;       ///< Bitmap showing which dimms failed training
+  OUT UINT16  ChannelTrainFail;    ///< Bitmap showing the channel information about failed Chip Selects
+                                   ///<  0 in any bit field indicates Channel 0
+                                   ///<  1 in any bit field indicates Channel 1
+  OUT UINT8   Dct;                 ///<  Need to be removed
+                                   ///<  DCT pointer
+  OUT BOOLEAN GangedMode;          ///< Ganged mode
+                                   ///<  0 = disabled
+                                   ///<  1 = enabled
+  OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
+                                   ///<
+  OUT UINT16  HostBiosSrvc1;       ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+                                   ///<
+  OUT UINT32  HostBiosSrvc2;       ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+                                   ///<
+  OUT UINT8   MLoad;               ///< Need to be removed
+                                   ///< Number of devices loading MAA bus
+                                   ///<
+  OUT UINT8   MaxAsyncLat;         ///< Legacy wrapper
+                                   ///<
+  OUT UINT8   ChbD3Rcvrdly;        ///< Legacy wrapper
+                                   ///<
+  OUT UINT16  ChaMaxRdLat;         ///< Max Read Latency (ns) for DCT 0
+                                   ///<
+  OUT UINT8   ChbD3BcRcvrdly;      ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+  OUT DCT_STRUCT *DctData;         ///< Pointed to a dynamically allocated array of DCT_STRUCTs
+  OUT UINT8   DctCount;            ///< Number of DCTs per this Die
+  OUT UINT8   Reserved[16];        ///< Reserved
+} DIE_STRUCT;
+
+/**********************************************************************
+ * S3 Support structure
+ **********************************************************************/
+/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
+typedef struct {
+     OUT   UINT32 Signature;           ///< "ASTR" for AMD Suspend-To-RAM
+     OUT   UINT16 Version;             ///< S3 Params version number
+  IN OUT   UINT32 Flags;               ///< Indicates operation
+  IN OUT   VOID   *NvStorage;          ///< Pointer to memory critical save state data
+  IN OUT   UINT32 NvStorageSize;       ///< Size in bytes of the NvStorage region
+  IN OUT   VOID   *VolatileStorage;    ///< Pointer to remaining AMD save state data
+  IN OUT   UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
+} AMD_S3_PARAMS;
+
+///===============================================================================
+/// MEM_PARAMETER_STRUCT
+/// This data structure is used to pass wrapper parameters to the memory configuration code
+///
+typedef struct _MEM_PARAMETER_STRUCT {
+
+  // Basic (Return parameters)
+  // (This section contains the outbound parameters from the memory init code)
+
+  OUT BOOLEAN GStatus[GsbEOL];    ///< Global Status bitfield.
+                                  ///<
+  OUT UINT32 HoleBase;            ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+                                  ///<
+  OUT UINT32 Sub4GCacheTop;       ///< If not zero, the 32-bit top of cacheable memory.
+                                  ///<
+  OUT UINT32 SysLimit;            ///< Limit[47:16] (system address).
+                                  ///<
+
+  OUT DIMM_VOLTAGE DDR3Voltage;   ///< Find support voltage and send back to platform BIOS.
+                                  ///< 0 = 1.5v
+                                  ///< 1 = 1.35v
+                                  ///< 2 = 1.2v
+                                  ///< 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded
+                                  ///<        from the system.
+                                  ///<
+
+  OUT struct _MEM_DATA_STRUCT *MemData;   ///< Access to global memory init data.
+
+  //  Advanced (Optional parameters)
+  //  Optional (all defaults values will be initialized by the
+  //  'AmdMemInitDataStructDef' based on AMD defaults. It is up
+  //  to the IBV/OEM to change the defaults after initialization
+  //  but prior to the main entry to the memory code):
+
+  // Memory Map/Mgt.
+
+  IN UINT16  BottomIo;             ///< Bottom of 32-bit IO space (8-bits).
+                                   ///<   NV_BOTTOM_IO[7:0]=Addr[31:24]
+                                   ///<
+  IN BOOLEAN MemHoleRemapping;     ///< Memory Hole Remapping (1-bit).
+                                   ///<  FALSE = disable
+                                   ///<  TRUE  = enable
+
+
+  // Dram Timing
+
+  IN USER_MEMORY_TIMING_MODE   UserTimingMode;  ///< User Memclock Mode.
+                                                ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
+
+  IN MEMORY_BUS_SPEED          MemClockValue;   ///< Memory Clock Value.
+                                                ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
+
+
+  // Dram Configuration
+
+  IN BOOLEAN EnableBankIntlv;      ///< Dram Bank (chip-select) Interleaving (1-bit).
+                                   ///<  - FALSE =disable (default)
+                                   ///<  - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
+
+  IN BOOLEAN EnableNodeIntlv;      ///< Node Memory Interleaving (1-bit).
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
+
+  IN BOOLEAN EnableChannelIntlv;   ///< Channel Interleaving (1-bit).
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
+  // ECC
+
+  IN BOOLEAN EnableEccFeature;     ///< enable ECC error to go into MCE.
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
+  // Dram Power
+
+  IN BOOLEAN EnablePowerDown;      ///< CKE based power down mode (1-bit).
+                                   ///<   - FALSE =disable (default)
+                                   ///<   - TRUE =enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
+
+  // Online Spare
+
+  IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
+                                   ///<  - FALSE = disable Spare (default)
+                                   ///<  - TRUE = enable Spare
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
+
+  IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
+
+  IN PSO_TABLE *PlatformMemoryConfiguration;
+                                   ///< A table that contains platform specific settings.
+                                   ///< For example, MemClk routing, the number of DIMM slots per channel, ....
+                                   ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+                                   ///< contains default conservative settings. Platform BIOS can either tweak
+                                   ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+                                   ///<
+  IN BOOLEAN EnableParity;         ///< Parity control.
+                                   ///<  - TRUE = enable
+                                   ///<  - FALSE = disable (default)
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
+
+  IN BOOLEAN EnableBankSwizzle;    ///< BankSwizzle control.
+                                   ///<  - FALSE = disable
+                                   ///<  - TRUE = enable  (default)
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
+
+                                   ///<
+
+  IN BOOLEAN EnableMemClr;         ///< Memory Clear functionality control.
+                                   ///<  - FALSE = disable
+                                   ///<  - TRUE = enable  (default)
+                                   ///<
+
+  // Uma Configuration
+
+  IN UMA_MODE UmaMode;             ///<  Uma Mode
+                                   ///<  0 = None
+                                   ///<  1 = Specified
+                                   ///<  2 = Auto
+  IN OUT UINT32 UmaSize;           ///<  The size of shared graphics dram (16-bits)
+                                   ///<  NV_UMA_Size[31:0]=Addr[47:16]
+                                   ///<
+  OUT UINT32 UmaBase;              ///<  The allocated Uma base address (32-bits)
+                                   ///<  NV_UMA_Base[31:0]=Addr[47:16]
+                                   ///<
+
+  /// Memory Restore Feature
+
+  IN BOOLEAN MemRestoreCtl;        ///< Memory context restore control
+                                   ///<   FALSE = perform memory init as normal (AMD default)
+                                   ///<   TRUE = restore memory context and skip training. This requires
+                                   ///<          MemContext is valid before AmdInitPost
+                                   ///<
+  IN BOOLEAN SaveMemContextCtl;    ///< Control switch to save memory context at the end of MemAuto
+                                   ///<   TRUE = AGESA will setup MemContext block before exit AmdInitPost
+                                   ///<   FALSE = AGESA will not setup MemContext block. Platform is
+                                   ///<           expected to call S3Save later in POST if it wants to
+                                   ///<           use memory context restore feature.
+                                   ///<
+  IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
+                                   ///< save and restore for memory context restore feature to work.
+                                   ///< It uses the subset of S3Save block to save/restore. Hence platform
+                                   ///< may save only S3 block and uses it for both S3 resume and
+                                   ///< memory context restore.
+                                   ///<  - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+                                   ///<    before AmdInitPost.
+                                   ///<  - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+                                   ///<    right after AmdInitPost.
+                                   ///<
+} MEM_PARAMETER_STRUCT;
+
+
+///
+/// Function definition.
+/// This data structure passes function pointers to the memory configuration code.
+/// The wrapper can use this structure with customized versions.
+///
+typedef struct _MEM_FUNCTION_STRUCT {
+
+  // PUBLIC required Internal functions
+
+  IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData);  ///< Proc for Unbuffered DIMMs, platform specific
+  IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData);   ///< Proc for Registered DIMMs, platform specific
+
+  // PUBLIC optional functions
+
+  IN OUT VOID (*amdMemEccInit) (VOID *pMemData);                  ///< NB proc for ECC feature
+  IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
+  IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData);      ///< NB proc for Channel interleave feature
+  IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData);      ///< NB proc for Node interleave feature
+  IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData);         ///< NB proc for parallel training feature
+  IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData);       ///< NB code for early sample support feature
+  IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData);     ///< NB code for 'multi-part'
+  IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData);       ///< NB code for On-Line Spare feature
+  IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData);                ///< NB code for UDIMMs
+  IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData);                ///< NB code for RDIMMs
+  IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData);                ///< NB code for LRDIMMs
+
+  IN OUT UINT32   Reserved[100]; ///< Reserved for later function definition
+} MEM_FUNCTION_STRUCT;
+
+///
+/// Socket Structure
+///
+///
+typedef struct _MEM_SOCKET_STRUCT {
+  OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels training data
+
+  OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels timing data
+} MEM_SOCKET_STRUCT;
+
+///
+/// Contains all data relevant to Memory Initialization.
+///
+typedef struct _MEM_DATA_STRUCT {
+  IN AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
+
+  IN MEM_PARAMETER_STRUCT *ParameterListPtr;  ///< List of input Parameters
+
+  OUT MEM_FUNCTION_STRUCT FunctionList;       ///< List of function Pointers
+
+  IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+
+  IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+
+
+  OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED];  ///< Socket list for memory code.
+                                   ///< SocketList is a shortcut for IBVs to retrieve training
+                                   ///< and timing data for each channel indexed by socket/channel,
+                                   ///< eliminating their need to parse die/dct/channel etc.
+                                   ///< It contains pointers to the populated data structures for
+                                   ///< each channel and skips the channel structures that are
+                                   ///< unpopulated. In the case of channels sharing the same DCT,
+                                   ///< the pTimings pointers will point to the same DCT Timing data.
+
+  OUT DIE_STRUCT *DiesPerSystem;  ///< Pointed to an array of DIE_STRUCTs
+  OUT UINT8      DieCount;        ///< Number of MCTs in the system.
+
+  IN SPD_DEF_STRUCT *SpdDataStructure;              ///< Pointer to SPD Data structure
+
+  IN OUT  struct _PLATFORM_CONFIGURATION   *PlatFormConfig;    ///< Platform profile/build option config structure
+
+  IN OUT BOOLEAN IsFlowControlSupported;    ///< Indicates if flow control is supported
+
+  OUT UINT32 TscRate;             ///< The rate at which the TSC increments in megahertz.
+
+} MEM_DATA_STRUCT;
+
+///
+/// Uma Structure
+///
+///
+typedef struct _UMA_INFO {
+  OUT UINT64 UmaBase;          ///< UmaBase[63:0] = Addr[63:0]
+  OUT UINT32 UmaSize;          ///< UmaSize[31:0] = Addr[31:0]
+  OUT UINT32 UmaAttributes;    ///< Indicate the attribute of Uma
+  OUT UINT8 UmaMode;           ///< Indicate the mode of Uma
+  OUT UINT16 MemClock;         ///< Indicate memory running speed in MHz
+  OUT UINT8 Reserved[3];       ///< Reserved for future usage
+} UMA_INFO;
+
+//  AGESA MEMORY ERRORS
+
+// AGESA_ALERT Memory Errors
+#define MEM_ALERT_USER_TMG_MODE_OVERRULED   0x04010000 ///< TIMING_MODE_SPECIFIC is requested but
+                                                       ///< cannot be applied to current configurations.
+#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100          ///< DIMM organization miss-match
+#define MEM_ALERT_BK_INT_DIS 0x04010200                 ///< Bank interleaving disable for internal issue
+
+// AGESA_ERROR Memory Errors
+#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300     ///< No DQS Position window for RD DQS
+#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300  ///< Small DQS Position window for RD DQS
+#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300     ///< No DQS Position window for WR DQS
+#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300  ///< Small DQS Position window for WR DQS
+#define MEM_ERROR_ECC_DIS 0x04010400                  ///< ECC has been disabled as a result of an internal issue
+#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window
+#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit
+#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit
+#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit
+#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit
+#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit
+#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit
+#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit
+#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit
+#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit
+#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit
+#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit
+#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit
+#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit
+#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training
+#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP
+#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training
+#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT  0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit
+#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR  0x04011200    ///< SPD Checksum error for NV_SPDCHK_RESTRT
+#define MEM_ERROR_NO_CHIPSELECT 0x04011300              ///< No chipselects found
+#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500   ///< Unbuffered dimm is not supported at 333MHz
+#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300   ///< Returned PRE value during write levelizzation was out of range
+
+// AGESA_WARNING Memory Errors
+#define MEM_WARNING_UNSUPPORTED_QRDIMM      0x04011600 ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM       0x04021600 ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM      0x04031600 ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM      0x04041600 ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM       0x04051600 ///< R DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_LRDIMM      0x04061600 ///< LR DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED       0x04011700 ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT            0x04021700  ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED         0x04031700  ///< Memory size is not power of two.
+#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800  ///< Performance has been enabled, but battery life is preferred.
+                                                        ///< bank interleaving, or bank swizzle is enabled.
+#define MEM_WARNING_NO_SPDTRC_FOUND         0x04011900  ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000    ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
+
+// AGESA_FATAL Memory Errors
+#define MEM_ERROR_MINIMUM_MODE 0x04011A00               ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00  ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00    ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS  0x04011D00      ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME 0x04011E00                ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS   0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs   0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV   0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD     0x04041F00    ///< Heap allocation error for SPD data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA     0x04051F00    ///< Heap allocation error for RECEIVED_DATA during parallel training
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS     0x04061F00    ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA     0x04071F00   ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK     0x04081F00    ///< Heap allocation error for  DIMM Identify "MEM_NB_BLOCK
+#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM     0x04022300   ///< No Constructor for DIMM Identify
+
+// AGESA_CRITICAL Memory Errors
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3     0x04091F00    ///< Heap allocation error for DMI table for DDR3
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2     0x040A1F00    ///< Heap allocation error for DMI table for DDR2
+#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG              0x04011400    ///< Dimm population is not supported
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ *                END OF MEMORY-SPECIFIC DATA STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ *                    CPU RELATED DEFINITIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// CPU Event definitions.
+
+// Defines used to filter CPU events based on functional blocks
+#define CPU_EVENT_PM_EVENT_MASK                         0xFF00FF00
+#define CPU_EVENT_PM_EVENT_CLASS                        0x08000400
+
+//================================================================
+// CPU General events
+//    Heap allocation                     (AppFunction =      01h)
+#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT            0x08000100
+#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED           0x08010100
+#define CPU_ERROR_HEAP_IS_FULL                          0x08020100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED    0x08030100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     0x08040100
+//    BrandId                             (AppFunction =      02h)
+#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE            0x08000200
+//    Micro code patch                    (AppFunction =      03h)
+#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED        0x08000300
+//    Power management                    (AppFunction =      04h)
+#define CPU_EVENT_PM_PSTATE_OVERCURRENT                 0x08000400
+#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT             0x08010400
+#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE             0x08020400
+#define CPU_ERROR_PM_NB_PSTATE_MISMATCH                 0x08030400
+//    BIST                                (AppFunction =      05h)
+#define CPU_EVENT_BIST_ERROR                            0x08000500
+
+//=================================================================
+// CPU Feature events
+//    Execution cache                     (AppFunction =      21h)
+//        AGESA_CACHE_SIZE_REDUCED                            2101
+//        AGESA_CACHE_REGIONS_ACROSS_1MB                      2102
+//        AGESA_CACHE_REGIONS_ACROSS_4GB                      2103
+//        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY                2104
+//        AGESA_CACHE_START_ADDRESS_LESS_D0000                2105
+//        AGESA_THREE_CACHE_REGIONS_ABOVE_1MB                 2106
+//        AGESA_DEALLOCATE_CACHE_REGIONS                      2107
+#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR      0x08002100
+//    Core Leveling                       (AppFunction =      22h)
+#define CPU_WARNING_ADJUSTED_LEVELING_MODE              0x08002200
+//    HT Assist                           (AppFunction =      23h)
+#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG            0x08002300
+
+// CPU Build Configuration structures and definitions
+
+/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
+typedef struct {
+  IN  UINT32 MsrAddr;     ///< Fixed-Sized MTRR address
+  IN  UINT64 MsrData;     ///< MTRR Settings
+} AP_MTRR_SETTINGS;
+
+#define AMD_AP_MTRR_FIX64k_00000    0x00000250
+#define AMD_AP_MTRR_FIX16k_80000    0x00000258
+#define AMD_AP_MTRR_FIX16k_A0000    0x00000259
+#define AMD_AP_MTRR_FIX4k_C0000     0x00000268
+#define AMD_AP_MTRR_FIX4k_C8000     0x00000269
+#define AMD_AP_MTRR_FIX4k_D0000     0x0000026A
+#define AMD_AP_MTRR_FIX4k_D8000     0x0000026B
+#define AMD_AP_MTRR_FIX4k_E0000     0x0000026C
+#define AMD_AP_MTRR_FIX4k_E8000     0x0000026D
+#define AMD_AP_MTRR_FIX4k_F0000     0x0000026E
+#define AMD_AP_MTRR_FIX4k_F8000     0x0000026F
+#define CPU_LIST_TERMINAL           0xFFFFFFFF
+
+/************************************************************************
+ *
+ *  AGESA interface Call-Out function parameter structures
+ *
+ ***********************************************************************/
+
+/// Parameters structure for interface call-out AgesaAllocateBuffer
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
+  IN OUT    UINT32              BufferLength;   ///< Size of buffer to allocate
+  IN        UINT32              BufferHandle;   ///< Identifier or name for the buffer
+  OUT       VOID                *BufferPointer; ///< location of the created buffer
+} AGESA_BUFFER_PARAMS;
+
+/// Parameters structure for interface call-out AgesaRunCodeOnAp
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;            ///< Standard configuration header
+  IN        UINT32              FunctionNumber;       ///< Index of the procedure to execute
+  IN        VOID                *RelatedDataBlock;    ///< Location of data structure the procedure will use
+  IN        UINT32              RelatedBlockLength;   ///< Size of the related data block
+} AP_EXE_PARAMS;
+
+/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
+  IN        UINT8               SocketId;       ///< Address of SPD - socket ID
+  IN        UINT8               MemChannelId;   ///< Address of SPD - memory channel ID
+  IN        UINT8               DimmId;         ///< Address of SPD - DIMM ID
+  IN OUT    UINT8               *Buffer;        ///< Location where to place the SPD content
+  IN OUT    MEM_DATA_STRUCT     *MemData;       ///< Location of the MemData structure, for reference
+} AGESA_READ_SPD_PARAMS;
+
+/// Buffer Handles
+typedef enum {
+  AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000,       ///< Assign 0x000D000 buffer handle to DMI function
+  AMD_PSTATE_DATA_BUFFER_HANDLE,                ///< Assign 0x000D001 buffer handle to Pstate data
+  AMD_PSTATE_ACPI_BUFFER_HANDLE,                ///< Assign 0x000D002 buffer handle to Pstate table
+  AMD_BRAND_ID_BUFFER_HANDLE,                   ///< Assign 0x000D003 buffer handle to Brand ID
+  AMD_ACPI_SLIT_BUFFER_HANDLE,                  ///< Assign 0x000D004 buffer handle to SLIT function
+  AMD_SRAT_INFO_BUFFER_HANDLE,                  ///< Assign 0x000D005 buffer handle to SRAT function
+  AMD_WHEA_BUFFER_HANDLE,                       ///< Assign 0x000D006 buffer handle to WHEA function
+  AMD_S3_INFO_BUFFER_HANDLE,                    ///< Assign 0x000D007 buffer handle to S3 function
+  AMD_S3_NB_INFO_BUFFER_HANDLE,                 ///< Assign 0x000D008 buffer handle to S3 NB device info
+  AMD_ACPI_ALIB_BUFFER_HANDLE                   ///< Assign 0x000D009 buffer handle to ALIB SSDT table
+} AMD_BUFFER_HANDLE;
+/************************************************************************
+ *
+ *  AGESA interface Call-Out function prototypes
+ *
+ ***********************************************************************/
+
+VOID
+AgesaDoReset (
+  IN        UINTN               ResetType,
+  IN OUT    AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+AgesaAllocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *AllocParams
+  );
+
+AGESA_STATUS
+AgesaDeallocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *DeallocParams
+  );
+
+AGESA_STATUS
+AgesaLocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *LocateParams
+  );
+
+AGESA_STATUS
+AgesaReadSpd (
+  IN        UINTN                 FcnData,
+  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+  );
+
+AGESA_STATUS
+AgesaReadSpdRecovery (
+  IN        UINTN                 FcnData,
+  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDramInitRecovery (
+  IN       UINTN           FcnData,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  );
+
+AGESA_STATUS
+AgesaRunFcnOnAp (
+  IN        UINTN               ApicIdOfCore,
+  IN        AP_EXE_PARAMS       *LaunchApParams
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+  IN        UINTN               FcnData,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+  IN        UINTN               FcnData,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+  IN        UINTN               FcnData,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+  IN      UINTN                 FcnData,
+  IN      PCIe_SLOT_RESET_INFO  *ResetInfo
+ );
+
+/************************************************************************
+ *
+ *  AGESA interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Platform Configuration:  The parameters in boot branch function
+ **********************************************************************/
+
+///  The possible platform control flow settings.
+typedef enum  {
+  Nfcm,                                          ///< Normal Flow Control Mode.
+  UmaDr,                                         ///< UMA using Display Refresh flow control.
+  UmaIfcm,                                       ///< UMA using Isochronous Flow Control.
+  Ifcm,                                          ///< Isochronous Flow Control Mode (other than for UMA).
+  Iommu,                                         ///< An IOMMU is in use in the system.
+  MaxControlFlow                                 ///< Not a control flow mode, use for limit checking.
+} PLATFORM_CONTROL_FLOW;
+
+///  Platform Deemphasis Levels.
+///
+/// The deemphasis level is set for the receiver, based on link characterization.  The DCV level is
+/// set based on the level of the far transmitter.
+typedef enum {
+  DeemphasisLevelNone,                           ///< No Deemphasis.
+  DeemphasisLevelMinus3,                         ///< Minus 3 db deemphasis.
+  DeemphasisLevelMinus6,                         ///< Minus 6 db deemphasis.
+  DeemphasisLevelMinus8,                         ///< Minus 8 db deemphasis.
+  DeemphasisLevelMinus11,                        ///< Minus 11 db deemphasis.
+  DeemphasisLevelMinus11pre8,                    ///< Minus 11, Minus 8 precursor db deemphasis.
+  DcvLevelNone = 16,                             ///< No DCV Deemphasis.
+  DcvLevelMinus2,                                ///< Minus 2 db DCV deemphasis.
+  DcvLevelMinus3,                                ///< Minus 3 db DCV deemphasis.
+  DcvLevelMinus5,                                ///< Minus 5 db DCV deemphasis.
+  DcvLevelMinus6,                                ///< Minus 6 db DCV deemphasis.
+  DcvLevelMinus7,                                ///< Minus 7 db DCV deemphasis.
+  DcvLevelMinus8,                                ///< Minus 8 db DCV deemphasis.
+  DcvLevelMinus9,                                ///< Minus 9 db DCV deemphasis.
+  DcvLevelMinus11,                               ///< Minus 11 db DCV deemphasis.
+  MaxPlatformDeemphasisLevel                     ///< Not a deemphasis level, use for limit checking.
+} PLATFORM_DEEMPHASIS_LEVEL;
+
+///  Provide Deemphasis Levels for HT Links.
+///
+///  For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
+///  be checked for a match.  The item matches for a Socket, Link if the link frequency is
+///  is in the inclusive range HighFreq:LoFreq.
+///  AGESA does not set deemphasis in IO devices, only in processors.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                                        ///< One Socket on which this Link is located
+  IN       UINT8 Link;                                          ///< The Link on this Processor.
+  IN       UINT8 LoFreq;                                        ///< If the link is set to this frequency or greater, apply these levels, and
+  IN       UINT8 HighFreq;                                      ///< If the link is set to this frequency or less, apply these levels.
+  // Value fields
+  IN       PLATFORM_DEEMPHASIS_LEVEL     ReceiverDeemphasis;    ///< The deemphasis level for this link
+  IN       PLATFORM_DEEMPHASIS_LEVEL     DcvDeemphasis;         ///< The DCV, or far transmitter deemphasis level.
+} CPU_HT_DEEMPHASIS_LEVEL;
+
+///  The possible platform power policy settings.
+typedef enum  {
+  Performance,                                   ///< Optimize for performance.
+  BatteryLife,                                   ///< Optimize for battery life.
+  MaxPowerPolicy                                 ///< Not a power policy mode, use for limit checking.
+} PLATFORM_POWER_POLICY;
+
+///  Platform performance settings for optimized settings.
+///  Several configuration settings for the processor depend upon other parts and
+///  general designer choices for the system. The determination of these data points
+///  is not standard for all platforms, so the host environment needs to provide these
+///  to specify how the system is to be configured.
+typedef struct {
+  IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;    ///< The platform's control flow mode for optimum platform performance.
+                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
+  IN BOOLEAN               UseHtAssist;                ///< HyperTransport link traffic optimization.
+                                                       ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST}
+  IN BOOLEAN               UseAtmMode;                 ///< HyperTransport link traffic optimization.
+                                                       ///< @BldCfgItem{BLDCFG_USE_ATM_MODE}
+  IN BOOLEAN               Use32ByteRefresh;           ///< Display Refresh traffic generates 32 byte requests.
+                                                       ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
+  IN BOOLEAN               UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
+                                                       ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
+  IN PLATFORM_POWER_POLICY PlatformPowerPolicy;        ///< The platform's desired power policy
+                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
+} PERFORMANCE_PROFILE;
+
+///  Platform settings that describe the voltage regulator modules of the system.
+///  Many power management settings are dependent upon the characteristics of the
+///  on-board voltage regulator module (VRM).  The host environment needs to provide
+///  these to specify how the system is to be configured.
+typedef struct {
+  IN UINT32  CurrentLimit;                         ///< Vrm Current Limit.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
+  IN UINT32  LowPowerThreshold;                    ///< Vrm Low Power Threshold.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
+  IN UINT32  SlewRate;                             ///< Vrm Slew Rate.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
+  IN UINT32  AdditionalDelay;                      ///< Vrm Additional Delay.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY}
+  IN BOOLEAN HiSpeedEnable;                        ///< Select high speed VRM.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
+  IN UINT32  InrushCurrentLimit;                   ///< Vrm Inrush Current Limit.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT}
+} PLATFORM_VRM_CONFIGURATION;
+
+///  The VRM types to characterize.
+typedef enum  {
+  CoreVrm,                                       ///< VDD plane.
+  NbVrm,                                         ///< VDDNB plane.
+  MaxVrmType                                     ///< Not a valid VRM type, use for limit checking.
+} PLATFORM_VRM_TYPE;
+
+
+/// Build Option/Configuration Boolean Structure.
+typedef struct {
+  IN  AMD_CODE_HEADER VersionString;              ///< AMD embedded code version string
+
+  //Build Option Area
+  IN BOOLEAN OptionUDimms;                        ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
+  IN BOOLEAN OptionRDimms;                        ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
+  IN BOOLEAN OptionLrDimms;                      ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
+  IN BOOLEAN OptionEcc;                           ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
+  IN BOOLEAN OptionBankInterleave;                ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
+  IN BOOLEAN OptionDctInterleave;                 ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
+  IN BOOLEAN OptionNodeInterleave;                ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
+  IN BOOLEAN OptionParallelTraining;              ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
+  IN BOOLEAN OptionOnlineSpare;                   ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
+  IN BOOLEAN OptionMemRestore;                    ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
+  IN BOOLEAN OptionMultisocket;                   ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
+  IN BOOLEAN OptionAcpiPstates;                   ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
+  IN BOOLEAN OptionSrat;                          ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
+  IN BOOLEAN OptionSlit;                          ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
+  IN BOOLEAN OptionWhea;                          ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
+  IN BOOLEAN OptionDmi;                           ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
+  IN BOOLEAN OptionEarlySamples;                  ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
+  IN BOOLEAN OptionAddrToCsTranslator;            ///< ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  IN UINT64 CfgPciMmioAddress;                    ///< Pci Mmio Base Address to use for PCI Config accesses.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
+  IN UINT32 CfgPciMmioSize;                       ///< Pci Mmio region Size.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
+  IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+  IN UINT32 CfgPlatNumIoApics;                    ///< The number of IO APICS for the platform.
+  IN UINT32 CfgMemInitPstate;                     ///< Memory Init Pstate.
+  IN PLATFORM_C1E_MODES CfgPlatformC1eMode;       ///< Select the C1e Mode that will used.
+  IN UINT32 CfgPlatformC1eOpData;                 ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData1;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData2;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
+  IN UINT32 CfgPlatformCStateOpData;              ///< An IO port or additional C-State setup data, depends on C-State mode.
+  IN UINT16 CfgPlatformCStateIoBaseAddress;       ///< Specifies I/O ports that can be used to allow CPU to enter CStates
+  IN PLATFORM_CPB_MODES CfgPlatformCpbMode;       ///< Enable or disable core performance boost
+  IN UINT32 CfgCoreLevelingMode;                  ///< Apply any downcoring or core count leveling as specified.
+  IN PERFORMANCE_PROFILE CfgPerformanceProfile;   ///< The platform's control flow mode and platform performance settings.
+  IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+
+  IN UINT32 CfgAmdPlatformType;                   ///< Designate the platform as a Server, Desktop, or Mobile.
+  IN UINT32 CfgAmdPstateCapValue;                 ///< Amd pstate ceiling enabling deck
+
+  IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
+  IN BOOLEAN CfgMemoryModeUnganged;               ///< Memory Mode Unganged.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
+  IN BOOLEAN CfgMemoryQuadRankCapable;            ///< Memory Quad Rank Capable.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
+  IN QUANDRANK_TYPE CfgMemoryQuadrankType;        ///< Memory Quadrank Type.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
+  IN BOOLEAN CfgMemoryRDimmCapable;               ///< Memory RDIMM Capable.
+  IN BOOLEAN CfgMemoryLRDimmCapable;              ///< Memory LRDIMM Capable.
+  IN BOOLEAN CfgMemoryUDimmCapable;               ///< Memory UDIMM Capable.
+  IN BOOLEAN CfgMemorySODimmCapable;              ///< Memory SODimm Capable.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
+  IN BOOLEAN CfgMemoryEnableBankInterleaving;     ///< Memory Enable Bank Interleaving.
+  IN BOOLEAN CfgMemoryEnableNodeInterleaving;     ///< Memory Enable Node Interleaving.
+  IN BOOLEAN CfgMemoryChannelInterleaving;        ///< Memory Channel Interleaving.
+  IN BOOLEAN CfgMemoryPowerDown;                  ///< Memory Power Down.
+  IN POWER_DOWN_MODE CfgPowerDownMode;            ///< Power Down Mode.
+  IN BOOLEAN CfgOnlineSpare;                      ///< Online Spare.
+  IN BOOLEAN CfgMemoryParityEnable;               ///< Memory Parity Enable.
+  IN BOOLEAN CfgBankSwizzle;                      ///< Bank Swizzle.
+  IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select.
+  IN MEMORY_BUS_SPEED CfgMemoryClockSelect;       ///< Memory Clock Select.
+  IN BOOLEAN CfgDqsTrainingControl;               ///< Dqs Training Control.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
+  IN BOOLEAN CfgIgnoreSpdChecksum;                ///< Ignore Spd Checksum.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
+  IN BOOLEAN CfgUseBurstMode;                     ///< Use Burst Mode.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
+  IN BOOLEAN CfgMemoryAllClocksOn;                ///< Memory All Clocks On.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
+  IN BOOLEAN CfgEnableEccFeature;                 ///< Enable ECC Feature.
+  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
+  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
+  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
+  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
+  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
+  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
+  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
+  IN UINT16  CfgEccSymbolSize;                    ///< ECC Symbol Size.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
+  IN UINT64  CfgHeapDramAddress;                  ///< Heap contents will be temporarily stored in this address during the transition.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
+  IN BOOLEAN CfgNodeMem1GBAlign;                  ///< Node Mem 1GB boundary Alignment
+  IN BOOLEAN CfgS3LateRestore;                    ///< S3 Late Restore
+  IN BOOLEAN CfgAcpiPstateIndependent;            ///< PSD method dependent/Independent
+  IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList;     ///< The AP's MTRR settings before final halt
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
+  IN UMA_MODE CfgUmaMode;                         ///< Uma Mode
+  IN UINT32 CfgUmaSize;                           ///< Uma Size [31:0]=Addr[47:16]
+  IN BOOLEAN CfgUmaAbove4G;                       ///< Uma Above 4G Support
+  IN UMA_ALIGNMENT CfgUmaAlignment;               ///< Uma alignment
+  IN BOOLEAN CfgProcessorScopeInSb;               ///< ACPI Processor Object in \\_SB scope
+  IN CHAR8   CfgProcessorScopeName0;              ///< OEM specific 1st character of processor scope name.
+  IN CHAR8   CfgProcessorScopeName1;              ///< OEM specific 2nd character of processor scope name.
+  IN UINT8   CfgGnbHdAudio;                       ///< GNB HD Audio
+  IN UINT8   CfgAbmSupport;                       ///< Abm Support
+  IN UINT8   CfgDynamicRefreshRate;               ///< DRR Dynamic Refresh Rate
+  IN UINT16  CfgLcdBackLightControl;              ///< LCD Backlight Control
+  IN UINT8   CfgGnb3dStereoPinIndex;                ///< 3D Stereo Pin ID.
+  IN UINT32  CfgTempPcieMmioBaseAddress;          ///< Temp pcie MMIO base Address
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
+  IN UINT32  CfgGnbIGPUSSID;                      ///< Gnb internal GPU SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
+  IN UINT32  CfgGnbHDAudioSSID;                   ///< Gnb HD Audio SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
+  IN UINT32  CfgGnbPcieSSID;                      ///< Gnb PCIe SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
+  IN UINT16  CfgLvdsSpreadSpectrum;               ///< Lvds Spread Spectrum
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+  IN UINT16  CfgLvdsSpreadSpectrumRate;           ///< Lvds Spread Spectrum Rate
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+  IN BOOLEAN Reserved;                            ///< reserved...
+} BUILD_OPT_CFG;
+
+///  A structure containing platform specific operational characteristics. This
+///  structure is initially populated by the initializer with a copy of the same
+///  structure that was created at build time using the build configuration controls.
+typedef struct _PLATFORM_CONFIGURATION {
+  IN PERFORMANCE_PROFILE PlatformProfile;             ///< Several configuration settings for the processor.
+  IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}.
+                                                      ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples".
+  IN UINT8               CoreLevelingMode;            ///< Indicates how to balance the number of cores per processor.
+                                                      ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
+  IN PLATFORM_C1E_MODES  C1eMode;                     ///< Specifies the method of C1e enablement - Disabled, HW, or message based.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE}
+  IN UINT32              C1ePlatformData;             ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA}
+  IN UINT32              C1ePlatformData1;            ///< If C1eMode is SW, specifies the address of chipset's SMI command port.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1}
+  IN UINT32              C1ePlatformData2;            ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2}
+  IN PLATFORM_CSTATE_MODES  CStateMode;               ///< Specifies the method of C-State enablement - Disabled, or C6.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
+  IN UINT32              CStatePlatformData;          ///< This element specifies some pertinent data needed for the operation of the Cstate feature
+                                                      ///< If CStateMode is CStateModeC6, this item is reserved
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
+  IN UINT16              CStateIoBaseAddress;         ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
+                                                      ///< can be used to allow the CPU to enter Cstates.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
+  IN PLATFORM_CPB_MODES  CpbMode;                     ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
+  IN BOOLEAN             UserOptionDmi;               ///< When set to TRUE, the DMI data table is generated.
+  IN BOOLEAN             UserOptionPState;            ///< When set to TRUE, the PState data tables are generated.
+  IN BOOLEAN             UserOptionSrat;              ///< When set to TRUE, the SRAT data table is generated.
+  IN BOOLEAN             UserOptionSlit;              ///< When set to TRUE, the SLIT data table is generated.
+  IN BOOLEAN             UserOptionWhea;              ///< When set to TRUE, the WHEA data table is generated.
+  IN UINT32              PowerCeiling;                ///< P-State Ceiling Enabling Deck - Max power milli-watts.
+  IN BOOLEAN             ForcePstateIndependent;      ///< P-State _PSD independence or dependence.
+                                                      ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
+  IN UINT32              NumberOfIoApics;             ///< Number of I/O APICs in the system
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
+  IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+  IN BOOLEAN             ProcessorScopeInSb;          ///< ACPI Processor Object in \\_SB scope
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
+  IN CHAR8               ProcessorScopeName0;         ///< OEM specific 1st character of processor scope name.
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
+  IN CHAR8               ProcessorScopeName1;         ///< OEM specific 2nd character of processor scope name.
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
+  IN UINT8               GnbHdAudio;                  ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
+                                                      ///< essentially it enables function 1 of graphics device.
+                                                      ///< @li 0 = HD Audio disable
+                                                      ///< @li 1 = HD Audio enable
+                                                      ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
+  IN UINT8               AbmSupport;                  ///< Automatic adjust LVDS/eDP Back light level support.It is
+                                                      ///< characteristic specific to display panel which used by platform design.
+                                                      ///< @li 0 = ABM support disabled
+                                                      ///< @li 1 = ABM support enabled
+                                                      ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
+  IN UINT8               DynamicRefreshRate;          ///< Adjust refresh rate on LVDS/eDP.
+                                                      ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
+  IN UINT16              LcdBackLightControl;         ///< The PWM frequency to LCD backlight control.
+                                                      ///< If equal to 0 backlight not controlled by iGPU
+                                                      ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
+} PLATFORM_CONFIGURATION;
+
+
+/**********************************************************************
+ * Structures for: AmdInitLate
+ **********************************************************************/
+#define PROC_VERSION_LENGTH 48
+#define MAX_DIMMS_PER_SOCKET 16
+
+/*  Interface Parameter Structures  */
+/// DMI Type4 - Processor ID
+typedef struct {
+  OUT UINT32                    ProcIdLsd;              ///< Lower half of 64b ID
+  OUT UINT32                    ProcIdMsd;              ///< Upper half of 64b ID
+} TYPE4_PROC_ID;
+
+/// DMI Type 4 - Processor information
+typedef struct {
+  OUT UINT8                     T4ProcType;             ///< CPU Type
+  OUT UINT8                     T4ProcFamily;           ///< Family 1
+  OUT TYPE4_PROC_ID             T4ProcId;               ///< Id
+  OUT UINT8                     T4Voltage;              ///< Voltage
+  OUT UINT16                    T4ExternalClock;        ///< External clock
+  OUT UINT16                    T4MaxSpeed;             ///< Max speed
+  OUT UINT16                    T4CurrentSpeed;         ///< Current speed
+  OUT UINT8                     T4Status;               ///< Status
+  OUT UINT8                     T4ProcUpgrade;          ///< Up grade
+  OUT UINT8                     T4CoreCount;            ///< Core count
+  OUT UINT8                     T4CoreEnabled;          ///< Core Enable
+  OUT UINT8                     T4ThreadCount;          ///< Thread count
+  OUT UINT16                    T4ProcCharacteristics;  ///< Characteristics
+  OUT UINT16                    T4ProcFamily2;          ///< Family 2
+  OUT CHAR8                     T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
+} TYPE4_DMI_INFO;
+
+/// DMI Type 7 - Cache information
+typedef struct _TYPE7_DMI_INFO {
+  OUT UINT16                    T7CacheCfg;             ///< Cache cfg
+  OUT UINT16                    T7MaxCacheSize;         ///< Max size
+  OUT UINT16                    T7InstallSize;          ///< Install size
+  OUT UINT16                    T7SupportedSramType;    ///< Supported Sram Type
+  OUT UINT16                    T7CurrentSramType;      ///< Current type
+  OUT UINT8                     T7CacheSpeed;           ///< Speed
+  OUT UINT8                     T7ErrorCorrectionType;  ///< ECC type
+  OUT UINT8                     T7SystemCacheType;      ///< Cache type
+  OUT UINT8                     T7Associativity;        ///< Associativity
+} TYPE7_DMI_INFO;
+
+/// DMI Type 16 offset 04h - Location
+typedef enum {
+  OtherLocation = 0x01,                                 ///< Assign 01 to Other
+  UnknownLocation,                                      ///< Assign 02 to Unknown
+  SystemboardOrMotherboard,                             ///< Assign 03 to systemboard or motherboard
+  IsaAddonCard,                                         ///< Assign 04 to ISA add-on card
+  EisaAddonCard,                                        ///< Assign 05 to EISA add-on card
+  PciAddonCard,                                         ///< Assign 06 to PCI add-on card
+  McaAddonCard,                                         ///< Assign 07 to MCA add-on card
+  PcmciaAddonCard,                                      ///< Assign 08 to PCMCIA add-on card
+  ProprietaryAddonCard,                                 ///< Assign 09 to proprietary add-on card
+  NuBus,                                                ///< Assign 0A to NuBus
+  Pc98C20AddonCard,                                     ///< Assign 0A0 to PC-98/C20 add-on card
+  Pc98C24AddonCard,                                     ///< Assign 0A1 to PC-98/C24 add-on card
+  Pc98EAddoncard,                                       ///< Assign 0A2 to PC-98/E add-on card
+  Pc98LocalBusAddonCard                                 ///< Assign 0A3 to PC-98/Local bus add-on card
+} DMI_T16_LOCATION;
+
+/// DMI Type 16 offset 05h - Memory Error Correction
+typedef enum {
+  OtherUse = 0x01,                                      ///< Assign 01 to Other
+  UnknownUse,                                           ///< Assign 02 to Unknown
+  SystemMemory,                                         ///< Assign 03 to system memory
+  VideoMemory,                                          ///< Assign 04 to video memory
+  FlashMemory,                                          ///< Assign 05 to flash memory
+  NonvolatileRam,                                       ///< Assign 06 to non-volatile RAM
+  CacheMemory                                           ///< Assign 07 to cache memory
+} DMI_T16_USE;
+
+/// DMI Type 16 offset 07h - Maximum Capacity
+typedef enum {
+  Dmi16OtherErrCorrection = 0x01,                       ///< Assign 01 to Other
+  Dmi16UnknownErrCorrection,                            ///< Assign 02 to Unknown
+  Dmi16NoneErrCorrection,                               ///< Assign 03 to None
+  Dmi16Parity,                                          ///< Assign 04 to parity
+  Dmi16SingleBitEcc,                                    ///< Assign 05 to Single-bit ECC
+  Dmi16MultiBitEcc,                                     ///< Assign 06 to Multi-bit ECC
+  Dmi16Crc                                              ///< Assign 07 to CRC
+} DMI_T16_ERROR_CORRECTION;
+
+/// DMI Type 16 - Physical Memory Array
+typedef struct {
+  OUT DMI_T16_LOCATION          Location;               ///< The physical location of the Memory Array,
+                                                        ///< whether on the system board or an add-in board.
+  OUT DMI_T16_USE               Use;                    ///< Identifies the function for which the array
+                                                        ///< is used.
+  OUT DMI_T16_ERROR_CORRECTION  MemoryErrorCorrection;  ///< The primary hardware error correction or
+                                                        ///< detection method supported by this memory array.
+  OUT UINT32                    MaximumCapacity;        ///< The maximum memory capacity, in kilobytes,
+                                                        ///< for the array.
+  OUT UINT16                    NumberOfMemoryDevices;  ///< The number of slots or sockets available
+                                                        ///< for memory devices in this array.
+} TYPE16_DMI_INFO;
+
+/// DMI Type 17 offset 0Eh - Form Factor
+typedef enum {
+  OtherFormFactor = 0x01,                               ///< Assign 01 to Other
+  UnknowFormFactor,                                     ///< Assign 02 to Unknown
+  SimmFormFactor,                                       ///< Assign 03 to SIMM
+  SipFormFactor,                                        ///< Assign 04 to SIP
+  ChipFormFactor,                                       ///< Assign 05 to Chip
+  DipFormFactor,                                        ///< Assign 06 to DIP
+  ZipFormFactor,                                        ///< Assign 07 to ZIP
+  ProprietaryCardFormFactor,                            ///< Assign 08 to Proprietary Card
+  DimmFormFactorFormFactor,                             ///< Assign 09 to DIMM
+  TsopFormFactor,                                       ///< Assign 10 to TSOP
+  RowOfChipsFormFactor,                                 ///< Assign 11 to Row of chips
+  RimmFormFactor,                                       ///< Assign 12 to RIMM
+  SodimmFormFactor,                                     ///< Assign 13 to SODIMM
+  SrimmFormFactor,                                      ///< Assign 14 to SRIMM
+  FbDimmFormFactor                                      ///< Assign 15 to FB-DIMM
+} DMI_T17_FORM_FACTOR;
+
+/// DMI Type 17 offset 12h - Memory Type
+typedef enum {
+  OtherMemType = 0x01,                                  ///< Assign 01 to Other
+  UnknownMemType,                                       ///< Assign 02 to Unknown
+  DramMemType,                                          ///< Assign 03 to DRAM
+  EdramMemType,                                         ///< Assign 04 to EDRAM
+  VramMemType,                                          ///< Assign 05 to VRAM
+  SramMemType,                                          ///< Assign 06 to SRAM
+  RamMemType,                                           ///< Assign 07 to RAM
+  RomMemType,                                           ///< Assign 08 to ROM
+  FlashMemType,                                         ///< Assign 09 to Flash
+  EepromMemType,                                        ///< Assign 10 to EEPROM
+  FepromMemType,                                        ///< Assign 11 to FEPROM
+  EpromMemType,                                         ///< Assign 12 to EPROM
+  CdramMemType,                                         ///< Assign 13 to CDRAM
+  ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
+  SdramMemType,                                         ///< Assign 15 to SDRAM
+  SgramMemType,                                         ///< Assign 16 to SGRAM
+  RdramMemType,                                         ///< Assign 17 to RDRAM
+  DdrMemType,                                           ///< Assign 18 to DDR
+  Ddr2MemType,                                          ///< Assign 19 to DDR2
+  Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
+  Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
+  Fbd2MemType                                           ///< Assign 25 to FBD2
+} DMI_T17_MEMORY_TYPE;
+
+/// DMI Type 17 offset 13h - Type Detail
+typedef struct {
+  OUT UINT16                    Reserved1:1;            ///< Reserved
+  OUT UINT16                    Other:1;                ///< Other
+  OUT UINT16                    Unknown:1;              ///< Unknown
+  OUT UINT16                    FastPaged:1;            ///< Fast-Paged
+  OUT UINT16                    StaticColumn:1;         ///< Static column
+  OUT UINT16                    PseudoStatic:1;         ///< Pseudo-static
+  OUT UINT16                    Rambus:1;               ///< RAMBUS
+  OUT UINT16                    Synchronous:1;          ///< Synchronous
+  OUT UINT16                    Cmos:1;                 ///< CMOS
+  OUT UINT16                    Edo:1;                  ///< EDO
+  OUT UINT16                    WindowDram:1;           ///< Window DRAM
+  OUT UINT16                    CacheDram:1;            ///< Cache Dram
+  OUT UINT16                    NonVolatile:1;          ///< Non-volatile
+  OUT UINT16                    Reserved2:3;            ///< Reserved
+} DMI_T17_TYPE_DETAIL;
+
+/// DMI Type 17 - Memory Device
+typedef struct {
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceSet;              ///< Identifies when the Memory Device is one of a set of
+                                                        ///< Memory Devices that must be populated with all devices of
+                                                        ///< the same type and size, and the set to which this device belongs.
+  OUT CHAR8                     DeviceLocator[8];       ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT CHAR8                     BankLocator[10];        ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT DMI_T17_MEMORY_TYPE       MemoryType;             ///< The type of memory used in this device.
+  OUT DMI_T17_TYPE_DETAIL       TypeDetail;             ///< Additional detail on the memory device type
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
+  OUT CHAR8                     PartNumber[19];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  OUT UINT32                    ExtSize;                ///< Extended Size.
+  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
+} TYPE17_DMI_INFO;
+
+/// Memory DMI Type 17 and 20 - for memory use
+typedef struct {
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceLocator;          ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT UINT8                     BankLocator;            ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT UINT8                     SerialNumber[4];        ///< Serial Number.
+  OUT UINT8                     PartNumber[18];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  OUT UINT32                    ExtSize;                ///< Extended Size.
+  OUT UINT8                     Socket:3;               ///< Socket ID
+  OUT UINT8                     Channel:2;              ///< Channel ID
+  OUT UINT8                     Dimm:2;                 ///< DIMM ID
+  OUT UINT8                     DimmPresent:1;          ///< Dimm Present
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
+} MEM_DMI_INFO;
+
+/// DMI Type 19 - Memory Array Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes,
+                                                        ///< of a range of memory mapped to the
+                                                        ///< specified physical memory array.
+  OUT UINT32                    EndingAddr;             ///< The physical ending address of the
+                                                        ///< last kilobyte of a range of addresses
+                                                        ///< mapped to the specified physical memory array.
+  OUT UINT16                    MemoryArrayHandle;      ///< The handle, or instance number, associated
+                                                        ///< with the physical memory array to which this
+                                                        ///< address range is mapped.
+  OUT UINT8                     PartitionWidth;         ///< Identifies the number of memory devices that
+                                                        ///< form a single row of memory for the address
+                                                        ///< partition defined by this structure.
+} TYPE19_DMI_INFO;
+
+///DMI Type 20 - Memory Device Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryDeviceHandle;     ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
+                                                        ///< with the Memory Array Mapped Address structure to
+                                                        ///< which this device address range is mapped.
+  OUT UINT8                     PartitionRowPosition;   ///< Identifies the position of the referenced Memory
+                                                        ///< Device in a row of the address partition.
+  OUT UINT8                     InterleavePosition;     ///< The position of the referenced Memory Device in
+                                                        ///< an interleave.
+  OUT UINT8                     InterleavedDataDepth;   ///< The maximum number of consecutive rows from the
+                                                        ///< referenced Memory Device that are accessed in a
+                                                        ///< single interleaved transfer.
+} TYPE20_DMI_INFO;
+
+/// Collection of pointers to the DMI records
+typedef struct {
+  OUT TYPE4_DMI_INFO            T4[MAX_SOCKETS_SUPPORTED];    ///< Type 4 struc
+  OUT TYPE7_DMI_INFO            T7L1[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 1
+  OUT TYPE7_DMI_INFO            T7L2[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 2
+  OUT TYPE7_DMI_INFO            T7L3[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 3
+  OUT TYPE16_DMI_INFO           T16;                          ///< Type 16 struc
+  OUT TYPE17_DMI_INFO           T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+  OUT TYPE19_DMI_INFO           T19;                          ///< Type 19 struc
+  OUT TYPE20_DMI_INFO           T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
+} DMI_INFO;
+
+/**********************************************************************
+ * Interface call:  AllocateExecutionCache
+ **********************************************************************/
+#define MAX_CACHE_REGIONS    3
+
+/// AllocateExecutionCache sub param structure for cached memory region
+typedef struct {
+  IN OUT   UINT32               ExeCacheStartAddr;      ///< Start address
+  IN OUT   UINT32               ExeCacheSize;           ///< Size
+} EXECUTION_CACHE_REGION;
+
+/**********************************************************************
+ * Interface call:  AmdGetAvailableExeCacheSize
+ **********************************************************************/
+/// Get available Cache remain
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;              ///< Standard configuration header
+     OUT   UINT32               AvailableExeCacheSize;  ///< Remain size
+} AMD_GET_EXE_SIZE_PARAMS;
+
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+  IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+  );
+
+/// Selection type for core leveling
+typedef enum {
+  CORE_LEVEL_LOWEST,            ///< Level to lowest common denominator
+  CORE_LEVEL_TWO,               ///< Level to 2 cores
+  CORE_LEVEL_POWER_OF_TWO,      ///< Level to 1,2,4 or 8
+  CORE_LEVEL_NONE,              ///< Do no leveling
+  CORE_LEVEL_COMPUTE_UNIT,      ///< Level cores to one core per compute unit
+  CORE_LEVEL_ONE,               ///< Level to 1 core
+  CORE_LEVEL_THREE,             ///< Level to 3 cores
+  CORE_LEVEL_FOUR,              ///< Level to 4 cores
+  CORE_LEVEL_FIVE,              ///< Level to 5 cores
+  CORE_LEVEL_SIX,               ///< Level to 6 cores
+  CORE_LEVEL_SEVEN,             ///< Level to 7 cores
+  CORE_LEVEL_EIGHT,             ///< Level to 8 cores
+  CORE_LEVEL_NINE,              ///< Level to 9 cores
+  CORE_LEVEL_TEN,               ///< Level to 10 cores
+  CORE_LEVEL_ELEVEN,            ///< Level to 11 cores
+  CORE_LEVEL_TWELVE,            ///< Level to 12 cores
+  CORE_LEVEL_THIRTEEN,          ///< Level to 13 cores
+  CORE_LEVEL_FOURTEEN,          ///< Level to 14 cores
+  CORE_LEVEL_FIFTEEN,           ///< Level to 15 cores
+  CoreLevelModeMax              ///< Used for bounds checking
+} CORE_LEVELING_TYPE;
+
+
+
+
+
+/************************************************************************
+ *
+ *  AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Interface call:  AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitReset
+ **********************************************************************/
+/// AmdInitReset param structure
+typedef struct {
+  IN       AMD_CONFIG_PARAMS         StdHeader;        ///< Standard configuration header
+  IN       EXECUTION_CACHE_REGION    CacheRegion[3];   ///< The cached memory region
+  IN       AMD_HT_RESET_INTERFACE    HtConfig;         ///< The interface for Ht Recovery
+} AMD_RESET_PARAMS;
+
+AGESA_STATUS
+AmdInitReset (
+  IN OUT   AMD_RESET_PARAMS     *ResetParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitEarly
+ **********************************************************************/
+/// InitEarly param structure
+///
+/// Provide defaults or customizations to each service performed in AmdInitEarly.
+///
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       EXECUTION_CACHE_REGION CacheRegion[3];   ///< Execution Map Interface
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       AMD_HT_INTERFACE       HtConfig;         ///< HyperTransport Interface
+  IN       GNB_CONFIGURATION      GnbConfig;        ///< GNB configuration
+} AMD_EARLY_PARAMS;
+
+AGESA_STATUS
+AmdInitEarly (
+  IN OUT   AMD_EARLY_PARAMS     *EarlyParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitPost
+ **********************************************************************/
+/// AmdInitPost param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       MEM_PARAMETER_STRUCT   MemConfig;        ///< Memory post param
+} AMD_POST_PARAMS;
+
+AGESA_STATUS
+AmdInitPost (
+  IN OUT   AMD_POST_PARAMS      *PostParams         ///< Amd Cpu init param
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitEnv
+ **********************************************************************/
+/// AmdInitEnv param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;            ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;       ///< platform operational characteristics.
+  IN       GNB_ENV_CONFIGURATION  GnbEnvConfiguration;  ///< platform operational characteristics.
+} AMD_ENV_PARAMS;
+
+AGESA_STATUS
+AmdInitEnv (
+  IN OUT   AMD_ENV_PARAMS       *EnvParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitMid
+ **********************************************************************/
+/// AmdInitMid param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+} AMD_MID_PARAMS;
+
+AGESA_STATUS
+AmdInitMid (
+  IN OUT   AMD_MID_PARAMS       *MidParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitLate
+ **********************************************************************/
+/// AmdInitLate param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;              ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;         ///< platform operational characteristics.
+     OUT   DMI_INFO               *DmiTable;              ///< DMI Interface
+     OUT   VOID                   *AcpiPState;            ///< Acpi Pstate SSDT Table
+     OUT   VOID                   *AcpiSrat;              ///< SRAT Table
+     OUT   VOID                   *AcpiSlit;              ///< SLIT Table
+     OUT   VOID                   *AcpiWheaMce;           ///< WHEA MCE Table
+     OUT   VOID                   *AcpiWheaCmc;           ///< WHEA CMC Table
+     OUT   VOID                   *AcpiAlib;              ///< ACPI SSDT table with ALIB implementation
+} AMD_LATE_PARAMS;
+
+AGESA_STATUS
+AmdInitLate (
+  IN OUT   AMD_LATE_PARAMS      *LateParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitRecovery
+ **********************************************************************/
+/// CPU Recovery Parameters
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+} AMD_CPU_RECOVERY_PARAMS;
+
+/// AmdInitRecovery param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS        StdHeader;            ///< Standard configuration header
+  IN       MEM_PARAMETER_STRUCT     MemConfig;            ///< Memory post param
+  IN       EXECUTION_CACHE_REGION   CacheRegion[3];       ///< The cached memory region. And the max cache region is 3
+  IN       AMD_CPU_RECOVERY_PARAMS  CpuRecoveryParams;    ///< Params for CPU related recovery init.
+} AMD_RECOVERY_PARAMS;
+
+AGESA_STATUS
+AmdInitRecovery (
+  IN OUT   AMD_RECOVERY_PARAMS    *RecoveryParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitResume
+ **********************************************************************/
+/// AmdInitResume param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;      ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
+  IN       AMD_S3_PARAMS          S3DataBlock;    ///< Save state data
+} AMD_RESUME_PARAMS;
+
+AGESA_STATUS
+AmdInitResume (
+  IN       AMD_RESUME_PARAMS    *ResumeParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdS3LateRestore
+ **********************************************************************/
+/// AmdS3LateRestore param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       AMD_S3_PARAMS          S3DataBlock;      ///< Save state data
+} AMD_S3LATE_PARAMS;
+
+AGESA_STATUS
+AmdS3LateRestore (
+  IN OUT   AMD_S3LATE_PARAMS    *S3LateParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdS3Save
+ **********************************************************************/
+/// AmdS3Save param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+     OUT   AMD_S3_PARAMS          S3DataBlock;      ///< Standard header
+} AMD_S3SAVE_PARAMS;
+
+AGESA_STATUS
+AmdS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS    *AmdS3SaveParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdLateRunApTask
+ **********************************************************************/
+/**
+ * Entry point for AP tasking.
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+);
+
+//
+// General Services API
+//
+
+/**********************************************************************
+ * Interface service call:  AmdGetApicId
+ **********************************************************************/
+/// Request the APIC ID of a particular core.
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN       UINT8             Socket;           ///< The Core's Socket.
+  IN       UINT8             Core;             ///< The Core id.
+     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  ApicAddress is valid.
+     OUT   UINT8             ApicAddress;      ///< The Core's APIC ID.
+} AMD_APIC_PARAMS;
+
+/**
+ * Get a specified Core's APIC ID.
+ */
+AGESA_STATUS
+AmdGetApicId (
+  IN OUT AMD_APIC_PARAMS *AmdParamApic
+);
+
+/**********************************************************************
+ * Interface service call:  AmdGetPciAddress
+ **********************************************************************/
+/// Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN       UINT8             Socket;           ///< The Processor's socket
+  IN       UINT8             Module;           ///< The Module in that Processor
+     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  PciAddress is valid.
+     OUT   PCI_ADDR          PciAddress;       ///< The Processor's PCI Config Space address (Function 0, Register 0)
+} AMD_GET_PCI_PARAMS;
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+  IN OUT   AMD_GET_PCI_PARAMS *AmdParamGetPci
+);
+
+/**********************************************************************
+ * Interface service call:  AmdIdentifyCore
+ **********************************************************************/
+/// Request the identity (Socket, Module, Core) of the current Processor Core
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
+     OUT   UINT8             Socket;            ///< The current Core's Socket
+     OUT   UINT8             Module;            ///< The current Core's Processor Module
+     OUT   UINT8             Core;              ///< The current Core's core id.
+} AMD_IDENTIFY_PARAMS;
+
+/**
+ * "Who am I" for the current running core.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+  IN OUT  AMD_IDENTIFY_PARAMS *AmdParamIdentify
+);
+
+/**********************************************************************
+ * Interface service call:  AmdReadEventLog
+ **********************************************************************/
+/// An Event Log Entry.
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
+     OUT   UINT32            EventClass;        ///< The severity of this event, matches AGESA_STATUS.
+     OUT   UINT32            EventInfo;         ///< The unique event identifier, zero means "no event".
+     OUT   UINT32            DataParam1;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam2;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam3;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam4;        ///< Data specific to the Event.
+} EVENT_PARAMS;
+
+/**
+ * Read an Event from the Event Log.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+  IN       EVENT_PARAMS *Event
+);
+
+/**********************************************************************
+ * Interface service call:  AmdIdentifyDimm
+ **********************************************************************/
+/// Request the identity of dimm from system address
+
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS StdHeader;            ///< Standard configuration header
+  IN       UINT64            MemoryAddress;        ///< System Address that needs to be translated to dimm identification.
+  OUT      UINT8             SocketId;             ///< The socket on which the targeted address locates.
+  OUT      UINT8             MemChannelId;         ///< The channel on which the targeted address locates.
+  OUT      UINT8             DimmId;               ///< The dimm on which the targeted address locates.
+} AMD_IDENTIFY_DIMM;
+
+/**
+ * Get the dimm identification for the address.
+ */
+AGESA_STATUS
+AmdIdentifyDimm (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
+);
+
+/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
+/// and the option value.
+///
+typedef struct {
+  IN    UINT16 IdsNvId;           ///< Unified ID for IDS Setup Option.
+  OUT UINT16 IdsNvValue;        ///< The value of IDS Setup Option.
+} IDS_NV_ITEM;
+
+/// Data Structure for IDS CallOut Function
+typedef struct {
+  IN    AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN    IDS_NV_ITEM *IdsNvPtr;              ///< Memory Pointer of IDS NV Table
+  IN OUT UINTN Reserved;              ///< reserved
+} IDS_CALLOUT_STRUCT;
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+  );
+
+
+#define AGESA_IDS_DFT_VAL   0xFFFF                  ///<  Default value of every uninitlized NV item, the action for it will be ignored
+#define AGESA_IDS_NV_END    0xFFFF                  ///< Flag specify end of option structure
+/// WARNING: Don't change the comment below, it used as signature for script
+/// AGESA IDS NV ID Definitions
+typedef enum {
+  AGESA_IDS_EXT_ID_START                   = 0x0000,///< 0x0000                                                             specify the start of external NV id
+
+  AGESA_IDS_NV_UCODE,                               ///< 0x0001                                                            Enable or disable microcode patching
+
+  AGESA_IDS_NV_TARGET_PSTATE,                       ///< 0x0002                                                        Set the P-state required to be activated
+  AGESA_IDS_NV_POSTPSTATE,                          ///< 0x0003                                           Set the P-state required to be activated through POST
+
+  AGESA_IDS_NV_BANK_INTERLEAVE,                     ///< 0x0004                                                               Enable or disable Bank Interleave
+  AGESA_IDS_NV_CHANNEL_INTERLEAVE,                  ///< 0x0005                                                            Enable or disable Channel Interleave
+  AGESA_IDS_NV_NODE_INTERLEAVE,                     ///< 0x0006                                                               Enable or disable Node Interleave
+  AGESA_IDS_NV_MEMHOLE,                             ///< 0x0007                                                                  Enables or disable memory hole
+
+  AGESA_IDS_NV_SCRUB_REDIRECTION,                   ///< 0x0008                                           Enable or disable a write to dram with corrected data
+  AGESA_IDS_NV_DRAM_SCRUB,                          ///< 0x0009                                                   Set the rate of background scrubbing for DRAM
+  AGESA_IDS_NV_DCACHE_SCRUB,                        ///< 0x000A                                            Set the rate of background scrubbing for the DCache.
+  AGESA_IDS_NV_L2_SCRUB,                            ///< 0x000B                                           Set the rate of background scrubbing for the L2 cache
+  AGESA_IDS_NV_L3_SCRUB,                            ///< 0x000C                                           Set the rate of background scrubbing for the L3 cache
+  AGESA_IDS_NV_ICACHE_SCRUB,                        ///< 0x000D                                             Set the rate of background scrubbing for the Icache
+  AGESA_IDS_NV_SYNC_ON_ECC_ERROR,                   ///< 0x000E                                    Enable or disable the sync flood on un-correctable ECC error
+  AGESA_IDS_NV_ECC_SYMBOL_SIZE,                     ///< 0x000F                                                                             Set ECC symbol size
+
+  AGESA_IDS_NV_ALL_MEMCLKS,                         ///< 0x0010                                                      Enable or disable all memory clocks enable
+  AGESA_IDS_NV_DCT_GANGING_MODE,                    ///< 0x0011                                                                             Set the Ganged mode
+  AGESA_IDS_NV_DRAM_BURST_LENGTH32,                 ///< 0x0012                                                                    Set the DRAM Burst Length 32
+  AGESA_IDS_NV_MEMORY_POWER_DOWN,                   ///< 0x0013                                                        Enable or disable Memory power down mode
+  AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE,              ///< 0x0014                                                                  Set the Memory power down mode
+  AGESA_IDS_NV_DLL_SHUT_DOWN,                       ///< 0x0015                                                                   Enable or disable DLLShutdown
+  AGESA_IDS_NV_ONLINE_SPARE,                        ///< 0x0016      Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
+
+  AGESA_IDS_NV_HT_ASSIST,                           ///< 0x0017                                                                     Enable or Disable HT Assist
+  AGESA_IDS_NV_ATMMODE,                             ///< 0x0018                                                                      Enable or Disable ATM mode
+
+  AGESA_IDS_NV_HDTOUT,                              ///< 0x0019                                                                Enable or disable HDTOUT feature
+
+  AGESA_IDS_NV_HTLINKSOCKET,                        ///< 0x001A                                                                                  HT Link Socket
+  AGESA_IDS_NV_HTLINKPORT,                          ///< 0x001B                                                                                    HT Link Port
+  AGESA_IDS_NV_HTLINKFREQ,                          ///< 0x001C                                                                               HT Link Frequency
+  AGESA_IDS_NV_HTLINKWIDTHIN,                       ///< 0x001D                                                                                HT Link In Width
+  AGESA_IDS_NV_HTLINKWIDTHOUT,                      ///< 0x001E                                                                               HT Link Out Width
+
+  AGESA_IDS_NV_GNBHDAUDIOEN,                        ///< 0x001F                                                                  Enable or disable GNB HD Audio
+
+  AGESA_IDS_NV_CPB_EN,                              ///< 0x0020                                                                          Core Performance Boost
+
+  AGESA_IDS_NV_HTC_EN,                              ///< 0x0021                                                                                      HTC Enable
+  AGESA_IDS_NV_HTC_OVERRIDE,                        ///< 0x0022                                                                                    HTC Override
+  AGESA_IDS_NV_HTC_PSTATE_LIMIT,                    ///< 0x0023                                                                        HTC P-state limit select
+  AGESA_IDS_NV_HTC_TEMP_HYS,                        ///< 0x0024                                                                      HTC Temperature Hysteresis
+  AGESA_IDS_NV_HTC_ACT_TEMP,                        ///< 0x0025                                                                             HTC Activation Temp
+
+  AGESA_IDS_NV_POWER_POLICY,                        ///< 0x0026                                                                    Select Platform Power Policy
+  AGESA_IDS_EXT_ID_END,                             ///< 0x0027                                                               specify the end of external NV ID
+} IDS_EX_NV_ID;
+
+
+#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
+
+#endif // _AGESA_H_

Added: trunk/src/vendorcode/amd/agesa/AMD.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/AMD.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,482 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+#define AGESA_REVISION  "Arch2008"
+#define AGESA_ID        "AGESA"
+
+#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+//
+//
+// AGESA Types and Definitions
+//
+//
+#define LAST_ENTRY          0xFFFFFFFF
+#define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+/// The return status for all AGESA public services.
+///
+/// Services return the most severe status of any logged event.  Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+/// will have log entries with more detail.
+///
+typedef enum {
+  AGESA_SUCCESS = 0,             ///< The service completed normally. Info may be logged.
+  AGESA_UNSUPPORTED,             ///< The dispatcher or create struct had an unimplemented function requested.
+                                 ///<  Not logged.
+  AGESA_BOUNDS_CHK,              ///< A dynamic parameter was out of range and the service was not provided.
+                                 ///< Example, memory address not installed, heap buffer handle not found.
+                                 ///< Not Logged.
+  // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+  AGESA_ALERT,                   ///< An observed condition, but no loss of function.
+                                 ///<  See log.  Example, HT CRC.
+  AGESA_WARNING,                 ///< Possible or minor loss of function.  See Log.
+  AGESA_ERROR,                   ///< Significant loss of function, boot may be possible.  See Log.
+  AGESA_CRITICAL,                ///< Continue boot only to notify user.  See Log.
+  AGESA_FATAL,                   ///< Halt booting.  See Log, however Fatal errors pertaining to heap problems
+                                 ///< may not be able to reliably produce log events.
+  AgesaStatusMax                 ///< Not a status, for limit checking.
+} AGESA_STATUS;
+
+/// For checking whether a status is at or above the mandatory log level.
+#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
+
+/**
+ * Callout method to the host environment.
+ *
+ * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
+ *
+ * @param[in]        Function      The specific callout function being invoked.
+ * @param[in]        FcnData       Function specific data item.
+ * @param[in,out]    ConfigPtr     Reference to Callout params.
+ */
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (
+  IN       UINT32  Function,
+  IN       UINTN   FcnData,
+  IN OUT   VOID    *ConfigPtr
+  );
+
+typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+  PreMemHeap = 0,                                           ///< Create heap in cache.
+  PostMemDram,                                              ///< Create heap in memory.
+  ByHost                                                    ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
+  AccessWidth16,                                            ///< Access width is 16 bits.
+  AccessWidth32,                                            ///< Access width is 32 bits.
+  AccessWidth64,                                            ///< Access width is 64 bits.
+
+  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
+  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
+  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
+  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+/// AGESA struct name
+typedef enum {
+  // AGESA BASIC FUNCTIONS
+  AMD_INIT_RECOVERY = 0x00020000,                           ///< AmdInitRecovery entry point handle
+  AMD_CREATE_STRUCT,                                        ///< AmdCreateStruct handle
+  AMD_INIT_EARLY,                                           ///< AmdInitEarly entry point handle
+  AMD_INIT_ENV,                                             ///< AmdInitEnv entry point handle
+  AMD_INIT_LATE,                                            ///< AmdInitLate entry point handle
+  AMD_INIT_MID,                                             ///< AmdInitMid entry point handle
+  AMD_INIT_POST,                                            ///< AmdInitPost entry point handle
+  AMD_INIT_RESET,                                           ///< AmdInitReset entry point handle
+  AMD_INIT_RESUME,                                          ///< AmdInitResume entry point handle
+  AMD_RELEASE_STRUCT,                                       ///< AmdReleaseStruct handle
+  AMD_S3LATE_RESTORE,                                       ///< AmdS3LateRestore entry point handle
+  AMD_S3_SAVE,                                              ///< AmdS3Save entry point handle
+  AMD_GET_APIC_ID,                                          ///< AmdGetApicId entry point handle
+  AMD_GET_PCI_ADDRESS,                                      ///< AmdGetPciAddress entry point handle
+  AMD_IDENTIFY_CORE,                                        ///< AmdIdentifyCore general service handle
+  AMD_READ_EVENT_LOG,                                       ///< AmdReadEventLog general service handle
+  AMD_GET_EXECACHE_SIZE,                                    ///< AmdGetAvailableExeCacheSize general service handle
+  AMD_LATE_RUN_AP_TASK,                                     ///< AmdLateRunApTask entry point handle
+  AMD_IDENTIFY_DIMMS                                        ///< AmdIdentifyDimm general service handle
+} AGESA_STRUCT_NAME;
+
+  /*  ResetType constant values */
+#define WARM_RESET_WHENEVER 1
+#define COLD_RESET_WHENEVER 2
+#define WARM_RESET_IMMEDIATELY 3
+#define COLD_RESET_IMMEDIATELY 4
+
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+/// For internal AGESA naming conventions, see @ref amdconfigparamname .
+typedef struct {
+  IN       UINT32          ImageBasePtr;     ///< The AGESA Image base address.
+  IN       UINT32          Func;             ///< The service desired
+  IN       UINT32          AltImageBasePtr;  ///< Alternate Image location
+  IN       CALLOUT_ENTRY   CalloutPtr;       ///< For Callout from AGESA
+  IN       UINT8           HeapStatus;       ///< For heap status from boot time slide.
+  IN       UINT64          HeapBasePtr;      ///< Location of the heap
+  IN OUT   UINT8           Reserved[7];      ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// Create Struct Interface.
+typedef struct {
+  IN       AMD_CONFIG_PARAMS   StdHeader;          ///< Standard configuration header
+  IN       AGESA_STRUCT_NAME   AgesaFunctionName;  ///< The service to init
+  IN       ALLOCATION_METHOD   AllocationMethod;   ///< How to handle buffer allocation
+  IN OUT   UINT32              NewStructSize;      ///< The size of the allocated data, in for ByHost, else out only.
+  IN OUT   VOID                *NewStructPtr;      ///< The struct for the service.
+                                                   ///< The struct to init for ByHost allocation,
+                                                   ///< the initialized struct on return.
+} AMD_INTERFACE_PARAMS;
+
+#define FUNC_0    0   // bit-placed for PCI address creation
+#define FUNC_1    1
+#define FUNC_2    2
+#define FUNC_3    3
+#define FUNC_4    4
+#define FUNC_5    5
+#define FUNC_6    6
+#define FUNC_7    7
+
+/// AGESA Binary module header structure
+typedef struct {
+  IN  UINT32  Signature;                          ///< Binary Signature
+  IN  CHAR8   CreatorID[8];                       ///< 8 characters ID
+  IN  CHAR8   Version[12];                        ///< 12 characters version
+  IN  UINT32  ModuleInfoOffset;                   ///< Offset of module
+  IN  UINT32  EntryPointAddress;                  ///< Entry address
+  IN  UINT32  ImageBase;                          ///< Image base
+  IN  UINT32  RelocTableOffset;                   ///< Relocate Table offset
+  IN  UINT32  ImageSize;                          ///< Size
+  IN  UINT16  Checksum;                           ///< Checksum
+  IN  UINT8   ImageType;                          ///< Type
+  IN  UINT8   V_Reserved;                         ///< Reserved
+} AMD_IMAGE_HEADER;
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+  IN  UINT32          ModuleHeaderSignature;      ///< Module signature
+  IN  CHAR8           ModuleIdentifier[8];        ///< 8 characters ID
+  IN  CHAR8           ModuleVersion[12];          ///< 12 characters version
+  IN  VOID            *ModuleDispatcher;          ///< A pointer point to dispatcher
+  IN  struct _AMD_MODULE_HEADER  *NextBlock;      ///< Next module header link
+} AMD_MODULE_HEADER;
+
+// AMD_CODE_HEADER Signatures.
+#define AGESA_CODE_SIGNATURE  {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
+#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
+#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
+
+/// AGESA_CODE_SIGNATURE
+typedef struct {
+  IN  CHAR8   Signature[8];                       ///< code header Signature
+  IN  CHAR8   ComponentName[8];                   ///< 8 character name of the code module
+  IN  CHAR8   Version[12];                        ///< 12 character version string
+  IN  CHAR8   TerminatorNull;                     ///< null terminated string
+  IN  CHAR8   VerReserved[7];                     ///< reserved space
+} AMD_CODE_HEADER;
+
+/// Extended PCI address format
+typedef struct {
+  IN OUT  UINT32      Register:12;                ///< Register offset
+  IN OUT  UINT32      Function:3;                 ///< Function number
+  IN OUT  UINT32      Device:5;                   ///< Device number
+  IN OUT  UINT32      Bus:8;                      ///< Bus number
+  IN OUT  UINT32      Segment:4;                  ///< Segment
+} EXT_PCI_ADDR;
+
+/// Union type for PCI address
+typedef union _PCI_ADDR {
+  IN  UINT32          AddressValue;               ///< Formal address
+  IN  EXT_PCI_ADDR    Address;                    ///< Extended address
+} PCI_ADDR;
+
+//   SBDFO - Segment Bus Device Function Offset
+//   31:28   Segment (4-bits)
+//   27:20   Bus     (8-bits)
+//   19:15   Device  (5-bits)
+//   14:12   Function(3-bits)
+//   11:00   Offset  (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+                   (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/// CPUID data received registers format
+typedef struct {
+  OUT UINT32          EAX_Reg;                    ///< CPUID instruction result in EAX
+  OUT UINT32          EBX_Reg;                    ///< CPUID instruction result in EBX
+  OUT UINT32          ECX_Reg;                    ///< CPUID instruction result in ECX
+  OUT UINT32          EDX_Reg;                    ///< CPUID instruction result in EDX
+} CPUID_DATA;
+
+/// HT frequency for external callbacks
+typedef enum {
+  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
+  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
+  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
+  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
+  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
+  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
+  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
+  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
+  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
+  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
+  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
+  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
+  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
+  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
+  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
+  HT_FREQUENCY_3200M         = 19,                ///< HT speed 3200 for external callbacks
+  HT_FREQUENCY_MAX                                ///< Limit check.
+} HT_FREQUENCIES;
+// The minimum HT3 frequency
+#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
+
+#ifndef BIT0
+  #define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+  #define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+  #define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+  #define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+  #define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+  #define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+  #define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+  #define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+  #define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+  #define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+  #define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+  #define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+  #define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+  #define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+  #define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+  #define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+  #define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+  #define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+  #define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+  #define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+  #define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+  #define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+  #define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+  #define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+  #define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+  #define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+  #define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+  #define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+  #define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+  #define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+  #define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+  #define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+  #define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+  #define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+  #define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+  #define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+  #define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+  #define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+  #define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+  #define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+  #define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+  #define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+  #define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+  #define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+  #define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+  #define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+  #define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+  #define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+  #define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+  #define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+  #define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+  #define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+  #define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+  #define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+  #define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+  #define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+  #define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+  #define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+  #define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+  #define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+  #define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+  #define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+  #define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+  #define BIT63       0x8000000000000000ull
+#endif
+
+#endif // _AMD_H_

Added: trunk/src/vendorcode/amd/agesa/Dispatcher.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Dispatcher.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,54 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Pushhigh Interface
+ *
+ * Contains interface to Pushhigh entry
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Legacy
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _DISPATCHER_H_
+#define _DISPATCHER_H_
+
+// AGESA function prototypes
+AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
+AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
+
+#endif // _DISPATCHER_H_

Added: trunk/src/vendorcode/amd/agesa/Include/AdvancedApi.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/AdvancedApi.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,168 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Advanced API Interface for HT, Memory and CPU
+ *
+ * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
+ * would be required by the basic interface implementations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+
+#ifndef _ADVANCED_API_H_
+#define _ADVANCED_API_H_
+
+/*----------------------------------------------------------------------------
+ *                           HT FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in]   StdHeader       Opaque handle to standard config header
+ * @param[in]   AmdHtInterface  HT Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+AmdHtInterfaceConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_HT_INTERFACE     *AmdHtInterface
+  );
+
+/**
+ * The top level external interface for Hypertransport Initialization.
+ *
+ * Create our initial internal state, initialize the coherent fabric,
+ * initialize the non-coherent chains, and perform any required fabric tuning or
+ * optimization.
+ *
+ * @param[in]   StdHeader              Opaque handle to standard config header
+ * @param[in]   PlatformConfiguration  The platform configuration options.
+ * @param[in]   AmdHtInterface         HT Interface structure.
+ *
+ * @retval      AGESA_SUCCESS     Only information events logged.
+ * @retval      AGESA_ALERT       Sync Flood or CRC error logged.
+ * @retval      AGESA_WARNING     Example: expected capability not found
+ * @retval      AGESA_ERROR       logged events indicating some devices may not be available
+ * @retval      AGESA_FATAL       Mixed Family or MP capability mismatch
+ *
+ */
+AGESA_STATUS
+AmdHtInitialize (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfiguration,
+  IN       AMD_HT_INTERFACE       *AmdHtInterface
+  );
+
+/*----------------------------------------------------------------------------
+ *                        HT Recovery   FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ */
+AGESA_STATUS
+AmdHtResetConstructor (
+  IN       AMD_CONFIG_PARAMS         *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE    *AmdHtResetInterface
+  );
+
+/**
+ * Initialize HT at Reset for both Normal and Recovery.
+ *
+ */
+AGESA_STATUS
+AmdHtInitReset (
+  IN       AMD_CONFIG_PARAMS        *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE   *AmdHtResetInterface
+  );
+
+/**
+ * Initialize the Node and Socket maps for an AP Core.
+ *
+ */
+AGESA_STATUS
+AmdHtInitRecovery (
+  IN       AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+///----------------------------------------------------------------------------
+///                          MEMORY FUNCTIONS PROTOTYPE
+///
+///----------------------------------------------------------------------------
+
+AGESA_STATUS
+AmdMemRecovery (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+AGESA_STATUS
+AmdMemAuto (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+AmdMemInitDataStructDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT  PLATFORM_CONFIGURATION   *PlatFormConfig
+  );
+
+VOID
+memDefRet (
+  VOID
+  );
+
+BOOLEAN
+memDefTrue (
+  VOID
+  );
+
+BOOLEAN
+memDefFalse (
+  VOID
+  );
+#endif // _ADVANCED_API_H_

Added: trunk/src/vendorcode/amd/agesa/Include/BrazosInstall.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/BrazosInstall.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Brazos platform solution
+ *
+ * This file generates the defaults tables for the "Brazos" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 40817 $   @e \$Date: 2010-10-28 03:28:12 +0800 (Thu, 28 Oct 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "BrazosPI"
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'O', 'n', 't', 'a', 'r', 'o', 'P', 'I'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '1', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+
+// The Brazos solution is defined to be family 0x14 in the FT1 socket.
+#define INSTALL_FT1_SOCKET_SUPPORT      TRUE
+#define INSTALL_FAMILY_14_SUPPORT       TRUE
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0)
+#define DFLT_SCRUB_L2_RATE              (0)
+#define DFLT_SCRUB_L3_RATE              (0)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE              (5000)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+

Added: trunk/src/vendorcode/amd/agesa/Include/CommonReturns.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/CommonReturns.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,125 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Common Return routines.
+ *
+ * Routines which do nothing, returning a result (preferably some version of zero) which
+ * is consistent with "do nothing" or "default".  Useful for function pointer tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _COMMON_RETURNS_H_
+#define _COMMON_RETURNS_H_
+
+
+/**
+* Return True
+*
+* @retval True    Default case, no special action
+*/
+BOOLEAN
+CommonReturnTrue (void);
+
+/**
+* Return False.
+*
+* @retval FALSE    Default case, no special action
+*/
+BOOLEAN
+CommonReturnFalse (void);
+
+/**
+ * Return (UINT8)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT8
+CommonReturnZero8 (void);
+
+/**
+ * Return (UINT32)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT32
+CommonReturnZero32 (void);
+
+/**
+ * Return (UINT64)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT64
+CommonReturnZero64 (void);
+
+/**
+ * Return NULL
+ *
+ * @retval NULL    pointer to nothing
+ */
+VOID *
+CommonReturnNULL (void);
+
+/**
+* Return AGESA_SUCCESS.
+*
+* @retval AGESA_SUCCESS Success.
+*/
+AGESA_STATUS
+CommonReturnAgesaSuccess (void);
+
+/**
+ * Do Nothing.
+ *
+ */
+VOID
+CommonVoid (void);
+
+/**
+ * ASSERT if this routine is called.
+ *
+ */
+VOID
+CommonAssert (void);
+
+#endif // _COMMON_RETURNS_H_

Added: trunk/src/vendorcode/amd/agesa/Include/DanNiInstall.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/DanNiInstall.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,117 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Danube + Nile platform solution
+ *
+ * This file generates the defaults tables for the "DanNi" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "DanNiPI "
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
+
+
+// The DanNi solution is defined to be family 0x10 in the S1g4 and ASB2 sockets.
+#define INSTALL_S1G4_SOCKET_SUPPORT      TRUE
+#define INSTALL_ASB2_SOCKET_SUPPORT      TRUE
+#define INSTALL_FAMILY_10_SUPPORT        TRUE
+
+#ifdef BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
+  #if BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT == TRUE
+    #undef INSTALL_S1G4_SOCKET_SUPPORT
+    #define INSTALL_S1G4_SOCKET_SUPPORT     FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
+  #if BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT == TRUE
+    #undef INSTALL_ASB2_SOCKET_SUPPORT
+    #define INSTALL_ASB2_SOCKET_SUPPORT     FALSE
+  #endif
+#endif
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0)
+#define DFLT_SCRUB_L2_RATE              (0x10)
+#define DFLT_SCRUB_L3_RATE              (0x10)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (5000)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+

Added: trunk/src/vendorcode/amd/agesa/Include/DanubeInstall.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/DanubeInstall.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Danube platform solution
+ *
+ * This file generates the defaults tables for the "Danube" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "DanNiPI "
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
+
+
+// The Danube solution is defined to be family 0x10 in the S1g4 socket.
+#define INSTALL_S1G4_SOCKET_SUPPORT      TRUE
+#define INSTALL_FAMILY_10_SUPPORT        TRUE
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0)
+#define DFLT_SCRUB_L2_RATE              (0x10)
+#define DFLT_SCRUB_L3_RATE              (0)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (5000)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+

Added: trunk/src/vendorcode/amd/agesa/Include/DevTestInstall.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/DevTestInstall.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,111 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a DevTest platform solution
+ *
+ * This file generates the defaults tables for the "DevTest" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "DevTest "
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'D', 'e', 'v', 'T', 'e', 's', 't', ' '}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
+
+
+// The DevTest solution is defined to be everything that AGESA supports.
+#define INSTALL_C32_SOCKET_SUPPORT       TRUE
+#define INSTALL_G34_SOCKET_SUPPORT       TRUE
+#define INSTALL_S1G4_SOCKET_SUPPORT      TRUE
+#define INSTALL_ASB2_SOCKET_SUPPORT      TRUE
+#define INSTALL_FS1_SOCKET_SUPPORT       TRUE
+#define INSTALL_FM1_SOCKET_SUPPORT       TRUE
+#define INSTALL_FT1_SOCKET_SUPPORT       TRUE
+#define INSTALL_AM3_SOCKET_SUPPORT       TRUE
+#define INSTALL_FAMILY_10_SUPPORT        TRUE
+#define INSTALL_FAMILY_12_SUPPORT        TRUE
+#define INSTALL_FAMILY_14_SUPPORT        TRUE
+#define INSTALL_FAMILY_15_SUPPORT        TRUE
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0xFF)
+#define DFLT_SCRUB_L2_RATE              (0x10)
+#define DFLT_SCRUB_L3_RATE              (0x10)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (2500)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+

Added: trunk/src/vendorcode/amd/agesa/Include/DragonInstall.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/DragonInstall.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Dragon platform solution
+ *
+ * This file generates the defaults tables for the "Dragon" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "DragonPI"
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'D', 'r', 'a', 'g', 'o', 'n', 'P', 'I'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
+
+
+// The Danube solution is defined to be family 0x10 in the AM3 socket.
+#define INSTALL_AM3_SOCKET_SUPPORT       TRUE
+#define INSTALL_FAMILY_10_SUPPORT        TRUE
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0)
+#define DFLT_SCRUB_L2_RATE              (0)
+#define DFLT_SCRUB_L3_RATE              (0)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (2500)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+

Added: trunk/src/vendorcode/amd/agesa/Include/Filecode.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/Filecode.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,849 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Collectively assign unique filecodes for assert and debug to each source file.
+ *
+ * Publish values for decorated filenames, which can be used for
+ * ASSERT and debug support using a preprocessor define like:
+ * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
+ * This file serves as a reference for debugging to associate the code and filename.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 40742 $   @e \$Date: 2010-10-27 04:04:08 +0800 (Wed, 27 Oct 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _FILECODE_H_
+#define _FILECODE_H_
+
+#define UNASSIGNED_FILE_FILECODE                                         (0xFFFF)
+
+/// For debug use in any Platform's options C file.
+/// Can be reused for platforms and image builds, since only one options file can be built.
+#define PLATFORM_SPECIFIC_OPTIONS_FILECODE                               (0xBBBB)
+
+
+#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE                          (0xA001)
+#define PROC_GNB_GFX_FAMILY_0X12_F12GFXSERVICES_FILECODE                 (0xA002)
+#define PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE                 (0xA003)
+#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE                              (0xA004)
+#define PROC_GNB_GFX_GFXDEBUGBAR_FILECODE                                (0xA005)
+#define PROC_GNB_GFX_GFXGMCINIT_FILECODE                                 (0xA006)
+#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE                           (0xA010)
+#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE                           (0xA011)
+#define PROC_GNB_GFX_GFXINITATPOST_FILECODE                              (0xA012)
+#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE                 (0xA013)
+#define PROC_GNB_GFX_GFXLIB_FILECODE                                     (0xA014)
+#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE                             (0xA015)
+#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE                              (0xA016)
+#define PROC_GNB_GNBINITATEARLY_FILECODE                                 (0xA017)
+#define PROC_GNB_GNBINITATENV_FILECODE                                   (0xA020)
+#define PROC_GNB_GNBINITATLATE_FILECODE                                  (0xA021)
+#define PROC_GNB_GNBINITATMID_FILECODE                                   (0xA022)
+#define PROC_GNB_GNBINITATPOST_FILECODE                                  (0xA023)
+#define PROC_GNB_GNBINITATRESET_FILECODE                                 (0xA024)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE                    (0xA025)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE              (0xA026)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE                (0xA027)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE               (0xA028)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE              (0xA029)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE                 (0xA02A)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE              (0xA030)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE            (0xA031)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE      (0xA032)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE      (0xA033)
+#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE          (0xA034)
+#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE                 (0xA035)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE           (0xA036)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE            (0xA037)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE          (0xA038)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE          (0xA039)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE              (0xA03A)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE     (0xA03B)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE   (0xA03C)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE       (0xA03D)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE       (0xA03E)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE        (0xA03F)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE      (0xA041)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE         (0xA043)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESBLINK_FILECODE            (0xA044)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE   (0xA045)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE             (0xA046)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE  (0xA047)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE        (0xA048)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE     (0xA049)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE         (0xA04A)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE      (0xA04B)
+#define PROC_GNB_NB_FAMILY_0X12_F12NBPOWERGATE_FILECODE                  (0xA04C)
+#define PROC_GNB_NB_FAMILY_0X12_F12NBSERVICES_FILECODE                   (0xA04D)
+#define PROC_GNB_NB_FAMILY_0X12_F12NBSMU_FILECODE                        (0xA04E)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKNCLKRATIO_FILECODE              (0xA04F)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBPOWERGATE_FILECODE                  (0xA050)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE                   (0xA051)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBSMU_FILECODE                        (0xA052)
+#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE                         (0xA053)
+#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE                           (0xA054)
+#define PROC_GNB_NB_FAMILY_0X12_F12NBLCLKDPM_FILECODE                    (0xA055)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKDPM_FILECODE                    (0xA056)
+#define PROC_GNB_NB_NBCONFIGDATA_FILECODE                                (0xA060)
+#define PROC_GNB_NB_NBINIT_FILECODE                                      (0xA061)
+#define PROC_GNB_NB_NBINITATEARLY_FILECODE                               (0xA062)
+#define PROC_GNB_NB_NBINITATENV_FILECODE                                 (0xA063)
+#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE                            (0xA070)
+#define PROC_GNB_NB_NBINITATPOST_FILECODE                                (0xA071)
+#define PROC_GNB_NB_NBINITATRESET_FILECODE                               (0xA072)
+#define PROC_GNB_NB_NBPOWERMGMT_FILECODE                                 (0xA073)
+#define PROC_GNB_NB_NBSMULIB_FILECODE                                    (0xA074)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEALIB_FILECODE                   (0xA075)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE          (0xA076)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXSERVICES_FILECODE        (0xA077)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPHYSERVICES_FILECODE            (0xA078)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPIFSERVICES_FILECODE            (0xA079)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEWRAPPERSERVICES_FILECODE        (0xA07A)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE                   (0xA07D)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE          (0xA07E)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE        (0xA07F)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE            (0xA080)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE            (0xA081)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE        (0xA082)
+#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE                     (0xA083)
+#define PROC_GNB_PCIE_PCIEINIT_FILECODE                                  (0xA084)
+#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE                       (0xA085)
+#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE                             (0xA086)
+#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE                        (0xA087)
+#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE                            (0xA088)
+#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE                              (0xA089)
+#define PROC_GNB_PCIE_PCIEMISCLIB_FILECODE                               (0xA08A)
+#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE                              (0xA08B)
+#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE                          (0xA08C)
+#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE              (0xA08D)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE              (0xA08E)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE             (0xA08F)
+
+#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE                           (0xAE01)
+#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE                        (0xAE02)
+
+// FCH
+#define PROC_COMMON_AMDFCH_FILECODE                                      (0xB000)
+#define PROC_FCH_AZALIA_AZALIA_FILECODE                                  (0xB001)
+#define PROC_FCH_AZALIA_AZALIARESET_FILECODE                             (0xB002)
+#define PROC_FCH_COMMON_ACPILIB_FILECODE                                 (0xB010)
+#define PROC_FCH_COMMON_AMDSBLIB_FILECODE                                (0xB011)
+#define PROC_FCH_COMMON_FCHCOMMON_FILECODE                               (0xB012)
+#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE                            (0xB013)
+#define PROC_FCH_COMMON_MEMLIB_FILECODE                                  (0xB014)
+#define PROC_FCH_COMMON_PCILIB_FILECODE                                  (0xB015)
+#define PROC_FCH_COMMON_SBPELIB_FILECODE                                 (0xB016)
+#define PROC_FCH_GEC_FAMILY_HUDSON2_GEC_FILECODE                        (0xB020)
+#define PROC_FCH_GEC_FAMILY_HUDSON2_GECRESET_FILECODE                   (0xB021)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPI_FILECODE                  (0xB030)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPIRESET_FILECODE             (0xB031)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HWM_FILECODE                        (0xB032)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HWMRESET_FILECODE                   (0xB033)
+#define PROC_FCH_IDE_IDE_FILECODE                                        (0xB040)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_IMC_FILECODE                        (0xB050)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCLIB_FILECODE                     (0xB051)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCRESET_FILECODE                   (0xB052)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_SBEC_FILECODE                       (0xB053)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_SBECRESET_FILECODE                  (0xB054)
+#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE                         (0xB060)
+#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE                           (0xB061)
+#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE                         (0xB062)
+#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE                           (0xB063)
+#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE                          (0xB064)
+#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE                           (0xB065)
+#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE                            (0xB066)
+#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE                      (0xB067)
+#define PROC_FCH_IR_IR_FILECODE                                          (0xB070)
+#define PROC_FCH_PCIB_PCIB_FILECODE                                      (0xB080)
+#define PROC_FCH_PCIB_PCIBRESET_FILECODE                                 (0xB081)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_AB_FILECODE                        (0xB090)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_ABRESET_FILECODE                   (0xB091)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPP_FILECODE                       (0xB092)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPHP_FILECODE                     (0xB093)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPLIB_FILECODE                    (0xB094)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPRESET_FILECODE                  (0xB095)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIE_FILECODE                      (0xB096)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIERESET_FILECODE                 (0xB097)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCI_FILECODE                      (0xB0A0)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCILIB_FILECODE                   (0xB0A1)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCI_FILECODE                  (0xB0A2)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCILIB_FILECODE               (0xB0A3)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_RAID_FILECODE                      (0xB0A4)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_RAIDLIB_FILECODE                   (0xB0A5)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_SATA_FILECODE                      (0xB0A6)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDE_FILECODE                   (0xB0A7)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDELIB_FILECODE                (0xB0A8)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_SATALIB_FILECODE                   (0xB0A9)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_SATARESET_FILECODE                 (0xB0AA)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCI_FILECODE                     (0xB0B0)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCIRESET_FILECODE                (0xB0B1)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCI_FILECODE                     (0xB0B2)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCIRESET_FILECODE                (0xB0B3)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USB_FILECODE                      (0xB0B4)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USBRESET_FILECODE                 (0xB0B5)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCI_FILECODE                     (0xB0B6)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCIRESET_FILECODE                (0xB0B7)
+#define PROC_FCH_SD_SD_FILECODE                                          (0xB0C0)
+#define PROC_FCH_SPI_LPC_FILECODE                                        (0xB0D0)
+#define PROC_FCH_SPI_LPCRESET_FILECODE                                   (0xB0D1)
+#define PROC_FCH_SPI_SPI_FILECODE                                        (0xB0D2)
+#define PROC_FCH_SPI_SPIRESET_FILECODE                                   (0xB0D3)
+
+#define UEFI_DXE_AMDSBDXE_AMDSBDXE_FILECODE                              (0xB200)
+#define UEFI_DXE_AMDSBWHEA_AMDSBWHEA_FILECODE                            (0xB210)
+#define UEFI_DXE_AMDSBWHEA_BERTTABLE_FILECODE                            (0xB211)
+#define UEFI_DXE_AMDSBWHEA_EINJTABLE_FILECODE                            (0xB212)
+#define UEFI_DXE_AMDSBWHEA_ERSTTABLE_FILECODE                            (0xB213)
+#define UEFI_DXE_AMDSBWHEA_HESTTABLE_FILECODE                            (0xB214)
+#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE                              (0xB220)
+#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE                     (0xB221)
+#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE                       (0xB222)
+#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE                (0xB230)
+#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE                          (0xB240)
+#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHDXECOMMON_FILECODE              (0xB250)
+#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHSMMLIB_FILECODE                 (0xB251)
+#define UEFI_LIBRARY_DECCAN_FCHDXELIB_FCHDXELIB_FILECODE                 (0xB252)
+#define UEFI_PEI_AMDSBPEI_AMDSBPEI_FILECODE                              (0xB260)
+#define UEFI_PEI_AMDSBPEI_SBRESET_FILECODE                               (0xB261)
+#define UEFI_PEI_AMDSBPEI_SBSTALL_FILECODE                               (0xB262)
+#define UEFI_PEI_SMBUS_SMBUS_FILECODE                                    (0xB270)
+#define UEFI_SMM_AMDSBSMM_AMDSBSMM_FILECODE                              (0xB280)
+#define UEFI_SMM_AMDSBSMM_GECSMI_FILECODE                                (0xB281)
+#define UEFI_SMM_AMDSBSMM_GPESMI_FILECODE                                (0xB282)
+#define UEFI_SMM_AMDSBSMM_IOTRAPSMI_FILECODE                             (0xB283)
+#define UEFI_SMM_AMDSBSMM_MISCSMI_FILECODE                               (0xB284)
+#define UEFI_SMM_AMDSBSMM_PERIODICTIMERSMI_FILECODE                      (0xB285)
+#define UEFI_SMM_AMDSBSMM_POWERBUTTONSMI_FILECODE                        (0xB286)
+#define UEFI_SMM_AMDSBSMM_SWSMI_FILECODE                                 (0xB287)
+#define UEFI_SMM_AMDSBSMM_SXSMI_FILECODE                                 (0xB288)
+#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE                               (0xB2A0)
+#define UEFI_SMM_AMDSBSMMDISPATCHER_AMDSBSMMDISPATCHER_FILECODE                     (0xB290)
+#define UEFI_SMM_AMDSBSMMGECROMDISPATCHER_AMDSBSMMGECROMDISPATCHER_FILECODE         (0xB291)
+#define UEFI_SMM_AMDSBSMMGPEDISPATCHER_AMDSBSMMGPEDISPATCHER_FILECODE               (0xB292)
+#define UEFI_SMM_AMDSBSMMIOTRAPDISPATCHER_AMDSBSMMIOTRAPDISPATCHER_FILECODE         (0xB293)
+#define UEFI_SMM_AMDSBSMMMISCDISPATCHER_AMDSBSMMMISCDISPATCHER_FILECODE             (0xB294)
+#define UEFI_SMM_AMDSBSMMPERIODICALDISPATCHER_AMDSBSMMPERIODICALDISPATCHER_FILECODE (0xB295)
+#define UEFI_SMM_AMDSBSMMPWRBTNDISPATCHER_AMDSBSMMPWRBTNDISPATCHER_FILECODE         (0xB296)
+#define UEFI_SMM_AMDSBSMMSWDISPATCHER_AMDSBSMMSWDISPATCHER_FILECODE                 (0xB297)
+#define UEFI_SMM_AMDSBSMMSXDISPATCHER_AMDSBSMMSXDISPATCHER_FILECODE                 (0xB298)
+#define UEFI_SMM_AMDSBSMMUSBDISPATCHER_AMDSBSMMUSBDISPATCHER_FILECODE               (0xB299)
+
+#define LIB_AMDLIB_FILECODE                                              (0xC001)
+
+#define LEGACY_PROC_AGESACALLOUTS_FILECODE                               (0xC010)
+#define LEGACY_PROC_HOBTRANSFER_FILECODE                                 (0xC011)
+#define LEGACY_PROC_DISPATCHER_FILECODE                                  (0xC012)
+
+#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE            (0xC120)
+
+#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE                (0xC140)
+#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE      (0xC141)
+#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE                (0xC142)
+#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE                               (0xC162)
+
+#define PROC_COMMON_AMDINITEARLY_FILECODE                                (0xC020)
+#define PROC_COMMON_AMDINITENV_FILECODE                                  (0xC021)
+#define PROC_COMMON_AMDINITLATE_FILECODE                                 (0xC022)
+#define PROC_COMMON_AMDINITMID_FILECODE                                  (0xC023)
+#define PROC_COMMON_AMDINITPOST_FILECODE                                 (0xC024)
+#define PROC_COMMON_AMDINITRECOVERY_FILECODE                             (0xC025)
+#define PROC_COMMON_AMDINITRESET_FILECODE                                (0xC026)
+#define PROC_COMMON_AMDINITRESUME_FILECODE                               (0xC027)
+#define PROC_COMMON_AMDS3LATERESTORE_FILECODE                            (0xC028)
+#define PROC_COMMON_AMDS3SAVE_FILECODE                                   (0xC029)
+#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE                            (0xC02A)
+
+#define PROC_COMMON_COMMONRETURNS_FILECODE                               (0xC0C0)
+#define PROC_COMMON_CREATESTRUCT_FILECODE                                (0xC0D0)
+#define PROC_COMMON_COMMONINITS_FILECODE                                 (0xC0F0)
+#define PROC_COMMON_S3RESTORESTATE_FILECODE                              (0xC0F8)
+#define PROC_COMMON_S3SAVESTATE_FILECODE                                 (0xC0F9)
+
+#define PROC_CPU_CPUAPICUTILITIES_FILECODE                               (0xC401)
+#define PROC_CPU_CPUBRANDID_FILECODE                                     (0xC402)
+#define PROC_CPU_TABLE_FILECODE                                          (0xC403)
+#define PROC_CPU_CPUEARLYINIT_FILECODE                                   (0xC405)
+#define PROC_CPU_CPUEVENTLOG_FILECODE                                    (0xC406)
+#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE                           (0xC407)
+#define PROC_CPU_CPUGENERALSERVICES_FILECODE                             (0xC408)
+#define PROC_CPU_CPUINITEARLYTABLE_FILECODE                              (0xC409)
+#define PROC_CPU_CPULATEINIT_FILECODE                                    (0xC40A)
+#define PROC_CPU_CPUMICROCODEPATCH_FILECODE                              (0xC40B)
+#define PROC_CPU_CPUWARMRESET_FILECODE                                   (0xC40C)
+#define PROC_CPU_HEAPMANAGER_FILECODE                                    (0xC40D)
+#define PROC_CPU_CPUBIST_FILECODE                                        (0xC40E)
+
+#define PROC_CPU_CPUPOSTINIT_FILECODE                                    (0xC420)
+#define PROC_CPU_CPUPOWERMGMT_FILECODE                                   (0xC430)
+#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE                        (0xC431)
+#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE                       (0xC432)
+#define PROC_CPU_S3_FILECODE                                             (0xC460)
+
+// Family 10h
+#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE              (0xC801)
+#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE                      (0xC802)
+#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE                (0xC803)
+#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE             (0xC804)
+#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE                          (0xC805)
+#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE                    (0xC806)
+#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE              (0xC807)
+#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE                  (0xC808)
+#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE                    (0xC809)
+#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE                    (0xC80A)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE                   (0xC80B)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE        (0xC80C)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE                   (0xC80D)
+#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE              (0xC80E)
+#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE                    (0xC80F)
+#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE           (0xC810)
+#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE                       (0xC811)
+#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE                          (0xC812)
+#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE             (0xC813)
+#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE                  (0xC820)
+#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE             (0xC821)
+#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE              (0xC822)
+#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE                  (0xC823)
+#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE                 (0xC824)
+#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE                  (0xC825)
+#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE          (0xC826)
+#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE                        (0xC827)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE              (0xC830)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE                  (0xC831)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE                  (0xC832)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE              (0xC833)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE              (0xC834)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE            (0xC835)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE           (0xC836)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE       (0xC837)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE  (0xC838)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE             (0xC839)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE      (0xC83A)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE             (0xC83B)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE      (0xC83C)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE           (0xC83D)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE       (0xC83E)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE  (0xC83F)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE             (0xC840)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE      (0xC841)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE             (0xC842)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE      (0xC843)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE           (0xC844)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE       (0xC845)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE  (0xC846)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE             (0xC847)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE      (0xC848)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE             (0xC849)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE              (0xC850)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE            (0xC851)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE               (0xC852)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE           (0xC853)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE        (0xC854)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE       (0xC855)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE  (0xC856)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE             (0xC857)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE      (0xC858)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE             (0xC859)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE              (0xC860)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE              (0xC861)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE              (0xC862)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE            (0xC863)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE      (0xC864)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE           (0xC865)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE       (0xC866)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE  (0xC867)
+
+// Family 12h
+#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE              (0xC901)
+#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE                      (0xC902)
+#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE                (0xC903)
+#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE                          (0xC904)
+#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE                    (0xC905)
+#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE            (0xC906)
+#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE                    (0xC907)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE                   (0xC908)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE        (0xC909)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE                   (0xC90A)
+#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE              (0xC90B)
+#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE                    (0xC90C)
+#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE           (0xC90D)
+#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE                       (0xC90E)
+#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE                         (0xC90F)
+#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE                             (0xC910)
+#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE                        (0xC911)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE            (0xC921)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE       (0xC922)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE           (0xC923)
+#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE             (0xC924)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE               (0xC925)
+
+// Family 14h
+#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE              (0xCA01)
+#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE                      (0xCA02)
+#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE                (0xCA03)
+#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE                          (0xCA04)
+#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE                    (0xCA05)
+#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE                    (0xCA06)
+#define PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE                   (0xCA07)
+#define PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE        (0xCA08)
+#define PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE                   (0xCA09)
+#define PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE              (0xCA0A)
+#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE                    (0xCA0B)
+#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE           (0xCA0C)
+#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE                       (0xCA0D)
+#define PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE                         (0xCA0E)
+#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE                        (0xCA0F)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE            (0xCA21)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE       (0xCA22)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE           (0xCA23)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE             (0xCA24)
+#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE             (0xCA25)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE               (0xCA26)
+
+// Family 15h
+#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE              (0xCB01)
+#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE                      (0xCB02)
+#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE                (0xCB03)
+#define PROC_CPU_FAMILY_0X15_CPUF15CACHEFLUSHONHALT_FILECODE             (0xCB04)
+#define PROC_CPU_FAMILY_0X15_CPUF15COREAFTERRESET_FILECODE               (0xCB05)
+#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE                          (0xCB06)
+#define PROC_CPU_FAMILY_0X15_CPUF15FEATURELEVELING_FILECODE              (0xCB07)
+#define PROC_CPU_FAMILY_0X15_CPUF15HTPHYTABLES_FILECODE                  (0xCB08)
+#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE                    (0xCB09)
+#define PROC_CPU_FAMILY_0X15_CPUF15NBAFTERRESET_FILECODE                 (0xCB0A)
+#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE                    (0xCB0B)
+#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE                   (0xCB0C)
+#define PROC_CPU_FAMILY_0X15_CPUF15POWERMGMTSYSTEMTABLES_FILECODE        (0xCB0D)
+#define PROC_CPU_FAMILY_0X15_CPUF15POWERPLANE_FILECODE                   (0xCB0E)
+#define PROC_CPU_FAMILY_0X15_CPUF15SOFTWARETHERMAL_FILECODE              (0xCB0F)
+#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE                    (0xCB10)
+#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE           (0xCB11)
+#define PROC_CPU_FAMILY_0X15_CPUF15PSTATE_FILECODE                       (0xCB12)
+#define PROC_CPU_FAMILY_0X15_F15PMNBCOFVIDINIT_FILECODE                  (0xCB13)
+#define PROC_CPU_FAMILY_0X15_F15SINGLELINKPCITABLES_FILECODE             (0xCB14)
+#define PROC_CPU_FAMILY_0X15_F15MULTILINKPCITABLES_FILECODE              (0xCB15)
+#define PROC_CPU_FAMILY_0X15_F15C6STATE_FILECODE                         (0xCB16)
+#define PROC_CPU_FAMILY_0X15_F15CPB_FILECODE                             (0xCB17)
+#define PROC_CPU_FAMILY_0X15_F15INITEARLYTABLE_FILECODE                  (0xCB18)
+#define PROC_CPU_FAMILY_0X15_F15LOWPWRPSTATE_FILECODE                    (0xCB19)
+#define PROC_CPU_FAMILY_0X15_CPUF15WORKAROUNDSTABLE_FILECODE             (0xCB1A)
+#define PROC_CPU_FAMILY_0X15_F15IOCSTATE_FILECODE                        (0xCB1B)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORHTASSIST_FILECODE                   (0xCB30)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE                (0xCB31)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE            (0xCB32)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE       (0xCB33)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE                  (0xCB34)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE             (0xCB35)
+#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE           (0xCB36)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE                  (0xCB37)
+
+
+
+#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE                    (0xDC01)
+#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE                           (0xDC02)
+#define PROC_CPU_FEATURE_CPUDMI_FILECODE                                 (0xDC10)
+#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE                     (0xDC20)
+#define PROC_CPU_FEATURE_CPUHTASSIST_FILECODE                            (0xDC30)
+#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE                        (0xDC41)
+#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE                      (0xDC42)
+#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE                        (0xDC43)
+#define PROC_CPU_FEATURE_CPUSLIT_FILECODE                                (0xDC50)
+#define PROC_CPU_FEATURE_CPUSRAT_FILECODE                                (0xDC60)
+#define PROC_CPU_FEATURE_CPUWHEA_FILECODE                                (0xDC70)
+#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE                               (0xDC80)
+#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE                               (0xDC81)
+#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE                             (0xDC82)
+#define PROC_CPU_FEATURE_CPUCPB_FILECODE                                 (0xDC83)
+#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE                        (0xDC84)
+#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE                            (0xDC85)
+#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE                            (0xDC90)
+#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE                         (0xDCA0)
+#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE                        (0xDCB0)
+#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE                        (0xDCC0)
+
+#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE                           (0xDE01)
+
+#define PROC_HT_FEATURES_HTFEATSETS_FILECODE                             (0xE001)
+#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE                 (0xE002)
+#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE                          (0xE003)
+#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE                      (0xE004)
+#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE                     (0xE005)
+#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE                          (0xE006)
+#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE                         (0xE007)
+#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE              (0xE008)
+#define PROC_HT_FEATURES_HTIDS_FILECODE                                  (0xE009)
+#define PROC_HT_HTFEAT_FILECODE                                          (0xE021)
+#define PROC_HT_HTINTERFACE_FILECODE                                     (0xE022)
+#define PROC_HT_HTINTERFACECOHERENT_FILECODE                             (0xE023)
+#define PROC_HT_HTINTERFACEGENERAL_FILECODE                              (0xE024)
+#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE                          (0xE025)
+#define PROC_HT_HTMAIN_FILECODE                                          (0xE026)
+#define PROC_HT_HTNOTIFY_FILECODE                                        (0xE027)
+#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE                                 (0xE028)
+#define PROC_HT_HTNB_FILECODE                                            (0xE081)
+#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE                           (0xE082)
+#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE                        (0xE083)
+#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE                       (0xE084)
+#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE                          (0xE085)
+#define PROC_HT_FAM10_HTNBFAM10_FILECODE                                 (0xE0C1)
+#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE                         (0xE0C2)
+#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE                      (0xE0C3)
+#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE                     (0xE0C4)
+#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE                           (0xE0C5)
+#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE                        (0xE0C6)
+#define PROC_HT_FAM12_HTNBFAM12_FILECODE                                 (0xE101)
+#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE                        (0xE102)
+#define PROC_HT_FAM14_HTNBFAM14_FILECODE                                 (0xE141)
+#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE                        (0xE142)
+#define PROC_HT_FAM15_HTNBFAM15_FILECODE                                 (0xE181)
+#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE                         (0xE182)
+#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE                      (0xE183)
+#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE                     (0xE184)
+#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE                           (0xE185)
+#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE                        (0xE186)
+
+#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE                         (0xE302)
+#define PROC_RECOVERY_HT_HTINITRESET_FILECODE                            (0xE301)
+
+#define PROC_IDS_CONTROL_IDSCTRL_FILECODE                                (0xE801)
+#define PROC_IDS_CONTROL_IDSLIB_FILECODE                                 (0xE802)
+#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE                                 (0xE803)
+#define PROC_IDS_PERF_IDSPERF_FILECODE                                   (0xE804)
+#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE                   (0xE805)
+#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE                 (0xE806)
+#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE                 (0xE807)
+#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE                 (0xE808)
+#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE                 (0xE809)
+#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE                   (0xE80A)
+#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE                   (0xE80B)
+#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE                   (0xE80C)
+
+#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE                              (0xE80D)
+#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE                            (0xE80E)
+
+///0xE820 ~ 0xE840 is reserved for ids extend module
+
+#define PROC_MEM_ARDK_MA_FILECODE                                    (0xF001)
+#define PROC_MEM_ARDK_DR_MARDR2_FILECODE                             (0xF002)
+#define PROC_MEM_ARDK_DR_MARDR3_FILECODE                             (0xF003)
+#define PROC_MEM_ARDK_HY_MARHY3_FILECODE                             (0xF004)
+#define PROC_MEM_ARDK_LN_MASLN3_FILECODE                             (0xF005)
+#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE                             (0xF006)
+#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE                             (0xF007)
+#define PROC_MEM_ARDK_LN_MAULN3_FILECODE                             (0xF008)
+#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE                             (0xF009)
+#define PROC_MEM_ARDK_DA_MASDA2_FILECODE                             (0xF00A)
+#define PROC_MEM_ARDK_DA_MASDA3_FILECODE                             (0xF00B)
+#define PROC_MEM_ARDK_NI_MASNI3_FILECODE                             (0xF00C)
+#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE                          (0xF00D)
+#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE                          (0xF00E)
+#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE                             (0xF00F)
+#define PROC_MEM_ARDK_ON_MASON3_FILECODE                             (0xF010)
+#define PROC_MEM_ARDK_ON_MAUON3_FILECODE                             (0xF011)
+#define PROC_MEM_ARDK_PH_MASPH3_FILECODE                             (0xF012)
+#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE                             (0xF013)
+#define PROC_MEM_ARDK_OR_MAROR3_FILECODE                             (0xF014)
+#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE                             (0xF017)
+#define PROC_MEM_ARDK_RB_MASRB3_FILECODE                             (0xF018)
+#define PROC_MEM_ARDK_RB_MAURB3_FILECODE                             (0xF019)
+
+#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE                         (0xF081)
+#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE                         (0xF082)
+#define PROC_MEM_FEAT_ECC_MFECC_FILECODE                             (0xF083)
+#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE                             (0xF085)
+#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE                (0xF086)
+#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE                   (0xF088)
+#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE                     (0xF089)
+#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE                       (0xF08A)
+#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE                       (0xF08B)
+#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE                         (0xF08C)
+#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE                 (0xF08D)
+#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE                         (0xF08E)
+#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE             (0xF08F)
+#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE             (0xF091)
+#define PROC_MEM_FEAT_S3_MFS3_FILECODE                               (0xF092)
+#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE                           (0xF093)
+
+#define PROC_MEM_MAIN_MDEF_FILECODE                                  (0xF101)
+#define PROC_MEM_MAIN_MINIT_FILECODE                                 (0xF102)
+#define PROC_MEM_MAIN_MM_FILECODE                                    (0xF103)
+#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE                             (0xF104)
+#define PROC_MEM_MAIN_MMECC_FILECODE                                 (0xF105)
+#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE                         (0xF106)
+#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE                           (0xF107)
+#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE                           (0xF108)
+#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE                           (0xF109)
+#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE                           (0xF10A)
+#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE                      (0xF10B)
+#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE                         (0xF10C)
+#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE                    (0xF10D)
+#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE                    (0xF10E)
+#define PROC_MEM_MAIN_MUC_FILECODE                                   (0xF10F)
+#define PROC_MEM_MAIN_MMMEMCLR_FILECODE                              (0xF110)
+#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE                           (0xF111)
+#define PROC_MEM_MAIN_MMFLOW_FILECODE                                (0xF112)
+#define PROC_MEM_MAIN_MERRHDL_FILECODE                               (0xF113)
+#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE                         (0xF114)
+#define PROC_MEM_MAIN_MMLVDDR3_FILECODE                              (0xF115)
+#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE                            (0xF116)
+#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE                          (0xF117)
+#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE                      (0xF118)
+#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE                           (0xF119)
+#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE                           (0xF11A)
+#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE                           (0xF11B)
+
+#define PROC_MEM_NB_DR_MNDR_FILECODE                                 (0XF213)
+#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE                             (0XF214)
+#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE                         (0XF216)
+#define PROC_MEM_NB_DR_MNMCTDR_FILECODE                              (0XF217)
+#define PROC_MEM_NB_DR_MNDCTDR_FILECODE                              (0XF218)
+#define PROC_MEM_NB_DR_MNOTDR_FILECODE                               (0XF219)
+#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE                         (0XF21A)
+#define PROC_MEM_NB_DR_MNPROTODR_FILECODE                            (0XF21C)
+#define PROC_MEM_NB_DR_MNS3DR_FILECODE                               (0XF21D)
+#define PROC_MEM_NB_DR_MNREGDR_FILECODE                              (0XF21E)
+#define PROC_MEM_NB_RB_MNRB_FILECODE                                 (0XF220)
+#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE                             (0XF221)
+#define PROC_MEM_NB_RB_MNS3RB_FILECODE                               (0XF222)
+#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE                         (0XF223)
+#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE                             (0XF233)
+#define PROC_MEM_NB_HY_MNHY_FILECODE                                 (0XF235)
+#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE                         (0XF236)
+#define PROC_MEM_NB_HY_MNMCTHY_FILECODE                              (0XF237)
+#define PROC_MEM_NB_HY_MNDCTHY_FILECODE                              (0XF238)
+#define PROC_MEM_NB_HY_MNOTHY_FILECODE                               (0XF239)
+#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE                         (0XF23A)
+#define PROC_MEM_NB_HY_MNPHYHY_FILECODE                              (0XF23B)
+#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE                            (0XF23C)
+#define PROC_MEM_NB_HY_MNS3HY_FILECODE                               (0XF23D)
+#define PROC_MEM_NB_HY_MNREGHY_FILECODE                              (0XF23E)
+#define PROC_MEM_NB_ON_MNON_FILECODE                                 (0xF240)
+#define PROC_MEM_NB_ON_MNREGON_FILECODE                              (0xF241)
+#define PROC_MEM_NB_ON_MNDCTON_FILECODE                              (0xF242)
+#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE                         (0xF244)
+#define PROC_MEM_NB_ON_MNMCTON_FILECODE                              (0xF245)
+#define PROC_MEM_NB_ON_MNOTON_FILECODE                               (0xF246)
+#define PROC_MEM_NB_ON_MNPHYON_FILECODE                              (0xF247)
+#define PROC_MEM_NB_ON_MNS3ON_FILECODE                               (0xF248)
+#define PROC_MEM_NB_ON_MNFLOWON_FILECODE                             (0xF249)
+#define PROC_MEM_NB_ON_MNPROTOON_FILECODE                            (0xF24A)
+#define PROC_MEM_NB_LN_MNDCTLN_FILECODE                              (0XF252)
+#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE                             (0XF253)
+#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE                         (0XF254)
+#define PROC_MEM_NB_LN_MNMCTLN_FILECODE                              (0XF255)
+#define PROC_MEM_NB_LN_MNOTLN_FILECODE                               (0XF256)
+#define PROC_MEM_NB_LN_MNPHYLN_FILECODE                              (0XF257)
+#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE                            (0XF258)
+#define PROC_MEM_NB_LN_MNLN_FILECODE                                 (0XF259)
+#define PROC_MEM_NB_LN_MNS3LN_FILECODE                               (0XF25A)
+#define PROC_MEM_NB_LN_MNREGLN_FILECODE                              (0XF25B)
+#define PROC_MEM_NB_DA_MNDA_FILECODE                                 (0XF260)
+#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE                             (0XF261)
+#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE                         (0XF263)
+#define PROC_MEM_NB_DA_MNMCTDA_FILECODE                              (0XF264)
+#define PROC_MEM_NB_DA_MNDCTDA_FILECODE                              (0XF265)
+#define PROC_MEM_NB_DA_MNOTDA_FILECODE                               (0XF266)
+#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE                         (0XF267)
+#define PROC_MEM_NB_DA_MNPROTODA_FILECODE                            (0XF269)
+#define PROC_MEM_NB_DA_MNS3DA_FILECODE                               (0XF26A)
+#define PROC_MEM_NB_DA_MNREGDA_FILECODE                              (0XF26B)
+#define PROC_MEM_NB_C32_MNC32_FILECODE                               (0XF26C)
+#define PROC_MEM_NB_C32_MNDCTC32_FILECODE                            (0XF26D)
+#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE                           (0XF26E)
+#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE                       (0XF26F)
+#define PROC_MEM_NB_C32_MNMCTC32_FILECODE                            (0XF270)
+#define PROC_MEM_NB_C32_MNOTC32_FILECODE                             (0XF271)
+#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE                       (0XF272)
+#define PROC_MEM_NB_C32_MNPHYC32_FILECODE                            (0XF273)
+#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE                          (0XF274)
+#define PROC_MEM_NB_C32_MNS3C32_FILECODE                             (0XF275)
+#define PROC_MEM_NB_C32_MNREGC32_FILECODE                            (0XF277)
+#define PROC_MEM_NB_MN_FILECODE                                      (0XF27C)
+#define PROC_MEM_NB_MNDCT_FILECODE                                   (0XF27D)
+#define PROC_MEM_NB_MNPHY_FILECODE                                   (0XF27E)
+#define PROC_MEM_NB_MNMCT_FILECODE                                   (0XF27F)
+#define PROC_MEM_NB_MNS3_FILECODE                                    (0XF280)
+#define PROC_MEM_NB_MNFLOW_FILECODE                                  (0XF281)
+#define PROC_MEM_NB_MNFEAT_FILECODE                                  (0XF282)
+#define PROC_MEM_NB_MNTRAIN2_FILECODE                                (0XF283)
+#define PROC_MEM_NB_MNTRAIN3_FILECODE                                (0XF284)
+#define PROC_MEM_NB_MNREG_FILECODE                                   (0XF285)
+#define PROC_MEM_NB_NI_MNNI_FILECODE                                 (0XF286)
+#define PROC_MEM_NB_NI_MNS3NI_FILECODE                               (0XF287)
+#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE                             (0XF288)
+#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE                             (0XF289)
+#define PROC_MEM_NB_PH_MNPH_FILECODE                                 (0XF28A)
+#define PROC_MEM_NB_PH_MNS3PH_FILECODE                               (0XF28B)
+#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE                         (0XF28C)
+#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE                             (0XF290)
+#define PROC_MEM_NB_OR_MNOR_FILECODE                                 (0XF291)
+#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE                         (0XF292)
+#define PROC_MEM_NB_OR_MNMCTOR_FILECODE                              (0XF293)
+#define PROC_MEM_NB_OR_MNDCTOR_FILECODE                              (0XF294)
+#define PROC_MEM_NB_OR_MNOTOR_FILECODE                               (0XF295)
+#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE                         (0XF296)
+#define PROC_MEM_NB_OR_MNPHYOR_FILECODE                              (0XF297)
+#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE                            (0XF298)
+#define PROC_MEM_NB_OR_MNS3OR_FILECODE                               (0XF299)
+#define PROC_MEM_NB_OR_MNREGOR_FILECODE                              (0XF29A)
+
+#define PROC_MEM_PS_MP_FILECODE                                      (0XF401)
+#define PROC_MEM_PS_DR_MPRDR3_FILECODE                               (0XF402)
+#define PROC_MEM_PS_HY_MPRHY3_FILECODE                               (0XF403)
+#define PROC_MEM_PS_LN_MPRLN3_FILECODE                               (0XF404)
+#define PROC_MEM_PS_DR_MPSDR3_FILECODE                               (0XF405)
+#define PROC_MEM_PS_HY_MPSHY3_FILECODE                               (0XF406)
+#define PROC_MEM_PS_LN_MPSLN3_FILECODE                               (0XF407)
+#define PROC_MEM_PS_DR_MPUDR3_FILECODE                               (0XF408)
+#define PROC_MEM_PS_HY_MPUHY3_FILECODE                               (0XF409)
+#define PROC_MEM_PS_LN_MPULN3_FILECODE                               (0XF40A)
+#define PROC_MEM_PS_DA_MPUDA3_FILECODE                               (0XF40B)
+#define PROC_MEM_PS_DA_MPSDA2_FILECODE                               (0XF40C)
+#define PROC_MEM_PS_DA_MPSDA3_FILECODE                               (0XF40D)
+#define PROC_MEM_PS_DR_MPRDR2_FILECODE                               (0XF40E)
+#define PROC_MEM_PS_DR_MPUDR2_FILECODE                               (0XF40F)
+#define PROC_MEM_PS_C32_MPRC32_3_FILECODE                            (0XF410)
+#define PROC_MEM_PS_C32_MPUC32_3_FILECODE                            (0XF411)
+#define PROC_MEM_PS_NI_MPSNI3_FILECODE                               (0XF412)
+#define PROC_MEM_PS_NI_MPUNI3_FILECODE                               (0XF413)
+#define PROC_MEM_PS_ON_MPSON3_FILECODE                               (0XF414)
+#define PROC_MEM_PS_ON_MPUON3_FILECODE                               (0XF415)
+#define PROC_MEM_PS_PH_MPSPH3_FILECODE                               (0XF416)
+#define PROC_MEM_PS_PH_MPUPH3_FILECODE                               (0XF417)
+#define PROC_MEM_PS_RB_MPSRB3_FILECODE                               (0XF418)
+#define PROC_MEM_PS_RB_MPURB3_FILECODE                               (0XF419)
+#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE                          (0XF41A)
+#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE                          (0XF41B)
+#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE                          (0XF41C)
+#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE                          (0XF41D)
+#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE                          (0XF41E)
+#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE                          (0XF41F)
+#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE                          (0XF420)
+#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE                          (0XF421)
+#define PROC_MEM_PS_MPRTT_FILECODE                                   (0XF422)
+#define PROC_MEM_PS_MPMAXFREQ_FILECODE                               (0XF423)
+#define PROC_MEM_PS_MPODTPAT_FILECODE                                (0XF424)
+#define PROC_MEM_PS_MPSAO_FILECODE                                   (0XF425)
+#define PROC_MEM_PS_MPMR0_FILECODE                                   (0XF426)
+#define PROC_MEM_PS_MPRC2IBT_FILECODE                                (0XF427)
+#define PROC_MEM_PS_MPRC10OPSPD_FILECODE                             (0XF428)
+#define PROC_MEM_PS_MPLRIBT_FILECODE                                 (0XF429)
+#define PROC_MEM_PS_MPLRNPR_FILECODE                                 (0XF42A)
+#define PROC_MEM_PS_MPLRNLR_FILECODE                                 (0XF42B)
+#define PROC_MEM_PS_OR_MPOR3_FILECODE                                (0XF42C)
+
+#define PROC_MEM_TECH_MT_FILECODE                                    (0XF501)
+#define PROC_MEM_TECH_MTHDI_FILECODE                                 (0XF502)
+#define PROC_MEM_TECH_MTTDIMBT_FILECODE                              (0XF504)
+#define PROC_MEM_TECH_MTTECC_FILECODE                                (0XF505)
+#define PROC_MEM_TECH_MTTHRC_FILECODE                                (0XF506)
+#define PROC_MEM_TECH_MTTML_FILECODE                                 (0XF507)
+#define PROC_MEM_TECH_MTTOPTSRC_FILECODE                             (0XF509)
+#define PROC_MEM_TECH_MTTSRC_FILECODE                                (0XF50B)
+#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE                         (0XF50C)
+#define PROC_MEM_TECH_DDR2_MT2_FILECODE                              (0XF541)
+#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE                            (0XF543)
+#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE                           (0XF544)
+#define PROC_MEM_TECH_DDR3_MT3_FILECODE                              (0XF581)
+#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE                            (0XF583)
+#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE                           (0XF584)
+#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE                           (0XF585)
+#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE                           (0XF586)
+#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE                           (0XF587)
+#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE                          (0XF588)
+#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE                        (0XF589)
+
+#define PROC_RECOVERY_MEM_MRDEF_FILECODE                             (0XF801)
+#define PROC_RECOVERY_MEM_MRINIT_FILECODE                            (0XF802)
+#define PROC_RECOVERY_MEM_MRM_FILECODE                               (0XF803)
+#define PROC_RECOVERY_MEM_MRUC_FILECODE                              (0XF804)
+#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE                       (0XF812)
+#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE                    (0XF813)
+#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE                    (0XF821)
+#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE                       (0XF822)
+#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE                    (0XF823)
+#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE                  (0XF825)
+#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE                    (0XF831)
+#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE                    (0XF832)
+#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE                       (0XF833)
+#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE                       (0XF842)
+#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE                    (0XF843)
+#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE                       (0XF845)
+#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE                     (0XF851)
+#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE                  (0XF852)
+#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE                (0XF853)
+#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE                    (0xF861)
+#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE                    (0xF862)
+#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE                       (0xF863)
+#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE                       (0xF871)
+#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE                       (0xF881)
+#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE                      (0XF8C1)
+#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE                      (0XF8C2)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE                    (0XF8C3)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE                 (0XF8C4)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE                 (0XF8C5)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE                 (0XF8C6)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE                 (0XF8C7)
+#define PROC_RECOVERY_MEM_NB_MRN_FILECODE                            (0XF8C8)
+#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE                         (0XF8C9)
+#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE                         (0XF8CA)
+#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE                      (0XF8CB)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE                      (0XF8CC)
+#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE                    (0XF8CD)
+#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE                       (0XF8CE)
+#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE                    (0XF8CF)
+#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE                  (0XF8D0)
+#define PROC_RECOVERY_MEM_PS_MRP_FILECODE                            (0XF8E0)
+#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE                         (0XF8E1)
+#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE                      (0XF8E2)
+#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE                         (0XF8E3)
+#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE                         (0XF8E4)
+#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE                      (0XF8E5)
+#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE                   (0XF8E6)
+#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE                       (0XF8E7)
+#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE                       (0XF8E8)
+#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE                       (0XF8E9)
+#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE                      (0XF8EA)
+#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE                (0XF8EB)
+#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE                (0XF8EC)
+#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE                (0XF8ED)
+#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE                (0XF8EE)
+#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE                (0XF8EF)
+#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE                (0XF8F0)
+#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE                (0XF8F1)
+#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE                (0XF8F2)
+
+#endif // _FILECODE_H_

Added: trunk/src/vendorcode/amd/agesa/Include/GeneralServices.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/GeneralServices.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,203 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * General Services
+ *
+ * Provides Services similar to the external General Services API, except
+ * suited to use within AGESA components.  Socket, Core and PCI identification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _GENERAL_SERVICES_H_
+#define _GENERAL_SERVICES_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define NUMBER_OF_EVENT_DATA_PARAMS 4
+
+/**
+ * AMD Device id for MMIO check.
+ */
+#define AMD_DEV_VEN_ID 0x1022
+#define AMD_DEV_VEN_ID_ADDRESS 0
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * An AGESA Event Log entry.
+ */
+typedef struct {
+  AGESA_STATUS EventClass;   ///< The severity of the event, its associated AGESA_STATUS.
+  UINT32   EventInfo;        ///< Uniquely identifies the event.
+  UINT32   DataParam1;       ///< Event specific additional data
+  UINT32   DataParam2;       ///< Event specific additional data
+  UINT32   DataParam3;       ///< Event specific additional data
+  UINT32   DataParam4;       ///< Event specific additional data
+} AGESA_EVENT;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Core         The Core id.
+ * @param[out]   ApicAddress  The Core's APIC ID.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, APIC Id valid
+ * @retval       FALSE        The core is not present, APIC Id not valid.
+ */
+BOOLEAN
+GetApicId (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Core,
+     OUT   UINT8             *ApicAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Module       The Module in that Processor
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, PCI Address valid
+ * @retval       FALSE        The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetPciAddress (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   PCI_ADDR          *PciAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ * "Who am I" for the current running core.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[out]   Socket       The current Core's Socket
+ * @param[out]   Module       The current Core's Processor Module
+ * @param[out]   Core         The current Core's core id.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+VOID
+IdentifyCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   UINT32            *Socket,
+     OUT   UINT32            *Module,
+     OUT   UINT32            *Core,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ *  A boolean function determine executed CPU is BSP core.
+ */
+BOOLEAN
+IsBsp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+     OUT   AGESA_STATUS      *AgesaStatus
+  );
+
+/**
+ * This function logs AGESA events into the event log.
+ */
+VOID
+PutEventLog (
+  IN       AGESA_STATUS EventClass,
+  IN       UINT32 EventInfo,
+  IN       UINT32 DataParam1,
+  IN       UINT32 DataParam2,
+  IN       UINT32 DataParam3,
+  IN       UINT32 DataParam4,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function gets event logs from the circular buffer.
+ */
+AGESA_STATUS
+GetEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function gets event logs from the circular buffer without flushing the entry.
+ */
+BOOLEAN
+PeekEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       UINT16 Index,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This routine programs the registers necessary to get the PCI MMIO mechanism
+ * up and functioning.
+ */
+VOID
+InitializePciMmio (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _GENERAL_SERVICES_H_

Added: trunk/src/vendorcode/amd/agesa/Include/GnbInterface.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/GnbInterface.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,96 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB API definition.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 37658 $   @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _GNBINTERFACE_H_
+#define _GNBINTERFACE_H_
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT  AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN      AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+#endif

Added: trunk/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,232 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  GNB
+ * @e \$Revision: 37658 $   @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Reset Stub
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early Stub
+ *
+ *
+ *
+ * @param[in,out] EarlyParamsPtr    Pointer to early configuration params.
+ * @retval        AGESA_STATUS      Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  )
+{
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Default constructor of GNB configuration at Env
+ *
+ *
+ *
+ * @param[in] GnbEnvConfigPtr     Pointer to gnb env configuration params.
+ * @param[in] EnvParamsPtr        Pointer to env configuration params.
+ */
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN      AMD_ENV_PARAMS          *EnvParamsPtr
+  )
+{
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Env
+ *
+ *
+ *
+ * @param[in] EnvParamsPtr        Pointer to env configuration params.
+* @retval     AGESA_STATUS        Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post
+ *
+ *
+ *
+ * @param[in,out] PostParamsPtr    Pointer to Post configuration params.
+ * @retval        AGESA_STATUS     Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Mid post
+ *
+ *
+ *
+ * @param[in,out] MidParamsPtr    Pointer to mid configuration params.
+ * @retval        AGESA_STATUS    Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Late post
+ *
+ *
+ *
+ * @param[in,out] LateParamsPtr    Pointer to late configuration params.
+ * @retval        AGESA_STATUS     Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AmdGnbRecovery
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS  Always succeeds
+ */
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post after DRAM init
+ *
+ *
+ *
+ * @param[in]     PostParamsPtr Pointer to post configuration parameters
+ * @retval                      Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+  return  AGESA_SUCCESS;
+}
\ No newline at end of file

Added: trunk/src/vendorcode/amd/agesa/Include/Ids.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/Ids.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,927 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 38634 $   @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+  /* Macros to aid debugging */
+  /* These definitions expand to zero (0) bytes of code when disabled */
+
+#ifndef _IDS_H_
+#define _IDS_H_
+
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE  1
+// Proto type for optionsids.h
+typedef UINT32 IDS_STATUS;  ///< Status of IDS function.
+#define IDS_SUCCESS         ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
+#define IDS_UNSUPPORTED     ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
+
+#define IDS_STRINGIZE(a) #a ///< for define stringize macro
+/**
+ *  IDS Option Hook Points
+ *
+ *  These are the values to indicate hook point in AGESA for IDS Options.
+ *
+ */
+typedef enum {                        //vv- for debug reference only
+  IDS_INIT_EARLY_BEFORE,              ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
+                                          ///<   IDS Object is initialized.
+                                          ///<   Override CPU Core Leveling Mode.
+                                          ///<   Set P-State in Post
+  IDS_INIT_EARLY_AFTER,               ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
+  IDS_INIT_LATE_BEFORE,               ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
+                                          ///< It will be used to control the following tables.
+                                          ///<   ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
+                                          ///<   ACPI SRAT Table
+                                          ///<   ACPI SLIT Table
+                                          ///<   ACPI WHEA Table
+                                          ///<   DMI Table
+  IDS_INIT_LATE_AFTER,                ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
+  IDS_INIT_MID_BEFORE,                ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
+  IDS_INIT_MID_AFTER,                 ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
+  IDS_INIT_POST_BEFORE,               ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
+                                          ///<   Control Interleaving and DRAM memory hole
+                                          ///<   Override the setting of ECC Control
+                                          ///<   Override the setting of Online Spare Rank
+  IDS_INIT_POST_AFTER,                ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
+  IDS_INIT_RESET_BEFORE,              ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
+  IDS_INIT_RESET_AFTER,               ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
+  IDS_INIT_POST_MID,                  ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
+  IDS_BEFORE_S3_SAVE,                 ///< 0b override any settings before S3 save.
+  IDS_BEFORE_S3_RESTORE,              ///< 0c  override any settings before S3 restore
+  IDS_AFTER_S3_SAVE,                  ///< 0d Override any settings after S3 save
+  IDS_AFTER_S3_RESTORE,               ///< 0e Override any settings after S3 restore
+  IDS_BEFORE_DQS_TRAINING,            ///< 0f override any settings before DQS training
+  IDS_BEFORE_DRAM_INIT,               ///< 10 override any settings before Dram initialization
+  IDS_BEFORE_MEM_FREQ_CHG,            ///< 11 override settings before MemClk frequency change
+  IDS_BEFORE_WARM_RESET ,             ///< 12 Override PCI or MSR Registers Before Warm Reset
+  IDS_BEFORE_MEM_INIT,                ///< 13 Override PCI or MSR Registers Before Memory Init
+  IDS_BEFORE_PCI_INIT,                ///< 14 Override PCI or MSR Registers Before PCI Init
+  IDS_BEFORE_OS,                      ///< 15 Override PCI or MSR Registers Before booting to OS
+  IDS_UCODE,                          ///< 16 Enable or Disable microcode patching
+  IDS_BEFORE_AP_EARLY_HALT,           ///< 17 Option Hook Point before AP early halt
+
+  IDS_PLATFORM_RSVD1 = 0x38,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD2 = 0x39,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD3 = 0x3a,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD4 = 0x3b,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD5 = 0x3c,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD6 = 0x3d,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD7 = 0x3e,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD8 = 0x3f,          ///< from 0x38 to 0x3f will reserved for platform used
+
+  // All the above timing point is used by BVM, their value should never be changed
+  IDS_HT_CONTROL,                     ///< 40 Override the setting of HT Link Control
+  IDS_HT_TRISTATE,                    ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
+  IDS_INIT_DRAM_TABLE,                ///< 42 Generate override table for Dram Timing
+                                          ///< Dram Controller, Drive Strength and DQS Timing
+  IDS_GET_DRAM_TABLE,                 ///< 43 Generate override table for Dram Timing
+  IDS_GANGING_MODE,                   ///< 44 override Memory Mode Unganged
+  IDS_POWERDOWN_MODE,                 ///< 45 override Power Down Mode
+  IDS_BURST_LENGTH32,                 ///< 46 override Burst Length32
+  IDS_ALL_MEMORY_CLOCK,               ///< 47 override All Memory Clks Enable
+  IDS_ECC,                            ///< 48 override ECC parameter
+  IDS_ECCSYMBOLSIZE,                  ///< 49 override ECC symbol size
+  IDS_CPU_Early_Override,             ///< 4a override CPU early parameter
+  IDS_CACHE_FLUSH_HLT,                ///< 4b override Cache Flush Hlt
+  IDS_CHANNEL_INTERLEAVE,             ///< 4c override Channel Interleave
+  IDS_MEM_ERROR_RECOVERY,             ///< 4d override memory error recovery
+  IDS_MEM_RETRAIN_TIMES,              ///< 4e override memory retrain times
+  IDS_MEM_SIZE_OVERLAY,               ///< 4f Override the syslimit
+  IDS_HT_ASSIST,                      ///< 50 Override Probe Filter
+  IDS_CHECK_NEGATIVE_WL,              ///< 51 Check for negative write leveling result
+  IDS_DLL_SHUT_DOWN,                  ///< 52 Check for Dll Shut Down
+  IDS_POR_MEM_FREQ,                   ///< 53 Entry to enable/disable MemClk frequency enforcement
+  IDS_PHY_DLL_STANDBY_CTRL,           ///< 54 Enable/Disable Phy DLL standby feature
+  IDS_PLATFORMCFG_OVERRIDE,           ///< 55 Hook for Override PlatformConfig structure
+  IDS_LOADCARD_ERROR_RECOVERY,        ///< 56 Special error handling for load card support
+  IDS_MEM_IGNORE_ERROR,               ///< 57 Ignore error and do not do fatal exit in memory
+  IDS_GNB_SMU_SERVICE_CONFIG,         ///< 58 Config GNB SMU service
+  IDS_GNB_ORBDYNAMIC_WAKE,            ///< 59 config GNB dynamic wake
+  IDS_GNB_PLATFORMCFG_OVERRIDE,       ///< 5a override ids gnb platform config
+  IDS_GNB_LCLK_DPM_EN,                ///< 5b override GNB LCLK DPM configuration
+  IDS_GNB_LCLK_DEEP_SLEEP,            ///< 5c override GNB LCLK DPM deep sleep
+  IDS_GNB_CLOCK_GATING,               ///< 5d Override GNB Clock gating config
+  IDS_NB_PSTATE_DIDVID,               ///< 5e Override NB P-state settings
+  IDS_CPB_CTRL,                       ///< 5f Config the Core peformance boost feature
+  IDS_HTC_CTRL,                       ///< 60 Hook for Hardware Thermal Control
+  IDS_CC6_WORKAROUND,                 ///< 61 Hook for skip CC6 work around
+  IDS_MEM_MR0,                        ///< 62 Hook for override Memory Mr0 register
+  IDS_REG_TABLE,                      ///< 63 Hook for add IDS register table to the loop
+  IDS_NBBUFFERALLOCATIONATEARLY,      ///< 64 Hook for override North bridge bufer allocation
+  IDS_BEFORE_S3_SPECIAL,              ///< 65 Hook to bypass S3 special functions
+  IDS_SET_PCI_REGISTER_ENTRY,         ///< 66 Hook to SetRegisterForPciEntry
+  IDS_ERRATUM463_WORKAROUND,          ///< 67 Hook to Erratum 463 workaround
+  IDS_BEFORE_MEMCLR,                  ///< 68 Hook before set Memclr bit
+  IDS_OVERRIDE_IO_CSTATE,             ///< 69 Hook for override io C-state setting
+  IDS_NBPSDIS_OVERRIDE,               ///< 6a Hook for override NB pstate disable setting
+  IDS_NBPS_REG_OVERRIDE,              ///< 6b Hook for override Memory NBps reg
+  IDS_LOW_POWER_PSTATE,               ///< 6c Hook for disalbe Low power_Pstates feature
+  IDS_CST_CREATE,                     ///< 6d Hook for create _CST
+  IDS_CST_SIZE,                       ///< 6e Hook for get _CST size
+  IDS_ENFORCE_VDDIO,                  ///< 6f Hook to override VDDIO
+  IDS_SKIP_PERFORMANCE_OPT,           ///< 70 Hook to skip performance optimization
+  IDS_INIT_MEM_REG_TABLE,             ///< 71 Hook for init memory register table
+  IDS_SKIP_FUSED_MAX_RATE             ///< 72 Hook to skip fused max rate cap
+} AGESA_IDS_OPTION;
+
+#include "OptionsIds.h"
+#include "Filecode.h"
+
+/* Initialize IDS controls */
+#ifndef IDSOPT_IDS_ENABLED
+  #define IDSOPT_IDS_ENABLED        FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_ENABLED
+  #define IDSOPT_CONTROL_ENABLED    FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_ENABLED
+  #define IDSOPT_TRACING_ENABLED    FALSE
+#endif
+
+#ifndef IDSOPT_TRACE_USER_OPTIONS
+  #define IDSOPT_TRACE_USER_OPTIONS TRUE
+#endif
+
+#ifndef IDSOPT_PERF_ANALYSIS
+  #define IDSOPT_PERF_ANALYSIS      FALSE
+#endif
+
+#ifndef IDSOPT_HEAP_CHECKING
+  #define IDSOPT_HEAP_CHECKING           FALSE
+#endif
+
+#ifndef IDSOPT_ASSERT_ENABLED
+  #define IDSOPT_ASSERT_ENABLED         FALSE
+#endif
+
+#ifndef IDSOPT_ERROR_TRAP_ENABLED
+  #define IDSOPT_ERROR_TRAP_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_DEBUG_CODE_ENABLED
+  #define IDSOPT_DEBUG_CODE_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
+  #define IDSOPT_C_OPTIMIZATION_DISABLED   FALSE
+#endif
+
+#if IDSOPT_IDS_ENABLED == FALSE
+  #undef  IDSOPT_CONTROL_ENABLED
+  #undef  IDSOPT_TRACING_ENABLED
+  #undef  IDSOPT_PERF_ANALYSIS
+  #undef  IDSOPT_HEAP_CHECKING
+  #undef  IDSOPT_ASSERT_ENABLED
+  #undef  IDSOPT_ERROR_TRAP_ENABLED
+  #undef  IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+  #undef  IDSOPT_DEBUG_CODE_ENABLED
+  #undef  IDSOPT_TRACE_USER_OPTIONS
+
+  #define IDSOPT_CONTROL_ENABLED    FALSE
+  #define IDSOPT_TRACING_ENABLED    FALSE
+  #define IDSOPT_PERF_ANALYSIS      FALSE
+  #define IDSOPT_HEAP_CHECKING      FALSE
+  #define IDSOPT_ASSERT_ENABLED     FALSE
+  #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+  #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+  #define IDSOPT_TRACE_USER_OPTIONS FALSE
+#endif
+
+/**
+ *  Make a Progress Report to the User.
+ *
+ *  This Macro is always enabled. The default action is to write the TestPoint value
+ *  to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
+ *  IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
+ *  in OptionsIds.h in their build tip.
+ *
+ *  @param[in]      TestPoint       The value for display indicating progress
+ *  @param[in,out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ **/
+
+#define AGESA_TESTPOINT(TestPoint, StdHeader)
+
+#ifndef IDS_DEBUG_PORT
+  #define IDS_DEBUG_PORT  0x80
+#endif
+
+/**
+ * @def STOP_HERE
+ *  (macro) - Causes program to halt. This is @b only for use during active debugging .
+ *
+ *  Causes the program to halt and display the file number of the source of the
+ *  halt (displayed in decimal).
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+  #define STOP_HERE
+#else
+  #define STOP_HERE
+#endif
+
+/**
+ * @def ASSERT
+ *  Test an assertion that the given statement is True.
+ *
+ *  The statement is evaluated to a boolean value. If the statement is True,
+ *  then no action is taken (no error). If the statement is False, a error stop
+ *  is generated to halt the program. Used for testing for fatal errors that
+ *  must be resolved before production. This is used to do parameter checks,
+ *  bounds checking, range checks and 'sanity' checks.
+ *
+ * @param[in]   conditional    Assert that evaluating this conditional results in TRUE.
+ *
+ **/
+#ifndef ASSERT
+  #if IDSOPT_ASSERT_ENABLED == TRUE
+    #ifdef STOP_CODE
+      #undef STOP_CODE
+    #endif
+    #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                        ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                        (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+    #define ASSERT(conditional)
+  #else
+    #define ASSERT(conditional)
+  #endif
+#endif
+
+#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
+  #undef  IDSOPT_ERROR_TRAP_ENABLED
+  #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#else
+  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#endif
+/**
+ * @def DEBUG_CODE
+ * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
+ *
+ */
+#ifndef DEBUG_CODE
+  #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
+    #define  DEBUG_CODE(Code)
+  #else
+    #define  DEBUG_CODE(Code)
+  #endif
+#endif
+
+/**
+ * @def IDS_ERROR_TRAP
+ * Trap AGESA Error events with stop code display.
+ *
+ * Works similarly to use of "ASSERT (FALSE);"
+ *
+ */
+#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+  #define IDS_ERROR_TRAP
+#else
+  #define IDS_ERROR_TRAP
+#endif
+
+///give the extended Macro default value
+#ifndef __IDS_EXTENDED__
+  #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
+  #define IDS_INITIAL_F10_PM_STEP
+  #define IDS_INITIAL_F12_PM_STEP
+  #define IDS_INITIAL_F14_PM_STEP
+  #define IDS_INITIAL_F15_PM_STEP
+  #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
+  #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
+  #define IDS_EXTENDED_HEAP_SIZE 0
+  #define IDS_EXT_INCLUDE_F10(file)
+  #define IDS_EXT_INCLUDE_F12(file)
+  #define IDS_EXT_INCLUDE_F14(file)
+  #define IDS_EXT_INCLUDE_F15(file)
+  #define IDS_EXT_INCLUDE(file)
+#endif
+
+#ifndef IDS_NUM_NV_ITEM
+  #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
+#endif
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+  #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
+#else
+  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+  #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
+#endif
+
+/**
+ *  Macro to add a *skip* hook for IDS options
+ *
+ *  The default minimal action is to do nothing and there is no any code to increase.
+ *  For debug environments, IDS dispatcher function will be called to perform
+ *  the detailed action and to skip AGESA code if necessary.
+ *
+ * @param[in]       IdsOption       IDS Option ID for this hook point
+ * @param[in, out]  DataPtr         Data Pointer to override
+ * @param[in, out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#else
+  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#endif
+
+/**
+ *  Macro to add a heap manager routine
+ *
+ *  when memory is allocated the heap manager actually allocates two extra dwords of data,
+ *  one dword buffer before the actual memory, and one dword afterwards.
+ *  a complete heap walk and check to be performed at any time.
+ *  it would ASSERT if the heap is corrupt
+ *
+ * @param[in]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+// Heap debug feature
+#define SENTINEL_BEFORE_VALUE 0x64616548    // "Head"
+#define SENTINEL_AFTER_VALUE  0x6C696154    // "Tail"
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_HEAP_CHECKING == TRUE
+    #define SIZE_OF_SENTINEL  0
+    #define NUM_OF_SENTINEL   0
+    #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+    #define SET_SENTINEL_AFTER(NodePtr)
+    #define Heap_Check(stdheader)
+  #else
+    #define SIZE_OF_SENTINEL  0
+    #define NUM_OF_SENTINEL   0
+    #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+    #define SET_SENTINEL_AFTER(NodePtr)
+    #define Heap_Check(stdheader)
+  #endif
+#else
+  #define SIZE_OF_SENTINEL    0
+  #define NUM_OF_SENTINEL     0
+  #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+  #define SET_SENTINEL_AFTER(NodePtr)
+  #define Heap_Check(stdheader)
+#endif
+
+
+ //Note a is from 0 to 63
+#define DEBUG_PRINT_SHIFT(a)   ((UINT64)1 << a)
+//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
+//Memory Masks
+#define MEM_SETREG                                  DEBUG_PRINT_SHIFT (0)
+#define MEM_GETREG                                  DEBUG_PRINT_SHIFT (1)
+#define MEM_FLOW                                    DEBUG_PRINT_SHIFT (2)
+#define MEM_STATUS                                  DEBUG_PRINT_SHIFT (3)
+#define MEMORY_TRACE_RSV1                           DEBUG_PRINT_SHIFT (4)
+#define MEMORY_TRACE_RSV2                           DEBUG_PRINT_SHIFT (5)
+#define MEMORY_TRACE_RSV3                           DEBUG_PRINT_SHIFT (6)
+#define MEMORY_TRACE_RSV4                           DEBUG_PRINT_SHIFT (7)
+#define MEMORY_TRACE_RSV5                           DEBUG_PRINT_SHIFT (8)
+#define MEMORY_TRACE_RSV6                           DEBUG_PRINT_SHIFT (9)
+
+
+
+//CPU Masks
+#define CPU_TRACE                                   DEBUG_PRINT_SHIFT (10)
+#define CPU_TRACE_RSV1                              DEBUG_PRINT_SHIFT (11)
+#define CPU_TRACE_RSV2                              DEBUG_PRINT_SHIFT (12)
+#define CPU_TRACE_RSV3                              DEBUG_PRINT_SHIFT (13)
+#define CPU_TRACE_RSV4                              DEBUG_PRINT_SHIFT (14)
+#define CPU_TRACE_RSV5                              DEBUG_PRINT_SHIFT (15)
+#define CPU_TRACE_RSV6                              DEBUG_PRINT_SHIFT (16)
+#define CPU_TRACE_RSV7                              DEBUG_PRINT_SHIFT (17)
+#define CPU_TRACE_RSV8                              DEBUG_PRINT_SHIFT (18)
+#define CPU_TRACE_RSV9                              DEBUG_PRINT_SHIFT (19)
+
+//GNB Masks
+#define GNB_TRACE                                   DEBUG_PRINT_SHIFT (20)
+#define PCIE_MISC                                   DEBUG_PRINT_SHIFT (21)
+#define PCIE_PORTREG_TRACE                          DEBUG_PRINT_SHIFT (22)
+#define PCIE_HOSTREG_TRACE                          DEBUG_PRINT_SHIFT (23)
+#define GNB_TRACE_RSV2                              DEBUG_PRINT_SHIFT (24)
+#define NB_MISC                                     DEBUG_PRINT_SHIFT (25)
+#define GNB_TRACE_RSV3                              DEBUG_PRINT_SHIFT (26)
+#define GFX_MISC                                    DEBUG_PRINT_SHIFT (27)
+#define NB_SMUREG_TRACE                             DEBUG_PRINT_SHIFT (28)
+#define GNB_TRACE_RSV1                              DEBUG_PRINT_SHIFT (29)
+
+//HT Masks
+#define HT_TRACE                                    DEBUG_PRINT_SHIFT (30)
+#define HT_TRACE_RSV1                               DEBUG_PRINT_SHIFT (31)
+#define HT_TRACE_RSV2                               DEBUG_PRINT_SHIFT (32)
+#define HT_TRACE_RSV3                               DEBUG_PRINT_SHIFT (33)
+#define HT_TRACE_RSV4                               DEBUG_PRINT_SHIFT (34)
+#define HT_TRACE_RSV5                               DEBUG_PRINT_SHIFT (35)
+#define HT_TRACE_RSV6                               DEBUG_PRINT_SHIFT (36)
+#define HT_TRACE_RSV7                               DEBUG_PRINT_SHIFT (37)
+#define HT_TRACE_RSV8                               DEBUG_PRINT_SHIFT (38)
+#define HT_TRACE_RSV9                               DEBUG_PRINT_SHIFT (39)
+
+//FCH Masks
+#define FCH_TRACE                                    DEBUG_PRINT_SHIFT (40)
+#define FCH_TRACE_RSV1                               DEBUG_PRINT_SHIFT (41)
+#define FCH_TRACE_RSV2                               DEBUG_PRINT_SHIFT (42)
+#define FCH_TRACE_RSV3                               DEBUG_PRINT_SHIFT (43)
+#define FCH_TRACE_RSV4                               DEBUG_PRINT_SHIFT (44)
+#define FCH_TRACE_RSV5                               DEBUG_PRINT_SHIFT (45)
+#define FCH_TRACE_RSV6                               DEBUG_PRINT_SHIFT (46)
+#define FCH_TRACE_RSV7                               DEBUG_PRINT_SHIFT (47)
+#define FCH_TRACE_RSV8                               DEBUG_PRINT_SHIFT (48)
+#define FCH_TRACE_RSV9                               DEBUG_PRINT_SHIFT (49)
+
+//Other Masks
+#define MAIN_FLOW                                    DEBUG_PRINT_SHIFT (50)
+#define EVENT_LOG                                    DEBUG_PRINT_SHIFT (51)
+#define PERFORMANCE_ANALYSE                          DEBUG_PRINT_SHIFT (52)
+
+//Ids Masks
+#define IDS_TRACE                                    DEBUG_PRINT_SHIFT (53)
+#define IDS_REG                                      DEBUG_PRINT_SHIFT (54)
+#define IDS_TRACE_RSV2                               DEBUG_PRINT_SHIFT (55)
+#define IDS_TRACE_RSV3                               DEBUG_PRINT_SHIFT (56)
+
+//S3
+#define S3_TRACE                                     DEBUG_PRINT_SHIFT (57)
+
+
+//Reserved
+#define TRACE_RSV1                                   DEBUG_PRINT_SHIFT (58)
+#define TRACE_RSV2                                   DEBUG_PRINT_SHIFT (59)
+#define TRACE_RSV3                                   DEBUG_PRINT_SHIFT (60)
+#define TRACE_RSV4                                   DEBUG_PRINT_SHIFT (61)
+#define TRACE_RSV5                                   DEBUG_PRINT_SHIFT (62)
+#define TRACE_RSV6                                   DEBUG_PRINT_SHIFT (63)
+
+#define GNB_TRACE_DEFAULT   0
+
+#define GNB_TRACE_REG       0
+
+#define GNB_TRACE_ALL       0
+
+#define CPU_TRACE_ALL       0
+
+#define MEMORY_TRACE_ALL    0
+
+#define HT_TRACE_ALL        0
+
+#define FCH_TRACE_ALL       0
+
+#define IDS_TRACE_ALL       0
+
+#define OTHER_TRACE_ALL     0
+
+#define TRACE_MASK_ALL (0ull)
+#ifndef IDS_DEBUG_PRINT_MASK
+  #define IDS_DEBUG_PRINT_MASK 0
+#endif
+
+
+/**
+ *  Macro to add HDT OUT
+ *
+ *  The default minimal action is to do nothing and there is no any code to increase.
+ *  For debug environments, the debug information can be displayed in HDT or other
+ *  devices.
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_TRACING_ENABLED == TRUE
+    #define IDS_HDT_CONSOLE_INIT(x)
+    #define IDS_HDT_CONSOLE_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+
+    #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
+      #ifdef __GNUC__
+        #define IDS_HDT_CONSOLE(f, s, ...)
+      #else
+        #define IDS_HDT_CONSOLE(f, s, ...)
+      #endif
+    #else
+      #pragma warning(disable: 4127)
+      #ifdef __GNUC__
+        #define IDS_HDT_CONSOLE(f, s, ...)
+      #else
+        #define IDS_HDT_CONSOLE(f, s, ...)
+      #endif
+    #endif
+
+    #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+    #define IDS_HDT_CONSOLE_ASSERT(x)
+    #define IDS_FUNCLIST_ADDR                   NULL
+    #define IDS_FUNCLIST_EXTERN()
+    #define IDS_TIMEOUT_CTL(t)
+    #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+    #define CONSOLE(s, ...)
+  #else
+    #define IDS_HDT_CONSOLE_INIT(x)
+    #define IDS_HDT_CONSOLE_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+    #define IDS_HDT_CONSOLE(f, s, ...)
+    #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+    #define IDS_HDT_CONSOLE_ASSERT(x)
+    #define IDS_FUNCLIST_ADDR                 NULL
+    #define IDS_FUNCLIST_EXTERN()
+    #define IDS_TIMEOUT_CTL(t)
+    #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+    #define CONSOLE(s, ...)
+  #endif
+#else
+  #define IDS_HDT_CONSOLE_INIT(x)
+  #define IDS_HDT_CONSOLE_EXIT(x)
+  #define IDS_HDT_CONSOLE_S3_EXIT(x)
+  #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+  #define IDS_HDT_CONSOLE(f, s, ...)
+  #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+  #define IDS_HDT_CONSOLE_ASSERT(x)
+  #define IDS_FUNCLIST_ADDR                   NULL
+  #define IDS_FUNCLIST_EXTERN()
+  #define IDS_TIMEOUT_CTL(t)
+  #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+  #define CONSOLE(s, ...)
+#endif
+
+#define IDS_TRACE_SHOW_BLD_OPT_CFG  IDSOPT_TRACE_USER_OPTIONS
+
+#if IDSOPT_PERF_ANALYSIS == TRUE
+  #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
+  #define IDS_PERF_ANALYSE(StdHeader)
+  #define IDS_PERF_TIME_MEASURE(StdHeader)
+#else
+  #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
+  #define IDS_PERF_ANALYSE(StdHeader)
+  #define IDS_PERF_TIME_MEASURE(StdHeader)
+#endif
+
+///For IDS feat use
+#define IDS_FAMILY_ALL  0x0ull
+#define IDS_BSP_ONLY    TRUE
+#define IDS_ALL_CORES   FALSE
+
+#define IDS_LATE_RUN_AP_TASK_ID     PROC_IDS_CONTROL_IDSLIB_FILECODE
+
+#define IDS_CALLOUT_INIT      0x00       ///< The function data of IDS callout function of initialization.
+
+#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE      0x00       ///< The function data of IDS callout function of GNB pp fuse table.
+#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG      0x00       ///< The function data of IDS callout function of GNB integrated table.
+#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG      0x00       ///< The function data of IDS callout function of GNB NB power gate config.
+#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG      0x00       ///< The function data of IDS callout function of GNB PCIE power gateconfig.
+#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG      0x00       ///< The function data of IDS callout function of GNB pcie platform config.
+#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG           0x00       ///< The function data of IDS callout function of GNB pcie PHY config.
+#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE           0x00       ///< The function data of IDS callout function of GNB GMM register override
+
+/// Function entry for HDT script to call
+typedef struct _SCRIPT_FUNCTION {
+  UINT32  FuncAddr;       ///< Function address in ROM
+  CHAR8   FuncName[40];   ///< Function name
+} SCRIPT_FUNCTION;
+
+/// Data Structure for Mem ECC parameter override
+typedef struct {
+  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection
+  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate
+  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate
+  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate
+  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate
+  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate
+  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood
+} ECC_OVERRIDE_STRUCT;
+
+
+
+
+/**
+ *  AGESA Test Points
+ *
+ *  These are the values displayed to the user to indicate progress through boot.
+ *  These can be used in a debug environment to stop the debugger at a specific
+ *  test point:
+ *  For SimNow!, this command
+ *      bi 81 w vb 49
+ *  will stop the debugger on one of the TracePoints (49 is the TP value in this example).
+ *
+ */
+typedef enum {
+  StartProcessorTestPoints,           ///< 00 Entry used for range testing for @b Processor related TPs
+
+  // Memory test points
+  TpProcMemBeforeMemDataInit,         ///< 01 .. Memory structure initialization (Public interface)
+  TpProcMemBeforeSpdProcessing,       ///< 02 .. SPD Data processing  (Public interface)
+  TpProcMemAmdMemAuto,                ///< 03 .. Memory configuration  (Public interface)
+  TpProcMemDramInit,                  ///< 04 .. DRAM initialization
+  TpProcMemSPDChecking,               ///< 05 ..
+  TpProcMemModeChecking,              ///< 06 ..
+  TpProcMemSpeedTclConfig,            ///< 07 .. Speed and TCL configuration
+  TpProcMemSpdTiming,                 ///< 08 ..
+  TpProcMemDramMapping,               ///< 09 ..
+  TpProcMemPlatformSpecificConfig,    ///< 0A ..
+  TPProcMemPhyCompensation,           ///< 0B ..
+  TpProcMemStartDcts,                 ///< 0C ..
+  TpProcMemBeforeDramInit,            ///< 0D .. (Public interface)
+  TpProcMemPhyFenceTraining,          ///< 0E ..
+  TpProcMemSynchronizeDcts,           ///< 0F ..
+  TpProcMemSystemMemoryMapping,       ///< 10 ..
+  TpProcMemMtrrConfiguration,         ///< 11 ..
+  TpProcMemDramTraining,              ///< 12 ..
+  TpProcMemBeforeAnyTraining,         ///< 13 .. (Public interface)
+  TpProcMemWriteLevelizationTraining, ///< 14 ..
+  TpProcMemWlFirstPass,               ///< 15 .. Below 800Mhz first pass start
+  TpProcMemWlSecondPass,              ///< 16 .. Above 800Mhz second pass start
+  TpProcMemWlDimmConfig,              ///< 17 .. Target DIMM configured
+  TpProcMemWlPrepDimms,               ///< 18 ..  Prepare DIMMS for WL
+  TpProcMemWlConfigDimms,             ///< 19 ..  Configure DIMMS for WL
+  TpProcMemReceiverEnableTraining,    ///< 1A ..
+  TpProcMemRcvrStartSweep,            ///< 1B .. Start sweep loop
+  TpProcMemRcvrSetDelay,              ///< 1C .. Set receiver Delay
+  TpProcMemRcvrWritePattern,          ///< 1D .. Write test pattern
+  TpProcMemRcvrReadPattern,           ///< 1E .. Read test pattern
+  TpProcMemRcvrTestPattern,           ///< 1F .. Compare test pattern
+  TpProcMemRcvrCalcLatency,           ///< 20 .. Calculate MaxRdLatency per channel
+  TpProcMemReceiveDqsTraining,        ///< 21 ..
+  TpProcMemRcvDqsSetDelay,            ///< 22 .. Set Write Data delay
+  TpProcMemRcvDqsWritePattern,        ///< 23 .. Write test pattern
+  TpProcMemRcvDqsStartSweep,          ///< 24 .. Start read sweep
+  TpProcMemRcvDqsSetRcvDelay,         ///< 25 .. Set Receive DQS delay
+  TpProcMemRcvDqsReadPattern,         ///< 26 .. Read Test pattern
+  TpProcMemRcvDqsTstPattern,          ///< 27 .. Compare Test pattern
+  TpProcMemRcvDqsResults,             ///< 28 .. Update results
+  TpProcMemRcvDqsFindWindow,          ///< 29 .. Start Find passing window
+  TpProcMemTransmitDqsTraining,       ///< 2A ..
+  TpProcMemTxDqStartSweep,            ///< 2B .. Start write sweep
+  TpProcMemTxDqSetDelay,              ///< 2C .. Set Transmit DQ delay
+  TpProcMemTxDqWritePattern,          ///< 2D .. Write test pattern
+  TpProcMemTxDqReadPattern,           ///< 2E .. Read Test pattern
+  TpProcMemTxDqTestPattern,           ///< 2F .. Compare Test pattern
+  TpProcMemTxDqResults,               ///< 30 .. Update results
+  TpProcMemTxDqFindWindow,            ///< 31 .. Start Find passing window
+  TpProcMemMaxRdLatencyTraining,      ///< 32 ..
+  TpProcMemMaxRdLatStartSweep,        ///< 33 .. Start sweep
+  TpProcMemMaxRdLatSetDelay,          ///< 34 .. Set delay
+  TpProcMemMaxRdLatWritePattern,      ///< 35 .. Write test pattern
+  TpProcMemMaxRdLatReadPattern,       ///< 36 .. Read Test pattern
+  TpProcMemMaxRdLatTestPattern,       ///< 37 .. Compare Test pattern
+  TpProcMemOnlineSpareInit,           ///< 38 .. Online Spare init
+  TpProcMemBankInterleaveInit,        ///< 39 .. Bank Interleave Init
+  TpProcMemNodeInterleaveInit,        ///< 3A .. Node Interleave Init
+  TpProcMemChannelInterleaveInit,     ///< 3B .. Channel Interleave Init
+  TpProcMemEccInitialization,         ///< 3C .. ECC initialization
+  TpProcMemPlatformSpecificInit,      ///< 3D .. Platform Specific Init
+  TpProcMemBeforeAgesaReadSpd,        ///< 3E .. Before callout for "AgesaReadSpd"
+  TpProcMemAfterAgesaReadSpd,         ///< 3F .. After callout for "AgesaReadSpd"
+  TpProcMemBeforeAgesaHookBeforeDramInit,     ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterAgesaHookBeforeDramInit,      ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
+  TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
+  TpProcMemAfterAgesaHookBeforeDQSTraining,  ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
+  TpProcMemBeforeAgesaHookBeforeExitSelfRef,     ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterAgesaHookBeforeExitSelfRef,      ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterMemDataInit,          ///< 46 .. After MemDataInit
+  TpProcMemInitializeMCT,             ///< 47 .. Before InitializeMCT
+  TpProcMemLvDdr3,                    ///< 48 .. Before LV DDR3
+  TpProcMemInitMCT,                   ///< 49 .. Before InitMCT
+  TpProcMemOtherTiming,               ///< 4A.. Before OtherTiming
+  TpProcMemUMAMemTyping,              ///< 4B .. Before UMAMemTyping
+  TpProcMemSetDqsEccTmgs,             ///< 4C .. Before SetDqsEccTmgs
+  TpProcMemMemClr,                    ///< 4D .. Before MemClr
+  TpProcMemOnDimmThermal,             ///< 4E .. Before On DIMM Thermal
+  TpProcMemDmi,                       ///< 4F .. Before DMI
+  TpProcMemEnd,                       ///< 50 .. End of memory code
+
+  // CPU test points
+  TpProcCpuEntryDmi,                  ///< 51 .. Entry point CreateDmiRecords
+  TpProcCpuEntryPstate,               ///< 52 .. Entry point GenerateSsdt
+  TpProcCpuEntryPstateLeveling,       ///< 53 .. Entry point PStateLeveling
+  TpProcCpuEntryPstateGather,         ///< 54 .. Entry point PStateGatherData
+  TpProcCpuEntryWhea,                 ///< 55 .. Entry point CreateAcpiWhea
+  TpProcCpuEntrySrat,                 ///< 56 .. Entry point CreateAcpiSrat
+  TpProcCpuEntrySlit,                 ///< 57 .. Entry point CreateAcpiSlit
+  TpProcCpuProcessRegisterTables,     ///< 58 .. Register table processing
+  TpProcCpuSetBrandID,                ///< 59 .. Set brand ID
+  TpProcCpuLocalApicInit,             ///< 5A .. Initialize local APIC
+  TpProcCpuLoadUcode,                 ///< 5B .. Load microcode patch
+  TpProcCpuBeforePMFeatureInit,       ///< 5C .. BeforePM feature dispatch point
+  TpProcCpuPowerMgmtInit,             ///< 5D .. Power Management table processing
+  TpProcCpuEarlyFeatureInit,          ///< 5E .. Early feature dispatch point
+  TpProcCpuCoreLeveling,              ///< 5F .. Core Leveling
+  TpProcCpuApMtrrSync,                ///< 60 .. AP MTRR sync up
+  TpProcCpuPostFeatureInit,           ///< 61 .. POST feature dispatch point
+  TpProcCpuFeatureLeveling,           ///< 62 .. CPU Feature Leveling
+  TpProcCpuBeforeAllocateWheaBuffer,  ///< 63 .. Before the WHEA init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateWheaBuffer,   ///< 64 .. After the WHEA init code calls out to allocate a buffer
+  TpProcCpuBeforeAllocateSratBuffer,  ///< 65 .. Before the SRAT init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateSratBuffer,   ///< 66 .. After the SRAT init code calls out to allocate a buffer
+  TpProcCpuBeforeLocateSsdtBuffer,    ///< 67 .. Before the P-state init code calls out to locate a buffer
+  TpProcCpuAfterLocateSsdtBuffer,     ///< 68 .. After the P-state init code calls out to locate a buffer
+  TpProcCpuBeforeAllocateSsdtBuffer,  ///< 69 .. Before the P-state init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateSsdtBuffer,   ///< 6A .. After the P-state init code calls out to allocate a buffer
+
+  // HT test points
+  TpProcHtEntry = 0x71,               ///< 71 .. Coherent Discovery begin (Public interface)
+  TpProcHtTopology,                   ///< 72 .. Topology match, routing, begin
+  TpProcHtManualNc,                   ///< 73 .. Manual Non-coherent Init begin
+  TpProcHtAutoNc,                     ///< 74 .. Automatic Non-coherent init begin
+  TpProcHtOptGather,                  ///< 75 .. Optimization: Gather begin
+  TpProcHtOptRegang,                  ///< 76 .. Optimization: Regang begin
+  TpProcHtOptLinks,                   ///< 77 .. Optimization: Link Begin
+  TpProcHtOptSubLinks,                ///< 78 .. Optimization: Sublinks begin
+  TpProcHtOptFinish,                  ///< 79 .. Optimization: Set begin
+  TpProcHtTrafficDist,                ///< 7A .. Traffic Distribution begin
+  TpProcHtTuning,                     ///< 7B .. Misc Tuning Begin
+  TpProcHtDone,                       ///< 7C .. HT Init complete
+  TpProcHtApMapEntry,                 ///< 7D .. AP HT: Init Maps begin
+  TpProcHtApMapDone,                  ///< 7E .. AP HT: Complete
+
+  StartNbTestPoints = 0x90,           ///< 90 Entry used for range testing for @b NorthBridge related TPs
+  TpNbxxx,                            ///< 91 .
+  EndNbTestPoints,                    ///< 92 End of TP range for NB
+
+  StartSbTestPoints = 0xB0,           ///< B0 Entry used for range testing for @b SouthBridge related TPs
+  TpSbxxx,                            ///< B1 .
+  EndSbTestPoints,                    ///< B2 End of TP range for SB
+
+  // Interface test points
+  TpIfAmdInitResetEntry = 0xC0,       ///< C0 .. Entry to AmdInitReset
+  TpIfAmdInitResetExit,               ///< C1 .. Exiting from AmdInitReset
+  TpIfAmdInitRecoveryEntry,           ///< C2 .. Entry to AmdInitRecovery
+  TpIfAmdInitRecoveryExit,            ///< C3 .. Exiting from AmdInitRecovery
+  TpIfAmdInitEarlyEntry,              ///< C4 .. Entry to AmdInitEarly
+  TpIfAmdInitEarlyExit,               ///< C5 .. Exiting from AmdInitEarly
+  TpIfAmdInitPostEntry,               ///< C6 .. Entry to AmdInitPost
+  TpIfAmdInitPostExit,                ///< C7 .. Exiting from AmdInitPost
+  TpIfAmdInitEnvEntry,                ///< C8 .. Entry to AmdInitEnv
+  TpIfAmdInitEnvExit,                 ///< C9 .. Exiting from AmdInitEnv
+  TpIfAmdInitMidEntry,                ///< CA .. Entry to AmdInitMid
+  TpIfAmdInitMidExit,                 ///< CB .. Exiting from AmdInitMid
+  TpIfAmdInitLateEntry,               ///< CC .. Entry to AmdInitLate
+  TpIfAmdInitLateExit,                ///< CD .. Exiting from AmdInitLate
+  TpIfAmdS3SaveEntry,                 ///< CE .. Entry to AmdS3Save
+  TpIfAmdS3SaveExit,                  ///< CF .. Exiting from AmdS3Save
+  TpIfAmdInitResumeEntry,             ///< D0 .. Entry to AmdInitResume
+  TpIfAmdInitResumeExit,              ///< D1 .. Exiting from AmdInitResume
+  TpIfAmdS3LateRestoreEntry,          ///< D2 .. Entry to AmdS3LateRestore
+  TpIfAmdS3LateRestoreExit,           ///< D3 .. Exiting from AmdS3LateRestore
+  TpIfAmdLateRunApTaskEntry,          ///< D4 .. Entry to AmdS3LateRestore
+  TpIfAmdLateRunApTaskExit,           ///< D5 .. Exiting from AmdS3LateRestore
+  TpIfAmdReadEventLogEntry,           ///< D6 .. Entry to AmdReadEventLog
+  TpIfAmdReadEventLogExit,            ///< D7 .. Exiting from AmdReadEventLog
+  TpIfAmdGetApicIdEntry,              ///< D8 .. Entry to AmdGetApicId
+  TpIfAmdGetApicIdExit,               ///< D9 .. Exiting from AmdGetApicId
+  TpIfAmdGetPciAddressEntry,          ///< DA .. Entry to AmdGetPciAddress
+  TpIfAmdGetPciAddressExit,           ///< DB .. Exiting from AmdGetPciAddress
+  TpIfAmdIdentifyCoreEntry,           ///< DC .. Entry to AmdIdentifyCore
+  TpIfAmdIdentifyCoreExit,            ///< DD .. Exiting from AmdIdentifyCore
+  TpIfBeforeRunApFromIds,             ///< DE .. After IDS calls out to run code on an AP
+  TpIfAfterRunApFromIds,              ///< DF .. After IDS calls out to run code on an AP
+  TpIfBeforeGetIdsData,               ///< E0 .. Before IDS calls out to get IDS data
+  TpIfAfterGetIdsData,                ///< E1 .. After IDS calls out to get IDS data
+  TpIfBeforeAllocateHeapBuffer,       ///< E2 .. Before the heap manager calls out to allocate a buffer
+  TpIfAfterAllocateHeapBuffer,        ///< E3 .. After the heap manager calls out to allocate a buffer
+  TpIfBeforeDeallocateHeapBuffer,     ///< E4 .. Before the heap manager calls out to deallocate a buffer
+  TpIfAfterDeallocateHeapBuffer,      ///< E5 .. After the heap manager calls out to deallocate a buffer
+  TpIfBeforeLocateHeapBuffer,         ///< E6 .. Before the heap manager calls out to locate a buffer
+  TpIfAfterLocateHeapBuffer,          ///< E7 .. After the heap manager calls out to locate a buffer
+  TpIfBeforeRunApFromAllAps,          ///< E8 .. Before the BSP calls out to run code on an AP
+  TpIfAfterRunApFromAllAps,           ///< E9 .. After the BSP calls out to run code on an AP
+  TpIfBeforeRunApFromAllCore0s,       ///< EA .. Before the BSP calls out to run code on an AP
+  TpIfAfterRunApFromAllCore0s,        ///< EB .. After the BSP calls out to run code on an AP
+  TpIfBeforeAllocateS3SaveBuffer,     ///< EC .. Before the S3 save code calls out to allocate a buffer
+  TpIfAfterAllocateS3SaveBuffer,      ///< ED .. After the S3 save code calls out to allocate a buffer
+  TpIfBeforeAllocateMemoryS3SaveBuffer,  ///< EE .. Before the memory S3 save code calls out to allocate a buffer
+  TpIfAfterAllocateMemoryS3SaveBuffer,   ///< EF .. After the memory S3 save code calls out to allocate a buffer
+  TpIfBeforeLocateS3PciBuffer,        ///< F0 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3PciBuffer,         ///< F1 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3CPciBuffer,       ///< F2 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3CPciBuffer,        ///< F3 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3MsrBuffer,        ///< F4 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3MsrBuffer,         ///< F5 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3CMsrBuffer,       ///< F6 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3CMsrBuffer,        ///< F7 .. After the memory code calls out to locate a buffer
+  TpPerfUnit,                              ///< F8 .. The Unit of performance measure.
+  EndAgesaTps = 0xFF,                 ///< Last defined AGESA TP
+} AGESA_TP;
+
+///Ids Feat description
+typedef enum {
+  IDS_FEAT_UCODE_UPDATE = 0x0000,   ///< Feat for Ucode Update
+  IDS_FEAT_TARGET_PSTATE,           ///< Feat for Target Pstate
+  IDS_FEAT_POSTPSTATE,              ///< Feat for Post Pstate
+  IDS_FEAT_ECC_CTRL,                ///< Feat for Ecc Control
+  IDS_FEAT_ECC_SYMBOL_SIZE,         ///< Feat for Ecc symbol size
+  IDS_FEAT_DCT_ALLMEMCLK,           ///< Feat for all memory clock
+  IDS_FEAT_DCT_GANGMODE,            ///< Feat for Dct gang mode
+  IDS_FEAT_DCT_BURSTLENGTH,         ///< Feat for dct burst length
+  IDS_FEAT_DCT_POWERDOWN,           ///< Feat for dct power down
+  IDS_FEAT_DCT_DLLSHUTDOWN,         ///< Feat for dct dll shut down
+  IDS_FEAT_PROBE_FILTER,            ///< Feat for probe filter
+  IDS_FEAT_HDTOUT,                  ///< Feat for hdt out
+  IDS_FEAT_HT_SETTING,              ///< Feat for Ht setting
+  IDS_FEAT_GNB_PLATFORMCFG,                 ///< Feat for override GNB platform config
+  IDS_FEAT_CPB_CTRL,             ///< Feat for Config the Core peformance boost feature
+  IDS_FEAT_HTC_CTRL,            ///< Feat for Hardware Thermal Control
+  IDS_FEAT_MEMORY_MAPPING,              ///< Feat for Memory Mapping
+  IDS_FEAT_POWER_POLICY,              ///< Feat for Power Policy
+  IDS_FEAT_END = 0xFF                      ///< End of Common feat
+} IDS_FEAT;
+
+typedef IDS_STATUS IDS_COMMON_FUNC (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
+
+/// Data Structure of IDS Feature block
+typedef  struct _IDS_FEAT_STRUCT {
+  IDS_FEAT  IdsFeat;      ///< Ids Feat ID
+  BOOLEAN IsBsp;          ///< swith for Bsp check
+  AGESA_IDS_OPTION IdsOption;   ///< IDS option
+  UINT64 CpuFamily;      ///<
+  PIDS_COMMON_FUNC  pf_idsoption;     ///<pointer to function
+} IDS_FEAT_STRUCT;
+
+
+/// Data Structure of IDS option
+typedef  struct _IDS_OPTION_STRUCT {
+  AGESA_IDS_OPTION idsoption;   ///< IDS option
+  PIDS_COMMON_FUNC  pf_idsoption;     ///<pointer to function
+} IDS_OPTION_STRUCT;
+
+/// Data Structure of IDS option table
+typedef struct _IDS_OPTION_STRUCT_TBL {
+  UINT8 version;      ///<Version of IDS option table
+  UINT16 size;        ///<Size of IDS option table
+  CONST IDS_OPTION_STRUCT  *pIdsOptionStruct; ///<pointer to array of  structure
+} IDS_OPTION_STRUCT_TBL;
+
+#endif // _IDS_H_

Added: trunk/src/vendorcode/amd/agesa/Include/IdsHt.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/IdsHt.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,126 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS HyperTransport Definitions
+ *
+ * Contains AMD AGESA Integrated Debug HT related items.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _IDS_HT_H_
+#define _IDS_HT_H_
+
+// Frequency equates for call backs which take an actual frequency setting
+#define HT_FREQUENCY_200M            0
+#define HT_FREQUENCY_400M            2
+#define HT_FREQUENCY_600M            4
+#define HT_FREQUENCY_800M            5
+#define HT_FREQUENCY_1000M           6
+#define HT_FREQUENCY_1200M           7
+#define HT_FREQUENCY_1400M           8
+#define HT_FREQUENCY_1600M           9
+#define HT_FREQUENCY_1800M           10
+#define HT_FREQUENCY_2000M           11
+#define HT_FREQUENCY_2200M           12
+#define HT_FREQUENCY_2400M           13
+#define HT_FREQUENCY_2600M           14
+#define HT_FREQUENCY_2800M           17
+#define HT_FREQUENCY_3000M           18
+#define HT_FREQUENCY_3200M           19
+#define HT_FREQUENCY_3600M           20
+
+/**
+ * HT IDS: HT Link Port Override params.
+ *
+ * Provide an absolute override of HT Link Port settings.  No checking is done that
+ * the settings obey limits or capabilities, this responsibility rests with the user.
+ *
+ * Rules for values of structure items:
+ * - Socket
+ *   - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
+ *   - HT_LIST_MATCH_ANY == Match Any Socket
+ *   - 0 .. 7 == The matching socket
+ * - Link
+ *   - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
+ *   - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
+ *   - 0 .. 7 == The matching package link.  0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
+ * - Frequency
+ *   - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
+ *   - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
+ * - Widthin
+ *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ *   - 2, 4, 8, 16, 32 == The width value to use
+ * - Widthout
+ *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ *   - 2, 4, 8, 16, 32 == The width value to use
+ */
+typedef struct {
+  // Match Fields
+  UINT8       Socket;      ///< The Socket which this port is on.
+  UINT8       Link;        ///< The port for this package link on that socket.
+  // Override fields
+  UINT8       Frequency;   ///< Absolutely override the port's frequency.
+  UINT8       WidthIn;     ///< Absolutely override the port's width.
+  UINT8       WidthOut;    ///< Absolutely override the port's width.
+} HTIDS_PORT_OVERRIDE;
+
+/**
+ * A list of port overrides to search.
+ */
+typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
+VOID
+HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  );
+
+typedef
+VOID
+F_HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  );
+typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
+#endif // _IDS_HT_H

Added: trunk/src/vendorcode/amd/agesa/Include/LynxInstall.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/LynxInstall.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Lynx platform solution
+ *
+ * This file generates the defaults tables for the "Lynx" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 37651 $   @e \$Date: 2010-09-09 07:05:06 +0800 (Thu, 09 Sep 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "LlanoPI "
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
+
+
+// The Lynx solution is defined to be family 0x12 in the FM1 socket.
+#define INSTALL_FM1_SOCKET_SUPPORT       TRUE
+#define INSTALL_FAMILY_12_SUPPORT        TRUE
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0)
+#define DFLT_SCRUB_L2_RATE              (0)
+#define DFLT_SCRUB_L3_RATE              (0)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (5000)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+

Added: trunk/src/vendorcode/amd/agesa/Include/MaranelloInstall.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/MaranelloInstall.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,118 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Maranello platform solution
+ *
+ * This file generates the defaults tables for the "Maranello" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                    // This is the delivery package title, "MarG34PI"
+                    // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
+
+                    // This is the release version number of the AGESA component
+                    // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
+
+
+
+// The Maranello solution is defined to be families 0x10 and 0x15 in the G34 socket.
+#define INSTALL_G34_SOCKET_SUPPORT       TRUE
+#define INSTALL_FAMILY_10_SUPPORT        TRUE
+#define INSTALL_FAMILY_15_SUPPORT        TRUE
+
+#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
+  #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
+    #undef INSTALL_FAMILY_10_SUPPORT
+    #define INSTALL_FAMILY_10_SUPPORT     FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
+  #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
+    #undef INSTALL_FAMILY_15_SUPPORT
+    #define INSTALL_FAMILY_15_SUPPORT     FALSE
+  #endif
+#endif
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0xFF)
+#define DFLT_SCRUB_L2_RATE              (0x10)
+#define DFLT_SCRUB_L3_RATE              (0x10)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (2500)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+

Added: trunk/src/vendorcode/amd/agesa/Include/NileInstall.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/NileInstall.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Nile platform solution
+ *
+ * This file generates the defaults tables for the "Nile" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "DanNiPI "
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
+
+
+// The Nile solution is defined to be family 0x10 in the ASB2 socket.
+#define INSTALL_ASB2_SOCKET_SUPPORT      TRUE
+#define INSTALL_FAMILY_10_SUPPORT        TRUE
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0)
+#define DFLT_SCRUB_L2_RATE              (0)
+#define DFLT_SCRUB_L3_RATE              (0)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (5000)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+

Added: trunk/src/vendorcode/amd/agesa/Include/OptionC6Install.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/vendorcode/amd/agesa/Include/OptionC6Install.h	Mon Feb 14 19:30:54 2011	(r6344)
@@ -0,0 +1,151 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: C6 C-state
+ *
+ * Contains AMD AGESA ins