[coreboot] [commit] r6395 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdfam10 northbridge/amd/amdht northbridge/amd/amdmct
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Mon Feb 28 01:10:38 CET 2011
Author: mjones
Date: Mon Feb 28 01:10:37 2011
New Revision: 6395
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6395
Log:
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Bring F3xD4 (Clock/Power Control Register 0) more in line
with BKDG i more cases. It requires looking at the CPU package type
so I add a function for that (in the wrong place?) and some
new constants
Signed-off-by: Xavi Drudis Ferran <xdrudis at tinet.cat>
Acked-by: Marc Jones <marcj303 at gmail.com>
Modified:
trunk/src/cpu/amd/model_10xxx/fidvid.c
trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c
trunk/src/northbridge/amd/amdht/AsPsDefs.h
trunk/src/northbridge/amd/amdmct/amddefs.h
Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:00:51 2011 (r6394)
+++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:10:37 2011 (r6395)
@@ -179,16 +179,51 @@
pci_write_config32(dev, 0xd8, dtemp);
}
-static u32 power_up_down(int node) {
+static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
+ u8 link0isGen3 = 0;
+ u8 offset;
+ if (AMD_CpuFindCapability(node, 0, &offset)) {
+ link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 );
+ }
+ /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package
+ S1g3 in link Gen3 mode, but I don't know how to tell
+ package S1g3 from S1g4 */
+ if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX)
+ && link0isGen3) {
+ return 5 ; /* divide clk by 128*/
+ } else {
+ return 4 ; /* divide clk by 16 */
+ }
+}
+
+
+static u32 power_up_down(int node, u8 procPkg) {
u32 dword=0;
- /* check platform type */
- if (!(get_platform_type() & AMD_PTYPE_SVR)) {
- /* For non-server platform
- * PowerStepUp=01000b - 50nS
- * PowerStepDown=01000b - 50ns
- */
- dword |= PW_STP_UP50 | PW_STP_DN50 ;
+ /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */
+ u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2)
+ || (procPkg == AMD_PKGTYPE_S1gX)
+ || (procPkg == AMD_PKGTYPE_ASB2));
+
+ if (singleLinkFlag) {
+ /*
+ * PowerStepUp=01000b - 50nS
+ * PowerStepDown=01000b - 50ns
+ */
+ dword |= PW_STP_UP50 | PW_STP_DN50;
} else {
+ u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1;
+ u32 isocEn = 0;
+ int j;
+ for(j=0 ; (j<4) && (!isocEn) ; j++ ) {
+ u8 offset;
+ if (AMD_CpuFindCapability(node, j, &offset)) {
+ isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1;
+ }
+ }
+
+ if (dispRefModeEn || isocEn) {
+ dword |= PW_STP_UP50 | PW_STP_DN50 ;
+ } else {
/* get number of cores for PowerStepUp & PowerStepDown in server
1 core - 400nS - 0000b
2 cores - 200nS - 0010b
@@ -210,28 +245,31 @@
dword |= PW_STP_UP100 | PW_STP_DN100;
break;
}
+ }
}
return dword;
}
-static void config_clk_power_ctrl_reg0(int node) {
+static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
device_t dev = NODE_PCI(node, 3);
-
/* Program fields in Clock Power/Control register0 (F3xD4) */
/* set F3xD4 Clock Power/Timing Control 0 Register
* NbClkDidApplyAll=1b
- * NbClkDid=100b
+ * NbClkDid=100b or 101b
* PowerStepUp= "platform dependent"
* PowerStepDown= "platform dependent"
* LinkPllLink=01b
- * ClkRampHystSel=HW default
+ * ClkRampHystCtl=HW default
+ * ClkRampHystSel=1111b
*/
u32 dword= pci_read_config32(dev, 0xd4);
dword &= CPTC0_MASK;
- dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; /* per BKDG */
- dword |= power_up_down(node);
+ dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL;
+ dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT);
+
+ dword |= power_up_down(node, procPkg);
pci_write_config32(dev, 0xd4, dword);
@@ -296,13 +334,15 @@
for (i = 0; i < nodes; i++) {
printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
dev = NODE_PCI(i, 3);
+ u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
+ u8 procPkg = mctGetProcessorPackageType();
setVSRamp(dev);
/* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
/* Figure out the value for VsSlamTime and program it */
recalculateVsSlamTimeSettingOnCorePre(dev);
- config_clk_power_ctrl_reg0(i);
+ config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
config_power_ctrl_misc_reg(dev);
Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Mon Feb 28 01:00:51 2011 (r6394)
+++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Mon Feb 28 01:10:37 2011 (r6395)
@@ -214,6 +214,11 @@
return ret;
}
+static u8 mctGetProcessorPackageType(void) {
+ /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */
+ u32 BrandId = cpuid_ebx(0x80000001);
+ return (u8)((BrandId >> 28) & 0x0F);
+}
static void raminit_amdmct(struct sys_info *sysinfo)
{
Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h
==============================================================================
--- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:00:51 2011 (r6394)
+++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:10:37 2011 (r6395)
@@ -111,6 +111,7 @@
#define NB_FID_EN 0x20 /* NbFidEn bit ON */
#define NB_CLKDID_ALL 0x80000000 /* NbClkDidApplyAll bit ON */
#define NB_CLKDID 0x40000000 /* NbClkDid value set by BIOS */
+#define NB_CLKDID_SHIFT 28 /* NbClkDid bit shift */
#define PW_STP_UP50 0x08000000 /* PowerStepUp 50nS(1000b) */
#define PW_STP_DN50 0x00800000 /* PowerStepDown 50nS (1000b)*/
#define PW_STP_UP100 0x03000000 /* PowerStepUp 100nS(0011b) */
@@ -119,6 +120,11 @@
#define PW_STP_DN200 0x00200000 /* PowerStepDown 200nS (0010b)*/
#define PW_STP_UP400 0x00000000 /* PowerStepUp 400nS(0000b) */
#define PW_STP_DN400 0x00000000 /* PowerStepDown 400nS (0000b)*/
+#define CLK_RAMP_HYST_SEL_VAL 0x00000f00 /* value mask for clock ramp
+ hysteresis select. BIOS
+ should program
+ F3xC4[ClkRampHystSel] to
+ 1111b */
#define LNK_PLL_LOCK 0x00010000 /* LnkPllLock value set (01b) by BIOS */
Modified: trunk/src/northbridge/amd/amdmct/amddefs.h
==============================================================================
--- trunk/src/northbridge/amd/amdmct/amddefs.h Mon Feb 28 01:00:51 2011 (r6394)
+++ trunk/src/northbridge/amd/amdmct/amddefs.h Mon Feb 28 01:10:37 2011 (r6395)
@@ -134,3 +134,13 @@
#define DC_CFG 0xC0011022
#define BU_CFG 0xC0011023
#define BU_CFG2 0xC001102A
+
+/*
+ * Processor package types
+ */
+#define AMD_PKGTYPE_FrX_1207 0
+#define AMD_PKGTYPE_AM3_2r2 1
+#define AMD_PKGTYPE_S1gX 2
+#define AMD_PKGTYPE_G34 3
+#define AMD_PKGTYPE_ASB2 4
+#define AMD_PKGTYPE_C32 5
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