[coreboot] [commit] r6405 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht

[repository service]

Author: mjones
Date: Mon Feb 28 04:25:07 2011
New Revision: 6405
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6405

Log:
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Add an untested step in BKDG 2.4.2.8. I don't
have the hardware with Core Performance Boost and
I think it's only available in revision E that does
not even have a constant yet.

Signed-off-by: Xavi Drudis Ferran <xdrudis at tinet.cat>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/cpu/amd/model_10xxx/fidvid.c
   trunk/src/northbridge/amd/amdht/AsPsDefs.h

Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/fidvid.c	Mon Feb 28 04:19:17 2011	(r6404)
+++ trunk/src/cpu/amd/model_10xxx/fidvid.c	Mon Feb 28 04:25:07 2011	(r6405)
@@ -65,6 +65,24 @@
 		       dword);
 	}
 }
+
+static void applyBoostFIDOffset(  device_t dev ) {
+  // BKDG 2.4.2.8
+  // revision E only, but E is apparently not supported yet, therefore untested
+  if ((cpuid_edx(0x80000007) & CPB_MASK)
+      &&  ((cpuid_ecx(0x80000008) & NC_MASK) ==5) ) {
+      u32 core =  get_node_core_id_x().coreid;
+      u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3;
+      msr_t msr =  rdmsr(PS_REG_BASE);
+      u32 cpuFid = msr.lo & PS_CPU_FID_MASK;
+      cpuFid = cpuFid + asymetricBoostThisCore;
+      msr.lo &=   ~PS_CPU_FID_MASK;
+      msr.lo |= cpuFid ; 
+      wrmsr(PS_REG_BASE , msr);
+    
+  }
+}
+
 static void enableNbPState1( device_t dev ) {
   u32 cpuRev =  mctGetLogicalCPUID(0xFF);
   if (cpuRev & AMD_FAM10_C3) {
@@ -872,7 +890,9 @@
 	pci_write_config32(dev, 0xA0, dtemp);
 
         dualPlaneOnly(dev);
+        applyBoostFIDOffset(dev);
         enableNbPState1(dev);
+
 	finalPstateChange();
 
 	/* Set TSC to tick at the P0 ndfid rate */

Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h
==============================================================================
--- trunk/src/northbridge/amd/amdht/AsPsDefs.h	Mon Feb 28 04:19:17 2011	(r6404)
+++ trunk/src/northbridge/amd/amdht/AsPsDefs.h	Mon Feb 28 04:25:07 2011	(r6405)
@@ -61,6 +61,8 @@
 #define PS_NB_VID_SHFT 25		/* P-state NBVID shift */
 #define PS_DIS 0x7fffffff		/* disable P-state reg */
 #define PS_EN 0x80000000		/* enable P-state reg */
+#define PS_CPU_FID_MASK 0x03f           /* MSRC001_00[68:64][CpuFid]
+					   Core Frequency Id */
 #define PS_CURDIV_SHFT 8		/* P-state Current Divisor shift position */
 #define PS_CPUDID_SHIFT 6		/* P-state CPU DID shift position */
 
@@ -202,6 +204,8 @@
 
 #define CPB_MASK 0x00000020             /* core performance
 					   boost. CPUID Fn8000 0007 edx */
+#define NC_MASK 0x000000FF              /* number of cores - 1. CPUID
+					   Fn8000 0008 ecx */
 #define PW_CTL_MISC 0x0a0		/* Power Control Miscellaneous Register */
 #define COF_VID_PROG_BIT 0x80000000	/* CofVidProg bit. 0= unfused part */
 #define DUAL_VDD_BIT 0x40000000	/* DualVdd bit. */