From rogerx.oss at gmail.com Sat Jan 1 02:02:09 2011 From: rogerx.oss at gmail.com (Roger) Date: Fri, 31 Dec 2010 16:02:09 -0900 Subject: [coreboot] Seabios - VGA & Boot From First Hard Drive Issues In-Reply-To: <20101231163752.GD29954@morn.localdomain> References: <20101231090701.GA19849@localhost2.local> <20101231093306.GB19849@localhost2.local> <20101231095051.GC19849@localhost2.local> <20101231105404.GD19849@localhost2.local> <20101231163752.GD29954@morn.localdomain> Message-ID: <20110101010209.GC4514@localhost2.local> On Fri, Dec 31, 2010 at 11:37:52AM -0500, Kevin O'Connor wrote: >On Fri, Dec 31, 2010 at 01:54:04AM -0900, Roger wrote: >> And still getting better here. >> >> I've reset some Seabios config.h options to defaults and disabled FLOPPY >> options. > >The floppy options have no impact on seabios when in coreboot mode. >What you're seeing here is likely random failures. You should try >running the memtest program. Yup. Figured-out, the user is required to press "F12" else Seabios will try to load a floppy image as defined in milliseconds within config.h. If Seabios doesn't find a floppy image or boot image, it will then reload coreboot/reboot as defined in milliseconds within config.h. (This I find nuts, Seabios infinitely reloading coreboot over & over again. Is this correct? Great stress testing though as I can see additional reloads fail sometime over time due to raminit issues.) I prefer Seabios to sit and wait forever (an unlimited amount of time). Also, if I do get things going correctly, would prefer Seabios just go ahead and boot the bootable drive partition (or main boot record... with grub/lilo installed). If anything, a slight pause might be essential in case a user does have a floppy image installed or chooses network, usb, etc. -- Roger http://rogerx.freeshell.org/ From kevin at koconnor.net Sat Jan 1 06:45:16 2011 From: kevin at koconnor.net (Kevin O'Connor) Date: Sat, 1 Jan 2011 00:45:16 -0500 Subject: [coreboot] Seabios - VGA & Boot From First Hard Drive Issues In-Reply-To: <20110101010209.GC4514@localhost2.local> References: <20101231090701.GA19849@localhost2.local> <20101231093306.GB19849@localhost2.local> <20101231095051.GC19849@localhost2.local> <20101231105404.GD19849@localhost2.local> <20101231163752.GD29954@morn.localdomain> <20110101010209.GC4514@localhost2.local> Message-ID: <20110101054516.GA28190@morn.localdomain> On Fri, Dec 31, 2010 at 04:02:09PM -0900, Roger wrote: > On Fri, Dec 31, 2010 at 11:37:52AM -0500, Kevin O'Connor wrote: > >On Fri, Dec 31, 2010 at 01:54:04AM -0900, Roger wrote: > >> And still getting better here. > >> > >> I've reset some Seabios config.h options to defaults and disabled FLOPPY > >> options. > > > >The floppy options have no impact on seabios when in coreboot mode. > >What you're seeing here is likely random failures. You should try > >running the memtest program. > > Yup. Figured-out, the user is required to press "F12" else Seabios will try to > load a floppy image as defined in milliseconds within config.h. Hrmm - Seabios wont load from floppy under coreboot. The floppy hardware support is disabled when on coreboot. The messages you are seeing are harmless. > If Seabios doesn't find a floppy image or boot image, it will then reload > coreboot/reboot as defined in milliseconds within config.h. (This I find nuts, > Seabios infinitely reloading coreboot over & over again. Is this correct? > Great stress testing though as I can see additional reloads fail sometime over > time due to raminit issues.) > > I prefer Seabios to sit and wait forever (an unlimited amount of time). > > Also, if I do get things going correctly, would prefer Seabios just go ahead > and boot the bootable drive partition (or main boot record... with grub/lilo > installed). If anything, a slight pause might be essential in case a user does > have a floppy image installed or chooses network, usb, etc. If SeaBIOS fails to find a boot method, it will wait infinitely. You're seeing an unrelated failure here. -Kevin From rogerx.oss at gmail.com Sat Jan 1 08:31:17 2011 From: rogerx.oss at gmail.com (Roger) Date: Fri, 31 Dec 2010 22:31:17 -0900 Subject: [coreboot] Seabios - VGA & Boot From First Hard Drive Issues In-Reply-To: <20110101054516.GA28190@morn.localdomain> References: <20101231090701.GA19849@localhost2.local> <20101231093306.GB19849@localhost2.local> <20101231095051.GC19849@localhost2.local> <20101231105404.GD19849@localhost2.local> <20101231163752.GD29954@morn.localdomain> <20110101010209.GC4514@localhost2.local> <20110101054516.GA28190@morn.localdomain> Message-ID: <20110101073117.GA4518@localhost2.local> On Sat, Jan 01, 2011 at 12:45:16AM -0500, Kevin O'Connor wrote: >On Fri, Dec 31, 2010 at 04:02:09PM -0900, Roger wrote: >> On Fri, Dec 31, 2010 at 11:37:52AM -0500, Kevin O'Connor wrote: >> >On Fri, Dec 31, 2010 at 01:54:04AM -0900, Roger wrote: >> >> And still getting better here. >> >> >> >> I've reset some Seabios config.h options to defaults and disabled FLOPPY >> >> options. >> > >> >The floppy options have no impact on seabios when in coreboot mode. >> >What you're seeing here is likely random failures. You should try >> >running the memtest program. >> >> Yup. Figured-out, the user is required to press "F12" else Seabios will try to >> load a floppy image as defined in milliseconds within config.h. > >Hrmm - Seabios wont load from floppy under coreboot. The floppy >hardware support is disabled when on coreboot. The messages you are >seeing are harmless. > >> If Seabios doesn't find a floppy image or boot image, it will then reload >> coreboot/reboot as defined in milliseconds within config.h. (This I find nuts, >> Seabios infinitely reloading coreboot over & over again. Is this correct? >> Great stress testing though as I can see additional reloads fail sometime over >> time due to raminit issues.) >> >> I prefer Seabios to sit and wait forever (an unlimited amount of time). >> >> Also, if I do get things going correctly, would prefer Seabios just go ahead >> and boot the bootable drive partition (or main boot record... with grub/lilo >> installed). If anything, a slight pause might be essential in case a user does >> have a floppy image installed or chooses network, usb, etc. > >If SeaBIOS fails to find a boot method, it will wait infinitely. >You're seeing an unrelated failure here. Wooh. Then the timeout here: #define CONFIG_BOOTMENU_WAIT 2500 ... is only a wait before booting the default (floppy) image and Seabios should not be rebooting coreboot? Because if so, I'm getting an endless reboot after failure to boot the floppy image. Well anyways, I've pretty much gotten both my 440BX (Tyan 1832dl using Tyan 1846 mainboard and DFI P2BX using Asus P2B mainboard) working. Just raminit seems to be spawning random bugs. It's really nice to see these old 440BX boards being able to boot from USB pen disks! -- Roger http://rogerx.freeshell.org/ From svn at coreboot.org Sat Jan 1 18:44:08 2011 From: svn at coreboot.org (repository service) Date: Sat, 01 Jan 2011 18:44:08 +0100 Subject: [coreboot] [commit] r6229 - in trunk: . src/cpu/amd/model_10xxx src/vendorcode src/vendorcode/amd src/vendorcode/amd/cimx src/vendorcode/amd/cimx/lib src/vendorcode/amd/cimx/sb800 Message-ID: Author: uwe Date: Sat Jan 1 18:44:07 2011 New Revision: 6229 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6229 Log: Add AMD SB800 southbridge CIMx code. The main CIMx code is in a src/vendorcode directory and should not be changed with regard to coding style etc. in order to remain easily syncable with the "upstream" AMD code. Signed-off-by: Kerry She Acked-by: Stefan Reinauer Added: trunk/src/vendorcode/ trunk/src/vendorcode/Makefile.inc trunk/src/vendorcode/amd/ trunk/src/vendorcode/amd/cimx/ trunk/src/vendorcode/amd/cimx/lib/ trunk/src/vendorcode/amd/cimx/lib/Makefile.inc trunk/src/vendorcode/amd/cimx/lib/amdlib32.c trunk/src/vendorcode/amd/cimx/lib/amdlib32.h trunk/src/vendorcode/amd/cimx/sb800/ trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.h trunk/src/vendorcode/amd/cimx/sb800/AMDLIB.c trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c trunk/src/vendorcode/amd/cimx/sb800/EC.c trunk/src/vendorcode/amd/cimx/sb800/ECLIB.c trunk/src/vendorcode/amd/cimx/sb800/ECfan.h trunk/src/vendorcode/amd/cimx/sb800/ECfanLIB.c trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c trunk/src/vendorcode/amd/cimx/sb800/GEC.c trunk/src/vendorcode/amd/cimx/sb800/Gpp.c trunk/src/vendorcode/amd/cimx/sb800/IOLIB.c trunk/src/vendorcode/amd/cimx/sb800/LEGACY.c trunk/src/vendorcode/amd/cimx/sb800/MEMLIB.c trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc trunk/src/vendorcode/amd/cimx/sb800/OEM.h trunk/src/vendorcode/amd/cimx/sb800/PCILIB.c trunk/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c trunk/src/vendorcode/amd/cimx/sb800/PMIOLIB.c trunk/src/vendorcode/amd/cimx/sb800/SATA.c trunk/src/vendorcode/amd/cimx/sb800/SB800.h trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c trunk/src/vendorcode/amd/cimx/sb800/SBDEF.h trunk/src/vendorcode/amd/cimx/sb800/SBMAIN.c trunk/src/vendorcode/amd/cimx/sb800/SBPELIB.c trunk/src/vendorcode/amd/cimx/sb800/SBPOR.c trunk/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h trunk/src/vendorcode/amd/cimx/sb800/SMM.c trunk/src/vendorcode/amd/cimx/sb800/SbModInf.c trunk/src/vendorcode/amd/cimx/sb800/USB.c Modified: trunk/Makefile trunk/src/cpu/amd/model_10xxx/init_cpus.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Dec 31 20:20:23 2010 (r6228) +++ trunk/Makefile Sat Jan 1 18:44:07 2011 (r6229) @@ -126,6 +126,7 @@ BUILD-y := src/lib src/boot src/console src/devices src/southbridge src/northbridge src/superio src/drivers BUILD-y += util/cbfstool util/sconfig BUILD-$(CONFIG_ARCH_X86) += src/pc80 +BUILD-y += src/vendorcode ifneq ($(CONFIG_LOCALVERSION),"") COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION)) Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Fri Dec 31 20:20:23 2010 (r6228) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Sat Jan 1 18:44:07 2011 (r6229) @@ -27,6 +27,7 @@ #include #include +#include static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); Added: trunk/src/vendorcode/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/Makefile.inc Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1 @@ +subdirs-y += amd Added: trunk/src/vendorcode/amd/cimx/lib/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/lib/Makefile.inc Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,3 @@ + +romstage-y += amdlib32.c +ramstage-y += amdlib32.c Added: trunk/src/vendorcode/amd/cimx/lib/amdlib32.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/lib/amdlib32.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,84 @@ +#include "amdlib32.h" + +UINT8 ReadIo8 (IN UINT16 port) +{ + UINT8 value; + __asm__ __volatile__ ("inb %w1, %b0" : "=a"(value) : "Nd" (port)); + return value; +} + +UINT16 ReadIo16 (IN UINT16 port) +{ + UINT16 value; + __asm__ __volatile__ ("inw %w1, %w0" : "=a"(value) : "Nd" (port)); + return value; +} + +UINT32 ReadIo32 (IN UINT16 port) +{ + UINT32 value; + __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port)); + return value; +} + +VOID WriteIo8 (IN UINT16 port, IN UINT8 value) +{ + __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port)); +} + +VOID WriteIo16 (IN UINT16 port, IN UINT16 value) +{ + __asm__ __volatile__ ("outw %w0, %w1" : : "a" (value), "Nd" (port)); +} + +VOID WriteIo32 (IN UINT16 port, IN UINT32 value) +{ + __asm__ __volatile__ ("outl %0, %w1" : : "a" (value), "Nd" (port)); +} + +UINT64 ReadTSC(VOID) +{ + struct tsc_struct { + unsigned lo; + unsigned hi; + } res; + UINT64 ret; + + __asm__ __volatile__ ( + "rdtsc" + : "=a" (res.lo), "=d"(res.hi) /* outputs */ + ); + ret = res.hi; + ret <<= 32; + ret |= res.lo; + return ret; +} + +VOID CpuidRead(IN UINT32 op, IN OUT SB_CPUID_DATA* Data) +{ + asm volatile( + "cpuid" + : "=a" (Data->EAX_Reg), + "=b" (Data->EBX_Reg), + "=c" (Data->ECX_Reg), + "=d" (Data->EDX_Reg) + : "0" (op)); +} + +static inline unsigned int cpuid_ecx(unsigned int op) +{ + unsigned int eax, ecx; + + __asm__("cpuid" + : "=a" (eax), "=c" (ecx) + : "0" (op) + : "ebx", "edx" ); + return ecx; +} + +//static inline unsigned get_core_num(void) +UINT8 ReadNumberOfCpuCores(VOID) +{ + return (cpuid_ecx(0x80000008) & 0xff); +} + Added: trunk/src/vendorcode/amd/cimx/lib/amdlib32.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/lib/amdlib32.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,16 @@ +#ifndef _AMDLIB32_H_ +#define _AMDLIB32_H_ + +#include "cbtypes.h" +#include "Amd.h" + +UINT8 ReadIo8 (IN UINT16 port); +UINT16 ReadIo16 (IN UINT16 port); +UINT32 ReadIo32 (IN UINT16 port); +VOID WriteIo8 (IN UINT16 port, IN UINT8 value); +VOID WriteIo16 (IN UINT16 port, IN UINT16 value); +VOID WriteIo32 (IN UINT16 port, IN UINT32 value); +UINT64 ReadTSC(VOID); +VOID CpuidRead(IN UINT32 op, IN OUT SB_CPUID_DATA* Data); +UINT8 ReadNumberOfCpuCores(VOID); +#endif //_AMDLIB32_H_ Added: trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,158 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +// +// +// Routine Description: +// +// Locate ACPI table +// +// Arguments: +// +// Signature - table signature +// +//Returns: +// +// pointer to ACPI table +// +// +VOID* +ACPI_LocateTable ( + IN UINT32 Signature + ) +{ + UINT32 i; + UINT32* RsdPtr; + UINT32* Rsdt; + UINTN tableOffset; + DESCRIPTION_HEADER* CurrentTable; + + RsdPtr = (UINT32*) (UINTN)0xe0000; + Rsdt = NULL; + do { + //if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) { //gcc multi-character character constant warning + if ( *RsdPtr == 0x20445352 && *(RsdPtr + 1) == 0x20525450) { + + Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress; + break; + } + RsdPtr += 4; + } while ( RsdPtr <= (UINT32*) (UINTN)0xffff0 ); + if ( Rsdt != NULL && ACPI_GetTableChecksum (Rsdt) == 0 ) { + for ( i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++ ) { + tableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i * 4); + CurrentTable = (DESCRIPTION_HEADER*)tableOffset; + if ( CurrentTable->Signature == Signature ) { + return CurrentTable; + } + } + } + return NULL; +} + +// +// +// Routine Description: +// +// Update table checksum +// +// Arguments: +// +// TablePtr - table pointer +// +// Returns: +// +// none +// +// +VOID +ACPI_SetTableChecksum ( + IN VOID* TablePtr + ) +{ + UINT8 Checksum; + Checksum = 0; + ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0; + Checksum = ACPI_GetTableChecksum (TablePtr); + ((DESCRIPTION_HEADER*)TablePtr)->Checksum = (UINT8)(0x100 - Checksum); +} + +// +// +// Routine Description: +// +// Get table checksum +// +// Arguments: +// +// TablePtr - table pointer +// +// Returns: +// +// none +// +// +UINT8 +ACPI_GetTableChecksum ( + IN VOID* TablePtr + ) +{ + return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length); +} + + +UINT8 +GetByteSum ( + IN VOID* pData, + IN UINT32 Length + ) +{ + UINT32 i; + UINT8 Checksum; + Checksum = 0; + for ( i = 0; i < Length; i++ ) { + Checksum = Checksum + (*((UINT8*)pData + i)); + } + return Checksum; +} +VOID +GetSbAcpiMmioBase ( + OUT UINT32* AcpiMmioBase + ) +{ + UINT32 Value16; + + ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint16, &Value16); + *AcpiMmioBase = Value16 << 16; +} + +VOID +GetSbAcpiPmBase ( + OUT UINT16* AcpiPmBase + ) +{ + ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase); +} + Added: trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,60 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +/** + * RSDP - ACPI 2.0 table RSDP + */ +typedef struct _RSDP +{ + UINT64 Signature; /* RSDP signature "RSD PTR" */ + UINT8 Checksum; /* checksum of the first 20 bytes */ + UINT8 OEMID[6]; /* OEM ID, "LXBIOS" */ + UINT8 Revision; /* 0 for APCI 1.0, 2 for ACPI 2.0 */ + UINT32 RsdtAddress; /* physical address of RSDT */ + UINT32 Length; /* total length of RSDP (including extended part) */ + UINT64 XsdtAddress; /* physical address of XSDT */ + UINT8 ExtendedChecksum; /* chechsum of whole table */ + UINT8 Reserved[3]; +} RSDP; + + +/** + * DESCRIPTION_HEADER - ACPI common table header + */ +typedef struct _DESCRIPTION_HEADER +{ + UINT32 Signature; /* ACPI signature (4 ASCII characters) */ + UINT32 Length; /* Length of table, in bytes, including header */ + UINT8 Revision; /* ACPI Specification minor version # */ + UINT8 Checksum; /* To make sum of entire table == 0 */ + UINT8 OEMID[6]; /* OEM identification */ + UINT8 OEMTableID[8]; /* OEM table identification */ + UINT32 OEMRevision; /* OEM revision number */ + UINT32 CreatorID; /* ASL compiler vendor ID */ + UINT32 CreatorRevision; /* ASL compiler revision number */ +} DESCRIPTION_HEADER; + +VOID* ACPI_LocateTable (IN UINT32 Signature); +VOID ACPI_SetTableChecksum (IN VOID* TablePtr); +UINT8 ACPI_GetTableChecksum (IN VOID* TablePtr); +UINT8 GetByteSum (IN VOID* pData, IN UINT32 Length); Added: trunk/src/vendorcode/amd/cimx/sb800/AMDLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/AMDLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,82 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +UINT8 +getNumberOfCpuCores ( + OUT VOID + ) +{ + UINT8 Result; + Result = 1; + Result = ReadNumberOfCpuCores (); + return Result; +} + +UINT32 +readAlink ( + IN UINT32 Index + ) +{ + UINT32 Data; + WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + ReadIO (ALINK_ACCESS_DATA, AccWidthUint32, &Data); + //Clear Index + Index = 0; + WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + return Data; +} + +VOID +writeAlink ( + IN UINT32 Index, + IN UINT32 Data + ) +{ + WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index); + WriteIO (ALINK_ACCESS_DATA, AccWidthUint32 | S3_SAVE, &Data); + //Clear Index + Index = 0; + WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index); +} + +VOID +rwAlink ( + IN UINT32 Index, + IN UINT32 AndMask, + IN UINT32 OrMask + ) +{ + UINT32 AccesType; + AccesType = Index & 0xE0000000; + if (AccesType == (AXINDC << 29)) { + writeAlink ((SB_AX_INDXC_REG30 | AccesType), Index & 0x1FFFFFFF); + Index = (SB_AX_DATAC_REG34 | AccesType); + } else if (AccesType == (AXINDP << 29)) { + writeAlink ((SB_AX_INDXP_REG38 | AccesType), Index & 0x1FFFFFFF); + Index = (SB_AX_DATAP_REG3C | AccesType); + } + writeAlink (Index, (readAlink (Index) & AndMask) | OrMask ); +} + Added: trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,142 @@ +/** + * @file + * + * Southbridge IO access common routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +/*----------------------------------------------------------------------------------------*/ +/** + * SbStall - Delay routine + * + * + * + * @param[in] uSec + * + */ +VOID +SbStall ( + IN UINT32 uSec + ) +{ + UINT16 timerAddr; + UINT32 startTime; + UINT32 elapsedTime; + + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr); + if ( timerAddr == 0 ) { + uSec = uSec / 2; + while ( uSec != 0 ) { + ReadIO (0x80, AccWidthUint8, (UINT8 *) (&startTime)); + uSec--; + } + } else { + ReadIO (timerAddr, AccWidthUint32, &startTime); + for ( ;; ) { + ReadIO (timerAddr, AccWidthUint32, &elapsedTime); + if ( elapsedTime < startTime ) { + elapsedTime = elapsedTime + 0xFFFFFFFF - startTime; + } else { + elapsedTime = elapsedTime - startTime; + } + if ( (elapsedTime * 28 / 100) > uSec ) { + break; + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SbReset - Generate a reset command + * + * + * + * @param[in] OpFlag - Dummy + * + */ +VOID +SbReset ( + IN UINT8 OpFlag + ) +{ + UINT8 Temp; + Temp = OpFlag; + RWIO (0xcf9, AccWidthUint8, 0x0, 0x06); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * outPort80 - Send data to PORT 80 (debug port) + * + * + * + * @param[in] pcode - debug code (32 bits) + * + */ +VOID +outPort80 ( + IN UINT32 pcode + ) +{ + WriteIO (0x80, AccWidthUint8, &pcode); + return; +} + +/** + * AmdSbCopyMem - Memory copy + * + * @param[in] pDest - Destance address point + * @param[in] pSource - Source Address point + * @param[in] Length - Data length + * + */ +VOID +AmdSbCopyMem ( + IN VOID* pDest, + IN VOID* pSource, + IN UINTN Length + ) +{ + UINTN i; + UINT8 *Ptr; + UINT8 *Source; + Ptr = (UINT8*)pDest; + Source = (UINT8*)pSource; + for (i = 0; i < Length; i++) { + *Ptr = *Source; + Source++; + Ptr++; + } +} Added: trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,97 @@ +/** + * @file + * + * Southbridge IO access common routine define file + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +//AMDSBLIB Routines + +/** + * SbStall - Delay routine + * + * + * + * @param[in] uSec + * + */ +VOID SbStall (IN UINT32 uSec); + +/** + * SbReset - Generate a reset command + * + * + * + * @param[in] OpFlag - Dummy + * + */ +VOID SbReset (IN UINT8 OpFlag); + +/** + * outPort80 - Send data to PORT 80 (debug port) + * + * + * + * @param[in] pcode - debug code (32 bits) + * + */ +VOID outPort80 (IN UINT32 pcode); + +/** + * getEfuseStatue - Get Efuse status + * + * + * @param[in] Value - Return Chip strap status + * + */ +VOID getEfuseStatus (IN VOID* Value); + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS AmdSbDispatcher (IN VOID *pConfig); + +/** + * AmdSbCopyMem - Memory copy + * + * @param[in] pDest - Destance address point + * @param[in] pSource - Source Address point + * @param[in] Length - Data length + * + */ +VOID AmdSbCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length); Added: trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,502 @@ +/** + * @file + * + * Config Southbridge HD Audio Controller + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ + +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +#include "SBPLATFORM.h" + +// +// Declaration of local functions +// + +VOID configureAzaliaPinCmd (IN AMDSBCFG* pConfig, IN UINT32 ddBAR0, IN UINT8 dbChannelNum); +VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN UINT32 ddChannelNum, IN UINT32 ddBAR0); + +/** + * Pin Config for ALC880, ALC882 and ALC883. + * + * + * + */ +CODECENTRY AzaliaCodecAlc882Table[] = +{ + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01012014}, + {0x18, 0x01A19030}, + {0x19, 0x411111F0}, + {0x1a, 0x01813080}, + {0x1b, 0x411111F0}, + {0x1C, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x01441150}, + {0x1f, 0x01C46160}, + {0xff, 0xffffffff} +}; + +/** + * Pin Config for ALC0262. + * + * + * + */ +CODECENTRY AzaliaCodecAlc262Table[] = +{ + {0x14, 0x01014010}, + {0x15, 0x411111F0}, + {0x16, 0x411111F0}, + {0x18, 0x01A19830}, + {0x19, 0x02A19C40}, + {0x1a, 0x01813031}, + {0x1b, 0x02014C20}, + {0x1c, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x0144111E}, + {0x1f, 0x01C46150}, + {0xff, 0xffffffff} +}; + +/** + * Pin Config for ALC0269. + * + * + * + */ +CODECENTRY AzaliaCodecAlc269Table[] = +{ + {0x12, 0x99A30960}, + {0x14, 0x99130110}, + {0x15, 0x0221401F}, + {0x16, 0x99130120}, + {0x18, 0x01A19850}, + {0x19, 0x02A15951}, + {0x1a, 0x01813052}, + {0x1b, 0x0181405F}, + {0x1d, 0x40134601}, + {0x1e, 0x01441130}, + {0x11, 0x18567140}, + {0x20, 0x0030FFFF}, + {0xff, 0xffffffff} +}; + +/** + * Pin Config for ALC0861. + * + * + * + */ +CODECENTRY AzaliaCodecAlc861Table[] = +{ + {0x01, 0x8086C601}, + {0x0B, 0x01014110}, + {0x0C, 0x01813140}, + {0x0D, 0x01A19941}, + {0x0E, 0x411111F0}, + {0x0F, 0x02214420}, + {0x10, 0x02A1994E}, + {0x11, 0x99330142}, + {0x12, 0x01451130}, + {0x1F, 0x411111F0}, + {0x20, 0x411111F0}, + {0x23, 0x411111F0}, + {0xff, 0xffffffff} +}; + +/** + * Pin Config for ALC0889. + * + * + * + */ +CODECENTRY AzaliaCodecAlc889Table[] = +{ + {0x11, 0x411111F0}, + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01013014}, + {0x18, 0x01A19030}, + {0x19, 0x411111F0}, + {0x1a, 0x411111F0}, + {0x1b, 0x411111F0}, + {0x1C, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x01442150}, + {0x1f, 0x01C42160}, + {0xff, 0xffffffff} +}; + +/** + * Pin Config for ADI1984. + * + * + * + */ +CODECENTRY AzaliaCodecAd1984Table[] = +{ + {0x11, 0x0221401F}, + {0x12, 0x90170110}, + {0x13, 0x511301F0}, + {0x14, 0x02A15020}, + {0x15, 0x50A301F0}, + {0x16, 0x593301F0}, + {0x17, 0x55A601F0}, + {0x18, 0x55A601F0}, + {0x1A, 0x91F311F0}, + {0x1B, 0x014511A0}, + {0x1C, 0x599301F0}, + {0xff, 0xffffffff} +}; + +/** + * FrontPanel Config table list + * + * + * + */ +CODECENTRY FrontPanelAzaliaCodecTableList[] = +{ + {0x19, 0x02A19040}, + {0x1b, 0x02214020}, + {0xff, 0xffffffff} +}; + +/** + * Current HD Audio support codec list + * + * + * + */ +CODECTBLLIST azaliaCodecTableList[] = +{ + {0x010ec0880, &AzaliaCodecAlc882Table[0]}, + {0x010ec0882, &AzaliaCodecAlc882Table[0]}, + {0x010ec0883, &AzaliaCodecAlc882Table[0]}, + {0x010ec0885, &AzaliaCodecAlc882Table[0]}, + {0x010ec0889, &AzaliaCodecAlc889Table[0]}, + {0x010ec0262, &AzaliaCodecAlc262Table[0]}, + {0x010ec0269, &AzaliaCodecAlc269Table[0]}, + {0x010ec0861, &AzaliaCodecAlc861Table[0]}, + {0x011d41984, &AzaliaCodecAd1984Table[0]}, + { (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF} +}; + +/** + * azaliaInitBeforePciEnum - Config HD Audio Before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +azaliaInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + if ( pConfig->AzaliaController == 1 ) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, BIT0); + if ( pConfig->BuildParameters.HdAudioMsi) { + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG44, AccWidthUint32 | S3_SAVE, ~BIT8, BIT8); + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG60, AccWidthUint32 | S3_SAVE, ~BIT16, BIT16); + } + } +} + +/** + * azaliaInitAfterPciEnum - Config HD Audio after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +azaliaInitAfterPciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 Data; + UINT8 i; + UINT8 dbEnableAzalia; + UINT8 dbPinRouting; + UINT8 dbChannelNum; + UINT8 dbTempVariable; + UINT16 dwTempVariable; + UINT32 ddBAR0; + UINT32 ddTempVariable; + dbEnableAzalia = 0; + dbChannelNum = 0; + dbTempVariable = 0; + dwTempVariable = 0; + ddBAR0 = 0; + ddTempVariable = 0; + + if ( pConfig->AzaliaController == 1 ) { + return; + } + + if ( pConfig->AzaliaController != 1 ) { + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1); + if ( pConfig->BuildParameters.AzaliaSsid != NULL ) { + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid); + } + ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); + if ( ddBAR0 != 0 ) { + if ( ddBAR0 != 0xFFFFFFFF ) { + ddBAR0 &= ~(0x03FFF); + dbEnableAzalia = 1; + } + } + } + + if ( dbEnableAzalia ) { + // Get SDIN Configuration + if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00); + } else { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01); + } + if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00); + } else { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01); + } + if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00); + } else { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01); + } + if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00); + } else { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01); + } + // INT#A Azalia resource + Data = 0x93; // Azalia APIC index + WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data); + Data = 0x10; // IRQ16 (INTA#) + WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data); + + i = 11; + do { + ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + dbTempVariable |= BIT0; + WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + SbStall (1000); + ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + i--; + } while ((! (dbTempVariable & BIT0)) && (i > 0) ); + + if ( i == 0 ) { + return; + } + + SbStall (1000); + ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable); + if ( dwTempVariable & 0x0F ) { + + //atleast one azalia codec found + // ?? E0 is not real register what we expect. we have change to GPIO/and program GPIO Mux + //ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint8, &dbPinRouting); + dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin; + do { + if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) { +// dbChannelNum = 3; + configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum); + } + dbPinRouting >>= 2; + dbChannelNum++; + } while ( dbChannelNum != 4 ); + } else { + //No Azalia codec found + if ( pConfig->AzaliaController != 2 ) { + dbEnableAzalia = 0; //set flag to disable Azalia + } + } + } + + if ( dbEnableAzalia ) { + //redo clear reset + do { + dwTempVariable = 0; + WriteMEM ( ddBAR0 + SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable); + ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + dbTempVariable &= ~(BIT0); + WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + } while ( dbTempVariable & BIT0 ); + + if ( pConfig->AzaliaSnoop == 1 ) { + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1 + BIT0); + } + } else { + //disable Azalia controller + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0); + // RWPMIO (SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~BIT3, 0); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0); + // RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0); + } +} + +/** + * configureAzaliaPinCmd - Configuration HD Audio PIN Command + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] ddBAR0 HD Audio BAR0 base address. + * @param[in] dbChannelNum Channel Number. + * + */ +VOID +configureAzaliaPinCmd ( + IN AMDSBCFG* pConfig, + IN UINT32 ddBAR0, + IN UINT8 dbChannelNum + ) +{ + UINT32 ddTempVariable; + UINT32 ddChannelNum; + CODECTBLLIST* ptempAzaliaOemCodecTablePtr; + CODECENTRY* tempAzaliaCodecEntryPtr; + + if ( (pConfig->AzaliaPinCfg) != 1 ) { + return; + } + + ddChannelNum = dbChannelNum << 28; + ddTempVariable = 0xF0000; + ddTempVariable |= ddChannelNum; + + WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable); + SbStall (600); + ReadMEM (ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable); + + if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF))) { + ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR (&azaliaCodecTableList[0]); + } else { + ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr; + } + + while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) { + if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) { + break; + } else { + ++ptempAzaliaOemCodecTablePtr; + } + } + + if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) { + tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr; + + if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) { + tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr); + } + configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); + if ( pConfig->AzaliaFrontPanel != 1 ) { + if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ) { + if ( ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == NULL) || ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) { + tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (&FrontPanelAzaliaCodecTableList[0]); + } else { + tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr; + } + configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); + } + } + } +} + +/** + * configureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table + * + * + * @param[in] tempAzaliaCodecEntryPtr HD Audio Codec table structure pointer. + * @param[in] ddChannelNum HD Audio Channel Number. + * @param[in] ddBAR0 HD Audio BAR0 base address. + * + */ +VOID +configureAzaliaSetConfigD4Dword ( + IN CODECENTRY* tempAzaliaCodecEntryPtr, + IN UINT32 ddChannelNum, + IN UINT32 ddBAR0 + ) +{ + UINT8 dbtemp1; + UINT8 dbtemp2; + UINT8 i; + UINT32 ddtemp; + UINT32 ddtemp2; + ddtemp = 0; + ddtemp2 = 0; + while ( (tempAzaliaCodecEntryPtr->Nid) != 0xFF ) { + dbtemp1 = 0x20; + if ( (tempAzaliaCodecEntryPtr->Nid) == 0x1 ) { + dbtemp1 = 0x24; + } + + ddtemp = tempAzaliaCodecEntryPtr->Nid; + ddtemp &= 0xff; + ddtemp <<= 20; + ddtemp |= ddChannelNum; + + ddtemp |= (0x700 << 8); + for ( i = 4; i > 0; i-- ) { + do { + ReadMEM (ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2); + } while ( ddtemp2 & BIT0 ); + + dbtemp2 = (UINT8) (( (tempAzaliaCodecEntryPtr->Byte40) >> ((4 - i) * 8 ) ) & 0xff); + ddtemp = (ddtemp & 0xFFFF0000) + ((dbtemp1 - i) << 8) + dbtemp2; + WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp); + SbStall (60); + } + ++tempAzaliaCodecEntryPtr; + } +} + Added: trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,247 @@ +/** + * @file + * + * Function dispatcher. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ + +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "SBPLATFORM.h" + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- +*/ + + +// +// Declaration of local functions +// + +VOID saveConfigPointer (IN AMDSBCFG* pConfig); +VOID* VerifyImage (IN UINT64 Signature, IN VOID* ImagePtr); +VOID* LocateImage (IN UINT64 Signature); + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS +AmdSbDispatcher ( + IN VOID *pConfig + ) +{ + AGESA_STATUS Status; + +#ifdef B1_IMAGE + VOID *pAltImagePtr; + CIM_IMAGE_ENTRY AltImageEntry; +#endif + + UINT64 tdValue; + tdValue = 0x32314130384253ULL; + +#ifdef B1_IMAGE + pAltImagePtr = NULL; +#endif + Status = AGESA_UNSUPPORTED; + +#ifdef B1_IMAGE + if ((UINT32) (UINTN) (((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr) != 0xffffffff ) { + if ( ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr ) { + pAltImagePtr = VerifyImage ( tdValue, (VOID*) (UINTN) ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr); + } + if ( pAltImagePtr == NULL ) { + pAltImagePtr = LocateImage ( tdValue ); + } + if ( pAltImagePtr != NULL ) { + ((AMD_CONFIG_PARAMS*)pConfig)->ImageBasePtr = (UINT32) (UINTN) pAltImagePtr; + AltImageEntry = (CIM_IMAGE_ENTRY) (UINTN) ((UINT32) (UINTN) pAltImagePtr + (UINT32) (((AMD_IMAGE_HEADER*) (UINTN) pAltImagePtr)->EntryPointAddress)); + (*AltImageEntry) (pConfig); + return Status; + } + } +#endif + saveConfigPointer (pConfig); + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) { + sbPowerOnInit ((AMDSBCFG*) pConfig); + } + +#ifndef B1_IMAGE + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) { + sbBeforePciInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) { + sbAfterPciInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_MID_POST_INIT ) { + sbMidPostInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) { + sbLatePost ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) { + sbBeforePciRestoreInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) { + sbAfterPciRestoreInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) { + sbSmmService ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) { + sbSmmAcpiOn ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) { + sbECfancontrolservice((AMDSBCFG*)pConfig);; + } +#endif + return Status; +} + +/** + * LocateImage - Locate Southbridge CIMx module + * + * + * + * @param[in] Signature Southbridge CIMx image signature. + * + */ +VOID* +LocateImage ( + IN UINT64 Signature + ) +{ + VOID *Result; + UINT32 ImagePtr; + ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1); + + while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) { +#ifdef x64 + 12346789 +#else + Result = VerifyImage (Signature, (VOID*) ImagePtr); +#endif + if ( Result != NULL ) { + return Result; + } + ImagePtr -= IMAGE_ALIGN; + } + return NULL; +} + +/** + * VerifyImage - Verify Southbridge CIMx module + * + * + * @param[in] Signature Southbridge CIMx image signature. + * @param[in] ImagePtr Southbridge CIMx image address. + * + */ +VOID* +VerifyImage ( + IN UINT64 Signature, + IN VOID* ImagePtr + ) +{ + UINT16 *TempImagePtr; + UINT16 Sum; + UINT32 i; + Sum = 0; + //if ( (*((UINT32*)ImagePtr) == 'DMA$' && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) { //gcc multi-character character constant warning + if ( (*((UINT32*)ImagePtr) == 0x444d4124 && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {//'DMA$' + //GetImage Image size + TempImagePtr = (UINT16*)ImagePtr; + for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) { + Sum = Sum + *TempImagePtr; + TempImagePtr++; + } + if ( Sum == 0 ) { + return ImagePtr; + } + } + return NULL; +} + +/** + * saveConfigPointer - Verify Southbridge CIMx module + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +saveConfigPointer ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 dbReg; + UINT8 i; + UINT32 ddValue; + + ddValue = (UINT32) (UINTN)pConfig; + dbReg = SB_ECMOS_REG08; + + for ( i = 0; i <= 3; i++ ) { + WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg); + WriteIO (SB_IOMAP_REG73, AccWidthUint8, (UINT8*)&ddValue); + ddValue = (ddValue >> 8); + dbReg++; + } +} Added: trunk/src/vendorcode/amd/cimx/sb800/EC.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/EC.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,121 @@ + +/** + * @file + * + * Config Southbridge EC Controller + * + * Init EC features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +#ifndef NO_EC_SUPPORT + +/** + * Config EC controller during power-on + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +ecPowerOnInit ( + IN AMDSBCFG* pConfig + ) +{ + //Enable config mode + EnterEcConfig (); + + //Do settings for mailbox - logical device 0x09 + RWEC8 (0x07, 0x00, 0x09); //switch to device 9 (Mailbox) + RWEC8 (0x60, 0x00, (MailBoxPort >> 8)); //set MSB of Mailbox port + RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port + RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1 + + if ( pConfig->BuildParameters.EcKbd == ENABLED) { + //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3); + + //Disable LPC Decoding of port 60/64 + RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0); + + //Enable logical device 0x07 (Keyboard controller) + RWEC8 (0x07, 0x00, 0x07); + RWEC8 (0x30, 0x00, 0x01); + } + + if ( pConfig->BuildParameters.EcChannel0 == ENABLED) { + //Logical device 0x03 + RWEC8 (0x07, 0x00, 0x03); + RWEC8 (0x60, 0x00, 0x00); + RWEC8 (0x61, 0x00, 0x62); + RWEC8 (0x30, 0x00, 0x01); //;Enable Device 8 + } + + //Enable EC (IMC) to generate SMI to BIOS + RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6); + ExitEcConfig (); +} + +/** + * Config EC controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +ecInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + AMDSBCFG* pTmp; // dummy code + pTmp = pConfig; +} + +/** + * Prepare EC controller to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +ecInitLatePost ( + IN AMDSBCFG* pConfig + ) +{ + AMDSBCFG* pTmp; // dummy code + pTmp = pConfig; +} +#endif Added: trunk/src/vendorcode/amd/cimx/sb800/ECLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ECLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,146 @@ +/** + * @file + * + * Southbridge EC IO access common routine + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +// #ifndef NO_EC_SUPPORT + +/*----------------------------------------------------------------------------------------*/ +/** + * EnterEcConfig - Force EC into Config mode + * + * + * + * + */ +VOID +EnterEcConfig ( + ) +{ + UINT16 dwEcIndexPort; + + ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(BIT0); + RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ExitEcConfig - Force EC exit Config mode + * + * + * + * + */ +VOID +ExitEcConfig ( + ) +{ + UINT16 dwEcIndexPort; + + ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(BIT0); + RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ReadEC8 - Read EC register data + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Read Data Buffer + * + */ +VOID +ReadEC8 ( + IN UINT8 Address, + IN UINT8* Value + ) +{ + UINT16 dwEcIndexPort; + + ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(BIT0); + WriteIO (dwEcIndexPort, AccWidthUint8, &Address); + ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * WriteEC8 - Write date into EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Write Data Buffer + * + */ +VOID +WriteEC8 ( + IN UINT8 Address, + IN UINT8* Value + ) +{ + UINT16 dwEcIndexPort; + + ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(BIT0); + + WriteIO (dwEcIndexPort, AccWidthUint8, &Address); + WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RWEC8 - Read/Write EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] AndMask - Data And Mask 8 bits + * @param[in] OrMask - Data OR Mask 8 bits + * + */ +VOID +RWEC8 ( + IN UINT8 Address, + IN UINT8 AndMask, + IN UINT8 OrMask + ) +{ + UINT8 Result; + ReadEC8 (Address, &Result); + Result = (Result & AndMask) | OrMask; + WriteEC8 (Address, &Result); +} + +// #endif + Added: trunk/src/vendorcode/amd/cimx/sb800/ECfan.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ECfan.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,60 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); +VOID WaitForEcLDN9MailboxCmdAck (VOID); +VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value); + +// IMC Message Register Software Interface +#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3) + +#define MSG_SYS_TO_IMC 0x80 +#define Fun_80 0x80 +#define Fun_81 0x81 +#define Fun_82 0x82 +#define Fun_83 0x83 +#define Fun_84 0x84 +#define Fun_85 0x85 +#define Fun_86 0x86 +#define Fun_87 0x87 +#define Fun_88 0x88 +#define Fun_89 0x89 +#define Fun_90 0x90 +#define MSG_IMC_TO_SYS 0x81 +#define MSG_REG0 0x82 +#define MSG_REG1 0x83 +#define MSG_REG2 0x84 +#define MSG_REG3 0x85 +#define MSG_REG4 0x86 +#define MSG_REG5 0x87 +#define MSG_REG6 0x88 +#define MSG_REG7 0x89 +#define MSG_REG8 0x8A +#define MSG_REG9 0x8B +#define MSG_REGA 0x8C +#define MSG_REGB 0x8D +#define MSG_REGC 0x8E +#define MSG_REGD 0x8F + + Added: trunk/src/vendorcode/amd/cimx/sb800/ECfanLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ECfanLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,87 @@ +/** + * @file + * + * Southbridge EC IO access common routine + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" +#include "ECfan.h" + +VOID +ReadECmsg ( + IN UINT8 Address, + IN UINT8 OpFlag, + OUT VOID* Value + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i = 0; i <= OpFlag; i++) { + WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS + Address++; + ReadIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS + } +} + + +VOID +WriteECmsg ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i = 0; i <= OpFlag; i++) { + WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS + Address++; + WriteIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS + } +} + +VOID +WaitForEcLDN9MailboxCmdAck ( + VOID + ) +{ + UINT8 Msgdata; + UINT16 Delaytime; + Msgdata = 0; + for (Delaytime = 0; Delaytime <= 500; Delaytime++) { + ReadECmsg (MSG_REG0, AccWidthUint8, &Msgdata); + if ( Msgdata == 0xfa) { + break; + } + SbStall (1000); // Wait for 1ms + } +} + + Added: trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,195 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +#include "SBPLATFORM.h" +#include "ECfan.h" +/** + * Table for Function Number + * + * + * + * + */ +UINT8 FunctionNumber[] = +{ + Fun_81, + Fun_83, + Fun_85, + Fun_89, +}; + +/** + * Table for Max Thermal Zone + * + * + * + * + */ +UINT8 MaxZone[] = +{ + 4, + 4, + 4, + 4, +}; + +/** + * Table for Max Register + * + * + * + * + */ +UINT8 MaxRegister[] = +{ + MSG_REG9, + MSG_REGB, + MSG_REG9, + MSG_REGA, +}; + +/*------------------------------------------------------------------------------- +;Procedure: IsZoneFuncEnable +; +;Description: This routine will check every zone support function with BitMap from user define +; +; +;Exit: None +; +;Modified: None +; +;----------------------------------------------------------------------------- +*/ +BOOLEAN +IsZoneFuncEnable ( + UINT16 Flag, + UINT8 func, + UINT8 Zone +) +{ + return (BOOLEAN)(((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone)); +} + +/*------------------------------------------------------------------------------- +;Procedure: sbECfancontrolservice +; +;Description: This routine service EC fan policy +; +; +;Exit: None +; +;Modified: None +; +;----------------------------------------------------------------------------- +*/ +VOID +sbECfancontrolservice ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 ZoneNum; + UINT8 FunNum; + UINT8 RegNum; + UINT8 * CurPoint; + UINT8 FunIndex; + BOOLEAN IsSendEcMsg; + + CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1); + for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) { + FunNum = FunctionNumber[FunIndex]; + for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { + IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); + for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { + if (IsSendEcMsg) { + WriteECmsg (RegNum, AccWidthUint8, CurPoint); // + } + CurPoint += 1; + } + if (IsSendEcMsg) { + WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number + WaitForEcLDN9MailboxCmdAck (); + } + } + } + CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0; + for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) { + FunNum = FunctionNumber[FunIndex]; + for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { + IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); + for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { + if (IsSendEcMsg) { + WriteECmsg (RegNum, AccWidthUint8, CurPoint); // + } + CurPoint += 1; + } + if (IsSendEcMsg) { + WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number + WaitForEcLDN9MailboxCmdAck (); + } + } + } +} + +/*------------------------------------------------------------------------------- +;Procedure: SBIMCFanInitializeS3 +; +;Description: This routine initialize IMC fan when S3 resume +; +; +;Exit: None +; +;Modified: None +; +;----------------------------------------------------------------------------- +*/ +VOID +SBIMCFanInitializeS3 (VOID) +{ + UINT8 dbPortStatus,Value80,Value82,Value83,Value84; + + getChipSysMode (&dbPortStatus); + if ((dbPortStatus & ChipSysEcEnable) != 0) { + Value80 = 0x98; + Value82 = 0x00; + Value83 = 0x02; + Value84 = 0x00; + + // Clear MSG_REG0 to receive acknowledge byte + WriteECmsg (MSG_REG0, AccWidthUint8, &Value82); + + // Set MSG_REG1 + // 0x02 - Notify IMC that the system is waken from any sleep state + WriteECmsg (MSG_REG1, AccWidthUint8, &Value83); + + // Set timeout counter value to 00 which disables watchdog timer + WriteECmsg (MSG_REG2, AccWidthUint8, &Value84); + + // Write mailbox function number to kick off the command + // 0x98 - IMC System Sleep and Wake Services + WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Value80); + + // Read acknowledge byte to make sure function is executed properly + WaitForEcLDN9MailboxCmdAck (); + } +} Added: trunk/src/vendorcode/amd/cimx/sb800/GEC.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/GEC.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,135 @@ +/** + * @file + * + * Config Southbridge GEC controller + * + * Init GEC features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +/** + * gecInitBeforePciEnum - Config GEC controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +gecInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 cimSBGecDebugBus; + UINT8 cimSBGecPwr; + + cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus; + cimSBGecPwr = (UINT8) pConfig->SBGecPwr; +#if SB_CIMx_PARAMETER == 0 + cimSBGecDebugBus = cimSBGecDebugBusDefault; + cimSBGecPwr = cimSBGecPwrDefault; +#endif + if ( pConfig->GecConfig == 0) { + // GEC Enabled + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01); + //RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5)); + } else { + // GEC Disabled + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0); + return; //return if GEC controller is disabled. + } + if ( cimSBGecDebugBus == 1) { + // GEC Debug Bus Enabled + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3); + } else { + // GEC Debug Bus Disabled + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00); + } +} + +/** + * gecInitAfterPciEnum - Config GEC controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +gecInitAfterPciEnum ( + IN AMDSBCFG* pConfig + ) +{ + VOID* GecRomAddress; + VOID* GecShadowRomAddress; + UINT32 ddTemp; + UINT8 dbVar; + UINT8 dbTemp; + if ( pConfig->GecConfig == 0) { + dbVar = 0; + ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); + dbTemp = 0x07; + WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp); + if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) { + GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr; + GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase; + AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); + ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp); + ddTemp = ddTemp & 0xFFFFFFF0; + RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29); + } + WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); + } +} + +/** + * gecInitLatePost - Prepare GEC controller to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +gecInitLatePost ( + IN AMDSBCFG* pConfig + ) +{ + if ( !pConfig->GecConfig == 0) { + return; //return if GEC controller is disabled. + } +} + + Added: trunk/src/vendorcode/amd/cimx/sb800/Gpp.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/Gpp.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,887 @@ + +/** + * @file + * + * Config Southbridge GPP controller + * + * Init GPP features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +/** + * PCIE_CAP_ID - PCIe Cap ID + * + */ +#define PCIE_CAP_ID 0x10 + +// +// Declaration of local functions +// + +/** + * PreInitGppLink - Enable GPP link training. + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID PreInitGppLink (IN AMDSBCFG* pConfig); + UINT8 CheckGppLinkStatus (IN AMDSBCFG* pConfig); + VOID AfterGppLinkInit (IN AMDSBCFG* pConfig); + VOID sbGppForceGen2 (IN UINT32 portId ); + VOID sbGppForceGen1 (IN UINT32 portId ); + VOID sbGppDisableUnusedPadMap (IN AMDSBCFG* pConfig ); + VOID sbGppSetAspm (IN UINT32 pciAddress, IN UINT8 LxState); + UINT8 sbFindPciCap (IN UINT32 pciAddress, IN UINT8 targetCapId); + +// +// Declaration of external functions +// + +// +//----------------------------------------------------------------------------------- +// Early SB800 GPP initialization sequence: +// +// 1) Set port enable bit fields by current GPP link configuration mode +// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) +// 3) Loop polling for the link status of all ports +// 4) Misc operations after link training: +// - (optional) Detect GFX device +// - Hide empty GPP configuration spaces (Disable empty GPP ports) +// - (optional) Power down unused GPP ports +// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0]) +// 5) GPP init completed +// +// +// *) Gen2 vs Gen1 +// Gen2 mode Gen1 mode +// --------------------------------------------------------------- +// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19 +// STRAP_BIF_GEN2_EN 1 0 +// +// PCIE_PHY_PLL clock locks @ 5GHz +// +// + +/** + * GPP early programming and link training. On exit all populated EPs should be fully operational. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbPcieGppEarlyInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 TogglePort; + UINT8 portNum; + UINT32 reg32Value; + UINT8 retryCount; + UINT8 cimGppMemWrImprove; + UINT8 cimGppLaneReversal; + UINT8 cimAlinkPhyPllPowerDown; + + cimGppMemWrImprove = pConfig->GppMemWrImprove; + cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal; + cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown; +#if SB_CIMx_PARAMETER == 0 + cimGppMemWrImprove = cimGppMemWrImproveDefault; + cimGppLaneReversal = cimGppLaneReversalDefault; + cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault; +#endif + +// +// Configure NB-SB link PCIE PHY PLL power down for L1 +// + if ( cimAlinkPhyPllPowerDown == TRUE ) { + UINT32 abValue; + // Set PCIE_P_CNTL in Alink PCIEIND space + writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40); + abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29)); + abValue |= BIT12 + BIT3 + BIT0; + abValue &= ~(BIT9 + BIT4); + writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue); + rwAlink (SB_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~BIT8, (BIT8)); + } + +// +// Set ABCFG 0x031C[0] = 1 enable the lane reversal support. +// + reg32Value = readAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29)); + if ( cimGppLaneReversal ) { + writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | BIT0); + } else { + writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | 0x00); + } +// +// Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function +// + reg32Value = readAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)); + writeAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), reg32Value | BIT20); + + +// +// Initialize and configure GPP +// + if (pConfig->GppFunctionEnable) { + // PreInit - Enable GPP link training + PreInitGppLink (pConfig); + +// +// GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1 +// GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4 +// + if ( cimGppMemWrImprove == TRUE ) { + rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~BIT26, (BIT26)); + rwAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12)); + } + + if ( pConfig->S3Resume ) { + for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) { + reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29)); + writeAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29), reg32Value & ~BIT21); + } + } + // + // a) Loop polling regA5 -> LcState (timeout ~100ms); + // b) if (LcState[5:0] == 0x10), training successful, go to g); + // c) if any of (LcState[13:8], [21:16], [29:24]) == 0x29 or 0x2A: + // d) Clear De-emphasis bit for relevant ports; + // e) Toggle GPP reset signal (via OEM callback); + // f) go back to a); + // g) exit; + // + for (retryCount = 0; retryCount < MAX_GPP_RESETS; retryCount++) { + // Polling each GPP port for link status + TogglePort = CheckGppLinkStatus (pConfig); + + if (TogglePort == 0) { + break; + } else { + // Check failure port and clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0) + for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) { + if (TogglePort & (1 << portNum)) { + reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29)); + writeAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29), reg32Value & ~BIT21); + } + sbGppForceGen1 (portNum); + } + + // Toggle GPP reset (Note this affects all SB800 GPP ports) + CallBackToOEM (CB_SBGPP_RESET_ASSERT, (UINT32)TogglePort, pConfig); + SbStall (500); + CallBackToOEM (CB_SBGPP_RESET_DEASSERT, (UINT32)TogglePort, pConfig); + } + }; + + // Misc operations after link training + AfterGppLinkInit (pConfig); + } else { + +// RPR 5.11 Power Saving With GPP Disable +// ABCFG 0xC0[8] = 0x0 +// ABCFG 0xC0[15:12] = 0xF +// Enable "Power Saving Feature for A-Link Express Lanes" +// Enable "Power Saving Feature for GPP Lanes" +// ABCFG 0x90[19] = 1 +// ABCFG 0x90[6] = 1 +// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF +// ABCFG 0xC0[7:4] = 0x0 + + rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT8, (BIT4 + BIT5 + BIT6 + BIT7)); + rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, (BIT12 + BIT13 + BIT14 + BIT15)); + rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); + rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); + rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19)); + rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, 0x0fffffff); + rwAlink ((SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)), ~(BIT4 + BIT5 + BIT6 + BIT7), 0); + } + sbGppDisableUnusedPadMap ( pConfig ); +} + +/** + * PreInitGppLink - Enable GPP link training. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +PreInitGppLink ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 portMask[5] = {0x01, + 0x00, + 0x03, + 0x07, + 0x0F + }; + UINT8 cfgMode; + UINT8 portId; + UINT32 reg32Value; + UINT16 tmp16Value; + +// PCIE_GPP_ENABLE (abcfg:0xC0): +// +// GPP_LINK_CONFIG ([3:0]) PortA PortB PortC PortD Description +// ---------------------------------------------------------------------------------- +// 0000 0-3 x4 Config +// 0001 N/A +// 0010 0-1 2-3 0 2:2 Config +// 0011 0-1 2 3 2:1:1 Config +// 0100 0 1 2 3 1:1:1:1 Config +// +// For A12 and above: +// ABCFG:0xC0[12] - Port A hold training (default 1) +// ABCFG:0xC0[13] - Port B hold training (default 1) +// ABCFG:0xC0[14] - Port C hold training (default 1) +// ABCFG:0xC0[15] - Port D hold training (default 1) +// +// + // + // Set port enable bit fields based on current GPP link configuration mode + // + cfgMode = (UINT8) pConfig->GppLinkConfig; + if ( cfgMode > GPP_CFGMODE_X1111 || cfgMode == 1 ) { + cfgMode = GPP_CFGMODE_X4000; + pConfig->GppLinkConfig = GPP_CFGMODE_X4000; + } + reg32Value = (UINT32) portMask[cfgMode]; + + // Mask out non-applicable ports according to the target link configuration mode + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + pConfig->PORTCONFIG[portId].PortCfg.PortPresent &= (reg32Value >> portId) & BIT0; + } + + // + // Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) + // + tmp16Value = (UINT16) (~reg32Value << 12); + reg32Value = (UINT32) (tmp16Value + (reg32Value << 4) + cfgMode); + writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), reg32Value); + + reg32Value = readAlink (0xC0 | (UINT32) (RCINDXC << 29)); + writeAlink (0xC0 | (UINT32) (RCINDXC << 29), reg32Value | 0x400); // Set STRAP_F0_MSI_EN + + // A-Link L1 Entry Delay Shortening + // AXINDP_Reg 0xA0[7:4] = 0x3 + rwAlink (SB_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30); + rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19); + rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28); + + // RPR5.22 GPP L1 Entry Delay Shortening + // RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request. + // This is done to reduce number of NAK received with L1 enabled. + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + rwAlink (SB_RCINDXP_REGA0 | portId << 24, 0xFFFFFF0F, 0x10); + } +} + +/** + * CheckGppLinkStatus - loop polling the link status for each GPP port + * + * + * Return: ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +UINT8 +CheckGppLinkStatus ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 retryCounter; + UINT32 portId; + UINT32 abIndex; + UINT32 Data32; + UINT8 portScanMap; + UINT8 portScanMap2; + UINT8 ToggleStatus; + UINT16 i; + SBGPPPORTCONFIG *portCfg; + + + portScanMap = 0; + retryCounter = MAX_TRAINING_RETRY; + ToggleStatus = 0; + + // Obtain a list of ports to be checked + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + portCfg = &pConfig->PORTCONFIG[portId].PortCfg; + if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) { + portScanMap |= 1 << portId; + } + } + portScanMap2 = portScanMap; + + // + // After training is enabled, Check LCSTATE for each port, if LCSTATE<= 4, then keep + // polling for up to 40ms. If LCSTATE still <= 4, then assume the port to be empty. + // + i = 400; + while ( --i && portScanMap2) { + for (portId = 0; portId < MAX_GPP_PORTS; portId++) { + portCfg = &pConfig->PORTCONFIG[portId].PortCfg; + if (((portCfg->PortHotPlug == FALSE) || ((portCfg->PortHotPlug == TRUE) && (pConfig->S3Resume == FALSE)) ) && (portScanMap2 & (1 << portId))) { + // + // Get port link state (reading LC_CURRENT_STATE of PCIEIND_P) + // + abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24); + Data32 = readAlink (abIndex) & 0x3F; + if ((UINT8) (Data32) > 4) { + portScanMap2 &= ~(1 << portId); // This port is not empty + break; + } + SbStall (100); // Delay 100us + } + } + } + portScanMap &= ~portScanMap2; // Mark remaining ports as empty + + + while ( --retryCounter && portScanMap ) { + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + portCfg = &pConfig->PORTCONFIG[portId].PortCfg; + if (( portCfg->PortHotPlug == TRUE ) && ( pConfig->S3Resume )) { + continue; + } + if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) { + // + // Get port link state (reading LC_CURRENT_STATE of PCIEIND_P) + // + SbStall (1000); // Delay 400us + abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24); + Data32 = readAlink (abIndex) & 0x3F3F3F3F; + + if ( (UINT8) (Data32) == 0x10 ) { + portCfg->PortDetected = TRUE; + portScanMap &= ~(1 << portId); + } else { + for (i = 0; i < 4; i++) { + // + // Compliance mode (0x7), downgrade from Gen2 to Gen1 (*A12) + // + if ((UINT8) (Data32) == 0x29 || (UINT8) (Data32) == 0x2A || (UINT8) (Data32) == 0x7 ) { + ToggleStatus |= (1 << portId); // A11 only: need to toggle GPP reset + portScanMap &= ~(1 << portId); + } + Data32 >>= 8; + } + } + } + } + } + return ToggleStatus; +} + + +/** + * AfterGppLinkInit + * - Search for display device behind each GPP port + * - If the port is empty AND not hotplug-capable: + * * Turn off link training + * * (optional) Power down the port + * * Hide the configuration space (Turn off the port) + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +AfterGppLinkInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 portId; + SBGPPPORTCONFIG *portCfg; + UINT32 regBusNumber; + UINT32 abValue; + UINT32 abIndex; + UINT32 i; + UINT32 Data32; + UINT8 bValue; + UINT8 cimGppGen2; + + cimGppGen2 = pConfig->GppGen2; +#if SB_CIMx_PARAMETER == 0 + cimGppGen2 = cimGppGen2Default; +#endif + + bValue = GPP_EFUSE_LOCATION; + getEfuseStatus (&bValue); + if ( (bValue & GPP_GEN2_EFUSE_BIT) != 0 ) { + cimGppGen2 = FALSE; + } else { + pConfig->CoreGen2Enable = TRUE; // Output for platform use + } + +//GPP Gen2 Speed Change +// if ((GPP Gen2 == enabled) and (RCINDP_Reg 0xA4[0] == 0x1)) { +// PCIe_Cfg 0x88[3:0] = 0x2 +// RCINDP_Reg 0xA2[13] = 0x0 +// RCINDP_Reg 0xC0[15] = 0x0 +// RCINDP_Reg 0xA4[29] = 0x1 +// } else { +// PCIe_Cfg 0x88[3:0] = 0x1 +// RCINDP_Reg 0xA4[0] = 0x0 +// RCINDP_Reg 0xA2[13] = 0x1 +// RCINDP_Reg 0xC0[15] = 0x0 +// RCINDP_Reg 0xA4[29] = 0x1 +// } + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + portCfg = &pConfig->PORTCONFIG[portId].PortCfg; + abValue = readAlink (SB_RCINDXP_REGA4 | portId << 24) & BIT0; + if (( cimGppGen2 == TRUE ) && (abValue == BIT0) && (portCfg->PortDetected == TRUE)) { + portCfg->PortIsGen2 = TRUE; // Output for platform use + sbGppForceGen2 (portId); + //_asm {jmp $}; + SbStall (400); // Delay 400us + i = 500; + Data32 = 0; + while ( --i ) { + abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24); + Data32 = readAlink (abIndex) & 0x3F; + if ((UINT8) (Data32) == 0x10) { + break; + } + SbStall (400); // Delay 100us + } + if (!( (UINT8) (Data32) == 0x10 )) { + if (pConfig->GppCompliance == FALSE) { + portCfg->PortIsGen2 = FALSE; // Revert to default; output for platform use + sbGppForceGen1 (portId); + } + } + } else { + if (pConfig->GppCompliance == FALSE) { + sbGppForceGen1 (portId); + } + } +//RPR 5.9 Link Bandwidth Notification Capability Enable +//RCINDC 0xC1[0] = 1 +//PCIe Cfg 0x68[10] = 0 +//PCIe Cfg 0x68[11] = 0 + + rwAlink (SB_RCINDXC_REGC1, 0xFFFFFFFF, BIT0); + RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x68), AccWidthUint16, ~(BIT10 + BIT11), 0); + } + +// Status = AGESA_SUCCESS; + pConfig->GppFoundGfxDev = 0; + abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + portCfg = &pConfig->PORTCONFIG[portId].PortCfg; + // Check if there is GFX device behind each GPP port + if ( portCfg->PortDetected == TRUE ) { + regBusNumber = (SBTEMP_BUS << 16) + (SBTEMP_BUS << 8); + WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, ®BusNumber); + // *** Stall (); + ReadPCI (PCI_ADDRESS (SBTEMP_BUS, 0, 0, 0x0B), AccWidthUint8, &bValue); + if ( bValue == 3 ) { + pConfig->GppFoundGfxDev |= (1 << portId); + } + regBusNumber = 0; + WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, ®BusNumber); + } + + // Mask off non-applicable ports + else if ( portCfg->PortPresent == FALSE ) { + abValue &= ~(1 << (portId + 4)); + } + // Mask off empty port if the port is not hotplug-capable + else if ( portCfg->PortHotPlug == FALSE ) { + abValue &= ~(1 << (portId + 4)); + } + // Clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0) to make hotplug working + if ( portCfg->PortHotPlug == TRUE ) { + rwAlink ((SB_ABCFG_REG340 + portId * 4) | (UINT32) (ABCFG << 29), ~BIT21, 0); + +// RPR5.12 Hot Plug: PCIe Native Support +// RCINDP_Reg 0x10[3] = 0x1 +// PCIe_Cfg 0x5A[8] = 0x1 +// PCIe_Cfg 0x6C[6] = 0x1 +// RCINDP_Reg 0x20[19] = 0x0 + + rwAlink ((SB_RCINDXP_REG10 | (UINT32) (RCINDXP << 29) | (portId << 24)), 0xFFFFFFFF, BIT3); + RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x5b), AccWidthUint8, 0xff, BIT0); + RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x6c), AccWidthUint8, 0xff, BIT6); + rwAlink ((SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24)), ~BIT19, 0); + } + } + if ( pConfig->GppUnhidePorts == FALSE ) { + if ((abValue & 0xF0) == 0) { + abValue = BIT8; // if all ports are empty set GPP_RESET + } else if ((abValue & 0xE0) != 0 && (abValue & 0x10) == 0) { + abValue |= BIT4; // PortA should always be visible whenever other ports are exist + } + + // Update GPP_Portx_Enable (abcfg:0xC0[7:5]) + writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), abValue); + } + + // + // Common initialization for open GPP ports + // + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + ReadPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue); + if (bValue != 0xff) { + // Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0]) + bValue &= 0xf0; + bValue |= 0x06; + WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue); + + // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1 + abIndex = SB_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (portId << 24); + abValue = readAlink (abIndex) | BIT19; + writeAlink (abIndex, abValue); + + // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0 + abIndex = SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24); + abValue = readAlink (abIndex) & ~BIT19; + writeAlink (abIndex, abValue); + + } + } +} + + +/** + * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbPcieGppLateInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 reg32Value; + UINT8 portId; + UINT8 busNum; + UINT8 aspmValue; + UINT8 reg8Value; + UINT8 cimGppPhyPllPowerDown; + + reg8Value = 0x01; +// +// Configure ASPM +// +// writeAlink (0xC0 | (UINT32) (RCINDXC << 29), 0x400); // Set STRAP_F0_MSI_EN + aspmValue = (UINT8)pConfig->GppPortAspm; + cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown; +#if SB_CIMx_PARAMETER == 0 + aspmValue = cimGppPortAspmDefault; + cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault; +#endif + + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + // write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under Vista + // when native PCIE is enabled but MSI is not available + // SB02029: SB800 BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg + WritePCI (PCI_ADDRESS (0, 21, portId, 0x3d), AccWidthUint8, ®8Value); + ReadPCI (PCI_ADDRESS (0, 21, portId, 0x19), AccWidthUint8, &busNum); + if (busNum != 0xFF) { + ReadPCI (PCI_ADDRESS (busNum, 0, 0, 0x00), AccWidthUint32, ®32Value); + if (reg32Value != 0xffffffff) { + // Set ASPM on EP side + sbGppSetAspm (PCI_ADDRESS (busNum, 0, 0, 0), aspmValue & 0x3); + // Set ASPM on port side + sbGppSetAspm (PCI_ADDRESS (0, 21, portId, 0), aspmValue & 0x3); + } + } + aspmValue = aspmValue >> 2; + } + +// +// Configure Lock HWInit registers +// + reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + if (reg32Value & 0xF0) { + reg32Value = readAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29)); + writeAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), reg32Value | BIT0); // Set HWINIT_WR_LOCK + + if ( cimGppPhyPllPowerDown == TRUE ) { +// +// RPR 5.4 Power Saving Feature for GPP Lanes +// + UINT32 abValue; + // Set PCIE_P_CNTL in Alink PCIEIND space + abValue = readAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29)); + abValue |= BIT12 + BIT3 + BIT0; + abValue &= ~(BIT9 + BIT4); + writeAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), abValue); + } + } + +// +// Configure Lock HWInit registers +// + reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); +// +// Disable hidden register decode and serial number capability +// + reg32Value = readAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29)); + writeAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29), reg32Value & ~(BIT26 + BIT10)); +} + +/** + * sbGppSetAspm - Set SPP ASPM + * + * + * @param[in] pciAddress PCI Address. + * @param[in] LxState Lane State. + * + */ +VOID +sbGppSetAspm ( + IN UINT32 pciAddress, + IN UINT8 LxState + ) +{ + UINT8 pcieCapOffset; + UINT8 value8; + UINT8 maxFuncs; + UINT32 devBDF; + + maxFuncs = 1; + ReadPCI (pciAddress + 0x0E, AccWidthUint8, &value8); + + if (value8 & BIT7) { + maxFuncs = 8; // multi-function device + } + while (maxFuncs != 0) { + devBDF = pciAddress + (UINT32) ((maxFuncs - 1) << 16); + pcieCapOffset = sbFindPciCap (devBDF, PCIE_CAP_ID); + if (pcieCapOffset) { + // Read link capabilities register (0x0C[11:10] - ASPM support) + ReadPCI (devBDF + pcieCapOffset + 0x0D, AccWidthUint8, &value8); + if (value8 & BIT2) { + value8 = (value8 >> 2) & (BIT1 + BIT0); + // Set ASPM state in link control register + RWPCI (devBDF + pcieCapOffset + 0x10, AccWidthUint8, 0xffffffff, LxState & value8); + } + } + maxFuncs--; + } +} + +/** + * sbFindPciCap - Find PCI Cap + * + * + * @param[in] pciAddress PCI Address. + * @param[in] targetCapId Target Cap ID. + * + */ +UINT8 +sbFindPciCap ( + IN UINT32 pciAddress, + IN UINT8 targetCapId + ) +{ + UINT8 NextCapPtr; + UINT8 CapId; + + NextCapPtr = 0x34; + while (NextCapPtr != 0) { + ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &NextCapPtr); + if (NextCapPtr == 0xff) { + return 0; + } + if (NextCapPtr != 0) { + ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &CapId); + if (CapId == targetCapId) { + break; + } else { + NextCapPtr++; + } + } + } + return NextCapPtr; +} + +/** + * sbGppForceGen2 - Set SPP to GENII + * + * + * @param[in] portId + * + */ +VOID +sbGppForceGen2 ( + IN UINT32 portId + ) +{ + RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x02); + rwAlink (SB_RCINDXP_REGA2 | portId << 24, ~BIT13, 0); + rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0); + rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29); +} + +/** + * sbGppForceGen1 - Set SPP to GENI + * + * + * @param[in] portId + * + */ +VOID +sbGppForceGen1 ( + IN UINT32 portId + ) +{ + RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x01); + rwAlink (SB_RCINDXP_REGA4 | portId << 24, ~BIT0, 0); + rwAlink (SB_RCINDXP_REGA2 | portId << 24, 0xFFFFFFFF, BIT13); + rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0); + rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29); +} + +/** + * sbGppDisableUnusedPadMap - Return GPP Pad Map + * + * + * @param[in] pConfig + * + */ +VOID +sbGppDisableUnusedPadMap ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 Data32; + UINT32 HoldData32; + SBGPPPORTCONFIG *portCfg; + UINT8 cimGppLaneReversal; + UINT8 cimAlinkPhyPllPowerDown; + UINT8 cimGppPhyPllPowerDown; + + cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown; + cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal; + cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown; +#if SB_CIMx_PARAMETER == 0 + cimGppLaneReversal = cimGppLaneReversalDefault; + cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault; + cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault; +#endif + + Data32 = 0; + HoldData32 = 0; + switch ( pConfig->GppLinkConfig ) { + case GPP_CFGMODE_X4000: + portCfg = &pConfig->PORTCONFIG[0].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= 0x0f0f; + HoldData32 |= 0x1000; + } + break; + case GPP_CFGMODE_X2200: + portCfg = &pConfig->PORTCONFIG[0].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303; + HoldData32 |= 0x1000; + } + portCfg = &pConfig->PORTCONFIG[1].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0303:0x0c0c; + HoldData32 |= 0x2000; + } + break; + case GPP_CFGMODE_X2110: + portCfg = &pConfig->PORTCONFIG[0].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303; + HoldData32 |= 0x1000; + } + portCfg = &pConfig->PORTCONFIG[1].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404; + HoldData32 |= 0x2000; + } + portCfg = &pConfig->PORTCONFIG[2].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808; + HoldData32 |= 0x4000; + } + break; + case GPP_CFGMODE_X1111: + portCfg = &pConfig->PORTCONFIG[0].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0808:0x0101; + HoldData32 |= 0x1000; + } + portCfg = &pConfig->PORTCONFIG[1].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0404:0x0202; + HoldData32 |= 0x2000; + } + portCfg = &pConfig->PORTCONFIG[2].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404; + HoldData32 |= 0x4000; + } + portCfg = &pConfig->PORTCONFIG[3].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808; + HoldData32 |= 0x8000; + } + break; + default: + break; + } + +// RPR 5.11 Power Saving With GPP Disable +// ABCFG 0xC0[8] = 0x0 +// ABCFG 0xC0[15:12] = 0xF +// Enable "Power Saving Feature for A-Link Express Lanes" +// Enable "Power Saving Feature for GPP Lanes" +// ABCFG 0x90[19] = 1 +// ABCFG 0x90[6] = 1 +// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF +// ABCFG 0xC0[7:4] = 0x0 + if ( (Data32 & 0xf) == 0xf ) Data32 |= 0x0cff0000; + if ( cimAlinkPhyPllPowerDown && cimGppPhyPllPowerDown ) { + rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT8, 0); + rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, HoldData32); + rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); + rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); + rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19)); + rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, Data32); + } +} Added: trunk/src/vendorcode/amd/cimx/sb800/IOLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/IOLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,81 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + + +VOID +ReadIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + *(UINT8*)Value = ReadIo8 (Address); + break; + case AccWidthUint16: + *(UINT16*)Value = ReadIo16 (Address); + break; + case AccWidthUint32: + *(UINT32*)Value = ReadIo32 (Address); + break; + } +} + +VOID +WriteIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + WriteIo8 (Address, *(UINT8*)Value); + break; + case AccWidthUint16: + WriteIo16 (Address, *(UINT16*)Value); + break; + case AccWidthUint32: + WriteIo32 (Address, *(UINT32*)Value); + break; + } +} + +VOID +RWIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + ReadIO (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WriteIO (Address, OpFlag, &Result); +} Added: trunk/src/vendorcode/amd/cimx/sb800/LEGACY.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/LEGACY.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,37 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +UINT32 +GetFixUp ( + OUT VOID + ) +{ + AMD_CONFIG_PARAMS* Result; + Result = (AMD_CONFIG_PARAMS*) getConfigPointer (); + if ( Result->ImageBasePtr > 0x100000 && Result->ImageBasePtr < 0xFF000000 ) { + return 0; + } + return Result->ImageBasePtr; +} Added: trunk/src/vendorcode/amd/cimx/sb800/MEMLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/MEMLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,86 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +VOID +ReadMEM ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + *((UINT8*)Value) = *((UINT8*) ((UINTN)Address)); + break; + case AccWidthUint16: + //*((UINT16*)Value) = *((UINT16*) ((UINTN)Address)); //gcc break strict-aliasing rules + *((UINT8*)Value) = *((UINT8*) ((UINTN)Address)); + *((UINT8*)Value + 1) = *((UINT8*)((UINTN)Address) + 1); + break; + case AccWidthUint32: + *((UINT32*)Value) = *((UINT32*) ((UINTN)Address)); + break; + } +} + +VOID +WriteMEM ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8 : + *((UINT8*) ((UINTN)Address)) = *((UINT8*)Value); + break; + case AccWidthUint16: + //*((UINT16*) ((UINTN)Address)) = *((UINT16*)Value); //gcc break strict-aliasing rules + *((UINT8*)((UINTN)Address)) = *((UINT8*)Value); + *((UINT8*)((UINTN)Address) + 1) = *((UINT8*)Value + 1); + break; + case AccWidthUint32: + *((UINT32*) ((UINTN)Address)) = *((UINT32*)Value); + break; + } +} + +VOID +RWMEM ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + ReadMEM (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WriteMEM (Address, OpFlag, &Result); +} + + Added: trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,75 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# CIMX Root directory +CIMX_ROOT = src/vendorcode/amd/cimx + +CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) +CIMX_INC += -I$(src)/southbridge/amd/cimx_wrapper/sb800 +CIMX_INC += -I$(CIMX_ROOT)/sb800 +#TODO merge withagesa lib functions +CIMX_INC += -I$(CIMX_ROOT)/lib + +# CIMX LIB files +romstage-y += MEMLIB.c +romstage-y += PCILIB.c +romstage-y += IOLIB.c +romstage-y += PMIOLIB.c +romstage-y += AMDLIB.c +romstage-y += SBPELIB.c +romstage-y += AMDSBLIB.c +romstage-y += SBPOR.c +romstage-y += ECLIB.c +romstage-y += EC.c +ramstage-y += DISPATCHER.c + +ramstage-y += ACPILIB.c +ramstage-y += AZALIA.c +ramstage-y += DISPATCHER.c +ramstage-y += ECfanc.c +ramstage-y += ECfanLIB.c +ramstage-y += GEC.c +ramstage-y += Gpp.c +ramstage-y += PMIO2LIB.c +ramstage-y += SATA.c +ramstage-y += SBCMN.c +ramstage-y += SBMAIN.c +ramstage-y += SBPOR.c +ramstage-y += MEMLIB.c +ramstage-y += PCILIB.c +ramstage-y += IOLIB.c +ramstage-y += PMIOLIB.c +ramstage-y += AMDLIB.c +ramstage-y += SBPELIB.c +ramstage-y += AMDSBLIB.c +ramstage-y += ECLIB.c +ramstage-y += EC.c +ramstage-y += SMM.c +ramstage-y += USB.c +#ramstage-y += LEGACY.c +#ramstage-y += SbModInf.c + +CIMX_CFLAGS = +export CIMX_ROOT +export CIMX_INC +export CIMX_CFLAGS +CC := $(CC) $(CIMX_INC) + +####################################################################### + Added: trunk/src/vendorcode/amd/cimx/sb800/OEM.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/OEM.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,274 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#define BIOS_SIZE 0x04 //04 - 1MB +#define LEGACY_FREE 0x00 +#define ACPI_SLEEP_TRAP 0x01 +//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01 + +/** + * Module Specific Defines for platform BIOS + * + */ + +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 + #define PCIEX_BASE_ADDRESS 0xF7000000 +#else + #define PCIEX_BASE_ADDRESS 0xE0000000 +#endif + +/** + * SMBUS0_BASE_ADDRESS - Smbus base address + * + */ +#ifndef SMBUS0_BASE_ADDRESS + #define SMBUS0_BASE_ADDRESS 0xB00 +#endif + +/** + * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address + * + */ +#ifndef SMBUS1_BASE_ADDRESS + #define SMBUS1_BASE_ADDRESS 0xB20 +#endif + +/** + * GEC_BASE_ADDRESS - Gec Shadow ROM base address + * + */ +#ifndef GEC_BASE_ADDRESS + #define GEC_BASE_ADDRESS 0xFED61000 +#endif + + +/** + * SIO_PME_BASE_ADDRESS - Super IO PME base address + * + */ +#ifndef SIO_PME_BASE_ADDRESS + #define SIO_PME_BASE_ADDRESS 0xE00 +#endif + +/** + * SPI_BASE_ADDRESS - SPI controller (ROM) base address + * + */ +#ifndef SPI_BASE_ADDRESS + #define SPI_BASE_ADDRESS 0xFEC10000 +#endif + +/** + * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address + * + */ +#ifndef WATCHDOG_TIMER_BASE_ADDRESS + #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address +#endif + +/** + * HPET_BASE_ADDRESS - HPET base address + * + */ +#ifndef HPET_BASE_ADDRESS + #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address +#endif + +/** + * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address + * + */ +#ifdef ALT_ADDR_400 + #define ACPI_BLK_BASE 0x400 +#else + #define ACPI_BLK_BASE 0x800 +#endif + +#define PM1_STATUS_OFFSET 0x00 +#define PM1_ENABLE_OFFSET 0x02 +#define PM1_CONTROL_OFFSET 0x04 +#define PM_TIMER_OFFSET 0x08 +#define CPU_CONTROL_OFFSET 0x10 +#define EVENT_STATUS_OFFSET 0x20 +#define EVENT_ENABLE_OFFSET 0x24 + +/** + * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address + * + */ +#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr + +/** + * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address + * + */ +#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr + +/** + * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address + * + */ +#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr + +/** + * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address + * + */ +#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr + +/** + * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address + * + */ +#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr + +/** + * SMI_CMD_PORT - ACPI SMI Command block base address + * + */ +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr + +/** + * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address + * + */ +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr + +/** + * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID. + * Define value for SSID while SATA controller set to IDE mode. + */ +#ifndef SATA_IDE_MODE_SSID + #define SATA_IDE_MODE_SSID 0x43901002 +#endif + +/** + * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID. + * Define value for SSID while SATA controller set to RAID mode. + */ +#ifndef SATA_RAID_MODE_SSID + #define SATA_RAID_MODE_SSID 0x43921002 +#endif + +/** + * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID. + * Define value for SSID while SATA controller set to RAID5 mode. + */ +#ifndef SATA_RAID5_MODE_SSID + #define SATA_RAID5_MODE_SSID 0x43931002 +#endif + +/** + * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID. + * Define value for SSID while SATA controller set to AHCI mode. + */ +#ifndef SATA_AHCI_SSID + #define SATA_AHCI_SSID 0x43911002 +#endif + +/** + * OHCI_SSID - All SB OHCI controllers SSID value. + * + */ +#ifndef OHCI_SSID + #define OHCI_SSID 0x43971002 +#endif + +/** + * EHCI_SSID - All SB EHCI controllers SSID value. + * + */ +#ifndef EHCI_SSID + #define EHCI_SSID 0x43961002 +#endif + +/** + * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value. + * + */ +#ifndef OHCI4_SSID + #define OHCI4_SSID 0x43991002 +#endif + +/** + * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value. + * + */ +#ifndef SMBUS_SSID + #define SMBUS_SSID 0x43851002 +#endif + +/** + * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value. + * + */ +#ifndef IDE_SSID + #define IDE_SSID 0x439C1002 +#endif + +/** + * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value. + * + */ +#ifndef AZALIA_SSID + #define AZALIA_SSID 0x43831002 +#endif + +/** + * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value. + * + */ +#ifndef LPC_SSID + #define LPC_SSID 0x439D1002 +#endif + +/** + * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value. + * + */ +#ifndef PCIB_SSID + #define PCIB_SSID 0x43841002 +#endif + +/** + * USB_PLL_Voltage - CG2 Clock voltage setting. + * + */ +#ifndef USB_PLL_Voltage + #define USB_PLL_Voltage 0x10 +#endif + +/** + * Spread_Spectrum_Type + * + * - 0 : Normal platform + * - 1 : Ontario platform + */ +#ifndef Spread_Spectrum_Type + #define Spread_Spectrum_Type 0x00 +#endif Added: trunk/src/vendorcode/amd/cimx/sb800/PCILIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/PCILIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,76 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +#include "SBPLATFORM.h" + +VOID +ReadPCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + + if ( (UINT16)Address < 0xff ) { + //Normal Config Access + UINT32 AddrCf8; + AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC); + WriteIO (0xCf8, AccWidthUint32, &AddrCf8); + ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); + } +} + +VOID +WritePCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + if ( (UINT16)Address < 0xff ) { + //Normal Config Access + UINT32 AddrCf8; + AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC); + WriteIO (0xCf8, AccWidthUint32, &AddrCf8); + WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); + } +} + +VOID +RWPCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + Result = 0; + OpFlag = OpFlag & 0x7f; + ReadPCI (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WritePCI (Address, OpFlag, &Result); +} Added: trunk/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,120 @@ +/** + * @file + * + * Southbridge PMIO2 access common routine + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * + */ +VOID +ReadPMIO2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + UINT8 i; + OpFlag = OpFlag & 0x7f; + + if ( OpFlag == 0x02 ) { + OpFlag = 0x03; + } + for ( i = 0; i <= OpFlag; i++ ) { + WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 + Address++; + ReadIO (0xCD1, AccWidthUint8, (UINT8 *) Value + i); // SB_IOMAP_REGCD1 + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PMIO 2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * + */ +VOID +WritePMIO2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + UINT8 i; + OpFlag = OpFlag & 0x7f; + + if ( OpFlag == 0x02 ) { + OpFlag = 0x03; + } + for ( i = 0; i <= OpFlag; i++ ) { + WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 + Address++; + WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD1 + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RWPMIO2 - Read/Write PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * + */ +VOID +RWPMIO2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN UINT32 AndMask, + IN UINT32 OrMask + ) +{ + UINT32 Result; + OpFlag = OpFlag & 0x7f; + ReadPMIO2 (Address, OpFlag, &Result); + Result = (Result & AndMask) | OrMask; + WritePMIO2 (Address, OpFlag, &Result); +} Added: trunk/src/vendorcode/amd/cimx/sb800/PMIOLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/PMIOLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,119 @@ +/** + * @file + * + * Southbridge PMIO access common routine + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * + */ +VOID +ReadPMIO ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + UINT8 i; + OpFlag = OpFlag & 0x7f; + + if ( OpFlag == 0x02 ) { + OpFlag = 0x03; + } + for ( i = 0; i <= OpFlag; i++ ) { + WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + Address++; + ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7 + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * + */ +VOID +WritePMIO ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + UINT8 i; + OpFlag = OpFlag & 0x7f; + + if ( OpFlag == 0x02 ) { + OpFlag = 0x03; + } + for ( i = 0; i <= OpFlag; i++ ) { + WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + Address++; + WriteIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7 + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RWPMIO - Read/Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * + */ +VOID +RWPMIO ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN UINT32 AndMask, + IN UINT32 OrMask + ) +{ + UINT32 Result; + OpFlag = OpFlag & 0x7f; + ReadPMIO (Address, OpFlag, &Result); + Result = (Result & AndMask) | OrMask; + WritePMIO (Address, OpFlag, &Result); +} Added: trunk/src/vendorcode/amd/cimx/sb800/SATA.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SATA.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,665 @@ + +/** + * @file + * + * Config Southbridge SATA controller + * + * Init SATA features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +// +// Declaration of local functions +// +VOID sataSetIrqIntResource (IN AMDSBCFG* pConfig); +VOID sataBar5setting (IN AMDSBCFG* pConfig, IN UINT32 *pBar5); +VOID shutdownUnconnectedSataPortClock (IN AMDSBCFG* pConfig, IN UINT32 ddBar5); +VOID sataDriveDetection (IN AMDSBCFG* pConfig, IN UINT32 *pBar5); + +/** + * sataSetIrqIntResource - Config SATA IRQ/INT# resource + * + * + * - Private function + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sataSetIrqIntResource ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 dbValue; + // IRQ14/IRQ15 come from IDE or SATA + dbValue = 0x08; + WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue); + ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); + dbValue = dbValue & 0x0F; + if (pConfig->SataClass == 3) { + dbValue = dbValue | 0x50; + } else { + if (pConfig->SataIdeMode == 1) { + // Both IDE & SATA set to Native mode + dbValue = dbValue | 0xF0; + } + } + WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); +} + +/** + * sataBar5setting - Config SATA BAR5 + * + * - Private function + * + * @param[in] pConfig - Southbridge configuration structure pointer. + * @param[in] *pBar5 - SATA BAR5 buffer. + * + */ +VOID +sataBar5setting ( + IN AMDSBCFG* pConfig, + IN UINT32 *pBar5 + ) +{ + //Get BAR5 value + ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5); + //Assign temporary BAR if is not already assigned + if ( (*pBar5 == 0) || (*pBar5 == - 1) ) { + //assign temporary BAR5 + if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) { + *pBar5 = 0xFEC01000; + } else { + *pBar5 = pConfig->TempMMIO; + } + WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5); + } + //Clear Bits 9:0 + *pBar5 = *pBar5 & 0xFFFFFC00; +} +/** + * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock + * + * - Private function + * + * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] ddBar5 Sata BAR5 base address. + * + */ +VOID +shutdownUnconnectedSataPortClock ( + IN AMDSBCFG* pConfig, + IN UINT32 ddBar5 + ) +{ + UINT8 dbPortNum; + UINT8 dbPortSataStatus; + UINT8 NumOfPorts; + UINT8 cimSataClkAutoOff; + + cimSataClkAutoOff = (UINT8) pConfig->SataClkAutoOff; +#if SB_CIMx_PARAMETER == 0 + cimSataClkAutoOff = cimSataClkAutoOffDefault; +#endif + NumOfPorts = 0; + if ( cimSataClkAutoOff == TRUE ) { + for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) { + ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus); + // Shutdown the clock for the port and do the necessary port reporting changes. + // ?? Error port status should be 1 not 3 + if ( ((dbPortSataStatus & 0x0F) != 0x03) && (! ((pConfig->SataEspPort) & (1 << dbPortNum))) ) { + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, (1 << dbPortNum)); + RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(1 << dbPortNum), 00); + } + } //end of for (dbPortNum=0;dbPortNum<6;dbPortNum++) + ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus); + //if all ports are in disabled state, report atleast one port + if ( (dbPortSataStatus & 0x3F) == 0) { + RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, (UINT32) ~(0x3F), 01); + } + ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus); + for (dbPortNum = 0; dbPortNum < 6; dbPortNum ++) { + if (dbPortSataStatus & (1 << dbPortNum)) { + NumOfPorts++; + } + } + if ( NumOfPorts == 0) { + NumOfPorts = 0x01; + } + RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1); + } //end of SataClkAuto Off option +} + +/** + * Table for class code of SATA Controller in different modes + * + * + * + * + */ +UINT32 sataIfCodeTable[] = +{ + 0x01018F40, //sata class ID of IDE + 0x01040040, //sata class ID of RAID + 0x01060140, //sata class ID of AHCI + 0x01018A40, //sata class ID of Legacy IDE + 0x01018F40, //sata class ID of IDE to AHCI mode +}; + +/** + * Table for device id of SATA Controller in different modes + * + * + * + * + */ +UINT16 sataDeviceIDTable[] = +{ + 0x4390, //sata device ID of IDE + 0x4392, //sata device ID of RAID + 0x4391, //sata class ID of AHCI + 0x4390, //sata device ID of Legacy IDE + 0x4390, //sata device ID of IDE->AHCI mode +}; + +/** + * Table for Sata Phy Fine Setting + * + * + * + * + */ +SATAPHYSETTING sataPhyTable[] = +{ + {0x3006, 0x0056A607}, + {0x2006, 0x00061400}, + {0x1006, 0x00061302}, + + {0x3206, 0x0056A607}, + {0x2206, 0x00061400}, + {0x1206, 0x00061302}, + + {0x3406, 0x0056A607}, + {0x2406, 0x00061402}, + {0x1406, 0x00064300}, + + {0x3606, 0x0056A607}, + {0x2606, 0x00061402}, + {0x1606, 0x00064300}, + + {0x3806, 0x0056A700}, + {0x2806, 0x00061502}, + {0x1806, 0x00064302}, + + {0x3A06, 0x0056A700}, + {0x2A06, 0x00061502}, + {0x1A06, 0x00064302} +}; + +/** + * sataInitBeforePciEnum - Config SATA controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sataInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddTempVar; + UINT32 ddValue; + UINT32 *tempptr; + UINT16 *pDeviceIdptr; + UINT32 dwDeviceId; + UINT8 dbValue; + UINT8 pValue; + UINT16 i; + SATAPHYSETTING *pPhyTable; + + ddTempVar = NULL; + // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h + // BIT4: Disable fast boot + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4); + // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting IDE PCI register 40h + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0, pConfig->SataPortPower); + dbValue = (UINT8)pConfig->SataClass; + if (dbValue == AHCI_MODE_4394) { + dbValue = AHCI_MODE; + } + if (dbValue == IDE_TO_AHCI_MODE_4394) { + dbValue = IDE_TO_AHCI_MODE; + } + // Disable PATA MSI + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG34), AccWidthUint8 | S3_SAVE, 0x00, 0x00); + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG06), AccWidthUint8 | S3_SAVE, 0xEF, 0x00); + + // Get the appropriate class code from the table and write it to PCI register 08h-0Bh + // Set the appropriate SATA class based on the input parameters + // SATA IDE Controller Class ID & SSID + tempptr = (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]); + if ( (pConfig->SataIdeMode == 1) && (pConfig->SataClass != 3) ) { + ddValue = tempptr[0]; + // Write the class code to IDE PCI register 08h-0Bh + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue); + } + ddValue = tempptr[dbValue]; + // Write the class code to SATA PCI register 08h-0Bh + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue); + if ( pConfig->SataClass == LEGACY_IDE_MODE ) { + //Set PATA controller to native mode + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); + } + if (pConfig->BuildParameters.IdeSsid != NULL ) { + RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid); + } + // SATA Controller Class ID & SSID + pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]); + if ( pConfig->BuildParameters.SataIDESsid != NULL ) { + ddTempVar = pConfig->BuildParameters.SataIDESsid; + } + dwDeviceId = pDeviceIdptr[dbValue]; + if ( pConfig->SataClass == RAID_MODE) { + if ( pConfig->BuildParameters.SataRAID5Ssid != NULL ) { + ddTempVar = pConfig->BuildParameters.SataRAID5Ssid; + } + dwDeviceId = V_SB_SATA_RAID5_DID; + pValue = SATA_EFUSE_LOCATION; + getEfuseStatus (&pValue); + if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) { + dwDeviceId = V_SB_SATA_RAID_DID; + if ( pConfig->BuildParameters.SataRAIDSsid != NULL ) { + ddTempVar = pConfig->BuildParameters.SataRAIDSsid; + } + } + } + if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) || + ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) { + if ( pConfig->BuildParameters.SataAHCISsid != NULL ) { + ddTempVar = pConfig->BuildParameters.SataAHCISsid; + } + } + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId); + if ( ddTempVar != NULL ) { + RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar); + } + // SATA IRQ Resource + sataSetIrqIntResource (pConfig); + + // 8.4 SATA PHY Programming Sequence + pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]); + for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) { + RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84, AccWidthUint16 | S3_SAVE, ~(BIT1 + BIT2 + BIT9 + BIT10 + BIT11 + BIT12 + BIT13 + BIT14), pPhyTable->wPhyCoreControl); + RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune); + ++pPhyTable; + } + +// CallBackToOEM (SATA_PHY_PROGRAMMING, NULL, pConfig); + + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); + // Disable write access to PCI header + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); +} + +/** + * sataInitAfterPciEnum - Config SATA controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sataInitAfterPciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddAndMask; + UINT32 ddOrMask; + UINT32 ddBar5; + UINT8 dbVar; + UINT8 dbPortNum; + UINT8 dbEfuse; + UINT8 dbPortMode; + UINT16 SataPortMode; + UINT8 cimSataAggrLinkPmCap; + UINT8 cimSataPortMultCap; + UINT8 cimSataPscCap; + UINT8 cimSataSscCap; + UINT8 cimSataFisBasedSwitching; + UINT8 cimSataCccSupport; + + cimSataAggrLinkPmCap = (UINT8) pConfig->SataAggrLinkPmCap; + cimSataPortMultCap = (UINT8) pConfig->SataPortMultCap; + cimSataPscCap = (UINT8) pConfig->SataPscCap; + cimSataSscCap = (UINT8) pConfig->SataSscCap; + cimSataFisBasedSwitching = (UINT8) pConfig->SataFisBasedSwitching; + cimSataCccSupport = (UINT8) pConfig->SataCccSupport; + +#if SB_CIMx_PARAMETER == 0 + cimSataAggrLinkPmCap = cimSataAggrLinkPmCapDefault; + cimSataPortMultCap = cimSataPortMultCapDefault; + cimSataPscCap = cimSataPscCapDefault; + cimSataSscCap = cimSataSscCapDefault; + cimSataFisBasedSwitching = cimSataFisBasedSwitchingDefault; + cimSataCccSupport = cimSataCccSupportDefault; +#endif + + ddAndMask = 0; + ddOrMask = 0; + ddBar5 = 0; + if ( pConfig->SATAMODE.SataMode.SataController == 0 ) { + return; //return if SATA controller is disabled. + } + + //Enable write access to pci header, pm capabilities + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + //Disable AHCI Prefetch function + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0x7F, BIT7); + + sataBar5setting (pConfig, &ddBar5); + + ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable + dbEfuse = SATA_FIS_BASE_EFUSE_LOC; + getEfuseStatus (&dbEfuse); + + if ( !cimSataPortMultCap ) { + ddAndMask |= BIT12; + } + if ( cimSataAggrLinkPmCap ) { + ddOrMask |= BIT11; + } else { + ddAndMask |= BIT11; + } + if ( cimSataPscCap ) { + ddOrMask |= BIT1; + } + if ( cimSataSscCap ) { + ddOrMask |= BIT26; + } + if ( cimSataFisBasedSwitching ) { + if (dbEfuse & BIT1) { + ddAndMask |= BIT10; + } else { + ddOrMask |= BIT10; + } + } else { + ddAndMask |= BIT10; + } + // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. + if ( cimSataCccSupport ) { + ddOrMask |= BIT19; + } else { + ddAndMask |= BIT19; + } + RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask); + + + // SATA ESP port setting + // These config bits are set for SATA driver to identify which ports are external SATA ports and need to + // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will + // not enable power management (HIPM & DIPM) for these ports. + if ( pConfig->SataEspPort != 0 ) { + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0); + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT12 + BIT13 + BIT14 + BIT15 + BIT16 + BIT17 + BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), (pConfig->SataEspPort << 12)); + // RPR 8.7 External SATA Port Indication Registers + // If any of the ports was programmed as an external port, HCAP.SXS should also be set + RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), BIT20); + } else { + // RPR 8.7 External SATA Port Indication Registers + // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port) + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x00); + RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), 0x00); + } + if ( cimSataFisBasedSwitching ) { + if (dbEfuse & BIT1) { + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00); + } else { + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), (BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27)); + } + } else { + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00); + } + + // Disabled SATA MSI and D3 Power State capability + // RPR 8.13 SATA MSI and D3 Power State Capability + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70); + + if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) { + // RIAD or AHCI + if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) { + RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); + // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. + // 8 messages + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1); + } else { + // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. + if ( pConfig->SataCccSupport ) { + // 8 messages + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1); + } else { + // 4 messages + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2); + } + } + } + + if ( pConfig->BIOSOSHandoff == 1 ) { + RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, BIT0); + } else { + RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, 0x00); + } + + SataPortMode = (UINT16)pConfig->SataPortMode; + dbPortNum = 0; + while ( dbPortNum < 6 ) { + dbPortMode = (UINT8) (SataPortMode & 3); + if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) { + if ( dbPortMode == BIT0 ) { + // set GEN 1 + RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10); + } + if ( dbPortMode == BIT1 ) { + // set GEN2 (default is GEN3) + RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x20); + } + RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); + } + SataPortMode >>= 2; + dbPortNum ++; + } + SbStall (1000); + SataPortMode = (UINT16)pConfig->SataPortMode; + dbPortNum = 0; + while ( dbPortNum < 6 ) { + dbPortMode = (UINT8) (SataPortMode & 3); + if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) { + RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); + } + dbPortNum ++; + SataPortMode >>= 2; + } + WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + //Disable write access to pci header, pm capabilities + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); +} + + +/** + * sataInitMidPost - Config SATA controller in Middle POST. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sataInitMidPost ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddBar5; + sataBar5setting (pConfig, &ddBar5); + //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround. + if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) ) ) { + sataDriveDetection (pConfig, &ddBar5); + } +} + +/** + * sataDriveDetection - Sata drive detection + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] *pBar5 Sata BAR5 base address. + * + */ +VOID +sataDriveDetection ( + IN AMDSBCFG* pConfig, + IN UINT32 *pBar5 + ) +{ + UINT32 ddVar0; + UINT8 dbPortNum; + UINT8 dbVar0; + UINT16 dwIoBase; + UINT16 dwVar0; + if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) { + for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) { + ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0); + if ( ( ddVar0 & 0x0F ) == 0x03 ) { + if ( dbPortNum & BIT0 ) { + //this port belongs to secondary channel + ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase); + } else { + //this port belongs to primary channel + ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase); + } + //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them + if ( pConfig->SataClass == LEGACY_IDE_MODE ) { + dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) ); + } + if ( dbPortNum & BIT1 ) { + //this port is slave + dbVar0 = 0xB0; + } else { + //this port is master + dbVar0 = 0xA0; + } + dwIoBase &= 0xFFF8; + WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0); + //Wait in loop for 30s for the drive to become ready + for ( dwVar0 = 0; dwVar0 < 300000; dwVar0++ ) { + ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0); + if ( (dbVar0 & 0x88) == 0 ) { + break; + } + SbStall (100); + } + } //end of if ( ( ddVar0 & 0x0F ) == 0x03) + } //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++) + } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)) +} + +/** + * sataInitLatePost - Prepare SATA controller to boot to OS. + * + * - Set class ID to AHCI (if set to AHCI * Mode) + * - Enable AHCI interrupt + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sataInitLatePost ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddBar5; + UINT8 dbVar; + UINT8 dbPortNum; + + //Return immediately is sata controller is not enabled + if ( pConfig->SATAMODE.SataMode.SataController == 0 ) { + return; + } + //Enable write access to pci header, pm capabilities + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); + +// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) { + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7); +// } + sataBar5setting (pConfig, &ddBar5); + + ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + //Enable memory and io access + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03); + + shutdownUnconnectedSataPortClock (pConfig, ddBar5); + + if (( pConfig->SataClass == IDE_TO_AHCI_MODE) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) { + //program the AHCI class code + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100); + //Set interrupt enable bit + RWMEM ((ddBar5 + 0x04), AccWidthUint8, (UINT32)~0, BIT1); + //program the correct device id for AHCI mode + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391); + } + + if (( pConfig->SataClass == AHCI_MODE_4394 ) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) { + //program the correct device id for AHCI 4394 mode + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4394); + } + + //Clear error status ?? only 4 port + RWMEM ((ddBar5 + SB_SATA_BAR5_REG130), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG1B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG230), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG2B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG330), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG3B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + //Restore memory and io access bits + WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar ); + //Disable write access to pci header and pm capabilities + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); + for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) { + RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00); + } +} + + Added: trunk/src/vendorcode/amd/cimx/sb800/SB800.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SB800.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,1893 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#pragma pack (push, 1) + +#define CIMX_SB_REVISION "1.1.0.6" +#define CIMX_SB_ID "SB80A13" +#ifndef SBCIMx_Version + #define SBCIMx_Version 0x1106 +#endif //CIMx_Version + + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_POWERON_INIT_Page SB_POWERON_INIT + * @section SB_POWERON_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_POWERON_INIT_CallIn Call Prototype + * @par + * sbPowerOnInit ((AMDSBCFG*) pConfig) (Followed PH Interface) + * @subsection SB_BEFORE_PCI_INIT_CallID Service ID + * @par + * + * + *
SB_POWERON_INIT --> 0x00010001
+ * @subsection SB_POWERON_INIT_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_POWERON_INIT_Config Prepare for Configuration Data. + * @par + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BUILDPARAM::BiosSize Required
BUILDPARAM::LegacyFree Required
BUILDPARAM::EcKbd Required
BUILDPARAM::Smbus0BaseAddress Required
BUILDPARAM::Smbus1BaseAddress Required
BUILDPARAM::SioPmeBaseAddress Required
BUILDPARAM::WatchDogTimerBase Required
BUILDPARAM::GecShadowRomBase Required
BUILDPARAM::SpiRomBaseAddress Required
BUILDPARAM::AcpiPm1EvtBlkAddr Required
BUILDPARAM::AcpiPm1CntBlkAddr Required
BUILDPARAM::AcpiPmTmrBlkAddr Required
BUILDPARAM::CpuControlBlkAddr Required
BUILDPARAM::AcpiGpe0BlkAddr Required
BUILDPARAM::SmiCmdPortAddr Required
BUILDPARAM::AcpiPmaCntBlkAddr Required
SATAST::SataController Required
SATAST::SataIdeCombinedMode Required
+ * + */ +#define SB_POWERON_INIT 0x00010001 +#define OUTDEBUG_PORT 0x00010002 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_BEFORE_PCI_INIT_Page SB_BEFORE_PCI_INIT + * @section SB_BEFORE_PCI_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_BEFORE_PCI_INIT_CallIn Call Prototype + * @par + * sbBeforePciInit ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_BEFORE_PCI_INIT_CallID Service ID + * @par + * + * + *
SB_BEFORE_PCI_INIT --> 0x00010010
+ * @subsection SB_BEFORE_PCI_INIT_CallOut Prepare for Callout + * @par + * + * + * + *
@ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"
@ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"
+ * @subsection SB_BEFORE_PCI_INIT_Config Prepare for Configuration Data. + * @par + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
SATAST::SataController Required
SATAST::SataIdeCombinedMode Required
AMDSBCFG::SataClass Required
AMDSBCFG::SataIdeMode Required
AMDSBCFG::USBDeviceConfig Required
AMDSBCFG::GecConfig Required
AMDSBCFG::AzaliaController Required
AMDSBCFG::PciClks Required
BUILDPARAM::SataIDESsid Optional
BUILDPARAM::SataRAID5Ssid Optional
BUILDPARAM::SataRAIDSsid Optional
BUILDPARAM::SataAHCISsid Optional
BUILDPARAM::SmbusSsid Optional
BUILDPARAM::LpcSsid Optional
BUILDPARAM::PCIBSsid Optional
+ * + */ +#define SB_BEFORE_PCI_INIT 0x00010010 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_AFTER_PCI_INIT_Page SB_AFTER_PCI_INIT + * @section SB_AFTER_PCI_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_AFTER_PCI_INIT_CallIn Call Prototype + * @par + * sbAfterPciInit ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_AFTER_PCI_INIT_CallID Service ID + * @par + * + * + *
SB_AFTER_PCI_INIT --> 0x00010020
+ * @subsection SB_AFTER_PCI_INIT_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_AFTER_PCI_INIT_Config Prepare for Configuration Data. + * @par + * + * + * + * + * + * + * + * + * + * + * + * + *
SATAST::SataController Required
SATAST::SataIdeCombinedMode Required
AMDSBCFG::SataClass Required
AMDSBCFG::SataEspPort Required
AMDSBCFG::AzaliaController Required
AMDSBCFG::AzaliaPinCfg Required
AMDSBCFG::AzaliaSdinPin Required
BUILDPARAM::OhciSsid Optional
BUILDPARAM::Ohci4Ssid Optional
BUILDPARAM::EhciSsid Optional
BUILDPARAM::AzaliaSsid Optional
+ * + */ +#define SB_AFTER_PCI_INIT 0x00010020 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_MID_POST_INIT_Page SB_MID_POST_INIT + * @section SB_MID_POST_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_MID_POST_INIT_CallIn Call Prototype + * @par + * sbMidPostInit ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_MID_POST_INIT_CallID Service ID + * @par + * + * + *
SB_MID_POST_INIT --> 0x00010021
+ * @subsection SB_MID_POST_INIT_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_MID_POST_INIT_Config Prepare for Configuration Data. + * @par + * + * + * + *
SATAST::SataController Required
AMDSBCFG::SataClass Required
+ * + */ +#define SB_MID_POST_INIT 0x00010021 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_LATE_POST_INIT_Page SB_LATE_POST_INIT + * @section SB_LATE_POST_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_LATE_POST_INIT_CallIn Call Prototype + * @par + * sbLatePost ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_LATE_POST_INIT_CallID Service ID + * @par + * + * + *
SB_LATE_POST_INIT --> 0x00010030
+ * @subsection SB_LATE_POST_INIT_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_LATE_POST_INIT_Config Prepare for Configuration Data. + * @par + * + * + * + * + *
SATAST::SataController Required
SATAST::SataIdeCombinedMode Required
AMDSBCFG::SataClass Required
+ * + */ +#define SB_LATE_POST_INIT 0x00010030 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_BEFORE_PCI_RESTORE_INIT_Page SB_BEFORE_PCI_RESTORE_INIT + * @section SB_BEFORE_PCI_RESTORE_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallIn Call Prototype + * @par + * sbBeforePciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallID Service ID + * @par + * + * + *
SB_BEFORE_PCI_RESTORE_INIT --> 0x00010040
+ * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallOut Prepare for Callout + * @par + * + * + * + *
@ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"
@ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"
+ * @subsection SB_BEFORE_PCI_RESTORE_INIT_Config Prepare for Configuration Data. + * @par + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
SATAST::SataController Required
SATAST::SataIdeCombinedMode Required
AMDSBCFG::SataClass Required
AMDSBCFG::SataIdeMode Required
AMDSBCFG::USBDeviceConfig Required
AMDSBCFG::GecConfig Required
AMDSBCFG::AzaliaController Required
AMDSBCFG::PciClks Required
BUILDPARAM::SataIDESsid Optional
BUILDPARAM::SataRAID5Ssid Optional
BUILDPARAM::SataRAIDSsid Optional
BUILDPARAM::SataAHCISsid Optional
BUILDPARAM::SmbusSsid Optional
BUILDPARAM::LpcSsid Optional
BUILDPARAM::PCIBSsid Optional
+ * + */ +#define SB_BEFORE_PCI_RESTORE_INIT 0x00010040 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_AFTER_PCI_RESTORE_INIT_Page SB_AFTER_PCI_RESTORE_INIT + * @section SB_AFTER_PCI_RESTORE_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_AFTER_PCI_RESTORE_INIT_CallIn Call Prototype + * @par + * sbAfterPciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_AFTER_PCI_RESTORE_INIT_CallID Service ID + * @par + * + * + *
SB_AFTER_PCI_RESTORE_INIT --> 0x00010050
+ * @subsection SB_AFTER_PCI_RESTORE_INIT_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_AFTER_PCI_RESTORE_INIT_Config Prepare for Configuration Data. + * @par + * + * + * + * + * + * + * + * + * + * + * + * + *
SATAST::SataController Required
SATAST::SataIdeCombinedMode Required
AMDSBCFG::SataClass Required
AMDSBCFG::SataEspPort Required
AMDSBCFG::AzaliaController Required
AMDSBCFG::AzaliaPinCfg Required
AMDSBCFG::AzaliaSdinPin Required
BUILDPARAM::OhciSsid Optional
BUILDPARAM::Ohci4Ssid Optional
BUILDPARAM::EhciSsid Optional
BUILDPARAM::AzaliaSsid Optional
+ * + */ +#define SB_AFTER_PCI_RESTORE_INIT 0x00010050 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_SMM_SERVICE_Page SB_SMM_SERVICE + * @section SB_SMM_SERVICE Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_SMM_SERVICE_CallIn Call Prototype + * @par + * sbSmmService ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_SMM_SERVICE_CallID Service ID + * @par + * + * + *
SB_SMM_SERVICE --> 0x00010060
+ * @subsection SB_SMM_SERVICE_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_SMM_SERVICE_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define SB_SMM_SERVICE 0x00010060 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_SMM_ACPION_Page SB_SMM_ACPION + * @section SB_SMM_ACPION Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_SMM_ACPION_CallIn Call Prototype + * @par + * sbSmmAcpiOn ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_SMM_ACPION_CallID Service ID + * @par + * + * + *
SB_SMM_ACPION --> 0x00010061
+ * @subsection SB_SMM_ACPION_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_SMM_ACPION_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define SB_SMM_ACPION 0x00010061 +#define SB_EC_FANCONTROL 0x00010070 + +#ifndef OEM_CALLBACK_BASE + #define OEM_CALLBACK_BASE 0x00010100 +#endif + +//0x00 - 0x0F callback functions are reserved for bootblock +#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10 +#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT + * @section CB_SBGPP_RESET_ASSERT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID + * @par + * + * + *
CB_SBGPP_RESET_ASSERT --> 0x00010130
+ * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT + * @section CB_SBGPP_RESET_DEASSERT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID + * @par + * + * + *
CB_SBGPP_RESET_DEASSERT --> 0x00010131
+ * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31 + +#define IMC_FIRMWARE_FAIL OEM_CALLBACK_BASE + 0x40 + +#define CFG_ADDR_PORT 0xCF8 +#define CFG_DATA_PORT 0xCFC + +#define ALINK_ACCESS_INDEX 0x0CD8 +#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4 + +/*------------------------------------------------------------------ +; I/O Base Address - Should be set by host BIOS +;------------------------------------------------------------------ */ +#define DELAY_PORT 0x0E0 + +/*------------------------------------------------------------------ +; Fuse ID and minor ID of efuse bits +;------------------------------------------------------------------ */ +#define FUSE_ID_EFUSE_LOC 0x1F // efuse bits 248-255 +#define MINOR_ID_EFUSE_LOC 0x1E // efuse bits 240-247 +#define M1_D1_FUSE_ID 0x70 +#define M1_MINOR_ID 0x02 + +/*------------------------------------------------------------------ +; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display +;------------------------------------------------------------------ */ +// ASIC VendorID and DeviceIDs +#define AMD_SB_VID 0x1002 +#define SB_DEVICE_ID 0x4385 /* AMD ER SB800 */ +#define V_SB_SATA_VID AMD_SB_VID // dev 17 Func 0 +#define V_SB_SATA_DID 0x4390 +#define V_SB_SATA_AHCI_DID 0x4391 +#define V_SB_SATA_RAID_DID 0x4392 +#define V_SB_SATA_RAID5_DID 0x4393 +#define V_SB_USB_OHCI_VID AMD_SB_VID // dev 18 Func 0, dev 19 Func 0, dev 22 Func 0 +#define V_SB_USB_OHCI_DID 0x4397 +#define V_SB_USB_EHCI_VID AMD_SB_VID // dev 18 Func 2, dev 19 Func 2, dev 22 Func 2 +#define V_SB_USB_EHCI_DID 0x4396 +#define V_SB_SMBUS_VID AMD_SB_VID // dev 20 Func 0 +#define V_SB_SMBUS_DID 0x4385 +#define V_SB_IDE_VID AMD_SB_VID // dev 20 Func 1 +#define V_SB_IDE_DID 0x439C +#define V_SB_AZALIA_VID AMD_SB_VID // dev 20 Func 2 +#define V_SB_AZALIA_DID 0x4383 +#define V_SB_LPC_VID AMD_SB_VID // dev 20 Func 3 +#define V_SB_LPC_DID 0x439D +#define V_SB_PCIB_VID AMD_SB_VID // dev 20 Func 4 +#define V_SB_PCIB_DID 0x4384 +#define V_SB_USB_OHCIF_VID AMD_SB_VID // dev 20 Func 5 +#define V_SB_USB_OHCIF_DID 0x4399 +#define V_SB_NIC_VID 0x14E4 // dev 20 Func 6 +#define V_SB_NIC_DID 0x1699 + +//Misc +#define ACPI_SMI_CMD_PORT 0xB0 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define R_SB_PM_ACPI_PMA_CNT_BLK_LO 0x2C + +#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0) +#define SB_SATA1_BUS 0 +#define SB_SATA1_DEV 17 +#define SB_SATA1_FUNC 0 + +#define FC_BUS_DEV_FUN ((0x11 << 3) + 1) +#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4 +#define SB_OHCI1_BUS 0 +#define SB_OHCI1_DEV 18 +#define SB_OHCI1_FUNC 0 +#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9 +#define SB_OHCI2_BUS 0 +#define SB_OHCI2_DEV 19 +#define SB_OHCI2_FUNC 0 +#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13 +#define SB_OHCI3_BUS 0 +#define SB_OHCI3_DEV 22 +#define SB_OHCI3_FUNC 0 +#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4 +#define SB_EHCI1_BUS 0 +#define SB_EHCI1_DEV 18 +#define SB_EHCI1_FUNC 2 +#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9 +#define SB_EHCI2_BUS 0 +#define SB_EHCI2_DEV 19 +#define SB_EHCI2_FUNC 2 +#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13 +#define SB_EHCI3_BUS 0 +#define SB_EHCI3_DEV 22 +#define SB_EHCI3_FUNC 2 + +#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0) +#define SB_ISA_BUS 0 +#define SB_ISA_DEV 20 +#define SB_ISA_FUNC 0 +#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1) +#define SB_IDE_BUS 0 +#define SB_IDE_DEV 20 +#define SB_IDE_FUNC 1 +#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2) +#define SB_AZALIA_BUS 0 +#define SB_AZALIA_DEV 20 +#define SB_AZALIA_FUNC 2 +#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3) +#define SB_LPC_BUS 0 +#define SB_LPC_DEV 20 +#define SB_LPC_FUNC 3 +#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700 +#define SB_PCI_BUS 0 +#define SB_PCI_DEV 20 +#define SB_PCI_FUNC 4 +#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1 +#define SB_OHCI4_BUS 0 +#define SB_OHCI4_DEV 20 +#define SB_OHCI4_FUNC 5 +//Gigabyte Ethernet Controller +#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6) +#define SB_GBEC_BUS 0 +#define SB_GBEC_DEV 20 +#define SB_GBEC_FUNC 6 + +#define SB_GPP_BUS 0 +#define SB_GPP_DEV 21 +#define SB_GPP_FUNC 0 +#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0 +#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1 +#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2 +#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3 + +#define ACPI_MMIO_BASE 0xFED80000 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 + +#define GPP_EFUSE_LOCATION 0x14 // bit 160 +#define GPP_GEN2_EFUSE_BIT BIT0 + +// RegSpace field (AB_INDEX[31:29] +#define AXINDC 0 // AXINDC +#define AXINDP 2 // AXINDP +#define ABCFG 6 // ABCFG +#define AXCFG 4 // AXCFG +#define RCINDXC 1 // PCIEIND +#define RCINDXP 3 // PCIEIND_P + +#define SBTEMP_BUS 8 +#define GPP_DEV_NUM 21 //?? Code style different +#define MAX_GPP_PORTS 4 +#ifndef TRUE + #define TRUE 1 +#endif +#ifndef FALSE + #define FALSE 0 +#endif +// +// ABCFG Registers +// +#define SB_ABCFG_REG00 0x00 // VENDOR ID +#define SB_ABCFG_REG08 0x08 // REVISION ID +#define SB_ABCFG_REG40 0x40 // BL_EVENTCNT0LO +#define SB_ABCFG_REG44 0x44 // BL_EVENTCNT1LO +#define SB_ABCFG_REG48 0x48 // BL_EVENTCNTSEL +#define SB_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI +#define SB_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI +#define SB_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL +#define SB_ABCFG_REG50 0x50 // MISCCTL_50 +#define SB_ABCFG_REG54 0x54 // MISCCTL_54 +#define SB_ABCFG_REG58 0x58 // BL RAB CONTROL + +#define SB_ABCFG_REG60 0x60 // LINKWIDTH_CTL +#define SB_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL +#define SB_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL +#define SB_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS +#define SB_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS +#define SB_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE +#define SB_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE + +#define SB_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL +#define SB_ABCFG_REG88 0x88 // +#define SB_ABCFG_REG90 0x90 // BIF CONTROL 0 +#define SB_ABCFG_REG94 0x94 // MSI CONTROL +#define SB_ABCFG_REG98 0x98 // BIF CONTROL 1 +#define SB_ABCFG_REG9C 0x9C // MISCCTL_9C +#define SB_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE +#define SB_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4 +#define SB_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8 +#define SB_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING +#define SB_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE +#define SB_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP +#define SB_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA +#define SB_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL +#define SB_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA +#define SB_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS +#define SB_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL +#define SB_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL +#define SB_ABCFG_REGFC 0xFC // SB_TRAP_CONTROL +#define SB_ABCFG_REG100 0x100 // SB_TRAP0_ADDRL +#define SB_ABCFG_REG104 0x104 // SB_TRAP0_ADDRH +#define SB_ABCFG_REG108 0x108 // SB_TRAP0_CMD +#define SB_ABCFG_REG10C 0x10C // SB_TRAP1_DATA +#define SB_ABCFG_REG110 0x110 // SB_TRAP1_ADDRL +#define SB_ABCFG_REG114 0x114 // SB_TRAP1_ADDRH +#define SB_ABCFG_REG118 0x118 // SB_TRAP1_CMD +#define SB_ABCFG_REG11C 0x11C // SB_TRAP1_DATA +#define SB_ABCFG_REG120 0x120 // SB_TRAP2_ADDRL +#define SB_ABCFG_REG124 0x124 // SB_TRAP2_ADDRH +#define SB_ABCFG_REG128 0x128 // SB_TRAP2_CMD +#define SB_ABCFG_REG12C 0x12C // SB_TRAP2_DATA +#define SB_ABCFG_REG130 0x130 // SB_TRAP3_ADDRL +#define SB_ABCFG_REG134 0x134 // SB_TRAP3_ADDRH +#define SB_ABCFG_REG138 0x138 // SB_TRAP3_CMD +#define SB_ABCFG_REG13C 0x13C // SB_TRAP3_DATA +#define SB_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL +#define SB_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0 +#define SB_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1 +#define SB_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0 +#define SB_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A +#define SB_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B +#define SB_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C +#define SB_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D +#define SB_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0 +#define SB_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1 +#define SB_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2 +#define SB_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A +#define SB_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B +#define SB_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C +#define SB_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D +#define SB_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0 +#define SB_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1 +#define SB_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND +#define SB_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER +#define SB_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE +#define SB_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE +#define SB_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE +#define SB_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER +#define SB_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER +#define SB_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER +#define SB_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL +#define SB_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND +#define SB_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER +#define SB_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE +#define SB_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE +#define SB_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE +#define SB_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER +#define SB_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER +#define SB_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER +#define SB_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL +#define SB_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND +#define SB_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER +#define SB_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE +#define SB_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE +#define SB_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE +#define SB_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER +#define SB_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER +#define SB_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER +#define SB_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL +#define SB_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND +#define SB_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER +#define SB_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE +#define SB_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE +#define SB_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE +#define SB_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER +#define SB_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER +#define SB_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER +#define SB_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL +#define SB_ABCFG_REG10040 0x10040 // AL_EVENTCNT0LO +#define SB_ABCFG_REG10044 0x10044 // AL_EVENTCNT1LO +#define SB_ABCFG_REG10048 0x10048 // AL_EVENTCNTSEL +#define SB_ABCFG_REG1004A 0x1004A // AL_EVENTCNT0HI +#define SB_ABCFG_REG1004B 0x1004B // AL_EVENTCNT1HI +#define SB_ABCFG_REG1004C 0x1004C // AL_EVENTCNTCTL +#define SB_ABCFG_REG10050 0x10050 // MISCCTL_10050 +#define SB_ABCFG_REG10054 0x10054 // AL_ARB_CTL +#define SB_ABCFG_REG10056 0x10056 // AL_CLK_CTL +#define SB_ABCFG_REG10058 0x10058 // AL RAB CONTROL +#define SB_ABCFG_REG1005C 0x1005C // AL MLT CONTROL +#define SB_ABCFG_REG10060 0x10060 // AL DMA PREFETCH ENABLE +#define SB_ABCFG_REG10064 0x10064 // AL DMA PREFETCH FLUSH CONTROL +#define SB_ABCFG_REG10068 0x10068 // AL PREFETCH LIMIT +#define SB_ABCFG_REG1006C 0x1006C // AL DMA PREFETCH CONTROL +#define SB_ABCFG_REG10070 0x10070 // MISCCTL_10070 +#define SB_ABCFG_REG10080 0x10080 // CLKMUXSTATUS +#define SB_ABCFG_REG10090 0x10090 // BIF CONTROL 0 +#define SB_ABCFG_REG1009C 0x1009C // MISCCTL_1009C + +// +// RCINDX_P Registers +// +#define SB_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH +#define SB_RCINDXP_REG10 0x10 | RCINDXP << 29 // +#define SB_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL +#define SB_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS +#define SB_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL +#define SB_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL +#define SB_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL +#define SB_RCINDXP_REGA2 0xA2 | RCINDXP << 29 // +#define SB_RCINDXP_REGA4 0xA4 | RCINDXP << 29 // +#define SB_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0 +#define SB_RCINDXP_REGC0 0xC0 | RCINDXP << 29 // + +// +// RCINDX_C Registers +// +#define SB_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG +#define SB_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL +#define SB_RCINDXC_REGC1 0xC1 | RCINDXC << 29 // + +// +// AXINDC Registers +// +#define SB_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG +#define SB_AX_INDXC_REG10 0x10 +#define SB_AX_INDXC_REG30 0x30 +#define SB_AX_DATAC_REG34 0x34 +#define SB_AX_INDXP_REG38 0x38 +#define SB_AX_DATAP_REG3C 0x3C +#define SB_AX_INDXC_REG40 0x40 | AXINDC << 29 +#define SB_AX_INDXC_REGA4 0xA4 | AXINDC << 29 + +#define SB_AX_INDXP_REGA0 0xA0 | AXINDP << 29 +#define SB_AX_INDXP_REGA4 0xA4 | AXINDP << 29 +#define SB_AX_INDXP_REGB1 0xB1 | AXINDP << 29 + +#define SB_AX_CFG_REG88 0x88 | AXCFG << 29 + +#define AX_INDXC 0 +#define AX_INDXP 1 +#define SB_AB_REG04 0x04 +#define SB_AB_REG40 0x40 + +#define RC_INDXC_REG40 0x40 | RCINDXC << 29 +#define RC_INDXC_REG65 0x65 | RCINDXC << 29 + +// +// SATA Device 0x4390 (IDE) +// 0x4391 (AHCI) +// 0x4392 (AHCI/RAID Promise with RAID driver) +// 0x4393 (RAID5) +// 0x4394/0x4395 (SATA HyperFlash OneNand support/SATA HyperFlash-PCIe support) +// Device 17 (0x11) Func 0 +// +//Sata Controller Mode +#define NATIVE_IDE_MODE 0 +#define RAID_MODE 1 +#define AHCI_MODE 2 +#define LEGACY_IDE_MODE 3 +#define IDE_TO_AHCI_MODE 4 +#define AHCI_MODE_4394 5 +#define IDE_TO_AHCI_MODE_4394 6 + +//Sata Port Configuration +#define SIX_PORTS 0 +#define FOUR_PORTS 1 + +#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133 +#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169 +#define SATA_EFUSE_BIT 0x20 // +#define SB_SATA_REG00 0x000 // Vendor ID - R- 16 bits +#define SB_SATA_REG02 0x002 // Device ID - RW -16 bits +#define SB_SATA_REG04 0x004 // PCI Command - RW - 16 bits +#define SB_SATA_REG06 0x006 // PCI Status - RW - 16 bits +#define SB_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08 +#define SB_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits +#define SB_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits +#define SB_SATA_REG0E 0x00E // Header Type - R - 8 bits +#define SB_SATA_REG0F 0x00F // BIST - R - 8 bits +#define SB_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits +#define SB_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits +#define SB_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits +#define SB_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits +#define SB_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits +#define SB_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits +#define SB_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits +#define SB_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits +#define SB_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits +#define SB_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits +#define SB_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits +#define SB_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits +#define SB_SATA_REG3E 0x03E // Min Grant - R - 8 bits +#define SB_SATA_REG3F 0x03F // Max Latency - R - 8 bits +#define SB_SATA_REG40 0x040 // Configuration - RW - 32 bits +#define SB_SATA_REG44 0x044 // Software Data Register - RW - 32 bits +#define SB_SATA_REG48 0x048 +#define SB_SATA_REG50 0x050 // Message Capability - R - 16 bits +#define SB_SATA_REG52 0x052 // Message Control - R/W - 16 bits +#define SB_SATA_REG54 0x054 // Message Address - R/W - 32 bits +#define SB_SATA_REG58 0x058 // Message Data - R/W - 16 bits +#define SB_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits +#define SB_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits +#define SB_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits +#define SB_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits +#define SB_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits +#define SB_SATA_REG68 0x068 // MSI Program - R/W - 8 bits +#define SB_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits +#define SB_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits +#define SB_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits +#define SB_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits +#define SB_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits +#define SB_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits +#define SB_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits +#define SB_SATA_REG86 0x086 // PY Global Control +#define SB_SATA_REG87 0x087 +#define SB_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23) +#define SB_SATA_REG8A 0x08A +#define SB_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23) +#define SB_SATA_REG8E 0x08E +#define SB_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23) +#define SB_SATA_REG92 0x092 +#define SB_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23) +#define SB_SATA_REG96 0x096 +#define SB_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits +#define SB_SATA_REGA0 0x0A0 // +#define SB_SATA_REGA4 0x0A4 // +#define SB_SATA_REGA5 0x0A5 //; +#define SB_SATA_REGA8 0x0A8 // +#define SB_SATA_REGAD 0x0AD //; +#define SB_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_REGB5 0x0B5 //; +#define SB_SATA_REGBD 0x0BD //; +#define SB_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits +#define SB_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits + +#define SB_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits +#define SB_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits +#define SB_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits +#define SB_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits +#define SB_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits +#define SB_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits +#define SB_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits +#define SB_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits +#define SB_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits +#define SB_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits +#define SB_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits +#define SB_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits +#define SB_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits +#define SB_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits +#define SB_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits +#define SB_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REGF8 0x0F8 // PORT Configuration +#define SB_SATA_BAR5_REGFC 0x0FC +#define SB_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180 +#define SB_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel +#define SB_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel +#define SB_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel +#define SB_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits +#define SB_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)] +#define SB_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)] +#define SB_SATA_BAR5_REG120 0x0120 // +#define SB_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status +#define SB_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control +#define SB_SATA_BAR5_REG130 0x0130 +#define SB_SATA_BAR5_REG1B0 0x01B0 +#define SB_SATA_BAR5_REG230 0x0230 +#define SB_SATA_BAR5_REG2B0 0x02B0 +#define SB_SATA_BAR5_REG330 0x0330 +#define SB_SATA_BAR5_REG3B0 0x03B0 + +// +// FC Device 0x439B +// Device 17 (0x11) Func 1 +// +#define SB_FC_REG00 0x00 // Device/Vendor ID - R +#define SB_FC_REG04 0x04 // Command - RW +#define SB_FC_REG10 0x10 // BAR + +#define SB_FC_MMIO_REG70 0x070 +#define SB_FC_MMIO_REG200 0x200 + +// +// USB OHCI Device 0x4397 +// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0 +// Device 20 (0x14) Func 5 (FL) +// +#define SB_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002) +#define SB_OHCI_REG04 0x04 // Command - RW +#define SB_OHCI_REG06 0x06 // Status - R +#define SB_OHCI_REG08 0x08 // Revision ID/Class Code - R +#define SB_OHCI_REG0C 0x0C // Miscellaneous - RW +#define SB_OHCI_REG10 0x10 // Bar_OCI - RW +#define SB_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW +#define SB_OHCI_REG34 0x34 // Capability Pointer - R +#define SB_OHCI_REG3C 0x3C // Interrupt Line - RW +#define SB_OHCI_REG3D 0x3D // Interrupt Line - RW +#define SB_OHCI_REG40 0x40 // Config Timers - RW +#define SB_OHCI_REG42 0x42 // Port Disable Control - RW (800) +#define SB_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800) +#define SB_OHCI_REG48 0x48 // Port Force Reset - RW (800) +#define SB_OHCI_REG4C 0x4C // MSI - RW (800) +#define SB_OHCI_REG50 0x50 // Misc Control - RW +#define SB_OHCI_REG51 0x51 +#define SB_OHCI_REG52 0x52 +#define SB_OHCI_REG58 0x58 // Over Current Control - RW +#define SB_OHCI_REG5C 0x5C // Over Current Control - RW (800)?? +#define SB_OHCI_REG60 0x60 // Serial Bus Release Number - R (800)?? +#define SB_OHCI_REG68 0x68 // Over Current PME Enable - RW +#define SB_OHCI_REG74 0x74 // Target Timeout Control - RW (800) +#define SB_OHCI_REGD0 0x0D0 // MSI Control - RW +#define SB_OHCI_REGD4 0x0D4 // MSI Address - RW +#define SB_OHCI_REGD8 0x0D8 // MSI Data - RW +#define SB_OHCI_REGE4 0x0E4 // HT MSI Support +#define SB_OHCI_REGF0 0x0F0 // Function Level Reset Capability +#define SB_OHCI_REGF4 0x0F4 // Function Level Reset Control + +#define SB_OHCI_BAR_REG00 0x00 // cRevision - R +#define SB_OHCI_BAR_REG04 0x04 // cControl +#define SB_OHCI_BAR_REG08 0x08 // cCommandStatus +#define SB_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW +#define SB_OHCI_BAR_REG10 0x10 // cInterruptEnable +#define SB_OHCI_BAR_REG14 0x14 // cInterruptDisable +#define SB_OHCI_BAR_REG18 0x18 // HcCCA +#define SB_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED +#define SB_OHCI_BAR_REG20 0x20 // HcControleadED +#define SB_OHCI_BAR_REG24 0x24 // cControlCurrentED RW +#define SB_OHCI_BAR_REG28 0x28 // HcBulkeadED +#define SB_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW +#define SB_OHCI_BAR_REG30 0x30 // HcDoneead +#define SB_OHCI_BAR_REG34 0x34 // cFmInterval +#define SB_OHCI_BAR_REG38 0x38 // cFmRemaining +#define SB_OHCI_BAR_REG3C 0x3C // cFmNumber +#define SB_OHCI_BAR_REG40 0x40 // cPeriodicStart +#define SB_OHCI_BAR_REG44 0x44 // HcLSThresold +#define SB_OHCI_BAR_REG48 0x48 // HcRDescriptorA +#define SB_OHCI_BAR_REG4C 0x4C // HcRDescriptorB +#define SB_OHCI_BAR_REG50 0x50 // HcRStatus +#define SB_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800) +#define SB_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800) +#define SB_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800) + +// +// USB EHCI Device 0x4396 +// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2 +// +#define SB_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R +#define SB_EHCI_REG04 0x04 // Command - RW +#define SB_EHCI_REG06 0x06 // Status - R +#define SB_EHCI_REG08 0x08 // Revision ID/Class Code - R +#define SB_EHCI_REG0C 0x0C // Miscellaneous - RW +#define SB_EHCI_REG10 0x10 // BAR - RW +#define SB_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW +#define SB_EHCI_REG34 0x34 // Capability Pointer - R +#define SB_EHCI_REG3C 0x3C // Interrupt Line - RW +#define SB_EHCI_REG3D 0x3D // Interrupt Line - RW ?? +#define SB_EHCI_REG40 0x40 // Config Timers - RW ?? +#define SB_EHCI_REG4C 0x4C // MSI - RW +#define SB_EHCI_REG50 0x50 // EHCI Misc Control - RW +#define SB_EHCI_REG54 0x54 // EHCI Misc Control - RW +#define SB_EHCI_REG60 0x60 // SBRN - R +#define SB_EHCI_REG61 0x61 // FLADJ - RW +#define SB_EHCI_REG62 0x62 // PORTWAKECAP - RW +#define SB_EHCI_REGC0 0x0C0 // PME control - RW (800) +#define SB_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800) +#define SB_EHCI_REGD0 0x0D0 // MSI Control - RW +#define SB_EHCI_REGD4 0x0D4 // MSI Address - RW +#define SB_EHCI_REGD8 0x0D8 // MSI Data - RW +#define SB_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800) +#define SB_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800) +#define SB_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800) + +#define SB_EHCI_BAR_REG00 0x00 // CAPLENGT - R +#define SB_EHCI_BAR_REG02 0x002 // CIVERSION- R +#define SB_EHCI_BAR_REG04 0x004 // CSPARAMS - R +#define SB_EHCI_BAR_REG08 0x008 // CCPARAMS - R +#define SB_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R + +#define SB_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits +#define SB_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits +#define SB_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits +#define SB_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits +#define SB_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits +#define SB_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits +#define SB_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits +#define SB_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits +#define SB_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits +#define SB_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800) +#define SB_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits +#define SB_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R +#define SB_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R +#define SB_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R +#define SB_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800) +#define SB_EHCI_BAR_REGB8 0x0B8 // Loopback Test +#define SB_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control +#define SB_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration +#define SB_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control +#define SB_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose +#define SB_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) ** +#define SB_EHCI_BAR_REG100 0x100 // USB debug port + +// +// SB800 SB CFG device 0x4385 +// Device 20 (0x14) Func 0 +// +#define SB_CFG_REG00 0x000 // VendorID - R +#define SB_CFG_REG02 0x002 // DeviceID - R +#define SB_CFG_REG04 0x004 // Command- RW +#define SB_CFG_REG05 0x005 // Command- RW +#define SB_CFG_REG06 0x006 // STATUS- RW +#define SB_CFG_REG08 0x008 // Revision ID/Class Code- R +#define SB_CFG_REG0A 0x00A // +#define SB_CFG_REG0B 0x00B // +#define SB_CFG_REG0C 0x00C // Cache Line Size- R +#define SB_CFG_REG0D 0x00D // Latency Timer- R +#define SB_CFG_REG0E 0x00E // Header Type- R +#define SB_CFG_REG0F 0x00F // BIST- R +#define SB_CFG_REG10 0x010 // Base Address 0- R +#define SB_CFG_REG11 0x011 //; +#define SB_CFG_REG12 0x012 //; +#define SB_CFG_REG13 0x013 //; +#define SB_CFG_REG14 0x014 // Base Address 1- R +#define SB_CFG_REG18 0x018 // Base Address 2- R +#define SB_CFG_REG1C 0x01C // Base Address 3- R +#define SB_CFG_REG20 0x020 // Base Address 4- R +#define SB_CFG_REG24 0x024 // Base Address 5- R +#define SB_CFG_REG28 0x028 // Cardbus CIS Pointer- R +#define SB_CFG_REG2C 0x02C // Subsystem Vendor ID- W +#define SB_CFG_REG2E 0x02E // Subsystem ID- W +#define SB_CFG_REG30 0x030 // Expansion ROM Base Address - R +#define SB_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00 +#define SB_CFG_REG3C 0x03C // Interrupt Line - R +#define SB_CFG_REG3D 0x03D // Interrupt Pin - R +#define SB_CFG_REG3E 0x03E // Min_Gnt - R +#define SB_CFG_REG3F 0x03F // Max_Lat - R +#define SB_CFG_REG90 0x090 // Smbus Base Address - R +#define SB_CFG_REG9C 0x09C // SBResourceMMIO_BASE + +// +// SB800 SATA IDE device 0x439C +// Device 20 (0x14) Func 1 +// + +#define SB_IDE_REG00 0x00 // Vendor ID +#define SB_IDE_REG02 0x02 // Device ID +#define SB_IDE_REG04 0x04 // Command +#define SB_IDE_REG06 0x06 // Status +#define SB_IDE_REG08 0x08 // Revision ID/Class Code +#define SB_IDE_REG09 0x09 // Class Code +#define SB_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID +#define SB_IDE_REG34 0x34 +#define SB_IDE_REG40 0x40 // Configuration - RW - 32 bits +#define SB_IDE_REG62 0x62 // IDE Internal Control +#define SB_IDE_REG63 0x63 // IDE Internal Control +// +// SB800 AZALIA device 0x4383 +// Device 20 (0x14) Func 2 +// +#define ATI_AZALIA_ExtBlk_Addr 0x0F8 +#define ATI_AZALIA_ExtBlk_DATA 0x0FC + +#define SB_AZ_REG00 0x00 // Vendor ID - R +#define SB_AZ_REG02 0x02 // Device ID - R/W +#define SB_AZ_REG04 0x04 // PCI Command +#define SB_AZ_REG06 0x06 // PCI Status - R/W +#define SB_AZ_REG08 0x08 // Revision ID +#define SB_AZ_REG09 0x09 // Programming Interface +#define SB_AZ_REG0A 0x0A // Sub Class Code +#define SB_AZ_REG0B 0x0B // Base Class Code +#define SB_AZ_REG0C 0x0C // Cache Line Size - R/W +#define SB_AZ_REG0D 0x0D // Latency Timer +#define SB_AZ_REG0E 0x0E // Header Type +#define SB_AZ_REG0F 0x0F // BIST +#define SB_AZ_REG10 0x10 // Lower Base Address Register +#define SB_AZ_REG14 0x14 // Upper Base Address Register +#define SB_AZ_REG2C 0x2C // Subsystem Vendor ID +#define SB_AZ_REG2D 0x2D // Subsystem ID +#define SB_AZ_REG34 0x34 // Capabilities Pointer +#define SB_AZ_REG3C 0x3C // Interrupt Line +#define SB_AZ_REG3D 0x3D // Interrupt Pin +#define SB_AZ_REG3E 0x3E // Minimum Grant +#define SB_AZ_REG3F 0x3F // Maximum Latency +#define SB_AZ_REG40 0x40 // Misc Control 1 +#define SB_AZ_REG42 0x42 // Misc Control 2 Register +#define SB_AZ_REG43 0x43 // Misc Control 3 Register +#define SB_AZ_REG44 0x44 // Interrupt Pin Control Register +#define SB_AZ_REG46 0x46 // Debug Control Register +#define SB_AZ_REG4C 0x4C +#define SB_AZ_REG50 0x50 // Power Management Capability ID +#define SB_AZ_REG52 0x52 // Power Management Capabilities +#define SB_AZ_REG54 0x54 // Power Management Control/Status +#define SB_AZ_REG60 0x60 // MSI Capability ID +#define SB_AZ_REG62 0x62 // MSI Message Control +#define SB_AZ_REG64 0x64 // MSI Message Lower Address +#define SB_AZ_REG68 0x68 // MSI Message Upper Address +#define SB_AZ_REG6C 0x6C // MSI Message Data + +#define SB_AZ_BAR_REG00 0x00 // Global Capabilities - R +#define SB_AZ_BAR_REG02 0x02 // Minor Version - R +#define SB_AZ_BAR_REG03 0x03 // Major Version - R +#define SB_AZ_BAR_REG04 0x04 // Output Payload Capability - R +#define SB_AZ_BAR_REG06 0x06 // Input Payload Capability - R +#define SB_AZ_BAR_REG08 0x08 // Global Control - R/W +#define SB_AZ_BAR_REG0C 0x0C // Wake Enable - R/W +#define SB_AZ_BAR_REG0E 0x0E // State Change Status - R/W +#define SB_AZ_BAR_REG10 0x10 // Global Status - R/W +#define SB_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R +#define SB_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R +#define SB_AZ_BAR_REG20 0x20 // Interrupt Control - R/W +#define SB_AZ_BAR_REG24 0x24 // Interrupt Status - R/W +#define SB_AZ_BAR_REG30 0x30 // Wall Clock Counter - R +#define SB_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W +#define SB_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W +#define SB_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW +#define SB_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W +#define SB_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W +#define SB_AZ_BAR_REG4C 0x4C // CORB Control - R/W +#define SB_AZ_BAR_REG4D 0x4D // CORB Status - R/W +#define SB_AZ_BAR_REG4E 0x4E // CORB Size - R/W +#define SB_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW +#define SB_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW +#define SB_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW +#define SB_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W +#define SB_AZ_BAR_REG5C 0x5C // RIRB Control - R/W +#define SB_AZ_BAR_REG5D 0x5D // RIRB Status - R/W +#define SB_AZ_BAR_REG5E 0x5E // RIRB Size - R/W +#define SB_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W +#define SB_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W +#define SB_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W +#define SB_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W +#define SB_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W +#define SB_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R + +// +// SB800 LPC Device 0x439D +// Device 20 (0x14) Func 3 +// +#define SB_LPC_REG00 0x00 // VID- R +#define SB_LPC_REG02 0x02 // DID- R +#define SB_LPC_REG04 0x04 // CMD- RW +#define SB_LPC_REG06 0x06 // STATUS- RW +#define SB_LPC_REG08 0x08 // Revision ID/Class Code - R +#define SB_LPC_REG0C 0x0C // Cache Line Size - R +#define SB_LPC_REG0D 0x0D // Latency Timer - R +#define SB_LPC_REG0E 0x0E // Header Type - R +#define SB_LPC_REG0F 0x0F // BIST- R +#define SB_LPC_REG10 0x10 // Base Address Reg 0- RW* +#define SB_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro +#define SB_LPC_REG34 0x34 // Capabilities Pointer - Ro +#define SB_LPC_REG40 0x40 // PCI Control - RW +#define SB_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW +#define SB_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW +#define SB_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW +#define SB_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW +#define SB_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW +#define SB_LPC_REG49 0x49 // LPC Sync Timeout Count - RW +#define SB_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW +#define SB_LPC_REG4C 0x4C // Memory Range Register - RW +#define SB_LPC_REG50 0x50 // Rom Protect 0 - RW +#define SB_LPC_REG54 0x54 // Rom Protect 1 - RW +#define SB_LPC_REG58 0x58 // Rom Protect 2 - RW +#define SB_LPC_REG5C 0x5C // Rom Protect 3 - RW +#define SB_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles - +#define SB_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles - +#define SB_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW +#define SB_LPC_REG65 0x65 +#define SB_LPC_REG66 0x66 +#define SB_LPC_REG67 0x67 +#define SB_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW +#define SB_LPC_REG69 0x69 +#define SB_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW +#define SB_LPC_REG6B 0x6B +#define SB_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW +#define SB_LPC_REG6D 0x6D +#define SB_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW +#define SB_LPC_REG6F 0x6F +#define SB_LPC_REG70 0x70 // Firmware ub Select - RW* +#define SB_LPC_REG71 0x71 +#define SB_LPC_REG72 0x72 +#define SB_LPC_REG73 0x73 +#define SB_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R +#define SB_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R +#define SB_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R +#define SB_LPC_REG9C 0x9C +#define SB_LPC_REG80 0x80 // MSI Capability Register- R +#define SB_LPC_REGA0 0x0A0 // SPI base address +#define SB_LPC_REGA1 0x0A1 // SPI base address +#define SB_LPC_REGA2 0x0A2 // SPI base address +#define SB_LPC_REGA3 0x0A3 // SPI base address +#define SB_LPC_REGA4 0x0A4 +#define SB_LPC_REGBA 0x0BA // EcControl +#define SB_LPC_REGBB 0x0BB // HostControl + +// +// SB800 PCIB 0x4384 +// Device 20 (0x14) Func 4 +// +#define SB_PCIB_REG04 0x04 // Command +#define SB_PCIB_REG0D 0x0D // Primary Master Latency Timer +#define SB_PCIB_REG1B 0x1B // Secondary Latency Timer +#define SB_PCIB_REG1C 0x1C // IO Base +#define SB_PCIB_REG1D 0x1D // IO Limit +#define SB_PCIB_REG40 0x40 // CPCTRL +#define SB_PCIB_REG42 0x42 // CLKCTRL +#define SB_PCIB_REG48 0x48 // +#define SB_PCIB_REG4A 0x4A // PCICLK Enable Bits +#define SB_PCIB_REG4B 0x4B // Misc Control +#define SB_PCIB_REG4C 0x4C // AutoClockRun Control +#define SB_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override +#define SB_PCIB_REG65 0x65 // Misc Control +#define SB_PCIB_REG66 0x66 // Misc Control +// +// SB800 NIC 0x4384 +// Device 20 (0x14) Func 6 (Func5 OHCI FL device) +// +#define SB_GEC_REG04 0x04 // Command +#define SB_GEC_REG10 0x10 // GEC BAR + +// +// SB800 SB MMIO Base (SMI) +// offset : 0x200 +// +#define SB_SMI_REG00 0x00 // EventStatus +#define SB_SMI_REG04 0x04 // EventEnable +#define SB_SMI_REG08 0x08 // SciTrig +#define SB_SMI_REG0C 0x0C // SciLevl +#define SB_SMI_REG10 0x10 // SmiSciStatus +#define SB_SMI_REG14 0x14 // SmiSciEn +#define SB_SMI_REG18 0x18 // ForceSciEn +#define SB_SMI_REG1C 0x1C // SciRwData +#define SB_SMI_REG20 0x20 // SciS0En +#define SB_SMI_Gevent0 0x40 // SciMap0 +#define SB_SMI_Gevent1 0x41 // SciMap1 +#define SB_SMI_Gevent2 0x42 // SciMap2 +#define SB_SMI_Gevent3 0x43 // SciMap3 +#define SB_SMI_Gevent4 0x44 // SciMap4 +#define SB_SMI_Gevent5 0x45 // SciMap5 +#define SB_SMI_Gevent6 0x46 // SciMap6 +#define SB_SMI_Gevent7 0x47 // SciMap7 +#define SB_SMI_Gevent8 0x48 // SciMap8 +#define SB_SMI_Gevent9 0x49 // SciMap9 +#define SB_SMI_Gevent10 0x4A // SciMap10 +#define SB_SMI_Gevent11 0x4B // SciMap11 +#define SB_SMI_Gevent12 0x4C // SciMap12 +#define SB_SMI_Gevent13 0x4D // SciMap13 +#define SB_SMI_Gevent14 0x4E // SciMap14 +#define SB_SMI_Gevent15 0x4F // SciMap15 +#define SB_SMI_Gevent16 0x50 // SciMap16 +#define SB_SMI_Gevent17 0x51 // SciMap17 +#define SB_SMI_Gevent18 0x52 // SciMap18 +#define SB_SMI_Gevent19 0x53 // SciMap19 +#define SB_SMI_Gevent20 0x54 // SciMap20 +#define SB_SMI_Gevent21 0x55 // SciMap21 +#define SB_SMI_Gevent22 0x56 // SciMap22 +#define SB_SMI_Gevent23 0x57 // SciMap23 +#define SB_SMI_Usbwakup0 0x58 // SciMap24 +#define SB_SMI_Usbwakup1 0x59 // SciMap25 +#define SB_SMI_Usbwakup2 0x5A // SciMap26 +#define SB_SMI_Usbwakup3 0x5B // SciMap27 +#define SB_SMI_SBGppPme0 0x5C // SciMap28 +#define SB_SMI_SBGppPme1 0x5D // SciMap29 +#define SB_SMI_SBGppPme2 0x5E // SciMap30 +#define SB_SMI_SBGppPme3 0x5F // SciMap31 +#define SB_SMI_SBGppHp0 0x60 // SciMap32 +#define SB_SMI_SBGppHp1 0x61 // SciMap33 +#define SB_SMI_SBGppHp2 0x62 // SciMap34 +#define SB_SMI_SBGppHp3 0x63 // SciMap35 +#define SB_SMI_AzaliaPme 0x64 // SciMap36 +#define SB_SMI_SataGevent0 0x65 // SciMap37 +#define SB_SMI_SataGevent1 0x66 // SciMap38 +#define SB_SMI_GecPme 0x67 // SciMap39 +#define SB_SMI_IMCGevent0 0x68 // SciMap40 +#define SB_SMI_IMCGevent1 0x69 // SciMap41 +#define SB_SMI_CIRPme 0x6A // SciMap42 +#define SB_SMI_WakePinGevent 0x6B // SciMap43 +#define SB_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent +#define SB_SMI_ASFMasterIntr 0x6D // SciMap45 +#define SB_SMI_ASFSlaveIntr 0x6E // SciMap46 +#define SB_SMI_SMBUS0 0x6F // SciMap47 +#define SB_SMI_TWARN 0x70 // SciMap48 +#define SB_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr + +// Empty from 0x72-0x7F +//#Define SB_SMI_REG7C 0x7F // SciMap63 *** + +#define SB_SMI_REG80 0x80 // SmiStatus0 +#define SB_SMI_REG84 0x84 // SmiStatus1 +#define SB_SMI_REG88 0x88 // SmiStatus2 +#define SB_SMI_REG8C 0x8C // SmiStatus3 +#define SB_SMI_REG90 0x90 // SmiStatus4 +#define SB_SMI_REG94 0x94 // SmiPointer +#define SB_SMI_REG96 0x96 // SmiTimer +#define SB_SMI_REG98 0x98 // SmiTrig +#define SB_SMI_REG9C 0x9C // SmiTrig +#define SB_SMI_REGA0 0xA0 +#define SB_SMI_REGA1 0xA1 +#define SB_SMI_REGA2 0xA2 +#define SB_SMI_REGA3 0xA3 +#define SB_SMI_REGA4 0xA4 +#define SB_SMI_REGA5 0xA5 +#define SB_SMI_REGA6 0xA6 +#define SB_SMI_REGA7 0xA7 +#define SB_SMI_REGA8 0xA8 +#define SB_SMI_REGA9 0xA9 +#define SB_SMI_REGAA 0xAA +#define SB_SMI_REGAB 0xAB +#define SB_SMI_REGAC 0xAC +#define SB_SMI_REGAD 0xAD +#define SB_SMI_REGAE 0xAE +#define SB_SMI_REGAF 0xAF +#define SB_SMI_REGB0 0xB0 +#define SB_SMI_REGB1 0xB1 +#define SB_SMI_REGB2 0xB2 +#define SB_SMI_REGB3 0xB3 +#define SB_SMI_REGB4 0xB4 +#define SB_SMI_REGB5 0xB5 +#define SB_SMI_REGB6 0xB6 +#define SB_SMI_REGB7 0xB7 +#define SB_SMI_REGB8 0xB8 +#define SB_SMI_REGB9 0xB9 +#define SB_SMI_REGBA 0xBA +#define SB_SMI_REGBB 0xBB +#define SB_SMI_REGBC 0xBC +#define SB_SMI_REGBD 0xBD +#define SB_SMI_REGBE 0xBE +#define SB_SMI_REGBF 0xBF +#define SB_SMI_REGC0 0xC0 +#define SB_SMI_REGC1 0xC1 +#define SB_SMI_REGC2 0xC2 +#define SB_SMI_REGC3 0xC3 +#define SB_SMI_REGC4 0xC4 +#define SB_SMI_REGC5 0xC5 +#define SB_SMI_REGC6 0xC6 +#define SB_SMI_REGC7 0xC7 +#define SB_SMI_REGC8 0xC8 +#define SB_SMI_REGCA 0xCA // IoTrapping1 +#define SB_SMI_REGCC 0xCC // IoTrapping2 +#define SB_SMI_REGCE 0xCE // IoTrapping3 +#define SB_SMI_REGD0 0xD0 // MemTrapping0 +#define SB_SMI_REGD4 0xD4 // MemRdOvrData0 +#define SB_SMI_REGD8 0xD8 // MemTrapping1 +#define SB_SMI_REGDC 0xDC // MemRdOvrData1 +#define SB_SMI_REGE0 0xE0 // MemTrapping2 +#define SB_SMI_REGE4 0xE4 // MemRdOvrData2 +#define SB_SMI_REGE8 0xE8 // MemTrapping3 +#define SB_SMI_REGEC 0xEC // MemRdOvrData3 +#define SB_SMI_REGF0 0xF0 // CfgTrapping0 +#define SB_SMI_REGF4 0xF4 // CfgTrapping1 +#define SB_SMI_REGF8 0xF8 // CfgTrapping2 +#define SB_SMI_REGFC 0xFC // CfgTrapping3 + +// +// SB800 SB MMIO Base (PMIO) +// offset : 0x300 +// +#define SB_PMIOA_REG00 0x00 // ISA Decode +#define SB_PMIOA_REG04 0x04 // ISA Control +#define SB_PMIOA_REG08 0x08 // PCI Control +#define SB_PMIOA_REG0C 0x0C // StpClkSmaf +#define SB_PMIOA_REG10 0x10 // RetryDetect +#define SB_PMIOA_REG14 0x14 // StuckDetect +#define SB_PMIOA_REG20 0x20 // BiosRamEn +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define SB_PMIOA_REG28 0x28 // AsfEn +#define SB_PMIOA_REG2C 0x2C // Smbus0En +#define SB_PMIOA_REG34 0x34 // IoApicEn +#define SB_PMIOA_REG3C 0x3C // SmartVoltEn +#define SB_PMIOA_REG40 0x40 // SmartVolt2En +#define SB_PMIOA_REG44 0x44 // BootTimerEn +#define SB_PMIOA_REG48 0x48 // WatchDogTimerEn +#define SB_PMIOA_REG4C 0x4C // WatchDogTimerConfig +#define SB_PMIOA_REG50 0x50 // HPETEn +#define SB_PMIOA_REG54 0x54 // SerialIrqConfig +#define SB_PMIOA_REG56 0x56 // RtcControl +#define SB_PMIOA_REG58 0x58 // VRT_T1 +#define SB_PMIOA_REG59 0x59 // VRT_T2 +#define SB_PMIOA_REG5A 0x5A // IntruderControl +#define SB_PMIOA_REG5B 0x5B // RtcShadow +#define SB_PMIOA_REG5C 0x5C +#define SB_PMIOA_REG5D 0x5D +#define SB_PMIOA_REG5E 0x5E // RtcExtIndex +#define SB_PMIOA_REG5F 0x5F // RtcExtData +#define SB_PMIOA_REG60 0x60 // AcpiPm1EvtBlk +#define SB_PMIOA_REG62 0x62 // AcpiPm1CntBlk +#define SB_PMIOA_REG64 0x64 // AcpiPmTmrBlk +#define SB_PMIOA_REG66 0x66 // P_CNTBlk +#define SB_PMIOA_REG68 0x68 // AcpiGpe0Blk +#define SB_PMIOA_REG6A 0x6A // AcpiSmiCmd +#define SB_PMIOA_REG6C 0x6C // AcpiPm2CntBlk +#define SB_PMIOA_REG6E 0x6E // AcpiPmaCntBlk +#define SB_PMIOA_REG74 0x74 // AcpiConfig +#define SB_PMIOA_REG78 0x78 // WakeIoAddr +#define SB_PMIOA_REG7A 0x7A // HaltCountEn +#define SB_PMIOA_REG7C 0x7C // C1eWrPortAdr +#define SB_PMIOA_REG7E 0x7E // CStateEn +#define SB_PMIOA_REG80 0x80 // BreakEvent +#define SB_PMIOA_REG84 0x84 // AutoArbEn +#define SB_PMIOA_REG88 0x88 // CStateControl +#define SB_PMIOA_REG8C 0x8C // StpClkHoldTime +#define SB_PMIOA_REG8E 0x8E // PopUpEndTime +#define SB_PMIOA_REG90 0x90 // C4Control +#define SB_PMIOA_REG94 0x94 // CStateTiming0 +#define SB_PMIOA_REG98 0x98 // CStateTiming1 +#define SB_PMIOA_REG9C 0x9C // C2Count +#define SB_PMIOA_REG9D 0x9D // C3Count +#define SB_PMIOA_REG9E 0x9E // C4Count +#define SB_PMIOA_REGA0 0xA0 // MessageCState +#define SB_PMIOA_REGA4 0xA4 // +#define SB_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime +#define SB_PMIOA_REGAA 0xAA // TrafficMonitorIntTime +#define SB_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount +#define SB_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount +#define SB_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick +#define SB_PMIOA_REGB4 0xB4 // FidVidControl +#define SB_PMIOA_REGB6 0xB6 // TPRESET1 +#define SB_PMIOA_REGB7 0xB7 // Tpreset1b +#define SB_PMIOA_REGB8 0xB8 // TPRESET2 +#define SB_PMIOA_REGB9 0xB9 // Test0 +#define SB_PMIOA_REGBA 0xBA // S_StateControl +#define SB_PMIOA_REGBC 0xBC // ThrottlingControl +#define SB_PMIOA_REGBE 0xBE // ResetControl +#define SB_PMIOA_REGBF 0xBF // ResetControl +#define SB_PMIOA_REGC0 0xC0 // S5Status +#define SB_PMIOA_REGC2 0xC2 // ResetStatus +#define SB_PMIOA_REGC4 0xC4 // ResetCommand +#define SB_PMIOA_REGC5 0xC5 // CF9Shadow +#define SB_PMIOA_REGC6 0xC6 // HTControl +#define SB_PMIOA_REGC8 0xC8 // Misc +#define SB_PMIOA_REGCC 0xCC // IoDrvSth +#define SB_PMIOA_REGD0 0xD0 // CLKRunEn +#define SB_PMIOA_REGD2 0xD2 // PmioDebug +#define SB_PMIOA_REGD6 0xD6 // IMCGating +#define SB_PMIOA_REGD8 0xD8 // MiscIndex +#define SB_PMIOA_REGD9 0xD9 // MiscData +#define SB_PMIOA_REGDA 0xDA // SataConfig +#define SB_PMIOA_REGDC 0xDC // HyperFlashConfig +#define SB_PMIOA_REGDE 0xDE // ABConfig +#define SB_PMIOA_REGE0 0xE0 // ABRegBar +#define SB_PMIOA_REGE6 0xE6 // FcEn +#define SB_PMIOA_REGEA 0xEA // PcibConfig +#define SB_PMIOA_REGEB 0xEB // AzEn +#define SB_PMIOA_REGEC 0xEC // LpcGating +#define SB_PMIOA_REGED 0xED // UsbGating +#define SB_PMIOA_REGEF 0xEF // UsbEnable +#define SB_PMIOA_REGF0 0xF0 // UsbControl +#define SB_PMIOA_REGF3 0xF3 // UsbDebug +#define SB_PMIOA_REGF6 0xF6 // GecEn +#define SB_PMIOA_REGF8 0xF8 // GecConfig +#define SB_PMIOA_REGFC 0xFC // TraceMemoryEn + +// +// SB800 SB MMIO Base (PMIO2) +// offset : 0x400 +// +#define SB_PMIO2_REG00 0x00 // Fan0InputControl +#define SB_PMIO2_REG01 0x01 // Fan0Control +#define SB_PMIO2_REG02 0x02 // Fan0Freq +#define SB_PMIO2_REG03 0x03 // LowDuty0 +#define SB_PMIO2_REG04 0x04 // MidDuty0 + +#define SB_PMIO2_REG10 0x00 // Fan1InputControl +#define SB_PMIO2_REG11 0x01 // Fan1Control +#define SB_PMIO2_REG12 0x02 // Fan1Freq +#define SB_PMIO2_REG13 0x03 // LowDuty1 +#define SB_PMIO2_REG14 0x04 // MidDuty1 + +#define SB_PMIO2_REG 0xFC // TraceMemoryEn + + +// +// SB800 SB MMIO Base (GPIO/IoMux) +// offset : 0x100/0xD00 +// +/* +GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226. +*/ +#define SB_GPIO_REG00 0x00 +#define SB_GPIO_REG32 0x20 +#define SB_GPIO_REG33 0x21 +#define SB_GPIO_REG34 0x22 +#define SB_GPIO_REG35 0x23 +#define SB_GPIO_REG36 0x24 +#define SB_GPIO_REG37 0x25 +#define SB_GPIO_REG38 0x26 +#define SB_GPIO_REG39 0x27 +#define SB_GPIO_REG40 0x28 +#define SB_GPIO_REG41 0x29 +#define SB_GPIO_REG42 0x2A +#define SB_GPIO_REG43 0x2B +#define SB_GPIO_REG44 0x2C +#define SB_GPIO_REG45 0x2D +#define SB_GPIO_REG46 0x2E +#define SB_GPIO_REG47 0x2F +#define SB_GPIO_REG48 0x30 +#define SB_GPIO_REG49 0x31 +#define SB_GPIO_REG50 0x32 +#define SB_GPIO_REG51 0x33 +#define SB_GPIO_REG52 0x34 +#define SB_GPIO_REG53 0x35 +#define SB_GPIO_REG54 0x36 +#define SB_GPIO_REG55 0x37 +#define SB_GPIO_REG56 0x38 +#define SB_GPIO_REG57 0x39 +#define SB_GPIO_REG58 0x3A +#define SB_GPIO_REG59 0x3B +#define SB_GPIO_REG60 0x3C +#define SB_GPIO_REG61 0x3D +#define SB_GPIO_REG62 0x3E +#define SB_GPIO_REG63 0x3F +#define SB_GPIO_REG64 0x40 +#define SB_GPIO_REG65 0x41 +#define SB_GPIO_REG66 0x42 +#define SB_GPIO_REG67 0x43 + +#define SB_GEVENT_REG00 0x60 +#define SB_GEVENT_REG01 0x61 +#define SB_GEVENT_REG02 0x62 +#define SB_GEVENT_REG03 0x63 +#define SB_GEVENT_REG04 0x64 +#define SB_GEVENT_REG05 0x65 +#define SB_GEVENT_REG06 0x66 +#define SB_GEVENT_REG07 0x67 +#define SB_GEVENT_REG08 0x68 +#define SB_GEVENT_REG09 0x69 +#define SB_GEVENT_REG10 0x6A +#define SB_GEVENT_REG11 0x6B +#define SB_GEVENT_REG12 0x6C +#define SB_GEVENT_REG13 0x6D +#define SB_GEVENT_REG14 0x6E +#define SB_GEVENT_REG15 0x6F +#define SB_GEVENT_REG16 0x70 +#define SB_GEVENT_REG17 0x71 +#define SB_GEVENT_REG18 0x72 +#define SB_GEVENT_REG19 0x73 +#define SB_GEVENT_REG20 0x74 +#define SB_GEVENT_REG21 0x75 +#define SB_GEVENT_REG22 0x76 +#define SB_GEVENT_REG23 0x77 +// S5-DOMAIN GPIO +#define SB_GPIO_REG160 0xA0 +#define SB_GPIO_REG161 0xA1 +#define SB_GPIO_REG162 0xA2 +#define SB_GPIO_REG163 0xA3 +#define SB_GPIO_REG164 0xA4 +#define SB_GPIO_REG165 0xA5 +#define SB_GPIO_REG166 0xA6 +#define SB_GPIO_REG167 0xA7 +#define SB_GPIO_REG168 0xA8 +#define SB_GPIO_REG169 0xA9 +#define SB_GPIO_REG170 0xAA +#define SB_GPIO_REG171 0xAB +#define SB_GPIO_REG172 0xAC +#define SB_GPIO_REG173 0xAD +#define SB_GPIO_REG174 0xAE +#define SB_GPIO_REG175 0xAF +#define SB_GPIO_REG176 0xB0 +#define SB_GPIO_REG177 0xB1 +#define SB_GPIO_REG178 0xB2 +#define SB_GPIO_REG179 0xB3 +#define SB_GPIO_REG180 0xB4 +#define SB_GPIO_REG181 0xB5 +#define SB_GPIO_REG182 0xB6 +#define SB_GPIO_REG183 0xB7 +#define SB_GPIO_REG184 0xB8 +#define SB_GPIO_REG185 0xB9 +#define SB_GPIO_REG186 0xBA +#define SB_GPIO_REG187 0xBB +#define SB_GPIO_REG188 0xBC +#define SB_GPIO_REG189 0xBD +#define SB_GPIO_REG190 0xBE +#define SB_GPIO_REG191 0xBF +#define SB_GPIO_REG192 0xC0 +#define SB_GPIO_REG193 0xC1 +#define SB_GPIO_REG194 0xC2 +#define SB_GPIO_REG195 0xC3 +#define SB_GPIO_REG196 0xC4 +#define SB_GPIO_REG197 0xC5 +#define SB_GPIO_REG198 0xC6 +#define SB_GPIO_REG199 0xC7 +#define SB_GPIO_REG200 0xC8 +#define SB_GPIO_REG201 0xC9 +#define SB_GPIO_REG202 0xCA +#define SB_GPIO_REG203 0xCB +#define SB_GPIO_REG204 0xCC +#define SB_GPIO_REG205 0xCD +#define SB_GPIO_REG206 0xCE +#define SB_GPIO_REG207 0xCF +#define SB_GPIO_REG208 0xD0 +#define SB_GPIO_REG209 0xD1 +#define SB_GPIO_REG210 0xD2 +#define SB_GPIO_REG211 0xD3 +#define SB_GPIO_REG212 0xD4 +#define SB_GPIO_REG213 0xD5 +#define SB_GPIO_REG214 0xD6 +#define SB_GPIO_REG215 0xD7 +#define SB_GPIO_REG216 0xD8 +#define SB_GPIO_REG217 0xD9 +#define SB_GPIO_REG218 0xDA +#define SB_GPIO_REG219 0xDB +#define SB_GPIO_REG220 0xDC +#define SB_GPIO_REG221 0xDD +#define SB_GPIO_REG222 0xDE +#define SB_GPIO_REG223 0xDF +#define SB_GPIO_REG224 0xF0 +#define SB_GPIO_REG225 0xF1 +#define SB_GPIO_REG226 0xF2 +#define SB_GPIO_REG227 0xF3 +#define SB_GPIO_REG228 0xF4 + +// +// SB800 SB MMIO Base (SMBUS) +// offset : 0xA00 +// +#define SB_SMBUS_REG12 0x12 // I2CbusConfig + +// +// SB800 SB MMIO Base (MISC) +// offset : 0xE00 +// +#define SB_MISC_REG00 0x00 // ClkCntrl0 +/* +SB_MISC_REG00 EQU 000h + ClkCntrl0 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG04 0x04 // ClkCntrl1 +/* +SB_MISC_REG04 EQU 004h + ClkCntrl1 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG08 0x08 // ClkCntrl2 +/* +SB_MISC_REG08 EQU 008h + ClkCntrl2 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG0C 0x0C // ClkCntrl3 +/* +SB_MISC_REG0C EQU 00Ch + ClkCntrl3 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG10 0x10 // ClkCntrl4 +/* +SB_MISC_REG10 EQU 010h + ClkCntrl4 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG14 0x14 // ClkCntrl5 +/* +SB_MISC_REG14 EQU 014h + ClkCntrl5 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG18 0x18 // ClkCntrl6 +/* +SB_MISC_REG18 EQU 018h + ClkCntrl6 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG30 0x30 // OscFreqCounter +/* +SB_MISC_REG30 EQU 030h + OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second. +*/ +#define SB_MISC_REG34 0x34 // HpetClkPeriod +/* +SB_MISC_REG34 EQU 034h + HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M). +*/ +#define SB_MISC_REG40 0x40 // MiscCntrl for clock only +/* +SB_MISC_REG40 EQU 040h +*/ + +#define SB_MISC_REG80 0x80 /**< SB_MISC_REG80 + * @par + * StrapStatus [15.0] - SB800 chip Strap Status + * @li 0001 - Not USED FWH + * @li 0002 - Not USED LPC ROM + * @li 0004 - EC enabled + * @li 0008 - Reserved + * @li 0010 - Internal Clock mode + */ + +#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad +#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1) + // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type. +#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC) +#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function +#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock ** + +#define SB_MISC_REG84 0x84 // StrapOverride +/* +SB_MISC_REG84 EQU 084h + Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin. + Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin. + Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin. + Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin. + Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin. + Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin. + Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin. + Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin. + Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin. + Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin. + Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin' + PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin ?? Not match 0x80 reg ?? + BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin' + ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin. + BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin. + StrapOverrideEn EQU BIT31 ; Enable override strapping feature. +*/ +#define SB_MISC_REGC0 0xC0 // CPU_Pstate0 +/* +SB_MISC_REGC0 EQU 0C0h + Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7 + Core1_PState EQU BIT4+BIT5+BIT6 + Core2_PState EQU BIT8+BIT9+BIT10 + Core3_PState EQU BIT12+BIT13+BIT14 + Core4_PState EQU BIT16++BIT17+BIT18 + Core5_PState EQU BIT20+BIT21+BIT22 + Core6_PState EQU BIT24+BIT25+BIT26 + Core7_PState EQU BIT28+BIT29+BIT30 +*/ +#define SB_MISC_REGC4 0xC4 // CPU_Pstate1 +/* +SB_MISC_REGC4 EQU 0C4h + Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7 + Core9_PState EQU BIT4+BIT5+BIT6 + Core10_PState EQU BIT8+BIT9+BIT10 + Core11_PState EQU BIT12+BIT13+BIT14 + Core12_PState EQU BIT16++BIT17+BIT18 + Core13_PState EQU BIT20+BIT21+BIT22 + Core14_PState EQU BIT24+BIT25+BIT26 + Core15_PState EQU BIT28+BIT29+BIT30 +*/ +#define SB_MISC_REGD0 0xD0 // CPU_Cstate0 +/* +SB_MISC_REGD0 EQU 0D0h + Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7 + Core1_CState EQU BIT4+BIT5+BIT6 + Core2_CState EQU BIT8+BIT9+BIT10 + Core3_CState EQU BIT12+BIT13+BIT14 + Core4_CState EQU BIT16++BIT17+BIT18 + Core5_CState EQU BIT20+BIT21+BIT22 + Core6_CState EQU BIT24+BIT25+BIT26 + Core7_CState EQU BIT28+BIT29+BIT30 +*/ +#define SB_MISC_REGD4 0xD4 // CPU_Cstate1 +/* +SB_MISC_REGD4 EQU 0D4h + Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7 + Core9_CState EQU BIT4+BIT5+BIT6 + Core10_CState EQU BIT8+BIT9+BIT10 + Core11_CState EQU BIT12+BIT13+BIT14 + Core12_CState EQU BIT16++BIT17+BIT18 + Core13_CState EQU BIT20+BIT21+BIT22 + Core14_CState EQU BIT24+BIT25+BIT26 + Core15_CState EQU BIT28+BIT29+BIT30 +*/ +#define SB_MISC_REGF0 0xF0 // SataPortSts ?? EC touch only +/* +SB_MISC_REGF0 EQU 0F0h + Port0Sts EQU BIT0 ; The selected status of Port 0. + Port1Sts EQU BIT1 ; The selected status of Port 1 + Port2Sts EQU BIT2 ; The selected status of Port 2. + Port3Sts EQU BIT3 ; The selected status of Port 3 + Port4Sts EQU BIT4 ; The selected status of Port 4. + Port5Sts EQU BIT5 ; The selected status of Port 5 + SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5 + ; 01 - Select "delete" for Port 0 to 5 + ; 10 - Select "err" for Port 0 to 5 + ; 11 - Select "led" for Port 0 to 5 +*/ + + + +#define SB_RTC_REG00 0x00 // Seconds - RW +#define SB_RTC_REG01 0x01 // Seconds Alarm - RW +#define SB_RTC_REG02 0x02 // Minutes - RW +#define SB_RTC_REG03 0x03 // Minutes Alarm - RW +#define SB_RTC_REG04 0x04 // ours - RW +#define SB_RTC_REG05 0x05 // ours Alarm- RW +#define SB_RTC_REG06 0x06 // Day of Week - RW +#define SB_RTC_REG07 0x07 // Date of Mont - RW +#define SB_RTC_REG08 0x08 // Mont - RW +#define SB_RTC_REG09 0x09 // Year - RW +#define SB_RTC_REG0A 0x0A // Register A - RW +#define SB_RTC_REG0B 0x0B // Register B - RW +#define SB_RTC_REG0C 0x0C // Register C - R +#define SB_RTC_REG0D 0x0D // DateAlarm - RW +#define SB_RTC_REG32 0x32 // AltCentury - RW +#define SB_RTC_REG48 0x48 // Century - RW +#define SB_RTC_REG50 0x50 // Extended RAM Address Port - RW +#define SB_RTC_REG53 0x53 // Extended RAM Data Port - RW +#define SB_RTC_REG7E 0x7E // RTC Time Clear - RW +#define SB_RTC_REG7F 0x7F // RTC RAM Enable - RW + +#define SB_ECMOS_REG00 0x00 // scratch - reg +//;BIT0=0 AsicDebug is enabled +//;BIT1=0 SLT S3 runs +#define SB_ECMOS_REG01 0x01 +#define SB_ECMOS_REG02 0x02 +#define SB_ECMOS_REG03 0x03 +#define SB_ECMOS_REG04 0x04 +#define SB_ECMOS_REG05 0x05 +#define SB_ECMOS_REG06 0x06 +#define SB_ECMOS_REG07 0x07 +#define SB_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure +#define SB_ECMOS_REG09 0x09 +#define SB_ECMOS_REG0A 0x0A +#define SB_ECMOS_REG0B 0x0B + +#define SB_ECMOS_REG0C 0x0C //;save MODULE_ID +#define SB_ECMOS_REG0D 0x0D //;Reserve for NB + +#define SB_IOMAP_REG00 0x000 // Dma_C 0 +#define SB_IOMAP_REG02 0x002 // Dma_C 1 +#define SB_IOMAP_REG04 0x004 // Dma_C 2 +#define SB_IOMAP_REG06 0x006 // Dma_C 3 +#define SB_IOMAP_REG08 0x008 // Dma_Status +#define SB_IOMAP_REG09 0x009 // Dma_WriteRest +#define SB_IOMAP_REG0A 0x00A // Dma_WriteMask +#define SB_IOMAP_REG0B 0x00B // Dma_WriteMode +#define SB_IOMAP_REG0C 0x00C // Dma_Clear +#define SB_IOMAP_REG0D 0x00D // Dma_MasterClr +#define SB_IOMAP_REG0E 0x00E // Dma_ClrMask +#define SB_IOMAP_REG0F 0x00F // Dma_AllMask +#define SB_IOMAP_REG20 0x020 // IntrCntrlReg1 +#define SB_IOMAP_REG21 0x021 // IntrCntrlReg2 +#define SB_IOMAP_REG40 0x040 // TimerC0 +#define SB_IOMAP_REG41 0x041 // TimerC1 +#define SB_IOMAP_REG42 0x042 // TimerC2 +#define SB_IOMAP_REG43 0x043 // Tmr1CntrlWord +#define SB_IOMAP_REG61 0x061 // Nmi_Status +#define SB_IOMAP_REG70 0x070 // Nmi_Enable +#define SB_IOMAP_REG71 0x071 // RtcDataPort +#define SB_IOMAP_REG72 0x072 // AlternatRtcAddrPort +#define SB_IOMAP_REG73 0x073 // AlternatRtcDataPort +#define SB_IOMAP_REG80 0x080 // Dma_Page_Reserved0 +#define SB_IOMAP_REG81 0x081 // Dma_PageC2 +#define SB_IOMAP_REG82 0x082 // Dma_PageC3 +#define SB_IOMAP_REG83 0x083 // Dma_PageC1 +#define SB_IOMAP_REG84 0x084 // Dma_Page_Reserved1 +#define SB_IOMAP_REG85 0x085 // Dma_Page_Reserved2 +#define SB_IOMAP_REG86 0x086 // Dma_Page_Reserved3 +#define SB_IOMAP_REG87 0x087 // Dma_PageC0 +#define SB_IOMAP_REG88 0x088 // Dma_Page_Reserved4 +#define SB_IOMAP_REG89 0x089 // Dma_PageC6 +#define SB_IOMAP_REG8A 0x08A // Dma_PageC7 +#define SB_IOMAP_REG8B 0x08B // Dma_PageC5 +#define SB_IOMAP_REG8C 0x08C // Dma_Page_Reserved5 +#define SB_IOMAP_REG8D 0x08D // Dma_Page_Reserved6 +#define SB_IOMAP_REG8E 0x08E // Dma_Page_Reserved7 +#define SB_IOMAP_REG8F 0x08F // Dma_Refres +#define SB_IOMAP_REG92 0x092 // FastInit +#define SB_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1 +#define SB_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2 +#define SB_IOMAP_REGC0 0x0C0 // Dma2_C4Addr +#define SB_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt +#define SB_IOMAP_REGC4 0x0C4 // Dma2_C5Addr +#define SB_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt +#define SB_IOMAP_REGC8 0x0C8 // Dma2_C6Addr +#define SB_IOMAP_REGCA 0x0CA // Dma2_C6Cnt +#define SB_IOMAP_REGCC 0x0CC // Dma2_C7Addr +#define SB_IOMAP_REGCE 0x0CE // Dma2_C7Cnt +#define SB_IOMAP_REGD0 0x0D0 // Dma_Status +#define SB_IOMAP_REGD2 0x0D2 // Dma_WriteRest +#define SB_IOMAP_REGD4 0x0D4 // Dma_WriteMask +#define SB_IOMAP_REGD6 0x0D6 // Dma_WriteMode +#define SB_IOMAP_REGD8 0x0D8 // Dma_Clear +#define SB_IOMAP_REGDA 0x0DA // Dma_Clear +#define SB_IOMAP_REGDC 0x0DC // Dma_ClrMask +#define SB_IOMAP_REGDE 0x0DE // Dma_ClrMask +#define SB_IOMAP_REGF0 0x0F0 // NCP_Error +#define SB_IOMAP_REG40B 0x040B // DMA1_Extend +#define SB_IOMAP_REG4D0 0x04D0 // IntrEdgeControl +#define SB_IOMAP_REG4D6 0x04D6 // DMA2_Extend +#define SB_IOMAP_REGC00 0x0C00 // Pci_Intr_Index +#define SB_IOMAP_REGC01 0x0C01 // Pci_Intr_Data +#define SB_IOMAP_REGC14 0x0C14 // Pci_Error +#define SB_IOMAP_REGC50 0x0C50 // CMIndex +#define SB_IOMAP_REGC51 0x0C51 // CMData +#define SB_IOMAP_REGC52 0x0C52 // GpmPort +#define SB_IOMAP_REGC6F 0x0C6F // Isa_Misc +#define SB_IOMAP_REGCD0 0x0CD0 // PMio2_Index +#define SB_IOMAP_REGCD1 0x0CD1 // PMio2_Data +#define SB_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index +#define SB_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data +#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index +#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data +#define SB_IOMAP_REGCF9 0x0CF9 // CF9Rst reg + + +#define SB_SPI_MMIO_REG00 0x00 //SPI_ +#define SB_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register + +#define AMD_NB_REG78 0x78 +#define AMD_NB_SCRATCH AMD_NB_REG78 +#define MailBoxPort 0x3E + +// GPP Link Configuration +#define GPP_CFGMODE_X4000 0x0 +#define GPP_CFGMODE_X2200 0x2 +#define GPP_CFGMODE_X2110 0x3 +#define GPP_CFGMODE_X1111 0x4 + +#define MAX_TRAINING_RETRY 0x4000 +#define MAX_GPP_RESETS 8 //lx-temp to confirm with jason + + +#pragma pack (pop) + Added: trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,1058 @@ +/** + * @file + * + * Southbridge Initial routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" +// +// Declaration of local functions +// + +VOID abcfgTbl (IN ABTBLENTRY* pABTbl); + +/** + * sbUsbPhySetting - USB Phy Calibration Adjustment + * + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * + */ +VOID sbUsbPhySetting (IN UINT32 Value); + + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page LegacyInterfaceCalls Legacy Interface Calls + * @subpage SB_POWERON_INIT_Page "SB_POWERON_INIT" + * @subpage SB_BEFORE_PCI_INIT_Page "SB_BEFORE_PCI_INIT" + * @subpage SB_AFTER_PCI_INIT_Page "SB_AFTER_PCI_INIT" + * @subpage SB_LATE_POST_INIT_Page "SB_LATE_POST_INIT" + * @subpage SB_BEFORE_PCI_RESTORE_INIT_Page "SB_BEFORE_PCI_RESTORE_INIT" + * @subpage SB_AFTER_PCI_RESTORE_INIT_Page "SB_AFTER_PCI_RESTORE_INIT" + * @subpage SB_SMM_SERVICE_Page "SB_SMM_SERVICE" + * @subpage SB_SMM_ACPION_Page "SB_SMM_ACPION" + * + * @page LegacyInterfaceCallOuts Legacy Interface CallOuts + * @subpage CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT + * @subpage CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT + * +*/ + +/** + * sbEarlyPostByteInitTable - PCI device registers initial during early POST. + * + */ +REG8MASK sbEarlyPostByteInitTable[] = +{ + // SMBUS Device (Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_CFG_REG10, 0X00, (SBCIMx_Version & 0xFF)}, //Program the version information + {SB_CFG_REG11, 0X00, (SBCIMx_Version >> 8)}, + {0xFF, 0xFF, 0xFF}, + + // IDE Device (Bus 0, Dev 20, Func 1) + {0x00, IDE_BUS_DEV_FUN, 0}, + {SB_IDE_REG62 + 1, ~BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0 + // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1 + {0xFF, 0xFF, 0xFF}, + + // Azalia Device (Bus 0, Dev 20, Func 2) + {0x00, AZALIA_BUS_DEV_FUN, 0}, + {SB_AZ_REG4C, ~BIT0, BIT0}, + {0xFF, 0xFF, 0xFF}, + + // LPC Device (Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REG40, ~BIT2, BIT2}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b + {SB_LPC_REG78, ~BIT0, 00}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b + {SB_LPC_REG78, ~BIT1, 00}, // Disables MSI capability + {SB_LPC_REGBB, ~BIT0, BIT0 + BIT3 + BIT4 + BIT5}, // Enabled SPI Prefetch from HOST. + {0xFF, 0xFF, 0xFF}, + + // PCIB Bridge (Bus 0, Dev 20, Func 4) + {0x00, PCIB_BUS_DEV_FUN, 0}, + {SB_PCIB_REG40, 0xFF, BIT5}, // RPR PCI-bridge Subtractive Decode + {SB_PCIB_REG4B, 0xFF, BIT7}, // + {SB_PCIB_REG66, 0xFF, BIT4}, // RPR Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20] + {SB_PCIB_REG65, 0xFF, BIT7}, // RPR proper operation of CLKRUN#. + {SB_PCIB_REG0D, 0x00, 0x40}, // Setting Latency Timers to 0x40, Enables the PCIB to retain ownership + {SB_PCIB_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted. + {SB_PCIB_REG66 + 1, 0xFF, BIT1}, // RPR Enable PCI bus GNT3#.. + {0xFF, 0xFF, 0xFF}, + + // SATA Device (Bus 0, Dev 17, Func 0) + {0x00, SATA_BUS_DEV_FUN, 0}, + {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post + {SB_SATA_REG44 + 2, 0, 0x20}, // RPR 8.12 SATA PCI Watchdog timer setting + // [SB01923] Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue. + {0xFF, 0xFF, 0xFF}, +}; + + +/** + * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST. + * + */ +AcpiRegWrite sbPmioEPostInitTable[] = +{ + // HPET workaround + {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, BIT7}, + {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, 0x00}, + // End of HPET workaround + // Enable SB800 A12 ACPI bits at PMIO 0xC0 [30,10:3] + // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time. + // UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time. + // ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood. + // MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event. + // IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled. + // GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit. + // PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state. + // UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled. + // Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support. + {PMIO_BASE >> 8, SB_PMIOA_REGC4, ~(BIT2 + BIT4), BIT2 + BIT4}, + {PMIO_BASE >> 8, SB_PMIOA_REGC0, 0, 0xF9}, + // PM_reg xC1 [3] = 1b, per RPR 2.7 CPU PwrGood Setting + {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 1, 0x04, 0x0B}, + // RtcSts 19-17 RTC_STS set only in Sleep State. + // GppPme 20 Set to 1 to enable PME request from SB GPP. + // Pcireset 22 Set to 1 to allow SW to reset PCIe. + {PMIO_BASE >> 8, SB_PMIOA_REGC2, 0x20, 0x58}, + {PMIO_BASE >> 8, SB_PMIOA_REGC2 + 1, 0, 0x40}, + + //Item Id: SB02037: RTC_STS should be set in S state + //set PMIO 0xC0 [19:16] Set to 1110 to allow RTC_STS to be set only in non_G0 state. + //{PMIO_BASE >> 8, SB_PMIOA_REGC2, (UINT8)~(0x0F), 0x0E}, + + //Item Id: SB02034 + //Title: SB GPP NIC auto wake at second time sleep + //set PMIO 0xC4 bit 2 to 1 then set PMIO 0xC0 bit 20 to 1 to enable fix for SB02034 + + {PMIO_BASE >> 8, SB_PMIOA_REGC2, ~(BIT4), BIT4}, + + //{GPIO_BASE >> 8, SB_GPIO_REG62 , 0x00, 0x4E}, + {PMIO_BASE >> 8, SB_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4}, + {PMIO_BASE >> 8, SB_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REGDE, ~BIT4, BIT4}, + {PMIO_BASE >> 8, SB_PMIOA_REGBA, ~BIT3, BIT3}, + {PMIO_BASE >> 8, SB_PMIOA_REGBA + 1, ~BIT6, BIT6}, + {PMIO_BASE >> 8, SB_PMIOA_REGBC, ~BIT1, BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REGED, ~(BIT0 + BIT1), 0}, + //RPR Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01 + {PMIO_BASE >> 8, SB_PMIOA_REGDC, 0x7C, BIT0}, + // RPR Turning off FC clock + {MISC_BASE >> 8, SB_MISC_REG40 + 1, ~(BIT3 + BIT2), BIT3 + BIT2}, + {MISC_BASE >> 8, SB_MISC_REG40 + 2, ~BIT0, BIT0}, + {SMI_BASE >> 8, SB_SMI_Gevent0, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent1, 0, 1}, + {SMI_BASE >> 8, SB_SMI_Gevent2, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent3, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent4, 0, 4}, + {SMI_BASE >> 8, SB_SMI_Gevent5, 0, 5}, + {SMI_BASE >> 8, SB_SMI_Gevent6, 0, 6}, + {SMI_BASE >> 8, SB_SMI_Gevent7, 0, 29}, + + {SMI_BASE >> 8, SB_SMI_Gevent9, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent10, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent11, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent12, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent13, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent14, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent15, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent16, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent17, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent18, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent19, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent20, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent21, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent22, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent23, 0, 29}, +// + {SMI_BASE >> 8, SB_SMI_Usbwakup0, 0, 11}, + {SMI_BASE >> 8, SB_SMI_Usbwakup1, 0, 11}, + {SMI_BASE >> 8, SB_SMI_Usbwakup2, 0, 11}, + {SMI_BASE >> 8, SB_SMI_Usbwakup3, 0, 11}, + {SMI_BASE >> 8, SB_SMI_IMCGevent0, 0, 12}, + {SMI_BASE >> 8, SB_SMI_IMCGevent1, 0, 29}, + {SMI_BASE >> 8, SB_SMI_FanThGevent, 0, 13}, + {SMI_BASE >> 8, SB_SMI_SBGppPme0, 0, 15}, + {SMI_BASE >> 8, SB_SMI_SBGppPme1, 0, 16}, + {SMI_BASE >> 8, SB_SMI_SBGppPme2, 0, 17}, + {SMI_BASE >> 8, SB_SMI_SBGppPme3, 0, 18}, + {SMI_BASE >> 8, SB_SMI_SBGppHp0, 0, 29}, + {SMI_BASE >> 8, SB_SMI_SBGppHp1, 0, 29}, + {SMI_BASE >> 8, SB_SMI_SBGppHp2, 0, 29}, + {SMI_BASE >> 8, SB_SMI_SBGppHp3, 0, 29}, + {SMI_BASE >> 8, SB_SMI_GecPme, 0, 19}, + {SMI_BASE >> 8, SB_SMI_CIRPme, 0, 23}, + {SMI_BASE >> 8, SB_SMI_Gevent8, 0, 26}, + {SMI_BASE >> 8, SB_SMI_AzaliaPme, 0, 27}, + {SMI_BASE >> 8, SB_SMI_SataGevent0, 0, 30}, + {SMI_BASE >> 8, SB_SMI_SataGevent1, 0, 31}, + + {SMI_BASE >> 8, SB_SMI_WakePinGevent, 0, 29}, + {SMI_BASE >> 8, SB_SMI_ASFMasterIntr, 0, 29}, + {SMI_BASE >> 8, SB_SMI_ASFSlaveIntr, 0, 29}, + +// {SMI_BASE >> 8, SB_SMI_REG04, ~BIT4, BIT4}, +// {SMI_BASE >> 8, SB_SMI_REG04 + 1, ~BIT0, BIT0}, +// {SMI_BASE >> 8, SB_SMI_REG04 + 2, ~BIT3, BIT3}, + {SMI_BASE >> 8, SB_SMI_REG08, ~BIT4, 0}, + {SMI_BASE >> 8, SB_SMI_REG08+3, ~BIT2, 0}, +// {SMI_BASE >> 8, SB_SMI_REG0C, ~BIT4, BIT4}, + {SMI_BASE >> 8, SB_SMI_REG0C + 2, ~BIT3, BIT3}, + {SMI_BASE >> 8, SB_SMI_TWARN, 0, 9}, + {SMI_BASE >> 8, SB_SMI_TMI, 0, 29}, + {0xFF, 0xFF, 0xFF, 0xFF}, +}; + +/** + * abTblEntry800 - AB-Link Configuration Table for SB800 + * + */ +ABTBLENTRY abTblEntry800[] = +{ + // RPR Enable downstream posted transactions to pass non-posted transactions. + {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16}, + + // RPR Enable SB800 to issue memory read/write requests in the upstream direction. + {AXCFG, SB_AB_REG04, BIT2, BIT2}, + + // RPR Enabling IDE/PCIB Prefetch for Performance Enhancement + // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1 + {ABCFG, SB_ABCFG_REG10060, BIT20, BIT20}, // PCIB prefetch enable + {ABCFG, SB_ABCFG_REG10064, BIT20, BIT20}, // PCIB prefetch enable + + // RPR Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices. + // RPR Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11) + {ABCFG, SB_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18}, + + // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21] + // RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17] + {ABCFG, SB_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17}, + + // RPR Disable the credit variable in the downstream arbitration equation + // RPR Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set) + {ABCFG, SB_ABCFG_REG9C, BIT0, BIT0}, + + // RPR Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1 + // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20] + {ABCFG, SB_ABCFG_REG94, BIT20, BIT20 + 0x00FEE}, + + // RPR Programming cycle delay for AB and BIF clock gating + // RPR Enable the AB and BIF clock-gating logic. + // RPR Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently + // RPR Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP + {ABCFG, SB_ABCFG_REG10054, 0x00FFFFFF, 0x010407FF}, + {ABCFG, SB_ABCFG_REG98, 0xFFFF00FF, 0x00034700}, + {ABCFG, SB_ABCFG_REG54, 0x00FF0000, 0x00040000}, + // RPR Non-Posted Memory Write Support + {AX_INDXC, SB_AX_INDXC_REG10, BIT9, BIT9}, + {ABCFG, 0, 0, (UINT8) 0xFF}, // This dummy entry is to clear ab index + { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, +}; + +/** + * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature + * + */ +ABTBLENTRY SbPcieOrderRule[] = +{ +// abPostPassNpDownStreamTbl + {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31}, + {ABCFG, SB_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5}, + {ABCFG, SB_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7}, + {ABCFG, SB_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23}, + {ABCFG, SB_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5}, + {AXINDC, SB_AX_INDXC_REG02, BIT9, BIT9}, + {ABCFG, SB_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12}, +// abPostPassNpUpStreamTbl + {ABCFG, SB_ABCFG_REG58, BIT10, BIT10}, + {ABCFG, SB_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4}, + {ABCFG, SB_ABCFG_REG54, BIT1, BIT1}, + { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, +}; + +/** + * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. + * + * This settings should be done during S3 resume also + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +commonInitEarlyBoot ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 abValue; + UINT16 dwTempVar; + SB_CPUID_DATA CpuId; + UINT8 cimNativepciesupport; + UINT8 cimIrConfig; + UINT8 Data; + + cimNativepciesupport = (UINT8) pConfig->NativePcieSupport; + cimIrConfig = (UINT8) pConfig->IrConfig; +#if SB_CIMx_PARAMETER == 0 + cimNativepciesupport = cimNativepciesupportDefault; + cimIrConfig = cimIrConfigDefault; +#endif + + //IR init Logical device 0x05 + if ( cimIrConfig ) { + // Enable EC_PortActive + RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0); + EnterEcConfig (); + RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller + RWEC8 (0x60, 0x00, 0x05); //Set Base Address to 550h + RWEC8 (0x61, 0x00, 0x50); + RWEC8 (0x70, 0xF0, 0x05); //Set IRQ to 05h + RWEC8 (0x30, 0x00, 0x01); //Enable logical device 5, IR controller + Data = 0xAB; + WriteIO (0x550, AccWidthUint8, &Data); + ReadIO (0x551, AccWidthUint8, &Data); + Data = ((Data & 0xFC ) | cimIrConfig); + WriteIO (0x551, AccWidthUint8, &Data); + ExitEcConfig (); + Data = 0xA0; // EC APIC index + WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data); + Data = 0x05; // IRQ5 + WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data); + } else { + EnterEcConfig (); + RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller + RWEC8 (0x30, 0x00, 0x00); //Disable logical device 5, IR controller + ExitEcConfig (); + } + + + CpuidRead (0x01, &CpuId); + + // + // SB CFG programming + // + //Make BAR registers of smbus visible. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); + //Early post initialization of pci config space + programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); + if ( pConfig->BuildParameters.SmbusSsid != NULL ) { + RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); + } + //Make BAR registers of smbus invisible. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6); + + // + // LPC CFG programming + // + // SSID for LPC Controller + if (pConfig->BuildParameters.LpcSsid != NULL ) { + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid); + } + // LPC MSI + if ( pConfig->BuildParameters.LpcMsi) { + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG78, AccWidthUint32 | S3_SAVE, ~BIT1, BIT1); + } + + // + // PCIB CFG programming + // + //Disable or Enable PCI Clks based on input + RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG42, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2), ((pConfig->PciClks) & 0x0F) << 2 ); + RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4A, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), (pConfig->PciClks) >> 4 ); + // PCIB MSI + if ( pConfig->BuildParameters.PcibMsi) { + RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG40, AccWidthUint8 | S3_SAVE, ~BIT3, BIT3); + } + + // + // AB CFG programming + // + // Read Arbiter address, Arbiter address is in PMIO 6Ch + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, &dwTempVar); + RWIO (dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter + + abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers + // AB MSI + if ( pConfig->BuildParameters.AbMsi) { + abValue = readAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29)); + abValue = abValue | BIT20; + writeAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29), abValue); + } + + + // + // SB Specific Function programming + // + + // PCIE Native setting + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBA + 1, AccWidthUint8, ~BIT14, 0); + if ( pConfig->NativePcieSupport == 1) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2 + BIT0); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2); + } + +#ifdef ACPI_SLEEP_TRAP + // Set SLP_TYPE as SMI event + RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB0, AccWidthUint8, ~(BIT2 + BIT3), BIT2); + // Disabled SLP function for S1/S3/S4/S5 + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~BIT5, 0x00); + // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1) + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG08 + 3, AccWidthUint8, ~(BIT0 + BIT1), BIT1); + // Enabled Global Smi ( BIT7 clear as 0 to enable ) + RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG98 + 3 , AccWidthUint8, ~BIT7, 0x00); +#endif + if ( pConfig->SbUsbPll == 0) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20); + } + // Set Stutter timer settings + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8, ~(BIT3 + BIT4), BIT3 + BIT4); + // Set LDTSTP# duration to 10us for HydraD CPU, or when HT link is 200MHz + if ((pConfig->AnyHT200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x0A); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x28); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x20); + } + + //PM_Reg 0x7A[15] (CountHaltMsgEn) should be set when C1e option is enabled + //PM_Reg 0x7A[3:0] (NumOfCpu) should be set to 1h when C1e option is enabled + //PM_Reg 0x80[13] has to set to 1 to enable Message C scheme. + if (pConfig->MTC1e) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, 0x7FF0, BIT15 + 1); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5); + } + + programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); +} + +/** + * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +abSpecialSetBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 abValue; + abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + abValue &= 0xf0; + if ( pConfig->SbPcieOrderRule && abValue ) { + abValue = readAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)); + abValue = abValue | BIT9; + writeAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), abValue); + } +} + +VOID +usbDesertPll ( + IN AMDSBCFG* pConfig + ) +{ + if ( pConfig->SbUsbPll == 0) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00); + } +} + +/** + * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. + * + * This settings might not program during S3 resume + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +commonInitEarlyPost ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 dbPortStatus; + UINT8 cimSpreadSpectrum; + UINT32 cimSpreadSpectrumType; + AMDSBCFG* pTmp; + pTmp = pConfig; + + cimSpreadSpectrum = pConfig->SpreadSpectrum; + cimSpreadSpectrumType = pConfig->BuildParameters.SpreadSpectrumType; +#if SB_CIMx_PARAMETER == 0 + cimSpreadSpectrum = cimSpreadSpectrumDefault; + cimSpreadSpectrumType = cimSpreadSpectrumTypeDefault; +#endif + programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioEPostInitTable[0])); + + // CallBackToOEM (PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig); + + if ( cimSpreadSpectrum ) { + // Misc_Reg_40[25]=1 -> allow to change spread profile + // Misc_Reg19=83 -> new spread profile + // Misc_Reg[12:10]=9975be + // Misc_Reg0B=91 + // Misc_Reg09=21 + // Misc_Misc_Reg_08[0]=1 -> enable spread + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x43, AccWidthUint8, ~BIT1, BIT1); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x19, AccWidthUint8, 0, 0x83); + getChipSysMode (&dbPortStatus); + if ( ((dbPortStatus & ChipSysIntClkGen) != ChipSysIntClkGen) ) { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1A, AccWidthUint8, ~(BIT5 + BIT6 + BIT7), 0x80); + } + + if ( cimSpreadSpectrumType == 0 ) { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x99); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x75); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xBE); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x91); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21); + } else { // Spread profile for Ontario CPU related platform + // This spread profile setting is for Ontario HDMI & DVI output from DP with -0.425% + // Misc_Reg[12:10]=828FA8 + // Misc_Reg0B=11 + // Misc_Reg09=21 + // Misc_Reg10[25:24]=01b + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x82); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x8F); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xA8); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x11); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccWidthUint8, 0xFC, 0x1); + } + + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x01); + } else { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00); + } + + // RPR PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode + getChipSysMode (&dbPortStatus); + if ( ((dbPortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04 + 1, AccWidthUint8, ~BIT5, BIT5); + } + + // Set ASF SMBUS master function enabled here (temporary) + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16 | S3_SAVE, ~(BIT0 + BIT2), BIT0 + BIT2); + + programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); +#ifndef NO_EC_SUPPORT + // Software IMC enable + if (((pConfig->BuildParameters.ImcEnableOverWrite == 1) && ((dbPortStatus & ChipSysEcEnable) == 0)) || ((pConfig->BuildParameters.ImcEnableOverWrite == 2) && ((dbPortStatus & ChipSysEcEnable) == ChipSysEcEnable))) { + if (validateImcFirmware (pConfig)) { + softwareToggleImcStrapping (pConfig); + } else { + CallBackToOEM (IMC_FIRMWARE_FAIL, 0, pConfig); + } + } +#endif + +} +/** + * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +abLinkInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 cimResetCpuOnSyncFlood; + ABTBLENTRY *pAbTblPtr; + AMDSBCFG* Temp; + + cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood; +#if SB_CIMx_PARAMETER == 0 + cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault; +#endif + Temp = pConfig; + if ( pConfig->SbPcieOrderRule ) { + pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]); + abcfgTbl (pAbTblPtr); + } + pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]); + abcfgTbl (pAbTblPtr); + if ( cimResetCpuOnSyncFlood ) { + rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2); + } +} + +/** + * abcfgTbl - Program ABCFG by input table. + * + * + * @param[in] pABTbl ABCFG config table. + * + */ +VOID +abcfgTbl ( + IN ABTBLENTRY* pABTbl + ) +{ + UINT32 ddValue; + + while ( (pABTbl->regType) != 0xFF ) { + if ( pABTbl->regType > AXINDC ) { + ddValue = pABTbl->regIndex | (pABTbl->regType << 29); + writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData); + } else { + ddValue = 0x30 | (pABTbl->regType << 29); + writeAlink (ddValue, pABTbl->regIndex); + ddValue = 0x34 | (pABTbl->regType << 29); + writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData); + } + ++pABTbl; + } + + //Clear ALink Access Index + ddValue = 0; + WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue); +} + +/** + * commonInitLateBoot - Prepare Southbridge register setting to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +commonInitLateBoot ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 dbValue; + UINT32 ddVar; + // We need to do the following setting in late post also because some bios core pci enumeration changes these values + // programmed during early post. + // RPR 4.5 Master Latency Timer + + dbValue = 0x40; + WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG0D, AccWidthUint8, &dbValue); + WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG1B, AccWidthUint8, &dbValue); + + //SB P2P AutoClock control settings. + ddVar = (pConfig->PcibAutoClkCtrlHigh << 16) | (pConfig->PcibAutoClkCtrlLow); + WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4C, AccWidthUint32, &ddVar); + ddVar = (pConfig->PcibClkStopOverride); + RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6)); + + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, 0xBF | S3_SAVE, BIT3 + BIT4 + BIT5); + + // USB Phy Calibration Adjustment + ddVar = (USB1_EHCI_BUS_DEV_FUN << 16); + sbUsbPhySetting (ddVar); + ddVar = (USB2_EHCI_BUS_DEV_FUN << 16); + sbUsbPhySetting (ddVar); + ddVar = (USB3_EHCI_BUS_DEV_FUN << 16); + sbUsbPhySetting (ddVar); + + c3PopupSetting (pConfig); + FusionRelatedSetting (pConfig); +} + +/** + * sbUsbPhySetting - USB Phy Calibration Adjustment + * + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * + */ +VOID +sbUsbPhySetting ( + IN UINT32 Value + ) +{ + UINT32 ddBarAddress; + UINT32 ddPhyStatus03; + UINT32 ddPhyStatus4; + UINT8 dbRevId; + //Get BAR address + ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress); + if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { + ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGA8, AccWidthUint32, &ddPhyStatus03); + ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGAC, AccWidthUint32, &ddPhyStatus4); + ddPhyStatus03 &= 0x07070707; + ddPhyStatus4 &= 0x00000007; + if ( (ddPhyStatus03 != 0x00) | (ddPhyStatus4 != 0x00) ) { + // RPR 7.7 USB 2.0 Ports Driving Strength step 1 + //Make BAR registers of smbus visible. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); + ReadPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08, AccWidthUint8, &dbRevId); + //Make BAR registers of smbus invisible. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6); + if (dbRevId == 0x41) { // A12 + RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x1500); + RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0); + } else if (dbRevId == 0x42) { // A13 + RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x0F00); + RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0x0100); + } + } + } +} + +/** + * hpetInit - Program Southbridge HPET function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] pStaticOptions Platform build configuration table. + * + */ +VOID +hpetInit ( + IN AMDSBCFG* pConfig, + IN BUILDPARAM *pStaticOptions + ) +{ + DESCRIPTION_HEADER* pHpetTable; + UINT8 cimHpetTimer; + UINT8 cimHpetMsiDis; + + cimHpetTimer = (UINT8) pConfig->HpetTimer; + cimHpetMsiDis = (UINT8) pConfig->HpetMsiDis; +#if SB_CIMx_PARAMETER == 0 + cimHpetTimer = cimHpetTimerDefault; + cimHpetMsiDis = cimHpetMsiDisDefault; +#endif + pHpetTable = NULL; + if ( cimHpetTimer == TRUE ) { + //Program the HPET BAR address + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, pStaticOptions->HpetBase); + //Enabling decoding of HPET MMIO + //Enable HPET MSI support + //Enable High Precision Event Timer (also called Multimedia Timer) interrupt + if ( cimHpetMsiDis == FALSE ) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1 + BIT2 + BIT3 + BIT4); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1); + } + + } else { + if ( ! (pConfig->S3Resume) ) { + //pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable ('TEPH'); //gcc multi-character character constant warning + pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (0x54455048);//'TEPH' + } + if ( pHpetTable != NULL ) { + //pHpetTable->Signature = 'HPET'; + pHpetTable->Signature = 0x48504554; //'HPET' + } + } +} + +/** + * c3PopupSetting - Program Southbridge C state function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +c3PopupSetting ( + IN AMDSBCFG* pConfig + ) +{ + AMDSBCFG* Temp; + UINT8 dbValue; + Temp = pConfig; + //RPR C-State and VID/FID Change + dbValue = getNumberOfCpuCores (); + if (dbValue > 1) { + //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated. + //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD + //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert + //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT2), (BIT1 + BIT2)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6); + } + //SB800 needs to changed for RD790 support + //PM 0x80 [8] = 0 for system with RS780 + //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link. + //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle. + //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F); + //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that + //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also + //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT + //link is disconnected. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94 + 2, AccWidthUint8, 0, 0x10); + + //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The + //delay will allow USB DMA to go on in a continuous manner + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 1, AccWidthUint8, 0, 0x10); + // Not in the RPR so far, it's hand writing from ASIC + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C, AccWidthUint8 | S3_SAVE, 0, 0x85); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C + 1, AccWidthUint8 | S3_SAVE, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E + 1, AccWidthUint8 | S3_SAVE, ~(BIT7 + BIT5), BIT7 + BIT5); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4); + // RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x10); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, 0, 0x10); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4 + 1, AccWidthUint8, 0, 0x0B); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, 0xFF, BIT4); + if (pConfig->LdtStpDisable) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~BIT5, 0); + } +} + +/** + * FusionRelatedSetting - Program Fusion C related function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +FusionRelatedSetting ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 cimAcDcMsg; + UINT8 cimTimerTickTrack; + UINT8 cimClockInterruptTag; + UINT8 cimOhciTrafficHanding; + UINT8 cimEhciTrafficHanding; + UINT8 cimFusionMsgCMultiCore; + UINT8 cimFusionMsgCStage; + UINT32 ddValue; + + cimAcDcMsg = (UINT8) pConfig->AcDcMsg; + cimTimerTickTrack = (UINT8) pConfig->TimerTickTrack; + cimClockInterruptTag = (UINT8) pConfig->ClockInterruptTag; + cimOhciTrafficHanding = (UINT8) pConfig->OhciTrafficHanding; + cimEhciTrafficHanding = (UINT8) pConfig->EhciTrafficHanding; + cimFusionMsgCMultiCore = (UINT8) pConfig->FusionMsgCMultiCore; + cimFusionMsgCStage = (UINT8) pConfig->FusionMsgCStage; +#if SB_CIMx_PARAMETER == 0 + cimAcDcMsg = cimAcDcMsgDefault; + cimTimerTickTrack = cimTimerTickTrackDefault; + cimClockInterruptTag = cimClockInterruptTagDefault; + cimOhciTrafficHanding = cimOhciTrafficHandingDefault; + cimEhciTrafficHanding = cimEhciTrafficHandingDefault; + cimFusionMsgCMultiCore = cimFusionMsgCMultiCoreDefault; + cimFusionMsgCStage = cimFusionMsgCStageDefault; +#endif + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue); + ddValue = ddValue & 0xC07F00A0; + if ( cimAcDcMsg ) { + ddValue = ddValue | BIT0; + } + if ( cimTimerTickTrack ) { + ddValue = ddValue | BIT1; + } + if ( cimClockInterruptTag ) { + ddValue = ddValue | BIT10; + } + if ( cimOhciTrafficHanding ) { + ddValue = ddValue | BIT13; + } + if ( cimEhciTrafficHanding ) { + ddValue = ddValue | BIT15; + } + if ( cimFusionMsgCMultiCore ) { + ddValue = ddValue | BIT23; + } + if ( cimFusionMsgCStage ) { + ddValue = (ddValue | (BIT6 + BIT4 + BIT3 + BIT2)); + } + WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue); +} +#ifndef NO_EC_SUPPORT +/** + * validateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + * @retval TRUE Pass + * @retval FALSE Failed + */ +BOOLEAN +validateImcFirmware ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ImcSig; + UINT32 ImcSigAddr; + UINT32 ImcAddr; + UINT32 CurAddr; + UINT32 ImcBinSig0; + UINT32 ImcBinSig1; + UINT16 ImcBinSig2; + UINT8 dbIMCChecksume; + UINT8 dbIMC; + ImcAddr = 0; + + // Software IMC enable + ImcSigAddr = 0x80000; // start from 512k to 64M + ImcSig = 0x0; // + while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) { + CurAddr = 0xffffffff - ImcSigAddr + 0x20001; + ReadMEM (CurAddr, AccWidthUint32, &ImcSig); + ReadMEM ((CurAddr + 4), AccWidthUint32, &ImcAddr); + ImcSigAddr <<= 1; + } + + dbIMCChecksume = 0xff; + if ( ImcSig == 0x55aa55aa ) { + // "_AMD_IMC_C" at offset 0x2000 of the binary + ReadMEM ((ImcAddr + 0x2000), AccWidthUint32, &ImcBinSig0); + ReadMEM ((ImcAddr + 0x2004), AccWidthUint32, &ImcBinSig1); + ReadMEM ((ImcAddr + 0x2008), AccWidthUint16, &ImcBinSig2); + if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) { + dbIMCChecksume = 0; + for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) { + ReadMEM (CurAddr, AccWidthUint8, &dbIMC); + dbIMCChecksume = dbIMCChecksume + dbIMC; + } + } + } + if ( dbIMCChecksume ) { + return FALSE; + } else { + return TRUE; + } +} + +/** + * softwareToggleImcStrapping - Software Toggle IMC Firmware Strapping. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +softwareToggleImcStrapping ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 dbValue; + UINT8 dbPortStatus; + UINT32 abValue; + UINT32 abValue1; + + getChipSysMode (&dbPortStatus); + + ReadPMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue); + //if ( (dbValue & (BIT6 + BIT7)) != 0xC0 ) { // PwrGoodOut =1, PwrGoodEnB=1 + //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference. + + //StrapStatus StrapOverride + // bit4 bit17 + // bit6 bit12 + // bit12 bit15 + // bit15 bit16 + // bit16 bit18 + ReadMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80), AccWidthUint32, &abValue); + abValue1 = abValue; + if (abValue & BIT4) { + abValue1 = (abValue1 & ~BIT4) | BIT17; + } + if (abValue & BIT6) { + abValue1 = (abValue1 & ~BIT6) | BIT12; + } + if (abValue & BIT12) { + abValue1 = (abValue1 & ~BIT12) | BIT15; + } + if (abValue & BIT15) { + abValue1 = (abValue1 & ~BIT15) | BIT16; + } + if (abValue & BIT16) { + abValue1 = (abValue1 & ~BIT16) | BIT18; + } + abValue1 |= BIT31; // Overwrite enable + if ((dbPortStatus & ChipSysEcEnable) == 0) { + abValue1 |= BIT2; // bit2- EcEnableStrap + } else { + abValue1 &= ~BIT2; // bit2=0 EcEnableStrap + } + WriteMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG84), AccWidthUint32, &abValue1); + dbValue |= BIT6; // PwrGoodOut =1 + dbValue &= ~BIT7; // PwrGoodEnB =0 + WritePMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue); + + dbValue = 06; + WriteIO (0xcf9, AccWidthUint8, &dbValue); + SbStall (0xffffffff); +} +#endif + +#ifndef NO_HWM_SUPPORT +/** + * validateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +hwmInit ( + IN AMDSBCFG* pConfig + ) +{ + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccWidthUint8 | S3_SAVE, 0, 0x55); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccWidthUint8 | S3_SAVE, 0, 0x55); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccWidthUint8 | S3_SAVE, 0, 0x55); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccWidthUint8 | S3_SAVE, 0, 0x55); + + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccWidthUint8 | S3_SAVE, 0, 0x06); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccWidthUint8 | S3_SAVE, 0, 0x06); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccWidthUint8 | S3_SAVE, 0, 0x06); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccWidthUint8 | S3_SAVE, 0, 0x06); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccWidthUint8 | S3_SAVE, 0, 0x06); + + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccWidthUint8 | S3_SAVE, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccWidthUint8 | S3_SAVE, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccWidthUint8 | S3_SAVE, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccWidthUint8 | S3_SAVE, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccWidthUint8 | S3_SAVE, 0, 0x01); + + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccWidthUint8 | S3_SAVE, 0, 0x05); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccWidthUint8 | S3_SAVE, 0, 0x06); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccWidthUint8 | S3_SAVE, 0, 0x42); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccWidthUint8 | S3_SAVE, 0, 0xFF); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccWidthUint8 | S3_SAVE, 0, 0x1F); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccWidthUint8 | S3_SAVE, 0, 0x04); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccWidthUint8 | S3_SAVE, 0, 0x00); +} +#endif Added: trunk/src/vendorcode/amd/cimx/sb800/SBDEF.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBDEF.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,252 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +//AMD Library Routines (AMDLIB.C) +UINT8 getNumberOfCpuCores (OUT VOID); +UINT32 readAlink (IN UINT32 Index); +VOID writeAlink (IN UINT32 Index, IN UINT32 Data); +VOID rwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask); + +//AMD Library Routines (LEGACY.C) +UINT32 GetFixUp (OUT VOID); + +//AMD Library Routines (IOLIB.C) +VOID ReadIO (IN UINT16 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID WriteIO (IN UINT16 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID RWIO (IN UINT16 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); + + + +//AMD Library Routines (MEMLIB.C) +VOID ReadMEM (IN UINT32 Address, IN UINT8 OpFlag, IN VOID* Value); +VOID WriteMEM (IN UINT32 Address, IN UINT8 OpFlag, IN VOID* Value); +VOID RWMEM (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); + +//AMD Library Routines (PCILIB.C) +VOID ReadPCI (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID WritePCI (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID RWPCI (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); + +//AMD Library Routines (SBPELIB.C) +/** + * Read Southbridge Revision ID cie Base + * + * + * @retval 0xXXXXXXXX Revision ID + * + */ +UINT8 getRevisionID (OUT VOID); + +/** + * programPciByteTable - Program PCI register by table (8 bits data) + * + * + * + * @param[in] pPciByteTable - Table data pointer + * @param[in] dwTableSize - Table length + * + */ +VOID programPciByteTable (IN REG8MASK* pPciByteTable, IN UINT16 dwTableSize); + +/** + * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data) + * + * + * + * @param[in] pAcpiTbl - Table data pointer + * + */ +VOID programSbAcpiMmioTbl (IN AcpiRegWrite *pAcpiTbl); + +/** + * getChipSysMode - Get Chip status + * + * + * @param[in] Value - Return Chip strap status + * StrapStatus [15.0] - SB800 chip Strap Status + * @li 0001 - Not USED FWH + * @li 0002 - Not USED LPC ROM + * @li 0004 - EC enabled + * @li 0008 - Reserved + * @li 0010 - Internal Clock mode + * + */ +VOID getChipSysMode (IN VOID* Value); + +/** + * Read Southbridge CIMx configuration structure pointer + * + * + * + * @retval 0xXXXXXXXX CIMx configuration structure pointer. + * + */ +AMDSBCFG* getConfigPointer (OUT VOID); + +//AMD Library Routines (PMIOLIB.C) +/** + * Read PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * + */ +VOID ReadPMIO (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * + */ +VOID WritePMIO (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * RWPMIO - Read/Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * + */ +VOID RWPMIO (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask); + +//AMD Library Routines (PMIO2LIB.C) + +/** + * Read PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * + */ +VOID ReadPMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * Write PMIO 2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * + */ +VOID WritePMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * RWPMIO2 - Read/Write PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * + */ +VOID RWPMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask); +//AMD Library Routines (ECLIB.C) +// ECLIB Routines + +// #ifndef NO_EC_SUPPORT + +/** + * EnterEcConfig - Force EC into Config mode + * + * + * + * + */ +VOID EnterEcConfig (VOID); + +/** + * ExitEcConfig - Force EC exit Config mode + * + * + * + * + */ +VOID ExitEcConfig (VOID); + +/** + * ReadEC8 - Read EC register data + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Read Data Buffer + * + */ +VOID ReadEC8 (IN UINT8 Address, IN UINT8* Value); + +/** + * WriteEC8 - Write date into EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Write Data Buffer + * + */ +VOID WriteEC8 (IN UINT8 Address, IN UINT8* Value); + +/** + * RWEC8 - Read/Write EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] AndMask - Data And Mask 8 bits + * @param[in] OrMask - Data OR Mask 8 bits + * + */ +VOID RWEC8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask); + +/** + * IsZoneFuncEnable - check every zone support function with BitMap from user define + * + */ +BOOLEAN IsZoneFuncEnable ( UINT16 Flag, UINT8 func, UINT8 Zone); + +VOID sbECfancontrolservice (IN AMDSBCFG* pConfig); +VOID SBIMCFanInitializeS3 (VOID); +VOID GetSbAcpiMmioBase (OUT UINT32* AcpiMmioBase); +VOID GetSbAcpiPmBase (OUT UINT16* AcpiPmBase); + +// #endif + Added: trunk/src/vendorcode/amd/cimx/sb800/SBMAIN.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBMAIN.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,248 @@ +/** + * @file + * + * SB Initialization. + * + * Init IOAPIC/IOMMU/Misc NB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +#ifndef B1_IMAGE + +/*----------------------------------------------------------------------------------------*/ +/** + * sbBeforePciInit - Config Southbridge before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + +VOID +sbBeforePciInit ( + IN AMDSBCFG* pConfig + ) +{ + commonInitEarlyBoot (pConfig); + commonInitEarlyPost (pConfig); +#ifndef NO_EC_SUPPORT + ecInitBeforePciEnum (pConfig); +#endif + usbInitBeforePciEnum (pConfig); // USB POST TIME Only + sataInitBeforePciEnum (pConfig); // Init SATA class code and PHY + gecInitBeforePciEnum (pConfig); // Init GEC + azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio + sbPcieGppEarlyInit (pConfig); // Gpp port init + abSpecialSetBeforePciEnum (pConfig); + usbDesertPll (pConfig); +} + +/** + * sbAfterPciInit - Config Southbridge after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + usbInitAfterPciInit (pConfig); // Init USB MMIO + sataInitAfterPciEnum (pConfig); // SATA port enumeration + gecInitAfterPciEnum (pConfig); + azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio + +#ifndef NO_HWM_SUPPORT + hwmInit (pConfig); +#endif +} + +/** + * sbMidPostInit - Config Southbridge during middle of POST + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbMidPostInit ( + IN AMDSBCFG* pConfig + ) +{ + sataInitMidPost (pConfig); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * sbLatePost - Prepare Southbridge to boot to OS. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbLatePost ( + IN AMDSBCFG* pConfig + ) +{ +// UINT16 dwVar; + BUILDPARAM *pStaticOptions; + pStaticOptions = &(pConfig->BuildParameters); + commonInitLateBoot (pConfig); + sataInitLatePost (pConfig); + gecInitLatePost (pConfig); + hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit +#ifndef NO_EC_SUPPORT + ecInitLatePost (pConfig); +#endif + sbPcieGppLateInit (pConfig); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + +VOID +sbBeforePciRestoreInit ( + IN AMDSBCFG* pConfig + ) +{ + pConfig->S3Resume = 1; + commonInitEarlyBoot (pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB + abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers + usbInitBeforePciEnum (pConfig); // USB POST TIME Only + sataInitBeforePciEnum (pConfig); + gecInitBeforePciEnum (pConfig); // Init GEC + azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio + sbPcieGppEarlyInit (pConfig); // Gpp port init + abSpecialSetBeforePciEnum (pConfig); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + +VOID +sbAfterPciRestoreInit ( + IN AMDSBCFG* pConfig + ) +{ + BUILDPARAM *pStaticOptions; + + pConfig->S3Resume = 1; + + usbSetPllDuringS3 (pConfig); + pStaticOptions = &(pConfig->BuildParameters); + commonInitLateBoot (pConfig); + sataInitAfterPciEnum (pConfig); + gecInitAfterPciEnum (pConfig); + azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio + hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit + sataInitLatePost (pConfig); + c3PopupSetting (pConfig); + +#ifndef NO_HWM_SUPPORT + SBIMCFanInitializeS3 (); +#endif +} + +/*----------------------------------------------------------------------------------------*/ +/** + * sbSmmAcpiOn - Config Southbridge during ACPI_ON + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbSmmAcpiOn ( + IN AMDSBCFG* pConfig + ) +{ + // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest + // recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows + AMDSBCFG* pTmp; //lx-dummy for /W4 build + pTmp = pConfig; + + // Disable Power Button SMI + RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB2, AccWidthUint8, ~(BIT4 + BIT5), 0); + RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6 + BIT7), 0); +} + +#endif + +/*----------------------------------------------------------------------------------------*/ +/** + * Call Back routine. + * + * + * + * @param[in] Func Callback ID. + * @param[in] Data Callback specific data. + * @param[in] pConfig Southbridge configuration structure pointer. + */ +UINTN +CallBackToOEM ( + IN UINT32 Func, + IN UINT32 Data, + IN AMDSBCFG* pConfig + ) +{ + UINT32 Result; + Result = 0; + if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result; + Result = (pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig); + + return Result; +} + + Added: trunk/src/vendorcode/amd/cimx/sb800/SBPELIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBPELIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,188 @@ +/** + * @file + * + * Southbridge IO access common routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +/** + * Read Southbridge Revision ID cie Base + * + * + * @retval 0xXXXXXXXX Revision ID + * + */ +UINT8 +getRevisionID ( + OUT VOID + ) +{ + UINT8 dbVar0; + ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0); + return dbVar0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * programPciByteTable - Program PCI register by table (8 bits data) + * + * + * + * @param[in] pPciByteTable - Table data pointer + * @param[in] dwTableSize - Table length + * + */ +VOID +programPciByteTable ( + IN REG8MASK* pPciByteTable, + IN UINT16 dwTableSize + ) +{ + UINT8 i; + UINT8 dbBusNo; + UINT8 dbDevFnNo; + UINT32 ddBDFR; + + dbBusNo = pPciByteTable->bRegIndex; + dbDevFnNo = pPciByteTable->bANDMask; + pPciByteTable++; + + for ( i = 1; i < dwTableSize; i++ ) { + if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) { + pPciByteTable++; + dbBusNo = pPciByteTable->bRegIndex; + dbDevFnNo = pPciByteTable->bANDMask; + pPciByteTable++; + i++; + } else { + ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ; + RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask); + pPciByteTable++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data) + * + * + * + * @param[in] pAcpiTbl - Table data pointer + * + */ +VOID +programSbAcpiMmioTbl ( + IN AcpiRegWrite *pAcpiTbl + ) +{ + UINT8 i; + UINT32 ddtempVar; + if (pAcpiTbl != NULL) { + for ( i = 1; pAcpiTbl->MmioBase < 0xf0; i++ ) { + ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg; + RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask); + pAcpiTbl++; + } + } +} + +/** + * getChipSysMode - Get Chip status + * + * + * @param[in] Value - Return Chip strap status + * StrapStatus [15.0] - SB800 chip Strap Status + * @li 0001 - Not USED FWH + * @li 0002 - Not USED LPC ROM + * @li 0004 - EC enabled + * @li 0008 - Reserved + * @li 0010 - Internal Clock mode + * + */ +VOID +getChipSysMode ( + IN VOID* Value + ) +{ + ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read Southbridge CIMx configuration structure pointer + * + * + * + * @retval 0xXXXXXXXX CIMx configuration structure pointer. + * + */ +AMDSBCFG* +getConfigPointer ( + OUT VOID + ) +{ + UINT8 dbReg; + UINT8 dbValue; + UINT8 i; + UINT32 ddValue; + ddValue = 0; + dbReg = SB_ECMOS_REG08; + + for ( i = 0; i <= 3; i++ ) { + WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg); + ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue); + ddValue |= (dbValue << (i * 8)); + dbReg++; + } + return ( (AMDSBCFG*) (UINTN)ddValue); +} + +/** + * getEfuseStatue - Get Efuse status + * + * + * @param[in] Value - Return Chip strap status + * + */ +VOID +getEfuseStatus ( + IN VOID* Value + ) +{ + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5); + WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value); + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0); +} Added: trunk/src/vendorcode/amd/cimx/sb800/SBPOR.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBPOR.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,347 @@ + +/** + * @file + * + * Southbridge Init during POWER-ON + * + * Prepare Southbridge environment during power on stage. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" +/** + * sbPorInitPciTable - PCI device registers initial during the power on stage. + */ +const static REG8MASK sbPorInitPciTable[] = +{ + // SATA device + {0x00, SATA_BUS_DEV_FUN, 0}, + {SB_SATA_REG84 + 3, ~BIT2, 0}, + {SB_SATA_REG84 + 1, ~(BIT4 + BIT5), BIT4 + BIT5}, + {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5}, + {0xFF, 0xFF, 0xFF}, + // LPC Device (Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2}, + {SB_LPC_REG7C, 0x00, BIT0 + BIT2}, + {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5}, + // A12 set 0xBB [5:3] = 111 to improve SPI timing margin. + // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement) + {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5}, + {SB_LPC_REGBA, 0x9F, BIT5 + BIT6}, + {0xFF, 0xFF, 0xFF}, + // P2P Bridge (Bus 0, Dev 20, Func 4) + {0x00, PCIB_BUS_DEV_FUN, 0}, + {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4}, + // Enable IO but not allocate any IO range. This is for post code display on debug port behind P2P bridge. + {SB_PCIB_REG1C, 0x00, 0xF0}, + {SB_PCIB_REG1D, 0x00, 0x00}, + {SB_PCIB_REG04, 0x00, 0x21}, + {SB_PCIB_REG40, 0xDF, 0x20}, + {SB_PCIB_REG50, 0x02, 0x01}, + {0xFF, 0xFF, 0xFF}, +}; + +/** + * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage. + */ +const static AcpiRegWrite sbPmioPorInitTable[] = +{ + {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0}, + {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, + {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0}, + {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0}, + {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x7F, BIT7}, + {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0}, + {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E}, + {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40}, + {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08}, + {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2}, + {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4}, + {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0}, + {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT7}, + {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3}, + {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00}, + // RPR GEC I/O Termination Setting + // PM_Reg 0xF6 = Power-on default setting + // PM_Reg 0xF7 = Power-on default setting + // PM_Reg 0xF8 = 0x6C + // PM_Reg 0xF9 = 0x21 + // PM_Reg 0xFA = 0x00 SB800 A12 GEC I/O Pad settings for 3.3V CMOS + {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C}, + {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x27}, + {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00}, + {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xFE, 0x14}, + {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40}, + + {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},//ENH210907 SB800: request to no longer clear kb_pcirst_en (bit 1) of PM_Reg BEh per the RPR + + {0xFF, 0xFF, 0xFF, 0xFF}, +}; + +/** + * sbPowerOnInit - Config Southbridge during power on stage. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbPowerOnInit ( + IN AMDSBCFG* pConfig + ) +{ + + UINT8 dbPortStatus; + UINT8 dbSysConfig; + UINT32 abValue; + UINT8 dbValue; + UINT8 dbEfuse; + UINT8 dbCg2WR; + UINT8 dbCg1Pll; + UINT8 cimNbSbGen2; + UINT8 cimSataMode; + UINT8 cimSpiFastReadEnable; + UINT8 cimSpiFastReadSpeed; + UINT8 SataPortNum; + + cimNbSbGen2 = pConfig->NbSbGen2; + cimSataMode = pConfig->SATAMODE.SataModeReg; +// Adding Fast Read Function support + if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) { + cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable; + } else { + cimSpiFastReadEnable = cimSpiFastReadEnableDefault; + } + cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed; +#if SB_CIMx_PARAMETER == 0 + cimNbSbGen2 = cimNbSbGen2Default; + cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default); + cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault)); + cimSpiFastReadEnable = cimSpiFastReadEnableDefault; + cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault; +#endif + +// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct + RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0); + +// Set A-Link bridge access address. This address is set at device 14h, function 0, +// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX); + writeAlink (0x80000004, 0x04); // RPR 4.2 Enable SB800 to issue memory read/write requests in the upstream direction + abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation + abValue = abValue | BIT0; + writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue); + writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. + writeAlink (0x34, readAlink (0x34) | BIT9); + + dbEfuse = FUSE_ID_EFUSE_LOC; + getEfuseStatus (&dbEfuse); + if ( dbEfuse == M1_D1_FUSE_ID ) { + dbEfuse = MINOR_ID_EFUSE_LOC; + getEfuseStatus (&dbEfuse); + if ( dbEfuse == M1_MINOR_ID ) { + // Limit ALink speed to 2.5G if Hudson-M1 + cimNbSbGen2 = 0; + } + } +// Step 1: +// AXINDP_Reg 0xA4[0] = 0x1 +// Step 2: +// AXCFG_Reg 0x88[3:0] = 0x2 +// Step3: +// AXINDP_Reg 0xA4[18] = 0x1 + if ( cimNbSbGen2 == TRUE ) { + rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT0); + rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, 0x2); + rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT18); + } + +// Set Build option into SB + WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress)); + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress)); + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1)); +// Enabled SMBUS0/SMBUS1 (ASF) Base Address + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1] + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 00, (pConfig->BuildParameters.Smbus1BaseAddress)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase)); + + dbEfuse = SATA_FIS_BASE_EFUSE_LOC; + getEfuseStatus (&dbEfuse); + + programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0])); + + + SataPortNum = 0; + for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) { + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum); + SbStall (2); + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00); + SbStall (2); + } + + + //The following bits must be set before enabling SPI prefetch. + // Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0). + // if Ec is enable + // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed. + // else + // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at + // the speed. + getChipSysMode (&dbSysConfig); + if (pConfig->BuildParameters.SpiSpeed < 0x02) { + pConfig->BuildParameters.SpiSpeed = 0x01; + if (dbSysConfig & ChipSysEcEnable) pConfig->BuildParameters.SpiSpeed = 0x02; + } + + if (pConfig->SbSpiSpeedSupport) { + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26)); + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 1 << 16 ); + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT13 + BIT12), (pConfig->BuildParameters.SpiSpeed << 12)); + } + // SPI Fast Read Function + if ( cimSpiFastReadEnable ) { + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, BIT18); + } else { + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, 0x00); + } + + if ( cimSpiFastReadSpeed ) { + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14)); + } + //Program power on pci init table + programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) ); + + programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); + + dbValue = 0x0A; + WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue); + ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); + dbValue &= 0xEF; + WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); + +// Change the CG PLL multiplier to x1.1 + if ( pConfig->UsbRxMode !=0 ) { + dbCg2WR = 0x00; + dbCg1Pll = 0x3A; + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, &dbCg2WR); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A); + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, &dbCg1Pll); + dbCg2WR &= BIT4; + if (( dbCg2WR == 0x00 ) && ( dbCg1Pll !=0x10 )) + { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint8, 0xE1, 0x10); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0, USB_PLL_Voltage); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x10); + dbValue = 0x06; + WriteIO (0xCF9, AccWidthUint8, &dbValue); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x00); + } + } + + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, ~(pConfig->BuildParameters.BiosSize << 4), 0); + + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0, (pConfig->SATAMODE.SataModeReg) & 0xFD ); + + if (dbEfuse & BIT0) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04); + } + + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus); + if ( ((dbPortStatus & 0xF0) == 0x10) ) { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5); + } + + if ( pConfig->BuildParameters.LegacyFree ) { + RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000); + } else { + RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5); + } + + dbValue = 0x09; + WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue); + ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); + if ( !pConfig->BuildParameters.EcKbd ) { + // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input + dbValue = dbValue & 0xF9; + } + if ( pConfig->BuildParameters.LegacyFree ) { + // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation. + dbValue = dbValue & 0x9F; + } + // Enabled IRQ input + dbValue = dbValue | BIT4; + WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); + +#ifndef NO_EC_SUPPORT + getChipSysMode (&dbPortStatus); + if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) { + // EC is disabled by jumper setting or board config + RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08); + ecPowerOnInit ( pConfig); + } +#endif + + ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, &dbValue); + if (dbValue & ChipSysIntClkGen) { + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, &dbValue); + if (dbValue & BIT2) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x40); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x00); + } + } + + // Restore GPP clock to on as it may be off during last POST when some device was disabled; + // the device can't be detected if enabled again as the values retain on S5 and warm reset. + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG00, AccWidthUint32, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04, AccWidthUint8, 0xFF, 0xFF); + + // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5); +} Added: trunk/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,514 @@ +/** + * @file + * + * Southbridge CIMx Function Support Define (All) + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +// Southbridge SBMAIN Routines + +/** + * Southbridge Main Function Public Function + * + */ + +/** + * sbBeforePciInit - Config Southbridge before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbBeforePciInit (IN AMDSBCFG* pConfig); + + +/** + * sbAfterPciInit - Config Southbridge after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbAfterPciInit (IN AMDSBCFG* pConfig); + +/** + * sbMidPostInit - Config Southbridge during middle of POST + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbMidPostInit (IN AMDSBCFG* pConfig); + +/** + * sbLatePost - Prepare Southbridge to boot to OS. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbLatePost (IN AMDSBCFG* pConfig); + +/** + * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbBeforePciRestoreInit (IN AMDSBCFG* pConfig); + +/** + * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbAfterPciRestoreInit (IN AMDSBCFG* pConfig); + +/** + * sbSmmAcpiOn - Config Southbridge during ACPI_ON + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbSmmAcpiOn (IN AMDSBCFG* pConfig); + +/** + * CallBackToOEM - Call Back routine. + * + * + * + * @param[in] Func Callback ID. + * @param[in] Data Callback specific data. + * @param[in] pConfig Southbridge configuration structure pointer. + */ +UINTN CallBackToOEM (IN UINT32 Func, IN UINT32 Data, IN AMDSBCFG* pConfig); + + +// Southbridge SBPOR Routines + +/** + * Southbridge power-on initial Public Function + * + */ + +/** + * sbPowerOnInit - Config Southbridge during power on stage. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbPowerOnInit (IN AMDSBCFG* pConfig); + + +// Southbridge Common Routines + +/** + * Southbridge Common Public Function + * + */ + +/** + * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. + * + * This settings should be done during S3 resume also + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID commonInitEarlyBoot (IN AMDSBCFG* pConfig); + +/** + * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. + * + * This settings might not program during S3 resume + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID commonInitEarlyPost (IN AMDSBCFG* pConfig); + +/** + * commonInitLateBoot - Prepare Southbridge register setting to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID commonInitLateBoot (IN AMDSBCFG* pConfig); + +/** + * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig); + +VOID usbSetPllDuringS3 (IN AMDSBCFG* pConfig); +VOID usbDesertPll (IN AMDSBCFG* pConfig); + +/** + * hpetInit - Program Southbridge HPET function + * + * ** Eric + * + * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] pStaticOptions Platform build configuration table. + * + */ +VOID hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions); + +/** + * c3PopupSetting - Program Southbridge C state function + * + * ** Eric + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID c3PopupSetting (IN AMDSBCFG* pConfig); + +/** + * FusionRelatedSetting - Program Fusion C related function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID FusionRelatedSetting (IN AMDSBCFG* pConfig); + +/** + * Southbridge Common Private Function + * + */ + +/** + * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig); + +// Southbridge SATA Routines + +/** + * Southbridge SATA Controller Public Function + * + */ + +/** + * sataInitMidPost - Config SATA controller in Middle POST. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sataInitMidPost (IN AMDSBCFG* pConfig); + +/** + * sataInitAfterPciEnum - Config SATA controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sataInitAfterPciEnum (IN AMDSBCFG* pConfig); + +/** + * sataInitBeforePciEnum - Config SATA controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sataInitBeforePciEnum (IN AMDSBCFG* pConfig); + +/** + * sataInitLatePost - Prepare SATA controller to boot to OS. + * + * - Set class ID to AHCI (if set to AHCI * Mode) + * - Enable AHCI interrupt + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sataInitLatePost (IN AMDSBCFG* pConfig); + +// Southbridge GEC Routines + +/** + * Southbridge GEC Controller Public Function + * + */ + +/** + * gecInitBeforePciEnum - Config GEC controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID gecInitBeforePciEnum (IN AMDSBCFG* pConfig); + +/** + * gecInitAfterPciEnum - Config GEC controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID gecInitAfterPciEnum (IN AMDSBCFG* pConfig); + +/** + * gecInitLatePost - Prepare GEC controller to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID gecInitLatePost (IN AMDSBCFG* pConfig); + +// Southbridge USB Routines + +/** + * Southbridge USB Controller Public Function + * + */ + +/** + * Config USB controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID usbInitBeforePciEnum (IN AMDSBCFG* pConfig); + +/** + * Config USB controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID usbInitAfterPciInit (IN AMDSBCFG* pConfig); + +/** + * Config USB1 EHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig); + +// Southbridge SMI Service Routines (SMM.C) + +/** + * Southbridge SMI Service Routines Public Function + * + */ + +/** + * Southbridge SMI service module + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbSmmService (IN AMDSBCFG* pConfig); + +/** + * softwareSMIservice - Software SMI service + * + * ** Eric + * + * @param[in] VOID Southbridge software SMI service ID. + * + */ +VOID softwareSMIservice (IN VOID); + +// Southbridge GPP Controller Routines + +/** + * Southbridge GPP Controller Routines Public Function + * + */ + +/** + * GPP early programming and link training. On exit all populated EPs should be fully operational. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbPcieGppEarlyInit (IN AMDSBCFG* pConfig); + +/** + * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbPcieGppLateInit (IN AMDSBCFG* pConfig); + +// Southbridge HD Controller Routines (AZALIA.C) + +/** + * Southbridge HD Controller Routines (AZALIA.C) Public Function + * + */ + +/** + * Config HD Audio Before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig); + +/** + * Config HD Audio after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig); + + +// Southbridge EC Routines + +#ifndef NO_EC_SUPPORT +/** + * Southbridge EC Controller Public Function + * + */ + +/** + * Config EC controller during power-on + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID ecPowerOnInit (IN AMDSBCFG* pConfig); + +/** + * Config EC controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID ecInitBeforePciEnum (IN AMDSBCFG* pConfig); + +/** + * Prepare EC controller to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID ecInitLatePost (IN AMDSBCFG* pConfig); + +/** + * validateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + * @retval TRUE Pass + * @retval FALSE Failed + */ + BOOLEAN validateImcFirmware (IN AMDSBCFG* pConfig); + +/** + * validateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID softwareToggleImcStrapping (IN AMDSBCFG* pConfig); +#endif + +#ifndef NO_HWM_SUPPORT +/** + * validateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID hwmInit (IN AMDSBCFG* pConfig); +#endif + Added: trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,1111 @@ + +/** + * @file + * + * Southbridge CIMx configuration structure define + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _AMD_SBTYPE_H_ +#define _AMD_SBTYPE_H_ + +#pragma pack (push, 1) + +/** + * Entry point of Southbridge CIMx + * + * + * @param[in] Param1 Southbridge CIMx Function ID. + * @param[in] Param2 Southbridge Input Data. + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +typedef UINT32 (*SBCIM_HOOK_ENTRY) (UINT32 Param1, UINT32 Param2, void* pConfig); +/** + * SMM_SERVICE_ROUTINE - Southbridge SMI service routine + * + */ +typedef void (*SMM_SERVICE_ROUTINE) (void); + + +/** + * The STATIC platform information for CIMx Module. + * + */ +typedef struct _BUILDPARAM { + UINT32 BiosSize:3; /**< BiosSize + * @par + * BIOSSize [2.0] - BIOS Image Size + * @li 0 - 1M + * @li 1 - 2M + * @li 3 - 4M + * @li 7 - 8M + * In SB800, default ROM size is 1M Bytes, if your platform ROM bigger then 1M + * you have to set the ROM size outside CIMx module and before AGESA module get call + * + */ + UINT32 LegacyFree:1; /**< LegacyFree + * @par + * Config Southbridge CIMx module for Legacy Free Mode + */ + UINT32 SpiSpeed:2; /**< SpiSpeed + * @par + * SPI Speed [1.0] - the clock speed for non-fast read command + * @li 00 - 66Mhz + * @li 01 - 33Mhz + * @li 10 - 22Mhz + * @li 11 - 16.5Mhz + * + */ + UINT32 ImcEnableOverWrite:2; /**< ImcEnableOverWrite + * @par + * Imc Enable OverWrite + * @li 00 - by default strapping + * @li 01 - On + * @li 10 - Off + * + */ + UINT32 SpiFastReadEnable:1; /**< SpiFastReadEnable + * @par + * @li 00 - Disable SPI Fast Read Function + * @li 01 - Enable SPI Fast Read Function + */ + UINT32 SpiFastReadSpeed:2; /**< SpiFastReadSpeed + * @par + * @li 00 - 66Mhz + * @li 01 - 33Mhz + * @li 10 - 22Mhz + * @li 11 - 16.5Mhz + */ + UINT32 SpreadSpectrumType:1; /**< SpreadSpectrumType + * @par + * @li 0 - Spread Spectrum for normal platform + * @li 1 - Spread Spectrum for Ontario platform + */ +/** Dummy0 - Reserved */ + UINT32 Dummy0:4; + UINT32 EcKbd:1; /**< EcKbd + * @par + * EcKbd [16] - Platform use EC (as SIO) or SIO chip for PS/2 Keyboard and Mouse + * @li 0 - Use SIO PS/2 function. + * @li 1 - Use EC PS/2 function instead of SIO PS/2 function. ** + * @li ** When set 1, EC function have to enable, otherwise, CIMx treat as legacy-free system. + */ +/** EcChannel0 - Reserved */ + UINT32 EcChannel0:1; +/** UsbMsi - Reserved */ + UINT32 UsbMsi:1; +/** HdAudioMsi - Reserved */ + UINT32 HdAudioMsi:1; +/** LpcMsi - Reserved */ + UINT32 LpcMsi:1; +/** PcibMsi - Reserved */ + UINT32 PcibMsi:1; +/** AbMsi - Reserved */ + UINT32 AbMsi:1; +/** Dummy1 - Reserved */ + UINT32 Dummy1:9; + + UINT32 Smbus0BaseAddress; /**< Smbus0BaseAddress + * @par + * Smbus BASE Address + */ + UINT32 Smbus1BaseAddress; /**< Smbus1BaseAddress + * @par + * Smbus1 (ASF) BASE Address + */ + UINT32 SioPmeBaseAddress; /**< SioPmeBaseAddress + * @par + * SIO PME BASE Address + */ + UINT32 WatchDogTimerBase; /**< WatchDogTimerBase + * @par + * Watch Dog Timer Address + */ + UINT32 GecShadowRomBase; /**< GecShadowRomBase + * @par + * GEC (NIC) SHADOWROM BASE Address + */ + UINT32 SpiRomBaseAddress; /**< SpiRomBaseAddress + * @par + * SPI ROM BASE Address + */ + UINT16 AcpiPm1EvtBlkAddr; /**< AcpiPm1EvtBlkAddr + * @par + * ACPI PM1 event block Address + */ + UINT16 AcpiPm1CntBlkAddr; /**< AcpiPm1CntBlkAddr + * @par + * ACPI PM1 Control block Address + */ + UINT16 AcpiPmTmrBlkAddr; /**< AcpiPmTmrBlkAddr + * @par + * ACPI PM timer block Address + */ + UINT16 CpuControlBlkAddr; /**< CpuControlBlkAddr + * @par + * ACPI CPU control block Address + */ + UINT16 AcpiGpe0BlkAddr; /**< AcpiGpe0BlkAddr + * @par + * ACPI GPE0 block Address + */ + UINT16 SmiCmdPortAddr; /**< SmiCmdPortAddr + * @par + * SMI command port Address + */ + UINT16 AcpiPmaCntBlkAddr; /**< AcpiPmaCntBlkAddr + * @par + * ACPI PMA Control block Address + */ + UINT32 HpetBase; /**< HpetBase + * @par + * HPET Base address + */ + UINT32 SataIDESsid; /**< SataIDESsid + * @par + * SATA IDE mode SSID + */ + UINT32 SataRAIDSsid; /**< SataRAIDSsid + * @par + * SATA RAID mode SSID + */ + UINT32 SataRAID5Ssid; /**< SataRAID5Ssid + * @par + * SATA RAID5 mode SSID + */ + UINT32 SataAHCISsid; /**< SataAHCISsid + * @par + * SATA AHCI mode SSID + */ + UINT32 OhciSsid; /**< OhciSsid + * @par + * OHCI Controller SSID + */ + UINT32 EhciSsid; /**< EhciSsid + * @par + * EHCI Controller SSID + */ + UINT32 Ohci4Ssid; /**< Ohci4Ssid + * @par + * OHCI4 Controller SSID (Force USB 1.1 mode) + */ + UINT32 SmbusSsid; /**< SmbusSsid + * @par + * SMBUS controller SSID + */ + UINT32 IdeSsid; /**< IdeSsid + * @par + * IDE (Sata) controller SSID + */ + UINT32 AzaliaSsid; /**< AzaliaSsid + * @par + * HD Audio controller SSID + */ + UINT32 LpcSsid; /**< LpcSsid + * @par + * LPC controller SSID + */ + UINT32 PCIBSsid; /**< PCIBSsid + * @par + * PCIB controller SSID + */ +} BUILDPARAM; + +/** + * The EC fan MSGREG struct for CIMx Module. * + */ +typedef struct _EC_struct { + UINT8 MSGFun81zone0MSGREG0; ///0 - Port doesn't have slot. No need to train the link + * @li 1 - Port connection defined and needs to be trained + */ + UINT32 PortDetected:1; /**< Link training status + * @par + * @li 0 - EP not detected + * @li 1 - EP detected + */ + UINT32 PortIsGen2:2; /**< Port link speed configuration + * @par + * @li 00 - Auto + * @li 01 - Forced GEN1 + * @li 10 - Forced GEN2 + * @li 11 - Reserved + */ + + UINT32 PortHotPlug:1; /**< Support hot plug? + * @par + * @li 0 - No support + * @li 1 - support + */ +/** PortMisc - Reserved */ + UINT32 PortMisc:27; +} SBGPPPORTCONFIG; + +/** CODECENTRY - Southbridge HD Audio OEM Codec structure */ +typedef struct _CODECENTRY { +/** Nid - Reserved ?? */ + UINT8 Nid; +/** Byte40 - Reserved ?? */ + UINT32 Byte40; +} CODECENTRY; + +/** CODECTBLLIST - Southbridge HD Audio Codec table list */ +typedef struct _CODECTBLLIST { +/** CodecID - Codec ID */ + UINT32 CodecID; +/** CodecTablePtr - Codec table pointer */ + CODECENTRY* CodecTablePtr; +} CODECTBLLIST; + +/** Sata Controller structure */ +typedef struct _SATAST { + UINT8 SataController:1; /**< SataController + * @par + * Sata Controller + * @li 0 - disable + * @li 1 - enable + */ + UINT8 SataIdeCombMdPriSecOpt:1; /**< SataIdeCombMdPriSecOpt - Reserved */ + UINT8 SataSetMaxGen2:1; /**< SataSetMaxGen2 + * @par + * Sata Controller Set to Max Gen2 mode + * @li 0 - disable + * @li 1 - enable + */ + UINT8 SataIdeCombinedMode:1; /**< SataIdeCombinedMode + * @par + * Sata IDE Controller set to Combined Mode + * @li 0 - enable + * @li 1 - disable + */ +/** SATARefClkSel - Reserved */ + UINT8 SATARefClkSel:2; // 4:5 +/** SATARefDivSel - Reserved */ + UINT8 SATARefDivSel:2; // 6:7 +} SATAST; + +/** _USBST Controller structure + * + * Usb Ohci1 Contoller is define at BIT0 + * - 0:disable 1:enable + * (Bus 0 Dev 18 Func0) * + * Usb Ehci1 Contoller is define at BIT1 + * - 0:disable 1:enable + * (Bus 0 Dev 18 Func2) * + * Usb Ohci2 Contoller is define at BIT2 + * - 0:disable 1:enable + * (Bus 0 Dev 19 Func0) * + * Usb Ehci2 Contoller is define at BIT3 + * - 0:disable 1:enable + * (Bus 0 Dev 19 Func2) * + * Usb Ohci3 Contoller is define at BIT4 + * - 0:disable 1:enable + * (Bus 0 Dev 22 Func0) * + * Usb Ehci3 Contoller is define at BIT5 + * - 0:disable 1:enable + * (Bus 0 Dev 22 Func2) * + * Usb Ohci4 Contoller is define at BIT6 + * - 0:disable 1:enable + * (Bus 0 Dev 20 Func5) * + */ +typedef struct _USBST { + UINT8 Ohci1:1; ///< Ohci0 controller - 0:disable, 1:enable + UINT8 Ehci1:1; ///< Ehci1 controller - 0:disable, 1:enable + UINT8 Ohci2:1; ///< Ohci2 controller - 0:disable, 1:enable + UINT8 Ehci2:1; ///< Ehci2 controller - 0:disable, 1:enable + UINT8 Ohci3:1; ///< Ohci3 controller - 0:disable, 1:enable + UINT8 Ehci3:1; ///< Ehci3 controller - 0:disable, 1:enable + UINT8 Ohci4:1; ///< Ohci4 controller - 0:disable, 1:enable + UINT8 UTemp:1; ///< Reserved +} USBST; + +/** + * _AZALIAPIN - HID Azalia or GPIO define structure. + * + */ +typedef struct _AZALIAPIN { + UINT8 AzaliaSdin0:2; /**< AzaliaSdin0 + * @par + * SDIN0 is define at BIT0 & BIT1 + * @li 00 - GPIO PIN + * @li 10 - As a Azalia SDIN pin + */ + UINT8 AzaliaSdin1:2; /**< AzaliaSdin1 + * @par + * SDIN0 is define at BIT2 & BIT3 + * @li 00 - GPIO PIN + * @li 10 - As a Azalia SDIN pin + */ + UINT8 AzaliaSdin2:2; /**< AzaliaSdin2 + * @par + * SDIN0 is define at BIT4 & BIT5 + * @li 00 - GPIO PIN + * @li 10 - As a Azalia SDIN pin + */ + UINT8 AzaliaSdin3:2; /**< AzaliaSdin3 + * @par + * SDIN0 is define at BIT6 & BIT7 + * @li 00 - GPIO PIN + * @li 10 - As a Azalia SDIN pin + */ +} AZALIAPIN; + +/** AMDSBCFG - Southbridge CIMx configuration structure (Main) */ +typedef struct _AMDSBCFG { +/** StdHeader - Standard header for all AGESA/CIMx services. */ + AMD_CONFIG_PARAMS StdHeader; + +/** BuildParameters - The STATIC platform information for CIMx Module. */ + BUILDPARAM BuildParameters; + //offset 90 bytes (32-121) + //MsgXchgBiosCimx //offset 4 bytes (122-125) + // SATA Configuration + + union /**< union - Reserved */ + { /**< SATAMODE - Sata Controller structure */ +/** SataModeReg - Reserved */ + UINT8 SataModeReg; +/** SataMode - Reserved */ + SATAST SataMode; + } SATAMODE; +/** S3Resume - Flag of ACPI S3 Resume. */ + UINT8 S3Resume:1; // 8 +/** RebootRequired - Flag of Reboot system is required. */ + UINT8 RebootRequired:1; // 9 +/** SbSpiSpeedSupport - Reserved */ + UINT8 SbSpiSpeedSupport:1; // 10 +/**< SpreadSpectrum + * @par + * Spread Spectrum function + * @li 0 - disable + * @li 1 - enable + */ + UINT8 SpreadSpectrum:1; // 11 +/** NbSbGen2 - Reserved */ + UINT8 NbSbGen2:1; // 12 + UINT8 GppGen2:1; // 13 + UINT8 GppMemWrImprove:1; // 14 +/** MsgXchgBiosCimxReserved - Reserved */ + UINT8 MsgXchgBiosCimxReserved:1; // 15 (BB USED) +/**< SataClass - SATA Controller mode [16:18] + * @par + * @li 000 - Native IDE mode + * @li 001 - RAID mode + * @li 010 - AHCI mode + * @li 011 - Legacy IDE mode + * @li 100 - IDE->AHCI mode + * @li 101 - AHCI mode as 4394 ID (AMD driver) + * @li 110 - IDE->AHCI mode as 4394 ID (AMD driver) + */ + UINT16 SataClass:3; // 16:18 +/**< Sata IDE Controller mode + * @par + * @li 0 - Legacy IDE mode + * @li 1 - Native IDE mode + */ + UINT16 SataIdeMode:1; // 19 +/**< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:) + * @par + * @li BIT0 - PORT0 set as ESP port + * @li BIT1 - PORT1 set as ESP port + * @li BIT2 - PORT2 set as ESP port + * @li BIT3 - PORT3 set as ESP port + * @li BIT4 - PORT4 set as ESP port + * @li BIT5 - PORT5 set as ESP port + */ + UINT16 SataEspPort:6; // 20:25 +/** SataPortPower - Reserved */ + UINT16 SataPortPower:6; // 31:26 + + // SATA Debug Option //offset 4 bytes (126-129) + +/**< SataPortMode - Force Each PORT to GEN1/GEN2 mode + * @par + * @li 0 Auto for each PORTs + * @li BIT0 = 1 - PORT0 set to GEN1 + * @li BIT1 = 1 - PORT0 set to GEN2 + * @li BIT2 = 1 - PORT1 set to GEN1 + * @li BIT3 = 1 - PORT1 set to GEN2 + * @li BIT4 = 1 - PORT2 set to GEN1 + * @li BIT5 = 1 - PORT2 set to GEN2 + * @li BIT6 = 1 - PORT3 set to GEN1 + * @li BIT7 = 1 - PORT3 set to GEN2 + * @li BIT8 = 1 - PORT4 set to GEN1 + * @li BIT9 = 1 - PORT4 set to GEN2 + * @li BIT10 = 1 - PORT5 set to GEN1 + * @li BIT11 = 1 - PORT5 set to GEN2 + */ + UINT32 SataPortMode:12; //11:0 +/** SATAClkSelOpt - Reserved */ + UINT32 SATAClkSelOpt:4; // Removed from coding side +/** SataAggrLinkPmCap - Reserved */ + UINT32 SataAggrLinkPmCap:1; //16, 0:OFF 1:ON +/** SataPortMultCap - Reserved */ + UINT32 SataPortMultCap:1; //17, 0:OFF 1:ON +/** SataClkAutoOff - Reserved */ + UINT32 SataClkAutoOff:1; //18, AutoClockOff 0:Disabled, 1:Enabled +/** SataPscCap - Reserved */ + UINT32 SataPscCap:1; //19, 0:Enable PSC capability, 1:Disable PSC capability +/** BIOSOSHandoff - Reserved */ + UINT32 BIOSOSHandoff:1; //20 +/** SataFisBasedSwitching - Reserved */ + UINT32 SataFisBasedSwitching:1; //21 +/** SataCccSupport - Reserved */ + UINT32 SataCccSupport:1; //22 +/** SataSscCap - Reserved */ + UINT32 SataSscCap:1; //23, 0:Enable SSC capability, 1:Disable SSC capability +/** SataMsiCapability - Reserved */ + UINT32 SataMsiCapability:1; //24 0:Hidden 1:Visible. This feature is disabled per RPR, but remains the interface. +/** SataForceRaid - Reserved */ + UINT32 SataForceRaid:1; //25 0:No function 1:Force RAID +/** SataDebugDummy - Reserved */ + UINT32 SataDebugDummy:6; //31:26 +// +// USB Configuration //offset 4 bytes (130-133) +// + +/** USBDeviceConfig - USB Controller Configuration + * + * - Usb Ohci1 Contoller is define at BIT0 + * - 0:disable 1:enable + * (Bus 0 Dev 18 Func0) * + * - Usb Ehci1 Contoller is define at BIT1 + * - 0:disable 1:enable + * (Bus 0 Dev 18 Func2) * + * - Usb Ohci2 Contoller is define at BIT2 + * - 0:disable 1:enable + * (Bus 0 Dev 19 Func0) * + * - Usb Ehci2 Contoller is define at BIT3 + * - 0:disable 1:enable + * (Bus 0 Dev 19 Func2) * + * - Usb Ohci3 Contoller is define at BIT4 + * - 0:disable 1:enable + * (Bus 0 Dev 22 Func0) * + * - Usb Ehci3 Contoller is define at BIT5 + * - 0:disable 1:enable + * (Bus 0 Dev 22 Func2) * + * - Usb Ohci4 Contoller is define at BIT6 + * - 0:disable 1:enable + * (Bus 0 Dev 20 Func5) * + */ + union /**< union - Reserved */ + { /**< USBMODE - USB Controller structure */ +/** SataModeReg - Reserved */ + UINT8 UsbModeReg; +/** SataMode - Reserved */ + USBST UsbMode; + } USBMODE; +/*! + */ + +/**< GecConfig + * @par + * InChip Gbit NIC + * @li 1 - disable + * @li 0 - enable + */ + UINT8 GecConfig:1; //8 + +/**< IrConfig + * @par + * Ir Controller setting + * @li 00 - disable + * @li 01 - Rx and Tx0 + * @li 10 - Rx and Tx1 + * @li 11 - Rx and both Tx0,Tx1 + */ + UINT8 IrConfig:2; //9:10 + +/** GecDummy - Reserved */ + UINT8 GecDummy:5; //15:11 + + //Azalia Configuration + +/**< AzaliaController - Azalia Controller Configuration + * @par + * Azalia Controller [0-1] + * @li 0 - Auto : Detect Azalia controller automatically. + * @li 1 - Diable : Disable Azalia controller. + * @li 2 - Enable : Enable Azalia controller. + */ + UINT8 AzaliaController:2; //17:16 +/**< AzaliaPinCfg - Azalia Controller SDIN pin Configuration + * @par + * @li 0 - disable + * @li 1 - enable + */ + UINT8 AzaliaPinCfg:1; //18 +/**< AzaliaFrontPanel - Azalia Controller Front Panel Configuration + * @par + * Support Front Panel configuration + * @li 0 - Auto + * @li 1 - disable + * @li 2 - enable + */ + UINT8 AzaliaFrontPanel:2; //20:19 +/**< FrontPanelDetected - Force Azalia Controller Front Panel Configuration + * @par + * Force Front Panel configuration + * @li 0 - Not Detected + * @li 1 - Detected + */ + UINT8 FrontPanelDetected:1; //21 +/**< AzaliaSnoop - Azalia Controller Snoop feature Configuration + * @par + * Azalia Controller Snoop feature Configuration + * @li 0 - disable + * @li 1 - enable + */ + UINT8 AzaliaSnoop:1; //22 +/** AzaliaDummy - Reserved */ + UINT8 AzaliaDummy:1; //23 + + union + { +/**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration + * + * SDIN0 is define at BIT0 & BIT1 + * - 00: GPIO PIN + * - 01: Reserved + * - 10: As a Azalia SDIN pin + * + * SDIN1 is define at BIT2 & BIT3 + * * Config same as SDIN0 + * SDIN2 is define at BIT4 & BIT5 + * * Config same as SDIN0 + * SDIN3 is define at BIT6 & BIT7 + * * Config same as SDIN0 + */ + UINT8 AzaliaSdinPin; + AZALIAPIN AzaliaConfig; + } AZALIACONFIG; + +/** AZOEMTBL - Azalia Controller OEM Codec Table Pointer + * + */ + union + { + PLACEHOLDER PlaceHolder; + CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 4 bytes (134-137) + } AZOEMTBL; + +/** AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer + * + */ + union + { + PLACEHOLDER PlaceHolder; + VOID* pAzaliaOemFpCodecTablePtr; //offset 4 bytes (138-141) + } AZOEMFPTBL; + + //Miscellaneous Configuration //offset 4 bytes (142-145) +/** AnyHT200MhzLink - Reserved */ + UINT32 AnyHT200MhzLink:1; //0 +/**< HpetTimer - South Bridge Hpet Timer Configuration + * @par + * @li 0 - disable + * @li 1 - enable + */ + UINT32 HpetTimer:1; //1 +/**< PciClks - PCI Slot Clock Control + * @par + * PCI SLOT 0 define at BIT0 + * - 00: disable + * - 01: enable + * + * PCI SLOT 1 define at BIT1 + * * Config same as PCI SLOT0 + * PCI SLOT 2 define at BIT2 + * * Config same as PCI SLOT0 + * PCI SLOT 3 define at BIT3 + * * Config same as PCI SLOT0 + * PCI SLOT 4 define at BIT4 + * * Config same as PCI SLOT0 + */ + UINT32 PciClks:5; //2:6 +/** MiscReserved1 - Reserved */ + UINT32 MiscReserved1:4; //9:7, Reserved +/** MobilePowerSavings - Debug function Reserved */ + UINT32 MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform +/** MiscDummy1 - Debug function Reserved */ + UINT32 MiscDummy1:1; +/** NativePcieSupport - Debug function Reserved */ + UINT32 NativePcieSupport:1; //13, 0:Enable, 1:Disabled +/** FlashPinConfig - Debug function Reserved */ + UINT32 FlashPinConfig:1; //14, 0:desktop mode 1:mobile mode +/** UsbPhyPowerDown - Debug function Reserved */ + UINT32 UsbPhyPowerDown:1; //15 +/** PcibClkStopOverride - Debug function Reserved */ + UINT32 PcibClkStopOverride:10; //25:16 +/**< HpetMsiDis - South Bridge HPET MSI Configuration + * @par + * @li 1 - disable + * @li 0 - enable + */ + UINT32 HpetMsiDis:1; //26 +/**< ResetCpuOnSyncFlood - Rest CPU on Sync Flood + * @par + * @li 0 - disable + * @li 1 - enable + */ + UINT32 ResetCpuOnSyncFlood:1; //27 +/**< LdtStpDisable - LdtStp# output disable + * @par + * @li 0 - LdtStp# output enable + * @li 1 - LdtStp# output disable + */ + UINT32 LdtStpDisable:1; //28 +/**< MTC1e - Message Triggered C1e + * @par + * @li 0 - disable + * @li 1 - enable + */ + UINT32 MTC1e:1; //29 +/** MiscDummy - Reserved */ + UINT32 MiscDummy:2; //31:30 + + //DebugOptions //offset 4 bytes (146-149) +/** PcibAutoClkCtrlLow - Debug function Reserved */ + UINT32 PcibAutoClkCtrlLow:16; +/** PcibAutoClkCtrlHigh - Debug function Reserved */ + UINT32 PcibAutoClkCtrlHigh:16; + +/**< OEMPROGTBL - ACPI MMIO register setting table OEM override + * @par + * OEM table for customer override ACPI MMIO register in their code. + */ + union + { + PLACEHOLDER OemProgrammingTablePtr; //offset 4 bytes (150-153) + VOID *OemProgrammingTablePtr_Ptr; + } OEMPROGTBL; + + //Gpp Configuration //offset 24 bytes total (154-177) + union { + UINT32 PORTCFG32; + SBGPPPORTCONFIG PortCfg; + } PORTCONFIG[MAX_GPP_PORTS]; //offset 16 bytes + + UINT32 GppLinkConfig; // GPP_LINK_CONFIG = PCIE_GPP_Enable[3:0] + // 0000 - Port ABCD -> 4:0:0:0 + // 0001 - N/A + // 0010 - Port ABCD -> 2:2:0:0 + // 0011 - Port ABCD -> 2:1:1:0 + // 0100 - Port ABCD -> 1:1:1:1 + // + UINT32 GppFoundGfxDev:4; //3:0 If port A-D (mapped to bit [3:0]) has GFX EP detected + UINT32 CoreGen2Enable:1; //4 + UINT32 GppFunctionEnable:1; //5 + UINT32 GppUnhidePorts:1; //6 + UINT32 AlinkPhyPllPowerDown:1; //7 + UINT32 GppConfigDummy1:2; //9:8 + UINT32 GppLaneReversal:1; //10 + UINT32 GppPhyPllPowerDown:1; //11 + UINT32 GppCompliance :1; //12 + UINT32 GppPortAspm:8; //20:13 ASPM state for GPP ports, 14:13 for port0, ..., 20:19 for port3 + // 00 - Disabled + // 01 - L0s + // 10 - L1 + // 11 - L0s + L1 + // + UINT32 GppConfigDummy:11; //31:21 + + //TempMMIO //offset 4 bytes (178-181) + UINT32 TempMMIO; + + // DebugOption2 + UINT32 GecPhyStatus:1; + UINT32 GecDebugOptionDummy:7; + UINT32 SBGecPwr:2; + UINT32 SBGecDebugBus:1; + UINT32 DebugOption2Dummy1:1; + UINT32 DebugOption2Dummy2:1; + UINT32 SbPcieOrderRule:1; + UINT32 SbUsbPll:1; + UINT32 AcDcMsg:1; + UINT32 TimerTickTrack:1; + UINT32 ClockInterruptTag:1; + UINT32 OhciTrafficHanding:1; + UINT32 EhciTrafficHanding:1; + UINT32 FusionMsgCMultiCore:1; + UINT32 FusionMsgCStage:1; +/**< UsbRxMode - CG PLL multiplier for USB Rx 1.1 mode + * @par + * @li 0 - disable + * @li 1 - enable + */ + UINT32 UsbRxMode:1; + UINT32 DebugOption2Dummy3:9; // + + union + { + PLACEHOLDER DynamicGecRomAddressPtr; //offset 4 bytes (182-185) + VOID *DynamicGecRomAddress_Ptr; + } DYNAMICGECROM; + EC_struct Pecstruct; +} AMDSBCFG; + +/** SMMSERVICESTRUC- Southbridge SMI service structure */ +typedef struct _SMMSERVICESTRUC { +/** enableRegNum - Reserved */ + UINT8 enableRegNum; +/** enableBit - Reserved */ + UINT8 enableBit; +/** statusRegNum - Reserved */ + UINT8 statusRegNum; +/** statusBit - Reserved */ + UINT8 statusBit; +/** *debugMessage- Reserved */ + CHAR8 *debugMessage; +/** serviceRoutine - Reserved */ + SMM_SERVICE_ROUTINE serviceRoutine; +} SMMSERVICESTRUC; + +#ifndef _NB_REG8MASK_ + +/** + * - Byte Register R/W structure + * + */ + typedef struct _Reg8Mask { +/** bRegIndex - Reserved */ + UINT8 bRegIndex; +/** bANDMask - Reserved */ + UINT8 bANDMask; +/** bORMask - Reserved */ + UINT8 bORMask; + } REG8MASK; +#endif + +/** + * - SATA Phy setting structure + * + */ +typedef struct _SATAPHYSETTING { +/** wPhyCoreControl - Reserved */ + UINT16 wPhyCoreControl; +/** dwPhyFineTune - Reserved */ + UINT32 dwPhyFineTune; +} SATAPHYSETTING; + +/** + * _ABTblEntry - AB link register table R/W structure + * + */ +typedef struct _ABTblEntry { + /** regType : AB Register Type (ABCFG, AXCFG and so on) */ + UINT8 regType; + /** regIndex : AB Register Index */ + UINT32 regIndex; + /** regMask : AB Register Mask */ + UINT32 regMask; + /** regData : AB Register Data */ + UINT32 regData; +} ABTBLENTRY; + +/** + * _AcpiRegWrite - ACPI MMIO register R/W structure + * + */ +typedef struct _AcpiRegWrite { + /** MmioBase : Index of Soubridge block (For instence GPIO_BASE:0x01 SMI_BASE:0x02) */ + UINT8 MmioBase; + /** MmioReg : Register index */ + UINT8 MmioReg; + /** DataANDMask : AND Register Data */ + UINT8 DataANDMask; + /** DataOrMask : Or Register Data */ + UINT8 DataOrMask; +} AcpiRegWrite; + +/** + * PCI_ADDRESS - PCI access structure + * + */ +#define PCI_ADDRESS(bus, dev, func, reg) \ +(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +/** + * CIM_STATUS - CIMx module function return code + */ +typedef UINT32 CIM_STATUS; +/** + * CIM_SUCCESS - Executed without error + */ +#define CIM_SUCCESS 0x00000000 +/** + * CIM_ERROR - call error + */ +#define CIM_ERROR 0x80000000 +/** + * CIM_UNSUPPORTED - function does not support + */ +#define CIM_UNSUPPORTED 0x80000001 + +#pragma pack (pop) + +/** + * DISABLED - Define disable in module + */ +#define DISABLED 0 +/** + * ENABLED - Define enable in module + */ +#define ENABLED 1 + +// mov al, code +// out 80h, al +// jmp $ + +/** + * DBG_STOP - define a debug point + */ +#define DBG_STOP __asm _emit 0xEB __asm _emit 0xFE + +/** + * STOP_CODE - define a debug point + * Warning: AL gets destroyed! + */ +#define STOP_CODE (code) __asm __emit 0xB0 __asm __emit code __asm __emit 0xE6 \ + __asm __emit 0x80 __asm _emit 0xEB __asm _emit 0xFE + +#endif // _AMD_SBTYPE_H_ Added: trunk/src/vendorcode/amd/cimx/sb800/SMM.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SMM.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,76 @@ +/** + * @file + * + * Southbridge SMM service function + * + * Prepare SMM service module for IBV call Southbridge SMI service routine. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +// +// Declaration of local functions +// + +/** + * Southbridge SMI service module + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbSmmService ( + IN AMDSBCFG* pConfig + ) +{ + AMDSBCFG* pTmp; //lx-dummy for /W4 build + pTmp = pConfig; +} + +/** + * softwareSMIservice - Software SMI service + * + * @param[in] VOID Southbridge software SMI service ID. + * + */ +VOID +softwareSMIservice ( + IN VOID + ) +{ +} + + + + + Added: trunk/src/vendorcode/amd/cimx/sb800/SbModInf.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SbModInf.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,64 @@ +/** + * @file + * + * Function dispatcher. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "SBPLATFORM.h" + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + + +/// module header +VOLATILE AMD_MODULE_HEADER mNbModuleHeader = { + 'DOM$', ///< Standard AMD module signature + CIMX_SB_ID, ///< Chipset ID + CIMX_SB_REVISION, ///< CIMx version + AmdSbDispatcher, ///< Pointer to the module entry + NULL ///< Pointer link to next module header +}; Added: trunk/src/vendorcode/amd/cimx/sb800/USB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/USB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,421 @@ +/** + * @file + * + * Config Southbridge USB controller + * + * Init USB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e \$Revision:$ @e \$Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +#include "SBPLATFORM.h" + +// +// Declaration of local functions +// + +/** + * EhciInitAfterPciInit - Config USB controller after PCI emulation + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] pConfig Southbridge configuration structure pointer. + */ +VOID EhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig); +/** + * OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] pConfig Southbridge configuration structure pointer. + */ +VOID OhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig); + +/** + * SetEhciP11Wr - FIXME + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] pConfig Southbridge configuration structure pointer. + */ +UINT32 SetEhciPllWr (IN UINT32 Value, IN AMDSBCFG* pConfig); + + +/** + * usbInitBeforePciEnum - Config USB controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usbInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + // Disabled All USB controller + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0); + // Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST. + // Enable UsbResumeEnable (USB PME) * Default value + // In SB700 USB SleepCtrl set as BIT10+BIT9, but SB800 default is BIT9+BIT8 (6 uframes) + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16 | S3_SAVE, ~BIT2, BIT2 + BIT7 + BIT8 + BIT9); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, pConfig->USBMODE.UsbModeReg); +} + +/** + * usbInitAfterPciInit - Config USB controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usbInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED, AccWidthUint8, ~BIT1, BIT1); + + usb1EhciInitAfterPciInit (pConfig); + usb2EhciInitAfterPciInit (pConfig); + usb3EhciInitAfterPciInit (pConfig); + usb1OhciInitAfterPciInit (pConfig); + usb2OhciInitAfterPciInit (pConfig); + usb3OhciInitAfterPciInit (pConfig); + usb4OhciInitAfterPciInit (pConfig); + + if ( pConfig->UsbPhyPowerDown ) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, BIT0); + } else + { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, 0); + } + +} + +/** + * usb1EhciInitAfterPciInit - Config USB1 EHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb1EhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB1_EHCI_BUS_DEV_FUN << 16); + EhciInitAfterPciInit (ddDeviceId, pConfig); +} + +/** + * usb2EhciInitAfterPciInit - Config USB2 EHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb2EhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB2_EHCI_BUS_DEV_FUN << 16); + EhciInitAfterPciInit (ddDeviceId, pConfig); +} + +/** + * usb3EhciInitAfterPciInit - Config USB3 EHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb3EhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB3_EHCI_BUS_DEV_FUN << 16); + EhciInitAfterPciInit (ddDeviceId, pConfig); +} + +VOID +EhciInitAfterPciInit ( + IN UINT32 Value, + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddBarAddress; + UINT32 ddVar; + //Get BAR address + ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress); + if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { + //Enable Memory access + RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); + if (pConfig->BuildParameters.EhciSsid != NULL ) { + RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid); + } + //USB Common PHY CAL & Control Register setting + ddVar = 0x00020F00; + WriteMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); + // RPR IN AND OUT DATA PACKET FIFO THRESHOLD + // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 + RWMEM (ddBarAddress + SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); + // RPR EHCI Dynamic Clock Gating Feature + RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~BIT12, 0); + // RPR Enable adding extra flops to PHY rsync path + // Step 1: + // EHCI_BAR 0xB4 [6] = 1 + // EHCI_BAR 0xB4 [7] = 0 + // EHCI_BAR 0xB4 [12] = 0 ("VLoad") + // All other bit field untouched + // Step 2: + // EHCI_BAR 0xB4[12] = 1 + RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~(BIT6 + BIT7 + BIT12), 0x00); + RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12); + //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support + //RPR recommended setting "EHCI Async Park Mode" + //Set EHCI_pci_configx50[23]='0' to enable "EHCI Async Park Mode support" + //RPR Enabling EHCI Async Stop Enhancement + //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement + RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(BIT23), BIT29 + BIT23 + BIT8 + BIT6); + // RPR recommended setting "EHCI Advance PHY Power Savings" + // Set EHCI_pci_configx50[31]='1' + // Fix for EHCI controller driver yellow sign issue under device manager + // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1 + RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT15); + // RPR USB Delay A-Link Express L1 State + // RPR PING Response Fix Enable EHCI_PCI_Config x54[1] = 1 + // RPR Empty-list Detection Fix Enable EHCI_PCI_Config x54[3] = 1 + RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT0, BIT0); + if ( pConfig->BuildParameters.UsbMsi) { + RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~BIT6, 0x00); + } + } +} + +/** + * usb1OhciInitAfterPciInit - Config USB1 OHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb1OhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB1_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (ddDeviceId, pConfig); +} + +/** + * usb2OhciInitAfterPciInit - Config USB2 OHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb2OhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB2_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (ddDeviceId, pConfig); +} + +/** + * usb3OhciInitAfterPciInit - Config USB3 OHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb3OhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB3_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (ddDeviceId, pConfig); +} + +/** + * usb4OhciInitAfterPciInit - Config USB4 OHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb4OhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (ddDeviceId, pConfig); + if (pConfig->BuildParameters.Ohci4Ssid != NULL ) { + RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid); + } +} + +VOID +OhciInitAfterPciInit ( + IN UINT32 Value, + IN AMDSBCFG* pConfig + ) +{ + // Disable the MSI capability of USB host controllers + RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT12), 0x00); + // RPR USB SMI Handshake + RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00); + // SB02186 + RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00); + if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { + if ( pConfig->BuildParameters.OhciSsid != NULL ) { + RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid); + } + } + //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices + //OHCI 0_PCI_Config 0x50[30] = 1 + RWPCI ((UINT32) Value + SB_OHCI_REG50 + 3, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6); + if ( pConfig->BuildParameters.UsbMsi) { + RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, ~BIT0, 0x00); + RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5); + } +} + + +UINT32 +SetEhciPllWr ( + IN UINT32 Value, + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddRetureValue; + UINT32 ddBarAddress; + UINT16 dwVar; + UINT16 dwData; + UINT8 portSC; + ddRetureValue = 0; + dwData = 0; + // Memory, and etc. + //_asm { jmp $}; + RWPCI ((UINT32) Value + 0xC4, AccWidthUint8, 0xF0, 0x00); + RWPCI ((UINT32) Value + 0x04, AccWidthUint8, 0xFF, 0x02); + // Get Bar address + ReadPCI ((UINT32) Value + 0x10, AccWidthUint32, &ddBarAddress); + for (portSC = 0x64; portSC < 0x75; portSC += 0x04 ) { + // Get OHCI command registers + ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwVar); + if ( dwVar & BIT6 ) { + ddRetureValue = ddBarAddress + portSC; + RWMEM (ddBarAddress + portSC, AccWidthUint16, ~BIT6, 0); + for (;;) { + SbStall (5); + ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwData); + if (dwData == 0x1005) break; + } + dwData = 0; + } + } + return ddRetureValue; +} + +VOID +usbSetPllDuringS3 ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 resumeEhciPortTmp; + UINT32 resumeEhciPort; + resumeEhciPortTmp = 0; + resumeEhciPort = 0; +// UINT32 ddDeviceId; +//if Force Port Resume == 1 +// { +// clear Force Port Resume; +// while (!(PORTSC == 0x1005)){wait 5 us; read PORTSC;} +// } + if (pConfig->USBMODE.UsbModeReg & BIT1) { + resumeEhciPortTmp = SetEhciPllWr (USB1_EHCI_BUS_DEV_FUN << 16, pConfig); + if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp; + } + if (pConfig->USBMODE.UsbModeReg & BIT3) { + resumeEhciPortTmp = SetEhciPllWr (USB2_EHCI_BUS_DEV_FUN << 16, pConfig); + if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp; + } + if (pConfig->USBMODE.UsbModeReg & BIT5) { + resumeEhciPortTmp = SetEhciPllWr (USB3_EHCI_BUS_DEV_FUN << 16, pConfig); + if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp; + } + + RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); + RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); + RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); + RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20); + SbStall (10); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00); + RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); + RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); + RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); + RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); + + if (resumeEhciPort > 0) { + RWMEM (resumeEhciPort, AccWidthUint8, ~BIT7, BIT7); + SbStall (4000); + RWMEM (resumeEhciPort, AccWidthUint8, ~BIT6, BIT6); + } + + RWPCI ((UINT32) (USB1_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03); + RWPCI ((UINT32) (USB2_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03); + RWPCI ((UINT32) (USB3_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03); + +} + From uwe at hermann-uwe.de Sat Jan 1 18:51:04 2011 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Sat, 1 Jan 2011 18:51:04 +0100 Subject: [coreboot] [PATCH 3/3] add amd sb800 support In-Reply-To: <4D1C6552.20300@coreboot.org> References: <4D1C6552.20300@coreboot.org> Message-ID: <20110101175104.GB9074@greenwood> On Thu, Dec 30, 2010 at 11:56:18AM +0100, Stefan Reinauer wrote: > On 12/30/10 5:04 AM, She, Kerry wrote: > > > > add amd sb800 southbridge support > > > > Signed-off-by: Kerry She > > > > > Dear Kerry, > > thanks a lot for making this possible. > > Regards, > Stefan > > Acked-by: Stefan Reinauer Committed in r6229, thanks a lot for the continued support by AMD! Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org From svn at coreboot.org Sat Jan 1 18:52:37 2011 From: svn at coreboot.org (repository service) Date: Sat, 01 Jan 2011 18:52:37 +0100 Subject: [coreboot] [commit] r6230 - in trunk/src: include/device southbridge/amd southbridge/amd/cimx_wrapper southbridge/amd/cimx_wrapper/sb800 Message-ID: Author: uwe Date: Sat Jan 1 18:52:34 2011 New Revision: 6230 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6230 Log: Add AMD SB800 southbridge support via cimx_wrapper. Signed-off-by: Kerry She Acked-by: Stefan Reinauer Acked-by: Uwe Hermann Added: trunk/src/southbridge/amd/cimx_wrapper/ trunk/src/southbridge/amd/cimx_wrapper/Kconfig trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc trunk/src/southbridge/amd/cimx_wrapper/sb800/ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c trunk/src/southbridge/amd/cimx_wrapper/sb800/cbtypes.h trunk/src/southbridge/amd/cimx_wrapper/sb800/chip.h trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h Modified: trunk/src/include/device/pci_ids.h trunk/src/southbridge/amd/Kconfig trunk/src/southbridge/amd/Makefile.inc Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Sat Jan 1 18:44:07 2011 (r6229) +++ trunk/src/include/device/pci_ids.h Sat Jan 1 18:52:34 2011 (r6230) @@ -312,6 +312,25 @@ #define PCI_DEVICE_ID_ATI_SB700_USB_19_2 0x4396 #define PCI_DEVICE_ID_ATI_SB700_USB_20_5 0x4399 +#define PCI_DEVICE_ID_ATI_SB800_LPC 0x439D +#define PCI_DEVICE_ID_ATI_SB800_SATA 0x4390 +#define PCI_DEVICE_ID_ATI_SB800_IDE 0x439C +#define PCI_DEVICE_ID_ATI_SB800_HDA 0x4383 +#define PCI_DEVICE_ID_ATI_SB800_PCI 0x4384 +#define PCI_DEVICE_ID_ATI_SB800_PCIEA 0x43A0 +#define PCI_DEVICE_ID_ATI_SB800_PCIEB 0x43A1 +#define PCI_DEVICE_ID_ATI_SB800_PCIEC 0x43A2 +#define PCI_DEVICE_ID_ATI_SB800_PCIED 0x43A3 +#define PCI_DEVICE_ID_ATI_SB800_SM 0x4385 +#define PCI_DEVICE_ID_ATI_SB800_USB_18_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB800_USB_18_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB800_USB_19_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB800_USB_19_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB800_USB_20_5 0x4399 +#define PCI_DEVICE_ID_ATI_SB800_USB_22_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB800_USB_22_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB800_GEC 0x1699 + #define PCI_DEVICE_ID_ATI_RS690_HT 0x7910 #define PCI_DEVICE_ID_ATI_RS690_PCIE 0x7912 #define PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2 0x7913 Modified: trunk/src/southbridge/amd/Kconfig ============================================================================== --- trunk/src/southbridge/amd/Kconfig Sat Jan 1 18:44:07 2011 (r6229) +++ trunk/src/southbridge/amd/Kconfig Sat Jan 1 18:52:34 2011 (r6230) @@ -10,3 +10,4 @@ source src/southbridge/amd/sb600/Kconfig source src/southbridge/amd/rs780/Kconfig source src/southbridge/amd/sb700/Kconfig +source src/southbridge/amd/cimx_wrapper/Kconfig Modified: trunk/src/southbridge/amd/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/Makefile.inc Sat Jan 1 18:44:07 2011 (r6229) +++ trunk/src/southbridge/amd/Makefile.inc Sat Jan 1 18:52:34 2011 (r6230) @@ -9,4 +9,5 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_WRAPPER) += cimx_wrapper Added: trunk/src/southbridge/amd/cimx_wrapper/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/Kconfig Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,29 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# +config SOUTHBRIDGE_AMD_CIMX_WRAPPER + bool + default n + +config SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 + bool + select IOAPIC + select SOUTHBRIDGE_AMD_CIMX_WRAPPER + +source src/southbridge/amd/cimx_wrapper/sb800/Kconfig Added: trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,19 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800) += sb800 Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,381 @@ +/***************************************************************************** + * AMD Generic Encapsulated Software Architecture */ +/** + * @file + * + * Agesa structures and definitions + * + * Contains AMD AGESA/CIMx core interface + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e \$Revision:$ @e \$Date:$ + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +#ifndef _AMD_H_ +#define _AMD_H_ + +// +// +// AGESA Types and Definitions +// +// +#ifndef NULL + #define NULL 0 +#endif + + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + +// AGESA Structures + +/// The standard header for all AGESA services. +typedef struct _AMD_CONFIG_PARAMS { + IN UINT32 ImageBasePtr; ///< The AGESA Image base address. + IN UINT32 Func; ///< The service desired, @sa dispatch.h. + IN UINT32 AltImageBasePtr; ///< Alternate Image location + IN UINT32 PcieBasePtr; ///< PCIe MMIO Base address, if configured. + union { ///< Callback pointer + IN UINT64 PlaceHolder; ///< Place holder + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + } CALLBACK; + IN OUT UINT32 Reserved[2]; ///< This space is reserved for future use. +} AMD_CONFIG_PARAMS; + + +/// AGESA Binary module header structure +typedef struct _AMD_IMAGE_HEADER { + IN UINT32 Signature; ///< Binary Signature + IN CHAR8 CreatorID[8]; ///< 8 characters ID + IN CHAR8 Version[12]; ///< 12 characters version + IN UINT32 ModuleInfoOffset; ///< Offset of module + IN UINT32 EntryPointAddress; ///< Entry address + IN UINT32 ImageBase; ///< Image base + IN UINT32 RelocTableOffset; ///< Relocate Table offset + IN UINT32 ImageSize; ///< Size + IN UINT16 Checksum; ///< Checksum + IN UINT8 ImageType; ///< Type + IN UINT8 V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; + +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN UINT32 ModuleHeaderSignature; ///< Module signature + IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID + IN CHAR8 ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link +} AMD_MODULE_HEADER; + + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function (3-bits) +// 11:00 Offset (12-bits) + +#if 0 +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ + (((UINT32) (Dev)) << 15) | (((UINT32) (Fun)) << 12) | ((UINT32) (Off))) +#endif +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct _SB_CPUID_DATA { + IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX + IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX + IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX + IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX +} SB_CPUID_DATA; + +#define WARM_RESET 1 +#define COLD_RESET 2 // Cold reset +#define RESET_CPU 4 // Triggers a CPU reset + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks +} HT_FREQUENCIES; + +#ifndef BIT0 + #define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 + #define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 + #define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 + #define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 + #define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 + #define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 + #define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 + #define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 + #define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 + #define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 + #define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 + #define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 + #define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 + #define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 + #define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 + #define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 + #define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 + #define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 + #define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 + #define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 + #define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 + #define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 + #define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 + #define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 + #define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 + #define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 + #define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 + #define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 + #define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 + #define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 + #define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 + #define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 + #define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 + #define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 + #define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 + #define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 + #define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 + #define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 + #define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 + #define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 + #define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 + #define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 + #define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 + #define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 + #define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 + #define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 + #define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 + #define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 + #define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 + #define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 + #define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 + #define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 + #define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 + #define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 + #define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 + #define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 + #define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 + #define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 + #define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 + #define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 + #define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 + #define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 + #define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 + #define BIT63 0x8000000000000000ull +#endif +#endif Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,175 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _AMD_SB_LIB_H_ +#define _AMD_SB_LIB_H_ + +typedef CHAR8 *va_list; +#ifndef _INTSIZEOF + #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) +#endif + +// Also support coding convention rules for var arg macros +#ifndef va_start + #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) +#endif +#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) +#define va_end(ap) ( ap = (va_list)0 ) + + +#pragma pack (push, 1) + +#define IMAGE_ALIGN 32*1024 +#define NUM_IMAGE_LOCATION 32 + +//Entry Point Call +typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); + +//Hook Call + +typedef struct _CIMFILEHEADER +{ + UINT32 AMDLogo; + UINT64 CreatorID; + UINT32 Version1; + UINT32 Version2; + UINT32 Version3; + UINT32 ModuleInfoOffset; + UINT32 EntryPoint; + UINT32 ImageBase; + UINT32 RelocTableOffset; + UINT32 ImageSize; + UINT16 CheckSum; + UINT8 ImageType; + UINT8 Reserved2; +} CIMFILEHEADER; + +#ifndef BIT0 + #define BIT0 (1 << 0) +#endif +#ifndef BIT1 + #define BIT1 (1 << 1) +#endif +#ifndef BIT2 + #define BIT2 (1 << 2) +#endif +#ifndef BIT3 + #define BIT3 (1 << 3) +#endif +#ifndef BIT4 + #define BIT4 (1 << 4) +#endif +#ifndef BIT5 + #define BIT5 (1 << 5) +#endif +#ifndef BIT6 + #define BIT6 (1 << 6) +#endif +#ifndef BIT7 + #define BIT7 (1 << 7) +#endif +#ifndef BIT8 + #define BIT8 (1 << 8) +#endif +#ifndef BIT9 + #define BIT9 (1 << 9) +#endif +#ifndef BIT10 + #define BIT10 (1 << 10) +#endif +#ifndef BIT11 + #define BIT11 (1 << 11) +#endif +#ifndef BIT12 + #define BIT12 (1 << 12) +#endif +#ifndef BIT13 + #define BIT13 (1 << 13) +#endif +#ifndef BIT14 + #define BIT14 (1 << 14) +#endif +#ifndef BIT15 + #define BIT15 (1 << 15) +#endif +#ifndef BIT16 + #define BIT16 (1 << 16) +#endif +#ifndef BIT17 + #define BIT17 (1 << 17) +#endif +#ifndef BIT18 + #define BIT18 (1 << 18) +#endif +#ifndef BIT19 + #define BIT19 (1 << 19) +#endif +#ifndef BIT20 + #define BIT20 (1 << 20) +#endif +#ifndef BIT21 + #define BIT21 (1 << 21) +#endif +#ifndef BIT22 + #define BIT22 (1 << 22) +#endif +#ifndef BIT23 + #define BIT23 (1 << 23) +#endif +#ifndef BIT24 + #define BIT24 (1 << 24) +#endif +#ifndef BIT25 + #define BIT25 (1 << 25) +#endif +#ifndef BIT26 + #define BIT26 (1 << 26) +#endif +#ifndef BIT27 + #define BIT27 (1 << 27) +#endif +#ifndef BIT28 + #define BIT28 (1 << 28) +#endif +#ifndef BIT29 + #define BIT29 (1 << 29) +#endif +#ifndef BIT30 + #define BIT30 (1 << 30) +#endif +#ifndef BIT31 + #define BIT31 (1 << 31) +#endif + +#pragma pack (pop) + +typedef enum +{ + AccWidthUint8 = 0, + AccWidthUint16, + AccWidthUint32, +} ACC_WIDTH; + +#define S3_SAVE 0x80 + +#endif Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + + +if SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/cimx_wrapper/sb800/bootblock.c" +endif #SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 + Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,35 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-y += ../../../../../src/vendorcode/amd/cimx/sb800 +#TODO: merge with agesa lib function +subdirs-y += ../../../../../src/vendorcode/amd/cimx/lib + +# SB800 Platform Files + +romstage-y += sb800_cfg.c +romstage-y += sb800_early.c +romstage-y += sb800_smbus.c + +ramstage-y += sb800_cfg.c +ramstage-y += sb800_late.c + +driver-y += sb800_smbus.c +driver-y += sb800_lpc.c + Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,156 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ + +#include "cbtypes.h" +typedef UINT64 PLACEHOLDER; +#include "Amdlib.h" +#include "Amd.h" +#include "amdlib32.h"//TODO merge with agesa wrapper +#include "SB800.h" +#include "SBTYPE.h" +#include "ACPILIB.h" +#include "SBDEF.h" +#include "AMDSBLIB.h" +#include "SBSUBFUN.h" +#include "OEM.h" + +#ifdef NULL + #undef NULL +#endif +#define NULL 0 + +#ifndef SBOEM_ACPI_RESTORE_SWSMI + #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 + #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 +#endif + +#ifndef _AMD_NB_CIM_X_PROTOCOL_H_ + +/// Extended PCI Address +typedef struct _EXT_PCI_ADDR { + UINT32 Reg :16; ///< / PCI Register + UINT32 Func:3; ///< / PCI Function + UINT32 Dev :5; ///< / PCI Device + UINT32 Bus :8; ///< / PCI Address +} EXT_PCI_ADDR; + +/// PCI Address +typedef union _PCI_ADDR { + UINT32 ADDR; ///< / 32 bit Address + EXT_PCI_ADDR Addr; ///< / Extended PCI Address +} PCI_ADDR; +#endif + +#define FIXUP_PTR(ptr) ptr + + + + +//------------------------------------------------------------------------------------------------------------------------// +/** + * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over + * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable + * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal + * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable + * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) + * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable + * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) + * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable + * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable + * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable + * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable + * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable + * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable + * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable + * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable + * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable + * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable + * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) + * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) + * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz + * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable + * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable + * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable + * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable + * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable + * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable + * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable + * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable + * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable + * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable + * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable + * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable + * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable + */ +#define SB_CIMx_PARAMETER 0x02 + +// Generic +#define cimSpreadSpectrumDefault TRUE +#define cimSpreadSpectrumTypeDefault 0x00 // Normal +#define cimHpetTimerDefault TRUE +#define cimHpetMsiDisDefault FALSE // Enable +#define cimIrConfigDefault 0x00 // Disable +#define cimSpiFastReadEnableDefault 0x00 // Disable +#define cimSpiFastReadSpeedDefault 0x00 // NULL +// GPP/AB Controller +#define cimNbSbGen2Default TRUE +#define cimAlinkPhyPllPowerDownDefault TRUE +#define cimResetCpuOnSyncFloodDefault TRUE +#define cimGppGen2Default FALSE +#define cimGppMemWrImproveDefault TRUE +#define cimGppPortAspmDefault FALSE +#define cimGppLaneReversalDefault FALSE +#define cimGppPhyPllPowerDownDefault TRUE +// USB Controller +#define cimUsbPhyPowerDownDefault FALSE +// GEC Controller +#define cimSBGecDebugBusDefault FALSE +#define cimSBGecPwrDefault 0x03 +// Sata Controller +#define cimSataSetMaxGen2Default 0x00 +#define cimSATARefClkSelDefault 0x10 +#define cimSATARefDivSelDefault 0x80 +#define cimSataAggrLinkPmCapDefault TRUE +#define cimSataPortMultCapDefault TRUE +#define cimSataPscCapDefault 0x00 // Enable +#define cimSataSscCapDefault 0x00 // Enable +#define cimSataFisBasedSwitchingDefault FALSE +#define cimSataCccSupportDefault FALSE +#define cimSataClkAutoOffDefault FALSE +#define cimNativepciesupportDefault FALSE +// Fusion Related +#define cimAcDcMsgDefault FALSE +#define cimTimerTickTrackDefault FALSE +#define cimClockInterruptTagDefault FALSE +#define cimOhciTrafficHandingDefault FALSE +#define cimEhciTrafficHandingDefault FALSE +#define cimFusionMsgCMultiCoreDefault FALSE +#define cimFusionMsgCStageDefault FALSE + +#endif // _AMD_SBPLATFORM_H_ Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_SB_EARLY_H_ +#define _CIMX_SB_EARLY_H_ + +/** + * @brief Get SouthBridge device number, called by finalize_node_setup() + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus); + +/** + * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper. + */ +void sb_poweron_init(void); +//void sb_before_pci_init(void); + +#endif Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include + + +#if CONFIG_SERIAL_POST == 1 + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 + +#ifndef CONFIG_TTYS0_DIV +#if ((115200%CONFIG_TTYS0_BAUD) != 0) +#error Bad ttys0 baud rate +#endif +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#endif // CONFIG_TTYS0_DIV + +#define UART_LCS CONFIG_TTYS0_LCS + +#endif // CONFIG_SERIAL_POST == 1 + + +static void sb800_enable_rom(void) +{ + u32 word; + u32 dword; + device_t dev; + + dev = PCI_DEV(0, 0x14, 0x03); + /* SB800 LPC Bridge 0:20:3:44h. + * BIT6: Port Enable for serial port 0x3f8-0x3ff + * BIT29: Port Enable for KBC port 0x60 and 0x64 + * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 + */ + dword = pci_io_read_config32(dev, 0x44); + //dword |= (1<<6) | (1<<29) | (1<<30) ; + /*Turn on all of LPC IO Port decode enable */ + dword = 0xffffffff; + pci_io_write_config32(dev, 0x44, dword); + + /* SB800 LPC Bridge 0:20:3:48h. + * BIT0: Port Enable for SuperIO 0x2E-0x2F + * BIT1: Port Enable for SuperIO 0x4E-0x4F + * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) + * BIT6: Port Enable for RTC IO 0x70-0x73 + * BIT21: Port Enable for Port 0x80 + */ + dword = pci_io_read_config32(dev, 0x48); + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + pci_io_write_config32(dev, 0x48, dword); + + /* Enable 2MB rom access at 0xFFE00000 - 0xFFFFFFFF */ + /* Set the 2MB enable bits */ + word = pci_io_read_config16(dev, 0x6c); + word = 0xFFE0; + pci_io_write_config16(dev, 0x6c, word); +} + + +static void uart_init(void) +{ +#if CONFIG_SERIAL_POST == 1 + /* disable interrupts */ + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); + /* enable fifo's */ + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); + /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); +#endif // CONFIG_SERIAL_POST == 1 +} + + +static void bootblock_southbridge_init(void) +{ + /* Setup the rom access for 2M */ + sb800_enable_rom(); + uart_init(); +} Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/cbtypes.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cbtypes.h Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CBTYPES_H_ +#define _CBTYPES_H_ + +//#include + +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN; +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +#endif Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/chip.h Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CIMX_WRAPPER_SB800_CHIP_H_ +#define _CIMX_WRAPPER_SB800_CHIP_H_ + +extern struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops; + +/* + * configuration set in mainboard/devicetree.cb + * boot_switch_sata_ide: + * 0 -set SATA as primary, PATA(IDE) as secondary. + * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE, + * gpp_configuration - The configuration of General Purpose Port A/B/C/D + * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0] + * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2] + * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3 + * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 + */ +struct southbridge_amd_cimx_wrapper_sb800_config +{ + u32 boot_switch_sata_ide : 1; + u8 gpp_configuration; +}; + +#endif /* _CIMX_WRAPPER_SB800_CHIP_H_ */ Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = { + CHIP_NAME("AMD South Bridge SB800") +}; Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include "SBPLATFORM.h" +#include "sb800_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb800_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + return; + } + //memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* header */ + sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; + sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS; + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; + sb_config->BuildParameters.OhciSsid = OHCI_SSID; + sb_config->BuildParameters.EhciSsid = EHCI_SSID; + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; + sb_config->BuildParameters.IdeSsid = IDE_SSID; + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; + sb_config->BuildParameters.LpcSsid = LPC_SSID; + sb_config->BuildParameters.PCIBSsid = PCIB_SSID; + sb_config->BuildParameters.SpreadSpectrumType = Spread_Spectrum_Type; + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + + /* General */ + sb_config->SpreadSpectrum = SPREAD_SPECTRUM; + sb_config->PciClks = PCI_CLOCK_CTRL; + sb_config->HpetTimer = HPET_TIMER; + + /* USB */ + sb_config->USBMODE.UsbModeReg = USB_CINFIG; + sb_config->SbUsbPll = 0; + + /* SATA */ + sb_config->SataClass = SATA_MODE; + sb_config->SataIdeMode = SATA_IDE_MODE; + sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED; + sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; + sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. + //TODO: set to secondary not take effect. + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled + sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE; + + /* Azalia HDA */ + sb_config->AzaliaController = AZALIA_CONTROLLER; + sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; + sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN; + sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; + + /* + * GPP. default configure only enable port0 with 4 lanes, + * configure in devicetree.cb would overwrite the default configuration + */ + sb_config->GppFunctionEnable = GPP_CONTROLLER; + sb_config->GppLinkConfig = GPP_CFGMODE; + //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE; + sb_config->PORTCONFIG[0].PortCfg.PortPresent = ENABLED; + sb_config->PORTCONFIG[1].PortCfg.PortPresent = ENABLED; + sb_config->PORTCONFIG[2].PortCfg.PortPresent = ENABLED; + sb_config->PORTCONFIG[3].PortCfg.PortPresent = ENABLED; + sb_config->GppUnhidePorts = TRUE; //visable always, even port empty + //sb_config->NbSbGen2 = TRUE; + //sb_config->GppGen2 = TRUE; + + //cimx BTS fix + sb_config->GppMemWrImprove = TRUE; + sb_config->SbPcieOrderRule = TRUE; + sb_config->AlinkPhyPllPowerDown = TRUE; + sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving + sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06, PLATFORM.H default define 0x11 was wrong + sb_config->GecConfig = 0; //ENABLE GEC controller + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.CALLBACK.CalloutPtr) { + sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ +} + Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB800_CFG_H_ +#define _SB800_CFG_H_ + +#include + + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB800, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 + #define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 + #define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 + #define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 + #define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CINFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#ifndef SATA_CONTROLLER + #define SATA_CONTROLLER ENABLED +#endif + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_MODE + #define SATA_MODE NATIVE_IDE_MODE +#endif + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_IDE_MODE + #define SATA_IDE_MODE IDE_LEGACY_MODE +#endif + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +/* NOTE: inagua have to using internal clock, + * otherwise can not detect sata drive + */ +#define SATA_CLOCK_SOURCE INTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#ifndef AZALIA_CONTROLLER + #define AZALIA_CONTROLLER AZALIA_AUTO +#endif + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#ifndef AZALIA_PIN_CONFIG + #define AZALIA_PIN_CONFIG 1 +#endif + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +#ifndef AZALIA_SDIN_PIN + //#define AZALIA_SDIN_PIN 0xAA + #define AZALIA_SDIN_PIN 0x2A +#endif + +/** + * @def GPP_CONTROLLER + */ +#ifndef GPP_CONTROLLER + #define GPP_CONTROLLER ENABLED +#endif + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#ifndef GPP_CFGMODE + #define GPP_CFGMODE GPP_CFGMODE_X1111 +#endif + + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb800_cimx_config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb800_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +//#include +#include +#include +#include /* inl, outl */ +#include /* device_t */ +#include "SBPLATFORM.h" +#include "SbEarly.h" +#include "sb800_cfg.h" /*sb800_cimx_config*/ + + +/** + * @brief Get SouthBridge device number + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus) +{ + device_t dev; + + //dev = PCI_DEV(bus, 0x14, 0); + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM), + bus); + + return (dev >> 15) & 0x1f; +} + + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of sbPowerOnInit entry point. + */ +void sb_poweron_init(void) +{ + AMDSBCFG sb_early_cfg; + + sb800_cimx_config(&sb_early_cfg); + //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; + //AmdSbDispatcher(&sb_early_cfg); + //TODO + //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, + // VerifyImage() will fail, LocateImage() take minitues to find the image. + sbPowerOnInit(&sb_early_cfg); +} Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,436 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include /* device_t */ +#include /* device_operations */ +#include +#include /* smbus_bus_operations */ +#include /* printk */ +#include "sb800_lpc.h" /* lpc_read_resources */ +#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "sb800_cfg.h" /* sb800 Cimx configuration */ +#include "chip.h" /* struct southbridge_amd_cimx_wrapper_sb800_config */ + + +/*implement in mainboard.c*/ +//void set_pcie_assert(void); +//void set_pcie_deassert(void); +void set_pcie_reset(void); +void set_pcie_dereset(void); + + +#ifndef _RAMSTAGE_ +#define _RAMSTAGE_ +#endif +static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config +static AMDSBCFG *sb_config = &sb_late_cfg; + + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_config Southbridge configuration structure pointer. + * + */ +u32 sb800_callout_entry(u32 func, u32 data, void* config) +{ + u32 ret = 0; + + switch (func) { + case CB_SBGPP_RESET_ASSERT: + //set_pcie_assert(); + set_pcie_reset(); + break; + + case CB_SBGPP_RESET_DEASSERT: + //set_pcie_deassert(); + set_pcie_dereset(); + break; + + case IMC_FIRMWARE_FAIL: + break; + + default: + break; + } + + return ret; +} + + +static struct pci_operations lops_pci = { + .set_subsystem = 0, +}; + +static void lpc_enable_resources(device_t dev) +{ + + pci_dev_enable_resources(dev); + //lpc_enable_childrens_resources(dev); +} + +static void lpc_init(device_t dev) +{ + /* SB Configure HPET base and enable bit */ + hpetInit(sb_config, &(sb_config->BuildParameters)); +} + +static struct device_operations lpc_ops = { + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_LPC, +}; + + +static void sata_enable_resources(struct device *dev) +{ + sataInitAfterPciEnum(sb_config); + pci_dev_enable_resources(dev); +} + +static void sata_init(struct device *dev) +{ + sb_config->StdHeader.Func = SB_MID_POST_INIT; + AmdSbDispatcher(sb_config); //sataInitMidPost only + commonInitLateBoot(sb_config); + sataInitLatePost(sb_config); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = sata_enable_resources, //pci_dev_enable_resources, + .init = sata_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver sata_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode 4390 +}; + + +#if CONFIG_USBDEBUG +static void usb_set_resources(struct device *dev) +{ + struct resource *res; + u32 base; + u32 old_debug; + + old_debug = get_ehci_debug(); + set_ehci_debug(0); + + pci_dev_set_resources(dev); + + res = find_resource(dev, 0x10); + set_ehci_debug(old_debug); + if (!res) + return; + base = res->base; + set_ehci_base(base); + report_resource_stored(dev, res, ""); +} +#endif + +static void usb_init(struct device *dev) +{ + usbInitAfterPciInit(sb_config); + commonInitLateBoot(sb_config); +} + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, +#if CONFIG_USBDEBUG + .set_resources = usb_set_resources, +#else + .set_resources = pci_dev_set_resources, +#endif + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +/* + * The pci id of usb ctrl 0 and 1 are the same. + */ +static const struct pci_driver usb_ohci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ +}; + +static const struct pci_driver usb_ehci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ +}; + +static const struct pci_driver usb_ohci4_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ +}; + + +static void azalia_init(struct device *dev) +{ + azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio +} + +static struct device_operations azalia_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver azalia_driver __pci_driver = { + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_HDA, +}; + + +static void gec_init(struct device *dev) +{ + gecInitAfterPciEnum(sb_config); + gecInitLatePost(sb_config); + printk(BIOS_DEBUG, "gec hda enabled\n"); +} + +static struct device_operations gec_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gec_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver gec_driver __pci_driver = { + .ops = &gec_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_GEC, +}; + + +static void pcie_init(device_t dev) +{ + sbPcieGppLateInit(sb_config); +} + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_PCI, +}; + + +struct device_operations bridge_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, +}; + +/* 0:15:0 PCIe PortA */ +static const struct pci_driver PORTA_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_PCIEA, +}; + +/* 0:15:1 PCIe PortB */ +static const struct pci_driver PORTB_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_PCIEB, +}; + +/* 0:15:2 PCIe PortC */ +static const struct pci_driver PORTC_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_PCIEC, +}; + +/* 0:15:3 PCIe PortD */ +static const struct pci_driver PORTD_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_PCIED, +}; + + +/** + * @brief SB Cimx entry point sbBeforePciInit wrapper + */ +static void sb800_enable(device_t dev) +{ + u8 gpp_port = 0; + struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip = + (struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info); + + sb800_cimx_config(sb_config); + printk(BIOS_DEBUG, "sb800_enable() "); + + /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/ + commonInitEarlyBoot(sb_config); + commonInitEarlyPost(sb_config); + + switch (dev->path.pci.devfn) { + case (0x11 << 3) | 0: /* 0:11.0 SATA */ + if (dev->enabled) { + sb_config->SATAMODE.SataMode.SataController = ENABLED; + if (1 == sb_chip->boot_switch_sata_ide) + sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. + else if (0 == sb_chip->boot_switch_sata_ide) + sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. + } else { + sb_config->SATAMODE.SataMode.SataController = DISABLED; + } + + sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY + break; + + case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ + case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ + case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ + case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ + case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ + case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ + case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ + usbInitBeforePciEnum(sb_config); // USB POST TIME Only + break; + + case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ + break; + + case (0x14 << 3) | 1: /* 0:14:1 IDE */ + if (dev->enabled) { + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; + } else { + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; + } + sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY + break; + + case (0x14 << 3) | 2: /* 0:14:2 HDA */ + if (dev->enabled) { + if (AZALIA_DISABLE == sb_config->AzaliaController) { + sb_config->AzaliaController = AZALIA_AUTO; + } + printk(BIOS_DEBUG, "hda enabled\n"); + } else { + sb_config->AzaliaController = AZALIA_DISABLE; + printk(BIOS_DEBUG, "hda disabled\n"); + } + azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio + break; + + + case (0x14 << 3) | 3: /* 0:14:3 LPC */ + break; + + case (0x14 << 3) | 4: /* 0:14:4 PCI */ + break; + + case (0x14 << 3) | 6: /* 0:14:6 GEC */ + if (dev->enabled) { + sb_config->GecConfig = 0; + printk(BIOS_DEBUG, "gec enabled\n"); + } else { + sb_config->GecConfig = 1; + printk(BIOS_DEBUG, "gec disabled\n"); + } + gecInitBeforePciEnum(sb_config); // Init GEC + break; + + case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ + case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */ + case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */ + case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */ + gpp_port = (dev->path.pci.devfn) & 0x03; + if (dev->enabled) { + sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED; + } else { + sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED; + } + + /* + * GPP_CFGMODE_X4000: PortA Lanes[3:0] + * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] + * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 + * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 + */ + if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) { + sb_config->GppLinkConfig = sb_chip->gpp_configuration; + } + + sbPcieGppEarlyInit(sb_config); + break; + + default: + break; + } + + /* Special setting ABCFG registers before PCI emulation. */ + abSpecialSetBeforePciEnum(sb_config); + usbDesertPll(sb_config); + //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + //AmdSbDispatcher(sb_config); +} + +struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = { + CHIP_NAME("ATI SB800") + .enable_dev = sb800_enable, +}; Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "sb800_lpc.h" + + +void lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ + + pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */ + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + compact_resources(dev); +} + +void lpc_set_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_set_resources(dev); + + /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ + res = find_resource(dev, SPIROM_BASE_ADDRESS); + pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); + +} + +/** + * @brief Enable resources for children devices + * + * @param dev the device whos children's resources are to be enabled + * + */ +void lpc_enable_childrens_resources(device_t dev) +{ + struct bus *link; + u32 reg, reg_x; + int var_num = 0; + u16 reg_var[3]; + + reg = pci_read_config32(dev, 0x44); + reg_x = pci_read_config32(dev, 0x48); + + for (link = dev->link_list; link; link = link->next) { + device_t child; + for (child = link->children; child; + child = child->sibling) { + if (child->enabled + && (child->path.type == DEVICE_PATH_PNP)) { + struct resource *res; + for (res = child->resource_list; res; res = res->next) { + u32 base, end; /* don't need long long */ + if (!(res->flags & IORESOURCE_IO)) + continue; + base = res->base; + end = resource_end(res); +/* + printk(BIOS_DEBUG, "sb800 lpc decode:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); +*/ + switch (base) { + case 0x60: /* KB */ + case 0x64: /* MS */ + reg |= (1 << 29); + break; + case 0x3f8: /* COM1 */ + reg |= (1 << 6); + break; + case 0x2f8: /* COM2 */ + reg |= (1 << 7); + break; + case 0x378: /* Parallal 1 */ + reg |= (1 << 0); + break; + case 0x3f0: /* FD0 */ + reg |= (1 << 26); + break; + case 0x220: /* Aduio 0 */ + reg |= (1 << 8); + break; + case 0x300: /* Midi 0 */ + reg |= (1 << 18); + break; + case 0x400: + reg_x |= (1 << 16); + break; + case 0x480: + reg_x |= (1 << 17); + break; + case 0x500: + reg_x |= (1 << 18); + break; + case 0x580: + reg_x |= (1 << 19); + break; + case 0x4700: + reg_x |= (1 << 22); + break; + case 0xfd60: + reg_x |= (1 << 23); + break; + default: + if (var_num >= 3) + continue; /* only 3 var ; compact them ? */ + switch (var_num) { + case 0: + reg_x |= (1 << 2); + break; + case 1: + reg_x |= (1 << 24); + break; + case 2: + reg_x |= (1 << 25); + break; + } + reg_var[var_num++] = + base & 0xffff; + } + } + } + } + } + pci_write_config32(dev, 0x44, reg); + pci_write_config32(dev, 0x48, reg_x); + /* Set WideIO for as many IOs found (fall through is on purpose) */ + switch (var_num) { + case 2: + pci_write_config16(dev, 0x90, reg_var[2]); + case 1: + pci_write_config16(dev, 0x66, reg_var[1]); + case 0: + //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata + break; + } +} Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB800_LPC_H_ +#define _SB800_LPC_H_ + + +#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ + +void lpc_read_resources(device_t dev); +void lpc_set_resources(device_t dev); +void lpc_enable_childrens_resources(device_t dev); + +#endif Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include "sb800_smbus.h" + +static inline void smbus_delay(void) +{ + outb(inb(0x80), 0x80); +} + +static int smbus_wait_until_ready(u32 smbus_io_base) +{ + u32 loops; + + loops = SMBUS_TIMEOUT; + do { + u8 val; + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { /* ready now */ + return 0; + } + outb(val, smbus_io_base + SMBHSTSTAT); + } while (--loops); + + return -2; /* time out */ +} + +static int smbus_wait_until_done(u32 smbus_io_base) +{ + u32 loops; + + loops = SMBUS_TIMEOUT; + do { + u8 val; + + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; /* mask off reserved bits */ + if (val & 0x1c) { + return -5; /* error */ + } + if (val == 0x02) { + outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ + return 0; + } + } while (--loops); + + return -3; /* timeout */ +} + +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + return byte; +} + +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + return 0; +} + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + return byte; +} + +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + /* output value */ + outb(val, smbus_io_base + SMBHSTDAT0); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + return 0; +} + +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) +{ + u32 tmp; + + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} + +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) +{ + u32 tmp; + + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} + +/* space = 0: AX_INDXC, AX_DATAC + * space = 1: AX_INDXP, AX_DATAP + */ +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) +{ + u32 tmp; + + /* read axindc to tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} + Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h Sat Jan 1 18:52:34 2011 (r6230) @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB800_SMBUS_H_ +#define _SB800_SMBUS_H_ + +//#include + +#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 + +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc + +/*//SB00.H +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 +*/ + +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4) + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); + +#endif From svn at coreboot.org Sat Jan 1 19:04:45 2011 From: svn at coreboot.org (repository service) Date: Sat, 01 Jan 2011 19:04:45 +0100 Subject: [coreboot] [commit] r6231 - in trunk/src/mainboard/amd: . bimini_fam10 bimini_fam10/acpi Message-ID: Author: uwe Date: Sat Jan 1 19:04:42 2011 New Revision: 6231 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6231 Log: Add support for the AMD Bimini eval mainboard. Signed-off-by: Kerry She Acked-by: Stefan Reinauer Acked-by: Uwe Hermann Added: trunk/src/mainboard/amd/bimini_fam10/ trunk/src/mainboard/amd/bimini_fam10/Kconfig trunk/src/mainboard/amd/bimini_fam10/Makefile.inc trunk/src/mainboard/amd/bimini_fam10/acpi/ trunk/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl trunk/src/mainboard/amd/bimini_fam10/acpi/debug.asl trunk/src/mainboard/amd/bimini_fam10/acpi/globutil.asl trunk/src/mainboard/amd/bimini_fam10/acpi/ide.asl trunk/src/mainboard/amd/bimini_fam10/acpi/routing.asl trunk/src/mainboard/amd/bimini_fam10/acpi/sata.asl trunk/src/mainboard/amd/bimini_fam10/acpi/statdef.asl trunk/src/mainboard/amd/bimini_fam10/acpi/usb.asl trunk/src/mainboard/amd/bimini_fam10/acpi_tables.c trunk/src/mainboard/amd/bimini_fam10/chip.h trunk/src/mainboard/amd/bimini_fam10/cmos.layout trunk/src/mainboard/amd/bimini_fam10/devicetree.cb trunk/src/mainboard/amd/bimini_fam10/dsdt.asl trunk/src/mainboard/amd/bimini_fam10/fadt.c trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c trunk/src/mainboard/amd/bimini_fam10/irq_tables.c trunk/src/mainboard/amd/bimini_fam10/mainboard.c trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h trunk/src/mainboard/amd/bimini_fam10/mptable.c trunk/src/mainboard/amd/bimini_fam10/pmio.c trunk/src/mainboard/amd/bimini_fam10/pmio.h trunk/src/mainboard/amd/bimini_fam10/reset.c trunk/src/mainboard/amd/bimini_fam10/resourcemap.c trunk/src/mainboard/amd/bimini_fam10/romstage.c Modified: trunk/src/mainboard/amd/Kconfig Modified: trunk/src/mainboard/amd/Kconfig ============================================================================== --- trunk/src/mainboard/amd/Kconfig Sat Jan 1 18:52:34 2011 (r6230) +++ trunk/src/mainboard/amd/Kconfig Sat Jan 1 19:04:42 2011 (r6231) @@ -23,6 +23,8 @@ bool "Serengeti Cheetah (Fam10)" config BOARD_AMD_TILAPIA_FAM10 bool "Tilapia (Fam10)" +config BOARD_AMD_BIMINI_FAM10 + bool "Bimini (Fam10)" endchoice @@ -36,6 +38,7 @@ source "src/mainboard/amd/serengeti_cheetah/Kconfig" source "src/mainboard/amd/serengeti_cheetah_fam10/Kconfig" source "src/mainboard/amd/tilapia_fam10/Kconfig" +source "src/mainboard/amd/bimini_fam10/Kconfig" config MAINBOARD_VENDOR string Added: trunk/src/mainboard/amd/bimini_fam10/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/Kconfig Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,113 @@ +if BOARD_AMD_BIMINI_FAM10 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_ASB2 + select DIMM_DDR3 + select DIMM_REGISTERED + #select QRANK_DIMM_SUPPORT + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_AMD_RS780 + select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 + select SUPERIO_ITE_IT8718F + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select GENERATE_PIRQ_TABLE + select GENERATE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select CACHE_AS_RAM + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select GENERATE_ACPI_TABLES + select BOARD_ROMSIZE_KB_2048 + select RAMINIT_SYSINFO + select ENABLE_APIC_EXT_ID + select TINY_BOOTBLOCK + select GFXUMA + +config MAINBOARD_DIR + string + default amd/bimini_fam10 + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Bimini (Fam10)" + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x1 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config IRQ_SLOT_COUNT + int + default 11 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_010000b6.h" + +config RAMTOP + hex + default 0x2000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config ACPI_SSDTX_NUM + int + default 0 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x3060 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + +config RAMBASE + hex + default 0x200000 + +config COMPRESS + hex + default 0 + +endif #BOARD_AMD_BIMINI_FAM10 Added: trunk/src/mainboard/amd/bimini_fam10/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/Makefile.inc Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,7 @@ +#FIXME romstage have include test_rest.c +#romstage-y += reset.c +romstage-y += pmio.c + +ramstage-y += reset.c +ramstage-y += pmio.c + Added: trunk/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } Added: trunk/src/mainboard/amd/bimini_fam10/acpi/debug.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/acpi/debug.asl Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,198 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + DefinitionBlock ( + "DSDT.AML", + "DSDT", + 0x01, + "XXXXXX", + "XXXXXXXX", + 0x00010001 + ) + { + #include "debug.asl" + } +*/ + +/* +* 0x80: POST_BASE +* 0x3F8: DEBCOM_BASE +* X80: POST_REGION +* P80: PORT80 +* +* CREG: DEBCOM_REGION +* CUAR: DEBCOM_UART +* CDAT: DEBCOM_DATA +* CDLM: DEBCOM_DLM +* DLCR: DEBCOM_LCR +* CMCR: DEBCOM_MCR +* CLSR: DEBCOM_LSR +* +* DEBUG_INIT DINI +*/ + +OperationRegion(X80, SystemIO, 0x80, 1) + Field(X80, ByteAcc, NoLock, Preserve) +{ + P80, 8 +} + +OperationRegion(CREG, SystemIO, 0x3F8, 8) + Field(CREG, ByteAcc, NoLock, Preserve) +{ + CDAT, 8, + CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8 +} + +/* +* DINI +* Initialize the COM port to 115,200 8-N-1 +*/ +Method(DINI) +{ + store(0x83, DLCR) + store(0x01, CDAT) /* 115200 baud (low) */ + store(0x00, CDLM) /* 115200 baud (high) */ + store(0x03, DLCR) /* word=8 stop=1 parity=none */ + store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */ + store(0x00, CDLM) /* turn off interrupts */ +} + +/* +* THRE +* Wait for COM port transmitter holding register to go empty +*/ +Method(THRE) +{ + and(CLSR, 0x20, local0) + while (Lequal(local0, Zero)) { + and(CLSR, 0x20, local0) + } +} + +/* +* OUTX +* Send a single raw character +*/ +Method(OUTX, 1) +{ + THRE() + store(Arg0, CDAT) +} + +/* +* OUTC +* Send a single character, expanding LF into CR/LF +*/ +Method(OUTC, 1) +{ + if (LEqual(Arg0, 0x0a)) { + OUTX(0x0d) + } + OUTX(Arg0) +} + +/* +* DBGN +* Send a single hex nibble +*/ +Method(DBGN, 1) +{ + and(Arg0, 0x0f, Local0) + if (LLess(Local0, 10)) { + add(Local0, 0x30, Local0) + } else { + add(Local0, 0x37, Local0) + } + OUTC(Local0) +} + +/* +* DBGB +* Send a hex byte +*/ +Method(DBGB, 1) +{ + ShiftRight(Arg0, 4, Local0) + DBGN(Local0) + DBGN(Arg0) +} + +/* +* DBGW +* Send a hex word +*/ +Method(DBGW, 1) +{ + ShiftRight(Arg0, 8, Local0) + DBGB(Local0) + DBGB(Arg0) +} + +/* +* DBGD +* Send a hex Dword +*/ +Method(DBGD, 1) +{ + ShiftRight(Arg0, 16, Local0) + DBGW(Local0) + DBGW(Arg0) +} + +/* +* DBGO +* Send either a string or an integer +*/ +Method(DBGO, 1) +{ + /* DINI() */ + if (LEqual(ObjectType(Arg0), 1)) { + if (LGreater(Arg0, 0xffff)) { + DBGD(Arg0) + } else { + if (LGreater(Arg0, 0xff)) { + DBGW(Arg0) + } else { + DBGB(Arg0) + } + } + } else { + Name(BDBG, Buffer(80) {}) + store(Arg0, BDBG) + store(0, Local1) + while (One) { + store(GETC(BDBG, Local1), Local0) + if (LEqual(Local0, 0)) { + return (0) + } + OUTC(Local0) + Increment(Local1) + } + } + return (0) +} + +/* Get a char from a string */ +Method(GETC, 2) +{ + CreateByteField(Arg0, Arg1, DBGC) + return (DBGC) +} Added: trunk/src/mainboard/amd/bimini_fam10/acpi/globutil.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/acpi/globutil.asl Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope(\_SB) { + #include "globutil.asl" +} +*/ + +/* string compare functions */ +Method(MIN, 2) +{ + if (LLess(Arg0, Arg1)) { + Return(Arg0) + } else { + Return(Arg1) + } +} + +Method(SLEN, 1) +{ + Store(Arg0, Local0) + Return(Sizeof(Local0)) +} + +Method(S2BF, 1) +{ + Add(SLEN(Arg0), One, Local0) + Name(BUFF, Buffer(Local0) {}) + Store(Arg0, BUFF) + Return(BUFF) +} + +/* Strong string compare. Checks both length and content */ +Method(SCMP, 2) +{ + Store(S2BF(Arg0), Local0) + Store(S2BF(Arg1), Local1) + Store(Zero, Local4) + Store(SLEN(Arg0), Local5) + Store(SLEN(Arg1), Local6) + Store(MIN(Local5, Local6), Local7) + + While(LLess(Local4, Local7)) { + Store(Derefof(Index(Local0, Local4)), Local2) + Store(Derefof(Index(Local1, Local4)), Local3) + if (LGreater(Local2, Local3)) { + Return(One) + } else { + if (LLess(Local2, Local3)) { + Return(Ones) + } + } + Increment(Local4) + } + if (LLess(Local4, Local5)) { + Return(One) + } else { + if (LLess(Local4, Local6)) { + Return(Ones) + } else { + Return(Zero) + } + } +} + +/* Weak string compare. Checks to find Arg1 at beginning of Arg0. +* Fails if length(Arg0) < length(Arg1). Returns 0 on Fail, 1 on +* Pass. +*/ +Method(WCMP, 2) +{ + Store(S2BF(Arg0), Local0) + Store(S2BF(Arg1), Local1) + if (LLess(SLEN(Arg0), SLEN(Arg1))) { + Return(0) + } + Store(Zero, Local2) + Store(SLEN(Arg1), Local3) + + While(LLess(Local2, Local3)) { + if (LNotEqual(Derefof(Index(Local0, Local2)), + Derefof(Index(Local1, Local2)))) { + Return(0) + } + Increment(Local2) + } + Return(One) +} + +/* ARG0 = IRQ Number(0-15) +* Returns Bit Map +*/ +Method(I2BM, 1) +{ + Store(0, Local0) + if (LNotEqual(ARG0, 0)) { + Store(1, Local1) + ShiftLeft(Local1, ARG0, Local0) + } + Return(Local0) +} Added: trunk/src/mainboard/amd/bimini_fam10/acpi/ide.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/acpi/ide.asl Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} Added: trunk/src/mainboard/amd/bimini_fam10/acpi/routing.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/acpi/routing.asl Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,398 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, INTB, 0 }, */ + /* Package(){0x0005FFFF, 1, INTC, 0 }, */ + /* Package(){0x0005FFFF, 2, INTD, 0 }, */ + /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + Package(){0x0009FFFF, 0, INTB, 0 }, + Package(){0x0009FFFF, 1, INTC, 0 }, + Package(){0x0009FFFF, 2, INTD, 0 }, + Package(){0x0009FFFF, 3, INTA, 0 }, + + Package(){0x000AFFFF, 0, INTC, 0 }, + Package(){0x000AFFFF, 1, INTD, 0 }, + Package(){0x000AFFFF, 2, INTA, 0 }, + Package(){0x000AFFFF, 3, INTB, 0 }, + + Package(){0x000BFFFF, 0, INTD, 0 }, + Package(){0x000BFFFF, 1, INTA, 0 }, + Package(){0x000BFFFF, 2, INTB, 0 }, + Package(){0x000BFFFF, 3, INTC, 0 }, + + Package(){0x000CFFFF, 0, INTA, 0 }, + Package(){0x000CFFFF, 1, INTB, 0 }, + Package(){0x000CFFFF, 2, INTC, 0 }, + Package(){0x000CFFFF, 3, INTD, 0 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Package(){0x0014FFFF, 1, INTA, 0 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + package(){0x0001FFFF, 1, 0, 19 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* Package(){0x0004FFFF, 1, 0, 17 }, */ + /* Package(){0x0004FFFF, 2, 0, 18 }, */ + /* Package(){0x0004FFFF, 3, 0, 19 }, */ + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, 0, 17 }, */ + /* Package(){0x0005FFFF, 1, 0, 18 }, */ + /* Package(){0x0005FFFF, 2, 0, 19 }, */ + /* Package(){0x0005FFFF, 3, 0, 16 }, */ + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Package(){0x0006FFFF, 0, 0, 18 }, */ + /* Package(){0x0006FFFF, 1, 0, 19 }, */ + /* Package(){0x0006FFFF, 2, 0, 16 }, */ + /* Package(){0x0006FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Package(){0x0007FFFF, 0, 0, 19 }, */ + /* Package(){0x0007FFFF, 1, 0, 16 }, */ + /* Package(){0x0007FFFF, 2, 0, 17 }, */ + /* Package(){0x0007FFFF, 3, 0, 18 }, */ + + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, 0, 17 }, + /* Package(){0x0009FFFF, 1, 0, 16 }, */ + /* Package(){0x0009FFFF, 2, 0, 17 }, */ + /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, 0, 18 }, + /* Package(){0x000AFFFF, 1, 0, 16 }, */ + /* Package(){0x000AFFFF, 2, 0, 17 }, */ + /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + /* Package(){0x0012FFFF, 2, 0, 18 }, */ + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + /* Package(){0x0013FFFF, 2, 0, 16 }, */ + + /* Package(){0x00140000, 0, 0, 16 }, */ + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + + /* TODO: pcie */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, + }) +} Added: trunk/src/mainboard/amd/bimini_fam10/acpi/sata.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/acpi/sata.asl Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} Added: trunk/src/mainboard/amd/bimini_fam10/acpi/statdef.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/acpi/statdef.asl Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* Status and notification definitions */ + +#define STA_MISSING 0x00 +#define STA_PRESENT 0x01 +#define STA_ENABLED 0x03 +#define STA_DISABLED 0x09 +#define STA_INVISIBLE 0x0B +#define STA_UNAVAILABLE 0x0D +#define STA_VISIBLE 0x0F + +/* SMBus status codes */ +#define SMB_OK 0x00 +#define SMB_UnknownFail 0x07 +#define SMB_DevAddrNAK 0x10 +#define SMB_DeviceError 0x11 +#define SMB_DevCmdDenied 0x12 +#define SMB_UnknownErr 0x13 +#define SMB_DevAccDenied 0x17 +#define SMB_Timeout 0x18 +#define SMB_HstUnsuppProtocol 0x19 +#define SMB_Busy 0x1A +#define SMB_PktChkError 0x1F + +/* Device Object Notification Values */ +#define NOTIFY_BUS_CHECK 0x00 +#define NOTIFY_DEVICE_CHECK 0x01 +#define NOTIFY_DEVICE_WAKE 0x02 +#define NOTIFY_EJECT_REQUEST 0x03 +#define NOTIFY_DEVICE_CHECK_JR 0x04 +#define NOTIFY_FREQUENCY_ERROR 0x05 +#define NOTIFY_BUS_MODE 0x06 +#define NOTIFY_POWER_FAULT 0x07 +#define NOTIFY_CAPABILITIES 0x08 +#define NOTIFY_PLD_CHECK 0x09 +#define NOTIFY_SLIT_UPDATE 0x0B + +/* Battery Device Notification Values */ +#define NOTIFY_BAT_STATUSCHG 0x80 +#define NOTIFY_BAT_INFOCHG 0x81 +#define NOTIFY_BAT_MAINTDATA 0x82 + +/* Power Source Object Notification Values */ +#define NOTIFY_PWR_STATUSCHG 0x80 + +/* Thermal Zone Object Notification Values */ +#define NOTIFY_TZ_STATUSCHG 0x80 +#define NOTIFY_TZ_TRIPPTCHG 0x81 +#define NOTIFY_TZ_DEVLISTCHG 0x82 +#define NOTIFY_TZ_RELTBLCHG 0x83 + +/* Power Button Notification Values */ +#define NOTIFY_POWER_BUTTON 0x80 + +/* Sleep Button Notification Values */ +#define NOTIFY_SLEEP_BUTTON 0x80 + +/* Lid Notification Values */ +#define NOTIFY_LID_STATUSCHG 0x80 + +/* Processor Device Notification Values */ +#define NOTIFY_CPU_PPCCHG 0x80 +#define NOTIFY_CPU_CSTATECHG 0x81 +#define NOTIFY_CPU_THROTLCHG 0x82 + +/* User Presence Device Notification Values */ +#define NOTIFY_USR_PRESNCECHG 0x80 + +/* Battery Device Notification Values */ +#define NOTIFY_ALS_ILLUMCHG 0x80 +#define NOTIFY_ALS_COLORTMPCHG 0x81 +#define NOTIFY_ALS_RESPCHG 0x82 + + Added: trunk/src/mainboard/amd/bimini_fam10/acpi/usb.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/acpi/usb.asl Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} Added: trunk/src/mainboard/amd/bimini_fam10/acpi_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/acpi_tables.c Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mb_sysconf.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; +extern const unsigned char AmlCode_ssdt[]; + +#if CONFIG_ACPI_SSDTX_NUM >= 1 +extern const unsigned char AmlCode_ssdt2[]; +extern const unsigned char AmlCode_ssdt3[]; +extern const unsigned char AmlCode_ssdt4[]; +extern const unsigned char AmlCode_ssdt5[]; +#endif + +#define IO_APIC_ADDR 0xfec00000UL + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; +#if CONFIG_ACPI_SSDTX_NUM >= 1 + acpi_header_t *ssdtx; + void *p; + int i; +#endif + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)current; + memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt->length; + memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c + update_ssdt((void*)ssdt); + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + current = acpi_add_ssdt_pstates(rsdp, current); + +#if CONFIG_ACPI_SSDTX_NUM >= 1 + + /* same htio, but different position? We may have to copy, + change HCIN, and recalculate the checknum and add_table */ + + for(i=1;ilength; + memcpy(ssdtx, p, ssdtx->length); + update_ssdtx((void *)ssdtx, i); + ssdtx->checksum = 0; + ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); + acpi_add_table(rsdp, ssdtx); + } +#endif + + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FDAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} Added: trunk/src/mainboard/amd/bimini_fam10/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/chip.h Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; Added: trunk/src/mainboard/amd/bimini_fam10/cmos.layout ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/cmos.layout Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + Added: trunk/src/mainboard/amd/bimini_fam10/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/devicetree.cb Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,108 @@ + # sample config for amd/bimini_fam10 +chip northbridge/amd/amdfam10/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_ASB2 #L1 and DDR3 + device lapic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 off end # + register "gppsb_configuration" = "4" # Configuration E + register "gpp_configuration" = "2" # Configuration C + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 off end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 on end # Gec + device pci 15.0 on end # PCIe 0 + device pci 15.1 on end # PCIe 1 + device pci 15.2 on end # PCIe 2 + device pci 15.3 on end # PCIe 3 + device pci 16.0 on end # USB + device pci 16.2 on end # USB + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "gpp_configuration" = "4" + end #southbridge/amd/cimx_wrapper/sb800 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end + end #pci_domain + #for node 32 to node 63 +# device pci_domain 0 on +# chip northbridge/amd/amdfam10 +# device pci 00.0 on end# northbridge +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.1 on end +# device pci 00.2 on end +# device pci 00.3 on end +# device pci 00.4 on end +# device pci 00.5 on end +# end +# end #pci_domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # hard reset +# device pnp 0.9 off end # mcp55 +# device pnp 0.a on end # GH ext table +# end + +end Added: trunk/src/mainboard/amd/bimini_fam10/dsdt.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/dsdt.asl Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,1824 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "BIMINI ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x808, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU2, /* name space name */ + 2, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU3, /* name space name */ + 3, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PIRA) + Store(0, PIRB) + Store(0, PIRC) + Store(0, PIRD) + Store(0, PIRE) + Store(0, PIRF) + Store(0, PIRG) + Store(0, PIRH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PIRA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PIRB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PIRC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIRD) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PIRE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PIRF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PIRG) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PIRH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + Return (APR1) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge, not used in Herring */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* GPP */ + Device(PBR9) { + Name(_ADR, 0x00090000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR9 */ + + Device(PBRa) { + Name(_ADR, 0x000A0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRa */ + + Device(PE20) { + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x00, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x00, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x00, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x00, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#if 0 + Device(HPTM) { + Name(_HID,EISAID("PNP0103")) + Name(CRS,ResourceTemplate() { + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + }) + Method(_STA, 0) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0) { + CreateDwordField(CRS, ^HPT._BAS, HPBA) + Store(HPBA, HPBA) + Return(CRS) + } + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#endif + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) +#if 0 + Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ + + /* DRAM Memory from 1MB to TopMem */ + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + + /* BIOS space just below 4GB */ + DWORDMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000000, /* Max-Min, RLEN */ + ,, + PCBM + ) + + /* DRAM memory from 4GB to TopMem2 */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0xFFFFFFFF, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000000, /* Max-Min, RLEN */ + ,, + DMHI + ) + + /* BIOS space just below 16EB */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0xFFFFFFFF, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000000, /* Max-Min, RLEN */ + ,, + PEBM + ) +#endif + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ +#if 0 + CreateDWordField(CRES, ^EMM1._BAS, EM1B) + CreateDWordField(CRES, ^EMM1._LEN, EM1L) + CreateDWordField(CRES, ^DMLO._BAS, DMLB) + CreateDWordField(CRES, ^DMLO._LEN, DMLL) + CreateDWordField(CRES, ^PCBM._MIN, PBMB) + CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateQWordField(CRES, ^DMHI._MIN, DMHB) + CreateQWordField(CRES, ^DMHI._LEN, DMHL) + CreateQWordField(CRES, ^PEBM._MIN, EBMB) + CreateQWordField(CRES, ^PEBM._LEN, EBML) + + If(LGreater(LOMH, 0xC0000)){ + Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ + Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ + } + + /* Set size of memory from 1MB to TopMem */ + Subtract(TOM1, 0x100000, DMLL) + + /* + * If(LNotEqual(TOM2, 0x00000000)){ + * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 + * Subtract(TOM2, 0x100000000, DMHL) + * } + */ + + /* If there is no memory above 4GB, put the BIOS just below 4GB */ + If(LEqual(TOM2, 0x00000000)){ + Store(PBAD,PBMB) /* Reserve the "BIOS" space */ + Store(PBLN,PBML) + } + Else { /* Otherwise, put the BIOS just below 16EB */ + ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ + Store(PBLN,EBML) + } +#endif + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ +#if 0 + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +#endif +} +/* End of ASL file */ Added: trunk/src/mainboard/amd/bimini_fam10/fadt.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/fadt.c Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + +#include +#include +#include +#include +#include +#include "pmio.h" + +/*extern*/ u16 pm_base = 0x800; +/* pm_base should be set in sb acpi */ +/* pm_base should be got from bar2 of rs780. Here I compact ACPI + * registers into 32 bytes limit. + * */ + +#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */ +#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */ + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + pm_base &= 0xFFFF; + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); + pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); + pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF); + pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8); + pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF); + pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8); + pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF); + pm_iowrite(0x69, ACPI_GPE0_BLK >> 8); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF); + pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8); + + pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ + pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ + + pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF); + pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8); + + pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses + * the contents of the PM registers at + * index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); +} Added: trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#if CONFIG_LOGICAL_CPUS==1 +#include +#endif + +#include + +/* Global variables for MB layouts and these will be shared by irqtable mptable +* and acpi_tables busnum is default. +*/ +int bus_isa; +u8 bus_rs780[11]; +u8 bus_sb800[3]; +u32 apicid_sb800; + +/* +* Here you only need to set value in pci1234 for HT-IO that could be installed or not +* You may need to preset pci1234 for HTIO board, +* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +*/ +u32 pci1234x[] = { + 0x0000ff0, +}; + +/* +* HT Chain device num, actually it is unit id base of every ht device in chain, +* assume every chain only have 4 ht device at most +*/ +u32 hcdnx[] = { + 0x20202020, +}; + +u32 bus_type[256]; + +u32 sbdn_rs780; +u32 sbdn_sb800; + +extern void get_pci1234(void); + +static u32 get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + u32 apicid_base; + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + get_bus_conf_done = 1; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); + sbdn_rs780 = sysconf.sbdn; + sbdn_sb800 = 0; + + for (i = 0; i < 3; i++) { + bus_sb800[i] = 0; + } + for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) { + bus_rs780[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb800[0] = bus_rs780[0]; + + bus_type[bus_rs780[0]] = 1; + + /* sb800 */ + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + if (dev) { + bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb800[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x15, i)); + if (dev) { + bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_sb800[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* rs780 */ + for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) { + dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0)); + if (dev) { + bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_rs780[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_rs780[i]] = 1; /* PCI bus. */ + } + } + } + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(1); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + apicid_sb800 = apicid_base + 0; +} Added: trunk/src/mainboard/amd/bimini_fam10/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/irq_tables.c Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +#include + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_rs780[8]; +extern u8 bus_sb800[2]; +extern unsigned long sbdn_sb800; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb800[0]; + pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} Added: trunk/src/mainboard/amd/bimini_fam10/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/mainboard.c Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include "pmio.h" +#include "chip.h" + + +uint64_t uma_memory_base, uma_memory_size; + +u8 is_dev3_present(void); +void set_pcie_dereset(void); +void set_pcie_reset(void); +void enable_int_gfx(void); + +/* GPIO6. */ +void enable_int_gfx(void) +{ + u8 byte; + + volatile u8 *gpio_reg; + + pm_iowrite(0xEA, 0x01); /* diable the PCIB */ + /* Disable Gec */ + byte = pm_ioread(0xF6); + byte |= 1; + pm_iowrite(0xF6, byte); + /* make sure the fed80000 is accessible */ + byte = pm_ioread(0x24); + byte |= 1; + pm_iowrite(0x24, byte); + + gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */ + + *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ + *(gpio_reg + 170) = 0x1; /* gpio_gate */ + + gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */ + + *(gpio_reg + 0x6) = 0x8; + *(gpio_reg + 170) = 0x0; +} + +/* + * Bimini uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to + * pull it up before training the slot. + ***/ +void set_pcie_dereset(void) +{ + /* GPIO 50h reset PCIe slot */ +/* + u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50); + u8 byte = ~(1 << 5); + byte |= ~(1 << 6); + *addr = byte; +*/ +} + +void set_pcie_reset(void) +{ + /* GPIO 50h reset PCIe slot */ +/* + u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50); + u8 byte = ~((1 << 5) | (1 << 6)); + *addr = byte; +*/ +} + +u8 is_dev3_present(void) +{ + return 0; +} +#if 0 /* not tested yet. */ +/******************************************************** +* bimini uses SB800 GPIO9 to detect IDE_DMA66. +* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to +* get the cable type, 40 pin or 80 pin? +********************************************************/ +static void get_ide_dma66(void) +{ + u8 byte; + /*u32 sm_dev, ide_dev; */ + device_t sm_dev, ide_dev; + + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + + byte = pci_read_config8(sm_dev, 0xA9); + byte |= (1 << 5); /* Set Gpio9 as input */ + pci_write_config8(sm_dev, 0xA9, byte); + + ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + byte = pci_read_config8(ide_dev, 0x56); + byte &= ~(7 << 0); + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) + byte |= 2 << 0; /* mode 2 */ + else + byte |= 5 << 0; /* mode 5 */ + pci_write_config8(ide_dev, 0x56, byte); +} +#endif /* get_ide_dma66() */ + +/************************************************* +* enable the dedicated function in bimini board. +* This function called early than rs780_enable. +*************************************************/ +static void bimini_enable(device_t dev) +{ + /* Leave it for furture use. */ + /* struct mainboard_config *mainboard = + (struct mainboard_config *)dev->chip_info; */ + + printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev); + +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in 780 BDG. */ + switch (msr.lo) { + case 0x10000000: /* 256M system memory */ + uma_memory_size = 0x4000000; /* 64M recommended UMA */ + break; + + case 0x20000000: /* 512M system memory */ + uma_memory_size = 0x8000000; /* 128M recommended UMA */ + break; + + default: /* 1GB and above system memory */ + uma_memory_size = 0x10000000; /* 256M recommended UMA */ + break; + } + + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 0x8000000; /* 128M recommended UMA */ + uma_memory_base = 0x38000000; /* 1GB system memory supposed */ +#endif + + set_pcie_dereset(); + enable_int_gfx(); + /* get_ide_dma66(); */ +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, + uma_memory_size); +#endif + return 0; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("AMD BIMINI Mainboard") + .enable_dev = bimini_enable, +}; Added: trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MB_SYSCONF_H + +#define MB_SYSCONF_H + +struct mb_sysconf_t { + u8 bus_isa; + u8 bus_8132_0; + u8 bus_8132_1; + u8 bus_8132_2; + u8 bus_8111_0; + u8 bus_8111_1; + u8 bus_8132a[31][3]; + u8 bus_8151[31][2]; + + u32 apicid_8111; + u32 apicid_8132_1; + u32 apicid_8132_2; + u32 apicid_8132a[31][2]; + u32 sbdn3; + u32 sbdn3a[31]; + u32 sbdn5[31]; + u32 bus_type[256]; +}; + +#endif + Added: trunk/src/mainboard/amd/bimini_fam10/mptable.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/mptable.c Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,180 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include +#include "pmio.h" + +#include + +extern int bus_isa; +extern u8 bus_rs780[11]; +extern u8 bus_sb800[2]; + +extern u32 apicid_sb800; + +extern u32 bus_type[256]; +extern u32 sbdn_rs780; +extern u32 sbdn_sb800; + +u8 intr_data[] = { + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "COREBOOT"; + static const char productid[12] = "BIMINI "; + struct mp_config_table *mc; + u32 dword; + u8 byte; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + + dword = 0; + dword = pm_ioread(0x34) & 0xF0; + dword |= (pm_ioread(0x35) & 0xFF) << 8; + dword |= (pm_ioread(0x36) & 0xFF) << 16; + dword |= (pm_ioread(0x37) & 0xFF) << 24; + smp_write_ioapic(mc, apicid_sb800, 0x11, dword); + + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#if CONFIG_GENERATE_ACPI_TABLES == 0 +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) +#else +#define PCI_INT(bus, dev, fn, pin) +#endif + + PCI_INT(0x0, 0x14, 0x0, 0x10); + /* HD Audio: */ + PCI_INT(0x0, 0x14, 0x2, 0x12); + + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ +/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ + PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */ + /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ + PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); + /* configuration B doesnt need dev 5,6,7 */ + /* + * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); + * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); + * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); + */ + PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); + PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = + smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Added: trunk/src/mainboard/amd/bimini_fam10/pmio.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/pmio.c Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include /*inb, outb*/ +#include "pmio.h" + +static void pmio_write_index(u16 port_base, u8 reg, u8 value) +{ + outb(reg, port_base); + outb(value, port_base + 1); +} + +static u8 pmio_read_index(u16 port_base, u8 reg) +{ + outb(reg, port_base); + return inb(port_base + 1); +} + +void pm_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM_INDEX, reg, value); +} + +u8 pm_ioread(u8 reg) +{ + return pmio_read_index(PM_INDEX, reg); +} + +void pm2_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM2_INDEX, reg, value); +} + +u8 pm2_ioread(u8 reg) +{ + return pmio_read_index(PM2_INDEX, reg); +} + Added: trunk/src/mainboard/amd/bimini_fam10/pmio.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/pmio.h Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _PMIO_H_ +#define _PMIO_H_ + +#define PM_INDEX 0xCD6 +#define PM_DATA 0xCD7 +#define PM2_INDEX 0xCD0 +#define PM2_DATA 0xCD1 + +void pm_iowrite(u8 reg, u8 value); +u8 pm_ioread(u8 reg); +void pm2_iowrite(u8 reg, u8 value); +u8 pm2_ioread(u8 reg); + +#endif Added: trunk/src/mainboard/amd/bimini_fam10/reset.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/reset.c Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + Added: trunk/src/mainboard/amd/bimini_fam10/resourcemap.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/resourcemap.c Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,281 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + + +static void setup_mb_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +} + Added: trunk/src/mainboard/amd/bimini_fam10/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/amd/bimini_fam10/romstage.c Sat Jan 1 19:04:42 2011 (r6231) @@ -0,0 +1,262 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +//#define SYSTEM_TYPE 0 /* SERVER */ +#define SYSTEM_TYPE 1 /* DESKTOP */ +//#define SYSTEM_TYPE 2 /* MOBILE */ + +#define CACHE_AS_RAM_ADDRESS_DEBUG 1 + +#define SET_NB_CFG_54 1 + +//used by raminit +#define QRANK_DIMM_SUPPORT 1 + +//used by incoherent_ht +#define FAM10_SCAN_PCI_BUS 0 +#define FAM10_ALLOCATE_IO_RANGE 0 + +//used by init_cpus and fidvid +#define SET_FIDVID 1 +#define SET_FIDVID_CORE_RANGE 0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "northbridge/amd/amdfam10/raminit.h" +#include "northbridge/amd/amdfam10/amdfam10.h" + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdfam10/reset_test.c" + +#include +#include "cpu/x86/bist.h" + +#include "cpu/x86/mtrr/earlymtrr.c" +#include +#include "northbridge/amd/amdfam10/setup_resource_map.c" + +#include "southbridge/amd/rs780/early_setup.c" +#include +#include /* SB OEM constants */ +#include +#include "northbridge/amd/amdfam10/debug.c" + + +static void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +static int spd_read_byte(u32 device, u32 address) +{ + int result; + result = do_smbus_read_byte(SMBUS_IO_BASE, device, address); + return result; +} + + +#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" +#include "northbridge/amd/amdfam10/pci.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" +#include "cpu/amd/model_10xxx/init_cpus.c" + +#include "northbridge/amd/amdfam10/early_ht.c" + +#define RC00 0 +#define RC01 1 + +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 + +#include +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; + u32 bsp_apicid = 0; + u32 val; + msr_t msr; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + /* mov bsp to bus 0xff when > 8 nodes */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + //enable port80 decoding and southbridge poweron init + sb_poweron_init(); + SbStall(200); //wait 200us, bimini must wait otherwise need to reset. + } + + post_code(0x30); + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ + /* All cores run this but the BSP(node0,core0) is the only core that returns. */ + } + + post_code(0x32); + + enable_rs780_dev8(); + + uart_init(); + console_init(); + printk(BIOS_DEBUG, "\n"); + +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); + + update_microcode(val); + post_code(0x33); + + cpuSetAMDMSR(); + post_code(0x34); + + amd_ht_init(sysinfo); + post_code(0x35); + + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + + /* wait for all the APs core0 started by finalize_node_setup. */ + /* FIXME: A bunch of cores are going to start output to serial at once. + It would be nice to fixup prink spinlocks for ROM XIP mode. + I think it could be done by putting the spinlock flag in the cache + of the BSP located right after sysinfo. + */ + wait_all_core0_started(); + + #if CONFIG_LOGICAL_CPUS==1 + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif + + post_code(0x38); + + /* run _early_setup before soft-reset. */ + rs780_early_setup(); + + #if SET_FIDVID == 1 + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + + /* FIXME: The sb fid change may survive the warm reset and only + need to be done once.*/ + //enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + + post_code(0x39); + + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + + post_code(0x3A); + + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + #endif + + rs780_htinit(); + + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + post_code(0x3B); + + /* It's the time to set ctrl in sysinfo now; */ + printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + post_code(0x40); + +// die("Die Before MCT init."); + + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); + post_code(0x41); + +/* + dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); + dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); + dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); + dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); +*/ + +// ram_check(0x00200000, 0x00200000 + (640 * 1024)); +// ram_check(0x40200000, 0x40200000 + (640 * 1024)); + +// die("After MCT init before CAR disabled."); + + rs780_before_pci_init(); + + post_code(0x42); + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. + post_code(0x43); // Should never see this post code. +} From svn at coreboot.org Sat Jan 1 19:10:07 2011 From: svn at coreboot.org (repository service) Date: Sat, 01 Jan 2011 19:10:07 +0100 Subject: [coreboot] [commit] r6232 - in trunk/src/mainboard/amd/bimini_fam10: . acpi Message-ID: Author: uwe Date: Sat Jan 1 19:10:07 2011 New Revision: 6232 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6232 Log: AMD Bimini: Drop duplicate ASL files as we did for other boards. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Deleted: trunk/src/mainboard/amd/bimini_fam10/acpi/debug.asl trunk/src/mainboard/amd/bimini_fam10/acpi/globutil.asl trunk/src/mainboard/amd/bimini_fam10/acpi/statdef.asl Modified: trunk/src/mainboard/amd/bimini_fam10/dsdt.asl Modified: trunk/src/mainboard/amd/bimini_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/dsdt.asl Sat Jan 1 19:04:42 2011 (r6231) +++ trunk/src/mainboard/amd/bimini_fam10/dsdt.asl Sat Jan 1 19:10:07 2011 (r6232) @@ -27,7 +27,7 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ From svn at coreboot.org Sat Jan 1 19:40:04 2011 From: svn at coreboot.org (repository service) Date: Sat, 01 Jan 2011 19:40:04 +0100 Subject: [coreboot] [commit] r6233 - trunk/src/mainboard/amd/bimini_fam10 Message-ID: Author: uwe Date: Sat Jan 1 19:40:02 2011 New Revision: 6233 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6233 Log: AMD Bimini: Small fixes, and updates to recent trunk conventions. - Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed to HAVE_DEBUG_CAR in r5898. - Move QRANK_DIMM_SUPPORT to Kconfig, see r6028. - Drop obsolete/unused COMPRESS, see r6145. - Drop obsolete SET_NB_CFG_54, see r6086. - Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077. Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it. - Rename some GENERATE_* options to HAVE_*, see r6027. - Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151. - Drop ACPI_SSDTX_NUM, the global default is 0 already. - Random whitespace and coding style fixes. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/src/mainboard/amd/bimini_fam10/Kconfig trunk/src/mainboard/amd/bimini_fam10/chip.h trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c trunk/src/mainboard/amd/bimini_fam10/irq_tables.c trunk/src/mainboard/amd/bimini_fam10/mainboard.c trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h trunk/src/mainboard/amd/bimini_fam10/mptable.c trunk/src/mainboard/amd/bimini_fam10/pmio.c trunk/src/mainboard/amd/bimini_fam10/pmio.h trunk/src/mainboard/amd/bimini_fam10/reset.c trunk/src/mainboard/amd/bimini_fam10/resourcemap.c trunk/src/mainboard/amd/bimini_fam10/romstage.c Modified: trunk/src/mainboard/amd/bimini_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/Kconfig Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/Kconfig Sat Jan 1 19:40:02 2011 (r6233) @@ -6,7 +6,9 @@ select CPU_AMD_SOCKET_ASB2 select DIMM_DDR3 select DIMM_REGISTERED - #select QRANK_DIMM_SUPPORT + # TODO: Enable QRANK_DIMM_SUPPORT? Was commented in the Kconfig file, + # but enabled in the romstage.c file. + select QRANK_DIMM_SUPPORT select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 @@ -14,21 +16,22 @@ select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE - select GENERATE_PIRQ_TABLE - select GENERATE_MP_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES - select CACHE_AS_RAM select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT select AMDMCT - select GENERATE_ACPI_TABLES + select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA + select HAVE_DEBUG_CAR + select SET_FIDVID config MAINBOARD_DIR string @@ -90,10 +93,6 @@ hex default 0xc0000 -config ACPI_SSDTX_NUM - int - default 0 - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x3060 @@ -106,8 +105,4 @@ hex default 0x200000 -config COMPRESS - hex - default 0 - endif #BOARD_AMD_BIMINI_FAM10 Modified: trunk/src/mainboard/amd/bimini_fam10/chip.h ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/chip.h Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/chip.h Sat Jan 1 19:40:02 2011 (r6233) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - extern struct chip_operations mainboard_ops; struct mainboard_config {}; Modified: trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c Sat Jan 1 19:40:02 2011 (r6233) @@ -26,7 +26,6 @@ #if CONFIG_LOGICAL_CPUS==1 #include #endif - #include /* Global variables for MB layouts and these will be shared by irqtable mptable Modified: trunk/src/mainboard/amd/bimini_fam10/irq_tables.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/irq_tables.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/irq_tables.c Sat Jan 1 19:40:02 2011 (r6233) @@ -22,10 +22,8 @@ #include #include #include - #include - static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, @@ -44,6 +42,7 @@ pirq_info->slot = slot; pirq_info->rfu = rfu; } + extern u8 bus_isa; extern u8 bus_rs780[8]; extern u8 bus_sb800[2]; Modified: trunk/src/mainboard/amd/bimini_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/mainboard.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/mainboard.c Sat Jan 1 19:40:02 2011 (r6233) @@ -29,7 +29,6 @@ #include "pmio.h" #include "chip.h" - uint64_t uma_memory_base, uma_memory_size; u8 is_dev3_present(void); @@ -94,6 +93,7 @@ { return 0; } + #if 0 /* not tested yet. */ /******************************************************** * bimini uses SB800 GPIO9 to detect IDE_DMA66. @@ -195,6 +195,6 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD BIMINI Mainboard") + CHIP_NAME("AMD Bimini Mainboard") .enable_dev = bimini_enable, }; Modified: trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h Sat Jan 1 19:40:02 2011 (r6233) @@ -18,7 +18,6 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -38,8 +37,7 @@ u32 sbdn3; u32 sbdn3a[31]; u32 sbdn5[31]; - u32 bus_type[256]; + u32 bus_type[256]; }; #endif - Modified: trunk/src/mainboard/amd/bimini_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/mptable.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/mptable.c Sat Jan 1 19:40:02 2011 (r6233) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include #include #include @@ -25,15 +24,12 @@ #include #include #include "pmio.h" - #include extern int bus_isa; extern u8 bus_rs780[11]; extern u8 bus_sb800[2]; - extern u32 apicid_sb800; - extern u32 bus_type[256]; extern u32 sbdn_rs780; extern u32 sbdn_sb800; Modified: trunk/src/mainboard/amd/bimini_fam10/pmio.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/pmio.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/pmio.c Sat Jan 1 19:40:02 2011 (r6233) @@ -17,8 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#include /*inb, outb*/ +#include #include "pmio.h" static void pmio_write_index(u16 port_base, u8 reg, u8 value) @@ -52,4 +51,3 @@ { return pmio_read_index(PM2_INDEX, reg); } - Modified: trunk/src/mainboard/amd/bimini_fam10/pmio.h ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/pmio.h Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/pmio.h Sat Jan 1 19:40:02 2011 (r6233) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #ifndef _PMIO_H_ #define _PMIO_H_ Modified: trunk/src/mainboard/amd/bimini_fam10/reset.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/reset.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/reset.c Sat Jan 1 19:40:02 2011 (r6233) @@ -17,10 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include -#include /*inb, outb*/ -#include /*pci_read_config32, device_t, PCI_DEV*/ +#include +#include #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) @@ -33,13 +32,12 @@ static inline void set_bios_reset(void) { - u32 nodes; - u32 htic; + u32 nodes, htic; device_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; @@ -63,4 +61,3 @@ /* link reset */ outb(0x06, 0x0cf9); } - Modified: trunk/src/mainboard/amd/bimini_fam10/resourcemap.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/resourcemap.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/resourcemap.c Sat Jan 1 19:40:02 2011 (r6233) @@ -17,8 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -278,4 +276,3 @@ max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } - Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/romstage.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/romstage.c Sat Jan 1 19:40:02 2011 (r6233) @@ -21,21 +21,10 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 - -#define SET_NB_CFG_54 1 - -//used by raminit -#define QRANK_DIMM_SUPPORT 1 - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include #include #include @@ -48,47 +37,36 @@ #include #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" - #include #include "cpu/x86/bist.h" - #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" - #include "southbridge/amd/rs780/early_setup.c" #include #include /* SB OEM constants */ #include #include "northbridge/amd/amdfam10/debug.c" - static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) { - int result; - result = do_smbus_read_byte(SMBUS_IO_BASE, device, address); - return result; + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } - #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" - #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" - #include "northbridge/amd/amdfam10/early_ht.c" #define RC00 0 @@ -110,11 +88,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { @@ -183,20 +159,20 @@ */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); - #endif +#endif post_code(0x38); /* run _early_setup before soft-reset. */ rs780_early_setup(); - #if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); From svn at coreboot.org Sat Jan 1 19:58:40 2011 From: svn at coreboot.org (repository service) Date: Sat, 01 Jan 2011 19:58:40 +0100 Subject: [coreboot] [commit] r6234 - trunk/src/mainboard/amd/bimini_fam10 Message-ID: Author: uwe Date: Sat Jan 1 19:58:39 2011 New Revision: 6234 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6234 Log: AMD Bimini: Use mptable_init() in mptable.c. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/src/mainboard/amd/bimini_fam10/mptable.c Modified: trunk/src/mainboard/amd/bimini_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/mptable.c Sat Jan 1 19:40:02 2011 (r6233) +++ trunk/src/mainboard/amd/bimini_fam10/mptable.c Sat Jan 1 19:58:39 2011 (r6234) @@ -46,29 +46,13 @@ static void *smp_write_config_table(void *v) { - static const char sig[4] = "PCMP"; - static const char oem[8] = "COREBOOT"; - static const char productid[12] = "BIMINI "; struct mp_config_table *mc; u32 dword; u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - memset(mc, 0, sizeof(*mc)); - memcpy(mc->mpc_signature, sig, sizeof(sig)); - mc->mpc_length = sizeof(*mc); /* initially just the header */ - mc->mpc_spec = 0x04; - mc->mpc_checksum = 0; /* not yet computed */ - memcpy(mc->mpc_oem, oem, sizeof(oem)); - memcpy(mc->mpc_productid, productid, sizeof(productid)); - mc->mpc_oemptr = 0; - mc->mpc_oemsize = 0; - mc->mpc_entry_count = 0; /* No entries yet... */ - mc->mpc_lapic = LAPIC_ADDR; - mc->mpe_length = 0; - mc->mpe_checksum = 0; - mc->reserved = 0; + mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); From darmawan.salihun at gmail.com Sat Jan 1 21:37:24 2011 From: darmawan.salihun at gmail.com (Darmawan Salihun) Date: Sun, 2 Jan 2011 03:37:24 +0700 Subject: [coreboot] IDE interface support code for AMDLX800-CS5536 Message-ID: Hi guys, I'm looking for the support code for the IDE controller in CS5536 southbridge. I checked-out Coreboot source code but only saw Flash interface support in there. I saw the IDE controller is switched to Flash interface support with the "DEADBEEF" magic number. The board I'm working with right now use the primary IDE channel for both HDD connectors and a CF connectors. I need to know how to initialize the chipset correctly for this setup. The CF connector is the primary master and the HDD connector is primary slave. I've checked with lspci and " cat /proc/ioports" and I found that the legacy I/O ports for IDE controller is working just fine. Also, the I/O ports for IDE bus mastering (SFF-8038i) registers are allocated correctly. Thanks, Darmawan -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =- From darmawan.salihun at gmail.com Sat Jan 1 21:38:47 2011 From: darmawan.salihun at gmail.com (Darmawan Salihun) Date: Sun, 2 Jan 2011 03:38:47 +0700 Subject: [coreboot] IDE interface support code for AMDLX800-CS5536 In-Reply-To: References: Message-ID: > On 1/2/11, Darmawan Salihun wrote: > Hi guys, > > I'm looking for the support code for the IDE controller in CS5536 > southbridge. > I checked-out Coreboot source code but only saw Flash interface > support in there. > I saw the IDE controller is switched to Flash interface support with > the "DEADBEEF" > magic number. > > The board I'm working with right now use the primary IDE channel for both > HDD connectors and a CF connectors. I need to know how to initialize > the chipset > correctly for this setup. The CF connector is the primary master and > the HDD connector is primary slave. > > I've checked with lspci and " cat /proc/ioports" and I found that the > legacy I/O ports > for IDE controller is working just fine. Also, the I/O ports for > IDE bus mastering (SFF-8038i) registers are allocated correctly. > I mean with the current code that I tested the I/O ports allocation is just fine. > Thanks, > > Darmawan > -- > -------------------------------------------------------------------- > -= Human knowledge belongs to the world =- > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =- From svn at coreboot.org Sat Jan 1 23:05:58 2011 From: svn at coreboot.org (repository service) Date: Sat, 01 Jan 2011 23:05:58 +0100 Subject: [coreboot] [commit] r6235 - trunk/util/superiotool Message-ID: Author: uwe Date: Sat Jan 1 23:05:57 2011 New Revision: 6235 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6235 Log: Add detection support for the ITE IT8721F. Tested on hardware by me. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/util/superiotool/ite.c Modified: trunk/util/superiotool/ite.c ============================================================================== --- trunk/util/superiotool/ite.c Sat Jan 1 19:58:39 2011 (r6234) +++ trunk/util/superiotool/ite.c Sat Jan 1 23:05:57 2011 (r6235) @@ -605,6 +605,8 @@ {EOT}}}, {0x8720, "IT8720F", { /* From sensors-detect */ {EOT}}}, + {0x8721, "IT8721F", { + {EOT}}}, {0x8722, "IT8722F", { {EOT}}}, {0x8726, "IT8726F", { From svn at coreboot.org Sun Jan 2 00:30:38 2011 From: svn at coreboot.org (repository service) Date: Sun, 02 Jan 2011 00:30:38 +0100 Subject: [coreboot] [commit] r6236 - in trunk/src: mainboard/amd/bimini_fam10 southbridge/amd/cimx_wrapper/sb800 Message-ID: Author: uwe Date: Sun Jan 2 00:30:37 2011 New Revision: 6236 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6236 Log: AMD SB800: Drop component prefix from filenames. We did the same with other chipsets in r6150. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h trunk/src/southbridge/amd/cimx_wrapper/sb800/early.c - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.c - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.h - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.c - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.h - copied unchanged from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h Deleted: trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/romstage.c Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/mainboard/amd/bimini_fam10/romstage.c Sun Jan 2 00:30:37 2011 (r6236) @@ -47,7 +47,7 @@ #include "southbridge/amd/rs780/early_setup.c" #include #include /* SB OEM constants */ -#include +#include #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) @@ -193,7 +193,7 @@ /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); - #endif +#endif rs780_htinit(); Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sun Jan 2 00:30:37 2011 (r6236) @@ -35,20 +35,15 @@ * */ - #ifndef _AMD_H_ #define _AMD_H_ -// -// // AGESA Types and Definitions -// -// + #ifndef NULL #define NULL 0 #endif - #define LAST_ENTRY 0xFFFFFFFF #define IOCF8 0xCF8 #define IOCFC 0xCFC @@ -58,7 +53,6 @@ typedef UINTN AGESA_STATUS; - #define AGESA_SUCCESS ((AGESA_STATUS) 0x0) #define AGESA_ALERT ((AGESA_STATUS) 0x40000000) #define AGESA_WARNING ((AGESA_STATUS) 0x40000001) @@ -131,7 +125,6 @@ IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link } AMD_MODULE_HEADER; - #define FUNC_0 0 // bit-placed for PCI address creation #define FUNC_1 1 #define FUNC_2 2 @@ -378,4 +371,5 @@ #ifndef BIT63 #define BIT63 0x8000000000000000ull #endif + #endif Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sun Jan 2 00:30:37 2011 (r6236) @@ -36,7 +36,6 @@ #define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) #define va_end(ap) ( ap = (va_list)0 ) - #pragma pack (push, 1) #define IMAGE_ALIGN 32*1024 Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig Sun Jan 2 00:30:37 2011 (r6236) @@ -17,10 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## - if SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 + config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx_wrapper/sb800/bootblock.c" -endif #SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 + string + default "southbridge/amd/cimx_wrapper/sb800/bootblock.c" + +endif Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc Sun Jan 2 00:30:37 2011 (r6236) @@ -23,13 +23,13 @@ # SB800 Platform Files -romstage-y += sb800_cfg.c -romstage-y += sb800_early.c -romstage-y += sb800_smbus.c +romstage-y += cfg.c +romstage-y += early.c +romstage-y += smbus.c -ramstage-y += sb800_cfg.c -ramstage-y += sb800_late.c +ramstage-y += cfg.c +ramstage-y += late.c -driver-y += sb800_smbus.c -driver-y += sb800_lpc.c +driver-y += smbus.c +driver-y += lpc.c Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sun Jan 2 00:30:37 2011 (r6236) @@ -24,18 +24,18 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -#include "cbtypes.h" +#include typedef UINT64 PLACEHOLDER; -#include "Amdlib.h" -#include "Amd.h" -#include "amdlib32.h"//TODO merge with agesa wrapper -#include "SB800.h" -#include "SBTYPE.h" -#include "ACPILIB.h" -#include "SBDEF.h" -#include "AMDSBLIB.h" -#include "SBSUBFUN.h" -#include "OEM.h" +#include +#include +#include //TODO merge with agesa wrapper +#include +#include +#include +#include +#include +#include +#include #ifdef NULL #undef NULL @@ -66,9 +66,6 @@ #define FIXUP_PTR(ptr) ptr - - - //------------------------------------------------------------------------------------------------------------------------// /** * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h Sun Jan 2 00:30:37 2011 (r6236) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #ifndef _CIMX_SB_EARLY_H_ #define _CIMX_SB_EARLY_H_ Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c Sun Jan 2 00:30:37 2011 (r6236) @@ -17,11 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include #include - #if CONFIG_SERIAL_POST == 1 /* Data */ @@ -53,7 +51,6 @@ #endif // CONFIG_SERIAL_POST == 1 - static void sb800_enable_rom(void) { u32 word; @@ -90,7 +87,6 @@ pci_io_write_config16(dev, 0x6c, word); } - static void uart_init(void) { #if CONFIG_SERIAL_POST == 1 @@ -106,7 +102,6 @@ #endif // CONFIG_SERIAL_POST == 1 } - static void bootblock_southbridge_init(void) { /* Setup the rom access for 2M */ Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c Sun Jan 2 00:30:37 2011 (r6236) @@ -17,10 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#include "SBPLATFORM.h" -#include "sb800_cfg.h" - +#include +#include /** * @brief South Bridge CIMx configuration @@ -124,4 +122,3 @@ //sb_config-> #endif //!__PRE_RAM__ } - Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h Sun Jan 2 00:30:37 2011 (r6236) @@ -17,13 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #ifndef _SB800_CFG_H_ #define _SB800_CFG_H_ #include - /** * @def BIOS_SIZE_1M * @def BIOS_SIZE_2M @@ -150,7 +148,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. @@ -218,10 +215,8 @@ #define GPP_CFGMODE GPP_CFGMODE_X1111 #endif - /** * @brief South Bridge CIMx configuration - * */ void sb800_cimx_config(AMDSBCFG *sb_cfg); @@ -233,7 +228,6 @@ * @param[in] func Southbridge CIMx Function ID. * @param[in] data Southbridge Input Data. * @param[in] sb_cfg Southbridge configuration structure pointer. - * */ u32 sb800_callout_entry(u32 func, u32 data, void* sb_cfg); Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c Sun Jan 2 00:30:37 2011 (r6236) @@ -21,5 +21,5 @@ #include "chip.h" struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = { - CHIP_NAME("AMD South Bridge SB800") + CHIP_NAME("AMD SB800 Southbridge") }; Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/early.c (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/early.c Sun Jan 2 00:30:37 2011 (r6236) @@ -17,16 +17,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - //#include #include #include -#include /* inl, outl */ -#include /* device_t */ -#include "SBPLATFORM.h" -#include "SbEarly.h" -#include "sb800_cfg.h" /*sb800_cimx_config*/ - +#include +#include +#include +#include +#include /** * @brief Get SouthBridge device number @@ -45,7 +43,6 @@ return (dev >> 15) & 0x1f; } - /** * @brief South Bridge CIMx romstage entry, * wrapper of sbPowerOnInit entry point. Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Sun Jan 2 00:30:37 2011 (r6236) @@ -17,17 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#include /* device_t */ -#include /* device_operations */ +#include +#include #include -#include /* smbus_bus_operations */ -#include /* printk */ -#include "sb800_lpc.h" /* lpc_read_resources */ -#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ -#include "sb800_cfg.h" /* sb800 Cimx configuration */ -#include "chip.h" /* struct southbridge_amd_cimx_wrapper_sb800_config */ - +#include +#include +#include +#include +#include +#include "chip.h" /*implement in mainboard.c*/ //void set_pcie_assert(void); @@ -35,14 +33,13 @@ void set_pcie_reset(void); void set_pcie_dereset(void); - #ifndef _RAMSTAGE_ #define _RAMSTAGE_ #endif + static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config static AMDSBCFG *sb_config = &sb_late_cfg; - /** * @brief Entry point of Southbridge CIMx callout * @@ -78,14 +75,12 @@ return ret; } - static struct pci_operations lops_pci = { .set_subsystem = 0, }; static void lpc_enable_resources(device_t dev) { - pci_dev_enable_resources(dev); //lpc_enable_childrens_resources(dev); } @@ -111,7 +106,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_LPC, }; - static void sata_enable_resources(struct device *dev) { sataInitAfterPciEnum(sb_config); @@ -141,7 +135,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode 4390 }; - #if CONFIG_USBDEBUG static void usb_set_resources(struct device *dev) { @@ -225,7 +218,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_HDA, }; - static void gec_init(struct device *dev) { gecInitAfterPciEnum(sb_config); @@ -248,7 +240,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_GEC, }; - static void pcie_init(device_t dev) { sbPcieGppLateInit(sb_config); @@ -270,7 +261,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_PCI, }; - struct device_operations bridge_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -310,7 +300,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_PCIED, }; - /** * @brief SB Cimx entry point sbBeforePciInit wrapper */ Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.c (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.c Sun Jan 2 00:30:37 2011 (r6236) @@ -18,8 +18,7 @@ */ #include -#include "sb800_lpc.h" - +#include void lpc_read_resources(device_t dev) { @@ -60,7 +59,6 @@ /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ res = find_resource(dev, SPIROM_BASE_ADDRESS); pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); - } /** Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.h (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.h Sun Jan 2 00:30:37 2011 (r6236) @@ -20,7 +20,6 @@ #ifndef _SB800_LPC_H_ #define _SB800_LPC_H_ - #define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.c (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.c Sun Jan 2 00:30:37 2011 (r6236) @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include -#include "sb800_smbus.h" +#include static inline void smbus_delay(void) { @@ -248,4 +247,3 @@ outl(tmp, AB_DATA); outl(0, AB_INDX); } - Copied: trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.h (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.h Sun Jan 2 00:30:37 2011 (r6236, copy of r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h) @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB800_SMBUS_H_ +#define _SB800_SMBUS_H_ + +//#include + +#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 + +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc + +/*//SB00.H +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 +*/ + +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4) + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); + +#endif From svn at coreboot.org Sun Jan 2 00:36:04 2011 From: svn at coreboot.org (repository service) Date: Sun, 02 Jan 2011 00:36:04 +0100 Subject: [coreboot] [commit] r6237 - in trunk/src/southbridge/amd/cimx_wrapper: . sb800 Message-ID: Author: uwe Date: Sun Jan 2 00:36:03 2011 New Revision: 6237 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6237 Log: src/southbridge/amd/cimx_wrapper: Run dos2unix on the files. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/src/southbridge/amd/cimx_wrapper/Kconfig trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Modified: trunk/src/southbridge/amd/cimx_wrapper/Kconfig ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/Kconfig Sun Jan 2 00:30:37 2011 (r6236) +++ trunk/src/southbridge/amd/cimx_wrapper/Kconfig Sun Jan 2 00:36:03 2011 (r6237) @@ -16,14 +16,15 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -# + config SOUTHBRIDGE_AMD_CIMX_WRAPPER - bool - default n + bool + default n config SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 - bool - select IOAPIC - select SOUTHBRIDGE_AMD_CIMX_WRAPPER + bool + select IOAPIC + select SOUTHBRIDGE_AMD_CIMX_WRAPPER source src/southbridge/amd/cimx_wrapper/sb800/Kconfig + Modified: trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc Sun Jan 2 00:30:37 2011 (r6236) +++ trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc Sun Jan 2 00:36:03 2011 (r6237) @@ -16,4 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800) += sb800 + Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sun Jan 2 00:30:37 2011 (r6236) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sun Jan 2 00:36:03 2011 (r6237) @@ -1,375 +1,375 @@ -/***************************************************************************** - * AMD Generic Encapsulated Software Architecture */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA/CIMx core interface - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision:$ @e \$Date:$ - */ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _AMD_H_ -#define _AMD_H_ - -// AGESA Types and Definitions - -#ifndef NULL - #define NULL 0 -#endif - -#define LAST_ENTRY 0xFFFFFFFF -#define IOCF8 0xCF8 -#define IOCFC 0xCFC -#define IN -#define OUT -#define IMAGE_SIGNATURE 'DMA$' - -typedef UINTN AGESA_STATUS; - -#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) -#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) -#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) -#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) -#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) -#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) -#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) - -typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); -typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); -typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); - -///This allocation type is used by the AmdCreateStruct entry point -typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. -} ALLOCATION_METHOD; - -/// These width descriptors are used by the library function, and others, to specify the data size -typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. - - AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. -} ACCESS_WIDTH; - -// AGESA Structures - -/// The standard header for all AGESA services. -typedef struct _AMD_CONFIG_PARAMS { - IN UINT32 ImageBasePtr; ///< The AGESA Image base address. - IN UINT32 Func; ///< The service desired, @sa dispatch.h. - IN UINT32 AltImageBasePtr; ///< Alternate Image location - IN UINT32 PcieBasePtr; ///< PCIe MMIO Base address, if configured. - union { ///< Callback pointer - IN UINT64 PlaceHolder; ///< Place holder - IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA - } CALLBACK; - IN OUT UINT32 Reserved[2]; ///< This space is reserved for future use. -} AMD_CONFIG_PARAMS; - - -/// AGESA Binary module header structure -typedef struct _AMD_IMAGE_HEADER { - IN UINT32 Signature; ///< Binary Signature - IN CHAR8 CreatorID[8]; ///< 8 characters ID - IN CHAR8 Version[12]; ///< 12 characters version - IN UINT32 ModuleInfoOffset; ///< Offset of module - IN UINT32 EntryPointAddress; ///< Entry address - IN UINT32 ImageBase; ///< Image base - IN UINT32 RelocTableOffset; ///< Relocate Table offset - IN UINT32 ImageSize; ///< Size - IN UINT16 Checksum; ///< Checksum - IN UINT8 ImageType; ///< Type - IN UINT8 V_Reserved; ///< Reserved -} AMD_IMAGE_HEADER; - -/// AGESA Binary module header structure -typedef struct _AMD_MODULE_HEADER { - IN UINT32 ModuleHeaderSignature; ///< Module signature - IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID - IN CHAR8 ModuleVersion[12]; ///< 12 characters version - IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link -} AMD_MODULE_HEADER; - -#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 - -// SBDFO - Segment Bus Device Function Offset -// 31:28 Segment (4-bits) -// 27:20 Bus (8-bits) -// 19:15 Device (5-bits) -// 14:12 Function (3-bits) -// 11:00 Offset (12-bits) - -#if 0 -#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ - (((UINT32) (Dev)) << 15) | (((UINT32) (Fun)) << 12) | ((UINT32) (Off))) -#endif -#define ILLEGAL_SBDFO 0xFFFFFFFF - -/// CPUID data received registers format -typedef struct _SB_CPUID_DATA { - IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX - IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX - IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX - IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX -} SB_CPUID_DATA; - -#define WARM_RESET 1 -#define COLD_RESET 2 // Cold reset -#define RESET_CPU 4 // Triggers a CPU reset - -/// HT frequency for external callbacks -typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks -} HT_FREQUENCIES; - -#ifndef BIT0 - #define BIT0 0x0000000000000001ull -#endif -#ifndef BIT1 - #define BIT1 0x0000000000000002ull -#endif -#ifndef BIT2 - #define BIT2 0x0000000000000004ull -#endif -#ifndef BIT3 - #define BIT3 0x0000000000000008ull -#endif -#ifndef BIT4 - #define BIT4 0x0000000000000010ull -#endif -#ifndef BIT5 - #define BIT5 0x0000000000000020ull -#endif -#ifndef BIT6 - #define BIT6 0x0000000000000040ull -#endif -#ifndef BIT7 - #define BIT7 0x0000000000000080ull -#endif -#ifndef BIT8 - #define BIT8 0x0000000000000100ull -#endif -#ifndef BIT9 - #define BIT9 0x0000000000000200ull -#endif -#ifndef BIT10 - #define BIT10 0x0000000000000400ull -#endif -#ifndef BIT11 - #define BIT11 0x0000000000000800ull -#endif -#ifndef BIT12 - #define BIT12 0x0000000000001000ull -#endif -#ifndef BIT13 - #define BIT13 0x0000000000002000ull -#endif -#ifndef BIT14 - #define BIT14 0x0000000000004000ull -#endif -#ifndef BIT15 - #define BIT15 0x0000000000008000ull -#endif -#ifndef BIT16 - #define BIT16 0x0000000000010000ull -#endif -#ifndef BIT17 - #define BIT17 0x0000000000020000ull -#endif -#ifndef BIT18 - #define BIT18 0x0000000000040000ull -#endif -#ifndef BIT19 - #define BIT19 0x0000000000080000ull -#endif -#ifndef BIT20 - #define BIT20 0x0000000000100000ull -#endif -#ifndef BIT21 - #define BIT21 0x0000000000200000ull -#endif -#ifndef BIT22 - #define BIT22 0x0000000000400000ull -#endif -#ifndef BIT23 - #define BIT23 0x0000000000800000ull -#endif -#ifndef BIT24 - #define BIT24 0x0000000001000000ull -#endif -#ifndef BIT25 - #define BIT25 0x0000000002000000ull -#endif -#ifndef BIT26 - #define BIT26 0x0000000004000000ull -#endif -#ifndef BIT27 - #define BIT27 0x0000000008000000ull -#endif -#ifndef BIT28 - #define BIT28 0x0000000010000000ull -#endif -#ifndef BIT29 - #define BIT29 0x0000000020000000ull -#endif -#ifndef BIT30 - #define BIT30 0x0000000040000000ull -#endif -#ifndef BIT31 - #define BIT31 0x0000000080000000ull -#endif -#ifndef BIT32 - #define BIT32 0x0000000100000000ull -#endif -#ifndef BIT33 - #define BIT33 0x0000000200000000ull -#endif -#ifndef BIT34 - #define BIT34 0x0000000400000000ull -#endif -#ifndef BIT35 - #define BIT35 0x0000000800000000ull -#endif -#ifndef BIT36 - #define BIT36 0x0000001000000000ull -#endif -#ifndef BIT37 - #define BIT37 0x0000002000000000ull -#endif -#ifndef BIT38 - #define BIT38 0x0000004000000000ull -#endif -#ifndef BIT39 - #define BIT39 0x0000008000000000ull -#endif -#ifndef BIT40 - #define BIT40 0x0000010000000000ull -#endif -#ifndef BIT41 - #define BIT41 0x0000020000000000ull -#endif -#ifndef BIT42 - #define BIT42 0x0000040000000000ull -#endif -#ifndef BIT43 - #define BIT43 0x0000080000000000ull -#endif -#ifndef BIT44 - #define BIT44 0x0000100000000000ull -#endif -#ifndef BIT45 - #define BIT45 0x0000200000000000ull -#endif -#ifndef BIT46 - #define BIT46 0x0000400000000000ull -#endif -#ifndef BIT47 - #define BIT47 0x0000800000000000ull -#endif -#ifndef BIT48 - #define BIT48 0x0001000000000000ull -#endif -#ifndef BIT49 - #define BIT49 0x0002000000000000ull -#endif -#ifndef BIT50 - #define BIT50 0x0004000000000000ull -#endif -#ifndef BIT51 - #define BIT51 0x0008000000000000ull -#endif -#ifndef BIT52 - #define BIT52 0x0010000000000000ull -#endif -#ifndef BIT53 - #define BIT53 0x0020000000000000ull -#endif -#ifndef BIT54 - #define BIT54 0x0040000000000000ull -#endif -#ifndef BIT55 - #define BIT55 0x0080000000000000ull -#endif -#ifndef BIT56 - #define BIT56 0x0100000000000000ull -#endif -#ifndef BIT57 - #define BIT57 0x0200000000000000ull -#endif -#ifndef BIT58 - #define BIT58 0x0400000000000000ull -#endif -#ifndef BIT59 - #define BIT59 0x0800000000000000ull -#endif -#ifndef BIT60 - #define BIT60 0x1000000000000000ull -#endif -#ifndef BIT61 - #define BIT61 0x2000000000000000ull -#endif -#ifndef BIT62 - #define BIT62 0x4000000000000000ull -#endif -#ifndef BIT63 - #define BIT63 0x8000000000000000ull -#endif - -#endif +/***************************************************************************** + * AMD Generic Encapsulated Software Architecture */ +/** + * @file + * + * Agesa structures and definitions + * + * Contains AMD AGESA/CIMx core interface + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e \$Revision:$ @e \$Date:$ + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +// AGESA Types and Definitions + +#ifndef NULL + #define NULL 0 +#endif + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + +// AGESA Structures + +/// The standard header for all AGESA services. +typedef struct _AMD_CONFIG_PARAMS { + IN UINT32 ImageBasePtr; ///< The AGESA Image base address. + IN UINT32 Func; ///< The service desired, @sa dispatch.h. + IN UINT32 AltImageBasePtr; ///< Alternate Image location + IN UINT32 PcieBasePtr; ///< PCIe MMIO Base address, if configured. + union { ///< Callback pointer + IN UINT64 PlaceHolder; ///< Place holder + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + } CALLBACK; + IN OUT UINT32 Reserved[2]; ///< This space is reserved for future use. +} AMD_CONFIG_PARAMS; + + +/// AGESA Binary module header structure +typedef struct _AMD_IMAGE_HEADER { + IN UINT32 Signature; ///< Binary Signature + IN CHAR8 CreatorID[8]; ///< 8 characters ID + IN CHAR8 Version[12]; ///< 12 characters version + IN UINT32 ModuleInfoOffset; ///< Offset of module + IN UINT32 EntryPointAddress; ///< Entry address + IN UINT32 ImageBase; ///< Image base + IN UINT32 RelocTableOffset; ///< Relocate Table offset + IN UINT32 ImageSize; ///< Size + IN UINT16 Checksum; ///< Checksum + IN UINT8 ImageType; ///< Type + IN UINT8 V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; + +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN UINT32 ModuleHeaderSignature; ///< Module signature + IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID + IN CHAR8 ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link +} AMD_MODULE_HEADER; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function (3-bits) +// 11:00 Offset (12-bits) + +#if 0 +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ + (((UINT32) (Dev)) << 15) | (((UINT32) (Fun)) << 12) | ((UINT32) (Off))) +#endif +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct _SB_CPUID_DATA { + IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX + IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX + IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX + IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX +} SB_CPUID_DATA; + +#define WARM_RESET 1 +#define COLD_RESET 2 // Cold reset +#define RESET_CPU 4 // Triggers a CPU reset + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks +} HT_FREQUENCIES; + +#ifndef BIT0 + #define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 + #define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 + #define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 + #define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 + #define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 + #define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 + #define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 + #define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 + #define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 + #define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 + #define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 + #define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 + #define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 + #define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 + #define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 + #define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 + #define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 + #define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 + #define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 + #define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 + #define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 + #define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 + #define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 + #define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 + #define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 + #define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 + #define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 + #define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 + #define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 + #define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 + #define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 + #define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 + #define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 + #define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 + #define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 + #define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 + #define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 + #define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 + #define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 + #define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 + #define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 + #define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 + #define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 + #define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 + #define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 + #define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 + #define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 + #define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 + #define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 + #define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 + #define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 + #define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 + #define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 + #define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 + #define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 + #define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 + #define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 + #define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 + #define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 + #define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 + #define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 + #define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 + #define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 + #define BIT63 0x8000000000000000ull +#endif + +#endif Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sun Jan 2 00:30:37 2011 (r6236) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sun Jan 2 00:36:03 2011 (r6237) @@ -1,174 +1,174 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _AMD_SB_LIB_H_ -#define _AMD_SB_LIB_H_ - -typedef CHAR8 *va_list; -#ifndef _INTSIZEOF - #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) -#endif - -// Also support coding convention rules for var arg macros -#ifndef va_start - #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) -#endif -#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) -#define va_end(ap) ( ap = (va_list)0 ) - -#pragma pack (push, 1) - -#define IMAGE_ALIGN 32*1024 -#define NUM_IMAGE_LOCATION 32 - -//Entry Point Call -typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); - -//Hook Call - -typedef struct _CIMFILEHEADER -{ - UINT32 AMDLogo; - UINT64 CreatorID; - UINT32 Version1; - UINT32 Version2; - UINT32 Version3; - UINT32 ModuleInfoOffset; - UINT32 EntryPoint; - UINT32 ImageBase; - UINT32 RelocTableOffset; - UINT32 ImageSize; - UINT16 CheckSum; - UINT8 ImageType; - UINT8 Reserved2; -} CIMFILEHEADER; - -#ifndef BIT0 - #define BIT0 (1 << 0) -#endif -#ifndef BIT1 - #define BIT1 (1 << 1) -#endif -#ifndef BIT2 - #define BIT2 (1 << 2) -#endif -#ifndef BIT3 - #define BIT3 (1 << 3) -#endif -#ifndef BIT4 - #define BIT4 (1 << 4) -#endif -#ifndef BIT5 - #define BIT5 (1 << 5) -#endif -#ifndef BIT6 - #define BIT6 (1 << 6) -#endif -#ifndef BIT7 - #define BIT7 (1 << 7) -#endif -#ifndef BIT8 - #define BIT8 (1 << 8) -#endif -#ifndef BIT9 - #define BIT9 (1 << 9) -#endif -#ifndef BIT10 - #define BIT10 (1 << 10) -#endif -#ifndef BIT11 - #define BIT11 (1 << 11) -#endif -#ifndef BIT12 - #define BIT12 (1 << 12) -#endif -#ifndef BIT13 - #define BIT13 (1 << 13) -#endif -#ifndef BIT14 - #define BIT14 (1 << 14) -#endif -#ifndef BIT15 - #define BIT15 (1 << 15) -#endif -#ifndef BIT16 - #define BIT16 (1 << 16) -#endif -#ifndef BIT17 - #define BIT17 (1 << 17) -#endif -#ifndef BIT18 - #define BIT18 (1 << 18) -#endif -#ifndef BIT19 - #define BIT19 (1 << 19) -#endif -#ifndef BIT20 - #define BIT20 (1 << 20) -#endif -#ifndef BIT21 - #define BIT21 (1 << 21) -#endif -#ifndef BIT22 - #define BIT22 (1 << 22) -#endif -#ifndef BIT23 - #define BIT23 (1 << 23) -#endif -#ifndef BIT24 - #define BIT24 (1 << 24) -#endif -#ifndef BIT25 - #define BIT25 (1 << 25) -#endif -#ifndef BIT26 - #define BIT26 (1 << 26) -#endif -#ifndef BIT27 - #define BIT27 (1 << 27) -#endif -#ifndef BIT28 - #define BIT28 (1 << 28) -#endif -#ifndef BIT29 - #define BIT29 (1 << 29) -#endif -#ifndef BIT30 - #define BIT30 (1 << 30) -#endif -#ifndef BIT31 - #define BIT31 (1 << 31) -#endif - -#pragma pack (pop) - -typedef enum -{ - AccWidthUint8 = 0, - AccWidthUint16, - AccWidthUint32, -} ACC_WIDTH; - -#define S3_SAVE 0x80 - -#endif +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _AMD_SB_LIB_H_ +#define _AMD_SB_LIB_H_ + +typedef CHAR8 *va_list; +#ifndef _INTSIZEOF + #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) +#endif + +// Also support coding convention rules for var arg macros +#ifndef va_start + #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) +#endif +#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) +#define va_end(ap) ( ap = (va_list)0 ) + +#pragma pack (push, 1) + +#define IMAGE_ALIGN 32*1024 +#define NUM_IMAGE_LOCATION 32 + +//Entry Point Call +typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); + +//Hook Call + +typedef struct _CIMFILEHEADER +{ + UINT32 AMDLogo; + UINT64 CreatorID; + UINT32 Version1; + UINT32 Version2; + UINT32 Version3; + UINT32 ModuleInfoOffset; + UINT32 EntryPoint; + UINT32 ImageBase; + UINT32 RelocTableOffset; + UINT32 ImageSize; + UINT16 CheckSum; + UINT8 ImageType; + UINT8 Reserved2; +} CIMFILEHEADER; + +#ifndef BIT0 + #define BIT0 (1 << 0) +#endif +#ifndef BIT1 + #define BIT1 (1 << 1) +#endif +#ifndef BIT2 + #define BIT2 (1 << 2) +#endif +#ifndef BIT3 + #define BIT3 (1 << 3) +#endif +#ifndef BIT4 + #define BIT4 (1 << 4) +#endif +#ifndef BIT5 + #define BIT5 (1 << 5) +#endif +#ifndef BIT6 + #define BIT6 (1 << 6) +#endif +#ifndef BIT7 + #define BIT7 (1 << 7) +#endif +#ifndef BIT8 + #define BIT8 (1 << 8) +#endif +#ifndef BIT9 + #define BIT9 (1 << 9) +#endif +#ifndef BIT10 + #define BIT10 (1 << 10) +#endif +#ifndef BIT11 + #define BIT11 (1 << 11) +#endif +#ifndef BIT12 + #define BIT12 (1 << 12) +#endif +#ifndef BIT13 + #define BIT13 (1 << 13) +#endif +#ifndef BIT14 + #define BIT14 (1 << 14) +#endif +#ifndef BIT15 + #define BIT15 (1 << 15) +#endif +#ifndef BIT16 + #define BIT16 (1 << 16) +#endif +#ifndef BIT17 + #define BIT17 (1 << 17) +#endif +#ifndef BIT18 + #define BIT18 (1 << 18) +#endif +#ifndef BIT19 + #define BIT19 (1 << 19) +#endif +#ifndef BIT20 + #define BIT20 (1 << 20) +#endif +#ifndef BIT21 + #define BIT21 (1 << 21) +#endif +#ifndef BIT22 + #define BIT22 (1 << 22) +#endif +#ifndef BIT23 + #define BIT23 (1 << 23) +#endif +#ifndef BIT24 + #define BIT24 (1 << 24) +#endif +#ifndef BIT25 + #define BIT25 (1 << 25) +#endif +#ifndef BIT26 + #define BIT26 (1 << 26) +#endif +#ifndef BIT27 + #define BIT27 (1 << 27) +#endif +#ifndef BIT28 + #define BIT28 (1 << 28) +#endif +#ifndef BIT29 + #define BIT29 (1 << 29) +#endif +#ifndef BIT30 + #define BIT30 (1 << 30) +#endif +#ifndef BIT31 + #define BIT31 (1 << 31) +#endif + +#pragma pack (pop) + +typedef enum +{ + AccWidthUint8 = 0, + AccWidthUint16, + AccWidthUint32, +} ACC_WIDTH; + +#define S3_SAVE 0x80 + +#endif Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sun Jan 2 00:30:37 2011 (r6236) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sun Jan 2 00:36:03 2011 (r6237) @@ -1,153 +1,153 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ - -#include -typedef UINT64 PLACEHOLDER; -#include -#include -#include //TODO merge with agesa wrapper -#include -#include -#include -#include -#include -#include -#include - -#ifdef NULL - #undef NULL -#endif -#define NULL 0 - -#ifndef SBOEM_ACPI_RESTORE_SWSMI - #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 - #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 -#endif - -#ifndef _AMD_NB_CIM_X_PROTOCOL_H_ - -/// Extended PCI Address -typedef struct _EXT_PCI_ADDR { - UINT32 Reg :16; ///< / PCI Register - UINT32 Func:3; ///< / PCI Function - UINT32 Dev :5; ///< / PCI Device - UINT32 Bus :8; ///< / PCI Address -} EXT_PCI_ADDR; - -/// PCI Address -typedef union _PCI_ADDR { - UINT32 ADDR; ///< / 32 bit Address - EXT_PCI_ADDR Addr; ///< / Extended PCI Address -} PCI_ADDR; -#endif - -#define FIXUP_PTR(ptr) ptr - -//------------------------------------------------------------------------------------------------------------------------// -/** - * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over - * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable - * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal - * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable - * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) - * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable - * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) - * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable - * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable - * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable - * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable - * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable - * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable - * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) - * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) - * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz - * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable - * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable - * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable - * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable - * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable - * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable - * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable - * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable - */ -#define SB_CIMx_PARAMETER 0x02 - -// Generic -#define cimSpreadSpectrumDefault TRUE -#define cimSpreadSpectrumTypeDefault 0x00 // Normal -#define cimHpetTimerDefault TRUE -#define cimHpetMsiDisDefault FALSE // Enable -#define cimIrConfigDefault 0x00 // Disable -#define cimSpiFastReadEnableDefault 0x00 // Disable -#define cimSpiFastReadSpeedDefault 0x00 // NULL -// GPP/AB Controller -#define cimNbSbGen2Default TRUE -#define cimAlinkPhyPllPowerDownDefault TRUE -#define cimResetCpuOnSyncFloodDefault TRUE -#define cimGppGen2Default FALSE -#define cimGppMemWrImproveDefault TRUE -#define cimGppPortAspmDefault FALSE -#define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE -// USB Controller -#define cimUsbPhyPowerDownDefault FALSE -// GEC Controller -#define cimSBGecDebugBusDefault FALSE -#define cimSBGecPwrDefault 0x03 -// Sata Controller -#define cimSataSetMaxGen2Default 0x00 -#define cimSATARefClkSelDefault 0x10 -#define cimSATARefDivSelDefault 0x80 -#define cimSataAggrLinkPmCapDefault TRUE -#define cimSataPortMultCapDefault TRUE -#define cimSataPscCapDefault 0x00 // Enable -#define cimSataSscCapDefault 0x00 // Enable -#define cimSataFisBasedSwitchingDefault FALSE -#define cimSataCccSupportDefault FALSE -#define cimSataClkAutoOffDefault FALSE -#define cimNativepciesupportDefault FALSE -// Fusion Related -#define cimAcDcMsgDefault FALSE -#define cimTimerTickTrackDefault FALSE -#define cimClockInterruptTagDefault FALSE -#define cimOhciTrafficHandingDefault FALSE -#define cimEhciTrafficHandingDefault FALSE -#define cimFusionMsgCMultiCoreDefault FALSE -#define cimFusionMsgCStageDefault FALSE - -#endif // _AMD_SBPLATFORM_H_ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ + +#include +typedef UINT64 PLACEHOLDER; +#include +#include +#include //TODO merge with agesa wrapper +#include +#include +#include +#include +#include +#include +#include + +#ifdef NULL + #undef NULL +#endif +#define NULL 0 + +#ifndef SBOEM_ACPI_RESTORE_SWSMI + #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 + #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 +#endif + +#ifndef _AMD_NB_CIM_X_PROTOCOL_H_ + +/// Extended PCI Address +typedef struct _EXT_PCI_ADDR { + UINT32 Reg :16; ///< / PCI Register + UINT32 Func:3; ///< / PCI Function + UINT32 Dev :5; ///< / PCI Device + UINT32 Bus :8; ///< / PCI Address +} EXT_PCI_ADDR; + +/// PCI Address +typedef union _PCI_ADDR { + UINT32 ADDR; ///< / 32 bit Address + EXT_PCI_ADDR Addr; ///< / Extended PCI Address +} PCI_ADDR; +#endif + +#define FIXUP_PTR(ptr) ptr + +//------------------------------------------------------------------------------------------------------------------------// +/** + * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over + * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable + * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal + * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable + * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) + * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable + * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) + * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable + * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable + * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable + * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable + * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable + * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable + * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable + * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable + * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable + * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable + * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) + * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) + * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz + * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable + * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable + * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable + * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable + * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable + * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable + * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable + * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable + * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable + * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable + * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable + * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable + * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable + */ +#define SB_CIMx_PARAMETER 0x02 + +// Generic +#define cimSpreadSpectrumDefault TRUE +#define cimSpreadSpectrumTypeDefault 0x00 // Normal +#define cimHpetTimerDefault TRUE +#define cimHpetMsiDisDefault FALSE // Enable +#define cimIrConfigDefault 0x00 // Disable +#define cimSpiFastReadEnableDefault 0x00 // Disable +#define cimSpiFastReadSpeedDefault 0x00 // NULL +// GPP/AB Controller +#define cimNbSbGen2Default TRUE +#define cimAlinkPhyPllPowerDownDefault TRUE +#define cimResetCpuOnSyncFloodDefault TRUE +#define cimGppGen2Default FALSE +#define cimGppMemWrImproveDefault TRUE +#define cimGppPortAspmDefault FALSE +#define cimGppLaneReversalDefault FALSE +#define cimGppPhyPllPowerDownDefault TRUE +// USB Controller +#define cimUsbPhyPowerDownDefault FALSE +// GEC Controller +#define cimSBGecDebugBusDefault FALSE +#define cimSBGecPwrDefault 0x03 +// Sata Controller +#define cimSataSetMaxGen2Default 0x00 +#define cimSATARefClkSelDefault 0x10 +#define cimSATARefDivSelDefault 0x80 +#define cimSataAggrLinkPmCapDefault TRUE +#define cimSataPortMultCapDefault TRUE +#define cimSataPscCapDefault 0x00 // Enable +#define cimSataSscCapDefault 0x00 // Enable +#define cimSataFisBasedSwitchingDefault FALSE +#define cimSataCccSupportDefault FALSE +#define cimSataClkAutoOffDefault FALSE +#define cimNativepciesupportDefault FALSE +// Fusion Related +#define cimAcDcMsgDefault FALSE +#define cimTimerTickTrackDefault FALSE +#define cimClockInterruptTagDefault FALSE +#define cimOhciTrafficHandingDefault FALSE +#define cimEhciTrafficHandingDefault FALSE +#define cimFusionMsgCMultiCoreDefault FALSE +#define cimFusionMsgCStageDefault FALSE + +#endif // _AMD_SBPLATFORM_H_ From buurin at gmail.com Sun Jan 2 03:59:44 2011 From: buurin at gmail.com (Keith Hui) Date: Sat, 1 Jan 2011 21:59:44 -0500 Subject: [coreboot] Need pointers Message-ID: While I try to help Roger with his raminit problems and/or port coreboot to SIS630, I also want to get the SCSI part of my P2B-LS fully working. This also means implementing an option table for this board. I am looking for pointers on what to read to know the relationships between option tables, cmos.layout, and where to implement a new option, especially one that isn't directly related to the southbridge, or is board specific. --- For the last few times I have tried leaving the SCSI part enabled on the board, I am getting lots of noise from the linux aic78xx driver, and the SCSI BIOS, extracted from OEM BIOS image and added to the coreboot image, wouldn't even run properly. I know the factory BIOS provides a setting to control the onboard termination of 2 of the 3 SCSI ports on the board (the third is always terminated), and I'm suspecting this is what making SCSI fail. So I have to implement it. This is where the option table comes in to play. Meanwhile I am mapping out where all the factory BIOS settings are in the nvram, so I can get the eventual cmos.layout as close to OEM as possible. I got some of it mapped out, by painstakingly toggling every option in its setup screen that won't immediately brick my test machine and taking a before and after nvram dump, looking for differences. --- Thanks Keith From bwhite82 at gmail.com Sun Jan 2 03:31:48 2011 From: bwhite82 at gmail.com (Brandon White) Date: Sat, 1 Jan 2011 21:31:48 -0500 Subject: [coreboot] Support for Google CR-48/Atom N455 Message-ID: Hello all. Someone was accidentally sent a CR-48 that had Windows 7 pre-installed and an actual BIOS instead of Google's EFI. Anways, he uploaded the BIOS, I was able to flash it and after that I installed Ubuntu as a dual boot with Chrome OS. I was wondering if Coreboot was possible on this machine? I have attached everything asked for in the wiki. Thanks, Brandon -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- flashrom v0.9.2-r1028 on Linux 2.6.35-22-generic (i686), built with libpci 3.0.0, GCC 4.4.4, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 3 usecs, 811M loops per second, 10 myus = 12 us, 100 myus = 99 us, 1000 myus = 986 us, 10000 myus = 10192 us, 12 myus = 22 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "IEC" DMI string system-product-name: "PineTrail" DMI string system-version: "0.08" DMI string baseboard-manufacturer: "IEC" DMI string baseboard-product-name: "Base Board Product Name" DMI string baseboard-version: "Base Board Version" DMI string chassis-type: "Other" Found chipset "Intel NM10", enabling flash write... chipset PCI ID is 8086:27bc, 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x9 Root Complex Register Block address = 0xfed1c000 GCS = 0x40460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3020 0x00: 0x0004 (SPIS) 0x02: 0x4140 (SPIC) 0x04: 0x00000000 (SPIA) 0x08: 0x001615ef (SPID0) 0x0c: 0x00000000 (SPID0+4) 0x10: 0x00000000 (SPID1) 0x14: 0x00000000 (SPID1+4) 0x18: 0x00000000 (SPID2) 0x1c: 0x00000000 (SPID2+4) 0x20: 0x00000000 (SPID3) 0x24: 0x00000000 (SPID3+4) 0x28: 0x00000000 (SPID4) 0x2c: 0x00000000 (SPID4+4) 0x30: 0x00000000 (SPID5) 0x34: 0x00000000 (SPID5+4) 0x38: 0x00000000 (SPID6) 0x3c: 0x00000000 (SPID6+4) 0x40: 0x00000000 (SPID7) 0x44: 0x00000000 (SPID7+4) 0x50: 0x00000000 (BBAR) 0x54: 0x5006 (PREOP) 0x56: 0x463b (OPTYPE) 0x58: 0x05d80302 (OPMENU) 0x5c: 0xc79f0190 (OPMENU+4) 0x60: 0x00000000 (PBR0) 0x64: 0x00000000 (PBR1) 0x68: 0x00000000 (PBR2) 0x6c: 0x00000000 (PBR3) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done SPI Read Configuration: prefetching enabled, caching enabled, OK. This chipset supports the following protocols: SPI. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Chip status register is 1c Found chip "Winbond W25Q32" (4096 KB, SPI) at physical address 0xffc00000. Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EON unknown EON SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xef, id2 0x15 === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom at flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. -------------- next part -------------- -[0000:00]-+-00.0 Intel Corporation N10 Family DMI Bridge [8086:a010] +-02.0 Intel Corporation N10 Family Integrated Graphics Controller [8086:a011] +-02.1 Intel Corporation N10 Family Integrated Graphics Controller [8086:a012] +-1b.0 Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8] +-1c.0-[01]----00.0 Atheros Communications Inc. AR928X Wireless Network Adapter (PCI-Express) [168c:002a] +-1c.1-[02]-- +-1c.2-[03]-- +-1c.3-[04]-- +-1d.0 Intel Corporation N10/ICH 7 Family USB UHCI Controller #1 [8086:27c8] +-1d.1 Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9] +-1d.2 Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca] +-1d.3 Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb] +-1d.7 Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc] +-1e.0-[05]-- +-1f.0 Intel Corporation NM10 Family LPC Controller [8086:27bc] +-1f.2 Intel Corporation N10/ICH7 Family SATA AHCI Controller [8086:27c1] \-1f.3 Intel Corporation N10/ICH 7 Family SMBus Controller [8086:27da] -------------- next part -------------- superiotool r5050 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x0001, id=0x0085 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x8500, rev=0x1 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x8500, rev=0x1 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x8500, rev=0x1 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x8500, rev=0x1 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: sid=0x85, srid=0x00 Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Found SMSC SCH5317 (id=0x85, rev=0x00) at 0x2e No dump available for this Super I/O Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Found SMSC FDC37N972 (id=0x0b, rev=0x00) at 0x4e Register dump: idx 02 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val 00 0b 00 00 00 00 00 4e 00 00 00 00 00 00 00 00 00 def 00 0b 00 00 00 04 04 NA NA 00 00 00 00 00 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f3 f4 f5 val 00 00 00 00 00 00 d1 15 0b 00 10 def 00 03 f0 06 02 0e 00 ff RR 00 00 LDN 0x01 (Power management (PM1)) idx 30 60 61 val 00 00 00 def 00 00 00 LDN 0x03 (Parallel port) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 00 00 d1 def 00 00 00 00 04 3c 00 LDN 0x04 (COM1) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 00 00 00 00 LDN 0x05 (COM2) idx 30 60 61 62 63 70 74 f0 f1 f2 f7 f8 val 00 00 00 00 00 00 00 00 d1 15 00 00 def 00 00 00 00 00 00 04 00 02 03 00 00 LDN 0x06 (Real-time clock (RTC)) idx 30 60 61 62 63 70 f0 f1 val 00 00 00 00 00 00 00 d1 def 00 00 70 00 74 00 00 NA LDN 0x07 (Keyboard) idx 30 60 61 70 72 f0 val 00 00 00 00 00 00 def 00 00 00 00 00 00 LDN 0x08 (Embedded controller (EC)) idx 30 60 61 val 00 00 00 def 00 00 62 LDN 0x09 (Mailbox) idx 30 60 61 val 00 00 00 def 00 00 00 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. From hagigatali at gmail.com Sun Jan 2 10:00:11 2011 From: hagigatali at gmail.com (ali hagigat) Date: Sun, 2 Jan 2011 12:30:11 +0330 Subject: [coreboot] incomplete documentation Message-ID: Coreboot declares a complete documentation of some chips by: http://www.coreboot.org/Datasheets and particularly 82815E by: http://www.coreboot.org/Datasheets#Intel_82801BA.2FBAM_.28ICH2.29 Where is the documentation for integrated graphics controller of this chip? Only the explanation of some configuration registers are available. Why Coreboot site maintainers do not clearly express that the necessary documentation for BIOS developing is not available? Even the open documents you have added in Data-sheet section are not complete. From joe at settoplinux.org Sun Jan 2 12:19:04 2011 From: joe at settoplinux.org (Joseph Smith) Date: Sun, 02 Jan 2011 06:19:04 -0500 Subject: [coreboot] incomplete documentation In-Reply-To: References: Message-ID: <7e60b003b28aeb9ef1bf2a707259f23a@imap.1and1.com> On Sun, 2 Jan 2011 12:30:11 +0330, ali hagigat wrote: > Coreboot declares a complete documentation of some chips by: > http://www.coreboot.org/Datasheets > and particularly 82815E by: > http://www.coreboot.org/Datasheets#Intel_82801BA.2FBAM_.28ICH2.29 > > Where is the documentation for integrated graphics controller of this > chip? Only the explanation of some configuration registers are > available. > It is publicly available, try googling "82815 PRM" or "Intel 815 programmers reference manual" > Why Coreboot site maintainers do not clearly express that the > necessary documentation for BIOS developing is not available? Even the > open documents you have added in Data-sheet section are not complete. > Watch your tongue, there is a huge difference "open documents" and public documents. The "coreboot site maintainers" which includes many people with wiki access, don't have the time to run around collecting 50 million documents floating around the web, especially chipsets that are not even supported by coreboot yet. Google is your friend. FYI: You refer to the i815E Northbridge and link to the i82801BA ICH2 southbridge... two completely different things... are you sure you know what your doing??? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From stepan at coreboot.org Sun Jan 2 17:55:37 2011 From: stepan at coreboot.org (Stefan Reinauer) Date: Sun, 02 Jan 2011 17:55:37 +0100 Subject: [coreboot] incomplete documentation In-Reply-To: References: Message-ID: <4D20AE09.3070408@coreboot.org> On 1/2/11 10:00 AM, ali hagigat wrote: > Coreboot declares a complete documentation of some chips by: > http://www.coreboot.org/Datasheets > and particularly 82815E by: > http://www.coreboot.org/Datasheets#Intel_82801BA.2FBAM_.28ICH2.29 > > Where is the documentation for integrated graphics controller of this > chip? Only the explanation of some configuration registers are > available. Is this an Intel chip? Why don't you ask Intel? > Why Coreboot site maintainers do not clearly express that the > necessary documentation for BIOS developing is not available? Even the > open documents you have added in Data-sheet section are not complete Please, stop trolling, it is really tiresome. We explained this especially to you before, that getting documentation for BIOS development is hard, and especially hard with Intel systems. If you don't want to listen, or don't want to learn, please just go away. Stefan From peter at stuge.se Sun Jan 2 19:53:32 2011 From: peter at stuge.se (Peter Stuge) Date: Sun, 2 Jan 2011 19:53:32 +0100 Subject: [coreboot] incomplete documentation In-Reply-To: References: Message-ID: <20110102185333.5373.qmail@stuge.se> ali hagigat wrote: > Coreboot declares a complete documentation of some chips by: > http://www.coreboot.org/Datasheets How do you know that it is complete? I doubt that we have (even links to) complete documentation for anything besides superio chips. > and particularly 82815E by: > http://www.coreboot.org/Datasheets#Intel_82801BA.2FBAM_.28ICH2.29 > > Where is the documentation for integrated graphics controller of this > chip? It may be available from the manufacturer, Intel. Please talk to them. If you can acquire documentation and the permission to redistribute, then more information is of course very welcome on the datasheets web page. > Why Coreboot site maintainers do not clearly express that the > necessary documentation for BIOS developing is not available? Because that is already immediately obvious for someone who looks at the documentation that *is* available, or for someone with experience from PC firmware development, or for someone who starts reading the coreboot source code and tries to look up what the meaning of the code is, or for someone who gets told about this fact e.g. via email. I'm sorry that none of this is sufficient for you. //Peter From stepan at coreboot.org Sun Jan 2 20:54:32 2011 From: stepan at coreboot.org (Stefan Reinauer) Date: Sun, 02 Jan 2011 20:54:32 +0100 Subject: [coreboot] Need pointers In-Reply-To: References: Message-ID: <4D20D7F8.80608@coreboot.org> Hi Keith, On 1/2/11 3:59 AM, Keith Hui wrote: > I also want to get the SCSI part of my P2B-LS > fully working. This also means implementing an option table for this > board. Why would that be required? > I am looking for pointers on what to read to know the relationships > between option tables, cmos.layout, and where to implement a new > option, especially one that isn't directly related to the southbridge, > or is board specific. See for example src/mainboard/kontron/986lcd-m/romstage.c and src/mainboard/kontron/986lcd-m/cmos.layout for some mainboard specific options. > --- > > For the last few times I have tried leaving the SCSI part enabled on > the board, I am getting lots of noise from the linux aic78xx driver, > and the SCSI BIOS, extracted from OEM BIOS image and added to the > coreboot image, wouldn't even run properly. This is where you'd want to start debugging, which of course would need some more detailed information. "wouldn't run properly" is not good enough for an error report. A log file might be better. Is this with SeaBIOS? Or with coreboot? With Yabel? Or native? > Meanwhile I am mapping out where all the factory BIOS settings are in > the nvram, so I can get the eventual cmos.layout as close to OEM as > possible. I got some of it mapped out, by painstakingly toggling every > option in its setup screen that won't immediately brick my test > machine and taking a before and after nvram dump, looking for > differences. Not sure what your goal is with this, but it sounds like there might be a better way to achieve this. Stefan From rogerx.oss at gmail.com Mon Jan 3 02:03:24 2011 From: rogerx.oss at gmail.com (Roger) Date: Sun, 2 Jan 2011 16:03:24 -0900 Subject: [coreboot] raminit.c example Message-ID: <20110103010324.GC4519@localhost2.local> I've read over the src/northbridge/intel/i440bx/raminit.c, but am still a little mystified on setting the settings. I can see where settings are set to zero (or default), but when I look at other settings, the values don't seem to match up to what is well documented within the comments. A good easy example would be setting DRAMC: DRAMC, 0x00, 0x08, Is the "0x00" designated by "000" as documented? Hex? What does "0x08" mean? -- Roger http://rogerx.freeshell.org/ From corey.osgood at gmail.com Mon Jan 3 06:14:39 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Mon, 3 Jan 2011 00:14:39 -0500 Subject: [coreboot] raminit.c example In-Reply-To: <20110103010324.GC4519@localhost2.local> References: <20110103010324.GC4519@localhost2.local> Message-ID: On Sun, Jan 2, 2011 at 8:03 PM, Roger wrote: > I've read over the src/northbridge/intel/i440bx/raminit.c, but am still a > little mystified on setting the settings. > > I can see where settings are set to zero (or default), but when I look at other > settings, the values don't seem to match up to what is well documented within > the comments. > > A good easy example would be setting DRAMC: > DRAMC, 0x00, 0x08, > > Is the "0x00" designated by "000" as documented? ?Hex? > > What does "0x08" mean? See sdram_set_registers(). Those values aren't written directly to the register, because there may be some data stored in other bits that we don't want to lose. So, for DRAMC, sdram_set_registers reads the value of the DRAMC register (defined in i440bx.h as 0x57), then does a logical AND with the first value, 0x00 (which will actually clear all the bits), then performs a logical OR with the second value, 0x08, which sets bit 3 to 1, indicating the memory type is SDRAM. It then writes that value back to the register. In situations like this, gcc should just optimize the whole thing down to writing 0x08 to the register, so there's no problem with wasting CPU/IO cycles performing unnecessary functions. -Corey From snes9xd at gmail.com Mon Jan 3 08:58:02 2011 From: snes9xd at gmail.com (William juice) Date: Mon, 3 Jan 2011 02:58:02 -0500 Subject: [coreboot] help with core boot and compaq deskpro ep c500 Message-ID: i have just seen and read about core boot and i was woundering about, if a Compaq Deskpro EP C500 <(old computer) could have core boot instaled with payload as seabios for a bios replacment due to slow booting(linux) and limited settings in bios ect. i have posted the hp link to the compaq bios ect below http://h20000.www2.hp.com/bizsupport/TechSupport/DriverDownload.jsp?prodNameId=96985&lang=en&cc=us&prodTypeId=12454&prodSeriesId=96269&taskId=135 thx ~SIN~ -------------- next part -------------- An HTML attachment was scrubbed... URL: From paulepanter at users.sourceforge.net Mon Jan 3 09:39:31 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Mon, 03 Jan 2011 09:39:31 +0100 Subject: [coreboot] Does coreboot support Compaq Deskpro EP c500? (was: help with core boot and compaq deskpro ep c500) In-Reply-To: References: Message-ID: <1294043971.4121.6.camel@mattotaupa> Dear William, please do only send plain text messages to lists. Am Montag, den 03.01.2011, 02:58 -0500 schrieb William juice: > i have just seen and read about core boot Thank you for your interest in coreboot (spelling with no space). > and i was woundering about, if a > Compaq Deskpro EP C500 <(old computer) could have core boot instaled with > payload as seabios for a bios replacment due to slow booting(linux) and > limited settings in bios ect. > > i have posted the hp link to the compaq bios ect below > > http://h20000.www2.hp.com/bizsupport/TechSupport/DriverDownload.jsp?prodNameId=96985&lang=en&cc=us&prodTypeId=12454&prodSeriesId=96269&taskId=135 Unfortunately it does not list the required information. Could you please follow [1] and report back if your chipsets and devices are supported. Thanks, Paul [1] http://www.coreboot.org/FAQ#Will_coreboot_work_on_my_machine.3F -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From anders at jenbo.dk Mon Jan 3 09:34:08 2011 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Mon, 03 Jan 2011 09:34:08 +0100 Subject: [coreboot] =?utf-8?q?help_with_core_boot_and_compaq_deskpro_ep_c5?= =?utf-8?q?00?= Message-ID: <20110103083426.818472403BA4@csmtp3.one.com> Give us The output from lspci -tvnn Mvh Anders ----- Reply message ----- Fra: "William juice" Dato: man., jan. 3, 2011 08:58 Emne: [coreboot] help with core boot and compaq deskpro ep c500 Til: i have just seen and read about core boot and i was woundering about, if a Compaq Deskpro EP C500 <(old computer) could have core boot instaled with payload as seabios for a bios replacment due to slow booting(linux) and limited settings in bios ect. i have posted the hp link to the compaq bios ect below http://h20000.www2.hp.com/bizsupport/TechSupport/DriverDownload.jsp?prodNameId=96985&lang=en&cc=us&prodTypeId=12454&prodSeriesId=96269&taskId=135 thx ~SIN~ -------------- next part -------------- An HTML attachment was scrubbed... URL: From rogerx.oss at gmail.com Mon Jan 3 10:20:00 2011 From: rogerx.oss at gmail.com (Roger) Date: Mon, 3 Jan 2011 00:20:00 -0900 Subject: [coreboot] raminit.c example In-Reply-To: References: <20110103010324.GC4519@localhost2.local> Message-ID: <20110103085539.GE4519@localhost2.local> On Mon, Jan 03, 2011 at 12:14:39AM -0500, Corey Osgood wrote: >On Sun, Jan 2, 2011 at 8:03 PM, Roger wrote: >> I've read over the src/northbridge/intel/i440bx/raminit.c, but am still a >> little mystified on setting the settings. >> >> I can see where settings are set to zero (or default), but when I look at other >> settings, the values don't seem to match up to what is well documented within >> the comments. >> >> A good easy example would be setting DRAMC: >> DRAMC, 0x00, 0x08, >> >> Is the "0x00" designated by "000" as documented? ?Hex? >> >> What does "0x08" mean? > >See sdram_set_registers(). Those values aren't written directly to the >register, because there may be some data stored in other bits that we >don't want to lose. So, for DRAMC, sdram_set_registers reads the value >of the DRAMC register (defined in i440bx.h as 0x57), then does a >logical AND with the first value, 0x00 (which will actually clear all >the bits), then performs a logical OR with the second value, 0x08, >which sets bit 3 to 1, indicating the memory type is SDRAM. It then >writes that value back to the register. In situations like this, gcc >should just optimize the whole thing down to writing 0x08 to the >register, so there's no problem with wasting CPU/IO cycles performing >unnecessary functions. wow. From hagigatali at gmail.com Mon Jan 3 13:14:08 2011 From: hagigatali at gmail.com (ali hagigat) Date: Mon, 3 Jan 2011 15:44:08 +0330 Subject: [coreboot] .cb files Message-ID: How .cb files are created? and what they are used for? From patrick at georgi-clan.de Mon Jan 3 13:28:56 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 03 Jan 2011 13:28:56 +0100 Subject: [coreboot] .cb files In-Reply-To: References: Message-ID: <4D21C108.6020300@georgi-clan.de> Am 03.01.2011 13:14, schrieb ali hagigat: > How .cb files are created? Creative work of human beings. > and what they are used for? All kinds of things. In case you're wondering (which might qualify you for the creative work mentioned above at least): Yes, these answers are mostly useless - I'm a proponent of the garbage-in-garbage-out principle. Patrick From joe at settoplinux.org Mon Jan 3 15:29:47 2011 From: joe at settoplinux.org (Joseph Smith) Date: Mon, 03 Jan 2011 09:29:47 -0500 Subject: [coreboot] .cb files In-Reply-To: <4D21C108.6020300@georgi-clan.de> References: <4D21C108.6020300@georgi-clan.de> Message-ID: LMFAO !!! "Patrick Georgi" wrote: >Am 03.01.2011 13:14, schrieb ali hagigat: >> How .cb files are created? >Creative work of human beings. > >> and what they are used for? >All kinds of things. > >In case you're wondering (which might qualify you for the creative work >mentioned above at least): Yes, these answers are mostly useless - I'm >a >proponent of the garbage-in-garbage-out principle. > > >Patrick > >-- >coreboot mailing list: coreboot at coreboot.org >http://www.coreboot.org/mailman/listinfo/coreboot -- Sent from my Android phone with K-9 Mail. Please excuse my brevity. From svn at coreboot.org Mon Jan 3 16:00:02 2011 From: svn at coreboot.org (coreboot tracker) Date: Mon, 03 Jan 2011 16:00:02 +0100 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From peter at stuge.se Mon Jan 3 16:07:59 2011 From: peter at stuge.se (Peter Stuge) Date: Mon, 3 Jan 2011 16:07:59 +0100 Subject: [coreboot] .cb files In-Reply-To: References: Message-ID: <20110103150759.10213.qmail@stuge.se> ali hagigat wrote: > How .cb files are created? As was pointed out already, by hand. > and what they are used for? Describing fixed parts of a system. What buses there are and what devices are on them. Please suggest how we can improve the syntax of .cb files. I want them to be self-documenting enough so that you can understand the above from just looking at the files. Can you help? //Peter From cristi.magherusan at net.utcluj.ro Mon Jan 3 18:07:28 2011 From: cristi.magherusan at net.utcluj.ro (Cristi Magherusan) Date: Mon, 3 Jan 2011 19:07:28 +0200 (EET) Subject: [coreboot] Support for Google CR-48/Atom N455 In-Reply-To: References: Message-ID: <22797.86.122.13.126.1294074448.squirrel@intranet.utcluj.ro> ?n Dum, Ianuarie 2, 2011 4:31, Brandon White a scris: > Hello all. Someone was accidentally sent a CR-48 that had Windows 7 > pre-installed and an actual BIOS instead of Google's EFI. Anways, he > uploaded the BIOS, I was able to flash it and after that I installed > Ubuntu > as a dual boot with Chrome OS. I was wondering if Coreboot was possible on > this machine? I have attached everything asked for in the wiki. > > Thanks, > Brandon > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot Hello, Flashrom seems to support your flash, but writes weren't tested/confirmed to work yet on the flashrom wiki. Did you flash it using Frashrom? The ICH7 southbridge is supported, no idea about the northbridge, you might need doc from Intel, which is hard to get unless you have an NDA. If you are lucky, the SMSC SCH5317 SuperIO might be easy to support, by porting the code for SCH5307 which is already supported. I have no clue about the other superIO chip or what could it be used for. maybe we don't need it at all for system init. Also, thew board might have an Embedded Controller, which might make things even harder. Good luck! Cristi From Frantisek.Rysanek at post.cz Mon Jan 3 22:23:34 2011 From: Frantisek.Rysanek at post.cz (Frantisek Rysanek) Date: Mon, 03 Jan 2011 22:23:34 +0100 Subject: [coreboot] superiotool sometimes skips further SuperIO chips in the system - suggested remedy included In-Reply-To: <4D1C6FCE.9020206@coreboot.org> References: <4D19E291.6984.59D2C23@Frantisek.Rysanek.post.cz>, <4D1C6956.4040508@coreboot.org>, <4D1C6FCE.9020206@coreboot.org> Message-ID: <4D224C66.6241.267AA7C2@Frantisek.Rysanek.post.cz> Dear gentlemen, thanks for the polite responses from Mr. Hendricks and Herr Reinauer. I have some further notes... As top-posting is a big no-no at least in the LKML, see my further comments way below :-) -------------------------------------------------- On 28 Dec 2010 at 23:51, David Hendricks wrote: Heh, I hacked that "if (chip_found) return;" stuff into SuperI/O tool a few months ago (http://www.coreboot.org/pipermail/coreboot/2010- August/059607.html). The reason was to avoid duplicate listings. In my specific case, I was working with an ITE chip that does not need an entry/exit sequence. So when probe_regs_ite() was called, it would find my chip 5 times and dump its registers 5 times. Sorry if it's causing you headaches now :-/ I think long-term we should make superiotool more intelligent with regard to duplicate entries. For example, if a chip has been found at 0x2e, then superiotool should stop probing devices on port 0x2e and continue probing devices on ports 0x4e, 0x3f0, etc (as listed in superioto_ports_table[]). I think we could accomplish this easily: - Add a return code to each chip's probe_idregs_* function. - Update the loop in main() which iterates thru superio_ports_table[]. If a probe_idregs_* function returns a specific code to indicate a chip has been found, then record the corresponding superio port entry and avoid further calls to superio_ports_table[i].probe_idregs() on that port. -------------------------------------------------- On 30 Dec 2010 at 12:41, Stefan Reinauer wrote: Therefore, after the first chip detected (of any kind), only the first init sequence is ever tried, in any subsequent calls to the aforementioned probe_* functions. That function is called with a port address. There can only be one chip at one port address. So leaving the function after a chip has been found at that address seems like the right thing to do. The bug is that chip_found is a global variable and not a local variable. Attached patch should fix the issue. And an equivalent change is needed for winbond.c I guess. ======= Okay here are my comments: ======= I have to say that I agree with Mr. Hendricks. Once you find a chip at a particular port, it should not make sense to probe *at that particular port* again. So you need some global way of tagging I/O ports already occupied. I do not think that making the "chip_found" local to the particular vendor-specific probe function would solve the problem. Yes it does make it scan all the different init sequences across all the ports, but other vendor-specific modules will re-scan the ports anyway (as the info about ports already occupied doesn't exist in the global scope). Now... the way the topmost superio_ports_table[vendor]->ports[] is organized, indeed the same port will be scanned by multiple probes. The I/O port is a "leaf attribute" of a vendor in the data model, and is not indexed upon in any way. I believe this calls for a slight "reinforcement" of the data model. Specifically: It seems to me that superiotool.c would have to keep an additional index (even just a list with some manipulator functions) of ports already known to be occupied. We'll need to retain the mapping of vendor->ports. It doesn't seem very fruitful to re-factor the table as port->vendors :-) Or does it? Side note: at a fist glance, it seemd to me that for some advanced functionality (writing to ports, separation of "probe" from "dump" etc) it might be interesting to create a global list of "devices" detected. This would have the neat side effect of having a list of the IO ports already probed... but at a closer look, it seems that the vendor-specific modules are much too "polymorphic", the "device private data" would have to be polymorphic (vendor-specific), and all the vendor-specific code would have to be somewhat heavily refactored in quite an individual fashion, to meet the new and more refined "abstraction model"... looks like too much work and very little immediate use. I have to say that I've dipped my toes in some intermediate-level C++, but I can also sculpt encapsulation and polymorphism in bare C... yet in this case I don't think there's any call for either of that. Another minor point: it seems interesting to me that the superio_ports_table is declared+defined "static const" _in_the_header_file_. Thus, each module that includes superiotool.h instantiates that table, even though only superiotool.c ever makes any use of it. The obvious solution would be to move the superio_ports_table to superiotool.c. Or maybe break it up and make the tables of ports "private" to the individual vendor modules, managed/walked by the per-module probe functions. Yet for the moment I admit that there is indeed certain beauty (elegance?) in having all that data in a single table in superiotool.c, in a common structure... so I'd probably just keep that arrangement :-) I am a newcomer :-) Sorry for talking so much. At the same time, I don't like adding further layers of cruft on top of each other - especially if this has been incited by my own "feedback". The Superiotool looks like a neatly compact piece of source code - small enough for me to understand / encompass :-) I'd like to offer a bit of my own time to add such a global index of "ports occupied" (likely not "devices detected" - see above why). I'd also have to touch all the vendor-specific modules, but only very slightly (to make the probe functions return a result code). I'd have to undo the interim hacks (sorry) added by Mr. Hendricks and Mr. Reinauer. I'd probably start from the version that I've checked out right now from SVN. I don't know how to return to an earlier version, and besides there has been a further detection update to the ITE module, on top of Mr. Reinauer's recent change... Would you be interested? It might take me days of real time - my job and family allow relatively little time for ad hoc meddling... :-) Frank Rysanek From peter at stuge.se Mon Jan 3 23:47:01 2011 From: peter at stuge.se (Peter Stuge) Date: Mon, 3 Jan 2011 23:47:01 +0100 Subject: [coreboot] superiotool sometimes skips further SuperIO chips in the system - suggested remedy included In-Reply-To: <4D1C6956.4040508@coreboot.org> References: <4D19E291.6984.59D2C23@Frantisek.Rysanek.post.cz> <4D1C6956.4040508@coreboot.org> Message-ID: <20110103224701.26620.qmail@stuge.se> Stefan Reinauer wrote: > That function is called with a port address. There can only be one chip > at one port address. But the same function can be called with a different port, and should find another chip. I think David's suggestion is the way to go. //Peter From peter at stuge.se Mon Jan 3 23:55:35 2011 From: peter at stuge.se (Peter Stuge) Date: Mon, 3 Jan 2011 23:55:35 +0100 Subject: [coreboot] superiotool sometimes skips further SuperIO chips in the system - suggested remedy included In-Reply-To: <4D224C66.6241.267AA7C2@Frantisek.Rysanek.post.cz> References: <4D1C6FCE.9020206@coreboot.org> <4D224C66.6241.267AA7C2@Frantisek.Rysanek.post.cz> Message-ID: <20110103225535.28048.qmail@stuge.se> Frantisek Rysanek wrote: > I'd like to offer a bit of my own time to add such a global index of > "ports occupied" (likely not "devices detected" - see above why). Great! Please send the patch with Signed-off-by according to the coreboot development guidelines: (they are short) http://www.coreboot.org/Development_Guidelines#How_to_contribute > Would you be interested? Yes. I suggest using a fixed size array for the ports: #define MAX_SUPERIOS 10 static unsigned char found_superios = 0; static unsigned short superio_port[MAX_SUPERIOS]; and when looping over devices, skip already-known ports: for(each device) { for(i=0;i References: <20110103150759.10213.qmail@stuge.se> Message-ID: Peter, Thank you. So devicetree.cb files are written by hand and the compilation process does not use them? They are just some information for the developers? About: file:///root/build/coreboot/coreboot-v4/src/mainboard/kontron/986lcd-m/devicetree.cb: #device pci 1e.2 off end # AC'97 Audio It means that AC'97 Audio is on Bus#=1 and Function#=2? But all the devices of the south bridge, ICH7 are on Bus number 0, as far as I know. Why you have not written, Bus number, Function number, Device number, Register number clearly. device pci 1d.0 on end, What does it mean, 1d.0? Regards On Mon, Jan 3, 2011 at 6:37 PM, Peter Stuge wrote: > ali hagigat wrote: >> How .cb files are created? > > As was pointed out already, by hand. > > >> and what they are used for? > > Describing fixed parts of a system. What buses there are and what > devices are on them. > > Please suggest how we can improve the syntax of .cb files. > I want them to be self-documenting enough so that you can understand > the above from just looking at the files. Can you help? > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From svn at coreboot.org Tue Jan 4 07:15:47 2011 From: svn at coreboot.org (repository service) Date: Tue, 04 Jan 2011 07:15:47 +0100 Subject: [coreboot] [commit] r6238 - trunk/src/mainboard/amd/bimini_fam10 Message-ID: Author: kerry Date: Tue Jan 4 07:15:46 2011 New Revision: 6238 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6238 Log: Trivial: use the IO_APIC_ADDR constant defined in ioapic.h, and spell check Signed-off-by: Kerry She Acked-by: Kerry She Modified: trunk/src/mainboard/amd/bimini_fam10/acpi_tables.c trunk/src/mainboard/amd/bimini_fam10/devicetree.cb Modified: trunk/src/mainboard/amd/bimini_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/acpi_tables.c Sun Jan 2 00:36:03 2011 (r6237) +++ trunk/src/mainboard/amd/bimini_fam10/acpi_tables.c Tue Jan 4 07:15:46 2011 (r6238) @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -56,8 +57,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/amd/bimini_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/devicetree.cb Sun Jan 2 00:36:03 2011 (r6237) +++ trunk/src/mainboard/amd/bimini_fam10/devicetree.cb Tue Jan 4 07:15:46 2011 (r6238) @@ -31,7 +31,7 @@ register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus + chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pci bus device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.2 on end # USB From svn at coreboot.org Tue Jan 4 07:39:30 2011 From: svn at coreboot.org (repository service) Date: Tue, 04 Jan 2011 07:39:30 +0100 Subject: [coreboot] [commit] r6239 - trunk/src/vendorcode/amd/cimx/sb800 Message-ID: Author: kerry Date: Tue Jan 4 07:39:29 2011 New Revision: 6239 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6239 Log: Trivial: add missed CIMx file to romstage. in order to link them into romstage, move all CIMx table to .rodata section. Run dos2unix on Makefile.inc, which is not upstream CIMx code Signed-off-by: Kerry She Acked-by: Kerry She Modified: trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc trunk/src/vendorcode/amd/cimx/sb800/SATA.c trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Modified: trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c Tue Jan 4 07:15:46 2011 (r6238) +++ trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c Tue Jan 4 07:39:29 2011 (r6239) @@ -51,7 +51,7 @@ * * */ -CODECENTRY AzaliaCodecAlc882Table[] = +const static CODECENTRY AzaliaCodecAlc882Table[] = { {0x14, 0x01014010}, {0x15, 0x01011012}, @@ -74,7 +74,7 @@ * * */ -CODECENTRY AzaliaCodecAlc262Table[] = +const static CODECENTRY AzaliaCodecAlc262Table[] = { {0x14, 0x01014010}, {0x15, 0x411111F0}, @@ -96,7 +96,7 @@ * * */ -CODECENTRY AzaliaCodecAlc269Table[] = +const static CODECENTRY AzaliaCodecAlc269Table[] = { {0x12, 0x99A30960}, {0x14, 0x99130110}, @@ -119,7 +119,7 @@ * * */ -CODECENTRY AzaliaCodecAlc861Table[] = +const static CODECENTRY AzaliaCodecAlc861Table[] = { {0x01, 0x8086C601}, {0x0B, 0x01014110}, @@ -142,7 +142,7 @@ * * */ -CODECENTRY AzaliaCodecAlc889Table[] = +const static CODECENTRY AzaliaCodecAlc889Table[] = { {0x11, 0x411111F0}, {0x14, 0x01014010}, @@ -166,7 +166,7 @@ * * */ -CODECENTRY AzaliaCodecAd1984Table[] = +const static CODECENTRY AzaliaCodecAd1984Table[] = { {0x11, 0x0221401F}, {0x12, 0x90170110}, @@ -188,7 +188,7 @@ * * */ -CODECENTRY FrontPanelAzaliaCodecTableList[] = +const static CODECENTRY FrontPanelAzaliaCodecTableList[] = { {0x19, 0x02A19040}, {0x1b, 0x02214020}, @@ -201,17 +201,17 @@ * * */ -CODECTBLLIST azaliaCodecTableList[] = +const static CODECTBLLIST azaliaCodecTableList[] = { - {0x010ec0880, &AzaliaCodecAlc882Table[0]}, - {0x010ec0882, &AzaliaCodecAlc882Table[0]}, - {0x010ec0883, &AzaliaCodecAlc882Table[0]}, - {0x010ec0885, &AzaliaCodecAlc882Table[0]}, - {0x010ec0889, &AzaliaCodecAlc889Table[0]}, - {0x010ec0262, &AzaliaCodecAlc262Table[0]}, - {0x010ec0269, &AzaliaCodecAlc269Table[0]}, - {0x010ec0861, &AzaliaCodecAlc861Table[0]}, - {0x011d41984, &AzaliaCodecAd1984Table[0]}, + {0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, + {0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, + {0x010ec0883, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, + {0x010ec0885, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, + {0x010ec0889, (CODECENTRY*)&AzaliaCodecAlc889Table[0]}, + {0x010ec0262, (CODECENTRY*)&AzaliaCodecAlc262Table[0]}, + {0x010ec0269, (CODECENTRY*)&AzaliaCodecAlc269Table[0]}, + {0x010ec0861, (CODECENTRY*)&AzaliaCodecAlc861Table[0]}, + {0x011d41984, (CODECENTRY*)&AzaliaCodecAd1984Table[0]}, { (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF} }; Modified: trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c Tue Jan 4 07:15:46 2011 (r6238) +++ trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c Tue Jan 4 07:39:29 2011 (r6239) @@ -31,7 +31,7 @@ * * */ -UINT8 FunctionNumber[] = +const static UINT8 FunctionNumber[] = { Fun_81, Fun_83, @@ -46,7 +46,7 @@ * * */ -UINT8 MaxZone[] = +const static UINT8 MaxZone[] = { 4, 4, @@ -61,7 +61,7 @@ * * */ -UINT8 MaxRegister[] = +const static UINT8 MaxRegister[] = { MSG_REG9, MSG_REGB, Modified: trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc Tue Jan 4 07:15:46 2011 (r6238) +++ trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc Tue Jan 4 07:39:29 2011 (r6239) @@ -1,75 +1,86 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2010 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# - -# CIMX Root directory -CIMX_ROOT = src/vendorcode/amd/cimx - -CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) -CIMX_INC += -I$(src)/southbridge/amd/cimx_wrapper/sb800 -CIMX_INC += -I$(CIMX_ROOT)/sb800 -#TODO merge withagesa lib functions -CIMX_INC += -I$(CIMX_ROOT)/lib - -# CIMX LIB files -romstage-y += MEMLIB.c -romstage-y += PCILIB.c -romstage-y += IOLIB.c -romstage-y += PMIOLIB.c -romstage-y += AMDLIB.c -romstage-y += SBPELIB.c -romstage-y += AMDSBLIB.c -romstage-y += SBPOR.c -romstage-y += ECLIB.c -romstage-y += EC.c -ramstage-y += DISPATCHER.c - -ramstage-y += ACPILIB.c -ramstage-y += AZALIA.c -ramstage-y += DISPATCHER.c -ramstage-y += ECfanc.c -ramstage-y += ECfanLIB.c -ramstage-y += GEC.c -ramstage-y += Gpp.c -ramstage-y += PMIO2LIB.c -ramstage-y += SATA.c -ramstage-y += SBCMN.c -ramstage-y += SBMAIN.c -ramstage-y += SBPOR.c -ramstage-y += MEMLIB.c -ramstage-y += PCILIB.c -ramstage-y += IOLIB.c -ramstage-y += PMIOLIB.c -ramstage-y += AMDLIB.c -ramstage-y += SBPELIB.c -ramstage-y += AMDSBLIB.c -ramstage-y += ECLIB.c -ramstage-y += EC.c -ramstage-y += SMM.c -ramstage-y += USB.c -#ramstage-y += LEGACY.c -#ramstage-y += SbModInf.c - -CIMX_CFLAGS = -export CIMX_ROOT -export CIMX_INC -export CIMX_CFLAGS -CC := $(CC) $(CIMX_INC) - -####################################################################### - +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# CIMX Root directory +CIMX_ROOT = src/vendorcode/amd/cimx + +CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) +CIMX_INC += -I$(src)/southbridge/amd/cimx_wrapper/sb800 +CIMX_INC += -I$(CIMX_ROOT)/sb800 +#TODO merge with agesa lib functions +CIMX_INC += -I$(CIMX_ROOT)/lib + +romstage-y += ACPILIB.c +romstage-y += AZALIA.c +romstage-y += DISPATCHER.c +romstage-y += ECfanc.c +romstage-y += ECfanLIB.c +romstage-y += GEC.c +romstage-y += Gpp.c +romstage-y += PMIO2LIB.c +romstage-y += SATA.c +romstage-y += SBCMN.c +romstage-y += SBMAIN.c +romstage-y += SBPOR.c +romstage-y += MEMLIB.c +romstage-y += PCILIB.c +romstage-y += IOLIB.c +romstage-y += PMIOLIB.c +romstage-y += AMDLIB.c +romstage-y += SBPELIB.c +romstage-y += AMDSBLIB.c +romstage-y += ECLIB.c +romstage-y += EC.c +romstage-y += SMM.c +romstage-y += USB.c + +ramstage-y += ACPILIB.c +ramstage-y += AZALIA.c +ramstage-y += DISPATCHER.c +ramstage-y += ECfanc.c +ramstage-y += ECfanLIB.c +ramstage-y += GEC.c +ramstage-y += Gpp.c +ramstage-y += PMIO2LIB.c +ramstage-y += SATA.c +ramstage-y += SBCMN.c +ramstage-y += SBMAIN.c +ramstage-y += SBPOR.c +ramstage-y += MEMLIB.c +ramstage-y += PCILIB.c +ramstage-y += IOLIB.c +ramstage-y += PMIOLIB.c +ramstage-y += AMDLIB.c +ramstage-y += SBPELIB.c +ramstage-y += AMDSBLIB.c +ramstage-y += ECLIB.c +ramstage-y += EC.c +ramstage-y += SMM.c +ramstage-y += USB.c +#ramstage-y += LEGACY.c +#ramstage-y += SbModInf.c + +CIMX_CFLAGS = +export CIMX_ROOT +export CIMX_INC +export CIMX_CFLAGS +CC := $(CC) $(CIMX_INC) + +####################################################################### + Modified: trunk/src/vendorcode/amd/cimx/sb800/SATA.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/SATA.c Tue Jan 4 07:15:46 2011 (r6238) +++ trunk/src/vendorcode/amd/cimx/sb800/SATA.c Tue Jan 4 07:39:29 2011 (r6239) @@ -166,7 +166,7 @@ * * */ -UINT32 sataIfCodeTable[] = +const static UINT32 sataIfCodeTable[] = { 0x01018F40, //sata class ID of IDE 0x01040040, //sata class ID of RAID @@ -182,7 +182,7 @@ * * */ -UINT16 sataDeviceIDTable[] = +const static UINT16 sataDeviceIDTable[] = { 0x4390, //sata device ID of IDE 0x4392, //sata device ID of RAID @@ -198,7 +198,7 @@ * * */ -SATAPHYSETTING sataPhyTable[] = +const static SATAPHYSETTING sataPhyTable[] = { {0x3006, 0x0056A607}, {0x2006, 0x00061400}, Modified: trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Tue Jan 4 07:15:46 2011 (r6238) +++ trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Tue Jan 4 07:39:29 2011 (r6239) @@ -73,7 +73,7 @@ * sbEarlyPostByteInitTable - PCI device registers initial during early POST. * */ -REG8MASK sbEarlyPostByteInitTable[] = +const static REG8MASK sbEarlyPostByteInitTable[] = { // SMBUS Device (Bus 0, Dev 20, Func 0) {0x00, SMBUS_BUS_DEV_FUN, 0}, @@ -124,7 +124,7 @@ * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST. * */ -AcpiRegWrite sbPmioEPostInitTable[] = +const static AcpiRegWrite sbPmioEPostInitTable[] = { // HPET workaround {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, @@ -241,7 +241,7 @@ * abTblEntry800 - AB-Link Configuration Table for SB800 * */ -ABTBLENTRY abTblEntry800[] = +const static ABTBLENTRY abTblEntry800[] = { // RPR Enable downstream posted transactions to pass non-posted transactions. {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16}, @@ -287,7 +287,7 @@ * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature * */ -ABTBLENTRY SbPcieOrderRule[] = +const static ABTBLENTRY SbPcieOrderRule[] = { // abPostPassNpDownStreamTbl {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31}, From Kerry.She at amd.com Tue Jan 4 07:25:55 2011 From: Kerry.She at amd.com (She, Kerry) Date: Tue, 4 Jan 2011 14:25:55 +0800 Subject: [coreboot] .cb files In-Reply-To: References: <20110103150759.10213.qmail@stuge.se> Message-ID: Hi ali hagigat, -----Original Message----- From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of ali hagigat Sent: Tuesday, January 04, 2011 1:30 PM To: coreboot at coreboot.org Cc: peter at stuge.se Subject: Re: [coreboot] .cb files Peter, Thank you. So devicetree.cb files are written by hand and the compilation process does not use them? They are just some information for the developers? [She, Kerry] no, during the compilation, sconfig will use it to generate the static device tree, Please see util/sconfig, and build/mainboard/kontron/986lcd-m/static.c after your compilation. About: file:///root/build/coreboot/coreboot-v4/src/mainboard/kontron/986lcd-m/devicetree.cb: #device pci 1e.2 off end # AC'97 Audio It means that AC'97 Audio is on Bus#=1 and Function#=2? But all the devices of the south bridge, ICH7 are on Bus number 0, as far as I know. Why you have not written, Bus number, Function number, Device number, Register number clearly. device pci 1d.0 on end, What does it mean, 1d.0? Regards On Mon, Jan 3, 2011 at 6:37 PM, Peter Stuge wrote: > ali hagigat wrote: >> How .cb files are created? > > As was pointed out already, by hand. > > >> and what they are used for? > > Describing fixed parts of a system. What buses there are and what > devices are on them. > > Please suggest how we can improve the syntax of .cb files. > I want them to be self-documenting enough so that you can understand > the above from just looking at the files. Can you help? > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot From Kerry.She at amd.com Tue Jan 4 08:51:32 2011 From: Kerry.She at amd.com (She, Kerry) Date: Tue, 4 Jan 2011 15:51:32 +0800 Subject: [coreboot] (no subject) Message-ID: Hello, I have made a little bit cleanup from the patches originally made by Bao Zheng, This sb800 code is derived from sb700 implementation. Release this patch is NOT to confusing people, but make other patches based on this implementation also works. So this patch don?t need to be checked into the tree. Regards, Kerry She < kerry.she at amd.com> Tel: 86-10-6280-1415 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: bimini_derived_from_sb700.diff Type: application/octet-stream Size: 3563 bytes Desc: bimini_derived_from_sb700.diff URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: sb800_derived_from_sb700.diff Type: application/octet-stream Size: 97178 bytes Desc: sb800_derived_from_sb700.diff URL: From Kerry.She at amd.com Tue Jan 4 09:12:01 2011 From: Kerry.She at amd.com (She, Kerry) Date: Tue, 4 Jan 2011 16:12:01 +0800 Subject: [coreboot] sb800 code derived from sb700 implementation Message-ID: Sorry to send again, forget the subject last email I have made a little bit cleanup from the patches originally made by Bao Zheng, This sb800 code is derived from sb700 implementation. Release this patch is NOT to confusing people, but make other patches based on this implementation also works. So this patch don?t need to be checked into the tree. Regards, Kerry She < kerry.she at amd.com> Tel: 86-10-6280-1415 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: bimini_derived_from_sb700.diff Type: application/octet-stream Size: 3563 bytes Desc: bimini_derived_from_sb700.diff URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: sb800_derived_from_sb700.diff Type: application/octet-stream Size: 97178 bytes Desc: sb800_derived_from_sb700.diff URL: From neotheuser at ymail.com Tue Jan 4 09:51:36 2011 From: neotheuser at ymail.com (Neo The User) Date: Tue, 4 Jan 2011 00:51:36 -0800 (PST) Subject: [coreboot] Test SeaBIOS AHCI support Message-ID: <266793.59619.qm@web114120.mail.gq1.yahoo.com> Hi, I have a GA-MA785GM-US2H (GIGABYTE 785GM board) with AHCI SATA, and if I have AHCI off in SeaBIOS, I get caught in an infinite restarting loop. If I have it on, I can actually reach GRUB and select my kernel but Windows 7 and Linux both don't start and with linux, a kernel panic happens with the last message on the screen "[ 0.180179] pci 0000:00:11.0: set SATA to AHCI mode" I spent about a month on and off porting coreboot to my board, but the only reason it took me that long was because I only have one PC and I do not have an environment set up for serial debugging, so it was all guess work. I noticed that the MA785GMT and MA78GM were in the tree so I based most of the work off of those two boards, plus some lines from the Tilapia board. I have attached the somewhat working port as a patch (ma785gm-us2h.patch) and I didn't touch the GPL headers at all, keeping the original ones from Tilapia, if that was ok. If not, I'll be glad to change it accordingly. I hope the patch format is correct! Signed-off-by: Alec Ari --- On Fri, 12/31/10, Scott Duplichan wrote: > From: Scott Duplichan > Subject: Re: [coreboot] Test SeaBIOS AHCI support > To: "'Kevin O'Connor'" > Cc: coreboot at coreboot.org > Date: Friday, December 31, 2010, 4:43 PM > > On Fri, Dec 31, 2010 at 10:21:32AM -0600, Scott Duplichan > wrote: > > Hello Kevin, > > > > Thanks a lot. Is this native 16-bit AHCI support that > doesn't rely on an option rom? > > > > ]It's native AHCI DMA support.? (No option rom > needed.) > > ]-Kevin > > > That is great to hear. Some HP notebooks have this > capability, but > I know of no others. This setup should allow cutting > seconds from > Windows boot time because Windows spends lots of time on > IDE drives > that are not installed. If all IDE devices are disabled and > only > AHCI visible, Windows can boot a lot faster. > > I made an initial test using coreboot+seabios on an AMD > RS780/SB700 > system. So far it is not detecting the drives. But this > test required > hacking in code to disable the SB700 IDE device and switch > the SATA > device from IDE mode to AHCI mode. I have not yet checked > to see if > that code is even working correctly. I will continue > debugging this > in a day or two. > > Thanks, > Scott > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- A non-text attachment was scrubbed... Name: ma785gm-us2h.patch Type: application/octet-stream Size: 132687 bytes Desc: not available URL: From peter at stuge.se Tue Jan 4 12:16:45 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 4 Jan 2011 12:16:45 +0100 Subject: [coreboot] .cb files In-Reply-To: References: <20110103150759.10213.qmail@stuge.se> Message-ID: <20110104111645.16957.qmail@stuge.se> ali hagigat wrote: > So devicetree.cb files are written by hand and the compilation > process does not use them? They are just some information for the > developers? Of course not, that would be redundant. As Kerry pointed out, they are very much part of the build process. You can also see this very clearly when watching the make output. > #device pci 1e.2 off end # AC'97 Audio > It means that AC'97 Audio is on Bus#=1 and Function#=2? I don't know about the bus number because you took the above line out of context, but device 0x1e function 2 yes. > But all the devices of the south bridge, ICH7 are on Bus number 0, > as far as I know. > Why you have not written, Bus number, Function number, Device number, > Register number clearly. Because it is not a list of registers. Device and function is there and bus is implicit, but the file encodes more complex knowledge about the board than simply a list of register/value pairs. > device pci 1d.0 on end, What does it mean, 1d.0? Device 0x1d function 0. I would hope that this is obvious with a little knowledge about the respective chipset. If you have the lspci next to you I think that devicetree.cb is rather clear. The bus number is implicit because the file is structured rather than a simple list. The indentation and the "end" keywords try to make this obvious. Again, please say how you think the information can be structured in a better way. //Peter From peter at stuge.se Tue Jan 4 12:21:26 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 4 Jan 2011 12:21:26 +0100 Subject: [coreboot] sb800 code derived from sb700 implementation In-Reply-To: References: Message-ID: <20110104112126.17789.qmail@stuge.se> She, Kerry wrote: > I have made a little bit cleanup from the patches originally made > by Bao Zheng, > > This sb800 code is derived from sb700 implementation. > > Release this patch is NOT to confusing people, but make other > patches based on this implementation also works. > > So this patch don?t need to be checked into the tree. Thanks! I think this is a nice addition. Maybe we should add a Kconfig option to choose between cimx and non-cimx? //Peter From peter at stuge.se Tue Jan 4 12:45:14 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 4 Jan 2011 12:45:14 +0100 Subject: [coreboot] Test SeaBIOS AHCI support In-Reply-To: <266793.59619.qm@web114120.mail.gq1.yahoo.com> References: <266793.59619.qm@web114120.mail.gq1.yahoo.com> Message-ID: <20110104114514.21919.qmail@stuge.se> Hi Alec, Neo The User wrote: > I have attached the somewhat working port as a patch > (ma785gm-us2h.patch) Cool! > I hope the patch format is correct! Well, I'd say no. It is impossible to review this patch because it duplicates (nearly) all code for another board. It would be very good if you could start with a patch that is simply a diff from the ma785gmt board. Finally, when copying files later, into the new ma785gm directory, please make sure to use svn to do copies, so that patches become much smaller, or at the very least that the history is kept. But please first start with a diff against an existing board. If the differences are small enough maybe the same code can handle both boards. //Peter From neotheuser at ymail.com Tue Jan 4 16:27:39 2011 From: neotheuser at ymail.com (Neo The User) Date: Tue, 4 Jan 2011 07:27:39 -0800 (PST) Subject: [coreboot] Test SeaBIOS AHCI support Message-ID: <256385.89886.qm@web114109.mail.gq1.yahoo.com> Hello! New patch :) Sorry about that, I have little to no experience with subversion. Also I found out that the rebooting loop wasn't caused by the AHCI SATA being off, but rather the console level for serial output was below 7 in the coreboot config file... I found it very strange. Anyway, the real result of having AHCI SATA off in SeaBIOS causes the payload to just hang, before it says to press F12. With it on, I can access GRUB but I get kernel panics in any Linux distro. NetBSD also fails. I attached a new patch, using svn copy and such from Tilapia, keeping almost everything the same in the diff. After creating the diff, I poked around a bit more, but I couldn't solve the kernel panics. This isn't really a big concern for me personally but I thought it would be cool to have a board with over 1,100 reviews on newegg that would be supported by Coreboot. Might spark some attention as well. -Alec --- On Tue, 1/4/11, Peter Stuge wrote: > From: Peter Stuge > Subject: Re: [coreboot] Test SeaBIOS AHCI support > To: coreboot at coreboot.org > Date: Tuesday, January 4, 2011, 11:45 AM > Hi Alec, > > Neo The User wrote: > > I have attached the somewhat working port as a patch > > (ma785gm-us2h.patch) > > Cool! > > > > I hope the patch format is correct! > > Well, I'd say no. It is impossible to review this patch > because it > duplicates (nearly) all code for another board. > > It would be very good if you could start with a patch that > is simply > a diff from the ma785gmt board. > > Finally, when copying files later, into the new ma785gm > directory, > please make sure to use svn to do copies, so that patches > become much > smaller, or at the very least that the history is kept. > > But please first start with a diff against an existing > board. If the > differences are small enough maybe the same code can handle > both boards. > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- A non-text attachment was scrubbed... Name: ma785gm-us2h.diff Type: application/octet-stream Size: 7588 bytes Desc: not available URL: From uwe at hermann-uwe.de Tue Jan 4 17:55:13 2011 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Tue, 4 Jan 2011 17:55:13 +0100 Subject: [coreboot] [PATCH 1/2] Geode GX2 cleanup again In-Reply-To: <4D1D7EDE.1060907@coreboot.org> References: <201012302248.40411.njacobs8@hetnet.nl> <4D1D7EDE.1060907@coreboot.org> Message-ID: <20110104165513.GC9074@greenwood> On Fri, Dec 31, 2010 at 07:57:34AM +0100, Stefan Reinauer wrote: > On 12/30/10 10:48 PM, Nils wrote: > > - {0xffffffff, {0xffffffff, 0xffffffff}}, > > + {0xFFFFFFFF, {0xFFFFFFFF, 0xFFFFFFFF}}, > > I don't think we should capitalize hexadecimal numbers. We never did (on > purpose) anywhere else. > > Bikeshed, anyone? Yup, I also prefer non-capitalized, but that's probably a matter of taste. I'm relatively sure the majority of our code-base uses lower-case right now. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org From svn at coreboot.org Tue Jan 4 18:36:55 2011 From: svn at coreboot.org (repository service) Date: Tue, 04 Jan 2011 18:36:55 +0100 Subject: [coreboot] [commit] r6240 - trunk/src/southbridge/nvidia/ck804 Message-ID: Author: uwe Date: Tue Jan 4 18:36:55 2011 New Revision: 6240 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6240 Log: CK804: Cosmetic fixes, switch to u8 et al. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/src/southbridge/nvidia/ck804/Kconfig trunk/src/southbridge/nvidia/ck804/chip.h trunk/src/southbridge/nvidia/ck804/ck804.c trunk/src/southbridge/nvidia/ck804/ck804.h trunk/src/southbridge/nvidia/ck804/early_setup.c trunk/src/southbridge/nvidia/ck804/early_setup_car.c trunk/src/southbridge/nvidia/ck804/early_smbus.c trunk/src/southbridge/nvidia/ck804/ide.c trunk/src/southbridge/nvidia/ck804/lpc.c trunk/src/southbridge/nvidia/ck804/nic.c trunk/src/southbridge/nvidia/ck804/pci.c trunk/src/southbridge/nvidia/ck804/pcie.c trunk/src/southbridge/nvidia/ck804/sata.c trunk/src/southbridge/nvidia/ck804/smbus.c trunk/src/southbridge/nvidia/ck804/smbus.h trunk/src/southbridge/nvidia/ck804/usb.c trunk/src/southbridge/nvidia/ck804/usb2.c Modified: trunk/src/southbridge/nvidia/ck804/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/ck804/Kconfig Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/Kconfig Tue Jan 4 18:36:55 2011 (r6240) @@ -8,7 +8,7 @@ if SOUTHBRIDGE_NVIDIA_CK804 config BOOTBLOCK_SOUTHBRIDGE_INIT - string + string default "southbridge/nvidia/ck804/bootblock.c" config ID_SECTION_OFFSET Modified: trunk/src/southbridge/nvidia/ck804/chip.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/chip.h Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/chip.h Tue Jan 4 18:36:55 2011 (r6240) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef CK804_CHIP_H -#define CK804_CHIP_H +#ifndef SOUTHBRIDGE_NVIDIA_CK804_CHIP_H +#define SOUTHBRIDGE_NVIDIA_CK804_CHIP_H struct southbridge_nvidia_ck804_config { unsigned int usb1_hc_reset : 1; Modified: trunk/src/southbridge/nvidia/ck804/ck804.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/ck804.c Tue Jan 4 18:36:55 2011 (r6240) @@ -26,7 +26,7 @@ #include #include "ck804.h" -static uint32_t final_reg; +static u32 final_reg; static device_t find_lpc_dev(device_t dev, unsigned devfn) { @@ -41,7 +41,7 @@ && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE))) { - uint32_t id; + u32 id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); if ((id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) @@ -61,8 +61,8 @@ { device_t lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; - uint32_t reg_old, reg; - uint8_t byte; + u32 reg_old, reg; + u8 byte; struct southbridge_nvidia_ck804_config *conf; conf = dev->chip_info; Modified: trunk/src/southbridge/nvidia/ck804/ck804.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804.h Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/ck804.h Tue Jan 4 18:36:55 2011 (r6240) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef CK804_H -#define CK804_H +#ifndef SOUTHBRIDGE_NVIDIA_CK804_CK804_H +#define SOUTHBRIDGE_NVIDIA_CK804_CK804_H #include "chip.h" Modified: trunk/src/southbridge/nvidia/ck804/early_setup.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/early_setup.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/early_setup.c Tue Jan 4 18:36:55 2011 (r6240) @@ -20,7 +20,7 @@ #include -static int set_ht_link_ck804(uint8_t ht_c_num) +static int set_ht_link_ck804(u8 ht_c_num) { unsigned vendorid = 0x10de; unsigned val = 0x01610169; @@ -91,7 +91,7 @@ static void ck804_early_set_port(void) { static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, #if CONFIG_CK804_NUM > 1 PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE, #endif @@ -229,7 +229,7 @@ RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, -#if CONFIG_CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, Modified: trunk/src/southbridge/nvidia/ck804/early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/early_setup_car.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/early_setup_car.c Tue Jan 4 18:36:55 2011 (r6240) @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static int set_ht_link_ck804(uint8_t ht_c_num) +static int set_ht_link_ck804(u8 ht_c_num) { unsigned vendorid = 0x10de; unsigned val = 0x01610169; @@ -89,13 +89,12 @@ int j; for (j = 0; j < ck804_num; j++) { u32 dev; - if (busn[j] == 0) //sb chain + if (busn[j] == 0) /* SB chain */ dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); else dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); setup_resource_map_offset(ctrl_devport_conf, - ARRAY_SIZE(ctrl_devport_conf), dev, - io_base[j]); + ARRAY_SIZE(ctrl_devport_conf), dev, io_base[j]); } } @@ -110,13 +109,12 @@ int j; for (j = 0; j < ck804_num; j++) { u32 dev; - if (busn[j] == 0) //sb chain + if (busn[j] == 0) /* SB chain */ dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); else dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); setup_resource_map_offset(ctrl_devport_conf_clear, - ARRAY_SIZE(ctrl_devport_conf_clear), dev, - io_base[j]); + ARRAY_SIZE(ctrl_devport_conf_clear), dev, io_base[j]); } } @@ -165,7 +163,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - /* Activate master port on primary SATA controller. */ + /* Activate master port on primary SATA controller. */ RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x50), ~(0x1f000013), 0x15000013, RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x64), ~(0x00000001), 0x00000001, RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x68), ~(0x02000000), 0x02000000, @@ -196,7 +194,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), -//SYSCTRL + /* SYSCTRL */ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), #if CONFIG_CK804_USE_NIC @@ -211,7 +209,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif - }; static const unsigned int ctrl_conf_multiple[] = { @@ -267,7 +264,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, -/* This line doesn't exist in the non-CAR version. */ + /* This line doesn't exist in the non-CAR version. */ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), @@ -296,8 +293,8 @@ } setup_resource_map_x_offset(ctrl_conf_slave, - ARRAY_SIZE(ctrl_conf_slave), - PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]); + ARRAY_SIZE(ctrl_conf_slave), + PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]); } for (j = 0; j < ck804_num; j++) { @@ -325,9 +322,9 @@ int i, ck804_num = 0; for (i = 0; i < 4; i++) { - uint32_t id; + u32 id; device_t dev; - if (i == 0) // SB chain + if (i == 0) /* SB chain */ dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0); else dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0); Modified: trunk/src/southbridge/nvidia/ck804/early_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/early_smbus.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/early_smbus.c Tue Jan 4 18:36:55 2011 (r6240) @@ -64,7 +64,7 @@ } int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address, - unsigned char val) + unsigned char val) { return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val); } Modified: trunk/src/southbridge/nvidia/ck804/ide.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ide.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/ide.c Tue Jan 4 18:36:55 2011 (r6240) @@ -28,9 +28,9 @@ static void ide_init(struct device *dev) { struct southbridge_nvidia_ck804_config *conf; - uint32_t dword; - uint16_t word; - uint8_t byte; + u32 dword; + u16 word; + u8 byte; conf = dev->chip_info; Modified: trunk/src/southbridge/nvidia/ck804/lpc.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/lpc.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/lpc.c Tue Jan 4 18:36:55 2011 (r6240) @@ -53,16 +53,16 @@ static void lpc_common_init(device_t dev) { - uint8_t byte; - uint32_t dword; + u8 byte; + u32 dword; - /* I/O APIC initialization */ + /* I/O APIC initialization. */ byte = pci_read_config8(dev, 0x74); byte |= (1 << 0); /* Enable APIC. */ pci_write_config8(dev, 0x74, byte); dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */ - setup_ioapic(dword, 0); // Don't rename IOAPIC ID + setup_ioapic(dword, 0); /* Don't rename IOAPIC ID. */ #if 1 dword = pci_read_config32(dev, 0xe4); @@ -78,8 +78,8 @@ static void rom_dummy_write(device_t dev) { - uint8_t old, new; - uint8_t *p; + u8 old, new; + u8 *p; old = pci_read_config8(dev, 0x88); new = old | 0xc0; @@ -92,7 +92,7 @@ pci_write_config8(dev, 0x6d, new); /* Dummy write. */ - p = (uint8_t *) 0xffffffe0; + p = (u8 *) 0xffffffe0; old = 0; *p = old; old = *p; @@ -113,11 +113,11 @@ printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address); } -unsigned pm_base=0; +unsigned pm_base = 0; static void lpc_init(device_t dev) { - uint8_t byte, byte_old; + u8 byte, byte_old; int on, nmi_option; lpc_common_init(dev); @@ -125,7 +125,7 @@ pm_base = pci_read_config32(dev, 0x60) & 0xff00; printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base); -#if CK804_CHIP_REV==1 +#if CK804_CHIP_REV == 1 if (dev->bus->secondary != 1) return; #endif @@ -136,7 +136,7 @@ pci_write_config8(dev, 0x46, byte | (1 << 0)); #endif - /* power after power fail */ + /* Power after power fail */ on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); @@ -150,18 +150,17 @@ on = SLOW_CPU_OFF; get_option(&on, "slow_cpu"); if (on) { - uint16_t pm10_bar; - uint32_t dword; + u16 pm10_bar; + u32 dword; pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); outl(((on << 1) + 0x10), (pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); on = 8 - on; printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on * 12) + (on >> 1), (on & 1) * 5); + (on * 12) + (on >> 1), (on & 1) * 5); } #if 0 -// default is enabled - /* Enable Port 92 fast reset. */ + /* Enable Port 92 fast reset (default is enabled). */ byte = pci_read_config8(dev, 0xe8); byte |= ~(1 << 3); pci_write_config8(dev, 0xe8, byte); @@ -178,11 +177,10 @@ byte_old = byte; nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); - if (nmi_option) { + if (nmi_option) byte &= ~(1 << 7); /* Set NMI. */ - } else { + else byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ - } if (byte != byte_old) outb(byte, 0x70); @@ -236,12 +234,11 @@ * * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. - * */ static void ck804_lpc_enable_childrens_resources(device_t dev) { struct bus *link; - uint32_t reg, reg_var[4]; + u32 reg, reg_var[4]; int i, var_num = 0; reg = pci_read_config32(dev, 0xa0); @@ -252,7 +249,7 @@ if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; for (res = child->resource_list; res; res = res->next) { - unsigned long base, end; // don't need long long + unsigned long base, end; /* Don't need long long. */ if (!(res->flags & IORESOURCE_IO)) continue; base = res->base; @@ -279,8 +276,9 @@ break; } if (base == 0x290 || base >= 0x400) { + /* Only 4 var; compact them? */ if (var_num >= 4) - continue; // only 4 var ; compact them ? + continue; reg |= (1 << (28 + var_num)); reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16); } Modified: trunk/src/southbridge/nvidia/ck804/nic.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/nic.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/nic.c Tue Jan 4 18:36:55 2011 (r6240) @@ -29,10 +29,10 @@ static void nic_init(struct device *dev) { - uint32_t dword, old, mac_h, mac_l; + u32 dword, old, mac_h, mac_l; int eeprom_valid = 0; struct southbridge_nvidia_ck804_config *conf; - static uint32_t nic_index = 0; + static u32 nic_index = 0; unsigned long base; struct resource *res; Modified: trunk/src/southbridge/nvidia/ck804/pci.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/pci.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/pci.c Tue Jan 4 18:36:55 2011 (r6240) @@ -28,7 +28,7 @@ static void pci_init(struct device *dev) { - uint32_t dword; + u32 dword; device_t pci_domain_dev; struct resource *mem, *pref; Modified: trunk/src/southbridge/nvidia/ck804/pcie.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/pcie.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/pcie.c Tue Jan 4 18:36:55 2011 (r6240) @@ -27,7 +27,7 @@ static void pcie_init(struct device *dev) { - uint32_t dword; + u32 dword; /* Enable PCI error detecting. */ dword = pci_read_config32(dev, 0x04); Modified: trunk/src/southbridge/nvidia/ck804/sata.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/sata.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/sata.c Tue Jan 4 18:36:55 2011 (r6240) @@ -35,11 +35,11 @@ // reset = 1 : reset // reset = 0 : clear { - uint32_t *base; - uint32_t dword; + u32 *base; + u32 dword; int loop; - base = (uint32_t *) pci_read_config32(dev, 0x24); + base = (u32 *) pci_read_config32(dev, 0x24); printk(BIOS_DEBUG, "base = %08lx\n", base); @@ -95,7 +95,7 @@ static void sata_init(struct device *dev) { - uint32_t dword; + u32 dword; struct southbridge_nvidia_ck804_config *conf; conf = dev->chip_info; @@ -161,7 +161,6 @@ sata_com_reset(dev, 1); /* For discover some s-atapi device. */ #endif - } static struct device_operations sata_ops = { Modified: trunk/src/southbridge/nvidia/ck804/smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/smbus.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/smbus.c Tue Jan 4 18:36:55 2011 (r6240) @@ -43,7 +43,7 @@ return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(device_t dev, u8 val) { unsigned device; struct resource *res; @@ -57,7 +57,7 @@ return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(device_t dev, u8 address) { unsigned device; struct resource *res; @@ -71,7 +71,7 @@ return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(device_t dev, u8 address, u8 val) { unsigned device; struct resource *res; Modified: trunk/src/southbridge/nvidia/ck804/smbus.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/smbus.h Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/smbus.h Tue Jan 4 18:36:55 2011 (r6240) @@ -90,7 +90,7 @@ outb(0, smbus_io_base + SMBHSTCMD); smbus_delay(); - /* Byte data recv */ + /* Byte data recv. */ outb(0x05, smbus_io_base + SMBHSTPRTCL); smbus_delay(); @@ -98,7 +98,7 @@ if (smbus_wait_until_done(smbus_io_base) < 0) return -3; - /* Lose check */ + /* Lose check. */ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* Read results of transaction. */ @@ -140,7 +140,7 @@ if (smbus_wait_until_done(smbus_io_base) < 0) return -3; - /* Lose check */ + /* Lose check. */ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; if (global_status_register != 0x80) @@ -169,7 +169,7 @@ outb(address & 0xff, smbus_io_base + SMBHSTCMD); smbus_delay(); - /* Byte data read */ + /* Byte data read. */ outb(0x07, smbus_io_base + SMBHSTPRTCL); smbus_delay(); @@ -177,7 +177,7 @@ if (smbus_wait_until_done(smbus_io_base) < 0) return -3; - /* Lose check */ + /* Lose check. */ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* Read results of transaction. */ @@ -219,7 +219,7 @@ if (smbus_wait_until_done(smbus_io_base) < 0) return -3; - /* Lose check */ + /* Lose check. */ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; if (global_status_register != 0x80) Modified: trunk/src/southbridge/nvidia/ck804/usb.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/usb.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/usb.c Tue Jan 4 18:36:55 2011 (r6240) @@ -28,20 +28,22 @@ static void usb1_init(struct device *dev) { struct southbridge_nvidia_ck804_config const *conf = dev->chip_info; - if (conf->usb1_hc_reset) { - /* - * Somehow the warm reset does not really reset the USB - * controller. Later, during boot, when the Bus Master bit is - * set, the USB controller trashes the memory, causing weird - * misbehavior. Was detected on Sun Ultra40, where mptable - * was damaged. - */ - uint32_t bar0 = pci_read_config32(dev, 0x10); - uint32_t *regs = (uint32_t *) (bar0 & ~0xfff); - /* OHCI USB HCCommandStatus Register, HostControllerReset bit */ - regs[2] |= 1; - } + if (!conf->usb1_hc_reset) + return; + + /* + * Somehow the warm reset does not really reset the USB + * controller. Later, during boot, when the Bus Master bit is + * set, the USB controller trashes the memory, causing weird + * misbehavior. Was detected on Sun Ultra40, where mptable + * was damaged. + */ + u32 bar0 = pci_read_config32(dev, 0x10); + u32 *regs = (u32 *) (bar0 & ~0xfff); + + /* OHCI USB HCCommandStatus Register, HostControllerReset bit */ + regs[2] |= 1; } static struct device_operations usb_ops = { Modified: trunk/src/southbridge/nvidia/ck804/usb2.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/usb2.c Tue Jan 4 07:39:29 2011 (r6239) +++ trunk/src/southbridge/nvidia/ck804/usb2.c Tue Jan 4 18:36:55 2011 (r6240) @@ -27,7 +27,8 @@ static void usb2_init(struct device *dev) { - uint32_t dword; + u32 dword; + dword = pci_read_config32(dev, 0xf8); dword |= 40; pci_write_config32(dev, 0xf8, dword); From marcj303 at gmail.com Tue Jan 4 19:10:01 2011 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 4 Jan 2011 11:10:01 -0700 Subject: [coreboot] IDE interface support code for AMDLX800-CS5536 In-Reply-To: References: Message-ID: On Sat, Jan 1, 2011 at 1:38 PM, Darmawan Salihun wrote: >> On 1/2/11, Darmawan Salihun wrote: >> Hi guys, >> >> I'm looking for the support code for the IDE controller in CS5536 >> southbridge. >> I checked-out Coreboot source code but only saw Flash interface >> support in there. >> I saw the IDE controller is switched to Flash interface support with >> the "DEADBEEF" >> magic number. >> >> The board I'm working with right now use the primary IDE channel for both >> HDD connectors and a CF connectors. I need to know how to initialize >> the chipset >> correctly for this setup. The CF connector is the primary master and >> the HDD connector is primary slave. >> >> I've checked with lspci and " cat /proc/ioports" and I found that the >> legacy I/O ports >> for IDE controller is working just fine. Also, the I/O ports for >> IDE bus mastering (SFF-8038i) registers are allocated correctly. >> > > I mean with the current code that I tested the I/O ports allocation is > just fine. > >> Thanks, >> >> Darmawan Hi Darmawan, The IDE should get setup by default if the flash switch path is not selected. I assume you have already read the registers in the databook.. http://support.amd.com/us/Embedded_TechDocs/33238G_cs5536_db.pdf There may be more information on the embedded developer site. The embedded guys are coreboot friendly, so they should be able to point at the appropriate doc. http://wwwd.amd.com/amd/devsite.nsf/home/welcome.htm?opendocument&login Marc -- http://se-eng.com From svn at coreboot.org Tue Jan 4 20:51:34 2011 From: svn at coreboot.org (repository service) Date: Tue, 04 Jan 2011 20:51:34 +0100 Subject: [coreboot] [commit] r6241 - trunk/src/southbridge/nvidia/mcp55 Message-ID: Author: uwe Date: Tue Jan 4 20:51:33 2011 New Revision: 6241 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6241 Log: MCP55: Cosmetic fixes, switch to u8 et al. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/src/southbridge/nvidia/mcp55/azalia.c trunk/src/southbridge/nvidia/mcp55/bootblock.c trunk/src/southbridge/nvidia/mcp55/chip.h trunk/src/southbridge/nvidia/mcp55/early_ctrl.c trunk/src/southbridge/nvidia/mcp55/early_setup_car.c trunk/src/southbridge/nvidia/mcp55/early_setup_ss.h trunk/src/southbridge/nvidia/mcp55/early_smbus.c trunk/src/southbridge/nvidia/mcp55/ht.c trunk/src/southbridge/nvidia/mcp55/ide.c trunk/src/southbridge/nvidia/mcp55/lpc.c trunk/src/southbridge/nvidia/mcp55/mcp55.c trunk/src/southbridge/nvidia/mcp55/mcp55.h trunk/src/southbridge/nvidia/mcp55/nic.c trunk/src/southbridge/nvidia/mcp55/pci.c trunk/src/southbridge/nvidia/mcp55/pcie.c trunk/src/southbridge/nvidia/mcp55/sata.c trunk/src/southbridge/nvidia/mcp55/smbus.c trunk/src/southbridge/nvidia/mcp55/usb2.c Modified: trunk/src/southbridge/nvidia/mcp55/azalia.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/azalia.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/azalia.c Tue Jan 4 20:51:33 2011 (r6241) @@ -28,33 +28,31 @@ #include "mcp55.h" #define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) static int set_bits(u32 port, u32 mask, u32 val) { u32 reg32; int count; - /* Write (val & mask) to port */ + /* Write (val & mask) to port. */ val &= mask; reg32 = read32(port); reg32 &= ~mask; reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was written to it. */ count = 50; do { - /* Wait 1ms based on BKDG wait time */ + /* Wait 1ms based on BKDG wait time. */ mdelay(1); reg32 = read32(port); reg32 &= mask; } while ((reg32 != val) && --count); - /* Timeout occurred */ + /* Timeout occurred. */ if (!count) return -1; return 0; @@ -64,15 +62,15 @@ { u32 reg32; - /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ + /* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0]. */ if (set_bits(base + 0x08, 1, 0) == -1) goto no_codec; - /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + /* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0]. */ if (set_bits(base + 0x08, 1, 1) == -1) goto no_codec; - /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in codec location (BAR + 0xe)[2..0]. */ reg32 = read32(base + 0xe); reg32 &= 0x0f; if (!reg32) @@ -81,48 +79,45 @@ return reg32; no_codec: - /* Codec Not found */ - /* Put HDA back in reset (BAR + 0x8) [0] */ + /* Codec not found. */ + /* Put HDA back in reset (BAR + 0x8)[0]. */ set_bits(base + 0x08, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } -u32 * cim_verb_data = NULL; +u32 *cim_verb_data = NULL; u32 cim_verb_data_size = 0; -static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb) +static u32 find_verb(struct device *dev, u32 viddid, u32 **verb) { - int idx=0; + int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; /* in u32 */ if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; /* Skip verb + header. */ continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } - /* Not all codecs need to load another verb */ + /* Not all codecs need to load another verb. */ return 0; } /** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ - static int wait_for_ready(u32 base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration. */ int timeout = 50; - while(timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + while (timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -132,25 +127,21 @@ } /** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ - static int wait_for_valid(u32 base) { u32 reg32; - /* Send the verb to the codec */ + /* Send the verb to the codec. */ reg32 = read32(base + 0x68); reg32 |= (1 << 0) | (1 << 1); write32(base + 0x68, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration. */ int timeout = 50; - while(timeout--) { + while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) @@ -163,9 +154,8 @@ static void codec_init(struct device *dev, u32 base, int addr) { - u32 reg32; + u32 reg32, verb_size; u32 *verb; - u32 verb_size; int i; printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); @@ -216,44 +206,44 @@ static void azalia_init(struct device *dev) { - u32 base; + u32 base, codec_mask, reg32; struct resource *res; - u32 codec_mask; u8 reg8; - u32 reg32; - /* Set Bus Master */ + /* Set bus master. */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); - pci_write_config8(dev, 0x3c, 0x0a); // unused? + pci_write_config8(dev, 0x3c, 0x0a); // TODO: Unused? reg8 = pci_read_config8(dev, 0x40); - reg8 |= (1 << 3); // Clear Clock Detect Bit + reg8 |= (1 << 3); /* Clear Clock Detect bit. */ pci_write_config8(dev, 0x40, reg8); - reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over + reg8 &= ~(1 << 3); /* Keep CLKDETCLR from clearing the bit over and over. */ pci_write_config8(dev, 0x40, reg8); - reg8 |= (1 << 2); // Enable clock detection + reg8 |= (1 << 2); /* Enable clock detection. */ pci_write_config8(dev, 0x40, reg8); mdelay(1); reg8 = pci_read_config8(dev, 0x40); - printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97"); + printk(BIOS_DEBUG, "Azalia: codec type: %s\n", + (reg8 & (1 << 1)) ? "Azalia" : "AC97"); - // - reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb + reg8 = pci_read_config8(dev, 0x40); /* Audio control */ + reg8 |= 1; /* Select Azalia mode. TODO: Control via devicetree.cb. */ pci_write_config8(dev, 0x40, reg8); - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported + reg8 = pci_read_config8(dev, 0x4d); /* Docking status. */ + reg8 &= ~(1 << 7); /* Docking not supported. */ pci_write_config8(dev, 0x4d, reg8); res = find_resource(dev, 0x10); if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + /* + * NOTE: This will break as soon as the Azalia gets a BAR above + * 4G. Is there anything we can do about it? + */ base = (u32)res->base; printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); codec_mask = codec_detect(base); @@ -276,7 +266,7 @@ } static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = azalia_set_subsystem, }; static struct device_operations azalia_ops = { @@ -294,4 +284,3 @@ .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_AZA, }; - Modified: trunk/src/southbridge/nvidia/mcp55/bootblock.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/bootblock.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/bootblock.c Tue Jan 4 20:51:33 2011 (r6241) @@ -28,28 +28,28 @@ static void mcp55_enable_rom(void) { - uint8_t byte; - uint16_t word; + u8 byte; + u16 word; device_t addr; - /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ + /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ #if 0 - /* default MCP55 LPC single */ + /* Default MCP55 LPC single */ addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0); #else // addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0); - addr = PCI_DEV(0, (MCP55_DEVN_BASE+1), 0); + addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0); #endif - /* Set the 4MB enable bit bit */ + /* Set the 15MB enable bits. */ byte = pci_read_config8(addr, 0x88); - byte |= 0xff; //256K + byte |= 0xff; /* 256K */ pci_write_config8(addr, 0x88, byte); byte = pci_read_config8(addr, 0x8c); - byte |= 0xff; //1M + byte |= 0xff; /* 1M */ pci_write_config8(addr, 0x8c, byte); word = pci_read_config16(addr, 0x90); - word |= 0x7fff; //15M + word |= 0x7fff; /* 15M */ pci_write_config16(addr, 0x90, word); } Modified: trunk/src/southbridge/nvidia/mcp55/chip.h ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/chip.h Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/chip.h Tue Jan 4 20:51:33 2011 (r6241) @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MCP55_CHIP_H -#define MCP55_CHIP_H +#ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H +#define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H #include @@ -36,4 +36,4 @@ struct chip_operations; extern struct chip_operations southbridge_nvidia_mcp55_ops; -#endif /* MCP55_CHIP_H */ +#endif Modified: trunk/src/southbridge/nvidia/mcp55/early_ctrl.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/early_ctrl.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/early_ctrl.c Tue Jan 4 20:51:33 2011 (r6241) @@ -26,14 +26,11 @@ { device_t dev; - /* Find the device. - */ - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT), - bus); - - return (dev>>15) & 0x1f; + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + return (dev >> 15) & 0x1f; } void soft_reset(void) @@ -55,7 +52,6 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { - /* default value for mcp55 is good */ - /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ + /* The default value for MCP55 is good. */ + /* Set VFSMAF (VID/FID System Management Action Field) to 2. */ } - Modified: trunk/src/southbridge/nvidia/mcp55/early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/early_setup_car.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/early_setup_car.c Tue Jan 4 20:51:33 2011 (r6241) @@ -19,30 +19,29 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #ifdef UNUSED_CODE -int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val); +int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); -static int set_ht_link_mcp55(uint8_t ht_c_num) +static int set_ht_link_mcp55(u8 ht_c_num) { unsigned vendorid = 0x10de; unsigned val = 0x01610109; - /* Nvidia mcp55 hardcode, hw can not set it automatically */ + /* NVIDIA MCP55 hardcode, hardware can not set it automatically. */ return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); } -static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) +static void setup_ss_table(unsigned index, unsigned where, unsigned control, + const unsigned int *register_values, int max) { int i; - unsigned val; val = inl(control); val &= 0xfffffffe; outl(val, control); - outl(0, index); //index - for(i = 0; i < max; i++) { + outl(0, index); /* Index */ + for (i = 0; i < max; i++) { unsigned long reg; reg = register_values[i]; outl(reg, where); @@ -51,7 +50,6 @@ val = inl(control); val |= 1; outl(val, control); - } #endif @@ -68,17 +66,18 @@ #define ACPICTRL_REG_POS 0x60 /* - 16 1 1 1 1 8 :0 - 16 0 4 0 0 8 :1 - 16 0 4 2 2 4 :2 - 4 4 4 4 4 8 :3 - 8 8 4 0 0 8 :4 - 8 0 4 4 4 8 :5 + * 16 1 1 1 1 8 :0 + * 16 0 4 0 0 8 :1 + * 16 0 4 2 2 4 :2 + * 4 4 4 4 4 8 :3 + * 8 8 4 0 0 8 :4 + * 8 0 4 4 4 8 :5 */ -#define MCP55_CHIP_REV 3 +#define MCP55_CHIP_REV 3 -static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base) +static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, + unsigned *devn, unsigned *io_base) { static const unsigned int ctrl_devport_conf[] = { @@ -88,16 +87,16 @@ }; int j; - for(j = 0; j < mcp55_num; j++ ) { + for (j = 0; j < mcp55_num; j++ ) { setup_resource_map_offset(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); } } -static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base) +static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, + unsigned *devn, unsigned *io_base) { - static const unsigned int ctrl_devport_conf_clear[] = { PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0, PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0, @@ -105,58 +104,56 @@ }; int j; - for(j = 0; j < mcp55_num; j++ ) { + for (j = 0; j < mcp55_num; j++ ) { setup_resource_map_offset(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); } - - } -static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) +static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, + unsigned anactrl_io_base, unsigned pci_e_x) { - uint32_t tgio_ctrl; - uint32_t pll_ctrl; - uint32_t dword; + u32 tgio_ctrl, pll_ctrl, dword; int i; device_t dev; - dev = PCI_DEV(busnx, devnx+1, 1); + + dev = PCI_DEV(busnx, devnx + 1, 1); + dword = pci_read_config32(dev, 0xe4); - dword |= 0x3f0; // disable it at first + dword |= 0x3f0; /* Disable it at first. */ pci_write_config32(dev, 0xe4, dword); - for(i=0; i<3; i++) { + for (i = 0; i < 3; i++) { tgio_ctrl = inl(anactrl_io_base + 0xcc); - tgio_ctrl &= ~(3<<9); - tgio_ctrl |= (i<<9); + tgio_ctrl &= ~(3 << 9); + tgio_ctrl |= (i << 9); outl(tgio_ctrl, anactrl_io_base + 0xcc); pll_ctrl = inl(anactrl_io_base + 0x30); - pll_ctrl |= (1<<31); + pll_ctrl |= (1 << 31); outl(pll_ctrl, anactrl_io_base + 0x30); do { pll_ctrl = inl(anactrl_io_base + 0x30); } while (!(pll_ctrl & 1)); } tgio_ctrl = inl(anactrl_io_base + 0xcc); - tgio_ctrl &= ~((7<<4)|(1<<8)); - tgio_ctrl |= (pci_e_x<<4)|(1<<8); + tgio_ctrl &= ~((7 << 4) | (1 << 8)); + tgio_ctrl |= (pci_e_x << 4) | (1 << 8); outl(tgio_ctrl, anactrl_io_base + 0xcc); - // wait 100us - udelay(100); + udelay(100); /* Wait 100us. */ dword = pci_read_config32(dev, 0xe4); - dword &= ~(0x3f0); // enable + dword &= ~(0x3f0); /* Enable. */ pci_write_config32(dev, 0xe4, dword); - // need to wait 100ms - mdelay(100); + mdelay(100); /* Need to wait 100ms. */ } -static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x) +static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, + unsigned *devn, unsigned *io_base, + unsigned *pci_e_x) { - static const unsigned int ctrl_conf_1[] = { RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000, RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000, @@ -199,11 +196,11 @@ RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ }; static const unsigned int ctrl_conf_1_1[] = { @@ -218,7 +215,6 @@ RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000, }; - static const unsigned int ctrl_conf_mcp55_only[] = { RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000, @@ -251,33 +247,30 @@ #if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, -// RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14, + // RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1 << 14), (1 << 14), #endif -// play a while with GPIO in MCP55 + #ifdef MCP55_MB_SETUP + /* Play a while with GPIO in MCP55. */ MCP55_MB_SETUP #endif #if CONFIG_MCP55_USE_AZA - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2), #endif - - }; static const unsigned int ctrl_conf_master_only[] = { - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000, - //Master MCP55 ????YHLU - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), - + /* Master MCP55???? YHLU */ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3 << 2), (0 << 2), }; static const unsigned int ctrl_conf_2[] = { - /* I didn't put pcie related stuff here */ + /* I didn't put PCI-E related stuff here. */ RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0, RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000, @@ -286,117 +279,129 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012, - #if CONFIG_MCP55_USE_NIC - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20), + RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), #endif - }; - int j, i; - for(j=0; j1) ) { - setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only), + if ((busn[j] == 0) && (mcp55_num>1)) { + setup_resource_map_x_offset(ctrl_conf_master_only, + ARRAY_SIZE(ctrl_conf_master_only), PCI_DEV(busn[j], devn[j], 0), io_base[j]); } - setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2), + setup_resource_map_x_offset(ctrl_conf_2, + ARRAY_SIZE(ctrl_conf_2), PCI_DEV(busn[j], devn[j], 0), io_base[j]); - } #if 0 - for(j=0; j< mcp55_num; j++) { + for (j = 0; j < mcp55_num; j++) { // PCI-E (XSPLL) SS table 0x40, x044, 0x48 // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44, - io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4, - io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4, - io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, + io_base[j] + ANACTRL_IO_BASE + 0x44, + io_base[j] + ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, + io_base[j] + ANACTRL_IO_BASE + 0xb4, + io_base[j] + ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, + io_base[j] + ANACTRL_IO_BASE + 0xc4, + io_base[j] + ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); } #endif - } #ifndef HT_CHAIN_NUM_MAX #define HT_CHAIN_NUM_MAX 4 -#define HT_CHAIN_BUSN_D 0x40 +#define HT_CHAIN_BUSN_D 0x40 #define HT_CHAIN_IOBASE_D 0x4000 #endif static int mcp55_early_setup_x(void) { - /*find out how many mcp55 we have */ + /* Find out how many MCP55 we have. */ unsigned busn[HT_CHAIN_NUM_MAX] = {0}; unsigned devn[HT_CHAIN_NUM_MAX] = {0}; unsigned io_base[HT_CHAIN_NUM_MAX] = {0}; + /* - FIXME: May have problem if there is different MCP55 HTX card with different PCI_E lane allocation - Need to use same trick about pci1234 to verify node/link connection - */ - unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1, CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3 }; - int mcp55_num = 0; - unsigned busnx; - unsigned devnx; - int ht_c_index; + * FIXME: May have problem if there is different MCP55 HTX card with + * different PCI_E lane allocation. Need to use same trick about + * pci1234 to verify node/link connection. + */ + unsigned pci_e_x[HT_CHAIN_NUM_MAX] = { + CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1, + CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3, + }; + int mcp55_num = 0, ht_c_index; + unsigned busnx, devnx; - /* FIXME: multi pci segment handling */ + /* FIXME: Multi PCI segment handling. */ /* Any system that only have IO55 without MCP55? */ - for(ht_c_index = 0; ht_c_index #include "mcp55.h" -static struct device_operations ht_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &mcp55_pci_ops, +static struct device_operations ht_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &mcp55_pci_ops, }; static const struct pci_driver ht_driver __pci_driver = { @@ -42,4 +42,3 @@ .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_HT, }; - Modified: trunk/src/southbridge/nvidia/mcp55/ide.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/ide.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/ide.c Tue Jan 4 20:51:33 2011 (r6241) @@ -31,33 +31,31 @@ static void ide_init(struct device *dev) { struct southbridge_nvidia_mcp55_config *conf; - /* Enable ide devices so the linux ide driver will work */ - uint32_t dword; - uint16_t word; - uint8_t byte; + u32 dword; + u16 word; + u8 byte; conf = dev->chip_info; word = pci_read_config16(dev, 0x50); - /* Ensure prefetch is disabled */ + /* Ensure prefetch is disabled. */ word &= ~((1 << 15) | (1 << 13)); if (conf->ide1_enable) { - /* Enable secondary ide interface */ - word |= (1<<0); + /* Enable secondary IDE interface. */ + word |= (1 << 0); printk(BIOS_DEBUG, "IDE1 \t"); } if (conf->ide0_enable) { - /* Enable primary ide interface */ - word |= (1<<1); + /* Enable primary IDE interface. */ + word |= (1 << 1); printk(BIOS_DEBUG, "IDE0\n"); } - word |= (1<<12); - word |= (1<<14); + word |= (1 << 12); + word |= (1 << 14); pci_write_config16(dev, 0x50, word); - - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; /* Latency: 64-->32 */ pci_write_config8(dev, 0xd, byte); dword = pci_read_config32(dev, 0xf8); @@ -66,17 +64,16 @@ #if CONFIG_PCI_ROM_RUN == 1 pci_dev_init(dev); #endif - } -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, -// .enable = mcp55_enable, - .ops_pci = &mcp55_pci_ops, +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .scan_bus = 0, +// .enable = mcp55_enable, + .ops_pci = &mcp55_pci_ops, }; static const struct pci_driver ide_driver __pci_driver = { @@ -84,4 +81,3 @@ .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE, }; - Modified: trunk/src/southbridge/nvidia/mcp55/lpc.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/lpc.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/lpc.c Tue Jan 4 20:51:33 2011 (r6241) @@ -54,14 +54,14 @@ static void lpc_common_init(device_t dev, int master) { - uint8_t byte; - uint32_t ioapic_base; + u8 byte; + u32 ioapic_base; - /* IO APIC initialization */ + /* IOAPIC initialization. */ byte = pci_read_config8(dev, 0x74); - byte |= (1<<0); // enable APIC + byte |= (1 << 0); /* Enable IOAPIC. */ pci_write_config8(dev, 0x74, byte); - ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 + ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */ if (master) setup_ioapic(ioapic_base, 0); @@ -78,24 +78,22 @@ { unsigned long hpet_address; - pci_write_config32(dev,0x44, 0xfed00001); - hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; + pci_write_config32(dev, 0x44, 0xfed00001); + hpet_address=pci_read_config32(dev, 0x44) & 0xfffffffe; printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } static void lpc_init(device_t dev) { - uint8_t byte; - uint8_t byte_old; - int on; - int nmi_option; + u8 byte, byte_old; + int on, nmi_option; lpc_common_init(dev, 1); #if 0 - /* posted memory write enable */ + /* Posted memory write enable. */ byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1<<0)); + pci_write_config8(dev, 0x46, byte | (1 << 0)); #endif /* power after power fail */ @@ -104,63 +102,58 @@ get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; - if (!on) { + if (!on) byte |= 0x40; - } pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); + printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); #endif - /* Throttle the CPU speed down for testing */ + /* Throttle the CPU speed down for testing. */ on = SLOW_CPU_OFF; get_option(&on, "slow_cpu"); - if(on) { - uint16_t pm10_bar; - uint32_t dword; - pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); - outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); + if (on) { + u16 pm10_bar; + u32 dword; + pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); + outl(((on << 1) + 0x10), (pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); - on = 8-on; + on = 8 - on; printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on*12)+(on>>1),(on&1)*5); + (on * 12) + (on >> 1), (on & 1) * 5); } #if 0 -// default is enabled - /* Enable Port 92 fast reset */ + /* Enable Port 92 fast reset (default is enabled). */ byte = pci_read_config8(dev, 0xe8); byte |= ~(1 << 3); pci_write_config8(dev, 0xe8, byte); #endif - /* Enable Error reporting */ - /* Set up sync flood detected */ + /* Enable error reporting. */ + /* Set up sync flood detected. */ byte = pci_read_config8(dev, 0x47); byte |= (1 << 1); pci_write_config8(dev, 0x47, byte); - /* Set up NMI on errors */ - byte = inb(0x70); // RTC70 + /* Set up NMI on errors. */ + byte = inb(0x70); /* RTC70 */ byte_old = byte; nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - } else { - byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW - } - if( byte != byte_old) { + if (nmi_option) + byte &= ~(1 << 7); /* Set NMI. */ + else + byte |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ + if (byte != byte_old) outb(byte, 0x70); - } - /* Initialize the real time clock */ + /* Initialize the real time clock. */ rtc_init(0); - /* Initialize isa dma */ + /* Initialize ISA DMA. */ isa_dma_init(); - /* Initialize the High Precision Event Timers */ + /* Initialize the High Precision Event Timers (HPET). */ enable_hpet(dev); - } static void mcp55_lpc_read_resources(device_t dev) @@ -191,16 +184,14 @@ } /** - * @brief Enable resources for children devices - * - * @param dev the device whos children's resources are to be enabled + * Enable resources for children devices. * + * @param dev The device whose children's resources are to be enabled. */ static void mcp55_lpc_enable_childrens_resources(device_t dev) { - uint32_t reg, reg_var[4]; - int i; - int var_num = 0; + u32 reg, reg_var[4]; + int i, var_num = 0; struct bus *link; reg = pci_read_config32(dev, 0xa0); @@ -208,43 +199,50 @@ for (link = dev->link_list; link; link = link->next) { device_t child; for (child = link->children; child; child = child->sibling) { - if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { + if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; - for(res = child->resource_list; res; res = res->next) { - unsigned long base, end; // don't need long long - if(!(res->flags & IORESOURCE_IO)) continue; + for (res = child->resource_list; res; res = res->next) { + unsigned long base, end; /* Don't need long long. */ + if (!(res->flags & IORESOURCE_IO)) + continue; base = res->base; end = resource_end(res); printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { - case 0x3f8: // COM1 - reg |= (1<<0); break; - case 0x2f8: // COM2 - reg |= (1<<1); break; - case 0x378: // Parallal 1 - reg |= (1<<24); break; - case 0x3f0: // FD0 - reg |= (1<<20); break; - case 0x220: // Aduio 0 - reg |= (1<<8); break; - case 0x300: // Midi 0 - reg |= (1<<12); break; + case 0x3f8: /* COM1 */ + reg |= (1 << 0); + break; + case 0x2f8: /* COM2 */ + reg |= (1 << 1); + break; + case 0x378: /* Parallel 1 */ + reg |= (1 << 24); + break; + case 0x3f0: /* FD0 */ + reg |= (1 << 20); + break; + case 0x220: /* Audio 0 */ + reg |= (1 << 8); + break; + case 0x300: /* Midi 0 */ + reg |= (1 << 12); + break; } - if( (base == 0x290) || (base >= 0x400)) { - if(var_num>=4) continue; // only 4 var ; compact them ? - reg |= (1<<(28+var_num)); - reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16); + if ((base == 0x290) + || (base >= 0x400)) { + /* Only 4 var; compact them? */ + if (var_num >= 4) + continue; + reg |= (1 << (28 + var_num)); + reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16); } } } } } pci_write_config32(dev, 0xa0, reg); - for(i=0;i - #include - #include #include #include #include #include "mcp55.h" -static uint32_t final_reg; +static u32 final_reg; -static device_t find_lpc_dev( device_t dev, unsigned devfn) +static device_t find_lpc_dev(device_t dev, unsigned devfn) { - device_t lpc_dev; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); - if ( !lpc_dev ) return lpc_dev; + if (!lpc_dev) + return lpc_dev; if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || ( (lpc_dev->device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) || - (lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO) - ) ) { - uint32_t id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) || - (id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16))) - ) { - lpc_dev = 0; - } + (lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO))) + { + u32 id; + id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); + if ((id < (PCI_VENDOR_ID_NVIDIA + | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) || + (id > (PCI_VENDOR_ID_NVIDIA + | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))) + { + lpc_dev = 0; + } } return lpc_dev; @@ -60,24 +60,18 @@ void mcp55_enable(device_t dev) { - device_t lpc_dev = 0; - device_t sm_dev = 0; - unsigned index = 0; - unsigned index2 = 0; - uint32_t reg_old, reg; - uint8_t byte; - unsigned deviceid; - unsigned vendorid; - + device_t lpc_dev = 0, sm_dev = 0; + unsigned index = 0, index2 = 0; + u32 reg_old, reg; + u8 byte; + unsigned deviceid, vendorid, devfn; struct southbridge_nvidia_mcp55_config *conf; conf = dev->chip_info; int i; - unsigned devfn; - - if(dev->device==0x0000) { + if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); - deviceid = (vendorid>>16) & 0xffff; + deviceid = (vendorid >> 16) & 0xffff; // vendorid &= 0xffff; } else { // vendorid = dev->vendor; @@ -85,138 +79,135 @@ } devfn = (dev->path.pci.devfn) & ~7; - switch(deviceid) { - case PCI_DEVICE_ID_NVIDIA_MCP55_HT: - return; - - case PCI_DEVICE_ID_NVIDIA_MCP55_SM2://? - index = 16; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_USB: - devfn -= (1<<3); - index = 8; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_USB2: - devfn -= (1<<3); - index = 20; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: //two - case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE://two - devfn -= (7<<3); - index = 10; - for(i=0;i<2;i++) { - lpc_dev = find_lpc_dev(dev, devfn - (i<<3)); - if(!lpc_dev) continue; - index -= i; - devfn -= (i<<3); - break; - } - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_AZA: - devfn -= (5<<3); - index = 11; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_IDE: - devfn -= (3<<3); - index = 14; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: //three - case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three - devfn -= (4<<3); - index = 22; - i = (dev->path.pci.devfn) & 7; - if(i>0) { - index -= (i+3); - } - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCI: - devfn -= (5<<3); - index = 15; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A: - devfn -= (0x9<<3); // to LPC - index2 = 9; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: //two - devfn -= (0xa<<3); // to LPC - index2 = 8; - for(i=0;i<2;i++) { - lpc_dev = find_lpc_dev(dev, devfn - (i<<3)); - if(!lpc_dev) continue; - index2 -= i; - devfn -= (i<<3); - break; - } - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D: - devfn -= (0xc<<3); // to LPC - index2 = 6; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E: - devfn -= (0xd<<3); // to LPC - index2 = 5; + switch (deviceid) { + case PCI_DEVICE_ID_NVIDIA_MCP55_HT: + return; + case PCI_DEVICE_ID_NVIDIA_MCP55_SM2: //? + index = 16; + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_USB: + devfn -= (1 << 3); + index = 8; + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_USB2: + devfn -= (1 << 3); + index = 20; + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: // two + case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE: // two + devfn -= (7 << 3); + index = 10; + for (i = 0; i < 2; i++) { + lpc_dev = find_lpc_dev(dev, devfn - (i << 3)); + if (!lpc_dev) + continue; + index -= i; + devfn -= (i << 3); break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F: - devfn -= (0xe<<3); // to LPC - index2 = 4; + } + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_AZA: + devfn -= (5 << 3); + index = 11; + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_IDE: + devfn -= (3 << 3); + index = 14; + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: // three + case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: // three + devfn -= (4 << 3); + index = 22; + i = (dev->path.pci.devfn) & 7; + if (i > 0) + index -= (i + 3); + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_PCI: + devfn -= (5 << 3); + index = 15; + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A: + devfn -= (0x9 << 3); // to LPC + index2 = 9; + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: // two + devfn -= (0xa << 3); // to LPC + index2 = 8; + for (i = 0; i < 2; i++) { + lpc_dev = find_lpc_dev(dev, devfn - (i << 3)); + if (!lpc_dev) + continue; + index2 -= i; + devfn -= (i << 3); break; - default: - index = 0; + } + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D: + devfn -= (0xc << 3); // to LPC + index2 = 6; + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E: + devfn -= (0xd << 3); // to LPC + index2 = 5; + break; + case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F: + devfn -= (0xe << 3); // to LPC + index2 = 4; + break; + default: + index = 0; } - if(!lpc_dev) + if (!lpc_dev) lpc_dev = find_lpc_dev(dev, devfn); - if ( !lpc_dev ) return; + if (!lpc_dev) + return; - if(index2!=0) { + if (index2 != 0) { sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); - if(!sm_dev) return; - - if ( sm_dev ) { - reg_old = reg = pci_read_config32(sm_dev, 0xe4); - - if (!dev->enabled) { //disable it - reg |= (1<enabled) + reg |= (1<bus->secondary, devfn + 1); - if(!sm_dev) return; + if (!sm_dev) + return; final_reg = pci_read_config32(sm_dev, 0xe8); - final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9)); - pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first + final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 14) + | (1 << 22) | (1 << 18) | (1 << 17) | (1 << 15) + | (1 << 11) | (1 << 10) | (1 << 9)); + pci_write_config32(sm_dev, 0xe8, final_reg); /* Enable all at first. */ + #if 0 reg_old = reg = pci_read_config32(sm_dev, 0xe4); -// reg |= (1<<0); - reg &= ~(0x3f<<4); +// reg |= (1 << 0); + reg &= ~(0x3f << 4); if (reg != reg_old) { printk(BIOS_DEBUG, "mcp55.c pcie enabled\n"); pci_write_config32(sm_dev, 0xe4, reg); @@ -225,21 +216,22 @@ } if (!dev->enabled) { - final_reg |= (1 << index);// disable it - //The reason for using final_reg, if diable func 1, the func 2 will be func 1 so We need disable them one time. + final_reg |= (1 << index); /* Disable it. */ + /* + * The reason for using final_reg, if diable func 1, + * the func 2 will be func 1, so we need disable them one time. + */ } - if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8 + /* NIC1 is the final, we need update final reg to 0xe8. */ + if (index == 9) { sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); - if(!sm_dev) return; + if (!sm_dev) + return; reg_old = pci_read_config32(sm_dev, 0xe8); - if (final_reg != reg_old) { + if (final_reg != reg_old) pci_write_config32(sm_dev, 0xe8, final_reg); - } - } - - } static void mcp55_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -250,9 +242,9 @@ struct pci_operations mcp55_pci_ops = { .set_subsystem = mcp55_set_subsystem, -}; +}; struct chip_operations southbridge_nvidia_mcp55_ops = { CHIP_NAME("NVIDIA MCP55 Southbridge") - .enable_dev = mcp55_enable, + .enable_dev = mcp55_enable, }; Modified: trunk/src/southbridge/nvidia/mcp55/mcp55.h ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55.h Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/mcp55.h Tue Jan 4 20:51:33 2011 (r6241) @@ -19,13 +19,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MCP55_H -#define MCP55_H +#ifndef SOUTHBRIDGE_NVIDIA_MCP55_MCP55_H +#define SOUTHBRIDGE_NVIDIA_MCP55_MCP55_H #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else - #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif #ifndef __PRE_RAM__ @@ -39,4 +39,4 @@ #endif #endif -#endif /* MCP55_H */ +#endif Modified: trunk/src/southbridge/nvidia/mcp55/nic.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/nic.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/nic.c Tue Jan 4 20:51:33 2011 (r6241) @@ -35,91 +35,97 @@ { u32 dword; unsigned loop = 0x100; - write32(base+0x190, 0x8000); //Clear MDIO lock bit - mdelay(1); - dword = read32(base+0x190); - if(dword & (1<<15)) return -1; - write32(base+0x180, 1); - write32(base + 0x190, (phy_addr<<5) | (phy_reg)); - do{ + write32(base + 0x190, 0x8000); /* Clear MDIO lock bit. */ + mdelay(1); + dword = read32(base + 0x190); + if (dword & (1 << 15)) + return -1; + + write32(base + 0x180, 1); + write32(base + 0x190, (phy_addr << 5) | (phy_reg)); + do { dword = read32(base + 0x190); - if(--loop==0) return -4; - } while ((dword & (1<<15)) ); + if (--loop==0) + return -4; + } while ((dword & (1 << 15))); dword = read32(base + 0x180); - if(dword & 1) return -3; + if (dword & 1) + return -3; dword = read32(base + 0x194); return dword; - } static void phy_detect(u32 base) { u32 dword; - int i; - int val; + int i, val; unsigned id; - dword = read32(base+0x188); - dword &= ~(1<<20); - write32(base+0x188, dword); + + dword = read32(base + 0x188); + dword &= ~(1 << 20); + write32(base + 0x188, dword); phy_read(base, 0, 1); - for(i=1; i<=32; i++) { + for (i = 1; i <= 32; i++) { int phyaddr = i & 0x1f; val = phy_read(base, phyaddr, 1); - if(val<0) continue; - if((val & 0xffff) == 0xfffff) continue; - if((val & 0xffff) == 0) continue; - if(!(val & 1)) { - break; // Ethernet PHY - } + if (val < 0) + continue; + if ((val & 0xffff) == 0xfffff) + continue; + if ((val & 0xffff) == 0) + continue; + if (!(val & 1)) + break; /* Ethernet PHY */ + val = phy_read(base, phyaddr, 3); - if (val < 0 || val == 0xffff) continue; + if (val < 0 || val == 0xffff) + continue; id = val & 0xfc00; val = phy_read(base, phyaddr, 2); - if (val < 0 || val == 0xffff) continue; - id |= ((val & 0xffff)<<16); - printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i); -// if((id == 0xe0180000) || (id==0x0032cc00)) + if (val < 0 || val == 0xffff) + continue; + id |= ((val & 0xffff) << 16); + printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", + id, i); +// if ((id == 0xe0180000) || (id == 0x0032cc00)) break; } - if(i>32) { + if (i > 32) printk(BIOS_DEBUG, "MCP55 MAC PHY not found\n"); - } } static void nic_init(struct device *dev) { - u32 mac_h, mac_l; + u32 mac_h, mac_l, base; int eeprom_valid = 0; struct southbridge_nvidia_mcp55_config *conf; - static u32 nic_index = 0; - - u32 base; struct resource *res; res = find_resource(dev, 0x10); - if(!res) return; + if (!res) + return; base = res->base; phy_detect(base); #define NvRegPhyInterface 0xC0 -#define PHY_RGMII 0x10000000 +#define PHY_RGMII 0x10000000 write32(base + NvRegPhyInterface, PHY_RGMII); conf = dev->chip_info; - if(conf->mac_eeprom_smbus != 0) { + if (conf->mac_eeprom_smbus != 0) { // read MAC address from EEPROM at first struct device *dev_eeprom; dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); Modified: trunk/src/southbridge/nvidia/mcp55/pci.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/pci.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/pci.c Tue Jan 4 20:51:33 2011 (r6241) @@ -31,9 +31,8 @@ static void pci_init(struct device *dev) { - - uint32_t dword; - uint16_t word; + u32 dword; + u16 word; device_t pci_domain_dev; struct resource *mem, *pref; Modified: trunk/src/southbridge/nvidia/mcp55/pcie.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/pcie.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/pcie.c Tue Jan 4 20:51:33 2011 (r6241) @@ -30,9 +30,8 @@ static void pcie_init(struct device *dev) { - /* Enable pci error detecting */ - uint32_t dword; + u32 dword; /* System error enable */ dword = pci_read_config32(dev, 0x04); Modified: trunk/src/southbridge/nvidia/mcp55/sata.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/sata.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/sata.c Tue Jan 4 20:51:33 2011 (r6241) @@ -31,7 +31,7 @@ static void sata_init(struct device *dev) { - uint32_t dword; + u32 dword; struct southbridge_nvidia_mcp55_config *conf; conf = dev->chip_info; Modified: trunk/src/southbridge/nvidia/mcp55/smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/smbus.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/smbus.c Tue Jan 4 20:51:33 2011 (r6241) @@ -46,7 +46,7 @@ return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(device_t dev, u8 val) { unsigned device; struct resource *res; @@ -60,7 +60,7 @@ return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(device_t dev, u8 address) { unsigned device; struct resource *res; @@ -74,7 +74,7 @@ return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(device_t dev, u8 address, u8 val) { unsigned device; struct resource *res; Modified: trunk/src/southbridge/nvidia/mcp55/usb2.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/usb2.c Tue Jan 4 18:36:55 2011 (r6240) +++ trunk/src/southbridge/nvidia/mcp55/usb2.c Tue Jan 4 20:51:33 2011 (r6241) @@ -33,7 +33,7 @@ static void usb2_init(struct device *dev) { - uint32_t dword; + u32 dword; dword = pci_read_config32(dev, 0xf8); dword |= 40; pci_write_config32(dev, 0xf8, dword); From bwhite82 at gmail.com Mon Jan 3 22:25:22 2011 From: bwhite82 at gmail.com (Brandon White) Date: Mon, 3 Jan 2011 16:25:22 -0500 Subject: [coreboot] Support for Google CR-48/Atom N455 In-Reply-To: <22797.86.122.13.126.1294074448.squirrel@intranet.utcluj.ro> References: <22797.86.122.13.126.1294074448.squirrel@intranet.utcluj.ro> Message-ID: Thanks Crisit for getting back to me. I have indeed flashed it with flashrom in Ubuntu. I will see what I can do about details of the northbridge. On Mon, Jan 3, 2011 at 12:07 PM, Cristi Magherusan < cristi.magherusan at net.utcluj.ro> wrote: > ?n Dum, Ianuarie 2, 2011 4:31, Brandon White a scris: > > Hello all. Someone was accidentally sent a CR-48 that had Windows 7 > > pre-installed and an actual BIOS instead of Google's EFI. Anways, he > > uploaded the BIOS, I was able to flash it and after that I installed > > Ubuntu > > as a dual boot with Chrome OS. I was wondering if Coreboot was possible > on > > this machine? I have attached everything asked for in the wiki. > > > > Thanks, > > Brandon > > -- > > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > Hello, > > Flashrom seems to support your flash, but writes weren't tested/confirmed > to work yet on the flashrom wiki. Did you flash it using Frashrom? > > The ICH7 southbridge is supported, no idea about the northbridge, you > might need doc from Intel, which is hard to get unless you have an NDA. > > If you are lucky, the SMSC SCH5317 SuperIO might be easy to support, by > porting the code for SCH5307 which is already supported. > > I have no clue about the other superIO chip or what could it be used for. > maybe we don't need it at all for system init. > > Also, thew board might have an Embedded Controller, which might make > things even harder. > > Good luck! > Cristi > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From darmawan.salihun at gmail.com Tue Jan 4 21:41:17 2011 From: darmawan.salihun at gmail.com (Darmawan Salihun) Date: Wed, 5 Jan 2011 03:41:17 +0700 Subject: [coreboot] IDE interface support code for AMDLX800-CS5536 In-Reply-To: References: Message-ID: Hi Mark, On 1/5/11, Marc Jones wrote: > On Sat, Jan 1, 2011 at 1:38 PM, Darmawan Salihun > wrote: >>> On 1/2/11, Darmawan Salihun wrote: >>> Hi guys, >>> >>> I'm looking for the support code for the IDE controller in CS5536 >>> southbridge. >>> I checked-out Coreboot source code but only saw Flash interface >>> support in there. >>> I saw the IDE controller is switched to Flash interface support with >>> the "DEADBEEF" >>> magic number. >>> >>> The board I'm working with right now use the primary IDE channel for both >>> HDD connectors and a CF connectors. I need to know how to initialize >>> the chipset >>> correctly for this setup. The CF connector is the primary master and >>> the HDD connector is primary slave. >>> >>> I've checked with lspci and " cat /proc/ioports" and I found that the >>> legacy I/O ports >>> for IDE controller is working just fine. Also, the I/O ports for >>> IDE bus mastering (SFF-8038i) registers are allocated correctly. >>> >> >> I mean with the current code that I tested the I/O ports allocation is >> just fine. >> >>> Thanks, >>> >>> Darmawan > > Hi Darmawan, > > The IDE should get setup by default if the flash switch path is not > selected. > > I assume you have already read the registers in the databook.. > http://support.amd.com/us/Embedded_TechDocs/33238G_cs5536_db.pdf Yes, I've been reading it several times over ;-). I have pin point the problem to be in setting the appropriate "ATA mode" for the attached drives. The motherboard I'm working with has a CF interface in the primary master. While the primary slave is a 44-pin IDE connector (currently connected to an 80GB HDD). I booted FreeBSD 8.0 installation disk in full debug (via USB DVD), but it failed when it tried to set the drive controller mode via "SET FEATURE" (ATA command). This renders the CF _and_ the HDD unusable. I also booted to backtrack 3 i386 Linux, but it also failed even earlier (via USB DVD), when it tried to check for drive presence via "IDENTIFY" (ATA command). I'm confused as to: What are the "acceptable" values for the IDE_DTC, IDE_CAST and IDE_ETC registers? I mean values which would enable the OS to use mass storage device(s) on the IDE primary channel. > > There may be more information on the embedded developer site. The > embedded guys are coreboot friendly, so they should be able to point > at the appropriate doc. > > http://wwwd.amd.com/amd/devsite.nsf/home/welcome.htm?opendocument&login > I see. On to the site. Thanks, Darmawan -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =- From stepan at coreboot.org Tue Jan 4 22:07:52 2011 From: stepan at coreboot.org (Stefan Reinauer) Date: Tue, 4 Jan 2011 22:07:52 +0100 Subject: [coreboot] sb800 code derived from sb700 implementation In-Reply-To: <20110104112126.17789.qmail@stuge.se> References: <20110104112126.17789.qmail@stuge.se> Message-ID: <20110104210751.GA16813@coreboot.org> * Peter Stuge [110104 12:21]: > She, Kerry wrote: > Thanks! I think this is a nice addition. Maybe we should add a > Kconfig option to choose between cimx and non-cimx? I think we should, once we actually hit a use case. From peter at stuge.se Tue Jan 4 22:18:42 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 4 Jan 2011 22:18:42 +0100 Subject: [coreboot] sb800 code derived from sb700 implementation In-Reply-To: <20110104210751.GA16813@coreboot.org> References: <20110104112126.17789.qmail@stuge.se> <20110104210751.GA16813@coreboot.org> Message-ID: <20110104211842.17335.qmail@stuge.se> Stefan Reinauer wrote: > > Maybe we should add a Kconfig option to choose between cimx and > > non-cimx? > > I think we should, once we actually hit a use case. Um? This is the case right here. I say add it now and get the patch commited, then can remove in future if not used. //Peter From stepan at coreboot.org Tue Jan 4 22:21:37 2011 From: stepan at coreboot.org (Stefan Reinauer) Date: Tue, 4 Jan 2011 22:21:37 +0100 Subject: [coreboot] sb800 code derived from sb700 implementation In-Reply-To: <20110104211842.17335.qmail@stuge.se> References: <20110104112126.17789.qmail@stuge.se> <20110104210751.GA16813@coreboot.org> <20110104211842.17335.qmail@stuge.se> Message-ID: <20110104212137.GA23863@coreboot.org> * Peter Stuge [110104 22:18]: > Stefan Reinauer wrote: > > > Maybe we should add a Kconfig option to choose between cimx and > > > non-cimx? > > > > I think we should, once we actually hit a use case. > > Um? This is the case right here. Oh? Which board? I thought the patch said "for reference only, not for checkin". Sorry if I missed something. Stefan From c-d.hailfinger.devel.2006 at gmx.net Wed Jan 5 00:05:02 2011 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 05 Jan 2011 00:05:02 +0100 Subject: [coreboot] sb800 code derived from sb700 implementation In-Reply-To: <20110104212137.GA23863@coreboot.org> References: <20110104112126.17789.qmail@stuge.se> <20110104210751.GA16813@coreboot.org> <20110104211842.17335.qmail@stuge.se> <20110104212137.GA23863@coreboot.org> Message-ID: <4D23A79E.1020102@gmx.net> Auf 04.01.2011 22:21, Stefan Reinauer schrieb: > * Peter Stuge [110104 22:18]: > >> Stefan Reinauer wrote: >> >>>> Maybe we should add a Kconfig option to choose between cimx and >>>> non-cimx? >>>> >>> I think we should, once we actually hit a use case. >>> >> Um? This is the case right here. >> > Oh? Which board? I thought the patch said "for reference only, not for > checkin". Sorry if I missed something. > Still, having the code checked in is IMHO better than having it on the list. If there are any CIMx integration issues later, we still have the alternative code (and as a nice benefit, we can actually touch that code whereas CIMx should be kept unchanged to allow easier updates). Regards, Carl-Daniel From stepan at coreboot.org Wed Jan 5 01:11:23 2011 From: stepan at coreboot.org (Stefan Reinauer) Date: Wed, 5 Jan 2011 01:11:23 +0100 Subject: [coreboot] sb800 code derived from sb700 implementation In-Reply-To: <4D23A79E.1020102@gmx.net> References: <20110104112126.17789.qmail@stuge.se> <20110104210751.GA16813@coreboot.org> <20110104211842.17335.qmail@stuge.se> <20110104212137.GA23863@coreboot.org> <4D23A79E.1020102@gmx.net> Message-ID: <20110105001123.GA8717@coreboot.org> * Carl-Daniel Hailfinger [110105 00:05]: > Still, having the code checked in is IMHO better than having it on the > list. If there are any CIMx integration issues later, we still have the > alternative code (and as a nice benefit, we can actually touch that code > whereas CIMx should be kept unchanged to allow easier updates). I would prefer to see CIMx integration issues fixed rather than worked around with an in-tree fork for a non-existant user base that might experience problems in the unforseeable future. There is nothing that prevents us from reporting issues with the CIMx code back to AMD to have it fixed. Stefan From svn at coreboot.org Wed Jan 5 02:37:48 2011 From: svn at coreboot.org (repository service) Date: Wed, 05 Jan 2011 02:37:48 +0100 Subject: [coreboot] [commit] r6242 - trunk Message-ID: Author: stepan Date: Wed Jan 5 02:37:48 2011 New Revision: 6242 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6242 Log: fix "make clean" Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Jan 4 20:51:33 2011 (r6241) +++ trunk/Makefile Wed Jan 5 02:37:48 2011 (r6242) @@ -364,7 +364,7 @@ rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm rmdir -p $(alldirs) 2>/dev/null >/dev/null || true - $(MAKE) -C payloads/external/SeaBIOS clean + $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean clean: clean-for-update rm -f $(obj)/coreboot* .ccwrap From svn at coreboot.org Wed Jan 5 03:10:51 2011 From: svn at coreboot.org (repository service) Date: Wed, 05 Jan 2011 03:10:51 +0100 Subject: [coreboot] [commit] r6243 - trunk/util/kconfig Message-ID: Author: stepan Date: Wed Jan 5 03:10:50 2011 New Revision: 6243 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6243 Log: fix compilation of mconf on some systems. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/util/kconfig/Makefile Modified: trunk/util/kconfig/Makefile ============================================================================== --- trunk/util/kconfig/Makefile Wed Jan 5 02:37:48 2011 (r6242) +++ trunk/util/kconfig/Makefile Wed Jan 5 03:10:50 2011 (r6243) @@ -304,7 +304,7 @@ $(objk)/gconf: $(patsubst %,$(objk)/%,$(gconf-objs)) $(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^ $(objk)/mconf: $(patsubst %,$(objk)/%,$(mconf-objs)) - $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^ + $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ $(HOST_LOADLIBES) -o $@ $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs)) $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ From svn at coreboot.org Wed Jan 5 03:27:54 2011 From: svn at coreboot.org (repository service) Date: Wed, 05 Jan 2011 03:27:54 +0100 Subject: [coreboot] [commit] r6244 - in trunk/src: . arch/x86 console Message-ID: Author: stepan Date: Wed Jan 5 03:27:53 2011 New Revision: 6244 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6244 Log: move single options out of main menu and remove stray "options" Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/Kconfig.deprecated_options trunk/src/arch/x86/Kconfig trunk/src/console/Kconfig Modified: trunk/src/Kconfig.deprecated_options ============================================================================== --- trunk/src/Kconfig.deprecated_options Wed Jan 5 03:10:50 2011 (r6243) +++ trunk/src/Kconfig.deprecated_options Wed Jan 5 03:27:53 2011 (r6244) @@ -2,6 +2,8 @@ # if possible, and if you find the time, or touch the general area # for other purposes, please consider removing their uses. +menu "Deprecated" + # It might be possible to consolidate hard_reset() to southbridges, # given that it (usually) uses its registers. # The long term goal would be to eliminate hard_reset() from boards. @@ -49,3 +51,4 @@ this option, then you can say N here to speed up boot time. Otherwise say Y. +endmenu Modified: trunk/src/arch/x86/Kconfig ============================================================================== --- trunk/src/arch/x86/Kconfig Wed Jan 5 03:10:50 2011 (r6243) +++ trunk/src/arch/x86/Kconfig Wed Jan 5 03:27:53 2011 (r6244) @@ -1,3 +1,5 @@ +menu "Architecture (x86)" + # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. @@ -91,3 +93,5 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string + +endmenu Modified: trunk/src/console/Kconfig ============================================================================== --- trunk/src/console/Kconfig Wed Jan 5 03:10:50 2011 (r6243) +++ trunk/src/console/Kconfig Wed Jan 5 03:27:53 2011 (r6244) @@ -1,4 +1,4 @@ -menu "Console options" +menu "Console" # TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete. config CONSOLE_SERIAL8250 bool "Serial port console output" From svn at coreboot.org Wed Jan 5 03:40:53 2011 From: svn at coreboot.org (repository service) Date: Wed, 05 Jan 2011 03:40:53 +0100 Subject: [coreboot] [commit] r6245 - trunk/src/lib Message-ID: Author: stepan Date: Wed Jan 5 03:40:53 2011 New Revision: 6245 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6245 Log: uart_init is only used in romstage. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/lib/uart8250.c Modified: trunk/src/lib/uart8250.c ============================================================================== --- trunk/src/lib/uart8250.c Wed Jan 5 03:27:53 2011 (r6244) +++ trunk/src/lib/uart8250.c Wed Jan 5 03:40:53 2011 (r6245) @@ -103,6 +103,7 @@ } #endif +#ifdef __PRE_RAM__ void uart_init(void) { #if CONFIG_USE_OPTION_TABLE @@ -117,4 +118,4 @@ uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV); #endif } - +#endif From hagigatali at gmail.com Wed Jan 5 04:43:57 2011 From: hagigatali at gmail.com (ali hagigat) Date: Wed, 5 Jan 2011 07:13:57 +0330 Subject: [coreboot] one super i/o Message-ID: I am looking for the data sheet and programming reference manual of a super I/O chip by ITE, IT8703F. I will be much appreciated if anybody can email it for me. From corey.osgood at gmail.com Wed Jan 5 05:10:42 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Tue, 4 Jan 2011 23:10:42 -0500 Subject: [coreboot] one super i/o In-Reply-To: References: Message-ID: On Tue, Jan 4, 2011 at 10:43 PM, ali hagigat wrote: > I am looking for the data sheet and programming reference manual of a > super I/O chip by ITE, IT8703F. > I will be much appreciated if anybody can email it for me. Looks like google can't find it, you're going to have to contact ITE http://www.ite.com.tw/EN/company.aspx From Zheng.Bao at amd.com Wed Jan 5 05:13:58 2011 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Wed, 5 Jan 2011 12:13:58 +0800 Subject: [coreboot] one super i/o In-Reply-To: References: Message-ID: You can run superiotool to find out the logical device number (LDN) of each device. That is the way if we don't have the datasheet. Zheng > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of ali hagigat > Sent: Wednesday, January 05, 2011 11:44 AM > To: coreboot at coreboot.org > Subject: [coreboot] one super i/o > > I am looking for the data sheet and programming reference manual of a > super I/O chip by ITE, IT8703F. > I will be much appreciated if anybody can email it for me. > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From buurin at gmail.com Wed Jan 5 06:06:29 2011 From: buurin at gmail.com (Keith Hui) Date: Wed, 5 Jan 2011 00:06:29 -0500 Subject: [coreboot] Next target: ASUS TUSI-M Message-ID: This is the next board I want to port coreboot to. And the three logs are attached. "Sissy" is what I name the machine the board is in, after SiS. :D The flash chip i know for sure is SST 39SF020A. It needs a board enable, for which I have figured out 3 of the 5 operations involved, thanks to Luc's slides up at Phoronix. It used a soldered PLCC32 flash chip. I soldered a socket on myself, and the chip miraclously survived. But I have not been able to get another of the same chip for backup. All my 3 spares are DIP32. Super I/O is IT8705F, already supported. So it looks like all that's needed is porting SiS630 from coreboot v1. I think I would also be the first to port a single chip chipset to v4. Thanks to a previous thread on this list, I got the '630 datasheet, but I don't know for sure what is different between it (the 630) and my chip (630ET). Appreciate all the help I can get for this one. -------------- next part -------------- flashrom v0.9.3-r1205 on Linux 2.6.36 (i686), built with libpci 3.1.3, GCC 4.3.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 2 usecs, 697M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 999 us, 10000 myus = 10120 us, 8 myus = 8 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System Manufacturer" DMI string system-product-name: "System Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "TUSI-M" DMI string baseboard-version: "REV 1.xx" DMI string chassis-type: "Tower" Found ITE Super I/O, ID 0x8705. Found chipset "SiS 630", enabling flash write... chipset PCI ID is 1039:0630, Found southbridge 1039:0018 at 00:01:0 OK. This chipset supports the following protocols: Non-SPI. Enabling IT8705F flash ROM interface write. Maximum IT8705F parallel flash decode size is 262144. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip size 2048 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: Chip size 1024 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip size 1024 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A25L512, 64 KB: skipped. Probing for AMIC A25L010, 128 KB: skipped. Probing for AMIC A25L020, 256 KB: skipped. Probing for AMIC A25L040, 512 KB: skipped. Probing for AMIC A25L080, 1024 KB: skipped. Probing for AMIC A25L016, 2048 KB: skipped. Probing for AMIC A25L032, 4096 KB: skipped. Probing for AMIC A25LQ032, 4096 KB: skipped. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: skipped. Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF081A, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25DQ161, 2048 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0xef, id2 0xdb, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C040A, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0xef, id2 0xdb, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F020, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Bright BM29F040, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for EMST F25L008A, 1024 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_m29f400bt: id1 0x20, id2 0x2d Probing for Fujitsu MBM29F400TC, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_m29f400bt: id1 0x20, id2 0x2d Probing for Hyundai HY29F002T, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Hyundai HY29F002B, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Hyundai HY29F040A, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-T, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: probe_82802ab: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_82802ab: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_82802ab: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_82802ab: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_82802ab: id1 0x20, id2 0x2d, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_82802ab: id1 0x20, id2 0x2d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L1635E, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 KB: probe_jedec_common: id1 0xef, id2 0xdb, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000T, 64 KB: probe_jedec_common: id1 0xef, id2 0xdb, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51400B, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51400T, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51000, 64 KB: probe_jedec_common: id1 0xef, id2 0xdb, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51001, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51002, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_82802ab: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0xef, id2 0xdb, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF040, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0xef, id2 0xdb, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF040, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF080, 1024 KB: Chip size 1024 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M25PX32, 4096 KB: skipped. Probing for ST M25PX64, 8192 KB: skipped. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_m29f400bt: id1 0x20, id2 0x2d Probing for ST M29F400BT, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_m29f400bt: id1 0x20, id2 0x2d Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0xef, id2 0xdb, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: probe_jedec_common: id1 0xe4, id2 0xd5, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C020(C)/W29C022, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C040/P, 512 KB: Chip size 512 kB is bigger than supported size 256 kB of chipset/board/programmer for Parallel interface, probe/read/erase/write may fail. probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040(F)B, 512 KB: skipped. Probing for Winbond W39V040(F)C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U/N, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F020, 256 KB: probe_jedec_common: id1 0x20, id2 0x98, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for Eon unknown Eon SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. -------------- next part -------------- 00:00.0 0600: 1039:0630 (rev 30) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- Kernel driver in use: agpgart-sis Kernel modules: sis-agp 00: 39 10 30 06 07 00 10 22 30 00 00 06 00 20 80 00 10: 00 00 00 e8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 9e 00 c1 00 95 01 81 01 00 55 51 00 00 00 00 00 60: 2a 2a 00 83 00 00 00 00 00 00 e2 00 af 00 00 00 70: 07 9f 00 00 00 00 00 00 00 00 00 00 42 00 00 00 80: 21 ff 7f 1f 60 00 03 40 00 08 00 00 88 67 00 2a 90: 00 00 ee 1e 43 00 00 05 00 00 00 00 00 00 00 00 a0: 00 00 03 01 00 00 00 00 00 00 00 00 00 00 fe 01 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 02 00 20 00 07 02 00 1f 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.1 0101: 1039:5513 (rev d0) (prog-if 80 [Master]) Subsystem: 1043:80e1 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 00: 39 10 01 00 07 00 00 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 a0 a0 00 20 20: 80 e5 f0 e5 00 f0 a0 fe 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:05.0 0401: 13f6:0111 (rev 10) Subsystem: 1043:80e1 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- [disabled] Capabilities: [40] Power Management version 1 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] AGP version 2.0 Status: RQ=16 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate= Kernel modules: sisfb 00: 39 10 00 63 03 00 b0 02 21 00 00 03 00 00 00 80 10: 08 00 00 f0 00 00 80 e5 01 a8 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 e1 80 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00 40: 01 50 01 06 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 00 20 00 07 02 00 0f 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -------------- next part -------------- superiotool r6245 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xf500, id=0x0587 Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8705F/AF / IT8700F (id=0x8705, rev=0x2) at 0x2e Register dump: idx 20 21 22 23 24 val 87 05 02 00 f5 def 87 05 00 00 NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 00 03 f8 04 00 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 01 02 f8 03 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 64 65 70 74 f0 val 01 03 78 07 78 00 80 07 03 03 def 00 03 78 07 78 00 80 07 03 03 LDN 0x04 (Environment controller) idx 2b 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 00 01 02 90 02 30 09 00 00 00 00 40 00 ff def 00 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (GPIO) idx 25 26 27 28 29 2a 60 61 62 63 64 65 70 71 72 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc cd d0 d1 d2 d3 d4 d5 d6 d8 d9 da f0 f1 f2 f5 f6 f7 f8 f9 fa fb fc fd fe ff val 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 def 00 00 00 ff e0 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x06 (Game port) idx 30 60 61 val 00 00 00 def 00 02 01 LDN 0x07 (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 00 00 00 03 def 00 03 00 0a 00 Environment controller (0x0295) Probing for ITE Super I/O (init=standard) at 0x4e... Found ITE IT8705F/AF / IT8700F (id=0x8705, rev=0x2) at 0x4e Register dump: idx 20 21 22 23 24 val 87 05 02 00 f5 def 87 05 00 00 NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 00 03 f8 04 00 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 01 02 f8 03 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 64 65 70 74 f0 val 01 03 78 07 78 00 80 07 03 03 def 00 03 78 07 78 00 80 07 03 03 LDN 0x04 (Environment controller) idx 2b 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 00 01 02 90 02 30 09 00 00 00 00 40 00 ff def 00 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (GPIO) idx 25 26 27 28 29 2a 60 61 62 63 64 65 70 71 72 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc cd d0 d1 d2 d3 d4 d5 d6 d8 d9 da f0 f1 f2 f5 f6 f7 f8 f9 fa fb fc fd fe ff val 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 def 00 00 00 ff e0 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x06 (Game port) idx 30 60 61 val 00 00 00 def 00 02 01 LDN 0x07 (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 00 00 00 03 def 00 03 00 0a 00 Environment controller (0x0295) Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0x00, rev=0x00 Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. From m.cassaniti at gmail.com Wed Jan 5 07:28:06 2011 From: m.cassaniti at gmail.com (Michael Cassaniti) Date: Wed, 5 Jan 2011 17:28:06 +1100 Subject: [coreboot] Support for Asus M2N-SLI Deluxe Message-ID: Hi, Answering the following questions from the FAQ, I have the following: Board Vendor: Asus Board Product Name: M2N-SLI Deluxe CPU Model: AMD Athlon 64FX, Socket AM2 Northbridge: Nvidia nForce 570 SLI Southbridge: Nvidia MCP55 Link to specifications: http://www.asus.com.au/product.aspx?P_ID=szSFtrap7crpBaQE Attached are the outputs of lspci, superiotool and flashrom. I noticed that a similar board (Asus M2N-E) is supported. I was hoping that porting to this board would not require major rework. Regards, Michael Cassaniti -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- flashrom v0.9.3-r1205 on Linux 2.6.34-gentoo-r12 (x86_64), built with libpci 3.1.4, GCC 4.3.4, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1156M loops per second, 10 myus = 11 us, 100 myus = 97 us, 1000 myus = 1082 us, 10000 myus = 10023 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. sh: dmidecode: command not found dmidecode execution unsucessfull - continuing without DMI info Found ITE Super I/O, ID 0x8716. Found chipset "NVIDIA MCP55", enabling flash write... chipset PCI ID is 10de:0360, OK. This chipset supports the following protocols: Non-SPI. No IT87* serial flash segment enabled. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0x00, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A25L512, 64 KB: skipped. Probing for AMIC A25L010, 128 KB: skipped. Probing for AMIC A25L020, 256 KB: skipped. Probing for AMIC A25L040, 512 KB: skipped. Probing for AMIC A25L080, 1024 KB: skipped. Probing for AMIC A25L016, 2048 KB: skipped. Probing for AMIC A25L032, 4096 KB: skipped. Probing for AMIC A25LQ032, 4096 KB: skipped. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF081A, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25DQ161, 2048 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Bright BM29F040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for EMST F25L008A, 1024 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0x00, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for Hyundai HY29F002T, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F002B, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Hyundai HY29F040A, 512 KB: probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F001BN/BX-T, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: probe_82802ab: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 KB: probe_82802ab: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: probe_82802ab: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: probe_82802ab: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: probe_82802ab: id1 0x21, id2 0x2d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: probe_82802ab: id1 0x21, id2 0x2d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L1635E, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x00, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x00, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 KB: probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51000T, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29C51400T, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51000, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51001, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for MoselVitelic V29LC51002, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0x00, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 KB: probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 KB: probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M25PX32, 4096 KB: skipped. Probing for ST M25PX64, 8192 KB: skipped. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0x00, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0xe9, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x21, id2 0x7e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0x37, id2 0x82, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C020(C)/W29C022, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C040/P, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040(F)B, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040(F)C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49F020, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x9d, id2 0x6e Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for Eon unknown Eon SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No operations were specified. -------------- next part -------------- -[0000:00]-+-00.0 nVidia Corporation MCP55 Memory Controller [10de:0369] +-01.0 nVidia Corporation MCP55 LPC Bridge [10de:0360] +-01.1 nVidia Corporation MCP55 SMBus [10de:0368] +-01.2 nVidia Corporation MCP55 Memory Controller [10de:036a] +-02.0 nVidia Corporation MCP55 USB Controller [10de:036c] +-02.1 nVidia Corporation MCP55 USB Controller [10de:036d] +-04.0 nVidia Corporation MCP55 IDE [10de:036e] +-05.0 nVidia Corporation MCP55 SATA Controller [10de:037f] +-05.1 nVidia Corporation MCP55 SATA Controller [10de:037f] +-05.2 nVidia Corporation MCP55 SATA Controller [10de:037f] +-06.0-[01]-- +-08.0 nVidia Corporation MCP55 Ethernet [10de:0373] +-09.0 nVidia Corporation MCP55 Ethernet [10de:0373] +-0e.0-[02]-- +-0f.0-[03]----00.0 nVidia Corporation G73 [GeForce 7300 GT] [10de:0393] +-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] \-18.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] -------------- next part -------------- superiotool r5728 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8716F (id=0x8716, rev=0x1) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 16 01 01 00 00 def 87 16 01 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 04 00 80 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 01 03 f8 04 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 01 03 78 00 00 07 04 09 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 00 00 0a 00 8a 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 00 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 00 00 40 80 00 00 1f 00 00 08 00 00 00 00 01 00 38 00 00 00 20 00 00 00 00 00 00 80 00 00 00 00 60 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 32 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 03 00 0a 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 00 02 01 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0x00, rev=0x00 Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. From Zheng.Bao at amd.com Wed Jan 5 10:14:28 2011 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Wed, 5 Jan 2011 17:14:28 +0800 Subject: [coreboot] [patch]Fix some settings of AMD MCT Message-ID: Fix some settings of AMD MCT. It is based on BIOS test suite. Signed-off-by: Index: src/northbridge/amd/amdmct/mct/mct_d.c =================================================================== --- src/northbridge/amd/amdmct/mct/mct_d.c (revision 6244) +++ src/northbridge/amd/amdmct/mct/mct_d.c (working copy) @@ -154,8 +154,11 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct); static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); +static u32 mct_DisDllShutdownSR(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u32 DramConfigLo, u8 dct); +static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); - /*See mctAutoInitMCT header for index relationships to CL and T*/ static const u16 Table_F_k[] = {00,200,266,333,400,533 }; static const u8 Table_T_k[] = {0x00,0x50,0x3D,0x30,0x25, 0x18 }; @@ -822,6 +825,8 @@ all of the MemClkDis bits should also be set.*/ val = 0xFF000000; Set_NB32(pDCTstat->dev_dct, reg_off+0x88, val); + } else { + mct_EnDllShutdownSR(pMCTstat, pDCTstat, dct); } } @@ -1589,8 +1594,8 @@ if ( mctGet_NVbits(NV_ECC)) DramConfigLo |= 1 << DimmEcEn; + DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct); - /* Build Dram Config Hi Register Value */ dword = pDCTstat->Speed; DramConfigHi |= dword - 1; /* get MemClk encoding */ @@ -3630,7 +3635,42 @@ } } +static u32 mct_DisDllShutdownSR(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u32 DramConfigLo, u8 dct) +{ + u32 reg_off = 0x100 * dct; + u32 dev = pDCTstat->dev_dct; + /* Write 0000_07D0h to register F2x[1, 0]98_x4D0FE006 */ + if (pDCTstat->LogicalCPUID & (AMD_DA_C2 | AMD_RB_C3)) { + Set_NB32(dev, 0x9C + reg_off, 0x7D0); + Set_NB32(dev, 0x98 + reg_off, 0x4D0FE006); + Set_NB32(dev, 0x9C + reg_off, 0x190); + Set_NB32(dev, 0x98 + reg_off, 0x4D0FE007); + } + + return DramConfigLo | /* DisDllShutdownSR */ 1 << 27; +} + +static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct) +{ + u32 reg_off = 0x100 * dct; + u32 dev = pDCTstat->dev_dct, val; + + /* Write 0000_07D0h to register F2x[1, 0]98_x4D0FE006 */ + if (pDCTstat->LogicalCPUID & (AMD_DA_C2 | AMD_RB_C3)) { + Set_NB32(dev, 0x9C + reg_off, 0x1C); + Set_NB32(dev, 0x98 + reg_off, 0x4D0FE006); + Set_NB32(dev, 0x9C + reg_off, 0x13D); + Set_NB32(dev, 0x98 + reg_off, 0x4D0FE007); + + val = Get_NB32(dev, 0x90 + reg_off); + val &= ~(1 << 27/* DisDllShutdownSR */); + Set_NB32(dev, 0x90 + reg_off, val); + } +} + void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { Index: src/northbridge/amd/amdmct/amddefs.h =================================================================== --- src/northbridge/amd/amdmct/amddefs.h (revision 6244) +++ src/northbridge/amd/amdmct/amddefs.h (working copy) @@ -69,6 +69,8 @@ #define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) #define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) +#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) +#define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3) /* * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE Index: src/northbridge/amd/amdfam10/raminit_amdmct.c =================================================================== --- src/northbridge/amd/amdfam10/raminit_amdmct.c (revision 6244) +++ src/northbridge/amd/amdfam10/raminit_amdmct.c (working copy) @@ -65,6 +65,7 @@ #include "../amdmct/mct_ddr3/mcthdi.c" #include "../amdmct/mct_ddr3/mctndi_d.c" #include "../amdmct/mct_ddr3/mctchi_d.c" +#include "../amdmct/mct_ddr3/modtrd.c" #if CONFIG_CPU_SOCKET_TYPE == 0x10 //TODO: S1G1? Index: src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c =================================================================== --- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c (revision 6244) +++ src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c (working copy) @@ -190,7 +190,6 @@ SetTargetFreq(pMCTstat, pDCTstat); PhyWLPass2(pMCTstat, pDCTstat, 0); PhyWLPass2(pMCTstat, pDCTstat, 1); - } SetEccWrDQS_D(pMCTstat, pDCTstat); Index: src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c =================================================================== --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c (revision 6244) +++ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c (working copy) @@ -552,6 +552,18 @@ } if (BanksPresent) { + #if 0 /* show the bitmap */ + for (ByteLane = 0; ByteLane < 8; ByteLane++) { /* just print ByteLane 0 */ + for (DQSDelay = 0; DQSDelay < dqsDelay_end; DQSDelay++) { + if (!(MutualCSPassW[DQSDelay] &(1 << ByteLane))) { + printk(BIOS_DEBUG, "."); + } else { + printk(BIOS_DEBUG, "*"); + } + } + printk(BIOS_DEBUG, "\n"); + } + #endif for (ByteLane = 0; ByteLane < 8; ByteLane++) { print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); if (!(pDCTstat->DqsRdWrPos_Saved &(1 << ByteLane))) { Index: src/northbridge/amd/amdmct/mct_ddr3/mctprob.c =================================================================== --- src/northbridge/amd/amdmct/mct_ddr3/mctprob.c (revision 6244) +++ src/northbridge/amd/amdmct/mct_ddr3/mctprob.c (working copy) @@ -35,3 +35,10 @@ Set_NB32(pDCTstat->dev_dct, 0x198, 0x4D0F4F07); } } + +void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat) +{ + if (pDCTstat->LogicalCPUID & (AMD_DR_Bx)) { + Set_NB32(pDCTstat->dev_dct, 0x11C, 0x0FE40FC0 | 1 << 29/* FlushWrOnStpGnt */); + } +} Index: src/northbridge/amd/amdmct/mct_ddr3/mctproc.c =================================================================== --- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c (revision 6244) +++ src/northbridge/amd/amdmct/mct_ddr3/mctproc.c (working copy) @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* mct_SetDramConfigMisc2_Cx & mct_SetDramConfigMisc2_Dx */ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, u8 dct, u32 misc2) { u32 val; @@ -40,6 +41,22 @@ val &= 0xFF; misc2 &= 0xFFF8FFFF; misc2 |= val << 16; /* DataTxFifoWrDly */ + if (pDCTstat->LogicalCPUID & AMD_DR_Dx) + misc2 |= 1 << 7; /* ProgOdtEn */ } return misc2; } + +void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat) +{ + u32 val; + + if (pDCTstat->LogicalCPUID & (AMD_DR_Cx)) { + Set_NB32(pDCTstat->dev_dct, 0x11C, 0x0CE00FC0 | 1 << 29/* FlushWrOnStpGnt */); + + val = Get_NB32(pDCTstat->dev_dct, 0x1B0); + val &= 0xFFFFF8C0; + val |= 0x101; /* BKDG recommended settings */ + Set_NB32(pDCTstat->dev_dct, 0x1B0, val); + } +} Index: src/northbridge/amd/amdmct/mct_ddr3/mctrci.c =================================================================== --- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c (revision 6244) +++ src/northbridge/amd/amdmct/mct_ddr3/mctrci.c (working copy) @@ -25,7 +25,7 @@ u32 dct = 0; u32 reg_off = 0; - DimmNum = MrsChipSel >> 20; + DimmNum = (MrsChipSel >> 20) & 0xFE; /* assume dct=0; */ /* if (dct == 1) */ @@ -39,6 +39,7 @@ dct = 0; } else if (pDCTstat->CSPresent_DCT[1] > 0 ){ dct = 1; + DimmNum ++; } reg_off = 0x100 * dct; Dimms = pDCTstat->MAdimms[dct]; @@ -49,27 +50,26 @@ else if (CtrlWordNum == 1) { if (!((pDCTstat->DimmDRPresent | pDCTstat->DimmQRPresent) & (1 << DimmNum))) val |= 0xC; /* if single rank, set DBA1 and DBA0 */ - } - else if (CtrlWordNum == 2) { + } else if (CtrlWordNum == 2) { if (MaxDimm == 4) { if (Speed == 4) { - if (((pDCTstat->DimmQRPresent & (1 << DimmNum)) && (Dimms == 1)) || Dimms == 2) + if (((pDCTstat->DimmQRPresent & (1 << DimmNum)) && (Dimms == 1)) || (Dimms == 2)) if (!(pDCTstat->MirrPresU_NumRegR & (1 << DimmNum))) val |= 1 << 2; } else { if (pDCTstat->MirrPresU_NumRegR & (1 << DimmNum)) - val |= 2; + val |= 1 << 2; } } else { if (Dimms > 1) - val |= 2; + val |= 1 << 2; } } else if (CtrlWordNum == 3) { - val = pDCTstat->CtrlWrd3 >> (DimmNum << 2); + val |= (pDCTstat->CtrlWrd3 >> (DimmNum << 2)) & 0xFF; } else if (CtrlWordNum == 4) { - val = pDCTstat->CtrlWrd4 >> (DimmNum << 2); + val |= (pDCTstat->CtrlWrd4 >> (DimmNum << 2)) & 0xFF; } else if (CtrlWordNum == 5) { - val = pDCTstat->CtrlWrd5 >> (DimmNum << 2); + val |= (pDCTstat->CtrlWrd5 >> (DimmNum << 2)) & 0xFF; } else if (CtrlWordNum == 8) { if (MaxDimm == 4) if (Speed == 4) @@ -78,9 +78,9 @@ } else if (CtrlWordNum == 9) { val |= 0xD; /* DBA1, DBA0, DA3 = 0 */ } - val &= 0xf; + val &= 0xffffff0f; - val = MrsChipSel | ((val >> 2) & 3) << 16 | MrsChipSel | ((val >> 2) & 3); + val = MrsChipSel | ((val >> 2) & 3) << 16 | ((val & 3) << 3); /* transfer Control word number to address [BA2,A2,A1,A0] */ if (CtrlWordNum > 7) { @@ -170,17 +170,19 @@ pDCTstat->DIMMAutoSpeed = pDCTstat->TargetFreq; for (MrsChipSel=0; MrsChipSel < 8; MrsChipSel++, MrsChipSel++) { if (pDCTstat->CSPresent & (1 << MrsChipSel)) { - val = Get_NB32(dev, 0xA8); + /* 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. */ + val = Get_NB32(dev, 0xA8); /* TODO: dct * 0x100 + 0xA8 */ val &= ~(0xFF << 8); - val |= (0x3 << MrsChipSel) << 8; - Set_NB32(dev, 0xA8, val); + val |= (0x3 << (MrsChipSel & 0xFE)) << 8; + Set_NB32(dev, 0xA8, val); /* TODO: dct * 0x100 + 0xA8 */ + /* Resend control word 10 */ mct_Wait(1600); switch (pDCTstat->TargetFreq) { - case 6: + case 5: mct_SendCtrlWrd(pMCTstat, pDCTstat, MrsChipSel << 20 | 0x4000A); break; - case 5: + case 6: mct_SendCtrlWrd(pMCTstat, pDCTstat, MrsChipSel << 20 | 0x40012); break; case 7: @@ -190,6 +192,7 @@ mct_Wait(1600); + /* Resend control word 2 */ val = mct_ControlRC(pMCTstat, pDCTstat, MrsChipSel << 20, 2); mct_SendCtrlWrd(pMCTstat, pDCTstat, val); Index: src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c =================================================================== --- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c (revision 6244) +++ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c (working copy) @@ -158,7 +158,7 @@ if (dword & (1 << 7)) ret |= 1 << 2; } else { - /* TODO: mct_MR1Odt_RDimm */ + ret |= mct_MR1Odt_RDimm(pMCTstat, pDCTstat, dct, MrsChipSel); } /* program MrsAddress[11]=TDQS: based on F2x[1,0]94[RDqsEn] */ Index: src/northbridge/amd/amdmct/mct_ddr3/mct_d.c =================================================================== --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c (revision 6244) +++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c (working copy) @@ -80,6 +80,8 @@ struct DCTStatStruc *pDCTstat, u8 dct); static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); +static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat); static void Get_Trdrd(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); @@ -133,7 +135,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void mct_EarlyArbEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); + struct DCTStatStruc *pDCTstat, u8 dct); static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat, @@ -153,7 +155,11 @@ struct DCTStatStruc *pDCTstat, u8 dct); static u32 mct_DisDllShutdownSR(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 DramConfigLo, u8 dct); +static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +static u32 mct_MR1Odt_RDimm(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel); static u32 mct_DramTermDyn_RDimm(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dimm); static u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, u8 dct, u32 misc2); @@ -163,6 +169,8 @@ struct DCTStatStruc *pDCTstat, u8 dct); static void SyncSetting(struct DCTStatStruc *pDCTstat); static u8 crcCheck(u8 smbaddr); +static void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat); +static void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat); /*See mctAutoInitMCT header for index relationships to CL and T*/ static const u16 Table_F_k[] = {00,200,266,333,400,533 }; @@ -334,7 +342,7 @@ MCTMemClr_D(pMCTstat,pDCTstatA); } - mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); /* Node 0 */ + mct_FinalMCT_D(pMCTstat, pDCTstatA); printk(BIOS_DEBUG, "All Done\n"); return; @@ -819,7 +827,7 @@ val = 0xFF000000; Set_NB32(pDCTstat->dev_dct, reg_off+0x88, val); } else { - /* mct_EnDllShutdownSR */ + mct_EnDllShutdownSR(pMCTstat, pDCTstat, dct); } } @@ -902,7 +910,14 @@ } while(reg < reg_end) { + if ((reg & 0xFF) == 0x90) { + if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { + val = Get_NB32(dev, reg); /* get DRAMConfigLow */ + val |= 0x08000000; /* preserve value of DisDllShutdownSR for only Rev.D */ + } + } Set_NB32(dev, reg, val); + val = 0; reg += 4; } @@ -1485,6 +1500,7 @@ if (pDCTstat->GangedMode == 1) { mctGet_PS_Cfg_D(pMCTstat, pDCTstat, 1); + mct_BeforePlatformSpec(pMCTstat, pDCTstat, 1); } if ( pDCTstat->_2Tmode == 2) { @@ -1495,6 +1511,7 @@ Set_NB32(dev, reg, val); } + mct_BeforePlatformSpec(pMCTstat, pDCTstat, dct); mct_PlatformSpec(pMCTstat, pDCTstat, dct); if (pDCTstat->DIMMAutoSpeed == 4) InitPhyCompensation(pMCTstat, pDCTstat, dct); @@ -1674,7 +1691,7 @@ dword = Get_NB32(dev, 0x94 + reg_off); DramConfigHi |= dword; mct_SetDramConfigHi_D(pDCTstat, dct, DramConfigHi); - mct_EarlyArbEn_D(pMCTstat, pDCTstat); + mct_EarlyArbEn_D(pMCTstat, pDCTstat, dct); mctHookAfterAutoCfg(); /* dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); */ @@ -2341,6 +2358,25 @@ } +static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct) +{ + /* mct_checkForCxDxSupport_D */ + if (pDCTstat->LogicalCPUID & AMD_DR_GT_Bx) { + /* 1. Write 00000000h to F2x[1,0]9C_xD08E000 */ + Set_NB32_index_wait(pDCTstat->dev_dct, 0x98 + dct * 0x100, 0x0D08E000, 0); + /* 2. If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is + greater than or equal to 011b (DDR-800 and higher), + then write 00000080h to F2x[1,0]9C_xD02E001, + else write 00000090h to F2x[1,0]9C_xD02E001. */ + if (pDCTstat->Speed >= 4) + Set_NB32_index_wait(pDCTstat->dev_dct, 0x98 + dct * 0x100, 0xD02E001, 0x80); + else + Set_NB32_index_wait(pDCTstat->dev_dct, 0x98 + dct * 0x100, 0xD02E001, 0x90); + } + return pDCTstat->ErrCode; +} + static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { @@ -2368,7 +2404,6 @@ } return pDCTstat->ErrCode; - } static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat) @@ -2870,11 +2905,97 @@ return word; } +static void mct_PhyController_Config(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct) +{ + u32 index_reg = 0x98 + 0x100 * dct; + u32 dev = pDCTstat->dev_dct; + u32 val; + + if (pDCTstat->LogicalCPUID & (AMD_DR_DAC2_OR_C3 | AMD_RB_C3)) { + if (pDCTstat->Dimmx4Present == 0) { + /* Set bit7 RxDqsUDllPowerDown to register F2x[1, 0]98_x0D0F0F13 for power saving */ + val = Get_NB32_index_wait(dev, index_reg, 0x0D0F0F13); /* Agesa v3 v6 might be wrong here. */ + val |= 1 << 7; /* BIOS should set this bit when x4 DIMMs are not present */ + Set_NB32_index_wait(dev, index_reg, 0x0D0F0F13, val); + } + } + + if (pDCTstat->LogicalCPUID & AMD_DR_DAC2_OR_C3) { + if (pDCTstat->DimmECCPresent == 0) { + /* Set bit4 PwrDn to register F2x[1, 0]98_x0D0F0830 for power saving */ + val = Get_NB32_index_wait(dev, index_reg, 0x0D0F0830); + val |= 1 << 4; /* BIOS should set this bit if ECC DIMMs are not present */ + Set_NB32_index_wait(dev, index_reg, 0x0D0F0830, val); + } + } + +} + static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) + struct DCTStatStruc *pDCTstatA) { + u8 Node; + struct DCTStatStruc *pDCTstat; + u32 val; + + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + pDCTstat = pDCTstatA + Node; + + if (pDCTstat->NodePresent) { + mct_PhyController_Config(pMCTstat, pDCTstat, 0); + mct_PhyController_Config(pMCTstat, pDCTstat, 1); + } + if (!(pDCTstat->LogicalCPUID & AMD_DR_Dx)) { /* mct_checkForDxSupport */ + mct_ExtMCTConfig_Cx(pDCTstat); + mct_ExtMCTConfig_Bx(pDCTstat); + } else { /* For Dx CPU */ + val = 0x0CE00F00 | 1 << 29/* FlushWrOnStpGnt */; + if (!(pDCTstat->GangedMode)) + val |= 0x20; /* MctWrLimit = 8 for Unganed mode */ + else + val |= 0x40; /* MctWrLimit = 16 for ganed mode */ + Set_NB32(pDCTstat->dev_dct, 0x11C, val); + + val = Get_NB32(pDCTstat->dev_dct, 0x1B0); + val &= 0xFFFFF8C0; + val |= 0x101; /* BKDG recommended settings */ + val |= 0x0FC00000; /* Agesa V5 */ + if (!(pDCTstat->GangedMode)) + val |= 1 << 12; + else + val &= ~(1 << 12); + + val &= 0x0FFFFFFF; + switch (pDCTstat->Speed) { + case 4: + val |= 0x50000000; /* 5 for DDR800 */ + break; + case 5: + val |= 0x60000000; /* 6 for DDR1066 */ + break; + case 6: + val |= 0x80000000; /* 8 for DDR800 */ + break; + default: + val |= 0x90000000; /* 9 for DDR1600 */ + break; + } + Set_NB32(pDCTstat->dev_dct, 0x1B0, val); + } + } + /* ClrClToNB_D postponed until we're done executing from ROM */ mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat); + + /* set F3x8C[DisFastTprWr] on all DR, if L3Size=0 */ + if (pDCTstat->LogicalCPUID & AMD_DR_ALL) { + if (!(cpuid_edx(0x80000006) & 0xFFFC0000)) { + val = Get_NB32(pDCTstat->dev_nbmisc, 0x8C); + val |= 1 << 24; + Set_NB32(pDCTstat->dev_nbmisc, 0x8C, val); + } + } } static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) @@ -3138,7 +3259,7 @@ } static void mct_EarlyArbEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) + struct DCTStatStruc *pDCTstat, u8 dct) { u32 reg; u32 val; @@ -3150,10 +3271,10 @@ * bit 19 of F2x[1,0]78 Dram Control Register, set this bit only when * NB CLK : Memclk ratio is between 3:1 (inclusive) to 4:5 (inclusive) */ - reg = 0x78; + reg = 0x78 + 0x100 * dct; val = Get_NB32(dev, reg); - if (pDCTstat->LogicalCPUID & (AMD_DR_Bx | AMD_DR_Cx)) + if (pDCTstat->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx)) val |= (1 << EarlyArbEn); else if (CheckNBCOFEarlyArbEn(pMCTstat, pDCTstat)) val |= (1 << EarlyArbEn); @@ -3272,6 +3393,25