[coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

[Jouni Mettälä]

Hi

Parts of original patch are already in coreboot. This version made cache
work in my board now. It might need work so it doesn't break others. Here is
part of serial capture. Rest is attached

Initializing CPU #0
CPU: vendor Intel device 673
CPU: family 06, model 07, stepping 03
microcode_info: sig = 0x00000673 pf=0x00000001 rev = 0x00000000
microcode updated to revision: 0000000e from revision 00000000
Configuring L2 cache... rdmsr(IA32_PLATFORM_ID) = 0, 11020000
L2 Cache latency is 8
Sending 0 to set_l2_register4
L2 ECC Checking is enabled
L2 Physical Address Range is 4096M
Maximum cache mask is 20000
L2 Cache Mask is 4000
read_l2(2) = 8
write_l2(2) = 8
L2 Cache size is 512K
L2 Cache lines initialized

Signed-off-by: Jouni Mettälä <jtmettala at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110107/7ae92c2b/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: cache_l2-6247.patch
Type: application/octet-stream
Size: 10346 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110107/7ae92c2b/attachment.obj>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: l2_cache.cap
Type: application/octet-stream
Size: 25107 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110107/7ae92c2b/attachment-0001.obj>