[coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this
Keith Hui
buurin at gmail.com
Wed Jan 12 05:17:17 CET 2011
Hi all,
Here is the new L2 cache patch. Sign-off in the patch itself. Still
very juicy and tasty at 25k. :D
Also done is including cpu/intel/model_68x again in slot_1. Otherwise
it will die with a Coppermine P3 installed.
My boot log on P2B-LS and a Katmai 600MHz attached.
I have optimized it some more, and added more information and
meaningful constants as I cross checked the code with Intel's
documentation. Some debugging messages are different too. Give this a
good workout.
Cheers
Keith
ps. Copying people who have sent me reports. :)
On Fri, Jan 7, 2011 at 3:45 PM, Jouni Mettälä <jtmettala at gmail.com> wrote:
> Hi
> Parts of original patch are already in coreboot. This version made cache
> work in my board now. It might need work so it doesn't break others. Here is
> part of serial capture. Rest is attached
> Initializing CPU #0
> CPU: vendor Intel device 673
> CPU: family 06, model 07, stepping 03
> microcode_info: sig = 0x00000673 pf=0x00000001 rev = 0x00000000
> microcode updated to revision: 0000000e from revision 00000000
> Configuring L2 cache... rdmsr(IA32_PLATFORM_ID) = 0, 11020000
> L2 Cache latency is 8
> Sending 0 to set_l2_register4
> L2 ECC Checking is enabled
> L2 Physical Address Range is 4096M
> Maximum cache mask is 20000
> L2 Cache Mask is 4000
> read_l2(2) = 8
> write_l2(2) = 8
> L2 Cache size is 512K
> L2 Cache lines initialized
> Signed-off-by: Jouni Mettälä <jtmettala at gmail.com>
-------------- next part --------------
coreboot-4.0-r5917:6247M Tue Jan 11 20:56:00 EST 2011 starting...
Loading image.
Check CBFS header at fffffc9e
magic is 4f524243
Found CBFS header at fffffc9e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 2c48 + align -> fffc2c80
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (278528 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-4.0-r5917:6247M Tue Jan 11 20:56:00 EST 2011 booting...
clocks_per_usec: 602
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:04.0: enabled 1
PNP: 03f0.0: enabled 1
PNP: 03f0.1: enabled 1
PNP: 03f0.2: enabled 1
PNP: 03f0.3: enabled 1
PNP: 03f0.5: enabled 1
PNP: 03f0.7: enabled 1
PNP: 03f0.8: enabled 1
PNP: 03f0.a: enabled 1
PCI: 00:04.1: enabled 1
PCI: 00:04.2: enabled 1
PCI: 00:04.3: enabled 1
Compare with tree...
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:04.0: enabled 1
PNP: 03f0.0: enabled 1
PNP: 03f0.1: enabled 1
PNP: 03f0.2: enabled 1
PNP: 03f0.3: enabled 1
PNP: 03f0.5: enabled 1
PNP: 03f0.7: enabled 1
PNP: 03f0.8: enabled 1
PNP: 03f0.a: enabled 1
PCI: 00:04.1: enabled 1
PCI: 00:04.2: enabled 1
PCI: 00:04.3: enabled 1
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/7190] ops
PCI: 00:00.0 [8086/7190] enabled
PCI: 00:01.0 [8086/7191] enabled
PCI: 00:04.0 [8086/7110] bus ops
PCI: 00:04.0 [8086/7110] enabled
PCI: 00:04.1 [8086/7111] ops
PCI: 00:04.1 [8086/7111] enabled
PCI: 00:04.2 [8086/7112] ops
PCI: 00:04.2 [8086/7112] enabled
PCI: 00:04.3 [8086/7113] bus ops
PCI: 00:04.3 [8086/7113] enabled
PCI: 00:06.0 [9005/001f] ops
PCI: 00:06.0 [9005/001f] enabled
PCI: 00:07.0 [8086/1229] enabled
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [1002/475a] enabled
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:04.0
PNP: 03f0.0 enabled
PNP: 03f0.1 enabled
PNP: 03f0.2 enabled
PNP: 03f0.3 enabled
PNP: 03f0.5 enabled
PNP: 03f0.7 enabled
PNP: 03f0.8 enabled
PNP: 03f0.a enabled
PNP: 03f0.6 enabled
scan_static_bus for PCI: 00:04.0 done
scan_static_bus for PCI: 00:04.3
scan_static_bus for PCI: 00:04.3 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 01:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:04.0 read_resources bus 0 link: 0
PNP: 03f0.8 missing read_resources
PCI: 00:04.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
PCI: 00:01.0 child on link 0 PCI: 01:00.0
PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 1200 index 10
PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
PCI: 00:04.0 child on link 0 PNP: 03f0.0
PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
PNP: 03f0.0
PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 03f0.1
PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 03f0.2
PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 03f0.3
PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 03f0.5
PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
PNP: 03f0.7
PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62
PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 03f0.8
PNP: 03f0.a
PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 03f0.6
PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PCI: 00:04.1
PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:04.2
PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
PCI: 00:04.3
PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
PCI: 00:06.0
PCI: 00:06.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
PCI: 00:06.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 14
PCI: 00:06.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
PCI: 00:07.0
PCI: 00:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 1200 index 10
PCI: 00:07.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 14
PCI: 00:07.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18
PCI: 00:07.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 2200 index 30
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 01:00.0 14 * [0x0 - 0xff] io
PCI: 00:01.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c * [0x0 - 0xfff] io
PCI: 00:06.0 10 * [0x1000 - 0x10ff] io
PCI: 00:04.2 20 * [0x1400 - 0x141f] io
PCI: 00:07.0 14 * [0x1420 - 0x143f] io
PCI: 00:04.1 20 * [0x1440 - 0x144f] io
PCI_DOMAIN: 0000 compute_resources_io: base: 1450 size: 1450 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 * [0x0 - 0xffffff] prefmem
PCI: 00:01.0 compute_resources_prefmem: base: 1000000 size: 1000000 align: 24 gran: 20 limit: ffffffff done
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 30 * [0x0 - 0x1ffff] mem
PCI: 01:00.0 18 * [0x20000 - 0x20fff] mem
PCI: 00:01.0 compute_resources_mem: base: 21000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem
PCI: 00:01.0 24 * [0x10000000 - 0x10ffffff] prefmem
PCI: 00:01.0 20 * [0x11000000 - 0x110fffff] mem
PCI: 00:07.0 18 * [0x11100000 - 0x111fffff] mem
PCI: 00:07.0 30 * [0x11200000 - 0x112fffff] mem
PCI: 00:06.0 30 * [0x11300000 - 0x1131ffff] mem
PCI: 00:06.0 14 * [0x11320000 - 0x11320fff] mem
PCI: 00:07.0 10 * [0x11321000 - 0x11321fff] prefmem
PCI_DOMAIN: 0000 compute_resources_mem: base: 11322000 size: 11322000 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:04.0
constrain_resources: PNP: 03f0.0
constrain_resources: PNP: 03f0.1
constrain_resources: PNP: 03f0.2
constrain_resources: PNP: 03f0.3
constrain_resources: PNP: 03f0.5
constrain_resources: PNP: 03f0.7
constrain_resources: PNP: 03f0.8
constrain_resources: PNP: 03f0.a
constrain_resources: PNP: 03f0.6
constrain_resources: PCI: 00:04.1
constrain_resources: PCI: 00:04.2
constrain_resources: PCI: 00:04.3
constrain_resources: PCI: 00:06.0
constrain_resources: PCI: 00:07.0
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 00001000 lim->limit 0000e3ff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 00000000 lim->limit ff7fffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:1450 align:12 gran:0 limit:e3ff
Assigned: PCI: 00:01.0 1c * [0x1000 - 0x1fff] io
Assigned: PCI: 00:06.0 10 * [0x2000 - 0x20ff] io
Assigned: PCI: 00:04.2 20 * [0x2400 - 0x241f] io
Assigned: PCI: 00:07.0 14 * [0x2420 - 0x243f] io
Assigned: PCI: 00:04.1 20 * [0x2440 - 0x244f] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 2450 size: 1450 align: 12 gran: 0 done
PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:e3ff
Assigned: PCI: 01:00.0 14 * [0x1000 - 0x10ff] io
PCI: 00:01.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:11322000 align:28 gran:0 limit:ff7fffff
Assigned: PCI: 00:00.0 10 * [0xe0000000 - 0xefffffff] prefmem
Assigned: PCI: 00:01.0 24 * [0xf0000000 - 0xf0ffffff] prefmem
Assigned: PCI: 00:01.0 20 * [0xf1000000 - 0xf10fffff] mem
Assigned: PCI: 00:07.0 18 * [0xf1100000 - 0xf11fffff] mem
Assigned: PCI: 00:07.0 30 * [0xf1200000 - 0xf12fffff] mem
Assigned: PCI: 00:06.0 30 * [0xf1300000 - 0xf131ffff] mem
Assigned: PCI: 00:06.0 14 * [0xf1320000 - 0xf1320fff] mem
Assigned: PCI: 00:07.0 10 * [0xf1321000 - 0xf1321fff] prefmem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f1322000 size: 11322000 align: 28 gran: 0 done
PCI: 00:01.0 allocate_resources_prefmem: base:f0000000 size:1000000 align:24 gran:20 limit:ff7fffff
Assigned: PCI: 01:00.0 10 * [0xf0000000 - 0xf0ffffff] prefmem
PCI: 00:01.0 allocate_resources_prefmem: next_base: f1000000 size: 1000000 align: 24 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:f1000000 size:100000 align:20 gran:20 limit:ff7fffff
Assigned: PCI: 01:00.0 30 * [0xf1000000 - 0xf101ffff] mem
Assigned: PCI: 01:00.0 18 * [0xf1020000 - 0xf1020fff] mem
PCI: 00:01.0 allocate_resources_mem: next_base: f1021000 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
Setting RAM size to 384 MB
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00f1000000 - 0x00f10fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x18 prefmem
PCI: 01:00.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:00.0 18 <- [0x00f1020000 - 0x00f1020fff] size 0x00001000 gran 0x0c mem
PCI: 01:00.0 30 <- [0x00f1000000 - 0x00f101ffff] size 0x00020000 gran 0x11 romem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:04.0 assign_resources, bus 0 link: 0
PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq
PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq
PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
ERROR: PNP: 03f0.1 74 drq size: 0x0000000001 not assigned
PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
ERROR: PNP: 03f0.7 60 io size: 0x0000000001 not assigned
ERROR: PNP: 03f0.7 62 io size: 0x0000000002 not assigned
ERROR: PNP: 03f0.7 70 irq size: 0x0000000001 not assigned
ERROR: PNP: 03f0.a 70 irq size: 0x0000000001 not assigned
ERROR: PNP: 03f0.6 60 io size: 0x0000000008 not assigned
ERROR: PNP: 03f0.6 70 irq size: 0x0000000001 not assigned
PCI: 00:04.0 assign_resources, bus 0 link: 0
PCI: 00:04.1 20 <- [0x0000002440 - 0x000000244f] size 0x00000010 gran 0x04 io
PCI: 00:04.2 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io
PCI: 00:06.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:06.0 14 <- [0x00f1320000 - 0x00f1320fff] size 0x00001000 gran 0x0c mem64
PCI: 00:06.0 30 <- [0x00f1300000 - 0x00f131ffff] size 0x00020000 gran 0x11 romem
PCI: 00:07.0 10 <- [0x00f1321000 - 0x00f1321fff] size 0x00001000 gran 0x0c prefmem
PCI: 00:07.0 14 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 io
PCI: 00:07.0 18 <- [0x00f1100000 - 0x00f11fffff] size 0x00100000 gran 0x14 mem
PCI: 00:07.0 30 <- [0x00f1200000 - 0x00f12fffff] size 0x00100000 gran 0x14 romem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
PCI_DOMAIN: 0000 resource base 1000 size 1450 align 12 gran 0 limit e3ff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base e0000000 size 11322000 align 28 gran 0 limit ff7fffff flags 40040200 index 10000100
PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
PCI_DOMAIN: 0000 resource base c0000 size 17f40000 align 0 gran 0 limit 0 flags e0004200 index b
PCI: 00:00.0
PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit ff7fffff flags 60001200 index 10
PCI: 00:01.0 child on link 0 PCI: 01:00.0
PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit e3ff flags 60080102 index 1c
PCI: 00:01.0 resource base f0000000 size 1000000 align 24 gran 20 limit ff7fffff flags 60081202 index 24
PCI: 00:01.0 resource base f1000000 size 100000 align 20 gran 20 limit ff7fffff flags 60080202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base f0000000 size 1000000 align 24 gran 24 limit ff7fffff flags 60001200 index 10
PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 14
PCI: 01:00.0 resource base f1020000 size 1000 align 12 gran 12 limit ff7fffff flags 60000200 index 18
PCI: 01:00.0 resource base f1000000 size 20000 align 17 gran 17 limit ff7fffff flags 60002200 index 30
PCI: 00:04.0 child on link 0 PNP: 03f0.0
PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
PNP: 03f0.0
PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
PNP: 03f0.1
PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 03f0.2
PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 03f0.3
PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 03f0.5
PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
PNP: 03f0.7
PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62
PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 03f0.8
PNP: 03f0.a
PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 03f0.6
PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PCI: 00:04.1
PCI: 00:04.1 resource base 2440 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20
PCI: 00:04.2
PCI: 00:04.2 resource base 2400 size 20 align 5 gran 5 limit e3ff flags 60000100 index 20
PCI: 00:04.3
PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
PCI: 00:06.0
PCI: 00:06.0 resource base 2000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 10
PCI: 00:06.0 resource base f1320000 size 1000 align 12 gran 12 limit ff7fffff flags 60000201 index 14
PCI: 00:06.0 resource base f1300000 size 20000 align 17 gran 17 limit ff7fffff flags 60002200 index 30
PCI: 00:07.0
PCI: 00:07.0 resource base f1321000 size 1000 align 12 gran 12 limit ff7fffff flags 60001200 index 10
PCI: 00:07.0 resource base 2420 size 20 align 5 gran 5 limit e3ff flags 60000100 index 14
PCI: 00:07.0 resource base f1100000 size 100000 align 20 gran 20 limit ff7fffff flags 60000200 index 18
PCI: 00:07.0 resource base f1200000 size 100000 align 20 gran 20 limit ff7fffff flags 60002200 index 30
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 008b
PCI: 00:01.0 cmd <- 07
PCI: 00:04.0 cmd <- 07
PCI: 00:04.1 cmd <- 01
PCI: 00:04.2 cmd <- 01
PCI: 00:04.3 cmd <- 01
PCI: 00:06.0 cmd <- 03
PCI: 00:07.0 cmd <- 03
PCI: 01:00.0 cmd <- 83
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor Intel device 673
CPU: family 06, model 07, stepping 03
microcode_info: sig = 0x00000673 pf=0x00000001 rev = 0x00000000
microcode updated to revision: 0000000e from revision 00000000
Configuring L2 cache... rdmsr(IA32_PLATFORM_ID) = 40210000:0
L2 Cache latency is 1
write_l2(4, 0)
L2 ECC Checking is enabled
L2 Physical Address Range is 4096M
Maximum cache mask is 20000
L2 Cache Mask is 4000
L2(2): 8 -> 8
size 512K... L2 Cache lines initialized
done.
Enabling cache
Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Setting variable MTRR 0, base: 0MB, range: 256MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 1, base: 256MB, range: 128MB, type WB
ADDRESS_MASK_HIGH=0xf
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Disabling local apic...done.
CPU #0 initialized
PCI: 00:00.0 init
Northbridge Init
PCI: 00:04.0 init
RTC Init
PCI: 00:04.1 init
IDE: Primary IDE interface: on
IDE: Secondary IDE interface: on
IDE: Access to legacy IDE ports: on
IDE: Primary IDE interface, drive 0: UDMA/33: off
IDE: Primary IDE interface, drive 1: UDMA/33: off
IDE: Secondary IDE interface, drive 0: UDMA/33: off
IDE: Secondary IDE interface, drive 1: UDMA/33: off
PCI: 00:04.2 init
PCI: 00:06.0 init
AIC7890 LVD termination = 1
AIC7890 SE termination = 1
PCI: 00:07.0 init
PCI: 01:00.0 init
PNP: 03f0.0 init
PNP: 03f0.1 init
PNP: 03f0.2 init
PNP: 03f0.3 init
PNP: 03f0.5 init
PNP: 03f0.7 init
PNP: 03f0.a init
PNP: 03f0.6 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:04.0: enabled 1
PNP: 03f0.0: enabled 1
PNP: 03f0.1: enabled 1
PNP: 03f0.2: enabled 1
PNP: 03f0.3: enabled 1
PNP: 03f0.5: enabled 1
PNP: 03f0.7: enabled 1
PNP: 03f0.8: enabled 1
PNP: 03f0.a: enabled 1
PCI: 00:04.1: enabled 1
PCI: 00:04.2: enabled 1
PCI: 00:04.3: enabled 1
PCI: 00:06.0: enabled 1
PCI: 00:07.0: enabled 1
PCI: 01:00.0: enabled 1
PNP: 03f0.6: enabled 1
CPU: 00: enabled 1
Initializing CBMEM area to 0x17ff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 17ff0200...ok
High Tables Base is 17ff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x17ff0400... done.
PIRQ table: 160 bytes.
Adding CBMEM entry as no. 3
ACPI: Writing ACPI tables at 17ff1400...
ACPI: * FACS
ACPI: * DSDT @ 17ff1540 Length 6a4
ACPI: * FADT
ACPI: added table 1/32, length now 40
ACPI: * MADT
ACPI: * SSDT
Found 1 CPU(s).
ACPI: added table 2/32, length now 44
ACPI: done.
ACPI tables: 2387 bytes.
Adding CBMEM entry as no. 4
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518 checksum 17df
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x17ffd000
rom_table_end = 0x17ffd000
Adjust low_table_end from 0x00000518 to 0x00001000
Adjust rom_table_end from 0x17ffd000 to 0x18000000
Adding high table area
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-0000000017feffff: RAM
3. 0000000017ff0000-0000000017ffffff: CONFIGURATION TABLES
4. 00000000ff800000-00000000ffffffff: RESERVED
Wrote coreboot table at: 17ffd000 - 17ffd1c0 checksum 9e74
coreboot table: 448 bytes.
Multiboot Information structure has been written.
0. FREE SPACE 17fff000 00001000
1. GDT 17ff0200 00000200
2. IRQ TABLE 17ff0400 00001000
3. ACPI 17ff1400 0000bc00
4. COREBOOT 17ffd000 00002000
Check CBFS header at fffffc9e
magic is 4f524243
Found CBFS header at fffffc9e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 2c48 + align -> fffc2c80
Check fallback/coreboot_ram
CBFS: follow chain: fffc2c80 + 38 + 18d68 + align -> fffdba40
Check fallback/payload
Got a payload
Loading segment from rom address 0xfffdba78
data (compression=1)
New segment dstaddr 0xe9590 memsize 0x16a70 srcaddr 0xfffdbab0 filesize 0xb6b1
(cleaned up) New segment addr 0xe9590 size 0x16a70 offset 0xfffdbab0 filesize 0xb6b1
Loading segment from rom address 0xfffdba94
Entry Point 0x000fc4fe
Loading Segment: addr: 0x00000000000e9590 memsz: 0x0000000000016a70 filesz: 0x000000000000b6b1
lb: [0x0000000000100000, 0x0000000000144000)
Post relocation: addr: 0x00000000000e9590 memsz: 0x0000000000016a70 filesz: 0x000000000000b6b1
using LZMA
[ 0x000e9590, 00100000, 0x00100000) <- fffdbab0
dest 000e9590, end 00100000, bouncebuffer 17f68000
Loaded segments
Jumping to boot code at fc4fe
entry = 0x000fc4fe
lb_start = 0x00100000
lb_size = 0x00044000
adjust = 0x17eac000
buffer = 0x17f68000
elf_boot_notes = 0x00136088
adjusted_boot_notes = 0x17fe2088
Start bios (version 0.6.1.2-20110102_010818-tonchan.tondebuurincentral.com)
Found mainboard ASUS P2B-LS
Found CBFS header at 0xfffffc9e
Ram Size=0x17ff0000 (0x0000000000000000 high)
CPU Mhz=601
No apic - only the main cpu is present.
Copying PIR from 0x17ff0400 to 0x000fd7f0
Copying ACPI RSDP from 0x17ff1400 to 0x000fd7d0
SMBIOS ptr=0x000fd7b0 table=0x17fefef0
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version 0.6.1.2-20110102_010818-tonchan.tondebuurincentral.com)
UHCI init on dev 00:04.2 (io=2400)
All threads complete.
Found 1 lpt ports
Found 2 serial ports
ATA controller 0 at 1f0/3f4/0 (irq 14 dev 21)
ATA controller 1 at 170/374/0 (irq 15 dev 21)
ata0-0: MAXTOR 6L080J4 ATA-5 Hard-Disk (74 GiBytes)
drive 0x000fd760: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=156355584
ata0-1: HL-DT-ST DVDRAM GSA-4120B ATAPI-5 DVD/CD
PS2 keyboard initialized
All threads complete.
Scan for option roms
Press F12 for boot menu.
ebda moved from 9fc00 to 9f400
Returned 61440 bytes of ZoneHigh
e820 map has 6 items:
0: 0000000000000000 - 000000000009f400 = 1
1: 000000000009f400 - 00000000000a0000 = 2
2: 00000000000f0000 - 0000000000100000 = 2
3: 0000000000100000 - 0000000017fef000 = 1
4: 0000000017fef000 - 0000000018000000 = 2
5: 00000000ff800000 - 0000000100000000 = 2
enter handle_19:
NULL
Booting from Floppy...
Boot failed: could not read the boot disk
enter handle_18:
NULL
Booting from DVD/CD...
Device reports MEDIUM NOT PRESENT
atapi_is_ready returned -1
Boot failed: Could not read from CDROM (code 0003)
enter handle_18:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
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