From devtadas at gmail.com Fri Jul 1 00:36:43 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Fri, 01 Jul 2011 01:36:43 +0300 Subject: [coreboot] Flashrom as a payload with usb flash drive support Message-ID: <1309473403.7857.10.camel@ts-laptop> Hi, this is for testing. Works for me with seabios. First optimize coreboot for your board, to get some space (remove microcode updates or sth, we need about 60 KB). Sorry haven't checked latest libpayload changes, so something might not work. I will write a blog post about this tomorrow. Thanks, Tadas Slotkus -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-coreboot-mods-for-flashrom-payload.patch Type: text/x-patch Size: 1530 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: filomods.diff Type: text/x-patch Size: 3200 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: flashrom_payload.diff Type: text/x-patch Size: 9326 bytes Desc: not available URL: From hamo.by at gmail.com Fri Jul 1 14:30:16 2011 From: hamo.by at gmail.com (Hamo) Date: Fri, 1 Jul 2011 20:30:16 +0800 Subject: [coreboot] [PATCH] porting coreboot to ARM mid-term evaluations Message-ID: Hi lists, Since it is too hard to get the detail information of Marvell CPU ( most of the information is covered under an NDA) , I decided to work on porting coreboot to Armltd Versatile PB. Most of its information is on the web of ARM ltd. and QEMU can emulate it so it is easy for me to test and use it. After applying those patches, we can now create a rom file only with bootblock. There is one problem when we add romstage to this rom file, I am trying to resolve this problem with the help of Patrick. Since no romstage and ramstage is in this rom file, no information will print to the screen. You can use the built-in gdb server in QEMU to trace the work of bootblock and walkcbfs. It is under vendor "Armltd" and mainboard "Versatile PB". Please test it and any comments are welcome. Thanks to you all for your kindly help. -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-xcompile-added-ARM-toolchain-support.patch Type: text/x-patch Size: 4879 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 0002-Makefile-added-support-for-the-new-xcompile-script.patch Type: text/x-patch Size: 1795 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 0003-CBFS-added-architecture-to-CBFS-master-header.patch Type: text/x-patch Size: 4707 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 0004-CBFS-fix-a-wrong-VERSION-define.patch Type: text/x-patch Size: 721 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 0005-cbfstool-added-support-for-ARM-architecture.patch Type: text/x-patch Size: 16038 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 0006-ARM-added-basic-layout-for-coreboot-ARM.patch Type: text/x-patch Size: 1461 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 0007-ARM-added-layout-for-Versatile-PB-board.patch Type: text/x-patch Size: 2704 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 0008-ARM-added-support-for-ARM926EJS-core.patch Type: text/x-patch Size: 6939 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 0009-Makefile-make-some-options-depending-on-ARCH_X86.patch Type: text/x-patch Size: 1048 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 0010-ARM-added-code-for-creating-rom-with-bootblock.patch Type: text/x-patch Size: 12408 bytes Desc: not available URL: From marcj303 at gmail.com Fri Jul 1 18:47:15 2011 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 1 Jul 2011 10:47:15 -0600 Subject: [coreboot] New patch to review: f65442a We use LDTSTOP# to trigger the FID/VID change on K8M890, because the FID/VID SMAF is blocked by not yet configured internal VGA. Workaround the errata #181. The memory controller is enabled later, nor the w In-Reply-To: <4E0C22A6.90700@assembler.cz> References: <4E0C22A6.90700@assembler.cz> Message-ID: 2011/6/30 Rudolf Marek : > I think that it is OK just this way, because the LDTSTOP is not used for > FID/VID changes, normal FID/VID SMAF is used instead. Right, This is a board/chipset thing and not normally used. Marc -- http://se-eng.com From marcj303 at gmail.com Fri Jul 1 18:58:37 2011 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 1 Jul 2011 10:58:37 -0600 Subject: [coreboot] [PATCH] porting coreboot to ARM mid-term evaluations In-Reply-To: References: Message-ID: On Fri, Jul 1, 2011 at 6:30 AM, Hamo wrote: > Hi lists, > Since it is too hard to get the detail information of Marvell CPU ( > most of the information is covered under an NDA) , I decided to work > on porting coreboot to Armltd Versatile PB. Most of its information is > on the web of ARM ltd. and QEMU can emulate it so it is easy for me to > test and use it. > After applying those patches, we can now create a rom file only with > bootblock. There is one problem when we add romstage to this rom file, > I am trying to resolve this problem with the help of Patrick. Since no > romstage and ramstage is in this rom file, no information will print > to the screen. You can use the built-in gdb server in QEMU to trace > the work of bootblock and walkcbfs. > > It is under vendor "Armltd" and mainboard "Versatile PB". Please test > it and any comments are welcome. > > Thanks to you all for your kindly help. Hi Hamo, Thanks for the patches. It looks like you have made some progress. i hope that it can continue. Marc -- http://se-eng.com From paulepanter at users.sourceforge.net Fri Jul 1 20:29:45 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Fri, 01 Jul 2011 20:29:45 +0200 Subject: [coreboot] Hackaton in Prague 2011 In-Reply-To: <4DC77D9C.8010804@assembler.cz> References: <4DC77D9C.8010804@assembler.cz> Message-ID: <1309544985.11759.16.camel@mattotaupa> Am Montag, den 09.05.2011, 07:37 +0200 schrieb Rudolf Marek: [?] > The Hackaton topics I have in mind: > > * make netconsole work on secondary PCI buses > * implement a gdb stub for coreboot > * fix the u-boot patches/submit them > * ... (need to get info from the attending guys) This event seems to be over. I hope you had fun. I am very interested in what you have done and achieved. Could some of the attendees write something up? That would be awesome. Thanks, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From patrick at georgi-clan.de Fri Jul 1 21:13:16 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Fri, 01 Jul 2011 21:13:16 +0200 Subject: [coreboot] looking for coreboot snapshots In-Reply-To: References: <7EB2278EA7F74D15BA617844722385DE@asusp67> <201106111109.p5BB9bQ6024208@mail2.student.tuwien.ac.at> Message-ID: <4E0E1C4C.2070805@georgi-clan.de> Am Donnerstag, 23. Juni 2011 03:20:05, Cristian M?gheru?an-Stanciu schrieb: > SetEnvIf Request_URI "\.gz$" no-gzip I had to disable it unconditionally for all of gitweb (REQUEST_URI matches the request url without the query string), but it looks okay for me now. Thanks, Patrick From gerrit at coreboot.org Fri Jul 1 23:16:31 2011 From: gerrit at coreboot.org (Cristian Măgherușan-Stanciu (cristi.magherusan@gmail.com)) Date: Fri, 1 Jul 2011 23:16:31 +0200 Subject: [coreboot] Patch set updated: 8de7fcd Workaround the errata #181. References: Message-ID: Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/69 -gerrit commit 8de7fcde0a1fcc5a56d5e8e03ed689253418c40c Author: Rudolf Marek Date: Wed Jun 29 23:59:13 2011 +0200 Workaround the errata #181. We use LDTSTOP# to trigger the FID/VID change on K8M890, because the FID/VID SMAF is blocked by not yet configured internal VGA. The memory controller is enabled later, nor the workaround makes any harm to non-affected CPUs. This update unbreaks compilation by declaring the tmp variable. Change-Id: Icf5d126b8c8cd9ece6af41d3129315a777c8cef2 Signed-off-by: Rudolf Marek Signed-off-by: Cristian M?gheru?an-Stanciu --- src/mainboard/asus/m2v-mx_se/romstage.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 580d8fa..9825e2b 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -74,10 +74,15 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define SB_VFSMAF 0 -/* this function might fail on some K8 CPUs with errata #181 */ static void ldtstop_sb(void) { print_debug("toggle LDTSTP#\n"); + + /* fix errata #181, disable DRAM controller it will get enabled later */ + u8 tmp = pci_read_config8(PCI_DEV(0, 0x18, 2), 0x94); + tmp |= (( 1 << 14) | (1 << 3)); + pci_write_config8(PCI_DEV(0, 0x18, 2), 0x94, tmp); + u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); reg = reg ^ (1 << 0); outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); From gerrit at coreboot.org Fri Jul 1 23:33:35 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 1 Jul 2011 23:33:35 +0200 Subject: [coreboot] Patch merged into master: 3b0c61f Relicense Makefile to match libpayload References: Message-ID: the following patch was just integrated into master: commit 3b0c61fd62a2775f54877d458539a516d9e0980c Author: Patrick Georgi Date: Thu Jun 30 15:48:57 2011 +0200 Relicense Makefile to match libpayload libpayload's license is more liberal than coreboot's. If we are to use the coreboot build system for libpayload (bringing a couple of new features to libpayload), we should adopt it for this shared part even if not strictly necessary. Change-Id: I1349616861e193b3e01407debbec3d82e09e72c2 Signed-off-by: Patrick Georgi See http://review.coreboot.org/70 for details. -gerrit From gerrit at coreboot.org Sat Jul 2 00:32:46 2011 From: gerrit at coreboot.org (Cristian Măgherușan-Stanciu (cristi.magherusan@gmail.com)) Date: Sat, 2 Jul 2011 00:32:46 +0200 Subject: [coreboot] Patch set updated: 2aa6b7f added a config option for ACPI debugging References: Message-ID: Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/36 -gerrit commit 2aa6b7fe12bd8ed6d4d3a8edcbc40b80dc746ba3 Author: Cristian M?gheru?an-Stanciu Date: Sat Jul 2 00:44:39 2011 +0300 added a config option for ACPI debugging Change-Id: Ie6296f5652196c6258aa6902d84dd86c17e224cb Signed-off-by: Cristian M?gheru?an-Stanciu --- src/Kconfig | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7e6214a..7b4f487 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -651,6 +651,23 @@ config DEBUG_MALLOC If unsure, say N. endif +config DEBUG_ACPI + def_bool n + +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. +if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 +config DEBUG_ACPI + bool "Output verbose ACPI debug messages" + default n + help + This option enables additional ACPI related debug messages. + + Note: This option will slightly increase the size of the coreboot image. + + If unsure, say N. +endif + config REALMODE_DEBUG def_bool n depends on PCI_OPTION_ROM_RUN_REALMODE From gerrit at coreboot.org Sat Jul 2 00:36:23 2011 From: gerrit at coreboot.org (Cristian Măgherușan-Stanciu (cristi.magherusan@gmail.com)) Date: Sat, 2 Jul 2011 00:36:23 +0200 Subject: [coreboot] New patch to review: 0362d89 whitespace-only changes in acpi.c, replaced spaces with tabs References: Message-ID: Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/74 -gerrit commit 0362d89266df43b756ee8a7c9d008ef71ae73011 Author: Cristian M?gheru?an-Stanciu Date: Sat Jul 2 00:57:07 2011 +0300 whitespace-only changes in acpi.c, replaced spaces with tabs Change-Id: Ibd598813bec0c93d77afbce8aee330498afbe5f6 Signed-off-by: Cristian M?gheru?an-Stanciu --- src/arch/x86/boot/acpi.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 957ec45..caf860e 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -69,7 +69,7 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) if (i >= entries_num) { printk(BIOS_ERR, "ACPI: Error: Could not add ACPI table, " - "too many tables.\n"); + "too many tables.\n"); return; } @@ -93,20 +93,20 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) /* Fix XSDT length. */ xsdt->header.length = sizeof(acpi_header_t) + - (sizeof(u64) * (i + 1)); + (sizeof(u64) * (i + 1)); /* Re-calculate checksum. */ xsdt->header.checksum = 0; xsdt->header.checksum = acpi_checksum((u8 *)xsdt, - xsdt->header.length); + xsdt->header.length); } printk(BIOS_DEBUG, "ACPI: added table %d/%d, length now %d\n", - i + 1, entries_num, rsdt->header.length); + i + 1, entries_num, rsdt->header.length); } int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end) + u16 seg_nr, u8 start, u8 end) { mmconfig->base_address = base; mmconfig->base_reserved = 0; @@ -135,7 +135,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current) for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { continue; } if (!cpu->enabled) @@ -149,7 +149,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current) } int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, - u32 gsi_base) + u32 gsi_base) { ioapic->type = 1; /* I/O APIC structure */ ioapic->length = sizeof(acpi_madt_ioapic_t); @@ -175,7 +175,7 @@ int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, } int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, - u16 flags, u8 lint) + u16 flags, u8 lint) { lapic_nmi->type = 4; /* Local APIC NMI structure */ lapic_nmi->length = sizeof(acpi_madt_lapic_nmi_t); @@ -287,7 +287,7 @@ int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic) } int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, - u32 flags) + u32 flags) { mem->type = 1; /* Memory affinity structure */ mem->length = sizeof(acpi_srat_mem_t); From gerrit at coreboot.org Sat Jul 2 00:36:30 2011 From: gerrit at coreboot.org (Cristian Măgherușan-Stanciu (cristi.magherusan@gmail.com)) Date: Sat, 2 Jul 2011 00:36:30 +0200 Subject: [coreboot] New patch to review: f137e6e added support for multiple vendors in the HPET code References: Message-ID: Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/75 -gerrit commit f137e6ef81c97589b7c94b4aea56fd1565c282e4 Author: Cristian M?gheru?an-Stanciu Date: Sat Jul 2 01:03:50 2011 +0300 added support for multiple vendors in the HPET code Change-Id: Id13709329c8cc2b3acb55b7ec78fc53c805543eb Signed-off-by: Cristian M?gheru?an-Stanciu --- src/arch/x86/boot/acpi.c | 15 +++++++++++++-- 1 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index caf860e..8be7437 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -376,9 +376,20 @@ void acpi_create_hpet(acpi_hpet_t *hpet) addr->addrl = HPET_ADDR & 0xffffffff; addr->addrh = HPET_ADDR >> 32; - hpet->id = 0x102282a0; /* AMD! FIXME */ + /* XXX: Add other vendors */ +#if CONFIG_VENDOR_INTEL + hpet->id = 0x8086a201; + hpet->min_tick = 0x80; +#endif +#if CONFIG_VENDOR_AMD + hpet->id = 0x102282a0; + hpet->min_tick = 0x1000; +#endif +#if CONFIG_VENDOR_VIA + hpet->id = 0x11068201; + hpet->min_tick = 0x90; +#endif hpet->number = 0; - hpet->min_tick = 4096; header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } From gerrit at coreboot.org Sat Jul 2 00:36:32 2011 From: gerrit at coreboot.org (Cristian Măgherușan-Stanciu (cristi.magherusan@gmail.com)) Date: Sat, 2 Jul 2011 00:36:32 +0200 Subject: [coreboot] New patch to review: a055ba5 implemented functions for writing most of the ACPI tables References: Message-ID: Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/76 -gerrit commit a055ba5416303da0f0cc8f728c36b3a5c8a5ea07 Author: Cristian M?gheru?an-Stanciu Date: Sat Jul 2 01:07:35 2011 +0300 implemented functions for writing most of the ACPI tables Change-Id: Ib84c845d3f004708a90fd3122485f00b7d20fdbc Signed-off-by: Cristian M?gheru?an-Stanciu --- src/arch/x86/boot/acpi.c | 242 ++++++++++++++++++++++++++++++++++++- src/arch/x86/include/arch/acpi.h | 16 +++- 2 files changed, 250 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 8be7437..20f2ddf 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -16,13 +16,15 @@ */ /* - * Each system port implementing ACPI has to provide two functions: - * - * write_acpi_tables() - * acpi_dump_apics() - * - * See Kontron 986LCD-M port for a good example of an ACPI implementation - * in coreboot. + * Currently each system port implementing ACPI has to provide the following functions: + * - acpi_fill_mcfg() + * - acpi_fill_madt() + * - acpi_fill_slit() + * - acpi_fill_srat() + * Optional + * - acpi_fill_ssdt_generator() + * - acpi_patch_dsdt() + * - acpi_dmi_workaround() */ #include @@ -249,6 +251,18 @@ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator( return current; } +/* stub functions that might be implemented in the mainboard code, if needed */ +void __attribute__((weak)) acpi_patch_dsdt( + acpi_header_t *dsdt, unsigned long *current) +{ +} + +void __attribute__((weak)) acpi_dmi_workaround(unsigned long *current) +{ +} + + + void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); @@ -476,6 +490,220 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt) rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); } + + +void acpi_write_dsdt(acpi_header_t *dsdt, const unsigned char AmlCode[], unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", *current); + dsdt = (acpi_header_t *) *current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + *current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + *current = ALIGN(*current, 64); + + acpi_patch_dsdt(dsdt, current); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); +} + +void acpi_write_facs(acpi_facs_t *facs, unsigned long *current) +{ + /* FACS */ // it needs 64 bit alignment + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", *current); + facs = (acpi_facs_t *) *current; // it will be used by fadt + *current += sizeof(acpi_facs_t); + *current = ALIGN(*current, 64); + acpi_create_facs(facs); +} + + +void acpi_write_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, acpi_header_t *dsdt, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", *current); + fadt = (acpi_fadt_t *) *current; + *current += sizeof(acpi_fadt_t); + *current = ALIGN(*current, 64); + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); +} + +void acpi_write_hpet(acpi_hpet_t *hpet, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", *current); + hpet = (acpi_hpet_t *) *current; + *current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + *current = ALIGN(*current, 64); + acpi_add_table(rsdp, hpet); +} + +void acpi_write_madt(acpi_madt_t *madt, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n", *current); + madt = (acpi_madt_t *) *current; + acpi_create_madt(madt); + *current += madt->header.length; + *current = ALIGN(*current, 64); + acpi_add_table(rsdp, madt); +} + +void acpi_write_srat(acpi_srat_t *srat, acpi_rsdp_t *rsdp, unsigned long *current) +{ + *current = ALIGN(*current, 64); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", *current); + srat = (acpi_srat_t *) *current; + acpi_create_srat(srat); + *current += srat->header.length; + acpi_add_table(rsdp, srat); +} + +void acpi_write_slit(acpi_slit_t *slit, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", *current); + slit = (acpi_slit_t *) *current; + acpi_create_slit(slit); + *current += slit->header.length; + *current = ALIGN(*current, 64); + acpi_add_table(rsdp, slit); +} +void acpi_write_mcfg(acpi_mcfg_t *mcfg, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * MCFG at %lx\n", *current); + mcfg = (acpi_mcfg_t *) *current; + acpi_create_mcfg(mcfg); + *current += mcfg->header.length; + *current = ALIGN(*current, 64); + acpi_add_table(rsdp, mcfg); +} + +#if CONFIG_HAVE_ACPI_SLIC +void acpi_write_slic(acpi_header_t *slic, acpi_rsdp_t *rsdp, unsigned long *current) + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)*current; + *current += acpi_create_slic(*current); + *current = ALIGN(*current, 64); + acpi_add_table(rsdp, slic); +#endif + + +void acpi_write_ssdt_generated(acpi_header_t *ssdt, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)*current; + + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + *current += ssdt->length; + acpi_add_table(rsdp, ssdt); + *current = ALIGN(*current, 64); +} + + +#if CONFIG_DEBUG_ACPI == 1 +static void dump_mem(void *start, void *end) +{ + int i; + printk(BIOS_DEBUG,"dump_mem:"); + for (i = (unsigned int)start; i < (unsigned int)end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", (unsigned int)i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + printk(BIOS_DEBUG,"\n"); +} +#endif + +unsigned long acpi_write_tables(unsigned long start, const unsigned char AmlCode[]) +{ + unsigned long current; + acpi_rsdp_t *rsdp = NULL; + acpi_srat_t *srat = NULL; + acpi_rsdt_t *rsdt = NULL; + acpi_mcfg_t *mcfg = NULL; + acpi_hpet_t *hpet = NULL; + acpi_madt_t *madt = NULL; + acpi_fadt_t *fadt = NULL; + acpi_facs_t *facs = NULL; + acpi_xsdt_t *xsdt = NULL; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic = NULL; +#endif + acpi_slit_t *slit = NULL; + acpi_header_t *ssdt = NULL; + acpi_header_t *dsdt = NULL; + + /* Align ACPI tables to 16 bytes */ + start = ALIGN(start, 16); + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + + current = ALIGN(current, 64); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + current = ALIGN(current, 64); + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + acpi_write_dsdt(dsdt, AmlCode , ¤t); + + acpi_write_facs(facs, ¤t); + acpi_write_fadt(fadt, facs, dsdt, rsdp, ¤t); + acpi_write_hpet(hpet, rsdp, ¤t); + + acpi_write_madt(madt, rsdp, ¤t); + + acpi_write_mcfg(mcfg, rsdp, ¤t); + + acpi_write_srat(srat, rsdp, ¤t); + acpi_write_slit(slit, rsdp, ¤t); + + + acpi_write_ssdt_generated(ssdt, rsdp, ¤t); + + printk(BIOS_DEBUG, "current = %lx\n", current); + + acpi_dmi_workaround(¤t); + +#if CONFIG_DEBUG_ACPI == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} + #if CONFIG_HAVE_ACPI_RESUME == 1 void suspend_resume(void) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 030745d..09de3a6 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -357,8 +357,9 @@ typedef struct acpi_ecdt { u8 ec_id[]; /* EC ID */ } __attribute__ ((packed)) acpi_ecdt_t; -/* These are implemented by the target port or north/southbridge. */ +/* This is implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); + unsigned long acpi_fill_madt(unsigned long current); unsigned long acpi_fill_mcfg(unsigned long current); unsigned long acpi_fill_srat(unsigned long current); @@ -411,6 +412,19 @@ unsigned long acpi_create_slic(unsigned long current); void acpi_write_rsdt(acpi_rsdt_t *rsdt); void acpi_write_xsdt(acpi_xsdt_t *xsdt); void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt); +void acpi_write_dsdt(acpi_header_t *dsdt, const unsigned char AmlCode[], unsigned long *current); +void acpi_patch_dsdt(acpi_header_t *dsdt, unsigned long *current); +void acpi_dmi_workaround(unsigned long *current); + +void acpi_write_facs(acpi_facs_t *facs, unsigned long *current); +void acpi_write_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, acpi_header_t *dsdt, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_hpet(acpi_hpet_t *hpet, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_madt(acpi_madt_t *madt, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_srat(acpi_srat_t *srat, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_slit(acpi_slit_t *slit, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_ssdt_generated(acpi_header_t *ssdt, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_mcfg(acpi_mcfg_t *mcfg, acpi_rsdp_t *rsdp, unsigned long *current); +unsigned long acpi_write_tables(unsigned long start, const unsigned char AmlCode[]); #if CONFIG_HAVE_ACPI_RESUME /* 0 = S0, 1 = S1 ...*/ From gerrit at coreboot.org Sat Jul 2 00:36:32 2011 From: gerrit at coreboot.org (Cristian Măgherușan-Stanciu (cristi.magherusan@gmail.com)) Date: Sat, 2 Jul 2011 00:36:32 +0200 Subject: [coreboot] New patch to review: 143687d usage example of the simplified ACPI code References: Message-ID: Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/77 -gerrit commit 143687d71bb7c17e7192d6cb63b2e19cbd09db11 Author: Cristian M?gheru?an-Stanciu Date: Sat Jul 2 01:11:11 2011 +0300 usage example of the simplified ACPI code Change-Id: I7dcbf14a327fb347973b4cd9b7b3a4d6cdb31d7f Signed-off-by: Cristian M?gheru?an-Stanciu --- src/mainboard/asus/m2v-mx_se/acpi_tables.c | 100 +-------------- src/mainboard/lenovo/t60/acpi_tables.c | 194 +++------------------------- 2 files changed, 20 insertions(+), 274 deletions(-) diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c index 73e3768..1471ad9 100644 --- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c +++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c @@ -94,103 +94,5 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta unsigned long write_acpi_tables(unsigned long start) { - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = (start + 0x0f) & -0x10; - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, "DYNADATA"); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; + return acpi_write_tables(start, AmlCode); } diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 3742c20..4056e75 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -32,9 +32,6 @@ #include "dmi.h" extern const unsigned char AmlCode[]; -#if CONFIG_HAVE_ACPI_SLIC -unsigned long acpi_create_slic(unsigned long current); -#endif #include "southbridge/intel/i82801gx/nvs.h" static void acpi_create_gnvs(global_nvs_t *gnvs) @@ -56,38 +53,6 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[4] = 0x00000005; } -static void acpi_create_intel_hpet(acpi_hpet_t * hpet) -{ -#define HPET_ADDR 0xfed00000ULL - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = 1; - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = HPET_ADDR & 0xffffffff; - addr->addrh = HPET_ADDR >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ @@ -136,129 +101,31 @@ unsigned long acpi_fill_srat(unsigned long current) void smm_setup_structures(void *gnvs, void *tcg, void *smi1); -#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) -unsigned long write_acpi_tables(unsigned long start) + +void acpi_patch_dsdt(acpi_header_t *dsdt, unsigned long *current) { - unsigned long current; int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; -#if CONFIG_HAVE_ACPI_SLIC - acpi_header_t *slic; -#endif - acpi_header_t *ssdt; - acpi_header_t *dsdt; void *gnvs; - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - /* - * We explicitly add these tables later on: - */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - /* Fix up global NVS region for SMI handler. The GNVS region lives - * in the (high) table area. The low memory map looks like this: - * - * 0x00000000 - 0x000003ff Real Mode IVT - * 0x00000020 - 0x0000019c Low MP Table (XXX conflict?) - * 0x00000400 - 0x000004ff BDA (somewhat unused) - * 0x00000500 - 0x0000052f Moved GDT - * 0x00000530 - 0x00000b64 coreboot table - * 0x0007c000 - 0x0007dfff OS boot sector (unused?) - * 0x0007e000 - 0x0007ffff free to use (so no good for acpi+smi) - * 0x00080000 - 0x0009fbff usable ram - * 0x0009fc00 - 0x0009ffff EBDA (unused?) - * 0x000a0000 - 0x000bffff VGA memory - * 0x000c0000 - 0x000cffff VGA option rom - * 0x000d0000 - 0x000dffff free for other option roms? - * 0x000e0000 - 0x000fffff SeaBIOS? (conflict with low tables:) - * 0x000f0000 - 0x000f03ff PIRQ table - * 0x000f0400 - 0x000f66?? ACPI tables - * 0x000f66?? - 0x000f???? DMI tables - */ - - ALIGN_CURRENT; + *current = ALIGN(*current, 64); /* Pack GNVS into the ACPI table area */ for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current); - *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)*current); + *(u32*)(((u32)dsdt) + i) = *current; // 0x92 bytes break; } } /* And fill it */ - acpi_create_gnvs((global_nvs_t *)current); + acpi_create_gnvs((global_nvs_t *)*current); /* Keep pointer around */ - gnvs = (void *)current; + gnvs = (void *)*current; - current += 0x100; - ALIGN_CURRENT; + *current += 0x100; + *current = ALIGN(*current, 64); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); @@ -266,48 +133,25 @@ unsigned long write_acpi_tables(unsigned long start) /* We patched up the DSDT, so we need to recalculate the checksum */ dsdt->checksum = 0; dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); +} - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - -#if CONFIG_HAVE_ACPI_SLIC - printk(BIOS_DEBUG, "ACPI: * SLIC\n"); - slic = (acpi_header_t *)current; - current += acpi_create_slic(current); - ALIGN_CURRENT; - acpi_add_table(rsdp, slic); -#endif - - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, "COREBOOT"); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "current = %lx\n", current); - +void acpi_dmi_workaround(unsigned long *current) +{ printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); #if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; + memcpy((void *)*current, dmi_table, DMI_TABLE_SIZE); + *current += DMI_TABLE_SIZE; + *current = ALIGN(*current, 64); #endif - printk(BIOS_INFO, "ACPI: done.\n"); +} +unsigned long write_acpi_tables(unsigned long start) +{ /* Enable Dummy DCC ON# for DVI */ printk(BIOS_DEBUG, "Laptop handling...\n"); outb(inb(0x60f) & ~(1 << 5), 0x60f); - return current; + return acpi_write_tables(start, AmlCode); } From gerrit at coreboot.org Sat Jul 2 00:36:47 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 2 Jul 2011 00:36:47 +0200 Subject: [coreboot] New patch to review: 626e5e0 Un-perl commit-msg hook References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/78 -gerrit commit 626e5e0018544d599c1c5d7d6797463f4803b756 Author: Patrick Georgi Date: Sat Jul 2 00:35:02 2011 +0200 Un-perl commit-msg hook To simplify installation on mingw a bit (even though git remains a pain), drop the perl dependency the commit-msg hook introduced to the coreboot development environment. It's replaced by awk which we use elsewhere already (and is a more lightweight utility in any case) Change-Id: I67adfe1ec43c898735d4bae4819ceb53e83c303b Signed-off-by: Patrick Georgi --- util/gitconfig/commit-msg | 61 ++++++++++++++++++-------------------------- 1 files changed, 25 insertions(+), 36 deletions(-) diff --git a/util/gitconfig/commit-msg b/util/gitconfig/commit-msg index 789bad3..4c80420 100755 --- a/util/gitconfig/commit-msg +++ b/util/gitconfig/commit-msg @@ -43,46 +43,35 @@ add_ChangeId() { fi id=`_gen_ChangeId` - perl -e ' - $MSG = shift; - $id = shift; - $CHANGE_ID_AFTER = shift; + T=`mktemp` + cat "$MSG" | awk ' + !/^[a-zA-Z0-9-]+:/ { + print $0; + next; + }; - undef $/; - open(I, $MSG); $_ = ; close I; - s|^diff --git a/.*||ms; - s|^#.*$||mg; - exit unless $_; + { + if (lines != "") { + lines = lines "\n"; + }; + lines = lines $0 + }; - @message = split /\n/; - $haveFooter = 0; - $startFooter = @message; - for($line = @message - 1; $line >= 0; $line--) { - $_ = $message[$line]; - - if (/^[a-zA-Z0-9-]+:/ && !m,^[a-z0-9-]+://,) { - $haveFooter++; - next; - } - next if /^[ []/; - $startFooter = $line if ($haveFooter && /^\r?$/); - last; + END { + split(lines, footer, "\n"); + numlines=length(footer); + pre=1; + for (line = 1; line <= numlines; line++) { + if (pre && match(footer[line], "('$CHANGE_ID_AFTER'):") != 1) { + pre=0; + print "Change-Id: I'$id'"; + }; + print footer[line]; } - - @footer = @message[$startFooter+1.. at message]; - @message = @message[0..$startFooter]; - push(@footer, "") unless @footer; - - for ($line = 0; $line < @footer; $line++) { - $_ = $footer[$line]; - next if /^($CHANGE_ID_AFTER):/i; - last; + if (pre) { + print "Change-Id: I'$id'"; } - splice(@footer, $line, 0, "Change-Id: I$id"); - - $_ = join("\n", @message, @footer); - open(O, ">$MSG"); print O; close O; - ' "$MSG" "$id" "$CHANGE_ID_AFTER" + }' > $T && mv $T "$MSG" || rm -f $T } _gen_ChangeIdInput() { echo "tree `git write-tree`" From gerrit at coreboot.org Sat Jul 2 00:38:10 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 2 Jul 2011 00:38:10 +0200 Subject: [coreboot] New patch to review: 4345556 Fixes to the libpayload build system References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/79 -gerrit commit 434555659991021344fcebd7fcef910c3ae78ae5 Author: Patrick Georgi Date: Sat Jul 2 00:29:09 2011 +0200 Fixes to the libpayload build system - its Makefile is part of the libpayload project - fix conversion bug in powerpc's Makefile.inc Change-Id: I84f2da092c3733ea7d0f232cb3768078cf13dfd5 Signed-off-by: Patrick Georgi --- payloads/libpayload/Makefile | 2 +- payloads/libpayload/arch/powerpc/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index b976baa..667822d 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -1,5 +1,5 @@ ## -## This file is part of the coreboot project. +## This file is part of the libpayload project. ## ## Copyright (C) 2008 Advanced Micro Devices, Inc. ## Copyright (C) 2008 Uwe Hermann diff --git a/payloads/libpayload/arch/powerpc/Makefile.inc b/payloads/libpayload/arch/powerpc/Makefile.inc index bfbec27..44ce431 100644 --- a/payloads/libpayload/arch/powerpc/Makefile.inc +++ b/payloads/libpayload/arch/powerpc/Makefile.inc @@ -29,6 +29,6 @@ head.o-y := head.S libc-y += main.c sysinfo.c -libc-y += timer.c coreboot.c util.S.c +libc-y += timer.c coreboot.c util.S libc-y += exec.S virtual.c From gerrit at coreboot.org Sat Jul 2 00:49:54 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 2 Jul 2011 00:49:54 +0200 Subject: [coreboot] Patch merged into master: 2aa6b7f added a config option for ACPI debugging References: Message-ID: the following patch was just integrated into master: commit 2aa6b7fe12bd8ed6d4d3a8edcbc40b80dc746ba3 Author: Cristian M??gheru??an-Stanciu Date: Sat Jul 2 00:44:39 2011 +0300 added a config option for ACPI debugging Change-Id: Ie6296f5652196c6258aa6902d84dd86c17e224cb Signed-off-by: Cristian M??gheru??an-Stanciu See http://review.coreboot.org/36 for details. -gerrit From scott at notabs.org Sat Jul 2 05:12:03 2011 From: scott at notabs.org (Scott Duplichan) Date: Fri, 1 Jul 2011 22:12:03 -0500 Subject: [coreboot] looking for coreboot snapshots In-Reply-To: <4E0E1C4C.2070805@georgi-clan.de> References: <7EB2278EA7F74D15BA617844722385DE@asusp67><201106111109.p5BB9bQ6024208@mail2.student.tuwien.ac.at> <4E0E1C4C.2070805@georgi-clan.de> Message-ID: <5B0C8F796F884EAA91B58DBD1C14E602@asusp67> Patrick Georgi wrote: ]Am Donnerstag, 23. Juni 2011 03:20:05, Cristian M?gheru?an-Stanciu ]schrieb: ]> SetEnvIf Request_URI "\.gz$" no-gzip ]I had to disable it unconditionally for all of gitweb (REQUEST_URI ]matches the request url without the query string), but it looks okay ]for me now. ] ]Thanks, ]Patrick Hello Patrick, 7-zip is happy now. Thanks for making the change, and thanks to Cristi and Thomas for figuring out details. Thanks, Scott From gerrit at coreboot.org Sat Jul 2 15:15:37 2011 From: gerrit at coreboot.org (Cristian Măgherușan-Stanciu (cristi.magherusan@gmail.com)) Date: Sat, 2 Jul 2011 15:15:37 +0200 Subject: [coreboot] Patch set updated: 93c64f0 Implemented functions for writing most of the ACPI tables References: Message-ID: Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/76 -gerrit commit 93c64f021d22ff5629de9d3c082e3715099d5f23 Author: Cristian M?gheru?an-Stanciu Date: Sat Jul 2 01:07:35 2011 +0300 Implemented functions for writing most of the ACPI tables Fixed compilation failures in the SILC code, but Intel xe7501devkit still fails to compile due to incomplete southbrige code that does not implement FADT generation as of yet. Change-Id: Ib84c845d3f004708a90fd3122485f00b7d20fdbc Signed-off-by: Cristian M?gheru?an-Stanciu --- src/arch/x86/boot/acpi.c | 248 ++++++++++++++++++++++++++++++++++++- src/arch/x86/include/arch/acpi.h | 19 +++- 2 files changed, 258 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 8be7437..6a17395 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -16,13 +16,15 @@ */ /* - * Each system port implementing ACPI has to provide two functions: - * - * write_acpi_tables() - * acpi_dump_apics() - * - * See Kontron 986LCD-M port for a good example of an ACPI implementation - * in coreboot. + * Currently each system port implementing ACPI has to provide the following functions: + * - acpi_fill_mcfg() + * - acpi_fill_madt() + * - acpi_fill_slit() + * - acpi_fill_srat() + * Optional + * - acpi_fill_ssdt_generator() + * - acpi_patch_dsdt() + * - acpi_dmi_workaround() */ #include @@ -249,6 +251,18 @@ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator( return current; } +/* stub functions that might be implemented in the mainboard code, if needed */ +void __attribute__((weak)) acpi_patch_dsdt( + acpi_header_t *dsdt, unsigned long *current) +{ +} + +void __attribute__((weak)) acpi_dmi_workaround(unsigned long *current) +{ +} + + + void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); @@ -476,6 +490,226 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt) rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); } + + +void acpi_write_dsdt(acpi_header_t *dsdt, const unsigned char AmlCode[], unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", *current); + dsdt = (acpi_header_t *) *current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + *current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + *current = ALIGN(*current, 64); + + acpi_patch_dsdt(dsdt, current); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); +} + +void acpi_write_facs(acpi_facs_t *facs, unsigned long *current) +{ + /* FACS */ // it needs 64 bit alignment + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", *current); + facs = (acpi_facs_t *) *current; // it will be used by fadt + *current += sizeof(acpi_facs_t); + *current = ALIGN(*current, 64); + acpi_create_facs(facs); +} + + +void acpi_write_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, acpi_header_t *dsdt, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", *current); + fadt = (acpi_fadt_t *) *current; + *current += sizeof(acpi_fadt_t); + *current = ALIGN(*current, 64); + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); +} + +void acpi_write_hpet(acpi_hpet_t *hpet, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", *current); + hpet = (acpi_hpet_t *) *current; + *current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + *current = ALIGN(*current, 64); + acpi_add_table(rsdp, hpet); +} + +void acpi_write_madt(acpi_madt_t *madt, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n", *current); + madt = (acpi_madt_t *) *current; + acpi_create_madt(madt); + *current += madt->header.length; + *current = ALIGN(*current, 64); + acpi_add_table(rsdp, madt); +} + +void acpi_write_srat(acpi_srat_t *srat, acpi_rsdp_t *rsdp, unsigned long *current) +{ + *current = ALIGN(*current, 64); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", *current); + srat = (acpi_srat_t *) *current; + acpi_create_srat(srat); + *current += srat->header.length; + acpi_add_table(rsdp, srat); +} + +void acpi_write_slit(acpi_slit_t *slit, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", *current); + slit = (acpi_slit_t *) *current; + acpi_create_slit(slit); + *current += slit->header.length; + *current = ALIGN(*current, 64); + acpi_add_table(rsdp, slit); +} +void acpi_write_mcfg(acpi_mcfg_t *mcfg, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * MCFG at %lx\n", *current); + mcfg = (acpi_mcfg_t *) *current; + acpi_create_mcfg(mcfg); + *current += mcfg->header.length; + *current = ALIGN(*current, 64); + acpi_add_table(rsdp, mcfg); +} + +#if CONFIG_HAVE_ACPI_SLIC +void acpi_write_slic(acpi_header_t *slic, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)*current; + *current += acpi_create_slic(*current); + *current = ALIGN(*current, 64); + acpi_add_table(rsdp, slic); +} +#endif + + +void acpi_write_ssdt_generated(acpi_header_t *ssdt, acpi_rsdp_t *rsdp, unsigned long *current) +{ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)*current; + + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + *current += ssdt->length; + acpi_add_table(rsdp, ssdt); + *current = ALIGN(*current, 64); +} + + +#if CONFIG_DEBUG_ACPI == 1 +static void dump_mem(void *start, void *end) +{ + int i; + printk(BIOS_DEBUG,"dump_mem:"); + for (i = (unsigned int)start; i < (unsigned int)end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", (unsigned int)i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + printk(BIOS_DEBUG,"\n"); +} +#endif + +unsigned long acpi_write_tables(unsigned long start, const unsigned char AmlCode[]) +{ + unsigned long current; + acpi_rsdp_t *rsdp = NULL; + acpi_srat_t *srat = NULL; + acpi_rsdt_t *rsdt = NULL; + acpi_mcfg_t *mcfg = NULL; + acpi_hpet_t *hpet = NULL; + acpi_madt_t *madt = NULL; + acpi_fadt_t *fadt = NULL; + acpi_facs_t *facs = NULL; + acpi_xsdt_t *xsdt = NULL; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic = NULL; +#endif + acpi_slit_t *slit = NULL; + acpi_header_t *ssdt = NULL; + acpi_header_t *dsdt = NULL; + + /* Align ACPI tables to 16 bytes */ + start = ALIGN(start, 16); + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + + current = ALIGN(current, 64); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + current = ALIGN(current, 64); + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + acpi_write_dsdt(dsdt, AmlCode , ¤t); + + acpi_write_facs(facs, ¤t); + acpi_write_fadt(fadt, facs, dsdt, rsdp, ¤t); + acpi_write_hpet(hpet, rsdp, ¤t); + + acpi_write_madt(madt, rsdp, ¤t); + + acpi_write_mcfg(mcfg, rsdp, ¤t); + + acpi_write_srat(srat, rsdp, ¤t); + + acpi_write_slit(slit, rsdp, ¤t); + +#if CONFIG_HAVE_ACPI_SLIC + acpi_write_slic(slic, rsdp, ¤t); +#endif + + acpi_write_ssdt_generated(ssdt, rsdp, ¤t); + + printk(BIOS_DEBUG, "current = %lx\n", current); + + acpi_dmi_workaround(¤t); + +#if CONFIG_DEBUG_ACPI == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} + #if CONFIG_HAVE_ACPI_RESUME == 1 void suspend_resume(void) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 030745d..01f4b12 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -357,14 +357,15 @@ typedef struct acpi_ecdt { u8 ec_id[]; /* EC ID */ } __attribute__ ((packed)) acpi_ecdt_t; -/* These are implemented by the target port or north/southbridge. */ +/* This is implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); + unsigned long acpi_fill_madt(unsigned long current); unsigned long acpi_fill_mcfg(unsigned long current); unsigned long acpi_fill_srat(unsigned long current); unsigned long acpi_fill_slit(unsigned long current); unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id); + const char *oem_table_id); void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt); @@ -406,11 +407,25 @@ void acpi_create_facs(acpi_facs_t *facs); #if CONFIG_HAVE_ACPI_SLIC unsigned long acpi_create_slic(unsigned long current); +void acpi_write_slic(acpi_header_t *slic, acpi_rsdp_t *rsdp, unsigned long *current); #endif void acpi_write_rsdt(acpi_rsdt_t *rsdt); void acpi_write_xsdt(acpi_xsdt_t *xsdt); void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt); +void acpi_write_dsdt(acpi_header_t *dsdt, const unsigned char AmlCode[], unsigned long *current); +void acpi_patch_dsdt(acpi_header_t *dsdt, unsigned long *current); +void acpi_dmi_workaround(unsigned long *current); + +void acpi_write_facs(acpi_facs_t *facs, unsigned long *current); +void acpi_write_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, acpi_header_t *dsdt, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_hpet(acpi_hpet_t *hpet, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_madt(acpi_madt_t *madt, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_srat(acpi_srat_t *srat, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_slit(acpi_slit_t *slit, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_ssdt_generated(acpi_header_t *ssdt, acpi_rsdp_t *rsdp, unsigned long *current); +void acpi_write_mcfg(acpi_mcfg_t *mcfg, acpi_rsdp_t *rsdp, unsigned long *current); +unsigned long acpi_write_tables(unsigned long start, const unsigned char AmlCode[]); #if CONFIG_HAVE_ACPI_RESUME /* 0 = S0, 1 = S1 ...*/ From gerrit at coreboot.org Sat Jul 2 15:15:38 2011 From: gerrit at coreboot.org (Cristian Măgherușan-Stanciu (cristi.magherusan@gmail.com)) Date: Sat, 2 Jul 2011 15:15:38 +0200 Subject: [coreboot] Patch set updated: d4b9079 usage example of the simplified ACPI code References: Message-ID: Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/77 -gerrit commit d4b907913375b334f26cfa294cac3212e49f2816 Author: Cristian M?gheru?an-Stanciu Date: Sat Jul 2 01:11:11 2011 +0300 usage example of the simplified ACPI code Change-Id: I7dcbf14a327fb347973b4cd9b7b3a4d6cdb31d7f Signed-off-by: Cristian M?gheru?an-Stanciu --- src/mainboard/asus/m2v-mx_se/acpi_tables.c | 100 +-------------- src/mainboard/lenovo/t60/acpi_tables.c | 194 +++------------------------- 2 files changed, 20 insertions(+), 274 deletions(-) diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c index 73e3768..1471ad9 100644 --- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c +++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c @@ -94,103 +94,5 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta unsigned long write_acpi_tables(unsigned long start) { - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = (start + 0x0f) & -0x10; - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, "DYNADATA"); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; + return acpi_write_tables(start, AmlCode); } diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 3742c20..4056e75 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -32,9 +32,6 @@ #include "dmi.h" extern const unsigned char AmlCode[]; -#if CONFIG_HAVE_ACPI_SLIC -unsigned long acpi_create_slic(unsigned long current); -#endif #include "southbridge/intel/i82801gx/nvs.h" static void acpi_create_gnvs(global_nvs_t *gnvs) @@ -56,38 +53,6 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->did[4] = 0x00000005; } -static void acpi_create_intel_hpet(acpi_hpet_t * hpet) -{ -#define HPET_ADDR 0xfed00000ULL - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = 1; - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = HPET_ADDR & 0xffffffff; - addr->addrh = HPET_ADDR >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ @@ -136,129 +101,31 @@ unsigned long acpi_fill_srat(unsigned long current) void smm_setup_structures(void *gnvs, void *tcg, void *smi1); -#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) -unsigned long write_acpi_tables(unsigned long start) + +void acpi_patch_dsdt(acpi_header_t *dsdt, unsigned long *current) { - unsigned long current; int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; -#if CONFIG_HAVE_ACPI_SLIC - acpi_header_t *slic; -#endif - acpi_header_t *ssdt; - acpi_header_t *dsdt; void *gnvs; - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - /* - * We explicitly add these tables later on: - */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - /* Fix up global NVS region for SMI handler. The GNVS region lives - * in the (high) table area. The low memory map looks like this: - * - * 0x00000000 - 0x000003ff Real Mode IVT - * 0x00000020 - 0x0000019c Low MP Table (XXX conflict?) - * 0x00000400 - 0x000004ff BDA (somewhat unused) - * 0x00000500 - 0x0000052f Moved GDT - * 0x00000530 - 0x00000b64 coreboot table - * 0x0007c000 - 0x0007dfff OS boot sector (unused?) - * 0x0007e000 - 0x0007ffff free to use (so no good for acpi+smi) - * 0x00080000 - 0x0009fbff usable ram - * 0x0009fc00 - 0x0009ffff EBDA (unused?) - * 0x000a0000 - 0x000bffff VGA memory - * 0x000c0000 - 0x000cffff VGA option rom - * 0x000d0000 - 0x000dffff free for other option roms? - * 0x000e0000 - 0x000fffff SeaBIOS? (conflict with low tables:) - * 0x000f0000 - 0x000f03ff PIRQ table - * 0x000f0400 - 0x000f66?? ACPI tables - * 0x000f66?? - 0x000f???? DMI tables - */ - - ALIGN_CURRENT; + *current = ALIGN(*current, 64); /* Pack GNVS into the ACPI table area */ for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current); - *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)*current); + *(u32*)(((u32)dsdt) + i) = *current; // 0x92 bytes break; } } /* And fill it */ - acpi_create_gnvs((global_nvs_t *)current); + acpi_create_gnvs((global_nvs_t *)*current); /* Keep pointer around */ - gnvs = (void *)current; + gnvs = (void *)*current; - current += 0x100; - ALIGN_CURRENT; + *current += 0x100; + *current = ALIGN(*current, 64); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); @@ -266,48 +133,25 @@ unsigned long write_acpi_tables(unsigned long start) /* We patched up the DSDT, so we need to recalculate the checksum */ dsdt->checksum = 0; dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); +} - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - -#if CONFIG_HAVE_ACPI_SLIC - printk(BIOS_DEBUG, "ACPI: * SLIC\n"); - slic = (acpi_header_t *)current; - current += acpi_create_slic(current); - ALIGN_CURRENT; - acpi_add_table(rsdp, slic); -#endif - - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, "COREBOOT"); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "current = %lx\n", current); - +void acpi_dmi_workaround(unsigned long *current) +{ printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); #if CONFIG_WRITE_HIGH_TABLES == 1 - memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); - current += DMI_TABLE_SIZE; - ALIGN_CURRENT; + memcpy((void *)*current, dmi_table, DMI_TABLE_SIZE); + *current += DMI_TABLE_SIZE; + *current = ALIGN(*current, 64); #endif - printk(BIOS_INFO, "ACPI: done.\n"); +} +unsigned long write_acpi_tables(unsigned long start) +{ /* Enable Dummy DCC ON# for DVI */ printk(BIOS_DEBUG, "Laptop handling...\n"); outb(inb(0x60f) & ~(1 << 5), 0x60f); - return current; + return acpi_write_tables(start, AmlCode); } From gerrit at coreboot.org Sat Jul 2 15:48:22 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 2 Jul 2011 15:48:22 +0200 Subject: [coreboot] Patch set updated: 6195e48 Un-perl commit-msg hook References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/78 -gerrit commit 6195e48fbe30cf93a53c2aec379534daa1d95582 Author: Patrick Georgi Date: Sat Jul 2 00:35:02 2011 +0200 Un-perl commit-msg hook To simplify installation on mingw a bit (even though git remains a pain), drop the perl dependency the commit-msg hook introduced to the coreboot development environment. It's replaced by awk which we use elsewhere already (and is a more lightweight utility in any case) Change-Id: I67adfe1ec43c898735d4bae4819ceb53e83c303b Signed-off-by: Patrick Georgi --- util/gitconfig/commit-msg | 61 ++++++++++++++++++-------------------------- 1 files changed, 25 insertions(+), 36 deletions(-) diff --git a/util/gitconfig/commit-msg b/util/gitconfig/commit-msg index 789bad3..4c80420 100755 --- a/util/gitconfig/commit-msg +++ b/util/gitconfig/commit-msg @@ -43,46 +43,35 @@ add_ChangeId() { fi id=`_gen_ChangeId` - perl -e ' - $MSG = shift; - $id = shift; - $CHANGE_ID_AFTER = shift; + T=`mktemp` + cat "$MSG" | awk ' + !/^[a-zA-Z0-9-]+:/ { + print $0; + next; + }; - undef $/; - open(I, $MSG); $_ = ; close I; - s|^diff --git a/.*||ms; - s|^#.*$||mg; - exit unless $_; + { + if (lines != "") { + lines = lines "\n"; + }; + lines = lines $0 + }; - @message = split /\n/; - $haveFooter = 0; - $startFooter = @message; - for($line = @message - 1; $line >= 0; $line--) { - $_ = $message[$line]; - - if (/^[a-zA-Z0-9-]+:/ && !m,^[a-z0-9-]+://,) { - $haveFooter++; - next; - } - next if /^[ []/; - $startFooter = $line if ($haveFooter && /^\r?$/); - last; + END { + split(lines, footer, "\n"); + numlines=length(footer); + pre=1; + for (line = 1; line <= numlines; line++) { + if (pre && match(footer[line], "('$CHANGE_ID_AFTER'):") != 1) { + pre=0; + print "Change-Id: I'$id'"; + }; + print footer[line]; } - - @footer = @message[$startFooter+1.. at message]; - @message = @message[0..$startFooter]; - push(@footer, "") unless @footer; - - for ($line = 0; $line < @footer; $line++) { - $_ = $footer[$line]; - next if /^($CHANGE_ID_AFTER):/i; - last; + if (pre) { + print "Change-Id: I'$id'"; } - splice(@footer, $line, 0, "Change-Id: I$id"); - - $_ = join("\n", @message, @footer); - open(O, ">$MSG"); print O; close O; - ' "$MSG" "$id" "$CHANGE_ID_AFTER" + }' > $T && mv $T "$MSG" || rm -f $T } _gen_ChangeIdInput() { echo "tree `git write-tree`" From gerrit at coreboot.org Sat Jul 2 15:48:56 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 2 Jul 2011 15:48:56 +0200 Subject: [coreboot] Patch merged into master: 0362d89 whitespace-only changes in acpi.c, replaced spaces with tabs References: Message-ID: the following patch was just integrated into master: commit 0362d89266df43b756ee8a7c9d008ef71ae73011 Author: Cristian M??gheru??an-Stanciu Date: Sat Jul 2 00:57:07 2011 +0300 whitespace-only changes in acpi.c, replaced spaces with tabs Change-Id: Ibd598813bec0c93d77afbce8aee330498afbe5f6 Signed-off-by: Cristian M??gheru??an-Stanciu See http://review.coreboot.org/74 for details. -gerrit From gerrit at coreboot.org Sat Jul 2 16:23:09 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 2 Jul 2011 16:23:09 +0200 Subject: [coreboot] New patch to review: fc9dd35 Fix lint-002-build-dir-handling References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/80 -gerrit commit fc9dd354ea48dfe132326f0b9d6ebece3c021bb8 Author: Patrick Georgi Date: Sat Jul 2 16:21:31 2011 +0200 Fix lint-002-build-dir-handling That lint test requires some Kconfig defaults and uses allyesconfig for that. Unfortunately that also draws in ccache and scanbuild support, which significantly change the behaviour of the toplevel Makefile. Notably, the ccache support breaks if no ccache is installed. Change-Id: I17cbb7974be33fc077e5cbd5fb616a5b00a47d97 Signed-off-by: Patrick Georgi --- util/lint/lint-002-build-dir-handling | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/lint/lint-002-build-dir-handling b/util/lint/lint-002-build-dir-handling index 39e3124..f10db17 100755 --- a/util/lint/lint-002-build-dir-handling +++ b/util/lint/lint-002-build-dir-handling @@ -33,7 +33,7 @@ fi # $1: object directory run_printall() { -$MAKE NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s, ,\n,g" -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," +$MAKE CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s, ,\n,g" -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," } # find GNU make From gerrit at coreboot.org Sat Jul 2 16:43:28 2011 From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz)) Date: Sat, 2 Jul 2011 16:43:28 +0200 Subject: [coreboot] New patch to review: 6974e42 Small SMM fixups References: Message-ID: Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/81 -gerrit commit 6974e425a31b1c798dd05e346e9ca4521e31079f Author: Rudolf Marek Date: Sat Jul 2 16:03:24 2011 +0200 Small SMM fixups Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of XCHG). While at it add the PAUSE instruction to spinlock loop to hint the CPU we are just spinlocking. The rep nop could not be used because "as" complains that rep is used without string instructions. Change-Id: I325cd83de3a6557b1bee6758bc151bc81e874f8c Signed-off-by: Rudolf Marek --- src/cpu/x86/smm/smihandler.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index d44a3ea..a6ab87f 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -28,7 +28,7 @@ typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ -static volatile smi_semaphore smi_handler_status = SMI_UNLOCKED; +static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED; static int smi_obtain_lock(void) { @@ -121,7 +121,11 @@ void smi_handler(u32 smm_revision) /* For security reasons we don't release the other CPUs * until the CPU with the lock is actually done */ - while (smi_handler_status == SMI_LOCKED) /* wait */ ; + while (smi_handler_status == SMI_LOCKED) { + asm volatile ( + ".byte 0xf3, 0x90\n" /* hint a CPU we are in spinlock (PAUSE instruction, REP NOP) */ + ); + } return; } From gerrit at coreboot.org Sat Jul 2 16:43:28 2011 From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz)) Date: Sat, 2 Jul 2011 16:43:28 +0200 Subject: [coreboot] New patch to review: 77439f0 Make AMD SMM SMP aware References: Message-ID: Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/82 -gerrit commit 77439f041fc6348cdaaa682d5cbe8c41f3f96241 Author: Rudolf Marek Date: Sat Jul 2 16:36:17 2011 +0200 Make AMD SMM SMP aware Move the SMM MSR init to a code run per CPU. Introduce global SMM_BASE define, later all 0xa0000 could be changed to use it. Remove the unnecessary test if the smm_init routine is called once (it is called by BSP only) and also remove if lock bit is set becuase this bit is cleared by INIT it seems. Add the defines for fam10h and famfh to respective files, we do not have any shared AMD MSR header file. Tested on M2V-MX SE with dualcore CPU. Change-Id: I1b2bf157d1cc79c566c9089689a9bfd9310f5683 Signed-off-by: Rudolf Marek --- src/cpu/amd/model_10xxx/model_10xxx_init.c | 13 +++- src/cpu/amd/model_fxx/model_fxx_init.c | 16 ++++ src/cpu/amd/smm/smm_init.c | 124 ++++++++++------------------ src/include/cpu/amd/model_10xxx_msr.h | 4 + src/include/cpu/amd/model_fxx_msr.h | 4 + src/include/cpu/x86/smm.h | 3 + 6 files changed, 82 insertions(+), 82 deletions(-) diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index a92852f..2e8bbfe 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -118,7 +119,17 @@ static void model_10xxx_init(device_t dev) msr.hi &= ~(1 << (35-32)); wrmsr(BU_CFG2_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ + /* Set SMM base address for this CPU */ + msr = rdmsr(SMM_BASE_MSR); + msr.lo = SMM_BASE - (lapicid() * 0x400); + wrmsr(SMM_BASE_MSR, msr); + + /* Enable the SMM memory window */ + msr = rdmsr(SMM_MASK_MSR); + msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ + wrmsr(SMM_MASK_MSR, msr); + + /* Set SMMLOCK to avoid exploits messing with SMM */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 0608d0a..ce5c810 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -547,6 +548,21 @@ static void model_fxx_init(device_t dev) */ if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0 + + /* Set SMM base address for this CPU */ + msr = rdmsr(SMM_BASE_MSR); + msr.lo = SMM_BASE - (lapicid() * 0x400); + wrmsr(SMM_BASE_MSR, msr); + + /* Enable the SMM memory window */ + msr = rdmsr(SMM_MASK_MSR); + msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ + wrmsr(SMM_MASK_MSR, msr); + + /* Set SMMLOCK to avoid exploits messing with SMM */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c index ad1c112..6398688 100644 --- a/src/cpu/amd/smm/smm_init.c +++ b/src/cpu/amd/smm/smm_init.c @@ -30,94 +30,56 @@ #include #include -#define SMM_BASE_MSR 0xc0010111 -#define SMM_ADDR_MSR 0xc0010112 -#define SMM_MASK_MSR 0xc0010113 -#define SMM_BASE 0xa0000 - extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_size; -static int smm_handler_copied = 0; - void smm_init(void) { - msr_t msr; - - msr = rdmsr(HWCR_MSR); - if (msr.lo & (1 << 0)) { - // This sounds like a bug... ? - printk(BIOS_DEBUG, "SMM is still locked from last boot, using old handler.\n"); - return; - } - - /* Only copy SMM handler once, not once per CPU */ - if (!smm_handler_copied) { - msr_t syscfg_orig, mtrr_aseg_orig; - - smm_handler_copied = 1; - - /* Back up MSRs for later restore */ - syscfg_orig = rdmsr(SYSCFG_MSR); - mtrr_aseg_orig = rdmsr(MTRRfix16K_A0000_MSR); - - /* MTRR changes don't like an enabled cache */ - disable_cache(); - - msr = syscfg_orig; - /* Allow changes to MTRR extended attributes */ - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - /* turn the extended attributes off until we fix - * them so A0000 is routed to memory - */ - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - /* set DRAM access to 0xa0000 */ - /* A0000 is memory */ - msr.lo = 0x18181818; - msr.hi = 0x18181818; - wrmsr(MTRRfix16K_A0000_MSR, msr); - - /* enable the extended features */ - msr = syscfg_orig; - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - enable_cache(); - /* copy the real SMM handler */ - memcpy((void *)SMM_BASE, &_binary_smm_start, (size_t)&_binary_smm_size); - wbinvd(); - - /* Restore MTRR */ - disable_cache(); - - /* Restore SYSCFG */ - wrmsr(SYSCFG_MSR, syscfg_orig); - - wrmsr(MTRRfix16K_A0000_MSR, mtrr_aseg_orig); - enable_cache(); - } - - - /* But set SMM base address on all CPUs/cores */ - msr = rdmsr(SMM_BASE_MSR); - msr.lo = SMM_BASE - (lapicid() * 0x400); - wrmsr(SMM_BASE_MSR, msr); - - /* enable the SMM memory window */ - msr = rdmsr(SMM_MASK_MSR); - msr.lo |= (1 << 0); // Enable ASEG SMRAM Range - wrmsr(SMM_MASK_MSR, msr); - - /* Set SMMLOCK to avoid exploits messing with SMM */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + msr_t msr, syscfg_orig, mtrr_aseg_orig; + + /* Back up MSRs for later restore */ + syscfg_orig = rdmsr(SYSCFG_MSR); + mtrr_aseg_orig = rdmsr(MTRRfix16K_A0000_MSR); + + /* MTRR changes don't like an enabled cache */ + disable_cache(); + + msr = syscfg_orig; + + /* Allow changes to MTRR extended attributes */ + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + /* turn the extended attributes off until we fix + * them so A0000 is routed to memory + */ + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* set DRAM access to 0xa0000 */ + msr.lo = 0x18181818; + msr.hi = 0x18181818; + wrmsr(MTRRfix16K_A0000_MSR, msr); + + /* enable the extended features */ + msr = syscfg_orig; + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + enable_cache(); + /* copy the real SMM handler */ + memcpy((void *)SMM_BASE, &_binary_smm_start, (size_t)&_binary_smm_size); + wbinvd(); + disable_cache(); + + /* Restore SYSCFG and MTRR */ + wrmsr(SYSCFG_MSR, syscfg_orig); + wrmsr(MTRRfix16K_A0000_MSR, mtrr_aseg_orig); + enable_cache(); + + /* CPU MSR are set in CPU init */ } void smm_lock(void) { - /* We lock SMM per CPU core */ + /* We lock SMM in CPU init */ } diff --git a/src/include/cpu/amd/model_10xxx_msr.h b/src/include/cpu/amd/model_10xxx_msr.h index f497eb3..b34a281 100644 --- a/src/include/cpu/amd/model_10xxx_msr.h +++ b/src/include/cpu/amd/model_10xxx_msr.h @@ -22,6 +22,10 @@ #include +#define SMM_BASE_MSR 0xC0010111 +#define SMM_ADDR_MSR 0xC0010112 +#define SMM_MASK_MSR 0xC0010113 + #define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f #define LS_CFG_MSR 0xC0011020 diff --git a/src/include/cpu/amd/model_fxx_msr.h b/src/include/cpu/amd/model_fxx_msr.h index b4795cb..2ac2d4e 100644 --- a/src/include/cpu/amd/model_fxx_msr.h +++ b/src/include/cpu/amd/model_fxx_msr.h @@ -1,6 +1,10 @@ #ifndef CPU_AMD_MODEL_FXX_MSR_H #define CPU_AMD_MODEL_FXX_MSR_H +#define SMM_BASE_MSR 0xc0010111 +#define SMM_ADDR_MSR 0xc0010112 +#define SMM_MASK_MSR 0xc0010113 + #define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f #define LS_CFG_MSR 0xC0011020 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 49ee2be..c314c39 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -24,6 +24,9 @@ #ifndef CPU_X86_SMM_H #define CPU_X86_SMM_H +/* used only by C programs so far */ +#define SMM_BASE 0xa0000 + #include typedef struct { u16 es_selector; From gerrit at coreboot.org Sat Jul 2 16:43:28 2011 From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz)) Date: Sat, 2 Jul 2011 16:43:28 +0200 Subject: [coreboot] New patch to review: 835a320 Enable SMI on M2V-MX SE References: Message-ID: Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/83 -gerrit commit 835a320916cd7a5032750b1fe1ca0df37a33f198 Author: Rudolf Marek Date: Sat Jul 2 16:41:38 2011 +0200 Enable SMI on M2V-MX SE Finally the SMI routines are in good shape on AMD, lets enable this and later implement ACPI on/off SMI commands. Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e Signed-off-by: Rudolf Marek --- src/mainboard/asus/m2v-mx_se/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 09157ee..1d8f367 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select VGA From r.marek at assembler.cz Sat Jul 2 17:29:04 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Sat, 02 Jul 2011 17:29:04 +0200 Subject: [coreboot] [RFC] use of SMM with SSE/MMX... Message-ID: <4E0F3940.9040000@assembler.cz> Hi all, The MMX/SSE/x87 is not handled in save state map. GCC might produce such instructions if it wants. Problem is what to do with that. Either we can compile all SMM code with -no-sse/mmx/fpu switches (I think those exists) or we could use the FXSAVE/FRSTORE instructions to backup the state. problem is that it needs 512 bytes / CPU. Either could put that on stack which is 0x400 bytes total and make it 2 times smaller or for AMD we have 0x200 bytes still free in the save state map, but not on Intel. Ideas? Thanks Rudolf From patrick at georgi-clan.de Sat Jul 2 19:06:30 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 02 Jul 2011 19:06:30 +0200 Subject: [coreboot] [RFC] use of SMM with SSE/MMX... In-Reply-To: <4E0F3940.9040000@assembler.cz> References: <4E0F3940.9040000@assembler.cz> Message-ID: <4E0F5016.6050907@georgi-clan.de> Am Samstag, 2. Juli 2011 17:29:04, Rudolf Marek schrieb: > Problem is what to do with that. Either we can compile all SMM code with > -no-sse/mmx/fpu switches (I think those exists) or we could use the To avoid future register additions to mess up things, what about -mcpu=i386 or something like that? From r.marek at assembler.cz Sat Jul 2 23:08:09 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Sat, 02 Jul 2011 23:08:09 +0200 Subject: [coreboot] [RFC] use of SMM with SSE/MMX... In-Reply-To: <4E0F5016.6050907@georgi-clan.de> References: <4E0F3940.9040000@assembler.cz> <4E0F5016.6050907@georgi-clan.de> Message-ID: <4E0F88B9.3000206@assembler.cz> Hi, Yes even 486 would be good fit! (It has more closer aligns etc). As Stefan mentioned, some CPU might not have SSE enabled failing to execute coreboot. Maybe this is a bit broader problem. Thanks Rudolf From gerrit at coreboot.org Sun Jul 3 14:47:49 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 3 Jul 2011 14:47:49 +0200 Subject: [coreboot] Patch merged into master: 4345556 Fixes to the libpayload build system References: Message-ID: the following patch was just integrated into master: commit 434555659991021344fcebd7fcef910c3ae78ae5 Author: Patrick Georgi Date: Sat Jul 2 00:29:09 2011 +0200 Fixes to the libpayload build system - its Makefile is part of the libpayload project - fix conversion bug in powerpc's Makefile.inc Change-Id: I84f2da092c3733ea7d0f232cb3768078cf13dfd5 Signed-off-by: Patrick Georgi See http://review.coreboot.org/79 for details. -gerrit From stefan.reinauer at coreboot.org Sun Jul 3 23:11:46 2011 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Sun, 03 Jul 2011 14:11:46 -0700 Subject: [coreboot] [RFC] use of SMM with SSE/MMX... In-Reply-To: <4E0F88B9.3000206@assembler.cz> References: <4E0F3940.9040000@assembler.cz> <4E0F5016.6050907@georgi-clan.de> <4E0F88B9.3000206@assembler.cz> Message-ID: <4E10DB12.4080502@coreboot.org> On 7/2/11 2:08 PM, Rudolf Marek wrote: > Hi, > > Yes even 486 would be good fit! (It has more closer aligns etc). As > Stefan mentioned, some CPU might not have SSE enabled failing to > execute coreboot. Maybe this is a bit broader problem. > > Thanks > Rudolf > Note that this problem does not happen with the reference toolchain that is i386-elf. I agree, we should add CFLAGS to not compile coreboot or at least the SMM handler with MMX/SSE/... instructions. There is no big gain in doing so anyways. Stefan From scott at notabs.org Mon Jul 4 04:56:23 2011 From: scott at notabs.org (Scott Duplichan) Date: Sun, 3 Jul 2011 21:56:23 -0500 Subject: [coreboot] [RFC] use of SMM with SSE/MMX... In-Reply-To: <4E10DB12.4080502@coreboot.org> References: <4E0F3940.9040000@assembler.cz> <4E0F5016.6050907@georgi-clan.de><4E0F88B9.3000206@assembler.cz> <4E10DB12.4080502@coreboot.org> Message-ID: Stefan Reinauer wrote: ]On 7/2/11 2:08 PM, Rudolf Marek wrote: ]> Hi, ]> ]> Yes even 486 would be good fit! (It has more closer aligns etc). As ]> Stefan mentioned, some CPU might not have SSE enabled failing to ]> execute coreboot. Maybe this is a bit broader problem. ]> ]> Thanks ]> Rudolf ]> ]Note that this problem does not happen with the reference toolchain that ]is i386-elf. The asrock e350m1 project ends up with some mmx and xmm register usage, at least as I build it. Some is forced in by the memory initialization code. Examples are the asm code in function _mm_stream_si128_fs2() and in file cache_as_ram.inc. In other cases, it appears the compiler chooses these registers on its own. For the AMD reference code, this is not surprising due to the use of compiler flags -march=k8-sse3 and -mtune=k8-sse3. However, there are cases in common coreboot code where xmm register accesses are generated, such as in coreboot_table.c. ]I agree, we should add CFLAGS to not compile coreboot or at least the ]SMM handler with MMX/SSE/... instructions. ]There is no big gain in doing so anyways. If the smm code is stand-alone and does not call library functions, then using separate compile flags for it should be easy. ]Stefan From gerrit at coreboot.org Mon Jul 4 08:36:42 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 4 Jul 2011 08:36:42 +0200 Subject: [coreboot] Patch merged into master: 6974e42 Small SMM fixups References: Message-ID: the following patch was just integrated into master: commit 6974e425a31b1c798dd05e346e9ca4521e31079f Author: Rudolf Marek Date: Sat Jul 2 16:03:24 2011 +0200 Small SMM fixups Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of XCHG). While at it add the PAUSE instruction to spinlock loop to hint the CPU we are just spinlocking. The rep nop could not be used because "as" complains that rep is used without string instructions. Change-Id: I325cd83de3a6557b1bee6758bc151bc81e874f8c Signed-off-by: Rudolf Marek See http://review.coreboot.org/81 for details. -gerrit From svn at coreboot.org Mon Jul 4 16:00:02 2011 From: svn at coreboot.org (coreboot tracker) Date: Mon, 04 Jul 2011 16:00:02 +0200 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From devtadas at gmail.com Mon Jul 4 20:46:28 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Mon, 04 Jul 2011 21:46:28 +0300 Subject: [coreboot] [PATCH 1/2] SerialICE files, receive function for romcc_console, bootblock_simple example In-Reply-To: <1309804372.3293.80.camel@ts-laptop> References: <1309804372.3293.80.camel@ts-laptop> Message-ID: <1309805188.3293.83.camel@ts-laptop> Copy required SerialICE files (not patched yet), add receive byte function to romcc_console, add SerialICE to bootblock_simple SerialICE revision: 107 Signed-off-by: Tadas Slotkus --- src/arch/x86/SerialICE/io.h | 195 ++++++++++++++++++++++++++ src/arch/x86/SerialICE/serial.c | 187 ++++++++++++++++++++++++ src/arch/x86/SerialICE/serialice.c | 257 ++++++++++++++++++++++++++++++++++ src/arch/x86/init/bootblock_simple.c | 2 + src/arch/x86/lib/romcc_console.c | 7 + 5 files changed, 648 insertions(+), 0 deletions(-) create mode 100644 src/arch/x86/SerialICE/io.h create mode 100644 src/arch/x86/SerialICE/serial.c create mode 100644 src/arch/x86/SerialICE/serialice.c diff --git a/src/arch/x86/SerialICE/io.h b/src/arch/x86/SerialICE/io.h new file mode 100644 index 0000000..a47feef --- /dev/null +++ b/src/arch/x86/SerialICE/io.h @@ -0,0 +1,195 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef IO_H +#define IO_H + +/* Memory functions */ + +static inline u8 read8(unsigned long addr) +{ + return *((volatile u8 *)(addr)); +} + +static inline u16 read16(unsigned long addr) +{ + return *((volatile u16 *)(addr)); +} + +static inline u32 read32(unsigned long addr) +{ + return *((volatile u32 *)(addr)); +} + +static inline void write8(unsigned long addr, u8 value) +{ + *((volatile u8 *)(addr)) = value; +} + +static inline void write16(unsigned long addr, u16 value) +{ + *((volatile u16 *)(addr)) = value; +} + +static inline void write32(unsigned long addr, u32 value) +{ + *((volatile u32 *)(addr)) = value; +} + +/* IO functions */ + +#if defined( __ROMCC__ ) && !defined (__GNUC__) +static inline void outb(u8 value, u16 port) +{ + __builtin_outb(value, port); +} + +static inline void outw(u16 value, u16 port) +{ + __builtin_outw(value, port); +} + +static inline void outl(u32 value, u16 port) +{ + __builtin_outl(value, port); +} + +static inline u8 inb(u16 port) +{ + return __builtin_inb(port); +} + +static inline u16 inw(u16 port) +{ + return __builtin_inw(port); +} + +static inline u32 inl(u16 port) +{ + return __builtin_inl(port); +} +#else +static inline void outb(u8 value, u16 port) +{ + __asm__ __volatile__("outb %b0, %w1"::"a"(value), "Nd"(port)); +} + +static inline void outw(u16 value, u16 port) +{ + __asm__ __volatile__("outw %w0, %w1"::"a"(value), "Nd"(port)); +} + +static inline void outl(u32 value, u16 port) +{ + __asm__ __volatile__("outl %0, %w1"::"a"(value), "Nd"(port)); +} + +static inline u8 inb(u16 port) +{ + u8 value; + __asm__ __volatile__("inb %w1, %b0":"=a"(value): "Nd"(port)); + return value; +} + +static inline u16 inw(u16 port) +{ + u16 value; + __asm__ __volatile__("inw %w1, %w0":"=a"(value): "Nd"(port)); + return value; +} + +static inline u32 inl(u16 port) +{ + u32 value; + __asm__ __volatile__("inl %w1, %0":"=a"(value): "Nd"(port)); + return value; +} +#endif /* __ROMCC__ && !__GNUC__ */ + +/* MSR functions */ + +typedef struct { u32 lo, hi; } msr_t; + +static inline msr_t rdmsr(u32 index, u32 key) +{ + msr_t result; + __asm__ __volatile__ ( + "rdmsr" + : "=a" (result.lo), "=d" (result.hi) + : "c" (index), "D" (key) + ); + return result; +} + +static inline void wrmsr(u32 index, msr_t msr, u32 key) +{ + __asm__ __volatile__ ( + "wrmsr" + : /* No outputs */ + : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (key) + ); +} + +/* CPUID functions */ + +static inline u32 cpuid_eax(u32 op, u32 op2) +{ + u32 eax; + + __asm__("cpuid" + : "=a" (eax) + : "a" (op), "c" (op2) + : "ebx", "edx" ); + return eax; +} + +static inline u32 cpuid_ebx(u32 op, u32 op2) +{ + u32 eax, ebx; + + __asm__("cpuid" + : "=b" (ebx) + : "a" (op), "c" (op2) + : "edx"); + return ebx; +} + +static inline u32 cpuid_ecx(u32 op, u32 op2) +{ + u32 eax, ecx; + + __asm__("cpuid" + : "=c" (ecx) + : "a" (op), "c" (op2) + : "ebx", "edx" ); + return ecx; +} + +static inline u32 cpuid_edx(u32 op, u32 op2) +{ + u32 eax, edx; + + __asm__("cpuid" + : "=d" (edx) + : "a" (op), "c" (op2) + : "ebx"); + return edx; +} + +#endif diff --git a/src/arch/x86/SerialICE/serial.c b/src/arch/x86/SerialICE/serial.c new file mode 100644 index 0000000..9aaecb6 --- /dev/null +++ b/src/arch/x86/SerialICE/serial.c @@ -0,0 +1,187 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 + +/* SIO functions */ + +static void sio_init(void) +{ + int divisor = 115200 / SIO_SPEED; + int lcs = 3; + outb(0x00, SIO_PORT + UART_IER); + outb(0x01, SIO_PORT + UART_FCR); + outb(0x03, SIO_PORT + UART_MCR); + outb(0x80 | lcs, SIO_PORT + UART_LCR); + outb(divisor & 0xff, SIO_PORT + UART_DLL); + outb((divisor >> 8) & 0xff, SIO_PORT + UART_DLM); + outb(lcs, SIO_PORT + UART_LCR); +} + +static void sio_putc(u8 data) +{ + while (!(inb(SIO_PORT + UART_LSR) & 0x20)) ; + outb(data, SIO_PORT + UART_TBR); + while (!(inb(SIO_PORT + UART_LSR) & 0x40)) ; +} + +static u8 sio_getc(void) +{ + u8 val; + while (!(inb(SIO_PORT + UART_LSR) & 0x01)) ; + + val = inb(SIO_PORT + UART_RBR); + +#if ECHO_MODE + sio_putc(val); +#endif + return val; +} + +/* SIO helpers */ + +static void sio_putstring(char *string) +{ + /* Very simple, no %d, %x etc. */ + while (*string) { + if (*string == '\n') + sio_putc('\r'); + sio_putc(*string); + string++; + } +} + +#define sio_put_nibble(nibble) \ + if (nibble > 9) \ + nibble += ('a' - 10); \ + else \ + nibble += '0'; \ + sio_putc(nibble) + +static void sio_put8(u8 data) +{ + int i; + u8 c; + + c = (data >> 4) & 0xf; + sio_put_nibble(c); + + c = data & 0xf; + sio_put_nibble(c); +} + +static void sio_put16(u16 data) +{ + int i; + for (i=12; i >= 0; i -= 4) { + u8 c = (data >> i) & 0xf; + sio_put_nibble(c); + } +} + +static void sio_put32(u32 data) +{ + int i; + for (i=28; i >= 0; i -= 4) { + u8 c = (data >> i) & 0xf; + sio_put_nibble(c); + } +} + +static u8 sio_get_nibble(void) +{ + u8 ret = 0; + u8 nibble = sio_getc(); + + if (nibble >= '0' && nibble <= '9') { + ret = (nibble - '0'); + } else if (nibble >= 'a' && nibble <= 'f') { + ret = (nibble - 'a') + 0xa; + } else if (nibble >= 'A' && nibble <= 'F') { + ret = (nibble - 'A') + 0xa; + } else { + sio_putstring("ERROR: parsing number\n"); + } + return ret; +} + +static u8 sio_get8(void) +{ + u8 data; + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + return data; +} + +static u16 sio_get16(void) +{ + u16 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +static u32 sio_get32(void) +{ + u32 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + + diff --git a/src/arch/x86/SerialICE/serialice.c b/src/arch/x86/SerialICE/serialice.c new file mode 100644 index 0000000..35531dc --- /dev/null +++ b/src/arch/x86/SerialICE/serialice.c @@ -0,0 +1,257 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +/* SIO functions */ +#include "serial.c" + +/* Hardware specific functions */ + +#include "chipset.c" + +/* Accessor functions */ + +static void serialice_read_memory(void) +{ + u8 width; + u32 addr; + + // Format: + // *rm00000000.w + addr = sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': sio_put8(read8(addr)); break; + case 'w': sio_put16(read16(addr)); break; + case 'l': sio_put32(read32(addr)); break; + } +} + +static void serialice_write_memory(void) +{ + u8 width; + u32 addr; + u32 data; + + // Format: + // *wm00000000.w=0000 + addr = sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': data = sio_get8(); write8(addr, (u8)data); break; + case 'w': data = sio_get16(); write16(addr, (u16)data); break; + case 'l': data = sio_get32(); write32(addr, (u32)data); break; + } +} + +static void serialice_read_io(void) +{ + u8 width; + u16 port; + + // Format: + // *ri0000.w + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': sio_put8(inb(port)); break; + case 'w': sio_put16(inw(port)); break; + case 'l': sio_put32(inl(port)); break; + } +} + +static void serialice_write_io(void) +{ + u8 width; + u16 port; + u32 data; + + // Format: + // *wi0000.w=0000 + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': data = sio_get8(); outb((u8)data, port); break; + case 'w': data = sio_get16(); outw((u16)data, port); break; + case 'l': data = sio_get32(); outl((u32)data, port); break; + } +} + +static void serialice_read_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *rc00000000.9c5a203a + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // key in %edi + + sio_putc('\r'); sio_putc('\n'); + + msr = rdmsr(addr, key); + sio_put32(msr.hi); + sio_putc('.'); + sio_put32(msr.lo); +} + +static void serialice_write_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *wc00000000.9c5a203a=00000000.00000000 + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // read key in %edi + sio_getc(); // skip = + msr.hi = sio_get32(); + sio_getc(); // skip . + msr.lo = sio_get32(); + +#ifdef __ROMCC__ + /* Cheat to avoid register outage */ + wrmsr(addr, msr, 0x9c5a203a); +#else + wrmsr(addr, msr, key); +#endif +} + +static void serialice_cpuinfo(void) +{ + u32 eax, ecx; + u32 reg32; + + // Format: + // --EAX--- --ECX--- + // *ci00000000.00000000 + eax = sio_get32(); + sio_getc(); // skip . + ecx = sio_get32(); + + sio_putc('\r'); sio_putc('\n'); + + /* This code looks quite crappy but this way we don't + * have to worry about running out of registers if we + * occupy eax, ebx, ecx, edx at the same time + */ + reg32 = cpuid_eax(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ebx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ecx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_edx(eax, ecx); + sio_put32(reg32); +} + +static void serialice_mainboard(void) +{ + sio_putc('\r'); sio_putc('\n'); + + /* must be defined in mainboard/.c */ + sio_putstring(boardname); +} + +static void serialice_version(void) +{ + sio_putstring("\nSerialICE v" VERSION " (" __DATE__ ")\n"); +} + +int main(void) +{ + chipset_init(); + + sio_init(); + + serialice_version(); + + while(1) { + u16 c; + sio_putstring("\n> "); + + c = sio_getc(); + if (c != '*') + continue; + + c = sio_getc() << 8; + c |= sio_getc(); + + switch(c) { + case (('r' << 8)|'m'): // Read Memory *rm + serialice_read_memory(); + break; + case (('w' << 8)|'m'): // Write Memory *wm + serialice_write_memory(); + break; + case (('r' << 8)|'i'): // Read IO *ri + serialice_read_io(); + break; + case (('w' << 8)|'i'): // Write IO *wi + serialice_write_io(); + break; + case (('r' << 8)|'c'): // Read CPU MSR *rc + serialice_read_msr(); + break; + case (('w' << 8)|'c'): // Write CPU MSR *wc + serialice_write_msr(); + break; + case (('c' << 8)|'i'): // Read CPUID *ci + serialice_cpuinfo(); + break; + case (('m' << 8)|'b'): // Read mainboard type *mb + serialice_mainboard(); + break; + case (('v' << 8)|'i'): // Read version info *vi + serialice_version(); + break; + default: + sio_putstring("ERROR\n"); + break; + } + } + + // Never get here: + return 0; +} diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 5d7c611..8386868 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -1,4 +1,5 @@ #include +#include "../SerialICE/serialice.c" static void main(unsigned long bist) { @@ -12,6 +13,7 @@ static void main(unsigned long bist) sanitize_cmos(); #endif + serialice_main(); const char* target1 = "fallback/romstage"; unsigned long entry; entry = findstage(target1); diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 13ee1f0..3747136 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -48,6 +48,13 @@ static void __console_tx_byte(unsigned char byte) #endif } +static unsigned char __console_rx_byte(void) +{ +#if CONFIG_CONSOLE_SERIAL8250 + return uart8250_rx_byte(CONFIG_TTYS0_BASE); +#endif +} + static void __console_tx_nibble(unsigned nibble) { unsigned char digit; -- 1.7.0.4 From devtadas at gmail.com Mon Jul 4 20:48:36 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Mon, 04 Jul 2011 21:48:36 +0300 Subject: [coreboot] [PATCH 2/2] SerialICE patch In-Reply-To: <1309804372.3293.80.camel@ts-laptop> References: <1309804372.3293.80.camel@ts-laptop> Message-ID: <1309805316.3293.85.camel@ts-laptop> Add serial init function example to use coreboot early serial funcions Add selection which cpuid or msr functions to use (coreboot's or serialice's) Addapt for coreboot Signed-off-by: Tadas Slotkus --- src/arch/x86/SerialICE/io.h | 8 +++--- src/arch/x86/SerialICE/serial.c | 23 ++++++++++++--------- src/arch/x86/SerialICE/serialice.c | 39 ++++++++++++++++++++++++----------- 3 files changed, 44 insertions(+), 26 deletions(-) diff --git a/src/arch/x86/SerialICE/io.h b/src/arch/x86/SerialICE/io.h index a47feef..efc0fe6 100644 --- a/src/arch/x86/SerialICE/io.h +++ b/src/arch/x86/SerialICE/io.h @@ -21,7 +21,7 @@ #define IO_H /* Memory functions */ - +#if 0 static inline u8 read8(unsigned long addr) { return *((volatile u8 *)(addr)); @@ -125,8 +125,8 @@ static inline u32 inl(u16 port) /* MSR functions */ typedef struct { u32 lo, hi; } msr_t; - -static inline msr_t rdmsr(u32 index, u32 key) +#endif +static inline msr_t _rdmsr(u32 index, u32 key) { msr_t result; __asm__ __volatile__ ( @@ -137,7 +137,7 @@ static inline msr_t rdmsr(u32 index, u32 key) return result; } -static inline void wrmsr(u32 index, msr_t msr, u32 key) +static inline void _wrmsr(u32 index, msr_t msr, u32 key) { __asm__ __volatile__ ( "wrmsr" diff --git a/src/arch/x86/SerialICE/serial.c b/src/arch/x86/SerialICE/serial.c index 9aaecb6..1181aff 100644 --- a/src/arch/x86/SerialICE/serial.c +++ b/src/arch/x86/SerialICE/serial.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if 0 /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -34,22 +35,23 @@ #define UART_LSR 0x05 #define UART_MSR 0x06 #define UART_SCR 0x07 - +#endif /* SIO functions */ +/* Early serial includes and defines */ +#include +#include +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +#include + +#define sio_putc __console_tx_byte +#define sio_getc __console_rx_byte static void sio_init(void) { - int divisor = 115200 / SIO_SPEED; - int lcs = 3; - outb(0x00, SIO_PORT + UART_IER); - outb(0x01, SIO_PORT + UART_FCR); - outb(0x03, SIO_PORT + UART_MCR); - outb(0x80 | lcs, SIO_PORT + UART_LCR); - outb(divisor & 0xff, SIO_PORT + UART_DLL); - outb((divisor >> 8) & 0xff, SIO_PORT + UART_DLM); - outb(lcs, SIO_PORT + UART_LCR); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } +#if 0 static void sio_putc(u8 data) { while (!(inb(SIO_PORT + UART_LSR) & 0x20)) ; @@ -69,6 +71,7 @@ static u8 sio_getc(void) #endif return val; } +#endif /* SIO helpers */ diff --git a/src/arch/x86/SerialICE/serialice.c b/src/arch/x86/SerialICE/serialice.c index 35531dc..a503cb9 100644 --- a/src/arch/x86/SerialICE/serialice.c +++ b/src/arch/x86/SerialICE/serialice.c @@ -18,15 +18,27 @@ */ #include -#include -#include + +//#define use_coreboot_stuff 1 +#ifdef use_coreboot_stuff +#include +#include +#define _rdmsr(addr, key) rdmsr(addr) +#define _wrmsr(addr, msr, key) wrmsr(addr, msr) +#define cpuid_eax(eax, ecx) cpuid_eax(eax) +#define cpuid_ebx(eax, ecx) cpuid_ebx(eax) +#define cpuid_ecx(eax, ecx) cpuid_ecx(eax) +#define cpuid_edx(eax, ecx) cpuid_edx(eax) +#else +#include "io.h" +#endif /* SIO functions */ #include "serial.c" /* Hardware specific functions */ -#include "chipset.c" +//#include "chipset.c" /* Accessor functions */ @@ -123,7 +135,7 @@ static void serialice_read_msr(void) sio_putc('\r'); sio_putc('\n'); - msr = rdmsr(addr, key); + msr = _rdmsr(addr, key); sio_put32(msr.hi); sio_putc('.'); sio_put32(msr.lo); @@ -146,7 +158,7 @@ static void serialice_write_msr(void) #ifdef __ROMCC__ /* Cheat to avoid register outage */ - wrmsr(addr, msr, 0x9c5a203a); + _wrmsr(addr, msr, 0x9c5a203a); #else wrmsr(addr, msr, key); #endif @@ -191,21 +203,22 @@ static void serialice_mainboard(void) sio_putc('\r'); sio_putc('\n'); /* must be defined in mainboard/.c */ - sio_putstring(boardname); +// sio_putstring(boardname); } static void serialice_version(void) { - sio_putstring("\nSerialICE v" VERSION " (" __DATE__ ")\n"); +// sio_putstring("\nSerialICE v" VERSION " (" __DATE__ ")\n"); } -int main(void) +int serialice_main(void) { - chipset_init(); +// chipset_init(); sio_init(); + console_init(); +// serialice_version(); - serialice_version(); while(1) { u16 c; @@ -246,12 +259,14 @@ int main(void) case (('v' << 8)|'i'): // Read version info *vi serialice_version(); break; + case (('q' << 8)|'i'): // quit *qi + goto quits; + break; default: sio_putstring("ERROR\n"); break; } } - - // Never get here: +quits: return 0; } -- 1.7.0.4 From devtadas at gmail.com Mon Jul 4 20:32:52 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Mon, 04 Jul 2011 21:32:52 +0300 Subject: [coreboot] [RFC][PATCH 0/2] SerialICE for coreboot. Message-ID: <1309804372.3293.80.camel@ts-laptop> This is for testing/developing purpose, not for merging. SerialICE in coreboot would be great for developing at least CPUs cache init code. This strategy makes use of early serial functions directly from coreboot tree. This is with example for one board (copy from romstage early serial code for your board). Comments are welcome! Patches (2): SerialICE files, receive function for romcc_console, bootblock_simple example SerialICE patch src/arch/x86/SerialICE/io.h | 195 ++++++++++++++++++++++++ src/arch/x86/SerialICE/serial.c | 190 ++++++++++++++++++++++++ src/arch/x86/SerialICE/serialice.c | 272 ++++++++++++++++++++++++++++++++++ src/arch/x86/init/bootblock_simple.c | 2 + src/arch/x86/lib/romcc_console.c | 7 + 5 files changed, 666 insertions(+), 0 deletions(-) create mode 100644 src/arch/x86/SerialICE/io.h create mode 100644 src/arch/x86/SerialICE/serial.c create mode 100644 src/arch/x86/SerialICE/serialice.c From andreas at galauner.de Mon Jul 4 22:42:29 2011 From: andreas at galauner.de (Andreas Galauner) Date: Mon, 04 Jul 2011 22:42:29 +0200 Subject: [coreboot] SPI clock rate Message-ID: <4E1225B5.50907@galauner.de> Hello everybody, I recently started to discover this great project you have here. I want to play with it a bit and port it to an AMD E-350 Motherboard (Sapphire Pure Fusion Mini E-350 - what a name...) I have at home in my spare time. Now I don't think that the development work is much fun, when you have to take the SPI chip off the motherboard, program it, put it back into the board, see the code failing and repeat the whole process ;) So, I had the idea of developing a small Board which contains a USB port and an SPI flash. I first thought about emulating the SPI flash completely by an AVR, but I think the clock rates of the SPI bus are too high to do this. My new approach is a SPI flash which resides on the AVR board which can be multiplexed between the AVR to program it and the motherboard. If I want to test a new BIOS, the AVR puts the motherboard into reset, detaches the flash chip with a multiplexer from the motherboard, programs it, switches it back to the motherboard and let off the reset. Rapid BIOS development :) As an added bonus, I'm thinking about using a USB 2.0 port of an USB-capable AVR as a USB debug interface (those USB debugging cables are expensive for a poor student ;) ) and add a second USB 1.1 port with a MAX3420 for host-communication, but that's step 2. I know that I won't get the full 480MBit/s with this, but I think I can live with that. As I am currently looking for suitable parts, I need to know some basic parameters of the SPI communication. Does anybody of you know what the typical clock rates between the chipset and the flash are? Andy From tsylla at alum.mit.edu Tue Jul 5 01:40:45 2011 From: tsylla at alum.mit.edu (Tom Sylla) Date: Mon, 4 Jul 2011 16:40:45 -0700 Subject: [coreboot] SPI clock rate In-Reply-To: <4E1225B5.50907@galauner.de> References: <4E1225B5.50907@galauner.de> Message-ID: Hello Andreas, Your ideas sound pretty good, but here are a couple of ideas that might make your life easier (and cheaper). I found some high-res pictures of your board on the web, and it looks like that board has a footprint for a SPI programming header (labelled SPI1, between USB1 and the SPI ROM). Board manufacturers put these headers on the board for BIOS development, to do exactly what you are trying to do: in-system SPI flash programming (they are often called in-system programming headers). One common commercial programmer is the SF100 from dediprog: http://www.dediprog.com/SPI-flash-in-circuit-programming You can solder in a header (looks like a 2mm), or even just wires, and connect whatever USB to SPI adapter you want. You just leave the SPI ROM installed, and program it through the header. The header is designed so that even with the board off, the programmer hardware supplies power to the ROM device (only). Your board manual may have the pinout, or just use a meter to figure out how it connects to the SPI ROM. Also, if you haven't seen it yet, take a look at the flashrom project: http://www.flashrom.org/Flashrom which can update flash from an OS, but also supports external programmers like you are trying to achieve: http://www.flashrom.org/FT2232SPI_Programmer To answer your question, SPI clock rates are often about 33MHz, but some devices support faster speeds. You can usually run it much slower though. Tom On Mon, Jul 4, 2011 at 1:42 PM, Andreas Galauner wrote: > Hello everybody, > > I recently started to discover this great project you have here. > I want to play with it a bit and port it to an AMD E-350 Motherboard > (Sapphire Pure Fusion Mini E-350 - what a name...) I have at home in my > spare time. > > Now I don't think that the development work is much fun, when you have > to take the SPI chip off the motherboard, program it, put it back into > the board, see the code failing and repeat the whole process ;) > So, I had the idea of developing a small Board which contains a USB port > and an SPI flash. > I first thought about emulating the SPI flash completely by an AVR, but > I think the clock rates of the SPI bus are too high to do this. My new > approach is a SPI flash which resides on the AVR board which can be > multiplexed between the AVR to program it and the motherboard. > If I want to test a new BIOS, the AVR puts the motherboard into reset, > detaches the flash chip with a multiplexer from the motherboard, > programs it, switches it back to the motherboard and let off the reset. > > Rapid BIOS development :) > > As an added bonus, I'm thinking about using a USB 2.0 port of an > USB-capable AVR as a USB debug interface (those USB debugging cables are > expensive for a poor student ;) ) and add a second USB 1.1 port with a > MAX3420 for host-communication, but that's step 2. > I know that I won't get the full 480MBit/s with this, but I think I can > live with that. > > As I am currently looking for suitable parts, I need to know some basic > parameters of the SPI communication. > Does anybody of you know what the typical clock rates between the > chipset and the flash are? > > Andy > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From peter at stuge.se Tue Jul 5 02:25:56 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 5 Jul 2011 02:25:56 +0200 Subject: [coreboot] SPI clock rate In-Reply-To: <4E1225B5.50907@galauner.de> References: <4E1225B5.50907@galauner.de> Message-ID: <20110705002556.24692.qmail@stuge.se> Andreas Galauner wrote: > I had the idea of developing a small Board which contains a USB port > and an SPI flash. Sure. Or just follow Tom's tip and wire a second SPI bus master directly onto the mainboard. > I first thought about emulating the SPI flash completely by an AVR, What do you mean by AVR? It's relevant for much of what you write. SPI flash must respond with data immediately after the last address bit is received. It's really inconvenient to emulate this. > new approach is a SPI flash which resides on the AVR board Sure. But simpler to just connect directly to the SPI on the mainboard. > If I want to test a new BIOS, the AVR puts the motherboard into reset, > detaches the flash chip with a multiplexer from the motherboard, > programs it, switches it back to the motherboard and let off the reset. Make that: Hold reset Program flash chip on mainboard Release reset > As an added bonus, I'm thinking about using a USB 2.0 port of an > USB-capable AVR as a USB debug interface Note that the Debug Class Device must be able to handle high speed communication ("USB 2.0" is orthogonal to "high speed") and it must be able to handle some out-of-spec transfers. It's not at all certain that your controller does this. > As I am currently looking for suitable parts, I need to know some > basic parameters of the SPI communication. > Does anybody of you know what the typical clock rates between the > chipset and the flash are? Any SPI bus master works, the SPI flashes are generally modern enough to not have a problem with very slow clocks. Since you seem interested in doing development for SPI flashing over USB, you may want to look at the preliminary USB protocol document that me and Stefan Tauner have been working on. Unfortunately it's been idle for a while, but it's nearly complete. The missing parts are the things that can vary between flash chips; erase command sequence and write command sequence. They need to be expressed in some nice way in the protocol. The intended development hardware is the Olimex LPC-P1343 board with an NXP LPC1343 Cortex-M3. Once software works, and once they become available, I want to put a LPC11U00 on a flexpcb cheap enough to be soldered permanently onto mainboards. (NXP promise <$1 for "quantity", probably 1k.) //Peter From peter at stuge.se Tue Jul 5 02:38:56 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 5 Jul 2011 02:38:56 +0200 Subject: [coreboot] SPI clock rate In-Reply-To: <20110705002556.24692.qmail@stuge.se> References: <4E1225B5.50907@galauner.de> <20110705002556.24692.qmail@stuge.se> Message-ID: <20110705003856.25628.qmail@stuge.se> Peter Stuge wrote: > you may want to look at the preliminary USB protocol document > that me and Stefan Tauner have been working on. http://titanpad.com/x8M9ZvNeMN //Peter From andreas at galauner.de Tue Jul 5 02:41:21 2011 From: andreas at galauner.de (Andreas Galauner) Date: Tue, 05 Jul 2011 02:41:21 +0200 Subject: [coreboot] SPI clock rate In-Reply-To: <20110705002556.24692.qmail@stuge.se> References: <4E1225B5.50907@galauner.de> <20110705002556.24692.qmail@stuge.se> Message-ID: <4E125DB1.7070108@galauner.de> On 7/5/11 2:25 AM, Peter Stuge wrote: > Andreas Galauner wrote: >> I had the idea of developing a small Board which contains a USB port >> and an SPI flash. > > Sure. Or just follow Tom's tip and wire a second SPI bus master > directly onto the mainboard. > Yep, I just found the pinheader. Seems to be 1.27x1.27mm. I also created a support ticket for the pinout on Sapphire's website. It would be nice if they give that to me, but I really doubt it. I'll try to measure the pinout tomorrow with a multimeter. >> I first thought about emulating the SPI flash completely by an AVR, > > What do you mean by AVR? It's relevant for much of what you write. Oh, sorry. I mean those Atmel AVR microcontrollers. I have a few of them lying around here and wanted to give them some new lifes apart from laying in my part box. > SPI flash must respond with data immediately after the last address > bit is received. It's really inconvenient to emulate this. > > >> new approach is a SPI flash which resides on the AVR board > > Sure. But simpler to just connect directly to the SPI on the > mainboard. > > >> If I want to test a new BIOS, the AVR puts the motherboard into reset, >> detaches the flash chip with a multiplexer from the motherboard, >> programs it, switches it back to the motherboard and let off the reset. > > Make that: > > Hold reset > Program flash chip on mainboard > Release reset > I'll try to figure out the pinout tomorow. And try to read the flash with flashrom and a bus pirate > >> As an added bonus, I'm thinking about using a USB 2.0 port of an >> USB-capable AVR as a USB debug interface > > Note that the Debug Class Device must be able to handle high speed > communication ("USB 2.0" is orthogonal to "high speed") and it must > be able to handle some out-of-spec transfers. It's not at all certain > that your controller does this. > Yes, I know. And I just saw that my microcontrollers only do full speed and the specification requires high speed. So, this isn't possible. > >> As I am currently looking for suitable parts, I need to know some >> basic parameters of the SPI communication. >> Does anybody of you know what the typical clock rates between the >> chipset and the flash are? > > Any SPI bus master works, the SPI flashes are generally modern enough > to not have a problem with very slow clocks. > > Since you seem interested in doing development for SPI flashing over > USB, you may want to look at the preliminary USB protocol document > that me and Stefan Tauner have been working on. Unfortunately it's > been idle for a while, but it's nearly complete. The missing parts > are the things that can vary between flash chips; erase command > sequence and write command sequence. They need to be expressed in > some nice way in the protocol. The intended development hardware is > the Olimex LPC-P1343 board with an NXP LPC1343 Cortex-M3. Once > software works, and once they become available, I want to put a > LPC11U00 on a flexpcb cheap enough to be soldered permanently onto > mainboards. (NXP promise <$1 for "quantity", probably 1k.) I haven't done very much with SPI flashes until now. I know how the physical protocol works and used it a few times in some smaller microcontroller projects, but I definetely would want to take a look at it. And the development board is easily available and cheap in Germany. Cool. Andreas From peter at stuge.se Tue Jul 5 03:02:05 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 5 Jul 2011 03:02:05 +0200 Subject: [coreboot] SPI clock rate In-Reply-To: <4E125DB1.7070108@galauner.de> References: <4E1225B5.50907@galauner.de> <20110705002556.24692.qmail@stuge.se> <4E125DB1.7070108@galauner.de> Message-ID: <20110705010205.27403.qmail@stuge.se> Andreas Galauner wrote: > Yep, I just found the pinheader. Seems to be 1.27x1.27mm. > I also created a support ticket for the pinout on Sapphire's website. > It would be nice if they give that to me, but I really doubt it. Did you check that it's not documented in the manual already? > I'll try to measure the pinout tomorrow with a multimeter. Sure, that will work fine. Each pin will be directly connected to a pin on the flash chip. > > What do you mean by AVR? It's relevant for much of what you write. > > Oh, sorry. I mean those Atmel AVR microcontrollers. Yes Atmel, but "AVR" says nothing about which family of devices you mean. If it's the wee small 8-bit ones I wouldn't bother, on the other hand if you have a toolchain then sure, why not! > I haven't done very much with SPI flashes until now. I know how the > physical protocol works and used it a few times in some smaller > microcontroller projects, but I definetely would want to take a > look at it. It's fairly simple. Pick up a flash chip datasheet and you've actually already got mostly all you need to know. The flashrom source code can also help, but be careful to not get unneccessarily confused by the code to deal with different types of SPI bus masters in there. > And the development board is easily available and cheap in Germany. Yup. What city are you in? //Peter From andreas at galauner.de Tue Jul 5 03:21:40 2011 From: andreas at galauner.de (Andreas Galauner) Date: Tue, 05 Jul 2011 03:21:40 +0200 Subject: [coreboot] SPI clock rate In-Reply-To: <20110705010205.27403.qmail@stuge.se> References: <4E1225B5.50907@galauner.de> <20110705002556.24692.qmail@stuge.se> <4E125DB1.7070108@galauner.de> <20110705010205.27403.qmail@stuge.se> Message-ID: <4E126724.1020703@galauner.de> On 7/5/11 3:02 AM, Peter Stuge wrote: > Andreas Galauner wrote: >> Yep, I just found the pinheader. Seems to be 1.27x1.27mm. >> I also created a support ticket for the pinout on Sapphire's website. >> It would be nice if they give that to me, but I really doubt it. > > Did you check that it's not documented in the manual already? > Yes. It's not in there. They labled the POST-Code display, they have huge tables of really cool POST code error message explanations and on one pciture of the POST display there even is a header on those SPI pins installed, but there is nothing about the pinout. > >> I'll try to measure the pinout tomorrow with a multimeter. > > Sure, that will work fine. Each pin will be directly connected to a > pin on the flash chip. > I'm just asking myself all the time what to do with the supply lines. If the board is without power or in standby, I obviously need to supply power (assuming that there is a VCC line on the header), but if it is on and I just pull the reset line before starting the programming, this sounds a bad idea to me. So the user needs to specify, if he wants to supply power or not, right? > >>> What do you mean by AVR? It's relevant for much of what you write. >> >> Oh, sorry. I mean those Atmel AVR microcontrollers. > > Yes Atmel, but "AVR" says nothing about which family of devices you > mean. If it's the wee small 8-bit ones I wouldn't bother, on the > other hand if you have a toolchain then sure, why not! > I think I'll get one of those Olimex boards. I always wanted to do something with ARM CPUs and it makes porting the firmware to your suggested final device much easier. Nice idea, BTW. > >> I haven't done very much with SPI flashes until now. I know how the >> physical protocol works and used it a few times in some smaller >> microcontroller projects, but I definetely would want to take a >> look at it. > > It's fairly simple. Pick up a flash chip datasheet and you've > actually already got mostly all you need to know. The flashrom source > code can also help, but be careful to not get unneccessarily confused > by the code to deal with different types of SPI bus masters in there. > I just had a look at some datasheets. > >> And the development board is easily available and cheap in Germany. > > Yup. What city are you in? Aachen or Cologne. Choose one ;) Andreas From diracshore at gmail.com Tue Jul 5 06:10:42 2011 From: diracshore at gmail.com (Thom Lauret) Date: Tue, 05 Jul 2011 00:10:42 -0400 Subject: [coreboot] Coreboot on the Thinkpad T61p ? Message-ID: <1309839042.2032.2.camel@cube> Has anyone succeeded installing coreboot onto a Lenovo Thinkpad T61/p ? I see it has been achieved on a T60. Thank You Thom From gerrit at coreboot.org Tue Jul 5 10:19:05 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 5 Jul 2011 10:19:05 +0200 Subject: [coreboot] New patch to review: f3a72e8 libpayload: fix wborder() References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/84 -gerrit commit f3a72e8244185a3d9226febac68739e11bb3a350 Author: Patrick Georgi Date: Tue Mar 15 12:34:04 2011 +0100 libpayload: fix wborder() wborder didn't provide default characters to draw a border. Change-Id: Ib746ed16be341598fd9fa1f1b7577606d1abd9e5 Signed-off-by: Patrick Georgi --- payloads/libpayload/curses/tinycurses.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/curses/tinycurses.c b/payloads/libpayload/curses/tinycurses.c index 4d3e8e1..fb492b6 100644 --- a/payloads/libpayload/curses/tinycurses.c +++ b/payloads/libpayload/curses/tinycurses.c @@ -584,6 +584,15 @@ int wborder(WINDOW *win, chtype ls, chtype rs, chtype ts, chtype bs, { int x, y; + if (ls == 0) ls = ACS_VLINE; + if (rs == 0) rs = ACS_VLINE; + if (ts == 0) ts = ACS_HLINE; + if (bs == 0) bs = ACS_HLINE; + if (tl == 0) tl = ACS_ULCORNER; + if (tr == 0) tr = ACS_URCORNER; + if (bl == 0) bl = ACS_LLCORNER; + if (br == 0) br = ACS_LRCORNER; + for(y = 0; y <= win->_maxy; y++) { if (y == 0) { From gerrit at coreboot.org Tue Jul 5 10:19:05 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 5 Jul 2011 10:19:05 +0200 Subject: [coreboot] New patch to review: 8f68886 libpayload: Implement strlcpy References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/85 -gerrit commit 8f688867d3237a6aa78cb1afa4d9ab4747b49275 Author: Patrick Georgi Date: Fri Mar 11 09:34:23 2011 +0100 libpayload: Implement strlcpy Change-Id: Ibd339957690afe2cded46895c3088eba87f0ffd1 Signed-off-by: Patrick Georgi --- payloads/libpayload/include/string.h | 10 ++++++- payloads/libpayload/libc/Makefile.inc | 1 + payloads/libpayload/libc/strlcpy.c | 51 +++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/include/string.h b/payloads/libpayload/include/string.h index 88054e0..9e4f791 100644 --- a/payloads/libpayload/include/string.h +++ b/payloads/libpayload/include/string.h @@ -55,7 +55,6 @@ int strncasecmp(const char *s1, const char *s2, size_t maxlen); char *strncpy(char *d, const char *s, size_t n); char *strcpy(char *d, const char *s); char *strncat(char *d, const char *s, size_t n); -size_t strlcat(char *d, const char *s, size_t n); char *strcat(char *d, const char *s); char *strchr(const char *s, int c); char *strrchr(const char *s, int c); @@ -68,4 +67,13 @@ char* strtok(char *str, const char *delim); char* strtok_r(char *str, const char *delim, char **ptr); /** @} */ +/** + * @defgroup string OpenBSD based safe string functions + * @{ + */ +size_t strlcpy(char *d, const char *s, size_t n); +size_t strlcat(char *d, const char *s, size_t n); +/** @} */ + + #endif diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index 4ec2a02..e5c626f 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -33,6 +33,7 @@ libc-$(CONFIG_LIBC) += memory.c ctype.c ipchecksum.c lib.c libc-$(CONFIG_LIBC) += rand.c time.c exec.c libc-$(CONFIG_LIBC) += readline.c getopt_long.c sysinfo.c libc-$(CONFIG_LIBC) += args.c strings.c +libc-$(CONFIG_LIBC) += strlcpy.c # should be moved to coreboot directory libc-$(CONFIG_LAR) += lar.c diff --git a/payloads/libpayload/libc/strlcpy.c b/payloads/libpayload/libc/strlcpy.c new file mode 100644 index 0000000..d32b659 --- /dev/null +++ b/payloads/libpayload/libc/strlcpy.c @@ -0,0 +1,51 @@ +/* $OpenBSD: strlcpy.c,v 1.11 2006/05/05 15:27:38 millert Exp $ */ + +/* + * Copyright (c) 1998 Todd C. Miller + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include + +/* + * Copy src to string dst of size siz. At most siz-1 characters + * will be copied. Always NUL terminates (unless siz == 0). + * Returns strlen(src); if retval >= siz, truncation occurred. + */ +size_t +strlcpy(char *dst, const char *src, size_t siz) +{ + char *d = dst; + const char *s = src; + size_t n = siz; + + /* Copy as many bytes as will fit */ + if (n != 0) { + while (--n != 0) { + if ((*d++ = *s++) == '\0') + break; + } + } + + /* Not enough room in dst, add NUL and traverse rest of src */ + if (n == 0) { + if (siz != 0) + *d = '\0'; /* NUL-terminate dst */ + while (*s++) + ; + } + + return(s - src - 1); /* count does not include NUL */ +} From gerrit at coreboot.org Tue Jul 5 10:27:19 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 5 Jul 2011 10:27:19 +0200 Subject: [coreboot] New patch to review: 0cda4b8 libpayload: Provide atol(), malloc.h References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/86 -gerrit commit 0cda4b86f6b9aa1dd8acdd733bca92d801627717 Author: Patrick Georgi Date: Fri May 27 15:31:52 2011 +0200 libpayload: Provide atol(), malloc.h Change-Id: I807ca061115146a6851eef481eb881b279fba8e1 Signed-off-by: Patrick Georgi --- payloads/libpayload/include/malloc.h | 1 + payloads/libpayload/include/stdlib.h | 1 + payloads/libpayload/libc/string.c | 5 +++++ 3 files changed, 7 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/include/malloc.h b/payloads/libpayload/include/malloc.h new file mode 100644 index 0000000..c8b49f2 --- /dev/null +++ b/payloads/libpayload/include/malloc.h @@ -0,0 +1 @@ +#include diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index a106607..6fb73ad 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -120,6 +120,7 @@ void *memalign(size_t align, size_t size); */ long int strtol(const char *s, char **nptr, int base); unsigned long int strtoul(const char *s, char **nptr, int base); +long atol(const char *nptr); /** @} */ diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index 2e0a558..8c6ea99 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -473,6 +473,11 @@ long int strtol(const char *ptr, char **endptr, int base) return ret * negative; } +long atol(const char *nptr) +{ + return strtol(nptr, NULL, 10); +} + /** * Convert the initial portion of a string into an unsigned int * @param ptr A pointer to the string to convert From gerrit at coreboot.org Tue Jul 5 10:27:20 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Tue, 5 Jul 2011 10:27:20 +0200 Subject: [coreboot] New patch to review: 6b83829 libpayload: Don't declare mouse support in tinycurses References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/87 -gerrit commit 6b8382926be735a0c14c7ff516f0a390df4f1708 Author: Patrick Georgi Date: Thu Mar 10 14:53:54 2011 +0100 libpayload: Don't declare mouse support in tinycurses Change-Id: Id1ff3d85617e3ec063ce332cf13920dfbbb7cf26 Signed-off-by: Patrick Georgi --- payloads/libpayload/curses/tinycurses.c | 2 ++ payloads/libpayload/include/curses.h | 6 +++++- payloads/libpayload/include/curses.priv.h | 2 ++ 3 files changed, 9 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/curses/tinycurses.c b/payloads/libpayload/curses/tinycurses.c index fb492b6..fe6e7de 100644 --- a/payloads/libpayload/curses/tinycurses.c +++ b/payloads/libpayload/curses/tinycurses.c @@ -286,7 +286,9 @@ int endwin(void) return ERR; SP->_endwin = TRUE; +#ifdef NCURSES_MOUSE_VERSION SP->_mouse_wrap(SP); +#endif // _nc_screen_wrap(); // _nc_mvcur_wrap(); /* wrap up cursor addressing */ // return reset_shell_mode(); diff --git a/payloads/libpayload/include/curses.h b/payloads/libpayload/include/curses.h index 1859f02..0c97941 100644 --- a/payloads/libpayload/include/curses.h +++ b/payloads/libpayload/include/curses.h @@ -58,7 +58,7 @@ /* * Identify the mouse encoding version. */ -#define NCURSES_MOUSE_VERSION 1 +// #define NCURSES_MOUSE_VERSION 1 /* * Definitions to facilitate DLL's. @@ -1495,6 +1495,7 @@ extern NCURSES_EXPORT(const char *) _nc_viswibuf(const wint_t *); /* mouse interface */ +#ifdef NCURSES_MOUSE_VERSION #if NCURSES_MOUSE_VERSION > 1 #define NCURSES_MOUSE_MASK(b,m) ((m) << (((b) - 1) * 5)) #else @@ -1591,6 +1592,7 @@ extern NCURSES_EXPORT(bool) wmouse_trafo (const WINDOW*, int*, int*, bool); extern NCURSES_EXPORT(bool) mouse_trafo (int*, int*, bool); /* generated */ #define mouse_trafo(y,x,to_screen) wmouse_trafo(stdscr,y,x,to_screen) +#endif /* other non-XSI functions */ @@ -1616,7 +1618,9 @@ extern NCURSES_EXPORT(char *) _tracecchar_t2 (int, const cchar_t *); #define _tracech_t _tracechtype #define _tracech_t2 _tracechtype2 #endif +#ifdef NCURSES_MOUSE_VERSION extern NCURSES_EXPORT(char *) _tracemouse (const MEVENT *); +#endif extern NCURSES_EXPORT(void) trace (const unsigned int); /* trace masks */ diff --git a/payloads/libpayload/include/curses.priv.h b/payloads/libpayload/include/curses.priv.h index 594b4da..78b7ff3 100644 --- a/payloads/libpayload/include/curses.priv.h +++ b/payloads/libpayload/include/curses.priv.h @@ -514,6 +514,7 @@ struct screen { #define _nc_idlok SP->_nc_sp_idlok #define _nc_idcok SP->_nc_sp_idcok +#ifdef NCURSES_MOUSE_VERSION /* * These are the data that support the mouse interface. */ @@ -531,6 +532,7 @@ struct screen { NCURSES_CONST char *_mouse_xtermcap; /* string to enable/disable mouse */ MEVENT _mouse_events[EV_MAX]; /* hold the last mouse event seen */ MEVENT *_mouse_eventp; /* next free slot in event queue */ +#endif #if USE_GPM_SUPPORT bool _mouse_gpm_loaded; From juhe at iki.fi Tue Jul 5 18:15:26 2011 From: juhe at iki.fi (Juhana Helovuo) Date: Tue, 05 Jul 2011 19:15:26 +0300 Subject: [coreboot] SPI clock rate In-Reply-To: <4E1225B5.50907@galauner.de> References: <4E1225B5.50907@galauner.de> Message-ID: <4E13389E.6040106@iki.fi> Andreas Galauner wrote: > So, I had the idea of developing a small Board which contains a USB port > and an SPI flash. > I first thought about emulating the SPI flash completely by an AVR, but > I think the clock rates of the SPI bus are too high to do this. My new > approach is a SPI flash which resides on the AVR board which can be > multiplexed between the AVR to program it and the motherboard. > If I want to test a new BIOS, the AVR puts the motherboard into reset, > detaches the flash chip with a multiplexer from the motherboard, > programs it, switches it back to the motherboard and let off the reset. > > Rapid BIOS development :) Hello Andreas, I agree with you that emulating a SPI ROM chip in software on AVR, or on any microcontroller, is near impossible because of the fast response times required. There is very little time between the last incoming address bit and the expected transmission of the data, if the SPI clock (generated by the mainboard) is in the order of 16...50 MHz. Regarding your idea of multiplexing SPI ROM between mainboard and AVR, some of the work has already been done here: http://www.coreboot.org/InSystemFlasher Perhaps you could use it as a starting point? Best Regards, Juhana Helovuo From svens at stackframe.org Tue Jul 5 19:37:33 2011 From: svens at stackframe.org (Sven Schnelle) Date: Tue, 05 Jul 2011 19:37:33 +0200 Subject: [coreboot] Coreboot on the Thinkpad T61p ? In-Reply-To: <1309839042.2032.2.camel@cube> (Thom Lauret's message of "Tue\, 05 Jul 2011 00\:10\:42 -0400") References: <1309839042.2032.2.camel@cube> Message-ID: <87y60cfx2a.fsf@begreifnix.stackframe.org> Thom Lauret writes: > Has anyone succeeded installing coreboot onto a Lenovo Thinkpad T61/p ? > I see it has been achieved on a T60. Unfortunaterly that won't work, as we don't have any documentation for the i965 (crestline) Memory Controller used in that Notebook. Regards, Sven. From devtadas at gmail.com Tue Jul 5 21:43:06 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Tue, 05 Jul 2011 22:43:06 +0300 Subject: [coreboot] ASRock e350m1 problems Message-ID: <1309894986.3293.127.camel@ts-laptop> Hi, just compiled coreboot for e350m1, flashed original flashchip and got this (log attached) everytime I power on or reset my system. Any hints? Thanks, Tadas -------------- next part -------------- coreboot-4.0-r Tue Jul 5 21:01:54 EEST 2011 starting... BSP Family_Model: 00500f10 cpu_init_detectedx = 00000000 Got past sb800_early_setup BSP Family_Model: 00500f10 cpu_init_detectedx = 00000001 Got past sb800_early_setup Got past agesawrapper_amdinitearly coreboot-4.0-r Tue Jul 5 21:01:54 EEST 2011 starting... BSP Family_Model: 00500f10 cpu_init_detectedx = 00000000 Got past sb800_early_setup Got past agesawrapper_amdinitearly EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 7, EventInfo = 4011c00. Param1 = 0, Param2 = 0. Param3 = 0, Param4 = 0. agesawrapper_amdinitpost failed: 7 Got past agesawrapper_amdinitpost From Frank.Vibrans at amd.com Tue Jul 5 22:01:41 2011 From: Frank.Vibrans at amd.com (Vibrans, Frank) Date: Tue, 5 Jul 2011 15:01:41 -0500 Subject: [coreboot] ASRock e350m1 problems In-Reply-To: <1309894986.3293.127.camel@ts-laptop> References: <1309894986.3293.127.camel@ts-laptop> Message-ID: <276EC11373289744A112A8FE6675506702E27140C6@SAUSEXMBP01.amd.com> Yep, you're running into heap issues. The specific error is CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT PRESENT. That may be because the heap allocation is failing early on. I'm currently working on a bunch of F14 code updates that I should be posting in a week or so. A fix to that issue may be in that code. FrankV -----Original Message----- From: Tadas Slotkus [mailto:devtadas at gmail.com] Sent: Tuesday, July 05, 2011 1:43 PM To: coreboot at coreboot.org Cc: Vibrans, Frank; Scott Duplichan Subject: ASRock e350m1 problems Hi, just compiled coreboot for e350m1, flashed original flashchip and got this (log attached) everytime I power on or reset my system. Any hints? Thanks, Tadas From r.marek at assembler.cz Tue Jul 5 23:56:31 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 05 Jul 2011 23:56:31 +0200 Subject: [coreboot] [RFC] NULL pointers checking Message-ID: <4E13888F.9020706@assembler.cz> Hi all, Here is a PoC of NULL pointer dereference checking in coreboot x86. It is surprisingly easy to implement. It uses strange expand down segments, making a data segment from 4KB-4GB (with base 0). It should catch most NULL derefence symbols. Unfortunately we access 0x500 while placing the coreboot tables. The hack in the patch just swaps the ds selector work arounding that. More advanced method would use paging and PAE, first 4MB with 4KB pages rest with 4MB pages identity mapped. We could even mark other than coreboot RAM range as "missing" allowing more fine grained tests what is where accessed. Even the segment hack above could be used to check the stack overflows, but I think we will need in IDT instead of interrupt gate a task gate and set there a exception stack, otherwise it will end very badly while CPU is trying to safe stack yet again during the exception. PS: Qemu does not implement segment limit checking, so just try on real HW. Dont forget to switch off GDB debugging otherwise you wont get human readable exception notice, on the other hand you can try to debug that ;) Thanks, Rudolf -------------- next part -------------- A non-text attachment was scrubbed... Name: check_null.patch Type: text/x-diff Size: 1648 bytes Desc: not available URL: From kevin at koconnor.net Wed Jul 6 03:08:36 2011 From: kevin at koconnor.net (Kevin O'Connor) Date: Tue, 5 Jul 2011 21:08:36 -0400 Subject: [coreboot] [PATCH 0/8] SeaBIOS code to extract config parameters Message-ID: This patch series enables SeaBIOS to pull common config settings from CBFS (on coreboot) or fw_cfg (on QEmu). The series also converts several compile-time settings to this new dynamic system. I choose to place the file names in the "etc/" directory so that it is clear they are configuration settings. On coreboot, a user would do the following to enable a setting: /path/to/seabios/tools/encodeint.py boot-menu-wait 5500 ./build/cbfstool coreboot.rom add boot-menu-wait etc/boot-menu-wait raw ./build/cbfstool coreboot.rom print See the patch descriptions below for the six compile-time settings that are converted. -Kevin Kevin O'Connor (8): Add "romfile" code to assist with extract integer config settings. Replace CONFIG_BOOTMENU_WAIT with dynamic "etc/boot-menu-wait" file. Replace CONFIG_EXTRA_PCI_ROOTS with dynamic "etc/extra-pci-roots" file. Replace CONFIG_PS2_KEYBOARD_SPINUP with "etc/ps2-keyboard-spinup" file. Replace "CONFIG_OPTIONROMS_CHECKSUM" with "etc/optionroms-checksum" file. Replace CONFIG_S3_RESUME_VGA_INIT with "etc/s3-resume-vga-init" file. Replace CONFIG_SCREEN_AND_DEBUG with "etc/screen-and-debug" file. Add utility "tools/encodeint.py" for CBFS config file creation. src/Kconfig | 50 -------------------------------------------------- src/boot.c | 5 ++++- src/optionroms.c | 14 ++++++++++++-- src/output.c | 4 ++-- src/paravirt.c | 19 +++++++++++++++++++ src/paravirt.h | 2 ++ src/pci.c | 8 ++++---- src/ps2port.c | 6 ++++-- src/util.h | 1 + tools/encodeint.py | 21 +++++++++++++++++++++ 10 files changed, 69 insertions(+), 61 deletions(-) create mode 100755 tools/encodeint.py -- 1.7.4.4 From andreas at galauner.de Wed Jul 6 13:23:47 2011 From: andreas at galauner.de (Andreas Galauner) Date: Wed, 06 Jul 2011 13:23:47 +0200 Subject: [coreboot] SPI flashing Message-ID: <4E1445C3.50400@galauner.de> Hello again, as you may have read yesterday, I'm currently trying to play with some in-system SPI flashing and I need some additional advice. I just soldered a Pinheader to an Intel D525MW Motherboard (http://www.dont.ru/i/img_1orig/129310882576.jpg - lower right corner) I'm currently not using, but I'm not sure if I should really connect some hardware to it and pull/push on the SPI lines. I suppose it's generally a bad idea to do this, when the Board is currently operating. If it is completely off, I can supply external power and just flash, right? And what about the reset state? I don't have any schematics of my motherboards, so I don't know if there are pull-up or pull-down resistors, I don't know if the chipset really switches its SPI lines into a Z-state, if it is held in reset and so on. I don't want to let the magic smoke escape from my motherboard ;) The only thing I found out is, that the HOLD# ("pauses" the flash chip) and WP# are connected to VCC over a 150 Ohm resistor, each. 150 Ohm is too low for a pull-up, so these two seem to be for limiting the current. Also the pinout is kind of "weird": 1 #CS 2 #CS 3 SI 4 NC 5 SO 6 VCC 7 SCK 8 GND Why is CS# connected to two pins? The resistance between those two pins is 1 Ohm, so they are connected directly. Interestingly the are connected through a 0 Ohm resistor. Any ideas on that? Are there some kind of "best practices" the vendors have when designing those in-system-SPI-flashing-headers? I mean they have to flash these boards in some way by themselves without sending them to heaven, if there is an SPI header. Any advice is greatly appreciated. Thanks, Andreas From ziltro at ziltro.com Wed Jul 6 23:33:11 2011 From: ziltro at ziltro.com (Andrew Morgan) Date: Wed, 06 Jul 2011 22:33:11 +0100 Subject: [coreboot] SPI flashing In-Reply-To: <4E1445C3.50400@galauner.de> References: <4E1445C3.50400@galauner.de> Message-ID: <4E14D497.3010000@ziltro.com> On 06/07/11 12:23, Andreas Galauner wrote: > Also the pinout is kind of "weird": > 1 #CS > 2 #CS > 3 SI > 4 NC > 5 SO > 6 VCC > 7 SCK > 8 GND > > Why is CS# connected to two pins? The resistance between those two pins > is 1 Ohm, so they are connected directly. Interestingly the are > connected through a 0 Ohm resistor. Any ideas on that? I don't know the answer, I'm just having a guess here. It could be that one of the #CS pins is connected to the flash chip, and the other is connected to the SPI controller (or whatever you call the thing an SPI flash chip is connected to on a computer motherboard). If that were the case then if the 0? link wasn't there you would be able to connect an SPI chip and a switch to that port. The switch would either short pins 1 and 2, to select the internal flash chip, or would connect whichever #CS pin is connected to the SPI controller to the #CS pin on the external SPI flash chip in order to select that chip instead. Does that sound like a possibility? -- Andrew. From scott at notabs.org Thu Jul 7 08:04:08 2011 From: scott at notabs.org (Scott Duplichan) Date: Thu, 7 Jul 2011 01:04:08 -0500 Subject: [coreboot] ASRock e350m1 problems In-Reply-To: <1309894986.3293.127.camel@ts-laptop> References: <1309894986.3293.127.camel@ts-laptop> Message-ID: Tadas Slotkus wrote: ]Hi, ] ]just compiled coreboot for e350m1, flashed original flashchip and got ]this (log attached) everytime I power on or reset my system. Any hints? Hello Tadas, AMD.h shows "EventClass = 2" corresponds to AGESA_BOUNDS_CHK, a warning that does not prevent booting. This is related to memory allocation, as Frank pointed out. Your log file stops with: EventLog: EventClass = 7, EventInfo = 4011c00. "EventClass = 7" is an unrecoverable error, according to amd.h. Searching the source code for 4011c00 finds: #define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs have been found I assume you have DIMMs installed, and the production BIOS confirms they are good. Though I believe the SPD addressing is correct for both slots, testing both single DIMM configurations is worthwhile. If the DIMMs work with the production BIOS but not with your BIOS, it is possible that you are using low cost modules that do not have a valid SPD checksum. The coreboot project is configured to validate the SPD checksum, while the Asrock production BIOS is configured to ignore the SPD checksum. To test your coreboot using the DIMM SPD checksum ignore option, change BLDCFG_IGNORE_SPD_CHECKSUM in buildopts.c and try it that way. Thanks, Scott From andrew.goodbody at tadpole.com Thu Jul 7 11:35:53 2011 From: andrew.goodbody at tadpole.com (Andrew Goodbody) Date: Thu, 07 Jul 2011 02:35:53 -0700 Subject: [coreboot] SPI flashing In-Reply-To: <4E14D497.3010000@ziltro.com> References: <4E1445C3.50400@galauner.de> <4E14D497.3010000@ziltro.com> Message-ID: <4E157DF9.50509@tadpole.com> Andrew Morgan wrote: > On 06/07/11 12:23, Andreas Galauner wrote: >> Also the pinout is kind of "weird": >> 1 #CS >> 2 #CS >> 3 SI >> 4 NC >> 5 SO >> 6 VCC >> 7 SCK >> 8 GND >> >> Why is CS# connected to two pins? The resistance between those two pins >> is 1 Ohm, so they are connected directly. Interestingly the are >> connected through a 0 Ohm resistor. Any ideas on that? > > I don't know the answer, I'm just having a guess here. > It could be that one of the #CS pins is connected to the flash chip, and > the other is connected to the SPI controller (or whatever you call the > thing an SPI flash chip is connected to on a computer motherboard). If > that were the case then if the 0? link wasn't there you would be able to > connect an SPI chip and a switch to that port. The switch would either > short pins 1 and 2, to select the internal flash chip, or would connect > whichever #CS pin is connected to the SPI controller to the #CS pin on > the external SPI flash chip in order to select that chip instead. > > Does that sound like a possibility? Very likely. Also I would expect that #4 NC is not NC at all, it just does not go to the SPI device. It could very well be some way to allow safe programming of the onboard SPI device such as by putting the board into reset. Andrew From gerrit at coreboot.org Thu Jul 7 12:04:16 2011 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Thu, 7 Jul 2011 12:04:16 +0200 Subject: [coreboot] New patch to review: f530383 libpayload: Add qsort() References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/88 -gerrit commit f53038334f203008b625669404794bbaa4dd9d8e Author: Patrick Georgi Date: Thu Jul 7 12:02:10 2011 +0200 libpayload: Add qsort() It's taken from OpenBSD and thus appropriately licensed (and reasonably tested). Change-Id: I5767600c9865d39e56c220b52e045f3501875b98 Signed-off-by: Patrick Georgi --- payloads/libpayload/include/stdlib.h | 2 + payloads/libpayload/libc/Makefile.inc | 1 + payloads/libpayload/libc/qsort.c | 162 +++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index 6fb73ad..52162fe 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -142,4 +142,6 @@ void exit(int status) __attribute__ ((noreturn)); /** @} */ +void qsort(void *aa, size_t n, size_t es, int (*cmp)(const void *, const void *)); + #endif diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index e5c626f..0dab8c1 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -34,6 +34,7 @@ libc-$(CONFIG_LIBC) += rand.c time.c exec.c libc-$(CONFIG_LIBC) += readline.c getopt_long.c sysinfo.c libc-$(CONFIG_LIBC) += args.c strings.c libc-$(CONFIG_LIBC) += strlcpy.c +libc-$(CONFIG_LIBC) += qsort.c # should be moved to coreboot directory libc-$(CONFIG_LAR) += lar.c diff --git a/payloads/libpayload/libc/qsort.c b/payloads/libpayload/libc/qsort.c new file mode 100644 index 0000000..f28449f --- /dev/null +++ b/payloads/libpayload/libc/qsort.c @@ -0,0 +1,162 @@ +/* $OpenBSD: qsort.c,v 1.11 2010/02/08 11:04:07 otto Exp $ */ +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include + +static __inline char *med3(char *, char *, char *, int (*)(const void *, const void *)); +static __inline void swapfunc(char *, char *, size_t, int); + +#define min(a, b) (a) < (b) ? a : b + +/* + * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function". + */ +#define swapcode(TYPE, parmi, parmj, n) { \ + size_t i = (n) / sizeof (TYPE); \ + TYPE *pi = (TYPE *) (parmi); \ + TYPE *pj = (TYPE *) (parmj); \ + do { \ + TYPE t = *pi; \ + *pi++ = *pj; \ + *pj++ = t; \ + } while (--i > 0); \ +} + +#define SWAPINIT(a, es) swaptype = ((char *)a - (char *)0) % sizeof(long) || \ + es % sizeof(long) ? 2 : es == sizeof(long)? 0 : 1; + +static __inline void +swapfunc(char *a, char *b, size_t n, int swaptype) +{ + if (swaptype <= 1) + swapcode(long, a, b, n) + else + swapcode(char, a, b, n) +} + +#define swap(a, b) \ + if (swaptype == 0) { \ + long t = *(long *)(a); \ + *(long *)(a) = *(long *)(b); \ + *(long *)(b) = t; \ + } else \ + swapfunc(a, b, es, swaptype) + +#define vecswap(a, b, n) if ((n) > 0) swapfunc(a, b, n, swaptype) + +static __inline char * +med3(char *a, char *b, char *c, int (*cmp)(const void *, const void *)) +{ + return cmp(a, b) < 0 ? + (cmp(b, c) < 0 ? b : (cmp(a, c) < 0 ? c : a )) + :(cmp(b, c) > 0 ? b : (cmp(a, c) < 0 ? a : c )); +} + +void +qsort(void *aa, size_t n, size_t es, int (*cmp)(const void *, const void *)) +{ + char *pa, *pb, *pc, *pd, *pl, *pm, *pn; + int cmp_result, swaptype, swap_cnt; + size_t d, r; + char *a = aa; + +loop: SWAPINIT(a, es); + swap_cnt = 0; + if (n < 7) { + for (pm = (char *)a + es; pm < (char *) a + n * es; pm += es) + for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0; + pl -= es) + swap(pl, pl - es); + return; + } + pm = (char *)a + (n / 2) * es; + if (n > 7) { + pl = (char *)a; + pn = (char *)a + (n - 1) * es; + if (n > 40) { + d = (n / 8) * es; + pl = med3(pl, pl + d, pl + 2 * d, cmp); + pm = med3(pm - d, pm, pm + d, cmp); + pn = med3(pn - 2 * d, pn - d, pn, cmp); + } + pm = med3(pl, pm, pn, cmp); + } + swap(a, pm); + pa = pb = (char *)a + es; + + pc = pd = (char *)a + (n - 1) * es; + for (;;) { + while (pb <= pc && (cmp_result = cmp(pb, a)) <= 0) { + if (cmp_result == 0) { + swap_cnt = 1; + swap(pa, pb); + pa += es; + } + pb += es; + } + while (pb <= pc && (cmp_result = cmp(pc, a)) >= 0) { + if (cmp_result == 0) { + swap_cnt = 1; + swap(pc, pd); + pd -= es; + } + pc -= es; + } + if (pb > pc) + break; + swap(pb, pc); + swap_cnt = 1; + pb += es; + pc -= es; + } + if (swap_cnt == 0) { /* Switch to insertion sort */ + for (pm = (char *) a + es; pm < (char *) a + n * es; pm += es) + for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0; + pl -= es) + swap(pl, pl - es); + return; + } + + pn = (char *)a + n * es; + r = min(pa - (char *)a, pb - pa); + vecswap(a, pb - r, r); + r = min(pd - pc, pn - pd - es); + vecswap(pb, pn - r, r); + if ((r = pb - pa) > es) + qsort(a, r / es, es, cmp); + if ((r = pd - pc) > es) { + /* Iterate rather than recurse to save stack space */ + a = pn - r; + n = r / es; + goto loop; + } +/* qsort(pn - r, r / es, es, cmp);*/ +} From andreas at galauner.de Thu Jul 7 12:54:58 2011 From: andreas at galauner.de (Andreas Galauner) Date: Thu, 07 Jul 2011 12:54:58 +0200 Subject: [coreboot] SPI flashing In-Reply-To: <4E157DF9.50509@tadpole.com> References: <4E1445C3.50400@galauner.de> <4E14D497.3010000@ziltro.com> <4E157DF9.50509@tadpole.com> Message-ID: <4E159082.8000603@galauner.de> On 7/7/11 11:35 AM, Andrew Goodbody wrote: > Also I would expect that #4 NC is not NC at all, it just > does not go to the SPI device. It could very well be some way to allow > safe programming of the onboard SPI device such as by putting the board > into reset. I doubt that. There is no Pin which could lead anywhere ;) I looked into the NM10 datasheet, which at least indicates, that CS# is input and output. And it seems that the chipset detects if some other SPI master pulls CS# to low. NM10 Express datasheet, page 58: >> SPI Chip Select: This chip select signal is also used as the SPI bus >> request signal. If that is the case, this pin is open-drain with an external pull-up. But I don't know what the board does, when it detects this condition. Perhaps it switches MISO, MOSI and SCK into a Z-State. Also, there is the SPI_ARB pin on the chipset. According to the datasheet it is used for the "shared flash" feature. I couldn't find any information about "shared flash", but I think this pin is used by a jumper to start a recovery mode on the board to reflash the BIOS in case of a previous failure. I connected my Bus Pirate yesterday, but I didn't get any data out of the flash. I'm just on a way to some place where I have an oscilloscope and logic analyzer to have some more fun :) - Andreas From gerrit at coreboot.org Thu Jul 7 13:25:54 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 7 Jul 2011 13:25:54 +0200 Subject: [coreboot] Patch merged into master: 1bab8b9 Run 'git fetch' in SeaBIOS only when really needed References: Message-ID: the following patch was just integrated into master: commit 1bab8b961b845ea1c6a3d9074bc5474675579101 Author: Cristian M??gheru??an-Stanciu Date: Tue Jun 7 15:03:14 2011 +0200 Run 'git fetch' in SeaBIOS only when really needed This allows coreboot to compile without Internet connectivity Change-Id: I969471e44e417f127fdc8744e868211500acee3e Signed-off-by: Cristian M??gheru??an-Stanciu See http://review.coreboot.org/11 for details. -gerrit From gerrit at coreboot.org Thu Jul 7 15:25:48 2011 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Thu, 7 Jul 2011 15:25:48 +0200 Subject: [coreboot] New patch to review: 87c40a8 T60: handle EC events in SMM if ACPI is disabled References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/89 -gerrit commit 87c40a816d41d4953c093decd8ac137235919226 Author: Sven Schnelle Date: Thu Jun 23 19:12:25 2011 +0200 T60: handle EC events in SMM if ACPI is disabled Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/acpi/video.asl | 4 + src/mainboard/lenovo/t60/devicetree.cb | 1 + src/mainboard/lenovo/t60/mainboard.c | 3 +- src/mainboard/lenovo/t60/mainboard_smi.c | 119 +++++++++++++++++++++++++++++- src/mainboard/lenovo/t60/smi.h | 2 + 5 files changed, 126 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t60/acpi/video.asl b/src/mainboard/lenovo/t60/acpi/video.asl index c2f9dfb..9a458e9 100644 --- a/src/mainboard/lenovo/t60/acpi/video.asl +++ b/src/mainboard/lenovo/t60/acpi/video.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include "smi.h" + Device (DSPC) { Name (_ADR, 0x00020001) @@ -31,6 +33,7 @@ Device (DSPC) Method(BRTD, 0, NotSerialized) { + Trap(SMI_BRIGHTNESS_DOWN) Store(BRTC, Local0) if (LGreater (Local0, 15)) { @@ -41,6 +44,7 @@ Device (DSPC) Method(BRTU, 0, NotSerialized) { + Trap(SMI_BRIGHTNESS_UP) Store (BRTC, Local0) if (LLess(Local0, 0xff)) { diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 9d7a414..3615e59 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -66,6 +66,7 @@ chip northbridge/intel/i945 register "sata_ahci" = "0x0" register "gpe0_en" = "0x11000006" + register "alt_gp_smi_en" = "0x1000" device pci 1b.0 on # Audio Cnotroller subsystemid 0x17aa 0x2010 diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 371085b..2b8c5fe 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -61,7 +61,8 @@ static void mainboard_enable(device_t dev) } /* set dock status led */ - ec_write(0x0c, inb(0x164c) & 8 ? 0x88 : 0x08); + ec_write(0x0c, 0x08); + ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) { printk(BIOS_INFO, "failed to get cmos_defaults_loaded"); diff --git a/src/mainboard/lenovo/t60/mainboard_smi.c b/src/mainboard/lenovo/t60/mainboard_smi.c index 30c2420..4a0b506 100644 --- a/src/mainboard/lenovo/t60/mainboard_smi.c +++ b/src/mainboard/lenovo/t60/mainboard_smi.c @@ -24,10 +24,12 @@ #include #include #include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" #include #include "dock.h" #include "smi.h" +#define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */ /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -38,7 +40,28 @@ static void mainboard_smm_init(void) printk(BIOS_DEBUG, "initializing SMI\n"); /* Enable 0x1600/0x1600 register pair */ ec_set_bit(0x00, 0x05); - ec_set_ports(0x1604, 0x1600); +} + +static void mainboard_smi_brightness_down(void) +{ + u8 *bar; + if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); + *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0; + if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10) + *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10; + } +} + +static void mainboard_smi_brightness_up(void) +{ + u8 *bar; + if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, *(bar+LVTMA_BL_MOD_LEVEL)); + *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; + if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) + *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; + } } int mainboard_io_trap_handler(int smif) @@ -55,18 +78,29 @@ int mainboard_io_trap_handler(int smif) dlpc_init(); if (!dock_connect()) { /* set dock LED to indicate status */ - ec_write(0x0c, 0x88); + ec_write(0x0c, 0x08); + ec_write(0x0c, 0x89); } else { /* blink dock LED to indicate failure */ ec_write(0x0c, 0xc8); + ec_write(0x0c, 0x09); } break; case SMI_DOCK_DISCONNECT: dock_disconnect(); + ec_write(0x0c, 0x09); ec_write(0x0c, 0x08); break; + case SMI_BRIGHTNESS_UP: + mainboard_smi_brightness_up(); + break; + + case SMI_BRIGHTNESS_DOWN: + mainboard_smi_brightness_down(); + break; + default: return 0; } @@ -76,3 +110,84 @@ int mainboard_io_trap_handler(int smif) return 1; } +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch(event) { + /* brightness up */ + case 0x14: + mainboard_smi_brightness_up(); + break; + /* brightness down */ + case 0x15: + mainboard_smi_brightness_down(); + break; + /* Fn-F9 Key */ + case 0x18: + /* power loss */ + case 0x27: + /* undock event */ + case 0x50: + mainboard_io_trap_handler(SMI_DOCK_DISCONNECT); + break; + /* dock event */ + case 0x37: + mainboard_io_trap_handler(SMI_DOCK_CONNECT); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u16 gpi) +{ + if (gpi & (1 << 12)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_apm_cnt(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + default: + break; + } + return 0; +} + diff --git a/src/mainboard/lenovo/t60/smi.h b/src/mainboard/lenovo/t60/smi.h index f89b6bd..f8e8a7c 100644 --- a/src/mainboard/lenovo/t60/smi.h +++ b/src/mainboard/lenovo/t60/smi.h @@ -22,5 +22,7 @@ #define SMI_DOCK_CONNECT 0x01 #define SMI_DOCK_DISCONNECT 0x02 +#define SMI_BRIGHTNESS_UP 0x03 +#define SMI_BRIGHTNESS_DOWN 0x04 #endif From gerrit at coreboot.org Thu Jul 7 15:47:30 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 7 Jul 2011 15:47:30 +0200 Subject: [coreboot] Patch merged into master: 87c40a8 T60: handle EC events in SMM if ACPI is disabled References: Message-ID: the following patch was just integrated into master: commit 87c40a816d41d4953c093decd8ac137235919226 Author: Sven Schnelle Date: Thu Jun 23 19:12:25 2011 +0200 T60: handle EC events in SMM if ACPI is disabled Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554 Signed-off-by: Sven Schnelle See http://review.coreboot.org/89 for details. -gerrit From corey.osgood at gmail.com Thu Jul 7 14:53:24 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Thu, 7 Jul 2011 08:53:24 -0400 Subject: [coreboot] SPI flashing In-Reply-To: <4E159082.8000603@galauner.de> References: <4E1445C3.50400@galauner.de> <4E14D497.3010000@ziltro.com> <4E157DF9.50509@tadpole.com> <4E159082.8000603@galauner.de> Message-ID: On Thu, Jul 7, 2011 at 6:54 AM, Andreas Galauner wrote: > On 7/7/11 11:35 AM, Andrew Goodbody wrote: >> Also I would expect that #4 NC is not NC at all, it just >> does not go to the SPI device. It could very well be some way to allow >> safe programming of the onboard SPI device such as by putting the board >> into reset. > I doubt that. There is no Pin which could lead anywhere ;) > > I looked into the NM10 datasheet, which at least indicates, that CS# is > input and output. And it seems that the chipset detects if some other > SPI master pulls CS# to low. > > NM10 Express datasheet, page 58: >>> SPI Chip Select: This chip select signal is also used as the SPI bus >>> request signal. > > If that is the case, this pin is open-drain with an external pull-up. > But I don't know what the board does, when it detects this condition. > Perhaps it switches MISO, MOSI and SCK into a Z-State. On my NM10 board, I looked into in-system programming, but Carl-Daniel convinced me that there was too much that could go wrong. Instead, I have a small board I built that connects all the pins of 2 different flash chips to the board, except CS# is switched so that the active chip is hooked to CS# on the board, the inactive chip's CS# pin is hooked to VCC via a set of 4 opticouples and a DPDT switch (this was a suggestion from Carl-Daniel and Stepan). You could probably hook CS# with a diode to each chip, then just switch VCC, but I didn't want to fry anything I then have debian set up to boot only to single user mode, pull a flash image off the network, and flash the chip, and if the flash succeeds, shut down to test the data. Since I'm using two different model flash chips (I don't remember the model #s of the top of my head), the script uses flashrom -c [chipname], so if I don't flip the switch in time, it will fail and wait instead of overwriting the stock BIOS. It takes about a minute if I get the chip switched during powerup to do the complete cycle. I could probably shave more time off that with a customized kernel and startup scripts, but so far it's been acceptable enough that it hasn't been worth the trouble. The next evolution of this will probably be hooking a USB hub, USB->parallel adapter (to do switching and check power light status), and USB->serial adapter up to my dd-wrt powered router, and having the entire process scripted, which would allow me to work entirely wirelessly or even remotely from my laptop. But, first I need to get the board back from Zotac's RMA department (unrelated issue, I've had problems with the memory slots ever since I got it, finally DIMM1 gave out entirely and DIMM2 is a pain to get to work). I've also had some luck with SerialICE, you may want to consider it as an alternative. Once the board gets back, I need to figure out how to disasseble the stock BIOS to bypass the keyboard wait, then I might be able to get some info on memory init. BTW, just curious, have you had any luck getting the datasheets from Intel that cover memory init? Or did you even bother trying? HTH -Corey From gerrit at coreboot.org Thu Jul 7 16:07:20 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 7 Jul 2011 16:07:20 +0200 Subject: [coreboot] Patch merged into master: fc9dd35 Fix lint-002-build-dir-handling References: Message-ID: the following patch was just integrated into master: commit fc9dd354ea48dfe132326f0b9d6ebece3c021bb8 Author: Patrick Georgi Date: Sat Jul 2 16:21:31 2011 +0200 Fix lint-002-build-dir-handling That lint test requires some Kconfig defaults and uses allyesconfig for that. Unfortunately that also draws in ccache and scanbuild support, which significantly change the behaviour of the toplevel Makefile. Notably, the ccache support breaks if no ccache is installed. Change-Id: I17cbb7974be33fc077e5cbd5fb616a5b00a47d97 Signed-off-by: Patrick Georgi See http://review.coreboot.org/80 for details. -gerrit From andreas at galauner.de Thu Jul 7 17:17:11 2011 From: andreas at galauner.de (Andreas Galauner) Date: Thu, 07 Jul 2011 17:17:11 +0200 Subject: [coreboot] SPI flashing In-Reply-To: References: <4E1445C3.50400@galauner.de> <4E14D497.3010000@ziltro.com> <4E157DF9.50509@tadpole.com> <4E159082.8000603@galauner.de> Message-ID: <4E15CDF7.8060004@galauner.de> On 7/7/11 2:53 PM, Corey Osgood wrote: > On my NM10 board, I looked into in-system programming, but Carl-Daniel > convinced me that there was too much that could go wrong. Well, I just read the Chip identification in-system with my bus pirate: SPI> [0x9f,r,r,r] /CS ENABLED WRITE: 0x9F READ: 0xFF READ: 0xC2 READ: 0x20 /CS DISABLED Looks good so far and the board isn't fried ;) It works while the board is in standby. I'm driving the pins directly with 3,3V and GND. No open-drain or something. I saw on the oscilloscope that, when using open-drain mode, the SCK line floats. So, there doesn't seem to be an external pull-down/-up resistor and the internal seems to be deactivated. The only weird thing is that I need to read 3 Bytes and not 2 as stated in the datasheet of the SPI flash, but I don't care about that right now. Also flashrom doesn't work with the buspirate. I'll have to look into this. > BTW, just curious, have you had any luck getting the datasheets from > Intel that cover memory init? Or did you even bother trying? No, the flashing is the first thing I'm doing with this board, sorry. -Andreas From stefan.tauner at student.tuwien.ac.at Thu Jul 7 20:25:59 2011 From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner) Date: Thu, 7 Jul 2011 20:25:59 +0200 Subject: [coreboot] SPI flashing In-Reply-To: <4E1445C3.50400@galauner.de> References: <4E1445C3.50400@galauner.de> Message-ID: <201107071826.p67IQ2BP020420@mail2.student.tuwien.ac.at> On Wed, 06 Jul 2011 13:23:47 +0200 Andreas Galauner wrote: > Hello again, > as you may have read yesterday, I'm currently trying to play with some > in-system SPI flashing and I need some additional advice. hello andreas you may wanna look at the flashrom wiki page about in-system programming: http://flashrom.org/ISP i wrote the most important stuff that i am aware of in there. if you (or anybody else without wiki access) think anything is missing, just drop me a mail. i should add the tip with standby mode probably. that one is new to me (although pretty obvious :) we are talking about S3 here i guess? -- Kind regards/Mit freundlichen Gr??en, Stefan Tauner From gerrit at coreboot.org Thu Jul 7 22:29:19 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 7 Jul 2011 22:29:19 +0200 Subject: [coreboot] Patch merged into master: f3a72e8 libpayload: fix wborder() References: Message-ID: the following patch was just integrated into master: commit f3a72e8244185a3d9226febac68739e11bb3a350 Author: Patrick Georgi Date: Tue Mar 15 12:34:04 2011 +0100 libpayload: fix wborder() wborder didn't provide default characters to draw a border. Change-Id: Ib746ed16be341598fd9fa1f1b7577606d1abd9e5 Signed-off-by: Patrick Georgi See http://review.coreboot.org/84 for details. -gerrit From gerrit at coreboot.org Thu Jul 7 22:29:36 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 7 Jul 2011 22:29:36 +0200 Subject: [coreboot] Patch merged into master: 8f68886 libpayload: Implement strlcpy References: Message-ID: the following patch was just integrated into master: commit 8f688867d3237a6aa78cb1afa4d9ab4747b49275 Author: Patrick Georgi Date: Fri Mar 11 09:34:23 2011 +0100 libpayload: Implement strlcpy Change-Id: Ibd339957690afe2cded46895c3088eba87f0ffd1 Signed-off-by: Patrick Georgi See http://review.coreboot.org/85 for details. -gerrit From gerrit at coreboot.org Thu Jul 7 22:29:53 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 7 Jul 2011 22:29:53 +0200 Subject: [coreboot] Patch merged into master: 0cda4b8 libpayload: Provide atol(), malloc.h References: Message-ID: the following patch was just integrated into master: commit 0cda4b86f6b9aa1dd8acdd733bca92d801627717 Author: Patrick Georgi Date: Fri May 27 15:31:52 2011 +0200 libpayload: Provide atol(), malloc.h Change-Id: I807ca061115146a6851eef481eb881b279fba8e1 Signed-off-by: Patrick Georgi See http://review.coreboot.org/86 for details. -gerrit From gerrit at coreboot.org Thu Jul 7 22:30:07 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 7 Jul 2011 22:30:07 +0200 Subject: [coreboot] Patch merged into master: 6b83829 libpayload: Don't declare mouse support in tinycurses References: Message-ID: the following patch was just integrated into master: commit 6b8382926be735a0c14c7ff516f0a390df4f1708 Author: Patrick Georgi Date: Thu Mar 10 14:53:54 2011 +0100 libpayload: Don't declare mouse support in tinycurses Change-Id: Id1ff3d85617e3ec063ce332cf13920dfbbb7cf26 Signed-off-by: Patrick Georgi See http://review.coreboot.org/87 for details. -gerrit From devtadas at gmail.com Fri Jul 8 01:02:22 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Fri, 08 Jul 2011 02:02:22 +0300 Subject: [coreboot] ASRock e350m1 problems In-Reply-To: References: <1309894986.3293.127.camel@ts-laptop> Message-ID: <1310079742.8900.12.camel@ts-laptop> Hi, thank you all for the quick reply. > If the DIMMs work with the production BIOS but not with your BIOS, it is > possible that you are using low cost modules that do not have a valid > SPD checksum. The coreboot project is configured to validate the SPD > checksum, while the Asrock production BIOS is configured to ignore the > SPD checksum. To test your coreboot using the DIMM SPD checksum ignore > option, change BLDCFG_IGNORE_SPD_CHECKSUM in buildopts.c and try it that > way. > I just tried that with fresh new tree, but the output remains the same. (except build timestamps...). The RAM is one dimm: PATRIOT PSD32G13332H Desktop Memory Device Signature Line (DDR3 SDRAM,2GB,1333MHz(PC3-10600),CL9,256 x 64,DIMM 240-pin,Unbuffered) Thanks, Tadas From dhendrix at google.com Fri Jul 8 01:26:06 2011 From: dhendrix at google.com (David Hendricks) Date: Thu, 7 Jul 2011 16:26:06 -0700 Subject: [coreboot] ASRock e350m1 problems In-Reply-To: <1310079742.8900.12.camel@ts-laptop> References: <1309894986.3293.127.camel@ts-laptop> <1310079742.8900.12.camel@ts-laptop> Message-ID: On Thu, Jul 7, 2011 at 4:02 PM, Tadas Slotkus wrote: > Hi, > > thank you all for the quick reply. > > > If the DIMMs work with the production BIOS but not with your BIOS, it is > > possible that you are using low cost modules that do not have a valid > > SPD checksum. The coreboot project is configured to validate the SPD > > checksum, while the Asrock production BIOS is configured to ignore the > > SPD checksum. To test your coreboot using the DIMM SPD checksum ignore > > option, change BLDCFG_IGNORE_SPD_CHECKSUM in buildopts.c and try it that > > way. > > > > I just tried that with fresh new tree, but the output remains the same. > (except build timestamps...). > > The RAM is one dimm: > PATRIOT PSD32G13332H Desktop Memory Device Signature Line (DDR3 > SDRAM,2GB,1333MHz(PC3-10600),CL9,256 x 64,DIMM 240-pin,Unbuffered) > Just to completely rule out the bad SPD idea, can you please dump the SPD content when you boot with the production BIOS? i2cdump output (ASCII) or raw output from sysfs would be great. Then we can plug it into bc and confirm that the checksum is correct. This would also be a good way to confirm that the SPD addresses are correct in Coreboot, and rule out the possibility that ASRock changed SPD addressing between board revisions... -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -------------- next part -------------- An HTML attachment was scrubbed... URL: From devtadas at gmail.com Fri Jul 8 15:52:42 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Fri, 08 Jul 2011 16:52:42 +0300 Subject: [coreboot] ASRock e350m1 problems In-Reply-To: References: <1309894986.3293.127.camel@ts-laptop> <1310079742.8900.12.camel@ts-laptop> Message-ID: <1310133162.3003.11.camel@ts-laptop> > Just to completely rule out the bad SPD idea, can you please dump the > SPD content when you boot with the production BIOS? i2cdump output > (ASCII) or raw output from sysfs would be great. Then we can plug it > into bc and confirm that the checksum is correct. This would also be a > good way to confirm that the SPD addresses are correct in Coreboot, > and rule out the possibility that ASRock changed SPD addressing > between board revisions... Attaching /sys/bus/i2c/drivers/eeprom/0-0050/eeprom as hex file + i2cdump output -------------- next part -------------- No size specified (using byte-data access) WARNING! This program can confuse your I2C bus, cause data loss and worse! I will probe file /dev/i2c-0, address 0x50, mode byte Continue? [Y/n] 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: 92 10 0b 02 02 11 00 09 03 52 01 08 0c 00 3c 00 ??????.??R???.<. 10: 6c 78 6b 30 6b 11 1f 8c d0 02 3c 3c 00 f0 03 0d lxk0k?????<<.??? 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 30: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 01 01 ............???? 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 70: 00 00 00 00 00 85 02 02 11 11 07 00 00 00 dc 3c .....??????...?< 80: 50 53 44 33 32 47 31 33 33 33 32 00 00 00 00 00 PSD32G13332..... 90: 00 00 00 00 00 00 02 31 34 30 30 31 30 30 30 33 ......?140010003 a0: 31 36 30 30 39 00 00 00 00 00 00 00 00 00 00 00 16009........... b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -------------- next part -------------- A non-text attachment was scrubbed... Name: eeprom.hex Type: text/x-hex Size: 256 bytes Desc: not available URL: From scott at notabs.org Fri Jul 8 20:00:30 2011 From: scott at notabs.org (Scott Duplichan) Date: Fri, 8 Jul 2011 13:00:30 -0500 Subject: [coreboot] ASRock e350m1 problems In-Reply-To: <1310133162.3003.11.camel@ts-laptop> References: <1309894986.3293.127.camel@ts-laptop><1310079742.8900.12.camel@ts-laptop> <1310133162.3003.11.camel@ts-laptop> Message-ID: <36AA234F06654198B86955810D07AA76@asusp67> Tadas Slotkus wrote: ]> Just to completely rule out the bad SPD idea, can you please dump the ]> SPD content when you boot with the production BIOS? i2cdump output ]> (ASCII) or raw output from sysfs would be great. Then we can plug it ]> into bc and confirm that the checksum is correct. This would also be a ]> good way to confirm that the SPD addresses are correct in Coreboot, ]> and rule out the possibility that ASRock changed SPD addressing ]> between board revisions... ] ]Attaching /sys/bus/i2c/drivers/eeprom/0-0050/eeprom as hex file ]+ i2cdump output Hello Tadas, Thanks for the data. I think DIMM SPD check bytes are OK. This SPD has bit zero of byte zero set, which means the crc covers the first 117 bytes instead of the first 126 bytes. The old simnow I have seems to not handle this case. The original log file you sent also suggests no SPD check byte problem. A check byte fail creates a error record like this: EventLog: EventClass = 5, EventInfo = 4011200. Param1 = 0, Param2 = 0. Param3 = 0, Param4 = 0. In addition, your experiment with disabling the check byte confirmation did not let it boot. It seems like it might not be able to read SPD at all. It is possible your DIMM has SMBus signaling difficulty when run at 400 KHz. You could try running the SMBus at the default frequency (93750 KHz) by removing the last statement in function setupFch in file dimmSpd.c: static void setupFch (int ioBase) { writePmReg (0x2D, ioBase >> 8); writePmReg (0x2C, ioBase | 1); writePmReg (0x29, 0x80); writePmReg (0x28, 0x61); __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz } If that doesn't solve the problem, I would add some code to log each SPD byte as it is read. Thanks, Scott From gerrit at coreboot.org Sat Jul 9 01:03:36 2011 From: gerrit at coreboot.org (Cristian Măgherușan-Stanciu (cristi.magherusan@gmail.com)) Date: Sat, 9 Jul 2011 01:03:36 +0200 Subject: [coreboot] Patch set updated: ad3e986 Fix memory size reporting on AMD family 14h systems for >= 4GB References: Message-ID: Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/48 -gerrit commit ad3e9864d761f3b4ab95447d3fbc313cec19306d Author: Cristian M?gheru?an-Stanciu Date: Fri Jul 8 22:41:12 2011 +0000 Fix memory size reporting on AMD family 14h systems for >= 4GB Applying Scott Duplichan's fix for memory >=4GB Adjusted it to the new directory structure (agesa_wrapper was renamed to just agesa). Boot-tested and confirmed to work, on my board Linux can now access the whole RAM. Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19 Signed-off-by: Scott Duplichan Acked-by: Marshall Buschman Signed-off-by: Cristian M?gheru?an-Stanciu --- src/northbridge/amd/agesa/family14/northbridge.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 78ba2da..e38500d 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -652,8 +652,8 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); d = get_dram_base_mask(0); if (d.mask & 1) { - basek = ((resource_t)(d.base)) << 8; - limitk = (resource_t)((d.mask << 8) | 0xFFFFFF); + basek = ((resource_t)((u64)d.base)) << 8; + limitk = (resource_t)(((u64)d.mask << 8) | 0xFFFFFF); printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk); /* Convert these values to multiples of 1K for ease of math. */ From gerrit at coreboot.org Sat Jul 9 01:51:42 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sat, 9 Jul 2011 01:51:42 +0200 Subject: [coreboot] Patch merged into master: ad3e986 Fix memory size reporting on AMD family 14h systems for >= 4GB References: Message-ID: the following patch was just integrated into master: commit ad3e9864d761f3b4ab95447d3fbc313cec19306d Author: Cristian M??gheru??an-Stanciu Date: Fri Jul 8 22:41:12 2011 +0000 Fix memory size reporting on AMD family 14h systems for >= 4GB Applying Scott Duplichan's fix for memory >=4GB Adjusted it to the new directory structure (agesa_wrapper was renamed to just agesa). Boot-tested and confirmed to work, on my board Linux can now access the whole RAM. Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19 Signed-off-by: Scott Duplichan Acked-by: Marshall Buschman Signed-off-by: Cristian M??gheru??an-Stanciu See http://review.coreboot.org/48 for details. -gerrit From r.marek at assembler.cz Sat Jul 9 09:37:01 2011 From: r.marek at assembler.cz (Rudolf Marek) Date: Sat, 09 Jul 2011 09:37:01 +0200 Subject: [coreboot] Hackaton in Prague 2011 In-Reply-To: <1309544985.11759.16.camel@mattotaupa> References: <4DC77D9C.8010804@assembler.cz> <1309544985.11759.16.camel@mattotaupa> Message-ID: <4E18051D.5000804@assembler.cz> Hi, > I am very interested in what you have done and achieved. Could some of > the attendees write something up? That would be awesome. Oh well I thought that someone ELSE will write what we were doing. I had to wrote by myself about FOSDEM too. :) If not then I will write about that soonish. Thanks for a ping. Thanks Rudolf From echelon at free.fr Sat Jul 9 17:04:43 2011 From: echelon at free.fr (Florentin Demetrescu) Date: Sat, 09 Jul 2011 17:04:43 +0200 Subject: [coreboot] Hackaton in Prague 2011 In-Reply-To: <4E18051D.5000804@assembler.cz> References: <4DC77D9C.8010804@assembler.cz> <1309544985.11759.16.camel@mattotaupa> <4E18051D.5000804@assembler.cz> Message-ID: <1310223883.4e186e0b41b41@webmail.free.fr> Hello, I wanted to reply but Rudolph was more swift than me (I'm so lazy these days! .. ;-)), but I can give you my travel impressions.. The hackathon in Prague proceeded very well, the organisation was excellent and we have been well received by Rudolph. I arrived by car from France Friday evening. My journey was approximatively 14 hours from Paris to Prague. Unfortunately for me, it wasn't possible for me to stay 2 full days (so many personal projects pending!!..), so I had to quit early Sunday. The accomodation was in the Masarykova dormitory of the CVUT University of Prague (the University of Rudolph), and it was OK (even if it was "student style" ;-)) On the technical side, Rudolph succeded to reserve a classroom in his University, so we installed our stuff early Saturday and began to work: - Rudolph on the integration of U-Boot with coreboot; - Christi focused mostly on the cleaning and reorganisation of some coreboot code, but I don't remember very well what (Christi can you give more details?) - Sven and Bj?rne worken with the T60 laptop coreboot port (again I'm not sure: can you give more details?); - for Peter I don't remember what was his topic of interest but he helped me very heavily for my board: - my objective was to install coreboot on my new board MA785GMT-UDH2. I had bring with me a Phenom II 1055T CPU with 6 cores. Unfortunately I met big problems because: * the factory BIOS version (F4) wasn't fit for this kind of CPU, so I was unable to boot the board even with the factory BIOS, so no flashrom solution for installing coreboot; * Peter helped me to "socketise" the BIOS chip and Sven helped me with his external programmer, but unfortunately the curent release of coreboot didn' work => it crashed at some stage in early initialisation (romstage.c?) before microcode update if I remember well.. To conclude, globally this hackaton was great for me even if I didn't get great results on the technical side, but the oportunity to meet and work with other coreboot people greatly offsets those technical drawbacks.. Thank you again friends and especially you Rudolph for this great event! Hope I see you soon at the next coreboot hackaton! Florentin PS : a friend of mine gave me a Phenom II with 4 cores so I was able to update the factory BIOS (I installed the F6 revision), and the board boots flawlessly with the factory bios even with my 6 core Phenom II cpu! So it is NOT a power supply problem Rudolph and Peter.. ;-). I didn't had the time to reinstall coreboot and give it a run, but I will do that ASAP! Also I will investigate the problem of the 6 core Phenom II on this board.. Quoting Rudolf Marek : > Hi, > > > I am very interested in what you have done and achieved. Could some of > > the attendees write something up? That would be awesome. > > Oh well I thought that someone ELSE will write what we were doing. I had to > wrote by myself about FOSDEM too. :) > > If not then I will write about that soonish. Thanks for a ping. > > Thanks > Rudolf > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From sfalco at coincident.com Sat Jul 9 17:55:01 2011 From: sfalco at coincident.com (Steven A. Falco) Date: Sat, 09 Jul 2011 11:55:01 -0400 Subject: [coreboot] Question about USB support in libpayload / FILO Message-ID: <4E1879D5.6020602@coincident.com> I am attempting to use FILO and libpayload with an Intel Atom E6XX processor; specifically, the Intel Tunnel Creek development kit. This is a SOC-type processor that has four integrated PCIe links, one of which goes to an Intel IOH (sort of a southbridge). The IOH in turn contains a USB host controller (EHCI/OHCI). Another of the PCIe links goes through a PCIe <-> PCI bridge to a standard PCI slot. Finally, the other two PCIe links go to standard PCIe slots. I want to boot Linux from a Sandisk USB stick, so I first tried inserting the stick into one of the IOH USB ports. When I do that, I get a message: giving up port 1, it's USB1 and FILO appears to hang. The next thing I tried was connecting a NEC USB host controller card to the PCI slot. That one works properly. The Sandisk stick is correctly recognized, and I get: port 2 hosts a USB2 device highspeed device device 0x0781:0x5530 is USB 2.0 (MSC) it uses SCSI transparent command set it uses Bulk-Only Transport protocol using endpoint 81 as in, 2 as out has 1 luns Waiting for device to become ready... ok. spin up. OK. Reading capacity of mass storage device. has 15625216 blocks sized 512b I've also tried connecting a Pericom USB host controller to one of the PCIe slots. It contains a Pericom PI7C9X440SL chip. It gives the same error behavior as does the IOH. So the FILO / libpayload tally at this point is: NEC host bridge works, IOH and Pericom don't. I've also tried an experiment where I boot Linux using the NEC controller, then plug a second Sandisk stick into the IOH controller. Linux has no problem using the IOH USB ports. Linux also has no problem using the Pericom USB ports. I'm trying to instrument the code in ehci_rh_scanport(). I added a number of printf messages. So far, I don't see the problem. Reading some of the port status bits gives me: port power 1, port enable 0, port reset 0, line status 2 The line status of 2 means this is an EHCI device and that an EHCI reset should be done. The code does that, but port_enable apparently stays at 0, which causes a call to ehci_rh_hand_over_port(). That routine prints the "giving up" message, and then the world ends. The one thing I noticed in the code that might be a problem is that bit-fields are used for things like port_enable and port_reset. So to reset the port, the code does: p->port_enable = 0; p->port_reset = 1; mdelay(50); p->port_reset = 0; That means that port_enable and port_reset won't change at the same moment, even though they are in the same register. In contrast, the Linux driver uses temporary variables, such that both bits will change in the same register access. I don't know if that is the problem, but it is one difference I noticed. The Linux code looks like this: } else { ehci_vdbg (ehci, "port %d reset\n", wIndex + 1); temp |= PORT_RESET; temp &= ~PORT_PE; /* * caller must wait, then call GetPortStatus * usb 2.0 spec says 50 ms resets on root */ ehci->reset_done [wIndex] = jiffies + msecs_to_jiffies (50); } ehci_writel(ehci, temp, status_reg); What have other folks experiences been with the EHCI driver in libpayload? Steve From devtadas at gmail.com Sat Jul 9 22:08:06 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Sat, 09 Jul 2011 23:08:06 +0300 Subject: [coreboot] Question about USB support in libpayload / FILO In-Reply-To: <4E1879D5.6020602@coincident.com> References: <4E1879D5.6020602@coincident.com> Message-ID: <1310242086.16207.22.camel@ts-laptop> > What have other folks experiences been with the EHCI driver in > libpayload? > > Steve > Hi, I had problems with USB2.0 expansion card and flash drive attached. It stopped with this log: > 05.830: FILO version 0.6.0 (ts at ts-laptop) Sat Dec 18 23:35:10 EET 2010 > 05.844: 00:07.2 7112:8086.2 UHCI controller > 05.966: 00:0e.2 3104:1106.2 EHCI controller > 05.966: root hub has 4 ports > 05.966: 00:0e.1 3038:1106.1 UHCI controller > 06.094: 00:0e.0 3038:1106.0 UHCI controller > 06.779: port 2 hosts a USB2 device > 06.779: highspeed device > 06.875: maxPacketSize0: 40 > 06.875: device 0x1005:0xb113 is USB 2.0 > 06.881: device has 1 configurations > 36.211: <00> 36.211 indicates power off or reset. Since the controller (EHCI) then was in an "unknown" state, it even was not detected after reset: > 56.057: FILO version 0.6.0 (ts at ts-laptop) Sat Dec 18 23:35:10 EET 2010 > 56.063: 00:07.2 7112:8086.2 UHCI controller > 56.188: 00:0e.1 3038:1106.1 UHCI controller > 56.314: 00:0e.0 3038:1106.0 UHCI controller > 56.585: fullspeed device > 56.679: maxPacketSize0: 40 > 56.679: device 0x1005:0xb113 is USB 2.0 > 56.681: device has 1 configurations > 56.681: device has 1 interfaces > 56.681: #0 has 3 endpoints, interface 8:6, protocol 50 > 56.681: #1: Endpoint 1 (out), max packet size 40, type bulk > 56.681: #2: Endpoint 2 (in), max packet size 40, type bulk > 56.681: #3: Endpoint 3 (in), max packet size 40, type interrupt > 56.681: (MSC) So I got only fullspeed booting :( I didn't managed to find out what caused this hang in the driver. I hope you will be the one who fix this :) Thanks, Tadas From sfalco at coincident.com Sat Jul 9 23:10:14 2011 From: sfalco at coincident.com (Steven A. Falco) Date: Sat, 09 Jul 2011 17:10:14 -0400 Subject: [coreboot] PATCH: Make EHCI root host accesses atomic Message-ID: <4E18C3B6.3080900@coincident.com> Some EHCI controllers misbehave if bits in the portsc register do not change atomically. Thus we use a temporary variable to do a single read-modify-write when changing related bits in the register. The symptom is an incorrect handoff from EHCI to OHCI. Signed-off-by: Steven A. Falco --- I've observed the problem with several EHCI controllers: an Intel Topcliff IOH and a Pericom PI7C9X440SL. With the changes below, both these controllers work properly. Note that several other registers in ehci_private.h are described in terms of separate bits too. I have not changed them because I have not observed any problems with them. diff --git a/payloads/libpayload/drivers/usb/ehci_private.h b/payloads/libpayload/drivers/usb/ehci_private.h index e63a81d..07c1a2f 100644 --- a/payloads/libpayload/drivers/usb/ehci_private.h +++ b/payloads/libpayload/drivers/usb/ehci_private.h @@ -37,8 +37,34 @@ #define FLADJ 0x61 #define FLADJ_framelength(x) (((x)-59488)/16) +#define PORT_WKOC_E (1<<22) +#define PORT_WKDISC_E (1<<21) +#define PORT_WKCONN_E (1<<20) +#define PORT_TEST_PKT (0x4<<16) +#define PORT_LED_OFF (0<<14) +#define PORT_LED_AMBER (1<<14) +#define PORT_LED_GREEN (2<<14) +#define PORT_LED_MASK (3<<14) +#define PORT_OWNER (1<<13) +#define PORT_POWER (1<<12) +#define PORT_LINESTATUS_MASK (3<<10) +#define PORT_LINESTATUS_KSTATE (1<<10) +#define PORT_RESET (1<<8) +#define PORT_SUSPEND (1<<7) +#define PORT_RESUME (1<<6) +#define PORT_OCC (1<<5) +#define PORT_OC (1<<4) +#define PORT_PEC (1<<3) +#define PORT_PE (1<<2) +#define PORT_CSC (1<<1) +#define PORT_CONNECT (1<<0) + typedef union { - u32 val; + volatile u32 val; + // WARNING - some controllers require port_enable and port_reset to + // change atomically. Therefore, using these separate bits is not + // recommended. +#if 0 volatile struct { unsigned long current_conn_status:1; unsigned long conn_status_change:1; @@ -60,6 +86,7 @@ typedef union { unsigned long wake_on_overcurrent_en:1; unsigned long:9; } __attribute__ ((packed)); +#endif } __attribute__ ((packed)) portsc_t; typedef struct { diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index 5eaeeb6..c588a3d 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -54,14 +54,19 @@ static void ehci_rh_hand_over_port (usbdev_t *dev, int port) { volatile portsc_t *p = &(RH_INST(dev)->ports[port]); + volatile u32 tmp; printf("giving up port %x, it's USB1\n", port+1); /* Lowspeed device. Hand over to companion */ - p->port_owner = 1; - do {} while (!p->conn_status_change); + tmp = p->val; + tmp |= PORT_OWNER; + p->val = tmp; + while (!(p->val & PORT_CSC)); /* RW/C register, so clear it by writing 1 */ - p->conn_status_change = 1; + tmp = p->val; + tmp |= PORT_CSC; + p->val = tmp; return; } @@ -69,41 +74,54 @@ static void ehci_rh_scanport (usbdev_t *dev, int port) { volatile portsc_t *p = &(RH_INST(dev)->ports[port]); + volatile u32 tmp; if (RH_INST(dev)->devices[port]!=-1) { printf("Unregister device at port %x\n", port+1); usb_detach_device(dev->controller, RH_INST(dev)->devices[port]); RH_INST(dev)->devices[port]=-1; } /* device connected, handle */ - if (p->current_conn_status) { + if (p->val & PORT_CONNECT) { mdelay(100); - if (p->line_status == 0x1) { + if ((p->val & PORT_LINESTATUS_MASK) == PORT_LINESTATUS_KSTATE) { ehci_rh_hand_over_port(dev, port); return; } - p->port_enable = 0; - p->port_reset = 1; + + /* Remove port_enable, set port_reset. This must be atomic. */ + tmp = p->val; + tmp &= ~PORT_PE; + tmp |= PORT_RESET; + p->val = tmp; + mdelay(50); - p->port_reset = 0; + tmp &= ~PORT_RESET; + p->val = tmp; + /* Wait for flag change to finish. The controller might take a while */ - while (p->port_reset) ; - if (!p->port_enable) { + while(p->val & PORT_RESET) ; + if (!(p->val & PORT_PE)) { ehci_rh_hand_over_port(dev, port); return; } printf("port %x hosts a USB2 device\n", port+1); RH_INST(dev)->devices[port] = usb_attach_device(dev->controller, dev->address, port, 2); } + /* RW/C register, so clear it by writing 1 */ - p->conn_status_change = 1; + tmp = p->val; + tmp |= PORT_CSC; + p->val = tmp; } static int ehci_rh_report_port_changes (usbdev_t *dev) { + volatile portsc_t *p; int i; for (i=0; in_ports; i++) { - if (RH_INST(dev)->ports[i].conn_status_change) + p = &(RH_INST(dev)->ports[i]); + if (p->val & PORT_CSC) return i; } return -1; @@ -121,6 +139,8 @@ ehci_rh_poll (usbdev_t *dev) void ehci_rh_init (usbdev_t *dev) { + volatile portsc_t *p; + volatile u32 tmp; int i; dev->destroy = ehci_rh_destroy; @@ -135,8 +155,11 @@ ehci_rh_init (usbdev_t *dev) RH_INST(dev)->devices = malloc(RH_INST(dev)->n_ports * sizeof(int)); for (i=0; i < RH_INST(dev)->n_ports; i++) { + p = &(RH_INST(dev)->ports[i]); + tmp = p->val; + tmp |= PORT_POWER; + p->val = tmp; RH_INST(dev)->devices[i] = -1; - RH_INST(dev)->ports[i].pp = 1; } dev->address = 0; From sfalco at coincident.com Sat Jul 9 23:14:33 2011 From: sfalco at coincident.com (Steven A. Falco) Date: Sat, 09 Jul 2011 17:14:33 -0400 Subject: [coreboot] PATCH: Warn about unknown USB devices Message-ID: <4E18C4B9.5090305@coincident.com> Print a warning regarding unknown USB controller devices. Signed-off-by: Steven A. Falco --- I have observed a device that claims a USB controller programming interface of 0xfe. I don't know what the device is, but it is helpful to see a warning. So I've changed the individual if() statements to a switch() and added a default case to spit out the warning. diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index f0d5a60..5c2eae6 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -70,40 +70,47 @@ usb_controller_initialize (int bus, int dev, int func) printf ("%02x:%02x.%x %04x:%04x.%d ", bus, dev, func, pciid >> 16, pciid & 0xFFFF, func); - if (prog_if == 0) { - printf ("UHCI controller\n"); + switch(prog_if) { + case 0x00: + printf ("UHCI controller\n"); #ifdef CONFIG_USB_UHCI - uhci_init (addr); + uhci_init (addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif - } - if (prog_if == 0x10) { - printf ("OHCI controller\n"); + break; + + case 0x10: + printf ("OHCI controller\n"); #ifdef CONFIG_USB_OHCI - ohci_init(addr); + ohci_init(addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif + break; - } - if (prog_if == 0x20) { - printf ("EHCI controller\n"); + case 0x20: + printf ("EHCI controller\n"); #ifdef CONFIG_USB_EHCI - ehci_init(addr); + ehci_init(addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif + break; - } - if (prog_if == 0x30) { - printf ("xHCI controller\n"); + case 0x30: + printf ("xHCI controller\n"); #ifdef CONFIG_USB_XHCI - xhci_init(addr); + xhci_init(addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif + break; + default: + printf ("unknown controller %x not supported\n", + prog_if); + break; } } From sfalco at coincident.com Sat Jul 9 23:17:22 2011 From: sfalco at coincident.com (Steven A. Falco) Date: Sat, 09 Jul 2011 17:17:22 -0400 Subject: [coreboot] PATCH: Missing bus address assignment Message-ID: <4E18C562.3090407@coincident.com> The EHCI controller does not set the bus_address field of the controller structure. Other controllers have this assignment, so let's be consistent. Signed-off-by: Steven A. Falco --- diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 3df0477..d979121 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -336,6 +336,7 @@ ehci_init (pcidev_t addr) controller->create_intr_queue = ehci_create_intr_queue; controller->destroy_intr_queue = ehci_destroy_intr_queue; controller->poll_intr_queue = ehci_poll_intr_queue; + controller->bus_address = addr; for (i = 0; i < 128; i++) { controller->devices[i] = 0; } From gerrit at coreboot.org Sun Jul 10 02:34:09 2011 From: gerrit at coreboot.org (Anonymous Coward (kevin@koconnor.net)) Date: Sun, 10 Jul 2011 02:34:09 +0200 Subject: [coreboot] New patch to review: 5176106 Do full flush on uart8250 only at end of printk. References: Message-ID: Anonymous Coward (kevin at koconnor.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/90 -gerrit commit 51761067ec0ded3b8fa73efffc1462f262a94759 Author: Kevin O'Connor Date: Sat Jul 9 20:22:21 2011 -0400 Do full flush on uart8250 only at end of printk. The previous code does a full flush of the uart after every character. Unfortunately, this can cause transmission delays on some serial ports. This patch changes the code so that it does a flush at the end of every printk instead of at the end of every character. This reduces the time it takes to transmit serial messages (up to 9% on my Asrock e350m1 board). It also makes the transmission time more consistent which is important when performing timing tests via serial transmissions. Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70 Signed-off-by: Kevin O'Connor --- src/arch/x86/lib/romstage_console.c | 16 +++++++++++++--- src/console/uart8250_console.c | 6 ++++++ src/include/uart8250.h | 1 + src/lib/uart8250.c | 5 ++++- 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index a5f2e2b..faa8afb 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -48,6 +48,16 @@ static void console_tx_byte(unsigned char byte) #endif } +static void console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_flush(CONFIG_TTYS0_BASE); +#endif +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +} + int do_printk(int msg_level, const char *fmt, ...) { va_list args; @@ -60,8 +70,8 @@ int do_printk(int msg_level, const char *fmt, ...) va_start(args, fmt); i = vtxprintf(console_tx_byte, fmt, args); va_end(args); -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif + + console_tx_flush(); + return i; } diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 4799ca6..330ed68 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -31,6 +31,11 @@ static void ttyS0_tx_byte(unsigned char data) uart8250_tx_byte(CONFIG_TTYS0_BASE, data); } +static void ttyS0_tx_flush(void) +{ + uart8250_tx_flush(CONFIG_TTYS0_BASE); +} + static unsigned char ttyS0_rx_byte(void) { return uart8250_rx_byte(CONFIG_TTYS0_BASE); @@ -44,6 +49,7 @@ static int ttyS0_tst_byte(void) static const struct console_driver uart8250_console __console = { .init = ttyS0_init, .tx_byte = ttyS0_tx_byte, + .tx_flush = ttyS0_tx_flush, .rx_byte = ttyS0_rx_byte, .tst_byte = ttyS0_tst_byte, }; diff --git a/src/include/uart8250.h b/src/include/uart8250.h index bbf2d8c..ee0cd39 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -131,6 +131,7 @@ unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); void uart8250_tx_byte(unsigned base_port, unsigned char data); +void uart8250_tx_flush(unsigned base_port); /* Yes it is silly to have three different uart init functions. But we used to * have three different sets of uart code, so it's an improvement. diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 64e8854..e7ddd0b 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -48,7 +48,10 @@ void uart8250_tx_byte(unsigned base_port, unsigned char data) { uart8250_wait_to_tx_byte(base_port); outb(data, base_port + UART_TBR); - /* Make certain the data clears the fifos */ +} + +void uart8250_tx_flush(unsigned base_port) +{ uart8250_wait_until_sent(base_port); } From gerrit at coreboot.org Sun Jul 10 03:17:19 2011 From: gerrit at coreboot.org (Marshall Buschman (mbuschman@lucidmachines.com)) Date: Sun, 10 Jul 2011 03:17:19 +0200 Subject: [coreboot] New patch to review: 67576b4 ASRock E350M1: ACPI-related BSOD fix References: Message-ID: Marshall Buschman (mbuschman at lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/91 -gerrit commit 67576b4126a4c5be0df8236601ad0728fc1b24fd Author: Scott Duplichan Date: Sat Jul 9 20:14:20 2011 -0500 ASRock E350M1: ACPI-related BSOD fix On installing/starting Windows (tested with Win7 Ultimate) the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error. From Scott Duplichan: To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT must be corrected. The attached patch does this. It uses the older patching method, and not the (possibly preferred) AML generation method. To simplify the patching operation, I moved the AML item 'TOM1' to the start of the SSDT. The patch also includes code to confirm the AML variable TOM1 is at the expected offset before patching. Also tested & working with Linux. Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3 Signed-off-by: Scott Duplichan Acked-by: Marshall Buschman --- src/mainboard/asrock/e350m1/acpi_tables.c | 5 +++++ src/northbridge/amd/agesa/family14/ssdt.asl | 2 +- 2 files changed, 6 insertions(+), 1 deletions(-) diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 20b0dc2..cd0a996 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -185,6 +185,11 @@ unsigned long write_acpi_tables(unsigned long start) memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); current += ssdt->length; memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + + char *position = ssdt; + if (memcmp (position + 50, "TOM1", 4) == 0) + *(u32 *) (position + 55) = __readmsr (0xc001001a); + /* recalculate checksum */ ssdt->checksum = 0; ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); diff --git a/src/northbridge/amd/agesa/family14/ssdt.asl b/src/northbridge/amd/agesa/family14/ssdt.asl index e69012b..1e694db 100644 --- a/src/northbridge/amd/agesa/family14/ssdt.asl +++ b/src/northbridge/amd/agesa/family14/ssdt.asl @@ -30,6 +30,7 @@ DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM14H", "AMD-ACPI", 0x1000) Scope (\_SB.PCI0) { + Name (TOM1, 0xaaaaaaaa) Name (BUSN, Package (0x20) /* HC_NUMS */ { 0x11111111, @@ -264,7 +265,6 @@ DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM14H", "AMD-ACPI", 0x1000) 0x44444444 }) Name (SBLK, 0x11) - Name (TOM1, 0xaaaaaaaa) Name (SBDN, 0xbbbbbbbb) Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */ { From gerrit at coreboot.org Sun Jul 10 03:18:35 2011 From: gerrit at coreboot.org (Anonymous Coward (kevin@koconnor.net)) Date: Sun, 10 Jul 2011 03:18:35 +0200 Subject: [coreboot] Patch set updated: 5f1cfd8 Do full flush on uart8250 only at end of printk. References: Message-ID: Anonymous Coward (kevin at koconnor.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/90 -gerrit commit 5f1cfd8ee9d400f20a5aa30eb50b9afb5e2694db Author: Kevin O'Connor Date: Sat Jul 9 20:22:21 2011 -0400 Do full flush on uart8250 only at end of printk. The previous code does a full flush of the uart after every character. Unfortunately, this can cause transmission delays on some serial ports. This patch changes the code so that it does a flush at the end of every printk instead of at the end of every character. This reduces the time it takes to transmit serial messages (up to 9% on my Asrock e350m1 board). It also makes the transmission time more consistent which is important when performing timing tests via serial transmissions. Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70 Signed-off-by: Kevin O'Connor --- src/arch/x86/lib/romstage_console.c | 19 ++++++++++++++++--- src/console/uart8250_console.c | 6 ++++++ src/console/uart8250mem_console.c | 6 ++++++ src/include/uart8250.h | 2 ++ src/lib/uart8250.c | 5 ++++- src/lib/uart8250mem.c | 5 ++++- 6 files changed, 38 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index a5f2e2b..8adb3ba 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -48,6 +48,19 @@ static void console_tx_byte(unsigned char byte) #endif } +static void console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250MEM + uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_flush(CONFIG_TTYS0_BASE); +#endif +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +} + int do_printk(int msg_level, const char *fmt, ...) { va_list args; @@ -60,8 +73,8 @@ int do_printk(int msg_level, const char *fmt, ...) va_start(args, fmt); i = vtxprintf(console_tx_byte, fmt, args); va_end(args); -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif + + console_tx_flush(); + return i; } diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 4799ca6..330ed68 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -31,6 +31,11 @@ static void ttyS0_tx_byte(unsigned char data) uart8250_tx_byte(CONFIG_TTYS0_BASE, data); } +static void ttyS0_tx_flush(void) +{ + uart8250_tx_flush(CONFIG_TTYS0_BASE); +} + static unsigned char ttyS0_rx_byte(void) { return uart8250_rx_byte(CONFIG_TTYS0_BASE); @@ -44,6 +49,7 @@ static int ttyS0_tst_byte(void) static const struct console_driver uart8250_console __console = { .init = ttyS0_init, .tx_byte = ttyS0_tx_byte, + .tx_flush = ttyS0_tx_flush, .rx_byte = ttyS0_rx_byte, .tst_byte = ttyS0_tst_byte, }; diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index a6968dd..e622ad0 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -36,6 +36,11 @@ static void uartmem_tx_byte(unsigned char data) uart8250_mem_tx_byte(uart_bar, data); } +static void uartmem_tx_flush(void) +{ + uart8250_mem_tx_flush(uart_bar); +} + static unsigned char uartmem_rx_byte(void) { if (!uart_bar) @@ -55,6 +60,7 @@ static int uartmem_tst_byte(void) static const struct console_driver uart8250mem_console __console = { .init = uartmem_init, .tx_byte = uartmem_tx_byte, + .tx_flush = uartmem_tx_flush, .rx_byte = uartmem_rx_byte, .tst_byte = uartmem_tst_byte, }; diff --git a/src/include/uart8250.h b/src/include/uart8250.h index bbf2d8c..4a02179 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -131,6 +131,7 @@ unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); void uart8250_tx_byte(unsigned base_port, unsigned char data); +void uart8250_tx_flush(unsigned base_port); /* Yes it is silly to have three different uart init functions. But we used to * have three different sets of uart code, so it's an improvement. @@ -142,6 +143,7 @@ void uart_init(void); unsigned char uart8250_mem_rx_byte(unsigned base_port); int uart8250_mem_can_rx_byte(unsigned base_port); void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); +void uart8250_mem_tx_flush(unsigned base_port); void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 64e8854..e7ddd0b 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -48,7 +48,10 @@ void uart8250_tx_byte(unsigned base_port, unsigned char data) { uart8250_wait_to_tx_byte(base_port); outb(data, base_port + UART_TBR); - /* Make certain the data clears the fifos */ +} + +void uart8250_tx_flush(unsigned base_port) +{ uart8250_wait_until_sent(base_port); } diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 918308e..e79cb63 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -51,7 +51,10 @@ void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) { uart8250_mem_wait_to_tx_byte(base_port); write8(base_port + UART_TBR, data); - /* Make certain the data clears the FIFOs */ +} + +void uart8250_mem_tx_flush(unsigned base_port) +{ uart8250_mem_wait_until_sent(base_port); } From scott at notabs.org Sun Jul 10 07:37:21 2011 From: scott at notabs.org (Scott Duplichan) Date: Sun, 10 Jul 2011 00:37:21 -0500 Subject: [coreboot] [PATCH] move AMD SB800 early clock setup code to common file Message-ID: <9E3C0B70828D4C0ABF5531FBCE1EE996@asusp67> The attached patch moves the AMD SB800 early clock setup code that is needed for early serial port operation from mainboard/romstage.c to sb800/bootblock.c. This prevents code duplication and simplifies porting. Signed-off-by: Scott Duplichan -------------- next part -------------- A non-text attachment was scrubbed... Name: sb800-bblk.patch Type: application/octet-stream Size: 3146 bytes Desc: not available URL: From gerrit at coreboot.org Sun Jul 10 18:31:29 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 10 Jul 2011 18:31:29 +0200 Subject: [coreboot] Patch merged into master: 67576b4 ASRock E350M1: ACPI-related BSOD fix References: Message-ID: the following patch was just integrated into master: commit 67576b4126a4c5be0df8236601ad0728fc1b24fd Author: Scott Duplichan Date: Sat Jul 9 20:14:20 2011 -0500 ASRock E350M1: ACPI-related BSOD fix On installing/starting Windows (tested with Win7 Ultimate) the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error. From Scott Duplichan: To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT must be corrected. The attached patch does this. It uses the older patching method, and not the (possibly preferred) AML generation method. To simplify the patching operation, I moved the AML item 'TOM1' to the start of the SSDT. The patch also includes code to confirm the AML variable TOM1 is at the expected offset before patching. Also tested & working with Linux. Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3 Signed-off-by: Scott Duplichan Acked-by: Marshall Buschman See http://review.coreboot.org/91 for details. -gerrit From viautbellum at gmail.com Sun Jul 10 23:27:23 2011 From: viautbellum at gmail.com (Aaron P) Date: Sun, 10 Jul 2011 16:27:23 -0500 Subject: [coreboot] Unsupported MB? Message-ID: I've noticed that there are no AOpen motherboards on the list. Is there any possibility of getting coreboot (and SeaBIOS) working on my old AX4BS-V? I'd like to be able to boot the FreeBSD installer via USB, but my BIOS doesn't support booting from it. vendor: AOpen model: AX4BS-V >From CPU-Z: CPU: Pentium 4 Southbridge: Intel 82801BA (ICH2) LPCIO: Winbond W83627HF from EZWinFlash: Flash Type: SST 49LF002A /3.3V -------------- next part -------------- An HTML attachment was scrubbed... URL: From gregg.drwho8 at gmail.com Mon Jul 11 00:18:15 2011 From: gregg.drwho8 at gmail.com (Gregg Levine) Date: Sun, 10 Jul 2011 18:18:15 -0400 Subject: [coreboot] Unsupported MB? In-Reply-To: References: Message-ID: On Sun, Jul 10, 2011 at 5:27 PM, Aaron P wrote: > I've noticed that there are no AOpen motherboards on the list. Is there any > possibility of getting coreboot (and SeaBIOS) working on my old AX4BS-V? I'd > like to be able to boot the FreeBSD installer via USB, but my BIOS doesn't > support booting from it. > > vendor: AOpen > model: AX4BS-V > > From CPU-Z: > CPU: Pentium 4 > Southbridge: Intel 82801BA (ICH2) > LPCIO: Winbond W83627HF > > from EZWinFlash: > Flash Type: SST 49LF002A /3.3V > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Hello! An admirable goal. However to help you better, (much better even) we'll need the information provided on the Wiki regarding your target. That information is found here http://www.coreboot.org/Support and most of what we need to know you've already provided. ----- Gregg C Levine gregg.drwho8 at gmail.com "This signature fought the Time Wars, time and again." From viautbellum at gmail.com Mon Jul 11 04:05:58 2011 From: viautbellum at gmail.com (Aaron P) Date: Sun, 10 Jul 2011 21:05:58 -0500 Subject: [coreboot] Unsupported MB? In-Reply-To: References: Message-ID: Unfortunately, I'm on Windows, so I can't really really use the tools listed there. If necessary, for instance to rebuild coreboot, I have Debian and FreeBSD on a VM, but obviously they can't access information about my system. Most of the information is info I already inadvertently gathered looking for my motherboard model and updating the BIOS. I've done a bit more digging, but I'm having trouble finding the northbridge. On Sun, Jul 10, 2011 at 5:18 PM, Gregg Levine wrote: > On Sun, Jul 10, 2011 at 5:27 PM, Aaron P wrote: > > I've noticed that there are no AOpen motherboards on the list. Is there > any > > possibility of getting coreboot (and SeaBIOS) working on my old AX4BS-V? > I'd > > like to be able to boot the FreeBSD installer via USB, but my BIOS > doesn't > > support booting from it. > > > > vendor: AOpen > > model: AX4BS-V > > > > From CPU-Z: > > CPU: Pentium 4 > > Southbridge: Intel 82801BA (ICH2) > > LPCIO: Winbond W83627HF > > > > from EZWinFlash: > > Flash Type: SST 49LF002A /3.3V > > > > > > -- > > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > > Hello! > An admirable goal. However to help you better, (much better even) > we'll need the information provided on the Wiki regarding your target. > That information is found here http://www.coreboot.org/Support and > most of what we need to know you've already provided. > ----- > Gregg C Levine gregg.drwho8 at gmail.com > "This signature fought the Time Wars, time and again." > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: From gregg.drwho8 at gmail.com Mon Jul 11 05:03:24 2011 From: gregg.drwho8 at gmail.com (Gregg Levine) Date: Sun, 10 Jul 2011 23:03:24 -0400 Subject: [coreboot] Unsupported MB? In-Reply-To: References: Message-ID: On Sun, Jul 10, 2011 at 10:05 PM, Aaron P wrote: > Unfortunately, I'm on Windows, so I can't really really use the tools listed > there. If necessary, for instance to rebuild coreboot, I have Debian and > FreeBSD on a VM, but obviously they can't access information about my > system. Most of the information is info I already inadvertently gathered > looking for my motherboard model and updating the BIOS. > > I've done a bit more digging, but I'm having trouble finding the > northbridge. > > On Sun, Jul 10, 2011 at 5:18 PM, Gregg Levine > wrote: >> >> On Sun, Jul 10, 2011 at 5:27 PM, Aaron P wrote: >> > I've noticed that there are no AOpen motherboards on the list. Is there >> > any >> > possibility of getting coreboot (and SeaBIOS) working on my old AX4BS-V? >> > I'd >> > like to be able to boot the FreeBSD installer via USB, but my BIOS >> > doesn't >> > support booting from it. >> > >> > vendor: AOpen >> > model: AX4BS-V >> > >> > From CPU-Z: >> > CPU: Pentium 4 >> > Southbridge: Intel 82801BA (ICH2) >> > LPCIO: Winbond W83627HF >> > >> > from EZWinFlash: >> > Flash Type: SST 49LF002A /3.3V >> > >> > >> > -- >> > coreboot mailing list: coreboot at coreboot.org >> > http://www.coreboot.org/mailman/listinfo/coreboot >> > >> >> Hello! >> An admirable goal. However to help you better, (much better even) >> we'll need the information provided on the Wiki regarding your target. >> That information is found here http://www.coreboot.org/Support and >> most of what we need to know you've already provided. >> ----- Hello! Oh okay. Do you have the ability to create a bootable CD? The idea is that the information could be gathered via the same tools, while using a Live CD of Debian such as Knoppix or its relatives. ----- Gregg C Levine gregg.drwho8 at gmail.com "This signature fought the Time Wars, time and again." From viautbellum at gmail.com Mon Jul 11 05:35:30 2011 From: viautbellum at gmail.com (Aaron P) Date: Sun, 10 Jul 2011 22:35:30 -0500 Subject: [coreboot] Unsupported MB? In-Reply-To: References: Message-ID: Corey: CPU-Z is one of the tools I've already used, but unfortunately it's only giving me the southbridge. Greg: Not for the next several days, but by that point I can just make a FreeBSD CD. I realize at this point I may just have to wait. On Sun, Jul 10, 2011 at 10:10 PM, Corey Osgood wrote: > On Sun, Jul 10, 2011 at 10:05 PM, Aaron P wrote: > > Unfortunately, I'm on Windows, so I can't really really use the tools > listed > > there. If necessary, for instance to rebuild coreboot, I have Debian and > > FreeBSD on a VM, but obviously they can't access information about my > > system. Most of the information is info I already inadvertently gathered > > looking for my motherboard model and updating the BIOS. > > > > I've done a bit more digging, but I'm having trouble finding the > > northbridge. > > > > On Sun, Jul 10, 2011 at 5:18 PM, Gregg Levine > > wrote: > >> > >> On Sun, Jul 10, 2011 at 5:27 PM, Aaron P wrote: > >> > I've noticed that there are no AOpen motherboards on the list. Is > there > >> > any > >> > possibility of getting coreboot (and SeaBIOS) working on my old > AX4BS-V? > >> > I'd > >> > like to be able to boot the FreeBSD installer via USB, but my BIOS > >> > doesn't > >> > support booting from it. > >> > > >> > vendor: AOpen > >> > model: AX4BS-V > >> > > >> > From CPU-Z: > >> > CPU: Pentium 4 > >> > Southbridge: Intel 82801BA (ICH2) > >> > LPCIO: Winbond W83627HF > >> > > >> > from EZWinFlash: > >> > Flash Type: SST 49LF002A /3.3V > >> > > >> > > >> > -- > >> > coreboot mailing list: coreboot at coreboot.org > >> > http://www.coreboot.org/mailman/listinfo/coreboot > >> > > >> > >> Hello! > >> An admirable goal. However to help you better, (much better even) > >> we'll need the information provided on the Wiki regarding your target. > >> That information is found here http://www.coreboot.org/Support and > >> most of what we need to know you've already provided. > >> ----- > >> Gregg C Levine gregg.drwho8 at gmail.com > >> "This signature fought the Time Wars, time and again." > > CPU-Z (google it) should tell you what the northbridge is, that's the > most important bit at this point. > > -Corey > -------------- next part -------------- An HTML attachment was scrubbed... URL: From corey.osgood at gmail.com Mon Jul 11 05:10:08 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Sun, 10 Jul 2011 23:10:08 -0400 Subject: [coreboot] Unsupported MB? In-Reply-To: References: Message-ID: On Sun, Jul 10, 2011 at 10:05 PM, Aaron P wrote: > Unfortunately, I'm on Windows, so I can't really really use the tools listed > there. If necessary, for instance to rebuild coreboot, I have Debian and > FreeBSD on a VM, but obviously they can't access information about my > system. Most of the information is info I already inadvertently gathered > looking for my motherboard model and updating the BIOS. > > I've done a bit more digging, but I'm having trouble finding the > northbridge. > > On Sun, Jul 10, 2011 at 5:18 PM, Gregg Levine > wrote: >> >> On Sun, Jul 10, 2011 at 5:27 PM, Aaron P wrote: >> > I've noticed that there are no AOpen motherboards on the list. Is there >> > any >> > possibility of getting coreboot (and SeaBIOS) working on my old AX4BS-V? >> > I'd >> > like to be able to boot the FreeBSD installer via USB, but my BIOS >> > doesn't >> > support booting from it. >> > >> > vendor: AOpen >> > model: AX4BS-V >> > >> > From CPU-Z: >> > CPU: Pentium 4 >> > Southbridge: Intel 82801BA (ICH2) >> > LPCIO: Winbond W83627HF >> > >> > from EZWinFlash: >> > Flash Type: SST 49LF002A /3.3V >> > >> > >> > -- >> > coreboot mailing list: coreboot at coreboot.org >> > http://www.coreboot.org/mailman/listinfo/coreboot >> > >> >> Hello! >> An admirable goal. However to help you better, (much better even) >> we'll need the information provided on the Wiki regarding your target. >> That information is found here http://www.coreboot.org/Support and >> most of what we need to know you've already provided. >> ----- >> Gregg C Levine gregg.drwho8 at gmail.com >> "This signature fought the Time Wars, time and again." CPU-Z (google it) should tell you what the northbridge is, that's the most important bit at this point. -Corey From corey.osgood at gmail.com Mon Jul 11 06:35:31 2011 From: corey.osgood at gmail.com (Corey Osgood) Date: Mon, 11 Jul 2011 00:35:31 -0400 Subject: [coreboot] Unsupported MB? In-Reply-To: References: Message-ID: On Sun, Jul 10, 2011 at 11:35 PM, Aaron P wrote: > Corey: > CPU-Z is one of the tools I've already used, but unfortunately it's only > giving me the southbridge. > > Greg: > Not for the next several days, but by that point I can just make a FreeBSD > CD. I realize at this point I may just have to wait. How about a USB flash drive? Is unetbootin an option? -Corey > > On Sun, Jul 10, 2011 at 10:10 PM, Corey Osgood > wrote: >> >> On Sun, Jul 10, 2011 at 10:05 PM, Aaron P wrote: >> > Unfortunately, I'm on Windows, so I can't really really use the tools >> > listed >> > there. If necessary, for instance to rebuild coreboot, I have Debian and >> > FreeBSD on a VM, but obviously they can't access information about my >> > system. Most of the information is info I already inadvertently gathered >> > looking for my motherboard model and updating the BIOS. >> > >> > I've done a bit more digging, but I'm having trouble finding the >> > northbridge. >> > >> > On Sun, Jul 10, 2011 at 5:18 PM, Gregg Levine >> > wrote: >> >> >> >> On Sun, Jul 10, 2011 at 5:27 PM, Aaron P wrote: >> >> > I've noticed that there are no AOpen motherboards on the list. Is >> >> > there >> >> > any >> >> > possibility of getting coreboot (and SeaBIOS) working on my old >> >> > AX4BS-V? >> >> > I'd >> >> > like to be able to boot the FreeBSD installer via USB, but my BIOS >> >> > doesn't >> >> > support booting from it. >> >> > >> >> > vendor: AOpen >> >> > model: AX4BS-V >> >> > >> >> > From CPU-Z: >> >> > CPU: Pentium 4 >> >> > Southbridge: Intel 82801BA (ICH2) >> >> > LPCIO: Winbond W83627HF >> >> > >> >> > from EZWinFlash: >> >> > Flash Type: SST 49LF002A /3.3V >> >> > >> >> > >> >> > -- >> >> > coreboot mailing list: coreboot at coreboot.org >> >> > http://www.coreboot.org/mailman/listinfo/coreboot >> >> > >> >> >> >> Hello! >> >> An admirable goal. However to help you better, (much better even) >> >> we'll need the information provided on the Wiki regarding your target. >> >> That information is found here http://www.coreboot.org/Support and >> >> most of what we need to know you've already provided. >> >> ----- >> >> Gregg C Levine gregg.drwho8 at gmail.com >> >> "This signature fought the Time Wars, time and again." >> >> CPU-Z (google it) should tell you what the northbridge is, that's the >> most important bit at this point. >> >> -Corey > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From gerrit at coreboot.org Mon Jul 11 14:59:43 2011 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Mon, 11 Jul 2011 14:59:43 +0200 Subject: [coreboot] New patch to review: 45a4244 T60: dont use X60 USB init flag References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/92 -gerrit commit 45a424419a5647d5016b1462255b1241988d36df Author: Sven Schnelle Date: Mon Jul 11 14:58:48 2011 +0200 T60: dont use X60 USB init flag ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch initialization. Don't touch it on T60. Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/devicetree.cb | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 3615e59..27ce46c 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -121,7 +121,7 @@ chip northbridge/intel/i945 register "config0" = "0xa6" register "config1" = "0x05" register "config2" = "0xa0" - register "config3" = "0x05" + register "config3" = "0x01" register "beepmask0" = "0xfe" register "beepmask1" = "0x96" From gerrit at coreboot.org Mon Jul 11 15:18:00 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 11 Jul 2011 15:18:00 +0200 Subject: [coreboot] Patch merged into master: 45a4244 T60: dont use X60 USB init flag References: Message-ID: the following patch was just integrated into master: commit 45a424419a5647d5016b1462255b1241988d36df Author: Sven Schnelle Date: Mon Jul 11 14:58:48 2011 +0200 T60: dont use X60 USB init flag ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch initialization. Don't touch it on T60. Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e Signed-off-by: Sven Schnelle See http://review.coreboot.org/92 for details. -gerrit From gerrit at coreboot.org Mon Jul 11 15:24:19 2011 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Mon, 11 Jul 2011 15:24:19 +0200 Subject: [coreboot] New patch to review: 9171c64 T60: enable GPIO before using GPIO I/O port range References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/93 -gerrit commit 9171c64a4c9860c5f1f434956fde6b03cd868917 Author: Sven Schnelle Date: Mon Jul 11 15:22:42 2011 +0200 T60: enable GPIO before using GPIO I/O port range Change-Id: I39369e6f8a39f53f58a4b7fbe357637a79f5b596 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/dock.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index cfaead3..6642bb3 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -132,6 +132,8 @@ static int dock_superio_init(void) dock_write_register(0x07, PC87384_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); + /* enable GPIO */ + dock_write_register(0x30, 0x01); dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP, 0x00); @@ -157,7 +159,6 @@ static int dock_superio_init(void) dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP, 0x00); - outb(0xfd, 0x1620); /* no GPIO events enabled for PORT0 */ outb(0x00, 0x1622); @@ -170,8 +171,7 @@ static int dock_superio_init(void) /* clear GPIO events on PORT1*/ outb(0xff, 0x1627); outb(0x1F, 0x1628); - /* enable GPIO */ - dock_write_register(0x30, 0x01); + outb(0xfd, 0x1620); return 0; } From gerrit at coreboot.org Mon Jul 11 15:50:04 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 11 Jul 2011 15:50:04 +0200 Subject: [coreboot] Patch merged into master: 9171c64 T60: enable GPIO before using GPIO I/O port range References: Message-ID: the following patch was just integrated into master: commit 9171c64a4c9860c5f1f434956fde6b03cd868917 Author: Sven Schnelle Date: Mon Jul 11 15:22:42 2011 +0200 T60: enable GPIO before using GPIO I/O port range Change-Id: I39369e6f8a39f53f58a4b7fbe357637a79f5b596 Signed-off-by: Sven Schnelle See http://review.coreboot.org/93 for details. -gerrit From svn at coreboot.org Mon Jul 11 16:00:02 2011 From: svn at coreboot.org (coreboot tracker) Date: Mon, 11 Jul 2011 16:00:02 +0200 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From pete at akeo.ie Mon Jul 11 19:02:03 2011 From: pete at akeo.ie (Pete Batard) Date: Mon, 11 Jul 2011 18:02:03 +0100 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock Message-ID: <4E1B2C8B.5050001@akeo.ie> Hello all, Having recently followed some of the old discussions regarding a coreboot panic-room (eg. [1], [2]), I have been wondering whether it would be possible to produce a universal panic-room/recovery console implementation on x86, i.e. one that does not necessarily rely on code that is mainboard specific, but is instead able to perform Super I/O and UART detection and init, in a generic fashion (a bit like superiotool or sensors-detect). The main reason for not wanting to go the mainboard-specific route is that there are a lot of motherboards out there where coreboot support is unavailable, especially recent ones, and providing those with at least some form of panic-room support may help with seeing coreboot implemented. The ability to transfer a bare-metal flashrom, SerialICE, or any other kind of payload to CAR (or to RAM, if a platform specific RAM init payload has previously been transferred and run from CAR), through Y-modem, would probably open a few new avenues for coreboot development. This is why I am presenting a Proof of Concept, which I call UBRX, of a near-universal yet *safe* method for detecting and providing a panic-room type serial console, aimed at being included in an x86 BIOS bootblock. My hope is that, should you be interested in such a concept, it could become the base of the coreboot panic-room implementation. Obviously, the focus of this exercise has to do with the safety of the detection, as, if the code that is going to be included in a bona fide BIOS bootblock, emphasis must be placed on making sure that no damage or unwanted stress of any kind, will be incurred on the hardware, even when run at every boot. While this may at first seem like an unreconcilable goal with blanket detection, I believe it is actually possible to solve the problem in a satisfactory way. Thus I hope you can take a look at the proposed solution and decide for yourself if you see technical merit in it. For some insight on how detection can be performed in a manner that is deemed safe, I am also pasting the the 'Detection Primer' section from the UBRX readme at the end of this e-mail. Now, the other claim of the solution that is likely to raise an eyebrow, is of course universality. As you can reasonably expect from knowledge of the various quirks of the Super I/O & early console detection that coreboot implements, there exist cases where a blanket generic detection does not apply easily. Plus, mostly because this is a PoC, I added some limitations on my own. So currently "universality" comes with the following restrictions: * The motherboard must have a physical serial port, provided by a Super I/O chip. Console over USB-RS232 adapters is not supported. * Only 16650 compliant UARTs are supported. * Only AMD and Intel x86 CPUs are supported. No VIA, no Transmeta. * The CPU must support the MMX instruction set (Intel Pentium MMX or later, AMD K6 or later) as we use MMX in lieu of stack. * Only Super I/O chipsets conforming to the ISA PnP specifications, and starting in PnP mode on reset are supported (except WMware compatible) * Some non widespread PnP Super I/O chips with complex config mode (eg. IT8671) have voluntarily been dropped. * Powering up of Super I/O Logical Devices is not currently conducted. We currently assert that UART LDs are powered up by default. * With regards to Super I/O chips that require extra configuration from the Southbridge for LPC bus access, only Intel ICH# (any version that requires it) and AMD SB6x0-SB9x0 are supported. Even with these limitations (most of which could be addressed), I have reason to think that the vast majority of post 2000 PC systems should find their Super I/O and UART properly detected, hence the claim. The big unknown at the moment has to do with nVidia chipsets, since non-NDA datasheets are unavailable for those. The other unknown is whether the current AMD implementation actually works, as I don't have an AMD system to test against. I tested UBRX on 2 Intel platforms (that coreboot does not support), and found that everything ran as expected: one was with a PIII system sporting a 440BX chipset and a W83977TF and the other was a dual core ICH8 with a W83627DHG. Therefore, I would greatly appreciate if people interested could have a look, possibly test the current PoC, and give their thoughts. The current code and downloads for UBRX can be obtained from visiting: http://code.google.com/p/akeo/ If you want to have a look at the main source, you can also do so at: http://code.google.com/p/akeo/source/browse/ubrx/bios.S It is pure x86 assembly, but please see point #3 at the end of this e-mail with regards to that. If you have a GNU compiler that can produce x86 code (either on Linux or Windows - 32 or 64 bit doesn't matter), you should easily be able to produce a BIOS ROM you can flash. See the README for instructions. You can also try with a VMware image, if you don't want to run on actual hardware first: just copy the (default) 512 KB bios.rom generated to your VMware install and add a 'bios440.filename = "bios.rom"' line to your .vmx Once you have an UBRX BIOS running, just set up a NULL-modem cable connection (if using VMware on Windows, you can use com0com to setup a virtual one), set your terminal to 115200 8N1, no hardware handshake, and boot the first machine while maintain the space key pressed in the console. If the detection process worked, you will enter the 'panic-room' console, which currently is limited to just an 'ubrx>' prompt and a serial repeater. Right now, I am especially interested in tests being conducted on AMD hardware to confirm that the AMD LCP/SouthBridge init works. Again, you should be able to test UBRX even if your platform is not supported by coreboot, provided of course that you can reflash your BIOS through external means afterwards (SPI, parallel programmer, etc.). Also, while I have reasons to believe that, as far as providing a console is concerned, doing so in a generic/universal fashion on x86 shouldn't be a problem, one of the questions I have is whether the same can apply for CAR init. I'm new to coreboot and a lot of the romstage.c sources I see seem to perform their own Cache As RAM init. On the other hand [3] seems to indicate that CAR init does not necessarily need to be mainboard specific. Do you see a CAR init as a feature that can be achieved in a generic panic-room (even if it may require provision of a few platform/CPU specific parameters through the serial console)? Or are you aware of major issues that would prevent doing so. I'd say that once we have CAR as well as Y-modem transfer of code to CAR, for execution, the game is pretty much won as far as a panic-room implementation is concerned. Thus, if we can a implement both a generic console detection as well as a generic CAR, we're done. Finally, I'm just going to point out a few items that may be seen as as valid reasons to dismiss UBRX upfront, whereas I don't believe these should really matter: 1. I am aware that there exists a GSoC project for the panic-room [4] but I think this does not touch on the provision of a serial console (yet?). Even then, separate efforts can of course always be merged, which is also why I am producing a PoC rather than a full implementation, and stopping there for the time being. 2. The current license for UBRX is GPLv3 or later (my preference). If you really believe that this will be an issue, I am open to discussion. 3. The source is pure x86 assembly (what's more using Intel syntax rather than the GNU default AT&T), and I have to agree that this will be harder to maintain than say a C source that could be compiled with ROM_CC. On the other hand, the code is intended to be generic, so it does not require duplication/changes for each motherboard and, more importantly, I believe anything that is meant to be part of a semi-permanent bootblock must focus on optimization and size, even if it means a drawback in maintainability, hence the choice of assembly. The current detection process takes less than 2K, which could be optimized further, and leaves enough room for CAR, Y-modem and console functionality in an 8K bootblock. I am doubtful that ROM_CC could include everything we need in 8K. Comments? Questions? Shoot away... Regards, /Pete [1] http://thread.gmane.org/gmane.linux.bios/25740/focus=26022 [2] http://www.coreboot.org/pipermail/coreboot/2010-February/thread.html#55950 [3] http://www.coreboot.org/data/yhlu/cache_as_ram_lb_09142006.pdf [4] http://blogs.coreboot.org/blog/2011/05/09/gsoc-project-coreboot-panic-room-diagnostics-also-remote-flashing/ ---------------------------------------------------------------------- Detection primer: The paragraphs below highlight the generic Super I/O and 16550 UART detection process as performed by UBRX. We believe that this process is safe to be executed at every boot, irrespective of the hardware and without side effects. The 2 main components UBRX needs to detect are: 1. a potential PnP Super I/O candidate. 2. a potential 16650 UART Logical Device (LD) on the Super I/O chip. As we start with absolutely no knowledge of the hardware, and must avoid writing data at random, since doing so can damage the hardware, our detection process has been designed with safety in mind from the ground up, by ensuring that write operations were limited to the bare minimum, and only executed after we had some assurance that the destination for the write would match the expectation. Below is a detailed description of how we ensure that our generic detection process is as innocuous to the hardware as possible. 1. The Super I/O chip is accessed through the LPC bus, which is not always accessible after reset, so we may have to enable LPC/SuperIO access first. Currently we only support Intel ICH# (all versions) and AMD SB6x0-9x0. The detection and initialisation of the chipset for LPC access is safe, since it is PCI based, and the PCI VID:PID of the South Bridge can be read beforehand to unconditionally identify a supported chip before we proceed with LPC initiation. You will notice that we use a blanket LPC initialization, as we don't distinguish between versions of the SouthBridge (eg: ICH6 is initialized the same as ICH9), but this is the result of a *thorough* review of all the Intel ICH# and AMD SBxx0 datasheets, to confirm that LPC init could indeed be factorized. Even for the chips that don't require LPC initialization (such as Intel ICH5 or earlier) and for which we do send the LPC initialization command, we have confirmed from the datasheet that we can simply let the PCI transaction fail as no register conflict in the destination config space. As such our LPC bus access initialization is deemed safe. 2. With the LPC bus accessible, we must probe a few common Super I/O ports. Currently, these are 0x2E, 0x4E, 0x370, 0x3f0, as well as their +1 data port. The last two I/O ports are commonly assigned to Tape and FDC so we expect any chip there to withstand unintended writes (plus these can be disabled through the bios.S build options). But even then, the extra checks we apply to the 0x2E and 0x4E ports ensure safe access. With regards to 0x2E and 0x4E, these are more problematic as a non PnP Super I/Os are expected to reside there on older machines, and unchecked write access (such as trying to configure PnP access on a non PnP aware chip) could very well have unintended consequences. To alleviate this problem we: a) always keep a copy of the original value at base and base+1 b) perform PnP enter conf (write to base only) and attempt to read the Super I/O ID (at base +1). If the id is either 0x00 of 0xff, we consider that the address is not one of a PnP Super I/O chip and restore the base data => only the base register will have been accessed, then restored. c) attempt to write 8 LDN values, read them back and check that at least 2 of them stick, indicating that the potential PnP Super I/O chip has at least 2 LDs. If this isn't the case, we also restore the content from base+1 and declare the PnP access to have failed. At most, since we are only writing LDNs, this modifies the 3 lowest bits of base +1. Considering that both superiotool and sensors-detect have let user perform similar Super I/O probing (without the extra restore step), and we are not aware of problems, as well as the fact that any recent PC from our targeted audience would have a Super I/O running in PnP mode at either 0x2e or 0x4e, we consider this approach safe to be executed at every boot. 3. Even with a possible PnP Super I/O chip accessible (and with the current PoC assertion that the UART LD we want to access is powered up by default on reset), we do not have any knowledge of the LDN of the potential UART. With other LDNs being set up for GPIO or hardware monitoring or control, trying to access each LDN as an UART, without exerting any form of caution, is not a viable option. To alleviate this issue, we perform an extensive yet non intrusive detection of a 16550 UART LD by first making sure, through read-only accesses, that the registers match the reset value of a 16550 compliant unit. Then, we try to flip the furthest 'safe' bit in the I/O range (register 7, bit 6, with backup), to eliminate any LD that has less than 7 registers. Then we check a significant unflippable bit from the 16550 register range (which we also restore in case of failure), and finish our testing with a complete UART loopback test. In all, we perform no less than 16 tests to confirm that an LD is indeed a 16550 UART, with more than 30 bits being tested in read-only mode, before we even start trying to flip a single bit. As such, we seem this form of detection both safe and conclusive. At the moment, we test up to 32 LDNs per potential PnP Super I/O for UART access. The 16550 tests are heavily documented in bios.S/check_16550. Only once we have successfully identified a 16650 UART do we attempt to fully configure it and read the console request key. If multiple UARTs have been identified, these will be checked in sequence, meaning that any serial port available on the motherboard can be used for console access. ---------------------------------------------------------------------- From patrick at georgi-clan.de Mon Jul 11 19:43:58 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 11 Jul 2011 19:43:58 +0200 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1B2C8B.5050001@akeo.ie> References: <4E1B2C8B.5050001@akeo.ie> Message-ID: <4E1B365E.4070809@georgi-clan.de> Am Montag, 11. Juli 2011 19:02:03, Pete Batard schrieb: > Comments? Questions? Shoot away... My main concern is that SuperIO and serial is going away completely ("legacy-free hardware"). When using PCI based boards (eg. extension stuff) we need to poke holes into the northbridge (and/or southbridge) to get access to them (ie. no generic solution either). We might be better off with widely available USB2 and USB3 debug port tools and software support (and even that requires _some_ chipset specific setup to make the chipset react to it). Patrick From gerrit at coreboot.org Mon Jul 11 20:23:57 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 11 Jul 2011 20:23:57 +0200 Subject: [coreboot] Patch merged into master: f530383 libpayload: Add qsort() References: Message-ID: the following patch was just integrated into master: commit f53038334f203008b625669404794bbaa4dd9d8e Author: Patrick Georgi Date: Thu Jul 7 12:02:10 2011 +0200 libpayload: Add qsort() It's taken from OpenBSD and thus appropriately licensed (and reasonably tested). Change-Id: I5767600c9865d39e56c220b52e045f3501875b98 Signed-off-by: Patrick Georgi See http://review.coreboot.org/88 for details. -gerrit From pete at akeo.ie Tue Jul 12 01:40:17 2011 From: pete at akeo.ie (Pete Batard) Date: Tue, 12 Jul 2011 00:40:17 +0100 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1B365E.4070809@georgi-clan.de> References: <4E1B2C8B.5050001@akeo.ie> <4E1B365E.4070809@georgi-clan.de> Message-ID: <4E1B89E1.2090207@akeo.ie> On 2011.07.11 18:43, Patrick Georgi wrote: > My main concern is that SuperIO and serial is going away completely > ("legacy-free hardware"). Alas, yes, native RS232 seems to be on the way out these days. Still (but I'm obviously biased here) we can support most of the non legacy-free hardware with less than 2 KB of code, so why not go for it? Requiring people to acquire hardware that duplicates a functionality they already have, and which we can support without too much effort, doesn't seem like the best approach to me. I'm also wondering how much real-estate a minimal xHCI stack will take in a panic-room bootblock. But part of the reason I posted is also to find out what the current coreboot plans with regards to the panic-room implementation are, especially as there is a GSoC project for it. Has the set of feature, and how they should be implemented, already been agreed on, or is it still open for discussion? Regards, /Pete From peter at stuge.se Tue Jul 12 02:03:46 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 12 Jul 2011 02:03:46 +0200 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1B89E1.2090207@akeo.ie> References: <4E1B2C8B.5050001@akeo.ie> <4E1B365E.4070809@georgi-clan.de> <4E1B89E1.2090207@akeo.ie> Message-ID: <20110712000346.31870.qmail@stuge.se> Pete Batard wrote: > a minimal xHCI stack Note needs DMA, except for EHCI Debug Port, which needs a special device. //Peter From devtadas at gmail.com Tue Jul 12 03:42:03 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Tue, 12 Jul 2011 04:42:03 +0300 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1B89E1.2090207@akeo.ie> References: <4E1B2C8B.5050001@akeo.ie> <4E1B365E.4070809@georgi-clan.de> <4E1B89E1.2090207@akeo.ie> Message-ID: <1310434923.24477.26.camel@ts-laptop> > But part of the reason I posted is also to find out what the current > coreboot plans with regards to the panic-room implementation are, > especially as there is a GSoC project for it. Has the set of feature, > and how they should be implemented, already been agreed on, or is it > still open for discussion? Hi Pete, currently my plan is to run flashrom out of cache (in romstage), transfer rom image over console (serial, maybe later ne2k) in small chunks like ~256 bytes so that cache_as_ram.inc would require less changes. Haven't thought about usb debugport, since even this is quite hard task for me. Thanks, Tadas From scott at notabs.org Tue Jul 12 03:38:29 2011 From: scott at notabs.org (Scott Duplichan) Date: Mon, 11 Jul 2011 20:38:29 -0500 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1B2C8B.5050001@akeo.ie> References: <4E1B2C8B.5050001@akeo.ie> Message-ID: <8D0935D19DF241D78420CD0E2801A25D@asusp67> Pete Batard wrote: ]... ]Right now, I am especially interested in tests being conducted on AMD ]hardware to confirm that the AMD LCP/SouthBridge init works. Again, you ]should be able to test UBRX even if your platform is not supported by ]coreboot, provided of course that you can reflash your BIOS through ]external means afterwards (SPI, parallel programmer, etc.). Hello Pete, This is an important subject because recovery is one of the few major features of a commercial BIOS that coreboot+SeaBIOS lacks. I tried the sample on ASRock E350M1 and it did not work. One reason is needed LPC clock initialization (http://permalink.gmane.org/gmane.linux.bios/67229). Another problem is the one mentioned in the release notes about cases where the serial port pins default to gpio use and must be configured for serial port use. I believe this will be the situation with Nuvoton NCT6776F. I spent a few minutes debugging with AMD simnow but was unable to get it to work there. Maybe some additional port 80 codes that mark algorithm milestones would simplify debug. Thanks, Scott From patrick at georgi-clan.de Tue Jul 12 08:02:49 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Tue, 12 Jul 2011 08:02:49 +0200 Subject: [coreboot] =?utf-8?q?=5BRFC=5D_Universal_panic-room_serial_consol?= =?utf-8?q?e=2C_for_x86=09BIOS_bootblock?= In-Reply-To: <20110712000346.31870.qmail@stuge.se> References: <4E1B2C8B.5050001@akeo.ie> <4E1B365E.4070809@georgi-clan.de> <4E1B89E1.2090207@akeo.ie> <20110712000346.31870.qmail@stuge.se> Message-ID: On Tue, 12 Jul 2011 02:03:46 +0200, Peter Stuge wrote: > Pete Batard wrote: >> a minimal xHCI stack > Note needs DMA, except for EHCI Debug Port, which needs a special > device. EHCI requires a special device and no DMA (but debug port support in the EHCI controller). xHCI requires no special device: if the optional debug port feature is provided, everything is inside the controller. However, xHCI potentially requires memory to be around for DMA: there's another optional feature to have the controller provide enough memory in MMIO range to do xHCI debug without RAM. Now I suppose the question is, if there's a PCIe xHCI controller with both debug port and MMIO-as-RAM features for a reasonable price? If so, all we'd need is a bit of bus poking to make xHCI debug useful for us. Patrick From patrick at georgi-clan.de Tue Jul 12 08:05:56 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Tue, 12 Jul 2011 08:05:56 +0200 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <8D0935D19DF241D78420CD0E2801A25D@asusp67> References: <4E1B2C8B.5050001@akeo.ie> <8D0935D19DF241D78420CD0E2801A25D@asusp67> Message-ID: <1075a942a649100701ef5e5dcda00e81@mail.georgi-clan.de> On Mon, 11 Jul 2011 20:38:29 -0500, Scott Duplichan wrote: > This is an important subject because recovery is one of the few major > features of a commercial BIOS that coreboot+SeaBIOS lacks. I tried > the > sample on ASRock E350M1 and it did not work. One reason is needed LPC "Panic Room" features won't be too useful for flash recovery. With partial flash updates and the fallback/normal bootblock it should be possible to build a recoverable update mechanism. Patrick From patrick at georgi-clan.de Tue Jul 12 08:09:01 2011 From: patrick at georgi-clan.de (Patrick Georgi) Date: Tue, 12 Jul 2011 08:09:01 +0200 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1B89E1.2090207@akeo.ie> References: <4E1B2C8B.5050001@akeo.ie> <4E1B365E.4070809@georgi-clan.de> <4E1B89E1.2090207@akeo.ie> Message-ID: On Tue, 12 Jul 2011 00:40:17 +0100, Pete Batard wrote: > I'm also wondering how much real-estate a minimal xHCI stack will > take in a > panic-room bootblock. xHCI debug port doesn't require an xHCI stack (though it needs some memory to work on in the background). Like the EHCI debug port, it's a bunch of MMIO registers to work with that provide a bidirectional serial pipe. Patrick From gerrit at coreboot.org Tue Jul 12 11:36:22 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 12 Jul 2011 11:36:22 +0200 Subject: [coreboot] Patch merged into master: 5f1cfd8 Do full flush on uart8250 only at end of printk. References: Message-ID: the following patch was just integrated into master: commit 5f1cfd8ee9d400f20a5aa30eb50b9afb5e2694db Author: Kevin O'Connor Date: Sat Jul 9 20:22:21 2011 -0400 Do full flush on uart8250 only at end of printk. The previous code does a full flush of the uart after every character. Unfortunately, this can cause transmission delays on some serial ports. This patch changes the code so that it does a flush at the end of every printk instead of at the end of every character. This reduces the time it takes to transmit serial messages (up to 9% on my Asrock e350m1 board). It also makes the transmission time more consistent which is important when performing timing tests via serial transmissions. Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70 Signed-off-by: Kevin O'Connor See http://review.coreboot.org/90 for details. -gerrit From pete at akeo.ie Tue Jul 12 14:02:22 2011 From: pete at akeo.ie (Pete Batard) Date: Tue, 12 Jul 2011 13:02:22 +0100 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <8D0935D19DF241D78420CD0E2801A25D@asusp67> References: <4E1B2C8B.5050001@akeo.ie> <8D0935D19DF241D78420CD0E2801A25D@asusp67> Message-ID: <4E1C37CE.1010204@akeo.ie> Hi Scott. Thanks a lot for testing! On 2011.07.12 02:38, Scott Duplichan wrote: > I tried the > sample on ASRock E350M1 and it did not work. One reason is needed LPC > clock initialization (http://permalink.gmane.org/gmane.linux.bios/67229). OK. I'm obviously a bit nervous about changing a clock frequency that defaults to 14 MHz to 48 MHz, even temporarily, if it is done on every boot, unless we first have insurance that devices connected there support 48 MHz. From looking at the SB800 datasheet, p232 [1], 2 clock lines are provided, so I'm not seeing much of a guarantee that a 48 MHz Super I/O chip is always connected to Clk1... So I see two possibilities: 1. Add code to identify the motherboard to confirm that the device connected to Clk1/Clk2 supports 48 MHz before we increase the frequency (and decide which Clk should be used) 2. Let the device run at 14 MHz and try to support a 14 MHz mode of operation #1 looks quite difficult to achieve while keeping a small footprint, so I'd rather go the #2 route, even if that results in the serial port being initialized at a lower nonstandard baudrate. The first thing we can do once we have panic-room access is set the clock to 48 MHz and continue with panic-room operations at 115200. However, looking at the NCT6776F datasheet for instance, it appears that the SuperI/O is only meant to support 24 and 48 MHz clock frequencies, and I'm guessing the LPC timings from a chip strapped into thinking it runs at 48 while actually running at 14 will be messed up, so that may not be that great an idea... > Another problem is the one mentioned in the release notes about cases > where the serial port pins default to gpio use and must be configured > for serial port use. I believe this will be the situation with Nuvoton > NCT6776F. That's a good point. From what I can see, the NCT6776F doesn't actually seem to use a dual GPIO/UART, but other Super I/O might. Depending on how widespread these chips are, we might want to detect those. Right now, with UBRX is still in a PoC state, I'd rather avoid introducing special cases. At least, I don't believe is should be needed for testing the E350M1 as it uses a W83627HF. > I spent a few minutes debugging with AMD simnow but was unable to get > it to work there. Maybe some additional port 80 codes that mark > algorithm milestones would simplify debug. I can do that, but you have to understand that, if we identify what looks like a PnP Super I/O, we test up to 32 possible LDs in sequence. If an LD is not identified as an UART, we just move on to the next one, so, unless you have a port 80 card with a buffer, I'd need to add a 1 second delay or something each time we fail to identify an LD as an UART, for the user to be notified, and the whole boot process would then take about half a minute (or more, if other PnP Super I/O candidates are identified at other bases). I'll see what I can do, but if you know your Super I/O base as well as the LDN for the UART you want to use, you can modify the code to only test those, and report the error. Or you can just wait, as I'll update UBRX soon, to make is easier to test only a specific UART LDN and Super I/O base and add extra debug, to facilitate troubleshooting. Regards, /Pete [1] http://support.amd.com/us/Embedded_TechDocs/45482.pdf From pete at akeo.ie Tue Jul 12 14:05:48 2011 From: pete at akeo.ie (Pete Batard) Date: Tue, 12 Jul 2011 13:05:48 +0100 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <1075a942a649100701ef5e5dcda00e81@mail.georgi-clan.de> References: <4E1B2C8B.5050001@akeo.ie> <8D0935D19DF241D78420CD0E2801A25D@asusp67> <1075a942a649100701ef5e5dcda00e81@mail.georgi-clan.de> Message-ID: <4E1C389C.3080208@akeo.ie> On 2011.07.12 07:05, Patrick Georgi wrote: > "Panic Room" features won't be too useful for flash recovery. > With partial flash updates and the fallback/normal bootblock it should > be possible to build a recoverable update mechanism. I'd tend to agree that, if you already have coreboot working, fallback is likely to be good enough. On the other hand, for all the platforms that do not have coreboot yet, a panic-room could be quite useful... Regards, /Pete From pete at akeo.ie Tue Jul 12 14:05:08 2011 From: pete at akeo.ie (Pete Batard) Date: Tue, 12 Jul 2011 13:05:08 +0100 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <1310434923.24477.26.camel@ts-laptop> References: <4E1B2C8B.5050001@akeo.ie> <4E1B365E.4070809@georgi-clan.de> <4E1B89E1.2090207@akeo.ie> <1310434923.24477.26.camel@ts-laptop> Message-ID: <4E1C3874.3080205@akeo.ie> Hi Tadas, On 2011.07.12 02:42, Tadas Slotkus wrote: > currently my plan is to run flashrom out of cache (in romstage), > transfer rom image over console (serial, maybe later ne2k) in small > chunks like ~256 bytes so that cache_as_ram.inc would require less > changes. That sounds good (and quite a lot of work!). If you manage to produce a flashrom that can run in CAR for romstage, I'm pretty sure it could easily be reused for flashrom in a CAR payload for panic-room. By the way, if you need a Y-modem implementation in C, for serial transfers, I can provide one, as I had to implement such a feature on another project (which was actually a panic-room payload, but for Realtek SoCs). It is available here: http://code.google.com/p/xtreamerdev/source/browse/trunk/rtdsr/ymodem.c (complete source package: http://xtreamerdev.googlecode.com/files/rtdsr_0.6_src.tar.gz) The license is GPLv3, but I'm open to relicensing that specific part of the code (as well as the .h) to GPLv2.1 or later if needed, as I was the only contributor on that project and everything reused was either GPLv2.1 or later, or public domain. > Haven't thought about usb debugport, since even this is quite > hard task for me. I think a lot of people will be happy if you just complete the flashrom goal. I'm definitely one of them. Regards, /Pete From me at andrewbolster.info Tue Jul 12 15:18:56 2011 From: me at andrewbolster.info (Andrew Bolster) Date: Tue, 12 Jul 2011 14:18:56 +0100 Subject: [coreboot] Coreboot on AMD Geode; No VGA Message-ID: I only started looking into coreboot yesterday, so forgive the incoming naivety. Can anyone point me in the direction of how to set up coreboot + seabios so that it actually uses the VGA? I've got the system up and running and talking to me over the OS's services fine, so all is working except for the VGA. I've tried the rational combinations of enabling and disabling the option roms, but I assume that I need a vgabios.bin? This board is a PC Engines ALIX3D3 (http://www.pcengines.ch/alix3d3.htm), and I can't seem to find any information on how to go about fixing the geode vga output. Any help would be great. Regards Andrew Bolster No trees were killed to send this message, but a large number of electrons were terribly inconvenienced.I enjoy the massacre of ads. This sentence will slaughter ads without a messy bloodbath. -------------- next part -------------- An HTML attachment was scrubbed... URL: From me at andrewbolster.info Tue Jul 12 16:38:32 2011 From: me at andrewbolster.info (Andrew Bolster) Date: Tue, 12 Jul 2011 15:38:32 +0100 Subject: [coreboot] Coreboot on AMD Geode; No VGA In-Reply-To: References: Message-ID: On 12 July 2011 15:31, Benjamin Henrion wrote: > On Tue, Jul 12, 2011 at 3:18 PM, Andrew Bolster > wrote: > > > > I only started looking into coreboot yesterday, so forgive the > incoming naivety. > > Can anyone point me in the direction of how to set up coreboot + seabios > so that it actually uses the VGA? I've got the system up and running and > talking to me over the OS's services fine, so all is working except for the > VGA. > > I've tried the rational combinations of enabling and disabling the option > roms, but I assume that I need a vgabios.bin? This board is a PC Engines > ALIX3D3 (http://www.pcengines.ch/alix3d3.htm), and I can't seem to find > any information on how to go about fixing the geode vga output. > > This is my experience with it: > > http://www.zoobab.com/alix-1c > > I still need to find the time to recover the firmware with an PLC > homemade adaptor (parallel port or arduino based). > > -- > Benjamin Henrion > FFII Brussels - +32-484-566109 - +32-2-4148403 > "In July 2005, after several failed attempts to legalise software > patents in Europe, the patent establishment changed its strategy. > Instead of explicitly seeking to sanction the patentability of > software, they are now seeking to create a central European patent > court, which would establish and enforce patentability rules in their > favor, without any possibility of correction by competing courts or > democratically elected legislators." > I saw your work, but unfortunately by the time I got to your page I had already sorted out the vsa issues. Fortunately I've been using a piggy-backed ROM so if/when it all goes kaput I just pull the LPC module. VGA isn't even a major problem for the product I'm working on, but I really can't understand how such an otherwise awesome chipset has missed out of VGA :S Thanks anyway Benjamin. -------------- next part -------------- An HTML attachment was scrubbed... URL: From bh at udev.org Tue Jul 12 16:31:52 2011 From: bh at udev.org (Benjamin Henrion) Date: Tue, 12 Jul 2011 16:31:52 +0200 Subject: [coreboot] Coreboot on AMD Geode; No VGA In-Reply-To: References: Message-ID: On Tue, Jul 12, 2011 at 3:18 PM, Andrew Bolster wrote: > > I only started looking into coreboot yesterday, so forgive the incoming?naivety. > Can anyone point me in the direction of how to set up coreboot + seabios so that it actually uses the VGA? I've got the system up and running and talking to me over the OS's services fine, so all is working except for the VGA. > I've tried the rational combinations of enabling and disabling the option roms, but I assume that I need a vgabios.bin? This board is a PC Engines ALIX3D3 (http://www.pcengines.ch/alix3d3.htm), and I can't seem to find any information on how to go about fixing the geode vga output. This is my experience with it: http://www.zoobab.com/alix-1c I still need to find the time to recover the firmware with an PLC homemade adaptor (parallel port or arduino based). -- Benjamin Henrion FFII Brussels - +32-484-566109 - +32-2-4148403 "In July 2005, after several failed attempts to legalise software patents in Europe, the patent establishment changed its strategy. Instead of explicitly seeking to sanction the patentability of software, they are now seeking to create a central European patent court, which would establish and enforce patentability rules in their favor, without any possibility of correction by competing courts or democratically elected legislators." From xdrudis at tinet.cat Tue Jul 12 18:18:14 2011 From: xdrudis at tinet.cat (xdrudis) Date: Tue, 12 Jul 2011 18:18:14 +0200 Subject: [coreboot] AMD Phenom II 1055T was : Hackaton in Prague 2011 In-Reply-To: <1310223883.4e186e0b41b41@webmail.free.fr> References: <4DC77D9C.8010804@assembler.cz> <1309544985.11759.16.camel@mattotaupa> <4E18051D.5000804@assembler.cz> <1310223883.4e186e0b41b41@webmail.free.fr> Message-ID: <20110712161814.GB9360@ideafix.casa.ct> On Sat, Jul 09, 2011 at 05:04:43PM +0200, Florentin Demetrescu wrote: > > - my objective was to install coreboot on my new board MA785GMT-UDH2. I had > bring with me a Phenom II 1055T CPU with 6 cores. Unfortunately I met big > problems because: [...] > coreboot and give it a run, but I will do that ASAP! Also I will investigate the > problem of the 6 core Phenom II on this board.. > Isn't it a fam 10 revision E CPU ? Coreboot did not have any code specific for Fam 10 rev E last time I checked (mid feb 2011) (no errata workarounds, no specific initialization, just a small untested part in fidvid.c). There wasn't even a constant defined for rev E. Back in August 2010 I asked how to extend the revision bitfield that's used as a trigger for rule based initializations and workarounds, and in a small thread it was suggested to get rid of it and use a struct, but I never did. http://www.coreboot.org/pipermail/coreboot/2010-August/059701.html From marcj303 at gmail.com Tue Jul 12 19:03:46 2011 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 12 Jul 2011 11:03:46 -0600 Subject: [coreboot] Coreboot on AMD Geode; No VGA In-Reply-To: References: Message-ID: On Tue, Jul 12, 2011 at 8:38 AM, Andrew Bolster wrote: > On 12 July 2011 15:31, Benjamin Henrion wrote: >> >> On Tue, Jul 12, 2011 at 3:18 PM, Andrew Bolster >> wrote: >> > >> > I only started looking into coreboot yesterday, so forgive the >> > incoming?naivety. >> > Can anyone point me in the direction of how to set up coreboot + seabios >> > so that it actually uses the VGA? I've got the system up and running and >> > talking to me over the OS's services fine, so all is working except for the >> > VGA. >> > I've tried the rational combinations of enabling and disabling the >> > option roms, but I assume that I need a vgabios.bin? This board is a PC >> > Engines ALIX3D3 (http://www.pcengines.ch/alix3d3.htm), and I can't seem to >> > find any information on how to go about fixing the geode vga output. >> >> This is my experience with it: >> >> http://www.zoobab.com/alix-1c >> >> I still need to find the time to recover the firmware with an PLC >> homemade adaptor (parallel port or arduino based). >> >> -- >> Benjamin Henrion >> FFII Brussels - +32-484-566109 - +32-2-4148403 >> "In July 2005, after several failed attempts to legalise software >> patents in Europe, the patent establishment changed its strategy. >> Instead of explicitly seeking to sanction the patentability of >> software, they are now seeking to create a central European patent >> court, which would establish and enforce patentability rules in their >> favor, without any possibility of correction by competing courts or >> democratically elected legislators." > > I saw your work, but unfortunately by the time I got to your page I had > already sorted out the vsa issues. Fortunately I've been using a > piggy-backed ROM so if/when it all goes kaput I just pull the LPC module. > VGA isn't even a major problem for the product I'm working on, but I really > can't understand how such an otherwise awesome chipset has missed out of VGA > :S > Thanks anyway Benjamin. > http://www.coreboot.org/AMD_Geode_Porting_Guide#Graphics -- http://se-eng.com From marcj303 at gmail.com Tue Jul 12 19:06:49 2011 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 12 Jul 2011 11:06:49 -0600 Subject: [coreboot] AMD Phenom II 1055T was : Hackaton in Prague 2011 In-Reply-To: <20110712161814.GB9360@ideafix.casa.ct> References: <4DC77D9C.8010804@assembler.cz> <1309544985.11759.16.camel@mattotaupa> <4E18051D.5000804@assembler.cz> <1310223883.4e186e0b41b41@webmail.free.fr> <20110712161814.GB9360@ideafix.casa.ct> Message-ID: On Tue, Jul 12, 2011 at 10:18 AM, xdrudis wrote: > On Sat, Jul 09, 2011 at 05:04:43PM +0200, Florentin Demetrescu wrote: >> >> ?- my objective was to install coreboot on my new board MA785GMT-UDH2. I had >> bring with me a Phenom II 1055T CPU with 6 cores. Unfortunately I met big >> problems because: > [...] >> coreboot and give it a run, but I will do that ASAP! Also I will investigate the >> problem of the 6 core Phenom II on this board.. >> > > Isn't it a fam 10 revision E CPU ? > > Coreboot did not have any code specific for Fam 10 rev E last time I > checked (mid feb 2011) (no errata workarounds, no specific > initialization, just a small untested part in fidvid.c). There wasn't > even a constant defined for rev E. > > Back in August 2010 I asked how to extend the revision bitfield that's > used as a trigger for rule based initializations and workarounds, and > in a small thread it was suggested to get rid of it and use a struct, > but I never did. > http://www.coreboot.org/pipermail/coreboot/2010-August/059701.html > The C32 support might handle rev E. I don't know if there is much different from rev D (bigger differences between revC and revD). If more support is required, there may be some updates from AMD in the future. Marc -- http://se-eng.com From pete at akeo.ie Tue Jul 12 19:42:10 2011 From: pete at akeo.ie (Pete Batard) Date: Tue, 12 Jul 2011 18:42:10 +0100 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1BE67C.6010805@tadpole.com> References: <4E1B2C8B.5050001@akeo.ie> <4E1BE67C.6010805@tadpole.com> Message-ID: <4E1C8772.5010006@akeo.ie> On 2011.07.12 07:15, Andrew Goodbody wrote: > Instead of attempting (and failing) to achieve universal support I'll start with the aside, that if "failing" means instantly supporting more than 90% of Intel based motherboards produced in the last 10 years (if you have an ICH# or a 440BX controller, you should be good, as you only have one clock for Super I/O, that isn't programmable), as well as a large chunk of AMD motherboards (once the SB clock programming issue is solved, which I'm pretty sure can be done), then I wonder how the rate of support that coreboot has with regards to motherboards produced in the last few years would qualify... Please do not misconstrue this as criticism of coreboot, as it isn't. It's just that, if I were to start coreboot development, I sure wouldn't mind if someone else had already sorted some kind of bare metal console access for my platform, even if that applied "only" to 3/4th of all x86 motherboards produced in the last 10 years... > I would > rather see a framework that could easily be configured with the > appropriate SIO support and allow for board specific configuration if > necessary. This should remove a lot of the complexity that gives very > little advantage in trying for universal support. coreboot is built as > hardware specific and I see no reason why the panic room support should > not be the same. I guess we have different definition of a panic-room then. From my dealings with Realtek SoCs, the way I see a panic-room is something that is as hardware agnostic as possible. In the ideal case, the panic-room is implemented ondie directly on a CPU that has an UART unit, and therefore with no possible knowledge of the hardware surrounding it. Such knowledge is to be provided by the user. This is what the RTD1283 provides for instance (8KB bootblock, with console and Y-modem upload in CPU ROM), and it is extremely powerful. The panic-room is then intended as a means for users to perform hardware initialization such as RAM or Flash access, as well as any other task they might fathom. Hence, this is the implementation of a panic-room I have been trying to follow, as it is the one that is most versatile and helpful to users IMO. > Choosing the SIO support to configure for the panic > room can be easily done from the output of superiotool. Provided superiotool knows about the chip, which may not be the case yet. If Nuvoton introduces a new chip tomorrow, for which we haven't seen a datasheet yet, I'm pretty sure UBRX will work just fine. Superiotool, not so much... Also picking a coreboot BIOS from one machine and soldering it into another, with the expectation that even if the motherboards have nothing in common but the flash they use, panic-room access will be available, can have its advantages, be it only for ghetto-style budget-constrained tinkerers. > Additionally if it was done in such a way that the serial transport > could be easily replaced by USB debug instead then we could really have > something that would be useful for new boards. Well, depending how much space EHCI/xHCI USB support would take, I don't see why UBRX wouldn't be able to provide both. But right now, considering that there is still an awful lot of modern yet legacy based systems out there that could benefit from coreboot support, concentrating on native UART doesn't seem like a bad idea. Regards, /Pete From peter at stuge.se Tue Jul 12 19:44:30 2011 From: peter at stuge.se (Peter Stuge) Date: Tue, 12 Jul 2011 19:44:30 +0200 Subject: [coreboot] Coreboot on AMD Geode; No VGA In-Reply-To: References: Message-ID: <20110712174430.21993.qmail@stuge.se> Andrew Bolster wrote: > Can anyone point me in the direction of how to set up coreboot + > seabios so that it actually uses the VGA? Are you sure there actually is VGA? For the Geode SC series it was neccessary to have a VSM that would emulate a fair bit of the legacy VGA. I think LX has some hardware support, but not the full monty. If you already have the correct VSM in your VSA blob then "all" you need is to extract the VGA BIOS from the original BIOS, and add that into coreboot.rom as pcixxxx,yyyy.rom where xxxx,yyyy is the graphics PCI id. > I've tried the rational combinations of enabling and disabling the option > roms, Note that coreboot should not be initializing option ROMs, instead SeaBIOS should be used for that. So disable option ROMs in coreboot config. > but I assume that I need a vgabios.bin? Yes. Try the bios_extract tool to grab the VGA BIOS out of the factory BIOS image. //Peter From njacobs8 at hetnet.nl Tue Jul 12 20:55:37 2011 From: njacobs8 at hetnet.nl (Nils) Date: Tue, 12 Jul 2011 20:55:37 +0200 Subject: [coreboot] Coreboot on AMD Geode; No VGA Message-ID: <1310496937.2249.14.camel@Debian.lan> Andrew Bolster wrote: > Can anyone point me in the direction of how to set up coreboot + > seabios so that it actually uses the VGA? I am struggling with the same problem for some time now. Extracting the original VGA as Peter suggests won't work because the LX VSA we use is stripped down and doesn't have the graphics init routines in it anymore. The most promising solution that should work (i didn't test it yet) i could find is this: http://patchwork.coreboot.org/patch/190/ It seems Chris is not working on it anymore and Kevin did not approve it in it's current state for inclusion in Seabios. Thanks, Nils. From gerrit at coreboot.org Wed Jul 13 02:01:35 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 13 Jul 2011 02:01:35 +0200 Subject: [coreboot] Patch merged into master: 77439f0 Make AMD SMM SMP aware References: Message-ID: the following patch was just integrated into master: commit 77439f041fc6348cdaaa682d5cbe8c41f3f96241 Author: Rudolf Marek Date: Sat Jul 2 16:36:17 2011 +0200 Make AMD SMM SMP aware Move the SMM MSR init to a code run per CPU. Introduce global SMM_BASE define, later all 0xa0000 could be changed to use it. Remove the unnecessary test if the smm_init routine is called once (it is called by BSP only) and also remove if lock bit is set becuase this bit is cleared by INIT it seems. Add the defines for fam10h and famfh to respective files, we do not have any shared AMD MSR header file. Tested on M2V-MX SE with dualcore CPU. Change-Id: I1b2bf157d1cc79c566c9089689a9bfd9310f5683 Signed-off-by: Rudolf Marek See http://review.coreboot.org/82 for details. -gerrit From gerrit at coreboot.org Wed Jul 13 02:01:48 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 13 Jul 2011 02:01:48 +0200 Subject: [coreboot] Patch merged into master: 835a320 Enable SMI on M2V-MX SE References: Message-ID: the following patch was just integrated into master: commit 835a320916cd7a5032750b1fe1ca0df37a33f198 Author: Rudolf Marek Date: Sat Jul 2 16:41:38 2011 +0200 Enable SMI on M2V-MX SE Finally the SMI routines are in good shape on AMD, lets enable this and later implement ACPI on/off SMI commands. Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e Signed-off-by: Rudolf Marek See http://review.coreboot.org/83 for details. -gerrit From Kerry.She at amd.com Wed Jul 13 04:58:32 2011 From: Kerry.She at amd.com (She, Kerry) Date: Wed, 13 Jul 2011 10:58:32 +0800 Subject: [coreboot] AMD Phenom II 1055T was : Hackaton in Prague 2011 In-Reply-To: <20110712161814.GB9360@ideafix.casa.ct> References: <4DC77D9C.8010804@assembler.cz><1309544985.11759.16.camel@mattotaupa><4E18051D.5000804@assembler.cz><1310223883.4e186e0b41b41@webmail.free.fr> <20110712161814.GB9360@ideafix.casa.ct> Message-ID: > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of xdrudis > Sent: Wednesday, July 13, 2011 12:18 AM > To: Florentin Demetrescu > Cc: coreboot at coreboot.org > Subject: [coreboot] AMD Phenom II 1055T was : Hackaton in Prague 2011 > > On Sat, Jul 09, 2011 at 05:04:43PM +0200, Florentin Demetrescu wrote: > > > > - my objective was to install coreboot on my new board MA785GMT-UDH2. I > had > > bring with me a Phenom II 1055T CPU with 6 cores. Unfortunately I met big > > problems because: > [...] > > coreboot and give it a run, but I will do that ASAP! Also I will > investigate the > > problem of the 6 core Phenom II on this board.. > > > > Isn't it a fam 10 revision E CPU ? > > Coreboot did not have any code specific for Fam 10 rev E last time I > checked (mid feb 2011) (no errata workarounds, no specific > initialization, just a small untested part in fidvid.c). There wasn't > even a constant defined for rev E. > > Back in August 2010 I asked how to extend the revision bitfield that's > used as a trigger for rule based initializations and workarounds, and > in a small thread it was suggested to get rid of it and use a struct, > but I never did. > http://www.coreboot.org/pipermail/coreboot/2010-August/059701.html AMD Family10 RevE support code was just added into Coreboot a few weeks ago, Please check http://review.coreboot.org/40 in detail, The RevD support code are ready, and will release soon. I think it's not hard to implement RevE, by using the RevD as an reference. thanks -- Kerry > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From paulepanter at users.sourceforge.net Wed Jul 13 11:44:46 2011 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Wed, 13 Jul 2011 11:44:46 +0200 Subject: [coreboot] Desktop Summit 2011 in Berlin Message-ID: <1310550286.4210.23.camel@mattotaupa> Dear coreboot folks, the Desktop Summit 2011 [1] will take place in Berlin from August 6th? 12th. The first three days will consist of keynotes and talks [2]. There seem to be some open slots on Monday and maybe on the weekend evening too. I am CCing Lennart Poettering as one of the organizers(?). Knowing that some coreboot or flashrom developers live in Berlin it would be awesome if one of them could present coreboot or flashrom. For coreboot a short introduction and demonstration of for example the ThinkPad X60/T60 and ASRock E350M1 would be a good idea. I know this is on short notice and the Desktop Summit is normally associated with GNOME and KDE and therefore coreboot seems out of place. But in my opinion ? if accepted ? coreboot could reach *developers* who might be interested in the possibilities of coreboot and do not know about this. flashrom could be interesting for the desktop developers to know that there are tools to upgrade the BIOS from the desktop and maybe someone is motivated to code up a GUI (graphical user interface) for flashrom. That is just a thought and I do not know how easy that would be and if flashrom provides these kinds of means to be hooked up to a GUI. I would do it, but I am only able to be there on Saturday and not being that knowledgeable with the internals I would rather not do it. Thanks, Paul [1] https://desktopsummit.org/ [2] https://desktopsummit.org/program -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From echelon at free.fr Wed Jul 13 11:57:07 2011 From: echelon at free.fr (Florentin Demetrescu) Date: Wed, 13 Jul 2011 11:57:07 +0200 Subject: [coreboot] AMD Phenom II 1055T was : Hackaton in Prague 2011 In-Reply-To: References: <4DC77D9C.8010804@assembler.cz><1309544985.11759.16.camel@mattotaupa><4E18051D.5000804@assembler.cz><1310223883.4e186e0b41b41@webmail.free.fr> <20110712161814.GB9360@ideafix.casa.ct> Message-ID: <1310551027.4e1d6bf3ed9a5@webmail.free.fr> Xavi, Kerry and Marc, Tahnk you very much for these advices! This will facilitate greatly my work.. Concerning my coreboot tests on MA785GMT-UDH2 with Phenom II 1055T, I hope to be able to give you a feedback next week. Thank you again! Florentin Demetrescu Quoting "She, Kerry" : > > > > -----Original Message----- > > From: coreboot-bounces at coreboot.org > [mailto:coreboot-bounces at coreboot.org] > > On Behalf Of xdrudis > > Sent: Wednesday, July 13, 2011 12:18 AM > > To: Florentin Demetrescu > > Cc: coreboot at coreboot.org > > Subject: [coreboot] AMD Phenom II 1055T was : Hackaton in Prague 2011 > > > > On Sat, Jul 09, 2011 at 05:04:43PM +0200, Florentin Demetrescu wrote: > > > > > > - my objective was to install coreboot on my new board > MA785GMT-UDH2. I > > had > > > bring with me a Phenom II 1055T CPU with 6 cores. Unfortunately I > met big > > > problems because: > > [...] > > > coreboot and give it a run, but I will do that ASAP! Also I will > > investigate the > > > problem of the 6 core Phenom II on this board.. > > > > > > > Isn't it a fam 10 revision E CPU ? > > > > Coreboot did not have any code specific for Fam 10 rev E last time I > > checked (mid feb 2011) (no errata workarounds, no specific > > initialization, just a small untested part in fidvid.c). There wasn't > > even a constant defined for rev E. > > > > Back in August 2010 I asked how to extend the revision bitfield that's > > used as a trigger for rule based initializations and workarounds, and > > in a small thread it was suggested to get rid of it and use a struct, > > but I never did. > > http://www.coreboot.org/pipermail/coreboot/2010-August/059701.html > > AMD Family10 RevE support code was just added into Coreboot a few weeks > ago, > Please check http://review.coreboot.org/40 in detail, > The RevD support code are ready, and will release soon. > I think it's not hard to implement RevE, by using the RevD as an > reference. > thanks > -- > Kerry > > > > -- > > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > From me at andrewbolster.info Wed Jul 13 14:50:09 2011 From: me at andrewbolster.info (Andrew Bolster) Date: Wed, 13 Jul 2011 13:50:09 +0100 Subject: [coreboot] Coreboot on AMD Geode; No VGA In-Reply-To: <20110712174430.21993.qmail@stuge.se> References: <20110712174430.21993.qmail@stuge.se> Message-ID: On 12 July 2011 18:44, Peter Stuge wrote: > Andrew Bolster wrote: > > Can anyone point me in the direction of how to set up coreboot + > > seabios so that it actually uses the VGA? > > Are you sure there actually is VGA? For the Geode SC series it was > neccessary to have a VSM that would emulate a fair bit of the legacy > VGA. I think LX has some hardware support, but not the full monty. If > you already have the correct VSM in your VSA blob then "all" you need > is to extract the VGA BIOS from the original BIOS, and add that into > coreboot.rom as pcixxxx,yyyy.rom where xxxx,yyyy is the graphics PCI > id. > I've tried the rational combinations of enabling and disabling the option > > roms, > > Note that coreboot should not be initializing option ROMs, instead > SeaBIOS should be used for that. So disable option ROMs in coreboot > config. > but I assume that I need a vgabios.bin? > > Yes. Try the bios_extract tool to grab the VGA BIOS out of the > factory BIOS image. > Well I'm using the gpl_vsa_lx_102.bin from MJones, turned off VGA option roms, Seabios Stable as the payload, and an extracted bios using the script from the wiki.[ http://www.coreboot.org/VGA_support#Extracting_from_the_system_.28if_everything_else_fails.29 ] There is a very old thread pertaining to this that I had a look through but couldn't really explain any of the problems (or why no fixes have been pushed up). [ http://www.coreboot.org/pipermail/coreboot/2008-October/039657.html] I admit that I don't understand alot of the details of the boot diagnostics, but if anyone cares to have a look, heres the bootlog for what happens with the above setup. http://pastebin.com/jNtuEyV7 Thanks for your quick responses. A -------------- next part -------------- An HTML attachment was scrubbed... URL: From devtadas at gmail.com Wed Jul 13 22:11:01 2011 From: devtadas at gmail.com (Tadas Slotkus) Date: Wed, 13 Jul 2011 23:11:01 +0300 Subject: [coreboot] Triggering another payload In-Reply-To: <1309473403.7857.10.camel@ts-laptop> References: <1309473403.7857.10.camel@ts-laptop> Message-ID: <1310587861.31044.52.camel@ts-laptop> This one is not bad for triggering another payload (flashrom) via key press or console input. Unfortunately it works only with PS/2 keyboard. Signed-off-by: Tadas Slotkus diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 3d15b55..7726afd 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -41,6 +41,14 @@ it with the version available from LANL. #if CONFIG_WRITE_HIGH_TABLES #include #endif +#include + +int keyboard_havechar(void); +int keyboard_havechar(void) +{ + unsigned char c = inb(0x64); + return (c == 0xFF) ? 0 : c & 1; +} /** * @brief Main function of the RAM part of coreboot. @@ -102,7 +110,20 @@ void hardwaremain(int boot_complete) * write our configuration tables. */ lb_mem = write_tables(); - cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload"); + + /* This is for PS/2 keyboard spurious scancodes */ + int i; + for (i = 0; i < 50; i++){ + while (keyboard_havechar()) + inb(0x60); + mdelay(10); + } + /* Now wait some time for real key press */ + mdelay(300); + if(console_tst_byte() || keyboard_havechar()) + cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/flashrom"); + else + cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload"); printk(BIOS_ERR, "Boot failed.\n"); } From lennart at poettering.net Wed Jul 13 23:02:18 2011 From: lennart at poettering.net (Lennart Poettering) Date: Wed, 13 Jul 2011 23:02:18 +0200 Subject: [coreboot] Desktop Summit 2011 in Berlin In-Reply-To: <1310550286.4210.23.camel@mattotaupa> References: <1310550286.4210.23.camel@mattotaupa> Message-ID: <20110713210217.GA8636@tango.0pointer.de> On Wed, 13.07.11 11:44, Paul Menzel (paulepanter at users.sourceforge.net) wrote: > Dear coreboot folks, > > the Desktop Summit 2011 [1] will take place in Berlin from August 6th? > 12th. The first three days will consist of keynotes and talks [2]. > > There seem to be some open slots on Monday and maybe on the weekend > evening too. I am CCing Lennart Poettering as one of the > organizers(?). Yes, I running the paper committee of the summit. At this time the talks schedule (sat-mon) is finalized and all slots filled. So we cannot add anything to that part of the schedule anymore. For the BoF/workshop part of the conference (i.e. tue-fri) the deadline for having a bof in the printed schedule is already passed, too. However, we kept a big chunk of the rooms for ad-hoc bofs, which will be handed out first come first serve, and registering a slot will be done via a wiki. You are welcome register a room from these at the conference. > I know this is on short notice and the Desktop Summit is normally > associated with GNOME and KDE and therefore coreboot seems out of place. > But in my opinion ? if accepted ? coreboot could reach *developers* who > might be interested in the possibilities of coreboot and do not know > about this. If we have a BoF room available (and I think we do) then I see no reason why coreboot should not be able to get one. I am only running the paper committe, not the bof commitee. If you have any questions regarding bofs, consider pinging Jon Nordby (jononor at gmail.com) directly who's looking after the bofs. Hope this is helpful, Lennart -- Lennart Poettering - Red Hat, Inc. From pete at akeo.ie Wed Jul 13 23:25:32 2011 From: pete at akeo.ie (Pete Batard) Date: Wed, 13 Jul 2011 22:25:32 +0100 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1D7B7F.3080807@tadpole.com> References: <4E1B2C8B.5050001@akeo.ie> <4E1BE67C.6010805@tadpole.com> <4E1C8772.5010006@akeo.ie> <4E1D7B7F.3080807@tadpole.com> Message-ID: <4E1E0D4C.8020909@akeo.ie> On 2011.07.13 12:03, Andrew Goodbody wrote: >> I'll start with the aside, that if "failing" means instantly supporting >> more than 90% of Intel based motherboards produced in the last 10 years > > Yes, universal means everything. If you do not support everything then > it is not universal. The use of universal sets false expectations. In that case, "unlimited broadband" means truly unlimited, and fair expectations are not supposed to be applied to the claim. I guess if you would prefer an asterisk after the Universal in UBRX, with a "Terms and Conditions apply", this can be arranged... ;) This being said, the 90% with regards to Intel chipsets applies to the *PoC* (guesstimate obviously, but I think I'm probably pessimistic when only those weird ITE init and non PnP Super I/Os are expected to fail detection, which I doubt many of the ICH motherboard from the last 10 years would have). The final version could be a lot closer to the 100% mark, especially if we attempt detect both native UART and USB 3.0 debug, as legacy free hardware, which I suppose is expected to have PCI-E, would just need an xHCI PCI-E card we can detect to get going. I also don't think the idea of dropping support for non PnP SIO chips detracts from the claim of Universality(*) that much. A comparison would be to claim that Windows software released in 2011 does not actually qualify as being "Windows compatible" or put Windows on the box if it doesn't support Windows 98 (And, just like Windows software comes with a "minimum system requirements", our Readme comes with about the same thing in the form of current UBRX limitations). My understanding is that most manufacturers would have switched to PnP SIOs around '98 as well, so the Windows 98 comparison seems appropriate. Finally, please remember that this is only a PoC, which is expected to be incomplete or, gasp, have bugs (still working on it). Most of the limitations or problems currently applying, can either be lifted or worked around one way or another. However, there is only so much I can test so yes, in its current instance, U(*)BRX does fall short of its established goal of Universality(*). However, I'm not seeing a major reason why it couldn't get there, hence the claim. At least I am hoping that it is OK to come to this list, with something that is still incomplete, to see if there is interest, and not being requested to come back with a solution that is feature complete and spotless. > Yes we see different priorities for a panic room, but I think you > misunderstood how much knowledge of the platform I was suggesting needed > to be configured. OK, that's probably fair. > To me a panic room should > be as simple and bullet proof as possible and if that means > pre-configuring the build then so be it. The problem I have with pre-configured is you need to have prior knowledge. So in effect, your panic room would be restricted to only platforms that coreboot already supports, which, to mirror your "unnecessary complication" below, I would see as an "unnecessary limitation". > Being 'hardware agnostic' helps > in putting it on a new platform, assuming that platform conforms to the > restrictions, but it does not help in actual operation of the panic > room. So to me that would be an unnecessary complication. > Your example of a panic room ondie with a UART is not hardware agnostic > at all, you have pre-knowledge of the critical elements for establishing > a console. Call me confrontational, but I am going to dispute the "not hardware agnostic at all". If AMD and Intel agreed tomorrow to provide an UART ondie, accessed in the same fashion, on all of their future x86 chips, should we consider that this knowledge should be out of bounds? Or how about FPUs? Older x86 CPUs did not have an FPU unit ondie. Should we then consider that a program that just uses the FPU, since it has been for about the past 20 years, and no external hardware, can not be considered hardware agnostic and should have performed FPU detection? To me there is such thing as internal hardware, which is 100% fair game to use as soon as it is introduced, as, in the worst case scenario, it can easily be detected from the public CPU specs, and external hardware, which, and this is the critical point, may include elements that have not even been designed yet. So I would say that a panic room ondie with an UART, if all CPUs from the same line have this feature, is hardware agnostic. But then again, whether hardware agnosticism applies to a CPU that is irrelevant to coreboot doesn't bring much to the discussion. > OK, well how about the SIO support from UBRX being one of the SIO > modules that can be chosen. My main concern is allowing a simple method > of getting panic room support to work on boards that do not meet your > restrictions. That's one of my concerns too. As I indicated above, I am not planning to spend much time on getting non PnP SIOs, or PnP SIOs that require some weird init to be supported by UBRX. This being said, UBRX does support the VMWare virtual SIO, which is not PnP, and I think your idea about trying to be modular in UBRX is a good one. I can probably create a separate module for the VMWare non PnP SIO, which could be used as a template for other SIOs that people want to see supported, and that may not be detected in UBRX main. Such modules could then be selected and included conditionally at buildtime. But I do see the need for blanket detection being the main focus, if we can easily perform it and it avoids being limited to only what we know. With this, unconditional universality may actually apply to UBRX after all (though some may claim that if everything isn't supported at the same time, it's still not universal)... ;) >> Superiotool, not so much... Also picking a coreboot BIOS from one >> machine and soldering it into another, with the expectation that even if >> the motherboards have nothing in common but the flash they use, >> panic-room access will be available, can have its advantages, be it only >> for ghetto-style budget-constrained tinkerers. > > Shudders! Do we really want to encourage that? I most certainly see some merit in that for the following reasons: One is the consideration that people who may have a lot of time on their end may not be the ones with the highest means of income, and coreboot could probably use people with a time on their hand to support new motherboards. The second reason is that there are an awful lot of proprietary systems out there with soldered (non SPI) flash chips (Dell, Compaq, etc...), that could really benefit from coreboot. Past their prime, these systems can be obtained fairly cheaply, from corporate sales, etc., and therefore are a good target for coreboot development. However, when the first step of coreboot development is to install a BIOS socket as well as get an external flasher, this is likely to put potential contributors off. On the other hand, while there is obviously a risk that the U(*)BRX panic-room may not work, there's a good chance that it will and thus provide developers with both the possibility to explore their hardware and test a coreboot development payload. So I guess the question is: do we want a panic-room that only applies to systems that coreboot already support? Or do we want it to also be used as a tool for the adding of new systems. If only the former, then U(*)BRX is likely an overkill. But even a panic-room seems a bit of an overkill to me, as all you probably want from it is flash recovery... Regards, /Pete (*) Terms and Conditions apply From gerrit at coreboot.org Thu Jul 14 00:20:46 2011 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Thu, 14 Jul 2011 00:20:46 +0200 Subject: [coreboot] New patch to review: d9b1942 Set SB800 ROM decode size based on kconfig. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/94 -gerrit commit d9b19420728cf7bab913bd8f88d5fe34125b5664 Author: Marc Jones Date: Tue Jul 12 23:02:03 2011 -0600 Set SB800 ROM decode size based on kconfig. Change-Id: I46ea26b5534064fe1c7e2ce2b2f12cacf18a4d4d Signed-off-by: Marc Jones --- src/southbridge/amd/cimx/sb800/bootblock.c | 5 ++--- src/southbridge/amd/sb800/bootblock.c | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index aaec03c..170276a 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -49,10 +49,9 @@ static void enable_rom(void) dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21); pci_io_write_config32(dev, 0x48, dword); - /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ - /* Set the 4MB enable bits */ + /* Enable rom access */ word = pci_io_read_config16(dev, 0x6c); - word = 0xFFC0; + word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6); pci_io_write_config16(dev, 0x6c, word); } diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 82d80f0..18eae24 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -57,7 +57,7 @@ static void sb800_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ pci_write_config16(dev, 0x6e, 0xffff); } From gerrit at coreboot.org Thu Jul 14 00:43:03 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 14 Jul 2011 00:43:03 +0200 Subject: [coreboot] Patch merged into master: d9b1942 Set SB800 ROM decode size based on kconfig. References: Message-ID: the following patch was just integrated into master: commit d9b19420728cf7bab913bd8f88d5fe34125b5664 Author: Marc Jones Date: Tue Jul 12 23:02:03 2011 -0600 Set SB800 ROM decode size based on kconfig. Change-Id: I46ea26b5534064fe1c7e2ce2b2f12cacf18a4d4d Signed-off-by: Marc Jones See http://review.coreboot.org/94 for details. -gerrit From gerrit at coreboot.org Thu Jul 14 01:52:50 2011 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Thu, 14 Jul 2011 01:52:50 +0200 Subject: [coreboot] New patch to review: 02583ab Move AMD SB800 early clock setup. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/96 -gerrit commit 02583ab3f03ece4c73580bbaab72a28a70858537 Author: Marc Jones Date: Wed Jul 13 17:34:16 2011 -0600 Move AMD SB800 early clock setup. Move the AMD SB800 early clock setup code that is needed for early serial port operation from mainboard/romstage.c to sb800/bootblock.c. This prevents code duplication and simplifies porting. Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3 Signed-off-by: Scott Duplichan Signed-off-by: Marc Jones --- src/mainboard/amd/persimmon/romstage.c | 15 --------------- src/mainboard/asrock/e350m1/romstage.c | 15 --------------- src/southbridge/amd/cimx/sb800/bootblock.c | 21 +++++++++++++++++++++ 3 files changed, 21 insertions(+), 30 deletions(-) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 5ef5557..dfc2b6a 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -55,21 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); - if (boot_cpu()) - { - u8 reg8; - // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - outb(reg8, 0xCD7); - - // program SB800 MiscCntrl - *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ - } - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 29df530..38790cd 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,21 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr(0xc0010062, 0); - if (boot_cpu()) { - u8 reg8; - // SB800: Program AcpiMmioEn to enable MMIO access to MiscCntrl register - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - outb(0x24, 0xCD6); - outb(reg8, 0xCD7); - - // Program SB800 MiscCntrl - *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */ - } - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 170276a..593bd6b 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -84,10 +84,31 @@ static void enable_spi_fast_mode(void) pci_io_write_config32(dev, 0xa0, save); } +static void enable_clocks(void) +{ + u8 reg8; + u32 reg32; + volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40); + + // Program AcpiMmioEn to enable MMIO access to MiscCntrl register + outb(0x24, 0xCD6); + reg8 = inb(0xCD7); + reg8 |= 1; + reg8 &= ~(1 << 1); + outb(reg8, 0xCD7); + + // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz) + reg32 = *acpi_mmio; + reg32 &= ~((1 << 0) | (1 << 2)); + reg32 |= 1 << 1; + *acpi_mmio = reg32; +} + static void bootblock_southbridge_init(void) { /* Setup the rom access for 2M */ enable_rom(); enable_prefetch(); enable_spi_fast_mode(); + enable_clocks(); } From marcj303 at gmail.com Thu Jul 14 01:53:52 2011 From: marcj303 at gmail.com (Marc Jones) Date: Wed, 13 Jul 2011 17:53:52 -0600 Subject: [coreboot] [PATCH] move AMD SB800 early clock setup code to common file In-Reply-To: <9E3C0B70828D4C0ABF5531FBCE1EE996@asusp67> References: <9E3C0B70828D4C0ABF5531FBCE1EE996@asusp67> Message-ID: On Sat, Jul 9, 2011 at 11:37 PM, Scott Duplichan wrote: > The attached patch moves the AMD SB800 early clock setup code that is > needed for early serial port operation from mainboard/romstage.c to > sb800/bootblock.c. This prevents code duplication and simplifies porting. > > Signed-off-by: Scott Duplichan > http://review.coreboot.org/#change,96 -- http://se-eng.com From andrew.goodbody at tadpole.com Wed Jul 13 13:03:27 2011 From: andrew.goodbody at tadpole.com (Andrew Goodbody) Date: Wed, 13 Jul 2011 12:03:27 +0100 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1C8772.5010006@akeo.ie> References: <4E1B2C8B.5050001@akeo.ie> <4E1BE67C.6010805@tadpole.com> <4E1C8772.5010006@akeo.ie> Message-ID: <4E1D7B7F.3080807@tadpole.com> Sorry but my replies are having problems getting to the list. Greylisting is not supported by the company mail system. On 07/12/11 18:42, Pete Batard wrote: > On 2011.07.12 07:15, Andrew Goodbody wrote: >> Instead of attempting (and failing) to achieve universal support > > I'll start with the aside, that if "failing" means instantly supporting > more than 90% of Intel based motherboards produced in the last 10 years Yes, universal means everything. If you do not support everything then it is not universal. The use of universal sets false expectations. ... >> I would >> rather see a framework that could easily be configured with the >> appropriate SIO support and allow for board specific configuration if >> necessary. This should remove a lot of the complexity that gives very >> little advantage in trying for universal support. coreboot is built as >> hardware specific and I see no reason why the panic room support should >> not be the same. > > I guess we have different definition of a panic-room then. > From my dealings with Realtek SoCs, the way I see a panic-room is > something that is as hardware agnostic as possible. In the ideal case, > the panic-room is implemented ondie directly on a CPU that has an UART > unit, and therefore with no possible knowledge of the hardware > surrounding it. Such knowledge is to be provided by the user. This is > what the RTD1283 provides for instance (8KB bootblock, with console and > Y-modem upload in CPU ROM), and it is extremely powerful. The panic-room > is then intended as a means for users to perform hardware initialization > such as RAM or Flash access, as well as any other task they might > fathom. Hence, this is the implementation of a panic-room I have been > trying to follow, as it is the one that is most versatile and helpful to > users IMO. Yes we see different priorities for a panic room, but I think you misunderstood how much knowledge of the platform I was suggesting needed to be configured. You would choose the SIO/UART support, possibly specifying IO to use. The board specific configuration, if needed, was only for setting GPIOs etc in order to get the RS232 port working or configuring programmable clocks. That's all. To me a panic room should be as simple and bullet proof as possible and if that means pre-configuring the build then so be it. Being 'hardware agnostic' helps in putting it on a new platform, assuming that platform conforms to the restrictions, but it does not help in actual operation of the panic room. So to me that would be an unnecessary complication. Your example of a panic room ondie with a UART is not hardware agnostic at all, you have pre-knowledge of the critical elements for establishing a console. I was not suggesting building in knowledge of anything more than how to reach and configure the UART in order to establish a console, so we both agree that more complex operations would require interaction with the user. > >> Choosing the SIO support to configure for the panic >> room can be easily done from the output of superiotool. > > Provided superiotool knows about the chip, which may not be the case > yet. If Nuvoton introduces a new chip tomorrow, for which we haven't > seen a datasheet yet, I'm pretty sure UBRX will work just fine. OK, well how about the SIO support from UBRX being one of the SIO modules that can be chosen. My main concern is allowing a simple method of getting panic room support to work on boards that do not meet your restrictions. > Superiotool, not so much... Also picking a coreboot BIOS from one > machine and soldering it into another, with the expectation that even if > the motherboards have nothing in common but the flash they use, > panic-room access will be available, can have its advantages, be it only > for ghetto-style budget-constrained tinkerers. Shudders! Do we really want to encourage that? >> Additionally if it was done in such a way that the serial transport >> could be easily replaced by USB debug instead then we could really have >> something that would be useful for new boards. > > Well, depending how much space EHCI/xHCI USB support would take, I don't > see why UBRX wouldn't be able to provide both. But right now, > considering that there is still an awful lot of modern yet legacy based > systems out there that could benefit from coreboot support, > concentrating on native UART doesn't seem like a bad idea. All I was asking was that the design allowed for an alternate transport with minimum disruption. I did not suggest abandoning the work for UARTs. Cheers, Andrew > Regards, > > /Pete > From andrew.goodbody at tadpole.com Tue Jul 12 08:15:24 2011 From: andrew.goodbody at tadpole.com (Andrew Goodbody) Date: Tue, 12 Jul 2011 07:15:24 +0100 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1B2C8B.5050001@akeo.ie> References: <4E1B2C8B.5050001@akeo.ie> Message-ID: <4E1BE67C.6010805@tadpole.com> On 07/11/11 18:02, Pete Batard wrote: > Comments? Questions? Shoot away... Instead of attempting (and failing) to achieve universal support I would rather see a framework that could easily be configured with the appropriate SIO support and allow for board specific configuration if necessary. This should remove a lot of the complexity that gives very little advantage in trying for universal support. coreboot is built as hardware specific and I see no reason why the panic room support should not be the same. Choosing the SIO support to configure for the panic room can be easily done from the output of superiotool. Additionally if it was done in such a way that the serial transport could be easily replaced by USB debug instead then we could really have something that would be useful for new boards. Andrew From gerrit at coreboot.org Thu Jul 14 02:17:13 2011 From: gerrit at coreboot.org (Frank Vibrans III (efdesign98@gmail.com)) Date: Thu, 14 Jul 2011 02:17:13 +0200 Subject: [coreboot] New patch to review: deaac04 Add AMD Family 10 support to cpu folder References: Message-ID: Frank Vibrans III (efdesign98 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/97 -gerrit commit deaac0427cf5023064fb2975d1efcb1e934b1208 Author: efdesign98 Date: Wed Jul 13 17:16:13 2011 -0700 Add AMD Family 10 support to cpu folder This change adds the AMD Family 10 cpu support to the cpu folder. It also updates the makefiles of the Families 12 and 14 to take advantage of a pair of shared files that are moved to the cpu/agesa folder. Change-Id: Ibd3a50ea7a3028bd6a2d2583f021506b73e2fce2 Signed-off-by: Frank Vibrans Signed-off-by: efdesign98 --- src/cpu/amd/Makefile.inc | 1 - src/cpu/amd/agesa/Kconfig | 1 + src/cpu/amd/agesa/Makefile.inc | 4 + src/cpu/amd/agesa/apic_timer.c | 59 +++++ src/cpu/amd/agesa/cache_as_ram.inc | 97 +++++++++ src/cpu/amd/agesa/family10/Kconfig | 64 ++++++ src/cpu/amd/agesa/family10/Makefile.inc | 304 +++++++++++++++++++++++++++ src/cpu/amd/agesa/family10/chip.h | 23 ++ src/cpu/amd/agesa/family10/chip_name.c | 25 +++ src/cpu/amd/agesa/family10/model_10_init.c | 133 ++++++++++++ src/cpu/amd/agesa/family12/Makefile.inc | 4 - src/cpu/amd/agesa/family12/apic_timer.c | 58 ----- src/cpu/amd/agesa/family12/cache_as_ram.inc | 98 --------- src/cpu/amd/agesa/family14/Makefile.inc | 2 - src/cpu/amd/agesa/family14/apic_timer.c | 58 ----- src/cpu/amd/agesa/family14/cache_as_ram.inc | 98 --------- 16 files changed, 710 insertions(+), 319 deletions(-) diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index c29b730..e695473 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -15,4 +15,3 @@ subdirs-$(CONFIG_CPU_AMD_SC520) += sc520 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1 subdirs-$(CONFIG_AMD_AGESA) += agesa -subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa/f14 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 1aa9544..60bb74b 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -17,5 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index d0538b8..4331435 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -16,5 +16,9 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 + +ramstage-y += apic_timer.c +cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/apic_timer.c b/src/cpu/amd/agesa/apic_timer.c new file mode 100755 index 0000000..ec6ddd5 --- /dev/null +++ b/src/cpu/amd/agesa/apic_timer.c @@ -0,0 +1,59 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include +#include +#include +#include + +/* NOTE: We use the APIC TIMER register is to hold flags for AP init during + * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is + * redirected to udelay_tsc(). + */ + + +void init_timer(void) +{ + /* Set the apic timer to no interrupts and periodic mode */ + lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); + + /* Set the divider to 1, no divider */ + lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); + + /* Set the initial counter to 0xffffffff */ + lapic_write(LAPIC_TMICT, 0xffffffff); + +} + + +void udelay(u32 usecs) +{ + u32 start, value, ticks; + /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ + ticks = usecs * 200; + start = lapic_read(LAPIC_TMCCT); + do { + value = lapic_read(LAPIC_TMCCT); + } while((start - value) < ticks); + +} diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc new file mode 100755 index 0000000..f328db4 --- /dev/null +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/****************************************************************************** + * AMD Generic Encapsulated Software Architecture + * + * $Workfile:: cache_as_ram.inc + * + * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier + * + ****************************************************************************** + */ + +#include "gcccar.inc" + +/* + * XMM map: + * xmm0: BIST + * xmm1: backup ebx -- cpu_init_detected + */ + +.code32 +.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out + +cache_as_ram_setup: + + post_code(0xa0) + + /* enable SSE2 128bit instructions */ + /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ + + movl %cr4, %eax + orl $(3<<9), %eax + movl %eax, %cr4 + + /* Get the cpu_init_detected */ + mov $1, %eax + cpuid + shr $24, %ebx + + /* Save the BIST result */ + cvtsi2sd %ebp, %xmm0 + + /* for normal part %ebx already contain cpu_init_detected from fallback call */ + + /* Save the cpu_init_detected */ + cvtsi2sd %ebx, %xmm1 + + post_code(0xa1) + AMD_ENABLE_STACK + + post_code(0xa1) + + /* Restore the BIST result */ + cvtsd2si %xmm0, %edx + + /* Restore the cpu_init_detected */ + cvtsd2si %xmm1, %ebx + + pushl %ebx /* init detected */ + pushl %edx /* bist */ + call cache_as_ram_main + + /* Should never see this postcode */ + post_code(0xaf) +stop: + jmp stop + +disable_cache_as_ram: + /* Save return stack */ + movd %esp, %xmm0 + + AMD_DISABLE_STACK + + /* Restore the return stack */ + movd %xmm0, %esp + ret + +cache_as_ram_setup_out: + + diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig new file mode 100755 index 0000000..81070e5 --- /dev/null +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -0,0 +1,64 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY10 + bool + select CPU_AMD_MODEL_10XXX + select PCI_IO_CFG_EXT + +if CPU_AMD_AGESA_FAMILY10 + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x80000 + +config HAVE_INIT_TIMER + bool + default y + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + depends on CPU_AMD_AGESA_FAMILY10 + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD AGESA code. + +endif #CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family10/Makefile.inc b/src/cpu/amd/agesa/family10/Makefile.inc new file mode 100755 index 0000000..6981a47 --- /dev/null +++ b/src/cpu/amd/agesa/family10/Makefile.inc @@ -0,0 +1,304 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += chip_name.c +driver-y += model_10_init.c + +AGESA_ROOT = ../../../../vendorcode/amd/agesa/f10 + +#agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/F10IoCstate.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnprotoon.c + +agesa_lib_src = $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/mrdef.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10PowerPlane.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/HT/htInitReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebug.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Perf/IdsPerf.c +agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Control/IdsCtrl.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c + +#agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/ON/mrnmcton.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/OR/mrnprotoor.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/mrm.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/mruc.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/CPU/cpuRecovery.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/HT/htInitRecovery.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/mrntrain3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/DDR3/mrt3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/mrn.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/mrttpos.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/mrnmct.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/NB/mrndct.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/Mem/Tech/mrttsrc.c +#agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnS3on.c +#agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Control/IdsLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/OLSPARE/mfspr.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuMsgBasedC1e.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCoreLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/PreserveMailbox.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/NbCommon/htNbCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/NbCommon/htNbNonCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/NbCommon/htNbOptimization.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/NbCommon/htNbUtilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbCoherentFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbOptimizationFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbNonCoherentFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbUtilitiesFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam10/htNbSystemFam10.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatDynamicDiscovery.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatSets.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatGanging.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatSublinks.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatNoncoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatTrafficDistribution.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatOptimization.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htIds.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Features/htFeatRouting.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10PciTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10PowerCheck.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandId.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10Dmi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10Pstate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10Utilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10MsrTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10EarlyInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c + +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c +##agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph1.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph6DoubloonUpper.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph2.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph6FullyConnected.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph3Line.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph6TwinTriangles.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph3Triangle.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph6TwistedLadder.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4Degenerate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph7FullyConnected.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4FullyConnected.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph7TwistedLadder.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4Kite.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph8DoubloonM.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4Line.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph8FullyConnected.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4Square.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph8Ladder.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph4Star.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph5FullyConnected.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph8TwistedLadder.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph5TwistedLadder.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htGraph/htGraph6DoubloonLower.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/HY/mmflowhy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/NDINTLV/mfndi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnS3hy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnhy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mndcthy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnflowhy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnidendimmhy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnmcthy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnothy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnParTrainHy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnphyhy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnprotohy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/HY/mnreghy.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/HY/mprhy3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/HY/mpuhy3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/HY/mpshy3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/HY/marhy3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/HY/mauhy3.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHtAssist.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x10/F10PmNbPstateInit.c + +##C32 +#agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/C32/mmflowC32.c + +romstage-y += $(agesa_lib_src) +ramstage-y += $(agesa_lib_src) + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm + diff --git a/src/cpu/amd/agesa/family10/chip.h b/src/cpu/amd/agesa/family10/chip.h new file mode 100755 index 0000000..d5a749b --- /dev/null +++ b/src/cpu/amd/agesa/family10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_agesa_family10_ops; + +struct cpu_amd_agesa_family10_config { +}; diff --git a/src/cpu/amd/agesa/family10/chip_name.c b/src/cpu/amd/agesa/family10/chip_name.c new file mode 100755 index 0000000..d99769c --- /dev/null +++ b/src/cpu/amd/agesa/family10/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations cpu_amd_agesa_family10_ops = { + CHIP_NAME("AMD CPU Family 10h") +}; diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c new file mode 100755 index 0000000..8c1cfad --- /dev/null +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "northbridge/amd/agesa/family10/amdfam10.h" + +#define MCI_STATUS 0x401 + +static msr_t rdmsr_amd(u32 index) +{ + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; +} + +static void wrmsr_amd(u32 index, msr_t msr) +{ + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); +} + +static void model_10_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n"); + + u8 i; + msr_t msr; +#if CONFIG_LOGICAL_CPUS == 1 + u32 siblings; +#endif + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + amd_setup_mtrrs(); + x86_mtrr_check(); + + disable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + enable_cache(); + + /* Enable the local cpu apics */ + setup_lapic(); + + /* Set the processor name string */ + // init_processor_name(); + + +#if CONFIG_LOGICAL_CPUS == 1 + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_10_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { 0, 0 }, +}; + +static const struct cpu_driver model_10 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 4e69355..5aa4127 100755 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -320,7 +320,3 @@ subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm - -ramstage-y += apic_timer.c - -cpu_incs += $(src)/cpu/amd/agesa/family12/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/family12/apic_timer.c b/src/cpu/amd/agesa/family12/apic_timer.c deleted file mode 100755 index 26d3f88..0000000 --- a/src/cpu/amd/agesa/family12/apic_timer.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include -#include -#include -#include - -/* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is - * redirected to udelay_tsc(). - */ - - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); -} - - -void udelay(u32 usecs) -{ - u32 start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} diff --git a/src/cpu/amd/agesa/family12/cache_as_ram.inc b/src/cpu/amd/agesa/family12/cache_as_ram.inc deleted file mode 100755 index 98da3cb..0000000 --- a/src/cpu/amd/agesa/family12/cache_as_ram.inc +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/****************************************************************************** - * AMD Generic Encapsulated Software Architecture - * - * $Workfile:: cache_as_ram.inc - * - * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier - * - ****************************************************************************** - */ - -#include "gcccar.inc" - -/* - * XMM map: - * xmm0: BIST - * xmm1: backup ebx -- cpu_init_detected - */ - -.code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out - -cache_as_ram_setup: - - post_code(0xa0) - - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3<<9), %eax - movl %eax, %cr4 - - /* Get the cpu_init_detected */ - mov $1, %eax - cpuid - shr $24, %ebx - - /* Save the BIST result */ - cvtsi2sd %ebp, %xmm0 - - /* for normal part %ebx already contain cpu_init_detected from fallback call */ - - /* Save the cpu_init_detected */ - cvtsi2sd %ebx, %xmm1 - - post_code(0xa1) - AMD_ENABLE_STACK - - post_code(0xa1) - - /* Restore the BIST result */ - cvtsd2si %xmm0, %edx - - /* Restore the cpu_init_detected */ - cvtsd2si %xmm1, %ebx - - pushl %ebx /* init detected */ - pushl %edx /* bist */ - call cache_as_ram_main - - /* Should never see this postcode */ - post_code(0xaf) -stop: - jmp stop - -disable_cache_as_ram: - /* Save return stack */ - cvtsi2sd %esp, %xmm0 - - AMD_DISABLE_STACK - - /* Restore the return stack */ - cvtsd2si %xmm0, %esp - - ret - -cache_as_ram_setup_out: - - diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 1e0f37b..3039300 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -278,5 +278,3 @@ subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm -ramstage-y += apic_timer.c -cpu_incs += $(src)/cpu/amd/agesa/family14/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/family14/apic_timer.c b/src/cpu/amd/agesa/family14/apic_timer.c deleted file mode 100644 index 26d3f88..0000000 --- a/src/cpu/amd/agesa/family14/apic_timer.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include -#include -#include -#include - -/* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is - * redirected to udelay_tsc(). - */ - - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); -} - - -void udelay(u32 usecs) -{ - u32 start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} diff --git a/src/cpu/amd/agesa/family14/cache_as_ram.inc b/src/cpu/amd/agesa/family14/cache_as_ram.inc deleted file mode 100644 index 98da3cb..0000000 --- a/src/cpu/amd/agesa/family14/cache_as_ram.inc +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/****************************************************************************** - * AMD Generic Encapsulated Software Architecture - * - * $Workfile:: cache_as_ram.inc - * - * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier - * - ****************************************************************************** - */ - -#include "gcccar.inc" - -/* - * XMM map: - * xmm0: BIST - * xmm1: backup ebx -- cpu_init_detected - */ - -.code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out - -cache_as_ram_setup: - - post_code(0xa0) - - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3<<9), %eax - movl %eax, %cr4 - - /* Get the cpu_init_detected */ - mov $1, %eax - cpuid - shr $24, %ebx - - /* Save the BIST result */ - cvtsi2sd %ebp, %xmm0 - - /* for normal part %ebx already contain cpu_init_detected from fallback call */ - - /* Save the cpu_init_detected */ - cvtsi2sd %ebx, %xmm1 - - post_code(0xa1) - AMD_ENABLE_STACK - - post_code(0xa1) - - /* Restore the BIST result */ - cvtsd2si %xmm0, %edx - - /* Restore the cpu_init_detected */ - cvtsd2si %xmm1, %ebx - - pushl %ebx /* init detected */ - pushl %edx /* bist */ - call cache_as_ram_main - - /* Should never see this postcode */ - post_code(0xaf) -stop: - jmp stop - -disable_cache_as_ram: - /* Save return stack */ - cvtsi2sd %esp, %xmm0 - - AMD_DISABLE_STACK - - /* Restore the return stack */ - cvtsd2si %xmm0, %esp - - ret - -cache_as_ram_setup_out: - - From gerrit at coreboot.org Thu Jul 14 02:33:53 2011 From: gerrit at coreboot.org (Frank Vibrans III (efdesign98@gmail.com)) Date: Thu, 14 Jul 2011 02:33:53 +0200 Subject: [coreboot] New patch to review: 30da094 Add AMD Family 10 cpu support to northbridge folder References: Message-ID: Frank Vibrans III (efdesign98 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/98 -gerrit commit 30da094c211e30e6564cb4e76b9b8e2884f318e6 Author: efdesign98 Date: Wed Jul 13 17:33:10 2011 -0700 Add AMD Family 10 cpu support to northbridge folder This change adds the AMD Family 10 cpu support to the northbridge folder. The northbridge/amd/agesa Kconfig and Makefile.inc are changed as well. Change-Id: Id76e9fa388c79ac469a673aaedaa4f1bfd7619d9 Signed-off-by: Frank Vibrans Signed-off-by: efdesign98 --- src/northbridge/amd/agesa/Kconfig | 1 + src/northbridge/amd/agesa/Makefile.inc | 1 + src/northbridge/amd/agesa/family10/Kconfig | 49 + src/northbridge/amd/agesa/family10/Makefile.inc | 22 + src/northbridge/amd/agesa/family10/amdfam10.h | 101 ++ src/northbridge/amd/agesa/family10/bootblock.c | 29 + src/northbridge/amd/agesa/family10/chip.h | 24 + src/northbridge/amd/agesa/family10/northbridge.c | 1518 ++++++++++++++++++++ src/northbridge/amd/agesa/family10/northbridge.h | 26 + src/northbridge/amd/agesa/family10/reset_test.h | 52 + .../amd/agesa/family10/root_complex/Kconfig | 2 + .../amd/agesa/family10/root_complex/chip.h | 24 + src/northbridge/amd/agesa/family10/ssdt.asl | 346 +++++ 13 files changed, 2195 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index d5fde57..463da5d 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,6 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 96798fc..1da8f60 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -16,5 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig new file mode 100755 index 0000000..62a6cd4 --- /dev/null +++ b/src/northbridge/amd/agesa/family10/Kconfig @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +config NORTHBRIDGE_AMD_AGESA_FAMILY10 + bool + select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_SMBUS + select HYPERTRANSPORT_PLUGIN_SUPPORT + select MMCONF_SUPPORT + select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX + +if NORTHBRIDGE_AMD_AGESA_FAMILY10 +config HT3_SUPPORT + bool + default y +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n +config MMCONF_BASE_ADDRESS + hex + default 0xE0000000 +config MMCONF_BUS_NUMBER + int + default 256 +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/amd/agesa/family10/bootblock.c" +endif #NORTHBRIDGE_AMD_AGESA_FAMILY10 + +source "src/northbridge/amd/agesa/family10/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family10/Makefile.inc b/src/northbridge/amd/agesa/family10/Makefile.inc new file mode 100755 index 0000000..8f0fe0d --- /dev/null +++ b/src/northbridge/amd/agesa/family10/Makefile.inc @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c + +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h new file mode 100755 index 0000000..e6f9d81 --- /dev/null +++ b/src/northbridge/amd/agesa/family10/amdfam10.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMDFAM10_H +#define AMDFAM10_H + +#include + +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define BU_CFG_MSR 0xC0011023 +#define BU_CFG2_MSR 0xC001102A + +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 + +/* Definitions of various FAM10 registers */ +/* Function 0 */ +#define HT_TRANSACTION_CONTROL 0x68 +#define HTTC_DIS_RD_B_P (1 << 0) +#define HTTC_DIS_RD_DW_P (1 << 1) +#define HTTC_DIS_WR_B_P (1 << 2) +#define HTTC_DIS_WR_DW_P (1 << 3) +#define HTTC_DIS_MTS (1 << 4) +#define HTTC_CPU1_EN (1 << 5) +#define HTTC_CPU_REQ_PASS_PW (1 << 6) +#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) +#define HTTC_DIS_P_MEM_C (1 << 8) +#define HTTC_DIS_RMT_MEM_C (1 << 9) +#define HTTC_DIS_FILL_P (1 << 10) +#define HTTC_RSP_PASS_PW (1 << 11) +#define HTTC_BUF_REL_PRI_SHIFT 13 +#define HTTC_BUF_REL_PRI_MASK 3 +#define HTTC_BUF_REL_PRI_64 0 +#define HTTC_BUF_REL_PRI_16 1 +#define HTTC_BUF_REL_PRI_8 2 +#define HTTC_BUF_REL_PRI_2 3 +#define HTTC_LIMIT_CLDT_CFG (1 << 15) +#define HTTC_LINT_EN (1 << 16) +#define HTTC_APIC_EXT_BRD_CST (1 << 17) +#define HTTC_APIC_EXT_ID (1 << 18) +#define HTTC_APIC_EXT_SPUR (1 << 19) +#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) +#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 +#define HTTC_DS_NP_REQ_LIMIT_MASK 3 +#define HTTC_DS_NP_REQ_LIMIT_NONE 0 +#define HTTC_DS_NP_REQ_LIMIT_1 1 +#define HTTC_DS_NP_REQ_LIMIT_4 2 +#define HTTC_DS_NP_REQ_LIMIT_8 3 + +/* Function 1 */ + +/* Function 2 */ + +/* Function 3 */ + + +/* Function 5 for FBDIMM */ +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) +#define NonCoherent (1 << 2) +#define ConnectionPending (1 << 4) + +#if CONFIG_MAX_PHYSICAL_CPUS > 8 + #if CONFIG_MAX_PHYSICAL_CPUS > 32 + #define NODE_NUMS 64 + #else + #define NODE_NUMS 32 + #endif +#else + #define NODE_NUMS 8 +#endif + +#ifdef __PRE_RAM__ +#if NODE_NUMS==64 + #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else + #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif +#endif + +#endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c new file mode 100755 index 0000000..f6ae8be --- /dev/null +++ b/src/northbridge/amd/agesa/family10/bootblock.c @@ -0,0 +1,29 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include +#include +#include + +static void bootblock_northbridge_init(void) { +} diff --git a/src/northbridge/amd/agesa/family10/chip.h b/src/northbridge/amd/agesa/family10/chip.h new file mode 100755 index 0000000..c0ac56e --- /dev/null +++ b/src/northbridge/amd/agesa/family10/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family10_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family10_ops; diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c new file mode 100755 index 0000000..b3e4c63 --- /dev/null +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -0,0 +1,1518 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG_LOGICAL_CPUS==1 +#include +#endif + +#include +#include +#include +#include +#include "root_complex/chip.h" +#include "northbridge.h" +#include "amdfam10.h" +#include "chip.h" + +extern uint32_t agesawrapper_amdinitmid(void); + +typedef struct amdfam10_sysconf_t sys_info_conf_t; +typedef struct dram_base_mask { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +} dram_base_mask_t; + + +struct amdfam10_sysconf_t sysconf; +static device_t __f0_dev[NODE_NUMS]; +static device_t __f1_dev[NODE_NUMS]; +static device_t __f2_dev[NODE_NUMS]; +static device_t __f4_dev[NODE_NUMS]; +static unsigned fx_devs = 0; + +#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! +#endif + +static dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + device_t dev; + dram_base_mask_t d; + dev = __f1_dev[0]; + +#if CONFIG_EXT_CONF_SUPPORT == 1 + /* I will use ext space only for simple */ + pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8] + d.mask = pci_read_config32(dev, 0x114); // enable is bit 0 + pci_write_config32(dev, 0x110, nodeid | (0<<28)); + d.base = pci_read_config32(dev, 0x114) & 0x1fffff00; //[47:27] at [28:8]; +#else + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp<<21; + + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + + d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.base |= temp<<21; +#endif + return d; +} + +#if CONFIG_EXT_CONF_SUPPORT +static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, + u32 busn_min, u32 busn_max, + u32 type) +{ + device_t dev; + u32 i; + u32 tempreg; + u32 index_min, index_max; + u32 dest_min, dest_max; + index_min = busn_min>>2; dest_min = busn_min - (index_min<<2); + index_max = busn_max>>2; dest_max = busn_max - (index_max<<2); + + // three case: index_min==index_max, index_min+1=index_max; index_min+11) { + tempreg = 0; + for (i=0; i<=3; i++) { + tempreg &= ~(0xff<<(i*8)); + tempreg |= (cfg_map_dest<<(i*8)); + } + for (i=index_min+1; i(0xe0-1)) {// use next segn + u32 segn = (segbusn >> 8) & 0x0f; + segn++; + segbusn = segn<<8; + } + if (segbusn>>8) { + u32 val; + val = pci_read_config32(dev, 0x160); + val &= ~(0xf<<25); + val |= (segbusn & 0xf00)<<(25-8); + pci_write_config32(dev, 0x160, val); + } + + return segbusn; +} +#endif + +static u32 get_io_addr_index(u32 nodeid, u32 linkn) +{ + u32 index; + + for (index=0; index<256; index++) { + if ((sysconf.conf_io_addrx[index+4] == 0)) { + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); + return index; + } + } + + return 0; + +} + +static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) +{ + u32 index; + + for (index=0; index<64; index++) { + if ((sysconf.conf_mmio_addrx[index+8] == 0)) { + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); + return index; + } + } + + return 0; +} + +static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 io_min, u32 io_max) +{ + u32 val; +#if CONFIG_EXT_CONF_SUPPORT + if (reg!=0x110) { +#endif + /* io range allocation */ + index = (reg-0xc0)>>3; +#if CONFIG_EXT_CONF_SUPPORT + } else { + index+=4; + } +#endif + + val = (nodeid & 0x3f); // 6 bits used + sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid + val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit + + if (sysconf.io_addr_num<(index+1)) + sysconf.io_addr_num = index+1; +} + +static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 mmio_min, u32 mmio_max) +{ + u32 val; +#if CONFIG_EXT_CONF_SUPPORT + if (reg!=0x110) { +#endif + /* io range allocation */ + index = (reg-0x80)>>3; +#if CONFIG_EXT_CONF_SUPPORT + } else { + index += 8; + } +#endif + + val = (nodeid & 0x3f) ; // 6 bits used + sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn + val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit + + if (sysconf.mmio_addr_num<(index+1)) + sysconf.mmio_addr_num = index+1; +} + +static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + + u32 i; + u32 tempreg; +#if CONFIG_EXT_CONF_SUPPORT + if (reg!=0x110) { +#endif + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; ilink[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + for (i=0; i 3, We should use extend space + if (io_min>io_max) return; + // for nodeid at first + cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0); + + set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4); + + // all other nodes + cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0); + for (j = 0; j< sysconf.nodes; j++) { + if (j== nodeid) continue; + set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4); + } +#endif +} + +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + + u32 i; + u32 tempreg; +#if CONFIG_EXT_CONF_SUPPORT + if (reg!=0x110) { +#endif + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + for (i=0; i 3, We should use extend space + // for nodeid at first + u32 enable; + + if (mmio_min>mmio_max) { + return; + } + + enable = 1; + dev = __f1_dev[nodeid]; + tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0); + pci_write_config32(dev, 0x110, index | (2<<28)); + pci_write_config32(dev, 0x114, tempreg); + + tempreg = ((mmio_max>>3) & 0x1fffff00) | enable; + pci_write_config32(dev, 0x110, index | (3<<28)); + pci_write_config32(dev, 0x114, tempreg); + + // all other nodes + tempreg = ((mmio_min>>3) & 0x1fffff00) | (0<<6) | (nodeid<<0); + for (j = 0; j< sysconf.nodes; j++) { + if (j== nodeid) continue; + dev = __f1_dev[j]; + pci_write_config32(dev, 0x110, index | (2<<28)); + pci_write_config32(dev, 0x114, tempreg); + } + + tempreg = ((mmio_max>>3) & 0x1fffff00) | enable; + for (j = 0; j< sysconf.nodes; j++) { + if(j==nodeid) continue; + dev = __f1_dev[j]; + pci_write_config32(dev, 0x110, index | (3<<28)); + pci_write_config32(dev, 0x114, tempreg); + } +#endif +} + +static device_t get_node_pci(u32 nodeid, u32 fn) +{ +#if NODE_NUMS == 64 + if (nodeid < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } + +#else + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); +#endif +} + +static unsigned int read_nb_cfg_54(void) +{ + msr_t msr; + msr = rdmsr(NB_CFG_MSR); + return (( msr.hi >> (54-32)) & 1); +} + +static void get_fx_devs(void) +{ + int i; + for (i = 0; i < NODE_NUMS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); + } +} + +static u32 f1_read_config32(unsigned reg) +{ + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned reg, u32 value) +{ + int i; + if (fx_devs == 0) + get_fx_devs(); + for(i = 0; i < fx_devs; i++) { + device_t dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static u32 amdfam10_nodeid(device_t dev) +{ +#if NODE_NUMS == 64 + unsigned busn; + busn = dev->bus->secondary; + if (busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; + } else { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + } + +#else + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; +#endif +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid<<4) | (linkn<<12); + /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, + 0x3c0:0x3df */ + f1_write_config32(0xf4, val); + +} + +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link = 0; + int result; + res = 0; + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for (link = 0; !res && (link < 8); link++) { + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + } + result = 2; + if (res) { + result = 0; + if ( (goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + return result; +} + +static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xd8) { + reg = free_reg; // if no free, the free_reg still be 0 + } + + //Ext conf space + if(!reg) { + //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range + u32 index = get_io_addr_index(nodeid, link); + reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + + return resource; +} + +static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } + + //Ext conf space + if (!reg) { + //because of Extend conf space, we will never run out of reg, + // but we need one index to differ them. so same node and + // same link can have multi range + u32 index = get_mmio_addr_index(nodeid, link); + reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 + + } + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + return resource; +} + +static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdfam10_find_iopair(dev, nodeid, link); + if (resource) { + u32 align; +#if CONFIG_EXT_CONF_SUPPORT == 1 + if((resource->index & 0x1fff) == 0x1110) { // ext + align = 8; + } + else +#endif + align = log2(HT_IO_HOST_ALIGN); + resource->base = 0; + resource->size = 0; + resource->align = align; + resource->gran = align; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam10_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + +#if CONFIG_EXT_CONF_SUPPORT == 1 + if ((resource->index & 0x1fff) == 0x1110) { // ext + normalize_resource(resource); + } +#endif + + } + + /* Initialize the memory constraints on the current bus */ + resource = amdfam10_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; +#if CONFIG_EXT_CONF_SUPPORT == 1 + if ((resource->index & 0x1fff) == 0x1110) { // ext + normalize_resource(resource); + } +#endif + } +} + +static void amdfam10_read_resources(device_t dev) +{ + u32 nodeid; + struct bus *link; + nodeid = amdfam10_nodeid(dev); + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam10_link_read_bases(dev, nodeid, link->link_num); + } + } +} + +static void amdfam10_set_resource(device_t dev, struct resource *resource, + u32 nodeid) +{ + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) { + return; + } + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); + + if (resource->flags & IORESOURCE_IO) { + + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] + store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); + } + resource->flags |= IORESOURCE_STORED; + sprintf(buf, " ", + nodeid, link_num); + report_resource_stored(dev, resource, buf); +} + +/** + * I tried to reuse the resource allocation code in amdfam10_set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +{ + struct bus *link; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 + extern device_t vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); + set_vga_enable_reg(nodeid, link->link_num); +} + +static void amdfam10_set_resources(device_t dev) +{ + unsigned nodeid; + struct bus *bus; + struct resource *res; + + /* Find the nodeid */ + nodeid = amdfam10_nodeid(dev); + + amdfam10_create_vga_resource(dev, nodeid); + + /* Set each resource we have found */ + for (res = dev->resource_list; res; res = res->next) { + amdfam10_set_resource(dev, res, nodeid); + } + + for (bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) { + assign_resources(bus); + } + } +} + +static void mcf0_control_init(struct device *dev) +{ +} + +static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +{ + unsigned nodeid; + struct bus *link; + unsigned sblink = sysconf.sblk; + device_t io_hub = NULL; + u32 next_unitid = 0xff; + + nodeid = amdfam10_nodeid(dev); + if (nodeid == 0) { + for (link = dev->link_list; link; link = link->next) { + if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[3] */ + io_hub = link->children; + if (!io_hub || !io_hub->enabled) { + die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); + } + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + } + } + } + + return max; +} + +static struct device_operations northbridge_operations = { + .read_resources = amdfam10_read_resources, + .set_resources = amdfam10_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = mcf0_control_init, + .scan_bus = amdfam10_scan_chains, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver mcf0_driver __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1200, +}; + +struct chip_operations northbridge_amd_agesa_family10_ops = { + CHIP_NAME("AMD FAM10 Northbridge") + .enable_dev = 0, +}; + + +static void amdfam10_domain_read_resources(device_t dev) +{ + unsigned reg; + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg<0xc0) { // mmio + nodeid = (limit & 0xf) + (base&0x30); + } else { // io + nodeid = (limit & 0xf) + ((base>>4)&0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + +#if CONFIG_PCI_64BIT_PREF_MEM == 0 + pci_domain_read_resources(dev); +#else + struct bus *link; + struct resource *resource; + for (link=dev->link_list; link; link = link->next) { + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0|(link->link_num<<2)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + } +#endif +} + +static void amdfam10_domain_enable_resources(device_t dev) +{ + u32 val; + /* Must be called after PCI enumeration and resource allocation */ + printk(BIOS_DEBUG, "\nFam10 - domain_enable_resources: AmdInitMid.\n"); + val = agesawrapper_amdinitmid(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + } + printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); +} + + +static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) +{ + struct resource *min; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; +} + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; + +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + + for (i = 0; i < sysconf.nodes; i++) { + dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(i); + if (!(d.mask & 1)) continue; // no memory on this node + + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i=0; i 4 *1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + + limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif + +#if CONFIG_WRITE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + +#if CONFIG_GFXUMA == 1 +extern uint64_t uma_memory_base, uma_memory_size; + +static void add_uma_resource(struct device *dev, int index) +{ + struct resource *resource; + + printk(BIOS_DEBUG, "Adding UMA memory area\n"); + resource = new_resource(dev, index); + resource->base = (resource_t) uma_memory_base; + resource->size = (resource_t) uma_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} +#endif + +static void amdfam10_domain_set_resources(device_t dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + struct resource *io, *mem1, *mem2; + struct resource *res; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; +#endif + +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + + for (link = dev->link_list; link; link = link->next) { + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first + */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + } + + for (res = &dev->resource_list; res; res = res->next) + { + res->flags |= IORESOURCE_ASSIGNED; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = my_find_pci_tolm(link, pci_tolm); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +/* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } + +#endif + + idx = 0x10; + for (i = 0; i < sysconf.nodes; i++) { + dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T + d = get_dram_base_mask(i); + + if (!(d.mask & 1)) continue; + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + sizek = limitk - basek; + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accomodate pci memory space */ + if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; +#if CONFIG_WRITE_HIGH_TABLES==1 + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, + high_tables_base); + } +#endif + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + +#if CONFIG_GFXUMA == 1 + /* Deduct uma memory before reporting because + * this is what the mtrr code expects */ + sizek -= uma_memory_size / 1024; +#endif + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; +#if CONFIG_WRITE_HIGH_TABLES==1 + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif + } + +#if CONFIG_GFXUMA == 1 + add_uma_resource(dev, 7); +#endif + + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + +static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +{ + u32 reg; + int i; + struct bus *link; + /* Unmap all of the HT chains */ + for (reg = 0xe0; reg <= 0xec; reg += 4) { + f1_write_config32(reg, 0); + } +#if CONFIG_EXT_CONF_SUPPORT == 1 + // all nodes + for (i = 0; i< sysconf.nodes; i++) { + int index; + for(index = 0; index < 64; index++) { + pci_write_config32(__f1_dev[i], 0x110, index | (6<<28)); + pci_write_config32(__f1_dev[i], 0x114, 0); + } + + } +#endif + + + for (link = dev->link_list; link; link = link->next) { + max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); + } + + /* Tune the hypertransport transaction for best performance. + * Including enabling relaxed ordering if it is safe. + */ + get_fx_devs(); + for (i = 0; i < fx_devs; i++) { + device_t f0_dev; + f0_dev = __f0_dev[i]; + if (f0_dev && f0_dev->enabled) { + u32 httc; + httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); + httc &= ~HTTC_RSP_PASS_PW; + if (!dev->link_list->disable_relaxed_ordering) { + httc |= HTTC_RSP_PASS_PW; + } + printk(BIOS_SPEW, "%s passpw: %s\n", + dev_path(dev), + (!dev->link_list->disable_relaxed_ordering)? + "enabled":"disabled"); + pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); + } + } + return max; +} + + +static struct device_operations pci_domain_ops = { + .read_resources = amdfam10_domain_read_resources, + .set_resources = amdfam10_domain_set_resources, + .enable_resources = amdfam10_domain_enable_resources, + .init = NULL, + .scan_bus = amdfam10_domain_scan_bus, +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + + +static void sysconf_init(device_t dev) // first node +{ + sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 + sysconf.segbit = 0; + sysconf.ht_c_num = 0; + + unsigned ht_c_index; + + for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + sysconf.ht_c_conf_bus[ht_c_index] = 0; + } + + sysconf.nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] + + /* Find the bootstrap processors apicid */ + sysconf.bsp_apicid = lapicid(); +} + +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + +/* dummy read_resources */ +static void lapic_read_resources(device_t dev) +{ +} + +static struct device_operations lapic_ops = { + .read_resources = lapic_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, +}; + +static u32 cpu_bus_scan(device_t dev, u32 max) +{ + struct bus *cpu_bus; + device_t dev_mc; +#if CONFIG_CBB + device_t pci_domain; +#endif + int i,j; + int nodes; + unsigned nb_cfg_54; + unsigned siblings; + int cores_found; + int disable_siblings; + unsigned ApicIdCoreIdSize; + + nb_cfg_54 = 0; + ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf); + if (ApicIdCoreIdSize) { + siblings = (1<bus) { + printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); + + } else { + printk(BIOS_DEBUG, " but it is not under pci_domain directly "); + } + printk(BIOS_DEBUG, "\n"); + } + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + while (dev_mc) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + dev_mc = dev_mc->sibling; + } + } + } + } + } + +#endif + + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + die(""); + } + + sysconf_init(dev_mc); + + nodes = sysconf.nodes; + +#if CONFIG_CBB && (NODE_NUMS > 32) + if (nodes>32) { // need to put node 32 to node 63 to bus 0xfe + if (pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); + } + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; + } +#endif + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < nodes; i++) { + device_t cdb_dev, cpu; + struct device_path cpu_path; + unsigned busn, devn; + struct bus *pbus; + + busn = CONFIG_CBB; + devn = CONFIG_CDB+i; + pbus = dev_mc->bus; +#if CONFIG_CBB && (NODE_NUMS > 32) + if (i>=32) { + busn--; + devn-=32; + pbus = pci_domain->link_list->next); + } +#endif + + /* Find the cpu's pci device */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for(fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + } + if (cdb_dev) { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + int linknum; +#if CONFIG_HT3_SUPPORT==1 + linknum = 8; +#else + linknum = 4; +#endif + add_more_links(cdb_dev, linknum); + } + + cores_found = 0; // one core + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); + if (cdb_dev && cdb_dev->enabled) { + j = pci_read_config32(cdb_dev, 0xe8); + cores_found = (j >> 12) & 3; // dev is func 3 + if (siblings > 3) + cores_found |= (j >> 13) & 4; + printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cdb_dev), cores_found); + } + + u32 jj; + if (disable_siblings) { + jj = 0; + } else { + jj = cores_found; + } + + for (j = 0; j <=jj; j++ ) { + extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + u32 modules = TopologyConfiguration.PlatformNumberOfModules; + u32 lapicid_start = 0; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ + if (nodes * (cores_found + 1) >= 0x10) { + lapicid_start = 0x10; + } + cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); + + /* See if I can find the cpu */ + cpu = find_dev_path(cpu_bus, &cpu_path); + + /* Enable the cpu if I have the processor */ + if (cdb_dev && cdb_dev->enabled) { + if (!cpu) { + cpu = alloc_dev(cpu_bus, &cpu_path); + } + if (cpu) { + cpu->enabled = 1; + } + } + + /* Disable the cpu if I don't have the processor */ + if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + cpu->enabled = 0; + } + + /* Report what I have done */ + if (cpu) { + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + if (cpu->path.type == DEVICE_PATH_APIC) { + cpu->ops = &lapic_ops; + } + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } + + } //j + } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static void cpu_bus_read_resources(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif +} + +static void cpu_bus_set_resources(device_t dev) +{ + struct resource *resource = find_resource(dev, 0xc0010058); + if (resource) { + report_resource_stored(dev, resource, " "); + } + pci_dev_set_resources(dev); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + +static void root_complex_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_amd_agesa_family10_root_complex_ops = { + CHIP_NAME("AMD FAM10 Root Complex") + .enable_dev = root_complex_enable_dev, +}; + diff --git a/src/northbridge/amd/agesa/family10/northbridge.h b/src/northbridge/amd/agesa/family10/northbridge.h new file mode 100755 index 0000000..0530ee7 --- /dev/null +++ b/src/northbridge/amd/agesa/family10/northbridge.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_AMD_AGESA_FAM10H_H +#define NORTHBRIDGE_AMD_AGESA_FAM10H_H + +static struct device_operations pci_domain_ops; +static struct device_operations cpu_bus_ops; + +#endif /* NORTHBRIDGE_AMD_AGESA_FAM10H_H */ diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h new file mode 100755 index 0000000..5b24f2d --- /dev/null +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * copy from src/northbridge/amd/amdfam10/reset_test.c + */ + +#ifndef _RESET_TEST_H_ +#define _RESET_TEST_H_ + +#include "amdfam10.h" /* NODE_PCI */ + +#define NODE_ID 0x60 +#define HT_INIT_CONTROL 0x6c +#define HTIC_ColdR_Detect (1<<4) +#define HTIC_BIOSR_Detect (1<<5) +#define HTIC_INIT_Detect (1<<6) + +static inline u32 warm_reset_detect(u8 nodeid) +{ + u32 htic; + device_t device; + device = NODE_PCI(nodeid, 0); + htic = pci_io_read_config32(device, HT_INIT_CONTROL); + return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); +} + +static inline void distinguish_cpu_resets(u8 nodeid) +{ + u32 htic; + device_t device; + device = NODE_PCI(nodeid, 0); + htic = pci_io_read_config32(device, HT_INIT_CONTROL); + htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; + pci_io_write_config32(device, HT_INIT_CONTROL, htic); +} + +#endif diff --git a/src/northbridge/amd/agesa/family10/root_complex/Kconfig b/src/northbridge/amd/agesa/family10/root_complex/Kconfig new file mode 100755 index 0000000..345896b --- /dev/null +++ b/src/northbridge/amd/agesa/family10/root_complex/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX + bool diff --git a/src/northbridge/amd/agesa/family10/root_complex/chip.h b/src/northbridge/amd/agesa/family10/root_complex/chip.h new file mode 100755 index 0000000..15a2e1a --- /dev/null +++ b/src/northbridge/amd/agesa/family10/root_complex/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family10_root_complex_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family10_root_complex_ops; diff --git a/src/northbridge/amd/agesa/family10/ssdt.asl b/src/northbridge/amd/agesa/family10/ssdt.asl new file mode 100755 index 0000000..e637f1f --- /dev/null +++ b/src/northbridge/amd/agesa/family10/ssdt.asl @@ -0,0 +1,346 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file + */ + +DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM15H", "AMD-ACPI", 0x1000) +{ + /* + * These objects were referenced but not defined in this table + */ + External (\_SB_.PCI0, DeviceObj) + + Scope (\_SB.PCI0) + { + Name (BUSN, Package (0x20) /* HC_NUMS */ + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x10101010, + 0x11111111, + 0x12121212, + 0x13131313, + 0x14141414, + 0x15151515, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc + }) + Name (MMIO, Package (0x80) /* HC_NUMS * 4 */ + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 + }) + Name (PCIO, Package (0x40) /* HC_NUMS * 2 */ + { + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x77777777, + 0x88888888, + 0x99999999, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444 + }) + Name (SBLK, 0x11) + Name (TOM1, 0xaaaaaaaa) + Name (SBDN, 0xbbbbbbbb) + Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */ + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 + }) + Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */ + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 + }) + Name (CBB, 0x99) + Name (CBST, 0x88) + Name (CBB2, 0x77) + Name (CBS2, 0x66) + + } +} + From gerrit at coreboot.org Thu Jul 14 02:50:16 2011 From: gerrit at coreboot.org (Frank Vibrans III (efdesign98@gmail.com)) Date: Thu, 14 Jul 2011 02:50:16 +0200 Subject: [coreboot] Patch set updated: 9f1b389 Add AMD Family 10 cpu support to northbridge folder References: Message-ID: Frank Vibrans III (efdesign98 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/98 -gerrit commit 9f1b3897c349e2ab3d7a4f4d027b78f1c7131856 Author: efdesign98 Date: Wed Jul 13 17:49:25 2011 -0700 Add AMD Family 10 cpu support to northbridge folder This change adds the AMD Family 10 cpu support to the northbridge folder. The northbridge/amd/agesa Kconfig and Makefile.inc are changed as well. Change-Id: Id76e9fa388c79ac469a673aaedaa4f1bfd7619d9 Signed-off-by: Frank Vibrans Signed-off-by: efdesign98 --- src/northbridge/amd/Makefile.inc | 1 + src/northbridge/amd/agesa/Kconfig | 1 + src/northbridge/amd/agesa/Makefile.inc | 1 + src/northbridge/amd/agesa/family10/Kconfig | 49 + src/northbridge/amd/agesa/family10/Makefile.inc | 22 + src/northbridge/amd/agesa/family10/amdfam10.h | 101 ++ src/northbridge/amd/agesa/family10/bootblock.c | 29 + src/northbridge/amd/agesa/family10/chip.h | 24 + src/northbridge/amd/agesa/family10/northbridge.c | 1518 ++++++++++++++++++++ src/northbridge/amd/agesa/family10/northbridge.h | 26 + src/northbridge/amd/agesa/family10/reset_test.h | 52 + .../amd/agesa/family10/root_complex/Kconfig | 2 + .../amd/agesa/family10/root_complex/chip.h | 24 + src/northbridge/amd/agesa/family10/ssdt.asl | 346 +++++ src/northbridge/amd/amdfam10/reset_test.c | 3 +- 15 files changed, 2198 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index dfbed75..5299780 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -5,5 +5,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += ../../vendorcode/amd/agesa/f10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += ../../vendorcode/amd/agesa/f12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../vendorcode/amd/agesa/f14 diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index d5fde57..463da5d 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,6 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 96798fc..1da8f60 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -16,5 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig new file mode 100755 index 0000000..62a6cd4 --- /dev/null +++ b/src/northbridge/amd/agesa/family10/Kconfig @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +config NORTHBRIDGE_AMD_AGESA_FAMILY10 + bool + select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_SMBUS + select HYPERTRANSPORT_PLUGIN_SUPPORT + select MMCONF_SUPPORT + select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX + +if NORTHBRIDGE_AMD_AGESA_FAMILY10 +config HT3_SUPPORT + bool + default y +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n +config MMCONF_BASE_ADDRESS + hex + default 0xE0000000 +config MMCONF_BUS_NUMBER + int + default 256 +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/amd/agesa/family10/bootblock.c" +endif #NORTHBRIDGE_AMD_AGESA_FAMILY10 + +source "src/northbridge/amd/agesa/family10/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family10/Makefile.inc b/src/northbridge/amd/agesa/family10/Makefile.inc new file mode 100755 index 0000000..8f0fe0d --- /dev/null +++ b/src/northbridge/amd/agesa/family10/Makefile.inc @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c + +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h new file mode 100755 index 0000000..e6f9d81 --- /dev/null +++ b/src/northbridge/amd/agesa/family10/amdfam10.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMDFAM10_H +#define AMDFAM10_H + +#include + +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define BU_CFG_MSR 0xC0011023 +#define BU_CFG2_MSR 0xC001102A + +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 + +/* Definitions of various FAM10 registers */ +/* Function 0 */ +#define HT_TRANSACTION_CONTROL 0x68 +#define HTTC_DIS_RD_B_P (1 << 0) +#define HTTC_DIS_RD_DW_P (1 << 1) +#define HTTC_DIS_WR_B_P (1 << 2) +#define HTTC_DIS_WR_DW_P (1 << 3) +#define HTTC_DIS_MTS (1 << 4) +#define HTTC_CPU1_EN (1 << 5) +#define HTTC_CPU_REQ_PASS_PW (1 << 6) +#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) +#define HTTC_DIS_P_MEM_C (1 << 8) +#define HTTC_DIS_RMT_MEM_C (1 << 9) +#define HTTC_DIS_FILL_P (1 << 10) +#define HTTC_RSP_PASS_PW (1 << 11) +#define HTTC_BUF_REL_PRI_SHIFT 13 +#define HTTC_BUF_REL_PRI_MASK 3 +#define HTTC_BUF_REL_PRI_64 0 +#define HTTC_BUF_REL_PRI_16 1 +#define HTTC_BUF_REL_PRI_8 2 +#define HTTC_BUF_REL_PRI_2 3 +#define HTTC_LIMIT_CLDT_CFG (1 << 15) +#define HTTC_LINT_EN (1 << 16) +#define HTTC_APIC_EXT_BRD_CST (1 << 17) +#define HTTC_APIC_EXT_ID (1 << 18) +#define HTTC_APIC_EXT_SPUR (1 << 19) +#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) +#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 +#define HTTC_DS_NP_REQ_LIMIT_MASK 3 +#define HTTC_DS_NP_REQ_LIMIT_NONE 0 +#define HTTC_DS_NP_REQ_LIMIT_1 1 +#define HTTC_DS_NP_REQ_LIMIT_4 2 +#define HTTC_DS_NP_REQ_LIMIT_8 3 + +/* Function 1 */ + +/* Function 2 */ + +/* Function 3 */ + + +/* Function 5 for FBDIMM */ +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) +#define NonCoherent (1 << 2) +#define ConnectionPending (1 << 4) + +#if CONFIG_MAX_PHYSICAL_CPUS > 8 + #if CONFIG_MAX_PHYSICAL_CPUS > 32 + #define NODE_NUMS 64 + #else + #define NODE_NUMS 32 + #endif +#else + #define NODE_NUMS 8 +#endif + +#ifdef __PRE_RAM__ +#if NODE_NUMS==64 + #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else + #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif +#endif + +#endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c new file mode 100755 index 0000000..f6ae8be --- /dev/null +++ b/src/northbridge/amd/agesa/family10/bootblock.c @@ -0,0 +1,29 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include +#include +#include + +static void bootblock_northbridge_init(void) { +} diff --git a/src/northbridge/amd/agesa/family10/chip.h b/src/northbridge/amd/agesa/family10/chip.h new file mode 100755 index 0000000..c0ac56e --- /dev/null +++ b/src/northbridge/amd/agesa/family10/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family10_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family10_ops; diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c new file mode 100755 index 0000000..b3e4c63 --- /dev/null +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -0,0 +1,1518 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG_LOGICAL_CPUS==1 +#include +#endif + +#include +#include +#include +#include +#include "root_complex/chip.h" +#include "northbridge.h" +#include "amdfam10.h" +#include "chip.h" + +extern uint32_t agesawrapper_amdinitmid(void); + +typedef struct amdfam10_sysconf_t sys_info_conf_t; +typedef struct dram_base_mask { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +} dram_base_mask_t; + + +struct amdfam10_sysconf_t sysconf; +static device_t __f0_dev[NODE_NUMS]; +static device_t __f1_dev[NODE_NUMS]; +static device_t __f2_dev[NODE_NUMS]; +static device_t __f4_dev[NODE_NUMS]; +static unsigned fx_devs = 0; + +#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! +#endif + +static dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + device_t dev; + dram_base_mask_t d; + dev = __f1_dev[0]; + +#if CONFIG_EXT_CONF_SUPPORT == 1 + /* I will use ext space only for simple */ + pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8] + d.mask = pci_read_config32(dev, 0x114); // enable is bit 0 + pci_write_config32(dev, 0x110, nodeid | (0<<28)); + d.base = pci_read_config32(dev, 0x114) & 0x1fffff00; //[47:27] at [28:8]; +#else + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp<<21; + + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + + d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.base |= temp<<21; +#endif + return d; +} + +#if CONFIG_EXT_CONF_SUPPORT +static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, + u32 busn_min, u32 busn_max, + u32 type) +{ + device_t dev; + u32 i; + u32 tempreg; + u32 index_min, index_max; + u32 dest_min, dest_max; + index_min = busn_min>>2; dest_min = busn_min - (index_min<<2); + index_max = busn_max>>2; dest_max = busn_max - (index_max<<2); + + // three case: index_min==index_max, index_min+1=index_max; index_min+11) { + tempreg = 0; + for (i=0; i<=3; i++) { + tempreg &= ~(0xff<<(i*8)); + tempreg |= (cfg_map_dest<<(i*8)); + } + for (i=index_min+1; i(0xe0-1)) {// use next segn + u32 segn = (segbusn >> 8) & 0x0f; + segn++; + segbusn = segn<<8; + } + if (segbusn>>8) { + u32 val; + val = pci_read_config32(dev, 0x160); + val &= ~(0xf<<25); + val |= (segbusn & 0xf00)<<(25-8); + pci_write_config32(dev, 0x160, val); + } + + return segbusn; +} +#endif + +static u32 get_io_addr_index(u32 nodeid, u32 linkn) +{ + u32 index; + + for (index=0; index<256; index++) { + if ((sysconf.conf_io_addrx[index+4] == 0)) { + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); + return index; + } + } + + return 0; + +} + +static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) +{ + u32 index; + + for (index=0; index<64; index++) { + if ((sysconf.conf_mmio_addrx[index+8] == 0)) { + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); + return index; + } + } + + return 0; +} + +static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 io_min, u32 io_max) +{ + u32 val; +#if CONFIG_EXT_CONF_SUPPORT + if (reg!=0x110) { +#endif + /* io range allocation */ + index = (reg-0xc0)>>3; +#if CONFIG_EXT_CONF_SUPPORT + } else { + index+=4; + } +#endif + + val = (nodeid & 0x3f); // 6 bits used + sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid + val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit + + if (sysconf.io_addr_num<(index+1)) + sysconf.io_addr_num = index+1; +} + +static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 mmio_min, u32 mmio_max) +{ + u32 val; +#if CONFIG_EXT_CONF_SUPPORT + if (reg!=0x110) { +#endif + /* io range allocation */ + index = (reg-0x80)>>3; +#if CONFIG_EXT_CONF_SUPPORT + } else { + index += 8; + } +#endif + + val = (nodeid & 0x3f) ; // 6 bits used + sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn + val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit + + if (sysconf.mmio_addr_num<(index+1)) + sysconf.mmio_addr_num = index+1; +} + +static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + + u32 i; + u32 tempreg; +#if CONFIG_EXT_CONF_SUPPORT + if (reg!=0x110) { +#endif + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; ilink[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + for (i=0; i 3, We should use extend space + if (io_min>io_max) return; + // for nodeid at first + cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0); + + set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4); + + // all other nodes + cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0); + for (j = 0; j< sysconf.nodes; j++) { + if (j== nodeid) continue; + set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4); + } +#endif +} + +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + + u32 i; + u32 tempreg; +#if CONFIG_EXT_CONF_SUPPORT + if (reg!=0x110) { +#endif + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + for (i=0; i 3, We should use extend space + // for nodeid at first + u32 enable; + + if (mmio_min>mmio_max) { + return; + } + + enable = 1; + dev = __f1_dev[nodeid]; + tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0); + pci_write_config32(dev, 0x110, index | (2<<28)); + pci_write_config32(dev, 0x114, tempreg); + + tempreg = ((mmio_max>>3) & 0x1fffff00) | enable; + pci_write_config32(dev, 0x110, index | (3<<28)); + pci_write_config32(dev, 0x114, tempreg); + + // all other nodes + tempreg = ((mmio_min>>3) & 0x1fffff00) | (0<<6) | (nodeid<<0); + for (j = 0; j< sysconf.nodes; j++) { + if (j== nodeid) continue; + dev = __f1_dev[j]; + pci_write_config32(dev, 0x110, index | (2<<28)); + pci_write_config32(dev, 0x114, tempreg); + } + + tempreg = ((mmio_max>>3) & 0x1fffff00) | enable; + for (j = 0; j< sysconf.nodes; j++) { + if(j==nodeid) continue; + dev = __f1_dev[j]; + pci_write_config32(dev, 0x110, index | (3<<28)); + pci_write_config32(dev, 0x114, tempreg); + } +#endif +} + +static device_t get_node_pci(u32 nodeid, u32 fn) +{ +#if NODE_NUMS == 64 + if (nodeid < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } + +#else + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); +#endif +} + +static unsigned int read_nb_cfg_54(void) +{ + msr_t msr; + msr = rdmsr(NB_CFG_MSR); + return (( msr.hi >> (54-32)) & 1); +} + +static void get_fx_devs(void) +{ + int i; + for (i = 0; i < NODE_NUMS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); + } +} + +static u32 f1_read_config32(unsigned reg) +{ + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned reg, u32 value) +{ + int i; + if (fx_devs == 0) + get_fx_devs(); + for(i = 0; i < fx_devs; i++) { + device_t dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static u32 amdfam10_nodeid(device_t dev) +{ +#if NODE_NUMS == 64 + unsigned busn; + busn = dev->bus->secondary; + if (busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; + } else { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + } + +#else + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; +#endif +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid<<4) | (linkn<<12); + /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, + 0x3c0:0x3df */ + f1_write_config32(0xf4, val); + +} + +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link = 0; + int result; + res = 0; + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for (link = 0; !res && (link < 8); link++) { + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + } + result = 2; + if (res) { + result = 0; + if ( (goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + return result; +} + +static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xd8) { + reg = free_reg; // if no free, the free_reg still be 0 + } + + //Ext conf space + if(!reg) { + //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range + u32 index = get_io_addr_index(nodeid, link); + reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + + return resource; +} + +static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } + + //Ext conf space + if (!reg) { + //because of Extend conf space, we will never run out of reg, + // but we need one index to differ them. so same node and + // same link can have multi range + u32 index = get_mmio_addr_index(nodeid, link); + reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 + + } + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + return resource; +} + +static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdfam10_find_iopair(dev, nodeid, link); + if (resource) { + u32 align; +#if CONFIG_EXT_CONF_SUPPORT == 1 + if((resource->index & 0x1fff) == 0x1110) { // ext + align = 8; + } + else +#endif + align = log2(HT_IO_HOST_ALIGN); + resource->base = 0; + resource->size = 0; + resource->align = align; + resource->gran = align; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam10_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + +#if CONFIG_EXT_CONF_SUPPORT == 1 + if ((resource->index & 0x1fff) == 0x1110) { // ext + normalize_resource(resource); + } +#endif + + } + + /* Initialize the memory constraints on the current bus */ + resource = amdfam10_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; +#if CONFIG_EXT_CONF_SUPPORT == 1 + if ((resource->index & 0x1fff) == 0x1110) { // ext + normalize_resource(resource); + } +#endif + } +} + +static void amdfam10_read_resources(device_t dev) +{ + u32 nodeid; + struct bus *link; + nodeid = amdfam10_nodeid(dev); + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam10_link_read_bases(dev, nodeid, link->link_num); + } + } +} + +static void amdfam10_set_resource(device_t dev, struct resource *resource, + u32 nodeid) +{ + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) { + return; + } + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); + + if (resource->flags & IORESOURCE_IO) { + + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] + store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); + } + resource->flags |= IORESOURCE_STORED; + sprintf(buf, " ", + nodeid, link_num); + report_resource_stored(dev, resource, buf); +} + +/** + * I tried to reuse the resource allocation code in amdfam10_set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +{ + struct bus *link; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 + extern device_t vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); + set_vga_enable_reg(nodeid, link->link_num); +} + +static void amdfam10_set_resources(device_t dev) +{ + unsigned nodeid; + struct bus *bus; + struct resource *res; + + /* Find the nodeid */ + nodeid = amdfam10_nodeid(dev); + + amdfam10_create_vga_resource(dev, nodeid); + + /* Set each resource we have found */ + for (res = dev->resource_list; res; res = res->next) { + amdfam10_set_resource(dev, res, nodeid); + } + + for (bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) { + assign_resources(bus); + } + } +} + +static void mcf0_control_init(struct device *dev) +{ +} + +static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +{ + unsigned nodeid; + struct bus *link; + unsigned sblink = sysconf.sblk; + device_t io_hub = NULL; + u32 next_unitid = 0xff; + + nodeid = amdfam10_nodeid(dev); + if (nodeid == 0) { + for (link = dev->link_list; link; link = link->next) { + if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[3] */ + io_hub = link->children; + if (!io_hub || !io_hub->enabled) { + die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); + } + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + } + } + } + + return max; +} + +static struct device_operations northbridge_operations = { + .read_resources = amdfam10_read_resources, + .set_resources = amdfam10_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = mcf0_control_init, + .scan_bus = amdfam10_scan_chains, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver mcf0_driver __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1200, +}; + +struct chip_operations northbridge_amd_agesa_family10_ops = { + CHIP_NAME("AMD FAM10 Northbridge") + .enable_dev = 0, +}; + + +static void amdfam10_domain_read_resources(device_t dev) +{ + unsigned reg; + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg<0xc0) { // mmio + nodeid = (limit & 0xf) + (base&0x30); + } else { // io + nodeid = (limit & 0xf) + ((base>>4)&0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + +#if CONFIG_PCI_64BIT_PREF_MEM == 0 + pci_domain_read_resources(dev); +#else + struct bus *link; + struct resource *resource; + for (link=dev->link_list; link; link = link->next) { + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0|(link->link_num<<2)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + } +#endif +} + +static void amdfam10_domain_enable_resources(device_t dev) +{ + u32 val; + /* Must be called after PCI enumeration and resource allocation */ + printk(BIOS_DEBUG, "\nFam10 - domain_enable_resources: AmdInitMid.\n"); + val = agesawrapper_amdinitmid(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + } + printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); +} + + +static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) +{ + struct resource *min; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; +} + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; + +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + + for (i = 0; i < sysconf.nodes; i++) { + dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(i); + if (!(d.mask & 1)) continue; // no memory on this node + + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i=0; i 4 *1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + + limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif + +#if CONFIG_WRITE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + +#if CONFIG_GFXUMA == 1 +extern uint64_t uma_memory_base, uma_memory_size; + +static void add_uma_resource(struct device *dev, int index) +{ + struct resource *resource; + + printk(BIOS_DEBUG, "Adding UMA memory area\n"); + resource = new_resource(dev, index); + resource->base = (resource_t) uma_memory_base; + resource->size = (resource_t) uma_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} +#endif + +static void amdfam10_domain_set_resources(device_t dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + struct resource *io, *mem1, *mem2; + struct resource *res; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; +#endif + +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + + for (link = dev->link_list; link; link = link->next) { + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first + */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + } + + for (res = &dev->resource_list; res; res = res->next) + { + res->flags |= IORESOURCE_ASSIGNED; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = my_find_pci_tolm(link, pci_tolm); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +/* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } + +#endif + + idx = 0x10; + for (i = 0; i < sysconf.nodes; i++) { + dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T + d = get_dram_base_mask(i); + + if (!(d.mask & 1)) continue; + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + sizek = limitk - basek; + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accomodate pci memory space */ + if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; +#if CONFIG_WRITE_HIGH_TABLES==1 + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, + high_tables_base); + } +#endif + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + +#if CONFIG_GFXUMA == 1 + /* Deduct uma memory before reporting because + * this is what the mtrr code expects */ + sizek -= uma_memory_size / 1024; +#endif + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; +#if CONFIG_WRITE_HIGH_TABLES==1 + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif + } + +#if CONFIG_GFXUMA == 1 + add_uma_resource(dev, 7); +#endif + + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + +static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +{ + u32 reg; + int i; + struct bus *link; + /* Unmap all of the HT chains */ + for (reg = 0xe0; reg <= 0xec; reg += 4) { + f1_write_config32(reg, 0); + } +#if CONFIG_EXT_CONF_SUPPORT == 1 + // all nodes + for (i = 0; i< sysconf.nodes; i++) { + int index; + for(index = 0; index < 64; index++) { + pci_write_config32(__f1_dev[i], 0x110, index | (6<<28)); + pci_write_config32(__f1_dev[i], 0x114, 0); + } + + } +#endif + + + for (link = dev->link_list; link; link = link->next) { + max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); + } + + /* Tune the hypertransport transaction for best performance. + * Including enabling relaxed ordering if it is safe. + */ + get_fx_devs(); + for (i = 0; i < fx_devs; i++) { + device_t f0_dev; + f0_dev = __f0_dev[i]; + if (f0_dev && f0_dev->enabled) { + u32 httc; + httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); + httc &= ~HTTC_RSP_PASS_PW; + if (!dev->link_list->disable_relaxed_ordering) { + httc |= HTTC_RSP_PASS_PW; + } + printk(BIOS_SPEW, "%s passpw: %s\n", + dev_path(dev), + (!dev->link_list->disable_relaxed_ordering)? + "enabled":"disabled"); + pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); + } + } + return max; +} + + +static struct device_operations pci_domain_ops = { + .read_resources = amdfam10_domain_read_resources, + .set_resources = amdfam10_domain_set_resources, + .enable_resources = amdfam10_domain_enable_resources, + .init = NULL, + .scan_bus = amdfam10_domain_scan_bus, +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + + +static void sysconf_init(device_t dev) // first node +{ + sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 + sysconf.segbit = 0; + sysconf.ht_c_num = 0; + + unsigned ht_c_index; + + for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + sysconf.ht_c_conf_bus[ht_c_index] = 0; + } + + sysconf.nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] + + /* Find the bootstrap processors apicid */ + sysconf.bsp_apicid = lapicid(); +} + +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + +/* dummy read_resources */ +static void lapic_read_resources(device_t dev) +{ +} + +static struct device_operations lapic_ops = { + .read_resources = lapic_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, +}; + +static u32 cpu_bus_scan(device_t dev, u32 max) +{ + struct bus *cpu_bus; + device_t dev_mc; +#if CONFIG_CBB + device_t pci_domain; +#endif + int i,j; + int nodes; + unsigned nb_cfg_54; + unsigned siblings; + int cores_found; + int disable_siblings; + unsigned ApicIdCoreIdSize; + + nb_cfg_54 = 0; + ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf); + if (ApicIdCoreIdSize) { + siblings = (1<bus) { + printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); + + } else { + printk(BIOS_DEBUG, " but it is not under pci_domain directly "); + } + printk(BIOS_DEBUG, "\n"); + } + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + while (dev_mc) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + dev_mc = dev_mc->sibling; + } + } + } + } + } + +#endif + + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + die(""); + } + + sysconf_init(dev_mc); + + nodes = sysconf.nodes; + +#if CONFIG_CBB && (NODE_NUMS > 32) + if (nodes>32) { // need to put node 32 to node 63 to bus 0xfe + if (pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); + } + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; + } +#endif + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < nodes; i++) { + device_t cdb_dev, cpu; + struct device_path cpu_path; + unsigned busn, devn; + struct bus *pbus; + + busn = CONFIG_CBB; + devn = CONFIG_CDB+i; + pbus = dev_mc->bus; +#if CONFIG_CBB && (NODE_NUMS > 32) + if (i>=32) { + busn--; + devn-=32; + pbus = pci_domain->link_list->next); + } +#endif + + /* Find the cpu's pci device */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for(fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + } + if (cdb_dev) { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + int linknum; +#if CONFIG_HT3_SUPPORT==1 + linknum = 8; +#else + linknum = 4; +#endif + add_more_links(cdb_dev, linknum); + } + + cores_found = 0; // one core + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); + if (cdb_dev && cdb_dev->enabled) { + j = pci_read_config32(cdb_dev, 0xe8); + cores_found = (j >> 12) & 3; // dev is func 3 + if (siblings > 3) + cores_found |= (j >> 13) & 4; + printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cdb_dev), cores_found); + } + + u32 jj; + if (disable_siblings) { + jj = 0; + } else { + jj = cores_found; + } + + for (j = 0; j <=jj; j++ ) { + extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + u32 modules = TopologyConfiguration.PlatformNumberOfModules; + u32 lapicid_start = 0; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ + if (nodes * (cores_found + 1) >= 0x10) { + lapicid_start = 0x10; + } + cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); + + /* See if I can find the cpu */ + cpu = find_dev_path(cpu_bus, &cpu_path); + + /* Enable the cpu if I have the processor */ + if (cdb_dev && cdb_dev->enabled) { + if (!cpu) { + cpu = alloc_dev(cpu_bus, &cpu_path); + } + if (cpu) { + cpu->enabled = 1; + } + } + + /* Disable the cpu if I don't have the processor */ + if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + cpu->enabled = 0; + } + + /* Report what I have done */ + if (cpu) { + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + if (cpu->path.type == DEVICE_PATH_APIC) { + cpu->ops = &lapic_ops; + } + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } + + } //j + } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static void cpu_bus_read_resources(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif +} + +static void cpu_bus_set_resources(device_t dev) +{ + struct resource *resource = find_resource(dev, 0xc0010058); + if (resource) { + report_resource_stored(dev, resource, " "); + } + pci_dev_set_resources(dev); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + +static void root_complex_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_amd_agesa_family10_root_complex_ops = { + CHIP_NAME("AMD FAM10 Root Complex") + .enable_dev = root_complex_enable_dev, +}; + diff --git a/src/northbridge/amd/agesa/family10/northbridge.h b/src/northbridge/amd/agesa/family10/northbridge.h new file mode 100755 index 0000000..0530ee7 --- /dev/null +++ b/src/northbridge/amd/agesa/family10/northbridge.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_AMD_AGESA_FAM10H_H +#define NORTHBRIDGE_AMD_AGESA_FAM10H_H + +static struct device_operations pci_domain_ops; +static struct device_operations cpu_bus_ops; + +#endif /* NORTHBRIDGE_AMD_AGESA_FAM10H_H */ diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h new file mode 100755 index 0000000..5b24f2d --- /dev/null +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * copy from src/northbridge/amd/amdfam10/reset_test.c + */ + +#ifndef _RESET_TEST_H_ +#define _RESET_TEST_H_ + +#include "amdfam10.h" /* NODE_PCI */ + +#define NODE_ID 0x60 +#define HT_INIT_CONTROL 0x6c +#define HTIC_ColdR_Detect (1<<4) +#define HTIC_BIOSR_Detect (1<<5) +#define HTIC_INIT_Detect (1<<6) + +static inline u32 warm_reset_detect(u8 nodeid) +{ + u32 htic; + device_t device; + device = NODE_PCI(nodeid, 0); + htic = pci_io_read_config32(device, HT_INIT_CONTROL); + return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); +} + +static inline void distinguish_cpu_resets(u8 nodeid) +{ + u32 htic; + device_t device; + device = NODE_PCI(nodeid, 0); + htic = pci_io_read_config32(device, HT_INIT_CONTROL); + htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; + pci_io_write_config32(device, HT_INIT_CONTROL, htic); +} + +#endif diff --git a/src/northbridge/amd/agesa/family10/root_complex/Kconfig b/src/northbridge/amd/agesa/family10/root_complex/Kconfig new file mode 100755 index 0000000..345896b --- /dev/null +++ b/src/northbridge/amd/agesa/family10/root_complex/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX + bool diff --git a/src/northbridge/amd/agesa/family10/root_complex/chip.h b/src/northbridge/amd/agesa/family10/root_complex/chip.h new file mode 100755 index 0000000..15a2e1a --- /dev/null +++ b/src/northbridge/amd/agesa/family10/root_complex/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family10_root_complex_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family10_root_complex_ops; diff --git a/src/northbridge/amd/agesa/family10/ssdt.asl b/src/northbridge/amd/agesa/family10/ssdt.asl new file mode 100755 index 0000000..e637f1f --- /dev/null +++ b/src/northbridge/amd/agesa/family10/ssdt.asl @@ -0,0 +1,346 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file + */ + +DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM15H", "AMD-ACPI", 0x1000) +{ + /* + * These objects were referenced but not defined in this table + */ + External (\_SB_.PCI0, DeviceObj) + + Scope (\_SB.PCI0) + { + Name (BUSN, Package (0x20) /* HC_NUMS */ + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x10101010, + 0x11111111, + 0x12121212, + 0x13131313, + 0x14141414, + 0x15151515, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc + }) + Name (MMIO, Package (0x80) /* HC_NUMS * 4 */ + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 + }) + Name (PCIO, Package (0x40) /* HC_NUMS * 2 */ + { + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x77777777, + 0x88888888, + 0x99999999, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444 + }) + Name (SBLK, 0x11) + Name (TOM1, 0xaaaaaaaa) + Name (SBDN, 0xbbbbbbbb) + Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */ + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 + }) + Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */ + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 + }) + Name (CBB, 0x99) + Name (CBST, 0x88) + Name (CBB2, 0x77) + Name (CBS2, 0x66) + + } +} + diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 21e06d1..c48fca6 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -83,7 +83,8 @@ static u32 warm_reset_detect(u8 nodeid) return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } -static void set_bios_reset(void) +void __attribute__ ((weak)) set_bios_reset(void); +void __attribute__ ((weak)) set_bios_reset(void) { u32 nodes; From gerrit at coreboot.org Thu Jul 14 03:26:55 2011 From: gerrit at coreboot.org (Steven A. Falco (sfalco@coincident.com)) Date: Thu, 14 Jul 2011 03:26:55 +0200 Subject: [coreboot] New patch to review: a4a414c EHCI driver missing bus_address assignment. References: Message-ID: Steven A. Falco (sfalco at coincident.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/99 -gerrit commit a4a414c022e2ee737404415b066ae576e0a156d2 Author: Steven A. Falco Date: Wed Jul 13 21:01:26 2011 -0400 EHCI driver missing bus_address assignment. Other USB drivers set the bus_address field. EHCI should do this too. Signed-off-by: Steven A. Falco Change-Id: Ic4274c6744951ef7fa0cb135caf8b9f177d8bcaf --- payloads/libpayload/drivers/usb/ehci.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 3df0477..d979121 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -336,6 +336,7 @@ ehci_init (pcidev_t addr) controller->create_intr_queue = ehci_create_intr_queue; controller->destroy_intr_queue = ehci_destroy_intr_queue; controller->poll_intr_queue = ehci_poll_intr_queue; + controller->bus_address = addr; for (i = 0; i < 128; i++) { controller->devices[i] = 0; } From gerrit at coreboot.org Thu Jul 14 03:43:06 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 14 Jul 2011 03:43:06 +0200 Subject: [coreboot] Patch merged into master: a4a414c EHCI driver missing bus_address assignment. References: Message-ID: the following patch was just integrated into master: commit a4a414c022e2ee737404415b066ae576e0a156d2 Author: Steven A. Falco Date: Wed Jul 13 21:01:26 2011 -0400 EHCI driver missing bus_address assignment. Other USB drivers set the bus_address field. EHCI should do this too. Signed-off-by: Steven A. Falco Change-Id: Ic4274c6744951ef7fa0cb135caf8b9f177d8bcaf See http://review.coreboot.org/99 for details. -gerrit From gerrit at coreboot.org Thu Jul 14 04:03:24 2011 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Thu, 14 Jul 2011 04:03:24 +0200 Subject: [coreboot] Patch set updated: 8b86089 Move AMD SB800 early clock setup. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/96 -gerrit commit 8b860896689f7e5360d86a2861600d10240a83d6 Author: Scott Duplichan Date: Wed Jul 13 17:34:16 2011 -0600 Move AMD SB800 early clock setup. Move the AMD SB800 early clock setup code that is needed for early serial port operation from mainboard/romstage.c to sb800/bootblock.c. This prevents code duplication and simplifies porting. Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3 Signed-off-by: Scott Duplichan Signed-off-by: Marc Jones --- src/mainboard/amd/persimmon/romstage.c | 15 --------------- src/mainboard/asrock/e350m1/romstage.c | 15 --------------- src/southbridge/amd/cimx/sb800/bootblock.c | 21 +++++++++++++++++++++ 3 files changed, 21 insertions(+), 30 deletions(-) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 5ef5557..dfc2b6a 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -55,21 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); - if (boot_cpu()) - { - u8 reg8; - // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - outb(reg8, 0xCD7); - - // program SB800 MiscCntrl - *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ - } - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 29df530..38790cd 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,21 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr(0xc0010062, 0); - if (boot_cpu()) { - u8 reg8; - // SB800: Program AcpiMmioEn to enable MMIO access to MiscCntrl register - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - outb(0x24, 0xCD6); - outb(reg8, 0xCD7); - - // Program SB800 MiscCntrl - *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */ - } - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 170276a..593bd6b 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -84,10 +84,31 @@ static void enable_spi_fast_mode(void) pci_io_write_config32(dev, 0xa0, save); } +static void enable_clocks(void) +{ + u8 reg8; + u32 reg32; + volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40); + + // Program AcpiMmioEn to enable MMIO access to MiscCntrl register + outb(0x24, 0xCD6); + reg8 = inb(0xCD7); + reg8 |= 1; + reg8 &= ~(1 << 1); + outb(reg8, 0xCD7); + + // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz) + reg32 = *acpi_mmio; + reg32 &= ~((1 << 0) | (1 << 2)); + reg32 |= 1 << 1; + *acpi_mmio = reg32; +} + static void bootblock_southbridge_init(void) { /* Setup the rom access for 2M */ enable_rom(); enable_prefetch(); enable_spi_fast_mode(); + enable_clocks(); } From gerrit at coreboot.org Thu Jul 14 04:03:38 2011 From: gerrit at coreboot.org (Steven A. Falco (sfalco@coincident.com)) Date: Thu, 14 Jul 2011 04:03:38 +0200 Subject: [coreboot] New patch to review: 2052a69 Print a warning when an unknow USB controller type is detected. References: Message-ID: Steven A. Falco (sfalco at coincident.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/100 -gerrit commit 2052a695ec9a3a831d1314742ef736a426c397d1 Author: Steven A. Falco Date: Wed Jul 13 21:59:31 2011 -0400 Print a warning when an unknow USB controller type is detected. The Intel E6XX Atom processor reports an unknown USB controller type (in addition to the standard EHCI and OHCI ones). Add a default case to print a warning when an unknown controller type is detected. Change-Id: I885d0ccec4c46fd212cceac599290e9bf85edbbb Signed-off-by: Steven A. Falco --- payloads/libpayload/drivers/usb/usbinit.c | 45 ++++++++++++++++------------ 1 files changed, 26 insertions(+), 19 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index f0d5a60..d3cfbb7 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -70,40 +70,47 @@ usb_controller_initialize (int bus, int dev, int func) printf ("%02x:%02x.%x %04x:%04x.%d ", bus, dev, func, pciid >> 16, pciid & 0xFFFF, func); - if (prog_if == 0) { - printf ("UHCI controller\n"); + switch(prog_if) { + case 0x00: + printf ("UHCI controller\n"); #ifdef CONFIG_USB_UHCI - uhci_init (addr); + uhci_init (addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif - } - if (prog_if == 0x10) { - printf ("OHCI controller\n"); + break; + + case 0x10: + printf ("OHCI controller\n"); #ifdef CONFIG_USB_OHCI - ohci_init(addr); + ohci_init(addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif + break; - } - if (prog_if == 0x20) { - printf ("EHCI controller\n"); + case 0x20: + printf ("EHCI controller\n"); #ifdef CONFIG_USB_EHCI - ehci_init(addr); + ehci_init(addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif + break; - } - if (prog_if == 0x30) { - printf ("xHCI controller\n"); + case 0x30: + printf ("xHCI controller\n"); #ifdef CONFIG_USB_XHCI - xhci_init(addr); + xhci_init(addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif + break; + default: + printf ("unknown controller %x not supported\n", + prog_if); + break; } } From gerrit at coreboot.org Thu Jul 14 04:16:24 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 14 Jul 2011 04:16:24 +0200 Subject: [coreboot] Patch merged into master: 8b86089 Move AMD SB800 early clock setup. References: Message-ID: the following patch was just integrated into master: commit 8b860896689f7e5360d86a2861600d10240a83d6 Author: Scott Duplichan Date: Wed Jul 13 17:34:16 2011 -0600 Move AMD SB800 early clock setup. Move the AMD SB800 early clock setup code that is needed for early serial port operation from mainboard/romstage.c to sb800/bootblock.c. This prevents code duplication and simplifies porting. Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3 Signed-off-by: Scott Duplichan Signed-off-by: Marc Jones See http://review.coreboot.org/96 for details. -gerrit From gerrit at coreboot.org Thu Jul 14 08:00:31 2011 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 14 Jul 2011 08:00:31 +0200 Subject: [coreboot] Patch merged into master: 2052a69 Print a warning when an unknow USB controller type is detected. References: Message-ID: the following patch was just integrated into master: commit 2052a695ec9a3a831d1314742ef736a426c397d1 Author: Steven A. Falco Date: Wed Jul 13 21:59:31 2011 -0400 Print a warning when an unknow USB controller type is detected. The Intel E6XX Atom processor reports an unknown USB controller type (in addition to the standard EHCI and OHCI ones). Add a default case to print a warning when an unknown controller type is detected. Change-Id: I885d0ccec4c46fd212cceac599290e9bf85edbbb Signed-off-by: Steven A. Falco See http://review.coreboot.org/100 for details. -gerrit From me at andrewbolster.info Thu Jul 14 10:03:13 2011 From: me at andrewbolster.info (Andrew Bolster) Date: Thu, 14 Jul 2011 09:03:13 +0100 Subject: [coreboot] Coreboot on AMD Geode; No VGA In-Reply-To: <1310496937.2249.14.camel@Debian.lan> References: <1310496937.2249.14.camel@Debian.lan> Message-ID: Also, Nils, that patch description implies that VGA is working but on switching from X to console, gets messed up. That is not the problem that I'm having. I literally get nothing coming out of the VGA device. Regards Andrew Bolster No trees were killed to send this message, but a large number of electrons were terribly inconvenienced.I enjoy the massacre of ads. This sentence will slaughter ads without a messy bloodbath. On 12 July 2011 19:55, Nils wrote: > Andrew Bolster wrote: > > Can anyone point me in the direction of how to set up coreboot + > > seabios so that it actually uses the VGA? > > I am struggling with the same problem for some time now. > Extracting the original VGA as Peter suggests won't work because the LX > VSA we use is stripped down and doesn't have the graphics init routines > in it anymore. > > The most promising solution that should work (i didn't test it yet) i > could find is this: http://patchwork.coreboot.org/patch/190/ > It seems Chris is not working on it anymore and Kevin did not approve it > in it's current state for inclusion in Seabios. > > Thanks, Nils. > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrew.goodbody at tadpole.com Thu Jul 14 12:59:29 2011 From: andrew.goodbody at tadpole.com (Andrew Goodbody) Date: Thu, 14 Jul 2011 11:59:29 +0100 Subject: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock In-Reply-To: <4E1E0D4C.8020909@akeo.ie> References: <4E1B2C8B.5050001@akeo.ie> <4E1BE67C.6010805@tadpole.com> <4E1C8772.5010006@akeo.ie> <4E1D7B7F.3080807@tadpole.com> <4E1E0D4C.8020909@akeo.ie> Message-ID: <4E1ECC11.2020209@tadpole.com> On 07/13/11 22:25, Pete Batard wrote: > On 2011.07.13 12:03, Andrew Goodbody wrote: >>> I'll start with the aside, that if "failing" means instantly supporting >>> more than 90% of Intel based motherboards produced in the last 10 years >> >> Yes, universal means everything. If you do not support everything then >> it is not universal. The use of universal sets false expectations. > > In that case, "unlimited broadband" means truly unlimited, and fair > expectations are not supposed to be applied to the claim. But that is the point. Your support is not universal and unlimited broadband is not unlimited and should not be described as such. I object to the use of an absolute description to refer to something that is not absolute. > I guess if you would prefer an asterisk after the Universal in UBRX, > with a "Terms and Conditions apply", this can be arranged... ;) I would prefer it not be described as universal at all. > This being said, the 90% with regards to Intel chipsets applies to the > *PoC* (guesstimate obviously, but I think I'm probably pessimistic when > only those weird ITE init and non PnP Super I/Os are expected to fail > detection, which I doubt many of the ICH motherboard from the last 10 > years would have). The final version could be a lot closer to the 100% > mark, especially if we attempt detect both native UART and USB 3.0 > debug, as legacy free hardware, which I suppose is expected to have > PCI-E, would just need an xHCI PCI-E card we can detect to get going. I will not argue over made up statistics. >... Nor will I argue a strawman. > Finally, please remember that this is only a PoC, which is expected to > be incomplete or, gasp, have bugs (still working on it). Most of the > limitations or problems currently applying, can either be lifted or > worked around one way or another. However, there is only so much I can > test so yes, in its current instance, U(*)BRX does fall short of its > established goal of Universality(*). However, I'm not seeing a major > reason why it couldn't get there, hence the claim. And so increase complexity and reducing reliability. > At least I am hoping that it is OK to come to this list, with something > that is still incomplete, to see if there is interest, and not being > requested to come back with a solution that is feature complete and > spotless. !!! Of course you are welcome to come to this list with incomplete ideas. I was trying to work with you to improve it. I object to your claim of universal support, not your aim of supporting as much as possible. I do not want your description to set up false expectations. I see no request in that to go away until your support is complete and spotless. That comes only from your desire to make your idea live up to the description you chose. >> Yes we see different priorities for a panic room, but I think you >> misunderstood how much knowledge of the platform I was suggesting needed >> to be configured. > > OK, that's probably fair. > >> To me a panic room should >> be as simple and bullet proof as possible and if that means >> pre-configuring the build then so be it. > > The problem I have with pre-configured is you need to have prior > knowledge. So in effect, your panic room would be restricted to only > platforms that coreboot already supports, which, to mirror your > "unnecessary complication" below, I would see as an "unnecessary > limitation". Not at all. The pre-knowledge of the hardware required is just how to get to the UART. It is very, very far from requiring existing coreboot support. You do not need to know how to set up memory, you do not need to know how the interrupts are configured, you do not need to know what PCI/PCIe devices there are, etc. etc. which are all things needed for coreboot. So no you are not limited to platforms that coreboot already supports. >> Being 'hardware agnostic' helps >> in putting it on a new platform, assuming that platform conforms to the >> restrictions, but it does not help in actual operation of the panic >> room. So to me that would be an unnecessary complication. >> Your example of a panic room ondie with a UART is not hardware agnostic >> at all, you have pre-knowledge of the critical elements for establishing >> a console. > > Call me confrontational, but I am going to dispute the "not hardware > agnostic at all". > > If AMD and Intel agreed tomorrow to provide an UART ondie, accessed in > the same fashion, on all of their future x86 chips, should we consider > that this knowledge should be out of bounds? > Or how about FPUs? Older x86 CPUs did not have an FPU unit ondie. Should > we then consider that a program that just uses the FPU, since it has > been for about the past 20 years, and no external hardware, can not be > considered hardware agnostic and should have performed FPU detection? > > To me there is such thing as internal hardware, which is 100% fair game > to use as soon as it is introduced, as, in the worst case scenario, it > can easily be detected from the public CPU specs, and external hardware, > which, and this is the critical point, may include elements that have > not even been designed yet. So I would say that a panic room ondie with > an UART, if all CPUs from the same line have this feature, is hardware > agnostic. But then again, whether hardware agnosticism applies to a CPU > that is irrelevant to coreboot doesn't bring much to the discussion. You are confrontational and you are arguing points that I do not hold and this I think is due to a misunderstanding of 'hardware agnostic'. All I was saying is that use of internal hardware implies pre-knowledge of that hardware and that is included into the build. My suggestion of being able to configure the use of a different SIO or allowing easy insertion of motherboard specific GPIO settings is on the same level of pre-knowledge as is required to use internal hardware. I never suggested that any knowledge was out of bounds. I was suggesting being able to build knowledge into a specific build of the panic room in order to reduce complexity and so get closer to your aim of universal support. >> OK, well how about the SIO support from UBRX being one of the SIO >> modules that can be chosen. My main concern is allowing a simple method >> of getting panic room support to work on boards that do not meet your >> restrictions. > > That's one of my concerns too. > > As I indicated above, I am not planning to spend much time on getting > non PnP SIOs, or PnP SIOs that require some weird init to be supported > by UBRX. I did not ask for support for these to be implemented by you, merely a framework that would allow them to be supported without having to make in depth changes to the core support. > This being said, UBRX does support the VMWare virtual SIO, which is not > PnP, and I think your idea about trying to be modular in UBRX is a good > one. I can probably create a separate module for the VMWare non PnP SIO, > which could be used as a template for other SIOs that people want to see > supported, and that may not be detected in UBRX main. Such modules could > then be selected and included conditionally at buildtime. I think we may even both be able to agree that this is a good idea. > But I do see the need for blanket detection being the main focus, if we > can easily perform it and it avoids being limited to only what we know. Yes, but not at the cost of excessive complexity and reduced reliability. > With this, unconditional universality may actually apply to UBRX after > all (though some may claim that if everything isn't supported at the > same time, it's still not universal)... ;) > >>> Superiotool, not so much... Also picking a coreboot BIOS from one >>> machine and soldering it into another, with the expectation that even if >>> the motherboards have nothing in common but the flash they use, >>> panic-room access will be available, can have its advantages, be it only >>> for ghetto-style budget-constrained tinkerers. >> >> Shudders! Do we really want to encourage that? > > I most certainly see some merit in that for the following reasons: One > is the consideration that people who may have a lot of time on their end > may not be the ones with the highest means of income, and coreboot could > probably use people with a time on their hand to support new > motherboards. The second reason is that there are an awful lot of > proprietary systems out there with soldered (non SPI) flash chips (Dell, > Compaq, etc...), that could really benefit from coreboot. Past their > prime, these systems can be obtained fairly cheaply, from corporate > sales, etc., and therefore are a good target for coreboot development. > However, when the first step of coreboot development is to install a > BIOS socket as well as get an external flasher, this is likely to put > potential contributors off. On the other hand, while there is obviously > a risk that the U(*)BRX panic-room may not work, there's a good chance > that it will and thus provide developers with both the possibility to > explore their hardware and test a coreboot development payload. Well your plan requires two motherboards plus a development system. The first with an existing coreboot image with working panic room. The second using a compatible BIOS flash chip. You start by removing the BIOS chip, containing the coreboot image with panic room, from a working board, rendering it useless. Then you swap in that BIOS flash chip onto the second board and hope that the panic room still works and will give you a console accessible from your development system. What if it does not work? You have no way forward. However if you allow the soldering of a socket (the same soldering skill needed as swapping a chip) you can do the following. One motherboard can act as your development system and as your flashing tool by doing a hot flash for the other. You do not need an existing coreboot support for either and you are not left with a useless motherboard. The cost of two sockets should be a lot less than another motherboard and no external flasher is needed. > So I guess the question is: do we want a panic-room that only applies to > systems that coreboot already support? Or do we want it to also be used > as a tool for the adding of new systems. You guess wrong. The question is how much complexity do we want for little or no discernible gain? Of course using it for new systems would be a good thing and my suggestions in no way prevent that. Andrew From me at andrewbolster.info Thu Jul 14 15:33:18 2011 From: me at andrewbolster.info (Andrew Bolster) Date: Thu, 14 Jul 2011 14:33:18 +0100 Subject: [coreboot] MSI E350IA-E45 Board Developments Message-ID: I'm getting my hands on this board soon for another project and would like to try coreboot off of it. The Mainboard is a Model MS-7698; not currently in the CB list, although it appears that most of the other pieces are already there in one shape or form so it *should* just be a case of stitching it all together as a mainboard descriptor. After some google fu, I came across this [1] thread that indicated that Tom Sylla had been looking into porting coreboot to this board. This is kinda a two fold post; Tom, if you're out there, can you give an update to your progress if any, and do you want an understudy to help out? I'm not very experienced in this area but I'm stubborn, so would love to actually contribute something useful back to the community for a change! PS, Anyone else can answer too... :P [1] http://comments.gmane.org/gmane.linux.bios/65839 Regards Andrew Bolster No trees were killed to send this message, but a large number of electrons were terribly inconvenienced.I enjoy the massacre of ads. This sentence will slaughter ads without a messy bloodbath. -------------- next part -------------- An HTML attachment was scrubbed... URL: From njacobs8 at hetnet.nl Thu Jul 14 18:23:50 2011 From: njacobs8 at hetnet.nl (Nils) Date: Thu, 14 Jul 2011 18:23:50 +0200 Subject: [coreboot] Coreboot on AMD Geode; No VGA Message-ID: <1310660630.2101.9.camel@Debian.lan> Hi Andrew, As i understand it the description of the problem belongs to the previous V2 version of the VGA patch witch this V3 version (at the bottom off the tread) together with the mode hack patch (little patch to vgatables.c) addresses. Thanks, Nils. From gerrit at coreboot.org Thu Jul 14 01:45:18 2011 From: gerrit at coreboot.org (Frank Vibrans III (efdesign98@gmail.com)) Date: Thu, 14 Jul 2011 01:45:18 +0200 Subject: [coreboot] New patch to review: e1bf4df Add the AMD Family10 Agesa code References: Message-ID: Frank Vibrans III (efdesign98 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/95 -gerrit commit e1bf4df28b64e4758f3220afb37f14fcea97669d Author: efdesign98 Date: Wed Jul 13 16:43:39 2011 -0700 Add the AMD Family10 Agesa code This change officially adds the Agesa code for the AMD Family 10 cpus. This code supports the G34 and C32 sockets. Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c Signed-off-by: Frank Vibrans Signed-off-by: efdesign98 --- src/vendorcode/Makefile.inc | 1 + src/vendorcode/amd/agesa/f10/AGESA.h | 2901 ++++++++++++++++++++ src/vendorcode/amd/agesa/f10/AMD.h | 478 ++++ src/vendorcode/amd/agesa/f10/Dispatcher.h | 51 + src/vendorcode/amd/agesa/f10/Include/AdvancedApi.h | 155 ++ .../amd/agesa/f10/Include/CommonReturns.h | 130 + .../amd/agesa/f10/Include/DanubeInstall.h | 1530 +++++++++++ .../amd/agesa/f10/Include/DragonInstall.h | 1531 +++++++++++ src/vendorcode/amd/agesa/f10/Include/Filecode.h | 547 ++++ .../amd/agesa/f10/Include/GeneralServices.h | 200 ++ .../amd/agesa/f10/Include/GnbInterface.h | 87 + .../amd/agesa/f10/Include/GnbInterfaceStub.h | 202 ++ src/vendorcode/amd/agesa/f10/Include/Ids.h | 791 ++++++ src/vendorcode/amd/agesa/f10/Include/IdsHt.h | 123 + src/vendorcode/amd/agesa/f10/Include/LynxInstall.h | 1535 +++++++++++ .../amd/agesa/f10/Include/MaranelloInstall.h | 1541 +++++++++++ src/vendorcode/amd/agesa/f10/Include/NileInstall.h | 1527 ++++++++++ .../amd/agesa/f10/Include/OptionC6Install.h | 84 + .../f10/Include/OptionCpuCacheFlushOnHaltInstall.h | 101 + .../f10/Include/OptionCpuCoreLevelingInstall.h | 92 + .../agesa/f10/Include/OptionCpuFeaturesInstall.h | 67 + .../f10/Include/OptionDanubeMicrocodeInstall.h | 63 + src/vendorcode/amd/agesa/f10/Include/OptionDmi.h | 89 + .../amd/agesa/f10/Include/OptionDmiInstall.h | 140 + .../f10/Include/OptionDragonMicrocodeInstall.h | 73 + .../amd/agesa/f10/Include/OptionFamily10h.h | 91 + .../agesa/f10/Include/OptionFamily10hBlInstall.h | 354 +++ .../agesa/f10/Include/OptionFamily10hDaInstall.h | 354 +++ .../agesa/f10/Include/OptionFamily10hHyInstall.h | 353 +++ .../amd/agesa/f10/Include/OptionFamily10hInstall.h | 345 +++ .../agesa/f10/Include/OptionFamily10hRbInstall.h | 355 +++ .../amd/agesa/f10/Include/OptionHtAssistInstall.h | 91 + .../amd/agesa/f10/Include/OptionHtInstall.h | 310 +++ .../amd/agesa/f10/Include/OptionHwC1eInstall.h | 80 + .../amd/agesa/f10/Include/OptionIdsInstall.h | 320 +++ .../agesa/f10/Include/OptionLynxMicrocodeInstall.h | 51 + .../f10/Include/OptionMaranelloMicrocodeInstall.h | 57 + .../amd/agesa/f10/Include/OptionMemory.h | 269 ++ .../amd/agesa/f10/Include/OptionMemoryInstall.h | 2683 ++++++++++++++++++ .../amd/agesa/f10/Include/OptionMemoryRecovery.h | 62 + .../f10/Include/OptionMemoryRecoveryInstall.h | 132 + .../agesa/f10/Include/OptionMsgBasedC1eInstall.h | 82 + .../amd/agesa/f10/Include/OptionMultiSocket.h | 156 ++ .../agesa/f10/Include/OptionMultiSocketInstall.h | 89 + .../agesa/f10/Include/OptionNileMicrocodeInstall.h | 63 + .../f10/Include/OptionPreserveMailboxInstall.h | 87 + .../amd/agesa/f10/Include/OptionPstate.h | 103 + .../amd/agesa/f10/Include/OptionPstateInstall.h | 209 ++ .../amd/agesa/f10/Include/OptionS3ScriptInstall.h | 82 + .../f10/Include/OptionSanMarinoMicrocodeInstall.h | 60 + src/vendorcode/amd/agesa/f10/Include/OptionSlit.h | 96 + .../amd/agesa/f10/Include/OptionSlitInstall.h | 79 + src/vendorcode/amd/agesa/f10/Include/OptionSrat.h | 82 + .../amd/agesa/f10/Include/OptionSratInstall.h | 73 + .../f10/Include/OptionTigrisMicrocodeInstall.h | 65 + src/vendorcode/amd/agesa/f10/Include/OptionWhea.h | 83 + .../amd/agesa/f10/Include/OptionWheaInstall.h | 74 + src/vendorcode/amd/agesa/f10/Include/Options.h | 203 ++ src/vendorcode/amd/agesa/f10/Include/OptionsHt.h | 100 + src/vendorcode/amd/agesa/f10/Include/OptionsPage.h | 283 ++ .../f10/Include/PlatformMemoryConfiguration.h | 303 ++ .../amd/agesa/f10/Include/SanMarinoInstall.h | 1527 ++++++++++ .../amd/agesa/f10/Include/TigrisInstall.h | 1495 ++++++++++ src/vendorcode/amd/agesa/f10/Include/Topology.h | 160 ++ src/vendorcode/amd/agesa/f10/Include/gcc-intrin.h | 630 +++++ .../f10/Legacy/PlatformMemoryConfiguration.inc | 383 +++ .../amd/agesa/f10/Legacy/Proc/Dispatcher.c | 155 ++ .../amd/agesa/f10/Legacy/Proc/agesaCallouts.c | 371 +++ .../amd/agesa/f10/Legacy/Proc/arch2008.asm | 2670 ++++++++++++++++++ .../amd/agesa/f10/Legacy/Proc/hobTransfer.c | 243 ++ src/vendorcode/amd/agesa/f10/Legacy/agesa.inc | 2466 +++++++++++++++++ src/vendorcode/amd/agesa/f10/Legacy/amd.inc | 461 ++++ src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc | 577 ++++ src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm | 624 +++++ src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm | 110 + src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm | 84 + src/vendorcode/amd/agesa/f10/Lib/amdlib.c | 1336 +++++++++ src/vendorcode/amd/agesa/f10/Lib/amdlib.h | 387 +++ src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm | 569 ++++ src/vendorcode/amd/agesa/f10/MainPage.h | 119 + src/vendorcode/amd/agesa/f10/Makefile.inc | 52 + src/vendorcode/amd/agesa/f10/Porting.h | 277 ++ .../Proc/CPU/Family/0x10/F10MultiLinkPciTables.c | 1442 ++++++++++ .../f10/Proc/CPU/Family/0x10/F10PackageType.h | 83 + .../f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c | 287 ++ .../f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h | 76 + .../f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c | 186 ++ .../f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.h | 76 + .../Proc/CPU/Family/0x10/F10SingleLinkPciTables.c | 1267 +++++++++ .../Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c | 146 + .../Family/0x10/RevC/BL/F10BlEquivalenceTable.c | 102 + .../CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c | 117 + .../CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c | 102 + .../0x10/RevC/BL/F10BlMicrocodePatchTables.c | 104 + .../Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c | 101 + .../Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c | 174 ++ .../Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c | 136 + .../Family/0x10/RevC/DA/F10DaEquivalenceTable.c | 102 + .../CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c | 278 ++ .../CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c | 102 + .../0x10/RevC/DA/F10DaMicrocodePatchTables.c | 104 + .../Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c | 101 + .../Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c | 172 ++ .../Family/0x10/RevC/F10MicrocodePatch01000085.c | 1035 +++++++ .../Family/0x10/RevC/F10MicrocodePatch01000086.c | 1035 +++++++ .../Family/0x10/RevC/F10MicrocodePatch01000098.c | 1035 +++++++ .../Family/0x10/RevC/F10MicrocodePatch010000b6.c | 1035 +++++++ .../Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c | 436 +++ .../f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c | 178 ++ .../Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c | 130 + .../Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c | 261 ++ .../Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c | 401 +++ .../Family/0x10/RevC/RB/F10RbEquivalenceTable.c | 105 + .../CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c | 115 + .../CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c | 109 + .../0x10/RevC/RB/F10RbMicrocodePatchTables.c | 104 + .../Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c | 115 + .../Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c | 212 ++ .../Family/0x10/RevD/F10MicrocodePatch010000c4.c | 1037 +++++++ .../Family/0x10/RevD/F10MicrocodePatch010000c5.c | 1035 +++++++ .../f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm | 113 + .../f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm | 127 + .../Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c | 454 +++ .../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c | 277 ++ .../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c | 372 +++ .../Family/0x10/RevD/HY/F10HyEquivalenceTable.c | 110 + .../CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c | 1290 +++++++++ .../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c | 138 + .../CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c | 112 + .../0x10/RevD/HY/F10HyMicrocodePatchTables.c | 112 + .../Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c | 139 + .../Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c | 362 +++ .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c | 343 +++ .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.h | 98 + .../agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c | 155 ++ .../f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c | 315 +++ .../f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c | 131 + .../f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c | 131 + .../f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c | 176 ++ .../f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c | 124 + .../f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c | 125 + .../f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c | 138 + .../f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c | 124 + .../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c | 136 + .../amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c | 411 +++ .../f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c | 403 +++ .../f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.h | 78 + .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c | 389 +++ .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h | 194 ++ .../f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c | 747 +++++ .../f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c | 270 ++ .../f10/Proc/CPU/Family/0x10/cpuF10PciTables.c | 768 ++++++ .../f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c | 376 +++ .../f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.h | 81 + .../f10/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h | 516 ++++ .../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c | 164 ++ .../f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c | 469 ++++ .../f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.h | 76 + .../agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c | 154 ++ .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c | 120 + .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h | 78 + .../f10/Proc/CPU/Family/0x10/cpuF10Utilities.c | 1768 ++++++++++++ .../f10/Proc/CPU/Family/0x10/cpuF10Utilities.h | 223 ++ .../CPU/Family/0x10/cpuF10WheaInitDataTables.c | 124 + .../agesa/f10/Proc/CPU/Family/cpuFamRegisters.h | 180 ++ .../agesa/f10/Proc/CPU/Feature/PreserveMailbox.c | 210 ++ .../agesa/f10/Proc/CPU/Feature/PreserveMailbox.h | 87 + .../amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c | 200 ++ .../amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h | 198 ++ .../f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c | 185 ++ .../amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c | 541 ++++ .../amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h | 101 + .../agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c | 283 ++ .../amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c | 694 +++++ .../f10/Proc/CPU/Feature/cpuFeatureLeveling.c | 262 ++ .../amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.c | 149 + .../amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h | 255 ++ .../amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c | 344 +++ .../amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h | 278 ++ .../amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c | 166 ++ .../amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h | 125 + .../agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c | 236 ++ .../agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h | 127 + .../agesa/f10/Proc/CPU/Feature/cpuPstateGather.c | 382 +++ .../agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c | 1088 ++++++++ .../agesa/f10/Proc/CPU/Feature/cpuPstateTables.c | 821 ++++++ .../agesa/f10/Proc/CPU/Feature/cpuPstateTables.h | 120 + .../amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c | 370 +++ .../amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c | 614 +++++ .../amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c | 276 ++ src/vendorcode/amd/agesa/f10/Proc/CPU/S3.c | 1166 ++++++++ src/vendorcode/amd/agesa/f10/Proc/CPU/S3.h | 394 +++ src/vendorcode/amd/agesa/f10/Proc/CPU/Table.c | 1576 +++++++++++ src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h | 1174 ++++++++ src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm | 319 +++ src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c | 309 +++ .../amd/agesa/f10/Proc/CPU/cpuApicUtilities.c | 1474 ++++++++++ .../amd/agesa/f10/Proc/CPU/cpuApicUtilities.h | 260 ++ src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBist.c | 168 ++ src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBrandId.c | 311 +++ .../amd/agesa/f10/Proc/CPU/cpuEarlyInit.c | 363 +++ .../amd/agesa/f10/Proc/CPU/cpuEarlyInit.h | 228 ++ src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEnvInit.h | 73 + .../amd/agesa/f10/Proc/CPU/cpuEventLog.c | 379 +++ .../amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.c | 481 ++++ .../amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h | 1030 +++++++ .../amd/agesa/f10/Proc/CPU/cpuGeneralServices.c | 1050 +++++++ .../amd/agesa/f10/Proc/CPU/cpuInitEarlyTable.c | 120 + .../amd/agesa/f10/Proc/CPU/cpuLateInit.c | 281 ++ .../amd/agesa/f10/Proc/CPU/cpuLateInit.h | 797 ++++++ .../amd/agesa/f10/Proc/CPU/cpuMicrocodePatch.c | 441 +++ src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPage.h | 60 + .../amd/agesa/f10/Proc/CPU/cpuPostInit.c | 480 ++++ .../amd/agesa/f10/Proc/CPU/cpuPostInit.h | 234 ++ .../amd/agesa/f10/Proc/CPU/cpuPowerMgmt.c | 243 ++ .../agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.c | 394 +++ .../agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.h | 101 + .../agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c | 224 ++ .../agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.h | 101 + .../agesa/f10/Proc/CPU/cpuPowerMgmtSystemTables.h | 92 + .../amd/agesa/f10/Proc/CPU/cpuRegisters.h | 359 +++ .../amd/agesa/f10/Proc/CPU/cpuServices.h | 256 ++ .../amd/agesa/f10/Proc/CPU/cpuWarmReset.c | 188 ++ .../amd/agesa/f10/Proc/CPU/heapManager.c | 593 ++++ .../amd/agesa/f10/Proc/CPU/heapManager.h | 221 ++ .../amd/agesa/f10/Proc/Common/AmdInitEarly.c | 255 ++ .../amd/agesa/f10/Proc/Common/AmdInitEnv.c | 159 ++ .../amd/agesa/f10/Proc/Common/AmdInitLate.c | 269 ++ .../amd/agesa/f10/Proc/Common/AmdInitMid.c | 156 ++ .../amd/agesa/f10/Proc/Common/AmdInitPost.c | 295 ++ .../amd/agesa/f10/Proc/Common/AmdInitRecovery.c | 165 ++ .../amd/agesa/f10/Proc/Common/AmdInitReset.c | 207 ++ .../amd/agesa/f10/Proc/Common/AmdInitResume.c | 223 ++ .../amd/agesa/f10/Proc/Common/AmdLateRunApTask.c | 156 ++ .../amd/agesa/f10/Proc/Common/AmdS3LateRestore.c | 207 ++ .../amd/agesa/f10/Proc/Common/AmdS3Save.c | 370 +++ .../amd/agesa/f10/Proc/Common/CommonInits.c | 114 + .../amd/agesa/f10/Proc/Common/CommonInits.h | 65 + .../amd/agesa/f10/Proc/Common/CommonPage.h | 116 + .../amd/agesa/f10/Proc/Common/CommonReturns.c | 159 ++ .../amd/agesa/f10/Proc/Common/CreateStruct.c | 291 ++ .../amd/agesa/f10/Proc/Common/CreateStruct.h | 195 ++ .../amd/agesa/f10/Proc/Common/S3RestoreState.c | 304 ++ .../amd/agesa/f10/Proc/Common/S3SaveState.c | 453 +++ .../amd/agesa/f10/Proc/Common/S3SaveState.h | 287 ++ .../agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c | 159 ++ .../agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.h | 66 + .../amd/agesa/f10/Proc/HT/Fam10/htNbFam10.c | 295 ++ .../agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c | 117 + .../agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.h | 57 + .../f10/Proc/HT/Fam10/htNbOptimizationFam10.c | 214 ++ .../f10/Proc/HT/Fam10/htNbOptimizationFam10.h | 71 + .../amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c | 398 +++ .../amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.h | 90 + .../agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c | 441 +++ .../agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.h | 128 + .../f10/Proc/HT/Features/htFeatDynamicDiscovery.c | 779 ++++++ .../f10/Proc/HT/Features/htFeatDynamicDiscovery.h | 79 + .../amd/agesa/f10/Proc/HT/Features/htFeatGanging.c | 215 ++ .../amd/agesa/f10/Proc/HT/Features/htFeatGanging.h | 80 + .../agesa/f10/Proc/HT/Features/htFeatNoncoherent.c | 313 +++ .../agesa/f10/Proc/HT/Features/htFeatNoncoherent.h | 80 + .../f10/Proc/HT/Features/htFeatOptimization.c | 886 ++++++ .../f10/Proc/HT/Features/htFeatOptimization.h | 139 + .../amd/agesa/f10/Proc/HT/Features/htFeatRouting.c | 467 ++++ .../amd/agesa/f10/Proc/HT/Features/htFeatRouting.h | 89 + .../amd/agesa/f10/Proc/HT/Features/htFeatSets.c | 110 + .../agesa/f10/Proc/HT/Features/htFeatSublinks.c | 228 ++ .../agesa/f10/Proc/HT/Features/htFeatSublinks.h | 79 + .../Proc/HT/Features/htFeatTrafficDistribution.c | 265 ++ .../Proc/HT/Features/htFeatTrafficDistribution.h | 78 + .../amd/agesa/f10/Proc/HT/Features/htIds.c | 148 + .../amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c | 488 ++++ .../amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h | 177 ++ .../agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c | 138 + .../agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.h | 61 + .../agesa/f10/Proc/HT/NbCommon/htNbOptimization.c | 252 ++ .../agesa/f10/Proc/HT/NbCommon/htNbOptimization.h | 89 + .../amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c | 331 +++ .../amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.h | 107 + src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c | 108 + src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.h | 559 ++++ src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h | 143 + .../amd/agesa/f10/Proc/HT/htGraph/htGraph.c | 195 ++ .../amd/agesa/f10/Proc/HT/htGraph/htGraph1.c | 66 + .../amd/agesa/f10/Proc/HT/htGraph/htGraph2.c | 67 + .../amd/agesa/f10/Proc/HT/htGraph/htGraph3Line.c | 72 + .../agesa/f10/Proc/HT/htGraph/htGraph3Triangle.c | 73 + .../agesa/f10/Proc/HT/htGraph/htGraph4Degenerate.c | 77 + .../f10/Proc/HT/htGraph/htGraph4FullyConnected.c | 79 + .../amd/agesa/f10/Proc/HT/htGraph/htGraph4Kite.c | 78 + .../amd/agesa/f10/Proc/HT/htGraph/htGraph4Line.c | 76 + .../amd/agesa/f10/Proc/HT/htGraph/htGraph4Square.c | 77 + .../amd/agesa/f10/Proc/HT/htGraph/htGraph4Star.c | 76 + .../f10/Proc/HT/htGraph/htGraph5FullyConnected.c | 76 + .../f10/Proc/HT/htGraph/htGraph5TwistedLadder.c | 85 + .../f10/Proc/HT/htGraph/htGraph6DoubloonLower.c | 71 + .../f10/Proc/HT/htGraph/htGraph6DoubloonUpper.c | 71 + .../f10/Proc/HT/htGraph/htGraph6FullyConnected.c | 82 + .../f10/Proc/HT/htGraph/htGraph6TwinTriangles.c | 88 + .../f10/Proc/HT/htGraph/htGraph6TwistedLadder.c | 88 + .../f10/Proc/HT/htGraph/htGraph7FullyConnected.c | 74 + .../f10/Proc/HT/htGraph/htGraph7TwistedLadder.c | 91 + .../agesa/f10/Proc/HT/htGraph/htGraph8DoubloonM.c | 73 + .../f10/Proc/HT/htGraph/htGraph8FullyConnected.c | 76 + .../amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c | 92 + .../Proc/HT/htGraph/htGraph8TwinFullyFourWays.c | 92 + .../f10/Proc/HT/htGraph/htGraph8TwistedLadder.c | 92 + src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c | 238 ++ src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.h | 487 ++++ .../amd/agesa/f10/Proc/HT/htInterfaceCoherent.c | 260 ++ .../amd/agesa/f10/Proc/HT/htInterfaceCoherent.h | 114 + .../amd/agesa/f10/Proc/HT/htInterfaceGeneral.c | 529 ++++ .../amd/agesa/f10/Proc/HT/htInterfaceGeneral.h | 160 ++ .../amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c | 390 +++ .../amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.h | 137 + src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c | 536 ++++ src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c | 240 ++ src/vendorcode/amd/agesa/f10/Proc/HT/htNb.h | 1065 +++++++ .../amd/agesa/f10/Proc/HT/htNbHardwareFam10.h | 117 + src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c | 659 +++++ src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h | 297 ++ src/vendorcode/amd/agesa/f10/Proc/HT/htPage.h | 64 + .../amd/agesa/f10/Proc/HT/htTopologies.h | 71 + .../amd/agesa/f10/Proc/IDS/Control/IdsCtrl.c | 771 ++++++ .../amd/agesa/f10/Proc/IDS/Control/IdsLib.c | 397 +++ .../amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm | 138 + .../amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm | 143 + .../amd/agesa/f10/Proc/IDS/Debug/IdsDebug.c | 1323 +++++++++ .../f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.c | 52 + .../f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.h | 45 + .../f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.c | 53 + .../f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.h | 45 + .../f10/Proc/IDS/Family/0x10/HY/IdsF10HYService.c | 173 ++ .../f10/Proc/IDS/Family/0x10/HY/IdsF10HYService.h | 45 + .../f10/Proc/IDS/Family/0x10/IdsF10AllService.c | 132 + .../f10/Proc/IDS/Family/0x10/IdsF10AllService.h | 79 + .../f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.c | 52 + .../f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.h | 45 + src/vendorcode/amd/agesa/f10/Proc/IDS/IdsLib.h | 295 ++ src/vendorcode/amd/agesa/f10/Proc/IDS/IdsPage.h | 57 + src/vendorcode/amd/agesa/f10/Proc/IDS/OptionsIds.h | 63 + .../amd/agesa/f10/Proc/IDS/Perf/IdsPerf.c | 241 ++ .../amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c | 577 ++++ .../amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c | 352 +++ .../amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c | 202 ++ .../amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c | 256 ++ .../amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c | 255 ++ .../amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c | 269 ++ .../amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c | 424 +++ .../amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c | 255 ++ .../amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c | 561 ++++ .../amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c | 352 +++ .../amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c | 256 ++ .../amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c | 255 ++ src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c | 136 + .../amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c | 208 ++ .../amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h | 80 + .../amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c | 331 +++ .../amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h | 80 + .../amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c | 566 ++++ .../amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c | 315 +++ .../amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h | 80 + .../amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c | 173 ++ .../f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c | 194 ++ .../agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c | 523 ++++ .../agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.h | 108 + .../agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c | 148 + .../agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h | 80 + .../amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c | 167 ++ .../amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.h | 78 + .../amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c | 147 + .../amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c | 239 ++ .../amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h | 78 + .../f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c | 168 ++ .../f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h | 78 + .../amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c | 166 ++ .../amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h | 79 + .../f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 284 ++ .../f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c | 83 + .../amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c | 753 +++++ .../amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c | 319 +++ .../amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c | 342 +++ .../amd/agesa/f10/Proc/Mem/Main/DA/mmflowda.c | 347 +++ .../amd/agesa/f10/Proc/Mem/Main/DR/mmflowdr.c | 343 +++ .../amd/agesa/f10/Proc/Mem/Main/HY/mmflowhy.c | 347 +++ src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mdef.c | 90 + .../amd/agesa/f10/Proc/Mem/Main/merrhdl.c | 186 ++ src/vendorcode/amd/agesa/f10/Proc/Mem/Main/minit.c | 134 + src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mm.c | 238 ++ .../amd/agesa/f10/Proc/Mem/Main/mmConditionalPso.c | 693 +++++ src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmEcc.c | 123 + .../amd/agesa/f10/Proc/Mem/Main/mmExcludeDimm.c | 235 ++ .../amd/agesa/f10/Proc/Mem/Main/mmLvDdr3.c | 126 + .../amd/agesa/f10/Proc/Mem/Main/mmMemClr.c | 107 + .../amd/agesa/f10/Proc/Mem/Main/mmMemRestore.c | 581 ++++ .../amd/agesa/f10/Proc/Mem/Main/mmNodeInterleave.c | 137 + .../amd/agesa/f10/Proc/Mem/Main/mmOnlineSpare.c | 157 ++ .../agesa/f10/Proc/Mem/Main/mmParallelTraining.c | 272 ++ .../agesa/f10/Proc/Mem/Main/mmStandardTraining.c | 110 + .../amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c | 224 ++ .../amd/agesa/f10/Proc/Mem/Main/mmflow.c | 352 +++ src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm | 483 ++++ src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.c | 253 ++ src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c | 685 +++++ .../amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c | 209 ++ .../amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c | 722 +++++ .../amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.h | 83 + .../amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c | 454 +++ .../amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h | 195 ++ .../amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c | 405 +++ .../amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c | 131 + .../amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c | 133 + .../amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c | 150 + .../amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c | 235 ++ .../amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c | 217 ++ .../amd/agesa/f10/Proc/Mem/NB/C32/mnprotoc32.c | 62 + .../amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c | 571 ++++ .../amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c | 210 ++ .../amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c | 739 +++++ .../amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.h | 83 + src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c | 460 ++++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h | 193 ++ .../amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c | 459 ++++ .../amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c | 135 + .../amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c | 134 + .../amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c | 154 ++ .../amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c | 195 ++ .../amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c | 81 + .../amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c | 554 ++++ .../amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c | 211 ++ .../amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c | 707 +++++ .../amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.h | 83 + .../amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c | 509 ++++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c | 452 +++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.h | 188 ++ .../amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c | 137 + .../amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c | 134 + .../amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c | 141 + .../amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c | 194 ++ .../amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c | 164 ++ .../amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c | 530 ++++ .../amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c | 213 ++ .../amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c | 738 +++++ .../amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.h | 83 + .../amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c | 361 +++ .../amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c | 130 + src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c | 453 +++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h | 189 ++ .../amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c | 134 + .../amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c | 150 + .../amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c | 239 ++ .../amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c | 234 ++ .../amd/agesa/f10/Proc/Mem/NB/HY/mnprotohy.c | 62 + .../amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c | 573 ++++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c | 462 ++++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h | 109 + .../amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c | 738 +++++ .../amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.h | 83 + src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c | 538 ++++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c | 677 +++++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c | 2053 ++++++++++++++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c | 560 ++++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c | 258 ++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c | 1043 +++++++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c | 1086 ++++++++ src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c | 396 +++ .../amd/agesa/f10/Proc/Mem/NB/mntrain2.c | 127 + .../amd/agesa/f10/Proc/Mem/NB/mntrain3.c | 193 ++ .../amd/agesa/f10/Proc/Mem/Ps/C32/mprc32_3.c | 322 +++ .../amd/agesa/f10/Proc/Mem/Ps/C32/mpuc32_3.c | 200 ++ .../amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c | 156 ++ .../amd/agesa/f10/Proc/Mem/Ps/DA/mpsda3.c | 252 ++ .../amd/agesa/f10/Proc/Mem/Ps/DA/mpuda3.c | 229 ++ .../amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c | 161 ++ .../amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c | 200 ++ .../amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c | 187 ++ .../amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c | 161 ++ .../amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c | 156 ++ .../amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c | 325 +++ .../amd/agesa/f10/Proc/Mem/Ps/HY/mpshy3.c | 216 ++ .../amd/agesa/f10/Proc/Mem/Ps/HY/mpuhy3.c | 194 ++ .../amd/agesa/f10/Proc/Mem/Ps/NI/mpsNi3.c | 252 ++ .../amd/agesa/f10/Proc/Mem/Ps/NI/mpuNi3.c | 230 ++ src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/mp.c | 231 ++ .../amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c | 229 ++ .../amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.h | 124 + .../amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c | 159 ++ .../amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.h | 88 + .../amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.c | 1112 ++++++++ .../amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.h | 182 ++ .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c | 223 ++ .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h | 135 + .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c | 167 ++ .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h | 90 + .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c | 307 +++ .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h | 87 + .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c | 521 ++++ .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h | 86 + .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c | 1089 ++++++++ .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h | 166 ++ .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c | 161 ++ .../amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c | 603 ++++ src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mt.c | 214 ++ src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mthdi.c | 122 + .../amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c | 851 ++++++ .../amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.h | 117 + .../amd/agesa/f10/Proc/Mem/Tech/mttdimbt.c | 1298 +++++++++ .../amd/agesa/f10/Proc/Mem/Tech/mttecc.c | 223 ++ .../amd/agesa/f10/Proc/Mem/Tech/mtthrc.c | 377 +++ src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttml.c | 211 ++ .../amd/agesa/f10/Proc/Mem/Tech/mttoptsrc.c | 420 +++ .../amd/agesa/f10/Proc/Mem/Tech/mttsrc.c | 339 +++ src/vendorcode/amd/agesa/f10/Proc/Mem/ma.h | 241 ++ src/vendorcode/amd/agesa/f10/Proc/Mem/memPage.h | 57 + src/vendorcode/amd/agesa/f10/Proc/Mem/merrhdl.h | 103 + .../amd/agesa/f10/Proc/Mem/mfParallelTraining.h | 113 + .../amd/agesa/f10/Proc/Mem/mfStandardTraining.h | 81 + src/vendorcode/amd/agesa/f10/Proc/Mem/mfmemclr.h | 83 + src/vendorcode/amd/agesa/f10/Proc/Mem/mfs3.h | 239 ++ src/vendorcode/amd/agesa/f10/Proc/Mem/mftds.h | 80 + src/vendorcode/amd/agesa/f10/Proc/Mem/mm.h | 842 ++++++ src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h | 1059 +++++++ src/vendorcode/amd/agesa/f10/Proc/Mem/mp.h | 241 ++ src/vendorcode/amd/agesa/f10/Proc/Mem/mport.h | 70 + src/vendorcode/amd/agesa/f10/Proc/Mem/mt.h | 364 +++ src/vendorcode/amd/agesa/f10/Proc/Mem/mu.h | 225 ++ .../amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c | 96 + .../amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.h | 75 + .../agesa/f10/Proc/Recovery/HT/htInitRecovery.c | 159 ++ .../amd/agesa/f10/Proc/Recovery/HT/htInitReset.c | 295 ++ .../agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.c | 700 +++++ .../agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.h | 103 + .../agesa/f10/Proc/Recovery/Mem/NB/C32/mrnmctc32.c | 126 + .../f10/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c | 57 + .../amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.c | 640 +++++ .../amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.h | 104 + .../agesa/f10/Proc/Recovery/Mem/NB/DA/mrnmctda.c | 129 + .../amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.c | 644 +++++ .../amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.h | 103 + .../agesa/f10/Proc/Recovery/Mem/NB/DR/mrnmctdr.c | 130 + .../agesa/f10/Proc/Recovery/Mem/NB/HY/mrndcthy.c | 152 + .../amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.c | 700 +++++ .../amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.h | 111 + .../agesa/f10/Proc/Recovery/Mem/NB/HY/mrnmcthy.c | 126 + .../agesa/f10/Proc/Recovery/Mem/NB/HY/mrnprotohy.c | 57 + .../amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.c | 641 +++++ .../amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.h | 95 + .../amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c | 188 ++ .../amd/agesa/f10/Proc/Recovery/Mem/NB/mrndct.c | 621 +++++ .../amd/agesa/f10/Proc/Recovery/Mem/NB/mrnmct.c | 295 ++ .../amd/agesa/f10/Proc/Recovery/Mem/NB/mrntrain3.c | 101 + .../agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrt3.c | 123 + .../f10/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c | 239 ++ .../f10/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c | 348 +++ .../f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c | 269 ++ .../f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h | 129 + .../f10/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c | 340 +++ .../amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c | 110 + .../amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttsrc.c | 499 ++++ .../amd/agesa/f10/Proc/Recovery/Mem/mrdef.c | 113 + .../amd/agesa/f10/Proc/Recovery/Mem/mrinit.c | 106 + .../amd/agesa/f10/Proc/Recovery/Mem/mrm.c | 287 ++ .../amd/agesa/f10/Proc/Recovery/Mem/mrport.h | 85 + .../amd/agesa/f10/Proc/Recovery/Mem/mrt3.h | 119 + .../amd/agesa/f10/Proc/Recovery/Mem/mru.asm | 187 ++ .../amd/agesa/f10/Proc/Recovery/Mem/mru.h | 131 + .../amd/agesa/f10/Proc/Recovery/Mem/mruc.c | 262 ++ .../amd/agesa/f10/Proc/Recovery/recoveryPage.h | 57 + src/vendorcode/amd/agesa/f10/cpcar.inc | 477 ++++ src/vendorcode/amd/agesa/f10/cpcarmac.inc | 406 +++ src/vendorcode/amd/agesa/f10/errno.h | 38 + src/vendorcode/amd/agesa/f10/gcccar.inc | 1612 +++++++++++ 573 files changed, 180355 insertions(+), 0 deletions(-) diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 260e2c1..bd55573 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -1,3 +1,4 @@ +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += $(src)/vendorcode/amd/agesa/f10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += $(src)/vendorcode/amd/agesa/f12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += $(src)/vendorcode/amd/agesa/f14 diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h new file mode 100755 index 0000000..c50086d --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/AGESA.h @@ -0,0 +1,2901 @@ +/** + * @file + * + * Agesa structures and definitions + * + * Contains AMD AGESA core interface + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e \$Revision: 47176 $ @e \$Date: 2011-02-15 19:56:01 -0700 (Tue, 15 Feb 2011) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#ifndef _AGESA_H_ +#define _AGESA_H_ + +#include "Porting.h" +#include "AMD.h" + +// +// +// AGESA Types and Definitions +// +// + +// AGESA BASIC CALLOUTS +#define AGESA_MEM_RELEASE 0x00028000 + +// AGESA ADVANCED CALLOUTS, Processor +#define AGESA_CHECK_UMA 0x00028100 +#define AGESA_DO_RESET 0x00028101 +#define AGESA_ALLOCATE_BUFFER 0x00028102 +#define AGESA_DEALLOCATE_BUFFER 0x00028103 +#define AGESA_LOCATE_BUFFER 0x00028104 +#define AGESA_RUNFUNC_ONAP 0x00028105 + +// AGESA ADVANCED CALLOUTS, HyperTransport + +// AGESA ADVANCED CALLOUTS, Memory +#define AGESA_READ_SPD 0x00028140 +#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141 +#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142 +#define AGESA_READ_SPD_RECOVERY 0x00028143 +#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144 + +// AGESA IDS CALLOUTS +#define AGESA_GET_IDS_INIT_DATA 0x00028200 + +// AGESA GNB CALLOUTS +#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301 + +//------------------------------------------------------------------------ +// +// HyperTransport Interface + + + +//----------------------------------------------------------------------------- +// HT DEFINITIONS AND MACROS +// +//----------------------------------------------------------------------------- + + +// Width equates for call backs +#define HT_WIDTH_8_BITS 8 ///< Specifies 8 bit, or up to 8 bit widths. +#define HT_WIDTH_16_BITS 16 ///< Specifies 16 bit, or up to 16 bit widths. +#define HT_WIDTH_4_BITS 4 +#define HT_WIDTH_2_BITS 2 +#define HT_WIDTH_NO_LIMIT HT_WIDTH_16_BITS + +// Frequency Limit equates for call backs which take a frequency supported mask. +#define HT_FREQUENCY_LIMIT_200M 1 ///< Specifies a limit of no more than 200 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_400M 7 ///< Specifies a limit of no more than 400 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_600M 0x1F ///< Specifies a limit of no more than 600 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_800M 0x3F ///< Specifies a limit of no more than 800 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_1000M 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_HT1_ONLY 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_1200M 0xFF ///< Specifies a limit of no more than 1200 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_1400M 0x1FF ///< Specifies a limit of no more than 1400 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_1600M 0x3FF ///< Specifies a limit of no more than 1600 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_1800M 0x7FF ///< Specifies a limit of no more than 1800 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_2000M 0xFFF ///< Specifies a limit of no more than 2000 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_2200M 0x1FFF ///< Specifies a limit of no more than 2200 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_2400M 0x3FFF ///< Specifies a limit of no more than 2400 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_2600M 0x7FFF ///< Specifies a limit of no more than 2600 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_2800M 0x27FFF ///< Specifies a limit of no more than 2800 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_3000M 0x67FFF ///< Specifies a limit of no more than 3000 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_3200M 0xE7FFF ///< Specifies a limit of no more than 3200 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_3600M 0x1E7FFF +#define HT_FREQUENCY_LIMIT_MAX HT_FREQUENCY_LIMIT_3600M +#define HT_FREQUENCY_NO_LIMIT 0xFFFFFFFF ///< Specifies a no limit of HT frequency. + +// Unit ID Clumping special values +#define HT_CLUMPING_DISABLE 0x00000000 +#define HT_CLUMPING_NO_LIMIT 0xFFFFFFFF + +#define HT_LIST_TERMINAL 0xFF ///< End of list. +#define HT_LIST_MATCH_ANY 0xFE ///< Match Any value, used for Sockets, Links, IO Chain Depth. +#define HT_LIST_MATCH_INTERNAL_LINK 0xFD ///< Match all of the internal links. + +// Event Notify definitions + +// Event definitions. + +// Coherent subfunction events +#define HT_EVENT_COH_EVENTS 0x10001000 +#define HT_EVENT_COH_NO_TOPOLOGY 0x10011000 ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY. +#define HT_EVENT_COH_OBSOLETE000 0x10021000 // No longer used. +#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000 ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX. +#define HT_EVENT_COH_NODE_DISCOVERED 0x10041000 ///< See ::HT_EVENT_COH_NODE_DISCOVERED. +#define HT_EVENT_COH_MPCAP_MISMATCH 0x10051000 ///< See ::HT_EVENT_COH_MPCAP_MISMATCH. + +// Non-coherent subfunction events +#define HT_EVENT_NCOH_EVENTS 0x10002000 +#define HT_EVENT_NCOH_BUID_EXCEED 0x10012000 ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED +#define HT_EVENT_NCOH_OBSOLETE000 0x10022000 // No longer used. +#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000 ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED. +#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000 ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED. +#define HT_EVENT_NCOH_DEVICE_FAILED 0x10052000 ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED +#define HT_EVENT_NCOH_AUTO_DEPTH 0x10062000 ///< See ::HT_EVENT_NCOH_AUTO_DEPTH + +// Optimization subfunction events +#define HT_EVENT_OPT_EVENTS 0x10003000 +#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x10013000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP. +#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x10023000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP. +#define HT_EVENT_OPT_UNUSED_LINKS 0x10033000 ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS. +#define HT_EVENT_OPT_LINK_PAIR_EXCEED 0x10043000 ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED. + +// HW Fault events +#define HT_EVENT_HW_EVENTS 0x10004000 +#define HT_EVENT_HW_SYNCFLOOD 0x10014000 ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD. +#define HT_EVENT_HW_HTCRC 0x10024000 ///< See ::HT_EVENT_DATA_HW_HT_CRC. + +// The Recovery HT component uses 0x10005000 for events. +// For consistency, we avoid that range here. + +#define HT_MAX_NC_BUIDS 32 +//---------------------------------------------------------------------------- +// HT TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- + +/// Specify the state redundant links are to be left in after match. +/// +/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone, +/// or powered off. + +typedef enum { + MATCHED, ///< The link matches the requested customization. + ///< When used with IGNORE_LINK, + ///< this will generally require other software to initialize the link. + ///< When used with SKIP_REGANG, + ///< the two unganged links will be available for distribution. + + POWERED_OFF, ///< Power the link off. Support may vary based on processor model. + ///< Power Off is only supported for coherent links. + ///< Link power off may occur at a warm reset rather than immediately. + ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link. + + UNMATCHED, ///< The link should be processed according to normal defaults. + ///< Effectively, the link does not match the requested customization. + ///< This can be used to exclude links from a following match any. + + MaxFinalLinkState ///< Not a final link state, use for limit checking. +} FINAL_LINK_STATE; + +/// Swap a device from its current id to a new one. + +typedef struct { + IN UINT8 FromId; ///< The device responding to FromId, + IN UINT8 ToId; ///< will be moved to ToId. +} BUID_SWAP_ITEM; + + +/// Each Non-coherent chain may have a list of device swaps. After performing the swaps, +/// the final in order list of device ids is provided. (There can be more swaps than devices.) +/// The unused entries in both are filled with 0xFF. + +typedef struct { + IN BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform + IN UINT8 FinalIds[HT_MAX_NC_BUIDS]; ///< The ordered final BUIDs, resulting from the swaps +} BUID_SWAP_LIST; + + +/// Control Manual Initialization of Non-Coherent Chains +/// +/// This interface is checked every time a non-coherent chain is +/// processed. BUID assignment may be controlled explicitly on a +/// non-coherent chain. Provide a swap list. Swaps controls the +/// BUID assignment and FinalIds provides the device to device +/// Linking. Device orientation can be detected automatically, or +/// explicitly. See interface documentation for more details. +/// +/// If a manual swap list is not supplied, +/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially +/// based on each device's unit count. + +typedef struct { + // Match fields + IN UINT8 Socket; ///< The Socket on which this chain is located + IN UINT8 Link; ///< The Link on the host for this chain + // Override fields + IN BUID_SWAP_LIST SwapList; ///< The swap list +} MANUAL_BUID_SWAP_LIST; + + +/// Override options for DEVICE_CAP_OVERRIDE. +/// +/// Specify which override actions should be performed. For Checks, 1 means to check the item +/// and 0 means to skip the check. For the override options, 1 means to apply the override and +/// 0 means to ignore the override. + +typedef struct { + IN UINT32 IsCheckDevVenId:1; ///< Check Match on Device/Vendor id + IN UINT32 IsCheckRevision:1; ///< Check Match on device Revision + IN UINT32 IsOverrideWidthIn:1; ///< Override Width In + IN UINT32 IsOverrideWidthOut:1; ///< Override Width Out + IN UINT32 IsOverrideFreq:1; ///< Override Frequency + IN UINT32 IsOverrideClumping:1; ///< Override Clumping + IN UINT32 IsDoCallout:1; ///< Make the optional callout +} DEVICE_CAP_OVERRIDE_OPTIONS; + +/// Override capabilities of a device. +/// +/// This interface is checked once for every Link on every IO device. +/// Provide the width and frequency capability if needed for this device. +/// This is used along with device capabilities, the limit interfaces, and northbridge +/// limits to compute the default settings. The components of the device's PCI config +/// address are provided, so its settings can be consulted if need be. +/// The optional callout is a catch all. + +typedef struct { + // Match fields + IN UINT8 HostSocket; ///< The Socket on which this chain is located. + IN UINT8 HostLink; ///< The Link on the host for this chain. + IN UINT8 Depth; ///< The Depth in the I/O chain from the Host. + IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00). + IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08). + IN UINT8 Link; ///< The Device's Link number (0 or 1). + IN DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override. + // Override fields + IN UINT8 LinkWidthIn; ///< modify to change the Link Width In. + IN UINT8 LinkWidthOut; ///< modify to change the Link Width Out. + IN UINT32 FreqCap; ///< modify to change the Link's frequency capability. + IN UINT32 Clumping; ///< modify to change Unit ID clumping support. + IN CALLOUT_ENTRY Callout; ///< optional call for really complex cases, or NULL. +} DEVICE_CAP_OVERRIDE; + +/// Callout param struct for override capabilities of a device. +/// +/// If the optional callout is implemented this param struct is passed to it. + +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + // Match fields + IN UINT8 HostSocket; ///< The Socket on which this chain is located. + IN UINT8 HostLink; ///< The Link on the host for this chain. + IN UINT8 Depth; ///< The Depth in the I/O chain from the Host. + IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00). + IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08). + IN UINT8 Link; ///< The Device's Link number (0 or 1). + IN PCI_ADDR PciAddress; ///< The Device's PCI Address. + // Override fields + OUT UINT8 *LinkWidthIn; ///< modify to change the Link Width In. + OUT UINT8 *LinkWidthOut; ///< modify to change the Link Width Out. + OUT UINT32 *FreqCap; ///< modify to change the Link's frequency capability. + OUT UINT32 *Clumping; ///< modify to change Unit ID clumping support. +} DEVICE_CAP_CALLOUT_PARAMS; + +/// Limits for CPU to CPU Links. +/// +/// For each coherent connection this interface is checked once. +/// Provide the frequency and width if needed for this Link (usually based on board +/// restriction). This is used with CPU device capabilities and northbridge limits +/// to compute the default settings. + +typedef struct { + // Match fields + IN UINT8 SocketA; ///< One Socket on which this Link is located + IN UINT8 LinkA; ///< The Link on this Node + IN UINT8 SocketB; ///< The other Socket on which this Link is located + IN UINT8 LinkB; ///< The Link on that Node + // Limit fields + IN UINT8 ABLinkWidthLimit; ///< modify to change the Link Width A->B + IN UINT8 BALinkWidthLimit; ///< modify to change the Link Width B- EndLane) + * See lane description for @ref F12PcieLaneDescription "Family 0x12" + * @ref F14PcieLaneDescription "Family 0x14". + */ + IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane) + * See lane description for @ref F12PcieLaneDescription "Family 0x12", + * @ref F14PcieLaneDescription "Family 0x14". + */ + +} PCIe_ENGINE_DATA; + +/// PCIe port descriptor +typedef struct { + IN UINT32 Flags; /**< Descriptor flags + * @li @b Bit31 - last descriptor in complex + */ + IN PCIe_ENGINE_DATA EngineData; ///< Engine data + IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info +} PCIe_PORT_DESCRIPTOR; + +/// DDI descriptor +typedef struct { + IN UINT32 Flags; /**< Descriptor flags + * @li @b Bit31 - last descriptor in complex + */ + IN PCIe_ENGINE_DATA EngineData; ///< Engine data + IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info +} PCIe_DDI_DESCRIPTOR; + +/// PCIe Complex descriptor +typedef struct { + IN UINT32 Flags; /**< Descriptor flags + * @li @b Bit31 - last descriptor in topology + */ + IN UINT32 SocketId; ///< Socket Id + IN PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). + IN PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). + IN VOID *Reserved; ///< Reserved for future use +} PCIe_COMPLEX_DESCRIPTOR; + +/// Action to control PCIe slot reset +typedef enum { + AssertSlotReset, ///< Assert slot reset + DeassertSlotReset ///< Deassert slot reset +} PCIE_RESET_CONTROL; + +///Slot Reset Info +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR + IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL +} PCIe_SLOT_RESET_INFO; + +/// Engine descriptor type +typedef enum { + PcieUnusedEngine = 0, ///< Unused descriptor + PciePortEngine = 1, ///< PCIe port + PcieDdiEngine = 2, ///< DDI + MaxPcieEngine ///< Max engine type for boundary check. +} PCIE_ENGINE_TYPE; + +/// PCIe link capability/speed +typedef enum { + PcieGenMaxSupported, ///< Maximum supported + PcieGen1 = 1, ///< Gen1 + PcieGen2, ///< Gen2 + MaxPcieGen ///< Max Gen for boundary check +} PCIE_LINK_SPEED_CAP; + +/// PCIe PSPP Power policy +typedef enum { + PsppDisabled, ///< PSPP disabled + PsppPerformance = 1, ///< Performance + PsppBalanceHigh, ///< Balance-High + PsppBalanceLow, ///< Balance-Low + PsppPowerSaving, ///< Power Saving + MaxPspp +} PCIE_PSPP_POLICY; + +/// DDI display connector type +typedef enum { + ConnectorTypeDP, ///< DP + ConnectorTypeEDP, ///< eDP + ConnectorTypeSingleLinkDVI, ///< Single Link DVI + ConnectorTypeDualLinkDVI, ///< Dual Link DVI + ConnectorTypeHDMI, ///< HDMI + ConnectorTypeTravisDpToVga, ///< Travis DP-to-VGA + ConnectorTypeTravisDpToLvds, ///< Travis DP-to-LVDS + ConnectorTypeNutmegDpToVga, ///< SB900 NutMeg DP-to-VGA + MaxConnectorType ///< Not valid value, used to verify input +} PCIE_CONNECTOR_TYPE; + +/// PCIe link channel type +typedef enum { + ChannelTypeLowLoss, ///< Low Loss + ChannelTypeHighLoss, ///< High Loss + ChannelTypeMob0db, ///< Mobile 0dB + ChannelTypeMob3db, ///< Mobile 3dB + ChannelTypeExt6db, ///< Extended 6dB + ChannelTypeExt8db, ///< Extended 8dB + MaxChannelType ///< Not valid value, used to verify input +} PCIE_CHANNEL_TYPE; + +/// PCIe link ASPM +typedef enum { + AspmDisabled, ///< Disabled + AspmL0s, ///< PCIe L0s link state + AspmL1, ///< PCIe L1 link state + AspmL0sL1, ///< PCIe L0s & L1 link state + MaxAspm ///< Not valid value, used to verify input +} PCIE_ASPM_TYPE; + +/// PCIe link hotplug support +typedef enum { + HotplugDisabled, ///< Hotplug disable + HotplugBasic, ///< Basic Hotplug + HotplugServer, ///< Server Hotplug + HotplugEnhanced, ///< Enhanced + MaxHotplug ///< Not valid value, used to verify input +} PCIE_HOTPLUG_TYPE; + +/// PCIe link initialization +typedef enum { + PortDisabled, ///< Disable + PortEnabled ///< Enable +} PCIE_PORT_ENABLE; + +/// DDI Aux channel +typedef enum { + Aux1, ///< Aux1 + Aux2, ///< Aux2 + Aux3, ///< Aux3 + Aux4, ///< Aux4 + Aux5, ///< Aux5 + Aux6, ///< Aux6 + MaxAux ///< Not valid value, used to verify input +} PCIE_AUX_TYPE; + +/// DDI Hdp Index +typedef enum { + Hdp1, ///< Hdp1 + Hdp2, ///< Hdp2 + Hdp3, ///< Hdp3 + Hdp4, ///< Hdp4 + Hdp5, ///< Hdp5 + Hdp6, ///< Hdp6 + MaxHdp ///< Not valid value, used to verify input +} PCIE_HDP_TYPE; + +// Macro for statically initialization of various structures +#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane} +#define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxGen, mSpeedChangeMode, mAspm, mResetId) \ +{mPortPresent, mChannelType, mDevAddress, 0, mMaxGen, mSpeedChangeMode, mAspm, mHotplug, mResetId } +#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ +{mConnectorType, mAuxIndex, mHpdIndex} + +/*---------------------------------------------------------------------------- + * GNB configuration info + *---------------------------------------------------------------------------- + */ + +/// GNB configuration info +typedef struct { + IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. + * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Example of topology definition for single socket system: + * @code + * PCIe_PORT_DESCRIPTOR PortList [] = { + * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) + * { + * 0, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), + * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + * }, + * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) + * { + * 0, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), + * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + * }, + * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + * { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + * } + * }; + * PCIe_PORT_DESCRIPTOR DdiList [] = { + * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...) + * { + * 0, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) + * }, + * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) + * { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) + * } + * }; + * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list + * 0, //Socket ID + * &PortList[0], + * &DdiList[0], + * } + * @endcode + */ + IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy) + * @li @b 0 - Disabled + * @li @b 1 - Performance + * @li @b 2 - Balance-High + * @li @b 3 - Balance-Low + * @li @b 4 - Power Saving + */ + +} GNB_CONFIGURATION; +// +// MEMORY-SPECIFIC DATA STRUCTURES +// +// +// +// +// AGESA MAXIMIUM VALUES +// +// These Max values are used to define array sizes and associated loop +// counts in the code. They reflect the maximum values that AGESA +// currently supports and does not necessarily reflect the hardware +// capabilities of configuration. +// + +#define MAX_SOCKETS_SUPPORTED 8 ///< Max number of sockets in system +#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets +#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform) +#define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT. + ///< Eg: UINT16 *RcvEnDlys; + ///< UINT8 *WrDqsDlys; + ///< UINT8 *RdDqsDlys; + ///< UINT8 *WrDatDlys; + ///< UINT8 *RdDqsMinDlys; + ///< UINT8 *RdDqsMaxDlys; + ///< UINT8 *WrDatMinDlys; + ///< UINT8 *WrDatMaxDlys; +#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables + +#define MAX_PLATFORM_TYPES 16 ///< Platform types per system + +#define MCT_TRNG_KEEPOUT_START 0x00004000 ///< base [39:8] +#define MCT_TRNG_KEEPOUT_END 0x00007FFF ///< base [39:8] + +#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000 ///< Uma Region is interleaved + +typedef UINT8 PSO_TABLE; ///< Platform Configuration Table + +// AGESA DEFINITIONS +// +// Many of these are derived from the platform and hardware specific definitions + +/// EccSymbolSize override value +#define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value +#define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4 +#define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8 +/// CPU Package Type +#define PT_L1 0 ///< L1 Package type +#define PT_M2 1 ///< AM Package type +#define PT_S1 2 ///< S1 Package type + +/// Structures use to pass system Logical CPU-ID +typedef struct { + IN OUT UINT64 Family; ///< Indicates logical ID Family + IN OUT UINT64 Revision; ///< Indicates logical ID Family +} CPU_LOGICAL_ID; + +/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE +typedef enum { + AMD_PLATFORM_SERVER = 0x8000, ///< Server + AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop + AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile +} AMD_PLATFORM_TYPE; + +/// Dram technology type +typedef enum { + DDR2_TECHNOLOGY, ///< DDR2 technology + DDR3_TECHNOLOGY ///< DDR3 technology +} TECHNOLOGY_TYPE; + +/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT +typedef enum { + DDR400_FREQUENCY = 200, ///< DDR 400 + DDR533_FREQUENCY = 266, ///< DDR 533 + DDR667_FREQUENCY = 333, ///< DDR 667 + DDR800_FREQUENCY = 400, ///< DDR 800 + DDR1066_FREQUENCY = 533, ///< DDR 1066 + DDR1333_FREQUENCY = 667, ///< DDR 1333 + DDR1600_FREQUENCY = 800, ///< DDR 1600 + DDR1866_FREQUENCY = 933, ///< DDR 1866 + UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency +} MEMORY_BUS_SPEED; + +/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE +typedef enum { + QUADRANK_REGISTERED, ///< Quadrank registered DIMM + QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM +} QUANDRANK_TYPE; + +/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT +typedef enum { + TIMING_MODE_AUTO, ///< Use best rate possible + TIMING_MODE_LIMITED, ///< Set user top limit + TIMING_MODE_SPECIFIC ///< Set user specified speed +} USER_MEMORY_TIMING_MODE; + +/// Build Configuration values for BLDCFG_POWER_DOWN_MODE +typedef enum { + POWER_DOWN_BY_CHANNEL, ///< Channel power down mode + POWER_DOWN_BY_CHIP_SELECT ///< Chip select power down mode +} POWER_DOWN_MODE; + +/// Low voltage support +typedef enum { + VOLT1_5, ///< 1.5 Volt + VOLT1_35, ///< 1.35 Volt + VOLT1_25, ///< 1.25 Volt + VOLT_UNSUPPORTED = 0xFF ///< No common voltage found +} DIMM_VOLTAGE; + +/// UMA Mode +typedef enum { + UMA_NONE = 0, ///< UMA None + UMA_SPECIFIED = 1, ///< UMA Specified + UMA_AUTO = 2 ///< UMA Auto +} UMA_MODE; + +/// Build Configuration values for BLDCFG_UMA_ALIGNMENT +typedef enum { + NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned + UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned + UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned + UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned +} UMA_ALIGNMENT; + +/// +/// Global MCT Configuration Status Word (GStatus) +/// +typedef enum { + GsbMTRRshort, ///< Ran out of MTRRs while mapping memory + GsbAllECCDimms, ///< All banks of all Nodes are ECC capable + GsbDramECCDis, ///< Dram ECC requested but not enabled. + GsbSoftHole, ///< A Node Base gap was created + GsbHWHole, ///< A HW dram remap was created + GsbNodeIntlv, ///< Node Memory interleaving was enabled + GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping + GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset + + GsbEOL ///< End of list +} GLOBAL_STATUS_FIELD; + +/// +/// Local Error Status (DIE_STRUCT.ErrStatus[31:0]) +/// +typedef enum { + EsbNoDimms, ///< No DIMMs + EsbSpdChkSum, ///< SPD Checksum fail + EsbDimmMismatchM, ///< dimm module type(buffer) mismatch + EsbDimmMismatchT, ///< dimm CL/T mismatch + EsbDimmMismatchO, ///< dimm organization mismatch (128-bit) + EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info + EsbNoCycTime, ///< SPD missing byte 23 or 25 + EsbBkIntDis, ///< Bank interleave requested but not enabled + EsbDramECCDis, ///< Dram ECC requested but not enabled + EsbSpareDis, ///< Online spare requested but not enabled + EsbMinimumMode, ///< Running in Minimum Mode + EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found + EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range) + EsbNoDqsPos, ///< No DQS-DQ passing positions + EsbSmallDqs, ///< DQS-DQ passing window too small + EsbDCBKScrubDis, ///< DCache scrub requested but not enabled + + EsbEMPNotSupported, ///< Processor is not capable for EMP. + EsbEMPConflict, ///< EMP requested but cannot be enabled since + ///< channel interleaving, bank interleaving, or bank swizzle is enabled. + EsbEMPDis, ///< EMP requested but cannot be enabled since + ///< memory size of each DCT is not a power of two. + + EsbEOL ///< End of list +} ERROR_STATUS_FIELD; + +/// +/// Local Configuration Status (DIE_STRUCT.Status[31:0]) +/// +typedef enum { + SbRegistered, ///< All DIMMs are Registered + SbEccDimms, ///< All banks ECC capable + SbParDimms, ///< All banks Addr/CMD Parity capable + SbDiagClks, ///< Jedec ALL slots clock enable diag mode + Sb128bitmode, ///< DCT in 128-bit mode operation + Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode. + Sb2TMode, ///< 2T CMD timing mode is enabled. + SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap. + SbHWHole, ///< Memory Hole created on this Node using HW remapping. + SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag + SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz + SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound. + SbExtConfig, ///< Indicate the default setting for extended PCI configuration support + + SbEOL ///< End of list +} LOCAL_STATUS_FIELD; + + +///< CPU MSR Register definitions ------------------------------------------ +#define SYS_CFG 0xC0010010 +#ifndef TOP_MEM + #define TOP_MEM 0xC001001A +#endif +#ifndef TOP_MEM2 + #define TOP_MEM2 0xC001001D +#endif +#define HWCR 0xC0010015 +#define NB_CFG 0xC001001F + +#define FS_BASE 0xC0000100 +#define IORR0_BASE 0xC0010016 +#define IORR0_MASK 0xC0010017 +#define BU_CFG 0xC0011023 +#define BU_CFG2 0xC001102A +#define COFVID_STAT 0xC0010071 +#define TSC 0x10 + +//----------------------------------------------------------------------------- +/// +/// SPD Data for each DIMM. +/// +typedef struct _SPD_DEF_STRUCT { + IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid + IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM +} SPD_DEF_STRUCT; + +/// +/// Channel Definition Structure. +/// This data structure defines entries that are specific to the channel initialization +/// +typedef struct _CH_DEF_STRUCT { + OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D) + OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel + OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. + ///< DIMM# Select Signal + ///< 0 MA0_CS_L[0, 1] + ///< 1 MB0_CS_L[0, 1] + ///< 2 MA1_CS_L[0, 1] + ///< 3 MB1_CS_L[0, 1] + ///< 4 MA2_CS_L[0, 1] + ///< 5 MB2_CS_L[0, 1] + ///< 6 MA3_CS_L[0, 1] + ///< 7 MB3_CS_L[0, 1] + + OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel. + OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel. + OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor) + OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to + ///< SPD Data for each Dimm. (Setup by Tech Block Constructor) + OUT UINT8 ChDimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is/will be configured + ///< + OUT UINT8 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is a registered DIMM + OUT UINT8 SODimmPresent; ///< For each bit n 0..7, 1 = DIMM n is a SO-DIMM + OUT UINT8 Loads; ///< Number of devices loading bus + OUT UINT8 Dimms; ///< Number of DIMMs loading Channel + OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA + OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) + ///< FALSE = 1T + ///< TRUE = 2T + ///< The following pointers will be pointed to dynamically allocated buffers. + ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below. + ///< Example: If DIMM and Byte based training, then + ///< XX is a value in Hex + ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE + ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX + ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX + OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays + OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3) + OUT UINT8 *RdDqsDlys; ///< Read Dqs delays + OUT UINT8 *WrDatDlys; ///< Write Data delays + OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS + OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS + OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data + OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data + OUT UINT8 RowCount; ///< Number of rows of the allocated buffer. + OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer. + OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits + OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h) + OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) + OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h) + OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h) + OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h) + OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183) + OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8]) + OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like... + OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale + OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern + OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern + OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7) + OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write) + OUT UINT8 Pattern; ///< Current pattern + OUT UINT8 DqsDelay; ///< Current DQS delay value + OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. + OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. + OUT UINT16 DctMaxRdLat; ///< Max Read Latency (ns) for the DCT + OUT UINT8 DIMMValidCh; ///< DIMM# in CH + OUT UINT8 MaxCh; ///< Max number of CH in system + OUT UINT8 Dct; ///< Dct pointer + OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value + OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low + + OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB + OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly + OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K) + OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag + OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag + OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training + + OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory + OUT UINT32 NodeSysBase; ///< for channel interleave usage + OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected + OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM + OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM + OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM + OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM + OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM + + OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present + OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable + OUT UINT8 DimmSpdCse; ///< For each bit n 0..7, 1 = DIMM n SPD checksum error + OUT UINT8 DimmExclude; ///< For each bit n 0..7, 1 = DIMM n gets excluded + OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006 + OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June) + OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present. + OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present? + OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present + OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present + OUT UINT8 Dimmx4Present; ///< For each bit n 0..7, 1 = DIMM n contains x4 data devices. + OUT UINT8 Dimmx8Present; ///< For each bit n 0..7, 1 = DIMM n contains x8 data devices. + OUT UINT8 Dimmx16Present; ///< For each bit n 0..7, 1 = DIMM n contains x16 data devices. + + OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes + ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will + ///< base on this array to disable unused MemClk to save power. + ///< + ///< The array must have 8 entries. Each entry, which associates with + ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to. + ///< Example: + ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package + ///< is like below: + ///< Bit AM3/S1g3 pin name + ///< 0 M[B,A]_CLK_H/L[0] + ///< 1 M[B,A]_CLK_H/L[1] + ///< 2 M[B,A]_CLK_H/L[2] + ///< 3 M[B,A]_CLK_H/L[3] + ///< 4 M[B,A]_CLK_H/L[4] + ///< 5 M[B,A]_CLK_H/L[5] + ///< 6 M[B,A]_CLK_H/L[6] + ///< 7 M[B,A]_CLK_H/L[7] + ///< And platform has the following routing: + ///< CS0 M[B,A]_CLK_H/L[4] + ///< CS1 M[B,A]_CLK_H/L[2] + ///< CS2 M[B,A]_CLK_H/L[3] + ///< CS3 M[B,A]_CLK_H/L[5] + ///< Then MemClkDisMap should be pointed to the following array: + ///< CLK_2 CLK_3 CLK_4 CLK_5 + ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00 + ///< Each entry of the array is the bitmask of 8 chip selects. + + OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes + ///< the routing of CKE pins to the DIMMs' ranks. + ///< The array must have 2 entries. Each entry, which associates with + ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to. + ///< AGESA will base on this array to disable unused CKE pins to save power. + + OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes + ///< the routing of ODT pins to the DIMMs' ranks. + ///< The array must have 4 entries. Each entry, which associates with + ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to. + ///< AGESA will base on this array to disable unused ODT pins to save power. + + OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes + ///< the routing of chip select pins to the DIMMs' ranks. + ///< The array must have 8 entries. Each entry is a bitmap of 8 CS. + ///< AGESA will base on this array to disable unused Chip select pins to save power. + + OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel. + + OUT UINT8 Reserved[100]; ///< Reserved +} CH_DEF_STRUCT; + +/// +/// DCT Channel Timing Parameters. +/// This data structure sets timings that are specific to the channel. +/// +typedef struct _CH_TIMING_STRUCT { + OUT UINT16 DctDimmValid; ///< For each bit n 0..7, 1=DIMM n is valid and is/will be configured + OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..7, 1=DIMM n is OnDimmMirror capable + OUT UINT16 DimmSpdCse; ///< For each bit n 0..7, 1=DIMM n SPD checksum error + OUT UINT16 DimmExclude; ///< For each bit n 0..7, 1 = DIMM n gets excluded + OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present + OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled + OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled + OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training + OUT UINT16 DIMM1KPage; ///< For each bit n 0..7, 1=DIMM n contains 1K page devices. + OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present? + OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present + OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present + OUT UINT16 Dimmx4Present; ///< For each bit n 0..7, 1=DIMM n contains x4 data devices. + OUT UINT16 Dimmx8Present; ///< For each bit n 0..7, 1=DIMM n contains x8 data devices. + OUT UINT16 Dimmx16Present; ///< For each bit n 0..7, 1=DIMM n contains x16 data devices. + + OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs + OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs + OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs + OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs + OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs + OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs + OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs + OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs + OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs + OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz + OUT UINT16 Speed; ///< DRAM bus speed in MHz + ///< 400 (MHz) + ///< 533 (MHz) + ///< 667 (MHz) + ///< 800 (MHz) + ///< and so on... + OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks) + OUT UINT8 Trcd; ///< DCT Trcd (busclocks) + OUT UINT8 Trp; ///< DCT Trp (busclocks) + OUT UINT8 Trtp; ///< DCT Trtp (busclocks) + OUT UINT8 Tras; ///< DCT Tras (busclocks) + OUT UINT8 Trc; ///< DCT Trc (busclocks) + OUT UINT8 Twr; ///< DCT Twr (busclocks) + OUT UINT8 Trrd; ///< DCT Trrd (busclocks) + OUT UINT8 Twtr; ///< DCT Twtr (busclocks) + OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks) + OUT UINT8 Trfc0; ///< DCT Logical DIMM0 Trfc + ///< 0 = 75ns (for 256Mb devs) + ///< 1 = 105ns (for 512Mb devs) + ///< 2 = 127.5ns (for 1Gb devs) + ///< 3 = 195ns (for 2Gb devs) + ///< 4 = 327.5ns (for 4Gb devs) + OUT UINT8 Trfc1; ///< DCT Logical DIMM1 Trfc (see Trfc0 for format) + OUT UINT8 Trfc2; ///< DCT Logical DIMM2 Trfc (see Trfc0 for format) + OUT UINT8 Trfc3; ///< DCT Logical DIMM3 Trfc (see Trfc0 for format) + OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT. + ///< + OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) + ///< FALSE = 1T + ///< TRUE = 2T + OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks) + OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks) + OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks) + OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks) + OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks) + OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks) + OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks) + OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks) + OUT UINT16 MaxRdLat; ///< Max Read Latency + OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed + OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed +} CH_TIMING_STRUCT; + +/// +/// Data for each DCT. +/// This data structure defines data used to configure each DRAM controller. +/// +typedef struct _DCT_STRUCT { + OUT UINT8 Dct; ///< Current Dct + OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure + OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures + OUT UINT8 ChannelCount; ///< Number of channel per this DCT +} DCT_STRUCT; + + +/// +/// Data Structure defining each Die. +/// This data structure contains information that is used to configure each Die. +/// +typedef struct _DIE_STRUCT { + + /// Advanced: + + OUT UINT8 NodeId; ///< Node ID of current controller + OUT UINT8 SocketId; ///< Socket ID of this Die + OUT UINT8 DieId; ///< ID of this die relative to the socket + OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller. + OUT AGESA_STATUS ErrCode; ///< Current error condition of Node + ///< 0x0 = AGESA_SUCCESS + ///< 0x1 = AGESA_UNSUPPORTED + ///< 0x2 = AGESA_BOUNDS_CHK + ///< 0x3 = AGESA_ALERT + ///< 0x4 = AGESA_WARNING + ///< 0x5 = AGESA_ERROR + ///< 0x6 = AGESA_CRITICAL + ///< 0x7 = AGESA_FATAL + ///< + OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field + ///< + OUT BOOLEAN Status[SbEOL]; ///< Status bit Field + ///< + OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node. + ///< + OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node. + ///< + OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node + ///< + OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node. + ///< + OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. + ///< DIMM# Select Signal + ///< 0 MA0_CS_L[0, 1] + ///< 1 MB0_CS_L[0, 1] + ///< 2 MA1_CS_L[0, 1] + ///< 3 MB1_CS_L[0, 1] + ///< 4 MA2_CS_L[0, 1] + ///< 5 MB2_CS_L[0, 1] + ///< 6 MA3_CS_L[0, 1] + ///< 7 MB3_CS_L[0, 1] + ///< + OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured + OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM + OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable. + OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable. + ///< + OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training + OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects + ///< 0 in any bit field indicates Channel 0 + ///< 1 in any bit field indicates Channel 1 + OUT UINT8 Dct; ///< Need to be removed + ///< DCT pointer + OUT BOOLEAN GangedMode; ///< Ganged mode + ///< 0 = disabled + ///< 1 = enabled + OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node + ///< + OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. + ///< + OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. + ///< + OUT UINT8 MLoad; ///< Need to be removed + ///< Number of devices loading MAA bus + ///< + OUT UINT8 MaxAsyncLat; ///< Legacy wrapper + ///< + OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper + ///< + OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0 + ///< + OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay + + OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs + OUT UINT8 DctCount; ///< Number of DCTs per this Die + OUT UINT8 Reserved[16]; ///< Reserved +} DIE_STRUCT; + +/********************************************************************** + * S3 Support structure + **********************************************************************/ +/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure +typedef struct { + OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM + OUT UINT16 Version; ///< S3 Params version number + IN OUT UINT32 Flags; ///< Indicates operation + IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data + IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region + IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data + IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region +} AMD_S3_PARAMS; + +///=============================================================================== +/// MEM_PARAMETER_STRUCT +/// This data structure is used to pass wrapper parameters to the memory configuration code +/// +typedef struct _MEM_PARAMETER_STRUCT { + + // Basic (Return parameters) + // (This section contains the outbound parameters from the memory init code) + + OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield. + ///< + OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping. + ///< + OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory. + ///< + OUT UINT32 Sub1THoleBase; ///< If not zero Base[47:16] (system address) of sub 1TB dram hole. + ///< + OUT UINT32 SysLimit; ///< Limit[47:16] (system address). + ///< + + OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS. + ///< 0 = 1.5v + ///< 1 = 1.35v + ///< 2 = 1.2v + ///< 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded + ///< from the system. + ///< + + OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data. + + // Advanced (Optional parameters) + // Optional (all defaults values will be initialized by the + // 'AmdMemInitDataStructDef' based on AMD defaults. It is up + // to the IBV/OEM to change the defaults after initialization + // but prior to the main entry to the memory code): + + // Memory Map/Mgt. + + IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits). + ///< NV_BOTTOM_IO[7:0]=Addr[31:24] + ///< + IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit). + ///< FALSE = disable + ///< TRUE = enable + ///< + IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB + ///< FALSE = disable + ///< TRUE = enable + ///< + ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB} + + + // Dram Timing + + IN USER_MEMORY_TIMING_MODE UserTimingMode; ///< User Memclock Mode. + ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT} + + IN MEMORY_BUS_SPEED MemClockValue; ///< Memory Clock Value. + ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT} + + + // Dram Configuration + + IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit). + ///< - FALSE =disable (default) + ///< - TRUE = enable + ///< + ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING} + + IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit). + ///< - FALSE = disable (default) + ///< - TRUE = enable + ///< + ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING} + + IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit). + ///< - FALSE = disable (default) + ///< - TRUE = enable + ///< + ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING} + // ECC + + IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE. + ///< - FALSE = disable (default) + ///< - TRUE = enable + ///< + ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE} + // Dram Power + + IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit). + ///< - FALSE =disable (default) + ///< - TRUE =enable + ///< + ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN} + + // Online Spare + + IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0. + ///< - FALSE = disable Spare (default) + ///< - TRUE = enable Spare + ///< + ///< @BldCfgItem{BLDCFG_ONLINE_SPARE} + + IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings. + + IN PSO_TABLE *PlatformMemoryConfiguration; + ///< A table that contains platform specific settings. + ///< For example, MemClk routing, the number of DIMM slots per channel, .... + ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that + ///< contains default conservative settings. Platform BIOS can either tweak + ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table. + ///< + IN BOOLEAN EnableParity; ///< Parity control. + ///< - TRUE = enable + ///< - FALSE = disable (default) + ///< + ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE} + + IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control. + ///< - FALSE = disable + ///< - TRUE = enable (default) + ///< + ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE} + + ///< + + IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control. + ///< - FALSE = disable + ///< - TRUE = enable (default) + ///< + + // Uma Configuration + + IN UMA_MODE UmaMode; ///< Uma Mode + ///< 0 = None + ///< 1 = Specified + ///< 2 = Auto + IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits) + ///< NV_UMA_Size[31:0]=Addr[47:16] + ///< + OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits) + ///< NV_UMA_Base[31:0]=Addr[47:16] + ///< + + /// Memory Restore Feature + + IN BOOLEAN MemRestoreCtl; ///< Memory context restore control + ///< FALSE = perform memory init as normal (AMD default) + ///< TRUE = restore memory context and skip training. This requires + ///< MemContext is valid before AmdInitPost + ///< + IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto + ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost + ///< FALSE = AGESA will not setup MemContext block. Platform is + ///< expected to call S3Save later in POST if it wants to + ///< use memory context restore feature. + ///< + IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to + ///< save and restore for memory context restore feature to work. + ///< It uses the subset of S3Save block to save/restore. Hence platform + ///< may save only S3 block and uses it for both S3 resume and + ///< memory context restore. + ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext + ///< before AmdInitPost. + ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext + ///< right after AmdInitPost. + ///< +} MEM_PARAMETER_STRUCT; + + +/// +/// Function definition. +/// This data structure passes function pointers to the memory configuration code. +/// The wrapper can use this structure with customized versions. +/// +typedef struct _MEM_FUNCTION_STRUCT { + + // PUBLIC required Internal functions + + IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific + IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific + + // PUBLIC optional functions + + IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature + IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature + IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature + IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature + IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature + IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature + IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part' + IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature + IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs + IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs + + IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition +} MEM_FUNCTION_STRUCT; + +/// +/// Socket Structure +/// +/// +typedef struct _MEM_SOCKET_STRUCT { + OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data + + OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data +} MEM_SOCKET_STRUCT; + +/// +/// Contains all data relevant to Memory Initialization. +/// +typedef struct _MEM_DATA_STRUCT { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + + IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters + + OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers + + IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info + + IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling + + + OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code. + ///< SocketList is a shortcut for IBVs to retrieve training + ///< and timing data for each channel indexed by socket/channel, + ///< eliminating their need to parse die/dct/channel etc. + ///< It contains pointers to the populated data structures for + ///< each channel and skips the channel structures that are + ///< unpopulated. In the case of channels sharing the same DCT, + ///< the pTimings pointers will point to the same DCT Timing data. + + OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs + OUT UINT8 DieCount; ///< Number of MCTs in the system. + + IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure + + IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure + +} MEM_DATA_STRUCT; + +/// +/// Uma Structure +/// +/// +typedef struct _UMA_INFO { + OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0] + OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0] + OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma + OUT UINT8 UmaMode; ///< Indicate the mode of Uma + OUT UINT16 MemClock; ///< Indicate memory running speed in MHz + OUT UINT8 Reserved[3]; ///< Reserved for future usage +} UMA_INFO; + +// AGESA MEMORY ERRORS + +// AGESA_ALERT Memory Errors +#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000 ///< TIMING_MODE_SPECIFIC is requested but + ///< cannot be applied to current configurations. +#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100 ///< DIMM organization miss-match +#define MEM_ALERT_BK_INT_DIS 0x04010200 ///< Bank interleaving disable for internal issue + +// AGESA_ERROR Memory Errors +#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300 ///< No DQS Position window for RD DQS +#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300 ///< Small DQS Position window for RD DQS +#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300 ///< No DQS Position window for WR DQS +#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300 ///< Small DQS Position window for WR DQS +#define MEM_ERROR_ECC_DIS 0x04010400 ///< ECC has been disabled as a result of an internal issue +#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues +#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large +#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window +#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit +#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit +#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit +#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit +#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit +#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit +#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit +#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit +#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit +#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit +#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit +#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit +#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit +#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training +#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP +#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training +#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm +#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value +#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit +#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200 ///< SPD Checksum error for NV_SPDCHK_RESTRT +#define MEM_ERROR_NO_CHIPSELECT 0x04011300 ///< No chipselects found +#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500 ///< Unbuffered dimm is not supported at 333MHz +#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x04011600 ///< Returned PRE value during write levelizzation was out of range + +// AGESA_WARNING Memory Errors +#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600 ///< QR DIMMs detected but not supported +#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600 ///< U DIMMs detected but not supported +#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600 ///< SO-DIMMs detected but not supported +#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600 ///< x4 DIMMs detected but not supported +#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600 ///< R DIMMs detected but not supported +#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700 ///< Processor is not capable for EMP +#define MEM_WARNING_EMP_CONFLICT 0x04021700 ///< EMP cannot be enabled if channel interleaving, +#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700 ///< Memory size is not power of two. +#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800 ///< Performance has been enabled, but battery life is preferred. + ///< bank interleaving, or bank swizzle is enabled. +#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900 ///< No Trc timing value found in SPD of a dimm. +#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000 ///< Node Interleaveing Requested, but could not be enabled +#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled +#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled +#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported + +// AGESA_FATAL Memory Errors +#define MEM_ERROR_MINIMUM_MODE 0x04011A00 ///< Running in minimum mode +#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00 ///< DIMM modules are miss-matched +#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs have been found +#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00 ///< DIMM clocks miss-matched +#define MEM_ERROR_NO_CYC_TIME 0x04011E00 ///< No cycle time found +#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00 ///< Heap allocation error with dynamic storing of trained timings +#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT +#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV +#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00 ///< Heap allocation error for SPD data +#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00 ///< Heap allocation error for RECEIVED_DATA during parallel training +#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00 ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER" +#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00 ///< Heap allocation error for Training Data +#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00 ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK +#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300 ///< No Constructor for DIMM Identify +#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500 ///< VDDIO of the dimms on the board is not supported + +// AGESA_CRITICAL Memory Errors +#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00 ///< Heap allocation error for DMI table for DDR3 +#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00 ///< Heap allocation error for DMI table for DDR2 +#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400 ///< Dimm population is not supported + + + +/*---------------------------------------------------------------------------- + * + * END OF MEMORY-SPECIFIC DATA STRUCTURES + * + *---------------------------------------------------------------------------- + */ + + + + +/*---------------------------------------------------------------------------- + * + * CPU RELATED DEFINITIONS + * + *---------------------------------------------------------------------------- + */ + +// CPU Event definitions. + +// Defines used to filter CPU events based on functional blocks +#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00 +#define CPU_EVENT_PM_EVENT_CLASS 0x08000400 + +//================================================================ +// CPU General events +// Heap allocation (AppFunction = 01h) +#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100 +#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100 +#define CPU_ERROR_HEAP_IS_FULL 0x08020100 +#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100 +#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100 +// BrandId (AppFunction = 02h) +#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200 +// Micro code patch (AppFunction = 03h) +#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300 +// Power management (AppFunction = 04h) +#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400 +#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400 +#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400 +// BIST (AppFunction = 05h) +#define CPU_EVENT_BIST_ERROR 0x08000500 + +//================================================================= +// CPU Feature events +// Execution cache (AppFunction = 21h) +// AGESA_CACHE_SIZE_REDUCED 2101 +// AGESA_CACHE_REGIONS_ACROSS_1MB 2102 +// AGESA_CACHE_REGIONS_ACROSS_4GB 2103 +// AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104 +// AGESA_CACHE_START_ADDRESS_LESS_D0000 2105 +// AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106 +// AGESA_DEALLOCATE_CACHE_REGIONS 2107 +#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100 +// Core Leveling (AppFunction = 22h) +#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200 +// HT Assist (AppFunction = 23h) +#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG 0x08002300 + +// CPU Build Configuration structures and definitions + +/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS +typedef struct { + IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address + IN UINT64 MsrData; ///< MTRR Settings +} AP_MTRR_SETTINGS; + +#define AMD_AP_MTRR_FIX64k_00000 0x00000250 +#define AMD_AP_MTRR_FIX16k_80000 0x00000258 +#define AMD_AP_MTRR_FIX16k_A0000 0x00000259 +#define AMD_AP_MTRR_FIX4k_C0000 0x00000268 +#define AMD_AP_MTRR_FIX4k_C8000 0x00000269 +#define AMD_AP_MTRR_FIX4k_D0000 0x0000026A +#define AMD_AP_MTRR_FIX4k_D8000 0x0000026B +#define AMD_AP_MTRR_FIX4k_E0000 0x0000026C +#define AMD_AP_MTRR_FIX4k_E8000 0x0000026D +#define AMD_AP_MTRR_FIX4k_F0000 0x0000026E +#define AMD_AP_MTRR_FIX4k_F8000 0x0000026F +#define CPU_LIST_TERMINAL 0xFFFFFFFF + +/************************************************************************ + * + * AGESA interface Call-Out function parameter structures + * + ***********************************************************************/ + +/// Parameters structure for interface call-out AgesaAllocateBuffer +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT32 BufferLength; ///< Size of buffer to allocate + IN UINT32 BufferHandle; ///< Identifier or name for the buffer + OUT VOID *BufferPointer; ///< location of the created buffer +} AGESA_BUFFER_PARAMS; + +/// Parameters structure for interface call-out AgesaRunCodeOnAp +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT32 FunctionNumber; ///< Index of the procedure to execute + IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use + IN UINT32 RelatedBlockLength; ///< Size of the related data block +} AP_EXE_PARAMS; + +/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT8 SocketId; ///< Address of SPD - socket ID + IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID + IN UINT8 DimmId; ///< Address of SPD - DIMM ID + IN OUT UINT8 *Buffer; ///< Location where to place the SPD content + IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference +} AGESA_READ_SPD_PARAMS; + +/// Buffer Handles +typedef enum { + AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function + AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data + AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table + AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID + AMD_ACPI_SLIT_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to SLIT function + AMD_SRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to SRAT function + AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to WHEA function + AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to S3 function + AMD_S3_NB_INFO_BUFFER_HANDLE ///< Assign 0x000D008 buffer handle to S3 NB device info +} AMD_BUFFER_HANDLE; +/************************************************************************ + * + * AGESA interface Call-Out function prototypes + * + ***********************************************************************/ + +VOID +AgesaDoReset ( + IN UINTN ResetType, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +AgesaAllocateBuffer ( + IN UINTN FcnData, + IN OUT AGESA_BUFFER_PARAMS *AllocParams + ); + +AGESA_STATUS +AgesaDeallocateBuffer ( + IN UINTN FcnData, + IN OUT AGESA_BUFFER_PARAMS *DeallocParams + ); + +AGESA_STATUS +AgesaLocateBuffer ( + IN UINTN FcnData, + IN OUT AGESA_BUFFER_PARAMS *LocateParams + ); + +AGESA_STATUS +AgesaReadSpd ( + IN UINTN FcnData, + IN OUT AGESA_READ_SPD_PARAMS *ReadSpd + ); + +AGESA_STATUS +AgesaReadSpdRecovery ( + IN UINTN FcnData, + IN OUT AGESA_READ_SPD_PARAMS *ReadSpd + ); + +AGESA_STATUS +AgesaRunFcnOnAp ( + IN UINTN ApicIdOfCore, + IN AP_EXE_PARAMS *LaunchApParams + ); + +AGESA_STATUS +AgesaHookBeforeDramInit ( + IN UINTN FcnData, + IN OUT MEM_DATA_STRUCT *MemData + ); + +AGESA_STATUS +AgesaHookBeforeDQSTraining ( + IN UINTN FcnData, + IN OUT MEM_DATA_STRUCT *MemData + ); + +AGESA_STATUS +AgesaHookBeforeExitSelfRefresh ( + IN UINTN FcnData, + IN OUT MEM_DATA_STRUCT *MemData + ); + +AGESA_STATUS +AgesaPcieSlotResetControl ( + IN UINTN FcnData, + IN PCIe_SLOT_RESET_INFO *ResetInfo + ); + +/************************************************************************ + * + * AGESA interface structure definition and function prototypes + * + ***********************************************************************/ + +/********************************************************************** + * Platform Configuration: The parameters in boot branch function + **********************************************************************/ + +/// The possible platform control flow settings. +typedef enum { + Nfcm, ///< Normal Flow Control Mode. + UmaDr, ///< UMA using Display Refresh flow control. + UmaIfcm, ///< UMA using Isochronous Flow Control. + Ifcm, ///< Isochronous Flow Control Mode (other than for UMA). + Iommu, ///< An IOMMU is in use in the system. + MaxControlFlow ///< Not a control flow mode, use for limit checking. +} PLATFORM_CONTROL_FLOW; + +/// Platform Deemphasis Levels. +/// +/// The deemphasis level is set for the receiver, based on link characterization. The DCV level is +/// set based on the level of the far transmitter. +typedef enum { + DeemphasisLevelNone, ///< No Deemphasis. + DeemphasisLevelMinus3, ///< Minus 3 db deemphasis. + DeemphasisLevelMinus6, ///< Minus 6 db deemphasis. + DeemphasisLevelMinus8, ///< Minus 8 db deemphasis. + DeemphasisLevelMinus11, ///< Minus 11 db deemphasis. + DeemphasisLevelMinus11pre8, ///< Minus 11, Minus 8 precursor db deemphasis. + DcvLevelNone = 16, ///< No DCV Deemphasis. + DcvLevelMinus2, ///< Minus 2 db DCV deemphasis. + DcvLevelMinus3, ///< Minus 3 db DCV deemphasis. + DcvLevelMinus5, ///< Minus 5 db DCV deemphasis. + DcvLevelMinus6, ///< Minus 6 db DCV deemphasis. + DcvLevelMinus7, ///< Minus 7 db DCV deemphasis. + DcvLevelMinus8, ///< Minus 8 db DCV deemphasis. + DcvLevelMinus9, ///< Minus 9 db DCV deemphasis. + DcvLevelMinus11, ///< Minus 11 db DCV deemphasis. + MaxPlatformDeemphasisLevel ///< Not a deemphasis level, use for limit checking. +} PLATFORM_DEEMPHASIS_LEVEL; + +/// Provide Deemphasis Levels for HT Links. +/// +/// For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will +/// be checked for a match. The item matches for a Socket, Link if the link frequency is +/// is in the inclusive range HighFreq:LoFreq. +/// AGESA does not set deemphasis in IO devices, only in processors. + +typedef struct { + // Match fields + IN UINT8 Socket; ///< One Socket on which this Link is located + IN UINT8 Link; ///< The Link on this Processor. + IN UINT8 LoFreq; ///< If the link is set to this frequency or greater, apply these levels, and + IN UINT8 HighFreq; ///< If the link is set to this frequency or less, apply these levels. + // Value fields + IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis; ///< The deemphasis level for this link + IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis; ///< The DCV, or far transmitter deemphasis level. +} CPU_HT_DEEMPHASIS_LEVEL; + +/// The possible platform power policy settings. +typedef enum { + Performance, ///< Optimize for performance. + BatteryLife, ///< Optimize for battery life. + MaxPowerPolicy ///< Not a power policy mode, use for limit checking. +} PLATFORM_POWER_POLICY; + +/// Platform performance settings for optimized settings. +/// Several configuration settings for the processor depend upon other parts and +/// general designer choices for the system. The determination of these data points +/// is not standard for all platforms, so the host environment needs to provide these +/// to specify how the system is to be configured. +typedef struct { + IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance. + ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE} + IN BOOLEAN UseHtAssist; ///< HyperTransport link traffic optimization. + ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST} + IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests. + ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH} + IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority. + ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY} + IN PLATFORM_POWER_POLICY PlatformPowerPolicy; ///< The platform's desired power policy + ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE} +} PERFORMANCE_PROFILE; + +/// Platform settings that describe the voltage regulator modules of the system. +/// Many power management settings are dependent upon the characteristics of the +/// on-board voltage regulator module (VRM). The host environment needs to provide +/// these to specify how the system is to be configured. +typedef struct { + IN UINT32 CurrentLimit; ///< Vrm Current Limit. + ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT} + IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold. + ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD} + IN UINT32 SlewRate; ///< Vrm Slew Rate. + ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE} + IN UINT32 AdditionalDelay; ///< Vrm Additional Delay. + ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY} + IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM. + ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE} + IN UINT32 InrushCurrentLimit; ///< Vrm Inrush Current Limit. + ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT} +} PLATFORM_VRM_CONFIGURATION; + + +/// Build Option/Configuration Boolean Structure. +typedef struct { + IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string + + //Build Option Area + IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT" + IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT" + IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT" + IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE" + IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE" + IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE" + IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING" + IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT" + IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT" + IN BOOLEAN OptionMultisocket; ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT" + IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES" + IN BOOLEAN OptionSrat; ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT" + IN BOOLEAN OptionSlit; ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT" + IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA" + IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI" + IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES" + IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR + + //Build Configuration Area + IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE} + IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE} + IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg; ///< Several configuration settings for the voltage regulator module. + IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform. + IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate. + IN PLATFORM_C1E_MODES CfgPlatformC1eMode; ///< Select the C1e Mode that will used. + IN UINT32 CfgPlatformC1eOpData; ///< An IO port or additional C1e setup data, depends on C1e mode. + IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used. + IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode. + IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified. + IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings. + IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links. + + IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile. + IN UINT32 CfgAmdPstateCapValue; ///< Amd pstate ceiling enabling deck + + IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT} + IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED} + IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE} + IN QUANDRANK_TYPE CfgMemoryQuadrankType; ///< Memory Quadrank Type. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE} + IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable. + IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable. + IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE} + IN BOOLEAN CfgLimitMemoryToBelow1Tb; ///< Limit memory address space to below 1TB + IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving. + IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving. + IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving. + IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. + IN POWER_DOWN_MODE CfgPowerDownMode; ///< Power Down Mode. + IN BOOLEAN CfgOnlineSpare; ///< Online Spare. + IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. + IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle. + IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select. + IN MEMORY_BUS_SPEED CfgMemoryClockSelect; ///< Memory Clock Select. + IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL} + IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM} + IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE} + IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON} + IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature. + IN BOOLEAN CfgEccRedirection; ///< ECC Redirection. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION} + IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE} + IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE} + IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE} + IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE} + IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE} + IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD} + IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE} + IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS} + IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment + IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore + IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent + IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt + ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST} + IN UMA_MODE CfgUmaMode; ///< Uma Mode + IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16] + IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support + IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment + IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope + IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name. + IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. + IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio + IN UINT8 CfgAbmSupport; ///< Abm Support + IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate + ///< Build-time customizable only - @BldCfgItem{BLDCFG_DYNAMIC_REFRESH_RATE} + IN UINT8 CfgLcdBackLightControl; ///< LCD Backlight Control + IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address + ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS} + + IN BOOLEAN Reserved; ///< reserved... +} BUILD_OPT_CFG; + +/// A structure containing platform specific operational characteristics. This +/// structure is initially populated by the initializer with a copy of the same +/// structure that was created at build time using the build configuration controls. +typedef struct _PLATFORM_CONFIGURATION { + IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor. + IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links. + ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}. + ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples". + IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor. + ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE} + IN PLATFORM_C1E_MODES C1eMode; ///< Specifies the method of C1e enablement - Disabled, HW, or message based. + ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE} + IN UINT32 C1ePlatformData; ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform. + ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA} + IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6. + ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE} + IN UINT32 CStatePlatformData; ///< If CStateMode is C6, specifies a block of 8 free I/O ports to be used for + ///< placing the CPU in C6. + ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA} + IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated. + IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated. + IN BOOLEAN UserOptionSrat; ///< When set to TRUE, the SRAT data table is generated. + IN BOOLEAN UserOptionSlit; ///< When set to TRUE, the SLIT data table is generated. + IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated. + IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts. + IN BOOLEAN ForcePstateIndependent; ///< P-State _PSD independence or dependence. + IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system + ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS} + IN PLATFORM_VRM_CONFIGURATION VrmProperties; ///< Several configuration settings for the voltage regulator module. + IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope + IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name. + IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. +} PLATFORM_CONFIGURATION; + + +/// P-state structure for each state +typedef struct { + IN OUT UINT32 PStateEnable; ///< Pstate enable + IN OUT UINT32 CoreFreq; ///< MHz + IN OUT UINT32 Power; ///< milliWatts + IN OUT UINT32 IddValue; ///< Current value field + IN OUT UINT32 IddDiv; ///< Current divisor field +} S_PSTATE_VALUES; + +/// P-state structure for each core +typedef struct { + IN OUT UINT8 PStateMaxValue; ///< Max p-state number in this core + IN OUT UINT8 HtcPstateLimit; ///< Htc limit + IN OUT UINT8 HtcCapable; ///< Htc capable + IN OUT UINT8 Reserved; ///< Reserved + IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc +} S_PSTATE; + +/// P-state structure for each node +typedef struct { + IN UINT8 SetPState0; ///< If value = 0x55 (Don't set PState0) + IN UINT8 TotalCoresInNode; ///< core number per node + IN UINT16 PStateLevelingSizeOfBytes; ///< Size + IN BOOLEAN OnlyOneEnabledPState; ///< Only P0 + IN UINT8 InitStruct; ///< Init struc + IN BOOLEAN AllCpusHaveIdenticalPStates; ///< Have Identical p state + IN UINT8 CreateAcpiTables; ///< Create table flag + IN UINT8 SocketNumber; ///< Physical socket number of this socket + IN UINT8 Reserved[3]; ///< Reserved. + IN OUT S_PSTATE PStateCoreStruct[1]; ///< P state core struc +} PSTATE_LEVELING; + +/// P-state structure for whole system +typedef struct { + IN OUT UINT32 TotalSocketInSystem; ///< Total node number in system + IN OUT UINT32 SizeOfBytes; ///< Structure size + IN OUT PSTATE_LEVELING PStateLevelingStruc[1]; ///< P state level structure +} S_CPU_AMD_PSTATE; + +/********************************************************************** + * Structures for: AmdInitLate + **********************************************************************/ +#define PROC_VERSION_LENGTH 0x3 +#define MAX_DIMMS_PER_SOCKET 16 + +/* Interface Parameter Structures */ +/// DMI Type4 - Processor ID +typedef struct { + OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID + OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID +} TYPE4_PROC_ID; + +/// DMI Type 4 - Processor information +typedef struct { + OUT UINT8 T4ProcType; ///< CPU Type + OUT UINT8 T4ProcFamily; ///< Family 1 + OUT TYPE4_PROC_ID T4ProcId; ///< Id + OUT UINT8 T4Voltage; ///< Voltage + OUT UINT16 T4ExternalClock; ///< External clock + OUT UINT16 T4MaxSpeed; ///< Max speed + OUT UINT16 T4CurrentSpeed; ///< Current speed + OUT UINT8 T4Status; ///< Status + OUT UINT8 T4ProcUpgrade; ///< Up grade + OUT UINT8 T4CoreCount; ///< Core count + OUT UINT8 T4CoreEnabled; ///< Core Enable + OUT UINT8 T4ThreadCount; ///< Thread count + OUT UINT16 T4ProcCharacteristics; ///< Characteristics + OUT UINT16 T4ProcFamily2; ///< Family 2 + OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version +} TYPE4_DMI_INFO; + +/// DMI Type 7 - Cache information +typedef struct _TYPE7_DMI_INFO { + OUT UINT16 T7CacheCfg; ///< Cache cfg + OUT UINT16 T7MaxCacheSize; ///< Max size + OUT UINT16 T7InstallSize; ///< Install size + OUT UINT16 T7SupportedSramType; ///< Supported Sram Type + OUT UINT16 T7CurrentSramType; ///< Current type + OUT UINT8 T7CacheSpeed; ///< Speed + OUT UINT8 T7ErrorCorrectionType; ///< ECC type + OUT UINT8 T7SystemCacheType; ///< Cache type + OUT UINT8 T7Associativity; ///< Associativity +} TYPE7_DMI_INFO; + +/// DMI Type 16 offset 04h - Location +typedef enum { + OtherLocation = 0x01, ///< Assign 01 to Other + UnknownLocation, ///< Assign 02 to Unknown + SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard + IsaAddonCard, ///< Assign 04 to ISA add-on card + EisaAddonCard, ///< Assign 05 to EISA add-on card + PciAddonCard, ///< Assign 06 to PCI add-on card + McaAddonCard, ///< Assign 07 to MCA add-on card + PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card + ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card + NuBus, ///< Assign 0A to NuBus + Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card + Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card + Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card + Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card +} DMI_T16_LOCATION; + +/// DMI Type 16 offset 05h - Memory Error Correction +typedef enum { + OtherUse = 0x01, ///< Assign 01 to Other + UnknownUse, ///< Assign 02 to Unknown + SystemMemory, ///< Assign 03 to system memory + VideoMemory, ///< Assign 04 to video memory + FlashMemory, ///< Assign 05 to flash memory + NonvolatileRam, ///< Assign 06 to non-volatile RAM + CacheMemory ///< Assign 07 to cache memory +} DMI_T16_USE; + +/// DMI Type 16 offset 07h - Maximum Capacity +typedef enum { + Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other + Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown + Dmi16NoneErrCorrection, ///< Assign 03 to None + Dmi16Parity, ///< Assign 04 to parity + Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC + Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC + Dmi16Crc ///< Assign 07 to CRC +} DMI_T16_ERROR_CORRECTION; + +/// DMI Type 16 - Physical Memory Array +typedef struct { + OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array, + ///< whether on the system board or an add-in board. + OUT DMI_T16_USE Use; ///< Identifies the function for which the array + ///< is used. + OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or + ///< detection method supported by this memory array. + OUT UINT32 MaximumCapacity; ///< The maximum memory capacity, in kilobytes, + ///< for the array. + OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available + ///< for memory devices in this array. +} TYPE16_DMI_INFO; + +/// DMI Type 17 offset 0Eh - Form Factor +typedef enum { + OtherFormFactor = 0x01, ///< Assign 01 to Other + UnknowFormFactor, ///< Assign 02 to Unknown + SimmFormFactor, ///< Assign 03 to SIMM + SipFormFactor, ///< Assign 04 to SIP + ChipFormFactor, ///< Assign 05 to Chip + DipFormFactor, ///< Assign 06 to DIP + ZipFormFactor, ///< Assign 07 to ZIP + ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card + DimmFormFactorFormFactor, ///< Assign 09 to DIMM + TsopFormFactor, ///< Assign 10 to TSOP + RowOfChipsFormFactor, ///< Assign 11 to Row of chips + RimmFormFactor, ///< Assign 12 to RIMM + SodimmFormFactor, ///< Assign 13 to SODIMM + SrimmFormFactor, ///< Assign 14 to SRIMM + FbDimmFormFactor ///< Assign 15 to FB-DIMM +} DMI_T17_FORM_FACTOR; + +/// DMI Type 17 offset 12h - Memory Type +typedef enum { + OtherMemType = 0x01, ///< Assign 01 to Other + UnknownMemType, ///< Assign 02 to Unknown + DramMemType, ///< Assign 03 to DRAM + EdramMemType, ///< Assign 04 to EDRAM + VramMemType, ///< Assign 05 to VRAM + SramMemType, ///< Assign 06 to SRAM + RamMemType, ///< Assign 07 to RAM + RomMemType, ///< Assign 08 to ROM + FlashMemType, ///< Assign 09 to Flash + EepromMemType, ///< Assign 10 to EEPROM + FepromMemType, ///< Assign 11 to FEPROM + EpromMemType, ///< Assign 12 to EPROM + CdramMemType, ///< Assign 13 to CDRAM + ThreeDramMemType, ///< Assign 14 to 3DRAM + SdramMemType, ///< Assign 15 to SDRAM + SgramMemType, ///< Assign 16 to SGRAM + RdramMemType, ///< Assign 17 to RDRAM + DdrMemType, ///< Assign 18 to DDR + Ddr2MemType, ///< Assign 19 to DDR2 + Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM + Ddr3MemType = 0x18, ///< Assign 24 to DDR3 + Fbd2MemType ///< Assign 25 to FBD2 +} DMI_T17_MEMORY_TYPE; + +/// DMI Type 17 offset 13h - Type Detail +typedef struct { + OUT UINT16 Reserved1:1; ///< Reserved + OUT UINT16 Other:1; ///< Other + OUT UINT16 Unknown:1; ///< Unknown + OUT UINT16 FastPaged:1; ///< Fast-Paged + OUT UINT16 StaticColumn:1; ///< Static column + OUT UINT16 PseudoStatic:1; ///< Pseudo-static + OUT UINT16 Rambus:1; ///< RAMBUS + OUT UINT16 Synchronous:1; ///< Synchronous + OUT UINT16 Cmos:1; ///< CMOS + OUT UINT16 Edo:1; ///< EDO + OUT UINT16 WindowDram:1; ///< Window DRAM + OUT UINT16 CacheDram:1; ///< Cache Dram + OUT UINT16 NonVolatile:1; ///< Non-volatile + OUT UINT16 Reserved2:3; ///< Reserved +} DMI_T17_TYPE_DETAIL; + +/// DMI Type 17 - Memory Device +typedef struct { + OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. + OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. + OUT UINT16 MemorySize; ///< The size of the memory device. + OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. + OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of + ///< Memory Devices that must be populated with all devices of + ///< the same type and size, and the set to which this device belongs. + OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. + OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. + OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. + OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type + OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). + OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. + OUT CHAR8 SerialNumber[9]; ///< Serial Number. + OUT CHAR8 PartNumber[19]; ///< Part Number. + OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. +} TYPE17_DMI_INFO; + +/// Memory DMI Type 17 and 20 - for memory use +typedef struct { + OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. + OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. + OUT UINT16 MemorySize; ///< The size of the memory device. + OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. + OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. + OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. + OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). + OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. + OUT UINT8 SerialNumber[4]; ///< Serial Number. + OUT UINT8 PartNumber[18]; ///< Part Number. + OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. + OUT UINT8 Socket:3; ///< Socket ID + OUT UINT8 Channel:2; ///< Channel ID + OUT UINT8 Dimm:2; ///< DIMM ID + OUT UINT8 DimmPresent:1; ///< Dimm Present + OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range + ///< of memory mapped to the referenced Memory Device. + OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with + ///< the Memory Device structure to which this address + ///< range is mapped. +} MEM_DMI_INFO; + +/// DMI Type 19 - Memory Array Mapped Address +typedef struct { + OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, + ///< of a range of memory mapped to the + ///< specified physical memory array. + OUT UINT32 EndingAddr; ///< The physical ending address of the + ///< last kilobyte of a range of addresses + ///< mapped to the specified physical memory array. + OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated + ///< with the physical memory array to which this + ///< address range is mapped. + OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that + ///< form a single row of memory for the address + ///< partition defined by this structure. +} TYPE19_DMI_INFO; + +///DMI Type 20 - Memory Device Mapped Address +typedef struct { + OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range + ///< of memory mapped to the referenced Memory Device. + OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with + ///< the Memory Device structure to which this address + ///< range is mapped. + OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with + ///< the Memory Device structure to which this address + ///< range is mapped. + OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated + ///< with the Memory Array Mapped Address structure to + ///< which this device address range is mapped. + OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory + ///< Device in a row of the address partition. + OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in + ///< an interleave. + OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the + ///< referenced Memory Device that are accessed in a + ///< single interleaved transfer. +} TYPE20_DMI_INFO; + +/// Collection of pointers to the DMI records +typedef struct { + OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc + OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1 + OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2 + OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3 + OUT TYPE16_DMI_INFO T16; ///< Type 16 struc + OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc + OUT TYPE19_DMI_INFO T19; ///< Type 19 struc + OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc +} DMI_INFO; + +AGESA_STATUS +CreateAcpiTables ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SsdtPtr + ); + + +/********************************************************************** + * Interface call: AllocateExecutionCache + **********************************************************************/ +#define MAX_CACHE_REGIONS 3 + +/// AllocateExecutionCache sub param structure for cached memory region +typedef struct { + IN OUT UINT32 ExeCacheStartAddr; ///< Start address + IN OUT UINT32 ExeCacheSize; ///< Size +} EXECUTION_CACHE_REGION; + +/********************************************************************** + * Interface call: AmdGetAvailableExeCacheSize + **********************************************************************/ +/// Get available Cache remain +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + OUT UINT32 AvailableExeCacheSize; ///< Remain size +} AMD_GET_EXE_SIZE_PARAMS; + +AGESA_STATUS +AmdGetAvailableExeCacheSize ( + IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams + ); + +/// Selection type for core leveling +typedef enum { + CORE_LEVEL_LOWEST, ///< Level to lowest common denominator + CORE_LEVEL_TWO, ///< Level to 2 cores + CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8 + CORE_LEVEL_NONE, ///< Do no leveling + CORE_LEVEL_ONE, ///< Level to 1 core + CORE_LEVEL_THREE, ///< Level to 3 cores + CORE_LEVEL_FOUR, ///< Level to 4 cores + CORE_LEVEL_FIVE, ///< Level to 5 cores + CORE_LEVEL_SIX, ///< Level to 6 cores + CORE_LEVEL_SEVEN, ///< Level to 7 cores + CORE_LEVEL_EIGHT, ///< Level to 8 cores + CORE_LEVEL_NINE, ///< Level to 9 cores + CORE_LEVEL_TEN, ///< Level to 10 cores + CORE_LEVEL_ELEVEN, ///< Level to 11 cores + CORE_LEVEL_TWELVE, ///< Level to 12 cores + CORE_LEVEL_THIRTEEN, ///< Level to 13 cores + CORE_LEVEL_FOURTEEN, ///< Level to 14 cores + CORE_LEVEL_FIFTEEN, ///< Level to 15 cores + CoreLevelModeMax ///< Used for bounds checking +} CORE_LEVELING_TYPE; + + + + + +/************************************************************************ + * + * AGESA Basic Level interface structure definition and function prototypes + * + ***********************************************************************/ + +/********************************************************************** + * Interface call: AmdCreateStruct + **********************************************************************/ +AGESA_STATUS +AmdCreateStruct ( + IN OUT AMD_INTERFACE_PARAMS *InterfaceParams + ); + +/********************************************************************** + * Interface call: AmdReleaseStruct + **********************************************************************/ +AGESA_STATUS +AmdReleaseStruct ( + IN OUT AMD_INTERFACE_PARAMS *InterfaceParams + ); + +/********************************************************************** + * Interface call: AmdInitReset + **********************************************************************/ +/// AmdInitReset param structure +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region + IN AMD_HT_RESET_INTERFACE HtConfig; ///< The interface for Ht Recovery +} AMD_RESET_PARAMS; + +AGESA_STATUS +AmdInitReset ( + IN OUT AMD_RESET_PARAMS *ResetParams + ); + + +/********************************************************************** + * Interface call: AmdInitEarly + **********************************************************************/ +/// InitEarly param structure +/// +/// Provide defaults or customizations to each service performed in AmdInitEarly. +/// +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + IN AMD_HT_INTERFACE HtConfig; ///< HyperTransport Interface + IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration +} AMD_EARLY_PARAMS; + +AGESA_STATUS +AmdInitEarly ( + IN OUT AMD_EARLY_PARAMS *EarlyParams + ); + + +/********************************************************************** + * Interface call: AmdInitPost + **********************************************************************/ +/// AmdInitPost param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param +} AMD_POST_PARAMS; + +AGESA_STATUS +AmdInitPost ( + IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param + ); + + +/********************************************************************** + * Interface call: AmdInitEnv + **********************************************************************/ +/// AmdInitEnv param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. +} AMD_ENV_PARAMS; + +AGESA_STATUS +AmdInitEnv ( + IN OUT AMD_ENV_PARAMS *EnvParams + ); + + +/********************************************************************** + * Interface call: AmdInitMid + **********************************************************************/ +/// AmdInitMid param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. +} AMD_MID_PARAMS; + +AGESA_STATUS +AmdInitMid ( + IN OUT AMD_MID_PARAMS *MidParams + ); + + +/********************************************************************** + * Interface call: AmdInitLate + **********************************************************************/ +/// AmdInitLate param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + OUT DMI_INFO *DmiTable; ///< DMI Interface + OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table + OUT VOID *AcpiSrat; ///< SRAT Table + OUT VOID *AcpiSlit; ///< SLIT Table + OUT VOID *AcpiWheaMce; ///< WHEA MCE Table + OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table +} AMD_LATE_PARAMS; + +AGESA_STATUS +AmdInitLate ( + IN OUT AMD_LATE_PARAMS *LateParams + ); + +/********************************************************************** + * Interface call: AmdInitRecovery + **********************************************************************/ +/// CPU Recovery Parameters +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. +} AMD_CPU_RECOVERY_PARAMS; + +/// AmdInitRecovery param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param + IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3 + IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init. +} AMD_RECOVERY_PARAMS; + +AGESA_STATUS +AmdInitRecovery ( + IN OUT AMD_RECOVERY_PARAMS *RecoveryParams + ); + +/********************************************************************** + * Interface call: AmdInitResume + **********************************************************************/ +/// AmdInitResume param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics + IN AMD_S3_PARAMS S3DataBlock; ///< Save state data +} AMD_RESUME_PARAMS; + +AGESA_STATUS +AmdInitResume ( + IN AMD_RESUME_PARAMS *ResumeParams + ); + + +/********************************************************************** + * Interface call: AmdS3LateRestore + **********************************************************************/ +/// AmdS3LateRestore param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + IN AMD_S3_PARAMS S3DataBlock; ///< Save state data +} AMD_S3LATE_PARAMS; + +AGESA_STATUS +AmdS3LateRestore ( + IN OUT AMD_S3LATE_PARAMS *S3LateParams + ); + + +/********************************************************************** + * Interface call: AmdS3Save + **********************************************************************/ +/// AmdS3Save param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + OUT AMD_S3_PARAMS S3DataBlock; ///< Standard header +} AMD_S3SAVE_PARAMS; + +AGESA_STATUS +AmdS3Save ( + IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams + ); + + +/********************************************************************** + * Interface call: AmdLateRunApTask + **********************************************************************/ +/** + * Entry point for AP tasking. + */ +AGESA_STATUS +AmdLateRunApTask ( + IN AP_EXE_PARAMS *AmdApExeParams +); + +// +// General Services API +// + +/********************************************************************** + * Interface service call: AmdGetApicId + **********************************************************************/ +/// Request the APIC ID of a particular core. + +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT8 Socket; ///< The Core's Socket. + IN UINT8 Core; ///< The Core id. + OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid. + OUT UINT8 ApicAddress; ///< The Core's APIC ID. +} AMD_APIC_PARAMS; + +/** + * Get a specified Core's APIC ID. + */ +AGESA_STATUS +AmdGetApicId ( + IN OUT AMD_APIC_PARAMS *AmdParamApic +); + +/********************************************************************** + * Interface service call: AmdGetPciAddress + **********************************************************************/ +/// Request the PCI Address of a Processor Module (that is, its Northbridge) + +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT8 Socket; ///< The Processor's socket + IN UINT8 Module; ///< The Module in that Processor + OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid. + OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0) +} AMD_GET_PCI_PARAMS; + +/** + * Get Processor Module's PCI Config Space address. + */ +AGESA_STATUS +AmdGetPciAddress ( + IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci +); + +/********************************************************************** + * Interface service call: AmdIdentifyCore + **********************************************************************/ +/// Request the identity (Socket, Module, Core) of the current Processor Core + +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + OUT UINT8 Socket; ///< The current Core's Socket + OUT UINT8 Module; ///< The current Core's Processor Module + OUT UINT8 Core; ///< The current Core's core id. +} AMD_IDENTIFY_PARAMS; + +/** + * "Who am I" for the current running core. + */ +AGESA_STATUS +AmdIdentifyCore ( + IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify +); + +/********************************************************************** + * Interface service call: AmdReadEventLog + **********************************************************************/ +/// An Event Log Entry. +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS. + OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event". + OUT UINT32 DataParam1; ///< Data specific to the Event. + OUT UINT32 DataParam2; ///< Data specific to the Event. + OUT UINT32 DataParam3; ///< Data specific to the Event. + OUT UINT32 DataParam4; ///< Data specific to the Event. +} EVENT_PARAMS; + +/** + * Read an Event from the Event Log. + */ +AGESA_STATUS +AmdReadEventLog ( + IN EVENT_PARAMS *Event +); + +/********************************************************************** + * Interface service call: AmdIdentifyDimm + **********************************************************************/ +/// Request the identity of dimm from system address + +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification. + OUT UINT8 SocketId; ///< The socket on which the targeted address locates. + OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates. + OUT UINT8 DimmId; ///< The dimm on which the targeted address locates. +} AMD_IDENTIFY_DIMM; + +/** + * Get the dimm identification for the address. + */ +AGESA_STATUS +AmdIdentifyDimm ( + IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify +); + +/// Data structure for the Mapping Item between Unified ID for IDS Setup Option +/// and the option value. +/// +typedef struct { + IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option. + OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option. +} IDS_NV_ITEM; + +/// Data Structure for IDS CallOut Function +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table + IN OUT UINTN Reserved; ///< reserved +} IDS_CALLOUT_STRUCT; + +AGESA_STATUS +AmdIdsRunApTaskLate ( + IN AP_EXE_PARAMS *AmdApExeParams + ); + + +#define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored +#define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure + +/// AGESA IDS NV ID Definitions +typedef enum { + AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id + + AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching + + AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated + AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST + + AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0004 Enable or disable Channel Interleave + + AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0005 Enable or disable a write to dram with corrected data + AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0006 Set the rate of background scrubbing for DRAM + AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x0007 Set the rate of background scrubbing for the DCache. + AGESA_IDS_NV_L2_SCRUB, ///< 0x0008 Set the rate of background scrubbing for the L2 cache + AGESA_IDS_NV_L3_SCRUB, ///< 0x0009 Set the rate of background scrubbing for the L3 cache + AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000A Enable or disable the sync flood on un-correctable ECC error + AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000B Set ECC symbol size + + AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x000C Enable or disable all memory clocks enable + AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x000D Set the Ganged mode + AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x000E Set the DRAM Burst Length 32 + AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x000F Enable or disable Memory power down mode + AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0010 Set the Memory power down mode + AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0011 Enable or disable DLLShutdown + + AGESA_IDS_NV_PROBEFILTER, ///< 0x0012 Enable or Disable ProbeFilter + + AGESA_IDS_NV_HDTOUT, ///< 0x0013 Enable or disable HDTOUT feature + + AGESA_IDS_NV_HTLINKSOCKET, ///< 0x0014 HT Link Socket + AGESA_IDS_NV_HTLINKPORT, ///< 0x0015 HT Link Port + AGESA_IDS_NV_HTLINKFREQ, ///< 0x0016 HT Link Frequency + AGESA_IDS_NV_HTLINKWIDTHIN, ///< 0x0017 HT Link In Width + AGESA_IDS_NV_HTLINKWIDTHOUT, ///< 0x0018 HT Link Out Width + + AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x0019 Enable or disable GNB HD Audio + AGESA_IDS_EXT_ID_END, ///< 0x001A specify the end of external NV ID +} IDS_EX_NV_ID; + + +#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1) + +#endif // _AGESA_H_ diff --git a/src/vendorcode/amd/agesa/f10/AMD.h b/src/vendorcode/amd/agesa/f10/AMD.h new file mode 100755 index 0000000..81a97ac --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/AMD.h @@ -0,0 +1,478 @@ +/** + * @file + * + * Agesa structures and definitions + * + * Contains AMD AGESA core interface + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e \$Revision: 7668 $ @e \$Date: 2008-08-25 18:59:15 -0700 (Mon, 25 Aug 2008) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#ifndef _AMD_H_ +#define _AMD_H_ + +#define AGESA_REVISION "Arch2008" +#define AGESA_ID "AGESA" + +#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) +#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) +// +// +// AGESA Types and Definitions +// +// +#define LAST_ENTRY 0xFFFFFFFF +#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') +#define IOCF8 0xCF8 +#define IOCFC 0xCFC + +/// The return status for all AGESA public services. +/// +/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK +/// will have log entries with more detail. +/// +typedef enum { + AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged. + AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested. + ///< Not logged. + AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided. + ///< Example, memory address not installed, heap buffer handle not found. + ///< Not Logged. + // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available. + AGESA_ALERT, ///< An observed condition, but no loss of function. + ///< See log. Example, HT CRC. + AGESA_WARNING, ///< Possible or minor loss of function. See Log. + AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log. + AGESA_CRITICAL, ///< Continue boot only to notify user. See Log. + AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems + ///< may not be able to reliably produce log events. + AgesaStatusMax ///< Not a status, for limit checking. +} AGESA_STATUS; + +/// For checking whether a status is at or above the mandatory log level. +#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT + +/** + * Callout method to the host environment. + * + * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment. + * + * @param[in] Function The specific callout function being invoked. + * @param[in] FcnData Function specific data item. + * @param[in,out] ConfigPtr Reference to Callout params. + */ +typedef AGESA_STATUS (*CALLOUT_ENTRY) ( + IN UINT32 Function, + IN UINTN FcnData, + IN OUT VOID *ConfigPtr + ); + +typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + +/// AGESA struct name +typedef enum { + // AGESA BASIC FUNCTIONS + AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle + AMD_CREATE_STRUCT, ///< AmdCreateStruct handle + AMD_INIT_EARLY, ///< AmdInitEarly entry point handle + AMD_INIT_ENV, ///< AmdInitEnv entry point handle + AMD_INIT_LATE, ///< AmdInitLate entry point handle + AMD_INIT_MID, ///< AmdInitMid entry point handle + AMD_INIT_POST, ///< AmdInitPost entry point handle + AMD_INIT_RESET, ///< AmdInitReset entry point handle + AMD_INIT_RESUME, ///< AmdInitResume entry point handle + AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle + AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle + AMD_S3_SAVE, ///< AmdS3Save entry point handle + AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle + AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle + AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle + AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle + AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle + AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle +} AGESA_STRUCT_NAME; + + /* ResetType constant values */ +#define WARM_RESET_WHENEVER 1 +#define COLD_RESET_WHENEVER 2 +#define WARM_RESET_IMMEDIATELY 3 +#define COLD_RESET_IMMEDIATELY 4 + + +// AGESA Structures + +/// The standard header for all AGESA services. +/// For internal AGESA naming conventions, see @ref amdconfigparamname . +typedef struct { + IN UINT32 ImageBasePtr; ///< The AGESA Image base address. + IN UINT32 Func; ///< The service desired + IN UINT32 AltImageBasePtr; ///< Alternate Image location + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + IN UINT8 HeapStatus; ///< For heap status from boot time slide. + IN UINT64 HeapBasePtr; ///< Location of the heap + IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use. +} AMD_CONFIG_PARAMS; + + +/// Create Struct Interface. +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init + IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation + IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only. + IN OUT VOID *NewStructPtr; ///< The struct for the service. + ///< The struct to init for ByHost allocation, + ///< the initialized struct on return. +} AMD_INTERFACE_PARAMS; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +/// AGESA Binary module header structure +typedef struct { + IN UINT32 Signature; ///< Binary Signature + IN CHAR8 CreatorID[8]; ///< 8 characters ID + IN CHAR8 Version[12]; ///< 12 characters version + IN UINT32 ModuleInfoOffset; ///< Offset of module + IN UINT32 EntryPointAddress; ///< Entry address + IN UINT32 ImageBase; ///< Image base + IN UINT32 RelocTableOffset; ///< Relocate Table offset + IN UINT32 ImageSize; ///< Size + IN UINT16 Checksum; ///< Checksum + IN UINT8 ImageType; ///< Type + IN UINT8 V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN UINT32 ModuleHeaderSignature; ///< Module signature + IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID + IN CHAR8 ModuleVersion[12]; ///< 12 characters version + IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link +} AMD_MODULE_HEADER; + +// AMD_CODE_HEADER Signatures. +#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '} +#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'} +#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'} + +/// AGESA_CODE_SIGNATURE +typedef struct { + IN CHAR8 Signature[8]; ///< code header Signature + IN CHAR8 ComponentName[8]; ///< 8 character name of the code module + IN CHAR8 Version[12]; ///< 12 character version string + IN CHAR8 TerminatorNull; ///< null terminated string + IN CHAR8 VerReserved[7]; ///< reserved space +} AMD_CODE_HEADER; + +/// Extended PCI address format +typedef struct { + IN OUT UINT32 Register:12; ///< Register offset + IN OUT UINT32 Function:3; ///< Function number + IN OUT UINT32 Device:5; ///< Device number + IN OUT UINT32 Bus:8; ///< Bus number + IN OUT UINT32 Segment:4; ///< Segment +} EXT_PCI_ADDR; + +/// Union type for PCI address +typedef union _PCI_ADDR { + IN UINT32 AddressValue; ///< Formal address + IN EXT_PCI_ADDR Address; ///< Extended address +} PCI_ADDR; + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function(3-bits) +// 11:00 Offset (12-bits) + +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ + (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off))) +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct { + OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX + OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX + OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX + OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX +} CPUID_DATA; + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks + HT_FREQUENCY_MAX ///< Limit check. +} HT_FREQUENCIES; +// The minimum HT3 frequency +#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M + +#ifndef BIT0 + #define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 + #define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 + #define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 + #define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 + #define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 + #define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 + #define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 + #define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 + #define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 + #define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 + #define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 + #define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 + #define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 + #define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 + #define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 + #define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 + #define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 + #define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 + #define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 + #define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 + #define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 + #define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 + #define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 + #define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 + #define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 + #define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 + #define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 + #define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 + #define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 + #define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 + #define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 + #define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 + #define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 + #define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 + #define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 + #define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 + #define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 + #define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 + #define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 + #define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 + #define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 + #define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 + #define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 + #define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 + #define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 + #define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 + #define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 + #define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 + #define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 + #define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 + #define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 + #define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 + #define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 + #define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 + #define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 + #define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 + #define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 + #define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 + #define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 + #define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 + #define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 + #define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 + #define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 + #define BIT63 0x8000000000000000ull +#endif + +#endif // _AMD_H_ diff --git a/src/vendorcode/amd/agesa/f10/Dispatcher.h b/src/vendorcode/amd/agesa/f10/Dispatcher.h new file mode 100755 index 0000000..ae4caa1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Dispatcher.h @@ -0,0 +1,51 @@ +/** + * @file + * + * AMD Pushhigh Interface + * + * Contains interface to Pushhigh entry + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Legacy + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + */ + +#ifndef _DISPATCHER_H_ +#define _DISPATCHER_H_ + +// AGESA function prototypes +AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr ); +AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr ); + +#endif // _DISPATCHER_H_ diff --git a/src/vendorcode/amd/agesa/f10/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f10/Include/AdvancedApi.h new file mode 100755 index 0000000..70211fc --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Include/AdvancedApi.h @@ -0,0 +1,155 @@ +/** + * @file + * + * Advanced API Interface for HT, Memory and CPU + * + * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as + * would be required by the basic interface implementations. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + + +#ifndef _ADVANCED_API_H_ +#define _ADVANCED_API_H_ + +/*---------------------------------------------------------------------------- + * HT FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +/** + * A constructor for the HyperTransport input structure. + * + * Sets inputs to valid, basic level, defaults. + * + * @param[in] StdHeader Opaque handle to standard config header + * @param[in] AmdHtInterface HT Interface structure to initialize. + * + * @retval AGESA_SUCCESS Constructors are not allowed to fail +*/ +AGESA_STATUS +AmdHtInterfaceConstructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_HT_INTERFACE *AmdHtInterface + ); + +/** + * The top level external interface for Hypertransport Initialization. + * + * Create our initial internal state, initialize the coherent fabric, + * initialize the non-coherent chains, and perform any required fabric tuning or + * optimization. + * + * @param[in] StdHeader Opaque handle to standard config header + * @param[in] PlatformConfiguration The platform configuration options. + * @param[in] AmdHtInterface HT Interface structure. + * + * @retval AGESA_SUCCESS Only information events logged. + * @retval AGESA_ALERT Sync Flood or CRC error logged. + * @retval AGESA_WARNING Example: expected capability not found + * @retval AGESA_ERROR logged events indicating some devices may not be available + * @retval AGESA_FATAL Mixed Family or MP capability mismatch + * + */ +AGESA_STATUS +AmdHtInitialize ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfiguration, + IN AMD_HT_INTERFACE *AmdHtInterface + ); + +/*---------------------------------------------------------------------------- + * HT Recovery FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +/** + * A constructor for the HyperTransport input structure. + * + */ +AGESA_STATUS +AmdHtResetConstructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface + ); + +/** + * Initialize HT at Reset for both Normal and Recovery. + * + */ +AGESA_STATUS +AmdHtInitReset ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface + ); + +/** + * Initialize the Node and Socket maps for an AP Core. + * + */ +AGESA_STATUS +AmdHtInitRecovery ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +///---------------------------------------------------------------------------- +/// MEMORY FUNCTIONS PROTOTYPE +/// +///---------------------------------------------------------------------------- + +AGESA_STATUS +AmdMemRecovery ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +AGESA_STATUS +AmdMemAuto ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +AmdMemInitDataStructDef ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT PLATFORM_CONFIGURATION *PlatFormConfig + ); + +VOID +memDefRet ( + IN VOID + ); + +#endif // _ADVANCED_API_H_ diff --git a/src/vendorcode/amd/agesa/f10/Include/CommonReturns.h b/src/vendorcode/amd/agesa/f10/Include/CommonReturns.h new file mode 100755 index 0000000..ee168a7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Include/CommonReturns.h @@ -0,0 +1,130 @@ +/** + * @file + * + * Common Return routines. + * + * Routines which do nothing, returning a result (preferably some version of zero) which + * is consistent with "do nothing" or "default". Useful for function pointer tables. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + */ +/* +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* + *************************************************************************** +*/ + +#ifndef _COMMON_RETURNS_H_ +#define _COMMON_RETURNS_H_ + +/** +* Return False. +* +* @retval FALSE Default case, no special action +*/ +BOOLEAN +CommonReturnFalse ( + IN VOID +); + +/** + * Return (UINT8)zero. + * + * + * @retval zero None, or only case zero. + */ +UINT8 +CommonReturnZero8 ( + IN VOID +); + +/** + * Return (UINT32)zero. + * + * + * @retval zero None, or only case zero. + */ +UINT32 +CommonReturnZero32 ( + IN VOID +); + +/** + * Return (UINT64)zero. + * + * + * @retval zero None, or only case zero. + */ +UINT64 +CommonReturnZero64 ( + IN VOID +); + +/** + * Return NULL + * + * @retval NULL pointer to nothing + */ +VOID * +CommonReturnNULL ( + IN VOID +); + +/** +* Return AGESA_SUCCESS. +* +* @retval AGESA_SUCCESS Success. +*/ +AGESA_STATUS +CommonReturnAgesaSuccess ( + IN VOID +); + +/** + * Do Nothing. + * + */ +VOID +CommonVoid ( + IN VOID +); + +/** + * ASSERT if this routine is called. + * + */ +VOID +CommonAssert ( + IN VOID +); + +#endif // _COMMON_RETURNS_H_ diff --git a/src/vendorcode/amd/agesa/f10/Include/DanubeInstall.h b/src/vendorcode/amd/agesa/f10/Include/DanubeInstall.h new file mode 100755 index 0000000..22f6392 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Include/DanubeInstall.h @@ -0,0 +1,1530 @@ +/** + * @file + * + * Install of build options for a Danube platform solution + * + * This file generates the defaults tables for the "Danube" platform solution + * set of processors. The documented build options are imported from a user + * controlled file for processing. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterfaceStub.h" + +extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4; +extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4; +extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2; +extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2; + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "DanNiPI " + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '} + +// +//Support multiple dll's per image for legacy BIOS only. +//Platform BIOS may need to extern AmdAgesaDispatcher, if ModuleDispatcher is not NULL. +// +//extern AGESA_STATUS CALLCONV AmdAgesaDispatcher( VOID *); + +VOLATILE AMD_MODULE_HEADER mCpuModuleID = { + //ModuleHeaderSignature + // Remove 'DOM$' as temp solution before update BinUtil.exe , + '0000', + //ModuleIdentifier[8] + AGESA_ID, + //ModuleVersion[12] + AGESA_VERSION_STRING, + //ModuleDispatcher + NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher), + //NextBlock + NULL +}; + +/***************************************************************************** + * + * Start processing the user options: First, set default settings + * + ****************************************************************************/ + +/* Available options for image builds. + * + * As part of the image build for each image, define the options below to select the + * AGESA entry points included in that image. Turn these on in your option c file, not + * here. + */ +// #define AGESA_ENTRY_INIT_RESET TRUE +// #define AGESA_ENTRY_INIT_RECOVERY TRUE +// #define AGESA_ENTRY_INIT_EARLY TRUE +// #define AGESA_ENTRY_INIT_POST TRUE +// #define AGESA_ENTRY_INIT_ENV TRUE +// #define AGESA_ENTRY_INIT_MID TRUE +// #define AGESA_ENTRY_INIT_LATE TRUE +// #define AGESA_ENTRY_INIT_S3SAVE TRUE +// #define AGESA_ENTRY_INIT_RESUME TRUE +// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE + +/* Defaults for private/internal build control settings */ +/* Available options for image builds. + * + * As part of the image build for each image, define the options below to select the + * AGESA entry points included in that image. + */ + + +#ifndef AGESA_ENTRY_INIT_RESET + #define AGESA_ENTRY_INIT_RESET FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RECOVERY + #define AGESA_ENTRY_INIT_RECOVERY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_EARLY + #define AGESA_ENTRY_INIT_EARLY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_POST + #define AGESA_ENTRY_INIT_POST FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_ENV + #define AGESA_ENTRY_INIT_ENV FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_MID + #define AGESA_ENTRY_INIT_MID FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE + #define AGESA_ENTRY_INIT_LATE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_S3SAVE + #define AGESA_ENTRY_INIT_S3SAVE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RESUME + #define AGESA_ENTRY_INIT_RESUME FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE_RESTORE + #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES + #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#endif + +// Add logic for determining if the AP callout is required +// by checking enabled entry points / enabled features that +// may need them. Leave the ifndef here in case the logic +// does not define this equate. +#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK + #define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE +#endif + +#define OPTION_FAMILY10H TRUE +#define OPTION_FAMILY10H_DA TRUE +#define OPTION_FAMILY10H_BL TRUE +#define OPTION_MEMCTLR_DA TRUE + +#ifdef BLDCFG_AMD_PLATFORM_TYPE + #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE +#else + #define CFG_AMD_PLATFORM_TYPE 0 +#endif + +CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; + +#define OPTION_HW_WRITE_LEV_TRAINING TRUE +#define OPTION_SW_WRITE_LEV_TRAINING FALSE +#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE +#define OPTION_HW_DQS_REC_EN_TRAINING FALSE +#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE +#define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE +#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE +#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE +#define OPTION_MAX_RD_LAT_TRAINING TRUE +#define OPTION_HW_DRAM_INIT FALSE +#define OPTION_SW_DRAM_INIT TRUE +#define OPTION_S3_MEM_SUPPORT TRUE +#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE + +/* Defaults for public user options */ +#define OPTION_MULTISOCKET FALSE +#define OPTION_UDIMMS TRUE +#define OPTION_RDIMMS FALSE +#define OPTION_SODIMMS TRUE +#define OPTION_ECC TRUE +#define OPTION_BANK_INTERLEAVE TRUE +#define OPTION_DCT_INTERLEAVE TRUE +#define OPTION_NODE_INTERLEAVE FALSE +#define OPTION_PARALLEL_TRAINING FALSE +#define OPTION_ONLINE_SPARE FALSE +#define OPTION_MEM_RESTORE TRUE +#define OPTION_DIMM_EXCLUDE TRUE +#define OPTION_ACPI_PSTATES TRUE +#define OPTION_SRAT FALSE +#define OPTION_SLIT FALSE +#define OPTION_WHEA TRUE +#define OPTION_DMI TRUE +#define OPTION_DDR2 FALSE +#define OPTION_DDR3 TRUE +#define OPTION_EARLY_SAMPLES FALSE +#define OPTION_HT_ASSIST FALSE +#define OPTION_CPU_CORELEVLING TRUE +#define OPTION_MSG_BASED_C1E FALSE +#define OPTION_CPU_CFOH TRUE +#define CFG_ACPI_PSTATES_PPC TRUE +#define CFG_ACPI_PSTATES_PCT TRUE +#define CFG_ACPI_PSTATES_PSD TRUE +#define CFG_ACPI_PSTATES_PSS TRUE +#define CFG_ACPI_PSTATES_XPSS TRUE +#define CFG_ACPI_PSTATE_PSD_INDPX FALSE +#define CFG_VRM_HIGH_SPEED_ENABLE FALSE + +/*--------------------------------------------------------------------------- + * Processing the options: Second, process the user's selections + *--------------------------------------------------------------------------*/ +#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT + #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ECC_SUPPORT + #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE + #undef OPTION_ECC + #define OPTION_ECC FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT + #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT + #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT + #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE + #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE + #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE + #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING + #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT + #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT + #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ACPI_PSTATES + #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE + #undef OPTION_ACPI_PSTATES + #define OPTION_ACPI_PSTATES FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SRAT + #if BLDOPT_REMOVE_SRAT == TRUE + #undef OPTION_SRAT + #define OPTION_SRAT FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SLIT + #if BLDOPT_REMOVE_SLIT == TRUE + #undef OPTION_SLIT + #define OPTION_SLIT FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_WHEA + #if BLDOPT_REMOVE_WHEA == TRUE + #undef OPTION_WHEA + #define OPTION_WHEA FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_DMI + #if BLDOPT_REMOVE_DMI == TRUE + #undef OPTION_DMI + #define OPTION_DMI FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR + #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_HT_ASSIST + #if BLDOPT_REMOVE_HT_ASSIST == TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_MSG_BASED_C1E + #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC + #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE + #undef CFG_ACPI_PSTATES_PPC + #define CFG_ACPI_PSTATES_PPC FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT + #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE + #undef CFG_ACPI_PSTATES_PCT + #define CFG_ACPI_PSTATES_PCT FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD + #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE + #undef CFG_ACPI_PSTATES_PSD + #define CFG_ACPI_PSTATES_PSD FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS + #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE + #undef CFG_ACPI_PSTATES_PSS + #define CFG_ACPI_PSTATES_PSS FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS + #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE + #undef CFG_ACPI_PSTATES_XPSS + #define CFG_ACPI_PSTATES_XPSS FALSE + #endif +#endif + +#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT + #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE + #undef CFG_ACPI_PSTATE_PSD_INDPX + #define CFG_ACPI_PSTATE_PSD_INDPX TRUE + #endif +#endif + +#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE + #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE + #undef CFG_VRM_HIGH_SPEED_ENABLE + #define CFG_VRM_HIGH_SPEED_ENABLE TRUE + #endif +#endif + +#ifdef BLDCFG_VRM_CURRENT_LIMIT + #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT +#else + #define CFG_VRM_CURRENT_LIMIT 0 +#endif + +#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD + #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD +#else + #define CFG_VRM_LOW_POWER_THRESHOLD 0 +#endif + +#ifdef BLDCFG_VRM_SLEW_RATE + #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#else + #define CFG_VRM_SLEW_RATE 5000 +#endif + +#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT + #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT +#else + #define CFG_VRM_INRUSH_CURRENT_LIMIT 0 +#endif + +#ifdef BLDCFG_PLAT_NUM_IO_APICS + #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS +#else + #define CFG_PLAT_NUM_IO_APICS 0 +#endif + +#ifdef BLDCFG_MEM_INIT_PSTATE + #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE +#else + #define CFG_MEM_INIT_PSTATE 0 +#endif + +#ifdef BLDCFG_PLATFORM_C1E_MODE + #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE +#else + #define CFG_C1E_MODE C1eModeDisabled +#endif + +#ifdef BLDCFG_PLATFORM_C1E_OPDATA + #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA +#else + #define CFG_C1E_OPDATA 0 +#endif + +#ifdef BLDCFG_PLATFORM_CSTATE_MODE + #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE +#else + #define CFG_CSTATE_MODE CStateModeDisabled +#endif + +#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA + #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA +#else + #define CFG_CSTATE_OPDATA 0 +#endif + +#ifdef BLDCFG_CORE_LEVELING_MODE + #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE +#else + #define CFG_CORE_LEVELING_MODE 0 +#endif + +#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE + #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE +#else + #define CFG_AMD_PSTATE_CAP_VALUE 0 +#endif + +#ifdef BLDCFG_HEAP_DRAM_ADDRESS + #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS +#else + #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS +#endif + +#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT +#else + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY +#endif + +#ifdef BLDCFG_MEMORY_MODE_UNGANGED + #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED +#else + #define CFG_MEMORY_MODE_UNGANGED TRUE +#endif + +#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE + #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE +#else + #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_QUADRANK_TYPE + #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE +#else + #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#endif + +#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE + #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE +#else + #define CFG_MEMORY_RDIMM_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE + #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE +#else + #define CFG_MEMORY_UDIMM_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE + #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE +#else + #define CFG_MEMORY_SODIMM_CAPABLE FALSE +#endif + +#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB + #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB +#else + #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE +#endif + +#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING + #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING +#else + #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#endif + +#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING + #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING +#else + #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#endif + +#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING + #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING +#else + #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#endif + +#ifdef BLDCFG_MEMORY_POWER_DOWN + #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN +#else + #define CFG_MEMORY_POWER_DOWN FALSE +#endif + +#ifdef BLDCFG_POWER_DOWN_MODE + #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE +#else + #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL +#endif + +#ifdef BLDCFG_ONLINE_SPARE + #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE +#else + #define CFG_ONLINE_SPARE FALSE +#endif + +#ifdef BLDCFG_MEMORY_PARITY_ENABLE + #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE +#else + #define CFG_MEMORY_PARITY_ENABLE FALSE +#endif + +#ifdef BLDCFG_BANK_SWIZZLE + #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE +#else + #define CFG_BANK_SWIZZLE TRUE +#endif + +#ifdef BLDCFG_TIMING_MODE_SELECT + #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT +#else + #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#endif + +#ifdef BLDCFG_MEMORY_CLOCK_SELECT + #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT +#else + #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#endif + +#ifdef BLDCFG_DQS_TRAINING_CONTROL + #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL +#else + #define CFG_DQS_TRAINING_CONTROL TRUE +#endif + +#ifdef BLDCFG_IGNORE_SPD_CHECKSUM + #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM +#else + #define CFG_IGNORE_SPD_CHECKSUM FALSE +#endif + +#ifdef BLDCFG_USE_BURST_MODE + #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE +#else + #define CFG_USE_BURST_MODE FALSE +#endif + +#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON + #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON +#else + #define CFG_MEMORY_ALL_CLOCKS_ON FALSE +#endif + +#ifdef BLDCFG_ENABLE_ECC_FEATURE + #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE +#else + #define CFG_ENABLE_ECC_FEATURE TRUE +#endif + +#ifdef BLDCFG_ECC_REDIRECTION + #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION +#else + #define CFG_ECC_REDIRECTION FALSE +#endif + +#ifdef BLDCFG_SCRUB_DRAM_RATE + #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE +#else + #define CFG_SCRUB_DRAM_RATE 0 +#endif + +#ifdef BLDCFG_SCRUB_L2_RATE + #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE +#else + #define CFG_SCRUB_L2_RATE 0 +#endif + +#ifdef BLDCFG_SCRUB_L3_RATE + #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE +#else + #define CFG_SCRUB_L3_RATE 0 +#endif + +#ifdef BLDCFG_SCRUB_IC_RATE + #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE +#else + #define CFG_SCRUB_IC_RATE 0 +#endif + +#ifdef BLDCFG_SCRUB_DC_RATE + #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE +#else + #define CFG_SCRUB_DC_RATE 0 +#endif + +#ifdef BLDCFG_ECC_SYNC_FLOOD + #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD +#else + #define CFG_ECC_SYNC_FLOOD 0 +#endif + +#ifdef BLDCFG_ECC_SYMBOL_SIZE + #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE +#else + #define CFG_ECC_SYMBOL_SIZE 0 +#endif + +#ifdef BLDCFG_1GB_ALIGN + #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN +#else + #define CFG_1GB_ALIGN FALSE +#endif + +#ifdef BLDCFG_UMA_ALLOCATION_MODE + #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE +#else + #define CFG_UMA_MODE UMA_AUTO +#endif + +#ifdef BLDCFG_UMA_ALLOCATION_SIZE + #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE +#else + #define CFG_UMA_SIZE 0 +#endif + +#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT + #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT +#else + #define CFG_UMA_ABOVE4G FALSE +#endif + +#ifdef BLDCFG_UMA_ALIGNMENT + #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT +#else + #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB + #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB +#else + #define CFG_PROCESSOR_SCOPE_IN_SB FALSE +#endif + +#ifdef BLDCFG_S3_LATE_RESTORE + #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE +#else + #define CFG_S3_LATE_RESTORE TRUE +#endif + +#ifdef BLDCFG_USE_32_BYTE_REFRESH + #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH) +#else + #define CFG_USE_32_BYTE_REFRESH (FALSE) +#endif + +#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY + #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY) +#else + #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE) +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0 + #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0 +#else + #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1 + #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1 +#else + #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1 +#endif + +#ifdef BLDCFG_CFG_GNB_HD_AUDIO + #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO +#else + #define CFG_GNB_HD_AUDIO FALSE +#endif + +#ifdef BLDCFG_CFG_ABM_SUPPORT + #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT +#else + #define CFG_ABM_SUPPORT FALSE +#endif + +#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE + #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE +#else + #define CFG_DYNAMIC_REFRESH_RATE 0 +#endif + +#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL + #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL +#else + #define CFG_LCD_BACK_LIGHT_CONTROL 0 +#endif + +#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS + #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS +#else + #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +#endif + +#ifdef BLDOPT_REMOVE_EARLY_SAMPLES + #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE + #undef OPTION_EARLY_SAMPLES + #define OPTION_EARLY_SAMPLES FALSE + #else + #undef OPTION_EARLY_SAMPLES + #define OPTION_EARLY_SAMPLES TRUE + #endif +#endif + + +/*--------------------------------------------------------------------------- + * Processing the options: Third, perform the option cross checks + *--------------------------------------------------------------------------*/ +// Assure that at least one type of memory support is included +#if OPTION_UDIMMS == FALSE + #if OPTION_RDIMMS == FALSE + #if OPTION_SODIMMS == FALSE + #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT must be FALSE. + #endif + #endif +#endif +// Ensure at least one dimm type is capable +#if CFG_MEMORY_RDIMM_CAPABLE == FALSE + #if CFG_MEMORY_UDIMM_CAPABLE == FALSE + #if CFG_MEMORY_SODIMM_CAPABLE == FALSE + #error BLDCFG: No dimm type is capable + #endif + #endif +#endif +// Turn off multi-socket based features if only one node... +#if OPTION_MULTISOCKET == FALSE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING FALSE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE FALSE +#endif +// Ensure that at least one write leveling option is selected +#if OPTION_DDR3 == TRUE + #if OPTION_HW_WRITE_LEV_TRAINING == FALSE + #if OPTION_SW_WRITE_LEV_TRAINING == FALSE + #error No Write leveling option selected for DDR3 + #endif + #endif + #if OPTION_SW_DRAM_INIT == FALSE + #error Software dram init must be enabled for DDR3 dimms + #endif +#endif +// Ensure at least one DQS receiver training option is selected +#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE + #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE + #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE + #error No DQS receiver training option has been slected + #endif + #endif +#endif +// Ensure at least one Rd Wr position training option has been selected +#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE + #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE + #error No Rd Wr position training option has been selected + #endif +#endif +// Ensure at least one dram init option has been selected +#if OPTION_HW_DRAM_INIT == FALSE + #if OPTION_SW_DRAM_INIT == FALSE + #error No Dram init option has been selected + #endif +#endif +// Ensure the frequency limit is valid +#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200) + #error BLDCFG: Unsupported memory bus frequency + #endif + #endif + #endif + #endif + #endif + #endif +#endif +// Ensure timing mode is valid +#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC + #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED + #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO + #error BLDCFG: Invalid timing mode is set + #endif + #endif +#endif +// Ensure the scrub rate is valid +#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) + #error BLDCFG: Unsupported dram scrub rate set +#endif +#if CFG_SCRUB_L2_RATE > 0x16 + #error BLDCFG: Unsupported L2 scrubber rate set +#endif +#if CFG_SCRUB_L3_RATE > 0x16 + #error BLDCFG: unsupported L3 scrubber rate set +#endif +#if CFG_SCRUB_IC_RATE > 0x16 + #error BLDCFG: Unsupported Instruction cache scrub rate set +#endif +#if CFG_SCRUB_DC_RATE > 0x16 + #error BLDCFG: Unsupported Dcache scrub rate set +#endif +// Ensure Quad rank dimm type is valid +#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED + #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED + #error BLDCFG: Invalid quad rank dimm type set + #endif +#endif +// Ensure ECC symbol size is valid +#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG + #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 + #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8 + #error BLDCFG: Invalid Ecc symbol size set + #endif + #endif +#endif +// Ensure power down mode is valid +#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT + #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL + #error BLDCFG: Invalid power down mode set + #endif +#endif + +/***************************************************************************** + * + * Process the option logic, setting local control variables + * + ****************************************************************************/ +#if OPTION_ACPI_PSTATES == TRUE + #define OPTFCN_ACPI_TABLES CreateAcpiTables + #define OPTFCN_GATHER_DATA PStateGatherData + #if OPTION_MULTISOCKET == TRUE + #define OPTFCN_PSTATE_LEVELING PStateLeveling + #else + #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess + #endif +#else + #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess + #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess + #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess +#endif + +#define GET_PSTATE_POWER FALSE +#define GET_PSTATE_FREQ FALSE +#define DISABLE_PSTATE FALSE +#define TRANSITION_PSTATE FALSE +#define PROC_IDD_MAX FALSE +#define GET_TSC_RATE FALSE +#define PSTATE_TRANSITION_LATENCY FALSE +#define GET_PSTATE_REGISTER_INFO FALSE +#define GET_PSTATE_MAX_STATE FALSE +#define SET_PSTATE_LEVELING_REG FALSE +#define GET_NB_FREQ FALSE +#define IS_NBCOF_INIT_NEEDED FALSE +#define IS_NB_PSTATE_ENABLED FALSE +#define AP_INITIAL_LAUNCH FALSE +#define GET_AP_MAILBOX_FROM_HW FALSE +#define SET_AP_CORE_NUMBER FALSE +#define GET_AP_CORE_NUMBER FALSE +#define TRANSFER_AP_CORE_NUMBER FALSE +#define ID_POSITION_INITIAL_APICID FALSE +#define SAVE_FEATURES FALSE +#define WRITE_FEATURES FALSE +#define SET_DOWN_CORE_REG FALSE +#define SET_WARM_RESET_FLAG FALSE +#define GET_WARM_RESET_FLAG FALSE +#define USES_REGISTER_TABLES FALSE +#define BASE_FAMILY_PCI FALSE +#define MODEL_SPECIFIC_PCI FALSE +#define BASE_FAMILY_MSR FALSE +#define MODEL_SPECIFIC_MSR FALSE +#define BRAND_STRING1 FALSE +#define BRAND_STRING2 FALSE +#define BASE_FAMILY_HT_PCI FALSE +#define MODEL_SPECIFIC_HT_PCI FALSE +#define GET_PATCHES FALSE +#define GET_PATCHES_EQUIVALENCE_TABLE FALSE +#define GET_CACHE_INFO FALSE +#define GET_SYSTEM_PM_TABLE FALSE +#define GET_WHEA_INIT FALSE +#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE + +#if AGESA_ENTRY_INIT_RESET == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef GET_AP_MAILBOX_FROM_HW + #define GET_AP_MAILBOX_FROM_HW TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef TRANSFER_AP_CORE_NUMBER + #define TRANSFER_AP_CORE_NUMBER TRUE +#endif + +#if AGESA_ENTRY_INIT_RECOVERY == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef USES_REGISTER_TABLES + #define USES_REGISTER_TABLES TRUE + #undef BASE_FAMILY_PCI + #define BASE_FAMILY_PCI TRUE + #undef MODEL_SPECIFIC_PCI + #define MODEL_SPECIFIC_PCI TRUE + #undef BASE_FAMILY_MSR + #define BASE_FAMILY_MSR TRUE + #undef MODEL_SPECIFIC_MSR + #define MODEL_SPECIFIC_MSR TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_EARLY == TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PROC_IDD_MAX + #define PROC_IDD_MAX TRUE + #undef GET_TSC_RATE + #define GET_TSC_RATE TRUE + #undef GET_NB_FREQ + #define GET_NB_FREQ TRUE + #undef IS_NBCOF_INIT_NEEDED + #define IS_NBCOF_INIT_NEEDED TRUE + #undef AP_INITIAL_LAUNCH + #define AP_INITIAL_LAUNCH TRUE + #undef GET_AP_MAILBOX_FROM_HW + #define GET_AP_MAILBOX_FROM_HW TRUE + #undef SET_AP_CORE_NUMBER + #define SET_AP_CORE_NUMBER TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef TRANSFER_AP_CORE_NUMBER + #define TRANSFER_AP_CORE_NUMBER TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef SET_DOWN_CORE_REG + #define SET_DOWN_CORE_REG TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef USES_REGISTER_TABLES + #define USES_REGISTER_TABLES TRUE + #undef BASE_FAMILY_PCI + #define BASE_FAMILY_PCI TRUE + #undef MODEL_SPECIFIC_PCI + #define MODEL_SPECIFIC_PCI TRUE + #undef BASE_FAMILY_MSR + #define BASE_FAMILY_MSR TRUE + #undef MODEL_SPECIFIC_MSR + #define MODEL_SPECIFIC_MSR TRUE + #undef BRAND_STRING1 + #define BRAND_STRING1 TRUE + #undef BRAND_STRING2 + #define BRAND_STRING2 TRUE + #undef BASE_FAMILY_HT_PCI + #define BASE_FAMILY_HT_PCI TRUE + #undef MODEL_SPECIFIC_HT_PCI + #define MODEL_SPECIFIC_HT_PCI TRUE + #undef GET_PATCHES + #define GET_PATCHES TRUE + #undef GET_PATCHES_EQUIVALENCE_TABLE + #define GET_PATCHES_EQUIVALENCE_TABLE TRUE + #undef GET_SYSTEM_PM_TABLE + #define GET_SYSTEM_PM_TABLE TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_POST == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef GET_PSTATE_POWER + #define GET_PSTATE_POWER TRUE + #undef GET_PSTATE_FREQ + #define GET_PSTATE_FREQ TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PROC_IDD_MAX + #define PROC_IDD_MAX TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef GET_PSTATE_REGISTER_INFO + #define GET_PSTATE_REGISTER_INFO TRUE + #undef GET_PSTATE_MAX_STATE + #define GET_PSTATE_MAX_STATE TRUE + #undef SET_PSTATE_LEVELING_REG + #define SET_PSTATE_LEVELING_REG TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef SAVE_FEATURES + #define SAVE_FEATURES TRUE + #undef WRITE_FEATURES + #define WRITE_FEATURES TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_ENV == TRUE +#endif + +#if AGESA_ENTRY_INIT_MID == TRUE +#endif + +#if AGESA_ENTRY_INIT_LATE == TRUE + #undef GET_PSTATE_FREQ + #define GET_PSTATE_FREQ TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PSTATE_TRANSITION_LATENCY + #define PSTATE_TRANSITION_LATENCY TRUE + #undef GET_WHEA_INIT + #define GET_WHEA_INIT TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE +#endif + +#if AGESA_ENTRY_INIT_S3SAVE == TRUE +#endif + +#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE +#endif + +#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE +#endif + +// Initialize family mask for the PCI MMIO MSR to 0 +#define FAMILY_MMIO_BASE_MASK (0ull) + +/***************************************************************************** + * + * Include the structure definitions for the defaults table structures + * + ****************************************************************************/ +#include "OptionFamily10h.h" +#include "OptionFamily10hBlInstall.h" +#include "OptionFamily10hDaInstall.h" +#include "OptionFamily10hHyInstall.h" +#include "OptionFamily10hRbInstall.h" +#include "OptionFamily10hInstall.h" +#include "Options.h" +#include "OptionsHt.h" +#include "OptionHtInstall.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "OptionMemoryInstall.h" +#include "OptionMemoryRecovery.h" +#include "OptionMemoryRecoveryInstall.h" +#include "OptionDmi.h" +#include "OptionDmiInstall.h" +#include "OptionPstate.h" +#include "OptionPstateInstall.h" +#include "OptionWhea.h" +#include "OptionWheaInstall.h" +#include "OptionSrat.h" +#include "OptionSratInstall.h" +#include "OptionSlit.h" +#include "OptionSlitInstall.h" +#include "OptionMultiSocket.h" +#include "OptionMultiSocketInstall.h" +#include "OptionCpuFeaturesInstall.h" +#include "OptionIdsInstall.h" +#include "OptionS3ScriptInstall.h" +#if (AGESA_ENTRY_INIT_EARLY == TRUE) + #include "OptionDanubeMicrocodeInstall.h" +#endif + + +// If size is 0, but base is not, break the build. +#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0) + #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 +#endif + +// If base is 0, but size is not, break the build. +#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0) + #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater +#endif + +#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0) + // Both are non-zero, begin further processing. + + // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB. + #if (CFG_PCI_MMIO_BASE < 0x800000) + #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater + #endif + + // Break the build if the address is too high for the enabled families. + #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0) + #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families + #endif + + // If the size parameter is not valid, break the build. + #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16) + #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256) + #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 + #endif + #endif + + #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1) + // If the base is not aligned according to size, break the build. + #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0) + #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size + #endif + #undef PCI_MMIO_ALIGNMENT +#endif + + +/***************************************************************************** + * + * Generate the output structures (defaults tables) + * + ****************************************************************************/ +#ifndef ADVCFG_PLATFORM_SOCKETS + #error BLDOPT Set Family supported sockets. +#endif +#ifndef ADVCFG_PLATFORM_MODULES + #error BLDOPT Set Family supported modules. +#endif + + +BUILD_OPT_CFG UserOptions = { + { // AGESA version string + AGESA_CODE_SIGNATURE, // code header Signature + AGESA_PACKAGE_STRING, // 8 character ID + AGESA_VERSION_STRING, // 12 character version string + 0 // null string terminator + }, + //Build Option Area + OPTION_UDIMMS, //UDIMMS + OPTION_RDIMMS, //RDIMMS + OPTION_ECC, //ECC + OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE + OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE + OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE + OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING + OPTION_ONLINE_SPARE, //ONLINE_SPARE + OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE + OPTION_MULTISOCKET, //MULTISOCKET + OPTION_ACPI_PSTATES, //ACPI_PSTATES + OPTION_SRAT, //SRAT + OPTION_SLIT, //SLIT + OPTION_WHEA, //WHEA + OPTION_DMI, //DMI + OPTION_EARLY_SAMPLES, //EARLY_SAMPLES + OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR + + //Build Configuration Area + CFG_PCI_MMIO_BASE, + CFG_PCI_MMIO_SIZE, + { + CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit + CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold + CFG_VRM_SLEW_RATE, // VrmSlewRate + CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay + CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable + CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit + }, + CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber + CFG_MEM_INIT_PSTATE, //MemoryInitPstate + CFG_C1E_MODE, //C1eMode + CFG_C1E_OPDATA, //C1ePlatformData + CFG_CSTATE_MODE, //CStateMode + CFG_CSTATE_OPDATA, //CStatePlatformData + CFG_CORE_LEVELING_MODE, //CoreLevelingCofig + { + CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode. + CFG_USE_HT_ASSIST, // CfgUseHtAssist + CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets. + CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority. + CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode. + }, + (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings + CFG_AMD_PLATFORM_TYPE, //AmdPlatformType + CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck + + CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit + CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged + CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable + CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType + CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable + CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable + CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable + CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb + CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving + CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving + CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving + CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown + CFG_POWER_DOWN_MODE, // CfgPowerDownMode + CFG_ONLINE_SPARE, // CfgOnlineSpare + CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable + CFG_BANK_SWIZZLE, // CfgBankSwizzle + CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect + CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect + CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl + CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum + CFG_USE_BURST_MODE, // CfgUseBurstMode + CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn + CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature + CFG_ECC_REDIRECTION, // CfgEccRedirection + CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate + CFG_SCRUB_L2_RATE, // CfgScrubL2Rate + CFG_SCRUB_L3_RATE, // CfgScrubL3Rate + CFG_SCRUB_IC_RATE, // CfgScrubIcRate + CFG_SCRUB_DC_RATE, // CfgScrubDcRate + CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood + CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize + CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress + CFG_1GB_ALIGN, // CfgNodeMem1GBAlign + CFG_S3_LATE_RESTORE, // CfgS3LateRestore + CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent + (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList + CFG_UMA_MODE, // CfgUmaMode + CFG_UMA_SIZE, // CfgUmaSize + CFG_UMA_ABOVE4G, // CfgUmaAbove4G + CFG_UMA_ALIGNMENT, // CfgUmaAlignment + CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb + CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0 + CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1 + CFG_GNB_HD_AUDIO, // CfgGnbHdAudio + CFG_ABM_SUPPORT, // CfgAbmSupport + CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate + CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl + CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress + + 0, //reserved... +}; + +/// @todo, hmmm options.c override? multisocket == false? Look broken. +CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration = +{ + ADVCFG_PLATFORM_SOCKETS, + ADVCFG_PLATFORM_MODULES +}; + +CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] = +{ + OPT_F10_ID_TABLE +}; + +CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable = +{ + (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)), + CpuSupportedFamilyIdArray +}; + +CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = +{ + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, + sizeof (AMD_RESET_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResetConstructor, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_RESET_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, + sizeof (AMD_RECOVERY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, + sizeof (AMD_EARLY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_EARLY_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, + sizeof (AMD_ENV_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEnvInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_ENV_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, + sizeof (AMD_LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdInitLateInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, + AMD_INIT_LATE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, + sizeof (AMD_MID_PARAMS), + (PF_AGESA_FUNCTION) AmdInitMidInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_MID_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, + sizeof (AMD_POST_PARAMS), + (PF_AGESA_FUNCTION) AmdInitPostInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, + sizeof (AMD_RESUME_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResumeInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, + AMD_INIT_RESUME_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, + sizeof (AMD_S3LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_S3_LATE_RESTORE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, + sizeof (AMD_S3SAVE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3SaveInitializer, + (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, + AMD_S3_SAVE_HANDLE + }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, + sizeof (AP_EXE_PARAMS), + (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_LATE_RUN_AP_TASK_HANDLE + }, + #endif + { 0, NULL } +}; + +CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); + +CONST DISPATCH_TABLE ROMDATA DispatchTable[] = +{ + { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, + { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, + + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, + #endif + + #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, + { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, + { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, + { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, + { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, + #endif + { 0, NULL } +}; + +CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = +{ + IDS_LATE_RUN_AP_TASK + // Get DMI info + + // Probe filter enable + + { 0, NULL } +}; + +CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] = +{ + &F10BrandIdString1ArrayS1g4, + &F10BrandIdString1ArrayAsb2 +}; + +CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] = +{ + &F10BrandIdString2ArrayS1g4, + &F10BrandIdString2ArrayAsb2 +}; +CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0])); +CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0])); diff --git a/src/vendorcode/amd/agesa/f10/Include/DragonInstall.h b/src/vendorcode/amd/agesa/f10/Include/DragonInstall.h new file mode 100755 index 0000000..8053073 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Include/DragonInstall.h @@ -0,0 +1,1531 @@ +/** + * @file + * + * Install of build options for a Dragon platform solution + * + * This file generates the defaults tables for the "Dragon" platform solution + * set of processors. The documented build options are imported from a user + * controlled file for processing. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterfaceStub.h" + +extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3; +extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3; + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "DragonPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'D', 'r', 'a', 'g', 'o', 'n', 'P', 'I'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '} + +// +//Support multiple dll's per image for legacy BIOS only. +//Platform BIOS may need to extern AmdAgesaDispatcher, if ModuleDispatcher is not NULL. +// +//extern AGESA_STATUS CALLCONV AmdAgesaDispatcher( VOID *); + +VOLATILE AMD_MODULE_HEADER mCpuModuleID = { + //ModuleHeaderSignature + // Remove 'DOM$' as temp solution before update BinUtil.exe , + '0000', + //ModuleIdentifier[8] + AGESA_ID, + //ModuleVersion[12] + AGESA_VERSION_STRING, + //ModuleDispatcher + NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher), + //NextBlock + NULL +}; + +/***************************************************************************** + * + * Start processing the user options: First, set default settings + * + ****************************************************************************/ + +/* Available options for image builds. + * + * As part of the image build for each image, define the options below to select the + * AGESA entry points included in that image. Turn these on in your option c file, not + * here. + */ +// #define AGESA_ENTRY_INIT_RESET TRUE +// #define AGESA_ENTRY_INIT_RECOVERY TRUE +// #define AGESA_ENTRY_INIT_EARLY TRUE +// #define AGESA_ENTRY_INIT_POST TRUE +// #define AGESA_ENTRY_INIT_ENV TRUE +// #define AGESA_ENTRY_INIT_MID TRUE +// #define AGESA_ENTRY_INIT_LATE TRUE +// #define AGESA_ENTRY_INIT_S3SAVE TRUE +// #define AGESA_ENTRY_INIT_RESUME TRUE +// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE + +/* Defaults for private/internal build control settings */ +/* Available options for image builds. + * + * As part of the image build for each image, define the options below to select the + * AGESA entry points included in that image. + */ + + +#ifndef AGESA_ENTRY_INIT_RESET + #define AGESA_ENTRY_INIT_RESET FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RECOVERY + #define AGESA_ENTRY_INIT_RECOVERY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_EARLY + #define AGESA_ENTRY_INIT_EARLY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_POST + #define AGESA_ENTRY_INIT_POST FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_ENV + #define AGESA_ENTRY_INIT_ENV FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_MID + #define AGESA_ENTRY_INIT_MID FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE + #define AGESA_ENTRY_INIT_LATE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_S3SAVE + #define AGESA_ENTRY_INIT_S3SAVE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RESUME + #define AGESA_ENTRY_INIT_RESUME FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE_RESTORE + #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES + #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#endif + +// Add logic for determining if the AP callout is required +// by checking enabled entry points / enabled features that +// may need them. Leave the ifndef here in case the logic +// does not define this equate. +#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK + #define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE +#endif + +#define OPTION_FAMILY10H TRUE +#define OPTION_FAMILY10H_BL TRUE +#define OPTION_FAMILY10H_DA TRUE +#define OPTION_FAMILY10H_HY FALSE +#define OPTION_FAMILY10H_RB TRUE + +#define OPTION_MEMCTLR_DR TRUE +#define OPTION_MEMCTLR_HY FALSE +#define OPTION_MEMCTLR_OR FALSE + +#ifdef BLDCFG_AMD_PLATFORM_TYPE + #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE +#else + #define CFG_AMD_PLATFORM_TYPE 0 +#endif + +CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; + +#define OPTION_HW_WRITE_LEV_TRAINING TRUE +#define OPTION_SW_WRITE_LEV_TRAINING FALSE +#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE +#define OPTION_HW_DQS_REC_EN_TRAINING FALSE +#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING TRUE +#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE +#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING TRUE +#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE +#define OPTION_MAX_RD_LAT_TRAINING TRUE +#define OPTION_HW_DRAM_INIT FALSE +#define OPTION_SW_DRAM_INIT TRUE +#define OPTION_S3_MEM_SUPPORT TRUE +#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE + +/* Defaults for public user options */ +#define OPTION_MULTISOCKET TRUE +#define OPTION_UDIMMS TRUE +#define OPTION_RDIMMS TRUE +#define OPTION_SODIMMS TRUE +#define OPTION_ECC TRUE +#define OPTION_BANK_INTERLEAVE TRUE +#define OPTION_DCT_INTERLEAVE TRUE +#define OPTION_NODE_INTERLEAVE TRUE +#define OPTION_PARALLEL_TRAINING TRUE +#define OPTION_ONLINE_SPARE TRUE +#define OPTION_MEM_RESTORE TRUE +#define OPTION_DIMM_EXCLUDE TRUE +#define OPTION_ACPI_PSTATES TRUE +#define OPTION_SRAT TRUE +#define OPTION_SLIT TRUE +#define OPTION_WHEA TRUE +#define OPTION_DMI TRUE +#define OPTION_DDR2 FALSE +#define OPTION_DDR3 TRUE +#define OPTION_EARLY_SAMPLES FALSE +#define OPTION_HT_ASSIST FALSE +#define OPTION_CPU_CORELEVLING TRUE +#define OPTION_MSG_BASED_C1E FALSE +#define OPTION_CPU_CFOH TRUE +#define CFG_ACPI_PSTATES_PPC TRUE +#define CFG_ACPI_PSTATES_PCT TRUE +#define CFG_ACPI_PSTATES_PSD TRUE +#define CFG_ACPI_PSTATES_PSS TRUE +#define CFG_ACPI_PSTATES_XPSS TRUE +#define CFG_ACPI_PSTATE_PSD_INDPX FALSE +#define CFG_VRM_HIGH_SPEED_ENABLE FALSE + +/*--------------------------------------------------------------------------- + * Processing the options: Second, process the user's selections + *--------------------------------------------------------------------------*/ +#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT + #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ECC_SUPPORT + #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE + #undef OPTION_ECC + #define OPTION_ECC FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT + #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT + #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT + #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE + #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE + #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE + #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING + #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT + #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT + #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ACPI_PSTATES + #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE + #undef OPTION_ACPI_PSTATES + #define OPTION_ACPI_PSTATES FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SRAT + #if BLDOPT_REMOVE_SRAT == TRUE + #undef OPTION_SRAT + #define OPTION_SRAT FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SLIT + #if BLDOPT_REMOVE_SLIT == TRUE + #undef OPTION_SLIT + #define OPTION_SLIT FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_WHEA + #if BLDOPT_REMOVE_WHEA == TRUE + #undef OPTION_WHEA + #define OPTION_WHEA FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_DMI + #if BLDOPT_REMOVE_DMI == TRUE + #undef OPTION_DMI + #define OPTION_DMI FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR + #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_HT_ASSIST + #if BLDOPT_REMOVE_HT_ASSIST == TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_MSG_BASED_C1E + #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC + #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE + #undef CFG_ACPI_PSTATES_PPC + #define CFG_ACPI_PSTATES_PPC FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT + #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE + #undef CFG_ACPI_PSTATES_PCT + #define CFG_ACPI_PSTATES_PCT FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD + #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE + #undef CFG_ACPI_PSTATES_PSD + #define CFG_ACPI_PSTATES_PSD FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS + #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE + #undef CFG_ACPI_PSTATES_PSS + #define CFG_ACPI_PSTATES_PSS FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS + #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE + #undef CFG_ACPI_PSTATES_XPSS + #define CFG_ACPI_PSTATES_XPSS FALSE + #endif +#endif + +#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT + #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE + #undef CFG_ACPI_PSTATE_PSD_INDPX + #define CFG_ACPI_PSTATE_PSD_INDPX TRUE + #endif +#endif + +#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE + #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE + #undef CFG_VRM_HIGH_SPEED_ENABLE + #define CFG_VRM_HIGH_SPEED_ENABLE TRUE + #endif +#endif + +#ifdef BLDCFG_VRM_CURRENT_LIMIT + #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT +#else + #define CFG_VRM_CURRENT_LIMIT 0 +#endif + +#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD + #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD +#else + #define CFG_VRM_LOW_POWER_THRESHOLD 0 +#endif + +#ifdef BLDCFG_VRM_SLEW_RATE + #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#else + #define CFG_VRM_SLEW_RATE 2500 +#endif + +#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT + #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT +#else + #define CFG_VRM_INRUSH_CURRENT_LIMIT 0 +#endif + +#ifdef BLDCFG_PLAT_NUM_IO_APICS + #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS +#else + #define CFG_PLAT_NUM_IO_APICS 0 +#endif + +#ifdef BLDCFG_MEM_INIT_PSTATE + #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE +#else + #define CFG_MEM_INIT_PSTATE 0 +#endif + +#ifdef BLDCFG_PLATFORM_C1E_MODE + #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE +#else + #define CFG_C1E_MODE C1eModeDisabled +#endif + +#ifdef BLDCFG_PLATFORM_C1E_OPDATA + #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA +#else + #define CFG_C1E_OPDATA 0 +#endif + +#ifdef BLDCFG_PLATFORM_CSTATE_MODE + #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE +#else + #define CFG_CSTATE_MODE CStateModeDisabled +#endif + +#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA + #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA +#else + #define CFG_CSTATE_OPDATA 0 +#endif + +#ifdef BLDCFG_CORE_LEVELING_MODE + #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE +#else + #define CFG_CORE_LEVELING_MODE 0 +#endif + +#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE + #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE +#else + #define CFG_AMD_PSTATE_CAP_VALUE 0 +#endif + +#ifdef BLDCFG_HEAP_DRAM_ADDRESS + #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS +#else + #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS +#endif + +#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT +#else + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY +#endif + +#ifdef BLDCFG_MEMORY_MODE_UNGANGED + #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED +#else + #define CFG_MEMORY_MODE_UNGANGED TRUE +#endif + +#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE + #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE +#else + #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_QUADRANK_TYPE + #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE +#else + #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#endif + +#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE + #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE +#else + #define CFG_MEMORY_RDIMM_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE + #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE +#else + #define CFG_MEMORY_UDIMM_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE + #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE +#else + #define CFG_MEMORY_SODIMM_CAPABLE FALSE +#endif + +#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB + #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB +#else + #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE +#endif + +#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING + #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING +#else + #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#endif + +#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING + #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING +#else + #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#endif + +#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING + #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING +#else + #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#endif + +#ifdef BLDCFG_MEMORY_POWER_DOWN + #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN +#else + #define CFG_MEMORY_POWER_DOWN FALSE +#endif + +#ifdef BLDCFG_POWER_DOWN_MODE + #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE +#else + #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL +#endif + +#ifdef BLDCFG_ONLINE_SPARE + #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE +#else + #define CFG_ONLINE_SPARE FALSE +#endif + +#ifdef BLDCFG_MEMORY_PARITY_ENABLE + #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE +#else + #define CFG_MEMORY_PARITY_ENABLE FALSE +#endif + +#ifdef BLDCFG_BANK_SWIZZLE + #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE +#else + #define CFG_BANK_SWIZZLE TRUE +#endif + +#ifdef BLDCFG_TIMING_MODE_SELECT + #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT +#else + #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#endif + +#ifdef BLDCFG_MEMORY_CLOCK_SELECT + #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT +#else + #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#endif + +#ifdef BLDCFG_DQS_TRAINING_CONTROL + #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL +#else + #define CFG_DQS_TRAINING_CONTROL TRUE +#endif + +#ifdef BLDCFG_IGNORE_SPD_CHECKSUM + #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM +#else + #define CFG_IGNORE_SPD_CHECKSUM FALSE +#endif + +#ifdef BLDCFG_USE_BURST_MODE + #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE +#else + #define CFG_USE_BURST_MODE FALSE +#endif + +#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON + #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON +#else + #define CFG_MEMORY_ALL_CLOCKS_ON FALSE +#endif + +#ifdef BLDCFG_ENABLE_ECC_FEATURE + #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE +#else + #define CFG_ENABLE_ECC_FEATURE TRUE +#endif + +#ifdef BLDCFG_ECC_REDIRECTION + #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION +#else + #define CFG_ECC_REDIRECTION FALSE +#endif + +#ifdef BLDCFG_SCRUB_DRAM_RATE + #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE +#else + #define CFG_SCRUB_DRAM_RATE 0 +#endif + +#ifdef BLDCFG_SCRUB_L2_RATE + #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE +#else + #define CFG_SCRUB_L2_RATE 0 +#endif + +#ifdef BLDCFG_SCRUB_L3_RATE + #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE +#else + #define CFG_SCRUB_L3_RATE 0 +#endif + +#ifdef BLDCFG_SCRUB_IC_RATE + #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE +#else + #define CFG_SCRUB_IC_RATE 0 +#endif + +#ifdef BLDCFG_SCRUB_DC_RATE + #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE +#else + #define CFG_SCRUB_DC_RATE 0 +#endif + +#ifdef BLDCFG_ECC_SYNC_FLOOD + #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD +#else + #define CFG_ECC_SYNC_FLOOD 0 +#endif + +#ifdef BLDCFG_ECC_SYMBOL_SIZE + #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE +#else + #define CFG_ECC_SYMBOL_SIZE 0 +#endif + +#ifdef BLDCFG_1GB_ALIGN + #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN +#else + #define CFG_1GB_ALIGN FALSE +#endif + +#ifdef BLDCFG_UMA_ALLOCATION_MODE + #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE +#else + #define CFG_UMA_MODE UMA_AUTO +#endif + +#ifdef BLDCFG_UMA_ALLOCATION_SIZE + #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE +#else + #define CFG_UMA_SIZE 0 +#endif + +#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT + #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT +#else + #define CFG_UMA_ABOVE4G FALSE +#endif + +#ifdef BLDCFG_UMA_ALIGNMENT + #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT +#else + #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB + #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB +#else + #define CFG_PROCESSOR_SCOPE_IN_SB FALSE +#endif + +#ifdef BLDCFG_S3_LATE_RESTORE + #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE +#else + #define CFG_S3_LATE_RESTORE TRUE +#endif + +#ifdef BLDCFG_USE_32_BYTE_REFRESH + #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH) +#else + #define CFG_USE_32_BYTE_REFRESH (FALSE) +#endif + +#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY + #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY) +#else + #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE) +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0 + #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0 +#else + #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1 + #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1 +#else + #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1 +#endif + +#ifdef BLDCFG_CFG_GNB_HD_AUDIO + #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO +#else + #define CFG_GNB_HD_AUDIO FALSE +#endif + +#ifdef BLDCFG_CFG_ABM_SUPPORT + #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT +#else + #define CFG_ABM_SUPPORT FALSE +#endif + +#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE + #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE +#else + #define CFG_DYNAMIC_REFRESH_RATE 0 +#endif + +#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL + #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL +#else + #define CFG_LCD_BACK_LIGHT_CONTROL 0 +#endif + +#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS + #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS +#else + #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +#endif + +#ifdef BLDOPT_REMOVE_EARLY_SAMPLES + #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE + #undef OPTION_EARLY_SAMPLES + #define OPTION_EARLY_SAMPLES FALSE + #else + #undef OPTION_EARLY_SAMPLES + #define OPTION_EARLY_SAMPLES TRUE + #endif +#endif + + +/*--------------------------------------------------------------------------- + * Processing the options: Third, perform the option cross checks + *--------------------------------------------------------------------------*/ +// Assure that at least one type of memory support is included +#if OPTION_UDIMMS == FALSE + #if OPTION_RDIMMS == FALSE + #if OPTION_SODIMMS == FALSE + #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT must be FALSE. + #endif + #endif +#endif +// Ensure at least one dimm type is capable +#if CFG_MEMORY_RDIMM_CAPABLE == FALSE + #if CFG_MEMORY_UDIMM_CAPABLE == FALSE + #if CFG_MEMORY_SODIMM_CAPABLE == FALSE + #error BLDCFG: No dimm type is capable + #endif + #endif +#endif +// Turn off multi-socket based features if only one node... +#if OPTION_MULTISOCKET == FALSE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING FALSE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE FALSE +#endif +// Ensure that at least one write leveling option is selected +#if OPTION_DDR3 == TRUE + #if OPTION_HW_WRITE_LEV_TRAINING == FALSE + #if OPTION_SW_WRITE_LEV_TRAINING == FALSE + #error No Write leveling option selected for DDR3 + #endif + #endif + #if OPTION_SW_DRAM_INIT == FALSE + #error Software dram init must be enabled for DDR3 dimms + #endif +#endif +// Ensure at least one DQS receiver training option is selected +#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE + #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE + #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE + #error No DQS receiver training option has been slected + #endif + #endif +#endif +// Ensure at least one Rd Wr position training option has been selected +#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE + #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE + #error No Rd Wr position training option has been selected + #endif +#endif +// Ensure at least one dram init option has been selected +#if OPTION_HW_DRAM_INIT == FALSE + #if OPTION_SW_DRAM_INIT == FALSE + #error No Dram init option has been selected + #endif +#endif +// Ensure the frequency limit is valid +#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200) + #error BLDCFG: Unsupported memory bus frequency + #endif + #endif + #endif + #endif + #endif + #endif +#endif +// Ensure timing mode is valid +#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC + #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED + #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO + #error BLDCFG: Invalid timing mode is set + #endif + #endif +#endif +// Ensure the scrub rate is valid +#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) + #error BLDCFG: Unsupported dram scrub rate set +#endif +#if CFG_SCRUB_L2_RATE > 0x16 + #error BLDCFG: Unsupported L2 scrubber rate set +#endif +#if CFG_SCRUB_L3_RATE > 0x16 + #error BLDCFG: unsupported L3 scrubber rate set +#endif +#if CFG_SCRUB_IC_RATE > 0x16 + #error BLDCFG: Unsupported Instruction cache scrub rate set +#endif +#if CFG_SCRUB_DC_RATE > 0x16 + #error BLDCFG: Unsupported Dcache scrub rate set +#endif +// Ensure Quad rank dimm type is valid +#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED + #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED + #error BLDCFG: Invalid quad rank dimm type set + #endif +#endif +// Ensure ECC symbol size is valid +#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG + #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 + #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8 + #error BLDCFG: Invalid Ecc symbol size set + #endif + #endif +#endif +// Ensure power down mode is valid +#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT + #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL + #error BLDCFG: Invalid power down mode set + #endif +#endif + +/***************************************************************************** + * + * Process the option logic, setting local control variables + * + ****************************************************************************/ +#if OPTION_ACPI_PSTATES == TRUE + #define OPTFCN_ACPI_TABLES CreateAcpiTables + #define OPTFCN_GATHER_DATA PStateGatherData + #if OPTION_MULTISOCKET == TRUE + #define OPTFCN_PSTATE_LEVELING PStateLeveling + #else + #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess + #endif +#else + #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess + #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess + #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess +#endif + +#define GET_PSTATE_POWER FALSE +#define GET_PSTATE_FREQ FALSE +#define DISABLE_PSTATE FALSE +#define TRANSITION_PSTATE FALSE +#define PROC_IDD_MAX FALSE +#define GET_TSC_RATE FALSE +#define PSTATE_TRANSITION_LATENCY FALSE +#define GET_PSTATE_REGISTER_INFO FALSE +#define GET_PSTATE_MAX_STATE FALSE +#define SET_PSTATE_LEVELING_REG FALSE +#define GET_NB_FREQ FALSE +#define IS_NBCOF_INIT_NEEDED FALSE +#define IS_NB_PSTATE_ENABLED FALSE +#define AP_INITIAL_LAUNCH FALSE +#define GET_AP_MAILBOX_FROM_HW FALSE +#define SET_AP_CORE_NUMBER FALSE +#define GET_AP_CORE_NUMBER FALSE +#define TRANSFER_AP_CORE_NUMBER FALSE +#define ID_POSITION_INITIAL_APICID FALSE +#define SAVE_FEATURES FALSE +#define WRITE_FEATURES FALSE +#define SET_DOWN_CORE_REG FALSE +#define SET_WARM_RESET_FLAG FALSE +#define GET_WARM_RESET_FLAG FALSE +#define USES_REGISTER_TABLES FALSE +#define BASE_FAMILY_PCI FALSE +#define MODEL_SPECIFIC_PCI FALSE +#define BASE_FAMILY_MSR FALSE +#define MODEL_SPECIFIC_MSR FALSE +#define BRAND_STRING1 FALSE +#define BRAND_STRING2 FALSE +#define BASE_FAMILY_HT_PCI FALSE +#define MODEL_SPECIFIC_HT_PCI FALSE +#define GET_PATCHES FALSE +#define GET_PATCHES_EQUIVALENCE_TABLE FALSE +#define GET_CACHE_INFO FALSE +#define GET_SYSTEM_PM_TABLE FALSE +#define GET_WHEA_INIT FALSE +#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE + +#if AGESA_ENTRY_INIT_RESET == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef GET_AP_MAILBOX_FROM_HW + #define GET_AP_MAILBOX_FROM_HW TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef TRANSFER_AP_CORE_NUMBER + #define TRANSFER_AP_CORE_NUMBER TRUE +#endif + +#if AGESA_ENTRY_INIT_RECOVERY == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef USES_REGISTER_TABLES + #define USES_REGISTER_TABLES TRUE + #undef BASE_FAMILY_PCI + #define BASE_FAMILY_PCI TRUE + #undef MODEL_SPECIFIC_PCI + #define MODEL_SPECIFIC_PCI TRUE + #undef BASE_FAMILY_MSR + #define BASE_FAMILY_MSR TRUE + #undef MODEL_SPECIFIC_MSR + #define MODEL_SPECIFIC_MSR TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_EARLY == TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PROC_IDD_MAX + #define PROC_IDD_MAX TRUE + #undef GET_TSC_RATE + #define GET_TSC_RATE TRUE + #undef GET_NB_FREQ + #define GET_NB_FREQ TRUE + #undef IS_NBCOF_INIT_NEEDED + #define IS_NBCOF_INIT_NEEDED TRUE + #undef AP_INITIAL_LAUNCH + #define AP_INITIAL_LAUNCH TRUE + #undef GET_AP_MAILBOX_FROM_HW + #define GET_AP_MAILBOX_FROM_HW TRUE + #undef SET_AP_CORE_NUMBER + #define SET_AP_CORE_NUMBER TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef TRANSFER_AP_CORE_NUMBER + #define TRANSFER_AP_CORE_NUMBER TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef SET_DOWN_CORE_REG + #define SET_DOWN_CORE_REG TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef USES_REGISTER_TABLES + #define USES_REGISTER_TABLES TRUE + #undef BASE_FAMILY_PCI + #define BASE_FAMILY_PCI TRUE + #undef MODEL_SPECIFIC_PCI + #define MODEL_SPECIFIC_PCI TRUE + #undef BASE_FAMILY_MSR + #define BASE_FAMILY_MSR TRUE + #undef MODEL_SPECIFIC_MSR + #define MODEL_SPECIFIC_MSR TRUE + #undef BRAND_STRING1 + #define BRAND_STRING1 TRUE + #undef BRAND_STRING2 + #define BRAND_STRING2 TRUE + #undef BASE_FAMILY_HT_PCI + #define BASE_FAMILY_HT_PCI TRUE + #undef MODEL_SPECIFIC_HT_PCI + #define MODEL_SPECIFIC_HT_PCI TRUE + #undef GET_PATCHES + #define GET_PATCHES TRUE + #undef GET_PATCHES_EQUIVALENCE_TABLE + #define GET_PATCHES_EQUIVALENCE_TABLE TRUE + #undef GET_SYSTEM_PM_TABLE + #define GET_SYSTEM_PM_TABLE TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_POST == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef GET_PSTATE_POWER + #define GET_PSTATE_POWER TRUE + #undef GET_PSTATE_FREQ + #define GET_PSTATE_FREQ TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PROC_IDD_MAX + #define PROC_IDD_MAX TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef GET_PSTATE_REGISTER_INFO + #define GET_PSTATE_REGISTER_INFO TRUE + #undef GET_PSTATE_MAX_STATE + #define GET_PSTATE_MAX_STATE TRUE + #undef SET_PSTATE_LEVELING_REG + #define SET_PSTATE_LEVELING_REG TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef SAVE_FEATURES + #define SAVE_FEATURES TRUE + #undef WRITE_FEATURES + #define WRITE_FEATURES TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_ENV == TRUE +#endif + +#if AGESA_ENTRY_INIT_MID == TRUE +#endif + +#if AGESA_ENTRY_INIT_LATE == TRUE + #undef GET_PSTATE_FREQ + #define GET_PSTATE_FREQ TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PSTATE_TRANSITION_LATENCY + #define PSTATE_TRANSITION_LATENCY TRUE + #undef GET_WHEA_INIT + #define GET_WHEA_INIT TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE +#endif + +#if AGESA_ENTRY_INIT_S3SAVE == TRUE +#endif + +#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE +#endif + +#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE +#endif + +// Initialize family mask for the PCI MMIO MSR to 0 +#define FAMILY_MMIO_BASE_MASK (0ull) + +/***************************************************************************** + * + * Include the structure definitions for the defaults table structures + * + ****************************************************************************/ +#include "OptionFamily10h.h" +#include "OptionFamily10hBlInstall.h" +#include "OptionFamily10hDaInstall.h" +#include "OptionFamily10hHyInstall.h" +#include "OptionFamily10hRbInstall.h" +#include "OptionFamily10hInstall.h" +#include "Options.h" +#include "OptionsHt.h" +#include "OptionHtInstall.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "OptionMemoryInstall.h" +#include "OptionMemoryRecovery.h" +#include "OptionMemoryRecoveryInstall.h" +#include "OptionDmi.h" +#include "OptionDmiInstall.h" +#include "OptionPstate.h" +#include "OptionPstateInstall.h" +#include "OptionWhea.h" +#include "OptionWheaInstall.h" +#include "OptionSrat.h" +#include "OptionSratInstall.h" +#include "OptionSlit.h" +#include "OptionSlitInstall.h" +#include "OptionMultiSocket.h" +#include "OptionMultiSocketInstall.h" +#include "OptionCpuFeaturesInstall.h" +#include "OptionIdsInstall.h" +#include "OptionS3ScriptInstall.h" +#if (AGESA_ENTRY_INIT_EARLY == TRUE) + #include "OptionDragonMicrocodeInstall.h" +#endif + +// If size is 0, but base is not, break the build. +#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0) + #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 +#endif + +// If base is 0, but size is not, break the build. +#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0) + #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater +#endif + +#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0) + // Both are non-zero, begin further processing. + + // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB. + #if (CFG_PCI_MMIO_BASE < 0x800000) + #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater + #endif + + // Break the build if the address is too high for the enabled families. + #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0) + #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families + #endif + + // If the size parameter is not valid, break the build. + #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16) + #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256) + #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 + #endif + #endif + + #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1) + // If the base is not aligned according to size, break the build. + #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0) + #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size + #endif + #undef PCI_MMIO_ALIGNMENT +#endif + + +/***************************************************************************** + * + * Generate the output structures (defaults tables) + * + ****************************************************************************/ +#ifndef ADVCFG_PLATFORM_SOCKETS + #error BLDOPT Set Family supported sockets. +#endif +#ifndef ADVCFG_PLATFORM_MODULES + #error BLDOPT Set Family supported modules. +#endif + + +BUILD_OPT_CFG UserOptions = { + { // AGESA version string + AGESA_CODE_SIGNATURE, // code header Signature + AGESA_PACKAGE_STRING, // 8 character ID + AGESA_VERSION_STRING, // 12 character version string + 0 // null string terminator + }, + //Build Option Area + OPTION_UDIMMS, //UDIMMS + OPTION_RDIMMS, //RDIMMS + OPTION_ECC, //ECC + OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE + OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE + OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE + OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING + OPTION_ONLINE_SPARE, //ONLINE_SPARE + OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE + OPTION_MULTISOCKET, //MULTISOCKET + OPTION_ACPI_PSTATES, //ACPI_PSTATES + OPTION_SRAT, //SRAT + OPTION_SLIT, //SLIT + OPTION_WHEA, //WHEA + OPTION_DMI, //DMI + OPTION_EARLY_SAMPLES, //EARLY_SAMPLES + OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR + + //Build Configuration Area + CFG_PCI_MMIO_BASE, + CFG_PCI_MMIO_SIZE, + { + CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit + CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold + CFG_VRM_SLEW_RATE, // VrmSlewRate + CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay + CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable + CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit + }, + CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber + CFG_MEM_INIT_PSTATE, //MemoryInitPstate + CFG_C1E_MODE, //C1eMode + CFG_C1E_OPDATA, //C1ePlatformData + CFG_CSTATE_MODE, //CStateMode + CFG_CSTATE_OPDATA, //CStatePlatformData + CFG_CORE_LEVELING_MODE, //CoreLevelingCofig + { + CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode. + CFG_USE_HT_ASSIST, // CfgUseHtAssist + CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets. + CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority. + CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode. + }, + (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings + CFG_AMD_PLATFORM_TYPE, //AmdPlatformType + CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck + + CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit + CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged + CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable + CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType + CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable + CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable + CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable + CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb + CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving + CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving + CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving + CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown + CFG_POWER_DOWN_MODE, // CfgPowerDownMode + CFG_ONLINE_SPARE, // CfgOnlineSpare + CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable + CFG_BANK_SWIZZLE, // CfgBankSwizzle + CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect + CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect + CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl + CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum + CFG_USE_BURST_MODE, // CfgUseBurstMode + CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn + CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature + CFG_ECC_REDIRECTION, // CfgEccRedirection + CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate + CFG_SCRUB_L2_RATE, // CfgScrubL2Rate + CFG_SCRUB_L3_RATE, // CfgScrubL3Rate + CFG_SCRUB_IC_RATE, // CfgScrubIcRate + CFG_SCRUB_DC_RATE, // CfgScrubDcRate + CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood + CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize + CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress + CFG_1GB_ALIGN, // CfgNodeMem1GBAlign + CFG_S3_LATE_RESTORE, // CfgS3LateRestore + CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent + (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList + CFG_UMA_MODE, // CfgUmaMode + CFG_UMA_SIZE, // CfgUmaSize + CFG_UMA_ABOVE4G, // CfgUmaAbove4G + CFG_UMA_ALIGNMENT, // CfgUmaAlignment + CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb + CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0 + CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1 + CFG_GNB_HD_AUDIO, // CfgGnbHdAudio + CFG_ABM_SUPPORT, // CfgAbmSupport + CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate + CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl + CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress + + 0, //reserved... +}; + +/// @todo, hmmm options.c override? multisocket == false? Look broken. +CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration = +{ + ADVCFG_PLATFORM_SOCKETS, + ADVCFG_PLATFORM_MODULES +}; + +CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] = +{ + OPT_F10_ID_TABLE +}; + +CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable = +{ + (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)), + CpuSupportedFamilyIdArray +}; + +CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = +{ + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, + sizeof (AMD_RESET_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResetConstructor, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_RESET_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, + sizeof (AMD_RECOVERY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, + sizeof (AMD_EARLY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_EARLY_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, + sizeof (AMD_ENV_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEnvInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_ENV_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, + sizeof (AMD_LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdInitLateInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, + AMD_INIT_LATE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, + sizeof (AMD_MID_PARAMS), + (PF_AGESA_FUNCTION) AmdInitMidInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_MID_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, + sizeof (AMD_POST_PARAMS), + (PF_AGESA_FUNCTION) AmdInitPostInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, + sizeof (AMD_RESUME_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResumeInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, + AMD_INIT_RESUME_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, + sizeof (AMD_S3LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_S3_LATE_RESTORE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, + sizeof (AMD_S3SAVE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3SaveInitializer, + (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, + AMD_S3_SAVE_HANDLE + }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, + sizeof (AP_EXE_PARAMS), + (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_LATE_RUN_AP_TASK_HANDLE + }, + #endif + { 0, NULL } +}; + +CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); + +CONST DISPATCH_TABLE ROMDATA DispatchTable[] = +{ + { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, + { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, + + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, + #endif + + #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, + { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, + { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, + { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, + { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, + #endif + { 0, NULL } +}; + +CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = +{ + IDS_LATE_RUN_AP_TASK + // Get DMI info + + // Probe filter enable + + { 0, NULL } +}; + +CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] = +{ + &F10BrandIdString1ArrayAm3 +}; + +CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] = +{ + &F10BrandIdString2ArrayAm3 +}; + +CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0])); +CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0])); diff --git a/src/vendorcode/amd/agesa/f10/Include/Filecode.h b/src/vendorcode/amd/agesa/f10/Include/Filecode.h new file mode 100755 index 0000000..b189398 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Include/Filecode.h @@ -0,0 +1,547 @@ +/** + * @file + * + * Collectively assign unique filecodes for assert and debug to each source file. + * + * Publish values for decorated filenames, which can be used for + * ASSERT and debug support using a preprocessor define like: + * @n \#define FILECODE MY_C_FILENAME_FILECODE @n + * This file serves as a reference for debugging to associate the code and filename. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + +#ifndef _FILECODE_H_ +#define _FILECODE_H_ + +#define UNASSIGNED_FILE_FILECODE (0xFFFF) + +/// For debug use in any Platform's options C file. +/// Can be reused for platforms and image builds, since only one options file can be built. +#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB) + +#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA001) +#define PROC_GNB_GNBINITATENV_FILECODE (0xA002) +#define PROC_GNB_GNBINITATLATE_FILECODE (0xA003) +#define PROC_GNB_GNBINITATMID_FILECODE (0xA004) +#define PROC_GNB_GNBINITATPOST_FILECODE (0xA005) +#define PROC_GNB_GNBINITATRESET_FILECODE (0xA006) +#define PROC_GNB_COMMON_CPUACCLIB_FILECODE (0xA010) +#define PROC_GNB_COMMON_GNBHEAPLIB_FILECODE (0xA011) +#define PROC_GNB_COMMON_GNBLIB_FILECODE (0xA012) +#define PROC_GNB_COMMON_MEMACCLIB_FILECODE (0xA013) +#define PROC_GNB_COMMON_PCIACCLIB_FILECODE (0xA014) +#define PROC_GNB_COMMON_PCILIB_FILECODE (0xA015) +#define PROC_GNB_COMMON_IOACCLIB_FILECODE (0xA016) +#define PROC_GNB_GFX_GFXCARDINFO_FILECODE (0xA020) +#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE (0xA021) +#define PROC_GNB_GFX_GFXGMCINIT_FILECODE (0xA022) +#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE (0xA023) +#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE (0xA024) +#define PROC_GNB_GFX_GFXINITATPOST_FILECODE (0xA025) +#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE (0xA026) +#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE (0xA027) +#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE (0xA028) +#define PROC_GNB_GFX_FAMILY_0X12_F12GFXSERVICES_FILECODE (0xA029) +#define PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE (0xA02A) +#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA030) +#define PROC_GNB_NB_NBINIT_FILECODE (0xA031) +#define PROC_GNB_NB_NBINITATEARLY_FILECODE (0xA032) +#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE (0xA033) +#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA034) +#define PROC_GNB_NB_NBINITATENV_FILECODE (0xA035) +#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA036) +#define PROC_GNB_NB_NBSMUSERVICES_FILECODE (0xA037) +#define PROC_GNB_NB_FAMILY_0X12_F12NBSERVICES_FILECODE (0xA038) +#define PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE (0xA039) +#define PROC_GNB_PCIE_PCIECONFIGDATA_FILECODE (0xA041) +#define PROC_GNB_PCIE_PCIEINIT_FILECODE (0xA043) +#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE (0xA044) +#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE (0xA045) +#define PROC_GNB_PCIE_PCIEINPUTPARSER_FILECODE (0xA046) +#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE (0xA047) +#define PROC_GNB_PCIE_PCIEMAPTOPOLOGY_FILECODE (0xA048) +#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE (0xA049) +#define PROC_GNB_PCIE_PCIEPIFSERVICES_FILECODE (0xA04A) +#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE (0xA04B) +#define PROC_GNB_PCIE_PCIEPORTREGACC_FILECODE (0xA04C) +#define PROC_GNB_PCIE_PCIETIMER_FILECODE (0xA04D) +#define PROC_GNB_PCIE_PCIETOPOLOGYSERVICES_FILECODE (0xA04E) +#define PROC_GNB_PCIE_PCIETRAINING_FILECODE (0xA04F) +#define PROC_GNB_PCIE_PCIEUTILITYLIB_FILECODE (0xA050) +#define PROC_GNB_PCIE_PCIEWRAPPERREGACC_FILECODE (0xA051) +#define PROC_GNB_PCIE_PCIEPOWERSAVINGFEATURES_FILECODE (0xA052) +#define PROC_GNB_PCIE_PCIESBLINK_FILECODE (0xA053) +#define PROC_GNB_PCIE_PCIEWORKAROUNDS_FILECODE (0xA054) +#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE (0xA060) +#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXSERVICES_FILECODE (0xA061) +#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPHYSERVICES_FILECODE (0xA062) +#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEWRAPPERSERVICES_FILECODE (0xA063) +#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE (0xA070) +#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE (0xA071) +#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE (0xA072) +#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE (0xA073) +#define PROC_GNB_PCIE_FEATURE_PCIEASPM_FILECODE (0xA074) +#define PROC_GNB_PCIE_FEATURE_PCIEASPMEXITLATENCY_FILECODE (0xA075) +#define PROC_GNB_GFX_GFXPOWERPLAYTABLE_FILECODE (0xA076) +#define PROC_GNB_GFX_GFXFUSETABLEINIT_FILECODE (0xA077) +#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA078) + +#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01) +#define PROC_RECOVERY_GNB_GFXRECOVERY_FILECODE (0xAE02) +#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE03) + +#define LIB_AMDLIB_FILECODE (0xC001) + +#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010) +#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011) +#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012) + +#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120) +#define UEFI_DXE_AMDAGESAS3DRIVER_AMDAGESAS3DRIVER_FILECODE (0xC121) +#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140) +#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141) +#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142) +#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE (0xC162) + +#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020) +#define PROC_COMMON_AMDINITENV_FILECODE (0xC021) +#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022) +#define PROC_COMMON_AMDINITMID_FILECODE (0xC023) +#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024) +#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025) +#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026) +#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027) +#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028) +#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029) +#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A) + +#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0) +#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0) +#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0) +#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8) +#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9) + +#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401) +#define PROC_CPU_CPUBRANDID_FILECODE (0xC402) +#define PROC_CPU_TABLE_FILECODE (0xC403) +#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405) +#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406) +#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407) +#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408) +#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC409) +#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A) +#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B) +#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C) +#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D) +#define PROC_CPU_CPUBIST_FILECODE (0xC40E) + +#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420) +#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430) +#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431) +#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432) +#define PROC_CPU_S3_FILECODE (0xC460) + +#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE (0xC801) +#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE (0xC802) +#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE (0xC803) +#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE (0xC804) +#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE (0xC805) +#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE (0xC806) +#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE (0xC807) +#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE (0xC808) +#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE (0xC809) +#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE (0xC80A) +#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE (0xC80B) +#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE (0xC80C) +#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE (0xC80D) +#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE (0xC80E) +#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE (0xC80F) +#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE (0xC810) +#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE (0xC827) +#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE (0xC811) +#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE (0xC812) +#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE (0xC813) +#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE (0xC814) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE (0xC815) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE (0xC816) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE (0xC81A) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE (0xC81B) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE (0xC81C) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE (0xC820) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE (0xC821) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE (0xC822) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE (0xC823) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE (0xC824) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE (0xC825) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE (0xC826) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE (0xC830) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE (0xC831) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE (0xC832) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE (0xC833) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE (0xC834) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE (0xC835) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE (0xC836) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE (0xC850) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE (0xC851) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE (0xC852) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE (0xC853) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE (0xC854) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE (0xC855) +#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE (0xC817) +#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE (0xC818) +#define PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE (0xC819) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE (0xC840) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE (0xC841) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE (0xC842) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE (0xC843) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE (0xC844) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE (0xC845) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE (0xC846) +#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE (0XC901) +#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE (0XC902) +#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE (0XC903) +#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE (0XC904) +#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE (0xC906) +#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE (0xC907) +#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE (0XC908) +#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE (0XC909) +#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE (0XC90A) +#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE (0XC90B) +#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE (0XC90C) +#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE (0XC90D) +#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE (0XC90E) +#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE (0XC90F) +#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE (0xC921) +#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE (0xC922) +#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE (0xC923) +#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE (0XCA01) +#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE (0XCA02) +#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE (0XCA03) +#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE (0XCA04) +#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE (0xCA06) +#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE (0xCA07) +#define PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE (0XCA08) +#define PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE (0XCA09) +#define PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE (0XCA0A) +#define PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE (0XCA0B) +#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE (0XCA0C) +#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE (0XCA0D) +#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0XCA0E) +#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA21) +#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA22) +#define PROC_CPU_FAMILY_0X14_ON_F14ONMSRTABLES_FILECODE (0xCA23) +#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA24) +#define PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE (0xCA25) + +#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01) +#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02) +#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10) +#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20) +#define PROC_CPU_FEATURE_CPUHTASSIST_FILECODE (0xDC30) +#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41) +#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42) +#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43) +#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50) +#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60) +#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70) +#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE (0xDC80) +#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC81) +#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90) +#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0) +#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0) +#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0) + +#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01) + +#define PROC_HT_FEATURES_HTFEATSETS_FILECODE (0xE001) +#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE (0xE002) +#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE (0xE003) +#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE (0xE004) +#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE (0xE005) +#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE (0xE006) +#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE (0xE007) +#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE (0xE008) +#define PROC_HT_FEATURES_HTIDS_FILECODE (0xE009) +#define PROC_HT_HTFEAT_FILECODE (0xE021) +#define PROC_HT_HTINTERFACE_FILECODE (0xE022) +#define PROC_HT_HTINTERFACECOHERENT_FILECODE (0xE023) +#define PROC_HT_HTINTERFACEGENERAL_FILECODE (0xE024) +#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE (0xE025) +#define PROC_HT_HTMAIN_FILECODE (0xE026) +#define PROC_HT_HTNOTIFY_FILECODE (0xE027) +#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE (0xE028) +#define PROC_HT_HTNB_FILECODE (0xE081) +#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE (0xE082) +#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE (0xE083) +#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE (0xE084) +#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE (0xE085) +#define PROC_HT_FAM10_HTNBFAM10_FILECODE (0xE0C1) +#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE (0xE0C2) +#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE (0xE0C3) +#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE (0xE0C4) +#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE (0xE0C5) +#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE (0xE0C6) +#define PROC_HT_FAM12_HTNBFAM12_FILECODE (0xE101) +#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE (0xE102) +#define PROC_HT_FAM14_HTNBFAM14_FILECODE (0xE141) +#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE (0xE142) + +#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE (0xE302) +#define PROC_RECOVERY_HT_HTINITRESET_FILECODE (0xE301) + +#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801) +#define PROC_IDS_CONTROL_IDSLIB_FILECODE (0xE802) +#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803) +#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804) +#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE (0xE805) +#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE (0xE806) +#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE (0xE807) +#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE (0xE808) +#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE (0xE809) +#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE (0xE80A) +#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE (0xE80B) + +#define PROC_MEM_ARDK_MA_FILECODE (0xF001) +#define PROC_MEM_ARDK_DR_MARDR2_FILECODE (0xF002) +#define PROC_MEM_ARDK_DR_MARDR3_FILECODE (0xF003) +#define PROC_MEM_ARDK_HY_MARHY3_FILECODE (0xF004) +#define PROC_MEM_ARDK_LN_MASLN3_FILECODE (0xF005) +#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE (0xF006) +#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE (0xF007) +#define PROC_MEM_ARDK_LN_MAULN3_FILECODE (0xF008) +#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE (0xF009) +#define PROC_MEM_ARDK_DA_MASDA2_FILECODE (0xF00A) +#define PROC_MEM_ARDK_DA_MASDA3_FILECODE (0xF00B) +#define PROC_MEM_ARDK_NI_MASNI3_FILECODE (0xF00C) +#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE (0xF00D) +#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE (0xF00E) +#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE (0xF00F) +#define PROC_MEM_ARDK_ON_MASON3_FILECODE (0xF010) +#define PROC_MEM_ARDK_ON_MAUON3_FILECODE (0xF011) + +#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081) +#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082) +#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083) +#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085) +#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086) +#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088) +#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089) +#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A) +#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B) +#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C) +#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D) +#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E) +#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F) +#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091) +#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092) +#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093) + +#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101) +#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102) +#define PROC_MEM_MAIN_MM_FILECODE (0xF103) +#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104) +#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105) +#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106) +#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE (0xF107) +#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE (0xF108) +#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE (0xF109) +#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE (0xF10A) +#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B) +#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C) +#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D) +#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E) +#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F) +#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110) +#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE (0xF111) +#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112) +#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113) +#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE (0xF114) +#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115) +#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116) +#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117) +#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118) + +#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213) +#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214) +#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216) +#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217) +#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218) +#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219) +#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A) +#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C) +#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D) +#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E) +#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233) +#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235) +#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236) +#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237) +#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238) +#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239) +#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A) +#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B) +#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C) +#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D) +#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E) +#define PROC_MEM_NB_ON_MNON_FILECODE (0xF240) +#define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241) +#define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242) +#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE (0xF244) +#define PROC_MEM_NB_ON_MNMCTON_FILECODE (0xF245) +#define PROC_MEM_NB_ON_MNOTON_FILECODE (0xF246) +#define PROC_MEM_NB_ON_MNPHYON_FILECODE (0xF247) +#define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248) +#define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249) +#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252) +#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253) +#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254) +#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255) +#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256) +#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257) +#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258) +#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259) +#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A) +#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B) +#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260) +#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261) +#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263) +#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264) +#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265) +#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266) +#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267) +#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269) +#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A) +#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B) +#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C) +#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D) +#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E) +#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F) +#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270) +#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271) +#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272) +#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273) +#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274) +#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275) +#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277) +#define PROC_MEM_NB_MN_FILECODE (0XF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0XF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) +#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) +#define PROC_MEM_NB_MNREG_FILECODE (0XF285) +#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286) +#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287) + +#define PROC_MEM_PS_MP_FILECODE (0XF401) +#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402) +#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403) +#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404) +#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405) +#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406) +#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407) +#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408) +#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409) +#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A) +#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B) +#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C) +#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D) +#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E) +#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F) +#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410) +#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411) +#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412) +#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413) +#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414) +#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415) + +#define PROC_MEM_TECH_MT_FILECODE (0XF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) +#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541) +#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543) +#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) + +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) +#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812) +#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813) +#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821) +#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822) +#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823) +#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825) +#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831) +#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832) +#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833) +#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842) +#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843) +#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845) +#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851) +#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852) +#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853) +#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861) +#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862) +#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) + +#endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f10/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f10/Include/GeneralServices.h new file mode 100755 index 0000000..1821fe3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Include/GeneralServices.h @@ -0,0 +1,200 @@ +/** + * @file + * + * General Services + * + * Provides Services similar to the external General Services API, except + * suited to use within AGESA components. Socket, Core and PCI identification. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#ifndef _GENERAL_SERVICES_H_ +#define _GENERAL_SERVICES_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define NUMBER_OF_EVENT_DATA_PARAMS 4 + +/** + * AMD Device id for MMIO check. + */ +#define AMD_DEV_VEN_ID 0x1022 +#define AMD_DEV_VEN_ID_ADDRESS 0 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +/** + * An AGESA Event Log entry. + */ +typedef struct { + AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS. + UINT32 EventInfo; ///< Uniquely identifies the event. + UINT32 DataParam1; ///< Event specific additional data + UINT32 DataParam2; ///< Event specific additional data + UINT32 DataParam3; ///< Event specific additional data + UINT32 DataParam4; ///< Event specific additional data +} AGESA_EVENT; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +/** + * Get a specified Core's APIC ID. + * + * @param[in] StdHeader Header for library and services. + * @param[in] Socket The Core's Socket. + * @param[in] Core The Core id. + * @param[out] ApicAddress The Core's APIC ID. + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + * @retval TRUE The core is present, APIC Id valid + * @retval FALSE The core is not present, APIC Id not valid. + */ +BOOLEAN +GetApicId ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 Socket, + IN UINT32 Core, + OUT UINT8 *ApicAddress, + OUT AGESA_STATUS *AgesaStatus +); + +/** + * Get Processor Module's PCI Config Space address. + * + * @param[in] StdHeader Header for library and services. + * @param[in] Socket The Core's Socket. + * @param[in] Module The Module in that Processor + * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + * @retval TRUE The core is present, PCI Address valid + * @retval FALSE The core is not present, PCI Address not valid. + */ +BOOLEAN +GetPciAddress ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 Socket, + IN UINT32 Module, + OUT PCI_ADDR *PciAddress, + OUT AGESA_STATUS *AgesaStatus +); + +/** + * "Who am I" for the current running core. + * + * @param[in] StdHeader Header for library and services. + * @param[out] Socket The current Core's Socket + * @param[out] Module The current Core's Processor Module + * @param[out] Core The current Core's core id. + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + */ +VOID +IdentifyCore ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT UINT32 *Socket, + OUT UINT32 *Module, + OUT UINT32 *Core, + OUT AGESA_STATUS *AgesaStatus +); + +/** + * A boolean function determine executed CPU is BSP core. + */ +BOOLEAN +IsBsp ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + OUT AGESA_STATUS *AgesaStatus + ); + +/** + * This function logs AGESA events into the event log. + */ +VOID +PutEventLog ( + IN AGESA_STATUS EventClass, + IN UINT32 EventInfo, + IN UINT32 DataParam1, + IN UINT32 DataParam2, + IN UINT32 DataParam3, + IN UINT32 DataParam4, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function gets event logs from the circular buffer. + */ +AGESA_STATUS +GetEventLog ( + OUT AGESA_EVENT *EventRecord, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function gets event logs from the circular buffer without flushing the entry. + */ +BOOLEAN +PeekEventLog ( + OUT AGESA_EVENT *EventRecord, + IN UINT16 Index, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * This routine programs the registers necessary to get the PCI MMIO mechanism + * up and functioning. + */ +VOID +InitializePciMmio ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif // _GENERAL_SERVICES_H_ diff --git a/src/vendorcode/amd/agesa/f10/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f10/Include/GnbInterface.h new file mode 100755 index 0000000..92f76e6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Include/GnbInterface.h @@ -0,0 +1,87 @@ +/** + * @file + * + * GNB API definition. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 20270 $ @e \$Date: 2009-10-09 10:09:20 -0700 (Fri, 09 Oct 2009) $ + * + */ +/* +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +#ifndef _GNBINTERFACE_H_ +#define _GNBINTERFACE_H_ + +AGESA_STATUS +GnbInitAtReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbInitAtEarly ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN GNB_CONFIGURATION *GnbConfig + ); + +AGESA_STATUS +GnbInitAtPost ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT MEM_PARAMETER_STRUCT *MemConfig + ); + +AGESA_STATUS +GnbInitAtEnv ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbInitAtMid ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbInitAtLate ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +AmdGnbRecovery ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f10/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f10/Include/GnbInterfaceStub.h new file mode 100755 index 0000000..cd06927 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Include/GnbInterfaceStub.h @@ -0,0 +1,202 @@ +/** + * @file + * + * + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 20379 $ @e \$Date: 2009-10-12 23:41:06 -0700 (Mon, 12 Oct 2009) $ + * + */ +/* +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Reset Stub + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GnbInitAtReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Early Stub + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] PlatformConfig Platform configuration + * @param[in] GnbConfig Gnb configuration + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GnbInitAtEarly ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN GNB_CONFIGURATION *GnbConfig + ) +{ + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Env + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GnbInitAtEnv ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Reset + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in,out] MemConfig Memory configuration + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GnbInitAtPost ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT MEM_PARAMETER_STRUCT *MemConfig + ) +{ + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Mid post + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GnbInitAtMid ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Late post + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GnbInitAtLate ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * AmdGnbRecovery + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ +AGESA_STATUS +AmdGnbRecovery ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return AGESA_SUCCESS; +} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f10/Include/Ids.h b/src/vendorcode/amd/agesa/f10/Include/Ids.h new file mode 100755 index 0000000..5de4415 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Include/Ids.h @@ -0,0 +1,791 @@ +/** + * @file + * + * AMD IDS Routines + * + * Contains AMD AGESA Integrated Debug Macros + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: $ @e \$Date: 2008-04-07 15:08:45 -0500 (Mon, 07 Apr 2008) $ + */ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + + /* Macros to aid debugging */ + /* These definitions expand to zero (0) bytes of code when disabled */ + +#ifndef _IDS_H_ +#define _IDS_H_ + +#undef FALSE +#undef TRUE +#define FALSE 0 +#define TRUE 1 +// Proto type for optionsids.h +typedef UINT32 IDS_STATUS; ///< Status of IDS function. +#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful. +#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed. + +#define IDS_STRINGIZE(a) #a ///< for define stringize macro +/** + * IDS Option Hook Points + * + * These are the values to indicate hook point in AGESA for IDS Options. + * + */ +typedef enum { //vv- for debug reference only + IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY. + ///< IDS Object is initialized. + ///< Override CPU Core Leveling Mode. + ///< Set P-State in Post + IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY. + IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE. + ///< It will be used to control the following tables. + ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC) + ///< ACPI SRAT Table + ///< ACPI SLIT Table + ///< ACPI WHEA Table + ///< DMI Table + IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE. + IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID. + IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID. + IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST. + ///< Control Interleaving and DRAM memory hole + ///< Override the setting of ECC Control + ///< Override the setting of Online Spare Rank + IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST. + IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET. + IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET. + IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST. + IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save. + IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore + IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save + IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore + IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training + IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization + IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change + IDS_AFTER_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset + IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init + IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init + IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS + IDS_UCODE, ///< 16 Enable or Disable microcode patching + + IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used + + // All the above timing point is used by BVM, their value should never be changed + IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control + IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP# + IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing + ///< Dram Controller, Drive Strength and DQS Timing + IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing + IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged + IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode + IDS_BURST_LENGTH32, ///< 46 override Burst Length32 + IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable + IDS_ECC, ///< 48 override ECC parameter + IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size + IDS_CPU_Early_Override, ///< 4a override CPU early parameter + IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt + IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave + IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery + IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times + IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit + IDS_HT_ASSIST, ///< 50 Override Probe Filter + IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result + IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down + IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement + IDS_PHY_DLL_STANDBY_CNTRL, ///< 54 Enable/Disable Phy DLL standby feature + IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure + IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support + IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory + IDS_GNB_PPFUSE_OVERRIDE, ///< 58 override GNB default PowerPlay fuse table + IDS_GNB_INTEGRATED_TABLE_CONFIG, ///<59 override GNB integrated table config + IDS_GNB_SMU_SERVICE_CONFIG, ///< 5a Config GNB SMU service + IDS_GNB_PCIE_PLATFORM_CONFIG, ///< 5b Config PCIE platform + IDS_GNB_ORBDYNAMIC_WAKE, ///< 5c config GNB dynamic wake + IDS_GNB_PLATFORMCFG_OVERRIDE ///< 5d override ids gnb platform config +} AGESA_IDS_OPTION; + +#include "OptionsIds.h" +#include "Filecode.h" + +/* Initialize IDS controls */ +#ifndef IDSOPT_IDS_ENABLED + #define IDSOPT_IDS_ENABLED FALSE +#endif + +#ifndef IDSOPT_CONTROL_ENABLED + #define IDSOPT_CONTROL_ENABLED FALSE +#endif + +#ifndef IDSOPT_TRACING_ENABLED + #define IDSOPT_TRACING_ENABLED FALSE +#endif + +#ifndef IDSOPT_PERF_ANALYSIS + #define IDSOPT_PERF_ANALYSIS FALSE +#endif + +#ifndef IDSOPT_HEAP_CHECKING + #define IDSOPT_HEAP_CHECKING FALSE +#endif + +#ifndef IDSOPT_ASSERT_ENABLED + #define IDSOPT_ASSERT_ENABLED FALSE +#endif + +#ifndef IDSOPT_ERROR_TRAP_ENABLED + #define IDSOPT_ERROR_TRAP_ENABLED FALSE +#endif + +#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE +#endif + +#if IDSOPT_IDS_ENABLED == FALSE + #undef IDSOPT_CONTROL_ENABLED + #undef IDSOPT_TRACING_ENABLED + #undef IDSOPT_PERF_ANALYSIS + #undef IDSOPT_HEAP_CHECKING + #undef IDSOPT_ASSERT_ENABLED + #undef IDSOPT_ERROR_TRAP_ENABLED + #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + + #define IDSOPT_CONTROL_ENABLED FALSE + #define IDSOPT_TRACING_ENABLED FALSE + #define IDSOPT_PERF_ANALYSIS FALSE + #define IDSOPT_HEAP_CHECKING FALSE + #define IDSOPT_ASSERT_ENABLED FALSE + #define IDSOPT_ERROR_TRAP_ENABLED FALSE + #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE +#endif + +/** + * Make a Progress Report to the User. + * + * This Macro is always enabled. The default action is to write the TestPoint value + * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80. + * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port + * in OptionsIds.h in their build tip. + * + * @param[in] TestPoint The value for display indicating progress + * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS + * + **/ + +#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader)) + +#ifndef IDS_DEBUG_PORT + #define IDS_DEBUG_PORT 0x80 +#endif + +/** + * @def STOP_HERE + * (macro) - Causes program to halt. This is @b only for use during active debugging . + * + * Causes the program to halt and display the file number of the source of the + * halt (displayed in decimal). + * + **/ +#if IDSOPT_IDS_ENABLED == TRUE + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + #define STOP_HERE IdsErrorStop (STOP_CODE); +#else + #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds." +#endif + +/** + * @def ASSERT + * Test an assertion that the given statement is True. + * + * The statement is evaluated to a boolean value. If the statement is True, + * then no action is taken (no error). If the statement is False, a error stop + * is generated to halt the program. Used for testing for fatal errors that + * must be resolved before production. This is used to do parameter checks, + * bounds checking, range checks and 'sanity' checks. + * + * @param[in] conditional Assert that evaluating this conditional results in TRUE. + * + **/ +#ifndef ASSERT + #if IDSOPT_ASSERT_ENABLED == TRUE + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + + #define ASSERT(conditional) ((conditional) ? 0 : IdsErrorStop (STOP_CODE)); + #else + #define ASSERT(conditional) + #endif +#endif +#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE + #undef IDSOPT_ERROR_TRAP_ENABLED + #define IDSOPT_ERROR_TRAP_ENABLED TRUE + #define IDS_CAR_CORRUPTION_CHECK(StdHeader) //IdsCarCorruptionCheck(StdHeader) +#else + #define IDS_CAR_CORRUPTION_CHECK(StdHeader) +#endif + +/** + * @def IDS_ERROR_TRAP + * Trap AGESA Error events with stop code display. + * + * Works similarly to use of "ASSERT (FALSE);" + * + */ +#if IDSOPT_ERROR_TRAP_ENABLED == TRUE + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + + #define IDS_ERROR_TRAP IdsErrorStop (STOP_CODE) +#else + #define IDS_ERROR_TRAP +#endif + +///give the extended Macro default value +#ifndef __IDS_EXTENDED__ + #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS + #define IDS_INITIAL_F10_PM_STEP + #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader) + #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader) + #define IDS_EXTENDED_HEAP_SIZE 0 + #define IDS_EXT_INCLUDE_F10(file) + #define IDS_EXT_INCLUDE(file) +#endif + +#ifndef IDS_NUM_NV_ITEM + #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM) +#endif + +#if IDSOPT_CONTROL_ENABLED == TRUE + #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \ + AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader)) +#else + #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) +#endif + +/** + * Macro to add a *skip* hook for IDS options + * + * The default minimal action is to do nothing and there is no any code to increase. + * For debug environments, IDS dispatcher function will be called to perform + * the detailed action and to skip AGESA code if necessary. + * + * @param[in] IdsOption IDS Option ID for this hook point + * @param[in, out] DataPtr Data Pointer to override + * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS + * + * + **/ + +#if IDSOPT_CONTROL_ENABLED == TRUE + #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \ + if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS) +#else + #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) +#endif + +/** + * Macro to add a heap manager routine + * + * when memory is allocated the heap manager actually allocates two extra dwords of data, + * one dword buffer before the actual memory, and one dword afterwards. + * a complete heap walk and check to be performed at any time. + * it would ASSERT if the heap is corrupt + * + * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS + * + * + **/ + +// Heap debug feature +#if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_HEAP_CHECKING == TRUE + #define SIZE_OF_SENTINEL 4 + #define SENTINEL_BEFORE_VALUE 0xCCAA5533 + #define SENTINEL_AFTER_VALUE 0x3355AACC + #define SET_SENTINEL_BEFORE(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE)) = SENTINEL_BEFORE_VALUE); + #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + NodePtr->BufferSize) = SENTINEL_AFTER_VALUE); + #define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader) + #else + #define SIZE_OF_SENTINEL 0 + #define SENTINEL_BEFORE_VALUE 0xCCAA5533 + #define SENTINEL_AFTER_VALUE 0x3355AACC + #define SET_SENTINEL_BEFORE(NodePtr) + #define SET_SENTINEL_AFTER(NodePtr) + #define Heap_Check(stdheader) + #endif +#else + #define SIZE_OF_SENTINEL 0 + #define SENTINEL_BEFORE_VALUE 0xCCAA5533 + #define SENTINEL_AFTER_VALUE 0x3355AACC + #define SET_SENTINEL_BEFORE(NodePtr) + #define SET_SENTINEL_AFTER(NodePtr) + #define Heap_Check(stdheader) +#endif + +/** + * Macro to add HDT OUT in memory code. + * + * The default minimal action is to do nothing and there is no any code to increase. + * For debug environments, the debug information can be displayed in HDT or other + * devices. + * + * @param[in] Command HDT_OUT command to control the communication between + * HDT and memory initialization code. + * @param[in] Data Data to be sent to HDT. + * @param[in] Condition Allow the Data to be output if TRUE. + * @param[in] NvId NV ID to control this HDT OUT. + * @param[in,out] StdHeader The Pointer of AGESA Header. + * + **/ +#define OPTION_NON_CONSOLE 0xD0 +#define OPTION_HDT_CONSOLE 0xD1 +#define OPTION_IDS_CONSOLE OPTION_NON_CONSOLE +#if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_TRACING_ENABLED == TRUE + #undef OPTION_IDS_CONSOLE + #define OPTION_IDS_CONSOLE OPTION_HDT_CONSOLE + #define IDS_FUNCLIST_ADDR ScriptFuncList + #define IDS_FUNCLIST_EXTERN() extern SCRIPT_FUNCTION ScriptFuncList[] + #define IDS_TIMEOUT_CTL(t) IdsMemTimeOut (t) + + #define IDS_HDT_CONSOLE_INIT(x) + #define IDS_HDT_CONSOLE_EXIT(x) + #ifdef __GNUC__ + #if CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + #define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) + ///#define IDS_HDT_CONSOLE(f, s, args...) printk(((MEM_FLOW) - (f) + (BIOS_DEBUG)), s, ##args) + #else + #define IDS_HDT_CONSOLE(s, args...) + #endif + #else + #define IDS_HDT_CONSOLE(s, args...) + #endif + #else + #define IDS_HDT_CONSOLE_INIT(x) + #define IDS_HDT_CONSOLE_EXIT(x) + #define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsConsolePrint + #define IDS_FUNCLIST_ADDR NULL + #define IDS_FUNCLIST_EXTERN() + #define IDS_TIMEOUT_CTL(t) + #endif +#else + #define IDS_HDT_CONSOLE_INIT(x) + #define IDS_HDT_CONSOLE_EXIT(x) + #define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsConsolePrint + #define IDS_FUNCLIST_ADDR NULL + #define IDS_FUNCLIST_EXTERN() + #define IDS_TIMEOUT_CTL(t) +#endif + +#if IDSOPT_PERF_ANALYSIS == TRUE + #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) //IdsPerfTimestamp ((StdHeader), (TestPoint)) + #define IDS_PERF_ANALYSE(StdHeader) //IdsPerfAnalyseTimestamp (StdHeader) + #define IDS_PERF_TIME_MEASURE(StdHeader) //AGESA_TESTPOINT (TpPerfUnit, StdHeader); AGESA_TESTPOINT (TpPerfUnit, StdHeader); +#else + #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) + #define IDS_PERF_ANALYSE(StdHeader) + #define IDS_PERF_TIME_MEASURE(StdHeader) +#endif + +///For IDS feat use +#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull +#define IDS_BSP_ONLY TRUE +#define IDS_ALL_CORES FALSE + +#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE + +#define IDS_CALLOUT_INIT 1 ///< The function data of IDS callout function of initialization. + +/// Function entry for HDT script to call +typedef struct _SCRIPT_FUNCTION { + UINT32 FuncAddr; ///< Function address in ROM + CHAR8 FuncName[40]; ///< Function name +} SCRIPT_FUNCTION; + +/// Data Structure for Mem ECC parameter override +typedef struct { + IN BOOLEAN CfgEccRedirection; ///< ECC Redirection + IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate + IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate + IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate + IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate + IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate + IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood +} ECC_OVERRIDE_STRUCT; + + + + +/** + * AGESA Test Points + * + * These are the values displayed to the user to indicate progress through boot. + * These can be used in a debug environment to stop the debugger at a specific + * test point: + * For SimNow!, this command + * bi 81 w vb 49 + * will stop the debugger on one of the TracePoints (49 is the TP value in this example). + * + */ +typedef enum { + StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs + + // Memory test points + TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface) + TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface) + TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface) + TpProcMemDramInit, ///< 04 .. DRAM initialization + TpProcMemSPDChecking, ///< 05 .. + TpProcMemModeChecking, ///< 06 .. + TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration + TpProcMemSpdTiming, ///< 08 .. + TpProcMemDramMapping, ///< 09 .. + TpProcMemPlatformSpecificConfig, ///< 0A .. + TPProcMemPhyCompensation, ///< 0B .. + TpProcMemStartDcts, ///< 0C .. + TpProcMemBeforeDramInit, ///< 0D .. (Public interface) + TpProcMemPhyFenceTraining, ///< 0E .. + TpProcMemSynchronizeDcts, ///< 0F .. + TpProcMemSystemMemoryMapping, ///< 10 .. + TpProcMemMtrrConfiguration, ///< 11 .. + TpProcMemDramTraining, ///< 12 .. + TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface) + TpProcMemWriteLevelizationTraining, ///< 14 .. + TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start + TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start + TpProcMemWlDimmConfig, ///< 17 .. Target DIMM configured + TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL + TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL + TpProcMemReceiverEnableTraining, ///< 1A .. + TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop + TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay + TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern + TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern + TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern + TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel + TpProcMemReceiveDqsTraining, ///< 21 .. + TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay + TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern + TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep + TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay + TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern + TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern + TpProcMemRcvDqsResults, ///< 28 .. Update results + TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window + TpProcMemTransmitDqsTraining, ///< 2A .. + TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep + TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay + TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern + TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern + TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern + TpProcMemTxDqResults, ///< 30 .. Update results + TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window + TpProcMemMaxRdLatencyTraining, ///< 32 .. + TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep + TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay + TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern + TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern + TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern + TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init + TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init + TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init + TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init + TpProcMemEccInitialization, ///< 3C .. ECC initialization + TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init + TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd" + TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd" + TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit" + TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit" + TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining" + TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining" + TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit" + TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit" + TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit + TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT + TpProcMemLvDdr3, ///< 48 .. Before LV DDR3 + TpProcMemInitMCT, ///< 49 .. Before InitMCT + TpProcMemOtherTiming, ///< 4A.. Before OtherTiming + TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping + TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs + TpProcMemMemClr, ///< 4D .. Before MemClr + TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal + TpProcMemDmi, ///< 4F .. Before DMI + TpProcMemEnd, ///< 50 .. End of memory code + + // CPU test points + TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords + TpProcCpuEntryPstate, ///< 52 .. Entry point CreateAcpiTables + TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling + TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData + TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea + TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat + TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit + TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing + TpProcCpuSetBrandID, ///< 59 .. Set brand ID + TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC + TpProcCpuLoadUcode, ///< 5B .. Load microcode patch + TpProcCpuPowerMgmtInit, ///< 5C .. Power Management table processing + TpProcCpuEarlyFeatureInit, ///< 5D .. Early feature dispatch point + TpProcCpuCoreLeveling, ///< 5E .. Core Leveling + TpProcCpuApMtrrSync, ///< 5F .. AP MTRR sync up + TpProcCpuPostFeatureInit, ///< 60 .. POST feature dispatch point + TpProcCpuFeatureLeveling, ///< 61 .. CPU Feature Leveling + TpProcCpuBeforeAllocateWheaBuffer, ///< 62 .. Before the WHEA init code calls out to allocate a buffer + TpProcCpuAfterAllocateWheaBuffer, ///< 63 .. After the WHEA init code calls out to allocate a buffer + TpProcCpuBeforeAllocateSratBuffer, ///< 64 .. Before the SRAT init code calls out to allocate a buffer + TpProcCpuAfterAllocateSratBuffer, ///< 65 .. After the SRAT init code calls out to allocate a buffer + TpProcCpuBeforeLocateSsdtBuffer, ///< 66 .. Before the P-state init code calls out to locate a buffer + TpProcCpuAfterLocateSsdtBuffer, ///< 67 .. After the P-state init code calls out to locate a buffer + TpProcCpuBeforeAllocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to allocate a buffer + TpProcCpuAfterAllocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to allocate a buffer + + // HT test points + TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface) + TpProcHtTopology, ///< 72 .. Topology match, routing, begin + TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin + TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin + TpProcHtOptGather, ///< 75 .. Optimization: Gather begin + TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin + TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin + TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin + TpProcHtOptFinish, ///< 79 .. Optimization: Set begin + TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin + TpProcHtTuning, ///< 7B .. Misc Tuning Begin + TpProcHtDone, ///< 7C .. HT Init complete + TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin + TpProcHtApMapDone, ///< 7E .. AP HT: Complete + + StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs + TpNbxxx, ///< 91 . + EndNbTestPoints, ///< 92 End of TP range for NB + + StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs + TpSbxxx, ///< B1 . + EndSbTestPoints, ///< B2 End of TP range for SB + + // Interface test points + TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset + TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset + TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery + TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery + TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly + TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly + TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost + TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost + TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv + TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv + TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid + TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid + TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate + TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate + TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save + TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save + TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume + TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume + TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore + TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore + TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore + TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore + TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog + TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog + TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId + TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId + TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress + TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress + TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore + TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore + TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP + TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP + TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data + TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data + TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer + TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer + TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer + TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer + TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer + TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer + TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP + TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP + TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP + TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP + TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer + TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer + TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer + TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer + TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer + TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer + TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer + TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer + TpPerfUnit, ///< F8 .. The Unit of performance measure. + EndAgesaTps = 0xFF, ///< Last defined AGESA TP +} AGESA_TP; + +///Ids Feat description +typedef enum { + IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update + IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate + IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate + IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control + IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size + IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock + IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode + IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length + IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down + IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down + IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter + IDS_FEAT_HDTOUT, ///< Feat for hdt out + IDS_FEAT_HT_SETTING, ///< Feat for Ht setting + IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config + IDS_FEAT_END ///< End of Common feat +} IDS_FEAT; + +typedef IDS_STATUS IDS_COMMON_FUNC ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC; + +/// Data Structure of IDS Feature block +typedef struct _IDS_FEAT_STRUCT { + IDS_FEAT IdsFeat; ///< Ids Feat ID + BOOLEAN IsBsp; ///< swith for Bsp check + AGESA_IDS_OPTION IdsOption; ///< IDS option + UINT64 CpuFamily; ///< + PIDS_COMMON_FUNC pf_idsoption; /// 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) + #error BLDCFG: Unsupported dram scrub rate set +#endif +#if CFG_SCRUB_L2_RATE > 0x16 + #error BLDCFG: Unsupported L2 scrubber rate set +#endif +#if CFG_SCRUB_L3_RATE > 0x16 + #error BLDCFG: unsupported L3 scrubber rate set +#endif +#if CFG_SCRUB_IC_RATE > 0x16 + #error BLDCFG: Unsupported Instruction cache scrub rate set +#endif +#if CFG_SCRUB_DC_RATE > 0x16 + #error BLDCFG: Unsupported Dcache scrub rate set +#endif +// Ensure Quad rank dimm type is valid +#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED + #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED + #error BLDCFG: Invalid quad rank dimm type set + #endif +#endif +// Ensure ECC symbol size is valid +#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG + #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 + #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8 + #error BLDCFG: Invalid Ecc symbol size set + #endif + #endif +#endif +// Ensure power down mode is valid +#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT + #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL + #error BLDCFG: Invalid power down mode set + #endif +#endif + +/***************************************************************************** + * + * Process the option logic, setting local control variables + * + ****************************************************************************/ +#if OPTION_ACPI_PSTATES == TRUE + #define OPTFCN_ACPI_TABLES CreateAcpiTables + #define OPTFCN_GATHER_DATA PStateGatherData + #if OPTION_MULTISOCKET == TRUE + #define OPTFCN_PSTATE_LEVELING PStateLeveling + #else + #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess + #endif +#else + #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess + #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess + #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess +#endif + +#define GET_PSTATE_POWER FALSE +#define GET_PSTATE_FREQ FALSE +#define DISABLE_PSTATE FALSE +#define TRANSITION_PSTATE FALSE +#define PROC_IDD_MAX FALSE +#define GET_TSC_RATE FALSE +#define PSTATE_TRANSITION_LATENCY FALSE +#define GET_PSTATE_REGISTER_INFO FALSE +#define GET_PSTATE_MAX_STATE FALSE +#define SET_PSTATE_LEVELING_REG FALSE +#define GET_NB_FREQ FALSE +#define IS_NBCOF_INIT_NEEDED FALSE +#define IS_NB_PSTATE_ENABLED FALSE +#define AP_INITIAL_LAUNCH FALSE +#define GET_AP_MAILBOX_FROM_HW FALSE +#define SET_AP_CORE_NUMBER FALSE +#define GET_AP_CORE_NUMBER FALSE +#define TRANSFER_AP_CORE_NUMBER FALSE +#define ID_POSITION_INITIAL_APICID FALSE +#define SAVE_FEATURES FALSE +#define WRITE_FEATURES FALSE +#define SET_DOWN_CORE_REG FALSE +#define SET_WARM_RESET_FLAG FALSE +#define GET_WARM_RESET_FLAG FALSE +#define USES_REGISTER_TABLES FALSE +#define BASE_FAMILY_PCI FALSE +#define MODEL_SPECIFIC_PCI FALSE +#define BASE_FAMILY_MSR FALSE +#define MODEL_SPECIFIC_MSR FALSE +#define BRAND_STRING1 FALSE +#define BRAND_STRING2 FALSE +#define BASE_FAMILY_HT_PCI FALSE +#define MODEL_SPECIFIC_HT_PCI FALSE +#define GET_PATCHES FALSE +#define GET_PATCHES_EQUIVALENCE_TABLE FALSE +#define GET_CACHE_INFO FALSE +#define GET_SYSTEM_PM_TABLE FALSE +#define GET_WHEA_INIT FALSE +#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE + +#if AGESA_ENTRY_INIT_RESET == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef GET_AP_MAILBOX_FROM_HW + #define GET_AP_MAILBOX_FROM_HW TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef TRANSFER_AP_CORE_NUMBER + #define TRANSFER_AP_CORE_NUMBER TRUE +#endif + +#if AGESA_ENTRY_INIT_RECOVERY == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef USES_REGISTER_TABLES + #define USES_REGISTER_TABLES TRUE + #undef BASE_FAMILY_PCI + #define BASE_FAMILY_PCI TRUE + #undef MODEL_SPECIFIC_PCI + #define MODEL_SPECIFIC_PCI TRUE + #undef BASE_FAMILY_MSR + #define BASE_FAMILY_MSR TRUE + #undef MODEL_SPECIFIC_MSR + #define MODEL_SPECIFIC_MSR TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_EARLY == TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PROC_IDD_MAX + #define PROC_IDD_MAX TRUE + #undef GET_TSC_RATE + #define GET_TSC_RATE TRUE + #undef GET_NB_FREQ + #define GET_NB_FREQ TRUE + #undef IS_NBCOF_INIT_NEEDED + #define IS_NBCOF_INIT_NEEDED TRUE + #undef AP_INITIAL_LAUNCH + #define AP_INITIAL_LAUNCH TRUE + #undef GET_AP_MAILBOX_FROM_HW + #define GET_AP_MAILBOX_FROM_HW TRUE + #undef SET_AP_CORE_NUMBER + #define SET_AP_CORE_NUMBER TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef TRANSFER_AP_CORE_NUMBER + #define TRANSFER_AP_CORE_NUMBER TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef SET_DOWN_CORE_REG + #define SET_DOWN_CORE_REG TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef USES_REGISTER_TABLES + #define USES_REGISTER_TABLES TRUE + #undef BASE_FAMILY_PCI + #define BASE_FAMILY_PCI TRUE + #undef MODEL_SPECIFIC_PCI + #define MODEL_SPECIFIC_PCI TRUE + #undef BASE_FAMILY_MSR + #define BASE_FAMILY_MSR TRUE + #undef MODEL_SPECIFIC_MSR + #define MODEL_SPECIFIC_MSR TRUE + #undef BRAND_STRING1 + #define BRAND_STRING1 TRUE + #undef BRAND_STRING2 + #define BRAND_STRING2 TRUE + #undef BASE_FAMILY_HT_PCI + #define BASE_FAMILY_HT_PCI TRUE + #undef MODEL_SPECIFIC_HT_PCI + #define MODEL_SPECIFIC_HT_PCI TRUE + #undef GET_PATCHES + #define GET_PATCHES TRUE + #undef GET_PATCHES_EQUIVALENCE_TABLE + #define GET_PATCHES_EQUIVALENCE_TABLE TRUE + #undef GET_SYSTEM_PM_TABLE + #define GET_SYSTEM_PM_TABLE TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_POST == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef GET_PSTATE_POWER + #define GET_PSTATE_POWER TRUE + #undef GET_PSTATE_FREQ + #define GET_PSTATE_FREQ TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PROC_IDD_MAX + #define PROC_IDD_MAX TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef GET_PSTATE_REGISTER_INFO + #define GET_PSTATE_REGISTER_INFO TRUE + #undef GET_PSTATE_MAX_STATE + #define GET_PSTATE_MAX_STATE TRUE + #undef SET_PSTATE_LEVELING_REG + #define SET_PSTATE_LEVELING_REG TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef SAVE_FEATURES + #define SAVE_FEATURES TRUE + #undef WRITE_FEATURES + #define WRITE_FEATURES TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_ENV == TRUE +#endif + +#if AGESA_ENTRY_INIT_MID == TRUE +#endif + +#if AGESA_ENTRY_INIT_LATE == TRUE + #undef GET_PSTATE_FREQ + #define GET_PSTATE_FREQ TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PSTATE_TRANSITION_LATENCY + #define PSTATE_TRANSITION_LATENCY TRUE + #undef GET_WHEA_INIT + #define GET_WHEA_INIT TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE +#endif + +#if AGESA_ENTRY_INIT_S3SAVE == TRUE +#endif + +#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE +#endif + +#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE +#endif + +// Initialize family mask for the PCI MMIO MSR to 0 +#define FAMILY_MMIO_BASE_MASK (0ull) + +/***************************************************************************** + * + * Include the structure definitions for the defaults table structures + * + ****************************************************************************/ +#include "OptionFamily12h.h" +#include "OptionFamily12hLnInstall.h" +#include "OptionFamily12hInstall.h" +#include "Options.h" +#include "OptionsHt.h" +#include "OptionHtInstall.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "OptionMemoryInstall.h" +#include "OptionMemoryRecovery.h" +#include "OptionMemoryRecoveryInstall.h" +#include "OptionDmi.h" +#include "OptionDmiInstall.h" +#include "OptionPstate.h" +#include "OptionPstateInstall.h" +#include "OptionWhea.h" +#include "OptionWheaInstall.h" +#include "OptionSrat.h" +#include "OptionSratInstall.h" +#include "OptionSlit.h" +#include "OptionSlitInstall.h" +#include "OptionMultiSocket.h" +#include "OptionMultiSocketInstall.h" +#include "OptionCpuFeaturesInstall.h" +#include "OptionIdsInstall.h" +#include "OptionS3ScriptInstall.h" +#include "OptionGfxRecovery.h" +#include "OptionGfxRecoveryInstall.h" +#if (AGESA_ENTRY_INIT_EARLY == TRUE) + #include "OptionLynxMicrocodeInstall.h" +#endif + +// If size is 0, but base is not, break the build. +#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0) + #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 +#endif + +// If base is 0, but size is not, break the build. +#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0) + #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater +#endif + +#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0) + // Both are non-zero, begin further processing. + + // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB. + #if (CFG_PCI_MMIO_BASE < 0x800000) + #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater + #endif + + // Break the build if the address is too high for the enabled families. + #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0) + #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families + #endif + + // If the size parameter is not valid, break the build. + #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16) + #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256) + #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 + #endif + #endif + + #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1) + // If the base is not aligned according to size, break the build. + #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0) + #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size + #endif + #undef PCI_MMIO_ALIGNMENT +#endif + + +/***************************************************************************** + * + * Generate the output structu