[coreboot] SPI clock rate
andreas at galauner.de
Mon Jul 4 22:42:29 CEST 2011
I recently started to discover this great project you have here.
I want to play with it a bit and port it to an AMD E-350 Motherboard
(Sapphire Pure Fusion Mini E-350 - what a name...) I have at home in my
Now I don't think that the development work is much fun, when you have
to take the SPI chip off the motherboard, program it, put it back into
the board, see the code failing and repeat the whole process ;)
So, I had the idea of developing a small Board which contains a USB port
and an SPI flash.
I first thought about emulating the SPI flash completely by an AVR, but
I think the clock rates of the SPI bus are too high to do this. My new
approach is a SPI flash which resides on the AVR board which can be
multiplexed between the AVR to program it and the motherboard.
If I want to test a new BIOS, the AVR puts the motherboard into reset,
detaches the flash chip with a multiplexer from the motherboard,
programs it, switches it back to the motherboard and let off the reset.
Rapid BIOS development :)
As an added bonus, I'm thinking about using a USB 2.0 port of an
USB-capable AVR as a USB debug interface (those USB debugging cables are
expensive for a poor student ;) ) and add a second USB 1.1 port with a
MAX3420 for host-communication, but that's step 2.
I know that I won't get the full 480MBit/s with this, but I think I can
live with that.
As I am currently looking for suitable parts, I need to know some basic
parameters of the SPI communication.
Does anybody of you know what the typical clock rates between the
chipset and the flash are?
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