[coreboot] SPI flashing

[Andreas Galauner]

On 7/7/11 2:53 PM, Corey Osgood wrote:
> On my NM10 board, I looked into in-system programming, but Carl-Daniel
> convinced me that there was too much that could go wrong.

Well, I just read the Chip identification in-system with my bus pirate:

SPI> [0x9f,r,r,r]
/CS ENABLED
WRITE: 0x9F
READ: 0xFF
READ: 0xC2
READ: 0x20
/CS DISABLED

Looks good so far and the board isn't fried ;)
It works while the board is in standby. I'm driving the pins directly
with 3,3V and GND. No open-drain or something.
I saw on the oscilloscope that, when using open-drain mode, the SCK line
floats. So, there doesn't seem to be an external pull-down/-up resistor
and the internal seems to be deactivated.

The only weird thing is that I need to read 3 Bytes and not 2 as stated
in the datasheet of the SPI flash, but I don't care about that right now.
Also flashrom doesn't work with the buspirate. I'll have to look into this.

> BTW, just curious, have you had any luck getting the datasheets from
> Intel that cover memory init? Or did you even bother trying?

No, the flashing is the first thing I'm doing with this board, sorry.

-Andreas