[coreboot] New patch to review: 0a1a420 Add SSE3 dependent code

[Frank Vibrans III (frank.vibrans@amd.com)]

Frank Vibrans III (frank.vibrans at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/113

-gerrit

commit 0a1a4205c7198b22597ace1bd2ddf301beee70cf
Author: efdesign98 <efdesign98 at gmail.com>
Date:   Wed Jul 20 20:11:46 2011 -0600

    Add SSE3 dependent code
    
    This change separates out changes that were initially found
    in the commit for XHCI and AHCI changes to "arch/x86/Makefile.
    inc".  It also corrects a comment.  The SSE3 dependent code
    adds a pair of CR4 access functions and a blob of code that
    re-sets CR4.OSFXSR and CR4.OSXMMEXCPT.
    
    Change-Id: Id97256978da81589d97dcae97981a049101b5258
    Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
    Signed-off-by: efdesign98 <efdesign98 at gmail.com>
---
 src/cpu/x86/lapic/lapic_cpu_init.c |   33 ++++++++++++++++++++++++++++++++-
 1 files changed, 32 insertions(+), 1 deletions(-)

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
old mode 100644
new mode 100755
index 53bbe79..53ea60d
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -262,7 +262,7 @@ int start_cpu(device_t cpu)
 
 	if (result) {
 		result = 0;
-		/* Wait 1s or until the new the new cpu calls in */
+		/* Wait 1s or until the new cpu calls in */
 		for(count = 0; count < 100000 ; count++) {
 			if (secondary_stack == 0) {
 				result = 1;
@@ -338,6 +338,26 @@ void stop_this_cpu(void)
 }
 #endif
 
+#ifdef __SSE3__
+static __inline__ __attribute__((always_inline)) unsigned long readcr4(void)
+{
+	unsigned long value;
+	__asm__ __volatile__ (
+			"mov %%cr4, %[value]" 
+			: [value] "=a" (value));
+	return value;
+}
+
+static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data)
+{
+	__asm__ __volatile__ (
+			"mov %%eax, %%cr4"
+			: 
+			: "a" (Data)
+			);
+}
+#endif
+
 /* C entry point of secondary cpus */
 void secondary_cpu_init(void)
 {
@@ -347,6 +367,17 @@ void secondary_cpu_init(void)
 	spin_lock(&start_cpu_lock);
   #endif
 #endif
+
+#ifdef __SSE3__
+	/*
+	 * Seems that CR4 was cleared when AP start via lapic_start_cpu()
+	 * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
+	 */
+	u32 cr4_val;
+	cr4_val = readcr4();
+	cr4_val |= (1 << 9 | 1 << 10);
+	writecr4(cr4_val);
+#endif
 	cpu_initialize();
 #if CONFIG_SERIAL_CPU_INIT == 1
   #if CONFIG_MAX_CPUS>2