[coreboot] Patch set updated: e83dd24 AMD family10 northbridge wrapper, supermicro/h8qgi mainboard

Kerry She (shekairui@gmail.com) gerrit at coreboot.org
Thu Jul 28 04:34:04 CEST 2011


Kerry She (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/121

-gerrit

commit e83dd24e1d779dd72ccdada77d382aa089e3855f
Author: Kerry She <shekairui at gmail.com>
Date:   Thu Jul 28 11:02:43 2011 +0800

    AMD family10 northbridge wrapper, supermicro/h8qgi mainboard
    
    update southbridge (IO hub) search function and VGA destination link
    setting in amd family10 northbridge wrapper.
    family10_scan_chains() not check link_num any more during IO hub searching,
    amdfam10_create_vga_resource() using SbLink ID to set VGA destination link,
    instead of link_num of the device link list.
    
    This change make a more clean devicetree of mainboard using amd family10
    wrapper, and supermicro/h8qgi mainboard family10 devicetree changes are
    include herein.
    
    Change-Id: I45e071ec2a7735ededd056e0ff38ba016f700ff4
    Signed-off-by: Kerry She <kerry.she at amd.com>
    Signed-off-by: Kerry She <shekairui at gmail.com>
---
 src/mainboard/supermicro/h8qgi/devicetree.cb     |   62 +---------------------
 src/northbridge/amd/agesa/family10/northbridge.c |    7 +--
 2 files changed, 5 insertions(+), 64 deletions(-)

diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb
index 9afaac7..a1a0bdf 100755
--- a/src/mainboard/supermicro/h8qgi/devicetree.cb
+++ b/src/mainboard/supermicro/h8qgi/devicetree.cb
@@ -25,10 +25,7 @@ chip northbridge/amd/agesa/family10/root_complex
 	device pci_domain 0 on
 		subsystemid 0x15d9 0xab11 inherit #SuperMicro
 		chip northbridge/amd/agesa/family10 # CPU side of HT root complex
-			device pci 18.0 on end # link 0
-			device pci 18.0 on end # link 1
-			device pci 18.0 on end # link 2
-			device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3
+			device pci 18.0 on # IO-HUB on socket0 link 2(internal Node0 Link 3)
 				chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex
 					device pci 0.0 on  end # HT Root Complex 0x9600
 					device pci 0.1 off end # CLKCONFIG
@@ -46,8 +43,7 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
 					register "gpp1_configuration" = "0"   # Configuration 16:0 default
 					register "gpp2_configuration" = "1"   # Configuration 8:8
-					register "gpp3a_configuration" = "2"   # Configuration 4:1:1:0:0:0
-					#register "gpp3a_configuration" = "11"   # Configuration 1:1:1:1:1:1
+					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
 					register "port_enable" = "0x2104"
 				end #southbridge/amd/sr5650
 				chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus
@@ -115,61 +111,7 @@ chip northbridge/amd/agesa/family10/root_complex
 					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
 				end # southbridge/amd/sp5100
 			end # device pci 18.0
-
 			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-			device pci 19.4 on end
-
-
-			device pci 1a.0 on end
-			device pci 1a.0 on end
-			device pci 1a.0 on end
-			device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3
-			end
-			device pci 1a.1 on end
-			device pci 1a.2 on end
-			device pci 1a.3 on end
-			device pci 1a.4 on end
-
-			device pci 1b.0 on end
-			device pci 1b.1 on end
-			device pci 1b.2 on end
-			device pci 1b.3 on end
-			device pci 1b.4 on end
-
-
-			device pci 1c.0 on end
-			device pci 1c.1 on end
-			device pci 1c.2 on end
-			device pci 1c.3 on end
-			device pci 1c.4 on end
-
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end
-			device pci 1d.3 on end
-			device pci 1d.4 on end
-
-
-			device pci 1e.0 on end
-			device pci 1e.1 on end
-			device pci 1e.2 on end
-			device pci 1e.3 on end
-			device pci 1e.4 on end
-
-			device pci 1f.0 on end
-			device pci 1f.1 on end
-			device pci 1f.2 on end
-			device pci 1f.3 on end
-			device pci 1f.4 on end
-
 		end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex
 	end #pci_domain
 end #northbridge/amd/agesa/family10/root_complex
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index b3e4c63..8e8a84c 100755
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -693,8 +693,8 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
 	if (link == NULL)
 		return;
 
-	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
-	set_vga_enable_reg(nodeid, link->link_num);
+	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sysconf.sblk);
+	set_vga_enable_reg(nodeid, sysconf.sblk);
 }
 
 static void amdfam10_set_resources(device_t dev)
@@ -728,14 +728,13 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max)
 {
 	unsigned nodeid;
 	struct bus *link;
-	unsigned sblink = sysconf.sblk;
 	device_t io_hub = NULL;
 	u32 next_unitid = 0xff;
 
 	nodeid = amdfam10_nodeid(dev);
 	if (nodeid == 0) {
 		for (link = dev->link_list; link; link = link->next) {
-			if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[3] */
+			if (link->link_num == 0) { /* IO Hub on link_lsit[0] in devicetree */
 				io_hub = link->children;
 				if (!io_hub || !io_hub->enabled) {
 					die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n");




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