From marcj303 at gmail.com  Wed Jun  1 01:17:23 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 31 May 2011 17:17:23 -0600
Subject: [coreboot] amd sb800 wrapper compile warning fix
In-Reply-To: <F53A09371FB723428826B442A4B20A41063CC51A@sbjgexmb1.amd.com>
References: <F53A09371FB723428826B442A4B20A41063CC51A@sbjgexmb1.amd.com>
Message-ID: <BANLkTi=AT=fEic+5nWpEQ9EuRP+L38RsmQ@mail.gmail.com>

On Sun, May 29, 2011 at 11:24 PM, She, Kerry <Kerry.She at amd.com> wrote:
> Hello,
>
>
>
> This patch fix a AMD sb800 wrapper compile warning:
>
> src/southbridge/amd/cimx_wrapper/sb800/late
>
> call clear_ioapic but not include the prototype declare header file.
>
> and remove some trivial blanks.
>
>
>
> Signed-off-by Kerry She <Kerry.she at amd.com>
>

Acked-by: Marc Jones <marcj303 at gmail.com>



-- 
http://se-eng.com



From peter at stuge.se  Wed Jun  1 01:29:07 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 1 Jun 2011 01:29:07 +0200
Subject: [coreboot] amd sb800 wrapper compile warning fix
In-Reply-To: <F53A09371FB723428826B442A4B20A41063CC51A@sbjgexmb1.amd.com>
References: <F53A09371FB723428826B442A4B20A41063CC51A@sbjgexmb1.amd.com>
Message-ID: <20110531232907.17461.qmail@stuge.se>

She, Kerry wrote:
> This patch fix a AMD sb800 wrapper compile warning:
> 
> src/southbridge/amd/cimx_wrapper/sb800/late
> 
> call clear_ioapic but not include the prototype declare header file.
> 
> and remove some trivial blanks. 

I think it is very important to make whitespace changes in a patch of
it's own, so that there are no other changes. Please also consider if
changing the license text in the source code is neccessary. It may be
better to keep unneccessary whitespace in the license texts, rather
than having a commit which changes the license.

Anyway, isolating whitespace changes in separate commits allows to
work more efficiently with the commit history in the future, which is
sooner or later always neccessary.

Please also create one patch for each logical change, with the
respective commit messages. Having multiple patches makes the review
process much easier, and also helps significantly when working with
the commit history in the future.


Thanks

//Peter



From svn at coreboot.org  Wed Jun  1 03:56:49 2011
From: svn at coreboot.org (repository service)
Date: Wed, 01 Jun 2011 03:56:49 +0200
Subject: [coreboot] [commit] r6613 - in trunk/src:
	southbridge/amd/cimx_wrapper/sb800 vendorcode/amd/cimx/sb800
Message-ID: <E1QRafx-0004CE-Ft@ra.coresystems.de>

Author: kerry
Date: Wed Jun  1 03:56:49 2011
New Revision: 6613
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6613

Log:
This patch fix a AMD sb800 wrapper compile warning:
 src/southbridge/amd/cimx_wrapper/sb800/late
 call clear_ioapic but not include the prototype declare header file.

Signed-off-by: Kerry She <kerry.she at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h
   trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
   trunk/src/vendorcode/amd/cimx/sb800/EC.c
   trunk/src/vendorcode/amd/cimx/sb800/SATA.c
   trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h	Tue May 24 00:48:13 2011	(r6612)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h	Wed Jun  1 03:56:49 2011	(r6613)
@@ -100,7 +100,7 @@
  * @breif INCHIP Sata Controller
  */
 #ifndef SATA_CONTROLLER
-  #define SATA_CONTROLLER		ENABLED
+  #define SATA_CONTROLLER		CIMX_OPTION_ENABLED
 #endif
 
 /**
@@ -202,7 +202,7 @@
  * @def GPP_CONTROLLER
  */
 #ifndef GPP_CONTROLLER
-  #define GPP_CONTROLLER		ENABLED
+  #define GPP_CONTROLLER		CIMX_OPTION_ENABLED
 #endif
 
 /**

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Tue May 24 00:48:13 2011	(r6612)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Wed Jun  1 03:56:49 2011	(r6613)
@@ -21,6 +21,7 @@
 #include <device/device.h>	/* device_t */
 #include <device/pci.h>		/* device_operations */
 #include <device/pci_ids.h>
+#include <arch/ioapic.h>
 #include <device/smbus.h>	/* smbus_bus_operations */
 #include <console/console.h>	/* printk */
 #include "lpc.h"		/* lpc_read_resources */
@@ -328,13 +329,13 @@
 	switch (dev->path.pci.devfn) {
 	case (0x11 << 3) | 0: /* 0:11.0  SATA */
 		if (dev->enabled) {
-  			sb_config->SATAMODE.SataMode.SataController = ENABLED;
+  			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
 			if (1 == sb_chip->boot_switch_sata_ide)
 				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
 			else if (0 == sb_chip->boot_switch_sata_ide)
 				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
 		} else {
-  			sb_config->SATAMODE.SataMode.SataController = DISABLED;
+  			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
 		}
 
 		sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
@@ -352,11 +353,10 @@
 
 	case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
         {
-	    u8 byte;
 	    u32 ioapic_base;
 
 	    printk(BIOS_INFO, "sm_init().\n");
-	    ioapic_base = 0xFEC00000;
+	    ioapic_base = IO_APIC_ADDR;
 	    clear_ioapic(ioapic_base);
 	    /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
 	    #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
@@ -374,9 +374,9 @@
 
 	case (0x14 << 3) | 1: /* 0:14:1 IDE */
 		if (dev->enabled) {
-			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
+			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED;
 		} else {
-  			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
+  			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED;
 		}
 		sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
 		break;

Modified: trunk/src/vendorcode/amd/cimx/sb800/EC.c
==============================================================================
--- trunk/src/vendorcode/amd/cimx/sb800/EC.c	Tue May 24 00:48:13 2011	(r6612)
+++ trunk/src/vendorcode/amd/cimx/sb800/EC.c	Wed Jun  1 03:56:49 2011	(r6613)
@@ -71,7 +71,7 @@
   RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF));  //set LSB of Mailbox port
   RWEC8 (0x30, 0x00, 0x01);               //;Enable Mailbox Registers Interface, bit0=1
 
-  if ( pConfig->BuildParameters.EcKbd == ENABLED) {
+  if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) {
     //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
 
@@ -83,7 +83,7 @@
     RWEC8 (0x30, 0x00, 0x01);
   }
 
-  if ( pConfig->BuildParameters.EcChannel0 == ENABLED) {
+  if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) {
     //Logical device 0x03
     RWEC8 (0x07, 0x00, 0x03);
     RWEC8 (0x60, 0x00, 0x00);

Modified: trunk/src/vendorcode/amd/cimx/sb800/SATA.c
==============================================================================
--- trunk/src/vendorcode/amd/cimx/sb800/SATA.c	Tue May 24 00:48:13 2011	(r6612)
+++ trunk/src/vendorcode/amd/cimx/sb800/SATA.c	Wed Jun  1 03:56:49 2011	(r6613)
@@ -470,7 +470,7 @@
 
   if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
     // RIAD or AHCI
-    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {
+    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
       RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
       RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
       // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
@@ -631,7 +631,7 @@
   //Enable write access to pci header, pm capabilities
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
 
-//  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {
+//  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
 //  }
   sataBar5setting (pConfig, &ddBar5);

Modified: trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h
==============================================================================
--- trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h	Tue May 24 00:48:13 2011	(r6612)
+++ trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h	Wed Jun  1 03:56:49 2011	(r6613)
@@ -1093,13 +1093,13 @@
 #pragma pack (pop)
 
 /**
- * DISABLED - Define disable in module
+ * CIMX_OPTION_DISABLED - Define disable in module
  */
-#define DISABLED   0
+#define CIMX_OPTION_DISABLED   0
 /**
- * ENABLED - Define enable in module
+ * CIMX_OPTION_ENABLED - Define enable in module
  */
-#define ENABLED    1
+#define CIMX_OPTION_ENABLED    1
 
 // mov al, code
 // out 80h, al



From svn at coreboot.org  Wed Jun  1 04:00:30 2011
From: svn at coreboot.org (repository service)
Date: Wed, 01 Jun 2011 04:00:30 +0200
Subject: [coreboot] [commit] r6614 - in trunk/src:
	southbridge/amd/cimx_wrapper/sb800 vendorcode/amd/cimx/sb800
Message-ID: <E1QRajW-00012g-9Y@ra.coresystems.de>

Author: kerry
Date: Wed Jun  1 04:00:30 2011
New Revision: 6614
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6614

Log:
trivial remove blanks at the end of line

Signed-off-by: Kerry She <kerry.she at amd.com>
Acked-by: Kerry She <kerry.she at amd.com>

Modified:
   trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
   trunk/src/vendorcode/amd/cimx/sb800/SATA.c

Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Wed Jun  1 03:56:49 2011	(r6613)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c	Wed Jun  1 04:00:30 2011	(r6614)
@@ -27,7 +27,7 @@
 #include "lpc.h"		/* lpc_read_resources */
 #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 #include "cfg.h"		/* sb800 Cimx configuration */
-#include "chip.h" 		/* struct southbridge_amd_cimx_wrapper_sb800_config */
+#include "chip.h"		/* struct southbridge_amd_cimx_wrapper_sb800_config */
 
 
 /*implement in mainboard.c*/
@@ -363,7 +363,7 @@
 	    /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
 	    setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
 	    #elif (CONFIG_APIC_ID_OFFSET > 0)
-	    /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ 
+	    /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
 	    setup_ioapic(ioapic_base, 0);
 	    #else
 	    #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"

Modified: trunk/src/vendorcode/amd/cimx/sb800/SATA.c
==============================================================================
--- trunk/src/vendorcode/amd/cimx/sb800/SATA.c	Wed Jun  1 03:56:49 2011	(r6613)
+++ trunk/src/vendorcode/amd/cimx/sb800/SATA.c	Wed Jun  1 04:00:30 2011	(r6614)
@@ -43,7 +43,7 @@
  * ***************************************************************************
  *
  */
- 
+
 #include "SBPLATFORM.h"
 #include "cbtypes.h"
 
@@ -317,7 +317,7 @@
   }
   if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||
     ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) {
-    if ( pConfig->BuildParameters.SataAHCISsid != NULL ) {    
+    if ( pConfig->BuildParameters.SataAHCISsid != NULL ) {
       ddTempVar = pConfig->BuildParameters.SataAHCISsid;
     }
   }



From Kerry.She at amd.com  Wed Jun  1 04:07:12 2011
From: Kerry.She at amd.com (She, Kerry)
Date: Wed, 1 Jun 2011 10:07:12 +0800
Subject: [coreboot] amd sb800 wrapper compile warning fix
In-Reply-To: <20110531232907.17461.qmail@stuge.se>
References: <F53A09371FB723428826B442A4B20A41063CC51A@sbjgexmb1.amd.com>
	<20110531232907.17461.qmail@stuge.se>
Message-ID: <F53A09371FB723428826B442A4B20A410641E43E@sbjgexmb1.amd.com>

> -----Original Message-----
> From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Peter Stuge
> Sent: Wednesday, June 01, 2011 7:29 AM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] amd sb800 wrapper compile warning fix
> 
> She, Kerry wrote:
> > This patch fix a AMD sb800 wrapper compile warning:
> >
> > src/southbridge/amd/cimx_wrapper/sb800/late
> >
> > call clear_ioapic but not include the prototype declare header file.
> >
> > and remove some trivial blanks.
> 
> I think it is very important to make whitespace changes in a patch of
> it's own, so that there are no other changes. Please also consider if
> changing the license text in the source code is neccessary. It may be
> better to keep unneccessary whitespace in the license texts, rather
> than having a commit which changes the license.
Removing the whitespace in the license text is not my intention.
I just use the script to remove all the whitespace when I found there is
some blank at the end of line in certain file.
 
> Anyway, isolating whitespace changes in separate commits allows to
> work more efficiently with the commit history in the future, which is
> sooner or later always neccessary.
Ok
 
> Please also create one patch for each logical change, with the
> respective commit messages. Having multiple patches makes the review
> process much easier, and also helps significantly when working with
> the commit history in the future.
Thanks for your advice

--
Kerry




From anders at jenbo.dk  Wed Jun  1 04:32:14 2011
From: anders at jenbo.dk (Anders Jenbo)
Date: Wed, 01 Jun 2011 04:32:14 +0200
Subject: [coreboot] [RFC]Using gerrit for patch management (and jenkins
 for QA)
In-Reply-To: <4DE53988.3010407@georgi-clan.de>
References: <4DE53988.3010407@georgi-clan.de>
Message-ID: <4DE5A4AE.8000205@jenbo.dk>

Den 31-05-2011 20:55, Patrick Georgi skrev:
> "The mix" would be inclue jenkins test-building all proposed patches on
> gerrit, vetoing those that fail in gerrit. Nice for commits where the
> dev forgot to add a file to the repo, or which were only partially tested.
>
> Anyway, this would be a rather large change in the development workflow,
> so unlike other chang
I favor this change



From peter at stuge.se  Wed Jun  1 04:33:41 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 1 Jun 2011 04:33:41 +0200
Subject: [coreboot] amd sb800 wrapper compile warning fix
In-Reply-To: <F53A09371FB723428826B442A4B20A410641E43E@sbjgexmb1.amd.com>
References: <F53A09371FB723428826B442A4B20A41063CC51A@sbjgexmb1.amd.com>
	<20110531232907.17461.qmail@stuge.se>
	<F53A09371FB723428826B442A4B20A410641E43E@sbjgexmb1.amd.com>
Message-ID: <20110601023341.3417.qmail@stuge.se>

She, Kerry wrote:
> > I think it is very important to make whitespace changes in a patch of
> > it's own,
..
> Removing the whitespace in the license text is not my intention.

Understood. Changing the license text is certainly not forbidden,
especially since you work with the copyright holder, and sometimes
the license text *does* change, but maybe it is preferable to skip
whitespace fixes. It's also possible that I am just being too
careful about this.


> I just use the script to remove all the whitespace when I found there
> is some blank at the end of line in certain file.

This is a good idea! Maybe it will be possible to run the script
before sending future patches, so that no extra commits for fixes
are neccessary.

If you are using git for version control then it can also be
configured to colour code trailing whitespace when viewing changes
using git diff:

git config --global core.whitespace trailing-space,space-before-tab,-cr-at-eol
git config --global color.diff auto


> Thanks for your advice

Thank you for your continued work contributing to coreboot!


//Peter



From peter at stuge.se  Wed Jun  1 05:02:05 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 1 Jun 2011 05:02:05 +0200
Subject: [coreboot] [RFC]Using gerrit for patch management (and
	jenkins	for QA)
In-Reply-To: <4DE53988.3010407@georgi-clan.de>
References: <4DE53988.3010407@georgi-clan.de>
Message-ID: <20110601030205.11341.qmail@stuge.se>

Patrick Georgi wrote:
> I'm officially sick and tired of patchwork. Or from losing patches
> to the mailing list.

Hear hear!


> Given how the git read-only mirror gains popularity, maybe we should use
> that to our advantage and upgrade other parts of our tool set, too.

Sounds good.


> Enter gerrit: A web tool to push git commits to, have them reviewed,
> with proper handling of updated patches. Automatic support for
> dependencies between commits (by default it assumes that ancestry means
> dependency). An automated gatekeeper to the repository.

Sounds even better! Does updated patches mean rebase?


> Should we use it, I'd also add Jenkins (http://www.jenkins-ci.org) to
> the mix.

Put into oven at 220 C and bake for 20 minutes. Yum, chocolate cake!


> Anyway, this would be a rather large change in the development workflow,
> so unlike other changes to our infrastructure this is nothing I can
> "just do".

So far there has been no way at all to push git commits to the main
repo and I really like the look of this setup so if we want to start
getting commits also via git then I think it makes perfect sense.

Maybe the svn repo can (and should) stay primary repo a while longer
still, but that would require a magic post-receive git hook to
transplant received commits into the svn repo, which comes with lots
of fun potential synchronization issues.

It may also be just as well to simply rip off the svn bandaid once
and for all.

Some contributors may experience issues with firewalls when switching
from svn to ssh, but meanwhile it would always be possible to send
patches generated by git via email. (There is even a git send-email
command that automates the process.)


//Peter



From paulepanter at users.sourceforge.net  Wed Jun  1 09:31:11 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 01 Jun 2011 09:31:11 +0200
Subject: [coreboot] [RFC]Using gerrit for patch management (and jenkins
 for QA)
In-Reply-To: <4DE53988.3010407@georgi-clan.de>
References: <4DE53988.3010407@georgi-clan.de>
Message-ID: <1306913471.4315.4.camel@mattotaupa>

Dear Patrick,


Am Dienstag, den 31.05.2011, 20:55 +0200 schrieb Patrick Georgi:

> I'm officially sick and tired of patchwork. Or from losing patches to
> the mailing list.

does that happen so often?

> Given how the git read-only mirror gains popularity, maybe we should use
> that to our advantage and upgrade other parts of our tool set, too.
> 
> Enter gerrit: A web tool to push git commits to, have them reviewed,
> with proper handling of updated patches. Automatic support for
> dependencies between commits (by default it assumes that ancestry means
> dependency). An automated gatekeeper to the repository.

Since you write Web tool, I am wondering if it is still possible to
review patches on the list and to manipulate it using email or the
command line.

[?]


Thanks,

Paul
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From neverforget_2002 at 163.com  Wed Jun  1 09:31:08 2011
From: neverforget_2002 at 163.com (Cui Lei)
Date: Wed, 01 Jun 2011 15:31:08 +0800
Subject: [coreboot]
 =?utf-8?b?QWJvdXQgZ3J1Yi5jZmfigJTigJRCdWlsZGluZyBjb3Jl?=
 =?utf-8?q?boot_with_grub2_payload?=
In-Reply-To: <BANLkTim_A4sfvvSpqCfnWyt66adhHo5oMg@mail.gmail.com>
References: <4DE496F7.5000108@163.com>
	<BANLkTim_A4sfvvSpqCfnWyt66adhHo5oMg@mail.gmail.com>
Message-ID: <4DE5EABC.6000202@163.com>

Thank you for your help, I have changed my operation, but my coreboot  
still step to grub.

/************************************* LOG 
*********************************************************/
Check fallback/payload
Got a payload
Loading segment from rom address 0xfff29ff8
   data (compression=1)
   New segment dstaddr 0x8200 memsize 0xd8b8 srcaddr 0xfff2a04c filesize 
0x3a69
   (cleaned up) New segment addr 0x8200 size 0xd8b8 offset 0xfff2a04c 
filesize 0x3a69
Loading segment from rom address 0xfff2a014
   data (compression=1)
   New segment dstaddr 0x15ab8 memsize 0x69914 srcaddr 0xfff2dab5 
filesize 0x1d0c0
   (cleaned up) New segment addr 0x15ab8 size 0x69914 offset 0xfff2dab5 
filesize 0x1d0c0
Loading segment from rom address 0xfff2a030
   Entry Point 0x00008200
Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000000d8b8 
filesz: 0x0000000000003a69
lb: [0x0000000000100000, 0x0000000000164000)
Post relocation: addr: 0x0000000000008200 memsz: 0x000000000000d8b8 
filesz: 0x0000000000003a69
using LZMA
[ 0x00008200, 0000e51b, 0x00015ab8) <- fff2a04c
Clearing Segment: addr: 0x000000000000e51b memsz: 0x000000000000759d
dest 00008200, end 00015ab8, bouncebuffer 7fe28000
Loading Segment: addr: 0x0000000000015ab8 memsz: 0x0000000000069914 
filesz: 0x000000000001d0c0
lb: [0x0000000000100000, 0x0000000000164000)
Post relocation: addr: 0x0000000000015ab8 memsz: 0x0000000000069914 
filesz: 0x000000000001d0c0
using LZMA
[ 0x00015ab8, 0007f3cc, 0x0007f3cc) <- fff2dab5
dest 00015ab8, end 0007f3cc, bouncebuffer 7fe28000
Loaded segments
Jumping to boot code at 8200
entry    = 0x00008200
lb_start = 0x00100000
lb_size  = 0x00064000
adjust   = 0x7fd8c000
buffer   = 0x7fe28000
      elf_boot_notes = 0x0011622c
adjusted_boot_notes = 0x7fea222c

/****************************************************************************************************/
I have added "grub_printf("Enter grub_main()!\n")" in the top of 
grub_main()(defined in grub-core/kern/main.c). Unfortunately, nothing 
can be printed out when booting. I don't know it is stopped before grub 
C code or I don't open some grub2 option which close the standard output 
mode.

> 2011/5/31 Cui Lei<neverforget_2002 at 163.com>:
>> I am working hard at building coreboot with grub2 payload. Now  I can build
>> a grub2 payload as follow:
>> 1: Download the lastest grub2 source code.
>> 2: ./autogen.sh
>>      ./configure --with-platform=coreboot
>>       make
>> 3: Use grub-mkimage to generate a "payload.elf", detail:
>>      ./grub-mkimage -d . -O i386-coreboot -o ../coreboot-v4/payload.elf
>> --prefix='/boot/grub2'
>>        memdisk cpio -m ../memdisk.tar
>>
>>      Accoding the coreboot website(http://www.coreboot.org/Talk:GRUB2),
>> memdisk is a virtual disk
>>      in grub image and it is suggested that grub.cfg is contained in a
>> memdisk image. So I made
>>      folders boot/grub2 in my work folder and add a new grub.cfg and some
>> modules(such as
>>      memdisk.mod cpio.mod ...) into the boot/grub2, then tar boot/grub2 to
>> memdisk.tar(according
>>      to the website tar can be used to build a memdisk image).
>>
>> Problems:
>>      1: I don't know wether grub2 can found my grub.cfg ,if I set  "
>> --prefix='/boot/grub2' " ?
>>          On the coreboot website,a sample is  --prefix='(ata0)/boot/grub2'. I
>> think the ata0 is hard disk.
>>          but I use the memdisk image, what should I do ?
>>
> I use this to create a custom grub2 efi app with memdisk embedded -
>
> /bin/grub-mkimage --directory=/usr/lib/grub/x86_64-efi
> --memdisk="${memdisk_64_img}" --prefix='(memdisk)/efi/grub2'
> --format=x86_64-efi --compression=xz
> --output="${grub2_efi_mp}/efi/boot/bootx64.efi" ${GRUB2_MODULES}
>
> Hope this helps.
>
>>      2: I want my grub.cfg in memdisk to load the grub.cfg from my hard disk.
>> Because I have install the
>>          ubuntu11.04 on my hard disk, a grub.cfg file should be in the
>> /boot/grub. So my grub.cfg just like
>>          this:
>>                  search -f -s /boot/grub/grub.cfg
>>                  configfile /boot/grub/grub.cfg
>>
>>          Is this practicable?
>>
> Make it
>
>   search --file --no-floppy --set=root /boot/grub/grub.cfg
>   configfile (${root})/boot/grub/grub.cfg
>
>>      3: I want the gurb can boot into the grub-shell, how to ?
>>
> I can't understand the question. You want grub to boot into
> grub-shell? Don't create a ${prefix}/grub.cfg file.
>
>> BRs,
>>
>> Rock.C
>>
> Regards.
>
> Keshav
>





From patrick at georgi-clan.de  Wed Jun  1 10:40:52 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 01 Jun 2011 10:40:52 +0200
Subject: [coreboot] [RFC]Using gerrit for patch management (and	jenkins
 for QA)
In-Reply-To: <20110601030205.11341.qmail@stuge.se>
References: <4DE53988.3010407@georgi-clan.de>
	<20110601030205.11341.qmail@stuge.se>
Message-ID: <4DE5FB14.7010707@georgi-clan.de>

Am 01.06.2011 05:02, schrieb Peter Stuge:
> Patrick Georgi wrote:
>> I'm officially sick and tired of patchwork. Or from losing patches
>> to the mailing list.
> Hear hear!
Mail is for spam-delivery, an ancient tool from a distant past ;-)

No, seriously - we have 100+ unhandled patches on patchwork, many of
them iterations on a single topic that must be cleaned up manually
(because the scripts can't).

If patches bitrot in gerrit, at least they're already build tested, and
iterations are grouped together automatically.
Which means less work for the poor soul trying to clean up.

>> Enter gerrit: A web tool to push git commits to, have them reviewed,
>> with proper handling of updated patches. Automatic support for
>> dependencies between commits (by default it assumes that ancestry means
>> dependency). An automated gatekeeper to the repository.
> Sounds even better! Does updated patches mean rebase?
rebase, modifications, ... essentially, it's possible to track a single
issue and its patches at a single location.

> So far there has been no way at all to push git commits to the main
> repo and I really like the look of this setup so if we want to start
> getting commits also via git then I think it makes perfect sense.
It's a special workflow, but for git there doesn't seem to be a default
workflow anyway. Specifically, there's no way to push to master
directly. Instead:
- commits are pushed to gerrit (by normal "git push" and a
commit-message hook that adds a Change-Id entry)
- commits are build tested by jenkins automatically, which registers its
vote with gerrit
- commits are reviewed by other developers
- sufficient positive review count -> commits are pushed to mainline by
gerrit

> Maybe the svn repo can (and should) stay primary repo a while longer
> still, but that would require a magic post-receive git hook to
> transplant received commits into the svn repo, which comes with lots
> of fun potential synchronization issues.
We'd need bidirectional bridging that doesn't always break...

> It may also be just as well to simply rip off the svn bandaid once
> and for all.
... so I'd prefer that.

> Some contributors may experience issues with firewalls when switching
> from svn to ssh, but meanwhile it would always be possible to send
> patches generated by git via email. (There is even a git send-email
> command that automates the process.)
People generally had a problem with accessing svn:// URLs already, so we
provided a http[s] read-only copy of the repo.
I guess we can do similar with a read-only git repo.


Patrick



From patrick at georgi-clan.de  Wed Jun  1 10:44:57 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 01 Jun 2011 10:44:57 +0200
Subject: [coreboot] [RFC]Using gerrit for patch management (and jenkins
 for QA)
In-Reply-To: <1306913471.4315.4.camel@mattotaupa>
References: <4DE53988.3010407@georgi-clan.de>
	<1306913471.4315.4.camel@mattotaupa>
Message-ID: <4DE5FC09.2020808@georgi-clan.de>

Am 01.06.2011 09:31, schrieb Paul Menzel:
> Am Dienstag, den 31.05.2011, 20:55 +0200 schrieb Patrick Georgi:
>> I'm officially sick and tired of patchwork. Or from losing patches to
>> the mailing list.
> does that happen so often?
http://patchwork.coreboot.org/project/coreboot/list/
More than 100 patches unhandled, with some of them duplicates/iterations
that must be tracked down manually.

> Since you write Web tool, I am wondering if it is still possible to
> review patches on the list and to manipulate it using email or the
> command line.
No bridge to mail exists at this time. I think it would also be hard to
map properly. But feel free to try.


Patrick



From paulepanter at users.sourceforge.net  Wed Jun  1 11:01:21 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 01 Jun 2011 11:01:21 +0200
Subject: [coreboot] [RFC]Using gerrit for patch management (and jenkins
 for QA)
In-Reply-To: <4DE5FC09.2020808@georgi-clan.de>
References: <4DE53988.3010407@georgi-clan.de>
	<1306913471.4315.4.camel@mattotaupa> <4DE5FC09.2020808@georgi-clan.de>
Message-ID: <1306918881.4315.22.camel@mattotaupa>

Am Mittwoch, den 01.06.2011, 10:44 +0200 schrieb Patrick Georgi:
> Am 01.06.2011 09:31, schrieb Paul Menzel:
> > Am Dienstag, den 31.05.2011, 20:55 +0200 schrieb Patrick Georgi:
> >> I'm officially sick and tired of patchwork. Or from losing patches to
> >> the mailing list.
> > does that happen so often?
> http://patchwork.coreboot.org/project/coreboot/list/
> More than 100 patches unhandled, with some of them duplicates/iterations
> that must be tracked down manually.

Well if people would mark there iterations [PATCH v2] or send them as a
reply, I guess it would be scriptable. But you would have to
teach/educate the developers.

> > Since you write Web tool, I am wondering if it is still possible to
> > review patches on the list and to manipulate it using email or the
> > command line.
> No bridge to mail exists at this time. I think it would also be hard to
> map properly.

So the question is, if the developers would adapt to this new work flow
using a Web interface. Most free software developers are used to email
as far as I know.

They would probably need to create an account, log in every time and do
some clicks before they can review something. The main developers need
to commit to and embrace that new work flow.

I am doing no coreboot development and therefore do not care much. But
the main developers (maybe also AMD) should be asked directly.

> But feel free to try.

No time and no intentions to do so.

It might be also a good idea to ask that question on the flashrom list,
since they also use the infrastructure(?) and there are some Google
folks who maybe have experience with at least Gerrit.


Thanks,

Paul
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From patrick at georgi-clan.de  Wed Jun  1 11:11:36 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 01 Jun 2011 11:11:36 +0200
Subject: [coreboot] [RFC]Using gerrit for patch management (and jenkins
 for QA)
In-Reply-To: <1306918881.4315.22.camel@mattotaupa>
References: <4DE53988.3010407@georgi-clan.de>	<1306913471.4315.4.camel@mattotaupa>
	<4DE5FC09.2020808@georgi-clan.de>
	<1306918881.4315.22.camel@mattotaupa>
Message-ID: <4DE60248.9060400@georgi-clan.de>

Am 01.06.2011 11:01, schrieb Paul Menzel:
> Well if people would mark there iterations [PATCH v2] or send them as a
> reply, I guess it would be scriptable. But you would have to
> teach/educate the developers.
Only if the tool is able to deduct which patch it is version 2 of.
Once it can do that, we wouldn't need that mark.

> So the question is, if the developers would adapt to this new work flow
> using a Web interface. Most free software developers are used to email
> as far as I know.
There used to be a time where no SCMs (distributed or not) were used.
Traditions are nice and all - until they get in the way.

> The main developers need
> to commit to and embrace that new work flow.
That's why I ask.

> It might be also a good idea to ask that question on the flashrom list,
> since they also use the infrastructure(?) and there are some Google
> folks who maybe have experience with at least Gerrit.
I've been approached by flashrom developers already. There's no issue
with keeping patchwork alive for them (and the mailing lists will
continue to exist anyway).

It's just that for coreboot, the infrastructure doesn't work all that
well - probably because compared to flashrom it's a less integrated package.


Patrick



From cristi.magherusan at net.utcluj.ro  Wed Jun  1 19:53:01 2011
From: cristi.magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Wed, 1 Jun 2011 20:53:01 +0300 (EEST)
Subject: [coreboot] [RFC]Using gerrit for patch management (and jenkins
 for QA)
In-Reply-To: <4DE5A4AE.8000205@jenbo.dk>
References: <4DE53988.3010407@georgi-clan.de> <4DE5A4AE.8000205@jenbo.dk>
Message-ID: <62909.192.100.130.7.1306950781.squirrel@intranet.utcluj.ro>

?n Mie, Iunie 1, 2011 5:32, Anders Jenbo a scris:
> Den 31-05-2011 20:55, Patrick Georgi skrev:
>
>> "The mix" would be inclue jenkins test-building all proposed patches on
>>  gerrit, vetoing those that fail in gerrit. Nice for commits where the
>> dev forgot to add a file to the repo, or which were only partially
>> tested.
>>
>> Anyway, this would be a rather large change in the development
>> workflow, so unlike other chang
> I favor this change
>

+1 from me too




From dhendrix at google.com  Wed Jun  1 20:28:03 2011
From: dhendrix at google.com (David Hendricks)
Date: Wed, 1 Jun 2011 11:28:03 -0700
Subject: [coreboot] [RFC]Using gerrit for patch management (and jenkins
 for QA)
In-Reply-To: <1306918881.4315.22.camel@mattotaupa>
References: <4DE53988.3010407@georgi-clan.de>
	<1306913471.4315.4.camel@mattotaupa>
	<4DE5FC09.2020808@georgi-clan.de> <1306918881.4315.22.camel@mattotaupa>
Message-ID: <BANLkTinP3DNyb-S0CETFBRsU=whSt3+Erb1mQApdo9wSaomUag@mail.gmail.com>

On Wed, Jun 1, 2011 at 2:01 AM, Paul Menzel <
paulepanter at users.sourceforge.net> wrote:

> It might be also a good idea to ask that question on the flashrom list,
> since they also use the infrastructure(?) and there are some Google
> folks who maybe have experience with at least Gerrit.


I can't say that I am an advanced user, however for simple usage cases I
find Gerrit to be excellent.

A few things I like about Gerrit:

   - Very good web-based side-by-side context diffs (with syntax
   highlighting and other nice features of native apps like gdiff, kompare,
   etc). One can still download a patch and apply, but I think the web-based
   diff saves the reviewer *a lot* of time overall since changes don't need to
   be downloaded and applied (sometimes with conflict resolution involved).
   *Saving the reviewers' time is critical.*
   - Better patch management. You can review side-by-side diffs of any patch
   revision. This is essential for reducing the burden of reviewing and to
   prevent patches from bit rotting IMHO. Especially true when the patch
   revision is >3.
   - Comments *do* show up in e-mail. I think there is a way to reply to
   comments in e-mail as well, but I always just use the web interface.
   - A plethora of log-in methods can be used. For chromium.org one can sign
   in using Open ID, a Google account, or a Yahoo account.
   - One-click commits are handy since you don't need to worry about
   sync'ing your tree

There is a learning curve with git, but I think a concise wiki entry
demonstrating some a simple workflow will help people get their toes wet
quickly. It's clear that many contributors on this list are already familiar
(and indeed eager) to use git.

Overall, I believe e-mail is fine up to a certain point, but Coreboot and
Flashrom both have enough developers contributing that it's worth moving to
a more advanced SCM. Especially since a lot of changes can linger for days
or weeks since hardware scarcity can often limit the ability of reviewers
and testers.

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From peter at stuge.se  Wed Jun  1 20:46:55 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 1 Jun 2011 20:46:55 +0200
Subject: [coreboot] [RFC]Using gerrit for patch management (and
	jenkins	for QA)
In-Reply-To: <BANLkTinP3DNyb-S0CETFBRsU=whSt3+Erb1mQApdo9wSaomUag@mail.gmail.com>
References: <4DE53988.3010407@georgi-clan.de>
	<1306913471.4315.4.camel@mattotaupa>
	<4DE5FC09.2020808@georgi-clan.de>
	<1306918881.4315.22.camel@mattotaupa>
	<BANLkTinP3DNyb-S0CETFBRsU=whSt3+Erb1mQApdo9wSaomUag@mail.gmail.com>
Message-ID: <20110601184655.31108.qmail@stuge.se>

David Hendricks wrote:
> Overall, I believe e-mail is fine up to a certain point, but Coreboot and
> Flashrom both have enough developers contributing that it's worth moving to
> a more advanced SCM.

I don't think the two are actually mutually exclusive.

Git is already quite email affine and gerrit comes with good tools
allowing other data entry points than the web.

I've made a pact with Patrick on IRC to look at an email->gerrit
bridge, that would simply take pgp signed email Acked-by: to count
just as web clicks.

Requiring PGP signature on acked-by emails is an acceptable price to
pay when the benefit is that the commit will be pushed to master repo
automatically *and* the entire process has been tracked and is
trivially browseable online.

Even for me (heavy email user + severe web allergy) gerrit looks grreit!


//Peter



From svn at coreboot.org  Wed Jun  1 21:29:48 2011
From: svn at coreboot.org (repository service)
Date: Wed, 01 Jun 2011 21:29:48 +0200
Subject: [coreboot] [commit] r6615 - trunk/util/abuild
Message-ID: <E1QRr6y-0006NJ-MI@ra.coresystems.de>

Author: oxygene
Date: Wed Jun  1 21:29:48 2011
New Revision: 6615
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6615

Log:
Report build result from abuild (did all requested boards build?)

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/util/abuild/abuild

Modified: trunk/util/abuild/abuild
==============================================================================
--- trunk/util/abuild/abuild	Wed Jun  1 04:00:30 2011	(r6614)
+++ trunk/util/abuild/abuild	Wed Jun  1 21:29:48 2011	(r6615)
@@ -35,6 +35,9 @@
 # Configure-only mode
 configureonly=0
 
+# Did any board fail to build?
+failed=0
+
 # One might want to adjust these in case of cross compiling
 for i in make gmake gnumake nonexistant_make; do
 	$i --version 2>/dev/null |grep "GNU Make" >/dev/null && break
@@ -294,6 +297,7 @@
 		printf "FAILED after ${duration}s!\nLog excerpt:\n"
 		tail -n $CONTEXT make.log 2> /dev/null || tail -$CONTEXT make.log
 		cd $CURR
+		failed=1
 		return 1
 	fi
 }
@@ -622,3 +626,4 @@
 fi
 xml '</abuild>'
 
+exit $failed



From svn at coreboot.org  Wed Jun  1 21:54:16 2011
From: svn at coreboot.org (repository service)
Date: Wed, 01 Jun 2011 21:54:16 +0200
Subject: [coreboot] [commit] r6616 - trunk
Message-ID: <E1QRrUe-000248-JY@ra.coresystems.de>

Author: oxygene
Date: Wed Jun  1 21:54:16 2011
New Revision: 6616
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6616

Log:
Really fix iasl filename issues in our build system

There's a remaining issue that iasl cuts of "\..*$" from
output paths, even if that substring contains "/" (ie.
across directories)

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/Makefile.inc

Modified: trunk/Makefile.inc
==============================================================================
--- trunk/Makefile.inc	Wed Jun  1 21:29:48 2011	(r6615)
+++ trunk/Makefile.inc	Wed Jun  1 21:54:16 2011	(r6616)
@@ -64,8 +64,8 @@
 $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h
 	@printf "    IASL       $$(subst $(top)/,,$$(@))\n"
 	$(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl
-	cd $$(dir $$@); iasl -p $$(abspath $$(obj)/$(1)) -tc $$(notdir $$(basename $$@)).asl
-	mv $$(obj)/$(1).hex $$(basename $$@).c
+	cd $$(dir $$@); iasl -p $$(notdir $$@) -tc $$(notdir $$(basename $$@)).asl
+	mv $$(basename $$@).hex $$(basename $$@).c
 	$(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$@).c
 	# keep %.o: %.c rule from catching the temporary .c file after a make clean
 	mv $$(basename $$@).c $$(basename $$@).hex



From lists at rewt.org.uk  Wed Jun  1 22:29:23 2011
From: lists at rewt.org.uk (Joe Holden)
Date: Wed, 01 Jun 2011 21:29:23 +0100
Subject: [coreboot] JetwayJNC92-330 support
Message-ID: <4DE6A123.7040608@rewt.org.uk>

Hi guys,

Not sure if this is the right place to ask, but what are the chances of 
the above board being supported?

I have a couple in use and they look like pretty standard ICH7/945 
boards: http://www.mini-itx.com/store/?c=47#jnc92-330

Thanks,
J



From stefan.reinauer at coreboot.org  Wed Jun  1 23:26:26 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 1 Jun 2011 23:26:26 +0200
Subject: [coreboot] JetwayJNC92-330 support
In-Reply-To: <4DE6A123.7040608@rewt.org.uk>
References: <4DE6A123.7040608@rewt.org.uk>
Message-ID: <20110601212626.GA14068@coreboot.org>

* Joe Holden <lists at rewt.org.uk> [110601 22:29]:
> Hi guys,
> 
> Not sure if this is the right place to ask, but what are the chances
> of the above board being supported?
> 
> I have a couple in use and they look like pretty standard ICH7/945
> boards: http://www.mini-itx.com/store/?c=47#jnc92-330

Slight modifications will probably be required, but the port should be
fairly straight forward. Look at the intel/d945gclf board as a basis.

Stefan




From r_boulware at hotmail.com  Thu Jun  2 00:52:16 2011
From: r_boulware at hotmail.com (Raleigh Boulware)
Date: Wed, 1 Jun 2011 18:52:16 -0400
Subject: [coreboot] Core boot basics
In-Reply-To: <BANLkTik4ncHpYj2UrA=BejiY2TwJqMGaKg@mail.gmail.com>
References: <COL109-W579394A9C95BCB77982E7AF7760@phx.gbl>,
	<4DDF502C.3060405@163.com>,
	<BANLkTik4ncHpYj2UrA=BejiY2TwJqMGaKg@mail.gmail.com>
Message-ID: <col109-w17CCC0866DB35936F6AB65F77D0@phx.gbl>



 OK I have finally got the code to build a .rom file thanks to everyones help on here. My next step, now that it looks like my enviroment is settup, is to just learn my way aeround the basics of how the project is organized.
My question is what is the flow of how the source code works? What is the first thing or file that gets executed? then how do I flow the code from there? 		 	   		  
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From peter at stuge.se  Thu Jun  2 01:31:27 2011
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jun 2011 01:31:27 +0200
Subject: [coreboot] Core boot basics
In-Reply-To: <col109-w17CCC0866DB35936F6AB65F77D0@phx.gbl>
References: <BANLkTik4ncHpYj2UrA=BejiY2TwJqMGaKg@mail.gmail.com>
	<col109-w17CCC0866DB35936F6AB65F77D0@phx.gbl>
Message-ID: <20110601233127.6479.qmail@stuge.se>

Raleigh Boulware wrote:
> OK I have finally got the code to build a .rom file thanks to
> everyones help on here.

That's a big warning sign.


> My next step, now that it looks like my enviroment is settup, is to
> just learn my way aeround the basics of how the project is
> organized.

I think you should actually have started with this step.


> My question is what is the flow of how the source code works?

Why do you ask?


> What is the first thing or file that gets executed?

Why do you ask?


> then how do I flow the code from there?

Why do you want to do that?


In short, what is your detailed motivation for using coreboot?


Noone has time to hold your hand along the learning curve of
coreboot; you have to study on your own. Fortunately there are many
resources available for learning. You can read the mailing list
archives, where the exact same questions you ask have already been
asked and answered in depth.

The fact that you are asking questions that have already been
answered in the archive, along with your questions about package
management in Fedora, reveals that you have put no significant effort
into even learning what you need to learn - which suggests that you
expect or want to be spoon-fed every thing. This is not a useful
approach in most open source projects, because everyone is
contributing on a voluntary basis and it is extremely inefficient to
spend time on 1:1 spoon feeding.

coreboot is a fairly advanced project so please be prepared to
educate yourself if you're only just starting out.

Education takes time. Usually a lot of time. I'd expect a year to get
up to speed on all aspects of coreboot.

Of course there's also the alternative to buy professional training.

Several service providers are active contributors in the coreboot
community; they may be interested in offering introductory coreboot
training. This mailing list is a great place to advertise interest in
such training. I don't know of any that has been held so far, but if
there is demand there will without a doubt also be a supply! I have
no idea about the price point but I can guess.. There would probably
be a few different levels to choose from as for how far in depth the
training goes, and I would guess fees starting at $1k per participant.

In short: if you don't want to self educate then you have to pay
someone to do it for you. No free lunch here.


//Peter



From v10lator at myway.de  Thu Jun  2 07:52:47 2011
From: v10lator at myway.de (Thomas Rohloff)
Date: Thu, 2 Jun 2011 07:52:47 +0200
Subject: [coreboot] Is this board supported?
Message-ID: <20110602075247.6bd513cb@schlepptop>

Hi,
I have a AsRock 870 Etreme3
( http://www.asrock.com/mb/overview.asp?model=870%20extreme3 ) and
wanted to know if it's supported b coreboot.

This is the output from flashrom:


flashrom v0.9.3-r1205 on Linux 3.0.0-rc1 (x86_64), built with libpci
3.1.7, GCC 4.6.0, little endian flashrom is free software, get the
source code at http://www.flashrom.org

Calibrating delay loop... OK.
No coreboot table found.
Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK.
This chipset supports the following protocols: LPC,FWH,SPI.
Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address
0xfff00000. No operations were specified.


- Northbridge: AMD 870
- Southbridge: AMD SB850
- SuperIO: Nuvoton W83677HG-I (NCT6771F/NCT6772F/NCT6775F)
- CPU: Unlocked AMD Athlon II X3 455

So, is this possible? And is it possible to unlock the 4th CPU-Core
with coreboot?



From russ at ashlandhome.net  Thu Jun  2 09:01:13 2011
From: russ at ashlandhome.net (Russell Whitaker)
Date: Thu, 2 Jun 2011 00:01:13 -0700 (PDT)
Subject: [coreboot] Is this board supported?
In-Reply-To: <20110602075247.6bd513cb@schlepptop>
References: <20110602075247.6bd513cb@schlepptop>
Message-ID: <alpine.LNX.2.00.1106012353570.3542@bigred.russwhit.org>



On Thu, 2 Jun 2011, Thomas Rohloff wrote:


> - CPU: Unlocked AMD Athlon II X3 455
>
> And is it possible to unlock the 4th CPU-Core?

You may not want to. I don't know about AMD, but if I were a semiconductor 
manufacture I would build 4 core chips and if one core failed QC, I'd
lock that core off and sell it as a 3 core.

   Russ



From v10lator at myway.de  Thu Jun  2 12:46:41 2011
From: v10lator at myway.de (Thomas Rohloff)
Date: Thu, 2 Jun 2011 12:46:41 +0200
Subject: [coreboot] Is this board supported?
In-Reply-To: <alpine.LNX.2.00.1106012353570.3542@bigred.russwhit.org>
References: <20110602075247.6bd513cb@schlepptop>
	<alpine.LNX.2.00.1106012353570.3542@bigred.russwhit.org>
Message-ID: <20110602124641.4c8ea311@schlepptop>

Am Thu, 2 Jun 2011 00:01:13 -0700 (PDT)
schrieb Russell Whitaker <russ at ashlandhome.net>:

> 
> 
> On Thu, 2 Jun 2011, Thomas Rohloff wrote:
> 
> 
> > - CPU: Unlocked AMD Athlon II X3 455
> >
> > And is it possible to unlock the 4th CPU-Core?
> 
> You may not want to. I don't know about AMD, but if I were a
> semiconductor manufacture I would build 4 core chips and if one core
> failed QC, I'd lock that core off and sell it as a 3 core.
> 
>    Russ
> 

I'm using the 4. core with the default BIOS (UCC) a long time now and
it's working fine.
So please don't tell me what I may want or not, simply answer my
original questions, please. :)

P.S. Sorry for my bad english, it's not my native language.



From stefan.reinauer at coreboot.org  Thu Jun  2 15:37:16 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Thu, 02 Jun 2011 06:37:16 -0700
Subject: [coreboot] Is this board supported?
In-Reply-To: <20110602075247.6bd513cb@schlepptop>
References: <20110602075247.6bd513cb@schlepptop>
Message-ID: <4DE7920C.3000905@coreboot.org>

On 6/1/11 10:52 PM, Thomas Rohloff wrote:
> Hi,
> I have a AsRock 870 Etreme3
> ( http://www.asrock.com/mb/overview.asp?model=870%20extreme3 ) and
> wanted to know if it's supported b coreboot.
>
See http://www.coreboot.org/Supported_Motherboards for a list of 
supported boards.


> So, is this possible? And is it possible to unlock the 4th CPU-Core
> with coreboot?
Yes it is possible. You will have to figure out, how, though.

Stefan





From patrick at georgi-clan.de  Thu Jun  2 17:01:42 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 02 Jun 2011 17:01:42 +0200
Subject: [coreboot] Is this board supported?
In-Reply-To: <alpine.LNX.2.00.1106012353570.3542@bigred.russwhit.org>
References: <20110602075247.6bd513cb@schlepptop>
	<alpine.LNX.2.00.1106012353570.3542@bigred.russwhit.org>
Message-ID: <4DE7A5D6.5060400@georgi-clan.de>

Am 02.06.2011 09:01, schrieb Russell Whitaker:
>> And is it possible to unlock the 4th CPU-Core?
> You may not want to. I don't know about AMD, but if I were a
> semiconductor manufacture I would build 4 core chips and if one core
> failed QC, I'd
> lock that core off and sell it as a 3 core.
They also do that to "good" chips if there's more demand for 3-core
chips than what they produce (ie. if their yield is too good).


Patrick



From marcj303 at gmail.com  Thu Jun  2 18:03:11 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 2 Jun 2011 10:03:11 -0600
Subject: [coreboot] [PATCH] ASRock E350M1 update
In-Reply-To: <71770C804BF1478782F3FFD7741E8CA0@asusp67>
References: <AcwWs82EUmmnvWnoR+OZ3akIgcBH+g==>
	<71770C804BF1478782F3FFD7741E8CA0@asusp67>
Message-ID: <BANLkTin9M-U1rzd6p+B8PNie4nbq0WAAXA@mail.gmail.com>

Hi Scott,

i have not forgotten about these. I'll try to get to these this week.

Marc


On Fri, May 20, 2011 at 12:04 AM, Scott Duplichan <scott at notabs.org> wrote:
> The attached changes for the ASRock E350M1 board improve OS support and
> reduce boot time. DOS boot from SSD drive takes 690 ms. Windows 7,
> Windows XP, and linux can install from DVD and boot from hard disk.
>
> Signed-off-by: Scott Duplichan <scott at notabs.org>
>
> OS install test:
> Using SeaBIOS 0.6.2 plus AHCI patch,
> http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/1663.
>
> Windows XP SP3 X86
> ? ?Tested with revision 6600 plus attached patches (removed rev 6579 AHCI
> enable).
> ? ?Setup from CD-ROM: pass.
> ? ?Install latest graphics driver 11-5_xp32_dd_ccc_ocl.exe: 8.850.0.0
> (4/19/2011): pass.
> Win7 Ultimate x64 SP1
> ? ?Tested with revision 6600 plus attached patches.
> ? ?Setup from DVD: pass.
> ? ?Install latest graphics driver 11-5_vista64_win7_64_dd_ccc_ocl.exe:
> 8.850.0.0 (4/19/2011): pass.
> Ubuntu 11.04 beta
>
> http://mirror.anl.gov/pub/ubuntu-iso/DVDs/ubuntu/natty/beta-2/ubuntu-11.04-b
> eta2-dvd-amd64.iso
> ? ?Tested with revision 6600 plus attached patches.
> ? ?Setup from DVD: pass.
>
> Thanks,
> Scott
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



-- 
http://se-eng.com



From stefan.reinauer at coreboot.org  Thu Jun  2 20:24:49 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Thu, 2 Jun 2011 20:24:49 +0200
Subject: [coreboot] [patch] ck804 ACPI PIC/APIC interrupt logic
In-Reply-To: <20110525165954.GS24800@tarantulon.kollasch.net>
References: <20110523192845.GQ24800@tarantulon.kollasch.net>
	<20110523195348.GA19525@coreboot.org>
	<20110525165954.GS24800@tarantulon.kollasch.net>
Message-ID: <20110602182449.GA28159@coreboot.org>

* Jonathan A. Kollasch <jakllsch at kollasch.net> [110525 18:59]:
> > > +	      If (LEqual (Arg0, 8)) {
> > white spaces look messed up
> 
> No, that was intentional, i wanted the LEqual to line up,
> though then I didn't pad the single character numbers ...

Sorry not sure what you were trying to achieve. As long as the code
looks like 

        If (LEqual (Arg0, 8)) {
                ....
        } ElseIf (LEqual (Arg0, 13)) {
                ....
        } ...

you should be fine

> > > +Device (APIB) {
> > > +	Name (_HID, EISAID ("PNP0C0F"))
> > 
> > Can you call these LNKA/LNKB... we used those names in all other targets
> > afaict.
> 
> This is intentional, I need a link Device for APIC and PIC for each
> device.


Yes, you should handle the APIC/PIC cases in your LNKA/LNKB/... nodes.
I think we should still call them LNKA/LNKB/... for readability of the
code.


                Device (LNKB)
                {
                        Name (_HID, EisaId ("PNP0C0F"))
                        Name (_UID, 0x02)
                        ...
                        /* Current Resources - return irq set up in BIOS */
                        Method (_CRS, 0, NotSerialized)
                        {
                                ...
                                If (LNot (PICF)) {
                                        Return (CRSP)
                                } Else {
                                        Return (CRSA)
                                }
                        }
                        ...
                }








From cristi.magherusan at gmail.com  Thu Jun  2 20:20:18 2011
From: cristi.magherusan at gmail.com (=?UTF-8?Q?Cristian_M=C4=83gheru=C8=99an=2DStanciu?=)
Date: Thu, 2 Jun 2011 20:20:18 +0200
Subject: [coreboot] [rfc] ACPI cleanup proposal
In-Reply-To: <BANLkTimugYmHXaLgQr3+SnQ-9JZiYw3tkw@mail.gmail.com>
References: <BANLkTimugYmHXaLgQr3+SnQ-9JZiYw3tkw@mail.gmail.com>
Message-ID: <BANLkTikra-O_ZZag-i=T1_+Y9Zk7keY=Cg@mail.gmail.com>

I found a few issues in the patch, please try the one attached to this
message instead.
Sorry for the clumsiness.

~Cristi
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From cristi.magherusan at gmail.com  Thu Jun  2 20:12:12 2011
From: cristi.magherusan at gmail.com (=?UTF-8?Q?Cristian_M=C4=83gheru=C8=99an=2DStanciu?=)
Date: Thu, 2 Jun 2011 20:12:12 +0200
Subject: [coreboot] [rfc] ACPI cleanup proposal
Message-ID: <BANLkTimugYmHXaLgQr3+SnQ-9JZiYw3tkw@mail.gmail.com>

Hello,

Please find attached a diff that contains my work done during the
hackathon in Prague. The motherboard code that creates ACPi is
cleaner, as you can see on the Asus M2V-MX-SE code modified as a
reference.

For some reasons the motherboard failed to boot after I applied it, so
most likely there is a bug which needs to be fixed.

I don't have access to the mainboard anymore (it was Ruik's) and I
will only have access to mine in a month or so, so I thought that I
should send the code as a RFC, maybe someone will be able to figure it
out sooner than that and why not port it to other boards if
appropriate.

Cheers,
Cristi
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From svn at coreboot.org  Fri Jun  3 12:14:56 2011
From: svn at coreboot.org (repository service)
Date: Fri, 03 Jun 2011 12:14:56 +0200
Subject: [coreboot] [commit] r6617 - trunk/src/mainboard/advansus/a785e-i
Message-ID: <E1QSRP6-0007ki-HR@ra.coresystems.de>

Author: kerry
Date: Fri Jun  3 12:14:56 2011
New Revision: 6617
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6617

Log:
advansus/a785e-i mainboard enable warning as error

Signed-off-by: Kerry She <kerry.she at amd.com>
Acked-by: Kerry She <kerry.she at amd.com>

Modified:
   trunk/src/mainboard/advansus/a785e-i/Kconfig
   trunk/src/mainboard/advansus/a785e-i/romstage.c

Modified: trunk/src/mainboard/advansus/a785e-i/Kconfig
==============================================================================
--- trunk/src/mainboard/advansus/a785e-i/Kconfig	Wed Jun  1 21:54:16 2011	(r6616)
+++ trunk/src/mainboard/advansus/a785e-i/Kconfig	Fri Jun  3 12:14:56 2011	(r6617)
@@ -107,6 +107,6 @@
 
 config WARNINGS_ARE_ERRORS
         bool
-        default n
+        default y
 
 endif #BOARD_ADVANSUS_A785E_I

Modified: trunk/src/mainboard/advansus/a785e-i/romstage.c
==============================================================================
--- trunk/src/mainboard/advansus/a785e-i/romstage.c	Wed Jun  1 21:54:16 2011	(r6616)
+++ trunk/src/mainboard/advansus/a785e-i/romstage.c	Fri Jun  3 12:14:56 2011	(r6617)
@@ -25,6 +25,7 @@
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
+#include <lib.h>
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>



From v10lator at myway.de  Fri Jun  3 12:33:28 2011
From: v10lator at myway.de (Thomas Rohloff)
Date: Fri, 3 Jun 2011 12:33:28 +0200
Subject: [coreboot] Is this board supported?
In-Reply-To: <4DE7920C.3000905@coreboot.org>
References: <20110602075247.6bd513cb@schlepptop>
	<4DE7920C.3000905@coreboot.org>
Message-ID: <20110603123328.40081039@schlepptop>

Am Thu, 02 Jun 2011 06:37:16 -0700
schrieb Stefan Reinauer <stefan.reinauer at coreboot.org>:

> On 6/1/11 10:52 PM, Thomas Rohloff wrote:
> > Hi,
> > I have a AsRock 870 Etreme3
> > ( http://www.asrock.com/mb/overview.asp?model=870%20extreme3 ) and
> > wanted to know if it's supported b coreboot.
> >
> See http://www.coreboot.org/Supported_Motherboards for a list of 
> supported boards.
> 
So it's not supported? Is there a change that it will be supported in
the near future?

> > So, is this possible? And is it possible to unlock the 4th CPU-Core
> > with coreboot?
> Yes it is possible. You will have to figure out, how, though.
> 
Can you give me some hints?



From mark.marshall at csr.com  Fri Jun  3 13:54:30 2011
From: mark.marshall at csr.com (Mark Marshall)
Date: Fri, 03 Jun 2011 12:54:30 +0100
Subject: [coreboot] [rfc] ACPI cleanup proposal
In-Reply-To: <BANLkTikra-O_ZZag-i=T1_+Y9Zk7keY=Cg@mail.gmail.com>
References: <BANLkTimugYmHXaLgQr3+SnQ-9JZiYw3tkw@mail.gmail.com>
	<BANLkTikra-O_ZZag-i=T1_+Y9Zk7keY=Cg@mail.gmail.com>
Message-ID: <isai1m$aoi$1@dough.gmane.org>

On 02/06/2011 19:20, Cristian M?gheru?an-Stanciu wrote:
> I found a few issues in the patch, please try the one attached to this
> message instead.
> Sorry for the clumsiness.
>
> ~Cristi
>
Hi.

In the new functions, all of the form acpi_write_foo, there is a pointer 
passed in that is of type acpi_header_t, called foo.  This "in" 
parameter is then set to a value by the new function?  This doesn't seem 
to be correct - either the acpi_header_t * variable should be local to 
the function or it should be a "in/out" parameter?

(I think dsdt, for instance, should be in/out.  hpet should be local to 
acpi_write_hpet).

MM




From xdrudis at tinet.cat  Fri Jun  3 14:17:29 2011
From: xdrudis at tinet.cat (Xavi Drudis Ferran)
Date: Fri, 03 Jun 2011 14:17:29 +0200
Subject: [coreboot] phoronix.com: Coreboot Finally Takes The Interest Of OEMs
Message-ID: <52429.1307103449@tinet.org>


Just saw an article on coreboot 

Coreboot Finally Takes The Interest Of OEMs
http://www.phoronix.com/scan.php?page=news_item&px=OTUyMg



From thomas at gstaedtner.net  Fri Jun  3 15:09:20 2011
From: thomas at gstaedtner.net (=?UTF-8?Q?Thomas_Gst=C3=A4dtner?=)
Date: Fri, 3 Jun 2011 15:09:20 +0200
Subject: [coreboot] phoronix.com: Coreboot Finally Takes The Interest Of
	OEMs
In-Reply-To: <52429.1307103449@tinet.org>
References: <52429.1307103449@tinet.org>
Message-ID: <BANLkTi=eHQW4-g67s2Woo41J1oBqrVe4yQ@mail.gmail.com>

On Fri, Jun 3, 2011 at 14:17, Xavi Drudis Ferran <xdrudis at tinet.cat> wrote:
>
> Just saw an article on coreboot
>
> Coreboot Finally Takes The Interest Of OEMs
> http://www.phoronix.com/scan.php?page=news_item&px=OTUyMg
>

I would get excited, but unfortunately that's just the typical
Phoronix nonsense.

That guy is like all the fortune tellers and self-proclaimed prophets:
he reports something vague without any real information - if something
close to the report happens he says "I told you so", if nothing
happens (what mostly is the case) he waits a few months and reports it
again.



From stefan.reinauer at coreboot.org  Fri Jun  3 20:43:17 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Fri, 3 Jun 2011 20:43:17 +0200
Subject: [coreboot] Is this board supported?
In-Reply-To: <20110603123328.40081039@schlepptop>
References: <20110602075247.6bd513cb@schlepptop>
	<4DE7920C.3000905@coreboot.org>
	<20110603123328.40081039@schlepptop>
Message-ID: <20110603184316.GA29494@coreboot.org>

* Thomas Rohloff <v10lator at myway.de> [110603 12:33]:
> Am Thu, 02 Jun 2011 06:37:16 -0700
> schrieb Stefan Reinauer <stefan.reinauer at coreboot.org>:
> 
> > On 6/1/11 10:52 PM, Thomas Rohloff wrote:
> > > Hi,
> > > I have a AsRock 870 Etreme3
> > > ( http://www.asrock.com/mb/overview.asp?model=870%20extreme3 ) and
> > > wanted to know if it's supported b coreboot.
> > >
> > See http://www.coreboot.org/Supported_Motherboards for a list of 
> > supported boards.
> 
> So it's not supported? 

Most likely, no. Didn't particularly check the list, but I don't think
it contains any AsRock boards right now.

> Is there a change that it will be supported in
> the near future?

If someone with the hardware steps up to do a port there is a chance
indeed. 

That someone could be you! :-)

Basically the way this works is that you look for the most similar board
in the tree, start out with that, and change it until everything works
the way you want it to. This might be an effort anywhere from an hour to
12 months ;) Most likely with AMD chipsets it's rather less time since
AMD supports coreboot quite well.

Also be sure that you have any means of recovery. A second flash chip if
yours is socketed, or an external eeprom burner for instance.

> > > So, is this possible? And is it possible to unlock the 4th CPU-Core
> > > with coreboot?
> > Yes it is possible. You will have to figure out, how, though.
> > 
> Can you give me some hints?


Have not looked into it, but I believe I read that the 3core/4core switch
is done by some code running on the EC, so it might not be a lot of work
on the bios side.






From marcj303 at gmail.com  Fri Jun  3 20:44:22 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 3 Jun 2011 12:44:22 -0600
Subject: [coreboot] [patch] revert sb800 cimx AHCI mode
Message-ID: <BANLkTinvLpgBJBvhnoJkziSP9qt-CTeFDw@mail.gmail.com>

Revert changes to set the sb800 to AHCI mode. Seabios doesn't have
this support included yet, which causes the generic Persimmon and
other CIMx sb800 platforms to not boot.

Signed-off-by: Marc Jones <marcj303 at gmail.com>


-- 
http://se-eng.com
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From heemeli at hotmail.com  Fri Jun  3 20:54:30 2011
From: heemeli at hotmail.com (Saku Sammakko)
Date: Fri, 3 Jun 2011 21:54:30 +0300
Subject: [coreboot] Asus M2A-MX progress?
Message-ID: <DUB104-w21EA61437D60A029C8A731AA7F0@phx.gbl>


Hi guys

I see the Asus M2A-MX board has a WIP status. I have one, and I'd be eager to try coreboot on it, for kicks mostly. Is anyone working on the code, a.k.a. do I have any hope of getting to try coreboot any time soon?

best regards and big hands to your work,
Sami A.
nOOb
 		 	   		  
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From uwe at hermann-uwe.de  Fri Jun  3 21:04:48 2011
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 3 Jun 2011 21:04:48 +0200
Subject: [coreboot] [PATCH] More explicite and straight way to set seed
In-Reply-To: <AANLkTi=NeTxVttn_XLm6UpmcTmiXghPwuKmuq0v2+2g=@mail.gmail.com>
References: <DD1CC71B621B004FA76856E5129D6B17045084A3@sbjgexmb1.amd.com>
	<AANLkTi=NeTxVttn_XLm6UpmcTmiXghPwuKmuq0v2+2g=@mail.gmail.com>
Message-ID: <20110603190448.GA7970@greenwood>

On Wed, Dec 01, 2010 at 10:35:41AM -0700, Marc Jones wrote:
> Acked-by: Marc Jones <marcj303 at gmail.com>

Just for archival purposes, this was r6136.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Fri Jun  3 21:46:26 2011
From: svn at coreboot.org (repository service)
Date: Fri, 03 Jun 2011 21:46:26 +0200
Subject: [coreboot] [commit] r6618 - trunk/src/include/device
Message-ID: <E1QSaKA-000135-3T@ra.coresystems.de>

Author: uwe
Date: Fri Jun  3 21:46:25 2011
New Revision: 6618
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6618

Log:
Correct wrong PCI ID for VIA K8M890 Chrome.

With the K8T800/M800 patch from r6367 the PCI IDs for the VIA chrome were
moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly.
(3220 instead of 3230). This patch defines the correct PCI ID for this device.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/include/device/pci_ids.h

Modified: trunk/src/include/device/pci_ids.h
==============================================================================
--- trunk/src/include/device/pci_ids.h	Fri Jun  3 12:14:56 2011	(r6617)
+++ trunk/src/include/device/pci_ids.h	Fri Jun  3 21:46:25 2011	(r6618)
@@ -1281,7 +1281,7 @@
 #define PCI_DEVICE_ID_VIA_K8M890CE_4	0x4336
 #define PCI_DEVICE_ID_VIA_K8M890CE_5	0x5336
 #define PCI_DEVICE_ID_VIA_K8M890CE_7	0x7336
-#define PCI_DEVICE_ID_VIA_K8M890_CHROME	0x3220
+#define PCI_DEVICE_ID_VIA_K8M890_CHROME	0x3230
 #define PCI_DEVICE_ID_VIA_K8T890CE_PEG	0xa238
 #define PCI_DEVICE_ID_VIA_K8T890CE_PEX0	0xc238
 #define PCI_DEVICE_ID_VIA_K8T890CE_PEX1	0xd238



From uwe at hermann-uwe.de  Fri Jun  3 21:48:01 2011
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 3 Jun 2011 21:48:01 +0200
Subject: [coreboot] [PATCH] Correct wrong PCI ID vor VIA K8M890 Chrome
In-Reply-To: <4D5F0AEC.1040300@gmail.com>
References: <4D5F0AEC.1040300@gmail.com>
Message-ID: <20110603194801.GB18563@greenwood>

On Sat, Feb 19, 2011 at 02:12:28AM +0200, Alex G. wrote:
> With the K8T800/M800 patch, the PCI IDs for the VIA chrome were moved
> to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly.
> (3220 instead of 3230).
> This patch defines the corect PCI ID for this device.

Indeed. Thanks, r6618.

I cross-checked with
http://www.openchrome.org/trac/browser/trunk/src/via_id.h, which also
correctly uses 0x3230.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Fri Jun  3 21:59:54 2011
From: svn at coreboot.org (repository service)
Date: Fri, 03 Jun 2011 21:59:54 +0200
Subject: [coreboot] [commit] r6619 - in trunk/src/northbridge/amd/amdmct:
	mct mct_ddr3 wrappers
Message-ID: <E1QSaXC-0004ya-13@ra.coresystems.de>

Author: mjones
Date: Fri Jun  3 21:59:52 2011
New Revision: 6619
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6619

Log:
This patch sets max freq defaults for ddr2 and ddr3for fam10.

Signed-off-by: Marc Jones <marcj303 at gmail.com>
Acked-by: Scott Duplichan <scott at notabs.org>

Modified:
   trunk/src/northbridge/amd/amdmct/mct/mct.h
   trunk/src/northbridge/amd/amdmct/mct/mct_d.h
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
   trunk/src/northbridge/amd/amdmct/wrappers/mcti.h
   trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c

Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mct.h	Fri Jun  3 21:46:25 2011	(r6618)
+++ trunk/src/northbridge/amd/amdmct/mct/mct.h	Fri Jun  3 21:59:52 2011	(r6619)
@@ -496,18 +496,6 @@
 					   0=disable
 					   1=enable*/
 
-#ifndef MAX_NODES_SUPPORTED
-#define MAX_NODES_SUPPORTED	8
-#endif
-
-#ifndef MAX_DIMMS_SUPPORTED
-#define MAX_DIMMS_SUPPORTED	8
-#endif
-
-#ifndef MAX_CS_SUPPORTED
-#define MAX_CS_SUPPORTED	8
-#endif
-
 
 /* global function */
 u32 NodePresent(u32 Node);

Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.h
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mct_d.h	Fri Jun  3 21:46:25 2011	(r6618)
+++ trunk/src/northbridge/amd/amdmct/mct/mct_d.h	Fri Jun  3 21:59:52 2011	(r6619)
@@ -667,23 +667,6 @@
 					yy1b = enable with DctSelIntLvAddr set to yyb */
 
 
-#ifndef MAX_NODES_SUPPORTED
-#define MAX_NODES_SUPPORTED	8
-#endif
-
-#ifndef MAX_DIMMS_SUPPORTED
-#define MAX_DIMMS_SUPPORTED	8
-#endif
-
-#ifndef MAX_CS_SUPPORTED
-#define MAX_CS_SUPPORTED	8
-#endif
-
-#ifndef MCT_DIMM_SPARE_NO_WARM
-#define MCT_DIMM_SPARE_NO_WARM	0
-#endif
-
-
 u32 Get_NB32(u32 dev, u32 reg);
 void Set_NB32(u32 dev, u32 reg, u32 val);
 u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c	Fri Jun  3 21:46:25 2011	(r6618)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c	Fri Jun  3 21:59:52 2011	(r6619)
@@ -1315,7 +1315,7 @@
 	u16 word;
 
 	/* Get CPU Si Revision defined limit (NPT) */
-	proposedFreq = 533;	 /* Rev F0 programmable max memclock is */
+	proposedFreq = 800;	 /* Rev F0 programmable max memclock is */
 
 	/*Get User defined limit if  "limit" mode */
 	if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h	Fri Jun  3 21:46:25 2011	(r6618)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h	Fri Jun  3 21:59:52 2011	(r6619)
@@ -728,22 +728,6 @@
 					yy1b = enable with DctSelIntLvAddr set to yyb */
 
 
-#ifndef MAX_NODES_SUPPORTED
-#define MAX_NODES_SUPPORTED	8
-#endif
-
-#ifndef MAX_DIMMS_SUPPORTED
-#define MAX_DIMMS_SUPPORTED	8
-#endif
-
-#ifndef MAX_CS_SUPPORTED
-#define MAX_CS_SUPPORTED	8
-#endif
-
-#ifndef MCT_DIMM_SPARE_NO_WARM
-#define MCT_DIMM_SPARE_NO_WARM	0
-#endif
-
 u32 Get_NB32(u32 dev, u32 reg);
 void Set_NB32(u32 dev, u32 reg, u32 val);
 u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);

Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti.h
==============================================================================
--- trunk/src/northbridge/amd/amdmct/wrappers/mcti.h	Fri Jun  3 21:46:25 2011	(r6618)
+++ trunk/src/northbridge/amd/amdmct/wrappers/mcti.h	Fri Jun  3 21:59:52 2011	(r6619)
@@ -57,6 +57,18 @@
 #define MAX_CS_SUPPORTED		8
 #endif
 
+#ifndef MCT_DIMM_SPARE_NO_WARM
+#define MCT_DIMM_SPARE_NO_WARM	0
+#endif
+
+#ifndef MEM_MAX_LOAD_FREQ
+#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+ #define MEM_MAX_LOAD_FREQ		800
+#else
+ #define MEM_MAX_LOAD_FREQ		400
+#endif
+#endif
+
 #define MCT_TRNG_KEEPOUT_START		0x00000C00
 #define MCT_TRNG_KEEPOUT_END		0x00000CFF
 

Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c	Fri Jun  3 21:46:25 2011	(r6618)
+++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c	Fri Jun  3 21:59:52 2011	(r6619)
@@ -48,7 +48,7 @@
 		//val =  200;	/* 200MHz(DDR400) */
 		//val =  266;	/* 266MHz(DDR533) */
 		//val =  333;	/* 333MHz(DDR667) */
-		val =  400;	/* 400MHz(DDR800) */
+		val =  MEM_MAX_LOAD_FREQ;;	/* 400MHz(DDR800) */
 		break;
 	case NV_ECC_CAP:
 #if SYSTEM_TYPE == SERVER
@@ -237,7 +237,7 @@
 
 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 {
-	pDCTstat->PresetmaxFreq = 400;
+	pDCTstat->PresetmaxFreq = MEM_MAX_LOAD_FREQ;
 }
 
 #ifdef UNUSED_CODE



From marcj303 at gmail.com  Fri Jun  3 22:05:20 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 3 Jun 2011 14:05:20 -0600
Subject: [coreboot] [patch] update ddr3 max frequency
In-Reply-To: <BANLkTim3OWzGEAThSkMtn0Neh_+sSJKRAQ@mail.gmail.com>
References: <BANLkTik-w6xpF-y91X-AyFxKnpCzSKor2w@mail.gmail.com>
	<4DB6D983.8060708@georgi-clan.de>
	<BANLkTim3OWzGEAThSkMtn0Neh_+sSJKRAQ@mail.gmail.com>
Message-ID: <BANLkTikp5F5hwbKAXUN-uE7FKMe-6Pgo+Q@mail.gmail.com>

On Tue, Apr 26, 2011 at 6:31 PM, Marc Jones <marcj303 at gmail.com> wrote:
> On Tue, Apr 26, 2011 at 8:41 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
>> Am 26.04.2011 15:59, schrieb Marc Jones:
>>> We found this with some testing at BTDC. This patch sets max freq
>>> defaults for ddr2 and ddr3for fam10. It may be overridden by a
>>> developer setting it in romstage.c.
>> Please find a better place for that. This way of doing things relies on
>> us including code fragments from romstage.c.
>>
>
> I don't understand what you mean about including code fragments from
> romstage. It is for memory setup and only used in romstage.
>
>> If it's actually necessary, please put it in northbridge/amd/amdfam10's
>> Kconfig as a hidden option (ie. no UI strings).
>> I'd love to see Kconfig options reduced as well, but where we need to
>> configure stuff, we have a configuration mechanism around, so we don't
>> have to abuse our current code layout for that anymore.
>
> I thought about a kconfig setting, but that seems to abuse kconfig.
> It isn't a feature, so much as an setting override. ?If we want to put
> items like in kconfg, we should do it for all the items in mcti.h.
> This can also get a little strange as the options start to rely on
> other kconfig settings.
>
>> (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005
>

I removed the commend about where the override could be done. I don't
think it should be a common occurance. If a config hook is needed, we
can discuss it further.

r6619

Marc

-- 
http://se-eng.com



From ansarm at gmail.com  Sat Jun  4 05:33:15 2011
From: ansarm at gmail.com (Ansar Mohammed)
Date: Fri, 3 Jun 2011 23:33:15 -0400
Subject: [coreboot] Wyse S10
Message-ID: <BANLkTimeD=U2BtKsDjLZ=h2m7mj_oeo3PQ@mail.gmail.com>

Hello All,

First off, I have just stumbled onto this project after tearing my hair out
with a Wyse S10 and the ultra crappy BIOS it comes with. Thank you for what
you do guys..


I have searched the archives of this DL and I see a few people have played
with installing coreboot on a Wyse S10.
Has anyone gotten it to successfully work?
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From ansarm at gmail.com  Sat Jun  4 06:48:47 2011
From: ansarm at gmail.com (Ansar Mohammed)
Date: Sat, 4 Jun 2011 00:48:47 -0400
Subject: [coreboot] Wyse S10
Message-ID: <BANLkTi=e8C0LP0XM=UX0PT3pRsSQUc1t-w@mail.gmail.com>

Hello All,
First off, I have just stumbled onto this project after tearing my hair out
with a Wyse S10 and the ultra crappy BIOS it comes with. Thank you for what
you do guys..
 I have searched the archives of this DL and I see a few people have played
with installing coreboot on a Wyse S10.
Has anyone gotten it to successfully work?
-------------- next part --------------
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From mbuschman at lucidmachines.com  Sat Jun  4 08:10:29 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:29 -0500
Subject: [coreboot] [PATCH 01/16] Port persimmon r6572 to e350m1: I/O APIC ID
Message-ID: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/acpi_tables.c  |    2 +-
 src/mainboard/asrock/e350m1/get_bus_conf.c |    2 +-
 src/mainboard/asrock/e350m1/mptable.c      |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c
index 292aaad..20b0dc2 100644
--- a/src/mainboard/asrock/e350m1/acpi_tables.c
+++ b/src/mainboard/asrock/e350m1/acpi_tables.c
@@ -64,7 +64,7 @@ unsigned long acpi_fill_madt(unsigned long current)
   current = acpi_create_madt_lapics(current);
 
   /* Write SB800 IOAPIC, only one */
-  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
              IO_APIC_ADDR, 0);
 
   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
index 9e148d0..5f48498 100644
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ b/src/mainboard/asrock/e350m1/get_bus_conf.c
@@ -138,7 +138,7 @@ void get_bus_conf(void)
 
   /* I/O APICs:   APIC ID Version State   Address */
   bus_isa = 10;
-  apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+  apicid_base = CONFIG_MAX_CPUS;
 //#if CONFIG_LOGICAL_CPUS==1
 //  apicid_base = get_apicid_base(1);
 //#endif
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 78eec6a..e286e6f 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
   dword |= (pm_ioread(0x35) & 0xFF) << 8;
   dword |= (pm_ioread(0x36) & 0xFF) << 16;
   dword |= (pm_ioread(0x37) & 0xFF) << 24;
-  smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+  smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
 
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:33 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:33 -0500
Subject: [coreboot] [PATCH 05/16] Port persimmon r6582 to e350m1: 33 MHz SPI
	read early
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-5-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Enable 33 MHz fast mode SPI read early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/romstage.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index d63fbe8..d761d73 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -47,6 +47,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
   u32 val;
   u8 reg8;
 
+  // early enable of SPI 33 MHz fast mode read
+  if (boot_cpu())
+    {
+    volatile u32 *spiBase = (void *) 0xa0000000;
+    u32 save;
+    __outdword (0xcf8, 0x8000a3a0);
+    save = __indword (0xcfc);
+    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
+    spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
+    spiBase [0] |= 1 << 18; // fast read enable
+    __outdword (0xcfc, save); // clear temp base
+    }
+
   if (!cpu_init_detectedx && boot_cpu()) {
     post_code(0x30);
     sb_poweron_init();
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:34 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:34 -0500
Subject: [coreboot] [PATCH 06/16] Port persimmon r6583 to e350m1: pstate 0
	early
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-6-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Switch processor cores to pstate 0 early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/romstage.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index d761d73..7f0b9df 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -47,6 +47,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
   u32 val;
   u8 reg8;
 
+  // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+  __writemsr (0xc0010062, 0);
+
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:31 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:31 -0500
Subject: [coreboot] [PATCH 03/16] Port persimmon r6574 to e350m1: MMCONF size
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-3-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/agesawrapper.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index e946a3b..4e3819a 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -138,7 +138,8 @@ agesawrapper_amdinitmmio (
    Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
    Address MSR register.
   */
-  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+
+  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
   LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
   
   /*
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:32 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:32 -0500
Subject: [coreboot] [PATCH 04/16] Port persimmon r6578 and r6596 to e350m1:
	MMCONF base
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-4-git-send-email-mbuschman@lucidmachines.com>

From: Marc Jones <marcj303 at gmail.com>

Remove multiple mmconf settings and just use kconfig setting.

Signed-off-by: Peter Stuge <peter at stuge.se>
---
 src/mainboard/asrock/e350m1/dsdt.asl |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl
index 32d4497..ddde158 100644
--- a/src/mainboard/asrock/e350m1/dsdt.asl
+++ b/src/mainboard/asrock/e350m1/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock (
 	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
 	Name(PBLN, 0x0)	/* Length of BIOS area */
 
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 
 	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:37 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:37 -0500
Subject: [coreboot] [PATCH 09/16] Port persimmon r6587 to e350m1: RTC is not
	PIIX4 compatible
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-9-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Declare RTC as not PIIX4 compatible to match AMD hardware.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/dsdt.asl |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl
index ddde158..ce23245 100644
--- a/src/mainboard/asrock/e350m1/dsdt.asl
+++ b/src/mainboard/asrock/e350m1/dsdt.asl
@@ -1379,7 +1379,7 @@ DefinitionBlock (
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:35 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:35 -0500
Subject: [coreboot] [PATCH 07/16] Port persimmon r6584 and r6601 to e350m1:
	SPI prefetch early
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-7-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/romstage.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 7f0b9df..41f9a6b 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -50,6 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);
 
+  // early enable of PrefetchEnSPIFromHost
+  if (boot_cpu())
+    {
+    __outdword (0xcf8, 0x8000a3b8);
+    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
+    }
+
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:39 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:39 -0500
Subject: [coreboot] [PATCH 11/16] Port persimmon r6589 to e350m1: Strip down
	AGESA options
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-11-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Remove some non-essential agesa options to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/buildOpts.c |   24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index aa32bb0..cde9df7 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -80,16 +80,16 @@
 #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT     TRUE
 
 #define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
 #define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
 //#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
 #define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
 #define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
 #define BLDOPT_REMOVE_DQS_TRAINING            FALSE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
 #define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
@@ -97,17 +97,17 @@
   #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
   #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
-//#define BLDOPT_REMOVE_SRAT            TRUE
-//#define BLDOPT_REMOVE_SLIT            TRUE
-//#define BLDOPT_REMOVE_WHEA            TRUE
-//#define BLDOPT_REMOVE_DMI             TRUE
-//#define BLDOPT_REMOVE_HT_ASSIST         TRUE
-//#define BLDOPT_REMOVE_ATM_MODE          TRUE
+#define BLDOPT_REMOVE_SRAT            TRUE
+#define BLDOPT_REMOVE_SLIT            TRUE
+#define BLDOPT_REMOVE_WHEA            TRUE
+#define BLDOPT_REMOVE_DMI             TRUE
+#define BLDOPT_REMOVE_HT_ASSIST         TRUE
+#define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
-//#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
+#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
 #define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
 
 /*
@@ -123,7 +123,7 @@
 #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
 #define AGESA_ENTRY_INIT_RESUME                   TRUE
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
 
 /* 
  * Agesa configuration values selection.  
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:40 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:40 -0500
Subject: [coreboot] [PATCH 12/16] Port persimmon r6590 to e350m1: Work
	around memory allocation problem
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-12-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Fix memory allocation problem in amdInitLate. Disabled until further debug.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/agesawrapper.c |   35 +++++++++++++--------------
 1 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index 4e3819a..9f587b9 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -444,33 +444,32 @@ agesawrapper_amdinitlate (
   )
 {
   AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
+  AMD_INTERFACE_PARAMS AmdParamStruct = {0};
+  AMD_LATE_PARAMS *AmdLateParams;
 
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
+  return 0; // this causes bad ACPI SSDT, need to debug
 
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-  Status = AmdInitLate (&AmdLateParams);
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+  AmdParamStruct.AllocationMethod = PostMemDram;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdCreateStruct (&AmdParamStruct);
+  AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+  Status = AmdInitLate (AmdLateParams);
   if (Status != AGESA_SUCCESS) {
     agesawrapper_amdreadeventlog();
     ASSERT(Status == AGESA_SUCCESS);
   }
 
-  DmiTable       = AmdLateParams.DmiTable;
-  AcpiPstate     = AmdLateParams.AcpiPState;
-  AcpiSrat       = AmdLateParams.AcpiSrat;
-  AcpiSlit       = AmdLateParams.AcpiSlit;
+  DmiTable    = AmdLateParams->DmiTable;
+  AcpiPstate  = AmdLateParams->AcpiPState;
+  AcpiSrat    = AmdLateParams->AcpiSrat;
+  AcpiSlit    = AmdLateParams->AcpiSlit;
 
-  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib       = AmdLateParams.AcpiAlib;
+  AcpiWheaMce = AmdLateParams->AcpiWheaMce;
+  AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
+  AcpiAlib    = AmdLateParams->AcpiAlib;
 
+  AmdReleaseStruct (&AmdParamStruct);
   return (UINT32)Status;
 }
 
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:38 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:38 -0500
Subject: [coreboot] [PATCH 10/16] Port persimmon r6588 to e350m1: Legacy
	video framebuffer
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-10-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Declare legacy video frame buffer so that Windows generic VGA driver will work.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/dsdt.asl |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl
index ce23245..8dc40d0 100644
--- a/src/mainboard/asrock/e350m1/dsdt.asl
+++ b/src/mainboard/asrock/e350m1/dsdt.asl
@@ -1483,9 +1483,8 @@ DefinitionBlock (
 					0xF300			/* length */
 				)
 
-#if 0
-				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+#if 0
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:30 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:30 -0500
Subject: [coreboot] [PATCH 02/16] Port persimmon r6573 to e350m1: VGA,
	PCI MMIO and SB800 legacy
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-2-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/agesawrapper.c |   37 ++++++++++++++-------------
 1 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index 649fcb7..e946a3b 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -85,38 +85,39 @@ agesawrapper_amdinitcpuio (
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
   
-  /* Enable MMIO on AMD CPU Address Map Controller */
-  
-  /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
+  /* Enable legacy video routing: D18F1xF4 VGA Enable */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+  PciData = 1;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+
+  /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+   * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+   * set to non-posted regions.
+   */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-  PciData = 0x00000B00;
+  PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
+  PciData |= 1 << 7;    // set NP (non-posted) bit
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-  PciData = 0x00000A03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  
-  /* Set TOM-DFFFFFFF to Node0 Link0. */
+  PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+   
+  /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-  PciData = 0x00DFFF00;
+  PciData = 0x00FECF00; // last address before non-posted range
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
-  PciData = 0x00FFFF00 | 0x80;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
-  PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
+   
+  /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-  PciData = 0x00000013;
+  PciData = 0x00000003;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:36 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:36 -0500
Subject: [coreboot] [PATCH 08/16] Port persimmon r6586 to e350m1: FADT
	revision
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-8-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Make fadt revision match its length. Solves Windows 7 checked build assert.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/fadt.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/fadt.c b/src/mainboard/asrock/e350m1/fadt.c
index 165a980..0b37885 100644
--- a/src/mainboard/asrock/e350m1/fadt.c
+++ b/src/mainboard/asrock/e350m1/fadt.c
@@ -53,7 +53,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
 	header->length = 244;
-	header->revision = 1;
+	header->revision = 3;
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:41 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:41 -0500
Subject: [coreboot] [PATCH 13/16] Port persimmon r6591 to e350m1: ROM cache
	early
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-13-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Enable rom cache early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
---
 src/mainboard/asrock/e350m1/agesawrapper.c |    7 -------
 src/mainboard/asrock/e350m1/romstage.c     |    5 +++++
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index 9f587b9..e98d874 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -157,13 +157,6 @@ agesawrapper_amdinitmmio (
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   
-
-  /* Set ROM cache onto WP to decrease post time */
-  MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
-  LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-  MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
-  LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
-
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 41f9a6b..4b45caf 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -47,6 +47,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
   u32 val;
   u8 reg8;
 
+  // all cores: allow caching of flash chip code and data
+  // (there are no cache-as-ram reliability concerns with family 14h)
+  __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
+  __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);
 
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:44 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:44 -0500
Subject: [coreboot] [PATCH 16/16] Port persimmon r6594 to e350m1: Cosmetic
	cleanup
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-16-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Signed-off-by: Peter Stuge <peter at stuge.se>
---
 src/mainboard/asrock/e350m1/get_bus_conf.c |   18 +-----------------
 1 files changed, 1 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
index 5f48498..cc7fb5d 100644
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ b/src/mainboard/asrock/e350m1/get_bus_conf.c
@@ -42,25 +42,12 @@ u32 pci1234x[] = {
   0x0000ff0,
 };
 
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
-  0x20202020,
-};
-
 u32 bus_type[256];
-
 u32 sbdn_sb800;
 
-//KZ [092110]extern void get_pci1234(void);
-
 static u32 get_bus_conf_done = 0;
 
 
-
-
 void get_bus_conf(void)
 {
   u32 apicid_base;
@@ -139,8 +126,5 @@ void get_bus_conf(void)
   /* I/O APICs:   APIC ID Version State   Address */
   bus_isa = 10;
   apicid_base = CONFIG_MAX_CPUS;
-//#if CONFIG_LOGICAL_CPUS==1
-//  apicid_base = get_apicid_base(1);
-//#endif
-  apicid_sb800 = apicid_base + 0;
+  apicid_sb800 = apicid_base;
 }
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:43 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:43 -0500
Subject: [coreboot] [PATCH 15/16] Port persimmon r6593 to e350m1: Remove
	unused Kconfig options
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-15-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Signed-off-by: Peter Stuge <peter at stuge.se>
---
 src/mainboard/asrock/e350m1/Kconfig |   15 ---------------
 1 files changed, 0 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index 9b73ea3..fdcc3c9 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -22,8 +22,6 @@ if BOARD_ASROCK_E350M1
 config BOARD_SPECIFIC_OPTIONS # dummy
         def_bool y
   select ARCH_X86
-        select DIMM_DDR3
-        select DIMM_UNREGISTERED
   select CPU_AMD_AGESA_WRAPPER_FAMILY14
   select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
   select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
@@ -42,7 +40,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
   select AMDMCT
         select HAVE_ACPI_TABLES
   select BOARD_ROMSIZE_KB_4096
-  select ENABLE_APIC_EXT_ID
   select TINY_BOOTBLOCK
         select GFXUMA
 
@@ -86,18 +83,6 @@ config MEM_TRAIN_SEQ
         int
         default 2
 
-config SB_HT_CHAIN_ON_BUS0
-        int
-        default 1
-
-config HT_CHAIN_END_UNITID_BASE
-        hex
-        default 0x1
-
-config HT_CHAIN_UNITID_BASE
-        hex
-        default 0x0
-
 config IRQ_SLOT_COUNT
         int
         default 11
-- 
1.7.4.1




From mbuschman at lucidmachines.com  Sat Jun  4 08:10:42 2011
From: mbuschman at lucidmachines.com (mbuschman at lucidmachines.com)
Date: Sat,  4 Jun 2011 01:10:42 -0500
Subject: [coreboot] [PATCH 14/16] Port persimmon r6592 to e350m1: Update GPP
	port configuration
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <1307167844-13392-14-git-send-email-mbuschman@lucidmachines.com>

From: Scott Duplichan <scott at notabs.org>

Signed-off-by: Peter Stuge <peter at stuge.se>
---
 src/mainboard/asrock/e350m1/devicetree.cb |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 9dceae6..d1e4a8b 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -99,12 +99,12 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
 					end #LPC
   					device pci 14.4 on end # PCI 0x4384
 	  				device pci 14.5 on end # USB 2
-					device pci 15.0 on end # PCIe PortA
-					device pci 15.1 on end # PCIe PortB
-					device pci 15.2 on end # PCIe PortC
-					device pci 15.3 on end # PCIe PortD
-					register "gpp_configuration" = "4" #1:1:1:1
-		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+					device pci 15.0 off end # PCIe PortA
+					device pci 15.1 off end # PCIe PortB
+					device pci 15.2 off end # PCIe PortC
+					device pci 15.3 off end # PCIe PortD
+					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
+ 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx_wrapper/sb800
 #                       end #  device pci 18.0
 # These seem unnecessary
-- 
1.7.4.1




From jakllsch at kollasch.net  Sat Jun  4 15:59:23 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Sat, 4 Jun 2011 13:59:23 +0000
Subject: [coreboot] [patch] revert sb800 cimx AHCI mode
In-Reply-To: <BANLkTinvLpgBJBvhnoJkziSP9qt-CTeFDw@mail.gmail.com>
References: <BANLkTinvLpgBJBvhnoJkziSP9qt-CTeFDw@mail.gmail.com>
Message-ID: <20110604135922.GA4184@tarantulon.kollasch.net>

On Fri, Jun 03, 2011 at 12:44:22PM -0600, Marc Jones wrote:
> Revert changes to set the sb800 to AHCI mode. Seabios doesn't have
> this support included yet, which causes the generic Persimmon and
> other CIMx sb800 platforms to not boot.
> 
> Signed-off-by: Marc Jones <marcj303 at gmail.com>

Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>



From jakllsch at kollasch.net  Sat Jun  4 16:01:37 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Sat, 4 Jun 2011 14:01:37 +0000
Subject: [coreboot] [patch v2] ck804 ACPI PIC/APIC interrupt logic
In-Reply-To: <20110523192845.GQ24800@tarantulon.kollasch.net>
References: <20110523192845.GQ24800@tarantulon.kollasch.net>
Message-ID: <20110604140137.GB4184@tarantulon.kollasch.net>

Add ACPI automatic PIC/APIC interrupt routing logic for ck804.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
-------------- next part --------------
Index: src/southbridge/nvidia/ck804/acpi/ck804.asl
===================================================================
--- src/southbridge/nvidia/ck804/acpi/ck804.asl	(revision 0)
+++ src/southbridge/nvidia/ck804/acpi/ck804.asl	(revision 0)
@@ -0,0 +1,618 @@
+Device (LPCB) {
+	Name (_ADR, 0x00010000)
+	OperationRegion (LPC0, PCI_Config, 0x00, 0x100)
+	Field (LPC0, AnyAcc, NoLock, Preserve) {
+		Offset (0x7c),
+		INTA, 4, INTB, 4,
+		INTC, 4, INTD, 4,
+		INTE, 4, INTF, 4,
+		INTG, 4, INTH, 4,
+
+		INTI, 4, INTJ, 4,
+		INTK, 4, INTL, 4,
+		INTM, 4, INTN, 4,
+		INTO, 4, INTP, 4,
+
+		INTQ, 4, INTR, 4,
+		INTS, 4, INTT, 4,
+		INTU, 4, INTV, 4,
+		INTW, 4, INTX, 4,
+	}
+}
+
+/* set "A", 8259 interrupts */
+Name (PRSA, ResourceTemplate () {
+	IRQ(Level, ActiveLow, Shared) {5, 7, 10, 11}
+})
+Method (CRSA, 1, Serialized) {
+	Name (LRTL, ResourceTemplate() {
+		IRQ(Level, ActiveLow, Shared) {}
+	})
+	CreateWordField(LRTL, 1, LIRQ)
+	ShiftLeft(1, Arg0, LIRQ)
+	Return (LRTL)
+}
+Method (SRSA, 1, Serialized) {
+	CreateWordField(Arg0, 1, LIRQ)
+	FindSetRightBit(LIRQ, Local0)
+	Decrement(Local0)
+	Return (Local0)
+}
+
+/* set "B", external (PCI) APIC interrupts */
+Name (PRSB, ResourceTemplate () {
+	Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {
+		16, 17, 18, 19,
+	}
+})
+Method (CRSB, 1, Serialized) {
+	Name (LRTL, ResourceTemplate() {
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { 0 }
+	})
+	CreateDWordField (LRTL, 5, LIRQ)
+	If (LEqual (Arg0, 8)) {
+		Store (16, LIRQ)
+	} ElseIf (LEqual (Arg0, 1)) {
+		Store (17, LIRQ)
+	} ElseIf (LEqual (Arg0, 2)) {
+		Store (18, LIRQ)
+	} ElseIf (LEqual (Arg0, 13)) {
+		Store (19, LIRQ)
+	} Else {
+		Store (0, LIRQ)
+	}
+	Return (LRTL)
+}
+Method (SRSB, 1, Serialized) {
+	CreateDWordField(Arg0, 5, LIRQ)
+	If (LEqual (LIRQ, 16)) {
+		Return (8)
+	} ElseIf (LEqual (LIRQ, 17)) {
+		Return (1)
+	} ElseIf (LEqual (LIRQ, 18)) {
+		Return (2)
+	} ElseIf (LEqual (LIRQ, 19)) {
+		Return (13)
+	} Else {
+		Return (0)
+	}
+}
+
+/* set "C", southbridge APIC interrupts */
+Name (PRSC, ResourceTemplate () {
+	Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {
+		20, 21, 22, 23,
+	}
+})
+Method (CRSC, 1, Serialized) {
+	Name (LRTL, ResourceTemplate() {
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { 0 }
+	})
+	CreateDWordField (LRTL, 5, LIRQ)
+	If (LEqual (Arg0, 8)) {
+		Store (20, LIRQ)
+	} ElseIf (LEqual (Arg0, 13)) {
+		Store (21, LIRQ)
+	} ElseIf (LEqual (Arg0, 2)) {
+		Store (22, LIRQ)
+	} ElseIf (LEqual (Arg0, 1)) {
+		Store (23, LIRQ)
+	} Else {
+		Store (0, LIRQ)
+	}
+	Return (LRTL)
+}
+Method (SRSC, 1, Serialized) {
+	CreateDWordField(Arg0, 5, LIRQ)
+	If (LEqual (LIRQ, 20)) {
+		Return (8)
+	} ElseIf (LEqual (LIRQ, 21)) {
+		Return (13)
+	} ElseIf (LEqual (LIRQ, 22)) {
+		Return (2)
+	} ElseIf (LEqual (LIRQ, 23)) {
+		Return (1)
+	} Else {
+		Return (0)
+	}
+}
+
+Device (LNKA) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 1)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTA) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTA)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSB)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSB(\_SB.PCI0.LPCB.INTA))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTA))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA)
+		}
+	}
+}
+Device (LNKB) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 2)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTB) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTB)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSB)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSB(\_SB.PCI0.LPCB.INTB))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTB))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB)
+		}
+	}
+}
+Device (LNKC) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 3)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTC) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTC)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSB)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSB(\_SB.PCI0.LPCB.INTC))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTC))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC)
+		}
+	}
+}
+Device (LNKD) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 4)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTD) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTD)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSB)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSB(\_SB.PCI0.LPCB.INTD))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTD))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD)
+		}
+	}
+}
+Device (LNKE) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 5)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTE) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTE)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSB)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSB(\_SB.PCI0.LPCB.INTE))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTE))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTE)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTE)
+		}
+	}
+}
+Device (LLAS) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 6)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTK) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTK)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSC)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSC(\_SB.PCI0.LPCB.INTK))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTK))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTK)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK)
+		}
+	}
+}
+Device (LUOH) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 7)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTQ) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTQ)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSC)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSC(\_SB.PCI0.LPCB.INTQ))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTQ))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ)
+		}
+	}
+}
+Device (LUEH) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 8)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTL) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTL)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSC)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSC(\_SB.PCI0.LPCB.INTL))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTL))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL)
+		}
+	}
+}
+Device (LAUD) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 9)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTU) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTU)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSC)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSC(\_SB.PCI0.LPCB.INTU))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTU))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTU)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTU)
+		}
+	}
+}
+Device (LMOD) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 10)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTV) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTV)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSC)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSC(\_SB.PCI0.LPCB.INTV))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTV))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTV)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTV)
+		}
+	}
+}
+Device (LPA0) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 11)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTW) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTW)
+		Store (0, \_SB.PCI0.LPCB.INTX)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSC)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSC(\_SB.PCI0.LPCB.INTW))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTW))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSC(Arg0), Local0)
+		} Else {
+			Store (SRSA(Arg0), Local0)
+		}
+		Store(Local0, \_SB.PCI0.LPCB.INTW)
+		Store(Local0, \_SB.PCI0.LPCB.INTX)
+	}
+}
+Device (LSA0) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 12)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTP) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTP)
+		Store (0, \_SB.PCI0.LPCB.INTG)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSC)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSC(\_SB.PCI0.LPCB.INTP))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTP))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSC(Arg0), Local0)
+		} Else {
+			Store (SRSA(Arg0), Local0)
+		}
+		Store(Local0, \_SB.PCI0.LPCB.INTP)
+		Store(Local0, \_SB.PCI0.LPCB.INTG)
+	}
+}
+Device (LSA1) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 13)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTO) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTO)
+		Store (0, \_SB.PCI0.LPCB.INTF)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSC)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSC(\_SB.PCI0.LPCB.INTO))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTO))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSC(Arg0), Local0)
+		} Else {
+			Store (SRSA(Arg0), Local0)
+		}
+		Store(Local0, \_SB.PCI0.LPCB.INTO)
+		Store(Local0, \_SB.PCI0.LPCB.INTF)
+	}
+}
+Device (LEMA) {
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 14)
+	Method (_STA, 0, Serialized) {
+		If (\_SB.PCI0.LPCB.INTS) {
+			Return (0xb)
+		} Else {
+			Return (0x9)
+		}
+	}
+	Method (_DIS, 0, Serialized) {
+		Store (0, \_SB.PCI0.LPCB.INTS)
+	}
+	Method (_PRS, 0, Serialized) {
+		If (PICM) {
+			Return (PRSC)
+		} Else {
+			Return (PRSA)
+		}
+	}
+	Method (_CRS, 0, Serialized) {
+		If (PICM) {
+			Return (CRSC(\_SB.PCI0.LPCB.INTS))
+		} Else {
+			Return (CRSA(\_SB.PCI0.LPCB.INTS))
+		}
+	}
+	Method (_SRS, 1, Serialized) {
+		If (PICM) {
+			Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTS)
+		} Else {
+			Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTS)
+		}
+	}
+}

From svn at coreboot.org  Sat Jun  4 17:40:13 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:40:13 +0200
Subject: [coreboot] [commit] r6620 - trunk/src/southbridge/via/vt8237r
Message-ID: <E1QSsxR-0000MK-BR@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:40:12 2011
New Revision: 6620
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6620

Log:
vt8237r: Simplify bootblock init to work around nested if() romcc problem

During the hackathon in Prague we discovered that romcc has a problem
compiling the previous nested if() statements correctly. This patch
makes the code a little simpler, and indeed works around the romcc issue.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/southbridge/via/vt8237r/bootblock.c

Modified: trunk/src/southbridge/via/vt8237r/bootblock.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/bootblock.c	Fri Jun  3 21:59:52 2011	(r6619)
+++ trunk/src/southbridge/via/vt8237r/bootblock.c	Sat Jun  4 17:40:12 2011	(r6620)
@@ -33,20 +33,23 @@
 	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
 		    PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
 
-	if (dev == PCI_DEV_INVALID) {
-		/* Power management controller */
-		dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
-			PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
-
-		if (dev == PCI_DEV_INVALID) {
-			/* Power management controller */
-			dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
-				PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);
-
-			if (dev == PCI_DEV_INVALID)
-				return;
-		}
-	}
+	if (dev != PCI_DEV_INVALID)
+		goto found;
 
+	/* Power management controller */
+	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
+		PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+
+	if (dev != PCI_DEV_INVALID)
+		goto found;
+
+	/* Power management controller */
+	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
+		PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);
+
+	if (dev == PCI_DEV_INVALID)
+		return;
+
+found:
 	pci_write_config8(dev, 0x41, 0x7f);
 }



From svn at coreboot.org  Sat Jun  4 17:43:16 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:43:16 +0200
Subject: [coreboot] [commit] r6621 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt0O-0004HO-0N@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:43:15 2011
New Revision: 6621
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6621

Log:
Port persimmon r6572 to e350m1: I/O APIC ID

1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/acpi_tables.c
   trunk/src/mainboard/asrock/e350m1/get_bus_conf.c
   trunk/src/mainboard/asrock/e350m1/mptable.c

Modified: trunk/src/mainboard/asrock/e350m1/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/acpi_tables.c	Sat Jun  4 17:40:12 2011	(r6620)
+++ trunk/src/mainboard/asrock/e350m1/acpi_tables.c	Sat Jun  4 17:43:15 2011	(r6621)
@@ -64,7 +64,7 @@
   current = acpi_create_madt_lapics(current);
 
   /* Write SB800 IOAPIC, only one */
-  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
              IO_APIC_ADDR, 0);
 
   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)

Modified: trunk/src/mainboard/asrock/e350m1/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/get_bus_conf.c	Sat Jun  4 17:40:12 2011	(r6620)
+++ trunk/src/mainboard/asrock/e350m1/get_bus_conf.c	Sat Jun  4 17:43:15 2011	(r6621)
@@ -138,7 +138,7 @@
 
   /* I/O APICs:   APIC ID Version State   Address */
   bus_isa = 10;
-  apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+  apicid_base = CONFIG_MAX_CPUS;
 //#if CONFIG_LOGICAL_CPUS==1
 //  apicid_base = get_apicid_base(1);
 //#endif

Modified: trunk/src/mainboard/asrock/e350m1/mptable.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/mptable.c	Sat Jun  4 17:40:12 2011	(r6620)
+++ trunk/src/mainboard/asrock/e350m1/mptable.c	Sat Jun  4 17:43:15 2011	(r6621)
@@ -69,7 +69,7 @@
   dword |= (pm_ioread(0x35) & 0xFF) << 8;
   dword |= (pm_ioread(0x36) & 0xFF) << 16;
   dword |= (pm_ioread(0x37) & 0xFF) << 24;
-  smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+  smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
 
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);



From svn at coreboot.org  Sat Jun  4 17:43:39 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:43:39 +0200
Subject: [coreboot] [commit] r6622 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt0l-0004tC-Fa@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:43:38 2011
New Revision: 6622
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6622

Log:
Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy

1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/agesawrapper.c

Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/agesawrapper.c	Sat Jun  4 17:43:15 2011	(r6621)
+++ trunk/src/mainboard/asrock/e350m1/agesawrapper.c	Sat Jun  4 17:43:38 2011	(r6622)
@@ -85,38 +85,39 @@
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
   
-  /* Enable MMIO on AMD CPU Address Map Controller */
-  
-  /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
+  /* Enable legacy video routing: D18F1xF4 VGA Enable */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+  PciData = 1;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+
+  /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+   * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+   * set to non-posted regions.
+   */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-  PciData = 0x00000B00;
+  PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
+  PciData |= 1 << 7;    // set NP (non-posted) bit
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-  PciData = 0x00000A03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  
-  /* Set TOM-DFFFFFFF to Node0 Link0. */
+  PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+   
+  /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-  PciData = 0x00DFFF00;
+  PciData = 0x00FECF00; // last address before non-posted range
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
-  PciData = 0x00FFFF00 | 0x80;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
-  PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
+   
+  /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-  PciData = 0x00000013;
+  PciData = 0x00000003;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   Status = AGESA_SUCCESS;
   return (UINT32)Status;



From svn at coreboot.org  Sat Jun  4 17:43:57 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:43:57 +0200
Subject: [coreboot] [commit] r6623 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt13-0005Nx-3Z@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:43:56 2011
New Revision: 6623
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6623

Log:
Port persimmon r6574 to e350m1: MMCONF size

Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/agesawrapper.c

Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/agesawrapper.c	Sat Jun  4 17:43:38 2011	(r6622)
+++ trunk/src/mainboard/asrock/e350m1/agesawrapper.c	Sat Jun  4 17:43:56 2011	(r6623)
@@ -138,7 +138,8 @@
    Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
    Address MSR register.
   */
-  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+
+  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
   LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
   
   /*



From svn at coreboot.org  Sat Jun  4 17:44:15 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:44:15 +0200
Subject: [coreboot] [commit] r6624 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt1L-0005qy-7D@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:44:14 2011
New Revision: 6624
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6624

Log:
Port persimmon r6578 and r6596 to e350m1: MMCONF base

Remove multiple mmconf settings and just use kconfig setting.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/dsdt.asl

Modified: trunk/src/mainboard/asrock/e350m1/dsdt.asl
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/dsdt.asl	Sat Jun  4 17:43:56 2011	(r6623)
+++ trunk/src/mainboard/asrock/e350m1/dsdt.asl	Sat Jun  4 17:44:14 2011	(r6624)
@@ -36,7 +36,7 @@
 	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
 	Name(PBLN, 0x0)	/* Length of BIOS area */
 
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 
 	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */



From svn at coreboot.org  Sat Jun  4 17:44:33 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:44:33 +0200
Subject: [coreboot] [commit] r6625 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt1d-0006P0-KJ@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:44:31 2011
New Revision: 6625
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6625

Log:
Port persimmon r6582 to e350m1: 33 MHz SPI read early

Enable 33 MHz fast mode SPI read early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/romstage.c

Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:14 2011	(r6624)
+++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:31 2011	(r6625)
@@ -47,6 +47,19 @@
   u32 val;
   u8 reg8;
 
+  // early enable of SPI 33 MHz fast mode read
+  if (boot_cpu())
+    {
+    volatile u32 *spiBase = (void *) 0xa0000000;
+    u32 save;
+    __outdword (0xcf8, 0x8000a3a0);
+    save = __indword (0xcfc);
+    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
+    spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
+    spiBase [0] |= 1 << 18; // fast read enable
+    __outdword (0xcfc, save); // clear temp base
+    }
+
   if (!cpu_init_detectedx && boot_cpu()) {
     post_code(0x30);
     sb_poweron_init();



From svn at coreboot.org  Sat Jun  4 17:44:55 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:44:55 +0200
Subject: [coreboot] [commit] r6626 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt1z-0006vS-Mc@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:44:54 2011
New Revision: 6626
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6626

Log:
Port persimmon r6583 to e350m1: pstate 0 early

Switch processor cores to pstate 0 early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/romstage.c

Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:31 2011	(r6625)
+++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:54 2011	(r6626)
@@ -47,6 +47,9 @@
   u32 val;
   u8 reg8;
 
+  // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+  __writemsr (0xc0010062, 0);
+
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {



From svn at coreboot.org  Sat Jun  4 17:45:13 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:45:13 +0200
Subject: [coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt2H-0007bq-WC@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:45:12 2011
New Revision: 6627
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6627

Log:
Port persimmon r6584 and r6601 to e350m1: SPI prefetch early

Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/romstage.c

Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:54 2011	(r6626)
+++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:45:12 2011	(r6627)
@@ -50,6 +50,13 @@
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);
 
+  // early enable of PrefetchEnSPIFromHost
+  if (boot_cpu())
+    {
+    __outdword (0xcf8, 0x8000a3b8);
+    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
+    }
+
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {



From svn at coreboot.org  Sat Jun  4 17:45:29 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:45:29 +0200
Subject: [coreboot] [commit] r6628 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt2X-0007zt-VG@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:45:29 2011
New Revision: 6628
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6628

Log:
Port persimmon r6586 to e350m1: FADT revision

Make fadt revision match its length. Solves Windows 7 checked build assert.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/fadt.c

Modified: trunk/src/mainboard/asrock/e350m1/fadt.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/fadt.c	Sat Jun  4 17:45:12 2011	(r6627)
+++ trunk/src/mainboard/asrock/e350m1/fadt.c	Sat Jun  4 17:45:29 2011	(r6628)
@@ -53,7 +53,7 @@
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
 	header->length = 244;
-	header->revision = 1;
+	header->revision = 3;
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);



From svn at coreboot.org  Sat Jun  4 17:45:47 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:45:47 +0200
Subject: [coreboot] [commit] r6629 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt2p-0008VJ-Bl@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:45:46 2011
New Revision: 6629
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6629

Log:
Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible

Declare RTC as not PIIX4 compatible to match AMD hardware.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/dsdt.asl

Modified: trunk/src/mainboard/asrock/e350m1/dsdt.asl
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/dsdt.asl	Sat Jun  4 17:45:29 2011	(r6628)
+++ trunk/src/mainboard/asrock/e350m1/dsdt.asl	Sat Jun  4 17:45:46 2011	(r6629)
@@ -1379,7 +1379,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)



From svn at coreboot.org  Sat Jun  4 17:46:14 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:46:14 +0200
Subject: [coreboot] [commit] r6630 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt3G-0000n3-DW@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:46:13 2011
New Revision: 6630
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6630

Log:
Port persimmon r6588 to e350m1: VGA framebuffer

Declare legacy video frame buffer so that Windows generic VGA driver will work.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/dsdt.asl

Modified: trunk/src/mainboard/asrock/e350m1/dsdt.asl
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/dsdt.asl	Sat Jun  4 17:45:46 2011	(r6629)
+++ trunk/src/mainboard/asrock/e350m1/dsdt.asl	Sat Jun  4 17:46:13 2011	(r6630)
@@ -1483,9 +1483,8 @@
 					0xF300			/* length */
 				)
 
-#if 0
-				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+#if 0
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 



From svn at coreboot.org  Sat Jun  4 17:46:33 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:46:33 +0200
Subject: [coreboot] [commit] r6631 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt3Z-00018v-Fu@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:46:32 2011
New Revision: 6631
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6631

Log:
Port persimmon r6589 to e350m1: Strip down AGESA options

Remove some non-essential agesa options to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/buildOpts.c

Modified: trunk/src/mainboard/asrock/e350m1/buildOpts.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/buildOpts.c	Sat Jun  4 17:46:13 2011	(r6630)
+++ trunk/src/mainboard/asrock/e350m1/buildOpts.c	Sat Jun  4 17:46:32 2011	(r6631)
@@ -80,16 +80,16 @@
 #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT     TRUE
 
 #define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
 #define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
 //#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
 #define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
 #define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
 #define BLDOPT_REMOVE_DQS_TRAINING            FALSE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
 #define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
@@ -97,17 +97,17 @@
   #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
   #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
-//#define BLDOPT_REMOVE_SRAT            TRUE
-//#define BLDOPT_REMOVE_SLIT            TRUE
-//#define BLDOPT_REMOVE_WHEA            TRUE
-//#define BLDOPT_REMOVE_DMI             TRUE
-//#define BLDOPT_REMOVE_HT_ASSIST         TRUE
-//#define BLDOPT_REMOVE_ATM_MODE          TRUE
+#define BLDOPT_REMOVE_SRAT            TRUE
+#define BLDOPT_REMOVE_SLIT            TRUE
+#define BLDOPT_REMOVE_WHEA            TRUE
+#define BLDOPT_REMOVE_DMI             TRUE
+#define BLDOPT_REMOVE_HT_ASSIST         TRUE
+#define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
-//#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
+#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
 #define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
 
 /*
@@ -123,7 +123,7 @@
 #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
 #define AGESA_ENTRY_INIT_RESUME                   TRUE
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
 
 /* 
  * Agesa configuration values selection.  



From svn at coreboot.org  Sat Jun  4 17:46:50 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:46:50 +0200
Subject: [coreboot] [commit] r6632 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt3q-0001YB-Fp@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:46:50 2011
New Revision: 6632
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6632

Log:
Port persimmon r6590 to e350m1: Work around memory allocation problem

Fix memory allocation problem in amdInitLate. Disabled until further debug.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/agesawrapper.c

Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/agesawrapper.c	Sat Jun  4 17:46:32 2011	(r6631)
+++ trunk/src/mainboard/asrock/e350m1/agesawrapper.c	Sat Jun  4 17:46:50 2011	(r6632)
@@ -444,33 +444,32 @@
   )
 {
   AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
+  AMD_INTERFACE_PARAMS AmdParamStruct = {0};
+  AMD_LATE_PARAMS *AmdLateParams;
 
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
-
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
+  return 0; // this causes bad ACPI SSDT, need to debug
 
-  Status = AmdInitLate (&AmdLateParams);
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+  AmdParamStruct.AllocationMethod = PostMemDram;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdCreateStruct (&AmdParamStruct);
+  AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+  Status = AmdInitLate (AmdLateParams);
   if (Status != AGESA_SUCCESS) {
     agesawrapper_amdreadeventlog();
     ASSERT(Status == AGESA_SUCCESS);
   }
 
-  DmiTable       = AmdLateParams.DmiTable;
-  AcpiPstate     = AmdLateParams.AcpiPState;
-  AcpiSrat       = AmdLateParams.AcpiSrat;
-  AcpiSlit       = AmdLateParams.AcpiSlit;
-
-  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib       = AmdLateParams.AcpiAlib;
+  DmiTable    = AmdLateParams->DmiTable;
+  AcpiPstate  = AmdLateParams->AcpiPState;
+  AcpiSrat    = AmdLateParams->AcpiSrat;
+  AcpiSlit    = AmdLateParams->AcpiSlit;
+
+  AcpiWheaMce = AmdLateParams->AcpiWheaMce;
+  AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
+  AcpiAlib    = AmdLateParams->AcpiAlib;
 
+  AmdReleaseStruct (&AmdParamStruct);
   return (UINT32)Status;
 }
 



From svn at coreboot.org  Sat Jun  4 17:47:08 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:47:08 +0200
Subject: [coreboot] [commit] r6633 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt48-00021X-IG@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:47:05 2011
New Revision: 6633
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6633

Log:
Port persimmon r6591 to e350m1: ROM cache early

Enable rom cache early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/asrock/e350m1/agesawrapper.c
   trunk/src/mainboard/asrock/e350m1/romstage.c

Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/agesawrapper.c	Sat Jun  4 17:46:50 2011	(r6632)
+++ trunk/src/mainboard/asrock/e350m1/agesawrapper.c	Sat Jun  4 17:47:05 2011	(r6633)
@@ -157,13 +157,6 @@
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   
-
-  /* Set ROM cache onto WP to decrease post time */
-  MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
-  LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-  MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
-  LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
-
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }

Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:46:50 2011	(r6632)
+++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:47:05 2011	(r6633)
@@ -47,6 +47,11 @@
   u32 val;
   u8 reg8;
 
+  // all cores: allow caching of flash chip code and data
+  // (there are no cache-as-ram reliability concerns with family 14h)
+  __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
+  __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);
 



From svn at coreboot.org  Sat Jun  4 17:47:32 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:47:32 +0200
Subject: [coreboot] [commit] r6634 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt4W-0002ae-3C@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:47:30 2011
New Revision: 6634
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6634

Log:
Port persimmon r6592 to e350m1: Update GPP port configuration

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Marshall Buschman <mbuschman at lucidmachines.com>

Modified:
   trunk/src/mainboard/asrock/e350m1/devicetree.cb

Modified: trunk/src/mainboard/asrock/e350m1/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/devicetree.cb	Sat Jun  4 17:47:05 2011	(r6633)
+++ trunk/src/mainboard/asrock/e350m1/devicetree.cb	Sat Jun  4 17:47:30 2011	(r6634)
@@ -99,12 +99,12 @@
 					end #LPC
   					device pci 14.4 on end # PCI 0x4384
 	  				device pci 14.5 on end # USB 2
-					device pci 15.0 on end # PCIe PortA
-					device pci 15.1 on end # PCIe PortB
-					device pci 15.2 on end # PCIe PortC
-					device pci 15.3 on end # PCIe PortD
-					register "gpp_configuration" = "4" #1:1:1:1
-		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+					device pci 15.0 off end # PCIe PortA
+					device pci 15.1 off end # PCIe PortB
+					device pci 15.2 off end # PCIe PortC
+					device pci 15.3 off end # PCIe PortD
+					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
+ 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx_wrapper/sb800
 #                       end #  device pci 18.0
 # These seem unnecessary



From svn at coreboot.org  Sat Jun  4 17:47:56 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:47:56 +0200
Subject: [coreboot] [commit] r6635 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt4u-0003IL-Ug@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:47:56 2011
New Revision: 6635
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6635

Log:
Port persimmon r6593 to e350m1: Remove unused Kconfig options

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Marshall Buschman <mbuschman at lucidmachines.com>

Modified:
   trunk/src/mainboard/asrock/e350m1/Kconfig

Modified: trunk/src/mainboard/asrock/e350m1/Kconfig
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/Kconfig	Sat Jun  4 17:47:30 2011	(r6634)
+++ trunk/src/mainboard/asrock/e350m1/Kconfig	Sat Jun  4 17:47:56 2011	(r6635)
@@ -22,8 +22,6 @@
 config BOARD_SPECIFIC_OPTIONS # dummy
         def_bool y
   select ARCH_X86
-        select DIMM_DDR3
-        select DIMM_UNREGISTERED
   select CPU_AMD_AGESA_WRAPPER_FAMILY14
   select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
   select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
@@ -42,7 +40,6 @@
   select AMDMCT
         select HAVE_ACPI_TABLES
   select BOARD_ROMSIZE_KB_4096
-  select ENABLE_APIC_EXT_ID
   select TINY_BOOTBLOCK
         select GFXUMA
 
@@ -86,18 +83,6 @@
         int
         default 2
 
-config SB_HT_CHAIN_ON_BUS0
-        int
-        default 1
-
-config HT_CHAIN_END_UNITID_BASE
-        hex
-        default 0x1
-
-config HT_CHAIN_UNITID_BASE
-        hex
-        default 0x0
-
 config IRQ_SLOT_COUNT
         int
         default 11



From svn at coreboot.org  Sat Jun  4 17:48:15 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 17:48:15 +0200
Subject: [coreboot] [commit] r6636 - trunk/src/mainboard/asrock/e350m1
Message-ID: <E1QSt5D-0003oZ-10@ra.coresystems.de>

Author: stuge
Date: Sat Jun  4 17:48:14 2011
New Revision: 6636
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6636

Log:
Port persimmon r6594 to e350m1: Cosmetic cleanup

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Marshall Buschman <mbuschman at lucidmachines.com>

Modified:
   trunk/src/mainboard/asrock/e350m1/get_bus_conf.c

Modified: trunk/src/mainboard/asrock/e350m1/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/get_bus_conf.c	Sat Jun  4 17:47:56 2011	(r6635)
+++ trunk/src/mainboard/asrock/e350m1/get_bus_conf.c	Sat Jun  4 17:48:14 2011	(r6636)
@@ -42,25 +42,12 @@
   0x0000ff0,
 };
 
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
-  0x20202020,
-};
-
 u32 bus_type[256];
-
 u32 sbdn_sb800;
 
-//KZ [092110]extern void get_pci1234(void);
-
 static u32 get_bus_conf_done = 0;
 
 
-
-
 void get_bus_conf(void)
 {
   u32 apicid_base;
@@ -139,8 +126,5 @@
   /* I/O APICs:   APIC ID Version State   Address */
   bus_isa = 10;
   apicid_base = CONFIG_MAX_CPUS;
-//#if CONFIG_LOGICAL_CPUS==1
-//  apicid_base = get_apicid_base(1);
-//#endif
-  apicid_sb800 = apicid_base + 0;
+  apicid_sb800 = apicid_base;
 }



From peter at stuge.se  Sat Jun  4 17:54:26 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 4 Jun 2011 17:54:26 +0200
Subject: [coreboot] [PATCH 01/16] Port persimmon r6572 to e350m1:
	I/O	APIC ID
In-Reply-To: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
Message-ID: <20110604155426.3769.qmail@stuge.se>

mbuschman at lucidmachines.com wrote:
> From: Scott Duplichan <scott at notabs.org>
> 
> 1) Set I/O APIC ID according to BKDG recommendation
> 2) Correct I/O APIC ID reported by mptable
> 
> Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>

All are either

Acked-by: Peter Stuge <peter at stuge.se>

or

Acked-by: Marshall Buschman <mbuschman at lucidmachines.com>

per IRC. Committed as r6621 to r6636.

Many thanks to Scott for these fixes to amd/persimmon, and to
Marshall for working on getting them over to asrock/e350m1, which
should now be functionally equivalent to amd/persimmon, as has also
been tested by Marshall.


//Peter



From stefan.reinauer at coreboot.org  Sat Jun  4 18:12:26 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 4 Jun 2011 18:12:26 +0200
Subject: [coreboot] [commit] r6625 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <E1QSt1d-0006P0-KJ@ra.coresystems.de>
References: <E1QSt1d-0006P0-KJ@ra.coresystems.de>
Message-ID: <20110604161226.GA15898@coreboot.org>

* repository service <svn at coreboot.org> [110604 17:44]:
> Author: stuge
> Date: Sat Jun  4 17:44:31 2011
> New Revision: 6625
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6625
> 
> Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
> ==============================================================================
> --- trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:14 2011	(r6624)
> +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:31 2011	(r6625)
> @@ -47,6 +47,19 @@
>    u32 val;
>    u8 reg8;
>  
> +  // early enable of SPI 33 MHz fast mode read
> +  if (boot_cpu())
> +    {
> +    volatile u32 *spiBase = (void *) 0xa0000000;
> +    u32 save;
> +    __outdword (0xcf8, 0x8000a3a0);

what's the reason to not use pci_read_config32() here?

> +    save = __indword (0xcfc);
> +    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
> +    spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
> +    spiBase [0] |= 1 << 18; // fast read enable
> +    __outdword (0xcfc, save); // clear temp base
> +    }
> +
>    if (!cpu_init_detectedx && boot_cpu()) {
>      post_code(0x30);
>      sb_poweron_init();
> 
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 



From stefan.reinauer at coreboot.org  Sat Jun  4 18:13:03 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 4 Jun 2011 18:13:03 +0200
Subject: [coreboot] [commit] r6626 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <E1QSt1z-0006vS-Mc@ra.coresystems.de>
References: <E1QSt1z-0006vS-Mc@ra.coresystems.de>
Message-ID: <20110604161303.GB15898@coreboot.org>

* repository service <svn at coreboot.org> [110604 17:44]:
> Author: stuge
> Date: Sat Jun  4 17:44:54 2011
> New Revision: 6626
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6626
> 
> Log:
> Port persimmon r6583 to e350m1: pstate 0 early
> 
> Switch processor cores to pstate 0 early to reduce boot time.
> 
> Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
> Acked-by: Peter Stuge <peter at stuge.se>
> 
> Modified:
>    trunk/src/mainboard/asrock/e350m1/romstage.c
> 
> Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
> ==============================================================================
> --- trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:31 2011	(r6625)
> +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:54 2011	(r6626)
> @@ -47,6 +47,9 @@
>    u32 val;
>    u8 reg8;
>  
> +  // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
> +  __writemsr (0xc0010062, 0);
> +

why not use writemsr instead of __writemsr?


>    // early enable of SPI 33 MHz fast mode read
>    if (boot_cpu())
>      {
> 
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 



From stefan.reinauer at coreboot.org  Sat Jun  4 18:16:05 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 4 Jun 2011 18:16:05 +0200
Subject: [coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <E1QSt2H-0007bq-WC@ra.coresystems.de>
References: <E1QSt2H-0007bq-WC@ra.coresystems.de>
Message-ID: <20110604161605.GC15898@coreboot.org>

* repository service <svn at coreboot.org> [110604 17:45]:
> Author: stuge
> Date: Sat Jun  4 17:45:12 2011
> New Revision: 6627
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6627
> 
> Log:
> Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
> 
> Enable SPI cacheline prefetch early to reduce boot time.
> 
> Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
> Acked-by: Peter Stuge <peter at stuge.se>
> 
> Modified:
>    trunk/src/mainboard/asrock/e350m1/romstage.c
> 
> Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
> ==============================================================================
> --- trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:54 2011	(r6626)
> +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:45:12 2011	(r6627)
> @@ -50,6 +50,13 @@
>    // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
>    __writemsr (0xc0010062, 0);
>  
> +  // early enable of PrefetchEnSPIFromHost
> +  if (boot_cpu())
> +    {
> +    __outdword (0xcf8, 0x8000a3b8);
> +    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
> +    }

This should use pci config space access functions. Also, enabling
Prefetch and 33MHz fast read mode should possibly go in the
southbridge's bootblock.c so the first cbfs scan does not run with the
slow settings.

>    // early enable of SPI 33 MHz fast mode read
>    if (boot_cpu())
>      {
> 



From peter at stuge.se  Sat Jun  4 18:16:00 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 4 Jun 2011 18:16:00 +0200
Subject: [coreboot] [commit] r6625 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <20110604161303.GB15898@coreboot.org>
	<20110604161226.GA15898@coreboot.org>
References: <E1QSt1z-0006vS-Mc@ra.coresystems.de>
	<20110604161303.GB15898@coreboot.org>
	<E1QSt1d-0006P0-KJ@ra.coresystems.de>
	<20110604161226.GA15898@coreboot.org>
Message-ID: <20110604161600.9197.qmail@stuge.se>

Stefan Reinauer wrote:
> > +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:31 2011	(r6625)
..
> > +    __outdword (0xcf8, 0x8000a3a0);
> 
> what's the reason to not use pci_read_config32() here?


> > +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:54 2011	(r6626)
..
> > +  __writemsr (0xc0010062, 0);
> 
> why not use writemsr instead of __writemsr?

This is how it looked in the previous patches committed to svn, which
were blindly applied to asrock/e350m1 after having tested that they
worked. Ie. blame Scott. :p


//Peter



From stefan.reinauer at coreboot.org  Sat Jun  4 18:18:32 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 4 Jun 2011 18:18:32 +0200
Subject: [coreboot] [commit] r6633 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <E1QSt48-00021X-IG@ra.coresystems.de>
References: <E1QSt48-00021X-IG@ra.coresystems.de>
Message-ID: <20110604161832.GD15898@coreboot.org>

* repository service <svn at coreboot.org> [110604 17:47]:
> Author: stuge
> Date: Sat Jun  4 17:47:05 2011
> New Revision: 6633
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6633
> 
> Log:
> Port persimmon r6591 to e350m1: ROM cache early
> 
> Enable rom cache early to reduce boot time.
> 
> Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>
> Acked-by: Peter Stuge <peter at stuge.se>
> 
> Modified:
>    trunk/src/mainboard/asrock/e350m1/agesawrapper.c
>    trunk/src/mainboard/asrock/e350m1/romstage.c
> 
> Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c
> ==============================================================================
> --- trunk/src/mainboard/asrock/e350m1/agesawrapper.c	Sat Jun  4 17:46:50 2011	(r6632)
> +++ trunk/src/mainboard/asrock/e350m1/agesawrapper.c	Sat Jun  4 17:47:05 2011	(r6633)
> @@ -157,13 +157,6 @@
>    PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
>    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
>    
> -
> -  /* Set ROM cache onto WP to decrease post time */
> -  MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
> -  LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
> -  MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
> -  LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
> -
>    Status = AGESA_SUCCESS;
>    return (UINT32)Status;
>  }
> 
> Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
> ==============================================================================
> --- trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:46:50 2011	(r6632)
> +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:47:05 2011	(r6633)
> @@ -47,6 +47,11 @@
>    u32 val;
>    u8 reg8;
>  
> +  // all cores: allow caching of flash chip code and data
> +  // (there are no cache-as-ram reliability concerns with family 14h)
> +  __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
> +  __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
> +


again, why __writemsr instead of writemsr?

I think this should go into cache_as_ram.S like on (all the?) other CPUs




From peter at stuge.se  Sat Jun  4 18:19:56 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 4 Jun 2011 18:19:56 +0200
Subject: [coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <20110604161605.GC15898@coreboot.org>
References: <E1QSt2H-0007bq-WC@ra.coresystems.de>
	<20110604161605.GC15898@coreboot.org>
Message-ID: <20110604161956.10245.qmail@stuge.se>

Stefan Reinauer wrote:
> > +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:45:12 2011	(r6627)
> > @@ -50,6 +50,13 @@
> >    // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
> >    __writemsr (0xc0010062, 0);
> >  
> > +  // early enable of PrefetchEnSPIFromHost
> > +  if (boot_cpu())
> > +    {
> > +    __outdword (0xcf8, 0x8000a3b8);
> > +    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
> > +    }
> 
> This should use pci config space access functions. Also, enabling
> Prefetch and 33MHz fast read mode should possibly go in the
> southbridge's bootblock.c so the first cbfs scan does not run with
> the slow settings.

Good idea! Please do it! Remember to also revert the commit for
persimmon.

I think the Fusion code is a good place for such cleanups, where we
have a chance to factor out more common code before it gets too wide
spread. :)


//Peter



From stefan.reinauer at coreboot.org  Sat Jun  4 18:22:30 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 4 Jun 2011 18:22:30 +0200
Subject: [coreboot] [commit] r6625 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <20110604161600.9197.qmail@stuge.se>
References: <E1QSt1z-0006vS-Mc@ra.coresystems.de>
	<20110604161303.GB15898@coreboot.org>
	<E1QSt1d-0006P0-KJ@ra.coresystems.de>
	<20110604161226.GA15898@coreboot.org>
	<20110604161600.9197.qmail@stuge.se>
Message-ID: <20110604162230.GA10068@coreboot.org>

* Peter Stuge <peter at stuge.se> [110604 18:16]:
> Stefan Reinauer wrote:
> > > +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:31 2011	(r6625)
> ..
> > > +    __outdword (0xcf8, 0x8000a3a0);
> > 
> > what's the reason to not use pci_read_config32() here?
> 
> 
> > > +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:44:54 2011	(r6626)
> ..
> > > +  __writemsr (0xc0010062, 0);
> > 
> > why not use writemsr instead of __writemsr?
> 
> This is how it looked in the previous patches committed to svn, which
> were blindly applied to asrock/e350m1 after having tested that they
> worked. Ie. blame Scott. :p

I'm not blaming anyone, I just think this should  get fixed, or at least not
repeated ;)

Blindly copy'n'pasting code is not always the answer.






From stefan.reinauer at coreboot.org  Sat Jun  4 18:23:32 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 4 Jun 2011 18:23:32 +0200
Subject: [coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <20110604161956.10245.qmail@stuge.se>
References: <E1QSt2H-0007bq-WC@ra.coresystems.de>
	<20110604161605.GC15898@coreboot.org>
	<20110604161956.10245.qmail@stuge.se>
Message-ID: <20110604162332.GB10068@coreboot.org>

* Peter Stuge <peter at stuge.se> [110604 18:19]:
> Stefan Reinauer wrote:
> > > +++ trunk/src/mainboard/asrock/e350m1/romstage.c	Sat Jun  4 17:45:12 2011	(r6627)
> > > @@ -50,6 +50,13 @@
> > >    // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
> > >    __writemsr (0xc0010062, 0);
> > >  
> > > +  // early enable of PrefetchEnSPIFromHost
> > > +  if (boot_cpu())
> > > +    {
> > > +    __outdword (0xcf8, 0x8000a3b8);
> > > +    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
> > > +    }
> > 
> > This should use pci config space access functions. Also, enabling
> > Prefetch and 33MHz fast read mode should possibly go in the
> > southbridge's bootblock.c so the first cbfs scan does not run with
> > the slow settings.
> 
> Good idea! Please do it! Remember to also revert the commit for
> persimmon.
> 

Unfortunately I have no hardware to test this.

> I think the Fusion code is a good place for such cleanups, where we
> have a chance to factor out more common code before it gets too wide
> spread. :)

Yes. Absolutely



From svn at coreboot.org  Sat Jun  4 18:30:27 2011
From: svn at coreboot.org (repository service)
Date: Sat, 04 Jun 2011 18:30:27 +0200
Subject: [coreboot] [commit] r6637 - in trunk/src/mainboard:
	advansus/a785e-i emulation/qemu-x86
Message-ID: <E1QStk3-0001oT-Ii@ra.coresystems.de>

Author: stepan
Date: Sat Jun  4 18:30:27 2011
New Revision: 6637
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6637

Log:
WARNINGS_ARE_ERRORS is y per default, don't set it twice.

Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/src/mainboard/advansus/a785e-i/Kconfig
   trunk/src/mainboard/emulation/qemu-x86/Kconfig

Modified: trunk/src/mainboard/advansus/a785e-i/Kconfig
==============================================================================
--- trunk/src/mainboard/advansus/a785e-i/Kconfig	Sat Jun  4 17:48:14 2011	(r6636)
+++ trunk/src/mainboard/advansus/a785e-i/Kconfig	Sat Jun  4 18:30:27 2011	(r6637)
@@ -105,8 +105,4 @@
         string
         default "1002,9712"
 
-config WARNINGS_ARE_ERRORS
-        bool
-        default y
-
 endif #BOARD_ADVANSUS_A785E_I

Modified: trunk/src/mainboard/emulation/qemu-x86/Kconfig
==============================================================================
--- trunk/src/mainboard/emulation/qemu-x86/Kconfig	Sat Jun  4 17:48:14 2011	(r6636)
+++ trunk/src/mainboard/emulation/qemu-x86/Kconfig	Sat Jun  4 18:30:27 2011	(r6637)
@@ -8,7 +8,6 @@
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
-	select WARNINGS_ARE_ERRORS
 	select TINY_BOOTBLOCK
 
 config MAINBOARD_DIR



From peter at stuge.se  Sat Jun  4 18:35:39 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 4 Jun 2011 18:35:39 +0200
Subject: [coreboot] [commit] r6625 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <20110604162230.GA10068@coreboot.org>
References: <E1QSt1z-0006vS-Mc@ra.coresystems.de>
	<20110604161303.GB15898@coreboot.org>
	<E1QSt1d-0006P0-KJ@ra.coresystems.de>
	<20110604161226.GA15898@coreboot.org>
	<20110604161600.9197.qmail@stuge.se>
	<20110604162230.GA10068@coreboot.org>
Message-ID: <20110604163539.14270.qmail@stuge.se>

Stefan Reinauer wrote:
> > previous patches committed to svn, which were blindly applied to
> > asrock/e350m1
> 
> Blindly copy'n'pasting code is not always the answer.

Of course not. The situation here is that we worked toward zero
differences between a nicely formatted patch set, and the single big
that Scott was kind to provide during his work on this code. To keep
complexity of this work manageable it was important to arrive on
nearly exactly the same code in the end. I think now is a great time
to make cleanups on code common for both boards.

What we have arrived at now is coreboot trunk working brilliantly for
a very recently announced consumer mainboard with the latest AMD
technology. It was considerably more difficult to test with
amd/persimmon because of more limited availability.


//Peter



From svens at stackframe.org  Sat Jun  4 19:47:34 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sat,  4 Jun 2011 19:47:34 +0200
Subject: [coreboot] [PATCH 1/2] SMM: add mainboard_apm_cnt() callback
Message-ID: <1307209655-14859-1-git-send-email-svens@stackframe.org>

motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/include/cpu/x86/smm.h                   |    2 +-
 src/southbridge/intel/i82801gx/smihandler.c |    3 +++
 2 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index ad0984e..559b1b7 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -263,4 +263,4 @@ void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_
 void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
 
 void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
-
+int __attribute__((weak)) mainboard_apm_cnt(u8 data);
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index aefa283..bccf6d5 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -362,6 +362,9 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 	/* Emulate B2 register as the FADT / Linux expects it */
 
 	reg8 = inb(APM_CNT);
+	if (mainboard_apm_cnt && mainboard_apm_cnt(reg8))
+		return;
+
 	switch (reg8) {
 	case CST_CONTROL:
 		/* Calling this function seems to cause
-- 
1.7.5.3




From svens at stackframe.org  Sat Jun  4 19:47:35 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sat,  4 Jun 2011 19:47:35 +0200
Subject: [coreboot] [PATCH 2/2] X60: add support for handling EC events in
	SMM
In-Reply-To: <1307209655-14859-1-git-send-email-svens@stackframe.org>
References: <1307209655-14859-1-git-send-email-svens@stackframe.org>
Message-ID: <1307209655-14859-2-git-send-email-svens@stackframe.org>

could be used for various things if the OS doesn't provide
ACPI support, or has ACPI disabled. The current patch only
uses this to enable operation of the backlight hotkeys.

As the Thinkpad EC doesn't support EC_QUERY on ports 0x1600/0x1604
and there are no event queue registers in the EC register space,
we're using 0x62/0x66 as EC I/O ports as long as ACPI is disabled.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/x60/devicetree.cb   |    4 +-
 src/mainboard/lenovo/x60/mainboard_smi.c |   89 +++++++++++++++++++++++++++++-
 2 files changed, 90 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index b708dce..42a45d1 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -53,13 +53,13 @@ chip northbridge/intel/i945
 			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
 			#  2 SCI (if corresponding GPIO_EN bit is also set)
 			register "gpi13_routing" = "2"
-			register "gpi12_routing" = "2"
+			register "gpi12_routing" = "1"
 			register "gpi8_routing" = "2"
 
 			register "sata_ahci" = "0x0"
 
 			register "gpe0_en" = "0x11000006"
-
+			register "alt_gp_smi_en" = "0x1000"
 			device pci 1b.0 on # Audio Cnotroller
 				subsystemid 0x17aa 0x2010
 			end
diff --git a/src/mainboard/lenovo/x60/mainboard_smi.c b/src/mainboard/lenovo/x60/mainboard_smi.c
index 5e0f6a9..e45c774 100644
--- a/src/mainboard/lenovo/x60/mainboard_smi.c
+++ b/src/mainboard/lenovo/x60/mainboard_smi.c
@@ -24,10 +24,14 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include "southbridge/intel/i82801gx/nvs.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 #include <ec/acpi/ec.h>
 #include "dock.h"
 #include "smi.h"
 
+#define ACPI_ENABLE 0xe1
+#define ACPI_DISABLE 0x1e
+
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
  */
@@ -38,7 +42,6 @@ static void mainboard_smm_init(void)
 	printk(BIOS_DEBUG, "initializing SMI\n");
 	/* Enable 0x1600/0x1600 register pair */
 	ec_set_bit(0x00, 0x05);
-	ec_set_ports(0x1604, 0x1600);
 }
 
 int mainboard_io_trap_handler(int smif)
@@ -76,3 +79,87 @@ int mainboard_io_trap_handler(int smif)
 	return 0;
 }
 
+static void mainboard_smi_brightness_up(void)
+{
+	u8 value;
+
+	if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+		pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+	u8 value;
+
+	if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+		pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+	u8 status = inb(EC_SC);
+	u8 event;
+
+	if (!(status & EC_SCI_EVT))
+		return;
+
+	event = ec_query();
+	printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+	switch(event) {
+		/* brightness up */
+		case 0x14:
+			mainboard_smi_brightness_up();
+			break;
+		/* brightness down */
+		case 0x15:
+			mainboard_smi_brightness_down();
+			break;
+		default:
+			break;
+	}
+}
+
+void mainboard_smi_gpi(u16 gpi)
+{
+	if (gpi & (1 << 12))
+		mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_apm_cnt(u8 data)
+{
+	u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+	u8 tmp;
+
+	printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
+
+	if (!pmbase)
+		return 0;
+
+	switch(data) {
+		case ACPI_ENABLE:
+			/* use 0x1600/0x1604 to prevent races with userspace */
+			ec_set_ports(0x1604, 0x1600);
+			/* route H8SCI to SCI */
+			outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+			tmp &= ~0x03;
+			tmp |= 0x02;
+			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+			break;
+		case ACPI_DISABLE:
+			/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+			   provide a EC query function */
+			ec_set_ports(0x66, 0x62);
+			/* route H8SCI# to SMI */
+			outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+			tmp &= ~0x03;
+			tmp |= 0x01;
+			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+			break;
+		default:
+			break;
+	}
+	return 0;
+}
-- 
1.7.5.3




From doverailing at gmail.com  Sun Jun  5 00:22:09 2011
From: doverailing at gmail.com (dove - railing)
Date: Sat, 4 Jun 2011 22:22:09 +0000
Subject: [coreboot] Fonts at the Bios
Message-ID: <BANLkTi=iLbx3U3xbnp=v6WGHTBehneOo_g@mail.gmail.com>

I am not a techie.

Would it be correct to say that fonts at the Bios level are decided by the
Video card / VGA firmware?  Is there an opensource utility for them?


Regards,


Meeku
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From stefan.reinauer at coreboot.org  Sun Jun  5 03:30:57 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 04 Jun 2011 18:30:57 -0700
Subject: [coreboot] Fonts at the Bios
In-Reply-To: <BANLkTi=iLbx3U3xbnp=v6WGHTBehneOo_g@mail.gmail.com>
References: <BANLkTi=iLbx3U3xbnp=v6WGHTBehneOo_g@mail.gmail.com>
Message-ID: <4DEADC51.20608@coreboot.org>

On 6/4/11 3:22 PM, dove - railing wrote:
> I am not a techie.
>
> Would it be correct to say that fonts at the Bios level are decided by 
> the Video card / VGA firmware?
The VGA BIOS loads the initial font.

> Is there an opensource utility for them?
>
I found this, it's not open source though:

http://www.procon.com.au/HVVCBIOS.htm

then there is setfont for linux in the kbd package that allows you 
changing the VGA text mode font during OS run time.

See the following link for more information:
http://www.faqs.org/docs/Linux-HOWTO/Keyboard-and-Console-HOWTO.html



From stefan.reinauer at coreboot.org  Sun Jun  5 03:32:52 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 04 Jun 2011 18:32:52 -0700
Subject: [coreboot] [PATCH 1/2] SMM: add mainboard_apm_cnt() callback
In-Reply-To: <1307209655-14859-1-git-send-email-svens@stackframe.org>
References: <1307209655-14859-1-git-send-email-svens@stackframe.org>
Message-ID: <4DEADCC4.5090305@coreboot.org>

On 6/4/11 10:47 AM, Sven Schnelle wrote:
> motherboards can use this hook to get notified if someone writes
> to the APM_CNT port (0xb2). If the hook returns 1, the chipset
> specific hook is also skipped.
>
> Signed-off-by: Sven Schnelle<svens at stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


> ---
>   src/include/cpu/x86/smm.h                   |    2 +-
>   src/southbridge/intel/i82801gx/smihandler.c |    3 +++
>   2 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
> index ad0984e..559b1b7 100644
> --- a/src/include/cpu/x86/smm.h
> +++ b/src/include/cpu/x86/smm.h
> @@ -263,4 +263,4 @@ void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_
>   void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
>
>   void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
> -
> +int __attribute__((weak)) mainboard_apm_cnt(u8 data);
> diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
> index aefa283..bccf6d5 100644
> --- a/src/southbridge/intel/i82801gx/smihandler.c
> +++ b/src/southbridge/intel/i82801gx/smihandler.c
> @@ -362,6 +362,9 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
>   	/* Emulate B2 register as the FADT / Linux expects it */
>
>   	reg8 = inb(APM_CNT);
> +	if (mainboard_apm_cnt&&  mainboard_apm_cnt(reg8))
> +		return;

Is it on purpose that the mainboard_apm_cnt function can prevent the 
generic 82801gx code (including the not implemented C state 
coordination) from running?

> +
>   	switch (reg8) {
>   	case CST_CONTROL:
>   		/* Calling this function seems to cause




From stefan.reinauer at coreboot.org  Sun Jun  5 03:33:18 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 04 Jun 2011 18:33:18 -0700
Subject: [coreboot] [PATCH 2/2] X60: add support for handling EC events
 in	SMM
In-Reply-To: <1307209655-14859-2-git-send-email-svens@stackframe.org>
References: <1307209655-14859-1-git-send-email-svens@stackframe.org>
	<1307209655-14859-2-git-send-email-svens@stackframe.org>
Message-ID: <4DEADCDE.1070302@coreboot.org>

On 6/4/11 10:47 AM, Sven Schnelle wrote:
> could be used for various things if the OS doesn't provide
> ACPI support, or has ACPI disabled. The current patch only
> uses this to enable operation of the backlight hotkeys.
>
> As the Thinkpad EC doesn't support EC_QUERY on ports 0x1600/0x1604
> and there are no event queue registers in the EC register space,
> we're using 0x62/0x66 as EC I/O ports as long as ACPI is disabled.
>
> Signed-off-by: Sven Schnelle<svens at stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>





From scott at notabs.org  Sun Jun  5 09:38:47 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 5 Jun 2011 02:38:47 -0500
Subject: [coreboot] [PATCH 01/16] Port persimmon r6572 to
	e350m1:I/O	APIC ID
In-Reply-To: <20110604155426.3769.qmail@stuge.se>
References: <1307167844-13392-1-git-send-email-mbuschman@lucidmachines.com>
	<20110604155426.3769.qmail@stuge.se>
Message-ID: <666E99F35F294FBEB9E9532190BFC21A@asusp67>

Peter Stuge wrote:

]All are either
]
]Acked-by: Peter Stuge <peter at stuge.se>
]
]or
]
]Acked-by: Marshall Buschman <mbuschman at lucidmachines.com>
]
]per IRC. Committed as r6621 to r6636.
]
]Many thanks to Scott for these fixes to amd/persimmon, and to
]Marshall for working on getting them over to asrock/e350m1, which
]should now be functionally equivalent to amd/persimmon, as has also
]been tested by Marshall.
]
]
]//Peter

Thank you Peter and Marshall. I will keep my e350m1 board around
for future testing and experiments.

Thanks,
Scott




From scott at notabs.org  Sun Jun  5 09:38:59 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 5 Jun 2011 02:38:59 -0500
Subject: [coreboot] [commit] r6625 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <20110604161226.GA15898@coreboot.org>
References: <E1QSt1d-0006P0-KJ@ra.coresystems.de>
	<20110604161226.GA15898@coreboot.org>
Message-ID: <473F3B52154C4A3E9B497380FCCB16E9@asusp67>

Stefan Reinauer wrote:

]> +  // early enable of SPI 33 MHz fast mode read
]> +  if (boot_cpu())
]> +    {
]> +    volatile u32 *spiBase = (void *) 0xa0000000;
]> +    u32 save;
]> +    __outdword (0xcf8, 0x8000a3a0);
]
]what's the reason to not use pci_read_config32() here?

Hello Stefan,

It was due to a quick copy/paste from some old code.
I will send a patch to update it.

Thanks,
Scott




From scott at notabs.org  Sun Jun  5 09:39:10 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 5 Jun 2011 02:39:10 -0500
Subject: [coreboot] [PATCH] AMD F14 persimmon and e350m1: use standard pci
	config functions
Message-ID: <FD374380643E4C25ABEED4F16D04F49D@asusp67>

AMD F14 persimmon and e350m1: replace inline cf8/cfc pci config
access with pci_read_config and pci_write_config function calls.

Signed-off-by: Scott Duplichan <scott at notabs.org>

Index: src/mainboard/amd/persimmon/romstage.c
===================================================================
--- src/mainboard/amd/persimmon/romstage.c	(revision 6637)
+++ src/mainboard/amd/persimmon/romstage.c	(working copy)
@@ -73,21 +73,20 @@
   // early enable of PrefetchEnSPIFromHost
   if (boot_cpu())
     {
-    __outdword (0xcf8, 0x8000a3b8);
-    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
+    device_t dev = PCI_DEV(0, 0x14, 3);
+    pci_write_config8(dev, 0xbb, pci_read_config8(dev, 0xbb) | 1);
     }
 
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {
     volatile u32 *spiBase = (void *) 0xa0000000;
-    u32 save;
-    __outdword (0xcf8, 0x8000a3a0);
-    save = __indword (0xcfc);
-    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
+    device_t dev = PCI_DEV(0, 0x14, 3);
+    u32 save = pci_read_config32(dev, 0xa0);
+    pci_write_config32(dev, 0xa0, (u32)spiBase | 2); // set temp MMIO base
     spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
     spiBase [0] |= 1 << 18; // fast read enable
-    __outdword (0xcfc, save); // clear temp base
+    pci_write_config32(dev, 0xa0, save);
     }
 
   if (!cpu_init_detectedx && boot_cpu()) {
Index: src/mainboard/asrock/e350m1/romstage.c
===================================================================
--- src/mainboard/asrock/e350m1/romstage.c	(revision 6637)
+++ src/mainboard/asrock/e350m1/romstage.c	(working copy)
@@ -58,21 +58,20 @@
   // early enable of PrefetchEnSPIFromHost
   if (boot_cpu())
     {
-    __outdword (0xcf8, 0x8000a3b8);
-    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
+    device_t dev = PCI_DEV(0, 0x14, 3);
+    pci_write_config8(dev, 0xbb, pci_read_config8(dev, 0xbb) | 1);
     }
 
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {
     volatile u32 *spiBase = (void *) 0xa0000000;
-    u32 save;
-    __outdword (0xcf8, 0x8000a3a0);
-    save = __indword (0xcfc);
-    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
+    device_t dev = PCI_DEV(0, 0x14, 3);
+    u32 save = pci_read_config32(dev, 0xa0);
+    pci_write_config32(dev, 0xa0, (u32)spiBase | 2); // set temp MMIO base
     spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
     spiBase [0] |= 1 << 18; // fast read enable
-    __outdword (0xcfc, save); // clear temp base
+    pci_write_config32(dev, 0xa0, save);
     }
 
   if (!cpu_init_detectedx && boot_cpu()) {
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From scott at notabs.org  Sun Jun  5 09:39:22 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 5 Jun 2011 02:39:22 -0500
Subject: [coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <20110604161605.GC15898@coreboot.org>
References: <E1QSt2H-0007bq-WC@ra.coresystems.de>
	<20110604161605.GC15898@coreboot.org>
Message-ID: <6CE9EBB920384B8282C963F06BE71CC1@asusp67>

Stefan Reinauer wrote:

]Also, enabling Prefetch and 33MHz fast read mode should possibly go in the
]southbridge's bootblock.c so the first cbfs scan does not run with the
]slow settings.

Hello Stefan,

You are probably right. In fact these settings are applied fairly early
even without the patch:
tracker.coreboot.org/trac/coreboot/browser/trunk/src/vendorcode/amd/cimx/
sb800/SBPOR.c#L67 (prefetch)
tracker.coreboot.org/trac/coreboot/browser/trunk/src/vendorcode/amd/cimx/
sb800/SBPOR.c#L249 (spi speed)

The patch applies the settings even earlier for boot time reduction. The
gain is small:

---e350m1 DOS AHCI SSD boot time in ms---
early prefetch   off    on     off    on 
early 33 mhz     off    off    on     on 
                 ---    ---    ---    ---
                 686    682    736    679	 

Together the changes save 7 ms. The question is, where do we draw the line
on boot time reduction? I worked in a group a while back where a manager
said, "every millisecond counts". This was due to a desire to make a
customer's board boot more quickly than a board from a competitor. Certainly
no user can notice a boot time difference of a few ms. The difference is
easy to measure though, and in some cases a few ms is enough to affect who
calls their board fastest. On the other hand, coreboot+seabios is already
several thousand ms faster than UEFI, so maybe saving 7 ms is not worth the
somewhat out of place code.

Thanks,
Scott







From scott at notabs.org  Sun Jun  5 09:39:28 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 5 Jun 2011 02:39:28 -0500
Subject: [coreboot] [commit] r6626 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <20110604161303.GB15898@coreboot.org>
References: <E1QSt1z-0006vS-Mc@ra.coresystems.de>
	<20110604161303.GB15898@coreboot.org>
Message-ID: <F2A0A90692E648DE816157FDDD3B21A8@asusp67>

Stefan Reinauer wrote:

]> +  // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot
]time
]> + __writemsr (0xc0010062, 0);
]> +
]
]why not use writemsr instead of __writemsr?

Hello Stefan,

The wrmsr function is certainly OK. I am in the habit us using the
Intel/MS functions because they are built into the Microsoft compiler
and therefore portable between all UEFI vendor code bases and any
other code that uses the MS complier. But portability with UEFI is
not the reason I still sometimes use these function types. Truthfully,
the coreboot wrmsr function seems awkward to me. With the Intel/MS
__writemsr function, any 64-bit value can be written with a single
statement. Coreboot code using wrmsr is often taking 4 statements to
do the same thing. While there is probably little difference in
generated code, using the coreboot wrmsr function does require more
source code typing. I also find it less readable. For example,

// set bit 46 of NB_CFG_MSR using wrmsr function:
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
msr.hi |= (1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);

// Making msr_t a union that adds a uint64_t would allow:
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
msr.all |= 1 << 46;
wrmsr(NB_CFG_MSR, msr);

// The Intel/MS style uint64_t prototypes allow:
__writemsr (__readmsr (NB_CFG_MSR) | 1 << 46);

A question I have wanted to ask for a while is why coreboot
doesn't use 64 bit integers in situations like this?

Thanks,
Scott




From avg at icyb.net.ua  Sun Jun  5 11:26:40 2011
From: avg at icyb.net.ua (Andriy Gapon)
Date: Sun, 05 Jun 2011 12:26:40 +0300
Subject: [coreboot] SB800/RS880 docs
Message-ID: <4DEB4BD0.6020306@icyb.net.ua>


Looks like the docs page http://www.coreboot.org/Datasheets#AMD_4 can be updated:

http://support.amd.com/us/psearch/Pages/psearch.aspx?type=2.2%3B2.3&product=2.7.4.3.5.3.2&contentType=Tech+Doc+Embedded&ostype=&keywords=&items=20

-- 
Andriy Gapon



From doverailing at gmail.com  Sun Jun  5 12:49:46 2011
From: doverailing at gmail.com (dove - railing)
Date: Sun, 5 Jun 2011 10:49:46 +0000
Subject: [coreboot] Fwd:  Fonts at the Bios
In-Reply-To: <BANLkTikFvUvoTWSWg2hr_Vv3N+1EB8brMg@mail.gmail.com>
References: <BANLkTi=iLbx3U3xbnp=v6WGHTBehneOo_g@mail.gmail.com>
	<4DEADC51.20608@coreboot.org>
	<BANLkTikFvUvoTWSWg2hr_Vv3N+1EB8brMg@mail.gmail.com>
Message-ID: <BANLkTimd_DOzNFtCfgT0=m3KD9NpQONr_g@mail.gmail.com>

---------- Forwarded message ----------
From: dove - railing <doverailing at gmail.com>
Date: Sun, Jun 5, 2011 at 10:49 AM
Subject: Re: [coreboot] Fonts at the Bios
To: Stefan Reinauer <stefan.reinauer at coreboot.org>




On Sun, Jun 5, 2011 at 1:30 AM, Stefan Reinauer <
stefan.reinauer at coreboot.org> wrote:

> On 6/4/11 3:22 PM, dove - railing wrote:
>
>> I am not a techie.
>>
>> Would it be correct to say that fonts at the Bios level are decided by the
>> Video card / VGA firmware?
>>
> The VGA BIOS loads the initial font.
>
>
>  Is there an opensource utility for them?
>>
>>  I found this, it's not open source though:
>
> http://www.procon.com.au/HVVCBIOS.htm
>  <http://www.coreboot.org/mailman/listinfo/coreboot>


Could not http://www.flashrom.org/Flashrom utility be an opensource utility
for Video card / VGA Bios?




Regards,



Meeku
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From doverailing at gmail.com  Sun Jun  5 14:34:20 2011
From: doverailing at gmail.com (dove - railing)
Date: Sun, 5 Jun 2011 12:34:20 +0000
Subject: [coreboot] Fonts at the Bios
In-Reply-To: <4DEADC51.20608@coreboot.org>
References: <BANLkTi=iLbx3U3xbnp=v6WGHTBehneOo_g@mail.gmail.com>
	<4DEADC51.20608@coreboot.org>
Message-ID: <BANLkTimLxO0zyTP3PhNcUrXz4TUftWZ3UQ@mail.gmail.com>

On Sun, Jun 5, 2011 at 1:30 AM, Stefan Reinauer <
stefan.reinauer at coreboot.org> wrote:

> On 6/4/11 3:22 PM, dove - railing wrote:
>
>> I am not a techie.
>>
>> Would it be correct to say that fonts at the Bios level are decided by the
>> Video card / VGA firmware?
>>
> The VGA BIOS loads the initial font.
>
>
>  Is there an opensource utility for them?
>>
>>  I found this, it's not open source though:
>
> http://www.procon.com.au/HVVCBIOS.htm
>  <http://www.coreboot.org/mailman/listinfo/coreboot>


I have contacted previously Procon.com.au via emails though strangely I have
not received any responses from them.


Regards,


Meeku
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From svens at stackframe.org  Sun Jun  5 15:47:23 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sun,  5 Jun 2011 15:47:23 +0200
Subject: [coreboot] [PATCH] SMM: add defines for APM_CNT register
Message-ID: <1307281643-31452-1-git-send-email-svens@stackframe.org>

in the current code, the defines for the APM_CNT (0xb2) register
are duplicated in almost every place where it is used. define those
values in cpu/x86/smm.h, and only include this file.

And while at it, fixup whitespace.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/include/cpu/x86/smm.h                   |    8 ++
 src/mainboard/getac/p470/fadt.c             |  169 +++++++++++++--------------
 src/mainboard/ibase/mb899/fadt.c            |  168 +++++++++++++--------------
 src/mainboard/intel/d945gclf/fadt.c         |  170 +++++++++++++--------------
 src/mainboard/intel/eagleheights/fadt.c     |    7 +-
 src/mainboard/iwave/iWRainbowG6/fadt.c      |   20 +---
 src/mainboard/kontron/986lcd-m/fadt.c       |  168 +++++++++++++--------------
 src/mainboard/lenovo/t60/fadt.c             |   15 +--
 src/mainboard/lenovo/x60/fadt.c             |   15 +--
 src/mainboard/lenovo/x60/mainboard_smi.c    |    1 -
 src/mainboard/roda/rk886ex/fadt.c           |   20 +---
 src/southbridge/intel/i82801dx/smihandler.c |   21 +---
 src/southbridge/intel/i82801gx/lpc.c        |   13 +-
 src/southbridge/intel/i82801gx/smihandler.c |   18 +--
 src/southbridge/intel/sch/smihandler.c      |    5 -
 src/southbridge/via/vt8237r/smihandler.c    |   18 +--
 16 files changed, 375 insertions(+), 461 deletions(-)

diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 559b1b7..5605453 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -248,6 +248,14 @@ typedef struct {
 	};
 } smm_state_save_area_t;
 
+#define APM_CNT		0xb2
+#define APM_CNT_CST_CONTROL	0x85
+#define APM_CNT_PST_CONTROL	0x80
+#define APM_CNT_ACPI_DISABLE	0x1e
+#define APM_CNT_ACPI_ENABLE	0xe1
+#define APM_CNT_MBI_UPDATE	0xeb
+#define APM_CNT_GNVS_UPDATE	0xea
+#define APM_STS		0xb3
 
 /* SMI handler function prototypes */
 void smi_handler(u32 smm_revision);
diff --git a/src/mainboard/getac/p470/fadt.c b/src/mainboard/getac/p470/fadt.c
index dcce467..7c9b113 100644
--- a/src/mainboard/getac/p470/fadt.c
+++ b/src/mainboard/getac/p470/fadt.c
@@ -22,17 +22,12 @@
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
+#include <cpu/x86/smm.h>
 
 /* FIXME: This needs to go into a separate .h file
  * to be included by the ich7 smi handler, ich7 smi init
  * code and the mainboard fadt.
  */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -41,8 +36,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
- 	header->length = sizeof(acpi_fadt_t);
- 	header->revision = 3;
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
 	memcpy(header->oem_id, "CORE  ", 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, "CORE", 4);
@@ -52,12 +47,12 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->dsdt = (unsigned long) dsdt;
 	fadt->preferred_pm_profile = PM_MOBILE;
 
-  	fadt->sci_int = 0x9;
- 	fadt->smi_cmd = APM_CNT;
- 	fadt->acpi_enable = ACPI_ENABLE;
- 	fadt->acpi_disable = ACPI_DISABLE;
-  	fadt->s4bios_req = 0x0; // S4 command disabled
- 	fadt->pstate_cnt = PST_CONTROL;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0; // S4 command disabled
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +70,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
- 	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
@@ -86,78 +81,78 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->mon_alrm = 0x00;
 	fadt->century = 0x00;
 	fadt->iapc_boot_arch = 0x00;
- 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- 			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
- 			ACPI_FADT_DOCKING_SUPPORTED;
-
- 	fadt->reset_reg.space_id = 0;
- 	fadt->reset_reg.bit_width = 0;
- 	fadt->reset_reg.bit_offset = 0;
- 	fadt->reset_reg.resv = 0;
- 	fadt->reset_reg.addrl = 0x0;
- 	fadt->reset_reg.addrh = 0x0;
-
- 	fadt->reset_value = 0;
- 	fadt->x_firmware_ctl_l = (unsigned long)facs;
- 	fadt->x_firmware_ctl_h = 0;
- 	fadt->x_dsdt_l = (unsigned long)dsdt;
- 	fadt->x_dsdt_h = 0;
-
- 	fadt->x_pm1a_evt_blk.space_id = 1;
- 	fadt->x_pm1a_evt_blk.bit_width = 32;
- 	fadt->x_pm1a_evt_blk.bit_offset = 0;
- 	fadt->x_pm1a_evt_blk.resv = 0;
- 	fadt->x_pm1a_evt_blk.addrl = pmbase;
- 	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_evt_blk.space_id = 1;
- 	fadt->x_pm1b_evt_blk.bit_width = 0;
- 	fadt->x_pm1b_evt_blk.bit_offset = 0;
- 	fadt->x_pm1b_evt_blk.resv = 0;
- 	fadt->x_pm1b_evt_blk.addrl = 0x0;
- 	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1a_cnt_blk.space_id = 1;
- 	fadt->x_pm1a_cnt_blk.bit_width = 16;
- 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1a_cnt_blk.resv = 0;
- 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_cnt_blk.space_id = 1;
- 	fadt->x_pm1b_cnt_blk.bit_width = 0;
- 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1b_cnt_blk.resv = 0;
- 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
- 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm2_cnt_blk.space_id = 1;
- 	fadt->x_pm2_cnt_blk.bit_width = 8;
- 	fadt->x_pm2_cnt_blk.bit_offset = 0;
- 	fadt->x_pm2_cnt_blk.resv = 0;
- 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
- 	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm_tmr_blk.space_id = 1;
- 	fadt->x_pm_tmr_blk.bit_width = 32;
- 	fadt->x_pm_tmr_blk.bit_offset = 0;
- 	fadt->x_pm_tmr_blk.resv = 0;
- 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
- 	fadt->x_gpe0_blk.space_id = 1;
- 	fadt->x_gpe0_blk.bit_width = 64;
- 	fadt->x_gpe0_blk.bit_offset = 0;
- 	fadt->x_gpe0_blk.resv = 0;
- 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- 	fadt->x_gpe0_blk.addrh = 0x0;
-
- 	fadt->x_gpe1_blk.space_id = 1;
- 	fadt->x_gpe1_blk.bit_width = 0;
- 	fadt->x_gpe1_blk.bit_offset = 0;
- 	fadt->x_gpe1_blk.resv = 0;
- 	fadt->x_gpe1_blk.addrl = 0x0;
- 	fadt->x_gpe1_blk.addrh = 0x0;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
+			ACPI_FADT_DOCKING_SUPPORTED;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
 
 	header->checksum =
 	    acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/ibase/mb899/fadt.c b/src/mainboard/ibase/mb899/fadt.c
index a0e381f..44d4c9b 100644
--- a/src/mainboard/ibase/mb899/fadt.c
+++ b/src/mainboard/ibase/mb899/fadt.c
@@ -20,17 +20,7 @@
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
+#include <cpu/x86/smm.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -39,8 +29,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
- 	header->length = sizeof(acpi_fadt_t);
- 	header->revision = 3;
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
 	memcpy(header->oem_id, "CORE  ", 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, "CORE", 4);
@@ -51,12 +41,12 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->model = 1;
 	fadt->preferred_pm_profile = PM_MOBILE;
 
-  	fadt->sci_int = 0x9;
- 	fadt->smi_cmd = APM_CNT;
- 	fadt->acpi_enable = ACPI_ENABLE;
- 	fadt->acpi_disable = ACPI_DISABLE;
-  	fadt->s4bios_req = 0x0;
- 	fadt->pstate_cnt = PST_CONTROL;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +65,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
- 	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
@@ -87,78 +77,78 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->century = 0x00;
 	fadt->iapc_boot_arch = 0x03;
 
- 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
 			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
 			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
 
- 	fadt->reset_reg.space_id = 0;
- 	fadt->reset_reg.bit_width = 0;
- 	fadt->reset_reg.bit_offset = 0;
- 	fadt->reset_reg.resv = 0;
- 	fadt->reset_reg.addrl = 0x0;
- 	fadt->reset_reg.addrh = 0x0;
-
- 	fadt->reset_value = 0;
- 	fadt->x_firmware_ctl_l = (unsigned long)facs;
- 	fadt->x_firmware_ctl_h = 0;
- 	fadt->x_dsdt_l = (unsigned long)dsdt;
- 	fadt->x_dsdt_h = 0;
-
- 	fadt->x_pm1a_evt_blk.space_id = 1;
- 	fadt->x_pm1a_evt_blk.bit_width = 32;
- 	fadt->x_pm1a_evt_blk.bit_offset = 0;
- 	fadt->x_pm1a_evt_blk.resv = 0;
- 	fadt->x_pm1a_evt_blk.addrl = pmbase;
- 	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_evt_blk.space_id = 1;
- 	fadt->x_pm1b_evt_blk.bit_width = 0;
- 	fadt->x_pm1b_evt_blk.bit_offset = 0;
- 	fadt->x_pm1b_evt_blk.resv = 0;
- 	fadt->x_pm1b_evt_blk.addrl = 0x0;
- 	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1a_cnt_blk.space_id = 1;
- 	fadt->x_pm1a_cnt_blk.bit_width = 16;
- 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1a_cnt_blk.resv = 0;
- 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_cnt_blk.space_id = 1;
- 	fadt->x_pm1b_cnt_blk.bit_width = 0;
- 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1b_cnt_blk.resv = 0;
- 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
- 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm2_cnt_blk.space_id = 1;
- 	fadt->x_pm2_cnt_blk.bit_width = 8;
- 	fadt->x_pm2_cnt_blk.bit_offset = 0;
- 	fadt->x_pm2_cnt_blk.resv = 0;
- 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
- 	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm_tmr_blk.space_id = 1;
- 	fadt->x_pm_tmr_blk.bit_width = 32;
- 	fadt->x_pm_tmr_blk.bit_offset = 0;
- 	fadt->x_pm_tmr_blk.resv = 0;
- 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
- 	fadt->x_gpe0_blk.space_id = 1;
- 	fadt->x_gpe0_blk.bit_width = 64;
- 	fadt->x_gpe0_blk.bit_offset = 0;
- 	fadt->x_gpe0_blk.resv = 0;
- 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- 	fadt->x_gpe0_blk.addrh = 0x0;
-
- 	fadt->x_gpe1_blk.space_id = 1;
- 	fadt->x_gpe1_blk.bit_width = 0;
- 	fadt->x_gpe1_blk.bit_offset = 0;
- 	fadt->x_gpe1_blk.resv = 0;
- 	fadt->x_gpe1_blk.addrl = 0x0;
- 	fadt->x_gpe1_blk.addrh = 0x0;
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
 
 	header->checksum =
 	    acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/intel/d945gclf/fadt.c b/src/mainboard/intel/d945gclf/fadt.c
index 5b2df8b..1a66eef 100644
--- a/src/mainboard/intel/d945gclf/fadt.c
+++ b/src/mainboard/intel/d945gclf/fadt.c
@@ -20,17 +20,7 @@
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
+#include <cpu/x86/smm.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -39,8 +29,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
- 	header->length = sizeof(acpi_fadt_t);
- 	header->revision = 3;
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
 	memcpy(header->oem_id, "CORE  ", 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, "CORE", 4);
@@ -51,12 +41,12 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->model = 1;
 	fadt->preferred_pm_profile = PM_MOBILE;
 
-  	fadt->sci_int = 0x9;
- 	fadt->smi_cmd = APM_CNT;
- 	fadt->acpi_enable = ACPI_ENABLE;
- 	fadt->acpi_disable = ACPI_DISABLE;
-  	fadt->s4bios_req = 0x0;
- 	fadt->pstate_cnt = PST_CONTROL;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +65,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
- 	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
@@ -87,78 +77,78 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->century = 0x00;
 	fadt->iapc_boot_arch = 0x03;
 
- 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
 			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
 
- 	fadt->reset_reg.space_id = 0;
- 	fadt->reset_reg.bit_width = 0;
- 	fadt->reset_reg.bit_offset = 0;
- 	fadt->reset_reg.resv = 0;
- 	fadt->reset_reg.addrl = 0x0;
- 	fadt->reset_reg.addrh = 0x0;
-
- 	fadt->reset_value = 0;
- 	fadt->x_firmware_ctl_l = (unsigned long)facs;
- 	fadt->x_firmware_ctl_h = 0;
- 	fadt->x_dsdt_l = (unsigned long)dsdt;
- 	fadt->x_dsdt_h = 0;
-
- 	fadt->x_pm1a_evt_blk.space_id = 1;
- 	fadt->x_pm1a_evt_blk.bit_width = 32;
- 	fadt->x_pm1a_evt_blk.bit_offset = 0;
- 	fadt->x_pm1a_evt_blk.resv = 0;
- 	fadt->x_pm1a_evt_blk.addrl = pmbase;
- 	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_evt_blk.space_id = 1;
- 	fadt->x_pm1b_evt_blk.bit_width = 0;
- 	fadt->x_pm1b_evt_blk.bit_offset = 0;
- 	fadt->x_pm1b_evt_blk.resv = 0;
- 	fadt->x_pm1b_evt_blk.addrl = 0x0;
- 	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1a_cnt_blk.space_id = 1;
- 	fadt->x_pm1a_cnt_blk.bit_width = 16;
- 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1a_cnt_blk.resv = 0;
- 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_cnt_blk.space_id = 1;
- 	fadt->x_pm1b_cnt_blk.bit_width = 0;
- 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1b_cnt_blk.resv = 0;
- 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
- 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm2_cnt_blk.space_id = 1;
- 	fadt->x_pm2_cnt_blk.bit_width = 8;
- 	fadt->x_pm2_cnt_blk.bit_offset = 0;
- 	fadt->x_pm2_cnt_blk.resv = 0;
- 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
- 	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm_tmr_blk.space_id = 1;
- 	fadt->x_pm_tmr_blk.bit_width = 32;
- 	fadt->x_pm_tmr_blk.bit_offset = 0;
- 	fadt->x_pm_tmr_blk.resv = 0;
- 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
- 	fadt->x_gpe0_blk.space_id = 1;
- 	fadt->x_gpe0_blk.bit_width = 64;
- 	fadt->x_gpe0_blk.bit_offset = 0;
- 	fadt->x_gpe0_blk.resv = 0;
- 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- 	fadt->x_gpe0_blk.addrh = 0x0;
-
- 	fadt->x_gpe1_blk.space_id = 1;
- 	fadt->x_gpe1_blk.bit_width = 0;
- 	fadt->x_gpe1_blk.bit_offset = 0;
- 	fadt->x_gpe1_blk.resv = 0;
- 	fadt->x_gpe1_blk.addrl = 0x0;
- 	fadt->x_gpe1_blk.addrh = 0x0;
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
 
 	header->checksum =
 	    acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c
index 86f4ba1..992c318 100644
--- a/src/mainboard/intel/eagleheights/fadt.c
+++ b/src/mainboard/intel/eagleheights/fadt.c
@@ -23,6 +23,7 @@
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
+#include <cpu/x86/smm.h>
 
 #define ACPI_PM1_STS        (pmbase + 0x00)
 #define ACPI_PM1_EN         (pmbase + 0x02)
@@ -67,12 +68,12 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->preferred_pm_profile = 7; /* Performance Server */
 	fadt->sci_int = 0x9;
 #if CONFIG_HAVE_SMI_HANDLER == 1
-	fadt->smi_cmd = 0xb2;
+	fadt->smi_cmd = APM_CNT;
 #else
 	fadt->smi_cmd = 0x00;
 #endif
-	fadt->acpi_enable = 0xe1;
-	fadt->acpi_disable = 0x1e;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 	fadt->s4bios_req = 0x0;
 	fadt->pstate_cnt = 0xe2;
 
diff --git a/src/mainboard/iwave/iWRainbowG6/fadt.c b/src/mainboard/iwave/iWRainbowG6/fadt.c
index ae58bbf..bc4a0d4 100644
--- a/src/mainboard/iwave/iWRainbowG6/fadt.c
+++ b/src/mainboard/iwave/iWRainbowG6/fadt.c
@@ -20,17 +20,7 @@
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
+#include <cpu/x86/smm.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -54,10 +44,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	fadt->sci_int = 0x9;
 	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = ACPI_ENABLE;
-	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = PST_CONTROL;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -76,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
-	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
diff --git a/src/mainboard/kontron/986lcd-m/fadt.c b/src/mainboard/kontron/986lcd-m/fadt.c
index 12aeac0..f945d3f 100644
--- a/src/mainboard/kontron/986lcd-m/fadt.c
+++ b/src/mainboard/kontron/986lcd-m/fadt.c
@@ -20,17 +20,7 @@
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
+#include <cpu/x86/smm.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -39,8 +29,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
- 	header->length = sizeof(acpi_fadt_t);
- 	header->revision = 3;
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
 	memcpy(header->oem_id, "CORE  ", 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, "CORE", 4);
@@ -51,12 +41,12 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->model = 1;
 	fadt->preferred_pm_profile = PM_MOBILE;
 
-  	fadt->sci_int = 0x9;
- 	fadt->smi_cmd = APM_CNT;
- 	fadt->acpi_enable = ACPI_ENABLE;
- 	fadt->acpi_disable = ACPI_DISABLE;
-  	fadt->s4bios_req = 0x0;
- 	fadt->pstate_cnt = PST_CONTROL;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +65,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
- 	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
@@ -87,79 +77,79 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->century = 0x00;
 	fadt->iapc_boot_arch = 0x03;
 
- 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
 			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
 			ACPI_FADT_RESET_REGISTER |
 			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
 
- 	fadt->reset_reg.space_id = 1;
- 	fadt->reset_reg.bit_width = 8;
- 	fadt->reset_reg.bit_offset = 0;
- 	fadt->reset_reg.resv = 0;
- 	fadt->reset_reg.addrl = 0xcf9;
- 	fadt->reset_reg.addrh = 0;
-
- 	fadt->reset_value = 6;
- 	fadt->x_firmware_ctl_l = (unsigned long)facs;
- 	fadt->x_firmware_ctl_h = 0;
- 	fadt->x_dsdt_l = (unsigned long)dsdt;
- 	fadt->x_dsdt_h = 0;
-
- 	fadt->x_pm1a_evt_blk.space_id = 1;
- 	fadt->x_pm1a_evt_blk.bit_width = 32;
- 	fadt->x_pm1a_evt_blk.bit_offset = 0;
- 	fadt->x_pm1a_evt_blk.resv = 0;
- 	fadt->x_pm1a_evt_blk.addrl = pmbase;
- 	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_evt_blk.space_id = 1;
- 	fadt->x_pm1b_evt_blk.bit_width = 0;
- 	fadt->x_pm1b_evt_blk.bit_offset = 0;
- 	fadt->x_pm1b_evt_blk.resv = 0;
- 	fadt->x_pm1b_evt_blk.addrl = 0x0;
- 	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1a_cnt_blk.space_id = 1;
- 	fadt->x_pm1a_cnt_blk.bit_width = 16;
- 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1a_cnt_blk.resv = 0;
- 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_cnt_blk.space_id = 1;
- 	fadt->x_pm1b_cnt_blk.bit_width = 0;
- 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1b_cnt_blk.resv = 0;
- 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
- 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm2_cnt_blk.space_id = 1;
- 	fadt->x_pm2_cnt_blk.bit_width = 8;
- 	fadt->x_pm2_cnt_blk.bit_offset = 0;
- 	fadt->x_pm2_cnt_blk.resv = 0;
- 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
- 	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm_tmr_blk.space_id = 1;
- 	fadt->x_pm_tmr_blk.bit_width = 32;
- 	fadt->x_pm_tmr_blk.bit_offset = 0;
- 	fadt->x_pm_tmr_blk.resv = 0;
- 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
- 	fadt->x_gpe0_blk.space_id = 1;
- 	fadt->x_gpe0_blk.bit_width = 64;
- 	fadt->x_gpe0_blk.bit_offset = 0;
- 	fadt->x_gpe0_blk.resv = 0;
- 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- 	fadt->x_gpe0_blk.addrh = 0x0;
-
- 	fadt->x_gpe1_blk.space_id = 1;
- 	fadt->x_gpe1_blk.bit_width = 0;
- 	fadt->x_gpe1_blk.bit_offset = 0;
- 	fadt->x_gpe1_blk.resv = 0;
- 	fadt->x_gpe1_blk.addrl = 0x0;
- 	fadt->x_gpe1_blk.addrh = 0x0;
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
 
 	header->checksum =
 	    acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/lenovo/t60/fadt.c b/src/mainboard/lenovo/t60/fadt.c
index e45db8a..9f73f9c 100644
--- a/src/mainboard/lenovo/t60/fadt.c
+++ b/src/mainboard/lenovo/t60/fadt.c
@@ -22,17 +22,12 @@
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
+#include <cpu/x86/smm.h>
 
 /* FIXME: This needs to go into a separate .h file
  * to be included by the ich7 smi handler, ich7 smi init
  * code and the mainboard fadt.
  */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -54,10 +49,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->preferred_pm_profile = PM_MOBILE;
 	fadt->sci_int = 0x9;
 	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = ACPI_ENABLE;
-	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = PST_CONTROL;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +70,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
-	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 0x23;
 	fadt->flush_size = 0;
diff --git a/src/mainboard/lenovo/x60/fadt.c b/src/mainboard/lenovo/x60/fadt.c
index e45db8a..9f73f9c 100644
--- a/src/mainboard/lenovo/x60/fadt.c
+++ b/src/mainboard/lenovo/x60/fadt.c
@@ -22,17 +22,12 @@
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
+#include <cpu/x86/smm.h>
 
 /* FIXME: This needs to go into a separate .h file
  * to be included by the ich7 smi handler, ich7 smi init
  * code and the mainboard fadt.
  */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -54,10 +49,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->preferred_pm_profile = PM_MOBILE;
 	fadt->sci_int = 0x9;
 	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = ACPI_ENABLE;
-	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = PST_CONTROL;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +70,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
-	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 0x23;
 	fadt->flush_size = 0;
diff --git a/src/mainboard/lenovo/x60/mainboard_smi.c b/src/mainboard/lenovo/x60/mainboard_smi.c
index 5e0f6a9..78f7f2a 100644
--- a/src/mainboard/lenovo/x60/mainboard_smi.c
+++ b/src/mainboard/lenovo/x60/mainboard_smi.c
@@ -75,4 +75,3 @@ int mainboard_io_trap_handler(int smif)
 	 * On failure, the IO Trap Handler returns a value != 0 */
 	return 0;
 }
-
diff --git a/src/mainboard/roda/rk886ex/fadt.c b/src/mainboard/roda/rk886ex/fadt.c
index e45db8a..b07856a 100644
--- a/src/mainboard/roda/rk886ex/fadt.c
+++ b/src/mainboard/roda/rk886ex/fadt.c
@@ -22,17 +22,7 @@
 #include <string.h>
 #include <device/pci.h>
 #include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
+#include <cpu/x86/smm.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
@@ -54,10 +44,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->preferred_pm_profile = PM_MOBILE;
 	fadt->sci_int = 0x9;
 	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = ACPI_ENABLE;
-	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = PST_CONTROL;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +65,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
-	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 0x23;
 	fadt->flush_size = 0;
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 4875ba7..1d306da 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -30,15 +30,6 @@
 
 #define DEBUG_SMI
 
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
-#define   MBI_UPDATE    0xeb
-#define APM_STS		0xb3
-
 /* I830M */
 #define SMRAM		0x90
 #define   D_OPEN	(1 << 6)
@@ -370,33 +361,33 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 
 	reg8 = inb(APM_CNT);
 	switch (reg8) {
-	case CST_CONTROL:
+	case APM_CNT_CST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "C-state control\n");
 		break;
-	case PST_CONTROL:
+	case APM_CNT_PST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "P-state control\n");
 		break;
-	case ACPI_DISABLE:
+	case APM_CNT_ACPI_DISABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl &= ~SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
-	case ACPI_ENABLE:
+	case APM_CNT_ACPI_ENABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl |= SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case GNVS_UPDATE:
+	case APM_CNT_GNVS_UPDATE:
 		if (smm_initialized) {
 			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;
@@ -407,7 +398,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 		smm_initialized = 1;
 		printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
 		break;
-	case MBI_UPDATE: // FIXME
+	case APM_CNT_MBI_UPDATE: // FIXME
 		if (mbi_initialized) {
 			printk(BIOS_DEBUG, "SMI#: mbi already registered!\n");
 			return;
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 7feb76a..394f161 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -29,6 +29,7 @@
 #include <arch/ioapic.h>
 #include <cpu/cpu.h>
 #include "i82801gx.h"
+#include <cpu/x86/smm.h>
 
 #define NMI_OFF	0
 
@@ -341,13 +342,13 @@ static void i82801gx_lock_smm(struct device *dev)
 #endif
 
 #if ENABLE_ACPI_MODE_IN_COREBOOT
-	printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
-	outb(0xe1, 0xb2); // Enable ACPI mode
-	printk(BIOS_DEBUG, "done.\n");
+		printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
+		outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
+		printk(BIOS_DEBUG, "done.\n");
 #else
-	printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
-	outb(0x1e, 0xb2); // Disable ACPI mode
-	printk(BIOS_DEBUG, "done.\n");
+		printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
+		outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
+		printk(BIOS_DEBUG, "done.\n");
 #endif
 	/* Don't allow evil boot loaders, kernels, or
 	 * userspace applications to deceive us:
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index bccf6d5..9befbf9 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -28,14 +28,6 @@
 #include <device/pci_def.h>
 #include "i82801gx.h"
 
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
-#define APM_STS		0xb3
-
 /* I945 */
 #define SMRAM		0x9d
 #define   D_OPEN	(1 << 6)
@@ -366,33 +358,33 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 		return;
 
 	switch (reg8) {
-	case CST_CONTROL:
+	case APM_CNT_CST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "C-state control\n");
 		break;
-	case PST_CONTROL:
+	case APM_CNT_PST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "P-state control\n");
 		break;
-	case ACPI_DISABLE:
+	case APM_CNT_ACPI_DISABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl &= ~SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
-	case ACPI_ENABLE:
+	case APM_CNT_ACPI_ENABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl |= SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case GNVS_UPDATE:
+	case APM_CNT_GNVS_UPDATE:
 		if (smm_initialized) {
 			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;
diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c
index 127f627..99ae018 100644
--- a/src/southbridge/intel/sch/smihandler.c
+++ b/src/southbridge/intel/sch/smihandler.c
@@ -28,11 +28,6 @@
 
 #define DEBUG_SMI
 
-#define APM_CNT		0xb2
-#define APM_STS		0xb3
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-
 /* I945 */
 #define SMRAM		0x9d
 #define   D_OPEN	(1 << 6)
diff --git a/src/southbridge/via/vt8237r/smihandler.c b/src/southbridge/via/vt8237r/smihandler.c
index 0c8ff2f..357e517 100644
--- a/src/southbridge/via/vt8237r/smihandler.c
+++ b/src/southbridge/via/vt8237r/smihandler.c
@@ -29,14 +29,6 @@
 #include <device/pci_def.h>
 #include "vt8237r.h"
 
-#define APM_CNT		0xb2
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x80
-#define   ACPI_DISABLE	0x1e
-#define   ACPI_ENABLE	0xe1
-#define   GNVS_UPDATE   0xea
-#define APM_STS		0xb3
-
 #include "nvs.h"
 
 /* While we read PMBASE dynamically in case it changed, let's
@@ -158,33 +150,33 @@ static void southbridge_smi_cmd(unsigned int node, smm_state_save_area_t *state_
 
 	reg8 = inb(pmbase + 0x2f);
 	switch (reg8) {
-	case CST_CONTROL:
+	case APM_CNT_CST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "C-state control\n");
 		break;
-	case PST_CONTROL:
+	case APM_CNT_PST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
 		printk(BIOS_DEBUG, "P-state control\n");
 		break;
-	case ACPI_DISABLE:
+	case APM_CNT_ACPI_DISABLE:
 		pmctrl = inw(pmbase + PM1_CNT);
 		pmctrl &= ~SCI_EN;
 		outw(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
-	case ACPI_ENABLE:
+	case APM_CNT_ACPI_ENABLE:
 		pmctrl = inw(pmbase + PM1_CNT);
 		pmctrl |= SCI_EN;
 		outw(pmctrl, pmbase + PM1_CNT);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case GNVS_UPDATE:
+	case APM_CNT_GNVS_UPDATE:
 		if (smm_initialized) {
 			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;
-- 
1.7.5.3




From svens at stackframe.org  Sun Jun  5 15:51:05 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sun,  5 Jun 2011 15:51:05 +0200
Subject: [coreboot] [PATCH] i82801gx: enable ACPI during S3 resume
Message-ID: <1307281865-32298-1-git-send-email-svens@stackframe.org>

disabling ACPI during S3 wakeup breaks ACPI wakeup, as the
Host OS is assuming that ACPI is enabled.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/southbridge/intel/i82801gx/lpc.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 394f161..b4b2f41 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -341,6 +341,7 @@ static void i82801gx_lock_smm(struct device *dev)
 	u8 reg8;
 #endif
 
+	if (acpi_slp_type != 3) {
 #if ENABLE_ACPI_MODE_IN_COREBOOT
 		printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
 		outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
@@ -350,6 +351,10 @@ static void i82801gx_lock_smm(struct device *dev)
 		outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
 		printk(BIOS_DEBUG, "done.\n");
 #endif
+	} else {
+		printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
+		outb(APM_CNT_ACPI_ENABLE, APM_CNT);
+	}
 	/* Don't allow evil boot loaders, kernels, or
 	 * userspace applications to deceive us:
 	 */
-- 
1.7.5.3




From svens at stackframe.org  Sun Jun  5 20:06:57 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sun, 05 Jun 2011 20:06:57 +0200
Subject: [coreboot] [PATCH 1/2] SMM: add mainboard_apm_cnt() callback
In-Reply-To: <4DEADCC4.5090305@coreboot.org> (Stefan Reinauer's message of
	"Sat\, 04 Jun 2011 18\:32\:52 -0700")
References: <1307209655-14859-1-git-send-email-svens@stackframe.org>
	<4DEADCC4.5090305@coreboot.org>
Message-ID: <877h909mpq.fsf@begreifnix.stackframe.org>

Stefan Reinauer <stefan.reinauer at coreboot.org> writes:

>> --- a/src/southbridge/intel/i82801gx/smihandler.c
>> +++ b/src/southbridge/intel/i82801gx/smihandler.c
>> @@ -362,6 +362,9 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
>>   	/* Emulate B2 register as the FADT / Linux expects it */
>>
>>   	reg8 = inb(APM_CNT);
>> +	if (mainboard_apm_cnt&&  mainboard_apm_cnt(reg8))
>> +		return;
>
> Is it on purpose that the mainboard_apm_cnt function can prevent the
> generic 82801gx code (including the not implemented C state
> coordination) from running?

Yes, that's intentional. If one mainboard doesn't like the way how the
i82801gx handles some APM_CNT, it could say so and does it's own
implementation. Most callbacks will probably simply return 0, but's IMHO
it's nice to have this option.

Sven



From patrick at georgi-clan.de  Sun Jun  5 22:48:09 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 05 Jun 2011 22:48:09 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
Message-ID: <1307306889.1783.36.camel@kubuntu>

Dear coreboot developers, stakeholders, and enthusiasts,

I'm glad to be able to announce that we moved the repository
infrastructure to git and gerrit, with jenkins as supporting facility.

This was done with the goal of improving the development workflow,
meaning less overhead for developers when managing the patch queue. This
should lead to losing fewer patch submissions.

So far we used patchwork[1], but it's more maintenance work than
practical given that it requires manual handling of patches that don't
match the commit diff, and of patches that went through multiple
iterations.
While it improved the visibility of patches (and I'm thankful for that),
it still posed a higher than necessary barrier to patch review.

Gerrit[2] is a code review utility developed by Google which uses the
distributed properties of git to provide a seamless path for patches
from submission to commit.

For this, git[3] is used: Gerrit uses its ability to create and tear
down branches as necessary to push every contribution into its own
branch. This way it's already "tracked" by the version control system
without influencing the master branch.

The use of git also plays well into the desire of several coreboot
contributors to switch from svn to git.

In addition to these changes, we also moved the build bot from our own
custom build variant to a more standard Jenkins[4] installation. In
addition to building commits after they are integrated on the master
branch ("trunk" in SVN terminology), it's also configured to build patch
submissions on gerrit as they come in. That way there's automated
feedback on a patch before spending time on it.

All this means that the coreboot development workflow changes
considerably:

1. New SCM
You will need git, so install it from your usual software distribution
channels.

For patch submission a gerrit account is necessary. You can register it
on http://review.coreboot.org. With the account you can also review
patches. The ability to merge patches to mainline will be granted by
admins.

ssh public keys are used for authentication. You can register them with
gerrit in your user preferences at http://review.coreboot.org/#settings
when logged in.

Gerrit requires that the commit message contains Change-Id: lines. "make
gitconfig" inside a coreboot checkout installs a commit message handler
which takes care of this.

The committer address must match an email address that is registered
with your gerrit acccount. Again these can be configured in gerrit user
preferences.

Fetching anonymously: git clone http://review.coreboot.org/p/coreboot
Fetching authenticated: git clone
ssh://<username>@review.coreboot.org:29418/coreboot

2. New patch submission process
Develop "as usual" in git, and commit freely.
When you're ready to submit patches, push them with
  git push origin HEAD:refs/for/master

This will tell gerrit which branch your commits are for (master) and it
will create internal branches for each commit you pushed, making them
separate changesets. If you push a number of commits at once, they're
properly linked as "dependencies", so people (and tools like gerrit and
jenkins) are aware about prerequisites.

For automating some aspects of patch submission, see the last paragraph
of http://review.coreboot.org/Documentation/user-upload.html#push_create

We will also document more of making live easier at
http://www.coreboot.org/Git as best practices are established.

3. New patch review process
The main interface to do patch reviews is the gerrit webapp at
http://review.coreboot.org. For those who tend to avoid web apps,
there's the option of controlling gerrit via ssh. Detailed information
on that will be posted at http://www.coreboot.org/Git.
There's no real workflow defined around this interface yet because it
seems to be an unpopular choice as _User_ Interface. This means, we'll
have to develop our own.

4. Mail notification
Mail notification to the mailing list is implemented from scratch. Right
now it only reports on new patch submissions and on patches merged into
the master branch. More events might/will follow in future, and we will
certainly tweak the ad-hoc messages and formatting some more.


Questions? Comments? Praise? Flames?
Patrick


[1] http://ozlabs.org/~jk/projects/patchwork
[2] http://gerrit.googlecode.com
[3] http://git-scm.com/
[4] http://jenkins-ci.org/




From njacobs8 at hetnet.nl  Sun Jun  5 23:14:27 2011
From: njacobs8 at hetnet.nl (Nils)
Date: Sun, 05 Jun 2011 23:14:27 +0200
Subject: [coreboot] Wyse S10
Message-ID: <1307308467.2343.23.camel@Debian.lan>

Hello Mohammed,

You wrote:

>First off, I have just stumbled onto this project after tearing my hair
>out
>with a Wyse S10 and the ultra crappy BIOS it comes with.
That's the reason i started to port the Wyse S50 to coreboot.:)
>
>
>I have searched the archives of this DL and I see a few people have
>played
>with installing coreboot on a Wyse S10.
>Has anyone gotten it to successfully work?
Not that i know, but it seems the hardware is the same as the S50.
The S50 port is still a work in progress as i have little time to spent
on Coreboot.
At the moment i am fighting SerialICE to be able to debug the original
BIOS to get enough information to get early VGA working.
If you are a programmer, i could use some help. :)
The current state of the S50 port boots Linux and is useable with the
kernel GX2 VGA driver.
Early VGA and ACPI are not supported yet so windows will probably not
work.

Greetings, Nils.





From gregg.drwho8 at gmail.com  Mon Jun  6 00:17:10 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sun, 5 Jun 2011 18:17:10 -0400
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <1307306889.1783.36.camel@kubuntu>
References: <1307306889.1783.36.camel@kubuntu>
Message-ID: <BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>

On Sun, Jun 5, 2011 at 4:48 PM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Dear coreboot developers, stakeholders, and enthusiasts,
>
> I'm glad to be able to announce that we moved the repository
> infrastructure to git and gerrit, with jenkins as supporting facility.
>
> This was done with the goal of improving the development workflow,
> meaning less overhead for developers when managing the patch queue. This
> should lead to losing fewer patch submissions.
>
> So far we used patchwork[1], but it's more maintenance work than
> practical given that it requires manual handling of patches that don't
> match the commit diff, and of patches that went through multiple
> iterations.
> While it improved the visibility of patches (and I'm thankful for that),
> it still posed a higher than necessary barrier to patch review.
>
> Gerrit[2] is a code review utility developed by Google which uses the
> distributed properties of git to provide a seamless path for patches
> from submission to commit.
>
> For this, git[3] is used: Gerrit uses its ability to create and tear
> down branches as necessary to push every contribution into its own
> branch. This way it's already "tracked" by the version control system
> without influencing the master branch.
>
> The use of git also plays well into the desire of several coreboot
> contributors to switch from svn to git.
>
> In addition to these changes, we also moved the build bot from our own
> custom build variant to a more standard Jenkins[4] installation. In
> addition to building commits after they are integrated on the master
> branch ("trunk" in SVN terminology), it's also configured to build patch
> submissions on gerrit as they come in. That way there's automated
> feedback on a patch before spending time on it.
>
> All this means that the coreboot development workflow changes
> considerably:
>
> 1. New SCM
> You will need git, so install it from your usual software distribution
> channels.
>
> For patch submission a gerrit account is necessary. You can register it
> on http://review.coreboot.org. With the account you can also review
> patches. The ability to merge patches to mainline will be granted by
> admins.
>
> ssh public keys are used for authentication. You can register them with
> gerrit in your user preferences at http://review.coreboot.org/#settings
> when logged in.
>
> Gerrit requires that the commit message contains Change-Id: lines. "make
> gitconfig" inside a coreboot checkout installs a commit message handler
> which takes care of this.
>
> The committer address must match an email address that is registered
> with your gerrit acccount. Again these can be configured in gerrit user
> preferences.
>
> Fetching anonymously: git clone http://review.coreboot.org/p/coreboot
> Fetching authenticated: git clone
> ssh://<username>@review.coreboot.org:29418/coreboot
>
> 2. New patch submission process
> Develop "as usual" in git, and commit freely.
> When you're ready to submit patches, push them with
> ?git push origin HEAD:refs/for/master
>
> This will tell gerrit which branch your commits are for (master) and it
> will create internal branches for each commit you pushed, making them
> separate changesets. If you push a number of commits at once, they're
> properly linked as "dependencies", so people (and tools like gerrit and
> jenkins) are aware about prerequisites.
>
> For automating some aspects of patch submission, see the last paragraph
> of http://review.coreboot.org/Documentation/user-upload.html#push_create
>
> We will also document more of making live easier at
> http://www.coreboot.org/Git as best practices are established.
>
> 3. New patch review process
> The main interface to do patch reviews is the gerrit webapp at
> http://review.coreboot.org. For those who tend to avoid web apps,
> there's the option of controlling gerrit via ssh. Detailed information
> on that will be posted at http://www.coreboot.org/Git.
> There's no real workflow defined around this interface yet because it
> seems to be an unpopular choice as _User_ Interface. This means, we'll
> have to develop our own.
>
> 4. Mail notification
> Mail notification to the mailing list is implemented from scratch. Right
> now it only reports on new patch submissions and on patches merged into
> the master branch. More events might/will follow in future, and we will
> certainly tweak the ad-hoc messages and formatting some more.
>
>
> Questions? Comments? Praise? Flames?
> Patrick
>
>
> [1] http://ozlabs.org/~jk/projects/patchwork
> [2] http://gerrit.googlecode.com
> [3] http://git-scm.com/
> [4] http://jenkins-ci.org/
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Hello!
I have one. What would prompt this to happen?
root at jimkirk2:/usr/src/lobos# git clone http://review.coreboot.org/p/coreboot
Initialized empty Git repository in /usr/src/lobos/coreboot/.git/
fatal: http://review.coreboot.org/p/coreboot/info/refs download error
- The requested URL returned error: 403
root at jimkirk2:/usr/src/lobos#

That's from my first efforts to clone the recently configured repository.

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From thomas at gstaedtner.net  Mon Jun  6 00:24:57 2011
From: thomas at gstaedtner.net (=?UTF-8?Q?Thomas_Gst=C3=A4dtner?=)
Date: Mon, 6 Jun 2011 00:24:57 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
Message-ID: <BANLkTim5x6pCNDOHfUzsZRuGgyoGxw4fUg@mail.gmail.com>

On Mon, Jun 6, 2011 at 00:17, Gregg Levine <gregg.drwho8 at gmail.com> wrote:
> On Sun, Jun 5, 2011 at 4:48 PM, Patrick Georgi <patrick at georgi-clan.de> wrote:
>> Dear coreboot developers, stakeholders, and enthusiasts,
>>
>> I'm glad to be able to announce that we moved the repository
>> infrastructure to git and gerrit, with jenkins as supporting facility.
>>
>> This was done with the goal of improving the development workflow,
>> meaning less overhead for developers when managing the patch queue. This
>> should lead to losing fewer patch submissions.
>>
>> So far we used patchwork[1], but it's more maintenance work than
>> practical given that it requires manual handling of patches that don't
>> match the commit diff, and of patches that went through multiple
>> iterations.
>> While it improved the visibility of patches (and I'm thankful for that),
>> it still posed a higher than necessary barrier to patch review.
>>
>> Gerrit[2] is a code review utility developed by Google which uses the
>> distributed properties of git to provide a seamless path for patches
>> from submission to commit.
>>
>> For this, git[3] is used: Gerrit uses its ability to create and tear
>> down branches as necessary to push every contribution into its own
>> branch. This way it's already "tracked" by the version control system
>> without influencing the master branch.
>>
>> The use of git also plays well into the desire of several coreboot
>> contributors to switch from svn to git.
>>
>> In addition to these changes, we also moved the build bot from our own
>> custom build variant to a more standard Jenkins[4] installation. In
>> addition to building commits after they are integrated on the master
>> branch ("trunk" in SVN terminology), it's also configured to build patch
>> submissions on gerrit as they come in. That way there's automated
>> feedback on a patch before spending time on it.
>>
>> All this means that the coreboot development workflow changes
>> considerably:
>>
>> 1. New SCM
>> You will need git, so install it from your usual software distribution
>> channels.
>>
>> For patch submission a gerrit account is necessary. You can register it
>> on http://review.coreboot.org. With the account you can also review
>> patches. The ability to merge patches to mainline will be granted by
>> admins.
>>
>> ssh public keys are used for authentication. You can register them with
>> gerrit in your user preferences at http://review.coreboot.org/#settings
>> when logged in.
>>
>> Gerrit requires that the commit message contains Change-Id: lines. "make
>> gitconfig" inside a coreboot checkout installs a commit message handler
>> which takes care of this.
>>
>> The committer address must match an email address that is registered
>> with your gerrit acccount. Again these can be configured in gerrit user
>> preferences.
>>
>> Fetching anonymously: git clone http://review.coreboot.org/p/coreboot
>> Fetching authenticated: git clone
>> ssh://<username>@review.coreboot.org:29418/coreboot
>>
>> 2. New patch submission process
>> Develop "as usual" in git, and commit freely.
>> When you're ready to submit patches, push them with
>> ?git push origin HEAD:refs/for/master
>>
>> This will tell gerrit which branch your commits are for (master) and it
>> will create internal branches for each commit you pushed, making them
>> separate changesets. If you push a number of commits at once, they're
>> properly linked as "dependencies", so people (and tools like gerrit and
>> jenkins) are aware about prerequisites.
>>
>> For automating some aspects of patch submission, see the last paragraph
>> of http://review.coreboot.org/Documentation/user-upload.html#push_create
>>
>> We will also document more of making live easier at
>> http://www.coreboot.org/Git as best practices are established.
>>
>> 3. New patch review process
>> The main interface to do patch reviews is the gerrit webapp at
>> http://review.coreboot.org. For those who tend to avoid web apps,
>> there's the option of controlling gerrit via ssh. Detailed information
>> on that will be posted at http://www.coreboot.org/Git.
>> There's no real workflow defined around this interface yet because it
>> seems to be an unpopular choice as _User_ Interface. This means, we'll
>> have to develop our own.
>>
>> 4. Mail notification
>> Mail notification to the mailing list is implemented from scratch. Right
>> now it only reports on new patch submissions and on patches merged into
>> the master branch. More events might/will follow in future, and we will
>> certainly tweak the ad-hoc messages and formatting some more.
>>
>>
>> Questions? Comments? Praise? Flames?
>> Patrick
>>
>>
>> [1] http://ozlabs.org/~jk/projects/patchwork
>> [2] http://gerrit.googlecode.com
>> [3] http://git-scm.com/
>> [4] http://jenkins-ci.org/
>>
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>
> Hello!
> I have one. What would prompt this to happen?
> root at jimkirk2:/usr/src/lobos# git clone http://review.coreboot.org/p/coreboot
> Initialized empty Git repository in /usr/src/lobos/coreboot/.git/
> fatal: http://review.coreboot.org/p/coreboot/info/refs download error
> - The requested URL returned error: 403
> root at jimkirk2:/usr/src/lobos#
>
> That's from my first efforts to clone the recently configured repository.
>
> -----
> Gregg C Levine gregg.drwho8 at gmail.com
> "This signature fought the Time Wars, time and again."
>

That's odd.
First of all: worksforme(tm).
This message should only appear when you do a "git init", not for a "git clone"
Maybe the path "/usr/src/lobos/coreboot" already exists? Highly
unlikely that this would cause this behavior, but if so, try to remove
the coreboot dir or chose another destination.



From gregg.drwho8 at gmail.com  Mon Jun  6 00:29:42 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sun, 5 Jun 2011 18:29:42 -0400
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <BANLkTim5x6pCNDOHfUzsZRuGgyoGxw4fUg@mail.gmail.com>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
	<BANLkTim5x6pCNDOHfUzsZRuGgyoGxw4fUg@mail.gmail.com>
Message-ID: <BANLkTikkDjHpqDK7-dMe5wC8VYun+txnDg@mail.gmail.com>

On Sun, Jun 5, 2011 at 6:24 PM, Thomas Gst?dtner <thomas at gstaedtner.net> wrote:
> On Mon, Jun 6, 2011 at 00:17, Gregg Levine <gregg.drwho8 at gmail.com> wrote:
>> On Sun, Jun 5, 2011 at 4:48 PM, Patrick Georgi <patrick at georgi-clan.de> wrote:
>>> Dear coreboot developers, stakeholders, and enthusiasts,
>>>
>>> I'm glad to be able to announce that we moved the repository
>>> infrastructure to git and gerrit, with jenkins as supporting facility.
>>>
>>> This was done with the goal of improving the development workflow,
>>> meaning less overhead for developers when managing the patch queue. This
>>> should lead to losing fewer patch submissions.
>>>
>>> So far we used patchwork[1], but it's more maintenance work than
>>> practical given that it requires manual handling of patches that don't
>>> match the commit diff, and of patches that went through multiple
>>> iterations.
>>> While it improved the visibility of patches (and I'm thankful for that),
>>> it still posed a higher than necessary barrier to patch review.
>>>
>>> Gerrit[2] is a code review utility developed by Google which uses the
>>> distributed properties of git to provide a seamless path for patches
>>> from submission to commit.
>>>
>>> For this, git[3] is used: Gerrit uses its ability to create and tear
>>> down branches as necessary to push every contribution into its own
>>> branch. This way it's already "tracked" by the version control system
>>> without influencing the master branch.
>>>
>>> The use of git also plays well into the desire of several coreboot
>>> contributors to switch from svn to git.
>>>
>>> In addition to these changes, we also moved the build bot from our own
>>> custom build variant to a more standard Jenkins[4] installation. In
>>> addition to building commits after they are integrated on the master
>>> branch ("trunk" in SVN terminology), it's also configured to build patch
>>> submissions on gerrit as they come in. That way there's automated
>>> feedback on a patch before spending time on it.
>>>
>>> All this means that the coreboot development workflow changes
>>> considerably:
>>>
>>> 1. New SCM
>>> You will need git, so install it from your usual software distribution
>>> channels.
>>>
>>> For patch submission a gerrit account is necessary. You can register it
>>> on http://review.coreboot.org. With the account you can also review
>>> patches. The ability to merge patches to mainline will be granted by
>>> admins.
>>>
>>> ssh public keys are used for authentication. You can register them with
>>> gerrit in your user preferences at http://review.coreboot.org/#settings
>>> when logged in.
>>>
>>> Gerrit requires that the commit message contains Change-Id: lines. "make
>>> gitconfig" inside a coreboot checkout installs a commit message handler
>>> which takes care of this.
>>>
>>> The committer address must match an email address that is registered
>>> with your gerrit acccount. Again these can be configured in gerrit user
>>> preferences.
>>>
>>> Fetching anonymously: git clone http://review.coreboot.org/p/coreboot
>>> Fetching authenticated: git clone
>>> ssh://<username>@review.coreboot.org:29418/coreboot
>>>
>>> 2. New patch submission process
>>> Develop "as usual" in git, and commit freely.
>>> When you're ready to submit patches, push them with
>>> ?git push origin HEAD:refs/for/master
>>>
>>> This will tell gerrit which branch your commits are for (master) and it
>>> will create internal branches for each commit you pushed, making them
>>> separate changesets. If you push a number of commits at once, they're
>>> properly linked as "dependencies", so people (and tools like gerrit and
>>> jenkins) are aware about prerequisites.
>>>
>>> For automating some aspects of patch submission, see the last paragraph
>>> of http://review.coreboot.org/Documentation/user-upload.html#push_create
>>>
>>> We will also document more of making live easier at
>>> http://www.coreboot.org/Git as best practices are established.
>>>
>>> 3. New patch review process
>>> The main interface to do patch reviews is the gerrit webapp at
>>> http://review.coreboot.org. For those who tend to avoid web apps,
>>> there's the option of controlling gerrit via ssh. Detailed information
>>> on that will be posted at http://www.coreboot.org/Git.
>>> There's no real workflow defined around this interface yet because it
>>> seems to be an unpopular choice as _User_ Interface. This means, we'll
>>> have to develop our own.
>>>
>>> 4. Mail notification
>>> Mail notification to the mailing list is implemented from scratch. Right
>>> now it only reports on new patch submissions and on patches merged into
>>> the master branch. More events might/will follow in future, and we will
>>> certainly tweak the ad-hoc messages and formatting some more.
>>>
>>>
>>> Questions? Comments? Praise? Flames?
>>> Patrick
>>>
>>>
>>> [1] http://ozlabs.org/~jk/projects/patchwork
>>> [2] http://gerrit.googlecode.com
>>> [3] http://git-scm.com/
>>> [4] http://jenkins-ci.org/
>>>
>>>
>>> --
>>> coreboot mailing list: coreboot at coreboot.org
>>> http://www.coreboot.org/mailman/listinfo/coreboot
>>>
>>
>> Hello!
>> I have one. What would prompt this to happen?
>> root at jimkirk2:/usr/src/lobos# git clone http://review.coreboot.org/p/coreboot
>> Initialized empty Git repository in /usr/src/lobos/coreboot/.git/
>> fatal: http://review.coreboot.org/p/coreboot/info/refs download error
>> - The requested URL returned error: 403
>> root at jimkirk2:/usr/src/lobos#
>>
>> That's from my first efforts to clone the recently configured repository.
>>
>> -----
>> Gregg C Levine gregg.drwho8 at gmail.com
>> "This signature fought the Time Wars, time and again."
>>
>
> That's odd.
> First of all: worksforme(tm).
> This message should only appear when you do a "git init", not for a "git clone"
> Maybe the path "/usr/src/lobos/coreboot" already exists? Highly
> unlikely that this would cause this behavior, but if so, try to remove
> the coreboot dir or chose another destination.
>

Hello!
Actually there was indeed a checked out directory present. It
complained and I first moved over with a new name attached. Then
repeated the statement. Twice in fact.

Since I usually synch my working directory with what is present on the
site on a Sunday, I am going to wait a week and try again.

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From peter at stuge.se  Mon Jun  6 00:32:05 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Jun 2011 00:32:05 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
Message-ID: <20110605223205.10281.qmail@stuge.se>

Gregg Levine wrote:
> What would prompt this to happen?
> root at jimkirk2:/usr/src/lobos# git clone http://review.coreboot.org/p/coreboot
> Initialized empty Git repository in /usr/src/lobos/coreboot/.git/
> fatal: http://review.coreboot.org/p/coreboot/info/refs download error
> - The requested URL returned error: 403
> root at jimkirk2:/usr/src/lobos#

I'm not sure why you get this error.

I can successfully clone using the exact same command.

I can however also confirm that I get a HTTP 403 error on the URL
shown in the error message. I guess the version of Git that you are
using requests different things from the server than my version.

I am using version 1.7.4.1 with success. Which version are you using?

If your Git version is older than 1.6.6 then please upgrade to a
version >= 1.6.6, since that version gained significant performance
improvements specifically when using HTTP.


//Peter



From gregg.drwho8 at gmail.com  Mon Jun  6 00:38:46 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sun, 5 Jun 2011 18:38:46 -0400
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <20110605223205.10281.qmail@stuge.se>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
	<20110605223205.10281.qmail@stuge.se>
Message-ID: <BANLkTi=REBJF_d3YV_gSouAHF1kDLPL27A@mail.gmail.com>

On Sun, Jun 5, 2011 at 6:32 PM, Peter Stuge <peter at stuge.se> wrote:
> Gregg Levine wrote:
>> What would prompt this to happen?
>> root at jimkirk2:/usr/src/lobos# git clone http://review.coreboot.org/p/coreboot
>> Initialized empty Git repository in /usr/src/lobos/coreboot/.git/
>> fatal: http://review.coreboot.org/p/coreboot/info/refs download error
>> - The requested URL returned error: 403
>> root at jimkirk2:/usr/src/lobos#
>
> I'm not sure why you get this error.
>
> I can successfully clone using the exact same command.
>
> I can however also confirm that I get a HTTP 403 error on the URL
> shown in the error message. I guess the version of Git that you are
> using requests different things from the server than my version.
>
> I am using version 1.7.4.1 with success. Which version are you using?
>
> If your Git version is older than 1.6.6 then please upgrade to a
> version >= 1.6.6, since that version gained significant performance
> improvements specifically when using HTTP.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Hello!
Peter the system that everything is hosted on, is wearing version
1.6.1.3 and the test system (same distribution) is wearing 1.7.1.

I am making plans, perhaps further decisions to upgrade to that
release. There are specific issues involved with doing so as all of us
can imagine.
(I'm running Slackware Linux here.)
-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From paulepanter at users.sourceforge.net  Mon Jun  6 00:54:16 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Mon, 06 Jun 2011 00:54:16 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <BANLkTi=REBJF_d3YV_gSouAHF1kDLPL27A@mail.gmail.com>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
	<20110605223205.10281.qmail@stuge.se>
	<BANLkTi=REBJF_d3YV_gSouAHF1kDLPL27A@mail.gmail.com>
Message-ID: <1307314456.5181.34.camel@mattotaupa>

Am Sonntag, den 05.06.2011, 18:38 -0400 schrieb Gregg Levine:
> On Sun, Jun 5, 2011 at 6:32 PM, Peter Stuge <peter at stuge.se> wrote:
> > Gregg Levine wrote:
> >> What would prompt this to happen?
> >> root at jimkirk2:/usr/src/lobos# git clone http://review.coreboot.org/p/coreboot
> >> Initialized empty Git repository in /usr/src/lobos/coreboot/.git/
> >> fatal: http://review.coreboot.org/p/coreboot/info/refs download error
> >> - The requested URL returned error: 403
> >> root at jimkirk2:/usr/src/lobos#
> >
> > I'm not sure why you get this error.
> >
> > I can successfully clone using the exact same command.
> >
> > I can however also confirm that I get a HTTP 403 error on the URL
> > shown in the error message. I guess the version of Git that you are
> > using requests different things from the server than my version.
> >
> > I am using version 1.7.4.1 with success. Which version are you using?
> >
> > If your Git version is older than 1.6.6 then please upgrade to a
> > version >= 1.6.6, since that version gained significant performance
> > improvements specifically when using HTTP.

> Peter the system that everything is hosted on, is wearing version
> 1.6.1.3 and the test system (same distribution) is wearing 1.7.1.

Is it working for you using Git 1.7.1?

[?]


Thanks,

Paul
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From gregg.drwho8 at gmail.com  Mon Jun  6 00:56:57 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sun, 5 Jun 2011 18:56:57 -0400
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <1307314456.5181.34.camel@mattotaupa>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
	<20110605223205.10281.qmail@stuge.se>
	<BANLkTi=REBJF_d3YV_gSouAHF1kDLPL27A@mail.gmail.com>
	<1307314456.5181.34.camel@mattotaupa>
Message-ID: <BANLkTi=UYegBikyG+sXEDy2hAPUPvnQ3rQ@mail.gmail.com>

On Sun, Jun 5, 2011 at 6:54 PM, Paul Menzel
<paulepanter at users.sourceforge.net> wrote:
> Am Sonntag, den 05.06.2011, 18:38 -0400 schrieb Gregg Levine:
>> On Sun, Jun 5, 2011 at 6:32 PM, Peter Stuge <peter at stuge.se> wrote:
>> > Gregg Levine wrote:
>> >> What would prompt this to happen?
>> >> root at jimkirk2:/usr/src/lobos# git clone http://review.coreboot.org/p/coreboot
>> >> Initialized empty Git repository in /usr/src/lobos/coreboot/.git/
>> >> fatal: http://review.coreboot.org/p/coreboot/info/refs download error
>> >> - The requested URL returned error: 403
>> >> root at jimkirk2:/usr/src/lobos#
>> >
>> > I'm not sure why you get this error.
>> >
>> > I can successfully clone using the exact same command.
>> >
>> > I can however also confirm that I get a HTTP 403 error on the URL
>> > shown in the error message. I guess the version of Git that you are
>> > using requests different things from the server than my version.
>> >
>> > I am using version 1.7.4.1 with success. Which version are you using?
>> >
>> > If your Git version is older than 1.6.6 then please upgrade to a
>> > version >= 1.6.6, since that version gained significant performance
>> > improvements specifically when using HTTP.
>
>> Peter the system that everything is hosted on, is wearing version
>> 1.6.1.3 and the test system (same distribution) is wearing 1.7.1.
>
> Is it working for you using Git 1.7.1?
>
> [?]
>
>
> Thanks,
>
> Paul
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Hello!
It in all probability will do so, but I have not tried as such.

This is my one complaint against just git, it is the only source
control method that has a strange learning curve.
-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From peter at stuge.se  Mon Jun  6 00:59:56 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Jun 2011 00:59:56 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <BANLkTi=REBJF_d3YV_gSouAHF1kDLPL27A@mail.gmail.com>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
	<20110605223205.10281.qmail@stuge.se>
	<BANLkTi=REBJF_d3YV_gSouAHF1kDLPL27A@mail.gmail.com>
Message-ID: <20110605225956.17493.qmail@stuge.se>

Gregg Levine wrote:
> >> What would prompt this to happen?
> >> root at jimkirk2:/usr/src/lobos# git clone http://review.coreboot.org/p/coreboot
> >> Initialized empty Git repository in /usr/src/lobos/coreboot/.git/
> >> fatal: http://review.coreboot.org/p/coreboot/info/refs download error
> >> - The requested URL returned error: 403
..
> > I guess the version of Git that you are
> > using requests different things from the server than my version.
..
> Peter the system that everything is hosted on, is wearing version
> 1.6.1.3 and the test system (same distribution) is wearing 1.7.1.

I understand. Version 1.6.1.3 is from February 2009, so is rather
old.


> I am making plans, perhaps further decisions to upgrade to that
> release. There are specific issues involved with doing so as all
> of us can imagine.
> (I'm running Slackware Linux here.)

It might be possible for you to upgrade only the git package, without
needing to upgrade the full distribution.

When I ran Slackware I could download a newer package, such as:

http://slackware.mirrors.easynews.com/linux/slackware/slackware-13.37/slackware/d/git-1.7.4.4-i486-1.txz

And then simply run

upgradepkg git-1.7.4.4-i486-1.txz

But I do not know if this still works. Could be worth a try!


//Peter



From gregg.drwho8 at gmail.com  Mon Jun  6 03:29:23 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sun, 5 Jun 2011 21:29:23 -0400
Subject: [coreboot] Linux and distribution versions and installed tools
Message-ID: <BANLkTikS1NxMxBHwkhiqnrbcEr0c2=D_jw@mail.gmail.com>

Hello!
Peter you are correct regarding how to upgrade a package for
Slackware. I've done it several times on every single release I've
run.

However I believe the libraries that the version of Git we now need
for Coreboot, are some what advanced versus the ones for the version
that was installed on my development (regular system). I've gone ahead
and downloaded the source for both Git, and the compression tool
needed to extract the supplied source code. Naturally my tools to make
the package are appropriate for the distribution version on it, and
not for the test system.

I first created the compression tool that the tar file would need to
use to extract that source tar file.

So to make the package, I then extracted the regular tar file from
what was supplied, and compressed it using the normal Gzip one. Then
from there it was a simple step to run the script file to make the
package. Of course it complained that the regular git program was
installed. I removed it, and started all over again. The package is
still being made. The system is still at work making the package.

Group we need to set up a page which states the absolute minimum
needed for the tools to work to retrieve things.

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From peter at stuge.se  Mon Jun  6 04:46:33 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Jun 2011 04:46:33 +0200
Subject: [coreboot] Linux and distribution versions and installed tools
In-Reply-To: <BANLkTikS1NxMxBHwkhiqnrbcEr0c2=D_jw@mail.gmail.com>
References: <BANLkTikS1NxMxBHwkhiqnrbcEr0c2=D_jw@mail.gmail.com>
Message-ID: <20110606024633.9666.qmail@stuge.se>

Gregg Levine wrote:
> we need to set up a page which states the absolute minimum
> needed for the tools to work to retrieve things.

It's a good idea. I would guess that Git 1.6.6 is the minimum
because of the significantly improved support for HTTP in that
version. It is 28 months old, I think that's OK.

Windows users I recommend to simply get latest msysGit. I'll reply to
the other thread with some tips and tricks.


//Peter



From mbuschman at lucidmachines.com  Mon Jun  6 05:44:36 2011
From: mbuschman at lucidmachines.com (Marshall Buschman)
Date: Sun, 05 Jun 2011 22:44:36 -0500
Subject: [coreboot] Flashrom -V output from E350M1/USB3
Message-ID: <4DEC4D24.3020609@lucidmachines.com>

Here's the output. I have also successfully used flashrom on the E350M1 
vanilla (without usb3).

fastboot ~ # flashrom -V
flashrom v0.9.3-r1205 on Linux 2.6.39-delevi (x86_64), built with libpci 
3.1.7, GCC 4.4.5, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 1 usecs, 797M loops per 
second, 10 myus = 10 us, 100 myus = 103 us,.
Initializing internal programmer
Found candidate at: 00000500-00000510
Found coreboot table at 0x00000500.
Found candidate at: 00000000-000001f8
Found coreboot table at 0x00000000.
coreboot table found at 0xc7ffe000.
coreboot header(24) checksum: 3dea table(504) checksum: 2e62 entries: 14
Vendor ID: ASROCK, part ID: E350M1
DMI string system-manufacturer: ""
DMI string system-product-name: ""
DMI string system-version: ""
DMI string baseboard-manufacturer: ""
DMI string baseboard-product-name: ""
DMI string baseboard-version: ""
DMI string chassis-type: ""
Found chipset "AMD SB700/SB710/SB750", enabling flash write... chipset 
PCI ID is 1002:439d, SPI base address is at 00
AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0
PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1
SpiArbEnable=0, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, 
ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0
NormSpeed is 16.5 MHz
GPIO11 used for SPI_DO
GPIO12 used for SPI_DI
GPIO31 used for SPI_HOLD
GPIO32 used for SPI_CS
GPIO47 used for SPI_CLK
SB700 IMC is not active.
ROM strap override is not active
OK.
This chipset supports the following protocols: LPC,FWH,SPI.
Probing for AMD Am29F010A/B, 128 KB: skipped.
Probing for AMD Am29F002(N)BB, 256 KB: skipped.
Probing for AMD Am29F002(N)BT, 256 KB: skipped.
Probing for AMD Am29F016D, 2048 KB: skipped.
Probing for AMD Am29F040B, 512 KB: skipped.
Probing for AMD Am29F080B, 1024 KB: skipped.
Probing for AMD Am29LV040B, 512 KB: skipped.
Probing for AMD Am29LV081B, 1024 KB: skipped.
Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for AMIC A29002B, 256 KB: skipped.
Probing for AMIC A29002T, 256 KB: skipped.
Probing for AMIC A29040B, 512 KB: skipped.
Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flast
Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT29C512, 64 KB: skipped.
Probing for Atmel AT29C010A, 128 KB: skipped.
Probing for Atmel AT29C020, 256 KB: skipped.
Probing for Atmel AT29C040A, 512 KB: skipped.
Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Atmel AT49BV512, 64 KB: skipped.
Probing for Atmel AT49F020, 256 KB: skipped.
Probing for Atmel AT49F002(N), 256 KB: skipped.
Probing for Atmel AT49F002(N)T, 256 KB: skipped.
Probing for Bright BM29F040, 512 KB: skipped.
Probing for EMST F49B002UA, 256 KB: skipped.
Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for Eon EN29F010, 128 KB: skipped.
Probing for Eon EN29F002(A)(N)B, 256 KB: skipped.
Probing for Eon EN29F002(A)(N)T, 256 KB: skipped.
Probing for Fujitsu MBM29F004BC, 512 KB: skipped.
Probing for Fujitsu MBM29F004TC, 512 KB: skipped.
Probing for Fujitsu MBM29F400BC, 512 KB: skipped.
Probing for Fujitsu MBM29F400TC, 512 KB: skipped.
Probing for Hyundai HY29F002T, 256 KB: skipped.
Probing for Hyundai HY29F002B, 256 KB: skipped.
Probing for Hyundai HY29F040A, 512 KB: skipped.
Probing for Intel 28F001BN/BX-B, 128 KB: skipped.
Probing for Intel 28F001BN/BX-T, 128 KB: skipped.
Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped.
Probing for Intel 28F008S3/S5/SC, 512 KB: skipped.
Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped.
Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped.
Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped.
Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped.
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff, 
id1 parity violation, id1 is normal flash contt
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, 
id1 parity violation, id1 is normal flash cont
Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix MX29F001B, 128 KB: skipped.
Probing for Macronix MX29F001T, 128 KB: skipped.
Probing for Macronix MX29F002B, 256 KB: skipped.
Probing for Macronix MX29F002T, 256 KB: skipped.
Probing for Macronix MX29F040, 512 KB: skipped.
Probing for Macronix MX29LV040, 512 KB: skipped.
Probing for MoselVitelic V29C51000B, 64 KB: skipped.
Probing for MoselVitelic V29C51000T, 64 KB: skipped.
Probing for MoselVitelic V29C51400B, 512 KB: skipped.
Probing for MoselVitelic V29C51400T, 512 KB: skipped.
Probing for MoselVitelic V29LC51000, 64 KB: skipped.
Probing for MoselVitelic V29LC51001, 128 KB: skipped.
Probing for MoselVitelic V29LC51002, 256 KB: skipped.
Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for PMC Pm29F002T, 256 KB: skipped.
Probing for PMC Pm29F002B, 256 KB: skipped.
Probing for PMC Pm39LV010, 128 KB: skipped.
Probing for PMC Pm39LV020, 256 KB: skipped.
Probing for PMC Pm39LV040, 512 KB: skipped.
Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flasht
Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flasht
Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, 
id1 parity violation, id1 is normal flash cot
Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x15
Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x15, id2 0x15
Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x15
Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for SST SST28SF040A, 512 KB: skipped.
Probing for SST SST29EE010, 128 KB: skipped.
Probing for SST SST29LE010, 128 KB: skipped.
Probing for SST SST29EE020A, 256 KB: skipped.
Probing for SST SST29LE020, 256 KB: skipped.
Probing for SST SST39SF512, 64 KB: skipped.
Probing for SST SST39SF010A, 128 KB: skipped.
Probing for SST SST39SF020A, 256 KB: skipped.
Probing for SST SST39SF040, 512 KB: skipped.
Probing for SST SST39VF512, 64 KB: skipped.
Probing for SST SST39VF010, 128 KB: skipped.
Probing for SST SST39VF020, 256 KB: skipped.
Probing for SST SST39VF040, 512 KB: skipped.
Probing for SST SST39VF080, 1024 KB: skipped.
Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal ft
Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal ft
Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal ft
Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xff, id2 0xff, 
id1 parity violation, id1 is normal flash cot
Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flt
Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, 
id1 parity violation, id1 is normal flash ct
Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xfd, id2 0x13, 
id1 is normal flash content, id2 is normal t
Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flast
Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flat
Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flast
Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flat
Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_jet
Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xfd, id2 0x13, 
id1 is normal flash content, id2 is normal t
Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID.
Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID.
Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID.
Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 
0x4016
Probing for ST M29F002B, 256 KB: skipped.
Probing for ST M29F002T/NT, 256 KB: skipped.
Probing for ST M29F040B, 512 KB: skipped.
Probing for ST M29F400BB, 512 KB: skipped.
Probing for ST M29F400BT, 512 KB: skipped.
Probing for ST M29W010B, 128 KB: skipped.
Probing for ST M29W040B, 512 KB: skipped.
Probing for ST M29W512B, 64 KB: skipped.
Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff, 
id1 parity violation, id1 is normal flash contt
Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff, 
id1 parity violation, id1 is normal flash contt
Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, 
id1 parity violation, id1 is normal flash cont
Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, 
id1 parity violation, id1 is normal flash cont
Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff, id1 
parity violation, id1 is normal flash content
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xfd, id2 0x13, id1 
is normal flash content, id2 is normal flast
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 
parity violation, id1 is normal flash content
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 
parity violation, id1 is normal flash contet
Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xfd, id2 0x13, 
id1 is normal flash content, id2 is normal flat
Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped.
Probing for TI TMS29F002RB, 256 KB: skipped.
Probing for TI TMS29F002RT, 256 KB: skipped.
Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Chip status register is 00
Found chip "Winbond W25Q32" (4096 KB, SPI) at physical address 0xffc00000.
Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, 
id2 0x4016
Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped.
Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped.
Probing for Winbond W29C040/P, 512 KB: skipped.
Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped.
Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flt
Probing for Winbond W39V040(F)B, 512 KB: probe_jedec_common: id1 0xff, 
id2 0xff, id1 parity violation, id1 is normalt
Probing for Winbond W39V040(F)C, 512 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probet
Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal ft
Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal ft
Probing for Winbond W49F002U/N, 256 KB: skipped.
Probing for Winbond W49F020, 256 KB: skipped.
Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal flt
Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 
0xff, id1 parity violation, id1 is normal ft
Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing 
information, using default 10mS/40uS. probe_t
Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct 
probe timing information, using default 10mS/4t
Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: 
id1 0xef, id2 0x4016
Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: 
id1 0xef, id2 0x4016
Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Macronix unknown Macronix SPI chip, 0 KB: 
probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 
0xef, id2 0x4016
Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: 
id1 0xef, id2 0x4016
Probing for Generic unknown SPI chip (RDID), 0 KB: 
probe_spi_rdid_generic: id1 0xef, id2 0x4016
Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 
0xef, id2 0x15
No operations were specified.
fastboot ~ #



From peter at stuge.se  Mon Jun  6 05:54:12 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Jun 2011 05:54:12 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <1307306889.1783.36.camel@kubuntu>
References: <1307306889.1783.36.camel@kubuntu>
Message-ID: <20110606035412.26788.qmail@stuge.se>

Patrick Georgi wrote:
> I'm glad to be able to announce that we moved the repository
> infrastructure to git and gerrit, with jenkins as supporting
> facility.

This is exciting!


> the coreboot development workflow changes considerably:
> 
> 1. New SCM
> You will need git, so install it from your usual software
> distribution channels.

For Windows users I would recommend installing the command line tools
in the msysGit package. During installation there is a somewhat
important question about how Git should handle line endings on
Windows.

Git can perform automatic translation between line ending formats, so
that code in the repository will never use anything but LF line
endings, while developers working on Windows will still have every
single file in their working tree use CRLF line endings. This
translation is enabled by the core.autocrlf setting, which is what
the installer will asks for the default value of.

There are many git configuration options. Options can be set either
per user (AKA global) or per repository. Options in a repo override
the global ones. Options are stored in plain text in ~/.gitconfig or
<repodir>/.git/config

You can edit the text files or use the git config command:

git config --global user.name "Peter Stuge"
git config --global user.email peter at stuge.se

The above two lines configure git so that all commits I make will
have my name and email. It's important that you do the same
configuration before you create commits, or they will look really
bad and ultimately end up being rejected.

If you run git config inside a repo dir you can leave out --global to
change settings locally for that repo only.

If you prefer to use a GUI for Git on Windows then I recommend
Git Extensions, which also includes a Visual Studio plugin, so that
you can interact with Git a little more easily directly from the IDE
if you prefer to use Visual Studio.

But allow me to emphasize that it is highly valuable to learn how to
work with Git on the command line. It may feel a little raw, but it
is incredibly efficient, and it very much exposes the concepts of Git
in a clear way, which I must say I have not really seen in any GUI so
far.


> For patch submission a gerrit account is necessary. You can register it
> on http://review.coreboot.org.

Currently registration requires OpenID and might be limited to Google
and Yahoo accounts, but I think this will change tomorrow. (I have
neither, so I can't register. :) We will certainly work something
out.


> 2. New patch submission process
> Develop "as usual" in git, and commit freely.
> When you're ready to submit patches, push them with
>   git push origin HEAD:refs/for/master

HEAD deserves a little discussion.

HEAD is a "meta name" which always refers to the last commit on
whatever branch is currently checked out.

Subversion has revisions, Git has commits. Git commits are identified
by a SHA-1 checksum calculated from the exact contents of the entire
repository. Commit ids can be abbreviated as long as they are unique.


In SVN, revisions are always linear.

In Git, commits can form a directed acyclic graph.
( http://en.wikipedia.org/wiki/Directed_acyclic_graph )

The graph theory is not important, just keep in mind that with Git
also the "parent commit" can be significant. So far, all coreboot
work has been quite linear, and I think it will continue to be mostly
linear, even if Git can handle more complicated situations.

With Git, the branch concept is very important. The actual commits
themselves are really low-level building blocks of a Git repository,
but it is only common to deal with commit ids while doing e.g.
interactive rebase or cherry-picking, which are slightly advanced
tasks compared to development using SVN. (But they are really lovely
features of Git! More later.)

A Git branch is nothing but a nickname pointing to one particular
commit in the repository commit graph. The branch thus also implies a
particular commit history; namely all commits that came before the
one that is the so-called branch HEAD.

Git is distributed, so *everything* is local by default in Git repos.
This goes for commits, branches, tags and everything else. But
everything can also be transferred to other repos easily. git push is
one way, email is another popular way to at least transfer commits
between repositories. Git can send email directly, but thanks to
Gerrit it will not likely be used for coreboot. By using git push to
transfer stuff over to Gerrit, emails will get sent out without
further action from the developer.

So, HEAD in the git push command above refers to the last commit on
the checked out branch.

The checked out branch was branched off the master branch at some
point in time, and maybe there are new commits in master since then.

Unless there is an actual conflict that's no problem. If there is a
conflict, you will eventually have to resolve it. Git may be able to
help, but can not always succeed without help, just like svn.

Instead of HEAD you could thus also type the current branch name.

All commits you have done since the branch was created will be
submitted to Gerrit, for proposed inclusion in the main coreboot
repository master branch.

How and when to create branches is very much a personal thing. I find
that I am a little too lazy to create branches as often as would
actually be practical, so I sometimes have to do a bit of surgery to
move commits around to fix that. :) It is much easier to deal with
too many branches, than it is to deal with too few branches.

Note that there is absolutely no requirement to create branches, but
it can be really really helpful, so it is a good habit to aquire
quickly if you are only just starting to use Git now.

Branches in Git are first class citizens, they are basically nothing
more than a name so they are very fast to deal with.

When you clone the coreboot repository, you will get a local Git
repository, where you can work completely freely. There are no
limitations to what you can do in the local Git repository, so please
feel free to work with it any way you like. You can also have
multiple repository clones, just like with svn, personally I find
this useful sometimes.

After cloning, your local repo only has one branch, called master.

I try to immediately create a branch named according to the
particular task or feature to work on next. This is so that the
master branch always has only commits that come from the main
coreboot repository. ("upstream") Again, I fail at this sometimes and
end up doing work on the master branch. I guess this is mostly a
matter of choice, how you want to work.

If you want to create a branch, you can do it two ways. The first is:

git branch newcoolfeature

This will create a branch called "newcoolfeature" which points to
HEAD. You will stay "on" the current branch. If you make a commit on
the current branch (as opposed to on the just-created branch) then
"newcoolfeature" does not change and still points to the same commit
as before; ie. the second last commit on the current branch.

The other way is:

git checkout -b newcoolfeature [<start_point>]

This does not only create a branch called "newcoolfeature" but it
also does a checkout of that branch, so that you will be "on" the
branch. If you create a commit after this, then newcoolfeature HEAD
will change, and the previous branch will stay unchanged. Sort-of the
opposite of what happened above - because even though a new branch
was created, "git branch" does not change what the current branch is.


Branches or not, you really only require very few commands after
having made a source code change:

git add changedfile.c
git commit

Git is more featureful than SVN, so creating a commit is split into
two steps. git add will let Git know what you want to include in the
commit. You can run git add many times before running git commit. You
can even undo. No commit will be created until you run git commit.
git add adds the changes you have made in the named files into the
"index" AKA "staging area" of the repository. This is a halfway house
before the changes are actually committed. It is possible to add only
some parts of a changed file, using "interactive add" which is
entered by the git add -i command.

Please see git add --help for more information on interactive add.

There exists a shortcut, in case you really truly want to create one
commit with every change that you have made in the source tree:

git commit -a

But I recommend to exercise caution with this command. Always using
git add is another good habit, because it makes you think a little
more about the changes that are about to be committed, which helps
create nicely formatted commits, which helps working with commits
going forward, which saves time.


Before you create a commit, please review the changes you have made,
just like with svn.

The command I like to use for review is git diff. In it's simplest
form, git diff will show all changes in your work tree which have not
yet been added to the index.

Use git diff --cached to instead show *only* the changes that *are*
added to the index; this is what will make up the commit if you would
run git commit.

git diff --cached is the perfect way to review changes before
creating a commit. git status is also helpful to get an overview of
the files that are involved. git status, git diff (with and
without --cached and/or other options) and git branch (without
parameters) are always safe, read-only, operations that can be run at
any point in time, regardless of the repository state, and will
provide helpful information about the repo state.


> If you push a number of commits at once, they're properly linked as
> "dependencies", so people (and tools like gerrit and jenkins) are
> aware about prerequisites.

Pushing a number of commits at once happens when the HEAD that you
push has more than one commit that is not available in the branch
that your push is targeted at. (Normally the master branch of the
main coreboot repo.) So if you have created two commits before you
push, then they will be assumed to depend on each other. If the
commits are not really related then please keep in mind to push one
at a time. Using one branch per related logical change is a good tool
to accomplish this.


> Praise?

Indeed! Thank you so much for the work getting this infrastructure up
and running. I am personally excited to see coreboot start using Git
and I think it will actually help developers a lot once everyone has
gotten up to speed. For example Marshall and I worked on the last
patchset for the E350M1 board exclusively using Git, and it would
have taken us a lot more time and would have been a lot more tedious
work to accomplish what we did without Git.

I think the same is true for much future development, in particular
since we tend to see (and very much prefer!) more patchsets, as
opposed to individual patches, and this fits Git very well.

Git is new for several coreboot developers, while some of us have
been using it for a while already. If you should run into trouble
please get in touch, the very best is to check on IRC, because if
there is a problem there will likely be a couple of commands back
and forth before the problem has been resolved, and email can be
somewhat slow and impractical.


Kind regards

//Peter



From gregg.drwho8 at gmail.com  Mon Jun  6 06:00:59 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Mon, 6 Jun 2011 00:00:59 -0400
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <1307314456.5181.34.camel@mattotaupa>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
	<20110605223205.10281.qmail@stuge.se>
	<BANLkTi=REBJF_d3YV_gSouAHF1kDLPL27A@mail.gmail.com>
	<1307314456.5181.34.camel@mattotaupa>
Message-ID: <BANLkTimWcfDAvGPZR4ni_wAzLNmcZWVU9A@mail.gmail.com>

On Sun, Jun 5, 2011 at 6:54 PM, Paul Menzel
<paulepanter at users.sourceforge.net> wrote:
> Am Sonntag, den 05.06.2011, 18:38 -0400 schrieb Gregg Levine:
>> On Sun, Jun 5, 2011 at 6:32 PM, Peter Stuge <peter at stuge.se> wrote:
>> > Gregg Levine wrote:
>> >> What would prompt this to happen?
>> >> root at jimkirk2:/usr/src/lobos# git clone http://review.coreboot.org/p/coreboot
>> >> Initialized empty Git repository in /usr/src/lobos/coreboot/.git/
>> >> fatal: http://review.coreboot.org/p/coreboot/info/refs download error
>> >> - The requested URL returned error: 403
>> >> root at jimkirk2:/usr/src/lobos#
>> >
>> > I'm not sure why you get this error.
>> >
>> > I can successfully clone using the exact same command.
>> >
>> > I can however also confirm that I get a HTTP 403 error on the URL
>> > shown in the error message. I guess the version of Git that you are
>> > using requests different things from the server than my version.
>> >
>> > I am using version 1.7.4.1 with success. Which version are you using?
>> >
>> > If your Git version is older than 1.6.6 then please upgrade to a
>> > version >= 1.6.6, since that version gained significant performance
>> > improvements specifically when using HTTP.
>
>> Peter the system that everything is hosted on, is wearing version
>> 1.6.1.3 and the test system (same distribution) is wearing 1.7.1.
>
> Is it working for you using Git 1.7.1?
>
> [?]
>
>
> Thanks,
>
> Paul

Hello!
And here we are. I've successfully built the version of git that Peter
and I were discussing both here, and in a separate but related thread.

And then found in my bash history cycle the original problem that
caused this thread. It worked and the problem is gone.

The one question that remains is one of, how do I go about updating a
properly cloned download from a git repository?
-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From lemenkov at gmail.com  Mon Jun  6 05:38:22 2011
From: lemenkov at gmail.com (Peter Lemenkov)
Date: Mon, 6 Jun 2011 07:38:22 +0400
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <1307306889.1783.36.camel@kubuntu>
References: <1307306889.1783.36.camel@kubuntu>
Message-ID: <BANLkTinh6WNjB7pWRaAZV-Xa8BydBf=bSQ@mail.gmail.com>

2011/6/6 Patrick Georgi <patrick at georgi-clan.de>:
> Dear coreboot developers, stakeholders, and enthusiasts,
>
> I'm glad to be able to announce that we moved the repository
> infrastructure to git and gerrit, with jenkins as supporting facility.

That's absolutely great!
Do you plan to switch other projects to new infrastructure as well? I
mean flashrom / superiotool / ectool and others.
-- 
With best regards, Peter Lemenkov.



From patrick at georgi-clan.de  Mon Jun  6 07:01:12 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 06 Jun 2011 07:01:12 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <BANLkTinh6WNjB7pWRaAZV-Xa8BydBf=bSQ@mail.gmail.com>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTinh6WNjB7pWRaAZV-Xa8BydBf=bSQ@mail.gmail.com>
Message-ID: <1307336472.1965.2.camel@kubuntu>

Am Montag, den 06.06.2011, 07:38 +0400 schrieb Peter Lemenkov:
> Do you plan to switch other projects to new infrastructure as well? I
> mean flashrom / superiotool / ectool and others.
superiotool and ectool are part of the coreboot tree, so these are moved
over already.

flashrom is a separate project (with separate repository for a year or
two). They can move if and when they want, but they can just as well
continue to use their current setup. That's up to them and I won't
interfere in that decision.


Patrick




From peter at stuge.se  Mon Jun  6 10:51:46 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Jun 2011 10:51:46 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <BANLkTimWcfDAvGPZR4ni_wAzLNmcZWVU9A@mail.gmail.com>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTikWK+p7J5JEdWfU3piOgNjQ=VjsBg@mail.gmail.com>
	<20110605223205.10281.qmail@stuge.se>
	<BANLkTi=REBJF_d3YV_gSouAHF1kDLPL27A@mail.gmail.com>
	<1307314456.5181.34.camel@mattotaupa>
	<BANLkTimWcfDAvGPZR4ni_wAzLNmcZWVU9A@mail.gmail.com>
Message-ID: <20110606085146.5646.qmail@stuge.se>

Gregg Levine wrote:
> how do I go about updating a properly cloned download from a git
> repository?

I recommend using:

git pull --rebase

git pull first does git fetch, then it does either git merge or
git rebase. Which of the second to use only matters if you have
changes committed to the local master branch. git merge creates a
merge commit to include these changes into the master branch. git
rebase will "unhook" the string of commands that you have made,
update to whatever the latest is on the coreboot.org server, and
finally try to re-apply the string of commits that you had made.
Usually this will be completely automatic, but if there are severe
conflicting changes (your local changes vs. the changes coming from
coreboot.org) then you will have to do manual conflict resolution.


//Peter



From peter at stuge.se  Mon Jun  6 10:52:56 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Jun 2011 10:52:56 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <1307336472.1965.2.camel@kubuntu>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTinh6WNjB7pWRaAZV-Xa8BydBf=bSQ@mail.gmail.com>
	<1307336472.1965.2.camel@kubuntu>
Message-ID: <20110606085256.5998.qmail@stuge.se>

Patrick Georgi wrote:
> superiotool and ectool are part of the coreboot tree, so these are
> moved over already.

We might want to revisit this.


//Peter



From peter at stuge.se  Mon Jun  6 10:53:44 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Jun 2011 10:53:44 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <1307306889.1783.36.camel@kubuntu>
References: <1307306889.1783.36.camel@kubuntu>
Message-ID: <20110606085344.6248.qmail@stuge.se>

Patrick Georgi wrote:
> [3] http://git-scm.com/

I would also like to recommend http://progit.org/ which in spite of
it's name is quite suitable also for those who are just starting to
use Git.


//Peter



From lists at rewt.org.uk  Mon Jun  6 12:17:00 2011
From: lists at rewt.org.uk (Joe Holden)
Date: Mon, 06 Jun 2011 11:17:00 +0100
Subject: [coreboot] ROM build errors
Message-ID: <4DECA91C.7070407@rewt.org.uk>

Hi guys,

I am trying to build a rom with generic defaults for ALIX (although the 
same error appears regardless of mainboard/chipset combination, with the 
exception of QEMU - that doesn't even start to build at all:

*snip*
# configuration written to 
/root/coreboot/payloads/external/SeaBIOS/seabios/.config
#
   Compiling whole program out/ccode.16.s
   Compiling to assembler out/asm-offsets.s
   Generating offset file out/asm-offsets.h
   Compiling (16bit) out/code16.o
   Compiling whole program out/ccode32flat.o
   Compiling whole program out/code32seg.o
   Building ld scripts (version "pre-0.6.2-20110606_111010-pseudobuild26")
Fixed space: 0xe05b-0x10000  total: 8101  slack: 2  Percent slack: 0.0%
16bit size:           39408
32bit segmented size: 2416
32bit flat size:      14016
32bit flat init size: 39600
   Linking out/rom16.o
out/romlayout16.lds:707 cannot move location counter backwards (from 
000000000000ca94 to 000000000000ca78)
make[2]: *** [out/rom16.o] Error 1
make[1]: *** [seabios] Error 2
make: *** [seabios] Error 2
*snip*

I suspect this might be related to the error I get when set to 'master' 
which looks like a binutils bug that was fixed post-packaging, My build 
machines run Slackwre 13.37.0 with binutils before the patch: 
http://sourceware.org/bugzilla/show_bug.cgi?id=12726

Can anyone confim this is actually the problem and it will go away if I 
build a more recent binutils?

Thanks,
J



From peter at stuge.se  Mon Jun  6 12:59:48 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Jun 2011 12:59:48 +0200
Subject: [coreboot] ROM build errors
In-Reply-To: <4DECA91C.7070407@rewt.org.uk>
References: <4DECA91C.7070407@rewt.org.uk>
Message-ID: <20110606105948.6647.qmail@stuge.se>

Hi Joe,

Joe Holden wrote:
> I am trying to build a rom with generic defaults for ALIX (although the 
> same error appears regardless of mainboard/chipset combination,
..

>   Linking out/rom16.o
> out/romlayout16.lds:707 cannot move location counter backwards (from 
> 000000000000ca94 to 000000000000ca78)
..

> Can anyone confim this is actually the problem and it will go away
> if I build a more recent binutils?

The problem is indeed with your toolchain. I strongly recommend that
you run make crossgcc in the top level coreboot source directory,
which will then build a reference toolchain with known working
components. The toolchain should be discovered automatically by the
coreboot and SeaBIOS build systems. You can verify this by cat:ing
the .xcompile file in the root source dir.


//Peter



From patrick at georgi-clan.de  Mon Jun  6 13:32:38 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 06 Jun 2011 13:32:38 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <BANLkTin7KT_=BDOmJyhNGdw9BG_Z9rBfuw@mail.gmail.com>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTin7KT_=BDOmJyhNGdw9BG_Z9rBfuw@mail.gmail.com>
Message-ID: <1307359958.1965.7.camel@kubuntu>

Am Montag, den 06.06.2011, 07:25 -0400 schrieb Leandro Dorileo:
> That sounds great, very good job. Could you move buildrom to gerrit as well?
I'd wait and see until the dust settled over coreboot before considering
any more migrations.


Patrick




From ldorileo at gmail.com  Mon Jun  6 13:35:40 2011
From: ldorileo at gmail.com (Leandro Dorileo)
Date: Mon, 6 Jun 2011 07:35:40 -0400
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <1307359958.1965.7.camel@kubuntu>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTin7KT_=BDOmJyhNGdw9BG_Z9rBfuw@mail.gmail.com>
	<1307359958.1965.7.camel@kubuntu>
Message-ID: <BANLkTimiRKHe8er1fDe0FAoozuM=cAJtDw@mail.gmail.com>

Hi Patrick,

On Mon, Jun 6, 2011 at 7:32 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am Montag, den 06.06.2011, 07:25 -0400 schrieb Leandro Dorileo:
>> That sounds great, very good job. Could you move buildrom to gerrit as well?
> I'd wait and see until the dust settled over coreboot before considering
> any more migrations.

Yeah, seems wise.

Thanks,

-- 
Leandro Dorileo



From ldorileo at gmail.com  Mon Jun  6 13:25:30 2011
From: ldorileo at gmail.com (Leandro Dorileo)
Date: Mon, 6 Jun 2011 07:25:30 -0400
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <1307306889.1783.36.camel@kubuntu>
References: <1307306889.1783.36.camel@kubuntu>
Message-ID: <BANLkTin7KT_=BDOmJyhNGdw9BG_Z9rBfuw@mail.gmail.com>

Hi Patrick


On Sun, Jun 5, 2011 at 4:48 PM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Dear coreboot developers, stakeholders, and enthusiasts,
>
> I'm glad to be able to announce that we moved the repository
> infrastructure to git and gerrit, with jenkins as supporting facility.


That sounds great, very good job. Could you move buildrom to gerrit as well?


Regards,

-- 
Leandro Dorileo



From svn at coreboot.org  Mon Jun  6 16:00:01 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 06 Jun 2011 16:00:01 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1QTaLZ-0006fX-V2@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110606/cefb0e24/attachment.html>

From marcj303 at gmail.com  Mon Jun  6 18:33:46 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 6 Jun 2011 10:33:46 -0600
Subject: [coreboot] [PATCH] AMD F14 persimmon and e350m1: use standard
 pci config functions
In-Reply-To: <FD374380643E4C25ABEED4F16D04F49D@asusp67>
References: <AcwjU6hoIMCh+JMuRwCnv0M2H/UCwg==>
	<FD374380643E4C25ABEED4F16D04F49D@asusp67>
Message-ID: <BANLkTinj0-JrQyqrRr4rMHet1EWhChnPmA@mail.gmail.com>

On Sun, Jun 5, 2011 at 1:39 AM, Scott Duplichan <scott at notabs.org> wrote:
> AMD F14 persimmon and e350m1: replace inline cf8/cfc pci config
> access with pci_read_config and pci_write_config function calls.
>
> Signed-off-by: Scott Duplichan <scott at notabs.org>
>
> Index: src/mainboard/amd/persimmon/romstage.c
> ===================================================================
> --- src/mainboard/amd/persimmon/romstage.c ? ? ?(revision 6637)
> +++ src/mainboard/amd/persimmon/romstage.c ? ? ?(working copy)
> @@ -73,21 +73,20 @@
> ? // early enable of PrefetchEnSPIFromHost
> ? if (boot_cpu())
> ? ? {
> - ? ?__outdword (0xcf8, 0x8000a3b8);
> - ? ?__outdword (0xcfc, __indword (0xcfc) | 1 << 24);
> + ? ?device_t dev = PCI_DEV(0, 0x14, 3);
> + ? ?pci_write_config8(dev, 0xbb, pci_read_config8(dev, 0xbb) | 1);
> ? ? }
>
> ? // early enable of SPI 33 MHz fast mode read
> ? if (boot_cpu())
> ? ? {
> ? ? volatile u32 *spiBase = (void *) 0xa0000000;
> - ? ?u32 save;
> - ? ?__outdword (0xcf8, 0x8000a3a0);
> - ? ?save = __indword (0xcfc);
> - ? ?__outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
> + ? ?device_t dev = PCI_DEV(0, 0x14, 3);
> + ? ?u32 save = pci_read_config32(dev, 0xa0);
> + ? ?pci_write_config32(dev, 0xa0, (u32)spiBase | 2); // set temp MMIO base
> ? ? spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
> ? ? spiBase [0] |= 1 << 18; // fast read enable
> - ? ?__outdword (0xcfc, save); // clear temp base
> + ? ?pci_write_config32(dev, 0xa0, save);
> ? ? }
>
> ? if (!cpu_init_detectedx && boot_cpu()) {
> Index: src/mainboard/asrock/e350m1/romstage.c
> ===================================================================
> --- src/mainboard/asrock/e350m1/romstage.c ? ? ?(revision 6637)
> +++ src/mainboard/asrock/e350m1/romstage.c ? ? ?(working copy)
> @@ -58,21 +58,20 @@
> ? // early enable of PrefetchEnSPIFromHost
> ? if (boot_cpu())
> ? ? {
> - ? ?__outdword (0xcf8, 0x8000a3b8);
> - ? ?__outdword (0xcfc, __indword (0xcfc) | 1 << 24);
> + ? ?device_t dev = PCI_DEV(0, 0x14, 3);
> + ? ?pci_write_config8(dev, 0xbb, pci_read_config8(dev, 0xbb) | 1);
> ? ? }
>
> ? // early enable of SPI 33 MHz fast mode read
> ? if (boot_cpu())
> ? ? {
> ? ? volatile u32 *spiBase = (void *) 0xa0000000;
> - ? ?u32 save;
> - ? ?__outdword (0xcf8, 0x8000a3a0);
> - ? ?save = __indword (0xcfc);
> - ? ?__outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
> + ? ?device_t dev = PCI_DEV(0, 0x14, 3);
> + ? ?u32 save = pci_read_config32(dev, 0xa0);
> + ? ?pci_write_config32(dev, 0xa0, (u32)spiBase | 2); // set temp MMIO base
> ? ? spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
> ? ? spiBase [0] |= 1 << 18; // fast read enable
> - ? ?__outdword (0xcfc, save); // clear temp base
> + ? ?pci_write_config32(dev, 0xa0, save);
> ? ? }
>
> ? if (!cpu_init_detectedx && boot_cpu()) {
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>


Acked-by:  Marc Jones <marcj303 at gmail.com>



-- 
http://se-eng.com



From marcj303 at gmail.com  Mon Jun  6 18:49:17 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 6 Jun 2011 10:49:17 -0600
Subject: [coreboot] SB800/RS880 docs
In-Reply-To: <4DEB4BD0.6020306@icyb.net.ua>
References: <4DEB4BD0.6020306@icyb.net.ua>
Message-ID: <BANLkTik=85uwrXz308oVohMX1O=Dfhug8A@mail.gmail.com>

Updated.

Thanks,
Marc


On Sun, Jun 5, 2011 at 3:26 AM, Andriy Gapon <avg at icyb.net.ua> wrote:
>
> Looks like the docs page http://www.coreboot.org/Datasheets#AMD_4 can be updated:
>
> http://support.amd.com/us/psearch/Pages/psearch.aspx?type=2.2%3B2.3&product=2.7.4.3.5.3.2&contentType=Tech+Doc+Embedded&ostype=&keywords=&items=20
>
> --
> Andriy Gapon
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



-- 
http://se-eng.com



From avg at icyb.net.ua  Mon Jun  6 18:54:16 2011
From: avg at icyb.net.ua (Andriy Gapon)
Date: Mon, 06 Jun 2011 19:54:16 +0300
Subject: [coreboot] SB800/RS880 docs
In-Reply-To: <BANLkTik=85uwrXz308oVohMX1O=Dfhug8A@mail.gmail.com>
References: <4DEB4BD0.6020306@icyb.net.ua>
	<BANLkTik=85uwrXz308oVohMX1O=Dfhug8A@mail.gmail.com>
Message-ID: <4DED0638.10907@icyb.net.ua>

on 06/06/2011 19:49 Marc Jones said the following:
> Updated.

Thank you.  That page is a very convenient place to get links to the specs.
BTW, looks like SB800 BDG was missed:
support.amd.com/us/Embedded_TechDocs/45483.pdf


> On Sun, Jun 5, 2011 at 3:26 AM, Andriy Gapon <avg at icyb.net.ua> wrote:
>>
>> Looks like the docs page http://www.coreboot.org/Datasheets#AMD_4 can be updated:
>>
>> http://support.amd.com/us/psearch/Pages/psearch.aspx?type=2.2%3B2.3&product=2.7.4.3.5.3.2&contentType=Tech+Doc+Embedded&ostype=&keywords=&items=20
>>
>> --
>> Andriy Gapon
>>
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
> 
> 
> 


-- 
Andriy Gapon



From Frank.Vibrans at amd.com  Mon Jun  6 21:47:15 2011
From: Frank.Vibrans at amd.com (Vibrans, Frank)
Date: Mon, 6 Jun 2011 14:47:15 -0500
Subject: [coreboot] [ANN] New code repository and development workflow
Message-ID: <276EC11373289744A112A8FE6675506702B513EE3F@SAUSEXMBP01.amd.com>

Hi All,

I'm a bit unhappy about the move to git because I was able to get the coreboot tree hooked up into our SVN as an external so we would always have the latest by simply doing an SVN update.  I'm afraid I won't be able to convince the rest of AMD to move to git just to make my life easier.

Does anybody know of a way or have a script to get SVN to run git for me?  All I need is the equivalent of SVN checkout and update.  Thanks,

FrankV

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From patrick at georgi-clan.de  Mon Jun  6 22:17:33 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 06 Jun 2011 22:17:33 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <276EC11373289744A112A8FE6675506702B513EE3F@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE6675506702B513EE3F@SAUSEXMBP01.amd.com>
Message-ID: <1307391453.9425.6.camel@kubuntu>

Am Montag, den 06.06.2011, 14:47 -0500 schrieb Vibrans, Frank:
> Does anybody know of a way or have a script to get SVN to run git for
> me?  All I need is the equivalent of SVN checkout and update.  Thanks,
git-svn provides a bidirectional gateway, and we used it to provide the
read-only git repository so far (ie. the other direction).

You could create a local SVN repository and convert the git repository
into it (cronjob or similar).


Patrick





From vikram186 at gmail.com  Mon Jun  6 22:14:42 2011
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Tue, 7 Jun 2011 01:44:42 +0530
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <276EC11373289744A112A8FE6675506702B513EE3F@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE6675506702B513EE3F@SAUSEXMBP01.amd.com>
Message-ID: <BANLkTi=rGL0OwiDD1Wo4o0GNRxUatgLp+g@mail.gmail.com>

Hi Frank,

On Tue, Jun 7, 2011 at 1:17 AM, Vibrans, Frank <Frank.Vibrans at amd.com> wrote:
>
> Hi All,
>
>
>
> I?m a bit unhappy about the move to git because I was able to get the coreboot tree hooked up into our SVN as an external so we would always have the latest by simply doing an SVN update.? I?m afraid I won?t be able to convince the rest of AMD to move to git just to make my life easier.
>
>
>
> Does anybody know of a way or have a script to get SVN to run git for me?? All I need is the equivalent of SVN checkout and update.? Thanks,

This may help you.
http://git.or.cz/course/svn.html
http://people.gnome.org/~newren/eg/git-for-svn-users.html

-
Thanks,
Vikram



From thomas at gstaedtner.net  Mon Jun  6 22:18:52 2011
From: thomas at gstaedtner.net (=?UTF-8?Q?Thomas_Gst=C3=A4dtner?=)
Date: Mon, 6 Jun 2011 22:18:52 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <276EC11373289744A112A8FE6675506702B513EE3F@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE6675506702B513EE3F@SAUSEXMBP01.amd.com>
Message-ID: <BANLkTi=Z3CScs-=XJUVcpAP9fK9Ri-Jc3w@mail.gmail.com>

On Mon, Jun 6, 2011 at 21:47, Vibrans, Frank <Frank.Vibrans at amd.com> wrote:
> Hi All,
>
>
>
> I?m a bit unhappy about the move to git because I was able to get the
> coreboot tree hooked up into our SVN as an external so we would always have
> the latest by simply doing an SVN update.? I?m afraid I won?t be able to
> convince the rest of AMD to move to git just to make my life easier.
>
>
>
> Does anybody know of a way or have a script to get SVN to run git for me?
> All I need is the equivalent of SVN checkout and update.? Thanks,
>
>
>
> FrankV
>
>

Usually it's used the other way around (i.e. use git to commit to a
upstream svn repo), but nevertheless, git has strong svn support, as
documented here:
http://www.kernel.org/pub/software/scm/git/docs/git-svn.html

The equivalent of 'svn co' would be 'git svn clone', the equivalent to
'svn up' would be 'git svn rebase'.
As you can see, updating is slightly less trivial because git works
very differently, but generally it should work fine.

Anyway, convincing the rest of AMD would probably be more fun :P
I understand that a lot of people hesitate to switch to git because it
seems so complex and powerful - but the regular workflow is very
simple and very very easy to learn.



From peter at stuge.se  Mon Jun  6 22:41:11 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Jun 2011 22:41:11 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <276EC11373289744A112A8FE6675506702B513EE3F@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE6675506702B513EE3F@SAUSEXMBP01.amd.com>
Message-ID: <20110606204111.26011.qmail@stuge.se>

Vibrans, Frank wrote:
> Does anybody know of a way or have a script to get SVN to run git
> for me?

http://stackoverflow.com/questions/3662114/rw-access-git-repository-using-svn-git-svnserver

This looks like the right thing:

http://git.q42.co.uk/git_svn_server.git


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Mon Jun  6 22:39:04 2011
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 06 Jun 2011 22:39:04 +0200
Subject: [coreboot] Fwd:  Fonts at the Bios
In-Reply-To: <BANLkTimd_DOzNFtCfgT0=m3KD9NpQONr_g@mail.gmail.com>
References: <BANLkTi=iLbx3U3xbnp=v6WGHTBehneOo_g@mail.gmail.com>	<4DEADC51.20608@coreboot.org>	<BANLkTikFvUvoTWSWg2hr_Vv3N+1EB8brMg@mail.gmail.com>
	<BANLkTimd_DOzNFtCfgT0=m3KD9NpQONr_g@mail.gmail.com>
Message-ID: <4DED3AE8.8050105@gmx.net>

Am 05.06.2011 12:49 schrieb dove - railing:
> Could not http://www.flashrom.org/Flashrom utility be an opensource
> utility for Video card / VGA Bios?

What are you trying to do?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From kevin at koconnor.net  Tue Jun  7 02:14:28 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Mon, 6 Jun 2011 20:14:28 -0400
Subject: [coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <6CE9EBB920384B8282C963F06BE71CC1@asusp67>
References: <E1QSt2H-0007bq-WC@ra.coresystems.de>
	<20110604161605.GC15898@coreboot.org>
	<6CE9EBB920384B8282C963F06BE71CC1@asusp67>
Message-ID: <20110607001428.GA26066@morn.localdomain>

On Sun, Jun 05, 2011 at 02:39:22AM -0500, Scott Duplichan wrote:
> Stefan Reinauer wrote:
> ]Also, enabling Prefetch and 33MHz fast read mode should possibly go in the
> ]southbridge's bootblock.c so the first cbfs scan does not run with the
> ]slow settings.
[...]
> Together the changes save 7 ms. The question is, where do we draw the line
> on boot time reduction? I worked in a group a while back where a manager
> said, "every millisecond counts". This was due to a desire to make a
> customer's board boot more quickly than a board from a competitor. Certainly
> no user can notice a boot time difference of a few ms. The difference is
> easy to measure though, and in some cases a few ms is enough to affect who
> calls their board fastest. On the other hand, coreboot+seabios is already
> several thousand ms faster than UEFI, so maybe saving 7 ms is not worth the
> somewhat out of place code.

I agree that no one would notice 7ms on it's own.  However, a handful
of 7ms improvements can be noticed.

I think of the bootblock as the place to fully map the flash device.
So, why would it be out of place to enable the faster flash accesses
in the bootblock?

-Kevin



From gerrit at coreboot.org  Mon Jun  6 16:21:00 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 06 Jun 2011 16:21:00 +0200
Subject: [coreboot] New patch to review: 9069251 SMM: add
	mainboard_apm_cnt() callback
Message-ID: <E1QTafs-0000cx-6n@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/3.

You will also find it attached for your convenience.

Regards,
gerrit
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From ataya65 at googlemail.com  Sat Jun  4 12:21:55 2011
From: ataya65 at googlemail.com (Omar-Mohammad Ataya)
Date: Sat, 4 Jun 2011 12:21:55 +0200
Subject: [coreboot] GIGABYTE GA-890GPA-UD3H seems to have the right rom chip
 to flash, but compiling cooreboot v4 fails
Message-ID: <BANLkTikU1ZjjO8UZ7kRezfzMd6woWwQTjw@mail.gmail.com>

flashrom v0.9.3-r1299 on Linux 2.6.38.6-27.fc15.x86_64 (x86_64), built with
libpci 3.1.7, GCC 4.6.0 20110428 (Red Hat 4.6.0-6), little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 1 usecs, 1003M loops per
second, 10 myus = 10 us, 100 myus = 106 us, 1000 myus = 1006 us, 10000 myus
= 10014 us, 4 myus = 5 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "Gigabyte Technology Co., Ltd."
DMI string system-product-name: "GA-890GPA-UD3H"
DMI string system-version: " "
DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd."
DMI string baseboard-product-name: "GA-890GPA-UD3H"
DMI string baseboard-version: "x.x"
DMI string chassis-type: "Desktop"
Found ITE Super I/O, ID 0x8720 on port 0x2e
Found chipset "AMD SB700/SB710/SB750/SB850", enabling flash write... chipset
PCI ID is 1002:439d, SPI base address is at 0xfec10000
AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0
PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1
SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=7,
SpiBridgeDisable=1, DropOneClkOnRd=0
NormSpeed is 16.5 MHz
GPIO11 used for SPI_DO
GPIO12 used for SPI_DI
GPIO31 used for SPI_HOLD
GPIO32 used for SPI_CS
GPIO47 used for SPI_CLK
SB700 IMC is not active.
ROM strap override is not active
OK.
This chipset supports the following protocols: LPC,FWH,SPI.
No IT87* serial flash segment enabled.
Probing for AMD Am29F010A/B, 128 KB: skipped.
Probing for AMD Am29F002(N)BB, 256 KB: skipped.
Probing for AMD Am29F002(N)BT, 256 KB: skipped.
Probing for AMD Am29F016D, 2048 KB: skipped.
Probing for AMD Am29F040B, 512 KB: skipped.
Probing for AMD Am29F080B, 1024 KB: skipped.
Probing for AMD Am29LV001BB, 128 KB: skipped.
Probing for AMD Am29LV001BT, 128 KB: skipped.
Probing for AMD Am29LV002BB, 256 KB: skipped.
Probing for AMD Am29LV002BT, 256 KB: skipped.
Probing for AMD Am29LV004BB, 512 KB: skipped.
Probing for AMD Am29LV004BT, 512 KB: skipped.
Probing for AMD Am29LV008BB, 1024 KB: skipped.
Probing for AMD Am29LV008BT, 1024 KB: skipped.
Probing for AMD Am29LV040B, 512 KB: skipped.
Probing for AMD Am29LV081B, 1024 KB: skipped.
Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for AMIC A29002B, 256 KB: skipped.
Probing for AMIC A29002T, 256 KB: skipped.
Probing for AMIC A29040B, 512 KB: skipped.
Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x16, id2 0x83,
id1 is normal flash content, id2 is normal flash content
Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT29C512, 64 KB: skipped.
Probing for Atmel AT29C010A, 128 KB: skipped.
Probing for Atmel AT29C020, 256 KB: skipped.
Probing for Atmel AT29C040A, 512 KB: skipped.
Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Atmel AT49BV512, 64 KB: skipped.
Probing for Atmel AT49F020, 256 KB: skipped.
Probing for Atmel AT49F002(N), 256 KB: skipped.
Probing for Atmel AT49F002(N)T, 256 KB: skipped.
Probing for Bright BM29F040, 512 KB: skipped.
Probing for EMST F49B002UA, 256 KB: skipped.
Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Eon EN29F010, 128 KB: skipped.
Probing for Eon EN29F002(A)(N)B, 256 KB: skipped.
Probing for Eon EN29F002(A)(N)T, 256 KB: skipped.
Probing for Fujitsu MBM29F004BC, 512 KB: skipped.
Probing for Fujitsu MBM29F004TC, 512 KB: skipped.
Probing for Fujitsu MBM29F400BC, 512 KB: skipped.
Probing for Fujitsu MBM29F400TC, 512 KB: skipped.
Probing for Hyundai HY29F002T, 256 KB: skipped.
Probing for Hyundai HY29F002B, 256 KB: skipped.
Probing for Hyundai HY29F040A, 512 KB: skipped.
Probing for Intel 28F001BN/BX-B, 128 KB: skipped.
Probing for Intel 28F001BN/BX-T, 128 KB: skipped.
Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped.
Probing for Intel 28F008S3/S5/SC, 512 KB: skipped.
Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped.
Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped.
Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped.
Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped.
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x16, id2 0x83, id1 is
normal flash content, id2 is normal flash content
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x24, id2 0x41, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Chip status register is 00
Chip status register: Status Register Write Disable (SRWD) is not set
Chip status register: Bit 6 is not set
Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address
0xfff00000.
Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Macronix MX29F001B, 128 KB: skipped.
Probing for Macronix MX29F001T, 128 KB: skipped.
Probing for Macronix MX29F002B, 256 KB: skipped.
Probing for Macronix MX29F002T, 256 KB: skipped.
Probing for Macronix MX29F040, 512 KB: skipped.
Probing for Macronix MX29LV040, 512 KB: skipped.
Probing for MoselVitelic V29C51000B, 64 KB: skipped.
Probing for MoselVitelic V29C51000T, 64 KB: skipped.
Probing for MoselVitelic V29C51400B, 512 KB: skipped.
Probing for MoselVitelic V29C51400T, 512 KB: skipped.
Probing for MoselVitelic V29LC51000, 64 KB: skipped.
Probing for MoselVitelic V29LC51001, 128 KB: skipped.
Probing for MoselVitelic V29LC51002, 256 KB: skipped.
Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for PMC Pm29F002T, 256 KB: skipped.
Probing for PMC Pm29F002B, 256 KB: skipped.
Probing for PMC Pm39LV010, 128 KB: skipped.
Probing for PMC Pm39LV020, 256 KB: skipped.
Probing for PMC Pm39LV040, 512 KB: skipped.
Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xde, id2 0xb9,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x16, id2 0x83,
id1 is normal flash content, id2 is normal flash content
Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0x24, id2 0x41, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Spansion S25FL004A, 512 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Spansion S25FL032A, 4096 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Spansion S25FL064A, 8192 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for SST SST25VF010.REMS, 128 KB: probe_spi_rems: id1 0xc2, id2 0x13
Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13
Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13
Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13
Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for SST SST28SF040A, 512 KB: skipped.
Probing for SST SST29EE010, 128 KB: skipped.
Probing for SST SST29LE010, 128 KB: skipped.
Probing for SST SST29EE020A, 256 KB: skipped.
Probing for SST SST29LE020, 256 KB: skipped.
Probing for SST SST39SF512, 64 KB: skipped.
Probing for SST SST39SF010A, 128 KB: skipped.
Probing for SST SST39SF020A, 256 KB: skipped.
Probing for SST SST39SF040, 512 KB: skipped.
Probing for SST SST39VF512, 64 KB: skipped.
Probing for SST SST39VF010, 128 KB: skipped.
Probing for SST SST39VF020, 256 KB: skipped.
Probing for SST SST39VF040, 512 KB: skipped.
Probing for SST SST39VF080, 1024 KB: skipped.
Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xde, id2
0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x08, id2
0x4b, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x16, id2
0x83, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x16, id2 0x83, id1
is normal flash content, id2 is normal flash content
Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0x24, id2
0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0x24, id2 0x41, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0x24, id2 0x41, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xde, id2 0xb9,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xde, id2 0xb9,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x16, id2 0x83,
id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x16, id2 0x83,
id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec_common: id1 0x24, id2
0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0x24, id2 0x41, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID.
Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID.
Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID.
Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for ST M25PX16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for ST M29F002B, 256 KB: skipped.
Probing for ST M29F002T/NT, 256 KB: skipped.
Probing for ST M29F040B, 512 KB: skipped.
Probing for ST M29F400BB, 512 KB: skipped.
Probing for ST M29F400BT, 512 KB: skipped.
Probing for ST M29W010B, 128 KB: skipped.
Probing for ST M29W040B, 512 KB: skipped.
Probing for ST M29W512B, 64 KB: skipped.
Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x16, id2 0x83, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x16, id2 0x83, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x24, id2 0x41, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x24, id2 0x41, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xde, id2 0xb9, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0x24, id2 0x41, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x16, id2 0x83, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x24, id2 0x41, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0x24, id2 0x41, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped.
Probing for TI TMS29F002RB, 256 KB: skipped.
Probing for TI TMS29F002RT, 256 KB: skipped.
Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2
0x2014
Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped.
Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped.
Probing for Winbond W29C040/P, 512 KB: skipped.
Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped.
Probing for Winbond W39L040, 512 KB: skipped.
Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x16, id2
0x83, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x16, id2
0x83, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040C, 512 KB: probe_jedec_common: id1 0x16, id2
0x83, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x16, id2
0x83, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FB, 512 KB: probe_jedec_common: id1 0x16, id2
0x83, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FC, 512 KB: probe_jedec_common: id1 0x16, id2
0x83, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0x24, id2
0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W49F002U/N, 256 KB: skipped.
Probing for Winbond W49F020, 256 KB: skipped.
Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xde, id2
0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xde, id2
0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W39V080FA, 1024 KB: probe_jedec_common: id1 0x24, id2
0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W39V080FA (dual mode), 512 KB: probe_jedec_common: id1
0x16, id2 0x83, id1 is normal flash content, id2 is normal flash content
Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xc2, id2 0x2014
Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xc2, id2 0x2014
Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xc2, id2 0x2014
Probing for Macronix unknown Macronix SPI chip, 0 KB:
probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xc2, id2 0x2014
Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xc2, id2 0x2014
Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2,
id2 0x2014
Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xc2, id2 0x2014
Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic:
id1 0xc2, id2 0x2014
Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xc2,
id2 0x13
===
This flash part has status UNTESTED for operations: WRITE
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From ataya65 at googlemail.com  Sat Jun  4 14:30:28 2011
From: ataya65 at googlemail.com (Omar-Mohammad Ataya)
Date: Sat, 4 Jun 2011 14:30:28 +0200
Subject: [coreboot] Builduing coreboot for Gigabyte GA-890GPA-UD3H always
 fails with this message (using Fedora 15 x86_64 and the Option SeaBios as
 loader)
Message-ID: <BANLkTikG4N1_DzqnQAEApk0PrWFNs2U5CQ@mail.gmail.com>

HOSTCC     util/romcc/romcc (this may take a while)
/home/omar/coreboot/util/romcc/romcc.c: In Funktion ?raw_next_token?:
/home/omar/coreboot/util/romcc/romcc.c:4083:7: Warnung: Variable ?wchar?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c:4116:7: Warnung: Variable ?wchar?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion ?pp_token?:
/home/omar/coreboot/util/romcc/romcc.c:4900:21: Warnung: Variable ?file?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion ?write_expr?:
/home/omar/coreboot/util/romcc/romcc.c:7512:6: Warnung: Variable ?op?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion
?decompose_compound_types?:
/home/omar/coreboot/util/romcc/romcc.c:9171:8: Warnung: Variable ?fp?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion
?register_builtin_function?:
/home/omar/coreboot/util/romcc/romcc.c:10465:45: Warnung: Variable ?last?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c:10465:23: Warnung: Variable ?arg?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion ?function_definition?:
/home/omar/coreboot/util/romcc/romcc.c:13312:52: Warnung: Variable ?result?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion ?expand_function_call?:
/home/omar/coreboot/util/romcc/romcc.c:14330:38: Warnung: Variable ?ret_set?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c:14329:17: Warnung: Variable ?jmp?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion ?join_functions?:
/home/omar/coreboot/util/romcc/romcc.c:14748:17: Warnung: Variable ?jmp?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion
?eliminate_inefectual_code?:
/home/omar/coreboot/util/romcc/romcc.c:17917:25: Warnung: Variable ?final?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c:17914:16: Warnung: Variable ?block?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion
?print_interference_block?:
/home/omar/coreboot/util/romcc/romcc.c:18296:7: Warnung: Variable ?op?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion ?allocate_registers?:
/home/omar/coreboot/util/romcc/romcc.c:20088:7: Warnung: Variable
?conflicts? gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion ?mod_div?:
/home/omar/coreboot/util/romcc/romcc.c:23189:23: Warnung: Variable ?piece0?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
/home/omar/coreboot/util/romcc/romcc.c: In Funktion ?print_op_move?:
/home/omar/coreboot/util/romcc/romcc.c:24396:7: Warnung: Variable ?bits?
gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
    HOSTCC     util/options/build_opt_tbl
    OPTION     option_table.h
    ROMCC      mainboard/emulation/qemu-x86/bootblock.inc
    GEN        bootblock/bootblock.S
    CC         mainboard/emulation/qemu-x86/bootblock.s
    CC         mainboard/emulation/qemu-x86/bootblock.o
    GEN        bootblock/ldscript.ld
    LINK       bootblock.elf
/usr/bin/ld: address 0x242 of build/bootblock.elf section `.rom' is not
within region `rom'
/usr/bin/ld: address 0x242 of build/bootblock.elf section `.rom' is not
within region `rom'
/usr/bin/ld: address 0x242 of build/bootblock.elf section `.rom' is not
within region `rom'
/usr/bin/ld: _start too low. Please report.
collect2: ld gab 1 als Ende-Status zur?ck
make: *** [build/bootblock.elf] Fehler 1
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From gerrit at coreboot.org  Mon Jun  6 17:13:51 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 6 Jun 2011 17:13:51 +0200
Subject: [coreboot] Patch merged into master: 2b72f48 Teach abuild to emit
	JUnit formatted build reports
Message-ID: <E1QTbV1-0002By-4A@ra.coresystems.de>

Dear list,

the following patch was just integrated into master.

commit 2b72f48fe21445397c81734c8564ad1a6c87aa24
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Fri Jun 3 21:56:13 2011 +0200

    Teach abuild to emit JUnit formatted build reports
    
    Jenkins can produce reports from JUnit test cases, so we fake testcases
    for each board.
    
    Change-Id: I34d46d15c83f4f04d2228f302eb626b261ac098d

Regards,
gerrit



From gerrit at coreboot.org  Mon Jun  6 17:21:17 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 06 Jun 2011 17:21:17 +0200
Subject: [coreboot] New patch to review: 74565c7 SMM: add
	mainboard_apm_cnt() callback
Message-ID: <E1QTbcD-0003A3-3C@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/3.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Mon Jun  6 17:56:14 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 6 Jun 2011 17:56:14 +0200
Subject: [coreboot] Patch merged into master: 74565c7 SMM: add
	mainboard_apm_cnt() callback
Message-ID: <E1QTcA2-00042M-7e@ra.coresystems.de>

Dear list,

the following patch was just integrated into master.

commit 74565c76e1d52c03627ad12900dbe551a311e18d
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sat Jun 4 19:35:22 2011 +0200

    SMM: add mainboard_apm_cnt() callback
    
    motherboards can use this hook to get notified if someone writes
    to the APM_CNT port (0xb2). If the hook returns 1, the chipset
    specific hook is also skipped.
    
    Change-Id: I05f1a27cebf9d25db8064f2adfd2a0f5759e48b5
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Regards,
gerrit



From gerrit at coreboot.org  Mon Jun  6 18:42:05 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 06 Jun 2011 18:42:05 +0200
Subject: [coreboot] New patch to review: 7e340ba SMM: add defines for
	APM_CNT register
Message-ID: <E1QTcsP-0005zc-Oj@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Mon Jun  6 18:43:34 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 06 Jun 2011 18:43:34 +0200
Subject: [coreboot] New patch to review: 7effe01 T60: fix touchpad option
Message-ID: <E1QTctq-0000BN-2F@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Mon Jun  6 18:47:43 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 06 Jun 2011 18:47:43 +0200
Subject: [coreboot] New patch to review: 3e4460c T60/PMH7: move 'touchpad'
	option to pmh7
Message-ID: <E1QTcxr-0001Ls-7l@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/6.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Mon Jun  6 18:49:23 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 06 Jun 2011 18:49:23 +0200
Subject: [coreboot] New patch to review: 5269a2d i82801gx: enable ACPI
	during S3 resume
Message-ID: <E1QTczT-00046J-IY@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Mon Jun  6 18:57:33 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 06 Jun 2011 18:57:33 +0200
Subject: [coreboot] New patch to review: f641e32 i82801gx: enable ACPI
	during S3 resume
Message-ID: <E1QTd7N-0004bG-Dv@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Mon Jun  6 18:58:53 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 06 Jun 2011 18:58:53 +0200
Subject: [coreboot] New patch to review: a17084b T60: fix touchpad option
Message-ID: <E1QTd8f-0007dO-Hi@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Mon Jun  6 18:58:54 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 06 Jun 2011 18:58:54 +0200
Subject: [coreboot] New patch to review: ab75145 T60/PMH7: move 'touchpad'
	option to pmh7
Message-ID: <E1QTd8g-0007eq-Hi@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/6.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Mon Jun  6 20:50:11 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 06 Jun 2011 20:50:11 +0200
Subject: [coreboot] New patch to review: c5f56ab i82801gx: enable ACPI
	during S3 resume
Message-ID: <E1QTesN-00015B-4s@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7.

You will also find it attached for your convenience.

Regards,
gerrit
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From scott at notabs.org  Tue Jun  7 03:41:52 2011
From: scott at notabs.org (Scott Duplichan)
Date: Mon, 6 Jun 2011 20:41:52 -0500
Subject: [coreboot] Builduing coreboot for Gigabyte GA-890GPA-UD3H
	always fails with this message (using Fedora 15 x86_64 and
	the Option SeaBios as loader)
In-Reply-To: <BANLkTikG4N1_DzqnQAEApk0PrWFNs2U5CQ@mail.gmail.com>
References: <BANLkTikG4N1_DzqnQAEApk0PrWFNs2U5CQ@mail.gmail.com>
Message-ID: <1A4937EB16374A34BAE947C8F66378C4@asusp67>

Omar-Mohammad Ataya wrote:

]HOSTCC???? util/romcc/romcc (this may take a while)
]/home/omar/coreboot/util/romcc/romcc.c: In Funktion ?raw_next_token?:
]/home/omar/coreboot/util/romcc/romcc.c:4083:7: Warnung: Variable ?wchar?
]gesetzt, aber nicht verwendet [-Wunused-but-set-variable]

Hello Omar,

>From the error messages, it looks like you are using gcc 4.6.0, and
possibly the wrong binutils. The current coreboot code is most often
compiled using gcc 4.5.2. The best way to ensure no build tool
related problems is build a cross compile tool set using
coreboot/util/crossgcc/buildgcc.

Thanks,
Scott




From gerrit at coreboot.org  Tue Jun  7 03:28:42 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 03:28:42 +0200
Subject: [coreboot] New patch to review: dc85f7a re-indent,
	so files conform to coding guidelines.
Message-ID: <E1QTl62-0005R3-HV@ra.coresystems.de>

Dear list,

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/8.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Tue Jun  7 03:28:43 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 03:28:43 +0200
Subject: [coreboot] New patch to review: 53c4a1a sb800: move spi prefetch
	and fast read mode to sb bootblock.
Message-ID: <E1QTl63-0005Rz-0N@ra.coresystems.de>

Dear list,

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/9.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Tue Jun  7 03:36:41 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 03:36:41 +0200
Subject: [coreboot] New patch to review: e814e70 sb800: move spi prefetch
	and fast read mode to sb bootblock.
Message-ID: <E1QTlDl-0006TR-6x@ra.coresystems.de>

Dear list,

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/9.

You will also find it attached for your convenience.

Regards,
gerrit
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From mbuschman at lucidmachines.com  Tue Jun  7 05:26:44 2011
From: mbuschman at lucidmachines.com (Marshall Buschman)
Date: Mon, 06 Jun 2011 22:26:44 -0500
Subject: [coreboot] [PATCH] ASRock E350M1 update
In-Reply-To: <BANLkTin9M-U1rzd6p+B8PNie4nbq0WAAXA@mail.gmail.com>
References: <AcwWs82EUmmnvWnoR+OZ3akIgcBH+g==>	<71770C804BF1478782F3FFD7741E8CA0@asusp67>
	<BANLkTin9M-U1rzd6p+B8PNie4nbq0WAAXA@mail.gmail.com>
Message-ID: <4DED9A74.8040207@lucidmachines.com>

Marc:

After taking a quick look through the git log, it looks like we've 
probably applied all of the patches you mentioned to me besides these:

"Move SB800 clock init earlier to fix problem where initial serial port 
output is garbled."
"Skip memory clear for boot time reduction. Memory clear is not required 
for non-ECC boards."

I'd confirm manually, but I don't know where to find the actual patches.

Thanks!
-Marshall

On 06/02/2011 11:03 AM, Marc Jones wrote:
> Hi Scott,
>
> i have not forgotten about these. I'll try to get to these this week.
>
> Marc
>
>
> On Fri, May 20, 2011 at 12:04 AM, Scott Duplichan<scott at notabs.org>  wrote:
>> The attached changes for the ASRock E350M1 board improve OS support and
>> reduce boot time. DOS boot from SSD drive takes 690 ms. Windows 7,
>> Windows XP, and linux can install from DVD and boot from hard disk.
>>
>> Signed-off-by: Scott Duplichan<scott at notabs.org>
>>
>> OS install test:
>> Using SeaBIOS 0.6.2 plus AHCI patch,
>> http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/1663.
>>
>> Windows XP SP3 X86
>>     Tested with revision 6600 plus attached patches (removed rev 6579 AHCI
>> enable).
>>     Setup from CD-ROM: pass.
>>     Install latest graphics driver 11-5_xp32_dd_ccc_ocl.exe: 8.850.0.0
>> (4/19/2011): pass.
>> Win7 Ultimate x64 SP1
>>     Tested with revision 6600 plus attached patches.
>>     Setup from DVD: pass.
>>     Install latest graphics driver 11-5_vista64_win7_64_dd_ccc_ocl.exe:
>> 8.850.0.0 (4/19/2011): pass.
>> Ubuntu 11.04 beta
>>
>> http://mirror.anl.gov/pub/ubuntu-iso/DVDs/ubuntu/natty/beta-2/ubuntu-11.04-b
>> eta2-dvd-amd64.iso
>>     Tested with revision 6600 plus attached patches.
>>     Setup from DVD: pass.
>>
>> Thanks,
>> Scott
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>
>




From scott at notabs.org  Tue Jun  7 06:56:52 2011
From: scott at notabs.org (Scott Duplichan)
Date: Mon, 6 Jun 2011 23:56:52 -0500
Subject: [coreboot] [PATCH] ASRock E350M1 update
In-Reply-To: <4DED9A74.8040207@lucidmachines.com>
References: <AcwWs82EUmmnvWnoR+OZ3akIgcBH+g==>	<71770C804BF1478782F3FFD7741E8CA0@asusp67><BANLkTin9M-U1rzd6p+B8PNie4nbq0WAAXA@mail.gmail.com>
	<4DED9A74.8040207@lucidmachines.com>
Message-ID: <2E39D53C03DF4BF99E0B8C7A2AF79DEC@asusp67>

Marshall Buschman wrote:

]Marc:
]
]After taking a quick look through the git log, it looks like we've 
]probably applied all of the patches you mentioned to me besides these:
]
]"Move SB800 clock init earlier to fix problem where initial serial port 
]output is garbled."
]"Skip memory clear for boot time reduction. Memory clear is not required 
]for non-ECC boards."
]
]I'd confirm manually, but I don't know where to find the actual patches.
]
]Thanks!
]-Marshall

Hello Marshall and Marc,

Thanks for committing these patches. The two mentioned above are
items "17-early-serial-fix.patch" and "skip-memclr.patch" from 
this set:
http://permalink.gmane.org/gmane.linux.bios/66598

Thanks,
Scott




From cristi.magherusan at gmail.com  Tue Jun  7 09:33:47 2011
From: cristi.magherusan at gmail.com (=?UTF-8?Q?Cristian_M=C4=83gheru=C8=99an=2DStanciu?=)
Date: Tue, 7 Jun 2011 09:33:47 +0200
Subject: [coreboot] GIGABYTE GA-890GPA-UD3H seems to have the right rom
 chip to flash, but compiling cooreboot v4 fails
In-Reply-To: <BANLkTikU1ZjjO8UZ7kRezfzMd6woWwQTjw@mail.gmail.com>
References: <BANLkTikU1ZjjO8UZ7kRezfzMd6woWwQTjw@mail.gmail.com>
Message-ID: <BANLkTimPfkA8n3CCj41=zEQD=M9E0cAnDA@mail.gmail.com>

Hi,

A message with the log of your compilation failure might be more
useful than an output of flashrom.

~Cristi



From gerrit at coreboot.org  Tue Jun  7 14:56:21 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 14:56:21 +0200
Subject: [coreboot] New patch to review: a02eb1b Added a basic .gitignore
Message-ID: <E1QTvpV-0003UJ-6u@ra.coresystems.de>

Dear list,

Cristian M??gheru??an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/10.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Tue Jun  7 15:05:11 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 15:05:11 +0200
Subject: [coreboot] New patch to review: d138cb2 Drop 'git fetch' when
	building seabios so that coreboot could compile without an
	Internet connection
Message-ID: <E1QTvy3-0005tE-9S@ra.coresystems.de>

Dear list,

Cristian M??gheru??an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/11.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Tue Jun  7 15:32:27 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 15:32:27 +0200
Subject: [coreboot] Patch set updated: 954af2a Added a basic .gitignore
Message-ID: <E1QTwOR-0002Be-9t@ra.coresystems.de>

Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/10

-gerrit
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From gerrit at coreboot.org  Tue Jun  7 16:56:51 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 16:56:51 +0200
Subject: [coreboot] Patch set updated: 6d35f03 SMM: add defines for APM_CNT
	register
Message-ID: <E1QTxi7-0008FU-0Z@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/4

-gerrit
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From gerrit at coreboot.org  Tue Jun  7 16:56:51 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 16:56:51 +0200
Subject: [coreboot] Patch set updated: 965d13d i82801gx: enable ACPI during
	S3 resume
Message-ID: <E1QTxi7-0008GX-KC@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7

-gerrit
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From scott at notabs.org  Tue Jun  7 18:29:31 2011
From: scott at notabs.org (Scott Duplichan)
Date: Tue, 7 Jun 2011 11:29:31 -0500
Subject: [coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <20110607001428.GA26066@morn.localdomain>
References: <E1QSt2H-0007bq-WC@ra.coresystems.de><20110604161605.GC15898@coreboot.org><6CE9EBB920384B8282C963F06BE71CC1@asusp67>
	<20110607001428.GA26066@morn.localdomain>
Message-ID: <19949738E1B246698D3BC62103DC2593@asusp67>

Kevin O'Connor wrote:

]I agree that no one would notice 7ms on it's own.  However, a handful
]of 7ms improvements can be noticed.
]
]I think of the bootblock as the place to fully map the flash device.
]So, why would it be out of place to enable the faster flash accesses
]in the bootblock?
]
]-Kevin

Hello Kevin,

The reason the patch code seems out of place is that the original code
enables the flash enhancements early (before memory initialization)
in sb800/sbpor.c. The patch moves this sb800 setting even earlier. That
is good, except that the sb800 setting is no longer grouped together
with other sb800 code. Instead, it is in romstage.c, which doesn't
usually embed chipset code. A better solution might be to move the flash
enhancement enabling code to an earlier position within sbpor.c. While
sbpor.c executes very early, it runs a fair amount of code before
enabling prefetch and SPI 33 MHz.

Thanks,
Scott




From marcj303 at gmail.com  Tue Jun  7 19:26:13 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 7 Jun 2011 11:26:13 -0600
Subject: [coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
In-Reply-To: <19949738E1B246698D3BC62103DC2593@asusp67>
References: <E1QSt2H-0007bq-WC@ra.coresystems.de>
	<20110604161605.GC15898@coreboot.org>
	<6CE9EBB920384B8282C963F06BE71CC1@asusp67>
	<20110607001428.GA26066@morn.localdomain>
	<19949738E1B246698D3BC62103DC2593@asusp67>
Message-ID: <BANLkTikXgZ6fQ82pWfZaj6dmqP7UZ7JmPg@mail.gmail.com>

On Tue, Jun 7, 2011 at 10:29 AM, Scott Duplichan <scott at notabs.org> wrote:
> Kevin O'Connor wrote:
>
> ]I agree that no one would notice 7ms on it's own. ?However, a handful
> ]of 7ms improvements can be noticed.
> ]
> ]I think of the bootblock as the place to fully map the flash device.
> ]So, why would it be out of place to enable the faster flash accesses
> ]in the bootblock?
> ]
> ]-Kevin
>
> Hello Kevin,
>
> The reason the patch code seems out of place is that the original code
> enables the flash enhancements early (before memory initialization)
> in sb800/sbpor.c. The patch moves this sb800 setting even earlier. That
> is good, except that the sb800 setting is no longer grouped together
> with other sb800 code. Instead, it is in romstage.c, which doesn't
> usually embed chipset code. A better solution might be to move the flash
> enhancement enabling code to an earlier position within sbpor.c. While
> sbpor.c executes very early, it runs a fair amount of code before
> enabling prefetch and SPI 33 MHz.
>
> Thanks,
> Scott

There are southbridge specific bootblock.c functions which enable
access etc., so moving the prefetch settings should be fine.

Can SPI be programmed to 33MHz always? Does it depend on the device or
platform? It may need to be a configuration option or a romstage.c
call.

Marc





-- 
http://se-eng.com



From gerrit at coreboot.org  Tue Jun  7 21:46:09 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 7 Jun 2011 21:46:09 +0200
Subject: [coreboot] Patch merged into master: e75d028 Add "gitconfig" make
	target to simplify gerrit configuration
Message-ID: <E1QU2E6-0001ts-03@ra.coresystems.de>

the following patch was just integrated into master:
commit e75d028c249067a8c59d2fc67d559046248245f3
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sun Jun 5 15:15:49 2011 +0200

    Add "gitconfig" make target to simplify gerrit configuration
    
    "make gitconfig" installs the gerrit commit-msg hook and validates
    that user.name and user.email are configured.
    
    No data will be overwritten.
    
    Change-Id: I49ec98538574866e7ad6238ff3d02b9c1beef1bb

See http://review.coreboot.org/2 for details.

-gerrit



From gerrit at coreboot.org  Tue Jun  7 22:01:30 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 7 Jun 2011 22:01:30 +0200
Subject: [coreboot] Patch merged into master: 6d35f03 SMM: add defines for
	APM_CNT register
Message-ID: <E1QU2Sw-0000aN-9C@ra.coresystems.de>

the following patch was just integrated into master:
commit 6d35f03d8770939967951a1a0e882896cdf007b8
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 5 11:33:41 2011 +0200

    SMM: add defines for APM_CNT register
    
    in the current code, the defines for the APM_CNT (0xb2) register
    are duplicated in almost every place where it is used. define those
    values in cpu/x86/smm.h, and only include this file.
    
    And while at it, fixup whitespace.
    
    Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/4 for details.

-gerrit



From gerrit at coreboot.org  Tue Jun  7 22:11:47 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 7 Jun 2011 22:11:47 +0200
Subject: [coreboot] Patch merged into master: 965d13d i82801gx: enable ACPI
	during S3 resume
Message-ID: <E1QU2ct-0003Sb-Fs@ra.coresystems.de>

the following patch was just integrated into master:
commit 965d13d8627ac29782af2cc3db3e4fffeaa7fc76
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 5 11:39:12 2011 +0200

    i82801gx: enable ACPI during S3 resume
    
    disabling ACPI during S3 wakeup breaks ACPI wakeup, as the
    Host OS is assuming that ACPI is enabled.
    
    Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/7 for details.

-gerrit



From gerrit at coreboot.org  Tue Jun  7 22:20:40 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 22:20:40 +0200
Subject: [coreboot] Patch set updated: 77ac4d1 T60/PMH7: move 'touchpad'
	option to pmh7
Message-ID: <E1QU2lU-0004yG-MQ@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/6

-gerrit
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From gerrit at coreboot.org  Tue Jun  7 22:43:15 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 7 Jun 2011 22:43:15 +0200
Subject: [coreboot] Patch merged into master: 77ac4d1 T60/PMH7: move
	'touchpad' option to pmh7
Message-ID: <E1QU37L-0004w6-1V@ra.coresystems.de>

the following patch was just integrated into master:
commit 77ac4d1a75e214e49e6770bd927a88c251b62e48
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 5 21:32:51 2011 +0200

    T60/PMH7: move 'touchpad' option to pmh7
    
    This option is PMH7 specific, and should be moved there,
    so all Notebook utilizing a PMH7 have this option.
    For Thinkpads without Touchpad (like the X60), simply
    don't add 'touchpad' to cmos.layout.
    
    Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/6 for details.

-gerrit



From dhendrix at google.com  Tue Jun  7 22:59:52 2011
From: dhendrix at google.com (David Hendricks)
Date: Tue, 7 Jun 2011 13:59:52 -0700
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <1307306889.1783.36.camel@kubuntu>
References: <1307306889.1783.36.camel@kubuntu>
Message-ID: <BANLkTimmKgFhJfavN7eyo=EgfmyHM5PWFVGPig+cawBxPRc8tQ@mail.gmail.com>

On Sun, Jun 5, 2011 at 1:48 PM, Patrick Georgi <patrick at georgi-clan.de>wrote:

> 4. Mail notification
> Mail notification to the mailing list is implemented from scratch. Right
> now it only reports on new patch submissions and on patches merged into
> the master branch. More events might/will follow in future, and we will
> certainly tweak the ad-hoc messages and formatting some more.
>

I suggest squelching the "Patch set updated" messages on the mailing list.
Reviewers will get the notifications anyway, so for those who are not
reviewing a patch those notifications are excessive.

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From patrick at georgi-clan.de  Wed Jun  8 07:13:14 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 08 Jun 2011 07:13:14 +0200
Subject: [coreboot] [ANN] New code repository and development workflow
In-Reply-To: <BANLkTimmKgFhJfavN7eyo=EgfmyHM5PWFVGPig+cawBxPRc8tQ@mail.gmail.com>
References: <1307306889.1783.36.camel@kubuntu>
	<BANLkTimmKgFhJfavN7eyo=EgfmyHM5PWFVGPig+cawBxPRc8tQ@mail.gmail.com>
Message-ID: <1307509994.1878.1.camel@kubuntu>

Am Dienstag, den 07.06.2011, 13:59 -0700 schrieb David Hendricks:

> I suggest squelching the "Patch set updated" messages on the mailing
> list. Reviewers will get the notifications anyway, so for those who
> are not reviewing a patch those notifications are excessive.
Good suggestion, thanks.


Patrick





From doverailing at gmail.com  Wed Jun  8 09:24:24 2011
From: doverailing at gmail.com (dove - railing)
Date: Wed, 8 Jun 2011 07:24:24 +0000
Subject: [coreboot] Any Coreboot users/subscribers in Britain?
Message-ID: <BANLkTinhzJYBO-kwv72HoSr68xgP7X8g=A@mail.gmail.com>

I would be interested to know if you have any Coreboot users/subscribers in
Britain and if they would be interested in helping a non-techie.

Regards,


Meeku
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From doverailing at gmail.com  Wed Jun  8 09:15:39 2011
From: doverailing at gmail.com (dove - railing)
Date: Wed, 8 Jun 2011 07:15:39 +0000
Subject: [coreboot] Fwd: Fonts at the Bios
In-Reply-To: <4DED3AE8.8050105@gmx.net>
References: <BANLkTi=iLbx3U3xbnp=v6WGHTBehneOo_g@mail.gmail.com>
	<4DEADC51.20608@coreboot.org>
	<BANLkTikFvUvoTWSWg2hr_Vv3N+1EB8brMg@mail.gmail.com>
	<BANLkTimd_DOzNFtCfgT0=m3KD9NpQONr_g@mail.gmail.com>
	<4DED3AE8.8050105@gmx.net>
Message-ID: <BANLkTikoLHoqTrx+UyTAb3ZLdgkvXLZbJQ@mail.gmail.com>

On Mon, Jun 6, 2011 at 8:39 PM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Am 05.06.2011 12:49 schrieb dove - railing:
> > Could not http://www.flashrom.org/Flashrom utility be an opensource
> > utility for Video card / VGA Bios?
>
> What are you trying to do?
>

Change the Video card / VGA font.  Could the Flashrom utility be used for
this?


Regards,


Meeku
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From gerrit at coreboot.org  Wed Jun  8 10:54:29 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 08 Jun 2011 10:54:29 +0200
Subject: [coreboot] New patch to review: 49493f5 T60: add volume CMOS setting
Message-ID: <E1QUEWz-0005eg-7x@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/12

-gerrit
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From paulepanter at users.sourceforge.net  Wed Jun  8 13:05:04 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 08 Jun 2011 13:05:04 +0200
Subject: [coreboot] gerrit: differences between patchset iterations (was:
 New patch to review: 49493f5 T60: add volume CMOS setting)
In-Reply-To: <E1QUEWz-0005eg-7x@ra.coresystems.de>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
Message-ID: <1307531104.4193.12.camel@mattotaupa>

Dear coreboot folks,


Am Mittwoch, den 08.06.2011, 10:54 +0200 schrieb gerrit at coreboot.org:
> Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
> http://review.coreboot.org/12

opening that URL I see that Sven uploaded a second iteration. How can I
see what changed regarding to the first iteration?


Thanks,

Paul
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From pat-lkml at erley.org  Wed Jun  8 16:18:40 2011
From: pat-lkml at erley.org (pat-lkml)
Date: Wed, 08 Jun 2011 10:18:40 -0400
Subject: [coreboot] gerrit: differences between patchset iterations
In-Reply-To: <1307531104.4193.12.camel@mattotaupa>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa>
Message-ID: <4DEF84C0.6090601@erley.org>

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From paulepanter at users.sourceforge.net  Wed Jun  8 16:45:13 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 08 Jun 2011 16:45:13 +0200
Subject: [coreboot] gerrit: differences between patchset iterations
In-Reply-To: <4DEF84C0.6090601@erley.org>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa>  <4DEF84C0.6090601@erley.org>
Message-ID: <1307544313.4193.20.camel@mattotaupa>

Am Mittwoch, den 08.06.2011, 10:18 -0400 schrieb pat-lkml:
> On 6/8/2011 7:05 AM, Paul Menzel wrote: 

> > Am Mittwoch, den 08.06.2011, 10:54 +0200 schrieb gerrit at coreboot.org:
> > > Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
> > > http://review.coreboot.org/12
> > opening that URL I see that Sven uploaded a second iteration. How can I
> > see what changed regarding to the first iteration?

> Change "Old Version History" to "Patch Set 1"

Thanks, but I do not want to compare them manually but see the
differences between v1 and v2.


Thanks,

Paul
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From pat-lkml at erley.org  Wed Jun  8 16:46:42 2011
From: pat-lkml at erley.org (pat-lkml)
Date: Wed, 08 Jun 2011 10:46:42 -0400
Subject: [coreboot] gerrit: differences between patchset iterations
In-Reply-To: <1307544313.4193.20.camel@mattotaupa>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>	<1307531104.4193.12.camel@mattotaupa>
	<4DEF84C0.6090601@erley.org> <1307544313.4193.20.camel@mattotaupa>
Message-ID: <4DEF8B52.2000503@erley.org>

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From paulepanter at users.sourceforge.net  Wed Jun  8 17:10:39 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 08 Jun 2011 17:10:39 +0200
Subject: [coreboot] [solved] gerrit: differences between patchset
 iterations
In-Reply-To: <4DEF8B52.2000503@erley.org>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa> <4DEF84C0.6090601@erley.org>
	<1307544313.4193.20.camel@mattotaupa>  <4DEF8B52.2000503@erley.org>
Message-ID: <1307545840.4193.21.camel@mattotaupa>

Am Mittwoch, den 08.06.2011, 10:46 -0400 schrieb pat-lkml:
> On 6/8/2011 10:45 AM, Paul Menzel wrote: 
> > Am Mittwoch, den 08.06.2011, 10:18 -0400 schrieb pat-lkml:
> > > On 6/8/2011 7:05 AM, Paul Menzel wrote: 
> > > > Am Mittwoch, den 08.06.2011, 10:54 +0200 schrieb gerrit at coreboot.org:
> > > > > Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
> > > > > http://review.coreboot.org/12
> > > > opening that URL I see that Sven uploaded a second iteration. How can I
> > > > see what changed regarding to the first iteration?
> > > Change "Old Version History" to "Patch Set 1"
> > Thanks, but I do not want to compare them manually but see the
> > differences between v1 and v2.

> Changing this setting changes the diffs to be incremental between
> patchsets (at least for me, changing that makes there only be 1 file
> difference, the changelog).

Thank you, I did not notice this one.


Thanks,

Paul
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From gerrit at coreboot.org  Wed Jun  8 17:19:22 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 08 Jun 2011 17:19:22 +0200
Subject: [coreboot] New patch to review: 9a25c3a Add ACPI automatic PIC/APIC
	interrupt routing logic for ck804.
Message-ID: <E1QUKXS-0000rA-V8@ra.coresystems.de>

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/13

-gerrit
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From gerrit at coreboot.org  Thu Jun  9 00:13:11 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 9 Jun 2011 00:13:11 +0200
Subject: [coreboot] Patch merged into master: fefca6d Add basic .gitignore
Message-ID: <E1QUQzv-0000yF-JF@ra.coresystems.de>

the following patch was just integrated into master:
commit fefca6d73492860d916dea2328397d62ad12dec2
Author: Cristian M??gheru??an-Stanciu <cristi.magherusan at gmail.com>
Date:   Tue Jun 7 14:55:40 2011 +0200

    Add basic .gitignore
    
    Ignore directories created by abuild, jenkins, payloads and crossgcc.
    
    Change-Id: I7d4145fc1e54a10ffdc4b884d8b8f0ae53e615c6
    Signed-off-by: Cristian M??gheru??an-Stanciu <cristi.magherusan at gmail.com>
    Signed-off-by: Peter Stuge <peter at stuge.se>

See http://review.coreboot.org/10 for details.

-gerrit



From gerrit at coreboot.org  Thu Jun  9 00:23:39 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 09 Jun 2011 00:23:39 +0200
Subject: [coreboot] New patch to review: 25f999d Revert changes to set the
	sb800 to AHCI mode. Seabios doesn't have this support included yet,
	which causes the generic Persimmon and other CIMx sb800 platforms to
	not boot.
Message-ID: <E1QURA3-00041D-3Y@ra.coresystems.de>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/14

-gerrit
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From marcj303 at gmail.com  Thu Jun  9 00:41:08 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 8 Jun 2011 16:41:08 -0600
Subject: [coreboot] [patch] revert sb800 cimx AHCI mode
In-Reply-To: <20110604135922.GA4184@tarantulon.kollasch.net>
References: <BANLkTinvLpgBJBvhnoJkziSP9qt-CTeFDw@mail.gmail.com>
	<20110604135922.GA4184@tarantulon.kollasch.net>
Message-ID: <BANLkTi=ZWqk+qm91pBubX5Jkihk2anKaxQ@mail.gmail.com>

On Sat, Jun 4, 2011 at 7:59 AM, Jonathan A. Kollasch
<jakllsch at kollasch.net> wrote:
> On Fri, Jun 03, 2011 at 12:44:22PM -0600, Marc Jones wrote:
>> Revert changes to set the sb800 to AHCI mode. Seabios doesn't have
>> this support included yet, which causes the generic Persimmon and
>> other CIMx sb800 platforms to not boot.
>>
>> Signed-off-by: Marc Jones <marcj303 at gmail.com>
>
> Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>
>


i didn't get this in before the switch to git/gerrit.
Please review this patch here: http://review.coreboot.org/#change,14

Marc


-- 
http://se-eng.com



From gerrit at coreboot.org  Thu Jun  9 01:07:02 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 9 Jun 2011 01:07:02 +0200
Subject: [coreboot] Patch merged into master: 838a68e Revert changes to set
	the sb800 to AHCI mode.
Message-ID: <E1QURq2-0006ir-G0@ra.coresystems.de>

the following patch was just integrated into master:
commit 838a68e275add894064cf0af19de878e582df84e
Author: Marc Jones <marcj303 at gmail.com>
Date:   Wed Jun 8 14:41:52 2011 -0600

    Revert changes to set the sb800 to AHCI mode.
    
    Seabios doesn't have this support included yet,
    which causes the generic Persimmon and other CIMx
    sb800 platforms to not boot.
    
    Change-Id: If07328b7c62d7fc314647adce8fab983ed327854
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

See http://review.coreboot.org/14 for details.

-gerrit



From dhendrix at google.com  Thu Jun  9 02:04:44 2011
From: dhendrix at google.com (David Hendricks)
Date: Wed, 8 Jun 2011 17:04:44 -0700
Subject: [coreboot] gerrit: differences between patchset iterations
 (was: New patch to review: 49493f5 T60: add volume CMOS setting)
In-Reply-To: <1307531104.4193.12.camel@mattotaupa>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa>
Message-ID: <BANLkTikmtehxoznf15=5eo+tQbZCyNw=VmitkkiBQjcchVomKQ@mail.gmail.com>

On Wed, Jun 8, 2011 at 4:05 AM, Paul Menzel <
paulepanter at users.sourceforge.net> wrote:

> Dear coreboot folks,
>
>
> Am Mittwoch, den 08.06.2011, 10:54 +0200 schrieb gerrit at coreboot.org:
> > Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to
> gerrit, which you can find at
> > http://review.coreboot.org/12
>
> opening that URL I see that Sven uploaded a second iteration. How can I
> see what changed regarding to the first iteration?
>

There are a couple ways, here's one:
1. Click on a file to diff (or click on "diff all" to open each file up in a
new browser tab)
2. Click the arrow next to "Patch history" in the upper left corner
3. Choose two patch sets to diff.
4. Hit the "update" button.

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From peter at stuge.se  Thu Jun  9 02:16:25 2011
From: peter at stuge.se (Peter Stuge)
Date: Thu, 9 Jun 2011 02:16:25 +0200
Subject: [coreboot] gerrit: patch iterations in email [was:
	differences	between patchset iterations]
In-Reply-To: <1307531104.4193.12.camel@mattotaupa>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa>
Message-ID: <20110609001625.20477.qmail@stuge.se>

Paul Menzel wrote:
> > http://review.coreboot.org/12
> 
> opening that URL I see that Sven uploaded a second iteration.

I think I would like to get later iterations in follow-up emails..


> How can I see what changed regarding to the first iteration?

..probably incremental, as opposed to the full patch again.


//Peter
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From v10lator at myway.de  Thu Jun  9 02:57:13 2011
From: v10lator at myway.de (Thomas Rohloff)
Date: Thu, 9 Jun 2011 02:57:13 +0200
Subject: [coreboot] Is this board supported?
In-Reply-To: <20110603184316.GA29494@coreboot.org>
References: <20110602075247.6bd513cb@schlepptop>
	<4DE7920C.3000905@coreboot.org>
	<20110603123328.40081039@schlepptop>
	<20110603184316.GA29494@coreboot.org>
Message-ID: <20110609025713.7a363a5b@schlepptop>

Am Fri, 3 Jun 2011 20:43:17 +0200
schrieb Stefan Reinauer <stefan.reinauer at coreboot.org>:

> If someone with the hardware steps up to do a port there is a chance
> indeed. 
I googled a bit and found somebody called "Jonathan A. Kollasch". He
wrote that he has a board with the same north- and southbridge. This
message was from 12.04. at 23:06. If anybody has his message (subject:
"SB850 SERR# routinh (almost off-topic)") please re-send it to me
because his e-mail isn't shown in the mailing list archives found by
google but I would like to speak to him. :)

> That someone could be you! :-)
I don't think so. I know all the documentation is there but my coding
skills are extreme poor.
> Also be sure that you have any means of recovery. A second flash chip
> if yours is socketed, or an external eeprom burner for instance.
I would buy a secound chip if I could help with it, but I don't think I
could do more then testing.
> Have not looked into it, but I believe I read that the 3core/4core
> switch is done by some code running on the EC, so it might not be a
> lot of work on the bios side.
What is EC? Is this a chip called "UCC" by AsRock?



From dhendrix at google.com  Thu Jun  9 04:24:39 2011
From: dhendrix at google.com (David Hendricks)
Date: Wed, 8 Jun 2011 19:24:39 -0700
Subject: [coreboot] gerrit: patch iterations in email [was: differences
 between patchset iterations]
In-Reply-To: <20110609001625.20477.qmail@stuge.se>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa>
	<20110609001625.20477.qmail@stuge.se>
Message-ID: <BANLkTimHDf7C4hBA68bvL3YRsncSi90SHLwHosPjCpFZc1RUJw@mail.gmail.com>

On Wed, Jun 8, 2011 at 5:16 PM, Peter Stuge <peter at stuge.se> wrote:

> Paul Menzel wrote:
> > > http://review.coreboot.org/12
> >
> > opening that URL I see that Sven uploaded a second iteration.
>
> I think I would like to get later iterations in follow-up emails..
>

If you add yourself as a reviewer, you should get e-mails for comments and
iterations.

(Note: I haven't verified this with Coreboot's gerrit setup)

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From dhendrix at google.com  Thu Jun  9 04:45:15 2011
From: dhendrix at google.com (David Hendricks)
Date: Wed, 8 Jun 2011 19:45:15 -0700
Subject: [coreboot] Is this board supported?
In-Reply-To: <20110609025713.7a363a5b@schlepptop>
References: <20110602075247.6bd513cb@schlepptop>
	<4DE7920C.3000905@coreboot.org>
	<20110603123328.40081039@schlepptop>
	<20110603184316.GA29494@coreboot.org>
	<20110609025713.7a363a5b@schlepptop>
Message-ID: <BANLkTin1nugZ9koRDpYzK2vyWitNfd5R_v913oBkgke84iO1YA@mail.gmail.com>

On Wed, Jun 8, 2011 at 5:57 PM, Thomas Rohloff <v10lator at myway.de> wrote:

> Am Fri, 3 Jun 2011 20:43:17 +0200
> schrieb Stefan Reinauer <stefan.reinauer at coreboot.org>:
>
> > If someone with the hardware steps up to do a port there is a chance
> > indeed.
> I googled a bit and found somebody called "Jonathan A. Kollasch". He
> wrote that he has a board with the same north- and southbridge. This
> message was from 12.04. at 23:06. If anybody has his message (subject:
> "SB850 SERR# routinh (almost off-topic)") please re-send it to me
> because his e-mail isn't shown in the mailing list archives found by
> google but I would like to speak to him. :)
>

He hangs out on #coreboot on freenode using the name "jakllsch".

On Wed, Jun 8, 2011 at 5:57 PM, Thomas Rohloff <v10lator at myway.de> wrote:

> > That someone could be you! :-)
> I don't think so. I know all the documentation is there but my coding
> skills are extreme poor.
>

That's fine. It sounds like your board is like 95% done thanks to Jonathan's
efforts (assuming he's been successful) and AMD. If you can copy some files
and make some minor tweaks to config files, that might be enough to get you
up and running without actually doing any coding.

On Wed, Jun 8, 2011 at 5:57 PM, Thomas Rohloff <v10lator at myway.de> wrote:

> > Also be sure that you have any means of recovery. A second flash chip
> > if yours is socketed, or an external eeprom burner for instance.
> I would buy a secound chip if I could help with it, but I don't think I
> could do more then testing.

> Have not looked into it, but I believe I read that the 3core/4core
> > switch is done by some code running on the EC, so it might not be a
> > lot of work on the bios side.
> What is EC? Is this a chip called "UCC" by AsRock?
>

EC is sort of a SuperIO chip, but with more functions commonly used in
laptops. I think you have a normal SuperIO chip. "UCC" seems to be a
marketing name from AsRock that means "Unlock CPU Core".

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From gerrit at coreboot.org  Thu Jun  9 05:02:22 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 09 Jun 2011 05:02:22 +0200
Subject: [coreboot] New patch to review: 063683f util/crossgcc: Skip gdb by
	running buildgcc with -G or --skip-gdb
Message-ID: <E1QUVVm-0007ct-Kl@ra.coresystems.de>

Peter Stuge (peter at stuge.se) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/15

-gerrit
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From gerrit at coreboot.org  Thu Jun  9 05:19:08 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 09 Jun 2011 05:19:08 +0200
Subject: [coreboot] New patch to review: 01422df util/crossgcc: Add
	build-without-gdb Makefile target
Message-ID: <E1QUVm0-0006L2-Rb@ra.coresystems.de>

Peter Stuge (peter at stuge.se) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/16

-gerrit
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From gerrit at coreboot.org  Thu Jun  9 05:19:09 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 09 Jun 2011 05:19:09 +0200
Subject: [coreboot] New patch to review: 01d2c28 Change make crossgcc to
	build without gdb by default
Message-ID: <E1QUVm1-0006Lq-8G@ra.coresystems.de>

Peter Stuge (peter at stuge.se) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/17

-gerrit
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From gerrit at coreboot.org  Thu Jun  9 06:09:18 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 9 Jun 2011 06:09:18 +0200
Subject: [coreboot] Patch merged into master: 01d2c28 Change make crossgcc
	to build without gdb by default
Message-ID: <E1QUWYY-00031U-F3@ra.coresystems.de>

the following patch was just integrated into master:
commit 01d2c2840b212335ae5d722c0320dfad0c72f97b
Author: Peter Stuge <peter at stuge.se>
Date:   Thu Jun 9 05:06:25 2011 +0200

    Change make crossgcc to build without gdb by default
    
    Using gdb with coreboot is not (yet) very common, so at least for
    now it makes sense to not build gdb by default. A make crosstools
    target is also added, which runs the full build in util/crossgcc
    and thus generates a toolchain with both compiler and debugger.
    
    Change-Id: I939ebcd06ae9a1bc485fd18e70cac98112d3bbbf
    Signed-off-by: Peter Stuge <peter at stuge.se>

See http://review.coreboot.org/17 for details.

-gerrit



From gerrit at coreboot.org  Thu Jun  9 06:09:18 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 9 Jun 2011 06:09:18 +0200
Subject: [coreboot] Patch merged into master: ce2c6d6 util/crossgcc: Add
	buildgcc -G and --skip-gdb options
Message-ID: <E1QUWYY-00031j-Na@ra.coresystems.de>

the following patch was just integrated into master:
commit ce2c6d646a3f4a8bd3569be3d45f3c3258997af2
Author: Peter Stuge <peter at stuge.se>
Date:   Thu Jun 9 04:54:16 2011 +0200

    util/crossgcc: Add buildgcc -G and --skip-gdb options
    
    Change-Id: Ic31130774ad56abf0b5498b04b4890348352a621
    Signed-off-by: Peter Stuge <peter at stuge.se>

See http://review.coreboot.org/15 for details.

-gerrit



From gerrit at coreboot.org  Thu Jun  9 06:09:18 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 9 Jun 2011 06:09:18 +0200
Subject: [coreboot] Patch merged into master: 01422df util/crossgcc: Add
	build-without-gdb Makefile target
Message-ID: <E1QUWYZ-000325-02@ra.coresystems.de>

the following patch was just integrated into master:
commit 01422df23fce60f42e6ee4f59e6c1b980de71047
Author: Peter Stuge <peter at stuge.se>
Date:   Thu Jun 9 05:04:20 2011 +0200

    util/crossgcc: Add build-without-gdb Makefile target
    
    Change-Id: I5d02f1a23e54aa67be0cc01d921898c28c22f8e4
    Signed-off-by: Peter Stuge <peter at stuge.se>

See http://review.coreboot.org/16 for details.

-gerrit



From gerrit at coreboot.org  Thu Jun  9 10:05:47 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 9 Jun 2011 10:05:47 +0200
Subject: [coreboot] Patch merged into master: 129a1de H8 EC: add volume CMOS
	setting
Message-ID: <E1QUaFP-0000nA-7G@ra.coresystems.de>

the following patch was just integrated into master:
commit 129a1dee1bef60b78439dc505d2671a28ca23a3d
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 5 20:47:49 2011 +0200

    H8 EC: add volume CMOS setting
    
    Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/12 for details.

-gerrit



From patrick at georgi-clan.de  Thu Jun  9 15:16:35 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 09 Jun 2011 15:16:35 +0200
Subject: [coreboot]
	=?utf-8?q?gerrit=3A_patch_iterations_in_email_=5Bwas?=
	=?utf-8?q?=3A_differences=09between_patchset_iterations=5D?=
In-Reply-To: <20110609001625.20477.qmail@stuge.se>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa>
	<20110609001625.20477.qmail@stuge.se>
Message-ID: <a16e9d8c0b26c5a83f460c7af8a5d91e@mail.georgi-clan.de>

On Thu, 9 Jun 2011 02:16:25 +0200, Peter Stuge wrote:
>> opening that URL I see that Sven uploaded a second iteration.
> I think I would like to get later iterations in follow-up emails..
I just disabled it yesterday because it spams the list.
As David says, if you're interested in individual topics, register as 
reviewer and you'll get updates.

>> How can I see what changed regarding to the first iteration?
> ..probably incremental, as opposed to the full patch again.
I fear that's a matter of taste.


Patrick



From marcj303 at gmail.com  Thu Jun  9 18:08:35 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 9 Jun 2011 10:08:35 -0600
Subject: [coreboot] [RFC]Using gerrit for patch management (and jenkins
 for QA)
In-Reply-To: <20110601184655.31108.qmail@stuge.se>
References: <4DE53988.3010407@georgi-clan.de>
	<1306913471.4315.4.camel@mattotaupa>
	<4DE5FC09.2020808@georgi-clan.de> <1306918881.4315.22.camel@mattotaupa>
	<BANLkTinP3DNyb-S0CETFBRsU=whSt3+Erb1mQApdo9wSaomUag@mail.gmail.com>
	<20110601184655.31108.qmail@stuge.se>
Message-ID: <BANLkTikvG0vBu+4KTQx8DH58x4NMXLM3Rw@mail.gmail.com>

Hi Patrick,

I have been discussing coreboot and gerrit with some people who have
been using gerrit on their projects for a while. They had two
recommendations for coreboot.

1. Get gitweb working

2.Star this bug @ google:  http://code.google.com/p/gerrit/issues/detail?id=924

Thoughts?

Marc


-- 
http://se-eng.com



From uwe at hermann-uwe.de  Thu Jun  9 18:39:36 2011
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 9 Jun 2011 18:39:36 +0200
Subject: [coreboot] gerrit: patch iterations in email [was: differences
 between patchset iterations]
In-Reply-To: <BANLkTimHDf7C4hBA68bvL3YRsncSi90SHLwHosPjCpFZc1RUJw@mail.gmail.com>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa>
	<20110609001625.20477.qmail@stuge.se>
	<BANLkTimHDf7C4hBA68bvL3YRsncSi90SHLwHosPjCpFZc1RUJw@mail.gmail.com>
Message-ID: <20110609163935.GC18563@greenwood>

On Wed, Jun 08, 2011 at 07:24:39PM -0700, David Hendricks wrote:
> On Wed, Jun 8, 2011 at 5:16 PM, Peter Stuge <peter at stuge.se> wrote:
> 
> > Paul Menzel wrote:
> > > > http://review.coreboot.org/12
> > >
> > > opening that URL I see that Sven uploaded a second iteration.
> >
> > I think I would like to get later iterations in follow-up emails..

Yep, me too.


> If you add yourself as a reviewer, you should get e-mails for comments and
> iterations.
> 
> (Note: I haven't verified this with Coreboot's gerrit setup)

I'd prefer to see all changes for all issues on the mailing list, I don't
think I want to go to the web interface for every new patch submission
someone does and add myself there just in order to get the notifications.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From uwe at hermann-uwe.de  Thu Jun  9 18:46:02 2011
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 9 Jun 2011 18:46:02 +0200
Subject: [coreboot] Patch merged into master: 129a1de H8 EC: add volume
 CMOS setting
In-Reply-To: <E1QUaFP-0000nA-7G@ra.coresystems.de>
References: <E1QUaFP-0000nA-7G@ra.coresystems.de>
Message-ID: <20110609164602.GD18563@greenwood>

On Thu, Jun 09, 2011 at 10:05:47AM +0200, gerrit at coreboot.org wrote:
> the following patch was just integrated into master:
> commit 129a1dee1bef60b78439dc505d2671a28ca23a3d
> Author: Sven Schnelle <svens at stackframe.org>
> Date:   Sun Jun 5 20:47:49 2011 +0200
> 
>     H8 EC: add volume CMOS setting
>     
>     Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d
>     Signed-off-by: Sven Schnelle <svens at stackframe.org>
> 
> See http://review.coreboot.org/12 for details.

Could these "merged" mails also list who acked/reviewed the stuff etc?
I.e. also print the Acked-by equivalent, in addition to the
Signed-off-by? At the moment you cannot see in the mail whether it's a
self-acked patch and/or who and how many people acked it.

Also, add any other relevant metadata here, IMHO, for example the comments:

  Sven Schnelle	Uploaded patch set 2.	Jun 8 Uploaded patch set 2.
  build bot (Jenkins)	Patch Set 1: Build Successful ?	Jun 8
  build bot (Jenkins)	Patch Set 2: Verified Build Successful ?	Jun 8
  Sven Schnelle	Patch Set 2: Looks good to me, approved	10:05
  Sven Schnelle	Change has been successfully cherry-picked as ?	10:05


Thanks, Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From gerrit at coreboot.org  Thu Jun  9 20:58:03 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 09 Jun 2011 20:58:03 +0200
Subject: [coreboot] New patch to review: 54a2294 superiotool: Cosmetics and
	coding style fixes.
Message-ID: <E1QUkQd-0001sC-JY@ra.coresystems.de>

Uwe Hermann (uwe at hermann-uwe.de) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/18

-gerrit
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From gerrit at coreboot.org  Thu Jun  9 21:26:48 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 9 Jun 2011 21:26:48 +0200
Subject: [coreboot] Patch merged into master: 54a2294 superiotool: Cosmetics
	and coding style fixes.
Message-ID: <E1QUksS-0002TI-6I@ra.coresystems.de>

the following patch was just integrated into master:
commit 54a22948eeb309c28d5b5249c9ec96bc96bd3bea
Author: Uwe Hermann <uwe at hermann-uwe.de>
Date:   Thu Jun 9 20:56:29 2011 +0200

    superiotool: Cosmetics and coding style fixes.
    
    Change-Id: Iacda2a9e37635d5cffc5004caf588ef3e5e09b5e
    Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

See http://review.coreboot.org/18 for details.

-gerrit



From dhendrix at google.com  Thu Jun  9 21:51:38 2011
From: dhendrix at google.com (David Hendricks)
Date: Thu, 9 Jun 2011 12:51:38 -0700
Subject: [coreboot] gerrit: patch iterations in email [was: differences
 between patchset iterations]
In-Reply-To: <20110609163935.GC18563@greenwood>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa>
	<20110609001625.20477.qmail@stuge.se>
	<BANLkTimHDf7C4hBA68bvL3YRsncSi90SHLwHosPjCpFZc1RUJw@mail.gmail.com>
	<20110609163935.GC18563@greenwood>
Message-ID: <BANLkTimEfuRivCZPV1PUbc2dhS5MDkaMdcExmUDYU2cMznwxrA@mail.gmail.com>

On Thu, Jun 9, 2011 at 9:39 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:

> On Wed, Jun 08, 2011 at 07:24:39PM -0700, David Hendricks wrote:
> > On Wed, Jun 8, 2011 at 5:16 PM, Peter Stuge <peter at stuge.se> wrote:
> >
> > > Paul Menzel wrote:
> > > > > http://review.coreboot.org/12
> > > >
> > > > opening that URL I see that Sven uploaded a second iteration.
> > >
> > > I think I would like to get later iterations in follow-up emails..
>
> Yep, me too.
>

Maybe I was over-reacting to what seemed like a lot of "Patch set updated"
e-mails drowning out ML discussion.

Perhaps it would be wise to create another e-mail list for verbose gerrit
messages? That could satisfy the needs of the more involved developers,
without creating too much traffic on the main discussion mailing list.

I don't think I want to go to the web interface for every new patch
> submission
> someone does and add myself there just in order to get the notifications.
>

FWIW, the sender can add people to the reviewer list from the CLI when
sending the patch. For example, if you and Patrick are discussing an issue
and you whip out a patch, then it's perfectly kosher for you to upload the
patch with Patrick listed as a reviewer so he automatically gets further
updates and comments.

The gerrit FAQ linked from the coreboot page uses this as an example:
Specific reviewers can be requested and/or additional `carbon copies'' of
the notification message may be sent by including these as arguments to `git
receive-pack:
git push --receive-pack='git receive-pack --reviewer=a at a.com --cc=b at o.com'
tr:kernel/common HEAD:refs/for/experimental


-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From gerrit at coreboot.org  Tue Jun  7 06:07:34 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 06:07:34 +0200
Subject: [coreboot] New patch to review: 65f4170 re-indent,
	so files conform to coding guidelines.
Message-ID: <E1QTnZm-00074o-1X@ra.coresystems.de>

Dear list,

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/8.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Tue Jun  7 06:07:34 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 06:07:34 +0200
Subject: [coreboot] New patch to review: 0557350 sb800: move spi prefetch
	and fast read mode to sb bootblock.
Message-ID: <E1QTnZm-00075z-Md@ra.coresystems.de>

Dear list,

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/9.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Tue Jun  7 10:07:56 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 10:07:56 +0200
Subject: [coreboot] New patch to review: c76c519 T60: fix touchpad option
Message-ID: <E1QTrKO-0002Gk-RZ@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Tue Jun  7 10:07:57 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 10:07:57 +0200
Subject: [coreboot] New patch to review: d11d66d T60/PMH7: move 'touchpad'
	option to pmh7
Message-ID: <E1QTrKP-0002Hy-Au@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/6.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Tue Jun  7 10:22:13 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 07 Jun 2011 10:22:13 +0200
Subject: [coreboot] New patch to review: 0aa262a T60/PMH7: move 'touchpad'
	option to pmh7
Message-ID: <E1QTrYD-0007cH-Kh@ra.coresystems.de>

Dear list,

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/6.

You will also find it attached for your convenience.

Regards,
gerrit
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From gerrit at coreboot.org  Tue Jun  7 11:58:31 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 7 Jun 2011 11:58:31 +0200
Subject: [coreboot] Patch merged into master: 65f4170 re-indent,
	so files conform to coding guidelines.
Message-ID: <E1QTt3P-00077R-Vt@ra.coresystems.de>

Dear list,

the following patch was just integrated into master.

commit 65f417015ae774f4f82772565c70d755eaf4f66e
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Sat Jun 4 10:36:21 2011 -0700

    re-indent, so files conform to coding guidelines.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    
    Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab

Regards,
gerrit



From gerrit at coreboot.org  Tue Jun  7 12:50:42 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 7 Jun 2011 12:50:42 +0200
Subject: [coreboot] Patch merged into master: c76c519 T60: fix touchpad
	option
Message-ID: <E1QTtru-00019S-VM@ra.coresystems.de>

Dear list,

the following patch was just integrated into master.

commit c76c51943a96409b13a9b3f0237472eed8566f07
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 5 20:43:04 2011 +0200

    T60: fix touchpad option
    
    Code used 'int' as return type, but the cmos option is only one
    bit. get_option returned with the value in bit 0-7, but all remaining
    bits were left unitialized by get_option(). fix this by using char
    as type.
    
    Change-Id: I60e609164277380f936f66c99ef9508fa6a6b67c
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Regards,
gerrit



From marcj303 at gmail.com  Fri Jun 10 17:44:48 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 10 Jun 2011 09:44:48 -0600
Subject: [coreboot] gerrit patch email content
Message-ID: <BANLkTinsC3XGZUR1a5xq3-PdR_q1ynkd1w@mail.gmail.com>

It would be nice if gerrit would send the entire commit message and
the list of files in the patch emails. That would be helpful in
parsing what patches require attention.


Marc


-- 
http://se-eng.com



From gerrit at coreboot.org  Fri Jun 10 19:44:05 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 10 Jun 2011 19:44:05 +0200
Subject: [coreboot] Patch merged into master: 3d6b821 Add ACPI automatic
	PIC/APIC interrupt routing logic for ck804
Message-ID: <E1QV5kb-00046f-4h@ra.coresystems.de>

the following patch was just integrated into master:
commit 3d6b821d5d692667212c502a6376b1f767ccada1
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Wed Jun 8 10:18:43 2011 -0500

    Add ACPI automatic PIC/APIC interrupt routing logic for ck804
    
    Change-Id: I2d462ca1220ea31af243c7a58a1dc33c39e9c840
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>

See http://review.coreboot.org/13 for details.

-gerrit



From gerrit at coreboot.org  Fri Jun 10 20:08:29 2011
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 10 Jun 2011 20:08:29 +0200
Subject: [coreboot] New patch to review: 35a048b Update README with newer
	version of the text from the web page
Message-ID: <E1QV68D-0003z7-6m@ra.coresystems.de>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/19

-gerrit
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From scott at notabs.org  Fri Jun 10 21:34:28 2011
From: scott at notabs.org (Scott Duplichan)
Date: Fri, 10 Jun 2011 14:34:28 -0500
Subject: [coreboot] looking for coreboot snapshots
Message-ID: <7EB2278EA7F74D15BA617844722385DE@asusp67>

Hello,

Is there a way to download an archived snapshot of recent coreboot source
code?

Thanks,
Scott




From patrick at georgi-clan.de  Fri Jun 10 22:19:53 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 10 Jun 2011 22:19:53 +0200
Subject: [coreboot] looking for coreboot snapshots
In-Reply-To: <7EB2278EA7F74D15BA617844722385DE@asusp67>
References: <7EB2278EA7F74D15BA617844722385DE@asusp67>
Message-ID: <30ff0af16a520ff59b1af1545adb3de6@mail.georgi-clan.de>

On Fri, 10 Jun 2011 14:34:28 -0500, Scott Duplichan wrote:
> Is there a way to download an archived snapshot of recent coreboot 
> source
> code?
I'll see that jenkins creates them for "coreboot" builds (not 
"coreboot-gerrit", that would be somewhat excessive, I think).


Patrick



From gerrit at coreboot.org  Sat Jun 11 04:36:03 2011
From: gerrit at coreboot.org (Marshall Buschman (mbuschman@lucidmachines.com))
Date: Sat, 11 Jun 2011 04:36:03 +0200
Subject: [coreboot] New patch to review: 2a221db Skip memory clear for boot
	time reduction
Message-ID: <E1QVE3P-0007UN-H3@ra.coresystems.de>

Marshall Buschman (mbuschman at lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/20

-gerrit
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From gerrit at coreboot.org  Sat Jun 11 04:36:04 2011
From: gerrit at coreboot.org (Marshall Buschman (mbuschman@lucidmachines.com))
Date: Sat, 11 Jun 2011 04:36:04 +0200
Subject: [coreboot] New patch to review: 8e11b36 Move SB800 clock init
	earlier
Message-ID: <E1QVE3Q-0007VB-1R@ra.coresystems.de>

Marshall Buschman (mbuschman at lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/21

-gerrit
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From gerrit at coreboot.org  Sat Jun 11 04:48:49 2011
From: gerrit at coreboot.org (Marshall Buschman (mbuschman@lucidmachines.com))
Date: Sat, 11 Jun 2011 04:48:49 +0200
Subject: [coreboot] New patch to review: 3218571 Really move SB800 clock
	init earlier
Message-ID: <E1QVEFl-0000GR-AC@ra.coresystems.de>

Marshall Buschman (mbuschman at lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/22

-gerrit
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From stefan.tauner at student.tuwien.ac.at  Sat Jun 11 13:09:43 2011
From: stefan.tauner at student.tuwien.ac.at (Stefan Tauner)
Date: Sat, 11 Jun 2011 13:09:43 +0200
Subject: [coreboot] looking for coreboot snapshots
In-Reply-To: <7EB2278EA7F74D15BA617844722385DE@asusp67>
References: <7EB2278EA7F74D15BA617844722385DE@asusp67>
Message-ID: <201106111109.p5BB9bQ6024208@mail2.student.tuwien.ac.at>

On Fri, 10 Jun 2011 14:34:28 -0500
"Scott Duplichan" <scott at notabs.org> wrote:

> Hello,
> 
> Is there a way to download an archived snapshot of recent coreboot source
> code?

gitweb can create snapshots on the fly.
i am not sure if the gitweb integration is completed so YMMV.
http://review.coreboot.org/gitweb?p=coreboot.git;a=summary

-- 
Kind regards/Mit freundlichen Gr??en, Stefan Tauner



From hamo.by at gmail.com  Sat Jun 11 15:27:49 2011
From: hamo.by at gmail.com (Hamo)
Date: Sat, 11 Jun 2011 21:27:49 +0800
Subject: [coreboot] First thought on how to porting coreboot to ARM,
	comments are very welcome
Message-ID: <BANLkTin0U36R-o0gaZ67bQmQRR8naieqgQ@mail.gmail.com>

Dear lists,
First of all, let me say thanks to Stefan for his patch and help on
porting. Without his patch, I couldn't figure out what shall I do and
what to do with CBFS on ARM. Following is the first thought on how to
implement it, justing using qemu-arm (versatilepb) as an example.
After power on, At 0x0, start execution at reset from
src/cpu/arm/arm926ejs/start.S. It will simply jump to the actual start
code. Following, it will set CPU to SVC32 mode and do some basic setup
then go toboard-specific lowlevel_init function to init the ram. After
that, ram is ready to use. Because it is easier initing ram than X86,
no romstage needed. After set the sp pointer, we move to CBFS and find
the ramstage then move it to ram and run it.
We do some init in ramstage and then move to payload.

src/mainboard/emulation/qemu-arm will be the dir for this board. In
this dir, Kconfig will set some configs for this board, including CPU
and its variant type, rambase address of this board and so on.
lowlevel.S will be the place where ram and console init code placed.
src/arch/arm will be the key dir that holds arm-specific lib, headers
and Makefile just like X86's.
src/cpu/arm/arm926ejs is for all cpu that uses arm926ejs core. CPU
variant  will be a subdir under this dir and holding CPU
variant-specific lib and headers.

Thanks,
Hamo



From patrick at georgi-clan.de  Sat Jun 11 16:36:07 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 11 Jun 2011 16:36:07 +0200
Subject: [coreboot] looking for coreboot snapshots
In-Reply-To: <201106111109.p5BB9bQ6024208@mail2.student.tuwien.ac.at>
References: <7EB2278EA7F74D15BA617844722385DE@asusp67>
	<201106111109.p5BB9bQ6024208@mail2.student.tuwien.ac.at>
Message-ID: <d65cfd3272b6c938a8e02351cadc9138@mail.georgi-clan.de>

On Sat, 11 Jun 2011 13:09:43 +0200, Stefan Tauner wrote:
> gitweb can create snapshots on the fly.
> i am not sure if the gitweb integration is completed so YMMV.
> http://review.coreboot.org/gitweb?p=coreboot.git;a=summary
Should work. If not, that's a bug.


Patrick



From scott at notabs.org  Sat Jun 11 17:55:33 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sat, 11 Jun 2011 10:55:33 -0500
Subject: [coreboot] looking for coreboot snapshots
In-Reply-To: <201106111109.p5BB9bQ6024208@mail2.student.tuwien.ac.at>
References: <7EB2278EA7F74D15BA617844722385DE@asusp67>
	<201106111109.p5BB9bQ6024208@mail2.student.tuwien.ac.at>
Message-ID: <49BA0EDDCEBD4F5DA2D1B825C8E1676E@asusp67>

Stefan Tauner wrote:

]> Hello,
]> 
]> Is there a way to download an archived snapshot of recent coreboot source
]> code?
]
]gitweb can create snapshots on the fly.
]i am not sure if the gitweb integration is completed so YMMV.
]http://review.coreboot.org/gitweb?p=coreboot.git;a=summary

Hello Stefan,

Thanks, this is perfect.

Thanks,
Scott





From devtadas at gmail.com  Sun Jun 12 05:58:32 2011
From: devtadas at gmail.com (Tadas Slotkus)
Date: Sun, 12 Jun 2011 06:58:32 +0300
Subject: [coreboot] [PATCH] Temporary libpayload fixes for flashrom as a
	payload
Message-ID: <1307851112.4370.5.camel@ts-laptop>


Signed-off-by: Tadas Slotkus <devtadas at gmail.com>
---
 payloads/libpayload/drivers/serial.c        |    2 +-
 payloads/libpayload/include/libpayload.h    |    1 +
 payloads/libpayload/lib/libpayload.ldscript |    4 ++--
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/payloads/libpayload/drivers/serial.c b/payloads/libpayload/drivers/serial.c
index 0674ec8..9ee9051 100644
--- a/payloads/libpayload/drivers/serial.c
+++ b/payloads/libpayload/drivers/serial.c
@@ -195,7 +195,7 @@ int serial_getchar(void)
 /* A vt100 doesn't do color, setaf/setab below are from xterm-color. */
 #define VT100_SET_COLOR   "\e[3%d;4%dm"
 
-static void serial_putcmd(char *str)
+void serial_putcmd(char *str)
 {
 	while(*str)
 		serial_putchar(*(str++));
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 74fb79a..3564898 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -154,6 +154,7 @@ int keyboard_set_layout(char *country);
  */
 void serial_init(void);
 void serial_putchar(unsigned int c);
+void serial_putcmd(char *str);
 int serial_havechar(void);
 int serial_getchar(void);
 void serial_clear(void);
diff --git a/payloads/libpayload/lib/libpayload.ldscript b/payloads/libpayload/lib/libpayload.ldscript
index 830a390..68c9079 100644
--- a/payloads/libpayload/lib/libpayload.ldscript
+++ b/payloads/libpayload/lib/libpayload.ldscript
@@ -34,8 +34,8 @@ OUTPUT_ARCH(i386)
 
 ENTRY(_entry)
 
-HEAP_SIZE = 16384;
-STACK_SIZE = 16384;
+HEAP_SIZE = 816384;
+STACK_SIZE = 216384;
 
 SECTIONS
 {
-- 
1.7.0.4





From gerrit at coreboot.org  Sun Jun 12 12:15:21 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sun, 12 Jun 2011 12:15:21 +0200
Subject: [coreboot] New patch to review: 46cc5bc CMOS: add set_option()
Message-ID: <E1QVhhR-0005O0-AX@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/23

-gerrit
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From gerrit at coreboot.org  Sun Jun 12 15:34:14 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sun, 12 Jun 2011 15:34:14 +0200
Subject: [coreboot] New patch to review: 0645233 i945 GMA: restore tft
	brightness from cmos
Message-ID: <E1QVknu-0005ad-W1@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/24

-gerrit
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From gerrit at coreboot.org  Sun Jun 12 15:39:01 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sun, 12 Jun 2011 15:39:01 +0200
Subject: [coreboot] New patch to review: a33c371 X60: trigger save cmos on
	volume/brightness change
Message-ID: <E1QVksX-0007Zf-93@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/25

-gerrit
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From gerrit at coreboot.org  Sun Jun 12 15:39:01 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sun, 12 Jun 2011 15:39:01 +0200
Subject: [coreboot] New patch to review: 4189bff X60/T60: set CMOS defaults
Message-ID: <E1QVksX-0007bE-Kv@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/26

-gerrit
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From gerrit at coreboot.org  Sun Jun 12 16:50:04 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sun, 12 Jun 2011 16:50:04 +0200
Subject: [coreboot] New patch to review: 0d807b9 X60: handle EC events in
	SMM if ACPI is disabled
Message-ID: <E1QVlzI-0008Vk-RW@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/27

-gerrit
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From gerrit at coreboot.org  Sun Jun 12 16:53:37 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sun, 12 Jun 2011 16:53:37 +0200
Subject: [coreboot] New patch to review: a245de9 log ec data with DEBUG_SPEW
Message-ID: <E1QVm2j-0007YI-Hr@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/28

-gerrit
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From gerrit at coreboot.org  Sun Jun 12 16:56:58 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sun, 12 Jun 2011 16:56:58 +0200
Subject: [coreboot] New patch to review: 3f222f9 X60/T60: fix return value
	of mainboard_io_trap_handler()
Message-ID: <E1QVm5y-0005vF-DI@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/29

-gerrit
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From gerrit at coreboot.org  Sun Jun 12 17:13:51 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sun, 12 Jun 2011 17:13:51 +0200
Subject: [coreboot] Patch merged into master: a245de9 log ec data with
	DEBUG_SPEW
Message-ID: <E1QVmMJ-0008S7-MG@ra.coresystems.de>

the following patch was just integrated into master:
commit a245de9d7793036eb7e74ff11183392e981bef99
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 16:53:25 2011 +0200

    log ec data with DEBUG_SPEW
    
    Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/28 for details.

-gerrit



From gerrit at coreboot.org  Sun Jun 12 17:28:10 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sun, 12 Jun 2011 17:28:10 +0200
Subject: [coreboot] Patch merged into master: 3f222f9 X60/T60: fix return
	value of mainboard_io_trap_handler()
Message-ID: <E1QVmaA-0004Xp-D8@ra.coresystems.de>

the following patch was just integrated into master:
commit 3f222f9c71578a54e057e25feb2f3f65c9f5b58f
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 16:55:56 2011 +0200

    X60/T60: fix return value of mainboard_io_trap_handler()
    
    The handler should return 1 if it handled the request. The current
    code returns 0, which causes 'Unknown function' logs.
    
    Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/29 for details.

-gerrit



From gerrit at coreboot.org  Sun Jun 12 19:27:34 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sun, 12 Jun 2011 19:27:34 +0200
Subject: [coreboot] Patch merged into master: dff4f19 ASRock/E350M1: Skip
	memory clear for boot time reduction
Message-ID: <E1QVoRi-00028X-TB@ra.coresystems.de>

the following patch was just integrated into master:
commit dff4f190110f4f0310dac1a7a986d2c3c79002fd
Author: Marshall Buschman <mbuschman at lucidmachines.com>
Date:   Fri Jun 10 21:16:41 2011 -0500

    ASRock/E350M1: Skip memory clear for boot time reduction
    
    Applying Scott's patches to e350m1, svn r6600:
    Memory clear is not required for non-ECC boards.
    
    Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1
    Signed-off-by: Scott Duplichan <scott at notabs.org>
    Signed-off-by: Marshall Buschman <mbuschman at lucidmachines.com>

See http://review.coreboot.org/20 for details.

-gerrit



From nothereforever at hotmail.com  Sun Jun 12 11:12:43 2011
From: nothereforever at hotmail.com (HC Barfield)
Date: Sun, 12 Jun 2011 19:12:43 +1000
Subject: [coreboot] Flashing bioses
Message-ID: <COL110-W28C67B5736B26469F52DADF660@phx.gbl>


Message to moderator:
firstly i would suggest not putting an email address on a html page to save on spam... encode it instead: email(A)server(o)com
unencoded email address found here: http://www.coreboot.org/mailman/listinfo/coreboot
 
Mesage to site owners:
i find a minor problem with the FAQ page
it says: "Alternatively you could either use the DOS uniflash utility, or use its source code, which is also available for download from the uniflash site (in Turbo Pascal 7) as a reference for adding support for your flash chip to flashrom. " there is no invitation here to contribute your chip code for flashrom!!
 
 
message to people (or to moderator):
hello, people!
i have made a brick out of a Gigabyte GA8i945 motherboard and was considering getting a MSI board, the MSI has a AMI and the GA has Award, do you know of any issues i may come accross. since i intend on fixing the GA by desoldering and socketing, i could possibly use it to test coreboot if people want me to (and if i have the time, and if the board lives). yes, dual bios, only gave two chances - the second wasnt read only...
 
Charlie.
  		 	   		  
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From svn at coreboot.org  Mon Jun 13 16:00:01 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 13 Jun 2011 16:00:01 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1QW7gP-0006e7-Vu@ra.coresystems.de>

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From marcj303 at gmail.com  Mon Jun 13 19:24:36 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 13 Jun 2011 11:24:36 -0600
Subject: [coreboot] First thought on how to porting coreboot to ARM,
 comments are very welcome
In-Reply-To: <BANLkTin0U36R-o0gaZ67bQmQRR8naieqgQ@mail.gmail.com>
References: <BANLkTin0U36R-o0gaZ67bQmQRR8naieqgQ@mail.gmail.com>
Message-ID: <BANLkTi=ne5JWTWPRFuAOcMD8yrKnqC7NJg@mail.gmail.com>

On Sat, Jun 11, 2011 at 7:27 AM, Hamo <hamo.by at gmail.com> wrote:
> Dear lists,
> First of all, let me say thanks to Stefan for his patch and help on
> porting. Without his patch, I couldn't figure out what shall I do and
> what to do with CBFS on ARM. Following is the first thought on how to
> implement it, justing using qemu-arm (versatilepb) as an example.
> After power on, At 0x0, start execution at reset from
> src/cpu/arm/arm926ejs/start.S. It will simply jump to the actual start
> code. Following, it will set CPU to SVC32 mode and do some basic setup
> then go toboard-specific lowlevel_init function to init the ram. After
> that, ram is ready to use. Because it is easier initing ram than X86,
> no romstage needed. After set the sp pointer, we move to CBFS and find
> the ramstage then move it to ram and run it.
> We do some init in ramstage and then move to payload.
>
> src/mainboard/emulation/qemu-arm will be the dir for this board. In
> this dir, Kconfig will set some configs for this board, including CPU
> and its variant type, rambase address of this board and so on.
> lowlevel.S will be the place where ram and console init code placed.
> src/arch/arm will be the key dir that holds arm-specific lib, headers
> and Makefile just like X86's.
> src/cpu/arm/arm926ejs is for all cpu that uses arm926ejs core. CPU
> variant ?will be a subdir under this dir and holding CPU
> variant-specific lib and headers.
>
> Thanks,
> Hamo

Hi Hamo,

This seems like a reasonable layout. Do you have any specific concerns
about the implementation?

Marc

-- 
http://se-eng.com



From gerrit at coreboot.org  Mon Jun 13 21:58:52 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 13 Jun 2011 21:58:52 +0200
Subject: [coreboot] Patch merged into master: a3cc985 X60/T60: set CMOS
	defaults
Message-ID: <E1QWDHg-0005V8-Ps@ra.coresystems.de>

the following patch was just integrated into master:
commit a3cc9858352dd5d92aec20f7fe86fe46a5053891
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 15:08:58 2011 +0200

    X60/T60: set CMOS defaults
    
    Change-Id: I5789a03898cdbade67887c0389aab5c773f867d9
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/26 for details.

-gerrit



From gerrit at coreboot.org  Tue Jun 14 15:03:02 2011
From: gerrit at coreboot.org (Anonymous Coward (mpnorman@gmail.com))
Date: Tue, 14 Jun 2011 15:03:02 +0200
Subject: [coreboot] New patch to review: 6d0a3dd Added support for Aaeon
	PFM-540I RevB PC104 SBC
Message-ID: <E1QWTGo-0006nM-HE@ra.coresystems.de>

Anonymous Coward (mpnorman at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/30

-gerrit
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From hamo.by at gmail.com  Tue Jun 14 16:44:20 2011
From: hamo.by at gmail.com (Hamo)
Date: Tue, 14 Jun 2011 22:44:20 +0800
Subject: [coreboot] Questions about coreboot on X86
Message-ID: <BANLkTikjCnu6xq334pJqfrR0YTgc5Fq5DQ@mail.gmail.com>

Dear lists,
I have been studying the boot process of coreboot more deeply, and
following questions came out:
1. Which code clean the bss and set sp pointer to the stack? Since
those addresses are defined in coreboot_ram.ld, Should it be in
ramstage? If so, where are they? I don't find them. If not, where are
they and how do they know the addresses of bss and stack?
2. What's the propose of romstage? Some init in romstage has been done
in bootblock, and why those init are done twice?

Thanks,
Hamo



-- 
? ? """
? ? Keep It Simple,Stupid.
? ? """

Chinese Name: ??
Nick Name: Hamo
Homepage: http://hamobai.com/
GPG KEY ID: 0xA4691A33
Key fingerprint = 09D5 2D78 8E2B 0995 CF8E? 4331 33C4 3D24 A469 1A33



From marcj303 at gmail.com  Tue Jun 14 17:44:24 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 14 Jun 2011 09:44:24 -0600
Subject: [coreboot] Questions about coreboot on X86
In-Reply-To: <BANLkTikjCnu6xq334pJqfrR0YTgc5Fq5DQ@mail.gmail.com>
References: <BANLkTikjCnu6xq334pJqfrR0YTgc5Fq5DQ@mail.gmail.com>
Message-ID: <BANLkTinF_Fi+pAdc5-c2mG81Uhf-c=RTMw@mail.gmail.com>

Hi Hamo,


On Tue, Jun 14, 2011 at 8:44 AM, Hamo <hamo.by at gmail.com> wrote:
> Dear lists,
> I have been studying the boot process of coreboot more deeply, and
> following questions came out:
> 1. Which code clean the bss and set sp pointer to the stack? Since
> those addresses are defined in coreboot_ram.ld, Should it be in
> ramstage? If so, where are they? I don't find them. If not, where are
> they and how do they know the addresses of bss and stack?

	/* bss does not contain data, it is just a space that should be zero
	 * initialized on startup. (typically uninitialized global variables)
	 * crt0.S fills between _bss and _ebss with zeroes.
	 */

As the comment says, it is handled by the ramstage crt0.S code. The
stack is the same that is used by romstage until it is changed by
ramstage.



> 2. What's the propose of romstage? Some init in romstage has been done
> in bootblock, and why those init are done twice?


What do you see done twice? There should be a minimal overlap. Some
things need to be setup for romstage to run.


Marc
-- 
http://se-eng.com



From patrick at georgi-clan.de  Tue Jun 14 17:57:07 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 14 Jun 2011 17:57:07 +0200
Subject: [coreboot] Questions about coreboot on X86
In-Reply-To: <BANLkTikjCnu6xq334pJqfrR0YTgc5Fq5DQ@mail.gmail.com>
References: <BANLkTikjCnu6xq334pJqfrR0YTgc5Fq5DQ@mail.gmail.com>
Message-ID: <358633615c2640ed62b449ec077d2dee@mail.georgi-clan.de>

On Tue, 14 Jun 2011 22:44:20 +0800, Hamo wrote:
> 2. What's the propose of romstage? Some init in romstage has been 
> done
> in bootblock, and why those init are done twice?
Historical reasons.

First, coreboot had two parts: bootblock/romstage (which was a single 
entity) and ramstage.
The romstage did raminit and generally set things up so the ramstage 
could work.
As only the top 64kb of flash are guaranteed to be mapped into memory 
space, it was also responsible for mapping the entire flash.

Then came AMD K8.

Its memory init was more complicated (with all the HyperTransport 
setup) and thus exceeded the 64kb the romstage lived in, so things were 
split up.
At some point we moved things around so there's a tiny bootblock (doing 
only flash mapping and maybe deciding which romstage to load), and the 
romstage doing raminit until the ramstage can be loaded as usual.

Many boards are converted to that new style. As it requires chipset 
modifications (essentially splitting out the flash mapping code), some 
boards were not.
At some point I hope we'll have all boards follow the new style.

It might not be necessary for ARM, but I'd propose you also stick to 
the general layout:
- bootblock does flash mapping (if necessary) and decides which 
romstage to load
- romstage does raminit
- ramstage does businit
- payload does whatever is necessary next.


Patrick



From gregg.drwho8 at gmail.com  Wed Jun 15 04:22:23 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Tue, 14 Jun 2011 22:22:23 -0400
Subject: [coreboot] Updating a git based local repository
Message-ID: <BANLkTimfQ5qc6TVu3HcAMSARLwBZaPT=Mw@mail.gmail.com>

Hello!
Here's an interesting one, the Emulab application running (both
hardware and software) at the University of Utah, at
http://www.emulab.net/ and describing here:
http://users.emulab.net/trac/emulab/wiki/GitRepository has gone and
made its software available in much the same way. That same document
also describes how to update an existing repository. In this case I
mean one that I pulled shortly after updating my client and then
completing the pull in the same way that one of you described it.

After issuing the command git pull, the screen showed just that. And
then after few minutes it burst into action and described everything
that's been pushed towards the repository since the creation.

I don't remember the name of the fellow who said to use that command
but it definitely worked. This means I owe one of you an excellent
deli lunch here in Manhattan RSN.

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From gerrit at coreboot.org  Wed Jun 15 06:20:33 2011
From: gerrit at coreboot.org (Marshall Buschman (mbuschman@lucidmachines.com))
Date: Wed, 15 Jun 2011 06:20:33 +0200
Subject: [coreboot] New patch to review: 35e1cb4 Move SB800 clock init
	earlier
Message-ID: <E1QWhaj-0006S1-JT@ra.coresystems.de>

Marshall Buschman (mbuschman at lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/31

-gerrit
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From gerrit at coreboot.org  Wed Jun 15 06:36:29 2011
From: gerrit at coreboot.org (Marshall Buschman (mbuschman@lucidmachines.com))
Date: Wed, 15 Jun 2011 06:36:29 +0200
Subject: [coreboot] New patch to review: 50f85d9 Move SB800 clock init
	earlier
Message-ID: <E1QWhq9-00059B-91@ra.coresystems.de>

Marshall Buschman (mbuschman at lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/32

-gerrit
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From mbuschman at lucidmachines.com  Wed Jun 15 06:59:34 2011
From: mbuschman at lucidmachines.com (Marshall Buschman)
Date: Tue, 14 Jun 2011 23:59:34 -0500
Subject: [coreboot] Automated build fails,
	manual works: Move SB800 clock init earlier
Message-ID: <4DF83C36.3090808@lucidmachines.com>

Hello All:

I need a little help -- gerrit's build fails on something that appears 
to be entirely unrelated -- lenovo support.
My changes are for the ASRock e350m1.

Links:

http://review.coreboot.org/#change,32
http://qa.coreboot.org/job/coreboot-gerrit/90/

Help?

Thanks!
-Marshall Buschman



From gerrit at coreboot.org  Wed Jun 15 08:44:16 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 15 Jun 2011 08:44:16 +0200
Subject: [coreboot] Patch merged into master: 33d3e85 CMOS: add set_option()
Message-ID: <E1QWjpo-0005sm-2Q@ra.coresystems.de>

the following patch was just integrated into master:
commit 33d3e854359d6e2ab6f5bd8f56e1a96057d6db77
Author: Sven Schnelle <svens at stackframe.org>
Date:   Mon Jun 6 15:58:54 2011 +0200

    CMOS: add set_option()
    
    Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/23 for details.

-gerrit



From gerrit at coreboot.org  Wed Jun 15 08:51:20 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 15 Jun 2011 08:51:20 +0200
Subject: [coreboot] Patch merged into master: 4e296db X60: trigger save cmos
	on volume/brightness change
Message-ID: <E1QWjwf-00023Q-0h@ra.coresystems.de>

the following patch was just integrated into master:
commit 4e296db29e90993db88da2252f74a7194fd4c0b5
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 14:35:11 2011 +0200

    X60: trigger save cmos on volume/brightness change
    
    Change-Id: I020e06bc311c4e4327c9d3cf2c379dc8fe070a7a
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/25 for details.

-gerrit



From gerrit at coreboot.org  Wed Jun 15 08:51:37 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 15 Jun 2011 08:51:37 +0200
Subject: [coreboot] Patch merged into master: a2996fc X60: handle EC events
	in SMM if ACPI is disabled
Message-ID: <E1QWjwv-0002Us-DU@ra.coresystems.de>

the following patch was just integrated into master:
commit a2996fc9eef76e71b852e3feef9994156d2fd11d
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 16:49:13 2011 +0200

    X60: handle EC events in SMM if ACPI is disabled
    
    Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/27 for details.

-gerrit



From patrick at georgi-clan.de  Wed Jun 15 09:01:00 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 15 Jun 2011 09:01:00 +0200
Subject: [coreboot] Automated build fails,
 manual works: Move SB800 clock init earlier
In-Reply-To: <4DF83C36.3090808@lucidmachines.com>
References: <4DF83C36.3090808@lucidmachines.com>
Message-ID: <1308121260.8425.4.camel@kubuntu>

Am Dienstag, den 14.06.2011, 23:59 -0500 schrieb Marshall Buschman:
> Hello All:
> 
> I need a little help -- gerrit's build fails on something that appears 
> to be entirely unrelated -- lenovo support.
> My changes are for the ASRock e350m1.
> 
> Links:
> 
> http://review.coreboot.org/#change,32
> http://qa.coreboot.org/job/coreboot-gerrit/90/
> 
> Help?
master was broken for a while because changes were submitted in the
wrong order.

I rebased your change onto latest master and pushed it again. In the
above URL you'll see a "patch set 2" now. It's identical except for
ancestry.


Patrick




From gerrit at coreboot.org  Wed Jun 15 10:16:33 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 15 Jun 2011 10:16:33 +0200
Subject: [coreboot] Patch merged into master: 35a048b Update README with
	newer version of the text from the web page
Message-ID: <E1QWlH7-0005aA-JL@ra.coresystems.de>

the following patch was just integrated into master:
commit 35a048bc818aa066d5428a88df3877e4b68f4991
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Fri Jun 10 20:05:53 2011 +0200

    Update README with newer version of the text from the web page
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Change-Id: I4f181979ca5e47b27731c681a320b34cbecc0027

See http://review.coreboot.org/19 for details.

-gerrit



From gerrit at coreboot.org  Wed Jun 15 14:22:01 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Wed, 15 Jun 2011 14:22:01 +0200
Subject: [coreboot] New patch to review: 0a22fb3 i82801gx: replace
	cafed00d/cafebabe by defines
Message-ID: <E1QWp6f-0007v6-Q7@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/33

-gerrit
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From gerrit at coreboot.org  Wed Jun 15 14:35:05 2011
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 15 Jun 2011 14:35:05 +0200
Subject: [coreboot] Patch set updated: b9b5f06 sb800: move spi prefetch and
	fast read mode to sb bootblock.
Message-ID: <E1QWpJJ-0008Eh-Rw@ra.coresystems.de>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/9

-gerrit

commit b9b5f06edeabec7fe0ac60d436e507ff555f9b50
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Sat Jun 4 10:37:35 2011 -0700

    sb800: move spi prefetch and fast read mode to sb bootblock.
    
    So we don't waste time on the first cbfs scan.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    [adapt persimmon with the same change, and work around romcc bug
     in bootblock code: it doesn't like MEMACCESS[idx] |= value;]
    
    Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
---
 src/mainboard/amd/persimmon/romstage.c             |   20 -----------
 src/mainboard/asrock/e350m1/romstage.c             |   17 ---------
 src/southbridge/amd/cimx_wrapper/sb800/bootblock.c |   37 ++++++++++++++++++--
 3 files changed, 34 insertions(+), 40 deletions(-)

diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 3f2aa10..5ef5557 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -70,26 +70,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
     *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
     }
 
-  // early enable of PrefetchEnSPIFromHost
-  if (boot_cpu())
-    {
-    __outdword (0xcf8, 0x8000a3b8);
-    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
-    }
-
-  // early enable of SPI 33 MHz fast mode read
-  if (boot_cpu())
-    {
-    volatile u32 *spiBase = (void *) 0xa0000000;
-    u32 save;
-    __outdword (0xcf8, 0x8000a3a0);
-    save = __indword (0xcfc);
-    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
-    spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
-    spiBase [0] |= 1 << 18; // fast read enable
-    __outdword (0xcfc, save); // clear temp base
-    }
-
   if (!cpu_init_detectedx && boot_cpu()) {
     post_code(0x30);
     sb_poweron_init();
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 7d25ec1..61de9f6 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -55,23 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
 	__writemsr(0xc0010062, 0);
 
-	// early enable of PrefetchEnSPIFromHost
-	if (boot_cpu()) {
-		__outdword(0xcf8, 0x8000a3b8);
-		__outdword(0xcfc, __indword(0xcfc) | 1 << 24);
-	}
-	// early enable of SPI 33 MHz fast mode read
-	if (boot_cpu()) {
-		volatile u32 *spiBase = (void *)0xa0000000;
-		u32 save;
-		__outdword(0xcf8, 0x8000a3a0);
-		save = __indword(0xcfc);
-		__outdword(0xcfc, (u32) spiBase | 2);	// set temp MMIO base
-		spiBase[3] = (spiBase[3] & ~(3 << 14)) | (1 << 14);
-		spiBase[0] |= 1 << 18;	// fast read enable
-		__outdword(0xcfc, save);	// clear temp base
-	}
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 		sb_poweron_init();
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
index 9d8a349..aaec03c 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
@@ -20,9 +20,9 @@
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 
-static void sb800_enable_rom(void)
+static void enable_rom(void)
 {
-	u32 word;
+	u16 word;
 	u32 dword;
 	device_t dev;
 
@@ -56,8 +56,39 @@ static void sb800_enable_rom(void)
 	pci_io_write_config16(dev, 0x6c, word);
 }
 
+static void enable_prefetch(void)
+{
+	u32 dword;
+	device_t dev = PCI_DEV(0, 0x14, 0x03);
+
+	/* Enable PrefetchEnSPIFromHost */
+	dword = pci_io_read_config32(dev, 0xb8);
+	pci_io_write_config32(dev, 0xb8, dword | (1 << 24));
+}
+
+static void enable_spi_fast_mode(void)
+{
+	u8 byte;
+	u32 dword;
+	device_t dev = PCI_DEV(0, 0x14, 0x03);
+
+	// set temp MMIO base
+	volatile u32 *spi_base = (void *)0xa0000000;
+	u32 save = pci_io_read_config32(dev, 0xa0);
+	pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2);
+
+	// early enable of SPI 33 MHz fast mode read
+	byte = spi_base[3];
+	spi_base[3] = (byte & ~(3 << 14)) | (1 << 14);
+	spi_base[0] = spi_base[0] | (1 << 18);	// fast read enable
+
+	pci_io_write_config32(dev, 0xa0, save);
+}
+
 static void bootblock_southbridge_init(void)
 {
 	/* Setup the rom access for 2M */
-	sb800_enable_rom();
+	enable_rom();
+	enable_prefetch();
+	enable_spi_fast_mode();
 }



From patrick at georgi-clan.de  Wed Jun 15 14:38:22 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 15 Jun 2011 14:38:22 +0200
Subject: [coreboot] gerrit: patch iterations in email [was: differences
 between patchset iterations]
In-Reply-To: <20110609163935.GC18563@greenwood>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa>
	<20110609001625.20477.qmail@stuge.se>
	<BANLkTimHDf7C4hBA68bvL3YRsncSi90SHLwHosPjCpFZc1RUJw@mail.gmail.com>
	<20110609163935.GC18563@greenwood>
Message-ID: <1308141502.8425.12.camel@kubuntu>

Am Donnerstag, den 09.06.2011, 18:39 +0200 schrieb Uwe Hermann:
> I'd prefer to see all changes for all issues on the mailing list, I don't
> think I want to go to the web interface for every new patch submission
> someone does and add myself there just in order to get the notifications.
Back again.


Patrick




From patrick at georgi-clan.de  Wed Jun 15 14:39:45 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 15 Jun 2011 14:39:45 +0200
Subject: [coreboot] gerrit patch email content
In-Reply-To: <BANLkTinsC3XGZUR1a5xq3-PdR_q1ynkd1w@mail.gmail.com>
References: <BANLkTinsC3XGZUR1a5xq3-PdR_q1ynkd1w@mail.gmail.com>
Message-ID: <1308141585.8425.14.camel@kubuntu>

Am Freitag, den 10.06.2011, 09:44 -0600 schrieb Marc Jones:
> It would be nice if gerrit would send the entire commit message and
> the list of files in the patch emails. That would be helpful in
> parsing what patches require attention.
It's "git show -p --stat" (commit message, diffstat, patch content) now,
inlined instead of as attachment. That should do what you want, right?


Patrick




From gerrit at coreboot.org  Wed Jun 15 15:15:08 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 15 Jun 2011 15:15:08 +0200
Subject: [coreboot] Patch merged into master: cb82c6b i82801gx: replace
	cafed00d/cafebabe by defines
Message-ID: <E1QWpw4-0005qa-6o@ra.coresystems.de>

the following patch was just integrated into master:
commit cb82c6bf099b09706d88bb4b7bc9e1363bafd05e
Author: Sven Schnelle <svens at stackframe.org>
Date:   Wed Jun 15 09:26:34 2011 +0200

    i82801gx: replace cafed00d/cafebabe by defines
    
    We're using '0xcafed00d' all over the code as magic for ACPI S3
    resume. Let's add a define for that. Also replace 0xcafebabe by
    a define.
    
    Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/33 for details.

-gerrit



From gerrit at coreboot.org  Wed Jun 15 15:38:12 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Wed, 15 Jun 2011 15:38:12 +0200
Subject: [coreboot] New patch to review: bcfeb89 SMM: don't overwrite SMM
	memory on resume
Message-ID: <E1QWqIO-0005QG-H1@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/34

-gerrit

commit bcfeb894551d4858d301ce5a51eded851d57629e
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jun 14 20:55:54 2011 +0200

    SMM: don't overwrite SMM memory on resume
    
    Overwriting the SMM Area on resume leaves us with
    all variables cleared out, i.e., the GNVS pointer
    is no longer available, which makes SMIF function
    calls impossible.
    
    Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/cpu/x86/smm/smihandler.c                |    2 +-
 src/include/cpu/x86/smm.h                   |    1 +
 src/southbridge/intel/i82801gx/smi.c        |   28 +++++++++++++++++++++-----
 src/southbridge/intel/i82801gx/smihandler.c |    7 ++++++
 4 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index bdaedf8..d44a3ea 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -46,7 +46,7 @@ static int smi_obtain_lock(void)
 	return (ret == SMI_UNLOCKED);
 }
 
-static void smi_release_lock(void)
+void smi_release_lock(void)
 {
 	asm volatile (
 		"movb %1, %%al\n"
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 5605453..07a9cae 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -272,3 +272,4 @@ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_
 
 void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
 int __attribute__((weak)) mainboard_apm_cnt(u8 data);
+void smi_release_lock(void);
diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c
index 95ec112..5be2404 100644
--- a/src/southbridge/intel/i82801gx/smi.c
+++ b/src/southbridge/intel/i82801gx/smi.c
@@ -320,6 +320,16 @@ static void smm_relocate(void)
 
 static int smm_handler_copied = 0;
 
+static int is_wakeup(void)
+{
+	device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
+
+	if (!dev0)
+		return 0;
+
+	return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC;
+}
+
 static void smm_install(void)
 {
 	/* The first CPU running this gets to copy the SMM handler. But not all
@@ -329,13 +339,19 @@ static void smm_install(void)
 		return;
 	smm_handler_copied = 1;
 
-	/* enable the SMM memory window */
-	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
-				D_OPEN | G_SMRAME | C_BASE_SEG);
 
-	/* copy the real SMM handler */
-	memcpy((void *)0xa0000, &_binary_smm_start, (size_t)&_binary_smm_size);
-	wbinvd();
+	/* if we're resuming from S3, the SMM code is already in place,
+	 * so don't copy it again to keep the current SMM state */
+
+	if (!is_wakeup()) {
+		/* enable the SMM memory window */
+		pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+					D_OPEN | G_SMRAME | C_BASE_SEG);
+
+		/* copy the real SMM handler */
+		memcpy((void *)0xa0000, &_binary_smm_start, (size_t)&_binary_smm_size);
+		wbinvd();
+	}
 
 	/* close the SMM memory window and enable normal SMM */
 	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 9befbf9..434bfeb 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -328,6 +328,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 	default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
 	}
 
+	/* Unlock the SMI semaphore. We're currently in SMM, and the semaphore
+	 * will never be unlocked because the next outl will switch off the CPU.
+	 * This might open a small race between the smi_release_lock() and the outl()
+	 * for other SMI handlers. Not sure if this could cause trouble. */
+	 if (slp_typ == 5)
+		smi_release_lock();
+
 	/* Write back to the SLP register to cause the originally intended
 	 * event again. We need to set BIT13 (SLP_EN) though to make the
 	 * sleep happen.



From gerrit at coreboot.org  Wed Jun 15 16:03:20 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Wed, 15 Jun 2011 16:03:20 +0200
Subject: [coreboot] Patch set updated: 412e186 i945 GMA: restore tft
	brightness from cmos
Message-ID: <E1QWqgi-0006VB-QG@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/24

-gerrit

commit 412e18612707f6251f933a67b31dedb0cfe7933f
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 14:30:10 2011 +0200

    i945 GMA: restore tft brightness from cmos
    
    Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/t60/romstage.c |    2 --
 src/mainboard/lenovo/x60/romstage.c |    2 --
 src/northbridge/intel/i945/gma.c    |    7 +++++++
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index aa92765..252ae40 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -336,6 +336,4 @@ void main(unsigned long bist)
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
-	/* Set legacy Brightness control to full brightness */
-	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
 }
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index c993a35..2aa506f 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -338,6 +338,4 @@ void main(unsigned long bist)
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
-	/* Set legacy Brightness control to full brightness */
-	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
 }
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index a43ef25..340ddcd 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -21,6 +21,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
 
 static void gma_func0_init(struct device *dev)
 {
@@ -36,11 +37,17 @@ static void gma_func0_init(struct device *dev)
 static void gma_func1_init(struct device *dev)
 {
 	u32 reg32;
+	u8 val;
 
 	/* IGD needs to be Bus Master, also enable IO accesss */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 |
 			PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+	if (!get_option(&val, "tft_brightness"))
+		pci_write_config8(dev, 0xf4, val);
+	else
+		pci_write_config8(dev, 0xf4, 0xff);
 }
 
 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)



From gerrit at coreboot.org  Wed Jun 15 16:07:17 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Wed, 15 Jun 2011 16:07:17 +0200
Subject: [coreboot] Patch set updated: 686382c i945 GMA: restore tft
	brightness from cmos
Message-ID: <E1QWqkX-0006GE-5m@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/24

-gerrit

commit 686382c6e10ed8d78ce92e87c6496ccb55b3cc2b
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 14:30:10 2011 +0200

    i945 GMA: restore tft brightness from cmos
    
    Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/t60/devicetree.cb |    2 +-
 src/mainboard/lenovo/t60/romstage.c    |    2 --
 src/mainboard/lenovo/x60/devicetree.cb |    2 +-
 src/mainboard/lenovo/x60/romstage.c    |    2 --
 src/northbridge/intel/i945/chip.h      |    1 +
 src/northbridge/intel/i945/gma.c       |   13 ++++++++++++-
 6 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 5419d71..73b9a9f 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -21,7 +21,7 @@
 ##
 
 chip northbridge/intel/i945
-
+	register "tft_present" = "1"
 	device lapic_cluster 0 on
 		chip cpu/intel/socket_mFCPGA478
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index aa92765..252ae40 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -336,6 +336,4 @@ void main(unsigned long bist)
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
-	/* Set legacy Brightness control to full brightness */
-	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
 }
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 42a45d1..887a6db 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -21,7 +21,7 @@
 ##
 
 chip northbridge/intel/i945
-
+	register "tft_present" = "1"
 	device lapic_cluster 0 on
 		chip cpu/intel/socket_mFCPGA478
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index c993a35..2aa506f 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -338,6 +338,4 @@ void main(unsigned long bist)
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
-	/* Set legacy Brightness control to full brightness */
-	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
 }
diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h
index 6c51394..80b4202 100644
--- a/src/northbridge/intel/i945/chip.h
+++ b/src/northbridge/intel/i945/chip.h
@@ -18,6 +18,7 @@
  */
 
 struct northbridge_intel_i945_config {
+	int tft_present;
 };
 
 extern struct chip_operations northbridge_intel_i945_ops;
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index a43ef25..9c79cda 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -21,6 +21,8 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include "chip.h"
 
 static void gma_func0_init(struct device *dev)
 {
@@ -35,13 +37,22 @@ static void gma_func0_init(struct device *dev)
 
 static void gma_func1_init(struct device *dev)
 {
+	struct northbridge_intel_i945_config *config = dev->chip_info;
 	u32 reg32;
+	u8 val;
 
 	/* IGD needs to be Bus Master, also enable IO accesss */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 |
 			PCI_COMMAND_MASTER | PCI_COMMAND_IO);
-}
+
+	if (config->tft_present) {
+		if (!get_option(&val, "tft_brightness"))
+			pci_write_config8(dev, 0xf4, val);
+		else
+			pci_write_config8(dev, 0xf4, 0xff);
+		}
+	}
 
 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {



From gerrit at coreboot.org  Wed Jun 15 16:10:02 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Wed, 15 Jun 2011 16:10:02 +0200
Subject: [coreboot] Patch set updated: f8059c6 i945 GMA: restore tft
	brightness from cmos
Message-ID: <E1QWqnC-00033Q-QA@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/24

-gerrit

commit f8059c6546bfbed2f122c90c5a33096afedd6a02
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 14:30:10 2011 +0200

    i945 GMA: restore tft brightness from cmos
    
    Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/t60/devicetree.cb |    2 +-
 src/mainboard/lenovo/t60/romstage.c    |    2 --
 src/mainboard/lenovo/x60/devicetree.cb |    2 +-
 src/mainboard/lenovo/x60/romstage.c    |    2 --
 src/northbridge/intel/i945/chip.h      |    1 +
 src/northbridge/intel/i945/gma.c       |   13 ++++++++++++-
 6 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 5419d71..73b9a9f 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -21,7 +21,7 @@
 ##
 
 chip northbridge/intel/i945
-
+	register "tft_present" = "1"
 	device lapic_cluster 0 on
 		chip cpu/intel/socket_mFCPGA478
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index aa92765..252ae40 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -336,6 +336,4 @@ void main(unsigned long bist)
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
-	/* Set legacy Brightness control to full brightness */
-	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
 }
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 42a45d1..887a6db 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -21,7 +21,7 @@
 ##
 
 chip northbridge/intel/i945
-
+	register "tft_present" = "1"
 	device lapic_cluster 0 on
 		chip cpu/intel/socket_mFCPGA478
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index c993a35..2aa506f 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -338,6 +338,4 @@ void main(unsigned long bist)
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
-	/* Set legacy Brightness control to full brightness */
-	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
 }
diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h
index 6c51394..80b4202 100644
--- a/src/northbridge/intel/i945/chip.h
+++ b/src/northbridge/intel/i945/chip.h
@@ -18,6 +18,7 @@
  */
 
 struct northbridge_intel_i945_config {
+	int tft_present;
 };
 
 extern struct chip_operations northbridge_intel_i945_ops;
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index a43ef25..30f8340 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -21,6 +21,8 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include "chip.h"
 
 static void gma_func0_init(struct device *dev)
 {
@@ -35,13 +37,22 @@ static void gma_func0_init(struct device *dev)
 
 static void gma_func1_init(struct device *dev)
 {
+	struct northbridge_intel_i945_config *config = dev->chip_info;
 	u32 reg32;
+	u8 val;
 
 	/* IGD needs to be Bus Master, also enable IO accesss */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 |
 			PCI_COMMAND_MASTER | PCI_COMMAND_IO);
-}
+
+	if (config && config->tft_present) {
+		if (!get_option(&val, "tft_brightness"))
+			pci_write_config8(dev, 0xf4, val);
+		else
+			pci_write_config8(dev, 0xf4, 0xff);
+		}
+	}
 
 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {



From gerrit at coreboot.org  Wed Jun 15 17:44:57 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Wed, 15 Jun 2011 17:44:57 +0200
Subject: [coreboot] New patch to review: 09d29a9 Remove old ACPI code
Message-ID: <E1QWsH3-0000d2-4H@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/35

-gerrit

commit 09d29a9a8cff248ff3eb64b532ab61ee978511e7
Author: Sven Schnelle <svens at stackframe.org>
Date:   Wed Jun 15 17:13:27 2011 +0200

    Remove old ACPI code
    
    it isn't used anywhere, and could be fetched from git/svn history if
    needed.
    
    Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/intel/d945gclf/acpi_tables.c |   93 ----------------------------
 src/mainboard/lenovo/t60/acpi_tables.c     |   55 ----------------
 src/mainboard/lenovo/x60/acpi_tables.c     |   55 ----------------
 src/mainboard/roda/rk886ex/acpi_tables.c   |   55 ----------------
 4 files changed, 0 insertions(+), 258 deletions(-)

diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c
index 1e8ea29..bc0a790 100644
--- a/src/mainboard/intel/d945gclf/acpi_tables.c
+++ b/src/mainboard/intel/d945gclf/acpi_tables.c
@@ -30,84 +30,13 @@
 #include <arch/ioapic.h>
 #include "dmi.h"
 
-#define OLD_ACPI 0
-
 extern const unsigned char AmlCode[];
 #if CONFIG_HAVE_ACPI_SLIC
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#if OLD_ACPI
-typedef struct acpi_oemb {
-	acpi_header_t header;
-	u8  ss;
-	u16 iost;
-	u32 topm;
-	u32 roms;
-	u32 mg1b;
-	u32 mg1l;
-	u32 mg2b;
-	u32 mg2l;
-	u8  rsvd;
-	u8  dmax;
-	u32 hpta;
-	u32 cpb0;
-	u32 cpb1;
-	u32 cpb2;
-	u32 cpb3;
-	u8  assb;
-	u8  aotb;
-	u32 aaxb;
-	u8  smif;
-	u8  dtse;
-	u8  dts1;
-	u8  dts2;
-	u8  mpen;
-} __attribute__((packed)) acpi_oemb_t;
-#endif
-
 #include "southbridge/intel/i82801gx/nvs.h"
 
-#if OLD_ACPI
-static void acpi_create_oemb(acpi_oemb_t *oemb)
-{
-	acpi_header_t *header = &(oemb->header);
-	unsigned long tolud;
-
-	memset (oemb, 0, sizeof(*oemb));
-
-	/* fill out header fields */
-	memcpy(header->signature, "OEMB", 4);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-
-	header->length = sizeof(acpi_oemb_t);
-	header->revision = 1;
-
-	oemb->ss   =   0x09; // ss1 + ss 4
-	oemb->iost = 0x0403; // ??
-
-        tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
-	oemb->topm = tolud;
-
-	oemb->roms = 0xfff00000; // 1M hardcoded
-
-	oemb->mg1b = 0x000d0000;
-	oemb->mg1l = 0x00010000;
-
-	oemb->mg2b = tolud;
-	oemb->mg2l = 0-tolud;
-
-	oemb->dmax = 0x87;
-	oemb->hpta = 0x000e36c0;
-
-	header->checksum =
-	    acpi_checksum((void *) oemb, sizeof(acpi_oemb_t));
-
-};
-#endif
-
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));
@@ -202,9 +131,6 @@ unsigned long write_acpi_tables(unsigned long start)
 #if CONFIG_HAVE_ACPI_SLIC
 	acpi_header_t *slic;
 #endif
-#if OLD_ACPI
-	acpi_oemb_t *oemb;
-#endif
 	acpi_header_t *ssdt;
 	acpi_header_t *dsdt;
 
@@ -256,15 +182,6 @@ unsigned long write_acpi_tables(unsigned long start)
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, mcfg);
 
-#if OLD_ACPI
-	printk(BIOS_DEBUG, "ACPI:    * OEMB\n");
-	oemb=(acpi_oemb_t *)current;
-	current += sizeof(acpi_oemb_t);
-	ALIGN_CURRENT;
-	acpi_create_oemb(oemb);
-	acpi_add_table(rsdp, oemb);
-#endif
-
 	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
@@ -276,16 +193,6 @@ unsigned long write_acpi_tables(unsigned long start)
 	current += dsdt->length;
 	memcpy(dsdt, &AmlCode, dsdt->length);
 
-#if OLD_ACPI
-	for (i=0; i < dsdt->length; i++) {
-		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBEEF) {
-			printk(BIOS_DEBUG, "ACPI: Patching up DSDT at offset 0x%04x -> 0x%08x\n", i, 0x24 + (u32)oemb);
-			*(u32*)(((u32)dsdt) + i) = 0x24 + (u32)oemb;
-			break;
-		}
-	}
-#endif
-
 	ALIGN_CURRENT;
 
 	/* Pack GNVS into the ACPI table area */
diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c
index d9275b5..3742c20 100644
--- a/src/mainboard/lenovo/t60/acpi_tables.c
+++ b/src/mainboard/lenovo/t60/acpi_tables.c
@@ -36,61 +36,6 @@ extern const unsigned char AmlCode[];
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#define OLD_ACPI 0
-#if OLD_ACPI
-static void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	memset (gnvs, 0, sizeof(global_nvs_t));
-
-	gnvs->LIDS = 1;
-	gnvs->PWRS = 1;
-
-	gnvs->ACTT = 0x37;
-	gnvs->PSVT = 0x4f;
-
-	gnvs->TC1V = 0x00;
-	gnvs->TC2V = 0x0a;
-	gnvs->TSPV = 0x02;
-
-	gnvs->CRTT = 0x77;
-
-	gnvs->B0SC = 0x54;
-	gnvs->APIC = 0x01;
-	gnvs->MPEN = 0x01;
-
-	gnvs->PPCM = 0x02;
-	gnvs->PCP0 = 0xbf;
-	gnvs->PCP1 = 0xbf;
-
-	gnvs->CMAP = 0x01;
-	gnvs->CMBP = 0x01;
-	gnvs->LT0  = 0x01;
-	gnvs->FDCP = 0x01;
-	gnvs->CMCP = 0x01;
-	gnvs->CMDP = 0x01;
-	gnvs->P2M  = 0x02;
-
-	gnvs->IGDS = 0x01;
-
-	gnvs->CADL = 0x09;
-	gnvs->PADL = 0x09;
-
-	gnvs->NDID = 3;
-	gnvs->DID1 = 0x80000100;
-	gnvs->DID2 = 0x80000240;
-	gnvs->DID3 = 0x80000410;
-	gnvs->DID4 = 0x80000410;
-	gnvs->DID5 = 0x00000005;
-
-	gnvs->ALAF = 0x64;
-	gnvs->LLOW = 0x2c;
-	gnvs->LHIH = 0x01;
-
-        // tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
-	// oemb->topm = tolud;
-}
-#endif
-
 #include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c
index d9275b5..3742c20 100644
--- a/src/mainboard/lenovo/x60/acpi_tables.c
+++ b/src/mainboard/lenovo/x60/acpi_tables.c
@@ -36,61 +36,6 @@ extern const unsigned char AmlCode[];
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#define OLD_ACPI 0
-#if OLD_ACPI
-static void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	memset (gnvs, 0, sizeof(global_nvs_t));
-
-	gnvs->LIDS = 1;
-	gnvs->PWRS = 1;
-
-	gnvs->ACTT = 0x37;
-	gnvs->PSVT = 0x4f;
-
-	gnvs->TC1V = 0x00;
-	gnvs->TC2V = 0x0a;
-	gnvs->TSPV = 0x02;
-
-	gnvs->CRTT = 0x77;
-
-	gnvs->B0SC = 0x54;
-	gnvs->APIC = 0x01;
-	gnvs->MPEN = 0x01;
-
-	gnvs->PPCM = 0x02;
-	gnvs->PCP0 = 0xbf;
-	gnvs->PCP1 = 0xbf;
-
-	gnvs->CMAP = 0x01;
-	gnvs->CMBP = 0x01;
-	gnvs->LT0  = 0x01;
-	gnvs->FDCP = 0x01;
-	gnvs->CMCP = 0x01;
-	gnvs->CMDP = 0x01;
-	gnvs->P2M  = 0x02;
-
-	gnvs->IGDS = 0x01;
-
-	gnvs->CADL = 0x09;
-	gnvs->PADL = 0x09;
-
-	gnvs->NDID = 3;
-	gnvs->DID1 = 0x80000100;
-	gnvs->DID2 = 0x80000240;
-	gnvs->DID3 = 0x80000410;
-	gnvs->DID4 = 0x80000410;
-	gnvs->DID5 = 0x00000005;
-
-	gnvs->ALAF = 0x64;
-	gnvs->LLOW = 0x2c;
-	gnvs->LHIH = 0x01;
-
-        // tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
-	// oemb->topm = tolud;
-}
-#endif
-
 #include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c
index d9275b5..3742c20 100644
--- a/src/mainboard/roda/rk886ex/acpi_tables.c
+++ b/src/mainboard/roda/rk886ex/acpi_tables.c
@@ -36,61 +36,6 @@ extern const unsigned char AmlCode[];
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#define OLD_ACPI 0
-#if OLD_ACPI
-static void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	memset (gnvs, 0, sizeof(global_nvs_t));
-
-	gnvs->LIDS = 1;
-	gnvs->PWRS = 1;
-
-	gnvs->ACTT = 0x37;
-	gnvs->PSVT = 0x4f;
-
-	gnvs->TC1V = 0x00;
-	gnvs->TC2V = 0x0a;
-	gnvs->TSPV = 0x02;
-
-	gnvs->CRTT = 0x77;
-
-	gnvs->B0SC = 0x54;
-	gnvs->APIC = 0x01;
-	gnvs->MPEN = 0x01;
-
-	gnvs->PPCM = 0x02;
-	gnvs->PCP0 = 0xbf;
-	gnvs->PCP1 = 0xbf;
-
-	gnvs->CMAP = 0x01;
-	gnvs->CMBP = 0x01;
-	gnvs->LT0  = 0x01;
-	gnvs->FDCP = 0x01;
-	gnvs->CMCP = 0x01;
-	gnvs->CMDP = 0x01;
-	gnvs->P2M  = 0x02;
-
-	gnvs->IGDS = 0x01;
-
-	gnvs->CADL = 0x09;
-	gnvs->PADL = 0x09;
-
-	gnvs->NDID = 3;
-	gnvs->DID1 = 0x80000100;
-	gnvs->DID2 = 0x80000240;
-	gnvs->DID3 = 0x80000410;
-	gnvs->DID4 = 0x80000410;
-	gnvs->DID5 = 0x00000005;
-
-	gnvs->ALAF = 0x64;
-	gnvs->LLOW = 0x2c;
-	gnvs->LHIH = 0x01;
-
-        // tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
-	// oemb->topm = tolud;
-}
-#endif
-
 #include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {



From gerrit at coreboot.org  Wed Jun 15 19:03:39 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 15 Jun 2011 19:03:39 +0200
Subject: [coreboot] Patch merged into master: 09d29a9 Remove old ACPI code
Message-ID: <E1QWtVD-0006DG-KL@ra.coresystems.de>

the following patch was just integrated into master:
commit 09d29a9a8cff248ff3eb64b532ab61ee978511e7
Author: Sven Schnelle <svens at stackframe.org>
Date:   Wed Jun 15 17:13:27 2011 +0200

    Remove old ACPI code
    
    it isn't used anywhere, and could be fetched from git/svn history if
    needed.
    
    Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/35 for details.

-gerrit



From gerrit at coreboot.org  Wed Jun 15 19:17:01 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Wed, 15 Jun 2011 19:17:01 +0200
Subject: [coreboot] Patch set updated: eaded8a i945 GMA: restore tft
	brightness from cmos
Message-ID: <E1QWti9-0005Oz-2P@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/24

-gerrit

commit eaded8a99aaf430d28b0ae3e01858a3d38fb8427
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 14:30:10 2011 +0200

    i945 GMA: restore tft brightness from cmos
    
    Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/t60/devicetree.cb |    1 -
 src/mainboard/lenovo/t60/romstage.c    |    2 --
 src/mainboard/lenovo/x60/devicetree.cb |    1 -
 src/mainboard/lenovo/x60/romstage.c    |    2 --
 src/northbridge/intel/i945/gma.c       |    7 +++++++
 5 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 5419d71..4de1be3 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -21,7 +21,6 @@
 ##
 
 chip northbridge/intel/i945
-
 	device lapic_cluster 0 on
 		chip cpu/intel/socket_mFCPGA478
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index aa92765..252ae40 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -336,6 +336,4 @@ void main(unsigned long bist)
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
-	/* Set legacy Brightness control to full brightness */
-	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
 }
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 42a45d1..1647f7a 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -21,7 +21,6 @@
 ##
 
 chip northbridge/intel/i945
-
 	device lapic_cluster 0 on
 		chip cpu/intel/socket_mFCPGA478
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index c993a35..2aa506f 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -338,6 +338,4 @@ void main(unsigned long bist)
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
-	/* Set legacy Brightness control to full brightness */
-	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
 }
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index a43ef25..340ddcd 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -21,6 +21,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
 
 static void gma_func0_init(struct device *dev)
 {
@@ -36,11 +37,17 @@ static void gma_func0_init(struct device *dev)
 static void gma_func1_init(struct device *dev)
 {
 	u32 reg32;
+	u8 val;
 
 	/* IGD needs to be Bus Master, also enable IO accesss */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 |
 			PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+	if (!get_option(&val, "tft_brightness"))
+		pci_write_config8(dev, 0xf4, val);
+	else
+		pci_write_config8(dev, 0xf4, 0xff);
 }
 
 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)



From gerrit at coreboot.org  Wed Jun 15 19:18:26 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Wed, 15 Jun 2011 19:18:26 +0200
Subject: [coreboot] Patch set updated: 645314c i945 GMA: restore tft
	brightness from cmos
Message-ID: <E1QWtjW-0007qJ-O7@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/24

-gerrit

commit 645314c5e045be3934c26654b87d474688454a0e
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 14:30:10 2011 +0200

    i945 GMA: restore tft brightness from cmos
    
    Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/t60/romstage.c |    2 --
 src/mainboard/lenovo/x60/romstage.c |    2 --
 src/northbridge/intel/i945/gma.c    |    7 +++++++
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index aa92765..252ae40 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -336,6 +336,4 @@ void main(unsigned long bist)
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
-	/* Set legacy Brightness control to full brightness */
-	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
 }
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index c993a35..2aa506f 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -338,6 +338,4 @@ void main(unsigned long bist)
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
-	/* Set legacy Brightness control to full brightness */
-	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
 }
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index a43ef25..340ddcd 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -21,6 +21,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
 
 static void gma_func0_init(struct device *dev)
 {
@@ -36,11 +37,17 @@ static void gma_func0_init(struct device *dev)
 static void gma_func1_init(struct device *dev)
 {
 	u32 reg32;
+	u8 val;
 
 	/* IGD needs to be Bus Master, also enable IO accesss */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 |
 			PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+	if (!get_option(&val, "tft_brightness"))
+		pci_write_config8(dev, 0xf4, val);
+	else
+		pci_write_config8(dev, 0xf4, 0xff);
 }
 
 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)



From gerrit at coreboot.org  Wed Jun 15 19:40:25 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 15 Jun 2011 19:40:25 +0200
Subject: [coreboot] Patch merged into master: 645314c i945 GMA: restore tft
	brightness from cmos
Message-ID: <E1QWu4n-0002co-GY@ra.coresystems.de>

the following patch was just integrated into master:
commit 645314c5e045be3934c26654b87d474688454a0e
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 12 14:30:10 2011 +0200

    i945 GMA: restore tft brightness from cmos
    
    Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/24 for details.

-gerrit



From dhendrix at google.com  Wed Jun 15 20:25:01 2011
From: dhendrix at google.com (David Hendricks)
Date: Wed, 15 Jun 2011 11:25:01 -0700
Subject: [coreboot] gerrit: patch iterations in email [was: differences
 between patchset iterations]
In-Reply-To: <1308141502.8425.12.camel@kubuntu>
References: <E1QUEWz-0005eg-7x@ra.coresystems.de>
	<1307531104.4193.12.camel@mattotaupa>
	<20110609001625.20477.qmail@stuge.se>
	<BANLkTimHDf7C4hBA68bvL3YRsncSi90SHLwHosPjCpFZc1RUJw@mail.gmail.com>
	<20110609163935.GC18563@greenwood> <1308141502.8425.12.camel@kubuntu>
Message-ID: <BANLkTikJmXOH0rYwfv9jw+=WJNoc692z9V+CMA-G0_VkxN6anA@mail.gmail.com>

On Wed, Jun 15, 2011 at 5:38 AM, Patrick Georgi <patrick at georgi-clan.de>wrote:

> Am Donnerstag, den 09.06.2011, 18:39 +0200 schrieb Uwe Hermann:
> > I'd prefer to see all changes for all issues on the mailing list, I don't
> > think I want to go to the web interface for every new patch submission
> > someone does and add myself there just in order to get the notifications.
> Back again.
>

Is there an option to keep all these related updates and merges in a single
thread, ie do not display the patch's hash in the subject: line? Shortly
after patch update notifications to the list were re-enabled, three updates
to "i945 GMA: restore tft brightness from cmos" spawned three different
threads within the span of 10 minutes. It has the same effect on my gmail
inbox as it does on the mailing list archive.

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From marcj303 at gmail.com  Wed Jun 15 21:32:45 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 15 Jun 2011 13:32:45 -0600
Subject: [coreboot] gerrit patch email content
In-Reply-To: <1308141585.8425.14.camel@kubuntu>
References: <BANLkTinsC3XGZUR1a5xq3-PdR_q1ynkd1w@mail.gmail.com>
	<1308141585.8425.14.camel@kubuntu>
Message-ID: <BANLkTi=Y_PMXfMrT+CyHphycjH21pJO9VQ@mail.gmail.com>

On Wed, Jun 15, 2011 at 6:39 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am Freitag, den 10.06.2011, 09:44 -0600 schrieb Marc Jones:
>> It would be nice if gerrit would send the entire commit message and
>> the list of files in the patch emails. That would be helpful in
>> parsing what patches require attention.
> It's "git show -p --stat" (commit message, diffstat, patch content) now,
> inlined instead of as attachment. That should do what you want, right?
>

I think just "git show --stat". i think that the patch content is good
as an attachment.  I think that is what the merge email does.

Marc




-- 
http://se-eng.com



From gerrit at coreboot.org  Wed Jun 15 23:11:44 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 15 Jun 2011 23:11:44 +0200
Subject: [coreboot] Patch merged into master: bcfeb89 SMM: don't overwrite
	SMM memory on resume
Message-ID: <E1QWxNI-0007zb-RP@ra.coresystems.de>

the following patch was just integrated into master:
commit bcfeb894551d4858d301ce5a51eded851d57629e
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jun 14 20:55:54 2011 +0200

    SMM: don't overwrite SMM memory on resume
    
    Overwriting the SMM Area on resume leaves us with
    all variables cleared out, i.e., the GNVS pointer
    is no longer available, which makes SMIF function
    calls impossible.
    
    Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/34 for details.

-gerrit



From gerrit at coreboot.org  Thu Jun 16 02:33:00 2011
From: gerrit at coreboot.org (Cristian Măgherușan-Stanciu (cristi.magherusan@gmail.com))
Date: Thu, 16 Jun 2011 02:33:00 +0200
Subject: [coreboot] New patch to review: fa59d35 ACPI cleanup proposal
Message-ID: <E1QX0W4-0005KM-Ae@ra.coresystems.de>

Cristian M?gheru?an-Stanciu (cristi.magherusan at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/36

-gerrit

commit fa59d35dc23c02c325f5de5976c327595441a380
Author: Cristian M?gheru?an-Stanciu <cristi.magherusan at gmail.com>
Date:   Thu Jun 16 02:12:55 2011 +0200

    ACPI cleanup proposal
    
    This is the evolution of the patch I sent a couple of weeks ago about
    ACPI code cleanup/deduplication, done during the hackathon in Prague.
    
    The current version should in theory support most of the AMD and i945
    motherboards, but I only ported it to two boards as a reference
    implementation.
    
    Compilation is known to fail in case of the motherboards where we
    don't automatically generate the ACPI SSDT table. This should be
    fixed on a per-motherboard basis.
    
    It wasn't yet tested on real hardware, so there's a high chance to
    be broken in the current state even on those supported boards.
    
    Change-Id: Ie6296f5652196c6258aa6902d84dd86c17e224cb
    Signed-off-by: Cristian M?gheru?an-Stanciu <cristi.magherusan at gmail.com>
---
 src/Kconfig                                |   17 ++
 src/arch/x86/boot/acpi.c                   |  278 ++++++++++++++++++++++++++--
 src/arch/x86/include/arch/acpi.h           |   16 ++-
 src/mainboard/asus/m2v-mx_se/acpi_tables.c |  100 +----------
 src/mainboard/lenovo/t60/acpi_tables.c     |  194 ++-----------------
 5 files changed, 312 insertions(+), 293 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 9abbc21..1eb3fb4 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -645,6 +645,23 @@ config DEBUG_MALLOC
 	  If unsure, say N.
 endif
 
+config DEBUG_ACPI
+	def_bool n
+
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+config DEBUG_ACPI
+	bool "Output verbose ACPI debug messages"
+	default n
+	help
+	  This option enables additional ACPI related debug messages.
+
+	  Note: This option will slightly increase the size of the coreboot image.
+
+	  If unsure, say N.
+endif
+
 config REALMODE_DEBUG
 	def_bool n
 	depends on PCI_OPTION_ROM_RUN_REALMODE
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index 957ec45..ee9d2ac 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -16,13 +16,15 @@
  */
 
 /*
- * Each system port implementing ACPI has to provide two functions:
- *
- *   write_acpi_tables()
- *   acpi_dump_apics()
- *
- * See Kontron 986LCD-M port for a good example of an ACPI implementation
- * in coreboot.
+ * Currently each system port implementing ACPI has to provide the following functions:
+ * - acpi_fill_mcfg()
+ * - acpi_fill_madt()
+ * - acpi_fill_slit()
+ * - acpi_fill_srat()
+ * - acpi_fill_ssdt_generator()
+ * Optional
+ * - acpi_patch_dsdt()
+ * - acpi_dmi_workaround()
  */
 
 #include <console/console.h>
@@ -69,7 +71,7 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table)
 
 	if (i >= entries_num) {
 		printk(BIOS_ERR, "ACPI: Error: Could not add ACPI table, "
-		       "too many tables.\n");
+			"too many tables.\n");
 		return;
 	}
 
@@ -93,20 +95,20 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table)
 
 		/* Fix XSDT length. */
 		xsdt->header.length = sizeof(acpi_header_t) +
-				      (sizeof(u64) * (i + 1));
+					(sizeof(u64) * (i + 1));
 
 		/* Re-calculate checksum. */
 		xsdt->header.checksum = 0;
 		xsdt->header.checksum = acpi_checksum((u8 *)xsdt,
-						      xsdt->header.length);
+							xsdt->header.length);
 	}
 
 	printk(BIOS_DEBUG, "ACPI: added table %d/%d, length now %d\n",
-	       i + 1, entries_num, rsdt->header.length);
+		i + 1, entries_num, rsdt->header.length);
 }
 
 int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base,
-			      u16 seg_nr, u8 start, u8 end)
+				u16 seg_nr, u8 start, u8 end)
 {
 	mmconfig->base_address = base;
 	mmconfig->base_reserved = 0;
@@ -135,7 +137,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
 
 	for (cpu = all_devices; cpu; cpu = cpu->next) {
 		if ((cpu->path.type != DEVICE_PATH_APIC) ||
-		   (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
+			(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
 			continue;
 		}
 		if (!cpu->enabled)
@@ -149,7 +151,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
 }
 
 int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,
-			    u32 gsi_base)
+				u32 gsi_base)
 {
 	ioapic->type = 1; /* I/O APIC structure */
 	ioapic->length = sizeof(acpi_madt_ioapic_t);
@@ -175,7 +177,7 @@ int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride,
 }
 
 int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu,
-			       u16 flags, u8 lint)
+				u16 flags, u8 lint)
 {
 	lapic_nmi->type = 4; /* Local APIC NMI structure */
 	lapic_nmi->length = sizeof(acpi_madt_lapic_nmi_t);
@@ -243,11 +245,26 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg)
  * This can be overriden by platform ACPI setup code, if it calls
  * acpi_create_ssdt_generator().
  */
+/* let's enforce the implementation of the DSDT generator in the motherboard code*/
+#if 0
 unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(
 			unsigned long current, const char *oem_table_id)
 {
 	return current;
 }
+#endif
+
+/* stub functions that might be implemented in the mainboard code, if needed */
+void __attribute__((weak)) acpi_patch_dsdt(
+			acpi_header_t *dsdt, unsigned long *current)
+{
+}
+
+void __attribute__((weak)) acpi_dmi_workaround(unsigned long *current)
+{
+}
+
+
 
 void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
 {
@@ -287,7 +304,7 @@ int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic)
 }
 
 int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek,
-			 u32 flags)
+				u32 flags)
 {
 	mem->type = 1; /* Memory affinity structure */
 	mem->length = sizeof(acpi_srat_mem_t);
@@ -376,9 +393,20 @@ void acpi_create_hpet(acpi_hpet_t *hpet)
 	addr->addrl = HPET_ADDR & 0xffffffff;
 	addr->addrh = HPET_ADDR >> 32;
 
-	hpet->id = 0x102282a0; /* AMD! FIXME */
+	/* XXX: Add other vendors */
+#if CONFIG_VENDOR_INTEL
+	hpet->id = 0x8086a201;
+	hpet->min_tick = 0x80;
+#endif
+#if CONFIG_VENDOR_AMD
+	hpet->id = 0x102282a0;
+	hpet->min_tick = 0x1000;
+#endif
+#if CONFIG_VENDOR_VIA
+	hpet->id = 0x11068201;
+	hpet->min_tick = 0x90;
+#endif
 	hpet->number = 0;
-	hpet->min_tick = 4096;
 
 	header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t));
 }
@@ -465,6 +493,220 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt)
 	rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t));
 }
 
+
+
+void acpi_write_dsdt(acpi_header_t *dsdt, const unsigned char AmlCode[], unsigned long *current)
+{
+	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", *current);
+	dsdt = (acpi_header_t *) *current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	*current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	*current = ALIGN(*current, 64);
+
+	acpi_patch_dsdt(dsdt, current);
+
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+}
+
+void acpi_write_facs(acpi_facs_t *facs, unsigned long *current)
+{
+	/* FACS */ // it needs 64 bit alignment
+	printk(BIOS_DEBUG, "ACPI:       * FACS at %lx\n", *current);
+	facs = (acpi_facs_t *) *current; // it will be used by fadt
+	*current += sizeof(acpi_facs_t);
+	*current = ALIGN(*current, 64);
+	acpi_create_facs(facs);
+}
+
+
+void acpi_write_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, acpi_header_t *dsdt, acpi_rsdp_t *rsdp, unsigned long *current)
+{
+	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", *current);
+	fadt = (acpi_fadt_t *) *current;
+	*current += sizeof(acpi_fadt_t);
+	*current = ALIGN(*current, 64);
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+}
+
+void acpi_write_hpet(acpi_hpet_t *hpet, acpi_rsdp_t *rsdp, unsigned long *current)
+{
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", *current);
+	hpet = (acpi_hpet_t *) *current;
+	*current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	*current = ALIGN(*current, 64);
+	acpi_add_table(rsdp, hpet);
+}
+
+void acpi_write_madt(acpi_madt_t *madt, acpi_rsdp_t *rsdp, unsigned long *current)
+{
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n", *current);
+	madt = (acpi_madt_t *) *current;
+	acpi_create_madt(madt);
+	*current += madt->header.length;
+	*current = ALIGN(*current, 64);
+	acpi_add_table(rsdp, madt);
+}
+
+void acpi_write_srat(acpi_srat_t *srat, acpi_rsdp_t *rsdp, unsigned long *current)
+{
+	*current = ALIGN(*current, 64);
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", *current);
+	srat = (acpi_srat_t *) *current;
+	acpi_create_srat(srat);
+	*current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+}
+
+void acpi_write_slit(acpi_slit_t *slit, acpi_rsdp_t *rsdp, unsigned long *current)
+{
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", *current);
+	slit = (acpi_slit_t *) *current;
+	acpi_create_slit(slit);
+	*current += slit->header.length;
+	*current = ALIGN(*current, 64);
+	acpi_add_table(rsdp, slit);
+}
+void acpi_write_mcfg(acpi_mcfg_t *mcfg, acpi_rsdp_t *rsdp, unsigned long *current)
+{
+	printk(BIOS_DEBUG, "ACPI:    * MCFG at %lx\n", *current);
+	mcfg = (acpi_mcfg_t *) *current;
+	acpi_create_mcfg(mcfg);
+	*current += mcfg->header.length;
+	*current = ALIGN(*current, 64);
+	acpi_add_table(rsdp, mcfg);
+}
+
+#if CONFIG_HAVE_ACPI_SLIC
+void acpi_write_slic(acpi_header_t *slic, acpi_rsdp_t *rsdp, unsigned long *current)
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)*current;
+	*current += acpi_create_slic(*current);
+	*current = ALIGN(*current, 64);
+	acpi_add_table(rsdp, slic);
+#endif
+
+
+void acpi_write_ssdt_generated(acpi_header_t *ssdt, acpi_rsdp_t *rsdp,  unsigned long *current)
+{
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
+	ssdt = (acpi_header_t *)*current;
+
+	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	*current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	*current = ALIGN(*current, 64);
+}
+
+
+#if CONFIG_DEBUG_ACPI == 1
+static void dump_mem(void *start, void *end)
+{
+	int i;
+	printk(BIOS_DEBUG,"dump_mem:");
+	for (i = (unsigned int)start; i < (unsigned int)end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", (unsigned int)i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	printk(BIOS_DEBUG,"\n");
+}
+#endif
+
+unsigned long acpi_write_tables(unsigned long start, const unsigned char AmlCode[])
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp = NULL;
+	acpi_srat_t *srat = NULL;
+	acpi_rsdt_t *rsdt = NULL;
+	acpi_mcfg_t *mcfg = NULL;
+	acpi_hpet_t *hpet = NULL;
+	acpi_madt_t *madt = NULL;
+	acpi_fadt_t *fadt = NULL;
+	acpi_facs_t *facs = NULL;
+	acpi_xsdt_t *xsdt = NULL;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic = NULL;
+#endif
+	acpi_slit_t *slit = NULL;
+	acpi_header_t *ssdt = NULL;
+	acpi_header_t *dsdt = NULL;
+
+	/* Align ACPI tables to 16 bytes */
+	start = ALIGN(start, 16);
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	
+	current = ALIGN(current, 64);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	current = ALIGN(current, 64);
+        xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	acpi_write_dsdt(dsdt, AmlCode , &current);
+
+	acpi_write_facs(facs, &current);
+	acpi_write_fadt(fadt, facs, dsdt, rsdp, &current);
+	acpi_write_hpet(hpet, rsdp, &current);
+
+	acpi_write_madt(madt, rsdp, &current);
+
+	acpi_write_mcfg(mcfg, rsdp, &current);
+
+	acpi_write_srat(srat, rsdp, &current);
+	acpi_write_slit(slit, rsdp, &current);
+
+
+	acpi_write_ssdt_generated(ssdt, rsdp, &current);
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+
+	acpi_dmi_workaround(&current);
+
+#if CONFIG_DEBUG_ACPI == 1
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
+
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
+
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
+
 #if CONFIG_HAVE_ACPI_RESUME == 1
 void suspend_resume(void)
 {
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 030745d..09de3a6 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -357,8 +357,9 @@ typedef struct acpi_ecdt {
 	u8 ec_id[];				/* EC ID  */
 } __attribute__ ((packed)) acpi_ecdt_t;
 
-/* These are implemented by the target port or north/southbridge. */
+/* This is implemented by the target port or north/southbridge. */
 unsigned long write_acpi_tables(unsigned long addr);
+
 unsigned long acpi_fill_madt(unsigned long current);
 unsigned long acpi_fill_mcfg(unsigned long current);
 unsigned long acpi_fill_srat(unsigned long current);
@@ -411,6 +412,19 @@ unsigned long acpi_create_slic(unsigned long current);
 void acpi_write_rsdt(acpi_rsdt_t *rsdt);
 void acpi_write_xsdt(acpi_xsdt_t *xsdt);
 void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt);
+void acpi_write_dsdt(acpi_header_t *dsdt, const unsigned char AmlCode[], unsigned long *current);
+void acpi_patch_dsdt(acpi_header_t *dsdt, unsigned long *current);
+void acpi_dmi_workaround(unsigned long *current);
+
+void acpi_write_facs(acpi_facs_t *facs, unsigned long *current);
+void acpi_write_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, acpi_header_t *dsdt, acpi_rsdp_t *rsdp, unsigned long *current);
+void acpi_write_hpet(acpi_hpet_t *hpet, acpi_rsdp_t *rsdp, unsigned long *current);
+void acpi_write_madt(acpi_madt_t *madt, acpi_rsdp_t *rsdp, unsigned long *current);
+void acpi_write_srat(acpi_srat_t *srat, acpi_rsdp_t *rsdp, unsigned long *current);
+void acpi_write_slit(acpi_slit_t *slit, acpi_rsdp_t *rsdp, unsigned long *current);
+void acpi_write_ssdt_generated(acpi_header_t *ssdt, acpi_rsdp_t *rsdp,  unsigned long *current);
+void acpi_write_mcfg(acpi_mcfg_t *mcfg, acpi_rsdp_t *rsdp, unsigned long *current);
+unsigned long acpi_write_tables(unsigned long start, const unsigned char AmlCode[]);
 
 #if CONFIG_HAVE_ACPI_RESUME
 /* 0 = S0, 1 = S1 ...*/
diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c
index 73e3768..1471ad9 100644
--- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c
+++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c
@@ -94,103 +94,5 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta
 
 unsigned long write_acpi_tables(unsigned long start)
 {
-	unsigned long current;
-	acpi_rsdp_t *rsdp;
-	acpi_srat_t *srat;
-	acpi_rsdt_t *rsdt;
-	acpi_mcfg_t *mcfg;
-	acpi_hpet_t *hpet;
-	acpi_madt_t *madt;
-	acpi_fadt_t *fadt;
-	acpi_facs_t *facs;
-	acpi_slit_t *slit;
-	acpi_header_t *ssdt;
-	acpi_header_t *dsdt;
-
-	/* Align ACPI tables to 16 byte. */
-	start = (start + 0x0f) & -0x10;
-	current = start;
-
-	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
-
-	/* We need at least an RSDP and an RSDT table. */
-	rsdp = (acpi_rsdp_t *) current;
-	current += sizeof(acpi_rsdp_t);
-	rsdt = (acpi_rsdt_t *) current;
-	current += sizeof(acpi_rsdt_t);
-
-	/* Clear all table memory. */
-	memset((void *) start, 0, current - start);
-
-	acpi_write_rsdp(rsdp, rsdt, NULL);
-	acpi_write_rsdt(rsdt);
-
-	/* We explicitly add these tables later on: */
-	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
-
-	/* we should align FACS to 64B as per ACPI specs */
-
-	current = ALIGN(current, 64);
-	facs = (acpi_facs_t *) current;
-	current += sizeof(acpi_facs_t);
-	acpi_create_facs(facs);
-
-	dsdt = (acpi_header_t *) current;
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	current += dsdt->length;
-	memcpy(dsdt, &AmlCode, dsdt->length);
-	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
-	dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
-	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
-		     dsdt->length);
-	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
-
-	fadt = (acpi_fadt_t *) current;
-	current += sizeof(acpi_fadt_t);
-
-	acpi_create_fadt(fadt, facs, dsdt);
-	acpi_add_table(rsdp, fadt);
-
-	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
-	hpet = (acpi_hpet_t *) current;
-	current += sizeof(acpi_hpet_t);
-	acpi_create_hpet(hpet);
-	acpi_add_table(rsdp, hpet);
-
-	/* If we want to use HPET timers Linux wants an MADT. */
-	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
-	madt = (acpi_madt_t *) current;
-	acpi_create_madt(madt);
-	current += madt->header.length;
-	acpi_add_table(rsdp, madt);
-
-	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
-	mcfg = (acpi_mcfg_t *) current;
-	acpi_create_mcfg(mcfg);
-	current += mcfg->header.length;
-	acpi_add_table(rsdp, mcfg);
-
-	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
-	srat = (acpi_srat_t *) current;
-	acpi_create_srat(srat);
-	current += srat->header.length;
-	acpi_add_table(rsdp, srat);
-
-	/* SLIT */
-        printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
-        slit = (acpi_slit_t *) current;
-        acpi_create_slit(slit);
-        current+=slit->header.length;
-        acpi_add_table(rsdp,slit);
-
-	/* SSDT */
-	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
-	ssdt = (acpi_header_t *)current;
-
-	acpi_create_ssdt_generator(ssdt, "DYNADATA");
-	current += ssdt->length;
-	acpi_add_table(rsdp, ssdt);
-
-	printk(BIOS_INFO, "ACPI: done.\n");
-	return current;
+	return acpi_write_tables(start, AmlCode);
 }
diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c
index 3742c20..4056e75 100644
--- a/src/mainboard/lenovo/t60/acpi_tables.c
+++ b/src/mainboard/lenovo/t60/acpi_tables.c
@@ -32,9 +32,6 @@
 #include "dmi.h"
 
 extern const unsigned char AmlCode[];
-#if CONFIG_HAVE_ACPI_SLIC
-unsigned long acpi_create_slic(unsigned long current);
-#endif
 
 #include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
@@ -56,38 +53,6 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->did[4] = 0x00000005;
 }
 
-static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
-{
-#define HPET_ADDR  0xfed00000ULL
-	acpi_header_t *header = &(hpet->header);
-	acpi_addr_t *addr = &(hpet->addr);
-
-	memset((void *) hpet, 0, sizeof(acpi_hpet_t));
-
-	/* fill out header fields */
-	memcpy(header->signature, "HPET", 4);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-
-	header->length = sizeof(acpi_hpet_t);
-	header->revision = 1;
-
-	/* fill out HPET address */
-	addr->space_id = 0;	/* Memory */
-	addr->bit_width = 64;
-	addr->bit_offset = 0;
-	addr->addrl = HPET_ADDR & 0xffffffff;
-	addr->addrh = HPET_ADDR >> 32;
-
-	hpet->id = 0x8086a201;	/* Intel */
-	hpet->number = 0x00;
-	hpet->min_tick = 0x0080;
-
-	header->checksum =
-	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
-}
-
 unsigned long acpi_fill_madt(unsigned long current)
 {
 	/* Local APICs */
@@ -136,129 +101,31 @@ unsigned long acpi_fill_srat(unsigned long current)
 
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
 
-#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
-unsigned long write_acpi_tables(unsigned long start)
+
+void acpi_patch_dsdt(acpi_header_t *dsdt, unsigned long *current)
 {
-	unsigned long current;
 	int i;
-	acpi_rsdp_t *rsdp;
-	acpi_rsdt_t *rsdt;
-	acpi_xsdt_t *xsdt;
-	acpi_hpet_t *hpet;
-	acpi_madt_t *madt;
-	acpi_mcfg_t *mcfg;
-	acpi_fadt_t *fadt;
-	acpi_facs_t *facs;
-#if CONFIG_HAVE_ACPI_SLIC
-	acpi_header_t *slic;
-#endif
-	acpi_header_t *ssdt;
-	acpi_header_t *dsdt;
 	void *gnvs;
 
-	current = start;
-
-	/* Align ACPI tables to 16byte */
-	ALIGN_CURRENT;
-
-	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
-
-	/* We need at least an RSDP and an RSDT Table */
-	rsdp = (acpi_rsdp_t *) current;
-	current += sizeof(acpi_rsdp_t);
-	ALIGN_CURRENT;
-	rsdt = (acpi_rsdt_t *) current;
-	current += sizeof(acpi_rsdt_t);
-	ALIGN_CURRENT;
-	xsdt = (acpi_xsdt_t *) current;
-	current += sizeof(acpi_xsdt_t);
-	ALIGN_CURRENT;
-
-	/* clear all table memory */
-	memset((void *) start, 0, current - start);
-
-	acpi_write_rsdp(rsdp, rsdt, xsdt);
-	acpi_write_rsdt(rsdt);
-	acpi_write_xsdt(xsdt);
-
-	/*
-	 * We explicitly add these tables later on:
-	 */
-	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
-
-	hpet = (acpi_hpet_t *) current;
-	current += sizeof(acpi_hpet_t);
-	ALIGN_CURRENT;
-	acpi_create_intel_hpet(hpet);
-	acpi_add_table(rsdp, hpet);
-
-	/* If we want to use HPET Timers Linux wants an MADT */
-	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
-
-	madt = (acpi_madt_t *) current;
-	acpi_create_madt(madt);
-	current += madt->header.length;
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, madt);
-
-	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
-	mcfg = (acpi_mcfg_t *) current;
-	acpi_create_mcfg(mcfg);
-	current += mcfg->header.length;
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, mcfg);
-
-	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
-	facs = (acpi_facs_t *) current;
-	current += sizeof(acpi_facs_t);
-	ALIGN_CURRENT;
-	acpi_create_facs(facs);
-
-	dsdt = (acpi_header_t *) current;
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	current += dsdt->length;
-	memcpy(dsdt, &AmlCode, dsdt->length);
-
-	/* Fix up global NVS region for SMI handler. The GNVS region lives
-	 * in the (high) table area. The low memory map looks like this:
-	 *
-	 * 0x00000000 - 0x000003ff	Real Mode IVT
-	 * 0x00000020 - 0x0000019c	Low MP Table (XXX conflict?)
-	 * 0x00000400 - 0x000004ff	BDA (somewhat unused)
-	 * 0x00000500 - 0x0000052f	Moved GDT
-	 * 0x00000530 - 0x00000b64	coreboot table
-	 * 0x0007c000 - 0x0007dfff	OS boot sector (unused?)
-	 * 0x0007e000 - 0x0007ffff	free to use (so no good for acpi+smi)
-	 * 0x00080000 - 0x0009fbff	usable ram
-	 * 0x0009fc00 - 0x0009ffff	EBDA (unused?)
-	 * 0x000a0000 - 0x000bffff	VGA memory
-	 * 0x000c0000 - 0x000cffff	VGA option rom
-	 * 0x000d0000 - 0x000dffff	free for other option roms?
-	 * 0x000e0000 - 0x000fffff	SeaBIOS? (conflict with low tables:)
-	 * 0x000f0000 - 0x000f03ff	PIRQ table
-	 * 0x000f0400 - 0x000f66??	ACPI tables
-	 * 0x000f66?? - 0x000f????	DMI tables
-	 */
-
-	ALIGN_CURRENT;
+	*current = ALIGN(*current, 64);
 
 	/* Pack GNVS into the ACPI table area */
 	for (i=0; i < dsdt->length; i++) {
 		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
-			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current);
-			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)*current);
+			*(u32*)(((u32)dsdt) + i) = *current; // 0x92 bytes
 			break;
 		}
 	}
 
 	/* And fill it */
-	acpi_create_gnvs((global_nvs_t *)current);
+	acpi_create_gnvs((global_nvs_t *)*current);
 
 	/* Keep pointer around */
-	gnvs = (void *)current;
+	gnvs = (void *)*current;
 
-	current += 0x100;
-	ALIGN_CURRENT;
+	*current += 0x100;
+	*current = ALIGN(*current, 64);
 
 	/* And tell SMI about it */
 	smm_setup_structures(gnvs, NULL, NULL);
@@ -266,48 +133,25 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* We patched up the DSDT, so we need to recalculate the checksum */
 	dsdt->checksum = 0;
 	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+}
 
-	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
-		     dsdt->length);
-
-#if CONFIG_HAVE_ACPI_SLIC
-	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
-	slic = (acpi_header_t *)current;
-	current += acpi_create_slic(current);
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, slic);
-#endif
-
-	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
-	fadt = (acpi_fadt_t *) current;
-	current += sizeof(acpi_fadt_t);
-	ALIGN_CURRENT;
-
-	acpi_create_fadt(fadt, facs, dsdt);
-	acpi_add_table(rsdp, fadt);
-
-	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
-	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, "COREBOOT");
-	current += ssdt->length;
-	acpi_add_table(rsdp, ssdt);
-	ALIGN_CURRENT;
-
-	printk(BIOS_DEBUG, "current = %lx\n", current);
-
+void acpi_dmi_workaround(unsigned long *current)
+{
 	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
 	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
 #if CONFIG_WRITE_HIGH_TABLES == 1
-	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
-	current += DMI_TABLE_SIZE;
-	ALIGN_CURRENT;
+	memcpy((void *)*current, dmi_table, DMI_TABLE_SIZE);
+	*current += DMI_TABLE_SIZE;
+	*current = ALIGN(*current, 64);
 #endif
 
-	printk(BIOS_INFO, "ACPI: done.\n");
+}
 
+unsigned long write_acpi_tables(unsigned long start)
+{
 	/* Enable Dummy DCC ON# for DVI */
 	printk(BIOS_DEBUG, "Laptop handling...\n");
 	outb(inb(0x60f) & ~(1 << 5), 0x60f);
 
-	return current;
+	return acpi_write_tables(start, AmlCode);
 }



From hamo.by at gmail.com  Thu Jun 16 15:50:33 2011
From: hamo.by at gmail.com (Hamo)
Date: Thu, 16 Jun 2011 21:50:33 +0800
Subject: [coreboot] Questions about CBFS
Message-ID: <BANLkTinwgx1S1A2a3sp9AbrvpMJCaWEr1A@mail.gmail.com>

Dear list,
Hi all. Here I come again. ^_^ This time, There are 2 questions about CBFS.
1. When we create the rom file, we covert all address and size from
LSB to MSB using htonl, and when we use them in the rom, we covert
them to LSB. Why we do this? Is it necessary or historical or
something else? Since ARM don't have an instruction like BSWAP in X86
(or I don't know it), it is not easy to covert a register from LSB to
MSB or vice versa.
2. What's the purpose of tryharder in src/arch/x86/lib/walkcbfs.S? In
my opinion, After we found a 'LARCHIVE', we can just compare the name
with the target name. If they are the same, OK, we got it and we can
jump to it, If not, we should jump to searchfile to find the next CBFS
component.

Thanks,
Hamo



From gerrit at coreboot.org  Thu Jun 16 16:46:43 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Thu, 16 Jun 2011 16:46:43 +0200
Subject: [coreboot] New patch to review: 5ec011a Lenovo H8 EC: add
	usb_power_enable()
Message-ID: <E1QXDqF-0002mi-1I@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/37

-gerrit

commit 5ec011a230a23bdc51e2c37c0b799cb44560fb6f
Author: Sven Schnelle <svens at stackframe.org>
Date:   Thu Jun 16 16:43:04 2011 +0200

    Lenovo H8 EC: add usb_power_enable()
    
    Can be used to disable/enable Power output on USB ports.
    
    Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/ec/lenovo/h8/acpi/ec.asl |    8 ++++++++
 src/ec/lenovo/h8/h8.c        |    9 +++++++++
 src/ec/lenovo/h8/h8.h        |    1 +
 3 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
index 0bcf441..3ba4aa9 100644
--- a/src/ec/lenovo/h8/acpi/ec.asl
+++ b/src/ec/lenovo/h8/acpi/ec.asl
@@ -40,6 +40,8 @@ Device(EC)
 		Offset (0x3B),
 				    , 1,
 				KBLT, 1,        /* Keyboard Light */
+				    , 2,
+				USPW, 1,	/* USB Power enable */
 		Offset (0x4e),
 		               WAKE, 16,
 		Offset (0x78),
@@ -73,6 +75,12 @@ Device(EC)
 		Store(Arg0, AMUT)
 	}
 
+	Method (USBP, 1, NotSerialized)
+	{
+		Store(Arg0, USPW)
+	}
+
+
 	/* Sleep Button pressed */
 	Method(_Q13, 0, NotSerialized)
 	{
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index ef308b1..2c25d29 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -88,6 +88,14 @@ void h8_disable_event(int event)
 
 }
 
+void h8_usb_power_enable(int onoff)
+{
+	if (onoff)
+		ec_set_bit(0x3b, 4);
+	else
+		ec_clr_bit(0x3b, 4);
+}
+
 int h8_ultrabay_device_present(void)
 {
 	return ec_read(H8_STATUS1) & 0x5 ? 0 : 1;
@@ -129,6 +137,7 @@ static void h8_enable(device_t dev)
 	ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO);
 	h8_wlan_enable(conf->wlan_enable);
 	h8_trackpoint_enable(conf->trackpoint_enable);
+	h8_usb_power_enable(1);
 
 	if (!get_option(&val, "volume"))
 		ec_write(H8_VOLUME_CONTROL, val);
diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h
index c87ace4..717c0ce 100644
--- a/src/ec/lenovo/h8/h8.h
+++ b/src/ec/lenovo/h8/h8.h
@@ -23,6 +23,7 @@
 void h8_trackpoint_enable(int on);
 void h8_wlan_enable(int on);
 void h8_set_audio_mute(int on);
+void h8_usb_power_enable(int on);
 void h8_enable_event(int event);
 void h8_disable_event(int event);
 int h8_ultrabay_device_present(void);



From gerrit at coreboot.org  Thu Jun 16 16:46:43 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Thu, 16 Jun 2011 16:46:43 +0200
Subject: [coreboot] New patch to review: b554950 X60/T60: disable USB power
	during suspend
Message-ID: <E1QXDqF-0002mz-Bj@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/38

-gerrit

commit b554950511184ed5132f7e54ff5bd1c57efea117
Author: Sven Schnelle <svens at stackframe.org>
Date:   Thu Jun 16 16:43:46 2011 +0200

    X60/T60: disable USB power during suspend
    
    Change-Id: I11afba5d7531132a0274e55e8a478985a0ef956f
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/t60/acpi/platform.asl |    1 +
 src/mainboard/lenovo/x60/acpi/platform.asl |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/lenovo/t60/acpi/platform.asl b/src/mainboard/lenovo/t60/acpi/platform.asl
index 85a987b..de76dea 100644
--- a/src/mainboard/lenovo/t60/acpi/platform.asl
+++ b/src/mainboard/lenovo/t60/acpi/platform.asl
@@ -68,6 +68,7 @@ Method(_PIC, 1)
 Method(_PTS,1)
 {
 	\_SB.PCI0.LPCB.EC.MUTE(1)
+	\_SB.PCI0.LPCB.EC.USBP(0)
 }
 
 /* The _WAK method is called on system wakeup */
diff --git a/src/mainboard/lenovo/x60/acpi/platform.asl b/src/mainboard/lenovo/x60/acpi/platform.asl
index 85a987b..de76dea 100644
--- a/src/mainboard/lenovo/x60/acpi/platform.asl
+++ b/src/mainboard/lenovo/x60/acpi/platform.asl
@@ -68,6 +68,7 @@ Method(_PIC, 1)
 Method(_PTS,1)
 {
 	\_SB.PCI0.LPCB.EC.MUTE(1)
+	\_SB.PCI0.LPCB.EC.USBP(0)
 }
 
 /* The _WAK method is called on system wakeup */



From gerrit at coreboot.org  Thu Jun 16 17:00:13 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 16 Jun 2011 17:00:13 +0200
Subject: [coreboot] Patch merged into master: 5ec011a Lenovo H8 EC: add
	usb_power_enable()
Message-ID: <E1QXE3J-0004uw-4t@ra.coresystems.de>

the following patch was just integrated into master:
commit 5ec011a230a23bdc51e2c37c0b799cb44560fb6f
Author: Sven Schnelle <svens at stackframe.org>
Date:   Thu Jun 16 16:43:04 2011 +0200

    Lenovo H8 EC: add usb_power_enable()
    
    Can be used to disable/enable Power output on USB ports.
    
    Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/37 for details.

-gerrit



From gerrit at coreboot.org  Thu Jun 16 17:20:56 2011
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 16 Jun 2011 17:20:56 +0200
Subject: [coreboot] Patch merged into master: b554950 X60/T60: disable USB
	power during suspend
Message-ID: <E1QXENM-0006m1-Js@ra.coresystems.de>

the following patch was just integrated into master:
commit b554950511184ed5132f7e54ff5bd1c57efea117
Author: Sven Schnelle <svens at stackframe.org>
Date:   Thu Jun 16 16:43:46 2011 +0200

    X60/T60: disable USB power during suspend
    
    Change-Id: I11afba5d7531132a0274e55e8a478985a0ef956f
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

See http://review.coreboot.org/38 for details.

-gerrit



From marcj303 at gmail.com  Thu Jun 16 23:54:08 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 16 Jun 2011 15:54:08 -0600
Subject: [coreboot] gerrit commits
Message-ID: <BANLkTin6Wzm9tQBemBkyBHHjBRPmS=3jLA@mail.gmail.com>

Can gerrit add the reviewed-by/acked-by to the commit message?

Marc


-- 
http://se-eng.com



From paulepanter at users.sourceforge.net  Fri Jun 17 00:10:48 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Fri, 17 Jun 2011 00:10:48 +0200
Subject: [coreboot] coreboot support: difference between ASRock E350M1 and
 ASRock E350M1/USB3
Message-ID: <1308262248.4251.54.camel@mattotaupa>

Dear coreboot folks,


looking at the offers there are two models ASRock E350M1 [1] and ASRock
E350M1/USB3 [2] where the second one cost about 10 ? more.

Does coreboot run on both boards?

OT: Does anyone know if there are different chips or plugs/ports used
for the ASRock E350M1/USB3 or is that a software/BIOS limitation?


Thanks,

Paul


[1] http://www.asrock.com/mb/overview.asp?Model=E350M1
[2] http://www.asrock.com/mb/overview.asp?Model=E350M1/USB3
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From mbuschman at lucidmachines.com  Fri Jun 17 00:58:56 2011
From: mbuschman at lucidmachines.com (Marshall Buschman)
Date: Thu, 16 Jun 2011 17:58:56 -0500
Subject: [coreboot] coreboot support: difference between ASRock E350M1
 and ASRock E350M1/USB3
In-Reply-To: <1308262248.4251.54.camel@mattotaupa>
References: <1308262248.4251.54.camel@mattotaupa>
Message-ID: <4DFA8AB0.3030904@lucidmachines.com>

I own both boards - both do work, BUT there are still bugs:
USB3 and built-in NIC do not work on either by default.
Memory is only reported as roughly 512mb at this point.

You're welcome to help. :)

As far as your other question... I'm not sure what you mean...
USB3 is a physically different connector, with a different pinout 
entirely, although it does retain backward compatibility with USB2. See 
http://www.addonics.com/emerging_technologies/usb3_tutorial.asp

If you're referring to the bios chips themselves, they're DIP8s -- both 
the USB3 and the regular E350M1 use the same kind of chip, but the 
BIOSes themselves do differ.

Hopefully this helps.

Thanks!
-Marshall

On 6/16/2011 5:10 PM, Paul Menzel wrote:
> Dear coreboot folks,
>
>
> looking at the offers there are two models ASRock E350M1 [1] and ASRock
> E350M1/USB3 [2] where the second one cost about 10 ? more.
>
> Does coreboot run on both boards?
>
> OT: Does anyone know if there are different chips or plugs/ports used
> for the ASRock E350M1/USB3 or is that a software/BIOS limitation?
>
>
> Thanks,
>
> Paul
>
>
> [1] http://www.asrock.com/mb/overview.asp?Model=E350M1
> [2] http://www.asrock.com/mb/overview.asp?Model=E350M1/USB3




From Patrick.Georgi at secunet.com  Fri Jun 17 08:29:04 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Fri, 17 Jun 2011 08:29:04 +0200
Subject: [coreboot] Questions about CBFS
In-Reply-To: <BANLkTinwgx1S1A2a3sp9AbrvpMJCaWEr1A@mail.gmail.com>
References: <BANLkTinwgx1S1A2a3sp9AbrvpMJCaWEr1A@mail.gmail.com>
Message-ID: <1308292144.2618.6.camel@linux-0a8x.site>

Am Donnerstag, den 16.06.2011, 21:50 +0800 schrieb Hamo:
> 1. When we create the rom file, we covert all address and size from
> LSB to MSB using htonl, and when we use them in the rom, we covert
> them to LSB. Why we do this? Is it necessary or historical or
> something else? Since ARM don't have an instruction like BSWAP in X86
> (or I don't know it), it is not easy to covert a register from LSB to
> MSB or vice versa.
We thought it's a good idea to mandate _some_ default, otherwise we'd
risk having incompatible image formats created by the same tool.

Question is if we should define native endianess per platform and let
cbfstool take care of things (instead of coreboot at runtime), adding a
flag to the CBFS header (which would have to be properly specified so
things are clear)

> 2. What's the purpose of tryharder in src/arch/x86/lib/walkcbfs.S? In
> my opinion, After we found a 'LARCHIVE', we can just compare the name
> with the target name. If they are the same, OK, we got it and we can
> jump to it, If not, we should jump to searchfile to find the next CBFS
> component.
It's probably somewhat misnamed:
searchfile takes the alignment property of an image and searches the
image for LARCHIVE headers in "align"-increments.
tryharder skips a file (of a known size) so the cbfs walker doesn't have
to search inside files (we know that new files won't start there).

Essentially the algorithm is like this:
1. determine ALIGN
2. set cursor to the beginning of the image
3. search for 'LARCHIVE' header in ALIGN-steps (address mod ALIGN == 0)
   (searchfile)
4. if a file is found, check filename
5. if filename matches, return success
7. otherwise skip file (tryharder)
8. if cursor left image area, return failure
9. go to 3.

where 3. expands to:
3a. look for 'LARCHIVE'
3b. if found, go to 4.
3c. otherwise do cursor += ALIGN;
3d. if cursor left image area, return failure
3e. go to 3a.

Regards,
Patrick
-- 
Patrick Georgi
Fachbereich SINA-Entwicklung
Gesch?ftsbereich Hochsicherheit
secunet Security Networks AG
Mergenthalerallee 77
65760 Eschborn, Germany
Telefon +49 201 54 54-3610
Telefax +49 201 54 54-1325
Patrick.Georgi at secunet.com 
www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen
Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
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From scott at notabs.org  Fri Jun 17 10:29:19 2011
From: scott at notabs.org (Scott Duplichan)
Date: Fri, 17 Jun 2011 03:29:19 -0500
Subject: [coreboot] coreboot support: difference between ASRock E350M1
	and ASRock E350M1/USB3
In-Reply-To: <4DFA8AB0.3030904@lucidmachines.com>
References: <1308262248.4251.54.camel@mattotaupa>
	<4DFA8AB0.3030904@lucidmachines.com>
Message-ID: <F83987BD4CB041D289C5F636CB572F94@asusp67>

Marshall Buschman wrote:

]I own both boards - both do work, BUT there are still bugs:
]USB3 and built-in NIC do not work on either by default.
]Memory is only reported as roughly 512mb at this point.
]
]You're welcome to help. :)

Hello Marshall,

Thanks for reporting these problems. Incorrect memory size
should be easy to fix. Can you send an e820 listing for a 
problem memory configuration?

I started looking at the NIC problem. The first thing wrong
is that its bridge is not enabled in devicetree.cb. The bridge
is at device 0x15, function 1. Also, the correct pcie lane option
needs to be selected with: register "gpp_configuration" = "4".
Once that is fixed, it doesn't work because its sb800_enable()
code is not running early enough. This a message such as:
"sb800_enable() PCI: Static device PCI: 00:15.1 not found,
disabling it." As a result, no bus number is assigned. I manually
assigned a bus number and was able to see the NIC, so the PCIe
link is trained and working. I will try to complete the debug
during the next couple of days.

Thanks,
Scott




From svens at stackframe.org  Fri Jun 17 14:51:45 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Fri, 17 Jun 2011 14:51:45 +0200
Subject: [coreboot] caching in SMI handler
Message-ID: <8762o4ipsu.fsf@begreifnix.stackframe.org>

Hi List,

i've encountered an interesting problem on my Thinkpad T60:

whenever i've docked/undocked the thinkpad from the docking station,
i had to do that twice to get the action actually to happen.

First i thought that would be some error in the ACPI code. Here's a
short explanation how docking/undocking works:

1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock)
2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows:

   a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range
   b) Store(0, 0x808)   // Generates I/O Trap to SMM
   c) // SMM is executed
   d) Return (SMIF)    // Return Result in SMIF

I've verified that a) is really executed with ACPI debugging in the
Linux Kernel. It writes the correct value to GNVS Memory. After that,
i've logged the SMIF value in SMM, which contains some random (or
former) value of SMIF.

So i've added the GNVS area to /proc/mtrr which made things work.
I've also tried a wbinvd() in SMM code, with the same result.

After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized
that it starts with:

        movw    $(smm_gdtptr16 - smm_handler_start +
        SMM_HANDLER_OFFSET), %bx 
        data32  lgdt %cs:(%bx)

        movl    %cr0, %eax
        andl    $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
        orl     $0x60000001, %eax /* CD, NW, PE = 1 */
        movl    %eax, %cr0

        /* Enable protected mode */
        data32  ljmp    $0x08, $1f 

...which disables caching in SMM code, but doesn't flush the cache.

So the problem is:

- the linux axpi write to the SMIF GNVS Area will be written to Cache,
  because GNVS is WB
- the SMM code runs with cache disabled, and fetches SMIF directly from
  Memory, which is some other value
 

Possible Solutions:

- enable cache in SMM (yeah, cache poisoning...)

- flush caches in SMM (really expensive)

- mark GNVS as UC in Memory Map (will only work if OS
  really marks that Area as UC. Checked various vendor BIOSes, none
  of them are marking NVS as UC. So this seems rather uncommon.)

- flush only the cache line which contains GNVS. Would fix this
  particular problem, but users/developers could see other Bugs like
  this. And not everyone likes to debug such problems. So i won't like
  this solution.

Opinions?

Cheers,

Sven. 



From hamo.by at gmail.com  Fri Jun 17 16:36:18 2011
From: hamo.by at gmail.com (Hamo)
Date: Fri, 17 Jun 2011 22:36:18 +0800
Subject: [coreboot] Questions about CBFS
In-Reply-To: <1308292144.2618.6.camel@linux-0a8x.site>
References: <BANLkTinwgx1S1A2a3sp9AbrvpMJCaWEr1A@mail.gmail.com>
	<1308292144.2618.6.camel@linux-0a8x.site>
Message-ID: <BANLkTimMLKO7wNXEp4XhEtgDmem-D96ZiQ@mail.gmail.com>

On Fri, Jun 17, 2011 at 2:29 PM, Georgi, Patrick
<Patrick.Georgi at secunet.com> wrote:
> Am Donnerstag, den 16.06.2011, 21:50 +0800 schrieb Hamo:
> We thought it's a good idea to mandate _some_ default, otherwise we'd
> risk having incompatible image formats created by the same tool.
>
You mean that we use MSB as default now?
> Question is if we should define native endianess per platform and let
> cbfstool take care of things (instead of coreboot at runtime), adding a
> flag to the CBFS header (which would have to be properly specified so
> things are clear)
>
A new question:
Why we use a binary file to create the rom but using an ELF to add a
stage to this rom?

Thanks,
Hamo



From gerrit at coreboot.org  Fri Jun 17 20:49:02 2011
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Fri, 17 Jun 2011 20:49:02 +0200
Subject: [coreboot] New patch to review: 0f56ebb SMM: flush caches after
	disabling caching
Message-ID: <E1QXe6I-0002sI-1W@ra.coresystems.de>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/39

-gerrit

commit 0f56ebbc8996cf760b6a2486f730f47664780568
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Jun 17 20:47:08 2011 +0200

    SMM: flush caches after disabling caching
    
    Fixes spurious SMI crashes i've seen, and ACPI/SMM interaction.
    For reference, the mail i've sent to ML with the bugreport:
    
    whenever i've docked/undocked the thinkpad from the docking station,
    i had to do that twice to get the action actually to happen.
    
    First i thought that would be some error in the ACPI code. Here's a
    short explanation how docking/undocking works:
    
    1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock)
    2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows:
    
       a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range
       b) Store(0, 0x808)   // Generates I/O Trap to SMM
       c) // SMM is executed
       d) Return (SMIF)    // Return Result in SMIF
    
    I've verified that a) is really executed with ACPI debugging in the
    Linux Kernel. It writes the correct value to GNVS Memory. After that,
    i've logged the SMIF value in SMM, which contains some random (or
    former) value of SMIF.
    
    So i've added the GNVS area to /proc/mtrr which made things work.
    I've also tried a wbinvd() in SMM code, with the same result.
    
    After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized
    that it starts with:
    
            movw    $(smm_gdtptr16 - smm_handler_start +
            SMM_HANDLER_OFFSET), %bx
            data32  lgdt %cs:(%bx)
    
            movl    %cr0, %eax
            andl    $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
            orl     $0x60000001, %eax /* CD, NW, PE = 1 */
            movl    %eax, %cr0
    
            /* Enable protected mode */
            data32  ljmp    $0x08, $1f
    
    ...which disables caching in SMM code, but doesn't flush the cache.
    
    So the problem is:
    
    - the linux axpi write to the SMIF GNVS Area will be written to Cache,
      because GNVS is WB
    - the SMM code runs with cache disabled, and fetches SMIF directly from
      Memory, which is some other value
    
    Possible Solutions:
    
    - enable cache in SMM (yeah, cache poisoning...)
    
    - flush caches in SMM (really expensive)
    
    - mark GNVS as UC in Memory Map (will only work if OS
      really marks that Area as UC. Checked various vendor BIOSes, none
      of them are marking NVS as UC. So this seems rather uncommon.)
    
    - flush only the cache line which contains GNVS. Would fix this
      particular problem, but users/developers could see other Bugs like
      this. And not everyone likes to debug such problems. So i won't like
      this solution.
    
    Change-Id: Ie60bf91c5fd1491bc3452d5d9b7fc8eae39fd77a
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/cpu/x86/smm/smmhandler.S |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 3dd0b14..450aa53 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -83,6 +83,7 @@ smm_handler_start:
 	andl    $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
 	orl     $0x60000001, %eax /* CD, NW, PE = 1 */
 	movl    %eax, %cr0
+	wbinvd
 
 	/* Enable protected mode */
 	data32  ljmp    $0x08, $1f



From patrick at georgi-clan.de  Fri Jun 17 22:01:44 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 17 Jun 2011 22:01:44 +0200
Subject: [coreboot] Questions about CBFS
In-Reply-To: <BANLkTimMLKO7wNXEp4XhEtgDmem-D96ZiQ@mail.gmail.com>
References: <BANLkTinwgx1S1A2a3sp9AbrvpMJCaWEr1A@mail.gmail.com>	<1308292144.2618.6.camel@linux-0a8x.site>
	<BANLkTimMLKO7wNXEp4XhEtgDmem-D96ZiQ@mail.gmail.com>
Message-ID: <4DFBB2A8.1020405@georgi-clan.de>

Am 17.06.2011 16:36, schrieb Hamo:
> You mean that we use MSB as default now?
I think there's an exception for one field (entry point?), but other
than that, yes.

> A new question:
> Why we use a binary file to create the rom but using an ELF to add a
> stage to this rom?
Mostly historical reasons, that is, no real reason, I guess.


Patrick



From gerrit at coreboot.org  Fri Jun 17 22:50:32 2011
From: gerrit at coreboot.org (Frank Vibrans III (efdesign98@gmail.com))
Date: Fri, 17 Jun 2011 22:50:32 +0200
Subject: [coreboot] New patch to review: 3bea4ad Add AMD SB900 CIMx code
Message-ID: <E1QXfzs-00025b-Sg@ra.coresystems.de>

Frank Vibrans III (efdesign98 at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/41

-gerrit

commit 3bea4ad540eb9a756f709b0588095ba6c352d5ba
Author: efdesign98 <efdesign98 at gmail.com>
Date:   Thu Jun 16 16:39:30 2011 -0700

    Add AMD SB900 CIMx code
    
    This code is added to support the AMD SB900 southbridge.
    This commit is done on behalf of AMD by Frank Vibrans
    <frank.vibrans at amd.com> operating under his private user name.
    
    Change-Id: I7dc5e13a53ffd479dcea4e05e8c8631096e2ba91
    Signed-off-by: efdesign98 <efdesign98 at gmail.com>
---
 src/vendorcode/amd/cimx/sb900/AcpiLib.c        |  179 ++
 src/vendorcode/amd/cimx/sb900/AcpiLib.h        |   62 +
 src/vendorcode/amd/cimx/sb900/AmdLib.c         |   89 +
 src/vendorcode/amd/cimx/sb900/AmdSbLib.c       |  336 ++++
 src/vendorcode/amd/cimx/sb900/AmdSbLib.h       |  112 ++
 src/vendorcode/amd/cimx/sb900/Azalia.c         |  517 ++++++
 src/vendorcode/amd/cimx/sb900/Debug.c          |  203 +++
 src/vendorcode/amd/cimx/sb900/Dispatcher.c     |  261 +++
 src/vendorcode/amd/cimx/sb900/Ec.c             |  128 ++
 src/vendorcode/amd/cimx/sb900/EcFan.h          |   66 +
 src/vendorcode/amd/cimx/sb900/EcFanLib.c       |  285 ++++
 src/vendorcode/amd/cimx/sb900/EcFanc.c         |  189 +++
 src/vendorcode/amd/cimx/sb900/EcLib.c          |  153 ++
 src/vendorcode/amd/cimx/sb900/Gec.c            |  141 ++
 src/vendorcode/amd/cimx/sb900/Gpp.c            | 1109 +++++++++++++
 src/vendorcode/amd/cimx/sb900/GppHp.c          |  165 ++
 src/vendorcode/amd/cimx/sb900/Hudson-2.h       | 2068 ++++++++++++++++++++++++
 src/vendorcode/amd/cimx/sb900/Hwm.c            |  578 +++++++
 src/vendorcode/amd/cimx/sb900/IoLib.c          |   92 ++
 src/vendorcode/amd/cimx/sb900/Legacy.c         |   44 +
 src/vendorcode/amd/cimx/sb900/Makefile.inc     |   88 +
 src/vendorcode/amd/cimx/sb900/MemLib.c         |   93 ++
 src/vendorcode/amd/cimx/sb900/Oem.h            |  229 +++
 src/vendorcode/amd/cimx/sb900/PciLib.c         |   83 +
 src/vendorcode/amd/cimx/sb900/Pmio2Lib.c       |  127 ++
 src/vendorcode/amd/cimx/sb900/PmioLib.c        |  126 ++
 src/vendorcode/amd/cimx/sb900/Sata.c           | 1042 ++++++++++++
 src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h |   53 +
 src/vendorcode/amd/cimx/sb900/SbCmn.c          | 1544 ++++++++++++++++++
 src/vendorcode/amd/cimx/sb900/SbDef.h          |  422 +++++
 src/vendorcode/amd/cimx/sb900/SbMain.c         |  295 ++++
 src/vendorcode/amd/cimx/sb900/SbModInf.c       |   74 +
 src/vendorcode/amd/cimx/sb900/SbPeLib.c        |  480 ++++++
 src/vendorcode/amd/cimx/sb900/SbPor.c          |  736 +++++++++
 src/vendorcode/amd/cimx/sb900/SbSubFun.h       |  607 +++++++
 src/vendorcode/amd/cimx/sb900/SbType.h         | 1389 ++++++++++++++++
 src/vendorcode/amd/cimx/sb900/Smm.c            |   88 +
 src/vendorcode/amd/cimx/sb900/Usb.c            |  979 +++++++++++
 38 files changed, 15232 insertions(+), 0 deletions(-)

diff --git a/src/vendorcode/amd/cimx/sb900/AcpiLib.c b/src/vendorcode/amd/cimx/sb900/AcpiLib.c
new file mode 100755
index 0000000..90b331d
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/AcpiLib.c
@@ -0,0 +1,179 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+//
+//
+// Routine Description:
+//
+//  Locate ACPI table
+//
+// Arguments:
+//
+//  Signature - table signature
+//
+//Returns:
+//
+//  pointer to ACPI table
+//
+//
+VOID*
+ACPI_LocateTable (
+  IN       unsigned int Signature
+  )
+{
+  UINT32  i;
+  UINT32* RsdPtr;
+  UINT32* Rsdt;
+  UINTN   tableOffset;
+  DESCRIPTION_HEADER* CurrentTable;
+  RsdPtr = (UINT32*) (UINTN)0xe0000;
+  Rsdt = NULL;
+  do {
+//    if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) {
+//    if ( (*RsdPtr == 0x52534420) && (*(RsdPtr + 1) == 0x50545220) ) {
+    if ( (*RsdPtr == 0x20445352) && (*(RsdPtr + 1) == 0x20525450) ) {
+      Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress;
+      break;
+    }
+    RsdPtr += 4;
+  } while ( RsdPtr <= (UINT32*) (UINTN)0xffff0 );
+  if ( Rsdt != NULL && ACPI_GetTableChecksum (Rsdt) == 0 ) {
+    for ( i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++ ) {
+      tableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i * 4);
+      CurrentTable = (DESCRIPTION_HEADER*)tableOffset;
+      if ( CurrentTable->Signature == Signature ) {
+        return CurrentTable;
+      }
+    }
+  }
+  return NULL;
+}
+
+//
+//
+//  Routine Description:
+//
+//  Update table checksum
+//
+//  Arguments:
+//
+//  TablePtr - table pointer
+//
+//  Returns:
+//
+//  none
+//
+//
+VOID
+ACPI_SetTableChecksum (
+  IN       VOID* TablePtr
+  )
+{
+  UINT8 Checksum;
+  Checksum = 0;
+  ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
+  Checksum = ACPI_GetTableChecksum (TablePtr);
+  ((DESCRIPTION_HEADER*)TablePtr)->Checksum = (UINT8) (0x100 - Checksum);
+}
+
+//
+//
+//  Routine Description:
+//
+//  Get table checksum
+//
+//  Arguments:
+//
+//  TablePtr - table pointer
+//
+//  Returns:
+//
+//  none
+//
+//
+UINT8
+ACPI_GetTableChecksum (
+  IN       VOID* TablePtr
+  )
+{
+  return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length);
+}
+
+
+UINT8
+GetByteSum (
+  IN       VOID* pData,
+  IN       UINT32 Length
+  )
+{
+  UINT32  i;
+  UINT8 Checksum;
+  Checksum = 0;
+  for ( i = 0; i < Length; i++ ) {
+    Checksum = Checksum + (*((UINT8*)pData + i));
+  }
+  return Checksum;
+}
+VOID
+GetSbAcpiMmioBase (
+  OUT     UINT32*    AcpiMmioBase
+  )
+{
+  UINT32    Value16;
+
+  ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint16, &Value16);
+  *AcpiMmioBase = Value16 << 16;
+}
+
+VOID
+GetSbAcpiPmBase (
+  OUT     UINT16*    AcpiPmBase
+  )
+{
+  ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase);
+}
+
+VOID
+SetAcpiPma (
+  IN     UINT8    pmaControl
+  )
+{
+  UINT16 pmaBase;
+  UINT16 dwValue;
+  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74, AccWidthUint16, &dwValue);
+  dwValue &= ~BIT6;
+  WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74, AccWidthUint16, &dwValue);
+  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, &pmaBase);
+  WriteIo8 (pmaBase, pmaControl);
+  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, ~BIT7, pmaControl << 7);
+}
+
diff --git a/src/vendorcode/amd/cimx/sb900/AcpiLib.h b/src/vendorcode/amd/cimx/sb900/AcpiLib.h
new file mode 100755
index 0000000..20d271a
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/AcpiLib.h
@@ -0,0 +1,62 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+/**
+ * RSDP - ACPI 2.0 table RSDP
+ */
+typedef struct _RSDP {
+  unsigned long long  Signature;        ///< RSDP signature "RSD PTR"
+  unsigned char  Checksum;          ///< checksum of the first 20 bytes
+  unsigned char  OEMID[6];          ///< OEM ID, "LXBIOS"
+  unsigned char  Revision;          ///< 0 for APCI 1.0, 2 for ACPI 2.0
+  unsigned int  RsdtAddress;      ///< physical address of RSDT
+  unsigned int  Length;           ///< total length of RSDP (including extended part)
+  unsigned long long  XsdtAddress;      ///< physical address of XSDT
+  unsigned char  ExtendedChecksum;  ///< chechsum of whole table
+  unsigned char  Reserved[3];       ///< Reserved
+} RSDP;
+
+
+/// DESCRIPTION_HEADER - ACPI common table header
+typedef struct _DESCRIPTION_HEADER {
+  unsigned int  Signature;        ///< ACPI signature (4 ASCII characters)
+  unsigned int  Length;           ///< Length of table, in bytes, including header
+  unsigned char  Revision;          ///< ACPI Specification minor version #
+  unsigned char  Checksum;          ///< To make sum of entire table == 0
+  unsigned char  OEMID[6];          ///< OEM identification
+  unsigned char  OEMTableID[8];     ///< OEM table identification
+  unsigned int  OEMRevision;      ///< OEM revision number
+  unsigned int  CreatorID;        ///< ASL compiler vendor ID
+  unsigned int  CreatorRevision;  ///< ASL compiler revision number
+} DESCRIPTION_HEADER;
+
+void* ACPI_LocateTable (IN unsigned int Signature);
+void  ACPI_SetTableChecksum (IN void* TablePtr);
+unsigned char ACPI_GetTableChecksum (IN void* TablePtr);
+unsigned char GetByteSum (IN void* pData, IN unsigned int Length);
diff --git a/src/vendorcode/amd/cimx/sb900/AmdLib.c b/src/vendorcode/amd/cimx/sb900/AmdLib.c
new file mode 100755
index 0000000..9d84b43
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/AmdLib.c
@@ -0,0 +1,89 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+UINT8
+getNumberOfCpuCores (
+  OUT VOID
+  )
+{
+  UINT8 Result;
+  Result = 1;
+  Result = ReadNumberOfCpuCores ();
+  return Result;
+}
+
+UINT32
+readAlink (
+  IN       UINT32 Index
+  )
+{
+  UINT32 Data;
+  WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+  ReadIO (ALINK_ACCESS_DATA, AccWidthUint32, &Data);
+  //Clear Index
+  Index = 0;
+  WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+  return Data;
+}
+
+VOID
+writeAlink (
+  IN       UINT32 Index,
+  IN       UINT32 Data
+  )
+{
+  WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
+  WriteIO (ALINK_ACCESS_DATA, AccWidthUint32 | S3_SAVE, &Data);
+  //Clear Index
+  Index = 0;
+  WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
+}
+
+VOID
+rwAlink (
+  IN       UINT32 Index,
+  IN       UINT32 AndMask,
+  IN       UINT32 OrMask
+  )
+{
+  UINT32 AccessType;
+  AccessType = Index & 0xE0000000;
+  if (AccessType == (AXINDC << 29)) {
+    writeAlink ((SB_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF);
+    Index = (SB_AX_DATAC_REG34 | AccessType);
+  } else if (AccessType == (AXINDP << 29)) {
+    writeAlink ((SB_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF);
+    Index = (SB_AX_DATAP_REG3C | AccessType);
+  }
+  writeAlink (Index, ((readAlink (Index) & AndMask) | OrMask) );
+}
+
diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.c b/src/vendorcode/amd/cimx/sb900/AmdSbLib.c
new file mode 100755
index 0000000..5329552
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/AmdSbLib.c
@@ -0,0 +1,336 @@
+/**
+ * @file
+ *
+ * Southbridge IO access common routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+/**< SbStall - Reserved  */
+VOID
+SbStall (
+  IN       UINT32 uSec
+  )
+{
+  UINT16 timerAddr;
+  UINT32 startTime;
+  UINT32 elapsedTime;
+
+  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr);
+  if ( timerAddr == 0 ) {
+    uSec = uSec / 2;
+    while ( uSec != 0 ) {
+      ReadIO (0x80, AccWidthUint8, (UINT8 *) (&startTime));
+      uSec--;
+    }
+  } else {
+    ReadIO (timerAddr, AccWidthUint32, &startTime);
+    for ( ;; ) {
+      ReadIO (timerAddr, AccWidthUint32, &elapsedTime);
+      if ( elapsedTime < startTime ) {
+        elapsedTime = elapsedTime + 0xFFFFFFFF - startTime;
+      } else {
+        elapsedTime = elapsedTime - startTime;
+      }
+      if ( (elapsedTime * 28 / 100) > uSec ) {
+        break;
+      }
+    }
+  }
+}
+
+/**< cimSbStall - Reserved  */
+VOID
+cimSbStall (
+  IN       UINT32 uSec
+  )
+{
+  UINT16 timerAddr;
+  UINT32 startTime;
+  UINT32 elapsedTime;
+
+  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr);
+  if ( timerAddr == 0 ) {
+    uSec = uSec / 2;
+    while ( uSec != 0 ) {
+      ReadIo8 (0x80);
+      uSec--;
+    }
+  } else {
+    startTime = ReadIo32 (timerAddr);
+    for ( ;; ) {
+      elapsedTime = ReadIo32 (timerAddr);
+      if ( elapsedTime < startTime ) {
+        elapsedTime = elapsedTime + 0xFFFFFFFF - startTime;
+      } else {
+        elapsedTime = elapsedTime - startTime;
+      }
+      if ( (elapsedTime * 28 / 100) > uSec ) {
+        break;
+      }
+    }
+  }
+}
+
+/**< SbReset - Reserved  */
+VOID
+SbReset ()
+{
+  RWIO (0xcf9, AccWidthUint8, 0x0, 0x06);
+}
+
+/**< outPort80 - Reserved  */
+VOID
+outPort80 (
+  IN  UINT32 pcode
+  )
+{
+  WriteIO (0x80, AccWidthUint8, &pcode);
+  return;
+}
+
+/**< outPort1080 - Reserved  */
+VOID
+outPort1080 (
+  IN  UINT32 pcode
+  )
+{
+  WriteIo32 (0x1080, pcode);
+  return;
+}
+
+/**< AmdSbCopyMem - Reserved  */
+VOID
+AmdSbCopyMem (
+  IN      VOID*   pDest,
+  IN      VOID*   pSource,
+  IN      UINTN   Length
+  )
+{
+  UINTN  i;
+  UINT8  *Ptr;
+  UINT8  *Source;
+  Ptr = (UINT8*)pDest;
+  Source = (UINT8*)pSource;
+  for (i = 0; i < Length; i++) {
+    *Ptr = *Source;
+    Source++;
+    Ptr++;
+  }
+}
+
+/** GetRomSigPtr - Reserved **/
+VOID*
+GetRomSigPtr (
+  IN UINTN* RomSigPtr
+  )
+{
+  UINTN  RomPtr;
+  UINT32 RomSig;
+  RomPtr = 0xFFF20000;  // 1M
+  ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
+  if ( RomSig != 0x55AA55AA ) {
+    RomPtr = 0xFFE20000; //2M
+    ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
+    if ( RomSig != 0x55AA55AA ) {
+      RomPtr = 0xFFC20000; //4M
+      ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
+      if ( RomSig != 0x55AA55AA ) {
+        RomPtr = 0xFF820000; //8M
+        ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
+        if ( RomSig != 0x55AA55AA ) {
+          RomPtr = 0xFF020000; //16M
+          ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
+          if ( RomSig != 0x55AA55AA ) {
+            RomPtr = 0x0; // not found
+          }
+        }
+      }
+    }
+  }
+  *RomSigPtr = RomPtr;
+  return RomSigPtr;
+}
+
+VOID
+RWXhciIndReg (
+  IN       UINT32 Index,
+  IN       UINT32 AndMask,
+  IN       UINT32 OrMask
+  )
+{
+  UINT32  IndReg;
+  WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
+  ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
+  IndReg &= AndMask;
+  IndReg |= OrMask;
+  WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
+
+#ifndef XHCI_SUPPORT_ONE_CONTROLLER
+  WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
+  ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
+  IndReg &= AndMask;
+  IndReg |= OrMask;
+  WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
+#endif
+}
+
+VOID
+RWXhci0IndReg (
+  IN       UINT32 Index,
+  IN       UINT32 AndMask,
+  IN       UINT32 OrMask
+  )
+{
+  UINT32  IndReg;
+  WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
+  ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
+  IndReg &= AndMask;
+  IndReg |= OrMask;
+  WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
+}
+
+VOID
+RWXhci1IndReg (
+  IN       UINT32 Index,
+  IN       UINT32 AndMask,
+  IN       UINT32 OrMask
+  )
+{
+  UINT32  IndReg;
+  WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
+  ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
+  IndReg &= AndMask;
+  IndReg |= OrMask;
+  WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
+}
+
+VOID
+AcLossControl (
+  IN       UINT8 AcLossControlValue
+  )
+{
+  AcLossControlValue &= 0x03;
+  AcLossControlValue |= BIT2;
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG5B, AccWidthUint8, 0xF0, AcLossControlValue);
+}
+
+VOID
+SbVgaInit (
+  VOID
+  )
+{
+  // OBS194249 Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B
+  //
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xff, BIT5 );
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0x00, 0x17 );
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0x00, ((BGADJ << 2) + (((DACADJ & 0xf0) >> 4) & 0x3)));
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0x00, 0x16 );
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0x0f, ((DACADJ & 0x0f) << 4));
+
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x00))) = (0x08 << 4) + (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 16) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x01))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 8) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x02))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 0) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x03))) = (UINT8) (0x03);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x04))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 0) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x05))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 8) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x06))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 16) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x07))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 24) & 0xff);
+  *((UINT8*) ((UINTN)(PKT_LEN_REG))) = 0x08;
+  *((UINT8*) ((UINTN)(PKT_CTRL_REG))) = 0x01;
+  //RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, ~(BIT5), 0 );
+}
+
+VOID
+RecordSbConfigPtr (
+  IN       UINT32 SbConfigPtr
+  )
+{
+  RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 0) & 0xFF) );
+  RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 8) & 0xFF) );
+  RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 16) & 0xFF) );
+  RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 24) & 0xFF) );
+}
+
+VOID
+SbGpioInit (
+  IN       SB_GPIO_INIT_ENTRY *SbGpioInitTable
+  )
+{
+  while ( SbGpioInitTable->GpioPin < 0xFF ) {
+    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SbGpioInitTable->GpioPin, AccWidthUint8, 0, SbGpioInitTable->GpioMux );
+    RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SbGpioInitTable->GpioPin, AccWidthUint8, ~ (BIT5 + BIT6), ((SbGpioInitTable->GpioOutEnB + (SbGpioInitTable->GpioOut << 1)) << 5) );
+    SbGpioInitTable ++;
+  }
+}
+
+VOID
+SbGpioControl (
+  IN       SB_GPIO_CONTROL_ENTRY *SbGpio
+  )
+{
+  UINT8 GpioCurrent;
+  ReadMEM (ACPI_MMIO_BASE + GPIO_BASE + SbGpio->GpioPin, AccWidthUint8, &GpioCurrent );
+  if ((GpioCurrent & BIT5) == 0) {
+    RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SbGpio->GpioPin, AccWidthUint8, ~ BIT6, (SbGpio->GpioControl << 6) );
+  }
+  GpioCurrent &= BIT7;
+  SbGpio->GpioControl = GpioCurrent >> 7;
+}
+
+VOID
+SbFlashUsbSmi (
+  VOID
+  )
+{
+  if ( ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) & (BIT4) ) {
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) &= ~ (BIT4);
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) |= (BIT4);
+  }
+}
+
+VOID
+SbEnableUsbIrq1Irq12ToPicApic (
+  VOID
+  )
+{
+  ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) |= (BIT1);
+}
+
diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h
new file mode 100755
index 0000000..619cdd4
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h
@@ -0,0 +1,112 @@
+/**
+ * @file
+ *
+ * Southbridge IO access common routine define file
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+
+//AMDSBLIB Routines
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**< SbStall - Reserved  */
+void  SbStall (IN unsigned int uSec);
+
+/**< cimSbStall - Reserved  */
+void  cimSbStall (IN unsigned int uSec);
+
+/**< SbReset - Reserved  */
+void SbReset (void);
+
+/**< outPort80 - Reserved  */
+void outPort80 (IN unsigned int pcode);
+
+/**< outPort80 - Reserved  */
+void outPort1080 (IN unsigned int pcode);
+
+/**< getEfuseStatue - Reserved  */
+void getEfuseStatus (IN void* Value);
+
+/**< getEfuseByte - Reserved  */
+unsigned char getEfuseByte (IN unsigned char Index);
+
+/**< AmdSbDispatcher - Reserved  */
+AGESA_STATUS  AmdSbDispatcher (IN void *pConfig);
+
+/**< AmdSbCopyMem - Reserved  */
+void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length);
+
+/**< GetRomSigPtr - Reserved  */
+void* GetRomSigPtr (IN unsigned int* RomSigPtr);
+
+/**< RWXhciIndReg - Reserved  */
+void RWXhciIndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
+
+/**< RWXhciIndReg - Reserved  */
+void RWXhci0IndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
+
+/**< RWXhciIndReg - Reserved  */
+void RWXhci1IndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
+
+/**< AcLossControl - Reserved  */
+void AcLossControl (IN unsigned char AcLossControlValue);
+
+/**< SbVgaInit - Reserved  */
+void SbVgaInit (void);
+
+/**< RecordSbConfigPtr - Reserved  */
+void RecordSbConfigPtr (IN unsigned int SbConfigPtr);
+
+/**< SbGpioInit - Reserved  */
+void
+SbGpioInit (
+  IN       SB_GPIO_INIT_ENTRY *SbGpioInitTable
+  );
+
+/**< SbGpioControl - Reserved  */
+void
+SbGpioControl (
+  IN       SB_GPIO_CONTROL_ENTRY *SbGpio
+  );
+
+/**< SbFlashUsbSmi - Reserved  */
+void SbFlashUsbSmi (void);
+
+/**< SbEnableUsbIrq1Irq12ToPicApic - Reserved  */
+void SbEnableUsbIrq1Irq12ToPicApic (void);
+
diff --git a/src/vendorcode/amd/cimx/sb900/Azalia.c b/src/vendorcode/amd/cimx/sb900/Azalia.c
new file mode 100755
index 0000000..3fe4647
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Azalia.c
@@ -0,0 +1,517 @@
+/**
+ * @file
+ *
+ * Config Southbridge HD Audio Controller
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+//
+// Declaration of local functions
+//
+
+VOID configureAzaliaPinCmd (IN AMDSBCFG* pConfig, IN UINT32 ddBAR0, IN UINT8 dbChannelNum);
+VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN UINT32 ddChannelNum, IN UINT32 ddBAR0);
+
+/**
+ * Pin Config for ALC880, ALC882 and ALC883.
+ *
+ *
+ *
+ */
+CODECENTRY AzaliaCodecAlc882Table[] =
+{
+  {0x14, 0x01014010},
+  {0x15, 0x01011012},
+  {0x16, 0x01016011},
+  {0x17, 0x01012014},
+  {0x18, 0x01A19030},
+  {0x19, 0x411111F0},
+  {0x1a, 0x01813080},
+  {0x1b, 0x411111F0},
+  {0x1C, 0x411111F0},
+  {0x1d, 0x411111F0},
+  {0x1e, 0x01441150},
+  {0x1f, 0x01C46160},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0262.
+ *
+ *
+ *
+ */
+CODECENTRY AzaliaCodecAlc262Table[] =
+{
+  {0x14, 0x01014010},
+  {0x15, 0x411111F0},
+  {0x16, 0x411111F0},
+  {0x18, 0x01A19830},
+  {0x19, 0x02A19C40},
+  {0x1a, 0x01813031},
+  {0x1b, 0x02014C20},
+  {0x1c, 0x411111F0},
+  {0x1d, 0x411111F0},
+  {0x1e, 0x0144111E},
+  {0x1f, 0x01C46150},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0269.
+ *
+ *
+ *
+ */
+CODECENTRY AzaliaCodecAlc269Table[] =
+{
+  {0x12, 0x99A308F0},
+  {0x14, 0x99130010},
+  {0x15, 0x0121101F},
+  {0x16, 0x99036120},
+  {0x18, 0x01A19850},
+  {0x19, 0x99A309F0},
+  {0x1a, 0x01813051},
+  {0x1b, 0x0181405F},
+  {0x1d, 0x40134601},
+  {0x1e, 0x01442130},
+  {0x11, 0x99430140},
+  {0x20, 0x0030FFFF},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0861.
+ *
+ *
+ *
+ */
+CODECENTRY AzaliaCodecAlc861Table[] =
+{
+  {0x01, 0x8086C601},
+  {0x0B, 0x01014110},
+  {0x0C, 0x01813140},
+  {0x0D, 0x01A19941},
+  {0x0E, 0x411111F0},
+  {0x0F, 0x02214420},
+  {0x10, 0x02A1994E},
+  {0x11, 0x99330142},
+  {0x12, 0x01451130},
+  {0x1F, 0x411111F0},
+  {0x20, 0x411111F0},
+  {0x23, 0x411111F0},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0889.
+ *
+ *
+ *
+ */
+CODECENTRY AzaliaCodecAlc889Table[] =
+{
+  {0x11, 0x411111F0},
+  {0x14, 0x01014010},
+  {0x15, 0x01011012},
+  {0x16, 0x01016011},
+  {0x17, 0x01013014},
+  {0x18, 0x01A19030},
+  {0x19, 0x411111F0},
+  {0x1a, 0x411111F0},
+  {0x1b, 0x411111F0},
+  {0x1C, 0x411111F0},
+  {0x1d, 0x411111F0},
+  {0x1e, 0x01442150},
+  {0x1f, 0x01C42160},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ADI1984.
+ *
+ *
+ *
+ */
+CODECENTRY AzaliaCodecAd1984Table[] =
+{
+  {0x11, 0x0221401F},
+  {0x12, 0x90170110},
+  {0x13, 0x511301F0},
+  {0x14, 0x02A15020},
+  {0x15, 0x50A301F0},
+  {0x16, 0x593301F0},
+  {0x17, 0x55A601F0},
+  {0x18, 0x55A601F0},
+  {0x1A, 0x91F311F0},
+  {0x1B, 0x014511A0},
+  {0x1C, 0x599301F0},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * FrontPanel Config table list
+ *
+ *
+ *
+ */
+CODECENTRY FrontPanelAzaliaCodecTableList[] =
+{
+  {0x19, 0x02A19040},
+  {0x1b, 0x02214020},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Current HD Audio support codec list
+ *
+ *
+ *
+ */
+CODECTBLLIST azaliaCodecTableList[] =
+{
+  {0x010ec0880, &AzaliaCodecAlc882Table[0]},
+  {0x010ec0882, &AzaliaCodecAlc882Table[0]},
+  {0x010ec0883, &AzaliaCodecAlc882Table[0]},
+  {0x010ec0885, &AzaliaCodecAlc882Table[0]},
+  {0x010ec0889, &AzaliaCodecAlc889Table[0]},
+  {0x010ec0262, &AzaliaCodecAlc262Table[0]},
+  {0x010ec0269, &AzaliaCodecAlc269Table[0]},
+  {0x010ec0861, &AzaliaCodecAlc861Table[0]},
+  {0x011d41984, &AzaliaCodecAd1984Table[0]},
+  { (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF}
+};
+
+/**
+ * azaliaInitBeforePciEnum - Config HD Audio Before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+azaliaInitBeforePciEnum (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  if ( pConfig->AzaliaController == 1 ) {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, BIT0);
+    if ( pConfig->BuildParameters.HdAudioMsi) {
+      RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG44, AccWidthUint32 | S3_SAVE, ~BIT8, BIT8);
+      RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG60, AccWidthUint32 | S3_SAVE, ~BIT16, BIT16);
+    }
+  }
+}
+
+/**
+ * azaliaInitAfterPciEnum - Config HD Audio after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+azaliaInitAfterPciEnum (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8   Data;
+  UINT8   i;
+  UINT8   dbEnableAzalia;
+  UINT8   dbPinRouting;
+  UINT8   dbChannelNum;
+  UINT8   dbTempVariable;
+  UINT16   dwTempVariable;
+  UINT32   ddBAR0;
+  UINT32   ddTempVariable;
+  dbEnableAzalia = 0;
+  dbChannelNum = 0;
+  dbTempVariable = 0;
+  dwTempVariable = 0;
+  ddBAR0 = 0;
+  ddTempVariable = 0;
+
+  if ( pConfig->AzaliaController == 1 ) {
+    return;
+  }
+
+  if ( pConfig->AzaliaController != 1 ) {
+    RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
+    if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
+      RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
+    }
+    ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
+    if ( ddBAR0 != 0 ) {
+      if ( ddBAR0 != 0xFFFFFFFF ) {
+        ddBAR0 &=  ~(0x03FFF);
+        dbEnableAzalia = 1;
+        TRACE ((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
+      }
+    }
+  }
+
+  if ( dbEnableAzalia ) {
+    pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 0);
+    pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 2);
+    pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 4);
+    pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 6);
+    // Get SDIN Configuration
+    if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {
+      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);
+      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);
+    } else {
+      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);
+      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);
+    }
+    if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {
+      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);
+      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);
+    } else {
+      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);
+      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);
+    }
+    if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {
+      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);
+      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);
+    } else {
+      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);
+      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);
+    }
+    if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {
+      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);
+      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);
+    } else {
+      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);
+      RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);
+    }
+    // INT#A Azalia resource
+    Data = 0x93; // Azalia APIC index
+    WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
+    Data = 0x10; // IRQ16 (INTA#)
+    WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
+
+    i = 11;
+    do {
+      ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+      dbTempVariable |= BIT0;
+      WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+      SbStall (1000);
+      ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+      i--;
+    }  while ((! (dbTempVariable & BIT0)) && (i > 0) );
+
+    if ( i == 0 ) {
+      TRACE ((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n"));
+      return;
+    }
+
+    SbStall (1000);
+    ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
+    if ( dwTempVariable & 0x0F ) {
+
+      TRACE ((DMSG_SB_TRACE, "CIMxSB - At least One Azalia CODEC found \n"));
+      //atleast one azalia codec found
+      dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
+      do {
+        if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {
+          configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);
+        }
+        dbPinRouting >>= 2;
+        dbChannelNum++;
+      }  while ( dbChannelNum != 4 );
+    } else {
+      TRACE ((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n"));
+      //No Azalia codec found
+      if ( pConfig->AzaliaController != 2 ) {
+        dbEnableAzalia = 0;     //set flag to disable Azalia
+      }
+    }
+  }
+
+  if ( dbEnableAzalia ) {
+    //redo clear reset
+    do {
+      dwTempVariable = 0;
+      WriteMEM ( ddBAR0 + SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);
+      ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+      dbTempVariable &= ~(BIT0);
+      WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+      ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+    }  while ( dbTempVariable & BIT0 );
+
+    if ( pConfig->AzaliaSnoop == 1 ) {
+      RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1 + BIT0);
+    }
+  } else {
+    //disable Azalia controller
+    RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
+  }
+}
+
+/**
+ * configureAzaliaPinCmd - Configuration HD Audio PIN Command
+ *
+ *
+ * @param[in] pConfig              Southbridge configuration structure pointer.
+ * @param[in] ddBAR0               HD Audio BAR0 base address.
+ * @param[in] dbChannelNum         Channel Number.
+ *
+ */
+VOID
+configureAzaliaPinCmd (
+  IN       AMDSBCFG* pConfig,
+  IN       UINT32 ddBAR0,
+  IN       UINT8 dbChannelNum
+  )
+{
+  UINT32   ddTempVariable;
+  UINT32   ddChannelNum;
+  CODECTBLLIST*  ptempAzaliaOemCodecTablePtr;
+  CODECENTRY* tempAzaliaCodecEntryPtr;
+
+  if ( (pConfig->AzaliaPinCfg) != 1 ) {
+    return;
+  }
+
+  ddChannelNum = dbChannelNum << 28;
+  ddTempVariable = 0xF0000;
+  ddTempVariable |= ddChannelNum;
+
+  WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+  SbStall (600);
+  ReadMEM (ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+
+  if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF))) {
+    ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR (&azaliaCodecTableList[0]);
+  } else {
+    ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr;
+  }
+
+  TRACE ((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %X \n", ptempAzaliaOemCodecTablePtr));
+
+  while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
+    if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) {
+      break;
+    } else {
+      ++ptempAzaliaOemCodecTablePtr;
+    }
+  }
+
+  if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
+    TRACE ((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n"));
+    tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
+    TRACE ((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %X \n", tempAzaliaCodecEntryPtr));
+
+    if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) {
+      tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr);
+    }
+    configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
+    if ( pConfig->AzaliaFrontPanel != 1 ) {
+      if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ) {
+        if ( ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == NULL) || ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) {
+          tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (&FrontPanelAzaliaCodecTableList[0]);
+        } else {
+          tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr;
+        }
+        configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
+      }
+    }
+  }
+}
+
+/**
+ * configureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table
+ *
+ *
+ * @param[in] tempAzaliaCodecEntryPtr    HD Audio Codec table structure pointer.
+ * @param[in] ddChannelNum               HD Audio Channel Number.
+ * @param[in] ddBAR0                     HD Audio BAR0 base address.
+ *
+ */
+VOID
+configureAzaliaSetConfigD4Dword (
+  IN       CODECENTRY* tempAzaliaCodecEntryPtr,
+  IN       UINT32 ddChannelNum,
+  IN       UINT32 ddBAR0
+  )
+{
+  UINT8 dbtemp1;
+  UINT8 dbtemp2;
+  UINT8 i;
+  UINT32 ddtemp;
+  UINT32 ddtemp2;
+  ddtemp = 0;
+  ddtemp2 = 0;
+  while ( (tempAzaliaCodecEntryPtr->Nid) != 0xFF ) {
+    dbtemp1 = 0x20;
+    if ( (tempAzaliaCodecEntryPtr->Nid) == 0x1 ) {
+      dbtemp1 = 0x24;
+    }
+
+    ddtemp =  tempAzaliaCodecEntryPtr->Nid;
+    ddtemp &= 0xff;
+    ddtemp <<= 20;
+    ddtemp |= ddChannelNum;
+
+    ddtemp |= (0x700 << 8);
+    for ( i = 4; i > 0; i-- ) {
+      do {
+        ReadMEM (ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);
+      } while ( ddtemp2 & BIT0 );
+
+      dbtemp2 = (UINT8) (( (tempAzaliaCodecEntryPtr->Byte40) >> ((4 - i) * 8 ) ) & 0xff);
+      ddtemp =  (ddtemp & 0xFFFF0000) + ((dbtemp1 - i) << 8) + dbtemp2;
+      WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);
+      SbStall (60);
+    }
+    ++tempAzaliaCodecEntryPtr;
+  }
+}
+
diff --git a/src/vendorcode/amd/cimx/sb900/Debug.c b/src/vendorcode/amd/cimx/sb900/Debug.c
new file mode 100755
index 0000000..76d63b8
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Debug.c
@@ -0,0 +1,203 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+
+#define COM_BASE_ADDRESS   0x3f8
+#define DIVISOR            115200
+#define LF                 0x0a
+#define CR                 0x0d
+
+
+#ifdef CIM_DEBUG
+
+VOID SendBytePort (IN UINT8 Data);
+VOID SendStringPort (IN CHAR8* pstr);
+VOID ItoA (IN UINT32 Value, IN UINT32 Radix, IN CHAR8* pstr);
+
+#ifndef CIM_DEBUG_LEVEL
+ #define CIM_DEBUG_LEVEL 0xf
+#endif
+
+VOID
+TraceCode (
+  IN       UINT32 Level,
+  IN       UINT32 Code
+  )
+{
+  if ( ! (Level & CIM_DEBUG_LEVEL) ) {
+    return;
+  }
+#if CIM_DEBUG & 1
+  if ( Code != 0xFF ) {
+    WriteIO (0x80, AccWidthUint8, &Code);
+  }
+#endif
+}
+
+
+VOID
+TraceDebug (
+  IN       UINT32 Level,
+  IN       CHAR8 *Format,
+  )
+{
+  CHAR8 temp[16];
+  va_list  ArgList;
+  UINT32 Radix;
+
+  if ( ! (Level & CIM_DEBUG_LEVEL) ) {
+    return;
+  }
+
+#if CIM_DEBUG & 2
+  ArgList = va_start (ArgList, Format);
+  Format = (CHAR8*) (Format);
+  while ( 1 ) {
+    if ( *Format == 0 ) {
+      break;
+    }
+    if ( *Format == ' % ' ) {
+      Radix = 0;
+      if ( *(Format + 1) == 's' || *(Format + 1) == 'S' ) {
+        SendStringPort ((CHAR8*) (va_arg (ArgList, CHAR8*)));
+        Format += 2;
+        continue;
+      }
+
+      if ( *(Format + 1) == 'd' || *(Format + 1) == 'D' ) {
+        Radix = 10;
+      }
+      if ( *(Format + 1) == 'x' || *(Format + 1) == 'X' ) {
+        Radix = 16;
+      }
+      if ( Radix ) {
+        ItoA (va_arg (ArgList, intqq), Radix, temp);
+        SendStringPort (temp);
+        Format += 2;
+        continue;
+      }
+    }
+    SendBytePort (*Format);
+    if ( *(Format) == 0x0a ) {
+      SendBytePort (0x0d);
+    }
+    Format++;
+  }
+  va_end (ArgList);
+#endif
+}
+
+
+VOID
+ItoA (
+  IN       UINT32 Value,
+  IN       UINT32 Radix,
+  IN       CHAR8* pstr
+  )
+{
+  CHAR8* tsptr;
+  CHAR8* rsptr;
+  CHAR8  ch1;
+  CHAR8  ch2;
+  UINT32 Reminder;
+  tsptr = pstr;
+  rsptr = pstr;
+//Create String
+  do {
+    Reminder = Value % Radix;
+    Value = Value / Radix;
+    if ( Reminder < 0xa ) {
+      *tsptr = Reminder + '0';
+    } else {
+      *tsptr = Reminder - 0xa + 'a';
+    }
+    tsptr++;
+  } while ( Value );
+//Reverse String
+  *tsptr = 0;
+  tsptr--;
+  while ( tsptr > rsptr ) {
+    ch1 = *tsptr;
+    ch2 = *rsptr;
+    *rsptr = ch1;
+    *tsptr = ch2;
+    tsptr--;
+    rsptr++;
+  }
+}
+
+VOID
+InitSerialOut (
+  )
+{
+  UINT8 Data;
+  UINT16   Divisor;
+  Data = 0x87;
+  WriteIO (COM_BASE_ADDRESS + 0x3, AccWidthUint8, &Data);
+  Divisor = 115200 / DIVISOR;
+  Data = Divisor & 0xFF;
+  WriteIO (COM_BASE_ADDRESS + 0x00, AccWidthUint8, &Data);
+  Data = Divisor >> 8;
+  WriteIO (COM_BASE_ADDRESS + 0x01, AccWidthUint8, &Data);
+  Data = 0x07;
+  WriteIO (COM_BASE_ADDRESS + 0x3, AccWidthUint8, &Data);
+}
+
+
+VOID
+SendStringPort (
+  IN       CHAR8* pstr
+  )
+{
+
+  while ( *pstr! = 0 ) {
+    SendBytePort (*pstr);
+    pstr++;
+  }
+}
+
+VOID
+SendBytePort (
+  IN       UINT8 Data
+  )
+{
+  INT8   Count;
+  UINT8 Status;
+  Count = 80;
+  do {
+    ReadIO ((COM_BASE_ADDRESS + 0x05), AccWidthUint8, &Status);
+    if ( Status == 0xff ) {
+      break;
+    }
+    // Loop  port is ready
+  } while ( (Status & 0x20) == 0 && (--Count) != 0 );
+  WriteIO (COM_BASE_ADDRESS + 0x00, AccWidthUint8, &Data);
+}
+#endif
diff --git a/src/vendorcode/amd/cimx/sb900/Dispatcher.c b/src/vendorcode/amd/cimx/sb900/Dispatcher.c
new file mode 100755
index 0000000..152ffc2
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Dispatcher.c
@@ -0,0 +1,261 @@
+/**
+ * @file
+ *
+ *  Function dispatcher.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+*/
+
+
+//
+// Declaration of local functions
+//
+
+VOID  saveConfigPointer (IN AMDSBCFG* pConfig);
+VOID* VerifyImage (IN UINT64 Signature, IN VOID* ImagePtr);
+VOID* LocateImage (IN UINT64 Signature);
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * AmdSbDispatcher - Dispatch Southbridge function
+ *
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+AmdSbDispatcher (
+  IN       VOID *pConfig
+  )
+{
+  AGESA_STATUS      Status;
+  UINT64            tdValue;
+
+#ifdef B1_IMAGE
+  VOID              *pAltImagePtr;
+  CIM_IMAGE_ENTRY   AltImageEntry;
+
+  pAltImagePtr = NULL;
+#endif
+
+  Status = AGESA_UNSUPPORTED;
+  tdValue = 0x313141324E4448ull;
+
+//#if CIM_DEBUG
+//  InitSerialOut ();
+//#endif
+
+  Status = AGESA_UNSUPPORTED;
+  TRACE ((DMSG_SB_TRACE, "CIM - Hudson-2 Entry\n"));
+
+#ifdef B1_IMAGE
+  if ((UINT32) (UINTN) (((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr) != 0xffffffff ) {
+    if ( ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr ) {
+      pAltImagePtr = VerifyImage ( tdValue, (VOID*) (UINTN) ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr);
+    }
+    if ( pAltImagePtr == NULL ) {
+      pAltImagePtr = LocateImage ( tdValue );
+    }
+    if ( pAltImagePtr != NULL ) {
+      ((AMD_CONFIG_PARAMS*)pConfig)->ImageBasePtr = (UINT32) (UINTN) pAltImagePtr;
+      AltImageEntry = (CIM_IMAGE_ENTRY) (UINTN) ((UINT32) (UINTN) pAltImagePtr + (UINT32) (((AMD_IMAGE_HEADER*) (UINTN) pAltImagePtr)->EntryPointAddress));
+      (*AltImageEntry) (pConfig);
+      return Status;
+    }
+  }
+#endif
+  saveConfigPointer (pConfig);
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
+    sbPowerOnInit ((AMDSBCFG*) pConfig);
+  }
+
+#ifndef B1_IMAGE
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
+    sbBeforePciInit ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {
+    sbAfterPciInit ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_MID_POST_INIT ) {
+    sbMidPostInit ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {
+    sbLatePost ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {
+    sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {
+    sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {
+    sbSmmService ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {
+    sbSmmAcpiOn ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
+    sbECfancontrolservice ((AMDSBCFG*)pConfig);
+  }
+#endif
+  TRACE ((DMSG_SB_TRACE, "CIMx - SB Exit\n"));
+  return Status;
+}
+
+/**
+ * LocateImage - Locate Southbridge CIMx module
+ *
+ *
+ *
+ * @param[in] Signature   Southbridge CIMx image signature.
+ *
+ */
+VOID*
+LocateImage (
+  IN       UINT64 Signature
+  )
+{
+  VOID  *Result;
+  UINT32   ImagePtr;
+  ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1);
+
+  while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) {
+#ifdef x64
+    12346789
+#else
+    Result = VerifyImage (Signature, (VOID*) (__int64)ImagePtr);
+#endif
+    if ( Result != NULL ) {
+      return Result;
+    }
+    ImagePtr -= IMAGE_ALIGN;
+  }
+  return NULL;
+}
+
+/**
+ * VerifyImage - Verify Southbridge CIMx module
+ *
+ *
+ * @param[in] Signature   Southbridge CIMx image signature.
+ * @param[in] ImagePtr    Southbridge CIMx image address.
+ *
+ */
+VOID*
+VerifyImage (
+  IN       UINT64 Signature,
+  IN       VOID* ImagePtr
+  )
+{
+  UINT16 *TempImagePtr;
+  UINT16 Sum;
+  UINT32  i;
+  Sum = 0;
+//  if ( (*((UINT32*)ImagePtr) == 'DMA$' && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {
+  if ( (*((UINT32*)ImagePtr) == Int32FromChar('D', 'M', 'A', '$') && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {
+    //GetImage Image size
+    TempImagePtr = (UINT16*)ImagePtr;
+    for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) {
+      Sum = Sum + *TempImagePtr;
+      TempImagePtr++;
+    }
+    if ( Sum == 0 ) {
+      return ImagePtr;
+    }
+  }
+  return NULL;
+}
+
+/**
+ * saveConfigPointer - Verify Southbridge CIMx module
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+VOID
+saveConfigPointer (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8   dbReg;
+  UINT8   i;
+  UINT32   ddValue;
+
+  ddValue =  (UINT32) (UINTN)pConfig;
+  dbReg = SB_ECMOS_REG08;
+
+  for ( i = 0; i <= 3; i++ ) {
+    WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
+    WriteIO (SB_IOMAP_REG73, AccWidthUint8, (UINT8*)&ddValue);
+    ddValue = (ddValue >> 8);
+    dbReg++;
+  }
+}
diff --git a/src/vendorcode/amd/cimx/sb900/Ec.c b/src/vendorcode/amd/cimx/sb900/Ec.c
new file mode 100755
index 0000000..ed79a59
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Ec.c
@@ -0,0 +1,128 @@
+
+/**
+ * @file
+ *
+ * Config Southbridge EC Controller
+ *
+ * Init EC features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+#ifndef NO_EC_SUPPORT
+
+/**
+ * Config EC controller during power-on
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+ecPowerOnInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  //Enable config mode
+  EnterEcConfig ();
+
+  //Do settings for mailbox - logical device 0x09
+  RWEC8 (0x07, 0x00, 0x09);               //switch to device 9 (Mailbox)
+  RWEC8 (0x60, 0x00, (MailBoxPort >> 8));    //set MSB of Mailbox port
+  RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF));  //set LSB of Mailbox port
+  RWEC8 (0x30, 0x00, 0x01);               //;Enable Mailbox Registers Interface, bit0=1
+
+  if ( pConfig->BuildParameters.EcKbd == ENABLED) {
+    //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
+
+    //Disable LPC Decoding of port 60/64
+    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0);
+
+    //Enable logical device 0x07 (Keyboard controller)
+    RWEC8 (0x07, 0x00, 0x07);
+    RWEC8 (0x30, 0x00, 0x01);
+  }
+
+  if (isImcEnabled () && ( pConfig->BuildParameters.EcChannel0 == ENABLED)) {
+    //Logical device 0x03
+    RWEC8 (0x07, 0x00, 0x03);
+    RWEC8 (0x60, 0x00, 0x00);
+    RWEC8 (0x61, 0x00, 0x62);
+    RWEC8 (0x30, 0x00, 0x01);            //;Enable Device 3
+  }
+
+  //Enable EC (IMC) to generate SMI to BIOS
+  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6);
+  ExitEcConfig ();
+}
+
+/**
+ * Config EC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+ecInitBeforePciEnum (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  AMDSBCFG*     pTmp;                                    // dummy code
+  pTmp = pConfig;
+}
+
+/**
+ * Prepare EC controller to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+ecInitLatePost (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  AMDSBCFG*     pTmp;                                    // dummy code
+  pTmp = pConfig;
+}
+#endif
diff --git a/src/vendorcode/amd/cimx/sb900/EcFan.h b/src/vendorcode/amd/cimx/sb900/EcFan.h
new file mode 100755
index 0000000..27940e5
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/EcFan.h
@@ -0,0 +1,66 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+
+void WriteECmsg (IN unsigned char  Address, IN unsigned char OpFlag, IN void* Value);
+void WaitForEcLDN9MailboxCmdAck (void);
+void ReadECmsg (IN unsigned char  Address, IN unsigned char OpFlag, OUT void* Value);
+
+// IMC Message Register Software Interface
+#define CPU_MISC_BUS_DEV_FUN  ((0x18 << 3) + 3)
+
+#define MSG_SYS_TO_IMC  0x80
+#define Fun_80  0x80
+#define Fun_81  0x81
+#define Fun_82  0x82
+#define Fun_83  0x83
+#define Fun_84  0x84
+#define Fun_85  0x85
+#define Fun_86  0x86
+#define Fun_87  0x87
+#define Fun_88  0x88
+#define Fun_89  0x89
+#define Fun_90  0x90
+#define MSG_IMC_TO_SYS  0x81
+#define MSG_REG0  0x82
+#define MSG_REG1  0x83
+#define MSG_REG2  0x84
+#define MSG_REG3  0x85
+#define MSG_REG4  0x86
+#define MSG_REG5  0x87
+#define MSG_REG6  0x88
+#define MSG_REG7  0x89
+#define MSG_REG8  0x8A
+#define MSG_REG9  0x8B
+#define MSG_REGA  0x8C
+#define MSG_REGB  0x8D
+#define MSG_REGC  0x8E
+#define MSG_REGD  0x8F
+
+
diff --git a/src/vendorcode/amd/cimx/sb900/EcFanLib.c b/src/vendorcode/amd/cimx/sb900/EcFanLib.c
new file mode 100755
index 0000000..aa75556
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/EcFanLib.c
@@ -0,0 +1,285 @@
+/**
+ * @file
+ *
+ * Southbridge EC IO access common routine
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+VOID
+ReadECmsg (
+  IN       UINT8 Address,
+  IN       UINT8 OpFlag,
+     OUT   VOID* Value
+  )
+{
+ UINT8 i;
+
+  OpFlag = OpFlag & 0x7f;
+  if (OpFlag == 0x02) OpFlag = 0x03;
+  WriteIo8((UINT16) (0x3E), Address);  // EC_LDN9_MAILBOX_BASE_ADDRESS
+  i = ReadIo8((UINT16) (0x3F));   // EC_LDN9_MAILBOX_BASE_ADDRESS
+  *((UINT8*) (Value)) = i;
+}
+
+
+VOID
+WriteECmsg (
+  IN       UINT8 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+ UINT8 i;
+
+  OpFlag = OpFlag & 0x7f;
+  if (OpFlag == 0x02) OpFlag = 0x03;
+  WriteIo8(0x3E, Address);  // EC_LDN9_MAILBOX_BASE_ADDRESS
+  i = *(UINT8*)Value;
+  WriteIo8(0x3F, i);   // EC_LDN9_MAILBOX_BASE_ADDRESS
+}
+
+VOID
+WaitForEcLDN9MailboxCmdAck (
+  VOID
+  )
+{
+  UINT8 Msgdata;
+  UINT16 Delaytime;
+  Msgdata = 0;
+  for (Delaytime = 0; Delaytime <= 500; Delaytime++) {
+    ReadECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
+    if ( Msgdata == 0xfa) {
+      break;
+    }
+    cimSbStall (1000); // Wait for 1ms
+  }
+}
+
+/**
+ * imcDisableSurebootTimer - IMC Disable Sureboot Timer.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+imcDisableSurebootTimer (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 Msgdata;
+
+  if (!(isImcEnabled ()) ) {
+    return; //IMC is not enabled
+  }
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
+  Msgdata = 0x01;
+  WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
+  Msgdata = 0x94;
+  WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
+  WaitForEcLDN9MailboxCmdAck ();
+}
+
+/**
+ * imcDisarmSurebootTimer - IMC Disarm Sureboot Timer.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+imcDisarmSurebootTimer (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  imcDisableSurebootTimer (pConfig);
+  pConfig->imc.imcSureBootTimer = 0;
+}
+
+/**
+ * imcEnableSurebootTimer - IMC Enable Sureboot Timer.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+imcEnableSurebootTimer (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 Msgdata;
+
+  imcDisableSurebootTimer (pConfig);
+
+  Msgdata = 0x00;
+  if (!(isImcEnabled ()) || (pConfig->imc.imcSureBootTimer == 0)) {
+    return; //IMC is not enabled
+  }
+  WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
+  Msgdata = 0x01;
+  WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
+  Msgdata = ( (pConfig->imc.imcSureBootTimer) << 6) -1;
+  WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
+  Msgdata = 0x94;
+  WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
+  WaitForEcLDN9MailboxCmdAck ();
+}
+
+/**
+ * imcSleep - IMC Sleep.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+imcSleep (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 Msgdata;
+
+  if (!(isImcEnabled ()) ) {
+    return; //IMC is not enabled
+  }
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
+  Msgdata = 0xB4;
+  WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
+  Msgdata = 0x96;
+  WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
+  WaitForEcLDN9MailboxCmdAck ();
+}
+
+/**
+ * imcWakeup - IMC Wakeup.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+imcWakeup (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 Msgdata;
+
+  if (!(isImcEnabled ()) ) {
+    return; //IMC is not enabled
+  }
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
+  Msgdata = 0xB5;
+  WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
+  Msgdata = 0x96;
+  WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
+  WaitForEcLDN9MailboxCmdAck ();
+}
+
+/**
+ * imcIdle - IMC Idle.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+imcIdle (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 Msgdata;
+
+  if (!(isImcEnabled ()) ) {
+    return; //IMC is not enabled
+  }
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
+  Msgdata = 0x01;
+  WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
+  Msgdata = 0x00;
+  WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
+  Msgdata = 0x98;
+  WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
+  WaitForEcLDN9MailboxCmdAck ();
+}
+
+VOID
+imcThermalZoneEnable (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8   Msgdata;
+  UINT8   ZoneNum;
+  BOOLEAN IsSendEcMsg;
+
+  if (!(isImcEnabled ()) ) {
+    return; //IMC is not enabled
+  }
+
+  for ( ZoneNum = 0; ZoneNum < 4; ZoneNum++ ) {
+    IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, 0, ZoneNum);
+    if (IsSendEcMsg) {
+      Msgdata = 0x00;
+      WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
+      Msgdata = ZoneNum;
+      WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
+      Msgdata = 0x80;
+      WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
+      WaitForEcLDN9MailboxCmdAck ();
+
+      Msgdata = 0x00;
+      WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
+      Msgdata = ZoneNum;
+      WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
+      ReadECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
+      Msgdata |= BIT0;
+      WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
+      Msgdata = 0x81;
+      WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
+      WaitForEcLDN9MailboxCmdAck ();
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/cimx/sb900/EcFanc.c b/src/vendorcode/amd/cimx/sb900/EcFanc.c
new file mode 100755
index 0000000..76a3b55
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/EcFanc.c
@@ -0,0 +1,189 @@
+/*;********************************************************************************
+;
+;Copyright (c) 2011, Advanced Micro Devices, Inc.
+;All rights reserved.
+;
+;Redistribution and use in source and binary forms, with or without
+;modification, are permitted provided that the following conditions are met:
+;    * Redistributions of source code must retain the above copyright
+;      notice, this list of conditions and the following disclaimer.
+;    * Redistributions in binary form must reproduce the above copyright
+;      notice, this list of conditions and the following disclaimer in the
+;      documentation and/or other materials provided with the distribution.
+;    * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;      its contributors may be used to endorse or promote products derived 
+;      from this software without specific prior written permission.
+;
+;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+;ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+;DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+;(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+;LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+;ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+;SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+/**
+ * Table for Function Number
+ *
+ *
+ *
+ *
+ */
+UINT8 FunctionNumber[] =
+{
+  Fun_81,
+  Fun_83,
+  Fun_85,
+  Fun_89,
+};
+
+/**
+ * Table for Max Thermal Zone
+ *
+ *
+ *
+ *
+ */
+UINT8 MaxZone[] =
+{
+  4,
+  4,
+  4,
+  4,
+};
+
+/**
+ * Table for Max Register
+ *
+ *
+ *
+ *
+ */
+UINT8 MaxRegister[] =
+{
+  MSG_REG9,
+  MSG_REGB,
+  MSG_REG9,
+  MSG_REGA,
+};
+/*-------------------------------------------------------------------------------
+;Procedure:  IsZoneFuncEnable
+;
+;Description:  This routine will check every zone support function with BitMap from user define
+;
+;
+;Exit:  None
+;
+;Modified:  None
+;
+;-----------------------------------------------------------------------------
+*/
+BOOLEAN
+IsZoneFuncEnable (
+  IN     UINT16 Flag,
+  IN     UINT8  func,
+  IN     UINT8  Zone
+  )
+{
+  return (BOOLEAN) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone));
+}
+
+/*-------------------------------------------------------------------------------
+;Procedure:  sbECfancontrolservice
+;
+;Description:  This routine service EC fan policy
+;
+;
+;Exit:  None
+;
+;Modified:  None
+;
+;-----------------------------------------------------------------------------
+*/
+VOID
+sbECfancontrolservice (
+  IN     AMDSBCFG* pConfig
+  )
+{
+  UINT8 ZoneNum;
+  UINT8 FunNum;
+  UINT8 RegNum;
+  UINT8 * CurPoint;
+  UINT8 FunIndex;
+  BOOLEAN IsSendEcMsg;
+  if (!isImcEnabled ()) {
+    return; //IMC is not enabled
+  }
+
+  CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
+  for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
+    FunNum = FunctionNumber[FunIndex];
+    for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
+      IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
+      if (IsSendEcMsg) {
+        for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
+          WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
+          CurPoint += 1;
+        }
+        WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
+        WaitForEcLDN9MailboxCmdAck ();
+      } else {
+        CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
+      }
+    }
+  }
+  CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0;
+  for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
+    FunNum = FunctionNumber[FunIndex];
+    for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
+      IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
+      if (IsSendEcMsg) {
+        for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
+          if (RegNum == MSG_REG2) {
+            *CurPoint &= 0xFE;
+          }
+          WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
+          CurPoint += 1;
+        }
+        WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
+        WaitForEcLDN9MailboxCmdAck ();
+      } else {
+        CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
+      }
+    }
+  }
+}
+
+/*-------------------------------------------------------------------------------
+;Procedure:  hwmImcInit
+;
+;Description:  This routine Init EC fan policy
+;
+;
+;Exit:  None
+;
+;Modified:  None
+;
+;-----------------------------------------------------------------------------
+*/
+VOID
+hwmImcInit (
+  IN     AMDSBCFG* pConfig
+  )
+{
+  imcWakeup ( pConfig);
+  if ( pConfig->hwm.hwmSbtsiAutoPoll == FALSE ) {
+    sbECfancontrolservice (pConfig);
+  }
+}
+
+
diff --git a/src/vendorcode/amd/cimx/sb900/EcLib.c b/src/vendorcode/amd/cimx/sb900/EcLib.c
new file mode 100755
index 0000000..79131bf
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/EcLib.c
@@ -0,0 +1,153 @@
+/**
+ * @file
+ *
+ * Southbridge EC IO access common routine
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+// #ifndef NO_EC_SUPPORT
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * EnterEcConfig - Force EC into Config mode
+ *
+ *
+ *
+ *
+ */
+VOID
+EnterEcConfig (
+  )
+{
+  UINT16   dwEcIndexPort;
+
+  ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+  dwEcIndexPort &= ~(BIT0);
+  RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ExitEcConfig - Force EC exit Config mode
+ *
+ *
+ *
+ *
+ */
+VOID
+ExitEcConfig (
+  )
+{
+  UINT16   dwEcIndexPort;
+
+  ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+  dwEcIndexPort &= ~(BIT0);
+  RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ReadEC8 - Read EC register data
+ *
+ *
+ *
+ * @param[in] Address  - EC Register Offset Value
+ * @param[in] Value    - Read Data Buffer
+ *
+ */
+VOID
+ReadEC8 (
+  IN       UINT8 Address,
+  IN       UINT8* Value
+  )
+{
+  UINT16   dwEcIndexPort;
+
+  ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+  dwEcIndexPort &= ~(BIT0);
+  WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
+  ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * WriteEC8 - Write date into EC register
+ *
+ *
+ *
+ * @param[in] Address  - EC Register Offset Value
+ * @param[in] Value    - Write Data Buffer
+ *
+ */
+VOID
+WriteEC8 (
+  IN       UINT8 Address,
+  IN       UINT8* Value
+  )
+{
+  UINT16   dwEcIndexPort;
+
+  ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+  dwEcIndexPort &= ~(BIT0);
+
+  WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
+  WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RWEC8 - Read/Write EC register
+ *
+ *
+ *
+ * @param[in] Address    - EC Register Offset Value
+ * @param[in] AndMask    - Data And Mask 8 bits
+ * @param[in] OrMask     - Data OR Mask 8 bits
+ *
+ */
+VOID
+RWEC8 (
+  IN       UINT8 Address,
+  IN       UINT8 AndMask,
+  IN       UINT8 OrMask
+  )
+{
+  UINT8 Result;
+  ReadEC8 (Address, &Result);
+  Result = (Result & AndMask) | OrMask;
+  WriteEC8 (Address, &Result);
+}
+
+// #endif
+
diff --git a/src/vendorcode/amd/cimx/sb900/Gec.c b/src/vendorcode/amd/cimx/sb900/Gec.c
new file mode 100755
index 0000000..cfd830d
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Gec.c
@@ -0,0 +1,141 @@
+/**
+ * @file
+ *
+ * Config Southbridge GEC controller
+ *
+ * Init GEC features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+/**
+ * gecInitBeforePciEnum - Config GEC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+gecInitBeforePciEnum (
+  IN       AMDSBCFG*   pConfig
+  )
+{
+  UINT8 cimSBGecDebugBus;
+  UINT8 cimSBGecPwr;
+
+  cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus;
+  cimSBGecPwr = (UINT8) pConfig->SBGecPwr;
+#if  (SB_CIMx_PARAMETER == 0 )
+  cimSBGecDebugBus = cimSBGecDebugBusDefault;
+  cimSBGecPwr = cimSBGecPwrDefault;
+#endif
+  if ( pConfig->Cg2Pll == 1 ) {
+    pConfig->GecConfig = 1;
+  }
+  if ( pConfig->GecConfig == 0) {
+    // GEC Enabled
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00);
+
+    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00);
+    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01);
+    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01);
+    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01);
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5));
+
+    if (  cimSBGecDebugBus == 1) {
+      // GEC Debug Bus Enabled
+      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3);
+    } else {
+      // GEC Debug Bus Disabled
+      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00);
+    }
+  } else {
+    // GEC Disabled
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0);
+    //return;   //return if GEC controller is disabled.
+  }
+}
+
+/**
+ * gecInitAfterPciEnum - Config GEC controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+gecInitAfterPciEnum (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  VOID* GecRomAddress;
+  VOID* GecShadowRomAddress;
+  UINT32 ddTemp;
+  if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) {
+    GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
+    GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
+    AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
+    ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp);
+    ddTemp = ddTemp & 0xFFFFFFF0;
+    RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29);
+  }
+  TRACE ((DMSG_SB_TRACE, "Exiting gec Init after PCI emulation\n"));
+}
+
+/**
+ * gecInitLatePost - Prepare GEC controller to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+gecInitLatePost (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  if ( !pConfig->GecConfig == 0) {
+    return;   //return if GEC controller is disabled.
+  }
+  TRACE ((DMSG_SB_TRACE, "Exiting Prepare GEC controller to boot to OS\n"));
+}
+
+
diff --git a/src/vendorcode/amd/cimx/sb900/Gpp.c b/src/vendorcode/amd/cimx/sb900/Gpp.c
new file mode 100755
index 0000000..b87bd87
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Gpp.c
@@ -0,0 +1,1109 @@
+
+/**
+ * @file
+ *
+ * Config Southbridge GPP controller
+ *
+ * Init GPP features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+****************************************************************************
+*/
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+/**
+ * PCIE_CAP_ID - PCIe Cap ID
+ *
+ */
+#define  PCIE_CAP_ID             0x10
+
+//
+// Declaration of local functions
+//
+UINT8
+sbFindPciCap (
+  IN       UINT32  pciAddress,
+  IN       UINT8  targetCapId
+  );
+
+VOID
+sbGppSetAspm (
+  IN       UINT32    pciAddress,
+  IN       UINT8     LxState
+  );
+
+VOID
+sbGppSetEPAspm (
+  IN       UINT32    pciAddress,
+  IN       UINT8     LxState
+  );
+
+VOID
+sbGppValidateAspm (
+  IN       UINT32    pciAddress,
+  IN       UINT8     *LxState
+  );
+
+VOID
+sbGppForceGen2 (
+  IN       AMDSBCFG        *pConfig,
+  IN       CONST UINT8     ActivePorts
+  );
+
+VOID
+sbGppForceGen1 (
+  IN       AMDSBCFG      *pConfig,
+  IN       CONST UINT8   ActivePorts
+  );
+
+VOID
+PreInitGppLink (
+  IN       AMDSBCFG* pConfig
+  );
+
+UINT8
+GppPortPollingLtssm (
+  IN       AMDSBCFG*      pConfig,
+  IN       UINT8          ActivePorts,
+  IN       BOOLEAN        IsGen2
+  );
+
+UINT8
+CheckGppLinkStatus (
+  IN       AMDSBCFG* pConfig
+  );
+
+VOID
+AfterGppLinkInit (
+  IN       AMDSBCFG* pConfig
+  );
+
+VOID
+sbGppDynamicPowerSaving (
+  IN       AMDSBCFG* pConfig
+  );
+
+VOID
+sbGppAerInitialization (
+  IN       AMDSBCFG* pConfig
+  );
+
+VOID
+sbGppRasInitialization (
+  IN     AMDSBCFG*   pConfig
+  );
+
+//
+// Declaration of external functions
+//
+
+
+/**
+ * sbFindPciCap - Find PCI Cap
+ *
+ *
+ * @param[in] pciAddress     PCI Address.
+ * @param[in] targetCapId    Target Cap ID.
+ *
+ */
+UINT8
+sbFindPciCap (
+  IN       UINT32  pciAddress,
+  IN       UINT8  targetCapId
+  )
+{
+  UINT8       NextCapPtr;
+  UINT8       CapId;
+
+  NextCapPtr = 0x34;
+  while (NextCapPtr != 0) {
+    ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &NextCapPtr);
+    if (NextCapPtr == 0xff) {
+      return 0;
+    }
+    if (NextCapPtr != 0) {
+      ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &CapId);
+      if (CapId == targetCapId) {
+        break;
+      } else {
+        NextCapPtr++;
+      }
+    }
+  }
+  return NextCapPtr;
+}
+
+/**
+ * sbGppSetAspm - Set GPP ASPM
+ *
+ *
+ * @param[in] pciAddress PCI Address.
+ * @param[in] LxState    Lane State.
+ *
+ */
+VOID
+sbGppSetAspm (
+  IN       UINT32    pciAddress,
+  IN       UINT8     LxState
+  )
+{
+  UINT8      pcieCapOffset;
+  UINT8      value8;
+
+  pcieCapOffset = sbFindPciCap (pciAddress, PCIE_CAP_ID);
+  if (pcieCapOffset) {
+    // Read link capabilities register (0x0C[11:10] - ASPM support)
+    ReadPCI (pciAddress + pcieCapOffset + 0x0D, AccWidthUint8, &value8);
+    if (value8 & BIT2) {
+      value8 = (value8 >> 2) & (BIT1 + BIT0);
+      // Set ASPM state in link control register
+      RWPCI (pciAddress + pcieCapOffset + 0x10, AccWidthUint8, 0xffffffff, LxState & value8);
+    }
+  }
+}
+
+/**
+ * sbGppSetEPAspm - Set EP GPP ASPM
+ *
+ *
+ * @param[in] pciAddress PCI Address.
+ * @param[in] LxState    Lane State.
+ *
+ */
+VOID
+sbGppSetEPAspm (
+  IN       UINT32    pciAddress,
+  IN       UINT8     LxState
+  )
+{
+  UINT8      value8;
+  UINT8      maxFuncs;
+  UINT32     devBDF;
+
+  maxFuncs = 1;
+  ReadPCI (pciAddress + 0x0E, AccWidthUint8, &value8);
+
+  if (value8 & BIT7) {
+    maxFuncs = 8;              // multi-function device
+  }
+  while (maxFuncs != 0) {
+    devBDF = pciAddress + (UINT32) ((maxFuncs - 1) << 16);
+    sbGppSetAspm (devBDF, LxState);
+    maxFuncs--;
+  }
+}
+
+/**
+ * sbGppValidateAspm - Validate endpoint support for GPP ASPM
+ *
+ *
+ * @param[in] pciAddress PCI Address.
+ * @param[in] LxState    Lane State.
+ *
+ */
+VOID
+sbGppValidateAspm (
+  IN       UINT32    pciAddress,
+  IN       UINT8     *LxState
+  )
+{
+  UINT8      pcieCapOffset;
+  UINT8      value8;
+  UINT8      maxFuncs;
+  UINT32     devBDF;
+
+  maxFuncs = 1;
+  ReadPCI (pciAddress + 0x0E, AccWidthUint8, &value8);
+
+  if (value8 & BIT7) {
+    maxFuncs = 8;              // multi-function device
+  }
+  while (maxFuncs != 0) {
+    devBDF = pciAddress + (UINT32) ((maxFuncs - 1) << 16);
+    pcieCapOffset = sbFindPciCap (devBDF, PCIE_CAP_ID);
+    if (pcieCapOffset) {
+      // Read link capabilities register (0x0C[11:10] - ASPM support)
+      ReadPCI (devBDF + pcieCapOffset + 0x0D, AccWidthUint8, &value8);
+      if (value8 & BIT2) {
+        value8 = (value8 >> 2) & (BIT1 + BIT0);
+        // Set ASPM state as what's endpoint support
+        *LxState &= value8;
+      }
+    }
+    maxFuncs--;
+  }
+}
+
+
+/**
+ * sbGppForceGen2 - Set GPP to Gen2
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ * @param[in] ActivePorts Activate Ports.
+ *
+ */
+VOID
+sbGppForceGen2 (
+  IN       AMDSBCFG        *pConfig,
+  IN       CONST UINT8     ActivePorts
+  )
+{
+  UINT32       portId;
+
+  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
+    if (ActivePorts & (1 << portId)) {
+      rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29 + BIT0);
+      rwAlink ((SB_ABCFG_REG340 + portId * 4) | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT21);
+      rwAlink (SB_RCINDXP_REGA2 | portId << 24, ~BIT13, 0);
+      rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0);
+      RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x02);
+
+      (&pConfig->PORTCONFIG[portId].PortCfg)->PortIsGen2 = 2;
+    }
+  }
+}
+
+/**
+ * sbGppForceGen1 - Set GPP to Gen1
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ * @param[in] ActivePorts Activate Ports.
+ *
+ */
+VOID
+sbGppForceGen1 (
+  IN       AMDSBCFG      *pConfig,
+  IN       CONST UINT8   ActivePorts
+  )
+{
+  UINT32       portId;
+
+  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
+    if (ActivePorts & (1 << portId) && pConfig->GppHardwareDowngrade != portId + 1) {
+      rwAlink ((SB_ABCFG_REG340 + portId * 4) | (UINT32) (ABCFG << 29), ~BIT21, 0);
+      rwAlink (SB_RCINDXP_REGA4 | portId << 24, ~BIT0, BIT29);
+      rwAlink (SB_RCINDXP_REGA2 | portId << 24, 0xFFFFFFFF, BIT13);
+      rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0);
+      RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x01);
+
+      (&pConfig->PORTCONFIG[portId].PortCfg)->PortIsGen2 = 1;
+    }
+  }
+}
+
+
+/**
+ * PreInitGppLink - Enable GPP link training.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+PreInitGppLink (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 portMask[5] = {
+    0x01,
+    0x00,
+    0x03,
+    0x07,
+    0x0F
+  };
+  UINT8  cfgMode;
+  UINT8  portId;
+  UINT32 reg32Value;
+  UINT16 tmp16Value;
+
+//  PCIE_GPP_ENABLE (abcfg:0xC0):
+//
+//     GPP_LINK_CONFIG ([3:0])  PortA   PortB   PortC   PortD    Description
+//    ----------------------------------------------------------------------------------
+//                       0000    0-3                             x4 Config
+//                       0001                                    N/A
+//                       0010    0-1     2-3      0              2:2 Config
+//                       0011    0-1      2       3              2:1:1 Config
+//                       0100     0       1       2       3      1:1:1:1 Config
+//
+//  For A12 and above:
+//                  ABCFG:0xC0[12] - Port A hold training (default 1)
+//                  ABCFG:0xC0[13] - Port B hold training (default 1)
+//                  ABCFG:0xC0[14] - Port C hold training (default 1)
+//                  ABCFG:0xC0[15] - Port D hold training (default 1)
+//
+//
+  //
+  // Set port enable bit fields based on current GPP link configuration mode
+  //
+  cfgMode = (UINT8) pConfig->GppLinkConfig;
+  if ( cfgMode > GPP_CFGMODE_X1111 || cfgMode == 1 ) {
+    cfgMode = GPP_CFGMODE_X4000;
+    pConfig->GppLinkConfig = GPP_CFGMODE_X4000;
+  }
+  reg32Value = (UINT32) portMask[cfgMode];
+
+  // Mask out non-applicable ports according to the target link configuration mode
+  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
+    pConfig->PORTCONFIG[portId].PortCfg.PortPresent &= (reg32Value >> portId) & BIT0;
+  }
+
+  //
+  // Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
+  //
+  tmp16Value = (UINT16) (~reg32Value << 12);
+  reg32Value = (UINT32) (tmp16Value + (reg32Value << 4) + cfgMode);
+  writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), reg32Value);
+
+  reg32Value = readAlink (0xC0 | (UINT32) (RCINDXC << 29));
+  writeAlink (0xC0 | (UINT32) (RCINDXC << 29), reg32Value | 0x400);  // Set STRAP_F0_MSI_EN
+
+  // A-Link L1 Entry Delay Shortening
+  // AXINDP_Reg 0xA0[7:4] = 0x3
+  rwAlink (SB_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30);
+  rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19);
+  rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28);
+
+  // RPR5.22 GPP L1 Entry Delay Shortening
+  // RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request.
+  // This is done to reduce number of NAK received with L1 enabled.
+  // ENH254401: Program L0S/L1 activity timer to enable L0S/L1 on GPP
+  // RCINDP_Reg 0xA0[11:8] = 0x9
+  // RCINDP_Reg 0xA0[15:12] = 0x6
+  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
+    rwAlink (SB_RCINDXP_REGA0 | portId << 24, 0xFFFF000F, 0x6910);
+    //OBS220313: Hard System Hang running MeatGrinder Test on multiple blocks
+    //RPR 5.13 GPP Error Reporting Configuration
+    rwAlink (SB_RCINDXP_REG6A | portId << 24, ~(BIT1), 0);
+  }
+
+  if (pConfig->S3Resume) {
+    SBGPPPORTCONFIG  *portCfg;
+
+    for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
+      portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
+      if (portCfg->PortHotPlug == TRUE) {
+        portCfg->PortDetected = FALSE;
+      } else {
+        if (portCfg->PortIsGen2 == 1) {
+          sbGppForceGen1 (pConfig, (UINT8) (1 << portId));
+        } else {
+          sbGppForceGen2 (pConfig, (UINT8) (1 << portId));
+        }
+      }
+    }
+  }
+
+  // Obtain original Gen2 strap value (LC_GEN2_EN_STRAP)
+  pConfig->GppGen2Strap = (UINT8) (readAlink (SB_RCINDXP_REGA4 | 0 << 24) & BIT0);
+}
+
+
+/**
+ * GppPortPollingLtssm - Loop polling the LTSSM for each GPP port marked in PortMap
+ *
+ *
+ * Return:     FailedPortMap   = A bitmap of ports which failed to train
+ *
+ * @param[in]    pConfig      Southbridge configuration structure pointer.
+ * @param[in]    ActivePorts  A bitmap of ports which should be polled
+ * @param[in]    IsGen2       TRUE if the polling is in Gen2 mode
+ *
+ */
+UINT8
+GppPortPollingLtssm (
+  IN       AMDSBCFG*      pConfig,
+  IN       UINT8          ActivePorts,
+  IN       BOOLEAN        IsGen2
+  )
+{
+  UINT32            retryCounter;
+  UINT8             PortId;
+  UINT8             FailedPorts;
+  SBGPPPORTCONFIG  *portCfg;
+  UINT32            abIndex;
+  UINT32            Data32;
+  UINT8             EmptyPorts;
+
+  FailedPorts = 0;
+  retryCounter = MAX_LT_POLLINGS;
+  EmptyPorts = ActivePorts;
+
+  while (retryCounter-- && ActivePorts) {
+    for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) {
+      if (ActivePorts & (1 << PortId)) {
+        portCfg = &pConfig->PORTCONFIG[PortId].PortCfg;
+        abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (PortId << 24);
+        Data32 = readAlink (abIndex) & 0x3F3F3F3F;
+
+        if ((UINT8) (Data32) > 0x04) {
+          EmptyPorts &= ~(1 << PortId);
+        }
+
+        if ((UINT8) (Data32) == 0x10) {
+          ActivePorts &= ~(1 << PortId);
+          portCfg->PortDetected = TRUE;
+          break;
+        }
+        if (IsGen2) {
+          UINT8      i;
+
+          for (i = 0; i < 4; i++) {
+            if ((UINT8) (Data32) == 0x29 || (UINT8) (Data32) == 0x2A ) {
+              ActivePorts &= ~(1 << PortId);
+              FailedPorts |= (1 << PortId);
+              break;
+            }
+            Data32 >>= 8;
+          }
+        }
+      }
+    }
+    if (EmptyPorts && retryCounter < (MAX_LT_POLLINGS - 200)) {
+      ActivePorts &= ~EmptyPorts;
+    }
+    SbStall (1000);
+  }
+  FailedPorts |= ActivePorts;
+  return FailedPorts;
+}
+
+
+/**
+ * CheckGppLinkStatus - loop polling the link status for each GPP port
+ *
+ *
+ * Return:     ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+UINT8
+CheckGppLinkStatus (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32            portId;
+  UINT8             portScanMap;
+  UINT8             GppHwDowngrade;
+  SBGPPPORTCONFIG  *portCfg;
+  UINT8             FailedPorts;
+
+
+  portScanMap = 0;
+  FailedPorts = 0;
+
+  // Obtain a list of ports to be checked
+  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
+    portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
+    if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) {
+      portScanMap |= 1 << portId;
+    }
+  }
+  GppHwDowngrade = (UINT8)pConfig->GppHardwareDowngrade;
+  if (GppHwDowngrade != 0) {
+    // Skip polling and always assume this port to be present
+    portScanMap &= ~(1 << (GppHwDowngrade - 1));
+  }
+
+  //GPP Gen2 Speed Change
+  // if ((GPP Gen2 == enabled) and (RCINDP_Reg 0xA4[0] == 0x1)) {
+  //   PCIe_Cfg 0x88[3:0]  = 0x2
+  //   RCINDP_Reg 0xA2[13] = 0x0
+  //   RCINDP_Reg 0xC0[15] = 0x0
+  //   RCINDP_Reg 0xA4[29] = 0x1
+  // } else {
+  //   PCIe_Cfg 0x88[3:0]  = 0x1
+  //   RCINDP_Reg 0xA4[0]  = 0x0
+  //   RCINDP_Reg 0xA2[13] = 0x1
+  //   RCINDP_Reg 0xC0[15] = 0x0
+  //   RCINDP_Reg 0xA4[29] = 0x1
+  // }
+  SbStall (5000);
+  if (pConfig->GppGen2 && pConfig->GppGen2Strap) {
+    sbGppForceGen2 (pConfig, portScanMap);
+    FailedPorts = GppPortPollingLtssm (pConfig, portScanMap, TRUE);
+
+    if (FailedPorts) {
+      sbGppForceGen1 (pConfig, FailedPorts);
+      FailedPorts = GppPortPollingLtssm (pConfig, FailedPorts, FALSE);
+    }
+  } else {
+    sbGppForceGen1 (pConfig, portScanMap);
+    FailedPorts = GppPortPollingLtssm (pConfig, portScanMap, FALSE);
+  }
+  return FailedPorts;
+}
+
+
+/**
+ * AfterGppLinkInit
+ *       - Search for display device behind each GPP port
+ *       - If the port is empty AND not hotplug-capable:
+ *           * Turn off link training
+ *           * (optional) Power down the port
+ *           * Hide the configuration space (Turn off the port)
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+AfterGppLinkInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32           portId;
+  SBGPPPORTCONFIG  *portCfg;
+  UINT32           regBusNumber;
+  UINT32           abValue;
+  UINT32           abIndex;
+  UINT8            bValue;
+  UINT8            cimGppGen2;
+
+  cimGppGen2 = pConfig->GppGen2;
+#if  SB_CIMx_PARAMETER == 0
+  cimGppGen2 = cimGppGen2Default;
+#endif
+
+  pConfig->GppFoundGfxDev = 0;
+  abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
+  //RPR 5.9 Link Bandwidth Notification Capability Enable
+  //RCINDC:0xC1[0] = 1
+  rwAlink (SB_RCINDXC_REGC1, 0xFFFFFFFF, BIT0);
+
+  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
+    // Program requester ID for every port
+    abIndex = SB_RCINDXP_REG21 | (UINT32) (RCINDXP << 29) | (portId << 24);
+    writeAlink (abIndex, (SB_GPP_DEV << 3) + portId);
+
+    //RPR 5.9 Link Bandwidth Notification Capability Enable
+    //PCIe Cfg 0x68[10] = 0
+    //PCIe Cfg 0x68[11] = 0
+    RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x68), AccWidthUint16, ~(BIT10 + BIT11), 0);
+
+    portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
+    // Check if there is GFX device behind each GPP port
+    if ( portCfg->PortDetected == TRUE ) {
+      regBusNumber = (SBTEMP_BUS << 16) + (SBTEMP_BUS << 8);
+      WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, &regBusNumber);
+      // *** Stall ();
+      ReadPCI (PCI_ADDRESS (SBTEMP_BUS, 0, 0, 0x0B), AccWidthUint8, &bValue);
+      if ( bValue == 3 ) {
+        pConfig->GppFoundGfxDev |= (1 << portId);
+      }
+      regBusNumber = 0;
+      WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, &regBusNumber);
+    } else if ( portCfg->PortPresent == FALSE || portCfg->PortHotPlug == FALSE ) {
+      // Mask off non-applicable ports
+      abValue &= ~(1 << (portId + 4));
+    }
+
+    if ( portCfg->PortHotPlug == TRUE ) {
+      // RPR5.12 Hot Plug: PCIe Native Support
+      // RCINDP_Reg 0x10[3] = 0x1
+      // PCIe_Cfg 0x5A[8] = 0x1
+      // PCIe_Cfg 0x6C[6] = 0x1
+      // RCINDP_Reg 0x20[19] = 0x0
+      rwAlink ((SB_RCINDXP_REG10 | (UINT32) (RCINDXP << 29) | (portId << 24)), 0xFFFFFFFF, BIT3);
+      RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x5b), AccWidthUint8, 0xff, BIT0);
+      RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x6c), AccWidthUint8, 0xff, BIT6);
+      rwAlink ((SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24)), ~BIT19, 0);
+    }
+  }
+  if ( pConfig->GppUnhidePorts == FALSE ) {
+    if ((abValue & 0xF0) == 0) {
+      abValue = BIT8;         // if all ports are empty set GPP_RESET
+    } else if ((abValue & 0xE0) != 0 && (abValue & 0x10) == 0) {
+      abValue |= BIT4;        // PortA should always be visible whenever other ports are exist
+    }
+
+    // Update GPP_Portx_Enable (abcfg:0xC0[7:5])
+    writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), abValue);
+  }
+
+  //
+  // Common initialization for open GPP ports
+  //
+  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
+    ReadPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue);
+    if (bValue != 0xff) {
+      // Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0])
+      bValue &= 0xf0;
+      bValue |= 0x06;
+      WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue);
+
+        // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1
+      abIndex = SB_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (portId << 24);
+      abValue = readAlink (abIndex) | BIT19;
+      writeAlink (abIndex, abValue);
+
+        // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0
+      abIndex = SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24);
+      abValue = readAlink (abIndex) & ~BIT19;
+      writeAlink (abIndex, abValue);
+
+        // Set Immediate Ack PM_Active_State_Request_L1 (0xA0:[23]) = 0
+      abIndex = SB_RCINDXP_REGA0 | (UINT32) (RCINDXP << 29) | (portId << 24);
+      abValue = readAlink (abIndex) & ~BIT23;
+      if ( pConfig->L1ImmediateAck == 0) {
+        abValue |= BIT23;
+      }
+      writeAlink (abIndex, abValue);
+    }
+  }
+}
+
+
+/**
+ * sbPcieGppLateInit - Late PCIE initialization for Hudson-2 GPP component
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbPcieGppLateInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8            portId;
+  UINT8            busNum;
+  UINT8            aspmValue;
+  UINT8            PortaspmValue;
+  UINT8            reg8Value;
+  UINT8            cimGppPhyPllPowerDown;
+  SBGPPPORTCONFIG  *portCfg;
+  UINT32           reg32Value;
+
+  // Disable hidden register decode and serial number capability
+  reg32Value = readAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29));
+  writeAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29), reg32Value & ~(BIT26 + BIT10));
+
+  if (readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)) & BIT8) {
+    return;
+  }
+
+  //
+  // Configure ASPM
+  //
+  //  writeAlink (0xC0 | (UINT32) (RCINDXC << 29), 0x400);  // Set STRAP_F0_MSI_EN
+  aspmValue = (UINT8)pConfig->GppPortAspm;
+  cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown;
+#if  SB_CIMx_PARAMETER == 0
+  aspmValue = cimGppPortAspmDefault;
+  cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault;
+#endif
+
+  reg8Value = 0x01;
+  for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {
+    // write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under Vista
+    // when native PCIE is enabled but MSI is not available
+    // SB02029: Hudson-2 BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg
+    portCfg = &pConfig->PORTCONFIG[portId].PortCfg;
+    if (portCfg->PortHotPlug) {
+      RWPCI (PCI_ADDRESS (0, 21, portId, 0x04), AccWidthUint8, 0xFE, 0x00);  //clear IO enable to fix possible hotplug hang
+    }
+    WritePCI (PCI_ADDRESS (0, 21, portId, 0x3d), AccWidthUint8, &reg8Value);
+    ReadPCI (PCI_ADDRESS (0, 21, portId, 0x19), AccWidthUint8, &busNum);
+    if (busNum != 0xFF) {
+      ReadPCI (PCI_ADDRESS (busNum, 0, 0, 0x00), AccWidthUint32, &reg32Value);
+      if (reg32Value != 0xffffffff) {
+        PortaspmValue = aspmValue;
+        // Vlidate if EP support ASPM
+        sbGppValidateAspm (PCI_ADDRESS (busNum, 0, 0, 0), &PortaspmValue);
+        // Set ASPM on EP side
+        sbGppSetEPAspm (PCI_ADDRESS (busNum, 0, 0, 0), PortaspmValue);
+        // Set ASPM on port side
+        sbGppSetAspm (PCI_ADDRESS (0, 21, portId, 0), PortaspmValue);
+      }
+    }
+    rwAlink ((SB_RCINDXP_REG02 | (UINT32) (RCINDXP << 29) | (portId << 24) ), ~(BIT15), (BIT15));
+  }
+  rwAlink ((SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)), ~(BIT0), (BIT0));
+
+  //
+  // Configure Lock HWInit registers
+  //
+  reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
+  if (reg32Value & 0xF0) {
+    reg32Value = readAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29));
+    writeAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), reg32Value | BIT0);  // Set HWINIT_WR_LOCK
+
+    if ( cimGppPhyPllPowerDown == TRUE ) {
+      //
+      // RPR 5.4 Power Saving Feature for GPP Lanes
+      //
+      UINT32  abValue;
+
+      // Set PCIE_P_CNTL in Alink PCIEIND space
+      abValue = readAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29));
+      abValue |= BIT12 + BIT3 + BIT0;
+      abValue &= ~(BIT9 + BIT4);
+      writeAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), abValue);
+      rwAlink (SB_RCINDXC_REG02, ~(BIT8), (BIT8));
+      rwAlink (SB_RCINDXC_REG02, ~(BIT3), (BIT3));
+    }
+  }
+
+  // Restore strap0 via override
+  if (pConfig->PcieAER) {
+    rwAlink (SB_ABCFG_REG310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7);
+    rwAlink (RC_INDXC_REGC0, 0xFFFFFFFF, BIT9);
+  }
+}
+
+
+/**
+ * sbGppDynamicPowerSaving - RPR 5.19 GPP Dynamic Power Saving
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+sbGppDynamicPowerSaving (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  SBGPPPORTCONFIG  *portCfg;
+  UINT8            cimGppLaneReversal;
+  UINT8            cimAlinkPhyPllPowerDown;
+  UINT8            cimGppPhyPllPowerDown;
+  UINT32           Data32;
+  UINT32           HoldData32;
+  UINT32           abValue;
+
+  if (!pConfig->GppDynamicPowerSaving || pConfig->sdbEnable) {
+    return;
+  }
+
+  cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown;
+  cimGppLaneReversal =  (UINT8) pConfig->GppLaneReversal;
+  cimGppPhyPllPowerDown =  (UINT8) pConfig->GppPhyPllPowerDown;
+#if  SB_CIMx_PARAMETER == 0
+  cimGppLaneReversal = cimGppLaneReversalDefault;
+  cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault;
+  cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault;
+#endif
+  if (pConfig->GppHardwareDowngrade) {
+    portCfg = &pConfig->PORTCONFIG[pConfig->GppHardwareDowngrade - 1].PortCfg;
+    portCfg->PortDetected = TRUE;
+  }
+
+  Data32 = 0;
+  HoldData32 = 0;
+  switch ( pConfig->GppLinkConfig ) {
+  case GPP_CFGMODE_X4000:
+    portCfg = &pConfig->PORTCONFIG[0].PortCfg;
+    if ( portCfg->PortDetected == FALSE ) {
+      Data32 |= 0x0f0f;
+      HoldData32 |= 0x1000;
+    }
+    break;
+  case GPP_CFGMODE_X2200:
+    portCfg = &pConfig->PORTCONFIG[0].PortCfg;
+    if ( portCfg->PortDetected == FALSE ) {
+      Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303;
+      HoldData32 |= 0x1000;
+    }
+    portCfg = &pConfig->PORTCONFIG[1].PortCfg;
+    if ( portCfg->PortDetected == FALSE ) {
+      Data32 |= ( cimGppLaneReversal )? 0x0303:0x0c0c;
+      HoldData32 |= 0x2000;
+    }
+    break;
+  case GPP_CFGMODE_X2110:
+    portCfg = &pConfig->PORTCONFIG[0].PortCfg;
+    if ( portCfg->PortDetected == FALSE ) {
+      Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303;
+      HoldData32 |= 0x1000;
+    }
+    portCfg = &pConfig->PORTCONFIG[1].PortCfg;
+    if ( portCfg->PortDetected == FALSE ) {
+      Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404;
+      HoldData32 |= 0x2000;
+    }
+    portCfg = &pConfig->PORTCONFIG[2].PortCfg;
+    if ( portCfg->PortDetected == FALSE ) {
+      Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808;
+      HoldData32 |= 0x4000;
+    }
+    break;
+  case GPP_CFGMODE_X1111:
+    portCfg = &pConfig->PORTCONFIG[0].PortCfg;
+    if ( portCfg->PortDetected == FALSE ) {
+      Data32 |= ( cimGppLaneReversal )? 0x0808:0x0101;
+      HoldData32 |= 0x1000;
+    }
+    portCfg = &pConfig->PORTCONFIG[1].PortCfg;
+    if ( portCfg->PortDetected == FALSE ) {
+      Data32 |= ( cimGppLaneReversal )? 0x0404:0x0202;
+      HoldData32 |= 0x2000;
+    }
+    portCfg = &pConfig->PORTCONFIG[2].PortCfg;
+    if ( portCfg->PortDetected == FALSE ) {
+      Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404;
+      HoldData32 |= 0x4000;
+    }
+    portCfg = &pConfig->PORTCONFIG[3].PortCfg;
+    if ( portCfg->PortDetected == FALSE ) {
+      Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808;
+      HoldData32 |= 0x8000;
+    }
+    break;
+  default:
+    break;
+  }
+
+  // RPR 5.11 Power Saving With GPP Disable
+  // ABCFG 0xC0[8] = 0x0
+  // ABCFG 0xC0[15:12] = 0xF
+  // Enable "Power Saving Feature for A-Link Express Lanes"
+  // Enable "Power Saving Feature for GPP Lanes"
+  // ABCFG 0x90[19] = 1
+  // ABCFG 0x90[6] = 1
+  // RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF
+  // ABCFG 0xC0[7:4] = 0x0
+  if ( cimAlinkPhyPllPowerDown && cimGppPhyPllPowerDown ) {
+    abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
+    writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), (( abValue | HoldData32 ) & (~ BIT8 )));
+    rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));
+    rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19));
+    rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, ((Data32 & 0x0F) == 0x0F) ? Data32 | 0x0CFF0000 : Data32);
+    rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));
+  }
+}
+
+
+/**
+ * sbGppAerInitialization - Initializing AER
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+sbGppAerInitialization (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8    PortId;
+  UINT32   ValueDd;
+
+  if (pConfig->PcieAER) {
+    // GPP strap configuration
+    rwAlink (SB_ABCFG_REG310 | (UINT32) (ABCFG << 29), ~(BIT7 + BIT4), BIT28 + BIT27 + BIT26 + BIT1);
+    rwAlink (SB_ABCFG_REG314 | (UINT32) (ABCFG << 29), ~(UINT32) (0xfff << 15), 0);
+
+    for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) {
+      ReadPCI (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x00), AccWidthUint32, &ValueDd);
+      if (ValueDd != 0xffffffff) {
+        rwAlink ((SB_RCINDXP_REG6A | (UINT32) (RCINDXP << 29) | (PortId << 24)), ~BIT1, 0);
+        rwAlink ((SB_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (PortId << 24)), 0xFFFFE000, 0);
+      }
+    }
+
+    rwAlink (SB_RCINDXC_REG10, ~(BIT18 + BIT21 + BIT22), 0);
+
+    // AB strap configuration
+    rwAlink (SB_ABCFG_REGF0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT15 + BIT14);
+    rwAlink (SB_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT3);
+
+    // Enable GPP function0 error reporting
+    rwAlink (SB_ABCFG_REG310 | (UINT32) (ABCFG << 29), ~BIT7, BIT7);
+    rwAlink (SB_RCINDXC_REGC0, ~BIT9, BIT9);
+  } else {
+    //OBS220313: Hard System Hang running MeatGrinder Test on multiple blocks
+    //RPR 5.13 GPP Error Reporting Configuration
+    rwAlink (SB_ABCFG_REGF0 | (UINT32) (ABCFG << 29), ~(BIT1), 0);
+    //rwAlink (SB_ABCFG_REG310 | (UINT32) (ABCFG << 29), ~BIT7, 0);
+    //rwAlink (SB_RCINDXC_REGC0, ~BIT8, 0);
+  }
+  //RPR 5.13 GPP Error Reporting Configuration
+  rwAlink (SB_ABCFG_REGB8 | (UINT32) (ABCFG << 29), ~(BIT8 + BIT24 + BIT25 + BIT26 + BIT28), BIT8 + BIT24 + BIT26 + BIT28);
+}
+
+/**
+ * sbGppRasInitialization - Initializing RAS
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+sbGppRasInitialization (
+  IN     AMDSBCFG*   pConfig
+  )
+{
+  if (pConfig->PcieRAS) {
+    rwAlink (SB_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT0);
+  }
+}
+
+
+//
+//-----------------------------------------------------------------------------------
+// Early Hudson-2 GPP initialization sequence:
+//
+// 1) Set port enable bit fields by current GPP link configuration mode
+// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
+// 3) Loop polling for the link status of all ports
+// 4) Misc operations after link training:
+//      - (optional) Detect GFX device
+//      - Hide empty GPP configuration spaces (Disable empty GPP ports)
+//      - (optional) Power down unused GPP ports
+//      - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0])
+// 5) GPP init completed
+//
+//
+// *) Gen2 vs Gen1
+//                                   Gen2 mode     Gen1 mode
+//  ---------------------------------------------------------------
+//    STRAP_PHY_PLL_CLKF[6:0]          7'h32         7'h19
+//    STRAP_BIF_GEN2_EN                  1             0
+//
+//    PCIE_PHY_PLL clock locks @       5GHz
+//
+//
+
+/**
+ * GPP early programming and link training. On exit all populated EPs should be fully operational.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbPcieGppEarlyInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32           reg32Value;
+  UINT8            cimNbSbGen2;
+  UINT8            cimGppMemWrImprove;
+  UINT8            cimGppLaneReversal;
+  UINT8            cimAlinkPhyPllPowerDown;
+  UINT32           abValue;
+
+  cimNbSbGen2 = pConfig->NbSbGen2;
+  cimGppMemWrImprove = pConfig->GppMemWrImprove;
+  cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal;
+  cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown;
+#if  SB_CIMx_PARAMETER == 0
+  cimNbSbGen2 = cimNbSbGen2Default;
+  cimGppMemWrImprove = cimGppMemWrImproveDefault;
+  cimGppLaneReversal = cimGppLaneReversalDefault;
+  cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault;
+#endif
+
+  outPort80 (0x90);
+  //
+  // Configure NB-SB link PCIE PHY PLL power down for L1
+  //
+  if ( cimAlinkPhyPllPowerDown == TRUE ) {
+    // Set PCIE_P_CNTL in Alink PCIEIND space
+    writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40);
+    abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));
+    abValue |= BIT12 + BIT3 + BIT0;
+    abValue &= ~(BIT9 + BIT4);
+    writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);
+    rwAlink (SB_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~(BIT8), (BIT8));
+    rwAlink (SB_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~(BIT3), (BIT3));
+  }
+
+  // AXINDC_Reg 0xA4[18] = 0x1
+  writeAlink (SB_AX_INDXP_REG38 | (UINT32) (AXINDP << 29), 0xA4);
+  abValue = readAlink (SB_AX_DATAP_REG3C | (UINT32) (AXINDP << 29));
+  abValue |= BIT18;
+  writeAlink (SB_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), abValue);
+
+
+  //
+  // Set ABCFG 0x031C[0] = 1 to enable lane reversal
+  //
+  reg32Value = readAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29));
+  if ( cimGppLaneReversal ) {
+    writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | BIT0);
+  } else {
+    writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | 0x00);
+  }
+  //
+  // Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function
+  //
+  reg32Value = readAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29));
+  writeAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), reg32Value | BIT20);
+
+
+  //
+  // Initialize and configure GPP
+  //
+  if (pConfig->GppFunctionEnable) {
+    sbGppTogglePcieReset (pConfig);
+
+    // PreInit - Enable GPP link training
+    PreInitGppLink (pConfig);
+
+    //
+    // GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1
+    // GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4
+    //
+    if ( cimGppMemWrImprove == TRUE ) {
+      rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~BIT26, (BIT26));
+      rwAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12));
+    }
+
+    if (CheckGppLinkStatus (pConfig) && !pConfig->S3Resume) {
+      // Toggle GPP reset (Note this affects all Hudson-2 GPP ports)
+      sbGppTogglePcieReset (pConfig);
+    }
+
+    // Misc operations after link training
+    AfterGppLinkInit (pConfig);
+
+
+    sbGppAerInitialization (pConfig);
+    sbGppRasInitialization (pConfig);
+  }
+  sbGppDynamicPowerSaving (pConfig);
+  outPort80 (0x9F);
+}
+
diff --git a/src/vendorcode/amd/cimx/sb900/GppHp.c b/src/vendorcode/amd/cimx/sb900/GppHp.c
new file mode 100755
index 0000000..4975b8a
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/GppHp.c
@@ -0,0 +1,165 @@
+/**
+ * @file
+ *
+ * Config Southbridge GPP controller
+ *
+ * Init GPP features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+****************************************************************************
+*/
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+//
+// Declaration of external functions
+//
+VOID  sbGppDynamicPowerSaving (IN AMDSBCFG* pConfig );
+VOID  sbGppForceGen1 (IN AMDSBCFG* pConfig, IN CONST UINT8 ActivePorts);
+VOID  sbGppForceGen2 (IN AMDSBCFG* pConfig, IN CONST UINT8 ActivePorts);
+UINT8 GppPortPollingLtssm (IN AMDSBCFG* pConfig, IN UINT8 ActivePorts, IN BOOLEAN IsGen2);
+
+
+/**
+ * GPP hot plug handler
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ * @param[in] HpPort    The hot plug port number.
+ *
+ */
+VOID
+sbGppHotPlugSmiProcess (
+  IN       AMDSBCFG*     pConfig,
+  IN       UINT32        HpPort
+  )
+{
+  UINT8         FailedPort;
+
+  // First restore GPP pads if needed
+  if (pConfig->GppDynamicPowerSaving && pConfig->AlinkPhyPllPowerDown && pConfig->GppPhyPllPowerDown) {
+    rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), 0);
+    rwAlink (RC_INDXC_REG65, ~(UINT32) (0x101 << HpPort), 0);
+    SbStall (1000);
+  }
+
+  FailedPort = (UINT8) (1 << HpPort);
+  if (pConfig->GppGen2 && pConfig->GppGen2Strap) {
+    if (GppPortPollingLtssm (pConfig, FailedPort, TRUE)) {
+      sbGppForceGen1 (pConfig, FailedPort);
+      FailedPort = GppPortPollingLtssm (pConfig, FailedPort, FALSE);
+    }
+  } else {
+    sbGppForceGen1 (pConfig, FailedPort);
+    FailedPort = GppPortPollingLtssm (pConfig, FailedPort, FALSE);
+  }
+}
+
+
+/**
+ * GPP hot-unplug handler
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ * @param[in] HpPort    The hot plug port number.
+ *
+ */
+VOID
+sbGppHotUnplugSmiProcess (
+  IN       AMDSBCFG*     pConfig,
+  IN       UINT32        HpPort
+  )
+{
+  pConfig->PORTCONFIG[HpPort].PortCfg.PortDetected = FALSE;
+
+  if (pConfig->GppGen2 && pConfig->GppGen2Strap) {
+    sbGppForceGen2 (pConfig, (UINT8) (1 << HpPort));
+  }
+
+  // 5.19.1 GPP Power Saving with Hot Unplug
+  if (pConfig->GppDynamicPowerSaving && pConfig->AlinkPhyPllPowerDown && pConfig->GppPhyPllPowerDown) {
+    rwAlink (SB_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), BIT17);
+    rwAlink (SB_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT8), BIT8);
+    rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), (1 << (12 + HpPort)));
+    rwAlink (SB_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), 0);
+
+    // Finally re-configure GPP pads if needed
+    sbGppDynamicPowerSaving (pConfig);
+  }
+}
+
+
+/**
+ * SMI handler for GPP hot-plug
+ *
+ *
+ * @param[in] pConfig     Southbridge configuration structure pointer.
+ * @param[in] IsPlugged   Is a card currently plugged in the GPP port?
+ *
+ */
+VOID
+sbGppHotplugSmiCallback (
+  IN       AMDSBCFG* pConfig,
+  IN       BOOLEAN   IsPlugged
+  )
+{
+  UINT32           portNum;
+  UINT32           HpPort;
+
+  if (!pConfig->GppFunctionEnable) {
+    return;
+  }
+
+  HpPort = 0xff;
+  for (portNum = 0; portNum < MAX_GPP_PORTS; portNum++) {
+    if (pConfig->PORTCONFIG[portNum].PortCfg.PortHotPlug == TRUE) {
+      HpPort = portNum;
+      break;
+    }
+  }
+  if (HpPort == 0xff) {
+    return;
+  }
+
+  if (IsPlugged) {
+    outPort80 (0x9C);
+    sbGppHotPlugSmiProcess (pConfig, HpPort);
+  } else {
+    outPort80 (0x9D);
+    sbGppHotUnplugSmiProcess (pConfig, HpPort);
+  }
+}
+
diff --git a/src/vendorcode/amd/cimx/sb900/Hudson-2.h b/src/vendorcode/amd/cimx/sb900/Hudson-2.h
new file mode 100755
index 0000000..ca65bbc
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Hudson-2.h
@@ -0,0 +1,2068 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#pragma pack (push, 1)
+
+#define CIMX_SB_REVISION       "1.0.0.2"
+#define CIMX_SB_ID             "HDN2A13"
+#define SBCIMx_Version         0x1002
+
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page SB_POWERON_INIT_Page SB_POWERON_INIT
+ *  @section SB_POWERON_INIT Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection SB_POWERON_INIT_CallIn Call Prototype
+ *  @par
+ *     sbPowerOnInit ((AMDSBCFG*) pConfig) (Followed PH Interface)
+ *  @subsection SB_BEFORE_PCI_INIT_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SB_POWERON_INIT   --> 0x00010001 </TD></TR>
+ *  </TABLE>
+ *  @subsection SB_POWERON_INIT_CallOut Prepare for Callout
+ *  @par
+ *     Not Applicable (Not necessary for the current implementation)
+ *  @subsection SB_POWERON_INIT_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::BiosSize </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::LegacyFree </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::EcKbd </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::WatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::GecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::CpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define SB_POWERON_INIT             0x00010001
+#define OUTDEBUG_PORT               0x00010002
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page SB_BEFORE_PCI_INIT_Page SB_BEFORE_PCI_INIT
+ *  @section SB_BEFORE_PCI_INIT Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection SB_BEFORE_PCI_INIT_CallIn Call Prototype
+ *  @par
+ *     sbBeforePciInit ((AMDSBCFG*)pConfig) (Followed PH Interface)
+ *  @subsection SB_BEFORE_PCI_INIT_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_INIT  --> 0x00010010 </TD></TR>
+ *  </TABLE>
+ *  @subsection SB_BEFORE_PCI_INIT_CallOut Prepare for Callout
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR>
+ *  </TABLE>
+ *  @subsection SB_BEFORE_PCI_INIT_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define SB_BEFORE_PCI_INIT          0x00010010
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page SB_AFTER_PCI_INIT_Page SB_AFTER_PCI_INIT
+ *  @section SB_AFTER_PCI_INIT Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection SB_AFTER_PCI_INIT_CallIn Call Prototype
+ *  @par
+ *     sbAfterPciInit ((AMDSBCFG*)pConfig)     (Followed PH Interface)
+ *  @subsection SB_AFTER_PCI_INIT_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SB_AFTER_PCI_INIT --> 0x00010020 </TD></TR>
+ *  </TABLE>
+ *  @subsection SB_AFTER_PCI_INIT_CallOut Prepare for Callout
+ *  @par
+ *    Not Applicable (Not necessary for the current implementation)
+ *  @subsection SB_AFTER_PCI_INIT_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define SB_AFTER_PCI_INIT           0x00010020
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page SB_MID_POST_INIT_Page SB_MID_POST_INIT
+ *  @section SB_MID_POST_INIT Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection SB_MID_POST_INIT_CallIn Call Prototype
+ *  @par
+ *     sbMidPostInit ((AMDSBCFG*)pConfig)     (Followed PH Interface)
+ *  @subsection SB_MID_POST_INIT_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SB_MID_POST_INIT  --> 0x00010021 </TD></TR>
+ *  </TABLE>
+ *  @subsection SB_MID_POST_INIT_CallOut Prepare for Callout
+ *  @par
+ *    Not Applicable (Not necessary for the current implementation)
+ *  @subsection SB_MID_POST_INIT_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define SB_MID_POST_INIT           0x00010021
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page SB_LATE_POST_INIT_Page SB_LATE_POST_INIT
+ *  @section SB_LATE_POST_INIT Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection SB_LATE_POST_INIT_CallIn Call Prototype
+ *  @par
+ *     sbLatePost ((AMDSBCFG*)pConfig)     (Followed PH Interface)
+ *  @subsection SB_LATE_POST_INIT_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SB_LATE_POST_INIT  --> 0x00010030 </TD></TR>
+ *  </TABLE>
+ *  @subsection SB_LATE_POST_INIT_CallOut Prepare for Callout
+ *  @par
+ *    Not Applicable (Not necessary for the current implementation)
+ *  @subsection SB_LATE_POST_INIT_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define SB_LATE_POST_INIT           0x00010030
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page SB_BEFORE_PCI_RESTORE_INIT_Page SB_BEFORE_PCI_RESTORE_INIT
+ *  @section SB_BEFORE_PCI_RESTORE_INIT Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection SB_BEFORE_PCI_RESTORE_INIT_CallIn Call Prototype
+ *  @par
+ *     sbBeforePciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface)
+ *  @subsection SB_BEFORE_PCI_RESTORE_INIT_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_RESTORE_INIT  --> 0x00010040 </TD></TR>
+ *  </TABLE>
+ *  @subsection SB_BEFORE_PCI_RESTORE_INIT_CallOut Prepare for Callout
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR>
+ *  </TABLE>
+ *  @subsection SB_BEFORE_PCI_RESTORE_INIT_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define SB_BEFORE_PCI_RESTORE_INIT  0x00010040
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page SB_AFTER_PCI_RESTORE_INIT_Page SB_AFTER_PCI_RESTORE_INIT
+ *  @section SB_AFTER_PCI_RESTORE_INIT Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection SB_AFTER_PCI_RESTORE_INIT_CallIn Call Prototype
+ *  @par
+ *     sbAfterPciRestoreInit ((AMDSBCFG*)pConfig)     (Followed PH Interface)
+ *  @subsection SB_AFTER_PCI_RESTORE_INIT_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SB_AFTER_PCI_RESTORE_INIT  --> 0x00010050 </TD></TR>
+ *  </TABLE>
+ *  @subsection SB_AFTER_PCI_RESTORE_INIT_CallOut Prepare for Callout
+ *  @par
+ *    Not Applicable (Not necessary for the current implementation)
+ *  @subsection SB_AFTER_PCI_RESTORE_INIT_Config Prepare for Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define SB_AFTER_PCI_RESTORE_INIT   0x00010050
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page SB_SMM_SERVICE_Page SB_SMM_SERVICE
+ *  @section SB_SMM_SERVICE Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection SB_SMM_SERVICE_CallIn Call Prototype
+ *  @par
+ *     sbSmmService ((AMDSBCFG*)pConfig)     (Followed PH Interface)
+ *  @subsection SB_SMM_SERVICE_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SB_SMM_SERVICE  --> 0x00010060 </TD></TR>
+ *  </TABLE>
+ *  @subsection SB_SMM_SERVICE_CallOut Prepare for Callout
+ *  @par
+ *    Not Applicable (Not necessary for the current implementation)
+ *  @subsection SB_SMM_SERVICE_Config Prepare for Configuration Data.
+ *  @par
+ *     Not necessary on current implementation
+ *
+ */
+#define SB_SMM_SERVICE              0x00010060
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page SB_SMM_ACPION_Page SB_SMM_ACPION
+ *  @section SB_SMM_ACPION Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection SB_SMM_ACPION_CallIn Call Prototype
+ *  @par
+ *     sbSmmAcpiOn ((AMDSBCFG*)pConfig)     (Followed PH Interface)
+ *  @subsection SB_SMM_ACPION_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> SB_SMM_ACPION  --> 0x00010061 </TD></TR>
+ *  </TABLE>
+ *  @subsection SB_SMM_ACPION_CallOut Prepare for Callout
+ *  @par
+ *    Not Applicable (Not necessary for the current implementation)
+ *  @subsection SB_SMM_ACPION_Config Prepare for Configuration Data.
+ *  @par
+ *     Not necessary on current implementation
+ *
+ */
+#define SB_SMM_ACPION               0x00010061
+
+#define SB_EC_FANCONTROL            0x00010070
+
+#ifndef OEM_CALLBACK_BASE
+  #define OEM_CALLBACK_BASE         0x00010100
+#endif
+
+//0x00 - 0x0F callback functions are reserved for bootblock
+#define SATA_PHY_PROGRAMMING        OEM_CALLBACK_BASE + 0x10
+#define PULL_UP_PULL_DOWN_SETTINGS  OEM_CALLBACK_BASE + 0x20
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
+ *  @section CB_SBGPP_RESET_ASSERT Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT  --> 0x00010130 </TD></TR>
+ *  </TABLE>
+ *  @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data.
+ *  @par
+ *     Not necessary on current implementation
+ *
+ */
+#define CB_SBGPP_RESET_ASSERT       OEM_CALLBACK_BASE + 0x30
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
+ *  @section CB_SBGPP_RESET_DEASSERT  Interface Call
+ *  Initialize structure referenced by AMDSBCFG to default recommended value.
+ *  @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT   --> 0x00010131 </TD></TR>
+ *  </TABLE>
+ *  @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data.
+ *  @par
+ *     Not necessary on current implementation
+ *
+ */
+#define CB_SBGPP_RESET_DEASSERT     OEM_CALLBACK_BASE + 0x31
+
+#define CFG_ADDR_PORT               0xCF8
+#define CFG_DATA_PORT               0xCFC
+
+#define ALINK_ACCESS_INDEX          0x0CD8
+#define ALINK_ACCESS_DATA           ALINK_ACCESS_INDEX + 4
+
+/*------------------------------------------------------------------
+; I/O Base Address - Should be set by host BIOS
+;------------------------------------------------------------------ */
+#define DELAY_PORT                  0x0E0
+
+/*------------------------------------------------------------------
+; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
+;------------------------------------------------------------------ */
+// ASIC VendorID and DeviceIDs
+#define AMD_SB_VID                  0x1022
+#define SB_DEVICE_ID                0x780B
+#define SB_SATA_VID                 AMD_SB_VID      // Dev 17 Func 0
+#define SB_SATA_DID                 0x7800
+#define SB_SATA_AHCI_DID            0x7801
+#define SB_SATA_RAID_DID            0x7802
+#define SB_SATA_RAID5_DID           0x7803
+#define SB_SATA_AMDAHCI_DID         0x7804
+#define SB_USB_OHCI_VID             AMD_SB_VID      // Dev 18 Func 0, Dev 19 Func 0
+#define SB_USB_OHCI_DID             0x7807
+#define SB_USB_EHCI_VID             AMD_SB_VID      // Dev 18 Func 2, Dev 19 Func 2
+#define SB_USB_EHCI_DID             0x7808
+#define SB_USB_XHCI_VID             AMD_SB_VID      // Dev 10 Func 0, Dev 10 Func 1
+#define SB_USB_XHCI_DID             0x7812
+#define SB_SMBUS_VID                AMD_SB_VID      // Dev 20 Func 0
+#define SB_SMBUS_DID                0x780B
+#define SB_IDE_VID                  AMD_SB_VID      // Dev 20 Func 1
+#define SB_IDE_DID                  0x780C
+#define SB_AZALIA_VID               AMD_SB_VID      // Dev 20 Func 2
+#define SB_AZALIA_DID               0x780D
+#define SB_LPC_VID                  AMD_SB_VID      // Dev 20 Func 3
+#define SB_LPC_DID                  0x780E
+#define SB_PCIB_VID                 AMD_SB_VID      // Dev 20 Func 4
+#define SB_PCIB_DID                 0x780F
+#define SB_USB_OHCIF_VID            AMD_SB_VID      // dev 20 Func 5
+#define SB_USB_OHCIF_DID            0x7809
+#define SB_NIC_VID                  0x14E4          // Dev 20 Func 6
+#define SB_NIC_DID                  0x1699
+#define SB_SD_VID                   AMD_SB_VID      // Dev 20 Func 7
+#define SB_SD_DID                   0x7806
+
+//FCH Variant
+#define FCH_Variant_EFUSE_LOCATION     0x1E    // EFUSE bit 240-247
+
+#define FCH_M2                            0x01
+#define FCH_M3                            0x03
+#define FCH_M3T                           0x07
+#define FCH_D2                            0x0F
+#define FCH_D3                            0x1F
+#define FCH_D4                            0x3F
+
+//Misc
+#define AMD_SB_A11                        0x11
+#define AMD_SB_A12                        0x12
+#define AMD_SB_A13                        0x13
+#define ACPI_SMI_CMD_PORT                 0xB0
+#define ACPI_SMI_DATA_PORT                0xB1
+#define R_SB_ACPI_PM1_STATUS              0x00
+#define R_SB_ACPI_PM1_ENABLE              0x02
+#define R_SB_ACPI_PM_CONTROL              0x04
+#define R_SB_ACPI_EVENT_STATUS            0x20
+#define R_SB_ACPI_EVENT_ENABLE            0x24
+#define R_SB_PM_ACPI_PMA_CNT_BLK_LO       0x2C
+
+//#define SATA_BUS_DEV_FUN_FPGA            0x228
+#define SATA_BUS_DEV_FUN            ((0x11 << 3) + 0)
+#define SB_SATA1_BUS        0
+#define SB_SATA1_DEV        17
+#define SB_SATA1_FUNC       0
+
+#define FC_BUS_DEV_FUN              ((0x11 << 3) + 1)
+#define SB_XHCI_BUS        0
+#define SB_XHCI_DEV        16
+#define SB_XHCI_FUNC       0
+#define USB_XHCI_BUS_DEV_FUN        ((SB_XHCI_DEV << 3) + SB_XHCI_FUNC)
+#define SB_XHCI1_BUS        0
+#define SB_XHCI1_DEV        16
+#define SB_XHCI1_FUNC       1
+#define USB_XHCI1_BUS_DEV_FUN       ((SB_XHCI1_DEV << 3) + SB_XHCI1_FUNC)
+#define USB1_OHCI_BUS_DEV_FUN       ((0x12 << 3) + 0)    // PORT 0-4
+#define SB_OHCI1_BUS        0
+#define SB_OHCI1_DEV        18
+#define SB_OHCI1_FUNC       0
+#define USB2_OHCI_BUS_DEV_FUN       ((0x13 << 3) + 0)    // PORT 5-9
+#define SB_OHCI2_BUS        0
+#define SB_OHCI2_DEV        19
+#define SB_OHCI2_FUNC       0
+#define USB3_OHCI_BUS_DEV_FUN       ((0x16 << 3) + 0)    // PORT 10-13
+#define SB_OHCI3_BUS        0
+#define SB_OHCI3_DEV        22
+#define SB_OHCI3_FUNC       0
+#define USB1_EHCI_BUS_DEV_FUN       ((0x12 << 3) + 2)    // PORT 0-4
+#define SB_EHCI1_BUS        0
+#define SB_EHCI1_DEV        18
+#define SB_EHCI1_FUNC       2
+#define USB2_EHCI_BUS_DEV_FUN       ((0x13 << 3) + 2)    // PORT 5-9
+#define SB_EHCI2_BUS        0
+#define SB_EHCI2_DEV        19
+#define SB_EHCI2_FUNC       2
+#define USB3_EHCI_BUS_DEV_FUN       ((0x16 << 3) + 2)  // PORT 10-13
+#define SB_EHCI3_BUS        0
+#define SB_EHCI3_DEV        22
+#define SB_EHCI3_FUNC       2
+#define SMBUS_BUS_DEV_FUN           ((0x14 << 3) + 0)
+#define SB_ISA_BUS          0
+#define SB_ISA_DEV          20
+#define SB_ISA_FUNC         0
+#define IDE_BUS_DEV_FUN             ((0x14 << 3) + 1)
+#define SB_IDE_BUS          0
+#define SB_IDE_DEV          20
+#define SB_IDE_FUNC         1
+#define AZALIA_BUS_DEV_FUN          ((0x14 << 3) + 2)
+#define SB_AZALIA_BUS       0
+#define SB_AZALIA_DEV       20
+#define SB_AZALIA_FUNC      2
+#define LPC_BUS_DEV_FUN             ((0x14 << 3) + 3)
+#define SB_LPC_BUS          0
+#define SB_LPC_DEV          20
+#define SB_LPC_FUNC         3
+#define PCIB_BUS_DEV_FUN            ((0x14 << 3) + 4)    // P2P in SB700
+#define SB_PCI_BUS          0
+#define SB_PCI_DEV          20
+#define SB_PCI_FUNC         4
+#define USB4_OHCI_BUS_DEV_FUN       ((0x14 << 3) + 5)    // PORT FL0 - FL1
+#define SB_OHCI4_BUS        0
+#define SB_OHCI4_DEV        20
+#define SB_OHCI4_FUNC       5
+//Gigabyte Ethernet Controller
+#define GEC_BUS_DEV_FUN             ((0x14 << 3) + 6)
+#define SB_GBEC_BUS         0
+#define SB_GBEC_DEV         20
+#define SB_GBEC_FUNC        6
+
+#define SD_BUS_DEV_FUN            ((0x14 << 3) + 7)    // SD in SB900
+#define SD_PCI_BUS          0
+#define SD_PCI_DEV          20
+#define SD_PCI_FUNC         7
+#define SD_PCI_REG00        0x00
+#define SD_PCI_REG2C        0x2C
+#define SD_PCI_REGA4        0xA4
+#define SD_PCI_REGB0        0xB0
+
+
+#define SB_GPP_BUS          0
+#define SB_GPP_DEV          21
+#define SB_GPP_FUNC         0
+#define GPP0_BUS_DEV_FUN            ((0x15 << 3) + 0)    // GPP P2P bridge PORT0
+#define GPP1_BUS_DEV_FUN            ((0x15 << 3) + 1)    // GPP P2P bridge PORT1
+#define GPP2_BUS_DEV_FUN            ((0x15 << 3) + 2)    // GPP P2P bridge PORT2
+#define GPP3_BUS_DEV_FUN            ((0x15 << 3) + 3)    // GPP P2P bridge PORT3
+
+#define ACPI_MMIO_BASE  0xFED80000
+#define SB_CFG_BASE     0x000   // DWORD
+#define GPIO_BASE       0x100   // BYTE
+#define SMI_BASE        0x200   // DWORD
+#define PMIO_BASE       0x300   // DWORD
+#define PMIO2_BASE      0x400   // BYTE
+#define BIOS_RAM_BASE   0x500   // BYTE
+#define CMOS_RAM_BASE   0x600   // BYTE
+#define CMOS_BASE       0x700   // BYTE
+#define ASF_BASE        0x900   // DWORD
+#define SMBUS_BASE      0xA00   // DWORD
+#define WATCHDOG_BASE   0xB00   // ??
+#define HPET_BASE       0xC00   // DWORD
+#define IOMUX_BASE      0xD00   // BYTE
+#define MISC_BASE       0xE00
+#define SERIAL_DEBUG_BASE  0x1000
+#define GFX_DAC_BASE       0x1400
+#define CEC_BASE           0x1800
+#define XHCI_BASE          0x1C00
+
+
+// RegSpace field (AB_INDEX[31:29]
+#define AXINDC         0               // AXINDC
+#define AXINDP         2               // AXINDP
+#define ABCFG          6               // ABCFG
+#define AXCFG          4               // AXCFG
+#define RCINDXC        1               // PCIEIND
+#define RCINDXP        3               // PCIEIND_P
+
+#define SBTEMP_BUS       8
+#define GPP_DEV_NUM    21              //?? Code style different
+#define MAX_GPP_PORTS  4
+#ifndef TRUE
+  #define TRUE         1
+#endif
+#ifndef FALSE
+  #define FALSE        0
+#endif
+//
+// ABCFG Registers
+//
+#define PCIE_FORCE_GEN1_EFUSE_LOCATION     0x14    // EFUSE bit 160
+
+#define SB_ABCFG_REG00     0x00  // VENDOR ID
+#define SB_ABCFG_REG08     0x08  // REVISION ID
+#define SB_ABCFG_REG40     0x40  // BL_EVENTCNT0LO
+#define SB_ABCFG_REG44     0x44  // BL_EVENTCNT1LO
+#define SB_ABCFG_REG48     0x48  // BL_EVENTCNTSEL
+#define SB_ABCFG_REG4A     0x4A  // BL_EVENTCNT0HI
+#define SB_ABCFG_REG4B     0x4B  // BL_EVENTCNT1HI
+#define SB_ABCFG_REG4C     0x4C  // BL_EVENTCNTCTL
+#define SB_ABCFG_REG50     0x50  // MISCCTL_50
+#define SB_ABCFG_REG54     0x54  // MISCCTL_54
+#define SB_ABCFG_REG58     0x58  // BL RAB CONTROL
+
+#define SB_ABCFG_REG60     0x60  // LINKWIDTH_CTL
+#define SB_ABCFG_REG64     0x64  // LINKWIDTH_UP_INTERVAL
+#define SB_ABCFG_REG68     0x68  // LINKWIDTH_DN_INVERVAL
+#define SB_ABCFG_REG6C     0x6C  // LINKWIDTH_UPSTREAM_DWORDS
+#define SB_ABCFG_REG70     0x70  // LINKWIDTH_DOWNSTREAM_DWORDS
+#define SB_ABCFG_REG74     0x74  // LINKWIDTH_THRESHOLD_INCREASE
+#define SB_ABCFG_REG78     0x78  // LINKWIDTH_THRESHOLD_DECREASE
+
+#define SB_ABCFG_REG80     0x80  // BL DMA PREFETCH CONTROL
+#define SB_ABCFG_REG88     0x88  //
+#define SB_ABCFG_REG8C     0x8C  //
+#define SB_ABCFG_REG90     0x90  // BIF CONTROL 0
+#define SB_ABCFG_REG94     0x94  // MSI CONTROL
+#define SB_ABCFG_REG98     0x98  // BIF CONTROL 1
+#define SB_ABCFG_REG9C     0x9C  // MISCCTL_9C
+#define SB_ABCFG_REGA0     0xA0  // BIF PHY CONTROL ENABLE
+#define SB_ABCFG_REGA4     0xA4  // BIF PHY CONTROL A4
+#define SB_ABCFG_REGA8     0xA8  // BIF PHY CONTROL A8
+#define SB_ABCFG_REGB0     0xB0  // HYPERFLASH-PCIE PORT MAPPING
+#define SB_ABCFG_REGB4     0xB4  //
+#define SB_ABCFG_REGB8     0xB8  //
+#define SB_ABCFG_REGC0     0xC0  // PCIE_GPP_ENABLE
+#define SB_ABCFG_REGC4     0xC4  // PCIE_P2P_INT_MAP
+#define SB_ABCFG_REGD0     0xD0  // MCTP_VDM_TX_FIFO_DATA
+#define SB_ABCFG_REGD4     0xD4  // MCTP_VMD_TX_CONTROL
+#define SB_ABCFG_REGE0     0xE0  // MCTP_VDM_RX_FIFO_DATA
+#define SB_ABCFG_REGE4     0xE4  // MCTP_VDM_RX_FIFO_STATUS
+#define SB_ABCFG_REGEC     0xEC  // MCTP_VDM_CONTROL
+#define SB_ABCFG_REGF0     0xF0  // GPP_UPSTREAM_CONTROL
+#define SB_ABCFG_REGF4     0xF4  // GPP_SYSTEM_ERROR_CONTROL
+#define SB_ABCFG_REGFC     0xFC  // SB_TRAP_CONTROL
+#define SB_ABCFG_REG100    0x100 // SB_TRAP0_ADDRL
+#define SB_ABCFG_REG104    0x104 // SB_TRAP0_ADDRH
+#define SB_ABCFG_REG108    0x108 // SB_TRAP0_CMD
+#define SB_ABCFG_REG10C    0x10C // SB_TRAP1_DATA
+#define SB_ABCFG_REG110    0x110 // SB_TRAP1_ADDRL
+#define SB_ABCFG_REG114    0x114 // SB_TRAP1_ADDRH
+#define SB_ABCFG_REG118    0x118 // SB_TRAP1_CMD
+#define SB_ABCFG_REG11C    0x11C // SB_TRAP1_DATA
+#define SB_ABCFG_REG120    0x120 // SB_TRAP2_ADDRL
+#define SB_ABCFG_REG124    0x124 // SB_TRAP2_ADDRH
+#define SB_ABCFG_REG128    0x128 // SB_TRAP2_CMD
+#define SB_ABCFG_REG12C    0x12C // SB_TRAP2_DATA
+#define SB_ABCFG_REG130    0x130 // SB_TRAP3_ADDRL
+#define SB_ABCFG_REG134    0x134 // SB_TRAP3_ADDRH
+#define SB_ABCFG_REG138    0x138 // SB_TRAP3_CMD
+#define SB_ABCFG_REG13C    0x13C // SB_TRAP3_DATA
+#define SB_ABCFG_REG300    0x300 // MCTP_VDM_RX_SMI_CONTROL
+#define SB_ABCFG_REG310    0x310 // BIF_GPP_STRAP_SYSTEM_0
+#define SB_ABCFG_REG314    0x314 // BIF_GPP_STRAP_SYSTEM_1
+#define SB_ABCFG_REG31C    0x31C // BIF_GPP_STRAP_LINK_CONTROL_0
+#define SB_ABCFG_REG320    0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A
+#define SB_ABCFG_REG324    0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B
+#define SB_ABCFG_REG328    0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C
+#define SB_ABCFG_REG32C    0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D
+#define SB_ABCFG_REG330    0x330 // BIF_GPP_STRAP_BIF_0
+#define SB_ABCFG_REG334    0x334 // BIF_GPP_STRAP_BIF_1
+#define SB_ABCFG_REG338    0x338 // BIF_GPP_STRAP_BIF_2
+#define SB_ABCFG_REG340    0x340 // BIF_GPP_STRAP_BIF_LANE_A
+#define SB_ABCFG_REG344    0x344 // BIF_GPP_STRAP_BIF_LANE_B
+#define SB_ABCFG_REG348    0x348 // BIF_GPP_STRAP_BIF_LANE_C
+#define SB_ABCFG_REG34C    0x34C // BIF_GPP_STRAP_BIF_LANE_D
+#define SB_ABCFG_REG350    0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0
+#define SB_ABCFG_REG354    0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1
+#define SB_ABCFG_REG404    0x404 // GPP0_SHADOW_COMMAND
+#define SB_ABCFG_REG418    0x418 // GPP0_SHADOW_BUS_NUMBER
+#define SB_ABCFG_REG41C    0x41C // GPP0_SHADOW_IO_LIMIT_BASE
+#define SB_ABCFG_REG420    0x420 // GPP0_SHADOW_MEM_LIMIT_BASE
+#define SB_ABCFG_REG424    0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE
+#define SB_ABCFG_REG428    0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER
+#define SB_ABCFG_REG42C    0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER
+#define SB_ABCFG_REG430    0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER
+#define SB_ABCFG_REG43C    0x43C // GPP0_SHADOW_BRIDGE_CONTROL
+#define SB_ABCFG_REG444    0x444 // GPP1_SHADOW_COMMAND
+#define SB_ABCFG_REG458    0x458 // GPP1_SHADOW_BUS_NUMBER
+#define SB_ABCFG_REG45C    0x45C // GPP1_SHADOW_IO_LIMIT_BASE
+#define SB_ABCFG_REG460    0x460 // GPP1_SHADOW_MEM_LIMIT_BASE
+#define SB_ABCFG_REG464    0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE
+#define SB_ABCFG_REG468    0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER
+#define SB_ABCFG_REG46C    0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER
+#define SB_ABCFG_REG470    0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER
+#define SB_ABCFG_REG47C    0x47C // GPP1_SHADOW_BRIDGE_CONTROL
+#define SB_ABCFG_REG484    0x484 // GPP2_SHADOW_COMMAND
+#define SB_ABCFG_REG498    0x498 // GPP2_SHADOW_BUS_NUMBER
+#define SB_ABCFG_REG49C    0x49C // GPP2_SHADOW_IO_LIMIT_BASE
+#define SB_ABCFG_REG4A0    0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE
+#define SB_ABCFG_REG4A4    0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE
+#define SB_ABCFG_REG4A8    0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER
+#define SB_ABCFG_REG4AC    0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER
+#define SB_ABCFG_REG4B0    0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER
+#define SB_ABCFG_REG4BC    0x4BC // GPP2_SHADOW_BRIDGE_CONTROL
+#define SB_ABCFG_REG4C4    0x4C4 // GPP3_SHADOW_COMMAND
+#define SB_ABCFG_REG4D8    0x4D8 // GPP3_SHADOW_BUS_NUMBER
+#define SB_ABCFG_REG4DC    0x4DC // GPP3_SHADOW_IO_LIMIT_BASE
+#define SB_ABCFG_REG4E0    0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE
+#define SB_ABCFG_REG4E4    0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE
+#define SB_ABCFG_REG4E8    0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER
+#define SB_ABCFG_REG4EC    0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER
+#define SB_ABCFG_REG4F0    0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER
+#define SB_ABCFG_REG4FC    0x4FC // GPP3_SHADOW_BRIDGE_CONTROL
+#define SB_ABCFG_REG10040  0x10040  // AL_EVENTCNT0LO
+#define SB_ABCFG_REG10044  0x10044  // AL_EVENTCNT1LO
+#define SB_ABCFG_REG10048  0x10048  // AL_EVENTCNTSEL
+#define SB_ABCFG_REG1004A  0x1004A  // AL_EVENTCNT0HI
+#define SB_ABCFG_REG1004B  0x1004B  // AL_EVENTCNT1HI
+#define SB_ABCFG_REG1004C  0x1004C  // AL_EVENTCNTCTL
+#define SB_ABCFG_REG10050  0x10050  // MISCCTL_10050
+#define SB_ABCFG_REG10054  0x10054  // AL_ARB_CTL
+#define SB_ABCFG_REG10056  0x10056  // AL_CLK_CTL
+#define SB_ABCFG_REG10058  0x10058  // AL RAB CONTROL
+#define SB_ABCFG_REG1005C  0x1005C  // AL MLT CONTROL
+#define SB_ABCFG_REG10060  0x10060  // AL DMA PREFETCH ENABLE
+#define SB_ABCFG_REG10064  0x10064  // AL DMA PREFETCH FLUSH CONTROL
+#define SB_ABCFG_REG10068  0x10068  // AL PREFETCH LIMIT
+#define SB_ABCFG_REG1006C  0x1006C  // AL DMA PREFETCH CONTROL
+#define SB_ABCFG_REG10070  0x10070  // MISCCTL_10070
+#define SB_ABCFG_REG10080  0x10080  // CLKMUXSTATUS
+#define SB_ABCFG_REG10090  0x10090  // BIF CONTROL 0
+#define SB_ABCFG_REG1009C  0x1009C  // MISCCTL_1009C
+
+//
+// RCINDX_P Registers
+//
+#define SB_RCINDXP_REG01   0x01 | RCINDXP << 29 // PCIEP_SCRATCH
+#define SB_RCINDXP_REG02   0x02 | RCINDXP << 29 //
+#define SB_RCINDXP_REG10   0x10 | RCINDXP << 29 //
+#define SB_RCINDXP_REG20   0x20 | RCINDXP << 29 // PCIE_TX_CNTL
+#define SB_RCINDXP_REG21   0x21 | RCINDXP << 29 // PCIE_TX_REQUESTER_ID
+#define SB_RCINDXP_REG50   0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS
+#define SB_RCINDXP_REG6A   0x6A | RCINDXP << 29 //
+#define SB_RCINDXP_REG70   0x70 | RCINDXP << 29 // PCIE_RX_CNTL
+#define SB_RCINDXP_REGA0   0xA0 | RCINDXP << 29 // PCIE_LC_CNTL
+#define SB_RCINDXP_REGA1   0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL
+#define SB_RCINDXP_REGA2   0xA2 | RCINDXP << 29 //
+#define SB_RCINDXP_REGA4   0xA4 | RCINDXP << 29 //
+#define SB_RCINDXP_REGA5   0xA5 | RCINDXP << 29 // PCIE_LC_STATE0
+#define SB_RCINDXP_REGC0   0xC0 | RCINDXP << 29 //
+
+//
+// RCINDX_C Registers
+//
+#define SB_RCINDXC_REG02   0x02 | RCINDXC << 29  // PCIE_HW_DEBUG
+#define SB_RCINDXC_REG10   0x10 | RCINDXC << 29  // PCIE_CNTL
+#define SB_RCINDXC_REGC0   0xC0 | RCINDXC << 29  //
+#define SB_RCINDXC_REGC1   0xC1 | RCINDXC << 29  //
+
+//
+// AXINDC Registers
+//
+#define SB_AX_INDXC_REG02  0x02 // PCIEP_HW_DEBUG
+#define SB_AX_INDXC_REG10  0x10
+#define SB_AX_INDXC_REG30  0x30
+#define SB_AX_DATAC_REG34  0x34
+#define SB_AX_INDXP_REG38  0x38
+#define SB_AX_DATAP_REG3C  0x3C
+#define SB_AX_INDXC_REG40  0x40 | AXINDC << 29
+#define SB_AX_INDXC_REGA4  0xA4 | AXINDC << 29
+
+#define SB_AX_INDXP_REG02  0x02 | AXINDP << 29
+#define SB_AX_INDXP_REGA0  0xA0 | AXINDP << 29
+#define SB_AX_INDXP_REGA4  0xA4 | AXINDP << 29
+#define SB_AX_INDXP_REGB1  0xB1 | AXINDP << 29
+
+#define SB_AX_CFG_REG68  0x68 | AXCFG << 29
+#define SB_AX_CFG_REG6A  0x6A | AXCFG << 29
+#define SB_AX_CFG_REG88  0x88 | AXCFG << 29
+
+#define SB_AB_REG04         0x04
+#define SB_AB_REG40         0x40
+
+#define RC_INDXC_REG40     0x40 | RCINDXC << 29
+#define RC_INDXC_REG65     0x65 | RCINDXC << 29
+#define RC_INDXC_REGC0     0xC0 | RCINDXC << 29
+
+//
+//  SATA Device 0x7800 (IDE)
+//              0x7801 (AHCI)
+//              0x7802 (AHCI/RAID Promise with RAID driver)
+//              0x7803 (RAID5)
+//  Device 17 (0x11) Func 0
+//
+//Sata Controller Mode
+#define NATIVE_IDE_MODE        0
+#define RAID_MODE              1
+#define AHCI_MODE              2
+#define LEGACY_IDE_MODE        3
+#define IDE_TO_AHCI_MODE       4
+#define AHCI_MODE_7804         5
+#define IDE_TO_AHCI_MODE_7804  6
+
+//Sata Port Configuration
+#define SIX_PORTS       0
+#define FOUR_PORTS      1
+
+#define SATA_EFUSE_LOCATION     0x10    // EFUSE bit 133
+#define SATA_FIS_BASE_EFUSE_LOC 0x15    // EFUSE bit 169
+#define SATA_EFUSE_BIT          0x20    //
+#define SB_SATA_REG00           0x000   // Vendor ID - R- 16 bits
+#define SB_SATA_REG02           0x002   // Device ID - RW -16 bits
+#define SB_SATA_REG04           0x004   // PCI Command - RW - 16 bits
+#define SB_SATA_REG06           0x006   // PCI Status - RW - 16 bits
+#define SB_SATA_REG08           0x008   // Revision ID/PCI Class Code - R - 32 bits - Offset: 08
+#define SB_SATA_REG0C           0x00C   // Cache Line Size - R/W - 8bits
+#define SB_SATA_REG0D           0x00D   // Latency Timer - RW - 8 bits
+#define SB_SATA_REG0E           0x00E   // Header Type - R - 8 bits
+#define SB_SATA_REG0F           0x00F   // BIST - R - 8 bits
+#define SB_SATA_REG10           0x010   // Base Address Register 0 - RW - 32 bits
+#define SB_SATA_REG14           0x014   // Base Address Register 1 - RW- 32 bits
+#define SB_SATA_REG18           0x018   // Base Address Register 2 - RW - 32 bits
+#define SB_SATA_REG1C           0x01C   // Base Address Register 3 - RW - 32 bits
+#define SB_SATA_REG20           0x020   // Base Address Register 4 - RW - 32 bits
+#define SB_SATA_REG24           0x024   // Base Address Register 5 - RW - 32 bits
+#define SB_SATA_REG2C           0x02C   // Subsystem Vendor ID - R - 16 bits
+#define SB_SATA_REG2D           0x02D   // Subsystem ID - R - 16 bits
+#define SB_SATA_REG30           0x030   // Expansion ROM Base Address - 32 bits
+#define SB_SATA_REG34           0x034   // Capabilities Pointer - R - 32 bits
+#define SB_SATA_REG3C           0x03C   // Interrupt Line - RW - 8 bits
+#define SB_SATA_REG3D           0x03D   // Interrupt Pin - R - 8 bits
+#define SB_SATA_REG3E           0x03E   // Min Grant - R - 8 bits
+#define SB_SATA_REG3F           0x03F   // Max Latency - R - 8 bits
+#define SB_SATA_REG40           0x040   // Configuration - RW - 32 bits
+#define SB_SATA_REG44           0x044   // Software Data Register - RW - 32 bits
+#define SB_SATA_REG48           0x048
+#define SB_SATA_REG4C           0x04C
+#define SB_SATA_REG50           0x050   // Message Capability - R - 16 bits
+#define SB_SATA_REG52           0x052   // Message Control - R/W - 16 bits
+#define SB_SATA_REG54           0x054   // Message Address - R/W - 32 bits
+#define SB_SATA_REG58           0x058   // Message Data - R/W - 16 bits
+#define SB_SATA_REG5C           0x05C   // RAMBIST Control Register - R/W - 8 bits
+#define SB_SATA_REG5D           0x05D   // RAMBIST Status0 Register - R - 8 bits
+#define SB_SATA_REG5E           0x05E   // RAMBIST Status1 Register - R - 8 bits
+#define SB_SATA_REG60           0x060   // Power Management Capabilities - R - 32 bits
+#define SB_SATA_REG64           0x064   // Power Management Control + Status - RW - 32 bits
+#define SB_SATA_REG68           0x068   // MSI Program - R/W - 8 bits
+#define SB_SATA_REG69           0x069   // PCI Burst Timer - R/W - 8 bits
+#define SB_SATA_REG70           0x070   // PCI Bus Master - IDE0 - RW - 32 bits
+#define SB_SATA_REG74           0x074   // PRD Table Address - IDE0 - RW - 32 bits
+#define SB_SATA_REG78           0x078   // PCI Bus Master - IDE1 - RW - 32 bits
+#define SB_SATA_REG7C           0x07C   // PRD Table Address - IDE1 - RW - 32 bits
+#define SB_SATA_REG80           0x080   // Data Transfer Mode - IDE0 - RW - 32 bits
+#define SB_SATA_REG84           0x084   // Data Transfer Mode - IDE1 - RW - 32 bits
+#define SB_SATA_REG86           0x086   // PY Global Control
+#define SB_SATA_REG87           0x087
+#define SB_SATA_REG88           0x088   // PHY Port0 Control - Port0 PY fine tune (0:23)
+#define SB_SATA_REG8A           0x08A
+#define SB_SATA_REG8C           0x08C   // PHY Port1 Control - Port0 PY fine tune (0:23)
+#define SB_SATA_REG8E           0x08E
+#define SB_SATA_REG90           0x090   // PHY Port2 Control - Port0 PY fine tune (0:23)
+#define SB_SATA_REG92           0x092
+#define SB_SATA_REG94           0x094   // PHY Port3 Control - Port0 PY fine tune (0:23)
+#define SB_SATA_REG96           0x096
+#define SB_SATA_REG98           0x098   // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define SB_SATA_REG9C           0x09C   // EEPROM Memory Data - RW - 32 bits
+#define SB_SATA_REGA0           0x0A0   //
+#define SB_SATA_REGA4           0x0A4   //
+#define SB_SATA_REGA5           0x0A5   //;
+#define SB_SATA_REGA8           0x0A8   //
+#define SB_SATA_REGAD           0x0AD   //;
+#define SB_SATA_REGB0           0x0B0   // IDE1 Task File Configuration + Status - RW - 32 bits
+#define SB_SATA_REGB5           0x0B5   //;
+#define SB_SATA_REGBD           0x0BD   //;
+#define SB_SATA_REGC0           0x0C0   // BA5 Indirect Address - RW - 32 bits
+#define SB_SATA_REGC4           0x0C4   // BA5 Indirect Access - RW - 32 bits
+
+#define SB_SATA_BAR5_REG00      0x000   // PCI Bus Master - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG04      0x004   // PRD Table Address - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG08      0x008   // PCI Bus Master - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG0C      0x00C   // PRD Table Address - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG10      0x010   // PCI Bus Master2 - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG1C      0x01C
+#define SB_SATA_BAR5_REG18      0x018   // PCI Bus Master2 - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG20      0x020   // PRD Address - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG24      0x024   // PCI Bus Master Byte Count - IDE0- RW - 32 bits
+#define SB_SATA_BAR5_REG28      0x028   // PRD Address - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG2C      0x02C   // PCI Bus Master Byte Count - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG40      0x040   // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG44      0x044   // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG48      0x048   // System Configuration Status - Command - RW - 32 bits
+#define SB_SATA_BAR5_REG4C      0x04C   // System Software Data Register - RW - 32 bits
+#define SB_SATA_BAR5_REG50      0x050   // FLAS Memory Address - Command + Status - RW - 32 bits
+#define SB_SATA_BAR5_REG54      0x054   // FLAS Memory Data - RW - 32 bits
+#define SB_SATA_BAR5_REG58      0x058   // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define SB_SATA_BAR5_REG5C      0x05C   // EEPROM Memory Data - RW - 32 bits
+#define SB_SATA_BAR5_REG60      0x060   // FIFO Port - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG68      0x068   // FIFO Pointers1- IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG6C      0x06C   // FIFO Pointers2- IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG70      0x070   // FIFO Port - IDE1- RW - 32 bits
+#define SB_SATA_BAR5_REG78      0x078   // FIFO Pointers1- IDE1- RW - 32 bits
+#define SB_SATA_BAR5_REG7C      0x07C   // FIFO Pointers2- IDE1- RW - 32 bits
+#define SB_SATA_BAR5_REG80      0x080   // IDE0 Task File Register 0- RW - 32 bits
+#define SB_SATA_BAR5_REG84      0x084   // IDE0 Task File Register 1- RW - 32 bits
+#define SB_SATA_BAR5_REG88      0x088   // IDE0 Task File Register 2- RW - 32 bits
+#define SB_SATA_BAR5_REG8C      0x08C   // IDE0 Read Data - RW - 32 bits
+#define SB_SATA_BAR5_REG90      0x090   // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REG94      0x094   // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REG9C      0x09C   // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits
+#define SB_SATA_BAR5_REGA0      0x0A0   // IDE0 Task File Configuration + Status - RW - 32 bits
+#define SB_SATA_BAR5_REGB4      0x0B4   // Data Transfer Mode -IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REGC0      0x0C0   // IDE1 Task File Register 0 - RW - 32 bits
+#define SB_SATA_BAR5_REGC4      0x0C4   // IDE1 Task File Register 1 - RW - 32 bits
+#define SB_SATA_BAR5_REGC8      0x0C8   // IDE1 Task File Register 2 - RW - 32 bits
+#define SB_SATA_BAR5_REGCC      0x0CC   //  Read/Write Data - RW - 32 bits
+#define SB_SATA_BAR5_REGD0      0x0D0   // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REGD4      0x0D4   // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REGDC      0x0DC   // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits
+#define SB_SATA_BAR5_REGE0      0x0E0   // IDE1 Task File Configuration + Status - RW - 32 bits
+#define SB_SATA_BAR5_REGF4      0x0F4   // Data Transfer Mode - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REGF8      0x0F8   // PORT Configuration
+#define SB_SATA_BAR5_REGFC      0x0FC
+#define SB_SATA_BAR5_REG100     0x0100  // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
+#define SB_SATA_BAR5_REG104     0x0104  // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
+#define SB_SATA_BAR5_REG108     0x0108  // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
+#define SB_SATA_BAR5_REG10C     0x010C  // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
+#define SB_SATA_BAR5_REG144     0x0144  // Serial ATA PY Configuration - RW - 32 bits
+#define SB_SATA_BAR5_REG148     0x0148  // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]
+#define SB_SATA_BAR5_REG14C     0x014C  // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]
+#define SB_SATA_BAR5_REG120     0x0120  //
+#define SB_SATA_BAR5_REG128     0x0128  // Port Serial ATA Status
+#define SB_SATA_BAR5_REG12C     0x012C  // Port Serial ATA Control
+#define SB_SATA_BAR5_REG130     0x0130
+#define SB_SATA_BAR5_REG1B0     0x01B0
+#define SB_SATA_BAR5_REG230     0x0230
+#define SB_SATA_BAR5_REG2B0     0x02B0
+#define SB_SATA_BAR5_REG330     0x0330
+#define SB_SATA_BAR5_REG3B0     0x03B0
+#define SB_SATA_BAR5_REG430     0x0430
+#define SB_SATA_BAR5_REG4B0     0x04B0
+//
+//  USB XHCI Device 0x7812
+//  Device 16 (0x10) Func 0/1
+//
+#define XHCI_EFUSE_LOCATION     0x18        // EFUSE bit 192, 193
+#define SB_XHCI_REG48           0x48        // Port Force Reset - RW (800)
+#define SB_XHCI_REG4C           0x4C        // MSI - RW   (800)
+//
+//  USB OHCI Device 0x7807
+//  Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0
+//  Device 20 (0x14) Func 5 (FL) 0x7809
+//
+#define SB_OHCI_REG00           0x00        // Device/Vendor ID - R (0x43971002)
+#define SB_OHCI_REG04           0x04        // Command - RW
+#define SB_OHCI_REG06           0x06        // Status - R
+#define SB_OHCI_REG08           0x08        // Revision ID/Class Code - R
+#define SB_OHCI_REG0C           0x0C        // Miscellaneous - RW
+#define SB_OHCI_REG10           0x10        // Bar_OCI - RW
+#define SB_OHCI_REG2C           0x2C        // Subsystem Vendor ID/ Subsystem ID - RW
+#define SB_OHCI_REG34           0x34        // Capability Pointer - R
+#define SB_OHCI_REG3C           0x3C        // Interrupt Line - RW
+#define SB_OHCI_REG3D           0x3D        // Interrupt Line - RW
+#define SB_OHCI_REG40           0x40        // Config Timers - RW
+#define SB_OHCI_REG42           0x42        // Port Disable Control - RW (800)
+#define SB_OHCI_REG46           0x46        // USB PHY Battery Charger - RW (800)
+#define SB_OHCI_REG48           0x48        // Port Force Reset - RW (800)
+#define SB_OHCI_REG4C           0x4C        // MSI - RW   (800)
+#define SB_OHCI_REG50           0x50        // Misc Control - RW
+#define SB_OHCI_REG51           0x51
+#define SB_OHCI_REG52           0x52
+#define SB_OHCI_REG58           0x58        // Over Current Control - RW
+#define SB_OHCI_REG5C           0x5C        // Over Current Control - RW  (800)??
+#define SB_OHCI_REG60           0x60        // Serial Bus Release Number - R (800)??
+#define SB_OHCI_REG68           0x68        // Over Current PME Enable - RW
+#define SB_OHCI_REG74           0x74        // Target Timeout Control - RW (800)
+#define SB_OHCI_REG78           0x78        //
+#define SB_OHCI_REG80           0x80        //
+#define SB_OHCI_REGD0           0x0D0       // MSI Control - RW
+#define SB_OHCI_REGD4           0x0D4       // MSI Address - RW
+#define SB_OHCI_REGD8           0x0D8       // MSI Data - RW
+#define SB_OHCI_REGE4           0x0E4       // HT MSI Support
+#define SB_OHCI_REGF0           0x0F0       // Function Level Reset Capability
+#define SB_OHCI_REGF4           0x0F4       // Function Level Reset Control
+
+#define SB_OHCI_BAR_REG00       0x00        // cRevision - R
+#define SB_OHCI_BAR_REG04       0x04        // cControl
+#define SB_OHCI_BAR_REG08       0x08        // cCommandStatus
+#define SB_OHCI_BAR_REG0C       0x0C        // cInterruptStatus  RW
+#define SB_OHCI_BAR_REG10       0x10        // cInterruptEnable
+#define SB_OHCI_BAR_REG14       0x14        // cInterruptDisable
+#define SB_OHCI_BAR_REG18       0x18        // HcCCA
+#define SB_OHCI_BAR_REG1C       0x1C        // cPeriodCurrentED
+#define SB_OHCI_BAR_REG20       0x20        // HcControleadED
+#define SB_OHCI_BAR_REG24       0x24        // cControlCurrentED  RW
+#define SB_OHCI_BAR_REG28       0x28        // HcBulkeadED
+#define SB_OHCI_BAR_REG2C       0x2C        // cBulkCurrentED- RW
+#define SB_OHCI_BAR_REG30       0x30        // HcDoneead
+#define SB_OHCI_BAR_REG34       0x34        // cFmInterval
+#define SB_OHCI_BAR_REG38       0x38        // cFmRemaining
+#define SB_OHCI_BAR_REG3C       0x3C        // cFmNumber
+#define SB_OHCI_BAR_REG40       0x40        // cPeriodicStart
+#define SB_OHCI_BAR_REG44       0x44        // HcLSThresold
+#define SB_OHCI_BAR_REG48       0x48        // HcRDescriptorA
+#define SB_OHCI_BAR_REG4C       0x4C        // HcRDescriptorB
+#define SB_OHCI_BAR_REG50       0x50        // HcRStatus
+#define SB_OHCI_BAR_REG54       0x54        // HcRhPortStatus (800)
+#define SB_OHCI_BAR_REG58       0x58        // HcRhPortStatus NPD (800)
+#define SB_OHCI_BAR_REGF0       0xF0        // OHCI Loop Back feature Support (800)
+
+//
+//  USB EHCI Device 0x7808
+//  Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2
+//
+#define SB_EHCI_REG00           0x00        // DEVICE/VENDOR ID - R
+#define SB_EHCI_REG04           0x04        // Command - RW
+#define SB_EHCI_REG06           0x06        // Status - R
+#define SB_EHCI_REG08           0x08        // Revision ID/Class Code - R
+#define SB_EHCI_REG0C           0x0C        // Miscellaneous - RW
+#define SB_EHCI_REG10           0x10        // BAR - RW
+#define SB_EHCI_REG2C           0x2C        // Subsystem ID/Subsystem Vendor ID - RW
+#define SB_EHCI_REG34           0x34        // Capability Pointer - R
+#define SB_EHCI_REG3C           0x3C        // Interrupt Line - RW
+#define SB_EHCI_REG3D           0x3D        // Interrupt Line - RW ??
+#define SB_EHCI_REG40           0x40        // Config Timers - RW ??
+#define SB_EHCI_REG4C           0x4C        // MSI - RW
+#define SB_EHCI_REG50           0x50        // EHCI Misc Control - RW
+#define SB_EHCI_REG54           0x54        // EHCI Misc Control - RW
+#define SB_EHCI_REG60           0x60        // SBRN - R
+#define SB_EHCI_REG61           0x61        // FLADJ - RW
+#define SB_EHCI_REG62           0x62        // PORTWAKECAP - RW
+#define SB_EHCI_REGC0           0x0C0       // PME control - RW (800)
+#define SB_EHCI_REGC4           0x0C4       // PME Data /Status - RW (800)
+#define SB_EHCI_REGD0           0x0D0       // MSI Control - RW
+#define SB_EHCI_REGD4           0x0D4       // MSI Address - RW
+#define SB_EHCI_REGD8           0x0D8       // MSI Data - RW
+#define SB_EHCI_REGE4           0x0E4       // EHCI Debug Port Support - RW (800)
+#define SB_EHCI_REGF0           0x0F0       // Function Level Reset Capability - R (800)
+#define SB_EHCI_REGF4           0x0F4       // Function Level Reset Capability - R (800)
+
+#define SB_EHCI_BAR_REG00       0x00        // CAPLENGT - R
+#define SB_EHCI_BAR_REG02       0x002       // CIVERSION- R
+#define SB_EHCI_BAR_REG04       0x004       // CSPARAMS - R
+#define SB_EHCI_BAR_REG08       0x008       // CCPARAMS - R
+#define SB_EHCI_BAR_REG0C       0x00C       // CSP-PORTROUTE - R
+
+#define SB_EHCI_BAR_REG20       0x020       // USBCMD - RW - 32 bits
+#define SB_EHCI_BAR_REG24       0x024       // USBSTS - RW - 32 bits
+#define SB_EHCI_BAR_REG28       0x028       // USBINTR -RW - 32 bits
+#define SB_EHCI_BAR_REG2C       0x02C       // FRINDEX -RW - 32 bits
+#define SB_EHCI_BAR_REG30       0x030       // CTRLDSSEGMENT -RW - 32 bits
+#define SB_EHCI_BAR_REG34       0x034       // PERIODICLISTBASE -RW - 32 bits
+#define SB_EHCI_BAR_REG38       0x038       // ASYNCLISTADDR -RW - 32 bits
+#define SB_EHCI_BAR_REG60       0x060       // CONFIGFLAG -RW - 32 bits
+#define SB_EHCI_BAR_REG64       0x064       // PORTSC (1-N_PORTS) -RW - 32 bits
+#define SB_EHCI_BAR_REGA0       0x0A0       // DebugPort MISC Control - RW - 32 bits (800)
+#define SB_EHCI_BAR_REGA4       0x0A4       // Packet Buffer Threshold Values - RW - 32 bits
+#define SB_EHCI_BAR_REGA8       0x0A8       // USB PHY Status 0 - R
+#define SB_EHCI_BAR_REGAC       0x0AC       // USB PHY Status 1 - R
+#define SB_EHCI_BAR_REGB0       0x0B0       // USB PHY Status 2 - R
+#define SB_EHCI_BAR_REGB4       0x0B4       // UTMI Control - RW (800)
+#define SB_EHCI_BAR_REGB8       0x0B8       // Loopback Test
+#define SB_EHCI_BAR_REGBC       0x0BC       // EHCI MISC Control
+#define SB_EHCI_BAR_REGC0       0x0C0       // USB PHY Calibration
+#define SB_EHCI_BAR_REGC4       0x0C4       // USB Common PHY Control
+#define SB_EHCI_BAR_REGC8       0x0C8       // EHCI Debug Purpose
+#define SB_EHCI_BAR_REGCC       0x0CC       // Ehci Spare 1 (800) **
+#define SB_EHCI_BAR_REG100      0x100       // USB debug port
+
+//
+//  Hudson-2 SB CFG device  0x780B
+//  Device 20 (0x14) Func 0
+//
+#define SB_CFG_REG00            0x000       // VendorID - R
+#define SB_CFG_REG02            0x002       // DeviceID - R
+#define SB_CFG_REG04            0x004       // Command- RW
+#define SB_CFG_REG05            0x005       // Command- RW
+#define SB_CFG_REG06            0x006       // STATUS- RW
+#define SB_CFG_REG08            0x008       // Revision ID/Class Code- R
+#define SB_CFG_REG0A            0x00A       //
+#define SB_CFG_REG0B            0x00B       //
+#define SB_CFG_REG0C            0x00C       // Cache Line Size- R
+#define SB_CFG_REG0D            0x00D       // Latency Timer- R
+#define SB_CFG_REG0E            0x00E       // Header Type- R
+#define SB_CFG_REG0F            0x00F       // BIST- R
+#define SB_CFG_REG10            0x010       // Base Address 0- R
+#define SB_CFG_REG11            0x011       //;
+#define SB_CFG_REG12            0x012       //;
+#define SB_CFG_REG13            0x013       //;
+#define SB_CFG_REG14            0x014       // Base Address 1- R
+#define SB_CFG_REG18            0x018       // Base Address 2- R
+#define SB_CFG_REG1C            0x01C       // Base Address 3- R
+#define SB_CFG_REG20            0x020       // Base Address 4- R
+#define SB_CFG_REG24            0x024       // Base Address 5- R
+#define SB_CFG_REG28            0x028       // Cardbus CIS Pointer- R
+#define SB_CFG_REG2C            0x02C       // Subsystem Vendor ID- W
+#define SB_CFG_REG2E            0x02E       // Subsystem ID- W
+#define SB_CFG_REG30            0x030       // Expansion ROM Base Address - R
+#define SB_CFG_REG34            0x034       // Capability Pointer - R  (800) default changed as 0x00
+#define SB_CFG_REG3C            0x03C       // Interrupt Line - R
+#define SB_CFG_REG3D            0x03D       // Interrupt Pin - R
+#define SB_CFG_REG3E            0x03E       // Min_Gnt - R
+#define SB_CFG_REG3F            0x03F       // Max_Lat - R
+#define SB_CFG_REG90            0x090       // Smbus Base Address - R
+#define SB_CFG_REG9C            0x09C       // SBResourceMMIO_BASE
+
+//
+//  Hudson-2 SATA IDE device
+//  Device 20 (0x14) Func 1
+//
+
+#define SB_IDE_REG00            0x00        // Vendor ID
+#define SB_IDE_REG02            0x02        // Device ID
+#define SB_IDE_REG04            0x04        // Command
+#define SB_IDE_REG06            0x06        // Status
+#define SB_IDE_REG08            0x08        // Revision ID/Class Code
+#define SB_IDE_REG09            0x09        // Class Code
+#define SB_IDE_REG2C            0x2C        // Subsystem ID and Subsystem Vendor ID
+#define SB_IDE_REG40            0x40        // Configuration - RW - 32 bits
+#define SB_IDE_REG34            0x34
+#define SB_IDE_REG62            0x62        // IDE Internal Control
+#define SB_IDE_REG63            0x63        // IDE Internal Control
+//
+//  Hudson-2 AZALIA device  0x780D
+//  Device 20 (0x14) Func 2
+//
+#define ATI_AZALIA_ExtBlk_Addr          0x0F8
+#define ATI_AZALIA_ExtBlk_DATA          0x0FC
+
+#define SB_AZ_REG00             0x00        // Vendor ID - R
+#define SB_AZ_REG02             0x02        // Device ID - R/W
+#define SB_AZ_REG04             0x04        // PCI Command
+#define SB_AZ_REG06             0x06        // PCI Status - R/W
+#define SB_AZ_REG08             0x08        // Revision ID
+#define SB_AZ_REG09             0x09        // Programming Interface
+#define SB_AZ_REG0A             0x0A        // Sub Class Code
+#define SB_AZ_REG0B             0x0B        // Base Class Code
+#define SB_AZ_REG0C             0x0C        // Cache Line Size - R/W
+#define SB_AZ_REG0D             0x0D        // Latency Timer
+#define SB_AZ_REG0E             0x0E        // Header Type
+#define SB_AZ_REG0F             0x0F        // BIST
+#define SB_AZ_REG10             0x10        // Lower Base Address Register
+#define SB_AZ_REG14             0x14        // Upper Base Address Register
+#define SB_AZ_REG2C             0x2C        // Subsystem Vendor ID
+#define SB_AZ_REG2D             0x2D        // Subsystem ID
+#define SB_AZ_REG34             0x34        // Capabilities Pointer
+#define SB_AZ_REG3C             0x3C        // Interrupt Line
+#define SB_AZ_REG3D             0x3D        // Interrupt Pin
+#define SB_AZ_REG3E             0x3E        // Minimum Grant
+#define SB_AZ_REG3F             0x3F        // Maximum Latency
+#define SB_AZ_REG40             0x40        // Misc Control 1
+#define SB_AZ_REG42             0x42        // Misc Control 2 Register
+#define SB_AZ_REG43             0x43        // Misc Control 3 Register
+#define SB_AZ_REG44             0x44        // Interrupt Pin Control Register
+#define SB_AZ_REG46             0x46        // Debug Control Register
+#define SB_AZ_REG4C             0x4C
+#define SB_AZ_REG50             0x50        // Power Management Capability ID
+#define SB_AZ_REG52             0x52        // Power Management Capabilities
+#define SB_AZ_REG54             0x54        // Power Management Control/Status
+#define SB_AZ_REG60             0x60        // MSI Capability ID
+#define SB_AZ_REG62             0x62        // MSI Message Control
+#define SB_AZ_REG64             0x64        // MSI Message Lower Address
+#define SB_AZ_REG68             0x68        // MSI Message Upper Address
+#define SB_AZ_REG6C             0x6C        // MSI Message Data
+
+#define SB_AZ_BAR_REG00         0x00        // Global Capabilities - R
+#define SB_AZ_BAR_REG02         0x02        // Minor Version - R
+#define SB_AZ_BAR_REG03         0x03        // Major Version - R
+#define SB_AZ_BAR_REG04         0x04        // Output Payload Capability - R
+#define SB_AZ_BAR_REG06         0x06        // Input Payload Capability - R
+#define SB_AZ_BAR_REG08         0x08        // Global Control - R/W
+#define SB_AZ_BAR_REG0C         0x0C        // Wake Enable - R/W
+#define SB_AZ_BAR_REG0E         0x0E        // State Change Status - R/W
+#define SB_AZ_BAR_REG10         0x10        // Global Status - R/W
+#define SB_AZ_BAR_REG18         0x18        // Output Stream Payload Capability - R
+#define SB_AZ_BAR_REG1A         0x1A        // Input Stream Payload Capability - R
+#define SB_AZ_BAR_REG20         0x20        // Interrupt Control - R/W
+#define SB_AZ_BAR_REG24         0x24        // Interrupt Status - R/W
+#define SB_AZ_BAR_REG30         0x30        // Wall Clock Counter - R
+#define SB_AZ_BAR_REG38         0x38        // Stream Synchronization - R/W
+#define SB_AZ_BAR_REG40         0x40        // CORB Lower Base Address - R/W
+#define SB_AZ_BAR_REG44         0x44        // CORB Upper Base Address - RW
+#define SB_AZ_BAR_REG48         0x48        // CORB Write Pointer - R/W
+#define SB_AZ_BAR_REG4A         0x4A        // CORB Read Pointer - R/W
+#define SB_AZ_BAR_REG4C         0x4C        // CORB Control - R/W
+#define SB_AZ_BAR_REG4D         0x4D        // CORB Status - R/W
+#define SB_AZ_BAR_REG4E         0x4E        // CORB Size - R/W
+#define SB_AZ_BAR_REG50         0x50        // RIRB Lower Base Address - RW
+#define SB_AZ_BAR_REG54         0x54        // RIRB Upper Address - RW
+#define SB_AZ_BAR_REG58         0x58        // RIRB Write Pointer - RW
+#define SB_AZ_BAR_REG5A         0x5A        // RIRB Response Interrupt Count - R/W
+#define SB_AZ_BAR_REG5C         0x5C        // RIRB Control - R/W
+#define SB_AZ_BAR_REG5D         0x5D        // RIRB Status - R/W
+#define SB_AZ_BAR_REG5E         0x5E        // RIRB Size - R/W
+#define SB_AZ_BAR_REG60         0x60        // Immediate Command Output Interface - R/W
+#define SB_AZ_BAR_REG64         0x64        // Immediate Command Input Interface - R/W
+#define SB_AZ_BAR_REG68         0x68        // Immediate Command Input Interface - R/W
+#define SB_AZ_BAR_REG70         0x70        // DMA Position Lower Base Address - R/W
+#define SB_AZ_BAR_REG74         0x74        // DMA Position Upper Base Address - R/W
+#define SB_AZ_BAR_REG2030       0x2030      // Wall Clock Counter Alias - R
+
+//
+//  Hudson-2 LPC Device  0x780E
+//  Device 20 (0x14) Func 3
+//
+#define SB_LPC_REG00            0x00        // VID- R
+#define SB_LPC_REG02            0x02        // DID- R
+#define SB_LPC_REG04            0x04        // CMD- RW
+#define SB_LPC_REG06            0x06        // STATUS- RW
+#define SB_LPC_REG08            0x08        // Revision  ID/Class Code - R
+#define SB_LPC_REG0C            0x0C        // Cache Line Size - R
+#define SB_LPC_REG0D            0x0D        // Latency Timer - R
+#define SB_LPC_REG0E            0x0E        // Header Type - R
+#define SB_LPC_REG0F            0x0F        // BIST- R
+#define SB_LPC_REG10            0x10        // Base Address Reg 0- RW*
+#define SB_LPC_REG2C            0x2C        // Subsystem ID & Subsystem Vendor ID - Wo/Ro
+#define SB_LPC_REG34            0x34        // Capabilities Pointer - Ro
+#define SB_LPC_REG40            0x40        // PCI Control - RW
+#define SB_LPC_REG44            0x44        // IO Port Decode Enable Register 1- RW
+#define SB_LPC_REG45            0x45        // IO Port Decode Enable Register 2- RW
+#define SB_LPC_REG46            0x46        // IO Port Decode Enable Register 3- RW
+#define SB_LPC_REG47            0x47        // IO Port Decode Enable Register 4- RW
+#define SB_LPC_REG48            0x48        // IO/Mem Port Decode Enable Register 5- RW
+#define SB_LPC_REG49            0x49        // LPC Sync Timeout Count - RW
+#define SB_LPC_REG4A            0x4A        // IO/Mem Port Decode Enable Register 6- RW
+#define SB_LPC_REG4C            0x4C        // Memory Range Register - RW
+#define SB_LPC_REG50            0x50        // Rom Protect 0 - RW
+#define SB_LPC_REG54            0x54        // Rom Protect 1 - RW
+#define SB_LPC_REG58            0x58        // Rom Protect 2 - RW
+#define SB_LPC_REG5C            0x5C        // Rom Protect 3 - RW
+#define SB_LPC_REG60            0x60        // PCI Memory Start Address of LPC Target Cycles -
+#define SB_LPC_REG62            0x62        // PCI Memory End Address of LPC Target Cycles -
+#define SB_LPC_REG64            0x64        // PCI IO base Address of Wide Generic Port - RW
+#define SB_LPC_REG65            0x65
+#define SB_LPC_REG66            0x66
+#define SB_LPC_REG67            0x67
+#define SB_LPC_REG68            0x68        // LPC ROM Address Range 1 (Start Address) - RW
+#define SB_LPC_REG69            0x69
+#define SB_LPC_REG6A            0x6A        // LPC ROM Address Range 1 (End Address) - RW
+#define SB_LPC_REG6B            0x6B
+#define SB_LPC_REG6C            0x6C        // LPC ROM Address Range 2 (Start Address)- RW
+#define SB_LPC_REG6D            0x6D
+#define SB_LPC_REG6E            0x6E        // LPC ROM Address Range 2 (End Address) - RW
+#define SB_LPC_REG6F            0x6F
+#define SB_LPC_REG70            0x70        // Firmware ub Select - RW*
+#define SB_LPC_REG71            0x71
+#define SB_LPC_REG72            0x72
+#define SB_LPC_REG73            0x73
+#define SB_LPC_REG74            0x74        // Alternative Wide IO Range Enable- W/R
+#define SB_LPC_REG78            0x78        // Miscellaneous Control Bits- W/R
+#define SB_LPC_REG7C            0x7C        // TPM (trusted plant form module) reg- W/R
+#define SB_LPC_REG9C            0x9C
+#define SB_LPC_REG80            0x80        // MSI Capability Register- R
+#define SB_LPC_REGA0            0x0A0       // SPI base address
+#define SB_LPC_REGA1            0x0A1       // SPI base address
+#define SB_LPC_REGA2            0x0A2       // SPI base address
+#define SB_LPC_REGA3            0x0A3       // SPI base address
+#define SB_LPC_REGA4            0x0A4
+#define SB_LPC_REGBA            0x0BA       // EcControl
+#define SB_LPC_REGBB            0x0BB       // HostControl
+#define SB_LPC_REGCC            0x0CC       // AutoRomCfg
+#define SB_LPC_REGD0            0x0D0       // SB_LPC_REGD0
+
+//
+//  Hudson-2 PCIB  0x780F
+//  Device 20 (0x14) Func 4
+//
+#define SB_PCIB_REG04            0x04       // Command
+#define SB_PCIB_REG0D            0x0D       // Primary Master Latency Timer
+#define SB_PCIB_REG1B            0x1B       // Secondary Latency Timer
+#define SB_PCIB_REG1C            0x1C       // IO Base
+#define SB_PCIB_REG1D            0x1D       // IO Limit
+#define SB_PCIB_REG40            0x40       // CPCTRL
+#define SB_PCIB_REG42            0x42       // CLKCTRL
+#define SB_PCIB_REG48            0x48       //
+#define SB_PCIB_REG4A            0x4A       // PCICLK Enable Bits
+#define SB_PCIB_REG4B            0x4B       // Misc Control
+#define SB_PCIB_REG4C            0x4C       // AutoClockRun Control
+#define SB_PCIB_REG50            0x50       // Dual Address Cycle Enable and PCIB_CLK_Stop Override
+#define SB_PCIB_REG65            0x65       // Misc Control
+#define SB_PCIB_REG66            0x66       // Misc Control
+//
+//  Hudson-2 GEC 0x14E4 0x1699
+//  Device 20 (0x14) Func 6
+//
+#define SB_GEC_REG10             0x10       // GEC BAR
+//
+//  Hudson-2 SB MMIO Base (SMI)
+//    offset : 0x200
+//
+#define SB_SMI_REG00            0x00         // EventStatus
+#define SB_SMI_REG04            0x04         // EventEnable
+#define SB_SMI_REG08            0x08         // SciTrig
+#define SB_SMI_REG0C            0x0C         // SciLevl
+#define SB_SMI_REG10            0x10         // SmiSciStatus
+#define SB_SMI_REG14            0x14         // SmiSciEn
+#define SB_SMI_REG18            0x18         // ForceSciEn
+#define SB_SMI_REG1C            0x1C         // SciRwData
+#define SB_SMI_REG20            0x20         // SciS0En
+#define SB_SMI_REG3C            0x3C         // DataErrStatus
+#define SB_SMI_Gevent0          0x40         // SciMap0
+#define SB_SMI_Gevent1          0x41         // SciMap1
+#define SB_SMI_Gevent2          0x42         // SciMap2
+#define SB_SMI_Gevent3          0x43         // SciMap3
+#define SB_SMI_Gevent4          0x44         // SciMap4
+#define SB_SMI_Gevent5          0x45         // SciMap5
+#define SB_SMI_Gevent6          0x46         // SciMap6
+#define SB_SMI_Gevent7          0x47         // SciMap7
+#define SB_SMI_Gevent8          0x48         // SciMap8
+#define SB_SMI_Gevent9          0x49         // SciMap9
+#define SB_SMI_Gevent10         0x4A         // SciMap10
+#define SB_SMI_Gevent11         0x4B         // SciMap11
+#define SB_SMI_Gevent12         0x4C         // SciMap12
+#define SB_SMI_Gevent13         0x4D         // SciMap13
+#define SB_SMI_Gevent14         0x4E         // SciMap14
+#define SB_SMI_Gevent15         0x4F         // SciMap15
+#define SB_SMI_Gevent16         0x50         // SciMap16
+#define SB_SMI_Gevent17         0x51         // SciMap17
+#define SB_SMI_Gevent18         0x52         // SciMap18
+#define SB_SMI_Gevent19         0x53         // SciMap19
+#define SB_SMI_Gevent20         0x54         // SciMap20
+#define SB_SMI_Gevent21         0x55         // SciMap21
+#define SB_SMI_Gevent22         0x56         // SciMap22
+#define SB_SMI_Gevent23         0x57         // SciMap23
+#define SB_SMI_Usbwakup0        0x58         // SciMap24
+#define SB_SMI_Usbwakup1        0x59         // SciMap25
+#define SB_SMI_Usbwakup2        0x5A         // SciMap26
+#define SB_SMI_Usbwakup3        0x5B         // SciMap27
+#define SB_SMI_SBGppPme0        0x5C         // SciMap28
+#define SB_SMI_SBGppPme1        0x5D         // SciMap29
+#define SB_SMI_SBGppPme2        0x5E         // SciMap30
+#define SB_SMI_SBGppPme3        0x5F         // SciMap31
+#define SB_SMI_SBGppHp0         0x60         // SciMap32
+#define SB_SMI_Reserved0        0x61         // SciMap33
+#define SB_SMI_Reserved1        0x62         // SciMap34
+#define SB_SMI_Reserved2        0x63         // SciMap35
+#define SB_SMI_AzaliaPme        0x64         // SciMap36
+#define SB_SMI_SataGevent0      0x65         // SciMap37
+#define SB_SMI_SataGevent1      0x66         // SciMap38
+#define SB_SMI_GecPme           0x67         // SciMap39
+#define SB_SMI_IMCGevent0       0x68         // SciMap40
+#define SB_SMI_IMCGevent1       0x69         // SciMap41
+#define SB_SMI_CIRPme           0x6A         // SciMap42
+#define SB_SMI_Reserved3        0x6B         // SciMap43
+#define SB_SMI_FanThGevent      0x6C         // SciMap44    //FanThermalGevent
+#define SB_SMI_ASFMasterIntr    0x6D         // SciMap45
+#define SB_SMI_ASFSlaveIntr     0x6E         // SciMap46
+#define SB_SMI_SMBUS0           0x6F         // SciMap47
+#define SB_SMI_TWARN            0x70         // SciMap48
+#define SB_SMI_TMI              0x71         // SciMap49    // TrafficMonitorIntr
+#define SB_SMI_iLLB             0x72         // SciMap50
+#define SB_SMI_PowerButton      0x73         // SciMap51
+#define SB_SMI_ProcHot          0x74         // SciMap52
+#define SB_SMI_APUHwAssertion   0x75         // SciMap53
+#define SB_SMI_APUSciAssertion  0x76         // SciMap54
+#define SB_SMI_RAS              0x77         // SciMap55
+#define SB_SMI_xHC0Pme          0x78         // SciMap56
+#define SB_SMI_xHC1Pme          0x79         // SciMap57
+
+// Empty from 0x72-0x7F
+//#Define SB_SMI_REG7C            0x7F         // SciMap63  ***
+
+#define SB_SMI_REG80            0x80         //  SmiStatus0
+#define SB_SMI_REG84            0x84         // SmiStatus1
+#define SB_SMI_REG88            0x88         // SmiStatus2
+#define SB_SMI_REG8C            0x8C         // SmiStatus3
+#define SB_SMI_REG90            0x90         // SmiStatus4
+#define SB_SMI_REG94            0x94         // SmiPointer
+#define SB_SMI_REG96            0x96         // SmiTimer
+#define SB_SMI_REG98            0x98         // SmiTrig
+#define SB_SMI_REG9C            0x9C         // SmiTrig
+#define SB_SMI_REGA0            0xA0
+#define SB_SMI_REGA1            0xA1
+#define SB_SMI_REGA2            0xA2
+#define SB_SMI_REGA3            0xA3
+#define SB_SMI_REGA4            0xA4
+#define SB_SMI_REGA5            0xA5
+#define SB_SMI_REGA6            0xA6
+#define SB_SMI_REGA7            0xA7
+#define SB_SMI_REGA8            0xA8
+#define SB_SMI_REGA9            0xA9
+#define SB_SMI_REGAA            0xAA
+#define SB_SMI_REGAB            0xAB
+#define SB_SMI_REGAC            0xAC
+#define SB_SMI_REGAD            0xAD
+#define SB_SMI_REGAE            0xAE
+#define SB_SMI_REGAF            0xAF
+#define SB_SMI_REGB0            0xB0
+#define SB_SMI_REGB1            0xB1
+#define SB_SMI_REGB2            0xB2
+#define SB_SMI_REGB3            0xB3
+#define SB_SMI_REGB4            0xB4
+#define SB_SMI_REGB5            0xB5
+#define SB_SMI_REGB6            0xB6
+#define SB_SMI_REGB7            0xB7
+#define SB_SMI_REGB8            0xB8
+#define SB_SMI_REGB9            0xB9
+#define SB_SMI_REGBA            0xBA
+#define SB_SMI_REGBB            0xBB
+#define SB_SMI_REGBC            0xBC
+#define SB_SMI_REGBD            0xBD
+#define SB_SMI_REGBE            0xBE
+#define SB_SMI_REGBF            0xBF
+#define SB_SMI_REGC0            0xC0
+#define SB_SMI_REGC1            0xC1
+#define SB_SMI_REGC2            0xC2
+#define SB_SMI_REGC3            0xC3
+#define SB_SMI_REGC4            0xC4
+#define SB_SMI_REGC5            0xC5
+#define SB_SMI_REGC6            0xC6
+#define SB_SMI_REGC7            0xC7
+#define SB_SMI_REGC8            0xC8
+#define SB_SMI_REGCA            0xCA         //  IoTrapping1
+#define SB_SMI_REGCC            0xCC         //  IoTrapping2
+#define SB_SMI_REGCE            0xCE         //  IoTrapping3
+#define SB_SMI_REGD0            0xD0         //  MemTrapping0
+#define SB_SMI_REGD4            0xD4         //  MemRdOvrData0
+#define SB_SMI_REGD8            0xD8         //  MemTrapping1
+#define SB_SMI_REGDC            0xDC         //  MemRdOvrData1
+#define SB_SMI_REGE0            0xE0         //  MemTrapping2
+#define SB_SMI_REGE4            0xE4         //  MemRdOvrData2
+#define SB_SMI_REGE8            0xE8         //  MemTrapping3
+#define SB_SMI_REGEC            0xEC         //  MemRdOvrData3
+#define SB_SMI_REGF0            0xF0         //  CfgTrapping0
+#define SB_SMI_REGF4            0xF4         //  CfgTrapping1
+#define SB_SMI_REGF8            0xF8         //  CfgTrapping2
+#define SB_SMI_REGFC            0xFC         //  CfgTrapping3
+
+//
+//  Hudson-2 SB MMIO Base (PMIO)
+//    offset : 0x300
+//
+#define SB_PMIOA_REG00          0x00        // ISA Decode
+#define SB_PMIOA_REG04          0x04        // ISA Control
+#define SB_PMIOA_REG08          0x08        // PCI Control
+#define SB_PMIOA_REG0C          0x0C        // StpClkSmaf
+#define SB_PMIOA_REG10          0x10        // RetryDetect
+#define SB_PMIOA_REG14          0x14        // StuckDetect
+#define SB_PMIOA_REG20          0x20        // BiosRamEn
+#define SB_PMIOA_REG24          0x24        //  AcpiMmioEn
+#define SB_PMIOA_REG28          0x28         // AsfEn
+#define SB_PMIOA_REG2C          0x2C         // Smbus0En
+#define SB_PMIOA_REG2E          0x2E         // Smbus0Sel
+#define SB_PMIOA_REG34          0x34         // IoApicEn
+#define SB_PMIOA_REG3C          0x3C         // SmartVoltEn
+#define SB_PMIOA_REG40          0x40         // SmartVolt2En
+#define SB_PMIOA_REG44          0x44         // BootTimerEn
+#define SB_PMIOA_REG48          0x48         // WatchDogTimerEn
+#define SB_PMIOA_REG4C          0x4C         // WatchDogTimerConfig
+#define SB_PMIOA_REG50          0x50         // HPETEn
+#define SB_PMIOA_REG54          0x54         // SerialIrqConfig
+#define SB_PMIOA_REG56          0x56         // RtcControl
+#define SB_PMIOA_REG57          0x57         //
+#define SB_PMIOA_REG58          0x58         // VRT_T1
+#define SB_PMIOA_REG59          0x59         // VRT_T2
+#define SB_PMIOA_REG5A          0x5A         // IntruderControl
+#define SB_PMIOA_REG5B          0x5B         // RtcShadow
+#define SB_PMIOA_REG5C          0x5C
+#define SB_PMIOA_REG5D          0x5D
+#define SB_PMIOA_REG5E          0x5E         // RtcExtIndex
+#define SB_PMIOA_REG5F          0x5F         // RtcExtData
+#define SB_PMIOA_REG60          0x60         // AcpiPm1EvtBlk
+#define SB_PMIOA_REG62          0x62         // AcpiPm1CntBlk
+#define SB_PMIOA_REG64          0x64         // AcpiPmTmrBlk
+#define SB_PMIOA_REG66          0x66         // P_CNTBlk
+#define SB_PMIOA_REG68          0x68         // AcpiGpe0Blk
+#define SB_PMIOA_REG6A          0x6A         // AcpiSmiCmd
+#define SB_PMIOA_REG6C          0x6C         // AcpiPm2CntBlk
+#define SB_PMIOA_REG6E          0x6E         // AcpiPmaCntBlk
+#define SB_PMIOA_REG74          0x74         // AcpiConfig
+#define SB_PMIOA_REG78          0x78         // WakeIoAddr
+#define SB_PMIOA_REG7A          0x7A         // HaltCountEn
+#define SB_PMIOA_REG7C          0x7C         // C1eWrPortAdr
+#define SB_PMIOA_REG7E          0x7E         // CStateEn
+#define SB_PMIOA_REG80          0x80         // BreakEvent
+#define SB_PMIOA_REG84          0x84         // AutoArbEn
+#define SB_PMIOA_REG88          0x88         // CStateControl
+#define SB_PMIOA_REG89          0x89         //
+#define SB_PMIOA_REG8C          0x8C         // StpClkHoldTime
+#define SB_PMIOA_REG8E          0x8E         // PopUpEndTime
+#define SB_PMIOA_REG90          0x90         // C4Control
+#define SB_PMIOA_REG94          0x94         // CStateTiming0
+#define SB_PMIOA_REG96          0x96         //
+#define SB_PMIOA_REG97          0x97         //
+#define SB_PMIOA_REG98          0x98         // CStateTiming1
+#define SB_PMIOA_REG99          0x99         //
+#define SB_PMIOA_REG9B          0x9B         //
+#define SB_PMIOA_REG9C          0x9C         // C2Count
+#define SB_PMIOA_REG9D          0x9D         // C3Count
+#define SB_PMIOA_REG9E          0x9E         // C4Count
+#define SB_PMIOA_REGA0          0xA0         // MessageCState
+#define SB_PMIOA_REGA4          0xA4         //
+#define SB_PMIOA_REGA8          0xA8         // TrafficMonitorIdleTime
+#define SB_PMIOA_REGAA          0xAA         // TrafficMonitorIntTime
+#define SB_PMIOA_REGAC          0xAC         // TrafficMonitorTrafficCount
+#define SB_PMIOA_REGAE          0xAE         // TrafficMonitorIntrCount
+#define SB_PMIOA_REGB0          0xB0         // TrafficMonitorTimeTick
+#define SB_PMIOA_REGB4          0xB4         // FidVidControl
+#define SB_PMIOA_REGB6          0xB6         // TPRESET1
+#define SB_PMIOA_REGB7          0xB7         // Tpreset1b
+#define SB_PMIOA_REGB8          0xB8         // TPRESET2
+#define SB_PMIOA_REGB9          0xB9         // Test0
+#define SB_PMIOA_REGBA          0xBA         // S_StateControl
+#define SB_PMIOA_REGBB          0xBB         //
+#define SB_PMIOA_REGBC          0xBC         // ThrottlingControl
+#define SB_PMIOA_REGBE          0xBE         // ResetControl
+#define SB_PMIOA_REGBF          0xBF         // ResetControl
+#define SB_PMIOA_REGC0          0xC0         // S5Status
+#define SB_PMIOA_REGC2          0xC2         // ResetStatus
+#define SB_PMIOA_REGC4          0xC4         // ResetCommand
+#define SB_PMIOA_REGC5          0xC5         // CF9Shadow
+#define SB_PMIOA_REGC6          0xC6         // HTControl
+#define SB_PMIOA_REGC8          0xC8         // Misc
+#define SB_PMIOA_REGCC          0xCC         // IoDrvSth
+#define SB_PMIOA_REGD0          0xD0         // CLKRunEn
+#define SB_PMIOA_REGD2          0xD2         // PmioDebug
+#define SB_PMIOA_REGD3          0xD3         // SD
+#define SB_PMIOA_REGD6          0xD6         // IMCGating
+#define SB_PMIOA_REGD8          0xD8         // MiscIndex
+#define SB_PMIOA_REGD9          0xD9         // MiscData
+#define SB_PMIOA_REGDA          0xDA         // SataConfig
+#define SB_PMIOA_REGDC          0xDC         // HyperFlashConfig
+#define SB_PMIOA_REGDE          0xDE         // ABConfig
+#define SB_PMIOA_REGE0          0xE0         // ABRegBar
+#define SB_PMIOA_REGE6          0xE6         // FcEn
+#define SB_PMIOA_REGE7          0xE7
+#define SB_PMIOA_REGEA          0xEA         // PcibConfig
+#define SB_PMIOA_REGEB          0xEB         // AzEn
+#define SB_PMIOA_REGEC          0xEC         // LpcGating
+#define SB_PMIOA_REGED          0xED         // UsbGating
+#define SB_PMIOA_REGEE          0xEE         // UsbCntrl
+#define SB_PMIOA_REGEF          0xEF         // UsbEnable
+#define SB_PMIOA_REGF0          0xF0         // UsbControl
+#define SB_PMIOA_REGF3          0xF3         // UsbDebug
+#define SB_PMIOA_REGF6          0xF6         // GecEn
+#define SB_PMIOA_REGF8          0xF8         // GecConfig
+#define SB_PMIOA_REGFC          0xFC         // TraceMemoryEn
+
+//
+//  Hudson-2 SB MMIO Base (PMIO2)
+//    offset : 0x400
+//
+#define SB_PMIO2_REG00          0x00        // Fan0InputControl
+#define SB_PMIO2_REG01          0x01        // Fan0Control
+#define SB_PMIO2_REG02          0x02        // Fan0Freq
+#define SB_PMIO2_REG03          0x03        // LowDuty0
+#define SB_PMIO2_REG04          0x04        // MidDuty0
+
+#define SB_PMIO2_REG10          0x00        // Fan1InputControl
+#define SB_PMIO2_REG11          0x01        // Fan1Control
+#define SB_PMIO2_REG12          0x02        // Fan1Freq
+#define SB_PMIO2_REG13          0x03        // LowDuty1
+#define SB_PMIO2_REG14          0x04        // MidDuty1
+
+#define SB_PMIO2_REG63          0x63        // SampleFreqDiv
+#define SB_PMIO2_REG69          0x69        // Fan0 Speed
+#define SB_PMIO2_REG95          0x95        // Temperature
+#define SB_PMIO2_REGB8          0xB8        // Voltage
+#define SB_PMIO2_REGEA          0xEA        // Hwm_Calibration
+
+#define SB_PMIO2_REG92          0x92        //
+#define SB_PMIO2_REGF8          0xF8        // VoltageSamleSel
+#define SB_PMIO2_REGF9          0xF9        // TempSampleSel
+
+#define SB_PMIO2_REG          0xFC         // TraceMemoryEn
+
+
+//
+//  Hudson-2 SB MMIO Base (GPIO/IoMux)
+//    offset : 0x100/0xD00
+//
+/*
+GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226.
+*/
+#define SB_GPIO_REG00           0x00
+#define SB_GPIO_REG06           0x06
+#define SB_GPIO_REG09           0x09
+#define SB_GPIO_REG10           0x0A
+#define SB_GPIO_REG17           0x11
+#define SB_GPIO_REG21           0x15
+#define SB_GPIO_REG28           0x1C
+#define SB_GPIO_REG32           0x20
+#define SB_GPIO_REG33           0x21
+#define SB_GPIO_REG34           0x22
+#define SB_GPIO_REG35           0x23
+#define SB_GPIO_REG36           0x24
+#define SB_GPIO_REG37           0x25
+#define SB_GPIO_REG38           0x26
+#define SB_GPIO_REG39           0x27
+#define SB_GPIO_REG40           0x28
+#define SB_GPIO_REG41           0x29
+#define SB_GPIO_REG42           0x2A
+#define SB_GPIO_REG43           0x2B
+#define SB_GPIO_REG44           0x2C
+#define SB_GPIO_REG45           0x2D
+#define SB_GPIO_REG46           0x2E
+#define SB_GPIO_REG47           0x2F
+#define SB_GPIO_REG48           0x30
+#define SB_GPIO_REG49           0x31
+#define SB_GPIO_REG50           0x32
+#define SB_GPIO_REG51           0x33
+#define SB_GPIO_REG52           0x34
+#define SB_GPIO_REG53           0x35
+#define SB_GPIO_REG54           0x36
+#define SB_GPIO_REG55           0x37
+#define SB_GPIO_REG56           0x38
+#define SB_GPIO_REG57           0x39
+#define SB_GPIO_REG58           0x3A
+#define SB_GPIO_REG59           0x3B
+#define SB_GPIO_REG60           0x3C
+#define SB_GPIO_REG61           0x3D
+#define SB_GPIO_REG62           0x3E
+#define SB_GPIO_REG63           0x3F
+#define SB_GPIO_REG64           0x40
+#define SB_GPIO_REG65           0x41
+#define SB_GPIO_REG66           0x42
+#define SB_GPIO_REG67           0x43
+
+#define SB_GEVENT_REG00         0x60
+#define SB_GEVENT_REG01         0x61
+#define SB_GEVENT_REG02         0x62
+#define SB_GEVENT_REG03         0x63
+#define SB_GEVENT_REG04         0x64
+#define SB_GEVENT_REG05         0x65
+#define SB_GEVENT_REG06         0x66
+#define SB_GEVENT_REG07         0x67
+#define SB_GEVENT_REG08         0x68
+#define SB_GEVENT_REG09         0x69
+#define SB_GEVENT_REG10         0x6A
+#define SB_GEVENT_REG11         0x6B
+#define SB_GEVENT_REG12         0x6C
+#define SB_GEVENT_REG13         0x6D
+#define SB_GEVENT_REG14         0x6E
+#define SB_GEVENT_REG15         0x6F
+#define SB_GEVENT_REG16         0x70
+#define SB_GEVENT_REG17         0x71
+#define SB_GEVENT_REG18         0x72
+#define SB_GEVENT_REG19         0x73
+#define SB_GEVENT_REG20         0x74
+#define SB_GEVENT_REG21         0x75
+#define SB_GEVENT_REG22         0x76
+#define SB_GEVENT_REG23         0x77
+// S5-DOMAIN GPIO
+#define SB_GPIO_REG160          0xA0
+#define SB_GPIO_REG161          0xA1
+#define SB_GPIO_REG162          0xA2
+#define SB_GPIO_REG163          0xA3
+#define SB_GPIO_REG164          0xA4
+#define SB_GPIO_REG165          0xA5
+#define SB_GPIO_REG166          0xA6
+#define SB_GPIO_REG167          0xA7
+#define SB_GPIO_REG168          0xA8
+#define SB_GPIO_REG169          0xA9
+#define SB_GPIO_REG170          0xAA
+#define SB_GPIO_REG171          0xAB
+#define SB_GPIO_REG172          0xAC
+#define SB_GPIO_REG173          0xAD
+#define SB_GPIO_REG174          0xAE
+#define SB_GPIO_REG175          0xAF
+#define SB_GPIO_REG176          0xB0
+#define SB_GPIO_REG177          0xB1
+#define SB_GPIO_REG178          0xB2
+#define SB_GPIO_REG179          0xB3
+#define SB_GPIO_REG180          0xB4
+#define SB_GPIO_REG181          0xB5
+#define SB_GPIO_REG182          0xB6
+#define SB_GPIO_REG183          0xB7
+#define SB_GPIO_REG184          0xB8
+#define SB_GPIO_REG185          0xB9
+#define SB_GPIO_REG186          0xBA
+#define SB_GPIO_REG187          0xBB
+#define SB_GPIO_REG188          0xBC
+#define SB_GPIO_REG189          0xBD
+#define SB_GPIO_REG190          0xBE
+#define SB_GPIO_REG191          0xBF
+#define SB_GPIO_REG192          0xC0
+#define SB_GPIO_REG193          0xC1
+#define SB_GPIO_REG194          0xC2
+#define SB_GPIO_REG195          0xC3
+#define SB_GPIO_REG196          0xC4
+#define SB_GPIO_REG197          0xC5
+#define SB_GPIO_REG198          0xC6
+#define SB_GPIO_REG199          0xC7
+#define SB_GPIO_REG200          0xC8
+#define SB_GPIO_REG201          0xC9
+#define SB_GPIO_REG202          0xCA
+#define SB_GPIO_REG203          0xCB
+#define SB_GPIO_REG204          0xCC
+#define SB_GPIO_REG205          0xCD
+#define SB_GPIO_REG206          0xCE
+#define SB_GPIO_REG207          0xCF
+#define SB_GPIO_REG208          0xD0
+#define SB_GPIO_REG209          0xD1
+#define SB_GPIO_REG210          0xD2
+#define SB_GPIO_REG211          0xD3
+#define SB_GPIO_REG212          0xD4
+#define SB_GPIO_REG213          0xD5
+#define SB_GPIO_REG214          0xD6
+#define SB_GPIO_REG215          0xD7
+#define SB_GPIO_REG216          0xD8
+#define SB_GPIO_REG217          0xD9
+#define SB_GPIO_REG218          0xDA
+#define SB_GPIO_REG219          0xDB
+#define SB_GPIO_REG220          0xDC
+#define SB_GPIO_REG221          0xDD
+#define SB_GPIO_REG222          0xDE
+#define SB_GPIO_REG223          0xDF
+#define SB_GPIO_REG224          0xF0
+#define SB_GPIO_REG225          0xF1
+#define SB_GPIO_REG226          0xF2
+#define SB_GPIO_REG227          0xF3
+#define SB_GPIO_REG228          0xF4
+
+//
+//  Hudson-2 SB MMIO Base (SMBUS)
+//    offset : 0xA00
+//
+#define SB_SMBUS_REG12           0x12        //   I2CbusConfig
+
+//
+//  Hudson-2 SB MMIO Base (MISC)
+//    offset : 0xE00
+//
+#define SB_MISC_REG00           0x00        //  ClkCntrl0
+/*
+SB_MISC_REG00                   EQU     000h
+  ClkCntrl0                   EQU     0FFFFFFFFh
+*/
+#define SB_MISC_REG04           0x04        //  ClkCntrl1
+/*
+SB_MISC_REG04                   EQU     004h
+  ClkCntrl1                   EQU     0FFFFFFFFh
+*/
+#define SB_MISC_REG08           0x08        //  ClkCntrl2
+/*
+SB_MISC_REG08                   EQU     008h
+  ClkCntrl2                   EQU     0FFFFFFFFh
+*/
+#define SB_MISC_REG0C           0x0C        //  ClkCntrl3
+/*
+SB_MISC_REG0C                   EQU     00Ch
+  ClkCntrl3                   EQU     0FFFFFFFFh
+*/
+#define SB_MISC_REG10           0x10        //  ClkCntrl4
+/*
+SB_MISC_REG10                   EQU     010h
+  ClkCntrl4                   EQU     0FFFFFFFFh
+*/
+#define SB_MISC_REG14           0x14        //   ClkCntrl5
+/*
+SB_MISC_REG14                   EQU     014h
+  ClkCntrl5                   EQU     0FFFFFFFFh
+*/
+#define SB_MISC_REG18           0x18        //   ClkCntrl6
+/*
+SB_MISC_REG18                   EQU     018h
+  ClkCntrl6                   EQU     0FFFFFFFFh
+*/
+#define SB_MISC_REG30           0x30         // OscFreqCounter
+/*
+SB_MISC_REG30                   EQU     030h
+  OscCounter                  EQU     0FFFFFFFFh                  ; The 32bit register shows the number of OSC clock per second.
+*/
+#define SB_MISC_REG34           0x34         //  HpetClkPeriod
+/*
+SB_MISC_REG34                   EQU     034h
+  HpetClkPeriod               EQU     0FFFFFFFFh                  ; default - 0x429B17Eh (14.31818M).
+*/
+#define SB_MISC_REG40           0x40         //  MiscCntrl      for clock only
+#define SB_MISC_REG41           0x41         //  MiscCntr2
+#define SB_MISC_REG42           0x42         //  MiscCntr3
+#define SB_MISC_REG50           0x50         //
+#define SB_MISC_REGB6           0xB6         //
+/*
+SB_MISC_REG40                   EQU     040h
+*/
+
+#define SB_MISC_REG80           0x80        /**< SB_MISC_REG80
+                                   *   @par
+                                   *   StrapStatus [15.0] - Hudson-2 chip Strap Status
+                                   *    @li <b>0001</b> - Not USED FWH
+                                   *    @li <b>0002</b> - Not USED LPC ROM
+                                   *    @li <b>0004</b> - EC enabled
+                                   *    @li <b>0008</b> - Reserved
+                                   *    @li <b>0010</b> - Internal Clock mode
+                                   */
+
+#define  ChipSysNotUseFWHRom    0x0001                            // EcPwm3 pad
+#define  ChipSysNotUseLpcRom    0x0002                            // Inverted version from EcPwm2 pad (default - 1)
+                                                                  // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type.
+#define  ChipSysEcEnable        0x0004                            // Enable Embedded Controller (EC)
+#define  ChipSysBootFailTmrEn   0x0008                            // Enable Watchdog function
+#define  ChipSysIntClkGen       0x0010                            // Select 25Mhz crystal clock or 100Mhz PCI-E clock **
+
+#define SB_MISC_REG84           0x84         //  StrapOverride
+/*
+SB_MISC_REG84                   EQU     084h
+  Override FWHDisableStrap    EQU     BIT0                        ; Override FWHDiableStrap value from external pin.
+  Override UseLpcRomStrap     EQU     BIT1                        ; Override UseLpcRomStrap value from external pin.
+  Override EcEnableStrap      EQU     BIT2                        ; Override EcEnableStrap value from external pin.
+  Override BootFailTmrEnStrap EQU     BIT3                        ; Override BootFailTmrEnStrap value from external pin.
+  Override DefaultModeStrap   EQU     BIT5                        ; Override DefaultModeStrap value from external pin.
+  Override I2CRomStrap        EQU     BIT7                        ; Override I2CRomStrap value from external pin.
+  Override ILAAutorunEnBStrap EQU     BIT8                        ; Override ILAAutorunEnBStrap value from external pin.
+  Override FcPllBypStrap      EQU     BIT9                        ; Override FcPllBypStrap value from external pin.
+  Override PciPllBypStrap     EQU     BIT10                       ; Override PciPllBypStrap value from external pin.
+  Override ShortResetStrap    EQU     BIT11                       ; Override ShortResetStrap value from external pin.
+  Override FastBif2ClkStrap   EQU     BIT13                       ; Override FastBif2ClkStrap value from external pin'
+  PciRomBootStrap             EQU     BIT15                       ; Override PCI Rom Boot Strap value from external pin ?? Not match 0x80 reg ??
+  BlinkSlowModestrap          EQU     BIT16                       ; Override Blink Slow mode (100Mhz) from external pin'
+  ClkGenStrap                 EQU     BIT17                       ; Override CLKGEN from external pin.
+  BIF_GEN2_COMPL_Strap        EQU     BIT18                       ; Override BIF_ GEN2_COMPLIANCE strap from external pin.
+  StrapOverrideEn             EQU     BIT31                       ; Enable override strapping feature.
+*/
+#define SB_MISC_REGC0           0xC0        //  CPU_Pstate0
+/*
+SB_MISC_REGC0                   EQU     0C0h
+  Core0_PState                EQU     BIT0+BIT1+BIT2              ; 000: P0  001: P1  010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
+  Core1_PState                EQU     BIT4+BIT5+BIT6
+  Core2_PState                EQU     BIT8+BIT9+BIT10
+  Core3_PState                EQU     BIT12+BIT13+BIT14
+  Core4_PState                EQU     BIT16++BIT17+BIT18
+  Core5_PState                EQU     BIT20+BIT21+BIT22
+  Core6_PState                EQU     BIT24+BIT25+BIT26
+  Core7_PState                EQU     BIT28+BIT29+BIT30
+*/
+#define SB_MISC_REGC4           0xC4         //  CPU_Pstate1
+/*
+SB_MISC_REGC4                   EQU     0C4h
+  Core8_PState                EQU     BIT0+BIT1+BIT2              ; 000: P0  001: P1  010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
+  Core9_PState                EQU     BIT4+BIT5+BIT6
+  Core10_PState               EQU     BIT8+BIT9+BIT10
+  Core11_PState               EQU     BIT12+BIT13+BIT14
+  Core12_PState               EQU     BIT16++BIT17+BIT18
+  Core13_PState               EQU     BIT20+BIT21+BIT22
+  Core14_PState               EQU     BIT24+BIT25+BIT26
+  Core15_PState               EQU     BIT28+BIT29+BIT30
+*/
+#define SB_MISC_REGD0           0xD0         //  CPU_Cstate0
+/*
+SB_MISC_REGD0                   EQU     0D0h
+  Core0_CState                EQU     BIT0+BIT1+BIT2              ; 000: C0  001: C1  010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
+  Core1_CState                EQU     BIT4+BIT5+BIT6
+  Core2_CState                EQU     BIT8+BIT9+BIT10
+  Core3_CState                EQU     BIT12+BIT13+BIT14
+  Core4_CState                EQU     BIT16++BIT17+BIT18
+  Core5_CState                EQU     BIT20+BIT21+BIT22
+  Core6_CState                EQU     BIT24+BIT25+BIT26
+  Core7_CState                EQU     BIT28+BIT29+BIT30
+*/
+#define SB_MISC_REGD4           0xD4         //  CPU_Cstate1
+/*
+SB_MISC_REGD4                   EQU     0D4h
+  Core8_CState                EQU     BIT0+BIT1+BIT2              ; 000: C0  001: C1  010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
+  Core9_CState                EQU     BIT4+BIT5+BIT6
+  Core10_CState               EQU     BIT8+BIT9+BIT10
+  Core11_CState               EQU     BIT12+BIT13+BIT14
+  Core12_CState               EQU     BIT16++BIT17+BIT18
+  Core13_CState               EQU     BIT20+BIT21+BIT22
+  Core14_CState               EQU     BIT24+BIT25+BIT26
+  Core15_CState               EQU     BIT28+BIT29+BIT30
+*/
+#define SB_MISC_REGF0           0xF0         //  SataPortSts    ?? EC touch only
+/*
+SB_MISC_REGF0                   EQU     0F0h
+  Port0Sts                    EQU     BIT0                        ; The selected status of Port 0.
+  Port1Sts                    EQU     BIT1                        ; The selected status of Port 1
+  Port2Sts                    EQU     BIT2                        ; The selected status of Port 2.
+  Port3Sts                    EQU     BIT3                        ; The selected status of Port 3
+  Port4Sts                    EQU     BIT4                        ; The selected status of Port 4.
+  Port5Sts                    EQU     BIT5                        ; The selected status of Port 5
+  SataPortSel                 EQU     BIT24+BIT25                 ; 00  - Select "led" for Port 0 to 5
+                                  ; 01 - Select "delete" for Port 0 to 5
+                                  ; 10 - Select "err" for Port 0 to 5
+                                  ; 11 - Select "led" for Port 0 to 5
+*/
+
+//
+//  Hudson-2 SB MMIO Base (SERIAL_DEBUG_BASE)
+//    offset : 0x1000
+//
+#define SB_SDB_REG00            0x00        //
+#define SB_SDB_REG74            0x74
+
+#define SB_RTC_REG00            0x00        // Seconds - RW
+#define SB_RTC_REG01            0x01        // Seconds Alarm - RW
+#define SB_RTC_REG02            0x02        // Minutes - RW
+#define SB_RTC_REG03            0x03        // Minutes Alarm - RW
+#define SB_RTC_REG04            0x04        // ours - RW
+#define SB_RTC_REG05            0x05        // ours Alarm- RW
+#define SB_RTC_REG06            0x06        // Day of Week - RW
+#define SB_RTC_REG07            0x07        // Date of Mont - RW
+#define SB_RTC_REG08            0x08        // Mont - RW
+#define SB_RTC_REG09            0x09        // Year - RW
+#define SB_RTC_REG0A            0x0A        // Register A - RW
+#define SB_RTC_REG0B            0x0B        // Register B - RW
+#define SB_RTC_REG0C            0x0C        // Register C - R
+#define SB_RTC_REG0D            0x0D        // DateAlarm - RW
+#define SB_RTC_REG32            0x32        // AltCentury - RW
+#define SB_RTC_REG48            0x48        // Century - RW
+#define SB_RTC_REG50            0x50        // Extended RAM Address Port - RW
+#define SB_RTC_REG53            0x53        // Extended RAM Data Port - RW
+#define SB_RTC_REG7E            0x7E        // RTC Time Clear - RW
+#define SB_RTC_REG7F            0x7F        // RTC RAM Enable - RW
+
+#define SB_ECMOS_REG00           0x00        // scratch - reg
+//;BIT0=0   AsicDebug is enabled
+//;BIT1=0   SLT S3 runs
+#define SB_ECMOS_REG01          0x01
+#define SB_ECMOS_REG02          0x02
+#define SB_ECMOS_REG03          0x03
+#define SB_ECMOS_REG04          0x04
+#define SB_ECMOS_REG05          0x05
+#define SB_ECMOS_REG06          0x06
+#define SB_ECMOS_REG07          0x07
+#define SB_ECMOS_REG08          0x08        // save 32BIT Physical address of Config structure
+#define SB_ECMOS_REG09          0x09
+#define SB_ECMOS_REG0A          0x0A
+#define SB_ECMOS_REG0B          0x0B
+
+#define SB_ECMOS_REG0C          0x0C        //;save MODULE_ID
+#define SB_ECMOS_REG0D          0x0D        //;Reserve for NB
+
+#define SB_IOMAP_REG00          0x000   // Dma_C 0
+#define SB_IOMAP_REG02          0x002   // Dma_C 1
+#define SB_IOMAP_REG04          0x004   // Dma_C 2
+#define SB_IOMAP_REG06          0x006   // Dma_C 3
+#define SB_IOMAP_REG08          0x008   // Dma_Status
+#define SB_IOMAP_REG09          0x009   // Dma_WriteRest
+#define SB_IOMAP_REG0A          0x00A   // Dma_WriteMask
+#define SB_IOMAP_REG0B          0x00B   // Dma_WriteMode
+#define SB_IOMAP_REG0C          0x00C   // Dma_Clear
+#define SB_IOMAP_REG0D          0x00D   // Dma_MasterClr
+#define SB_IOMAP_REG0E          0x00E   // Dma_ClrMask
+#define SB_IOMAP_REG0F          0x00F   // Dma_AllMask
+#define SB_IOMAP_REG20          0x020   // IntrCntrlReg1
+#define SB_IOMAP_REG21          0x021   // IntrCntrlReg2
+#define SB_IOMAP_REG40          0x040   // TimerC0
+#define SB_IOMAP_REG41          0x041   // TimerC1
+#define SB_IOMAP_REG42          0x042   // TimerC2
+#define SB_IOMAP_REG43          0x043   // Tmr1CntrlWord
+#define SB_IOMAP_REG61          0x061   // Nmi_Status
+#define SB_IOMAP_REG70          0x070   // Nmi_Enable
+#define SB_IOMAP_REG71          0x071   // RtcDataPort
+#define SB_IOMAP_REG72          0x072   // AlternatRtcAddrPort
+#define SB_IOMAP_REG73          0x073   // AlternatRtcDataPort
+#define SB_IOMAP_REG80          0x080   // Dma_Page_Reserved0
+#define SB_IOMAP_REG81          0x081   // Dma_PageC2
+#define SB_IOMAP_REG82          0x082   // Dma_PageC3
+#define SB_IOMAP_REG83          0x083   // Dma_PageC1
+#define SB_IOMAP_REG84          0x084   // Dma_Page_Reserved1
+#define SB_IOMAP_REG85          0x085   // Dma_Page_Reserved2
+#define SB_IOMAP_REG86          0x086   // Dma_Page_Reserved3
+#define SB_IOMAP_REG87          0x087   // Dma_PageC0
+#define SB_IOMAP_REG88          0x088   // Dma_Page_Reserved4
+#define SB_IOMAP_REG89          0x089   // Dma_PageC6
+#define SB_IOMAP_REG8A          0x08A   // Dma_PageC7
+#define SB_IOMAP_REG8B          0x08B   // Dma_PageC5
+#define SB_IOMAP_REG8C          0x08C   // Dma_Page_Reserved5
+#define SB_IOMAP_REG8D          0x08D   // Dma_Page_Reserved6
+#define SB_IOMAP_REG8E          0x08E   // Dma_Page_Reserved7
+#define SB_IOMAP_REG8F          0x08F   // Dma_Refres
+#define SB_IOMAP_REG92          0x092   // FastInit
+#define SB_IOMAP_REGA0          0x0A0   // IntrCntrl2Reg1
+#define SB_IOMAP_REGA1          0x0A1   // IntrCntrl2Reg2
+#define SB_IOMAP_REGC0          0x0C0   // Dma2_C4Addr
+#define SB_IOMAP_REGC2          0x0C2   // Dma2_C4Cnt
+#define SB_IOMAP_REGC4          0x0C4   // Dma2_C5Addr
+#define SB_IOMAP_REGC6          0x0C6   // Dma2_C5Cnt
+#define SB_IOMAP_REGC8          0x0C8   // Dma2_C6Addr
+#define SB_IOMAP_REGCA          0x0CA   // Dma2_C6Cnt
+#define SB_IOMAP_REGCC          0x0CC   // Dma2_C7Addr
+#define SB_IOMAP_REGCE          0x0CE   // Dma2_C7Cnt
+#define SB_IOMAP_REGD0          0x0D0   // Dma_Status
+#define SB_IOMAP_REGD2          0x0D2   // Dma_WriteRest
+#define SB_IOMAP_REGD4          0x0D4   // Dma_WriteMask
+#define SB_IOMAP_REGD6          0x0D6   // Dma_WriteMode
+#define SB_IOMAP_REGD8          0x0D8   // Dma_Clear
+#define SB_IOMAP_REGDA          0x0DA   // Dma_Clear
+#define SB_IOMAP_REGDC          0x0DC   // Dma_ClrMask
+#define SB_IOMAP_REGDE          0x0DE   // Dma_ClrMask
+#define SB_IOMAP_REGF0          0x0F0   // NCP_Error
+#define SB_IOMAP_REG40B         0x040B  // DMA1_Extend
+#define SB_IOMAP_REG4D0         0x04D0  // IntrEdgeControl
+#define SB_IOMAP_REG4D6         0x04D6  // DMA2_Extend
+#define SB_IOMAP_REGC00         0x0C00  // Pci_Intr_Index
+#define SB_IOMAP_REGC01         0x0C01  // Pci_Intr_Data
+#define SB_IOMAP_REGC14         0x0C14  // Pci_Error
+#define SB_IOMAP_REGC50         0x0C50  // CMIndex
+#define SB_IOMAP_REGC51         0x0C51  // CMData
+#define SB_IOMAP_REGC52         0x0C52  // GpmPort
+#define SB_IOMAP_REGC6F         0x0C6F  // Isa_Misc
+#define SB_IOMAP_REGCD0         0x0CD0  // PMio2_Index
+#define SB_IOMAP_REGCD1         0x0CD1  // PMio2_Data
+#define SB_IOMAP_REGCD4         0x0CD4  // BIOSRAM_Index
+#define SB_IOMAP_REGCD5         0x0CD5  // BIOSRAM_Data
+#define SB_IOMAP_REGCD6         0x0CD6  // PM_Index
+#define SB_IOMAP_REGCD7         0x0CD7  // PM_Data
+#define SB_IOMAP_REGCF9         0x0CF9          // CF9Rst reg
+
+
+#define SB_SPI_MMIO_REG00       0x00        //SPI_
+#define SB_SPI_MMIO_REG0C       0x0C        //SPI_Cntrl1 Register
+#define SB_SPI_MMIO_REG1C       0x1C        //
+
+#define SB_SPI_MODE_FAST        0x7        //
+#define SB_SPI_MODE_NORMAL      0x6        //
+#define SB_SPI_MODE_QUAL_144    0x5        //
+#define SB_SPI_MODE_QUAL_122    0x4        //
+#define SB_SPI_MODE_QUAL_114    0x3        //
+#define SB_SPI_MODE_QUAL_112    0x2        //
+
+#define AMD_NB_REG78            0x78
+#define AMD_NB_SCRATCH          AMD_NB_REG78
+#define MailBoxPort             0x3E
+
+// GPP Link Configuration
+#define GPP_CFGMODE_X4000       0x0
+#define GPP_CFGMODE_X2200       0x2
+#define GPP_CFGMODE_X2110       0x3
+#define GPP_CFGMODE_X1111       0x4
+
+#define MAX_LT_POLLINGS         0x4000
+
+
+#define ACPIMMIO32(x) (*(unsigned int*)(unsigned int)(x))
+#define ACPIMMIO16(x) (*(unsigned short*)(unsigned int)(x))
+#define ACPIMMIO8(x)  (*(unsigned char*)(unsigned int)(x))
+
+#ifdef XHCI_SUPPORT
+  #define XHCI_ACPI_MMIO_AMD_REG00     0x00
+  #define U3PLL_LOCK                   BIT7
+  #define U3PLL_RESET                  BIT8
+  #define U3PHY_RESET                  BIT9
+  #define U3CORE_RESET                 BIT10
+  #define XHC0_FUNC_RESET              BIT11
+  #define XHC1_FUNC_RESET              BIT12
+
+  #define XHCI_ACPI_MMIO_AMD_REG04     0x04
+  #define XHCI_ACPI_MMIO_AMD_REG08     0x08
+  #define XHCI_ACPI_MMIO_AMD_REG10     0x10
+  #define XHCI_ACPI_MMIO_AMD_REG20     0x20
+  #define XHCI_ACPI_MMIO_AMD_REG88     0x88
+  #define XHCI_ACPI_MMIO_AMD_REG90     0x90 // adaptation timer settings
+  #define XHCI_ACPI_MMIO_AMD_REG98     0x98 //
+  #define XHCI_ACPI_MMIO_AMD_REGA0     0xA0 // BAR 0
+  #define XHCI_ACPI_MMIO_AMD_REGA4     0xA4 // BAR 1
+  #define XHCI_ACPI_MMIO_AMD_REGA8     0xA8 // BAR 2
+  #define XHCI_ACPI_MMIO_AMD_REGB0     0xB0 // SPI_Valid_Base.
+  #define XHCI_ACPI_MMIO_AMD_REGC0     0xC0 // Firmware starting offset for coping
+  #define XHCI_ACPI_MMIO_AMD_REGB4     0xB4
+  #define XHCI_ACPI_MMIO_AMD_REGD0     0xD0
+
+  #define SB_XHCI_REG48                0x48 // XHCI IND_REG Index registers
+  #define SB_XHCI_REG4C                0x4C // XHCI IND_REG Data registers
+
+  #define SB_XHCI_IND_REG00            0x00 //
+  #define SB_XHCI_IND_REG04            0x04 //
+  #define SB_XHCI_IND_REG94            0x94 // adaptation mode settings
+  #define SB_XHCI_IND_REG98            0x98 // CR phase and frequency filter settings
+  #define SB_XHCI_IND_REGD4            0xD4 // adaptation mode settings
+  #define SB_XHCI_IND_REGD8            0xD8 // CR phase and frequency filter settings
+
+  #define SB_XHCI_IND60_BASE            0x40000000 //
+
+  #define SB_XHCI_IND60_REG00          SB_XHCI_IND60_BASE + 0x00 //
+  #define SB_XHCI_IND60_REG04          SB_XHCI_IND60_BASE + 0x04 //
+  #define SB_XHCI_IND60_REG08          SB_XHCI_IND60_BASE + 0x08 //
+  #define SB_XHCI_IND60_REG0C          SB_XHCI_IND60_BASE + 0x0C //
+
+  #define SPI_HEAD_LENGTH 0x0E
+  #define SPI_BAR0_VLD  0x01
+  #define SPI_BASE0     (0x00 << 7)
+  #define SPI_BAR1_VLD  (0x01 << 8)
+  #define SPI_BASE1     (SPI_HEAD_LENGTH << 10)
+  #define SPI_BAR2_VLD  (0x01 << 16)
+  #define SPI_BASE2(x)  ((SPI_HEAD_LENGTH + ACPIMMIO16(x)) << 18)
+
+  #define FW_TO_SIGADDR_OFFSET  0x0C
+  #define BCD_ADDR_OFFSET       0x02
+  #define BCD_SIZE_OFFSET       0x04
+  #define FW_ADDR_OFFSET        0x06
+  #define FW_SIZE_OFFSET        0x08
+  #define ACD_ADDR_OFFSET       0x0A
+  #define ACD_SIZE_OFFSET       0x0C
+
+#endif
+
+#define PKT_DATA_REG       ACPI_MMIO_BASE + GFX_DAC_BASE + 0x00
+#define PKT_LEN_REG        ACPI_MMIO_BASE + GFX_DAC_BASE + 0x14
+#define PKT_CTRL_REG       ACPI_MMIO_BASE + GFX_DAC_BASE + 0x15
+#define EFUS_DAC_ADJUSTMENT_CONTROL    0x850A8
+#define BGADJ                             0x1F
+#define DACADJ                            0x1B
+#define EFUS_DAC_ADJUSTMENT_CONTROL_DATA  (BGADJ + (DACADJ << 8) + BIT16 )
+
+//#define SB_USB1_OVER_CURRENT_CONTROL                            0x11111111
+//#define SB_USB2_OVER_CURRENT_CONTROL                            0x22222222
+//#define SB_USB3_OVER_CURRENT_CONTROL                            0x33333333
+//#define SB_USB4_OVER_CURRENT_CONTROL                            0x44444444
+//#define SB_XHCI0_OVER_CURRENT_CONTROL                           0x55555555
+//#define SB_XHCI1_OVER_CURRENT_CONTROL                           0x66666666
+
+#pragma pack (pop)
+
diff --git a/src/vendorcode/amd/cimx/sb900/Hwm.c b/src/vendorcode/amd/cimx/sb900/Hwm.c
new file mode 100755
index 0000000..8f0992f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Hwm.c
@@ -0,0 +1,578 @@
+/**
+ * @file
+ *
+ * Southbridge Initial routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+//
+// Declaration of local functions
+//
+VOID
+hwmInitRegister (
+  IN       AMDSBCFG* pConfig
+  );
+
+VOID
+hwmGetRawData (
+  IN       AMDSBCFG* pConfig
+  );
+
+VOID
+hwmCaculate (
+  IN       AMDSBCFG* pConfig
+  );
+
+VOID
+hwmGetCalibrationFactor (
+  IN       AMDSBCFG* pConfig
+  );
+
+VOID
+hwmProcessParameter (
+  IN       AMDSBCFG* pConfig
+  );
+
+VOID
+hwmSetRegister (
+  IN       AMDSBCFG* pConfig
+  );
+
+
+HWM_temp_par_struct tempParDefault[] = {
+  { 5219, 27365 , 0 },
+  { 5222, 27435 , 0 },
+  { 5219, 27516 , BIT0 },  //High Ratio
+  { 5221, 27580 , BIT1 },  //High Current
+  { 5123, 27866 , 0 }
+};
+
+//#ifndef NO_HWM_SUPPORT
+/**
+ * hwmInitRegister - Init Hardware Monitor Register.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmInitRegister (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32 LinearRangeOutLimit;
+
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccWidthUint8, 0, 0x55);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccWidthUint8, 0, 0x55);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccWidthUint8, 0, 0x55);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccWidthUint8, 0, 0x55);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccWidthUint8, 0, 0x06);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccWidthUint8, 0, 0x06);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccWidthUint8, 0, 0x06);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccWidthUint8, 0, 0x06);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccWidthUint8, 0, 0x06);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccWidthUint8, 0, 0x01);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccWidthUint8, 0, 0x01);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccWidthUint8, 0, 0x01);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccWidthUint8, 0, 0x01);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccWidthUint8, 0, 0x01);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE6, AccWidthUint8, 0xff, 0x02);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccWidthUint8, 0, 0x05);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccWidthUint8, 0, 0x06);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccWidthUint8, 0, 0x42);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccWidthUint8, 0, 0xFF);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccWidthUint8, 0, 0x1F);
+  //2.13 HWM Sensor Clk
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccWidthUint8, 0, 0x0A);
+  RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccWidthUint8, 0, 0x00);
+
+  //2.9 Enhancement of FanOut0 Control
+  //check for fanLinearEnhanceEn
+  if (pConfig->hwm.fanLinearEnhanceEn == 0) {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT11, BIT11);
+    LinearRangeOutLimit = (UINT32) (pConfig->hwm.fanLinearRangeOutLimit);
+    LinearRangeOutLimit = LinearRangeOutLimit << 20;
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4, AccWidthUint32, 0xFF0FFFFF, LinearRangeOutLimit);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT11, 0);
+  }
+  //check for fanLinearHoldFix
+  if (pConfig->hwm.fanLinearHoldFix == 0) {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT20, BIT20);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT20, 0);
+  }
+}
+
+
+/**
+ * hwmSbtsiAutoPolling - Hardware Monitor Auto Poll SB-TSI.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmSbtsiAutoPolling (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 dbValue;
+  UINT16 smbusBase;
+
+  smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
+  if (pConfig->hwm.hwmSbtsiAutoPoll == 1) {
+    hwmSbtsiAutoPollingPause (pConfig);
+
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), BIT2);
+    dbValue = 0xff;
+    WriteIO (smbusBase, AccWidthUint8, &dbValue);
+    dbValue = 0x08;
+    WriteIO (smbusBase + 2, AccWidthUint8, &dbValue);
+    dbValue = 0x09;
+    WriteIO (smbusBase + 3, AccWidthUint8, &dbValue);
+    dbValue = 0x98;
+    WriteIO (smbusBase + 4, AccWidthUint8, &dbValue);
+    if ( IsSbA11 () ) {
+      dbValue = 0x00;
+    } else {
+      dbValue = 0x20;
+    }
+    WriteIO (smbusBase + 5, AccWidthUint8, &dbValue);
+    dbValue = 0x48;
+    WriteIO (smbusBase + 2, AccWidthUint8, &dbValue);
+
+    ReadIO (smbusBase + 0, AccWidthUint8, &dbValue);
+    while ( dbValue & BIT0 ) {
+      ReadIO (smbusBase + 0, AccWidthUint8, &dbValue);
+    }
+
+    if ( IsSbA11 () ) {
+      dbValue = 0x09;
+    } else {
+      dbValue = 0x08;
+    }
+    WriteIO (smbusBase + 2, AccWidthUint8, &dbValue);
+    if ( IsSbA11 () ) {
+      dbValue = 0x01;
+    } else {
+      dbValue = 0x10;
+    }
+    WriteIO (smbusBase + 3, AccWidthUint8, &dbValue);
+    dbValue = 0x99;
+    WriteIO (smbusBase + 4, AccWidthUint8, &dbValue);
+    if ( IsSbA11 () ) {
+      dbValue = 0x0f;
+      WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
+    }
+
+    if ( IsSbA12Plus () ) {
+      dbValue = 0x80;
+      WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
+      dbValue = 0x01;
+      WriteIO (smbusBase + 0x17, AccWidthUint8, &dbValue);
+      dbValue = 0x81;
+      WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
+    }
+    //map SB-TSI to tempin0
+    RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + SB_PMIO2_REG92, AccWidthUint8, ~BIT3, BIT3);
+    dbValue = 0x00;
+    WriteIO (smbusBase + 0x16, AccWidthUint8, &dbValue);
+    pConfig->hwm.hwmSbtsiAutoPollStarted = TRUE;
+  } else {
+    hwmSbtsiAutoPollingOff (pConfig);
+  }
+}
+
+/**
+ * hwmSbtsiAutoPollingOff - Hardware Monitor Auto Poll SB-TSI
+ * Off.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmSbtsiAutoPollingOff (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 dbValue;
+  UINT16 smbusBase;
+
+  if ( pConfig->hwm.hwmEnable ) {
+    smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
+    dbValue = 0x00;
+    WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
+    hwmSbtsiAutoPollingPause (pConfig);
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0);
+    RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + SB_PMIO2_REG92, AccWidthUint8, ~BIT3, 0x00);
+    pConfig->hwm.hwmSbtsiAutoPollStarted = FALSE;
+  }
+}
+
+/**
+ * hwmSbtsiAutoPollingPause - Pause Hardware Monitor Auto Poll
+ * SB-TSI Off.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmSbtsiAutoPollingPause (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 dbValue;
+  UINT16 smbusBase;
+
+  if ( pConfig->hwm.hwmEnable && (pConfig->hwm.hwmSbtsiAutoPoll == 1) ) {
+    smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
+    dbValue = 0x01;
+    WriteIO (smbusBase + 0x16, AccWidthUint8, &dbValue);
+    dbValue = 0x00;
+    while ( dbValue == 0x00 ) {
+      ReadIO (smbusBase + 0x16, AccWidthUint8, &dbValue);
+    }
+  }
+}
+
+/**
+ * hwmGetRawData - Hardware Monitor Get Raw Data.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmGetRawData (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 i;
+  UINT16 dwValue;
+//_asm { jmp $ };
+  //fan speed
+  for ( i = 0; i < 5 ; i++ ) {
+    ReadPMIO2 (SB_PMIO2_REG69 + i * 5, AccWidthUint16, &dwValue);
+    if ( (dwValue & 0xFFC0) != 0xFFC0 ) {
+      pConfig->hwm.hwmCurrentRaw.fanSpeed[i] = dwValue;
+    } else {
+      pConfig->hwm.hwmCurrentRaw.fanSpeed[i] = 0xFFFF;
+    }
+  }
+  //temperatue
+  for ( i = 0; i < 5 ; i++ ) {
+    ReadPMIO2 (SB_PMIO2_REG95 + i * 4, AccWidthUint16, &dwValue);
+    if ( ( i == 1 ) || (dwValue > 0x4000) ) {
+      pConfig->hwm.hwmCurrentRaw.temperature[i] = dwValue;
+    }
+  }
+  //voltage
+  for ( i = 0; i < 8 ; i++ ) {
+    ReadPMIO2 (SB_PMIO2_REGB8 + i * 4, AccWidthUint16, &dwValue);
+    if ( (dwValue & 0xFFC0) != 0xFFC0 ) {
+      pConfig->hwm.hwmCurrentRaw.voltage[i] = dwValue;
+    }
+  }
+}
+
+/**
+ * hwmCaculate - Hardware Monitor Caculate Raw Data to Display Data.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmCaculate (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 i;
+  UINT16 dwValue;
+  //UINT32 ddValue;
+  //fan speed
+  for ( i = 0; i < 5 ; i++ ) {
+    dwValue = pConfig->hwm.hwmCurrentRaw.fanSpeed[i];
+    if ((dwValue == 0xffff) || (dwValue == 0x0000)) {
+      pConfig->hwm.hwmCurrent.fanSpeed[i] = 0;
+    } else {
+      pConfig->hwm.hwmCurrent.fanSpeed[i] = ( 22720 >> pConfig->hwm.fanSampleFreqDiv ) * 60 / dwValue / 2;
+    }
+  }
+  //temperatue
+  for ( i = 0; i < 5 ; i++ ) {
+    dwValue = pConfig->hwm.hwmCurrentRaw.temperature[i];
+    if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 1)) {
+      if ( IsSbA11 () ) {
+        dwValue = (dwValue >> 8) * 10;
+      } else {
+        dwValue = ((dwValue & 0xff00) >> 8) * 10 + (((dwValue & 0x00ff) * 10 ) >> 8);
+      }
+    } else {
+      dwValue = ((dwValue << 3) * pConfig->hwm.hwmTempPar[i].At / pConfig->hwm.hwmCalibrationFactor / 100 - pConfig->hwm.hwmTempPar[i].Ct) / 10  ;
+    }
+    if ( pConfig->hwm.hwmCurrentRaw.temperature[i] == 0 ) {
+      dwValue = 0;
+    }
+    if ( dwValue < 10000 ) {
+      pConfig->hwm.hwmCurrent.temperature[i] = dwValue;
+    } else {
+      pConfig->hwm.hwmCurrent.temperature[i] = 0;
+    }
+  }
+  //voltage
+  for ( i = 0; i < 8 ; i++ ) {
+    dwValue = pConfig->hwm.hwmCurrentRaw.voltage[i];
+    pConfig->hwm.hwmCurrent.voltage[i] = (dwValue >> 6) * 512 / pConfig->hwm.hwmCalibrationFactor;
+  }
+}
+
+/**
+ * hwmGetCalibrationFactor - Hardware Monitor Get Calibration
+ * Factor
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmGetCalibrationFactor (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 dbValue;
+//  UINT16 dwValue;
+//  UINT32 ddValue;
+  //temperatue parameter
+  ReadPMIO2 (SB_PMIO2_REGEA, AccWidthUint8, &dbValue);
+  if ( dbValue & BIT7 ) {
+    if ( dbValue & BIT6 ) {pConfig->hwm.hwmCalibrationFactor = 0x100 + dbValue;
+      } else {pConfig->hwm.hwmCalibrationFactor = 0x200 + (dbValue & 0x3f ); }
+  } else {
+    pConfig->hwm.hwmCalibrationFactor = 0x200;
+  }
+}
+
+/**
+ * hwmProcessParameter - Hardware Monitor process Parameter
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmProcessParameter (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 i;
+  UINT8 tempChannel;
+  UINT8 dbValue;
+  UINT16 dwValue;
+//  UINT32 ddValue;
+  hwmGetCalibrationFactor (pConfig);
+  //temperatue parameter
+  for ( i = 0; i < 5 ; i++ ) {
+    if ( pConfig->hwm.hwmTempPar[i].At == 0 ) {
+      pConfig->hwm.hwmTempPar[i] = tempParDefault[i];
+    }
+  }
+  for ( i = 0; i < 5 ; i++ ) {
+    if ( pConfig->hwm.hwmFanControl[i].LowDuty_reg03 == 100 ) {
+      pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03 = 255;
+    } else {
+      pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03 = (pConfig->hwm.hwmFanControl[i].LowDuty_reg03 << 8) / 100;
+    }
+    if ( pConfig->hwm.hwmFanControl[i].MedDuty_reg04 == 100 ) {
+      pConfig->hwm.hwmFanControlCooked[i].MedDuty_reg04 = 255;
+    } else {
+      pConfig->hwm.hwmFanControlCooked[i].MedDuty_reg04 = (pConfig->hwm.hwmFanControl[i].MedDuty_reg04 << 8) / 100;
+    }
+
+    if ( pConfig->hwm.hwmFanControl[i].HighTemp_reg0A > pConfig->hwm.hwmFanControl[i].MedTemp_reg08 ) {
+      dbValue = (UINT8) ((256 - pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03) / (pConfig->hwm.hwmFanControl[i].HighTemp_reg0A - pConfig->hwm.hwmFanControl[i].MedTemp_reg08));
+    } else {
+      dbValue = (UINT8) ((256 - pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03));
+    }
+
+    dwValue = pConfig->hwm.hwmFanControl[i].LowTemp_reg06;
+    if (pConfig->hwm.hwmFanControl[i].InputControl_reg00 > 4) {
+      tempChannel = 0;
+    } else {
+      tempChannel = pConfig->hwm.hwmFanControl[i].InputControl_reg00;
+    }
+    if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 0)) {
+      dwValue = dwValue << 8;
+    } else {
+      dbValue = (UINT8) (dbValue * 10000 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At / 512);
+      dwValue = ((dwValue * 100 + pConfig->hwm.hwmTempPar[tempChannel].Ct ) * 100 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At) >> 3;
+    }
+    pConfig->hwm.hwmFanControlCooked[i].LowTemp_reg06 = dwValue;
+    pConfig->hwm.hwmFanControlCooked[i].Multiplier_reg05 = dbValue & 0x3f;
+
+    dwValue = pConfig->hwm.hwmFanControl[i].MedTemp_reg08;
+    if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 0)) {
+      dwValue = dwValue << 8;
+    } else {
+      dwValue = ((dwValue * 100 + pConfig->hwm.hwmTempPar[tempChannel].Ct ) * 100 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At) >> 3;
+    }
+    pConfig->hwm.hwmFanControlCooked[i].MedTemp_reg08 = dwValue;
+    dwValue = pConfig->hwm.hwmFanControl[i].HighTemp_reg0A;
+    if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 0)) {
+      dwValue = dwValue << 8;
+    } else {
+      dwValue = ((dwValue * 100 + pConfig->hwm.hwmTempPar[tempChannel].Ct ) * 100 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At) >> 3;
+    }
+    pConfig->hwm.hwmFanControlCooked[i].HighTemp_reg0A = dwValue;
+  }
+}
+
+/**
+ * hwmSetRegister - Hardware Monitor Set Parameter
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmSetRegister (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 *pDbValue;
+  UINT8 i;
+  UINT8 registerN;
+  UINT8 registerPM2RegF8;
+  UINT8 registerPM2RegF9;
+
+  //UINT16 dwValue;
+//  UINT32 ddValue;
+  //Configure Fans
+  for ( i = 0; i < 5 ; i++ ) {
+    pDbValue = &(pConfig->hwm.hwmFanControlCooked[i].InputControl_reg00);
+    for ( registerN = 0; registerN < 0x0E ; registerN++ ) {
+      WritePMIO2 (i * 0x10 + registerN, AccWidthUint8, pDbValue);
+      pDbValue ++;
+    }
+  }
+  //Configure Sample Frequency Divider
+  WritePMIO2 (SB_PMIO2_REG63, AccWidthUint8, &(pConfig->hwm.fanSampleFreqDiv));
+
+  //Configure Mode
+  ReadPMIO2 (0xF8, AccWidthUint8, &registerPM2RegF8);
+  ReadPMIO2 (0xF9, AccWidthUint8, &registerPM2RegF9);
+  for ( i = 0; i < 5 ; i++ ) {
+    if (pConfig->hwm.hwmTempPar[i].Mode == BIT0) {
+      registerPM2RegF8 |= 1 << (i + 3);
+    } else if (pConfig->hwm.hwmTempPar[i].Mode == BIT1) {
+      registerPM2RegF9 |= 1 << (i + 3);
+    }
+  }
+  WritePMIO2 (0xF8, AccWidthUint8, &registerPM2RegF8);
+  WritePMIO2 (0xF9, AccWidthUint8, &registerPM2RegF9);
+}
+
+/**
+ * hwmUpdateData - Hardware Monitor Update Data.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmUpdateData (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  if ( pConfig->hwm.hwmEnable ) {
+    hwmSbtsiAutoPolling (pConfig);
+    hwmGetRawData (pConfig);
+    hwmCaculate (pConfig);
+  }
+}
+
+/**
+ * hwmCopyFanControl - Hardware Monitor Copy Fan Control Data.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmCopyFanControl (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 *fanControl;
+  UINT8 *fanControlCooked;
+  if ( pConfig->hwm.hwmEnable ) {
+    fanControl = & pConfig->hwm.hwmFanControl[0].InputControl_reg00;
+    fanControlCooked = & pConfig->hwm.hwmFanControlCooked[0].InputControl_reg00;
+    MemoryCopy (fanControlCooked, fanControl, (sizeof (HWM_fan_ctl_struct) * 5));
+  }
+}
+/**
+ * hwmInit - Init Hardware Monitor.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  hwmInitRegister (pConfig);
+  if ( pConfig->hwm.hwmEnable ) {
+    hwmCopyFanControl (pConfig);
+    hwmProcessParameter (pConfig);
+    hwmSetRegister (pConfig);
+    hwmSbtsiAutoPolling (pConfig);
+  }
+}
+
+//#endif
diff --git a/src/vendorcode/amd/cimx/sb900/IoLib.c b/src/vendorcode/amd/cimx/sb900/IoLib.c
new file mode 100755
index 0000000..d6eea67
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/IoLib.c
@@ -0,0 +1,92 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+
+VOID
+ReadIO (
+  IN       UINT16 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+  switch ( OpFlag ) {
+  case AccWidthUint8:
+    *(UINT8*)Value = ReadIo8 (Address);
+    break;
+  case AccWidthUint16:
+    *(UINT16*)Value = ReadIo16 (Address);
+    break;
+  case AccWidthUint32:
+    *(UINT32*)Value = ReadIo32 (Address);
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+WriteIO (
+  IN       UINT16 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+  switch ( OpFlag ) {
+  case AccWidthUint8:
+    WriteIo8 (Address, *(UINT8*)Value);
+    break;
+  case AccWidthUint16:
+    WriteIo16 (Address, *(UINT16*)Value);
+    break;
+  case AccWidthUint32:
+    WriteIo32 (Address, *(UINT32*)Value);
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+RWIO (
+  IN       UINT16 Address,
+  IN       UINT8 OpFlag,
+  IN       UINT32 Mask,
+  IN       UINT32 Data
+  )
+{
+  UINT32 Result;
+  ReadIO (Address, OpFlag, &Result);
+  Result = (Result & Mask) | Data;
+  WriteIO (Address, OpFlag, &Result);
+}
diff --git a/src/vendorcode/amd/cimx/sb900/Legacy.c b/src/vendorcode/amd/cimx/sb900/Legacy.c
new file mode 100755
index 0000000..cbdb540
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Legacy.c
@@ -0,0 +1,44 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+UINT32
+GetFixUp (
+  OUT VOID
+  )
+{
+  AMD_CONFIG_PARAMS* Result;
+  Result = (AMD_CONFIG_PARAMS*) getConfigPointer ();
+  if ( Result->ImageBasePtr > 0x100000 && Result->ImageBasePtr < 0xFF000000 ) {
+    return 0;
+  }
+  return Result->ImageBasePtr;
+}
diff --git a/src/vendorcode/amd/cimx/sb900/Makefile.inc b/src/vendorcode/amd/cimx/sb900/Makefile.inc
new file mode 100755
index 0000000..76b610f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Makefile.inc
@@ -0,0 +1,88 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+# CIMX Root directory
+CIMX_ROOT = $(src)/vendorcode/amd/cimx
+
+CIMX_INC  = -I$(src)/mainboard/$(MAINBOARDDIR)
+CIMX_INC  += -I$(src)/southbridge/amd/cimx/sb900
+CIMX_INC  += -I$(CIMX_ROOT)/sb900
+
+romstage-y += AcpiLib.c
+romstage-y += Azalia.c
+romstage-y += Dispatcher.c
+romstage-y += EcFanc.c
+romstage-y += EcFanLib.c
+romstage-y += Gec.c
+romstage-y += Gpp.c
+romstage-y += Pmio2Lib.c
+romstage-y += Sata.c
+romstage-y += SbCmn.c
+romstage-y += SbMain.c
+romstage-y += SbPor.c
+romstage-y += MemLib.c
+romstage-y += PciLib.c
+romstage-y += IoLib.c
+romstage-y += PmioLib.c
+romstage-y += AmdLib.c
+romstage-y += SbPeLib.c
+romstage-y += AmdSbLib.c
+romstage-y += EcLib.c
+romstage-y += Ec.c
+romstage-y += Smm.c
+romstage-y += Usb.c
+romstage-y += Hwm.c
+
+ramstage-y += AcpiLib.c
+ramstage-y += Azalia.c
+ramstage-y += Dispatcher.c
+ramstage-y += EcFanc.c
+ramstage-y += EcFanLib.c
+ramstage-y += Gec.c
+ramstage-y += Gpp.c
+ramstage-y += Pmio2Lib.c
+ramstage-y += Sata.c
+ramstage-y += SbCmn.c
+ramstage-y += SbMain.c
+ramstage-y += SbPor.c
+ramstage-y += MemLib.c
+ramstage-y += PciLib.c
+ramstage-y += IoLib.c
+ramstage-y += PmioLib.c
+ramstage-y += AmdLib.c
+ramstage-y += SbPeLib.c
+ramstage-y += AmdSbLib.c
+ramstage-y += EcLib.c
+ramstage-y += Ec.c
+ramstage-y += Smm.c
+ramstage-y += Usb.c
+#ramstage-y += Legacy.c
+#ramstage-y += SbModInf.c
+ramstage-y += Debug.c
+ramstage-y += GppHp.c
+ramstage-y += Hwm.c
+
+CIMX_CFLAGS =
+export CIMX_ROOT
+export CIMX_INC
+export CIMX_CFLAGS
+CC := $(CC) $(CIMX_INC)
+
+#######################################################################
+
diff --git a/src/vendorcode/amd/cimx/sb900/MemLib.c b/src/vendorcode/amd/cimx/sb900/MemLib.c
new file mode 100755
index 0000000..4e158c9
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/MemLib.c
@@ -0,0 +1,93 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+VOID
+ReadMEM (
+  IN       UINT32 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+  switch ( OpFlag ) {
+  case AccWidthUint8:
+    *((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
+    break;
+  case AccWidthUint16:
+    *((UINT16*)Value) = *((UINT16*) ((UINTN)Address));
+    break;
+  case AccWidthUint32:
+    *((UINT32*)Value) = *((UINT32*) ((UINTN)Address));
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+WriteMEM (
+  IN       UINT32 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+  switch ( OpFlag ) {
+  case AccWidthUint8 :
+    *((UINT8*) ((UINTN)Address)) = *((UINT8*)Value);
+    break;
+  case AccWidthUint16:
+    *((UINT16*) ((UINTN)Address)) = *((UINT16*)Value);
+    break;
+  case AccWidthUint32:
+    *((UINT32*) ((UINTN)Address)) = *((UINT32*)Value);
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+RWMEM (
+  IN       UINT32 Address,
+  IN       UINT8 OpFlag,
+  IN       UINT32 Mask,
+  IN       UINT32 Data
+  )
+{
+  UINT32 Result;
+  ReadMEM (Address, OpFlag, &Result);
+  Result = (Result & Mask) | Data;
+  WriteMEM (Address, OpFlag, &Result);
+}
+
+
diff --git a/src/vendorcode/amd/cimx/sb900/Oem.h b/src/vendorcode/amd/cimx/sb900/Oem.h
new file mode 100755
index 0000000..edda541
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Oem.h
@@ -0,0 +1,229 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#define BIOS_SIZE                      0x04   //04 - 1MB
+#define LEGACY_FREE                    0x00
+#define ACPI_SLEEP_TRAP                0x01
+//#define SPREAD_SPECTRUM_EPROM_LOAD     0x01
+
+/**
+ * Module Specific Defines for platform BIOS
+ *
+ */
+
+/**
+ * PCIEX_BASE_ADDRESS - Define PCIE base address
+ *
+ * @param[Option]     MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
+ */
+#ifdef  MOVE_PCIEBAR_TO_F0000000
+  #define PCIEX_BASE_ADDRESS           0xF7000000
+#else
+  #define PCIEX_BASE_ADDRESS           0xE0000000
+#endif
+
+/**
+ * SMBUS0_BASE_ADDRESS - Smbus base address
+ *
+ */
+#ifndef SMBUS0_BASE_ADDRESS
+  #define SMBUS0_BASE_ADDRESS          0xB00
+#endif
+
+/**
+ * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
+ *
+ */
+#ifndef SMBUS1_BASE_ADDRESS
+  #define SMBUS1_BASE_ADDRESS          0xB20
+#endif
+
+/**
+ * SIO_PME_BASE_ADDRESS - Super IO PME base address
+ *
+ */
+#ifndef SIO_PME_BASE_ADDRESS
+  #define SIO_PME_BASE_ADDRESS         0xE00
+#endif
+
+/**
+ * SPI_BASE_ADDRESS - SPI controller (ROM) base address
+ *
+ */
+#ifndef SPI_BASE_ADDRESS
+  #define SPI_BASE_ADDRESS             0xFEC10000
+#endif
+
+/**
+ * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
+ *
+ */
+#ifndef WATCHDOG_TIMER_BASE_ADDRESS
+  #define WATCHDOG_TIMER_BASE_ADDRESS  0xFEC000F0        // Watchdog Timer Base Address
+#endif
+
+/**
+ * HPET_BASE_ADDRESS - HPET base address
+ *
+ */
+#ifndef HPET_BASE_ADDRESS
+  #define HPET_BASE_ADDRESS            0xFED00000        // HPET Base address
+#endif
+
+/**
+ * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
+ *
+ */
+#ifdef ALT_ADDR_400
+  #define ACPI_BLK_BASE                0x400
+#else
+  #define ACPI_BLK_BASE                0x800
+#endif
+
+#define PM1_STATUS_OFFSET              0x00
+#define PM1_ENABLE_OFFSET              0x02
+#define PM1_CONTROL_OFFSET             0x04
+#define PM_TIMER_OFFSET                0x08
+#define CPU_CONTROL_OFFSET             0x10
+#define EVENT_STATUS_OFFSET            0x20
+#define EVENT_ENABLE_OFFSET            0x24
+
+/**
+ * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
+ *
+ */
+#define PM1_EVT_BLK_ADDRESS           ACPI_BLK_BASE + PM1_STATUS_OFFSET     // AcpiPm1EvtBlkAddr
+
+/**
+ * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
+ *
+ */
+#define PM1_CNT_BLK_ADDRESS           ACPI_BLK_BASE + PM1_CONTROL_OFFSET    // AcpiPm1CntBlkAddr
+
+/**
+ * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
+ *
+ */
+#define PM1_TMR_BLK_ADDRESS           ACPI_BLK_BASE + PM_TIMER_OFFSET       // AcpiPmTmrBlkAddr
+
+/**
+ * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
+ *
+ */
+#define CPU_CNT_BLK_ADDRESS           ACPI_BLK_BASE + CPU_CONTROL_OFFSET    // CpuControlBlkAddr
+
+/**
+ * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
+ *
+ */
+#define GPE0_BLK_ADDRESS              ACPI_BLK_BASE + EVENT_STATUS_OFFSET   // AcpiGpe0BlkAddr
+
+/**
+ * SMI_CMD_PORT - ACPI SMI Command block base address
+ *
+ */
+#define SMI_CMD_PORT                  0xB0              // SmiCmdPortAddr
+
+/**
+ * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
+ *
+ */
+#define ACPI_PMA_CNT_BLK_ADDRESS      0xFE00            // AcpiPmaCntBlkAddr
+
+/**
+ * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
+ *    Define value for SSID while SATA controller set to IDE mode.
+ */
+#define SATA_IDE_MODE_SSID           0x78001022
+/**
+ * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
+ *    Define value for SSID while SATA controller set to RAID mode.
+ */
+#define SATA_RAID_MODE_SSID          0x78021022
+
+/**
+ * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
+ *    Define value for SSID while SATA controller set to RAID5 mode.
+ */
+#define SATA_RAID5_MODE_SSID         0x78031022
+
+/**
+ * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
+ *    Define value for SSID while SATA controller set to AHCI mode.
+ */
+#define SATA_AHCI_SSID               0x78011022
+
+/**
+ * OHCI_SSID - All SB OHCI controllers SSID value.
+ *
+ */
+#define OHCI_SSID                    0x78071022
+
+/**
+ * EHCI_SSID - All SB EHCI controllers SSID value.
+ *
+ */
+#define EHCI_SSID                    0x78081022
+
+/**
+ * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
+ *
+ */
+#define OHCI4_SSID                   0x78091022
+
+/**
+ * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
+ *
+ */
+#define SMBUS_SSID                   0x780B1022
+
+/**
+ * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
+ *
+ */
+#define IDE_SSID                     0x780C1022
+
+/**
+ * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
+ *
+ */
+#define AZALIA_SSID                  0x780D1022
+
+/**
+ * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
+ *
+ */
+#define LPC_SSID                     0x780E1022
+
+/**
+ * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
+ *
+ */
+#define PCIB_SSID                    0x780F1022
+
diff --git a/src/vendorcode/amd/cimx/sb900/PciLib.c b/src/vendorcode/amd/cimx/sb900/PciLib.c
new file mode 100755
index 0000000..cba6701
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/PciLib.c
@@ -0,0 +1,83 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+VOID
+ReadPCI (
+  IN       UINT32 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+
+  if ( (UINT16)Address < 0xff ) {
+    //Normal Config Access
+    UINT32 AddrCf8;
+    AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
+    WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
+    ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
+  }
+}
+
+VOID
+WritePCI (
+  IN       UINT32 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+  if ( (UINT16)Address < 0xff ) {
+    //Normal Config Access
+    UINT32 AddrCf8;
+    AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
+    WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
+    WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
+  }
+}
+
+VOID
+RWPCI (
+  IN       UINT32 Address,
+  IN       UINT8 OpFlag,
+  IN       UINT32 Mask,
+  IN       UINT32 Data
+  )
+{
+  UINT32 Result;
+  Result = 0;
+  OpFlag = OpFlag & 0x7f;
+  ReadPCI (Address, OpFlag, &Result);
+  Result = (Result & Mask) | Data;
+  WritePCI (Address, OpFlag, &Result);
+}
diff --git a/src/vendorcode/amd/cimx/sb900/Pmio2Lib.c b/src/vendorcode/amd/cimx/sb900/Pmio2Lib.c
new file mode 100755
index 0000000..8c1a980
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Pmio2Lib.c
@@ -0,0 +1,127 @@
+/**
+ * @file
+ *
+ * Southbridge PMIO2 access common routine
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PMIO2
+ *
+ *
+ *
+ * @param[in] Address  - PMIO2 Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Read Data Buffer
+ *
+ */
+VOID
+ReadPMIO2 (
+  IN       UINT8 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  UINT8 i;
+  OpFlag = OpFlag & 0x7f;
+
+  if ( OpFlag == 0x02 ) {
+    OpFlag = 0x03;
+  }
+  for ( i = 0; i <= OpFlag; i++ ) {
+    WriteIO (0xCD0, AccWidthUint8, &Address);                   // SB_IOMAP_REGCD0
+    Address++;
+    ReadIO (0xCD1, AccWidthUint8, (UINT8 *) Value + i);         // SB_IOMAP_REGCD1
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PMIO 2
+ *
+ *
+ *
+ * @param[in] Address  - PMIO2 Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Write Data Buffer
+ *
+ */
+VOID
+WritePMIO2 (
+  IN       UINT8 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  UINT8 i;
+  OpFlag = OpFlag & 0x7f;
+
+  if ( OpFlag == 0x02 ) {
+    OpFlag = 0x03;
+  }
+  for ( i = 0; i <= OpFlag; i++ ) {
+    WriteIO (0xCD0, AccWidthUint8, &Address);                   // SB_IOMAP_REGCD0
+    Address++;
+    WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i);            // SB_IOMAP_REGCD1
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RWPMIO2 - Read/Write PMIO2
+ *
+ *
+ *
+ * @param[in] Address    - PMIO2 Offset value
+ * @param[in] OpFlag     - Access sizes
+ * @param[in] AndMask    - Data And Mask 32 bits
+ * @param[in] OrMask     - Data OR Mask 32 bits
+ *
+ */
+VOID
+RWPMIO2 (
+  IN       UINT8 Address,
+  IN       UINT8  OpFlag,
+  IN       UINT32 AndMask,
+  IN       UINT32 OrMask
+  )
+{
+  UINT32 Result;
+  OpFlag = OpFlag & 0x7f;
+  ReadPMIO2 (Address, OpFlag, &Result);
+  Result = (Result & AndMask) | OrMask;
+  WritePMIO2 (Address, OpFlag, &Result);
+}
diff --git a/src/vendorcode/amd/cimx/sb900/PmioLib.c b/src/vendorcode/amd/cimx/sb900/PmioLib.c
new file mode 100755
index 0000000..75b6fed
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/PmioLib.c
@@ -0,0 +1,126 @@
+/**
+ * @file
+ *
+ * Southbridge PMIO access common routine
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PMIO
+ *
+ *
+ *
+ * @param[in] Address  - PMIO Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Read Data Buffer
+ *
+ */
+VOID
+ReadPMIO (
+  IN       UINT8 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  UINT8 i;
+  OpFlag = OpFlag & 0x7f;
+
+  if ( OpFlag == 0x02 ) {
+    OpFlag = 0x03;
+  }
+  for ( i = 0; i <= OpFlag; i++ ) {
+    WriteIO (0xCD6, AccWidthUint8, &Address);                   // SB_IOMAP_REGCD6
+    Address++;
+    ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i);          // SB_IOMAP_REGCD7
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PMIO
+ *
+ *
+ *
+ * @param[in] Address  - PMIO Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Write Data Buffer
+ *
+ */
+VOID
+WritePMIO (
+  IN       UINT8 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  UINT8 i;
+  OpFlag = OpFlag & 0x7f;
+
+  if ( OpFlag == 0x02 ) {
+    OpFlag = 0x03;
+  }
+  for ( i = 0; i <= OpFlag; i++ ) {
+    WriteIO (0xCD6, AccWidthUint8, &Address);                   // SB_IOMAP_REGCD6
+    Address++;
+    WriteIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i);         // SB_IOMAP_REGCD7
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RWPMIO - Read/Write PMIO
+ *
+ *
+ *
+ * @param[in] Address    - PMIO Offset value
+ * @param[in] OpFlag     - Access sizes
+ * @param[in] AndMask    - Data And Mask 32 bits
+ * @param[in] OrMask     - Data OR Mask 32 bits
+ *
+ */
+VOID
+RWPMIO (
+  IN       UINT8 Address,
+  IN       UINT8   OpFlag,
+  IN       UINT32 AndMask,
+  IN       UINT32 OrMask
+  )
+{
+  UINT32 Result;
+  OpFlag = OpFlag & 0x7f;
+  ReadPMIO (Address, OpFlag, &Result);
+  Result = (Result & AndMask) | OrMask;
+  WritePMIO (Address, OpFlag, &Result);
+}
diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c
new file mode 100755
index 0000000..9a7cf53
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/Sata.c
@@ -0,0 +1,1042 @@
+
+/**
+ * @file
+ *
+ * Config Southbridge SATA controller
+ *
+ * Init SATA features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+****************************************************************************
+*/
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+//
+// Declaration of local functions
+//
+VOID  sataSetIrqIntResource (IN AMDSBCFG* pConfig);
+VOID  sataBar5setting (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
+#ifdef SATA_BUS_DEV_FUN_FPGA
+  VOID  sataBar5settingFpga (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
+#endif
+VOID  shutdownUnconnectedSataPortClock (IN AMDSBCFG* pConfig, IN UINT32 ddBar5);
+VOID  CaculateAhciPortNumber (IN AMDSBCFG* pConfig, IN UINT32 ddBar5);
+VOID  sataDriveDetection (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
+#ifdef SATA_BUS_DEV_FUN_FPGA
+  VOID  sataDriveDetectionFpga (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
+#endif
+VOID  sataGpioPorcedure (IN AMDSBCFG* pConfig);
+
+/**
+ * sataSetIrqIntResource - Config SATA IRQ/INT# resource
+ *
+ *
+ *   - Private function
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataSetIrqIntResource (
+  IN       AMDSBCFG*   pConfig
+  )
+{
+  UINT8   dbValue;
+  // IRQ14/IRQ15 come from IDE or SATA
+  dbValue = 0x08;
+  WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
+  ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+  dbValue = dbValue & 0x0F;
+  if (pConfig->SataClass == 3) {
+    dbValue = dbValue | 0x50;
+  } else {
+    if (pConfig->SataIdeMode == 1) {
+      // Both IDE & SATA set to Native mode
+      dbValue = dbValue | 0xF0;
+    }
+  }
+  WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+}
+
+/**
+ * sataBar5setting - Config SATA BAR5
+ *
+ *   - Private function
+ *
+ * @param[in] pConfig - Southbridge configuration structure pointer.
+ * @param[in] *pBar5   - SATA BAR5 buffer.
+ *
+ */
+VOID
+sataBar5setting (
+  IN       AMDSBCFG*   pConfig,
+  IN       UINT32      *pBar5
+  )
+{
+  //Get BAR5 value
+  ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
+  //Assign temporary BAR if is not already assigned
+  if ( (*pBar5 == 0) || (*pBar5 == - 1) ) {
+    //assign temporary BAR5
+    if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) {
+      *pBar5 = 0xFEC01000;
+    } else {
+      *pBar5 = pConfig->TempMMIO;
+    }
+    WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
+  }
+  //Clear Bits 9:0
+  *pBar5 = *pBar5 & 0xFFFFFC00;
+}
+#ifdef SATA_BUS_DEV_FUN_FPGA
+VOID
+sataBar5settingFpga (
+  IN       AMDSBCFG*   pConfig,
+  IN       UINT32      *pBar5
+  )
+{
+  UINT8  dbValue;
+  //Get BAR5 value
+  ReadPCI (((SATA_BUS_DEV_FUN_FPGA << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
+  //Assign temporary BAR if is not already assigned
+  if ( (*pBar5 == 0) || (*pBar5 == - 1) ) {
+    //assign temporary BAR5
+    if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) {
+      *pBar5 = 0xFEC01000;
+    } else {
+      *pBar5 = pConfig->TempMMIO;
+    }
+    WritePCI (((SATA_BUS_DEV_FUN_FPGA << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
+  }
+  //Clear Bits 9:0
+  *pBar5 = *pBar5 & 0xFFFFFC00;
+  dbValue = 0x07;
+  WritePCI (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x04), AccWidthUint8, &dbValue);
+  WritePCI (((PCIB_BUS_DEV_FUN << 16) + 0x04), AccWidthUint8, &dbValue);
+}
+#endif
+/**
+ * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock
+ *
+ *   - Private function
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ * @param[in] ddBar5 Sata BAR5 base address.
+ *
+ */
+VOID
+shutdownUnconnectedSataPortClock (
+  IN       AMDSBCFG* pConfig,
+  IN       UINT32 ddBar5
+  )
+{
+  UINT8  dbPortNum;
+  UINT32  ddPortSataStatus;
+  UINT8  cimSataClkAutoOff;
+
+  cimSataClkAutoOff = (UINT8) pConfig->SataClkAutoOff;
+#if  SB_CIMx_PARAMETER == 0
+  cimSataClkAutoOff = cimSataClkAutoOffDefault;
+#endif
+  if ( cimSataClkAutoOff == TRUE ) {
+    //ENH225976 Enable SATA auto clock control by default ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) {
+    for ( dbPortNum = 0; dbPortNum < 8; dbPortNum++ ) {
+      ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint32, &ddPortSataStatus);
+      // Shutdown the clock for the port and do the necessary port reporting changes.
+      // ?? Error port status should be 1 not 3
+      ddPortSataStatus &= 0x00000F0F;
+      if ( (!((ddPortSataStatus == 0x601) || (ddPortSataStatus == 0x201) || (ddPortSataStatus == 0x103))) && (! ((pConfig->SATAESPPORT.SataPortReg) & (1 << dbPortNum))) ) {
+        TRACE ((DMSG_SB_TRACE, "Shutting down clock for SATA port %X \n", dbPortNum));
+        RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, (1 << dbPortNum));
+      }
+    }     //end of for (dbPortNum=0;dbPortNum<6;dbPortNum++)
+  }  //end of SataClkAuto Off option
+}
+
+/**
+ * CaculateAhciPortNumber - Caculat AHCI Port Number
+ *
+ *   - Private function
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ * @param[in] ddBar5 Sata BAR5 base address.
+ *
+ */
+VOID
+CaculateAhciPortNumber (
+  IN       AMDSBCFG* pConfig,
+  IN       UINT32 ddBar5
+  )
+{
+  UINT8  dbPortNum;
+  UINT8  dbPortSataStatus;
+  UINT8  NumOfPorts;
+  UINT8  MaxPortNum;
+  NumOfPorts = 0;
+  MaxPortNum = 4;
+  if ( (pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt) == ENABLED ) {
+    MaxPortNum = 6;
+  } else if ( (pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == ENABLED ) {
+    MaxPortNum = 8;
+  }
+  ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, &dbPortSataStatus);
+  for ( dbPortNum = 0; dbPortNum < MaxPortNum; dbPortNum++ ) {
+    if ( dbPortSataStatus & (1 << dbPortNum) ) {
+      RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(1 << dbPortNum), 00);
+    }
+  }
+  ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
+  //if all ports are in disabled state, report atleast one port
+  if ( (dbPortSataStatus & 0xFF) == 0) {
+    RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, (UINT32) ~(0xFF), 01);
+  }
+  ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
+  for (dbPortNum = 0; dbPortNum < MaxPortNum; dbPortNum ++) {
+    if (dbPortSataStatus & (1 << dbPortNum)) {
+      NumOfPorts++;
+    }
+  }
+  if ( NumOfPorts == 0) {
+    NumOfPorts = 0x01;
+  }
+  RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1);
+}
+
+/**
+ * sataGpioPorcedure - Sata GPIO function Procedure
+ *
+ *   - Private function
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataGpioPorcedure (
+  IN  AMDSBCFG* pConfig
+  )
+{
+  UINT32  ddBar5;
+  UINT32  ddData;
+  UINT32  eMb;
+  UINT32  ddTempVariable;
+  UINT8  cimSataSgpio0;
+
+  ddBar5 = 0;
+  eMb = 0;
+  cimSataSgpio0 = (UINT8) pConfig->SataSgpio0;
+
+#if  SB_CIMx_PARAMETER == 0
+  cimSataSgpio0 = cimSataSgpio0Default;
+#endif
+
+  sataBar5setting (pConfig, &ddBar5);
+  ReadMEM (ddBar5 + SB_SATA_BAR5_REG1C , AccWidthUint32 | S3_SAVE, &ddData);
+  eMb = (ddBar5 + (( ddData & 0xFFFF0000) >> 14));
+  if ( eMb ) {
+    ddTempVariable = 0x03040C00;
+    WriteMEM ( ddBar5 + eMb, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+    ddTempVariable = 0x00C08240;
+    WriteMEM ( ddBar5 + eMb + 4, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+    ddTempVariable = 0x00000001;
+    WriteMEM ( ddBar5 + eMb + 8, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+    if ( cimSataSgpio0 ) {
+      ddTempVariable = 0x00000060;
+    } else {
+      ddTempVariable = 0x00000061;
+    }
+    WriteMEM ( ddBar5 + eMb + 0x0C, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+
+    RWMEM ((ddBar5 + SB_SATA_BAR5_REG20), AccWidthUint16 | S3_SAVE, ~(BIT8), BIT8);
+    do {
+      ReadMEM (ddBar5 + SB_SATA_BAR5_REG20 , AccWidthUint32 | S3_SAVE, &ddData);
+      ddData = ddData & BIT8;
+    } while ( ddData != 0 );
+
+    ddTempVariable = 0x03040F00;
+    WriteMEM ( ddBar5 + eMb, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+    ddTempVariable = 0x00008240;
+    WriteMEM ( ddBar5 + eMb + 4, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+    ddTempVariable = 0x00000002;
+    WriteMEM ( ddBar5 + eMb + 8, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+    ddTempVariable = 0x00800000;
+    WriteMEM ( ddBar5 + eMb + 0x0C, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+    ddTempVariable = 0x0F003700;
+    WriteMEM ( ddBar5 + eMb + 0x0C, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+    RWMEM ((ddBar5 + SB_SATA_BAR5_REG20), AccWidthUint16 | S3_SAVE, ~(BIT8), BIT8);
+    do {
+      ReadMEM (ddBar5 + SB_SATA_BAR5_REG20 , AccWidthUint32 | S3_SAVE, &ddData);
+      ddData = ddData & BIT8;
+    } while ( ddData != 0 );
+  }
+}
+
+
+/**
+ * Table for class code of SATA Controller in different modes
+ *
+ *
+ *
+ *
+ */
+UINT32 sataIfCodeTable[] =
+{
+  0x01018F40, //sata class ID of IDE
+  0x01040040, //sata class ID of RAID
+  0x01060140, //sata class ID of AHCI
+  0x01018A40, //sata class ID of Legacy IDE
+  0x01018F40, //sata class ID of IDE to AHCI mode
+};
+
+/**
+ * Table for device id of SATA Controller in different modes
+ *
+ *
+ *
+ *
+ */
+
+UINT16 sataDeviceIDTable[] =
+{
+  SB_SATA_DID,  //sata device ID of IDE
+  SB_SATA_RAID_DID,  //sata device ID of RAID
+  SB_SATA_AHCI_DID,  //sata class ID of AHCI
+  SB_SATA_DID,  //sata device ID of Legacy IDE
+  SB_SATA_DID,  //sata device ID of IDE->AHCI mode
+};
+
+/**
+ * Table for Sata Phy Fine Setting
+ *
+ *
+ *
+ *
+ */
+SATAPHYSETTING sataPhyTable[] =
+{
+  //Gen3
+  {0x0030, 0x0057A607},
+  {0x0031, 0x0057A607},
+  {0x0032, 0x0057A407},
+  {0x0033, 0x0057A407},
+  {0x0034, 0x0057A607},
+  {0x0035, 0x0057A607},
+  {0x0036, 0x0057A403},
+  {0x0037, 0x0057A403},
+
+  //Gen2
+  {0x0120, 0x00071302},
+
+  //Gen1
+  {0x0110, 0x00174101}
+};
+
+/**
+ * sataInitBeforePciEnum - Config SATA controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataInitBeforePciEnum (
+  IN       AMDSBCFG*   pConfig
+  )
+{
+  UINT32  ddTempVar;
+  UINT32  ddValue;
+  UINT32  *tempptr;
+  UINT16  *pDeviceIdptr;
+  UINT32  dwDeviceId;
+  UINT8   dbValue;
+  UINT8   pValue;
+  UINT8   dbChannel;
+  UINT16    i;
+  SATAPHYSETTING  *pPhyTable;
+
+  pConfig->SATAPORTPOWER.SataPortPowerReg = \
+    + pConfig->SATAPORTPOWER.SataPortPower.PORT0 \
+    + (pConfig->SATAPORTPOWER.SataPortPower.PORT1 << 1) \
+    + (pConfig->SATAPORTPOWER.SataPortPower.PORT2 << 2) \
+    + (pConfig->SATAPORTPOWER.SataPortPower.PORT3 << 3) \
+    + (pConfig->SATAPORTPOWER.SataPortPower.PORT4 << 4) \
+    + (pConfig->SATAPORTPOWER.SataPortPower.PORT5 << 5) \
+    + (pConfig->SATAPORTPOWER.SataPortPower.PORT6 << 6) \
+    + (pConfig->SATAPORTPOWER.SataPortPower.PORT7 << 7);
+  // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h
+  // BIT4:disable fast boot //?
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT4);
+  // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting IDE PCI register 40h
+  RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
+  // RPR Enable IDE DMA read enhancement
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48 + 3), AccWidthUint8 | S3_SAVE, 0xff, BIT7);
+  // RPR Unused SATA Ports Disabled
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0, pConfig->SATAPORTPOWER.SataPortPowerReg);
+  dbValue = (UINT8)pConfig->SataClass;
+  if (dbValue == AHCI_MODE_7804) {
+    dbValue = AHCI_MODE;
+  }
+  if (dbValue == IDE_TO_AHCI_MODE_7804) {
+    dbValue = IDE_TO_AHCI_MODE;
+  }
+  // Disable PATA MSI
+  RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG34), AccWidthUint8 | S3_SAVE, 0x00, 0x00);
+  RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG06), AccWidthUint8 | S3_SAVE, 0xEF, 0x00);
+
+  if ( (pConfig->SataClass == 3) | (pConfig->SataClass == 0)) {
+    dbChannel = 0x00;
+    ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48 + 3), AccWidthUint8, &dbChannel);
+    dbChannel &= 0xCF;
+    if ( pConfig->SataDisUnusedIdePChannel ) {
+      dbChannel |= 0x10;
+    }
+    if ( pConfig->SataDisUnusedIdeSChannel ) {
+      dbChannel |= 0x20;
+    }
+    WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48 + 3), AccWidthUint8, &dbChannel);
+  }
+
+  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED ) {
+    ReadPCI (((IDE_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 11), AccWidthUint8, &dbChannel);
+    dbChannel &= 0xCF;
+    if ( pConfig->IdeDisUnusedIdePChannel ) {
+      dbChannel |= 0x10;
+    }
+    if ( pConfig->IdeDisUnusedIdeSChannel ) {
+      dbChannel |= 0x20;
+    }
+    WritePCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40 + 11), AccWidthUint8, &dbChannel);
+  }
+  // Get the appropriate class code from the table and write it to PCI register 08h-0Bh
+  // Set the appropriate SATA class based on the input parameters
+  // SATA IDE Controller Class ID & SSID
+  tempptr = (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]);
+  if ( (pConfig->SataIdeMode == 1) && (pConfig->SataClass != 3) ) {
+    ddValue = tempptr[0];
+    // Write the class code to IDE PCI register 08h-0Bh
+    RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
+  }
+  ddValue = tempptr[dbValue];
+  // Write the class code to SATA PCI register 08h-0Bh
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
+  if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
+    //Set PATA controller to native mode
+    RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
+  }
+  if (pConfig->BuildParameters.IdeSsid != NULL ) {
+    RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
+  }
+  // SATA Controller Class ID & SSID
+  pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
+  ddTempVar = pConfig->BuildParameters.SataIDESsid;
+  dwDeviceId = pDeviceIdptr[dbValue];
+  if ( pConfig->SataClass == RAID_MODE) {
+    ddTempVar = pConfig->BuildParameters.SataRAID5Ssid;
+    dwDeviceId = SB_SATA_RAID5_DID;
+    pValue = SATA_EFUSE_LOCATION;
+    getEfuseStatus (&pValue);
+    if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) {
+      dwDeviceId = SB_SATA_RAID_DID;
+      ddTempVar = pConfig->BuildParameters.SataRAIDSsid;
+    }
+  }
+  if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||
+    ((pConfig->SataClass) == AHCI_MODE_7804) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_7804) ) {
+    ddTempVar = pConfig->BuildParameters.SataAHCISsid;
+  }
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
+  RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
+
+  // SATA IRQ Resource
+  sataSetIrqIntResource (pConfig);
+
+  // RPR 9.5 SATA PHY Programming Sequence
+  pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]);
+  for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) {
+    RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80, AccWidthUint16 | S3_SAVE, 0x00, pPhyTable->wPhyCoreControl);
+    RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune);
+    ++pPhyTable;
+  }
+  RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80, AccWidthUint16 | S3_SAVE, 0x00, 0x110);
+  RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG9C, AccWidthUint32 | S3_SAVE, (UINT32) (~(0x7 << 4)), (UINT32) (0x2 << 4));
+  RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80, AccWidthUint16 | S3_SAVE, 0x00, 0x10);
+
+  RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
+  // Disable write access to PCI header
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
+  if ( IsSbA12Plus () ) {
+    //SATA PCI Config 0x4C[31:26] program 111111b (six 1's)
+    //SATA PCI Config 0x48[11] program 1
+    //SATA PCI Config 0x84[31] program 0
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG4C), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x3f << 26)), (UINT32) (0x3f << 26));
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11));
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31));
+  }
+
+  //SATA PCI config register 0x4C [20] =1
+  //SATA PCI config register 0x4C [21] =1
+  //SATA PCI config register 0x4C [18] =1
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG4C), AccWidthUint32 | S3_SAVE, ~ (BIT18 + BIT20 + BIT21), (BIT18 + BIT20 + BIT21));
+}
+
+/**
+ * sataInitAfterPciEnum - Config SATA controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataInitAfterPciEnum (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32  ddAndMask;
+  UINT32  ddOrMask;
+  UINT32  ddBar5;
+  UINT8  dbVar;
+  UINT8  dbPortNum;
+  UINT8  dbEfuse;
+  UINT8  dbPortMode;
+  UINT16  SataPortMode;
+  UINT8  cimSataAggrLinkPmCap;
+  UINT8  cimSataPortMultCap;
+  UINT8  cimSataPscCap;
+  UINT8  cimSataSscCap;
+  UINT8  cimSataFisBasedSwitching;
+  UINT8  cimSataCccSupport;
+  UINT8  cimSataMsiCapability;
+  UINT8  cimSataTargetSupport8Device;
+  UINT8  cimSataDisableGenericMode;
+  UINT8  cimSataAhciEnclosureManagement;
+  UINT8  cimSataSgpio0;
+  UINT8  cimSataSgpio1;
+  UINT8  cimSataHotRemovelEnh;
+  UINT8  cimSataPhyPllShutDown;
+  UINT8  dbCccInt;
+
+  cimSataAggrLinkPmCap = (UINT8) pConfig->SataAggrLinkPmCap;
+  cimSataPortMultCap = (UINT8) pConfig->SataPortMultCap;
+  cimSataPscCap = (UINT8) pConfig->SataPscCap;
+  cimSataSscCap = (UINT8) pConfig->SataSscCap;
+  cimSataFisBasedSwitching = (UINT8) pConfig->SataFisBasedSwitching;
+  cimSataCccSupport = (UINT8) pConfig->SataCccSupport;
+  cimSataMsiCapability = (UINT8) pConfig->SataMsiCapability;
+  cimSataTargetSupport8Device = (UINT8) pConfig->SataTargetSupport8Device;
+  cimSataDisableGenericMode = (UINT8) pConfig->SataDisableGenericMode;
+  cimSataAhciEnclosureManagement = (UINT8) pConfig->SataAhciEnclosureManagement;
+  cimSataSgpio0 = (UINT8) pConfig->SataSgpio0;
+  cimSataSgpio1 = (UINT8) pConfig->SataSgpio1;
+  cimSataHotRemovelEnh = (UINT8) pConfig->SataHotRemoveEnh;
+  cimSataPhyPllShutDown = (UINT8) pConfig->SataPhyPllShutDown;
+
+#if  SB_CIMx_PARAMETER == 0
+  cimSataAggrLinkPmCap = cimSataAggrLinkPmCapDefault;
+  cimSataPortMultCap = cimSataPortMultCapDefault;
+  cimSataPscCap = cimSataPscCapDefault;
+  cimSataSscCap = cimSataSscCapDefault;
+  cimSataFisBasedSwitching = cimSataFisBasedSwitchingDefault;
+  cimSataCccSupport = cimSataCccSupportDefault;
+  cimSataMsiCapability = cimSataMsiCapabilityDefault;
+  cimSataTargetSupport8Device = cimSataTargetSupport8DeviceDefault;
+  cimSataDisableGenericMode = cimSataDisableGenericModeDefault;
+  cimSataAhciEnclosureManagement = cimSataAhciEnclosureManagementDefault;
+  cimSataSgpio0 = cimSataSgpio0Default;
+  cimSataSgpio1 = cimSataSgpio1Default;
+  cimSataHotRemovelEnh = cimSataHotRemoveEnhDefault;
+  cimSataPhyPllShutDown = cimSataPhyPllShutDownDefault;
+#endif
+
+  ddAndMask = 0;
+  ddOrMask = 0;
+  ddBar5 = 0;
+  if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {
+    return;   //return if SATA controller is disabled.
+  }
+
+  //Enable write access to pci header, pm capabilities
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+
+  sataBar5setting (pConfig, &ddBar5);
+
+  ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);   //memory and io access enable
+  dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
+  getEfuseStatus (&dbEfuse);
+
+  if ( !cimSataPortMultCap ) {
+    ddAndMask |= BIT12;
+  }
+  if ( cimSataAggrLinkPmCap ) {
+    ddOrMask |= BIT11;
+  } else {
+    ddAndMask |= BIT11;
+  }
+  if ( cimSataPscCap ) {
+    ddOrMask |= BIT1;
+  } else {
+    ddAndMask |= BIT1;
+  }
+  if ( cimSataSscCap ) {
+    ddOrMask |= BIT26;
+  } else {
+    ddAndMask |= BIT26;
+  }
+  if ( cimSataFisBasedSwitching ) {
+    if (dbEfuse & BIT1) {
+      ddAndMask |= BIT10;
+    } else {
+      ddOrMask |= BIT10;
+    }
+  } else {
+    ddAndMask |= BIT10;
+  }
+  // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
+  if ( cimSataCccSupport ) {
+    ddOrMask |= BIT19;
+  } else {
+    ddAndMask |= BIT19;
+  }
+  if ( cimSataAhciEnclosureManagement ) {
+    ddOrMask |= BIT27;
+  } else {
+    ddAndMask |= BIT27;
+  }
+  RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);
+
+
+  // SATA ESP port setting
+  // These config bits are set for SATA driver to identify which ports are external SATA ports and need to
+  // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
+  // not enable power management (HIPM & DIPM) for these ports.
+  pConfig->SATAESPPORT.SataPortReg = \
+    + pConfig->SATAESPPORT.SataEspPort.PORT0 \
+    + (pConfig->SATAESPPORT.SataEspPort.PORT1 << 1) \
+    + (pConfig->SATAESPPORT.SataEspPort.PORT2 << 2) \
+    + (pConfig->SATAESPPORT.SataEspPort.PORT3 << 3) \
+    + (pConfig->SATAESPPORT.SataEspPort.PORT4 << 4) \
+    + (pConfig->SATAESPPORT.SataEspPort.PORT5 << 5) \
+    + (pConfig->SATAESPPORT.SataEspPort.PORT6 << 6) \
+    + (pConfig->SATAESPPORT.SataEspPort.PORT7 << 7);
+  if ( pConfig->SATAESPPORT.SataPortReg != 0 ) {
+    RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(pConfig->SATAESPPORT.SataPortReg), 0);
+    RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, 0xFF00FF00, (pConfig->SATAESPPORT.SataPortReg << 16));
+    // RPR 8.7 External SATA Port Indication Registers
+    // If any of the ports was programmed as an external port, HCAP.SXS should also be set
+    RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), BIT20);
+  } else {
+    // RPR 8.7 External SATA Port Indication Registers
+    // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port)
+    RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, 0xFF00FF00, 0x00);
+    RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), 0x00);
+  }
+
+  if ( cimSataFisBasedSwitching ) {
+    if (dbEfuse & BIT1) {
+      RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, 0x00FFFFFF, 0x00);
+    } else {
+      RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, 0x00FFFFFF, 0xFF000000);
+    }
+  } else {
+    RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, 0x00FFFFFF, 0x00);
+  }
+
+  //SB02712 Turn off MSI for SATA IDE mode.
+  if ((pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE)) {
+    cimSataMsiCapability = 0;
+  }
+  //Enabled SATA MSI capability
+  // RPR 8.11 SATA MSI and D3 Power State Capability
+  if (IsSbA12Plus ()) {
+    if ( cimSataMsiCapability ) {
+      RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x50);
+    } else {
+      RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70);
+    }
+  } else {
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70);
+  }
+
+  if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
+    // RIAD or AHCI
+    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {
+      // IDE2 Controller is enabled
+      if ((pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt) == ENABLED) {
+        // 6 AHCI mode
+        RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0x00, 0x3F);
+        RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
+        RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
+        RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint8, 0x07, 0x30);
+      } else {
+        RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0x00, 0x0F);
+        if ( pConfig->SataCccSupport ) {
+          RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
+        } else {
+          RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2);
+        }
+      }
+    } else {
+      // IDE2 Controller is disabled
+      RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT1 + BIT0);
+      RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0x00, 0xFF);
+      if ( pConfig->SataCccSupport ) {
+        RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT3);
+      } else {
+        RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
+      }
+    }
+  }
+  if ( pConfig->BIOSOSHandoff == 1 ) {
+    RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, BIT0);
+  } else {
+    RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);
+  }
+  pConfig->SATAPORTMODE.SataPortMode = \
+    pConfig->SATAPORTMODE.SataPortMd.PORT0 \
+    + (pConfig->SATAPORTMODE.SataPortMd.PORT1 << 2) \
+    + (pConfig->SATAPORTMODE.SataPortMd.PORT2 << 4) \
+    + (pConfig->SATAPORTMODE.SataPortMd.PORT3 << 6) \
+    + (pConfig->SATAPORTMODE.SataPortMd.PORT4 << 8) \
+    + (pConfig->SATAPORTMODE.SataPortMd.PORT5 << 10) \
+    + (pConfig->SATAPORTMODE.SataPortMd.PORT6 << 12) \
+    + (pConfig->SATAPORTMODE.SataPortMd.PORT7 << 14);
+  SataPortMode = (UINT16)pConfig->SATAPORTMODE.SataPortMode;
+  dbPortNum = 0;
+
+  while ( dbPortNum < 8 ) {
+    dbPortMode = (UINT8) (SataPortMode & 3);
+    if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {
+      if ( dbPortMode == BIT0 ) {
+        // set GEN 1
+        RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);
+      }
+      if ( dbPortMode == BIT1 ) {
+        // set GEN2 (default is GEN3)
+        RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x20);
+      }
+      RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
+      cimSbStall (1000);
+      RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
+    }
+    SataPortMode >>= 2;
+    dbPortNum ++;
+  }
+  SbStall (1000);
+  SataPortMode = (UINT16)pConfig->SATAPORTMODE.SataPortMode;
+  dbPortNum = 0;
+
+  while ( dbPortNum < 8 ) {
+    dbPortMode = (UINT8) (SataPortMode & 3);
+    if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {
+      RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
+    }
+    dbPortNum ++;
+    SataPortMode >>= 2;
+  }
+
+  if ( cimSataTargetSupport8Device ) {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint16, ~BIT12, BIT12);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint16, ~BIT12, 0x00);
+  }
+
+  if ( cimSataDisableGenericMode ) {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint16, ~BIT13, BIT13);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint16, ~BIT13, 0x00);
+  }
+  // 9.19 Optionally Disable Hot-removal Detection Enhancement
+  if ( cimSataHotRemovelEnh ) {
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80), AccWidthUint16 | S3_SAVE, ~BIT8, BIT8 );
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA8), AccWidthUint16 | S3_SAVE, ~BIT0, BIT0);
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80), AccWidthUint16 | S3_SAVE, ~BIT8, 0 );
+  }
+  if ( cimSataSgpio0 ) {
+    sataGpioPorcedure (pConfig);
+  }
+  if ( cimSataSgpio1 ) {
+    sataGpioPorcedure (pConfig);
+  }
+  if ( IsSbA11 () ) {
+    if ( cimSataPhyPllShutDown ) {
+      RWPCI (((SATA_BUS_DEV_FUN << 16) + 0x87), AccWidthUint8 | S3_SAVE, ~(BIT6 + BIT7), BIT6 + BIT7);
+    } else {
+      RWPCI (((SATA_BUS_DEV_FUN << 16) + 0x87), AccWidthUint8 | S3_SAVE, ~(BIT6 + BIT7), 0x00);
+    }
+  } else {
+    if ( cimSataPhyPllShutDown ) {
+      RWPCI (((SATA_BUS_DEV_FUN << 16) + 0x87), AccWidthUint8 | S3_SAVE, ~(BIT6), BIT6);
+    } else {
+      RWPCI (((SATA_BUS_DEV_FUN << 16) + 0x87), AccWidthUint8 | S3_SAVE, ~(BIT6), 0x00);
+    }
+  }
+  if ( IsSbA12Plus () ) {
+    //SATA PCI Config 0x4C[31:26] program 111111b (six 1's)
+    //SATA PCI Config 0x48[11] program 1
+    //SATA PCI Config 0x84[31] program 0
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG4C), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x3f << 26)), (UINT32) (0x3f << 26));
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11));
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31));
+  }
+  // RPR 9.18 CCC Interrupt
+  dbCccInt = 4;
+  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {
+    if ((pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt) == ENABLED) {
+      dbCccInt = 6;
+    }
+  } else {
+    dbCccInt = 8;
+  }
+  RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint8, 0x07, (dbCccInt << 3));
+
+  shutdownUnconnectedSataPortClock (pConfig, ddBar5);
+
+  WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+
+  // RPR 9.13 Disable SATA FLR Capability
+  // SATA_PCI_config 0x70 [15:8] = 0x00
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG70), AccWidthUint32 | S3_SAVE, 0xFFFF00FF, 0x00);
+  //Disable write access to pci header, pm capabilities
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
+}
+
+
+/**
+ * sataInitMidPost - Config SATA controller in Middle POST.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataInitMidPost (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32   ddBar5;
+  sataBar5setting (pConfig, &ddBar5);
+  //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround.
+  if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE)  && ((pConfig->SataClass) != RAID_MODE) ) ) {
+    sataDriveDetection (pConfig, &ddBar5);
+  }
+#ifdef SATA_BUS_DEV_FUN_FPGA
+  sataBar5settingFpga (pConfig, &ddBar5);
+  sataDriveDetectionFpga (pConfig, &ddBar5);
+#endif
+}
+
+/**
+ * sataDriveDetection - Sata drive detection
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ * @param[in] *pBar5 Sata BAR5 base address.
+ *
+ */
+VOID
+sataDriveDetection (
+  IN       AMDSBCFG* pConfig,
+  IN       UINT32 *pBar5
+  )
+{
+  UINT32   ddVar0;
+  UINT8   dbPortNum;
+  UINT8   dbVar0;
+  UINT16   dwIoBase;
+  UINT32   ddVar1;
+  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
+  TRACE ((DMSG_SB_TRACE, "SATA BAR5 is %X \n", *pBar5));
+  if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) {
+    for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) {
+      ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
+      if ( ( ddVar0 & 0x0F ) == 0x03 ) {
+        if ( dbPortNum & BIT0 ) {
+          //this port belongs to secondary channel
+          ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
+        } else {
+          //this port belongs to primary channel
+          ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
+        }
+        //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
+        if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
+          dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) );
+        }
+        if ( dbPortNum & BIT1 ) {
+          //this port is slave
+          dbVar0 = 0xB0;
+        } else {
+          //this port is master
+          dbVar0 = 0xA0;
+        }
+        dwIoBase &= 0xFFF8;
+        WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0);
+        //Wait in loop for 30s for the drive to become ready
+        for ( ddVar1 = 0; ddVar1 < 300000; ddVar1++ ) {
+          ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0);
+          if ( (dbVar0 & 0x88) == 0 ) {
+            break;
+          }
+          SbStall (100);
+        }
+      } //end of if ( ( ddVar0 & 0x0F ) == 0x03)
+    } //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++)
+  } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE))
+}
+
+#ifdef SATA_BUS_DEV_FUN_FPGA
+VOID
+sataDriveDetectionFpga (
+  IN       AMDSBCFG* pConfig,
+  IN       UINT32 *pBar5
+  )
+{
+  UINT32   ddVar0;
+  UINT8   dbPortNum;
+  UINT8   dbVar0;
+  UINT16   dwIoBase;
+  UINT32   ddVar1;
+  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
+  TRACE ((DMSG_SB_TRACE, "SATA BAR5 is %X \n", *pBar5));
+  for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) {
+    ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
+    if ( ( ddVar0 & 0x0F ) == 0x03 ) {
+      if ( dbPortNum & BIT0 ) {
+        //this port belongs to secondary channel
+        ReadPCI (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
+      } else {
+        //this port belongs to primary channel
+        ReadPCI (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
+      }
+      //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
+      if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
+        dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) );
+      }
+      if ( dbPortNum & BIT1 ) {
+        //this port is slave
+        dbVar0 = 0xB0;
+      } else {
+        //this port is master
+        dbVar0 = 0xA0;
+      }
+      dwIoBase &= 0xFFF8;
+      WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0);
+      //Wait in loop for 30s for the drive to become ready
+      for ( ddVar1 = 0; ddVar1 < 300000; ddVar1++ ) {
+        ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0);
+        if ( (dbVar0 & 0x88) == 0 ) {
+          break;
+        }
+        SbStall (100);
+      }
+    } //end of if ( ( ddVar0 & 0x0F ) == 0x03)
+  } //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++)
+}
+#endif
+
+/**
+ * sataInitLatePost - Prepare SATA controller to boot to OS.
+ *
+ *              - Set class ID to AHCI (if set to AHCI * Mode)
+ *              - Enable AHCI interrupt
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataInitLatePost (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32  ddBar5;
+  UINT8  dbVar;
+  UINT8  dbPortNum;
+
+  //Return immediately is sata controller is not enabled
+  if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {
+    return;
+  }
+  //Enable write access to pci header, pm capabilities
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
+
+  sataBar5setting (pConfig, &ddBar5);
+
+  ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+  //Enable memory and io access
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);
+
+  if (( pConfig->SataClass == IDE_TO_AHCI_MODE) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_7804 )) {
+    //program the AHCI class code
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100);
+    //Set interrupt enable bit
+    RWMEM ((ddBar5 + 0x04), AccWidthUint8, (UINT32)~0, BIT1);
+    //program the correct device id for AHCI mode
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, SB_SATA_AHCI_DID);
+  }
+
+  if (( pConfig->SataClass == AHCI_MODE_7804 ) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_7804 )) {
+    //program the correct device id for AHCI 7804 mode
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, SB_SATA_AMDAHCI_DID);
+  }
+  // OBS236459 IDE controller not shown in device manager when Os installed on IDE mode port
+  //if ( pConfig->SataClass == IDE_TO_AHCI_MODE_7804 ) {
+    //Disable IDE2 and Enable 8 channel for IDE-AHCI mode
+    //RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, ~BIT1, BIT3);
+  //}
+
+  //Clear error status
+  RWMEM ((ddBar5 + SB_SATA_BAR5_REG130), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+  RWMEM ((ddBar5 + SB_SATA_BAR5_REG1B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+  RWMEM ((ddBar5 + SB_SATA_BAR5_REG230), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+  RWMEM ((ddBar5 + SB_SATA_BAR5_REG2B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+  RWMEM ((ddBar5 + SB_SATA_BAR5_REG330), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+  RWMEM ((ddBar5 + SB_SATA_BAR5_REG3B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+  RWMEM ((ddBar5 + SB_SATA_BAR5_REG430), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+  RWMEM ((ddBar5 + SB_SATA_BAR5_REG4B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+  CaculateAhciPortNumber (pConfig, ddBar5);
+  //Restore memory and io access bits
+  WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar );
+  //Disable write access to pci header and pm capabilities
+  RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
+  for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) {
+    RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00);
+  }
+}
+
+
diff --git a/src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h b/src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h
new file mode 100755
index 0000000..1447e9c
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h
@@ -0,0 +1,53 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#ifndef _BIOS_RAM_USAGE_H_
+#define _BIOS_RAM_USAGE_H_
+
+#define RESTORE_MEMORY_CONTROLLER_START 0
+#define XHCI_REGISTER_BAR00           0xD0
+#define XHCI_REGISTER_BAR01           0xD1
+#define XHCI_REGISTER_BAR02           0xD2
+#define XHCI_REGISTER_BAR03           0xD3
+#define XHCI_REGISTER_04H             0xD4
+#define XHCI_REGISTER_0CH             0xD5
+#define XHCI_REGISTER_3CH             0xD6
+#define XHCI1_REGISTER_BAR00          0xE0
+#define XHCI1_REGISTER_BAR01          0xE1
+#define XHCI1_REGISTER_BAR02          0xE2
+#define XHCI1_REGISTER_BAR03          0xE3
+#define XHCI1_REGISTER_04H            0xE4
+#define XHCI1_REGISTER_0CH            0xE5
+#define XHCI1_REGISTER_3CH            0xE6
+#define RTC_WORKAROUND_DATA_START     0xF0
+#define BOOT_TIME_FLAG_SEC            0xF8
+#define BOOT_TIME_FLAG_INT19          0xFC
+
+#endif
+
diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c
new file mode 100755
index 0000000..29f6fd1
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c
@@ -0,0 +1,1544 @@
+/**
+ * @file
+ *
+ * Southbridge Initial routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+//
+// Declaration of local functions
+//
+
+VOID abcfgTbl (IN ABTBLENTRY* pABTbl);
+VOID A13ResumeResetTwoSecondRtcWakeup (void);
+
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page LegacyInterfaceCalls  Legacy Interface Calls
+ *  <TD>@subpage SB_POWERON_INIT_Page "SB_POWERON_INIT"</TD><TD></TD>
+ *  <TD>@subpage SB_BEFORE_PCI_INIT_Page "SB_BEFORE_PCI_INIT"</TD><TD></TD>
+ *  <TD>@subpage SB_AFTER_PCI_INIT_Page "SB_AFTER_PCI_INIT"</TD><TD></TD>
+ *  <TD>@subpage SB_LATE_POST_INIT_Page "SB_LATE_POST_INIT"</TD><TD></TD>
+ *  <TD>@subpage SB_BEFORE_PCI_RESTORE_INIT_Page "SB_BEFORE_PCI_RESTORE_INIT"</TD><TD></TD>
+ *  <TD>@subpage SB_AFTER_PCI_RESTORE_INIT_Page "SB_AFTER_PCI_RESTORE_INIT"</TD><TD></TD>
+ *  <TD>@subpage SB_SMM_SERVICE_Page "SB_SMM_SERVICE"</TD><TD></TD>
+ *  <TD>@subpage SB_SMM_ACPION_Page "SB_SMM_ACPION"</TD><TD></TD>
+ *
+ *  @page LegacyInterfaceCallOuts  Legacy Interface CallOuts
+ *  <TD>@subpage CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
+ *  <TD>@subpage CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
+ *
+*/
+
+/**
+ * sbEarlyPostByteInitTable - PCI device registers initial during early POST.
+ *
+ */
+REG8MASK sbEarlyPostByteInitTable[] =
+{
+  // SMBUS Device (Bus 0, Dev 20, Func 0)
+  {0x00, SMBUS_BUS_DEV_FUN, 0},
+  {SB_CFG_REG10, 0X00, (SBCIMx_Version & 0xFF)}, //Program the version information
+  {SB_CFG_REG11, 0X00, (SBCIMx_Version >> 8)},
+  {0xFF, 0xFF, 0xFF},
+
+  // IDE Device (Bus 0, Dev 20, Func 1)
+  {0x00, IDE_BUS_DEV_FUN, 0},
+  {SB_IDE_REG62 + 1, ~BIT0, BIT5},  // Enabling IDE Explicit Pre-Fetch  IDE PCI Config 0x62[8]=0
+  // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1
+  {0xFF, 0xFF, 0xFF},
+
+  // Azalia Device (Bus 0, Dev 20, Func 2)
+  {0x00, AZALIA_BUS_DEV_FUN, 0},
+  {SB_AZ_REG4C, ~BIT0, BIT0},
+  {0xFF, 0xFF, 0xFF},
+
+  // LPC Device (Bus 0, Dev 20, Func 3)
+  {0x00, LPC_BUS_DEV_FUN, 0},
+  {SB_LPC_REG40, ~BIT2, BIT2},                          // RPR Enabling LPC DMA Function  0x40[2]=1b 0x78[0]=0b
+  {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
+  {SB_LPC_REG78, 0xFC, 00},                             // RPR Enabling LPC DMA Function  0x40[2]=1b 0x78[0]=0b / Disables MSI capability
+  {SB_LPC_REGBB, ~BIT0, BIT0 + BIT3 + BIT4 + BIT5},     // Enabled SPI Prefetch from HOST.
+  {0xFF, 0xFF, 0xFF},
+
+  // PCIB Bridge (Bus 0, Dev 20, Func 4)
+  {0x00, PCIB_BUS_DEV_FUN, 0},
+  {SB_PCIB_REG40, 0xFF, BIT5},      // RPR PCI-bridge Subtractive Decode
+  {SB_PCIB_REG4B, 0xFF, BIT7},      //
+  {SB_PCIB_REG66, 0xFF, BIT4},      // RPR Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
+  {SB_PCIB_REG65, 0xFF, BIT7},      // RPR proper operation of CLKRUN#.
+  {SB_PCIB_REG0D, 0x00, 0x40},      // Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
+  {SB_PCIB_REG1B, 0x00, 0x40},      // of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
+  {SB_PCIB_REG66 + 1, 0xFF, BIT1},  // RPR Enable PCI bus GNT3#..
+  {0xFF, 0xFF, 0xFF},
+
+  // SATA Device (Bus 0, Dev 17, Func 0)
+  {0x00, SATA_BUS_DEV_FUN, 0},
+  {SB_SATA_REG44, 0xff, BIT0},       // RPR Enables the SATA watchdog timer register prior to the SATA BIOS post
+  {SB_SATA_REG44 + 2, 0, 0x20},      // RPR SATA PCI Watchdog timer setting
+                                     // [SB01923] Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
+  {0xFF, 0xFF, 0xFF},
+};
+
+
+/**
+ * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.
+ *
+ */
+AcpiRegWrite sbPmioEPostInitTable[] =
+{
+  {00, 00, 0xB0, 0xAC}, // Signature
+  // HPET workaround
+  {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 2, 0x7F, BIT7},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 2, 0x7F, 0x00},
+  // End of HPET workaround
+  // Enable Hudson-2 A12 ACPI bits at PMIO 0xC0 [30, 10:3]
+  // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time.
+  // UsbGoodClkDlyEn         4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time.
+  // ForceNBCPUPwr           5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood.
+  // MergeUsbPerReq          6 Set to 1 to merge usb perdical traffic into usb request as one of break event.
+  // IMCWatchDogRstEn        7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled.
+  // GeventStsFixEn          8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit.
+  // PmeTimerFixEn           9 Set to 1 to reset Pme Timer when going to sleep state.
+  // UserRst2EcEn           10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled.
+  // Smbus0ClkSEn           30 Set to 1 to enable SMBus0 controller clock stretch support.
+  {PMIO_BASE >> 8, SB_PMIOA_REGC4, ~BIT2, BIT2},
+  {PMIO_BASE >> 8, SB_PMIOA_REGC0, 0, 0xF9},
+  {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 1, 0x04, 0x03},
+  // RtcSts              19-17 RTC_STS set only in Sleep State.
+  // GppPme                 20 Set to 1 to enable PME request from SB GPP.
+  // Pcireset               22 Set to 1 to allow SW to reset PCIe.
+  {PMIO_BASE >> 8, SB_PMIOA_REGC2, 0x20, 0x58},
+  {PMIO_BASE >> 8, SB_PMIOA_REGC2 + 1, 0, 0x40},
+  {PMIO_BASE >> 8, SB_PMIOA_REGC2, ~(BIT4), BIT4},
+  {PMIO_BASE >> 8, SB_PMIOA_REGCC, 0xF8, 0x01},
+  {PMIO_BASE >> 8, SB_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
+  {PMIO_BASE >> 8, SB_PMIOA_REG74 + 3, ~BIT5, 0},
+  {PMIO_BASE >> 8, SB_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},
+  {PMIO_BASE >> 8, SB_PMIOA_REGDE, ~BIT4, BIT4},
+  {PMIO_BASE >> 8, SB_PMIOA_REGBA, ~BIT3, BIT3},
+  {PMIO_BASE >> 8, SB_PMIOA_REGBA + 1, ~BIT6, BIT6},
+  {PMIO_BASE >> 8, SB_PMIOA_REGBC, ~BIT1, BIT1},
+  {PMIO_BASE >> 8, SB_PMIOA_REGED, ~(BIT4 + BIT0 + BIT1), 0},
+  //RPR Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01
+  {PMIO_BASE >> 8, SB_PMIOA_REGDC, 0x7C, BIT0},
+  {SMI_BASE >> 8, SB_SMI_Gevent1, 0, 1},
+  {SMI_BASE >> 8, SB_SMI_Gevent3, 0, 3},
+  {SMI_BASE >> 8, SB_SMI_Gevent4, 0, 4},
+  {SMI_BASE >> 8, SB_SMI_Gevent5, 0, 5},
+  {SMI_BASE >> 8, SB_SMI_Gevent6, 0, 6},
+  {SMI_BASE >> 8, SB_SMI_Gevent23, 0, 23},
+  {SMI_BASE >> 8, SB_SMI_xHC0Pme, 0, 11},
+  {SMI_BASE >> 8, SB_SMI_xHC1Pme, 0, 11},
+  {SMI_BASE >> 8, SB_SMI_Usbwakup0, 0, 11},
+  {SMI_BASE >> 8, SB_SMI_Usbwakup1, 0, 11},
+#ifndef USB_LOGO_SUPPORT
+  {SMI_BASE >> 8, SB_SMI_Usbwakup2, 0, 11},
+  {SMI_BASE >> 8, SB_SMI_Usbwakup3, 0, 11},
+#endif
+  {SMI_BASE >> 8, SB_SMI_IMCGevent0, 0, 12},
+  {SMI_BASE >> 8, SB_SMI_FanThGevent, 0, 13},
+  {SMI_BASE >> 8, SB_SMI_SBGppPme0, 0, 15},
+  {SMI_BASE >> 8, SB_SMI_SBGppPme1, 0, 16},
+  {SMI_BASE >> 8, SB_SMI_SBGppPme2, 0, 17},
+  {SMI_BASE >> 8, SB_SMI_SBGppPme3, 0, 18},
+  {SMI_BASE >> 8, SB_SMI_GecPme, 0, 19},
+  {SMI_BASE >> 8, SB_SMI_CIRPme, 0, 28},
+  {SMI_BASE >> 8, SB_SMI_Gevent8, 0, 24},
+  {SMI_BASE >> 8, SB_SMI_AzaliaPme, 0, 27},
+  {SMI_BASE >> 8, SB_SMI_SataGevent0, 0, 30},
+  {SMI_BASE >> 8, SB_SMI_SataGevent1, 0, 31},
+  {SMI_BASE >> 8, SB_SMI_REG08,  0xE7, 0},
+  {SMI_BASE >> 8, SB_SMI_REG0C + 2, ~BIT3, BIT3},
+  {SMI_BASE >> 8, SB_SMI_TWARN, 0, 9},
+// RPR CG PLL CMOX Clock Driver Setting for power saving
+  {MISC_BASE >> 8, SB_MISC_REG18 + 0x06, 0, 0xE0},
+  {MISC_BASE >> 8, SB_MISC_REG18 + 0x07, 0, 0x1F},
+  //{SERIAL_DEBUG_BASE >> 8, SB_SDB_REG74, 0, 0},
+  {0xFF, 0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * abTblEntry800 - AB-Link Configuration Table for Hudson-2
+ *
+ */
+ABTBLENTRY abTblEntry800[] =
+{
+  // RPR Enable downstream posted transactions to pass non-posted transactions.
+  {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
+
+  // RPR Enable Hudson-2 to issue memory read/write requests in the upstream direction.
+  {AXCFG, SB_AB_REG04, BIT2, BIT2},
+
+  // RPR Enabling IDE/PCIB Prefetch for Performance Enhancement
+  // PCIB prefetch   ABCFG 0x10060 [20] = 1   ABCFG 0x10064 [20] = 1
+  {ABCFG, SB_ABCFG_REG10060, BIT20, BIT20}, //  PCIB prefetch enable
+  {ABCFG, SB_ABCFG_REG10064, BIT20, BIT20}, //  PCIB prefetch enable
+
+  // RPR Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices.
+  // RPR Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11)
+  {ABCFG, SB_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18},
+
+  // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21]
+  // RPR 7.7 USB Delay A-Link Express L1 State. ABCFG 0x90[16]
+  {ABCFG, SB_ABCFG_REG90, BIT21 + BIT16, BIT21 + BIT16},
+
+  // RPR Disable the credit variable in the downstream arbitration equation
+  // RPR Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set)
+  {ABCFG, SB_ABCFG_REG9C, BIT0, BIT0},
+
+  // RPR Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
+  // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
+  {ABCFG, SB_ABCFG_REG94, BIT20, BIT20 + 0x00FEE},
+
+  // RPR Programming cycle delay for AB and BIF clock gating
+  // RPR Enable the AB and BIF clock-gating logic.
+  // RPR Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently
+  // RPR Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP
+  {ABCFG, SB_ABCFG_REG10054,  0x00FFFFFF, 0x010407FF},
+  {ABCFG, SB_ABCFG_REG98,  0xFFFC00FF, 0x00034700},
+  {ABCFG, SB_ABCFG_REG54,  0x00FF0000, 0x00040000},
+  // RPR Non-Posted Memory Write Support
+  {AXINDC, SB_AX_INDXC_REG10, BIT9, BIT9},
+  // RPR 4.18 UMI L1 Configuration
+  //Step 1: AXINDC_Reg 0x02[0] = 0x1 Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off.
+  //Step 2: AXINDP_Reg 0x02[15] = 0x1 Sets REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to prevent LC from going to L1 when there are outstanding completions.
+  {AXINDC, SB_AX_INDXC_REG02, BIT0, BIT0},
+  {AXINDP, SB_AX_INDXP_REG02, BIT15, BIT15},
+  {ABCFG, 0, 0, (UINT8) 0xFF},  // This dummy entry is to clear ab index
+  { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
+};
+
+/**
+ * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature
+ *
+ */
+ABTBLENTRY SbPcieOrderRule[] =
+{
+// abPostPassNpDownStreamTbl
+  {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},
+  {ABCFG, SB_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5},
+  {ABCFG, SB_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7},
+  {ABCFG, SB_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23},
+  {ABCFG, SB_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5},
+  {AXINDC, SB_AX_INDXC_REG02, BIT9, BIT9},
+  {ABCFG, SB_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12},
+// abPostPassNpUpStreamTbl
+  {ABCFG, SB_ABCFG_REG58, BIT10, BIT10},
+  {ABCFG, SB_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4},
+  {ABCFG, SB_ABCFG_REG54, BIT1, BIT1},
+  { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
+};
+
+/**
+ * Table for SD controller capability register
+ *
+ *
+ *
+ *
+ */
+UINT32 sdCap[] =
+{
+  0x00000000, //
+  0x039FD972, //
+  0x839ED972, //
+  0x839AD972, //
+  0x839DD972, //
+  0x839CD972, //
+  0x8398D972, //
+};
+
+/**
+ * Table for Spread Spectrum
+ *
+ * RPR 12.9 Internal Clock Generator Spread Profile - to set default value to 0.363%.
+ *
+ *
+ */
+SB_SPREAD_SPECTRUM_ENTRY SpreadParameterTable[] =
+{
+  {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},               //  Disabled
+  {1, 0x318, 0, 0x6F83, 0x90, 0, 0x07, 0, 1, 1},// -3630 ppm :1:Default
+  {1, 0x318, 0, 0x7AE1, 0x9F, 0, 0x0D, 0, 1, 1},// -4000 ppm :2
+  {1, 0x318, 0, 0x77CF, 0x9B, 0, 0x0B, 0, 1, 1},// -3900 ppm :3
+  {1, 0x318, 0, 0x74BC, 0x94, 0, 0x0A, 0, 1, 1},// -3800 ppm :4
+  {1, 0x318, 0, 0x71AA, 0x93, 0, 0x08, 0, 1, 1},// -3700 ppm :5
+  {1, 0x318, 0, 0x6FD2, 0x90, 0, 0x07, 0, 1, 1},// -3640 ppm :6
+  {1, 0x318, 0, 0x6F83, 0x90, 0, 0x07, 0, 1, 1},// -3630 ppm :7
+  {1, 0x318, 0, 0x6F35, 0x8F, 0, 0x07, 0, 1, 1},// -3620 ppm :8
+  {1, 0x318, 0, 0x6EE6, 0x8F, 0, 0x07, 0, 1, 1},// -3610 ppm :9
+  {1, 0x318, 0, 0x6E98, 0x8F, 0, 0x07, 0, 1, 1},// -3600 ppm :10
+  {1, 0x318, 0, 0x6E49, 0x8E, 0, 0x07, 0, 1, 1},// -3590 ppm :11
+  {1, 0x018, 0, 0x6666, 0x83, 0, 0x00, 0, 0, 1} // -3500 ppm :12
+};
+
+/**
+ * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
+ *
+ *    This settings should be done during S3 resume also
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+commonInitEarlyBoot (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32   abValue;
+  UINT16   dwTempVar;
+  SB_CPUID_DATA  CpuId;
+  UINT8   cimNativepciesupport;
+  UINT8   cimIrConfig;
+  UINT8   Data;
+  UINT8   cimALinkClkGateOff;
+  UINT8   cimBLinkClkGateOff;
+
+  cimNativepciesupport = (UINT8) pConfig->NativePcieSupport;
+  cimIrConfig = (UINT8) pConfig->IrConfig;
+  cimALinkClkGateOff = (UINT8) pConfig->ALinkClkGateOff;
+  cimBLinkClkGateOff = (UINT8) pConfig->BLinkClkGateOff;
+
+#if  SB_CIMx_PARAMETER == 0
+  cimNativepciesupport = cimNativepciesupportDefault;
+  cimIrConfig = cimIrConfigDefault;
+#endif
+  //Clear hwmSbtsiAutoPollStarted
+  pConfig->hwm.hwmSbtsiAutoPollStarted = FALSE;
+  //Ac Loss Control
+  AcLossControl (pConfig->PwrFailShadow);
+
+  //SB VGA Init
+  // OBS194249 Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B
+  // Removed for OBS194249 causes display issue in Windows
+  // SbVgaInit ();
+
+  //IR init Logical device 0x05
+  if ( cimIrConfig ) {
+    EnterEcConfig ();
+    RWEC8 (0x07, 0x00, 0x05);         //Select logical device 05, IR controller
+    RWEC8 (0x60, 0x00, 0x05);         //Set Base Address to 550h
+    RWEC8 (0x61, 0x00, 0x50);
+    RWEC8 (0x70, 0xF0, 0x05);         //Set IRQ to 05h
+    RWEC8 (0x30, 0x00, 0x01);         //Enable logical device 5, IR controller
+    Data = 0xAB;
+    WriteIO (0x550, AccWidthUint8, &Data);
+    ReadIO (0x551, AccWidthUint8, &Data);
+    Data = (((Data & 0xFC ) | 0x20) | cimIrConfig);
+    WriteIO (0x551, AccWidthUint8, &Data);
+//    Data = 0xCA;
+//    WriteIO (0x550, AccWidthUint8, &Data);
+//    Data = 0x81;
+//    WriteIO (0x551, AccWidthUint8, &Data);
+
+    ExitEcConfig ();
+    Data = 0xA0;                      // EC APIC index
+    WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
+    Data = 0x05;                      // IRQ5
+    WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
+  } else {
+    EnterEcConfig ();
+    //if (pConfig->Sdb != 1 ) {
+      //RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 0x04, AccWidthUint8, 0, 0);
+    //}
+    RWEC8 (0x07, 0x00, 0x05);         //Select logical device 05, IR controller
+    RWEC8 (0x30, 0x00, 0x00);         //Disable logical device 5, IR controller
+    ExitEcConfig ();
+  }
+
+
+  TRACE ((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n"));
+  CpuidRead (0x01, &CpuId);
+
+  //
+  // SB CFG programming
+  //
+  //Make BAR registers of smbus visible.
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
+  //Early post initialization of pci config space
+  programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );
+  if ( pConfig->BuildParameters.SmbusSsid != NULL ) {
+    RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
+  }
+  //Make BAR registers of smbus invisible.
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6);
+
+  //
+  // LPC CFG programming
+  //
+  // SSID for LPC Controller
+  if (pConfig->BuildParameters.LpcSsid != NULL ) {
+    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
+  }
+  // LPC MSI
+  if ( pConfig->BuildParameters.LpcMsi) {
+    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG78, AccWidthUint32 | S3_SAVE, ~BIT1, BIT1);
+  }
+
+  //
+  // PCIB CFG programming
+  //
+  //Disable or Enable PCI Clks based on input
+  Data = ~(pConfig->PciClks);
+  RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG42, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2), (Data & 0x0F) << 2 );
+  RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4A, AccWidthUint8 | S3_SAVE, ~(BIT3 + BIT2 + BIT1 + BIT0), Data >> 4 );
+  // PCIB MSI
+  if ( pConfig->BuildParameters.PcibMsi) {
+    RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG40, AccWidthUint8 | S3_SAVE, ~BIT3, BIT3);
+  }
+
+  if (  pConfig->SlowSpeedABlinkClock ) {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG40, AccWidthUint8, ~BIT1, BIT1);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG40, AccWidthUint8, ~BIT1, 0);
+  }
+
+  //
+  // AB CFG programming
+  //
+  // Read Arbiter address, Arbiter address is in PMIO 6Ch
+  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, &dwTempVar);
+  RWIO (dwTempVar, AccWidthUint8, 0, 0);        // Write 0 to enable the arbiter
+
+  abLinkInitBeforePciEnum (pConfig);            // Set ABCFG registers
+  // AB MSI
+  if ( pConfig->BuildParameters.AbMsi) {
+    abValue = readAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29));
+    abValue = abValue | BIT20;
+    writeAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29), abValue);
+  }
+
+
+  //
+  // SB Specific Function programming
+  //
+
+  // PCIE Native setting
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBA + 1, AccWidthUint8, ~BIT14, 0);
+  if ( pConfig->NativePcieSupport == 1) {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT3 + BIT2 + BIT0);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT3 + BIT2);
+  }
+
+#ifdef ACPI_SLEEP_TRAP
+  // Set SLP_TYPE as SMI event
+  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB0, AccWidthUint8, ~(BIT2 + BIT3), BIT2);
+  // Disabled SLP function for S1/S3/S4/S5
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~BIT5, 0x00);
+  // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1)
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG08 + 3, AccWidthUint8, ~(BIT0 + BIT1), BIT1);
+  // Enabled Global Smi ( BIT7 clear as 0 to enable )
+  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG98 + 3 , AccWidthUint8, ~BIT7, 0x00);
+#endif
+  // Set Stutter timer settings
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8, ~(BIT3 + BIT4), BIT3 + BIT4);
+  // Set LDTSTP# duration to 10us for HydraD CPU, or when HT link is 200MHz
+  if ((pConfig->AnyHT200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x0A);
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8, 0xFE, 0x28);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x01);
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8, 0xFE, 0x20);
+  }
+  // A/B Clock Gate-OFF
+  if ( (IsSbA12Plus ()) && ( cimALinkClkGateOff || cimBLinkClkGateOff )) {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG04 + 2, AccWidthUint8, ~(BIT0), BIT0);
+  }
+  if ( cimALinkClkGateOff ) {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccWidthUint8, 0xFE, BIT0);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccWidthUint8, 0xFE, 0x00);
+  }
+  if ( cimBLinkClkGateOff ) {
+    if ( IsSbA11 () ) {
+      // RPR13.7 B-Link Clock Gating Threshold for A11 only
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x2D, AccWidthUint8, 0xEF, 0x10); //A11 Only
+    }
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccWidthUint8, 0xFD, BIT1);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccWidthUint8, 0xFD, 0x00);
+  }
+  // RPR SSC will provide better jitter margin
+  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccWidthUint8, 0xFC, 0x01);
+  // Set ACPIMMIO by OEM Input table
+  programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
+  // 2.9 NB Power Good Control on System Reset
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBF, AccWidthUint8, ~ (BIT0), 0);
+  // 2.10 Extend SerIrq request
+  RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ (BIT29), (BIT29));
+  // 2.13 Clear status of SATA PERR
+  Data = BIT6;
+  WriteMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG3C, AccWidthUint8, &Data);
+  Data = BIT7;
+  WriteMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG84 + 2, AccWidthUint8, &Data);
+
+  if (IsSbA13Plus ()) {
+    // 2.14 Enable Delayed SLP_S3/S5 to the Board
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 1, AccWidthUint8, 0xFF, BIT2);
+    // 2.15 Enable C-State Wake-up before Warm Reset
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~ (BIT0), BIT0);
+    // 3.16 Disable LPC A-Link Cycle Bypass
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ (BIT19), (BIT19));
+  }
+  //RPR 3.5 Enabling  LPCCLK0 Power-down Function
+  //OBS261463 Torpedo-IMC Fan Control-System stops somewhere when running S3
+  if ((!isImcEnabled ()) && (IsSbA13Plus ())) {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD2, AccWidthUint8, ~ (BIT3), BIT3);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD2, AccWidthUint8, ~ (BIT3), 0);
+  }
+  TRACE ((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n"));
+}
+
+/**
+ * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+abSpecialSetBeforePciEnum (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32   abValue;
+  abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
+  abValue &= 0xf0;
+  if ( pConfig->SbPcieOrderRule && abValue ) {
+    abValue = readAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29));
+    abValue = abValue | BIT9;
+    writeAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), abValue);
+  }
+}
+
+/**
+ * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
+ *
+ *    This settings might not program during S3 resume
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+commonInitEarlyPost (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8  dbPortStatus;
+  UINT8  Data;
+  UINT32  Data32;
+  UINT8  cimSpreadSpectrum;
+  UINT8  maxSpreadEntry;
+  AMDSBCFG*   pTmp;
+  pTmp = pConfig;
+
+  maxSpreadEntry = (sizeof SpreadParameterTable) / (sizeof (SB_SPREAD_SPECTRUM_ENTRY));
+
+  cimSpreadSpectrum = pConfig->SpreadSpectrum;
+#if  SB_CIMx_PARAMETER == 0
+  cimSpreadSpectrum = cimSpreadSpectrumDefault;
+#endif
+  programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioEPostInitTable[0]));
+
+  // Turn on and configure LPC clock (48MHz)
+  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x28, AccWidthUint32, ~(BIT21 + BIT20 + BIT19), 2 << 19);
+  RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG40, AccWidthUint8, ~BIT7, 0);
+
+  if ( cimSpreadSpectrum ) {
+    if ( IsSbA11 () ) {
+    // Misc_Reg_40[25]=1 -> allow to change spread profile
+    // Misc_Reg19=83 -> new spread profile
+    // Misc_Reg[12:10]=9975be
+    // Misc_Reg0B=91
+    // Misc_Reg09=21
+    // Misc_Misc_Reg_08[0]=1 -> enable spread
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x43, AccWidthUint8, ~BIT1, BIT1);
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x19, AccWidthUint8, 0, 0x83);
+      getChipSysMode (&dbPortStatus);
+      if ( ((dbPortStatus & ChipSysIntClkGen) != ChipSysIntClkGen) ) {
+        RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1A, AccWidthUint8, ~(BIT5 + BIT6 + BIT7), 0x80);
+      }
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x99);
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x75);
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xBE);
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x91);
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21);
+    }
+    if ( cimSpreadSpectrum >= maxSpreadEntry ) {
+      cimSpreadSpectrum = 1;
+    }
+    if ( IsSbA12Plus () ) {
+
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccWidthUint32, (UINT32) (~(0x1 << 25)), ( SpreadParameterTable[cimSpreadSpectrum].P_40_25 << 25));
+
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint32, (UINT32) (~(0x1 << 0)), (0x0 << 0));
+
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint32, (UINT32) (~(0x7FF << 5)), (SpreadParameterTable[cimSpreadSpectrum].P_18_15_5 << 5));
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint32, (UINT32) (~(0xF << 16)), (SpreadParameterTable[cimSpreadSpectrum].P_18_19_16 << 16));
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint32, (UINT32) (~(0xFFFF << 8)), (SpreadParameterTable[cimSpreadSpectrum].P_10_23_8 << 8));
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint32, (UINT32) (~(0xFF << 0)), (SpreadParameterTable[cimSpreadSpectrum].P_10_7_0 << 0));
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccWidthUint32, (UINT32) (~(0x3F << 0)), (SpreadParameterTable[cimSpreadSpectrum].P_1C_5_0 << 0));
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint32, (UINT32) (~(0xF << 28)), (SpreadParameterTable[cimSpreadSpectrum].P_08_31_28 << 28));
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint32, (UINT32) (~(0x1 << 7)), (SpreadParameterTable[cimSpreadSpectrum].P_08_7 << 7));
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint32, (UINT32) (~(0x1 << 8)), (SpreadParameterTable[cimSpreadSpectrum].P_08_8 << 8));
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint32, (UINT32) (~(0x3 << 24)), (SpreadParameterTable[cimSpreadSpectrum].P_10_25_24 << 24));
+    }
+    if ( IsExternalClockMode () ) {
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00);
+    } else {
+      RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x01);
+    }
+  } else {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00);
+  }
+
+  // SD Configuration
+  if ( pConfig->sdConfig ) {
+    //OBS263741 TTP1000D: SD Host Controller can't be enabled after disabling it in BIOS setup.
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE +  SB_PMIOA_REGD3, AccWidthUint8, 0xBF, 0x40);
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE +  SB_MISC_REG41, AccWidthUint8, 0xF1, 0x48);
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE +  SB_MISC_REG42, AccWidthUint8, 0xFE, 0x00);
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE +  SB_PMIOA_REGE7, AccWidthUint8, 0x00, 0x12);
+    // INT#A SD resource
+    Data = 0x97; // Azalia APIC index
+    WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
+    Data = 0x10; // IRQ16 (INTA#)
+    WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
+
+    ReadPCI ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA4, AccWidthUint32, &Data32);
+    Data32 |= BIT31 + BIT24 + BIT18 + BIT16; //ADMA
+    if ( pConfig->sdConfig == 2) {
+      Data32 &=  ~(BIT16 + BIT24); //DMA
+    } else if ( pConfig->sdConfig == 3) {
+      Data32 &=  ~(BIT16 + BIT18 + BIT24); //PIO
+    }
+    Data32 &= ~(BIT17 + BIT23); //clear bitwidth
+    Data32 |= (pConfig->sdSpeed << 17) + (pConfig->sdBitwidth << 23);
+    RWPCI ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA4, AccWidthUint32 | S3_SAVE, 0, Data32);
+    //SB02544: SD: Some SD cards cannot be detected in HIGH speed mode
+    if ( IsSbA12Plus () ) {
+      RWPCI ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGB0, AccWidthUint32 | S3_SAVE, (UINT32) (~ (0x03 << 10)), (UINT32) (0x03 << 10));
+    }
+    //BUG260949  There isn't code that set SSID of SD Controller in Hudson CIMX
+    ReadPCI ((SD_BUS_DEV_FUN << 16) + SD_PCI_REG00, AccWidthUint32, &Data32);
+    RWPCI ((SD_BUS_DEV_FUN << 16) + SD_PCI_REG2C, AccWidthUint32 | S3_SAVE, 0, Data32);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE +  SB_PMIOA_REGD3, AccWidthUint8, 0xBF, 0x00);
+  }
+
+  // RPR PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5)
+  // RPR OSC Clock setting for  internal clock generator mode (BIT6)
+  getChipSysMode (&dbPortStatus);
+  if ( ((dbPortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE +  SB_MISC_REG04 + 1, AccWidthUint8, ~(BIT5 + BIT6), BIT5 + BIT6);
+  }
+
+  // Set ASF SMBUS master function enabled here (temporary)
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16 | S3_SAVE, ~(BIT0 + BIT2), BIT0 + BIT2);
+
+  programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
+
+#ifndef NO_EC_SUPPORT
+  // Software IMC enable
+  if (((pConfig->BuildParameters.ImcEnableOverWrite == 1) && ((dbPortStatus & ChipSysEcEnable) == 0)) || ((pConfig->BuildParameters.ImcEnableOverWrite == 2) && ((dbPortStatus & ChipSysEcEnable) == ChipSysEcEnable))) {
+    if (validateImcFirmware (pConfig)) {
+      softwareToggleImcStrapping (pConfig);
+    }
+  }
+#endif
+
+}
+/**
+ * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+abLinkInitBeforePciEnum (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32  cimResetCpuOnSyncFlood;
+  ABTBLENTRY  *pAbTblPtr;
+  AMDSBCFG* Temp;
+
+  cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood;
+#if  SB_CIMx_PARAMETER == 0
+  cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault;
+#endif
+  Temp = pConfig;
+  if ( pConfig->SbPcieOrderRule == 1 ) {
+    pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]);
+    abcfgTbl (pAbTblPtr);
+  }
+  if ( pConfig->SbPcieOrderRule == 2 ) {
+    rwAlink (SB_ABCFG_REG10090 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 10), (UINT32) (0x7 << 10));
+    rwAlink (SB_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1F << 11), (UINT32) (0x1C << 11));
+    rwAlink (SB_ABCFG_REGB4 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 0), (UINT32) (0x3 << 0));
+  }
+  pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]);
+  abcfgTbl (pAbTblPtr);
+  if ( cimResetCpuOnSyncFlood ) {
+    rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2);
+  }
+
+  if ( pConfig->AbClockGating ) {
+    rwAlink (SB_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
+    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
+    rwAlink (SB_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24));
+    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24));
+  } else {
+    rwAlink (SB_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24));
+    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24));
+  }
+
+
+  if ( pConfig->GppClockGating ) {
+    rwAlink (SB_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 12), (UINT32) (0x4 << 12));
+    rwAlink (SB_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x7 << 8));
+    rwAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0));
+  } else {
+    rwAlink (SB_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x0 << 8));
+    rwAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0));
+  }
+
+  if ( pConfig->L1TimerOverwrite ) {
+    rwAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 12), (UINT32) (pConfig->L1TimerOverwrite  << 12));
+    rwAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1  << 15));
+  }
+
+  if ( pConfig->UmiLinkWidth ) {
+//    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
+  }
+  if ( pConfig->UmiDynamicSpeedChange ) {
+    rwAlink ((UINT32) SB_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0));
+    rwAlink ((UINT32) SB_AX_CFG_REG88, ~ (UINT32) (0xF << 0), (UINT32) (0x2 << 0));
+    rwAlink ((UINT32) SB_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 18), (UINT32) (0x1 << 18));
+  }
+  if ( pConfig->PcieRefClockOverclocking ) {
+//    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
+  }
+  if ( pConfig->SbAlinkGppTxDriverStrength  ) {
+    rwAlink (SB_ABCFG_REGA8 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 18), (UINT32) ((pConfig->SbAlinkGppTxDriverStrength - 1) << 18));
+    rwAlink (SB_ABCFG_REGA0 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 8), (UINT32) (0x1 << 8));
+  }
+  if ( pConfig->PcieAER ) {
+//    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
+  }
+  if ( pConfig->PcieRAS ) {
+//    rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
+  }
+}
+
+/**
+ * abcfgTbl - Program ABCFG by input table.
+ *
+ *
+ * @param[in] pABTbl  ABCFG config table.
+ *
+ */
+VOID
+abcfgTbl (
+  IN       ABTBLENTRY* pABTbl
+  )
+{
+  UINT32   ddValue;
+
+  while ( (pABTbl->regType) != 0xFF ) {
+    TRACE ((DMSG_SB_TRACE, "RegType: %X, RegNumber: %X, AndMask = %X, OrMask = %X \n", pABTbl->regType, pABTbl->regIndex, pABTbl->regMask, pABTbl->regData));
+    if ( pABTbl->regType == AXINDC ) {
+      ddValue = 0x30 | (pABTbl->regType << 29);
+      writeAlink (ddValue, (pABTbl->regIndex & 0x00FFFFFF));
+      ddValue = 0x34 | (pABTbl->regType << 29);
+      writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
+    } else if ( pABTbl->regType == AXINDP ) {
+      ddValue = 0x38 | (pABTbl->regType << 29);
+      writeAlink (ddValue, (pABTbl->regIndex & 0x00FFFFFF));
+      ddValue = 0x3C | (pABTbl->regType << 29);
+      writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
+    } else {
+      ddValue = pABTbl->regIndex | (pABTbl->regType << 29);
+      writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
+    }
+    ++pABTbl;
+  }
+
+  //Clear ALink Access Index
+  ddValue = 0;
+  WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue);
+  TRACE ((DMSG_SB_TRACE, "Exiting abcfgTbl\n"));
+}
+
+/**
+ * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+commonInitLateBoot (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8  dbValue;
+  UINT32  ddVar;
+  UINT8  NStBit;
+  UINT8  NSBit;
+  UINT8  indexValue;
+
+  // We need to do the following setting in late post also because some bios core pci enumeration changes these values
+  // programmed during early post.
+  // RPR 4.5 Master Latency Timer
+
+  dbValue = 0x40;
+  WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG0D, AccWidthUint8, &dbValue);
+  WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG1B, AccWidthUint8, &dbValue);
+
+  //RPR 6.4 CLKRUN#
+  // SB P2P AutoClock control settings.
+  // ddVar = (pConfig->PcibAutoClkCtrlLow) | (pConfig->PcibAutoClkCtrlLow);
+  if ( pConfig->ClockRun ) {
+    ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG54, AccWidthUint8, &dbValue);
+    NStBit = dbValue & 0x03;
+    NSBit = (dbValue & 0x3F ) >> 2;
+    ddVar = (4 + (NStBit * 2) + (( 17 + NSBit) * 3) + 4) | 0x01;
+    if ( IsSbA12Plus () ) {
+      ddVar = 9; //4 clocks
+    }
+    WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4C, AccWidthUint32, &ddVar);
+  }
+
+
+
+  ddVar = (pConfig->PcibClkStopOverride);
+  RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6));
+
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, 0xBF | S3_SAVE, BIT3 + BIT4 + BIT5);
+
+  if ( IsGCPU () ) {
+    GcpuRelatedSetting (pConfig);
+  } else {
+    c3PopupSetting (pConfig);
+  }
+  //[RPR 2.12] Mt C1E Enable
+  MtC1eEnable (pConfig);
+
+  RWPCI ((0xC1 << 16) + 0xBC, AccWidthUint8, 0x7f, 0x80);
+
+  //if (pConfig->Sdb == 1 ) {
+    //RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE +  SB_SDB_REG00, AccWidthUint8, 0xFF, 0x05);
+  //}
+
+  if ( pConfig->XhciSwitch == 1 ) {
+    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccWidthUint8, &dbValue);
+    indexValue = XHCI_REGISTER_BAR00;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x11, AccWidthUint8, &dbValue);
+    indexValue = XHCI_REGISTER_BAR01;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x12, AccWidthUint8, &dbValue);
+    indexValue = XHCI_REGISTER_BAR02;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x13, AccWidthUint8, &dbValue);
+    indexValue = XHCI_REGISTER_BAR03;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
+    indexValue = XHCI_REGISTER_04H;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
+    indexValue = XHCI_REGISTER_0CH;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
+    indexValue = XHCI_REGISTER_3CH;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccWidthUint8, &dbValue);
+    indexValue = XHCI1_REGISTER_BAR00;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x11, AccWidthUint8, &dbValue);
+    indexValue = XHCI1_REGISTER_BAR01;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x12, AccWidthUint8, &dbValue);
+    indexValue = XHCI1_REGISTER_BAR02;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x13, AccWidthUint8, &dbValue);
+    indexValue = XHCI1_REGISTER_BAR03;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
+    indexValue = XHCI1_REGISTER_04H;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
+    indexValue = XHCI1_REGISTER_0CH;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+
+    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
+    indexValue = XHCI1_REGISTER_3CH;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    WriteIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+  }
+}
+
+/**
+ * hpetInit - Program Southbridge HPET function
+ *
+ *
+ *
+ * @param[in] pConfig         Southbridge configuration structure pointer.
+ * @param[in] pStaticOptions  Platform build configuration table.
+ *
+ */
+VOID
+hpetInit (
+  IN       AMDSBCFG* pConfig,
+  IN       BUILDPARAM *pStaticOptions
+  )
+{
+  DESCRIPTION_HEADER* pHpetTable;
+  UINT8 cimHpetTimer;
+  UINT8 cimHpetMsiDis;
+
+  cimHpetTimer = (UINT8) pConfig->HpetTimer;
+  cimHpetMsiDis = (UINT8) pConfig->HpetMsiDis;
+#if  SB_CIMx_PARAMETER == 0
+  cimHpetTimer = cimHpetTimerDefault;
+  cimHpetMsiDis = cimHpetMsiDisDefault;
+#endif
+  pHpetTable = NULL;
+  if ( cimHpetTimer == TRUE ) {
+    //Program the HPET BAR address
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, pStaticOptions->HpetBase);
+    //Enabling decoding of HPET MMIO
+    //Enable HPET MSI support
+    //Enable High Precision Event Timer (also called Multimedia Timer) interrupt
+    if ( cimHpetMsiDis == FALSE ) {
+      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1 + BIT2 + BIT3 + BIT4);
+#ifdef SB_TIMER_TICK_INTERVAL_WA
+      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1);
+#endif
+    } else {
+      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1);
+    }
+
+  } else {
+    if ( ! (pConfig->S3Resume) ) {
+      pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (Int32FromChar('T', 'E', 'P', 'H'));
+    }
+    if ( pHpetTable != NULL ) {
+      pHpetTable->Signature = Int32FromChar('H', 'P', 'E', 'T');
+    }
+  }
+}
+
+/**
+ * c3PopupSetting - Program Southbridge C state function
+ *
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+VOID
+c3PopupSetting (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  AMDSBCFG* Temp;
+  UINT8  dbValue;
+  Temp = pConfig;
+  dbValue = getNumberOfCpuCores  ();
+#define NON_SUPPORT_PREVIOUS_C3 TRUE
+#ifndef NON_SUPPORT_PREVIOUS_C3
+  if (dbValue > 1) {
+    //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
+    //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
+    //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert
+    //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT2), (BIT1 + BIT2));
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);
+  }
+  //SB800 needs to changed for RD790 support
+  //PM 0x80 [8] = 0 for system with RS780
+  //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
+  //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
+  //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F);
+  //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
+  //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
+  //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
+  //link is disconnected.
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94 + 2, AccWidthUint8, 0, 0x10);
+
+  //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
+  //delay will allow USB DMA to go on in a continuous manner
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 1, AccWidthUint8, 0, 0x10);
+  // Not in the RPR so far, it's hand writing from ASIC
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C, AccWidthUint8 | S3_SAVE, 0, 0x85);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C + 1, AccWidthUint8 | S3_SAVE, 0, 0x01);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E + 1, AccWidthUint8 | S3_SAVE, ~(BIT7 + BIT5), BIT7 + BIT5);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4);
+  // RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x10);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, 0, 0x10);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4 + 1, AccWidthUint8, 0, 0x0B);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~(BIT4 + BIT5), BIT4 + BIT5);
+
+#else
+  //RPR2.4 C-State and VID/FID Change
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~(BIT5), BIT5);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT2), BIT2);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT1), BIT1);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~(BIT6), BIT6);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8 | S3_SAVE, 0, 0x01);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG89, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG9B, AccWidthUint8 | S3_SAVE, ~(BIT6 + BIT5 + BIT4), BIT4);
+
+  //RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT10), BIT10);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG9B, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), 0);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG96, AccWidthUint8 | S3_SAVE, 0, 0x10);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG99, AccWidthUint8 | S3_SAVE, 0, 0x10);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG8E, AccWidthUint8 | S3_SAVE, 0, 0x80);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG97, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), 0);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT4), BIT4);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9), BIT9);
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT7), 0);
+
+#endif
+}
+
+/**
+ * GcpuRelatedSetting - Program GCPU C related function
+ *
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+VOID
+GcpuRelatedSetting (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8 cimAcDcMsg;
+  UINT8 cimTimerTickTrack;
+  UINT8 cimClockInterruptTag;
+  UINT8 cimOhciTrafficHanding;
+  UINT8 cimEhciTrafficHanding;
+  UINT8 cimFusionMsgCMultiCore;
+  UINT8 cimFusionMsgCStage;
+  UINT32 ddValue;
+
+  cimAcDcMsg = (UINT8) pConfig->AcDcMsg;
+  cimTimerTickTrack = (UINT8) pConfig->TimerTickTrack;
+  cimClockInterruptTag = (UINT8) pConfig->ClockInterruptTag;
+  cimOhciTrafficHanding = (UINT8) pConfig->OhciTrafficHanding;
+  cimEhciTrafficHanding = (UINT8) pConfig->EhciTrafficHanding;
+  cimFusionMsgCMultiCore = (UINT8) pConfig->FusionMsgCMultiCore;
+  cimFusionMsgCStage = (UINT8) pConfig->FusionMsgCStage;
+#if  SB_CIMx_PARAMETER == 0
+  cimAcDcMsg = cimAcDcMsgDefault;
+  cimTimerTickTrack = cimTimerTickTrackDefault;
+  cimClockInterruptTag = cimClockInterruptTagDefault;
+  cimOhciTrafficHanding = cimOhciTrafficHandingDefault;
+  cimEhciTrafficHanding = cimEhciTrafficHandingDefault;
+  cimFusionMsgCMultiCore = cimFusionMsgCMultiCoreDefault;
+  cimFusionMsgCStage = cimFusionMsgCStageDefault;
+#endif
+  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);
+  ddValue = ddValue & 0xC07F00A0;
+  if ( cimAcDcMsg ) {
+    ddValue = ddValue | BIT0;
+  }
+  if ( cimTimerTickTrack ) {
+    ddValue = ddValue | BIT1;
+  }
+  if ( cimClockInterruptTag ) {
+    ddValue = ddValue | BIT10;
+  }
+  if ( cimOhciTrafficHanding ) {
+    ddValue = ddValue | BIT13;
+  }
+  if ( cimEhciTrafficHanding ) {
+    ddValue = ddValue | BIT15;
+  }
+  if ( cimFusionMsgCMultiCore ) {
+    ddValue = ddValue | BIT23;
+  }
+  if ( cimFusionMsgCMultiCore ) {
+    ddValue = (ddValue | (BIT6 + BIT4 + BIT3 + BIT2));
+  }
+
+  WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);
+}
+
+/**
+ * MtC1eEnable - Program Mt C1E Enable Function
+ *
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+VOID
+MtC1eEnable (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  if ( pConfig->MtC1eEnable ) {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, ~ BIT15, BIT15);
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, ~ (BIT3 + BIT2 + BIT1 + BIT0), 0x01);
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~ BIT13, BIT13);
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~ BIT7, BIT7);
+  }
+}
+
+#ifndef NO_EC_SUPPORT
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ * @retval        TRUE   Pass
+ * @retval        FALSE  Failed
+ */
+BOOLEAN
+validateImcFirmware (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32  ImcSig;
+  UINT32  ImcSigAddr;
+  UINT32  ImcAddr;
+  UINT32  CurAddr;
+  UINT32  ImcBinSig0;
+  UINT32  ImcBinSig1;
+  UINT16  ImcBinSig2;
+  UINT8  dbIMCChecksume;
+  UINT8  dbIMC;
+  ImcAddr = 0;
+
+  // Software IMC enable
+  ImcSigAddr = 0x80000; // start from 512k to 64M
+  ImcSig = 0x0; //
+  while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) {
+    CurAddr = 0xffffffff - ImcSigAddr + 0x20001;
+    ReadMEM (CurAddr, AccWidthUint32, &ImcSig);
+    ReadMEM ((CurAddr + 4), AccWidthUint32, &ImcAddr);
+    ImcSigAddr <<= 1;
+  }
+
+  dbIMCChecksume = 0xff;
+  if ( ImcSig == 0x55aa55aa ) {
+    // "_AMD_IMC_C" at offset 0x2000 of the binary
+    ReadMEM ((ImcAddr + 0x2000), AccWidthUint32, &ImcBinSig0);
+    ReadMEM ((ImcAddr + 0x2004), AccWidthUint32, &ImcBinSig1);
+    ReadMEM ((ImcAddr + 0x2008), AccWidthUint16, &ImcBinSig2);
+    if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) {
+      dbIMCChecksume = 0;
+      for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) {
+        ReadMEM (CurAddr, AccWidthUint8, &dbIMC);
+        dbIMCChecksume = dbIMCChecksume + dbIMC;
+      }
+    }
+  }
+  if ( dbIMCChecksume ) {
+    return  FALSE;
+  } else {
+    return  TRUE;
+  }
+}
+
+/**
+ * softwareToggleImcStrapping - Software Toggle IMC Firmware Strapping.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+softwareToggleImcStrapping (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8  dbValue;
+  UINT8  dbPortStatus;
+  UINT32  abValue;
+  UINT32  abValue1;
+
+  getChipSysMode (&dbPortStatus);
+
+  ReadPMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);
+  //if ( (dbValue & (BIT6 + BIT7)) != 0xC0 ) {  // PwrGoodOut =1, PwrGoodEnB=1
+  //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference.
+
+  //StrapStatus                               StrapOverride
+  //   bit4                                            bit17
+  //   bit6                                            bit12
+  //   bit12                                           bit15
+  //   bit15                                           bit16
+  //   bit16                                           bit18
+  ReadMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80), AccWidthUint32, &abValue);
+  abValue1 = abValue & (~ (BIT4 + BIT6 + BIT17 + BIT12 + BIT15 + BIT16 + BIT18));
+  if (abValue & BIT4) {
+    abValue1 = (abValue1 & ~BIT4) | BIT17;
+  }
+  if (abValue & BIT6) {
+    abValue1 = (abValue1 & ~BIT6) | BIT12;
+  }
+  if (abValue & BIT12) {
+    abValue1 = (abValue1 & ~BIT12) | BIT15;
+  }
+  if (abValue & BIT15) {
+    abValue1 = (abValue1 & ~BIT15) | BIT16;
+  }
+  if (abValue & BIT16) {
+    abValue1 = (abValue1 & ~BIT16) | BIT18;
+  }
+  abValue1 |= BIT31;             // Overwrite enable
+  if ((dbPortStatus & ChipSysEcEnable) == 0) {
+    abValue1 |= BIT2;            // bit2- EcEnableStrap
+  } else {
+    abValue1 &= ~BIT2;           // bit2=0 EcEnableStrap
+  }
+  WriteMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG84), AccWidthUint32, &abValue1);
+  dbValue |= (BIT6 + BIT7);                                             // PwrGoodOut =1, PwrGoodEnB=1
+  WritePMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);
+
+  dbValue = 06;
+  WriteIO (0xcf9, AccWidthUint8, &dbValue);
+  SbStall (0xffffffff);
+}
+#endif
+
+/**
+ * A13ResumeResetTwoSecondRtcWakeup - A13 Resume Reset 2 Seconds
+ * RTC Wakeup
+ *
+ *
+ *
+ * @retval  Nothing
+ *
+ */
+VOID
+A13ResumeResetTwoSecondRtcWakeup (
+  void
+  )
+{
+  if ( IsSbA13Plus () ) {
+    //Configure RTC clocks and power failure to "off"
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG57) |= 0x03;
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG56) |= 0x80;
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG56) &= 0x7f;
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG5B) = 0x04;
+
+    //set 2 seconds RTC wake up
+    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x00) = 0;
+    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x01) = 2;
+    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x02) = 0;
+    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x03) = 0;
+    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x04) = 0;
+    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x05) = 0;
+    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x0d) = 0x80;
+    ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_BASE + 0x0b) |= 0x22;
+
+    //Do ResumeReset by SB A13 ECO
+    WriteIo8 (0x80, 0xef);
+    ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6) |= 0x40;
+    do {
+      WriteIo8 (0x80, 0xfe);
+    } while ( ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6) );
+  }
+}
+
+/**
+ * StressResetModeLate - Stress Reset Mode
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+StressResetModeLate (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  switch ( pConfig->StressResetMode ) {
+  case 1:
+    WriteIo8 ((UINT16) (0x64), 0xFE);
+    break;
+  case 2:
+    WriteIo8 ((UINT16) (0xCF9), 0x06);
+    break;
+  case 3:
+    WriteIo8 ((UINT16) (0xCF9), 0x0E);
+    break;
+  case 4:
+    A13ResumeResetTwoSecondRtcWakeup ();
+    return;
+  default:
+    return;
+  }
+  while (pConfig->StressResetMode) {
+  }
+}
+
+/**
+ * CheckEfuse - Check Efuse
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+CheckEfuse (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8     EfuseIndex;
+  UINT8     EfuseFailureCount;
+  pConfig->EfuseRemainder = 0;
+  pConfig->EfuseSum = 0;
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5);
+  for ( EfuseIndex = 0; EfuseIndex < 0x20; EfuseIndex ++ ) {
+    pConfig->EfuseByte [EfuseIndex] = getEfuseByte (EfuseIndex);
+  }
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0);
+  for ( EfuseIndex = 0x10; EfuseIndex < 0x20; EfuseIndex ++ ) {
+    pConfig->EfuseSum = pConfig->EfuseSum + pConfig->EfuseByte [EfuseIndex];
+    pConfig->EfuseRemainder = (((pConfig->EfuseRemainder) << 8) + pConfig->EfuseByte [0x2f - EfuseIndex]) % 0xc1;
+  }
+  pConfig->EfuseSum = (UINT8) (0x100 - pConfig->EfuseSum);
+  if (!(( pConfig->EfuseByte [0x0e] == 0 ) && ( pConfig->EfuseByte [0x0f] == 0 ))) {
+    if (( pConfig->EfuseRemainder != pConfig->EfuseByte [0x0e] ) || ( pConfig->EfuseSum != pConfig->EfuseByte [0x0f])) {
+      EfuseFailureCount = ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D);
+      if ( EfuseFailureCount == 0xff ) {
+        EfuseFailureCount = 0;
+        ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D) = 0;
+      }
+      if ( EfuseFailureCount < 2 ) {
+        EfuseFailureCount++;
+        ACPIMMIO8 (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D) = EfuseFailureCount;
+        A13ResumeResetTwoSecondRtcWakeup ();
+      }
+    }
+  }
+}
+
+/**
+ * ValidateFchVariant - Validate FCH Variant
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+ValidateFchVariant (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8     XhciEfuse;
+  UINT8     PcieEfuse;
+  UINT8     FchVariantEfuse;
+
+  switch ( pConfig->FchVariant ) {
+  case FCH_M3T:
+    //Disable Devices for M3T
+    pConfig->GecConfig = 1;
+    pConfig->hwm.hwmEnable = 0;
+    pConfig->sdConfig = 0;
+    pConfig->IrConfig = 0;
+//    pConfig->USBMODE.UsbMode.Ohci3 = 0;
+//    pConfig->USBMODE.UsbMode.Ehci3 = 0;
+    break;
+  default:
+    break;
+  }
+
+  // add Efuse checking for Xhci enable/disable
+  XhciEfuse = XHCI_EFUSE_LOCATION;
+  getEfuseStatus (&XhciEfuse);
+  if ((XhciEfuse & (BIT0 + BIT1)) == (BIT0 + BIT1)) {
+    pConfig->XhciSwitch = 0;
+  }
+
+  // add Efuse checking for PCIE Gen2 enable
+  PcieEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
+  getEfuseStatus (&PcieEfuse);
+  if ( PcieEfuse & BIT0 ) {
+    pConfig->NbSbGen2 = 0;
+    pConfig->GppGen2 = 0;
+  }
+
+  FchVariantEfuse = FCH_Variant_EFUSE_LOCATION;
+  getEfuseStatus (&FchVariantEfuse);
+  if ((FchVariantEfuse == 0x07) || (FchVariantEfuse == 0x08)) {
+    pConfig->NbSbGen2 = 0;
+  }
+}
+
+/**
+ * Is GCPU?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsGCPU (
+  OUT VOID
+  )
+{
+  UINT8 ExtendedFamily;
+  UINT8 ExtendedModel;
+  UINT8 BaseFamily;
+  UINT8 BaseModel;
+  UINT8 Stepping;
+  UINT8 Family;
+  UINT8 Model;
+  SB_CPUID_DATA  CpuId;
+
+  CpuidRead (0x01, &CpuId);
+  ExtendedFamily = (UINT8) ((CpuId.EAX_Reg >> 20) & 0xff);
+  ExtendedModel = (UINT8) ((CpuId.EAX_Reg >> 16) & 0xf);
+  BaseFamily = (UINT8) ((CpuId.EAX_Reg >> 8) & 0xf);
+  BaseModel = (UINT8) ((CpuId.EAX_Reg >> 4) & 0xf);
+  Stepping = (UINT8) ((CpuId.EAX_Reg >> 0) & 0xf);
+  Family = BaseFamily + ExtendedFamily;
+  Model = (ExtendedModel >> 4) + BaseModel;
+  if ( (Family == 0x12) || \
+       (Family == 0x14) || \
+       (Family == 0x16) || \
+       ((Family == 0x15) && ((Model == 0x10) || (Model == 0x30))) ) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/**
+ * Is UMI One Lane GEN1 Mode?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsUmiOneLaneGen1Mode (
+  OUT VOID
+  )
+{
+  UINT32   abValue;
+  abValue = readAlink ((UINT32) (SB_AX_CFG_REG68));
+  abValue >>= 16;
+  if (((abValue & 0x0f) == 1) && ((abValue & 0x03f0) == 0x0010)) {
+    return (TRUE);
+  } else {
+    return (FALSE);
+  }
+}
+
+/**
+ * Record SMI Status
+ *
+ *
+ * @retval  Nothing
+ *
+ */
+VOID
+RecordSmiStatus (
+  OUT VOID
+  )
+{
+  UINTN   i;
+  UINT8   SwSmiValue;
+  ACPIMMIO8 (0xfed80320) |= 0x01;
+  for ( i = 0; i < 20; i++ ) {
+    ACPIMMIO8 (0xfed10020 + i) = ACPIMMIO8 (0xfed80280 + i);
+  }
+  SwSmiValue = ReadIo8 (0xb0);
+  ACPIMMIO8 (0xfed10040) = SwSmiValue;
+}
+
diff --git a/src/vendorcode/amd/cimx/sb900/SbDef.h b/src/vendorcode/amd/cimx/sb900/SbDef.h
new file mode 100755
index 0000000..3a727ab
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SbDef.h
@@ -0,0 +1,422 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+
+//AMD Library Routines (AMDLIB.C)
+void  InitSerialOut (void);
+unsigned char getNumberOfCpuCores (OUT void);
+unsigned int  readAlink (IN unsigned int Index);
+void  writeAlink (IN unsigned int Index, IN unsigned int Data);
+void  rwAlink (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
+
+//AMD Library Routines (LEGACY.C)
+unsigned int   GetFixUp (OUT void);
+
+//AMD Library Routines (IOLIB.C)
+void  ReadIO (IN unsigned short  Address, IN unsigned char OpFlag, IN void *Value);
+void  WriteIO (IN unsigned short Address, IN unsigned char OpFlag, IN void *Value);
+void  RWIO (IN unsigned short Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
+
+/// CPUID data received registers format
+typedef struct _SB_CPUID_DATA {
+  IN OUT   unsigned int          EAX_Reg;                ///< CPUID instruction result in EAX
+  IN OUT   unsigned int          EBX_Reg;                ///< CPUID instruction result in EBX
+  IN OUT   unsigned int          ECX_Reg;                ///< CPUID instruction result in ECX
+  IN OUT   unsigned int          EDX_Reg;                ///< CPUID instruction result in EDX
+} SB_CPUID_DATA;
+
+//AMD Library Routines (AMDLIB32.ASM)
+unsigned char ReadIo8 (IN unsigned short Address);
+unsigned short ReadIo16 (IN unsigned short Address);
+unsigned int ReadIo32 (IN unsigned short Address);
+void WriteIo8 (IN unsigned short Address, IN unsigned char Data);
+void WriteIo16 (IN unsigned short Address, IN unsigned short Data);
+void WriteIo32 (IN unsigned short Address, IN unsigned int Data);
+unsigned char ReadNumberOfCpuCores (void);
+unsigned long long  ReadTSC (void);
+void CpuidRead (IN unsigned int CpuidFcnAddress, OUT SB_CPUID_DATA  *Value);
+
+
+//AMD Library Routines (MEMLIB.C)
+void  ReadMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value);
+void  WriteMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value);
+void  RWMEM (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
+void
+MemoryCopy (
+  IN       unsigned char *Dest,
+  IN       unsigned char *Source,
+  IN       unsigned int Size
+  );
+
+//AMD Library Routines (PCILIB.C)
+void  ReadPCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value);
+void  WritePCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value);
+void  RWPCI (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int  Data);
+
+//AMD Library Routines (SBPELIB.C)
+/**
+ * Read Southbridge Revision ID cie Base
+ *
+ *
+ * @retval  0xXXXXXXXX   Revision ID
+ *
+ */
+unsigned char getRevisionID (OUT void);
+
+//AMD Library Routines (SBPELIB.C)
+/**
+ * Is SB A11?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+unsigned char IsSbA11 (OUT void);
+
+//AMD Library Routines (SBPELIB.C)
+/**
+ * Is SB A12?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+unsigned char IsSbA12 (OUT void);
+
+//AMD Library Routines (SBPELIB.C)
+/**
+ * Is SB A12 Plus?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+unsigned char IsSbA12Plus (OUT void);
+
+//AMD Library Routines (SBPELIB.C)
+/**
+ * Is SB A13 Plus?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+unsigned char IsSbA13Plus (OUT void);
+
+/**
+ * Is LPC Rom?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+unsigned char IsExternalClockMode (OUT void);
+
+/**
+ * Is External Clock Mode?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+unsigned char IsLpcRom (OUT void);
+
+/**
+ * Is GCPU?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+unsigned char
+IsGCPU (
+  OUT void
+  );
+
+//AMD Library Routines (SBPELIB.C)
+/**
+ * Assert/deassert Hudson-2 pins used to toggle SB GPP reset or NB PCIE reset
+ *
+ *
+ * @param[in] ResetBlock - PCIE reset for SB GPP or NB PCIE
+ * @param[in] ResetOp    - Assert or deassert PCIE reset
+ *
+ */
+void SbResetPcie (IN RESET_BLOCK  ResetBlock, IN RESET_OP ResetOp);
+
+/**
+ * sbGppTogglePcieReset - Toggle PCIE_RST2#
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+void sbGppTogglePcieReset (IN AMDSBCFG* pConfig);
+
+/**
+ * sbSpiUnlock - Sb SPI Unlock
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+void sbSpiUnlock (IN AMDSBCFG* pConfig);
+
+/**
+ * sbSpilock - Sb SPI lock
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+void sbSpilock (IN AMDSBCFG* pConfig);
+
+/**
+ * programPciByteTable - Program PCI register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pPciByteTable    - Table data pointer
+ * @param[in] dwTableSize      - Table length
+ *
+ */
+void  programPciByteTable (IN REG8MASK* pPciByteTable, IN unsigned short dwTableSize);
+
+/**
+ * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pAcpiTbl   - Table data pointer
+ *
+ */
+void  programSbAcpiMmioTbl (IN AcpiRegWrite  *pAcpiTbl);
+
+/**
+ * getChipSysMode - Get Chip status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ *   StrapStatus [15.0] - Hudson-2 chip Strap Status
+ *    @li <b>0001</b> - Not USED FWH
+ *    @li <b>0002</b> - Not USED LPC ROM
+ *    @li <b>0004</b> - EC enabled
+ *    @li <b>0008</b> - Reserved
+ *    @li <b>0010</b> - Internal Clock mode
+ *
+ */
+void getChipSysMode (IN void* Value);
+
+/**
+ * isImcEnabled - Is IMC Enabled
+ * @retval  TRUE for IMC Enabled; FALSE for IMC Disabled
+ */
+unsigned char isImcEnabled (void);
+
+/**
+ * Read Southbridge CIMx configuration structure pointer
+ *
+ *
+ *
+ * @retval  0xXXXXXXXX   CIMx configuration structure pointer.
+ *
+ */
+AMDSBCFG* getConfigPointer (OUT void);
+
+//AMD Library Routines (PMIOLIB.C)
+/**
+ * Read PMIO
+ *
+ *
+ *
+ * @param[in] Address  - PMIO Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Read Data Buffer
+ *
+ */
+void  ReadPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
+
+/**
+ * Write PMIO
+ *
+ *
+ *
+ * @param[in] Address  - PMIO Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Write Data Buffer
+ *
+ */
+void  WritePMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
+
+/**
+ * RWPMIO - Read/Write PMIO
+ *
+ *
+ *
+ * @param[in] Address    - PMIO Offset value
+ * @param[in] OpFlag     - Access sizes
+ * @param[in] AndMask    - Data And Mask 32 bits
+ * @param[in] OrMask     - Data OR Mask 32 bits
+ *
+ */
+void  RWPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN unsigned int AndMask, IN unsigned int OrMask);
+
+//AMD Library Routines (PMIO2LIB.C)
+
+/**
+ * Read PMIO2
+ *
+ *
+ *
+ * @param[in] Address  - PMIO2 Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Read Data Buffer
+ *
+ */
+void  ReadPMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
+
+/**
+ * Write PMIO 2
+ *
+ *
+ *
+ * @param[in] Address  - PMIO2 Offset value
+ * @param[in] OpFlag   - Access sizes
+ * @param[in] Value    - Write Data Buffer
+ *
+ */
+void  WritePMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
+
+/**
+ * RWPMIO2 - Read/Write PMIO2
+ *
+ *
+ *
+ * @param[in] Address    - PMIO2 Offset value
+ * @param[in] OpFlag     - Access sizes
+ * @param[in] AndMask    - Data And Mask 32 bits
+ * @param[in] OrMask     - Data OR Mask 32 bits
+ *
+ */
+void  RWPMIO2 (IN unsigned char Address, IN unsigned char  OpFlag, IN unsigned int AndMask, IN unsigned int OrMask);
+//AMD Library Routines (ECLIB.C)
+// ECLIB Routines
+
+// #ifndef NO_EC_SUPPORT
+
+/**
+ * EnterEcConfig - Force EC into Config mode
+ *
+ *
+ *
+ *
+ */
+void  EnterEcConfig (void);
+
+/**
+ * ExitEcConfig - Force EC exit Config mode
+ *
+ *
+ *
+ *
+ */
+void  ExitEcConfig (void);
+
+/**
+ * ReadEC8 - Read EC register data
+ *
+ *
+ *
+ * @param[in] Address  - EC Register Offset Value
+ * @param[in] Value    - Read Data Buffer
+ *
+ */
+void  ReadEC8 (IN unsigned char Address, IN unsigned char* Value);
+
+/**
+ * WriteEC8 - Write date into EC register
+ *
+ *
+ *
+ * @param[in] Address  - EC Register Offset Value
+ * @param[in] Value    - Write Data Buffer
+ *
+ */
+void  WriteEC8 (IN unsigned char Address, IN unsigned char* Value);
+
+/**
+ * RWEC8 - Read/Write EC register
+ *
+ *
+ *
+ * @param[in] Address    - EC Register Offset Value
+ * @param[in] AndMask    - Data And Mask 8 bits
+ * @param[in] OrMask     - Data OR Mask 8 bits
+ *
+ */
+void  RWEC8 (IN unsigned char Address, IN unsigned char AndMask, IN unsigned char OrMask);
+
+unsigned char IsZoneFuncEnable (IN unsigned short Flag, IN unsigned char func, IN unsigned char Zone);
+void sbECfancontrolservice (IN AMDSBCFG* pConfig);
+void hwmImcInit (IN AMDSBCFG* pConfig);
+void GetSbAcpiMmioBase (OUT unsigned int* AcpiMmioBase);
+void GetSbAcpiPmBase (OUT  unsigned short* AcpiPmBase);
+void SetAcpiPma (IN  unsigned char pmaControl);
+void imcEnableSurebootTimer (IN AMDSBCFG* pConfig);
+void imcDisableSurebootTimer (IN AMDSBCFG* pConfig);
+void imcDisarmSurebootTimer (IN AMDSBCFG* pConfig);
+void hwmSbtsiAutoPolling (IN AMDSBCFG* pConfig);
+void hwmSbtsiAutoPollingOff (IN AMDSBCFG* pConfig);
+void hwmSbtsiAutoPollingPause (IN AMDSBCFG* pConfig);
+void imcSleep (IN AMDSBCFG* pConfig);
+void imcWakeup (IN AMDSBCFG* pConfig);
+void imcIdle (IN AMDSBCFG* pConfig);
+void imcThermalZoneEnable (IN AMDSBCFG* pConfig);
+void ValidateFchVariant (IN AMDSBCFG* pConfig);
+void CheckEfuse (IN AMDSBCFG* pConfig);
+
+/**
+ * Is UMI One Lane GEN1 Mode?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+unsigned char IsUmiOneLaneGen1Mode ( OUT void );
+
+/**
+ * Record SMI Status
+ *
+ *
+ * @retval  Nothing
+ *
+ */
+void RecordSmiStatus ( OUT void );
+// #endif
+
diff --git a/src/vendorcode/amd/cimx/sb900/SbMain.c b/src/vendorcode/amd/cimx/sb900/SbMain.c
new file mode 100755
index 0000000..c6d7954
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SbMain.c
@@ -0,0 +1,295 @@
+/**
+ * @file
+ *
+ * SB Initialization.
+ *
+ * Init IOAPIC/IOMMU/Misc NB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+#ifndef B1_IMAGE
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * sbBeforePciInit - Config Southbridge before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+
+VOID
+sbBeforePciInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n"));
+  RecordSbConfigPtr ( (UINT32) ((UINTN) (pConfig)));
+  CheckEfuse (pConfig);
+  ValidateFchVariant (pConfig);
+  imcEnableSurebootTimer (pConfig);
+  commonInitEarlyPost (pConfig);
+  commonInitEarlyBoot (pConfig);
+#ifndef NO_EC_SUPPORT
+  ecInitBeforePciEnum (pConfig);
+#endif
+  usbInitBeforePciEnum (pConfig);                     // USB POST TIME Only
+  sataInitBeforePciEnum (pConfig);                    // Init SATA class code and PHY
+  gecInitBeforePciEnum (pConfig);                     // Init GEC
+  azaliaInitBeforePciEnum (pConfig);                  // Detect and configure High Definition Audio
+  sbPcieGppEarlyInit (pConfig);                       // Gpp port init
+  abSpecialSetBeforePciEnum (pConfig);
+  hwmInit (pConfig);
+  TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n"));
+}
+
+/**
+ *  sbAfterPciInit - Config Southbridge after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbAfterPciInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
+
+  imcEnableSurebootTimer (pConfig);
+  usbInitAfterPciInit (pConfig);                      // Init USB MMIO
+  sataInitAfterPciEnum (pConfig);                     // SATA port enumeration
+  gecInitAfterPciEnum (pConfig);
+  azaliaInitAfterPciEnum (pConfig);                   // Detect and configure High Definition Audio
+  hwmUpdateData (pConfig);
+  TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
+}
+
+/**
+ *  sbMidPostInit - Config Southbridge during middle of POST
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbMidPostInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbMidPostInit \n"));
+  imcEnableSurebootTimer (pConfig);
+  sataInitMidPost (pConfig);
+  TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbMidPostInit \n"));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  sbLatePost - Prepare Southbridge to boot to OS.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbLatePost (
+  IN       AMDSBCFG* pConfig
+  )
+{
+// UINT16 dwVar;
+  BUILDPARAM  *pStaticOptions;
+  pStaticOptions = &(pConfig->BuildParameters);
+  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
+  commonInitLateBoot (pConfig);
+  sataInitLatePost (pConfig);
+  gecInitLatePost (pConfig);
+  hpetInit (pConfig, pStaticOptions);                 // SB Configure HPET base and enable bit
+#ifndef NO_EC_SUPPORT
+  ecInitLatePost (pConfig);
+#endif
+  sbPcieGppLateInit (pConfig);
+  hwmImcInit (pConfig);
+//  hwmSbtsiAutoPollingOff (pConfig);
+  imcDisarmSurebootTimer (pConfig);
+  usbInitLate (pConfig);                      // Init USB
+  StressResetModeLate (pConfig);                      //
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+
+VOID
+sbBeforePciRestoreInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n"));
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
+  pConfig->S3Resume = 1;
+  ValidateFchVariant (pConfig);
+  commonInitEarlyBoot (pConfig);                      // set /SMBUS/ACPI/IDE/LPC/PCIB
+  abLinkInitBeforePciEnum (pConfig);                  // Set ABCFG registers
+  usbInitBeforePciEnum (pConfig);                     // USB POST TIME Only
+  sataInitBeforePciEnum (pConfig);
+  gecInitBeforePciEnum (pConfig);                     // Init GEC
+  azaliaInitBeforePciEnum (pConfig);                  // Detect and configure High Definition Audio
+  sbPcieGppEarlyInit (pConfig);                       // Gpp port init
+  abSpecialSetBeforePciEnum (pConfig);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+
+VOID
+sbAfterPciRestoreInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  BUILDPARAM  *pStaticOptions;
+
+  pConfig->S3Resume = 1;
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
+  pStaticOptions = &(pConfig->BuildParameters);
+  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
+  commonInitLateBoot (pConfig);
+  sataInitAfterPciEnum (pConfig);
+  gecInitAfterPciEnum (pConfig);
+  azaliaInitAfterPciEnum (pConfig);          // Detect and configure High Definition Audio
+  hpetInit (pConfig, pStaticOptions);        // SB Configure HPET base and enable bit
+  sataInitLatePost (pConfig);
+  c3PopupSetting (pConfig);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
+  hwmInit (pConfig);
+  hwmImcInit (pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * sbSmmAcpiOn - Config Southbridge during ACPI_ON
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbSmmAcpiOn (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
+  // recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows
+  AMDSBCFG*   pTmp;      //lx-dummy for /W4 build
+  pTmp = pConfig;
+
+  // Disable Power Button SMI
+  RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6), 0);
+  // USB workaroud
+  // x00[0] = 1;
+  // x04[31] = 0, x04[0] = 1;
+  // x08[31] = 0, x08[7] = 0;
+  // x0C[31] = 0, x0C[7] = 0,
+  // x10[31] = 0, x10[0] = 1;
+  // x14[31] = 0, x14[0] = 1;
+  // x18[31] = 0, x18[7] = 0;
+  // x1C[31] = 0,
+  // x20[31] = 0,
+  //RWMEM (0x00, AccWidthUint32, 0, BIT0);
+  //RWMEM (0x04, AccWidthUint32, 0, BIT0);
+  //RWMEM (0x08, AccWidthUint32, 0, 0);
+  //RWMEM (0x0C, AccWidthUint32, 0, 0);
+  //RWMEM (0x10, AccWidthUint32, 0, BIT0);
+  //RWMEM (0x14, AccWidthUint32, 0, BIT0);
+  //RWMEM (0x18, AccWidthUint32, 0, 0);
+  //RWMEM (0x1C, AccWidthUint32, 0, 0);
+  //RWMEM (0x20, AccWidthUint32, 0, 0);
+}
+
+#endif
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Call Back routine.
+ *
+ *
+ *
+ * @param[in] Func    Callback ID.
+ * @param[in] Data    Callback specific data.
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ */
+UINTN
+CallBackToOEM (
+  IN       UINT32 Func,
+  IN       UINT32 Data,
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT32 Result;
+  Result = 0;
+  if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result;
+  TRACE ((DMSG_SB_TRACE, "Calling %lx ( % x, % x, % x)\n", pConfig->StdHeader.CalloutPtr, Func, Data, pConfig));
+  Result = (*(SBCIM_HOOK_ENTRY*) (UINTN)&pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig);
+
+  TRACE ((DMSG_SB_TRACE, "SB Hook Status [ % x]\n", Result));
+  return Result;
+}
+
+
diff --git a/src/vendorcode/amd/cimx/sb900/SbModInf.c b/src/vendorcode/amd/cimx/sb900/SbModInf.c
new file mode 100755
index 0000000..6efedaf
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SbModInf.c
@@ -0,0 +1,74 @@
+/**
+ * @file
+ *
+ *  Function dispatcher.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/// module header
+VOLATILE AMD_MODULE_HEADER mNbModuleHeader = {
+  'DOM$',                        ///< Standard AMD module signature
+  CIMX_SB_ID,                    ///< Chipset ID
+  CIMX_SB_REVISION,              ///< CIMx version
+  AmdSbDispatcher,               ///< Pointer to the module entry
+  NULL                           ///< Pointer link to next module header
+};
diff --git a/src/vendorcode/amd/cimx/sb900/SbPeLib.c b/src/vendorcode/amd/cimx/sb900/SbPeLib.c
new file mode 100755
index 0000000..e65bc05
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SbPeLib.c
@@ -0,0 +1,480 @@
+/**
+ * @file
+ *
+ * Southbridge IO access common routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+/**
+ * Read Southbridge Revision ID cie Base
+ *
+ *
+ * @retval  0xXXXXXXXX   Revision ID
+ *
+ */
+UINT8
+getRevisionID (
+  OUT VOID
+  )
+{
+  UINT8  dbVar0;
+  ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0);
+  return dbVar0;
+}
+
+/**
+ * Is SB A11?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsSbA11 (
+  OUT VOID
+  )
+{
+  return ( getRevisionID () == AMD_SB_A11 );
+}
+
+/**
+ * Is SB A12?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsSbA12 (
+  OUT VOID
+  )
+{
+  return ( getRevisionID () == AMD_SB_A12 );
+}
+
+/**
+ * Is SB A12 Plus?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsSbA12Plus (
+  OUT VOID
+  )
+{
+  return ( getRevisionID () >= AMD_SB_A12 );
+}
+
+/**
+ * Is SB A13 Plus?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsSbA13Plus (
+  OUT VOID
+  )
+{
+  return ( getRevisionID () >= AMD_SB_A13 );
+}
+
+/**
+ * Is External Clock Mode?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsExternalClockMode (
+  OUT VOID
+  )
+{
+  return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80) & BIT4) == 0) );
+}
+
+/**
+ * Is LPC Rom?
+ *
+ *
+ * @retval  TRUE or FALSE
+ *
+ */
+BOOLEAN
+IsLpcRom (
+  OUT VOID
+  )
+{
+  return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80) & BIT1) == 0) );
+}
+
+/**
+ * Memory Copy
+ *
+ *
+ * @retval  VOID
+ *
+ */
+VOID
+MemoryCopy (
+  IN       UINT8 *Dest,
+  IN       UINT8 *Source,
+  IN       UINTN Size
+  )
+{
+  UINTN i;
+  for ( i = 0; i < Size; i++  ) {
+    *Dest = *Source;
+    Dest++;
+    Source++;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * programPciByteTable - Program PCI register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pPciByteTable    - Table data pointer
+ * @param[in] dwTableSize      - Table length
+ *
+ */
+VOID
+programPciByteTable (
+  IN       REG8MASK* pPciByteTable,
+  IN       UINT16 dwTableSize
+  )
+{
+  UINT8  i;
+  UINT8  dbBusNo;
+  UINT8  dbDevFnNo;
+  UINT32  ddBDFR;
+
+  dbBusNo = pPciByteTable->bRegIndex;
+  dbDevFnNo = pPciByteTable->bANDMask;
+  pPciByteTable++;
+
+  for ( i = 1; i < dwTableSize; i++ ) {
+    if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) {
+      pPciByteTable++;
+      dbBusNo = pPciByteTable->bRegIndex;
+      dbDevFnNo = pPciByteTable->bANDMask;
+      pPciByteTable++;
+      i++;
+    } else {
+      ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;
+      TRACE ((DMSG_SB_TRACE, "PFA = %X  AND = %X, OR = %X", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask));
+      RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);
+      pPciByteTable++;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pAcpiTbl   - Table data pointer
+ *
+ */
+VOID
+programSbAcpiMmioTbl (
+  IN       AcpiRegWrite *pAcpiTbl
+  )
+{
+  UINT8 i;
+  UINT32 ddtempVar;
+  if (pAcpiTbl != NULL) {
+    if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataANDMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) {
+      // Signature Checking
+      pAcpiTbl++;
+      for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) {
+        ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
+        RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask);
+        pAcpiTbl++;
+      }
+    }
+  }
+}
+
+/**
+ * getChipSysMode - Get Chip status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ *   StrapStatus [15.0] - Hudson-2 chip Strap Status
+ *    @li <b>0001</b> - Not USED FWH
+ *    @li <b>0002</b> - Not USED LPC ROM
+ *    @li <b>0004</b> - EC enabled
+ *    @li <b>0008</b> - Reserved
+ *    @li <b>0010</b> - Internal Clock mode
+ *
+ */
+VOID
+getChipSysMode (
+  IN       VOID* Value
+  )
+{
+  ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value);
+}
+
+/**
+ * isImcEnabled - Is IMC Enabled
+ * @retval  TRUE for IMC Enabled; FALSE for IMC Disabled
+ */
+BOOLEAN
+isImcEnabled (
+  )
+{
+  UINT8   dbSysConfig;
+  getChipSysMode (&dbSysConfig);
+  if (dbSysConfig & ChipSysEcEnable) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read Southbridge CIMx configuration structure pointer
+ *
+ *
+ *
+ * @retval  0xXXXXXXXX   CIMx configuration structure pointer.
+ *
+ */
+AMDSBCFG*
+getConfigPointer (
+  OUT VOID
+  )
+{
+  UINT8  dbReg;
+  UINT8  dbValue;
+  UINT8  i;
+  UINT32  ddValue;
+  ddValue = 0;
+  dbReg = SB_ECMOS_REG08;
+
+  for ( i = 0; i <= 3; i++ ) {
+    WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
+    ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue);
+    ddValue |= (dbValue << (i * 8));
+    dbReg++;
+  }
+  return ( (AMDSBCFG*) (UINTN)ddValue);
+}
+
+/**
+ * getEfuseStatue - Get Efuse status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ *
+ */
+VOID
+getEfuseStatus (
+  IN       VOID* Value
+  )
+{
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5);
+  WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value);
+  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0);
+}
+
+/**
+ * getEfuseByte - Get Efuse Byte
+ *
+ *
+ * @param[in] Index - Efuse Index value
+ *
+ */
+UINT8
+getEfuseByte (
+  IN       UINT8 Index
+  )
+{
+  UINT8 Data;
+  WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, &Index);
+  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, &Data);
+  return Data;
+}
+
+
+/**
+ * SbResetGppDevice - Toggle GEVENT4 to assert/deassert GPP device reset
+ *
+ *
+ * @param[in] ResetBlock - PCIE reset for SB GPP or NB PCIE
+ * @param[in] ResetOp    - Assert or deassert PCIE reset
+ *
+ */
+VOID
+SbResetPcie (
+  IN       RESET_BLOCK  ResetBlock,
+  IN       RESET_OP     ResetOp
+  )
+{
+
+  if (ResetBlock == NbBlock) {
+    if (ResetOp == AssertReset) {
+      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFF, BIT4);
+    } else if (ResetOp == DeassertReset) {
+      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, ~BIT4, 0);
+    }
+  } else if (ResetBlock == SbBlock) {
+    RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG04, AccWidthUint8, ~(BIT1 + BIT0), 0x02);
+    if (ResetOp == AssertReset) {
+      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GEVENT_REG04, AccWidthUint8, ~BIT5, 0);
+      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBF, AccWidthUint8, 0xFF, BIT4);
+    } else if (ResetOp == DeassertReset) {
+      RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBF, AccWidthUint8, ~BIT4, 0);
+      RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GEVENT_REG04, AccWidthUint8, 0xff, BIT5);
+    }
+  }
+}
+
+
+/**
+ * sbGppTogglePcieReset - Toggle PCIE_RST2#
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+sbGppTogglePcieReset (
+  IN     AMDSBCFG*   pConfig
+  )
+{
+  if (pConfig->GppToggleReset) {
+    SbResetPcie (SbBlock, AssertReset);
+    SbStall (500);
+    SbResetPcie (SbBlock, DeassertReset);
+  }
+}
+
+/**
+ * sbSpiUnlock - Sb SPI Unlock
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+sbSpiUnlock (
+  IN     AMDSBCFG*   pConfig
+  )
+{
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG50, AccWidthUint32, ~(BIT0 + BIT1), 0);
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG54, AccWidthUint32, ~(BIT0 + BIT1), 0);
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG58, AccWidthUint32, ~(BIT0 + BIT1), 0);
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG5C, AccWidthUint32, ~(BIT0 + BIT1), 0);
+  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32, ~(BIT22 + BIT23), (BIT22 + BIT23));
+}
+
+/**
+ * sbSpilock - Sb SPI lock
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+sbSpilock (
+  IN     AMDSBCFG*   pConfig
+  )
+{
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG50, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG54, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG58, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG5C, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
+  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32, ~(BIT22 + BIT23), 0);
+}
+
+/**
+ * TurnOffCG2
+ *
+ *
+ * @retval  VOID
+ *
+ */
+VOID
+TurnOffCG2 (
+  OUT VOID
+  )
+{
+  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccWidthUint8, ~BIT6, 0);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x0F, 0xA0);
+  RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + 0x41, AccWidthUint8, ~(BIT1 + BIT0), (BIT1 + BIT0));
+  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccWidthUint8, ~( BIT4), (BIT4));
+  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccWidthUint8, ~(BIT6), (BIT6));
+  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint8, ~BIT6, BIT6);
+  RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccWidthUint8, ~BIT6, BIT6);
+}
+
+/**
+ * BackUpCG2
+ *
+ *
+ * @retval  VOID
+ *
+ */
+VOID
+BackUpCG2 (
+  OUT VOID
+  )
+{
+  UINT8 dByte;
+  ReadMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccWidthUint8, &dByte);
+  if (dByte & BIT6) {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccWidthUint8, ~(BIT6), (0));
+  }
+}
diff --git a/src/vendorcode/amd/cimx/sb900/SbPor.c b/src/vendorcode/amd/cimx/sb900/SbPor.c
new file mode 100755
index 0000000..3161d9d
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SbPor.c
@@ -0,0 +1,736 @@
+
+/**
+ * @file
+ *
+ * Southbridge Init during POWER-ON
+ *
+ * Prepare Southbridge environment during power on stage.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+#include    "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+
+/**
+ * sbPorInitPciTable - PCI device registers initial during the power on stage.
+ *
+ *
+ *
+ *
+ */
+REG8MASK sbPorInitPciTable[] =
+{
+  // SATA device
+  {0x00, SATA_BUS_DEV_FUN, 0},
+  {SB_SATA_REG84 + 3, ~BIT2, 0},
+  {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
+  {0xFF, 0xFF, 0xFF},
+  // LPC Device (Bus 0, Dev 20, Func 3)
+  {0x00, LPC_BUS_DEV_FUN, 0},
+  {SB_LPC_REG44, 0xFF, BIT6 + BIT7}, //Enable COM1 and COM2
+  {SB_LPC_REG47, 0xFF, BIT5},
+  {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
+  {SB_LPC_REG7C, 0x00, BIT0 + BIT2},
+  {SB_LPC_REG78, 0xF0, BIT2 + BIT3},     // Enable LDRQ pin
+  {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
+  // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
+  // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
+  {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
+  {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
+  {SB_LPC_REGA4, ~ BIT0, BIT0}, //[BUG Fix] Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined
+  {0xFF, 0xFF, 0xFF},
+  // P2P Bridge (Bus 0, Dev 20, Func 4)
+  {0x00, PCIB_BUS_DEV_FUN, 0},
+  {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
+  // ENH230012: Disable P2P bridge decoder for IO address 0x1000-0x1FFF in SBPOR
+  // ENH260809: Add PCI port 80 support in Hudson-2/3
+#ifdef SB_PCIB_PORT_80_SUPPORT
+  {SB_PCIB_REG1C, 0x00, 0xF0},
+  {SB_PCIB_REG1D, 0x00, 0x00},
+  {SB_PCIB_REG04, 0x00, 0x21},
+#endif
+  {SB_PCIB_REG40, 0xDF, 0x20},
+  {SB_PCIB_REG50, 0x02, 0x01},
+  {0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
+ *
+ *
+ *
+ *
+ */
+AcpiRegWrite sbPmioPorInitTable[] =
+{
+  {00, 00, 0xB0, 0xAC}, // Signature
+  {MISC_BASE >> 8,  SB_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12]
+  //RPR 8.9 USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock.
+  {MISC_BASE >> 8,  SB_MISC_REG40, 0xEF, 0x00},
+//  {MISC_BASE >> 8,  0x24 + 2, 0xFF, 0x20}, Testing CPU clk strength
+  {PMIO_BASE >> 8,  SB_PMIOA_REG5D, 0x00, BIT0},
+  {PMIO_BASE >> 8,  SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
+  {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG28, 0xFF, BIT0 + BIT2},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG44 + 3, 0x67, BIT7 + BIT3}, // 2.5 Enable Boot Timer
+  {PMIO_BASE >> 8,  SB_PMIOA_REG48, 0xFF, BIT0},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG00, 0xFF, 0x0E},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG00 + 2, 0xFF, 0x40},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG00 + 3, 0xFF, 0x08},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
+  {PMIO_BASE >> 8,  SB_PMIOA_REGEC, 0xFD, BIT1},
+  //{PMIO_BASE >> 8,  SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG08 + 1, 0xFF, BIT0},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG04 + 3, 0xFD, BIT1},
+  {PMIO_BASE >> 8,  SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
+  {PMIO_BASE >> 8,  SB_PMIOA_REGF0, ~BIT2, 0x00},
+  // RPR GEC I/O Termination Setting
+  // PM_Reg 0xF6 = Power-on default setting
+  // PM_Reg 0xF7 = Power-on default setting
+  // PM_Reg 0xF8 = 0x6C
+  // PM_Reg 0xF9 = 0x21
+  // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS
+  {PMIO_BASE >> 8, SB_PMIOA_REGF8,     0x00, 0x6C},
+  {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x07},
+  {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
+  // PRP GEC -end
+  {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xee, 0x04},      // Release NB_PCIE_RST
+  {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
+
+  {PMIO_BASE >> 8,  SB_PMIOA_REGBE, 0xDF, BIT5},
+
+  //OBS200280
+  //{PMIO_BASE >> 8,  SB_PMIOA_REGBE, 0xFF, BIT1},
+
+
+  {0xFF, 0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * sbPowerOnInit - Config Southbridge during power on stage.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbPowerOnInit (
+  IN       AMDSBCFG* pConfig
+  )
+{
+  UINT8   dbPortStatus;
+  //UINT8   dbSysConfig;
+  UINT32  abValue;
+  UINT32  abValue2;
+  UINT8   dbValue;
+  UINT8   dbEfuse;
+  UINT32   dbSpiMode;
+  UINT16  dwAsfPort;
+  UINT16  smbusBase;
+  UINT8   cimSataMode;
+//  UINT8   cimSpiFastReadEnable;
+//  UINT8   cimSpiFastReadSpeed;
+  UINT8   cimSataInternal100Spread;
+  UINT8   indexValue;
+  UINT32  ddValue;
+  UINT8  SataPortNum;
+  UINT8     XhciEfuse;
+  XhciEfuse = XHCI_EFUSE_LOCATION;
+
+  cimSataMode = pConfig->SATAMODE.SataModeReg;
+//  if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {
+//    cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
+//  } else {
+//    cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
+//  }
+//  cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
+  cimSataInternal100Spread = ( UINT8 ) pConfig->SataInternal100Spread;
+
+#if  SB_CIMx_PARAMETER == 0
+  cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
+  cimSataMode = (UINT8) ((cimSataMode & 0x0F) | cimSataClkModeDefault);
+  cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
+  cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
+  cimSataInternal100Spread = SataInternal100SpreadDefault;
+#endif
+
+  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
+
+// Hudson-2 Only Enabled (Mmio_mem_enablr)  // Default value is correct
+  RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
+
+  RWPMIO (0xD3, AccWidthUint8, ~BIT4, 0);
+  RWPMIO (0xD3, AccWidthUint8, ~BIT4, BIT4);
+
+  if ( pConfig->Cg2Pll == 1 ) {
+    TurnOffCG2 ();
+    pConfig->SATAMODE.SataMode.SataClkMode = 0x0a;
+  }
+
+  //enable CF9
+  RWPMIO (0xD2, AccWidthUint8, ~BIT6, 0);
+
+// Set A-Link bridge access address. This address is set at device 14h, function 0,
+// register 0f0h.   This is an I/O address. The I/O address must be on 16-byte boundary.
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
+  writeAlink (0x80000004, 0x04);     // RPR 4.2 Enable Hudson-2 to issue memory read/write requests in the upstream direction
+  abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29));      // RPR 4.5 Disable the credit variable in the downstream arbitration equation
+  abValue = abValue | BIT0;
+  writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
+  writeAlink (0x30, 0x10);         // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
+  writeAlink (0x34, readAlink (0x34) | BIT9);
+  rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00);
+
+  // Enable external Stickybit register reset feature
+  //writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x30);
+  //abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));
+  //abValue |= BIT6 + BIT5;
+  //writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);
+
+  // Configure UMI target link speed
+  dbEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
+  getEfuseStatus (&dbEfuse);
+  if ( dbEfuse & BIT0 ) {
+    pConfig->NbSbGen2 = 0;
+  }
+
+  dbEfuse = FCH_Variant_EFUSE_LOCATION;
+  getEfuseStatus (&dbEfuse);
+  if ((dbEfuse == 0x07) || (dbEfuse == 0x08)) {
+    pConfig->NbSbGen2 = 0;
+  }
+
+  if (pConfig->NbSbGen2) {
+    abValue = 2;
+    abValue2 = BIT0;
+  } else {
+    abValue = 1;
+    abValue2 = 0;
+  }
+  rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFE, abValue2);
+  rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, abValue);
+
+  if (pConfig->sdbEnable) {
+    rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT12, 0x00);
+    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 0, AccWidthUint8, 0, pConfig->Debug_Reg00);
+    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 2, AccWidthUint8, 0, pConfig->Debug_Reg02);
+    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 4, AccWidthUint8, 0, pConfig->Debug_Reg04);
+    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 1, AccWidthUint8, 0, pConfig->Debug_Reg01);
+    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 3, AccWidthUint8, 0, pConfig->Debug_Reg03);
+    RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 5, AccWidthUint8, 0, pConfig->Debug_Reg05);
+  }
+
+// Set Build option into SB
+  WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
+// Enabled SMBUS0/SMBUS1 (ASF) Base Address
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus1BaseAddress) + BIT0);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0); //clear BIT[2:1]
+  smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
+  dbValue = 0x00;
+  WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
+
+  dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
+  getEfuseStatus (&dbEfuse);
+
+  programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
+
+  //RPR 3.4 Enabling ClkRun Function
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, ~ BIT2, BIT2);
+  //BUG265683: Mismatch clkrun enable register setting between RPR and CIMX code
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGD0, AccWidthUint8, ~ BIT2, 0);
+
+  SataPortNum = 0;
+  for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
+    SbStall (2);
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
+    SbStall (2);
+  }
+
+  dbValue = 0x0A;
+  WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
+  ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+  dbValue &= 0xEF;
+  WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+
+  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
+  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 0 );
+  if (pConfig->BuildParameters.SpiSpeed) {
+    RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT13 + BIT12), ((pConfig->BuildParameters.SpiSpeed - 1 ) << 12));
+  }
+  if (pConfig->BuildParameters.SpiFastSpeed) {
+    RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT15 + BIT14), ((pConfig->BuildParameters.SpiFastSpeed - 1 ) << 14));
+  }
+  //if (pConfig->BuildParameters.SpiBurstWrite) {
+  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG1C, AccWidthUint32 | S3_SAVE, ~(BIT10), ((pConfig->BuildParameters.SpiBurstWrite) << 10));
+  //}
+  dbSpiMode = pConfig->BuildParameters.SpiMode;
+  if (pConfig->BuildParameters.SpiMode) {
+    if ((dbSpiMode == SB_SPI_MODE_QUAL_114) || (dbSpiMode == SB_SPI_MODE_QUAL_112) || (dbSpiMode == SB_SPI_MODE_QUAL_144) || (dbSpiMode == SB_SPI_MODE_QUAL_122)) {
+    //  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFF0000, 0x013e);
+    //  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0x80 );
+    //  RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFEFFFF, 0x10000);
+    //  SbStall (1000);
+    }
+    RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, ~( BIT18 + BIT29 + BIT30), ((pConfig->BuildParameters.SpiMode & 1) << 18) + ((pConfig->BuildParameters.SpiMode & 6) << 28));
+  }
+
+//  if ( cimSpiFastReadSpeed ) {
+//    RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
+//  }
+  //Program power on pci init table
+  programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
+
+  programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
+
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0);
+
+  if (pConfig->SATAMODE.SataModeReg == 0) {
+    pConfig->SATAMODE.SataModeReg = (pConfig->SATAMODE.SataMode.SataController << 0) \
+      + (pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt << 1) \
+      + (pConfig->SATAMODE.SataMode.SataSetMaxGen2 << 2) \
+      + (pConfig->SATAMODE.SataMode.SataIdeCombinedMode << 3) \
+      + (pConfig->SATAMODE.SataMode.SataClkMode << 4);
+  }
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x00, pConfig->SATAMODE.SataModeReg);
+
+  if (dbEfuse & BIT0) {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
+  }
+
+  ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
+  if ( ((dbPortStatus & 0xF0) == 0x10) ) {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
+  }
+
+  if ( pConfig->BuildParameters.LegacyFree ) {
+    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+  } else {
+    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
+  }
+
+  if ( cimSataInternal100Spread ) {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, 0xFF, BIT4);
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFB, 0x00);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, ~BIT4, 0x00);
+  }
+  // Toggle GEVENT4 to reset all GPP devices
+  sbGppTogglePcieReset (pConfig);
+
+  if ( cimSataInternal100Spread ) {
+    RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFF, 0x04);
+  }
+
+  dbValue = 0x08;
+  WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
+  ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+  if ( !pConfig->BuildParameters.EcKbd ) {
+    // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
+    dbValue = dbValue | 0x0A;
+  }
+  WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+
+  dbValue = 0x09;
+  WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
+  ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+  if ( !pConfig->BuildParameters.EcKbd ) {
+    // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
+    dbValue = dbValue & 0xF9;
+  }
+  if ( pConfig->BuildParameters.LegacyFree ) {
+    // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
+    dbValue = dbValue & 0x9F;
+  }
+  // Enabled IRQ input
+  dbValue = dbValue | BIT4;
+  WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+
+  dwAsfPort = ((UINT16) pConfig->BuildParameters.Smbus1BaseAddress & 0xFFF0);
+  if ( dwAsfPort != 0 ) {
+    RWIO (dwAsfPort + 0x0E, AccWidthUint8, 0x0, 0x70);  // 0x70 will change to EQU ( Remote control address)
+  }
+
+#ifndef NO_EC_SUPPORT
+  getChipSysMode (&dbPortStatus);
+  if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
+    // EC is disabled by jumper setting or board config
+    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
+  } else {
+    RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
+    ecPowerOnInit ( pConfig);
+    imcSleep ( pConfig);
+  }
+#endif
+
+
+  ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+  ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+  if ( ddValue == 0x78121022 ) {
+//
+// First Xhci controller.
+//
+    ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+    ddValue = 0;
+    indexValue = XHCI_REGISTER_BAR03;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    ddValue = (UINT32) dbValue;
+
+    indexValue = XHCI_REGISTER_BAR02;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    ddValue <<= 8;
+    ddValue |= (UINT32) dbValue;
+
+    indexValue = XHCI_REGISTER_BAR01;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    ddValue <<= 8;
+    ddValue |= (UINT32) dbValue;
+
+    indexValue = XHCI_REGISTER_BAR00;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    ddValue <<= 8;
+    ddValue |= (UINT32) dbValue;
+    WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
+
+    indexValue = XHCI_REGISTER_04H;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
+
+    indexValue = XHCI_REGISTER_0CH;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
+
+    indexValue = XHCI_REGISTER_3CH;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
+//
+// Second Xhci controller.
+//
+    ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+    ddValue = 0;
+    indexValue = XHCI1_REGISTER_BAR03;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    ddValue = (UINT32) dbValue;
+
+    indexValue = XHCI1_REGISTER_BAR02;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    ddValue <<= 8;
+    ddValue |= (UINT32) dbValue;
+
+    indexValue = XHCI1_REGISTER_BAR01;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    ddValue <<= 8;
+    ddValue |= (UINT32) dbValue;
+
+    indexValue = XHCI1_REGISTER_BAR00;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    ddValue <<= 8;
+    ddValue |= (UINT32) dbValue;
+    WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
+
+    indexValue = XHCI1_REGISTER_04H;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
+
+    indexValue = XHCI1_REGISTER_0CH;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
+
+    indexValue = XHCI1_REGISTER_3CH;
+    WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+    ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+    WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
+  }
+  // RPR 3.2 Enabling SPI ROM Prefetch
+  // Set LPC cfg 0xBA bit 8
+  RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT8);
+  if (IsSbA12Plus ()) {
+    // Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1 for A12 and above
+    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT7);
+  }
+#ifdef XHCI_SUPPORT
+#ifdef XHCI_INIT_IN_ROM_SUPPORT
+  if ( pConfig->XhciSwitch == 1 ) {
+    if ( pConfig->S3Resume == 0 ) {
+      XhciEarlyInit ();
+    } else {
+      XhciInitIndirectReg ();
+    }
+  } else {
+    // for power saving.
+
+    // add Efuse checking for Xhci enable/disable
+    getEfuseStatus (&XhciEfuse);
+    if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
+      RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFBFF, 0x0);
+    }
+  }
+#endif
+#endif
+}
+
+#ifdef XHCI_SUPPORT
+VOID
+XhciInitIndirectReg (
+  )
+{
+  UINT32 ddDrivingStrength;
+  UINT32 port;
+  ddDrivingStrength = 0;
+  port = 0;
+#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
+  RWXhciIndReg ( 0x40000018, 0xFFFFFFFF, 0x00000030);
+#endif
+//
+// RPR SuperSpeed PHY Configuration (adaptation mode setting)
+//
+  RWXhciIndReg ( SB_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021);
+  RWXhciIndReg ( SB_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021);
+//
+// RPR SuperSpeed PHY Configuration (CR phase and frequency filter settings)
+//
+  RWXhciIndReg ( SB_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A);
+  RWXhciIndReg ( SB_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A);
+
+//
+// RPR BLM Meaasge
+//
+  RWXhciIndReg ( SB_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000);
+//
+// RPR 8.13 xHCI USB 2.0 PHY Settings
+// Step 1 is done by hardware default
+// Step 2
+#ifdef USB3_EHCI_DRIVING_STRENGTH
+  for (port = 0; port < 4; port ++) {
+    ddDrivingStrength = (USB3_EHCI_DRIVING_STRENGTH >> (port * 4)) & 0xF;
+    if (ddDrivingStrength & BIT3) {
+      ddDrivingStrength &= 0x07;
+      if (port < 2) {
+        RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
+        RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
+      } else {
+        RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
+        RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
+      }
+    }
+  }
+#endif
+
+// Step 3
+  if (IsSbA11 ()) {
+    RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x00 << 8)));
+    RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x15 << 8)));
+  } else {
+    RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)));
+    RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)));
+  }
+}
+
+VOID
+XhciEarlyInit (
+  )
+{
+  UINT16  BcdAddress;
+  UINT16  BcdSize;
+  UINT16  AcdAddress;
+  UINT16  AcdSize;
+  UINT16  FwAddress;
+  UINT16  FwSize;
+  UINTN   XhciFwStarting;
+  UINT32  SpiValidBase;
+  UINT32  RegData;
+  UINT16  i;
+
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0x00000000, 0x00400700);
+  SbStall (20);
+//
+// Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
+//
+  GetRomSigPtr (&XhciFwStarting);
+
+  if (XhciFwStarting == 0) {
+    return;
+  }
+
+  XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
+  if (IsLpcRom ()) {
+  //XHCI firmware re-load
+    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, ~BIT2, (BIT2 + BIT1 + BIT0));
+    RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, 0x00000FFF, (UINT32) (XhciFwStarting));
+  }
+//
+// RPR Enable SuperSpeed receive special error case logic. 0x20 bit8
+// RPR Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
+// Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
+//
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, 0xFFFFF8FF, 0x00000700);
+//
+// RPR SuperSpeed PHY Configuration (adaptation timer setting)
+//
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
+  //RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
+
+//
+// Step 1. to enable Xhci IO and Firmware load mode
+//
+
+#ifdef XHCI_SUPPORT_ONE_CONTROLLER
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000001);
+#else
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000003);
+#endif
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xEFFFFFFF, 0x10000000);
+
+//
+// Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
+//
+
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccWidthUint32, 0x00000000, (SPI_HEAD_LENGTH << 16));
+
+  BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
+  BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccWidthUint16, 0x0000, BcdAddress);
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccWidthUint16, 0x0000, BcdSize);
+
+  AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
+  AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccWidthUint16, 0x0000, AcdAddress);
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccWidthUint16, 0x0000, AcdSize);
+
+  SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccWidthUint32, 0x00000000, SpiValidBase);
+
+    //
+    // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
+    //
+  for (i = 0; i < SPI_HEAD_LENGTH; i++) {
+    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + i));
+  }
+
+  for (i = 0; i < BcdSize; i++) {
+    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + i));
+  }
+
+  for (i = 0; i < AcdSize; i++) {
+    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + i));
+  }
+
+//
+// Step 3. to enable the instruction RAM preload functionality.
+//
+  FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
+  FwAddress += 2;
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccWidthUint16, 0x0000, FwAddress);
+
+  FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccWidthUint16, 0x0000, FwSize);
+
+    //
+    // Set the starting address offset for Instruction RAM preload.
+    //
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccWidthUint16, 0x0000, 0);
+
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, BIT29);
+
+  for (;;) {
+    ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
+    if (RegData & BIT30) break;
+  }
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, 0);
+
+//
+// Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
+//
+
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PLL_RESET, 0); //Release U3PLLreset
+  for (;;) {
+    ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
+    if (RegData & U3PLL_LOCK) break;
+  }
+
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PHY_RESET, 0); //Release U3PHY
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3CORE_RESET, 0); //Release core reset
+
+// RPR 8.8 SuperSpeed PHY Configuration, it is only for A11.
+  if (IsSbA11 ()) {
+    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
+    RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
+  }
+
+  XhciInitIndirectReg ();
+
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5), 0); // Disable Device 22
+  RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7), BIT7); // Enable 2.0 devices
+  //if (!(pConfig->S4Resume)) {
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
+  //}
+//
+// Step 5.
+//
+  RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
+}
+#endif
diff --git a/src/vendorcode/amd/cimx/sb900/SbSubFun.h b/src/vendorcode/amd/cimx/sb900/SbSubFun.h
new file mode 100755
index 0000000..3349c1b
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SbSubFun.h
@@ -0,0 +1,607 @@
+/**
+ * @file
+ *
+ * Southbridge CIMx Function Support Define (All)
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*********************************************************************************/
+
+// Southbridge SBMAIN Routines
+
+/**
+ * Southbridge Main Function Public Function
+ *
+ */
+
+/**
+ * sbBeforePciInit - Config Southbridge before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbBeforePciInit (IN AMDSBCFG* pConfig);
+
+
+/**
+ * sbAfterPciInit - Config Southbridge after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbAfterPciInit (IN AMDSBCFG* pConfig);
+
+/**
+ *  sbMidPostInit - Config Southbridge during middle of POST
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbMidPostInit (IN AMDSBCFG* pConfig);
+
+/**
+ *  sbLatePost - Prepare Southbridge to boot to OS.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbLatePost (IN AMDSBCFG* pConfig);
+
+/**
+ * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbBeforePciRestoreInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbAfterPciRestoreInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbSmmAcpiOn - Config Southbridge during ACPI_ON
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbSmmAcpiOn (IN AMDSBCFG* pConfig);
+
+/**
+ * CallBackToOEM - Call Back routine.
+ *
+ *
+ *
+ * @param[in] Func    Callback ID.
+ * @param[in] Data    Callback specific data.
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ */
+unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig);
+
+
+// Southbridge SBPOR Routines
+
+/**
+ * Southbridge power-on initial Public Function
+ *
+ */
+
+/**
+ * sbPowerOnInit - Config Southbridge during power on stage.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbPowerOnInit (IN AMDSBCFG* pConfig);
+
+/**
+ * XhciEarlyInit - XhciEarlyInit.
+ *
+ *
+ *
+ *
+ *
+ */
+void XhciEarlyInit (void);
+
+/**
+ * XhciInitIndirectReg - XhciInitIndirectReg.
+ *
+ *
+ *
+ *
+ *
+ */
+void XhciInitIndirectReg (void);
+
+
+// Southbridge Common Routines
+
+/**
+ * Southbridge Common Public Function
+ *
+ */
+
+/**
+ * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
+ *
+ *    This settings should be done during S3 resume also
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void commonInitEarlyBoot (IN AMDSBCFG* pConfig);
+
+/**
+ * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
+ *
+ *    This settings might not program during S3 resume
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void commonInitEarlyPost (IN AMDSBCFG* pConfig);
+
+/**
+ * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void commonInitLateBoot (IN AMDSBCFG* pConfig);
+
+/**
+ * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * hpetInit - Program Southbridge HPET function
+ *
+ *  ** Eric
+ *
+ * @param[in] pConfig         Southbridge configuration structure pointer.
+ * @param[in] pStaticOptions  Platform build configuration table.
+ *
+ */
+void hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions);
+
+/**
+ * c3PopupSetting - Program Southbridge C state function
+ *
+ *  ** Eric
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+void c3PopupSetting (IN AMDSBCFG* pConfig);
+
+/**
+ * GcpuRelatedSetting - Program GCPU C related function
+ *
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+void GcpuRelatedSetting (IN AMDSBCFG* pConfig);
+
+/**
+ * MtC1eEnable - Program Mt C1E Enable Function
+ *
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+void MtC1eEnable (IN AMDSBCFG* pConfig);
+
+/**
+ * Southbridge Common Private Function
+ *
+ */
+
+/**
+ * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+// Southbridge SATA Routines
+
+/**
+ * Southbridge SATA Controller Public Function
+ *
+ */
+
+/**
+ * sataInitMidPost - Config SATA controller in Middle POST.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sataInitMidPost (IN AMDSBCFG* pConfig);
+
+/**
+ * sataInitAfterPciEnum - Config SATA controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void  sataInitAfterPciEnum (IN AMDSBCFG*   pConfig);
+
+/**
+ * sataInitBeforePciEnum - Config SATA controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void  sataInitBeforePciEnum (IN AMDSBCFG*  pConfig);
+
+/**
+ * sataInitLatePost - Prepare SATA controller to boot to OS.
+ *
+ *              - Set class ID to AHCI (if set to AHCI * Mode)
+ *              - Enable AHCI interrupt
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void  sataInitLatePost (IN AMDSBCFG* pConfig);
+
+// Southbridge GEC Routines
+
+/**
+ * Southbridge GEC Controller Public Function
+ *
+ */
+
+/**
+ * gecInitBeforePciEnum - Config GEC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void gecInitBeforePciEnum (IN AMDSBCFG*   pConfig);
+
+/**
+ * gecInitAfterPciEnum - Config GEC controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void gecInitAfterPciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * gecInitLatePost - Prepare GEC controller to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void gecInitLatePost (IN AMDSBCFG* pConfig);
+
+// Southbridge USB Routines
+
+/**
+ * Southbridge USB Controller Public Function
+ *
+ */
+
+/**
+ * Config USB controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void usbInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * Config USB controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void usbInitAfterPciInit (IN AMDSBCFG* pConfig);
+
+/**
+ * Config USB controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void usbInitLate (IN AMDSBCFG* pConfig);
+
+/**
+ * Config USB1 EHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+
+// Southbridge SMI Service Routines (SMM.C)
+
+/**
+ * Southbridge SMI Service Routines Public Function
+ *
+ */
+
+/**
+ * Southbridge SMI service module
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbSmmService (IN AMDSBCFG* pConfig);
+
+/**
+ * softwareSMIservice - Software SMI service
+ *
+ *  ** Eric
+ *
+ * @param[in] VOID Southbridge software SMI service ID.
+ *
+ */
+void softwareSMIservice (IN void);
+
+// Southbridge GPP Controller Routines
+
+/**
+ * Southbridge GPP Controller Routines Public Function
+ *
+ */
+
+/**
+ * GPP early programming and link training. On exit all populated EPs should be fully operational.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbPcieGppEarlyInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbPcieGppLateInit - Late PCIE initialization for Hudson-2 GPP component
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbPcieGppLateInit (IN AMDSBCFG* pConfig);
+
+// Southbridge HD Controller Routines (AZALIA.C)
+
+/**
+ * Southbridge HD Controller Routines (AZALIA.C) Public Function
+ *
+ */
+
+/**
+ * Config HD Audio Before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * Config HD Audio after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig);
+
+
+// Southbridge EC Routines
+
+#ifndef NO_EC_SUPPORT
+/**
+ * Southbridge EC Controller Public Function
+ *
+ */
+
+/**
+ * Config EC controller during power-on
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  ecPowerOnInit (IN AMDSBCFG* pConfig);
+
+/**
+ * Config EC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  ecInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * Prepare EC controller to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  ecInitLatePost (IN AMDSBCFG* pConfig);
+
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ * @retval        TRUE   Pass
+ * @retval        FALSE     Failed
+ */
+  unsigned char  validateImcFirmware (IN AMDSBCFG* pConfig);
+
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  softwareToggleImcStrapping (IN AMDSBCFG* pConfig);
+#endif
+
+#ifndef NO_HWM_SUPPORT
+/**
+ * hwmInit - Init Hardware Monitor.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  hwmInit (IN AMDSBCFG* pConfig);
+/**
+ * hwmUpdateData - Hardware Monitor Update Data.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  hwmUpdateData (IN AMDSBCFG* pConfig);
+/**
+ * hwmUpdateData - Hardware Monitor Update Data.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  hwmCopyFanControl (IN AMDSBCFG* pConfig);
+/**
+ * hwmCopyFanControl - Copy Hardware Monitor Update Data.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+#endif
+/**
+ * Stress Reset Mode Late
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void StressResetModeLate (IN AMDSBCFG* pConfig);
+
+/**
+ * TurnOffCG2
+ *
+ *
+ * @retval  VOID
+ *
+ */
+void TurnOffCG2 (OUT void);
+
+/**
+ * BackUpCG2
+ *
+ *
+ * @retval  VOID
+ *
+ */
+void BackUpCG2 (OUT void);
+
diff --git a/src/vendorcode/amd/cimx/sb900/SbType.h b/src/vendorcode/amd/cimx/sb900/SbType.h
new file mode 100755
index 0000000..ee88e71
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SbType.h
@@ -0,0 +1,1389 @@
+
+/**
+ * @file
+ *
+ * Southbridge CIMx configuration structure define
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENC