From marcj303 at gmail.com  Tue Mar  1 02:17:34 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 28 Feb 2011 18:17:34 -0700
Subject: [coreboot] Google Summer of Code 2011
Message-ID: <AANLkTinnR-_y64jtTe+0VORe+6heGE4tKObqb2v=2xYf@mail.gmail.com>

GSoC mentoring org signup starts this week and is due by March 11. I
can take the lead this year, unless someone else would like to do it.

If we are accepted (I expect we will be), Student applications are
March 28 - April 8.

Please add your project ideas to the wiki : http://www.coreboot.org/GSoC

Who would like to be a mentor this year?

Marc


-- 
http://se-eng.com



From buurin at gmail.com  Tue Mar  1 06:20:07 2011
From: buurin at gmail.com (Keith Hui)
Date: Tue, 1 Mar 2011 00:20:07 -0500
Subject: [coreboot] [PATCH] First step in converting W83977TF early serial
 from included to linked
Message-ID: <AANLkTik1i0DMaJP2GQDMsm5ycvb+kKBxrRhtwwqjFADi@mail.gmail.com>

And here is the patch. abuild-tested. I will boot test it with P2B-LS
and P3B-F tomorrow but I want this patch out there to generate some
discussions and get more boot test coverage.

This I believe falls under "infrastructure projects" [1].

This patch facilitates, for boards using Winbond W83977TF superio,
dropping early_serial.c from #includes of their romstage, instead
linking to them; and converts 12 of 13 mainboards using this superio
to do exactly this. The lone board out, iei/nova4899r, is a
Geode/CS5530 board that has not yet been converted to CAR or tiny
bootblock. The rest are all slot 1/440BX/i82371eb boards that have
been converted. At this stage I should leave converting CS5530 to tiny
bootblock to someone better versed in this platform.

The pnp_... functions defined in romcc_io.h now have a new home in
arch/x86/lib/pnp.c, and is compiled and linked like any other C files
meant for romstage.

This patch puts the W83977TF early serial code in a state where it can
be incorporated both through the old setup (ie. #included in mainboard
romstage), or be compiled separately and linked into romstage. Once
this conversion is done on all superios and all southbridges/boards
have been converted, the few #ifdefs that made this possible can be
cleaned out.

Signed-off-by: Keith Hui <buurin at gmail.com>

[1] http://www.coreboot.org/Infrastructure_Projects#Remove_.c_includes

On Mon, Feb 28, 2011 at 1:00 PM, Keith Hui <buurin at gmail.com> wrote:
> Hi all,
>
> In my pipeline is something more infrastructural, something different
> from what I usually do -
>
> I am converting early serial code for Winbond W83977TF from code
> included in romstage to compiled unit to be linked into romstage.
>
> 13 boards use this superio, some apparently still not converted to CAR
> (including one Intel server board). I have yet to complete running
> abuild on my change. Should I let it break when I submit it for review
> given earlier buzz suggesting we leave non-CAR boards behind?
>
> The reason I'm doing this is I want to do this for ITE IT8705F, which
> happens to have no board using it at the moment, but I want to test
> this approach on a board that I can boot test right now. Enter the
> P2B-LS and W83977TF. If this proof of concept works, we can start this
> conversion one superio at a time and nail down one more goal of the
> infrastructure refactoring.
>
> Thoughts and comments?
>
Thanks
Keith
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From anders at jenbo.dk  Tue Mar  1 07:27:29 2011
From: anders at jenbo.dk (Anders Jenbo)
Date: Tue, 01 Mar 2011 07:27:29 +0100
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <AANLkTik5JdmeNdBWigQiORPVgcEdg4oS+kCX5KFxU4JB@mail.gmail.com>
References: <4CA7B5C3.9000002@gmx.net>	<AANLkTinU2Bd8TGaawVrnJrQiihV=UqDf-wG0Xx74bzex@mail.gmail.com>	<4CA978ED.8000002@georgi-clan.de>	<201010041950.25088.phorsyon@gmx.net>	<20101004192314.7903.qmail@stuge.se>	<AANLkTimROPLy7jwLcLhNDF0SPNL6R-hw2HS6YPi0zm_B@mail.gmail.com>	<AANLkTikStpx9167n_eC4FyQovxRu-nZtYujEWW3Kxnh8@mail.gmail.com>	<4CAAE908.5090708@assembler.cz>	<AANLkTikKA_veW1YHwB3WmctCFZwZrOGStm6Q5v5PtXTh@mail.gmail.com>	<20101005162634.30508.qmail@stuge.se>
	<AANLkTik5JdmeNdBWigQiORPVgcEdg4oS+kCX5KFxU4JB@mail.gmail.com>
Message-ID: <4D6C91D1.9030409@jenbo.dk>

Wondered if you guys have seen this:

http://www.h-online.com/open/news/item/Intel-releases-GRUB-based-BIOS-test-suite-1197828.html

-Anders

Den 05-10-2010 18:34, ron minnich skrev:
> Making your own certification is hard. Using someone else's test is
> easier. Maybe we should invert the problem. Have a page which shows,
> for each board, what suite of tests it passes under coreboot.
>
> - boots vista
> - boots windows 7
> - boots linux
> - runs intels firmware validation
>
> and so on.
>
> ron
>




From svn at coreboot.org  Tue Mar  1 08:12:09 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 08:12:09 +0100
Subject: [coreboot] [commit] r6413 - trunk/payloads/libpayload/bin
Message-ID: <E1PuJkf-0005wi-6e@ra.coresystems.de>

Author: oxygene
Date: Tue Mar  1 08:12:08 2011
New Revision: 6413
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6413

Log:
Add lib/ to the default library path of lpgcc, so -l works

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/payloads/libpayload/bin/lpgcc

Modified: trunk/payloads/libpayload/bin/lpgcc
==============================================================================
--- trunk/payloads/libpayload/bin/lpgcc	Mon Feb 28 19:09:58 2011	(r6412)
+++ trunk/payloads/libpayload/bin/lpgcc	Tue Mar  1 08:12:08 2011	(r6413)
@@ -123,7 +123,7 @@
 
 _CFLAGS="$_CFLAGS -I`$DEFAULT_CC -m32 -print-search-dirs | head -n 1 | cut -d' ' -f2`include"
 
-_LDFLAGS="$_LDSCRIPT -static"
+_LDFLAGS="-L$BASE/../lib $_LDSCRIPT -static"
 
 if [ $DOLINK -eq 0 ]; then
     if [ $DEBUGME -eq 1 ]; then
@@ -134,7 +134,7 @@
 else
     _LIBGCC=`$DEFAULT_CC -m32 -print-libgcc-file-name`
     if [ $DEBUGME -eq 1 ]; then
-	echo "$DEFAULT_CC $_CFLAGS $_LDFLAGS $_ARCHLIBDIR/head.o $CMDLINE $_LIBDIR/libpayload.a $_LIBGCC"
+	echo "$DEFAULT_CC $_CFLAGS $_LDFLAGS $_ARCHLIBDIR/head.o $CMDLINE -lpayload $_LIBGCC"
     fi
 
     # Note: $_ARCHLIBDIR/head.o must be the first object being linked, because it
@@ -142,5 +142,5 @@
     # header to be placed below 0x2000 in the resulting image.  See:
     # http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format.html
 
-    $DEFAULT_CC $_CFLAGS $_LDFLAGS $_ARCHLIBDIR/head.o  $CMDLINE $_LIBDIR/libpayload.a $_LIBGCC
+    $DEFAULT_CC $_CFLAGS $_LDFLAGS $_ARCHLIBDIR/head.o  $CMDLINE -lpayload $_LIBGCC
 fi



From svn at coreboot.org  Tue Mar  1 08:13:11 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 08:13:11 +0100
Subject: [coreboot] [commit] r6414 - trunk/payloads/libpayload/include
Message-ID: <E1PuJlf-000789-8x@ra.coresystems.de>

Author: oxygene
Date: Tue Mar  1 08:13:10 2011
New Revision: 6414
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6414

Log:
Some more standard types and defines (libpayload)

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/payloads/libpayload/include/limits.h
   trunk/payloads/libpayload/include/stdint.h

Modified: trunk/payloads/libpayload/include/limits.h
==============================================================================
--- trunk/payloads/libpayload/include/limits.h	Tue Mar  1 08:12:08 2011	(r6413)
+++ trunk/payloads/libpayload/include/limits.h	Tue Mar  1 08:13:10 2011	(r6414)
@@ -40,4 +40,6 @@
 # endif
 #endif
 
+#define UINT_MAX (unsigned int)0xffffffff
+
 #endif

Modified: trunk/payloads/libpayload/include/stdint.h
==============================================================================
--- trunk/payloads/libpayload/include/stdint.h	Tue Mar  1 08:12:08 2011	(r6413)
+++ trunk/payloads/libpayload/include/stdint.h	Tue Mar  1 08:13:10 2011	(r6414)
@@ -27,4 +27,9 @@
  * SUCH DAMAGE.
  */
 
+#ifndef __STDINT_H
+#define __STDINT_H
 #include <arch/types.h>
+
+typedef unsigned long uintptr_t;
+#endif



From svn at coreboot.org  Tue Mar  1 08:23:49 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 08:23:49 +0100
Subject: [coreboot] [commit] r6415 - in trunk/payloads/libpayload: include
	libc
Message-ID: <E1PuJvx-00079t-Rk@ra.coresystems.de>

Author: oxygene
Date: Tue Mar  1 08:23:49 2011
New Revision: 6415
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6415

Log:
libpayload: Implement ffs()

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Added:
   trunk/payloads/libpayload/include/strings.h
   trunk/payloads/libpayload/libc/strings.c
Modified:
   trunk/payloads/libpayload/libc/Makefile.inc

Added: trunk/payloads/libpayload/include/strings.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/payloads/libpayload/include/strings.h	Tue Mar  1 08:23:49 2011	(r6415)
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2011 secunet Security Networks AG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _STRINGS_H
+#define _STRINGS_H
+
+int ffs(int i);
+
+#endif

Modified: trunk/payloads/libpayload/libc/Makefile.inc
==============================================================================
--- trunk/payloads/libpayload/libc/Makefile.inc	Tue Mar  1 08:13:10 2011	(r6414)
+++ trunk/payloads/libpayload/libc/Makefile.inc	Tue Mar  1 08:23:49 2011	(r6415)
@@ -32,7 +32,7 @@
 TARGETS-$(CONFIG_LIBC) += libc/memory.o libc/ctype.o libc/ipchecksum.o libc/lib.o
 TARGETS-$(CONFIG_LIBC) += libc/rand.o libc/time.o libc/exec.o
 TARGETS-$(CONFIG_LIBC) += libc/readline.o libc/getopt_long.o libc/sysinfo.o
-TARGETS-$(CONFIG_LIBC) += libc/args.o
+TARGETS-$(CONFIG_LIBC) += libc/args.o libc/strings.o
 
 # should be moved to coreboot directory
 TARGETS-$(CONFIG_LAR) += libc/lar.o

Added: trunk/payloads/libpayload/libc/strings.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/payloads/libpayload/libc/strings.c	Tue Mar  1 08:23:49 2011	(r6415)
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2011 secunet Security Networks AG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+int ffs(int i)
+{
+	int count = 1;
+	if (i == 0) return 0;
+
+	while ((i & 1) != 1) {
+		i>>=1;
+		count++;
+	}
+	return count;
+}



From svn at coreboot.org  Tue Mar  1 08:24:53 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 08:24:53 +0100
Subject: [coreboot] [commit] r6416 - in trunk/payloads/libpayload:
	include/pci libpci
Message-ID: <E1PuJwz-0000KH-Tk@ra.coresystems.de>

Author: oxygene
Date: Tue Mar  1 08:24:53 2011
New Revision: 6416
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6416

Log:
libpayload: Implement pci_cleanup()

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/payloads/libpayload/include/pci/pci.h
   trunk/payloads/libpayload/libpci/libpci.c

Modified: trunk/payloads/libpayload/include/pci/pci.h
==============================================================================
--- trunk/payloads/libpayload/include/pci/pci.h	Tue Mar  1 08:23:49 2011	(r6415)
+++ trunk/payloads/libpayload/include/pci/pci.h	Tue Mar  1 08:24:53 2011	(r6416)
@@ -70,6 +70,7 @@
 
 struct pci_access *pci_alloc(void);
 void pci_init(struct pci_access*);
+void pci_cleanup(struct pci_access*);
 char *pci_filter_parse_slot(struct pci_filter*, const char*);
 int pci_filter_match(struct pci_filter*, struct pci_dev*);
 void pci_filter_init(struct pci_access*, struct pci_filter*);

Modified: trunk/payloads/libpayload/libpci/libpci.c
==============================================================================
--- trunk/payloads/libpayload/libpci/libpci.c	Tue Mar  1 08:23:49 2011	(r6415)
+++ trunk/payloads/libpayload/libpci/libpci.c	Tue Mar  1 08:24:53 2011	(r6416)
@@ -77,11 +77,15 @@
 	return pacc;
 }
 
-void pci_init(struct pci_access* pacc)
+void pci_init(struct pci_access *pacc)
 {
 	memset(pacc, 0, sizeof(*pacc));
 }
 
+void pci_cleanup(__attribute__ ((unused)) struct pci_access *pacc)
+{
+}
+
 void pci_filter_init(struct pci_access* pacc, struct pci_filter* pf)
 {
 	pf->domain = -1;



From svn at coreboot.org  Tue Mar  1 08:26:01 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 08:26:01 +0100
Subject: [coreboot] [commit] r6417 - in trunk/payloads/libpayload/include: .
	pci
Message-ID: <E1PuJy5-0002Jf-7U@ra.coresystems.de>

Author: oxygene
Date: Tue Mar  1 08:26:00 2011
New Revision: 6417
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6417

Log:
libpayload: Add more libpci-compatibility (#defines)

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/payloads/libpayload/include/pci.h
   trunk/payloads/libpayload/include/pci/pci.h

Modified: trunk/payloads/libpayload/include/pci.h
==============================================================================
--- trunk/payloads/libpayload/include/pci.h	Tue Mar  1 08:24:53 2011	(r6416)
+++ trunk/payloads/libpayload/include/pci.h	Tue Mar  1 08:26:00 2011	(r6417)
@@ -42,6 +42,8 @@
 #define REG_SUBSYS_VENDOR_ID 0x2C
 #define REG_SUBSYS_ID   0x2E
 
+#define REG_COMMAND_IO  (1 << 0)
+#define REG_COMMAND_MEM (1 << 1)
 #define REG_COMMAND_BM  (1 << 2)
 
 #define HEADER_TYPE_NORMAL  0

Modified: trunk/payloads/libpayload/include/pci/pci.h
==============================================================================
--- trunk/payloads/libpayload/include/pci/pci.h	Tue Mar  1 08:24:53 2011	(r6416)
+++ trunk/payloads/libpayload/include/pci/pci.h	Tue Mar  1 08:26:00 2011	(r6417)
@@ -39,6 +39,32 @@
 #define PCI_SUBSYSTEM_VENDOR_ID REG_SUBSYS_VENDOR_ID
 #define PCI_SUBSYSTEM_ID	REG_SUBSYS_ID
 
+#define PCI_COMMAND		REG_COMMAND
+#define PCI_COMMAND_IO		REG_COMMAND_IO
+#define PCI_COMMAND_MEMORY	REG_COMMAND_MEM
+#define PCI_COMMAND_MASTER	REG_COMMAND_BM
+
+#define PCI_HEADER_TYPE		REG_HEADER_TYPE
+#define PCI_HEADER_TYPE_NORMAL	HEADER_TYPE_NORMAL
+#define PCI_HEADER_TYPE_BRIDGE	HEADER_TYPE_BRIDGE
+#define PCI_HEADER_TYPE_CARDBUS	HEADER_TYPE_CARDBUS
+
+#define PCI_BASE_ADDRESS_0	0x10
+#define PCI_BASE_ADDRESS_1	0x14
+#define PCI_BASE_ADDRESS_2	0x18
+#define PCI_BASE_ADDRESS_3	0x1c
+#define PCI_BASE_ADDRESS_4	0x20
+#define PCI_BASE_ADDRESS_5	0x24
+#define PCI_BASE_ADDRESS_SPACE	1 // mask
+#define PCI_BASE_ADDRESS_SPACE_IO	1
+#define PCI_BASE_ADDRESS_SPACE_MEM	0
+#define PCI_BASE_ADDRESS_IO_MASK	~0xf
+#define PCI_BASE_ADDRESS_MEM_MASK	~0x3
+
+#define PCI_ROM_ADDRESS		0x30
+#define PCI_ROM_ADDRESS1	0x38 // on bridges
+#define PCI_ROM_ADDRESS_MASK	~0x7ff
+
 struct pci_dev {
 	u16 domain;
 	u8 bus, dev, func;



From svn at coreboot.org  Tue Mar  1 08:30:15 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 08:30:15 +0100
Subject: [coreboot] [commit] r6418 - trunk/src/northbridge/amd/lx
Message-ID: <E1PuK2B-0000HX-Ev@ra.coresystems.de>

Author: oxygene
Date: Tue Mar  1 08:30:14 2011
New Revision: 6418
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6418

Log:
Mark non-returning function as noreturn to help some compiler versions

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/src/northbridge/amd/lx/raminit.c

Modified: trunk/src/northbridge/amd/lx/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/lx/raminit.c	Tue Mar  1 08:26:00 2011	(r6417)
+++ trunk/src/northbridge/amd/lx/raminit.c	Tue Mar  1 08:30:14 2011	(r6418)
@@ -32,7 +32,7 @@
 	printk(BIOS_DEBUG, " * %s\n", s);
 }
 
-static void hcf(void)
+static void __attribute__((noreturn)) hcf(void)
 {
 	print_emerg("DIE\n");
 	/* this guarantees we flush the UART fifos (if any) and also



From svn at coreboot.org  Tue Mar  1 09:09:23 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 09:09:23 +0100
Subject: [coreboot] [commit] r6419 - trunk
Message-ID: <E1PuKe3-0008O0-4w@ra.coresystems.de>

Author: oxygene
Date: Tue Mar  1 09:09:22 2011
New Revision: 6419
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6419

Log:
Fix double inclusion of toplevel Makefile.inc

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/Makefile

Modified: trunk/Makefile
==============================================================================
--- trunk/Makefile	Tue Mar  1 08:30:14 2011	(r6418)
+++ trunk/Makefile	Tue Mar  1 09:09:22 2011	(r6419)
@@ -44,6 +44,9 @@
 export KCONFIG_AUTOHEADER := $(obj)/config.h
 export KCONFIG_AUTOCONFIG := $(obj)/auto.conf
 
+# directory containing the toplevel Makefile.inc
+TOPLEVEL := .
+
 CONFIG_SHELL := sh
 KBUILD_DEFCONFIG := configs/defconfig
 UNAME_RELEASE := $(shell uname -r)
@@ -73,9 +76,8 @@
 
 all: real-all
 
-# This include must come _before_ he pattern rules below!
+# This include must come _before_ the pattern rules below!
 # Order _does_ matter for pattern rules.
-include Makefile.inc
 include util/kconfig/Makefile
 
 # Three cases where we don't need fully populated $(obj) lists:
@@ -93,6 +95,7 @@
 endif
 
 ifeq ($(NOCOMPILE),1)
+include $(TOPLEVEL)/Makefile.inc
 real-all: config
 
 else
@@ -189,7 +192,7 @@
 	$(if $(subdirs),$(eval $(call evaluate_subdirs)))
 
 # collect all object files eligible for building
-subdirs:=.
+subdirs:=$(TOPLEVEL)
 $(eval $(call evaluate_subdirs))
 
 src-to-obj=$(addsuffix .$(1).o, $(basename $(patsubst src/%, $(obj)/%, $($(1)-srcs))))



From hagigatali at gmail.com  Tue Mar  1 09:58:08 2011
From: hagigatali at gmail.com (ali hagigat)
Date: Tue, 1 Mar 2011 12:28:08 +0330
Subject: [coreboot] Tiny bootblock vs Bigbootblock
Message-ID: <AANLkTi=_mGkbFrJ2hcxw7dTE2tgyrTAhz8hgQJ49dgps@mail.gmail.com>

I created a new source code tree for only one motherboard, ASUS,
MEW_AM. There is no build/bootblock folder and CONFIG_TINY_BOOTBLOCK
and CONFIG_BOOTBLOCK_SIMPLE are not set. What is the difference
between tiny and big boot block?
My second question is that the code of bootblock is copied to romstage
too. I mean we have a duplicate code in two different components. Is
that right?



From joe at settoplinux.org  Tue Mar  1 10:08:40 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 01 Mar 2011 04:08:40 -0500
Subject: [coreboot] Google Summer of Code 2011
In-Reply-To: <AANLkTinnR-_y64jtTe+0VORe+6heGE4tKObqb2v=2xYf@mail.gmail.com>
References: <AANLkTinnR-_y64jtTe+0VORe+6heGE4tKObqb2v=2xYf@mail.gmail.com>
Message-ID: <34dd433c9e05e4b3bb30ac7c9fff035a@imap.1and1.com>



On Mon, 28 Feb 2011 18:17:34 -0700, Marc Jones <marcj303 at gmail.com> wrote:
> GSoC mentoring org signup starts this week and is due by March 11. I
> can take the lead this year, unless someone else would like to do it.
> 
> If we are accepted (I expect we will be), Student applications are
> March 28 - April 8.
> 
> Please add your project ideas to the wiki : http://www.coreboot.org/GSoC
> 
> Who would like to be a mentor this year?
> 
> Marc
> 
Hmm, even though I am getting old I am going to go back to school in the
fall 2011 to further my education (and hopefully take some x86 assembly
courses, cause I know some of you get sick of my assembly questions :-)). 
Could I be considered a student candidate for GSoC?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From mr.nuke.me at gmail.com  Tue Mar  1 10:19:09 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Tue, 01 Mar 2011 11:19:09 +0200
Subject: [coreboot] [PATCH][RFC] First step in converting W83977TF early
 serial from included to linked
In-Reply-To: <AANLkTik1i0DMaJP2GQDMsm5ycvb+kKBxrRhtwwqjFADi@mail.gmail.com>
References: <AANLkTik1i0DMaJP2GQDMsm5ycvb+kKBxrRhtwwqjFADi@mail.gmail.com>
Message-ID: <4D6CBA0D.1000609@gmail.com>

On 03/01/2011 07:20 AM, Keith Hui wrote:
> And here is the patch. abuild-tested. I will boot test it with P2B-LS
> and P3B-F tomorrow but I want this patch out there to generate some
> discussions and get more boot test coverage.
> 
OK.

> This I believe falls under "infrastructure projects" [1].
> 
Indeed, and for that reason people should be _more_ involved and open to
discuss this issue, not just leave it aside and ignore it. I'm glad
you're at least thinking of that.

> This patch facilitates, for boards using Winbond W83977TF superio,
> dropping early_serial.c from #includes of their romstage, instead
> linking to them; and converts 12 of 13 mainboards using this superio
> to do exactly this. The lone board out, iei/nova4899r, is a
> Geode/CS5530 board that has not yet been converted to CAR or tiny
> bootblock. The rest are all slot 1/440BX/i82371eb boards that have
> been converted. At this stage I should leave converting CS5530 to tiny
> bootblock to someone better versed in this platform.
> 
Definitely leave it out for now. Converting that to CAR is for a
different patch, though I think the tanks will expect you to convert it.

> The pnp_... functions defined in romcc_io.h now have a new home in
> arch/x86/lib/pnp.c, and is compiled and linked like any other C files
> meant for romstage.
> 
I do not like this. I would prefer to have the pnp functions declared
inline in a header file. It's more elegant for functions this small, and
avoids call/ret.

> This patch puts the W83977TF early serial code in a state where it can
> be incorporated both through the old setup (ie. #included in mainboard
> romstage), or be compiled separately and linked into romstage. Once
> this conversion is done on all superios and all southbridges/boards
> have been converted, the few #ifdefs that made this possible can be
> cleaned out.
> 
Don't worry about new board using this superio. If you broke the one
non-CAR board using this superio, leave it broken and ignore all the
torro-fecal matter surrounding the issue of the old build system. If you
think you can convert that board to CAR (and have the time), definitely
go for it. :)

> 
> Index: src/include/device/device.h
> ===================================================================
> --- src/include/device/device.h	(revision 6411)
> +++ src/include/device/device.h	(working copy)
> @@ -7,7 +7,15 @@
>  
>  
>  struct device;
> +
> +// In ramstage, device_t will be a structure.
> +#if defined(__PRE_RAM__) && !defined(__ROMCC__)
> +typedef unsigned device_t;
OK. I can see where this is going. I'm still not convinced it is the
best option, but I don't have a suggestion on this.

> Index: src/superio/winbond/w83977tf/Makefile.inc
> ===================================================================
> --- src/superio/winbond/w83977tf/Makefile.inc	(revision 6411)
> +++ src/superio/winbond/w83977tf/Makefile.inc	(working copy)
> @@ -22,3 +22,5 @@
>  
>  ramstage-$(CONFIG_SUPERIO_WINBOND_W83977TF) += superio.c
>  
> +romstage-$(CONFIG_SUPERIO_WINBOND_W83977TF) += early_serial.c
> +romstage-$(CONFIG_SUPERIO_WINBOND_W83977TF) += ../../../arch/x86/lib/pnp.c
This last line is ugly. Just keep the functions inlined. pnp.c is
unnecessarry.

> Index: src/superio/winbond/w83977tf/early_serial.c
> ===================================================================
> --- src/superio/winbond/w83977tf/early_serial.c	(revision 6411)
> +++ src/superio/winbond/w83977tf/early_serial.c	(working copy)
> @@ -20,7 +20,12 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>   */
>  
> +#if defined(__ROMCC__)
>  #include <arch/romcc_io.h>
> +#else
> +#include <device/pnp.h>
> +#include <arch/io.h>
> +#endif
Keith, nothing here for you, move along. For others, why can't we just
get rid of romcc altogether?.


>  
> Index: src/arch/x86/lib/pnp.c
> 
AAAAAAAAAAAAAAAAARGH!

Another thing we need to discuss (THAT MEANS __*EVERYBODY*__, NOT JUST
ME AND KEITH) is whether or not we should declare the
enable_early_serial() in a common place, and just have the superio code
implement it. I prefer common name option, as it makes the superio code
more transparent to the developer.

Alex



From zxy__1127 at 163.com  Tue Mar  1 11:36:16 2011
From: zxy__1127 at 163.com (zxy__1127)
Date: Tue, 1 Mar 2011 18:36:16 +0800
Subject: [coreboot] how to deal with large romstage size?
References: <AANLkTik1i0DMaJP2GQDMsm5ycvb+kKBxrRhtwwqjFADi@mail.gmail.com>,
	<4D6CBA0D.1000609@gmail.com>
Message-ID: <201103011836164586965@163.com >

Hi all,

After I add some memory initialisize code, the romstage is over 64K byte,and tne code can't run properly.
Then what should I do when romstage is over 64K byte? Is romstage's size limits to 64KB?

Thanks a lot!
2011-03-01 



zxy__1127 
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From svens at stackframe.org  Tue Mar  1 16:16:57 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue,  1 Mar 2011 16:16:57 +0100
Subject: [coreboot] (no subject)
Message-ID: <1298992619-6601-1-git-send-email-svens@stackframe.org>

Hi List,

this patches are adding a new subsystemid option to sconfig. This option
can be used to specify subsystem IDs in devicetree.cb, and is intended to
replace the old Kconfig option.

Main motivation for this patch is the fact that the current Kconfig mechanism
only allows to set a Subsystem Vendor/Device ID per Board, but not per Device.

My ThinkPad X60 and my T60 are using several subsystem device ids per Board,
so we want to have something more flexible.

A simple demo config which would equal the old Kconfig option:

device pci_domain 0 on
       subsystemid 0xdead 0xbeef inherit
       device pci 00.0 on end
       device pci 01.0 on end
       device pci 02.0 on end
end

This tells sconfig that it should use 0xdead as Vendor and 0xbeef as
device id for all devices below pci_domain 0.

A more complex config (taken from X60):

        device pci_domain 0 on
                device pci 00.0 on # Host bridge
                        subsystemid 0x17aa 0x2017
                end
                device pci 02.0 on # VGA controller
                        subsystemid 0x17aa 0x201a
                end
                device pci 02.1 on # display controller
                        subsystemid 0x17aa 0x201a
		[...]
	        device pci 1b.0 on # Audio Cnotroller
                        subsystemid 0x17aa 0x2010
                end

                device pci 1c.0 on end # Ethernet
                device pci 1c.1 on end # Atheros WLAN
                device pci 1d.0 on # USB UHCI
                        subsystemid 0x17aa 0x200a
                end
	        [...]

This config would set different device IDs depending on the device.




From svens at stackframe.org  Tue Mar  1 16:16:58 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue,  1 Mar 2011 16:16:58 +0100
Subject: [coreboot] [PATCH 1/2] Add subsystemid option to sconfig
In-Reply-To: <1298992619-6601-1-git-send-email-svens@stackframe.org>
References: <1298992619-6601-1-git-send-email-svens@stackframe.org>
Message-ID: <1298992619-6601-2-git-send-email-svens@stackframe.org>

Allow user to add 'subsystemid <vendor> <device> [inherit]' to devicetree.cb for
PCI and PCI domain devices.

Example:

	device pci 00.0 on
	       subsystemid dead beef
	end

If the user wants to have this ID inherited to all subdevices/functions,
he can add 'inherit', like in the following example:

	device pci 00.0 on
	       subsystemid dead beef inherit
	end

If the user don't want to inherit a Subsystem for a single device, he can
specify 'subsystemid 0 0' on this particular device.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/include/device/device.h        |    2 +
 util/sconfig/main.c                |   46 +++++++++++++
 util/sconfig/sconfig.h             |    4 +
 util/sconfig/sconfig.l             |    2 +
 util/sconfig/sconfig.tab.c_shipped |  124 +++++++++++++++++++++---------------
 util/sconfig/sconfig.tab.h_shipped |    4 +-
 util/sconfig/sconfig.y             |   12 +++-
 7 files changed, 139 insertions(+), 55 deletions(-)

diff --git a/src/include/device/device.h b/src/include/device/device.h
index 7dbbb4f..f6bbe9a 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -64,6 +64,8 @@ struct device {
 	struct device_path path;
 	unsigned 	vendor;
 	unsigned 	device;
+	unsigned subsystem_vendor;
+	unsigned subsystem_device;
 	unsigned int	class;		/* 3 bytes: (base, sub, prog-if) */
 	unsigned int	hdr_type;	/* PCI header type */
 	unsigned int    enabled : 1;	/* set if we should enable the device */
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index a3994fb..1243af7 100755
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -59,6 +59,8 @@ static struct device *new_dev(struct device *parent, struct device *bus) {
 	dev->id = ++devcount;
 	dev->parent = parent;
 	dev->bus = bus;
+	dev->subsystem_vendor = -1;
+	dev->subsystem_device = -1;
 	head->next = dev;
 	head = dev;
 	return dev;
@@ -279,6 +281,18 @@ void add_register(struct device *dev, char *name, char *val) {
 	}
 }
 
+void add_pci_subsystem_ids(struct device *dev, int vendor, int device, int inherit)
+{
+	if (dev->bustype != PCI && dev->bustype != PCI_DOMAIN) {
+		printf("ERROR: 'subsystem' only allowed for PCI devices\n");
+		exit(1);
+	}
+
+	dev->subsystem_vendor = vendor;
+	dev->subsystem_device = device;
+	dev->inherit_subsystem = inherit;
+}
+
 static void pass0(FILE *fil, struct device *ptr) {
 	if (ptr->type == device && ptr->id == 0)
 		fprintf(fil, "struct bus %s_links[];\n", ptr->name);
@@ -303,6 +317,12 @@ static void pass1(FILE *fil, struct device *ptr) {
 		fprintf(fil, "},\n");
 		fprintf(fil, "\t.enabled = %d,\n", ptr->enabled);
 		fprintf(fil, "\t.on_mainboard = 1,\n");
+		if (ptr->subsystem_vendor > 0)
+			fprintf(fil, "\t.subsystem_vendor = 0x%x,\n", ptr->subsystem_vendor);
+
+		if (ptr->subsystem_device > 0)
+			fprintf(fil, "\t.subsystem_device = 0x%x,\n", ptr->subsystem_device);
+
 		if (ptr->rescnt > 0) {
 			fprintf(fil, "\t.resource_list = &%s_res[0],\n", ptr->name);
 		}
@@ -392,6 +412,29 @@ static void walk_device_tree(FILE *fil, struct device *ptr, void (*func)(FILE *,
 	} while (ptr);
 }
 
+static void inherit_subsystem_ids(FILE *file, struct device *dev)
+{
+	struct device *p;
+	int i =0;
+
+	if (dev->subsystem_vendor != -1 && dev->subsystem_device != -1) {
+		/* user already gave us a subsystem vendor/device */
+		return;
+	}
+
+	for(p = dev; p && p != p->parent; (p = p->parent), i++) {
+
+		if (p->bustype != PCI && p->bustype != PCI_DOMAIN)
+			continue;
+
+		if (p->inherit_subsystem && p->subsystem_vendor && p->subsystem_device) {
+			dev->subsystem_vendor = p->subsystem_vendor;
+			dev->subsystem_device = p->subsystem_device;
+			break;
+		}
+	}
+}
+
 int main(int argc, char** argv) {
 	if (argc != 3) {
 		printf("usage: sconfig vendor/mainboard outputdir\n");
@@ -444,6 +487,9 @@ int main(int argc, char** argv) {
 		h = h->next;
 		fprintf(staticc, "#include \"%s/chip.h\"\n", h->name);
 	}
+
+	walk_device_tree(staticc, &root, inherit_subsystem_ids, NULL);
+
 	fprintf(staticc, "\n/* pass 0 */\n");
 	walk_device_tree(staticc, &root, pass0, NULL);
 	fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device *last_dev = &%s;\n", lastdev->name);
diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h
index 8fbae6a..d893c05 100755
--- a/util/sconfig/sconfig.h
+++ b/util/sconfig/sconfig.h
@@ -52,6 +52,9 @@ struct device {
 	int link;
 	int rescnt;
 	int chiph_exists;
+	int subsystem_vendor;
+	int subsystem_device;
+	int inherit_subsystem;
 	char *ops;
 	char *name;
 	char *name_underscore;
@@ -90,3 +93,4 @@ struct device *new_device(struct device *parent, struct device *busdev, const in
 void alias_siblings(struct device *d);
 void add_resource(struct device *dev, int type, int index, int base);
 void add_register(struct device *dev, char *name, char *val);
+void add_pci_subsystem_ids(struct device *dev, int vendor, int device, int inherit);
diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l
index 3d1593a..f0da034 100755
--- a/util/sconfig/sconfig.l
+++ b/util/sconfig/sconfig.l
@@ -42,6 +42,8 @@ pci_domain	{yylval.number=PCI_DOMAIN; return(BUS);}
 irq		{yylval.number=IRQ; return(RESOURCE);}
 drq		{yylval.number=DRQ; return(RESOURCE);}
 io		{yylval.number=IO; return(RESOURCE);}
+inherit		{return(INHERIT); }
+subsystemid	{return(SUBSYSTEMID);}
 end		{return(END);}
 =		{return(EQUALS);}
 0x[0-9a-fA-F.]+	{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped
index 4c78b62..dbefe06 100644
--- a/util/sconfig/sconfig.tab.c_shipped
+++ b/util/sconfig/sconfig.tab.c_shipped
@@ -139,7 +139,9 @@ static struct device *cur_parent, *cur_bus;
      IRQ = 274,
      DRQ = 275,
      IO = 276,
-     NUMBER = 277
+     NUMBER = 277,
+     SUBSYSTEMID = 278,
+     INHERIT = 279
    };
 #endif
 
@@ -380,20 +382,20 @@ union yyalloc
 /* YYFINAL -- State number of the termination state.  */
 #define YYFINAL  3
 /* YYLAST -- Last index in YYTABLE.  */
-#define YYLAST   24
+#define YYLAST   34
 
 /* YYNTOKENS -- Number of terminals.  */
-#define YYNTOKENS  23
+#define YYNTOKENS  25
 /* YYNNTS -- Number of nonterminals.  */
-#define YYNNTS  11
+#define YYNNTS  12
 /* YYNRULES -- Number of rules.  */
-#define YYNRULES  17
+#define YYNRULES  20
 /* YYNRULES -- Number of states.  */
-#define YYNSTATES  31
+#define YYNSTATES  36
 
 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
 #define YYUNDEFTOK  2
-#define YYMAXUTOK   277
+#define YYMAXUTOK   279
 
 #define YYTRANSLATE(YYX)						\
   ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
@@ -428,7 +430,7 @@ static const yytype_uint8 yytranslate[] =
        2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
        2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
        5,     6,     7,     8,     9,    10,    11,    12,    13,    14,
-      15,    16,    17,    18,    19,    20,    21,    22
+      15,    16,    17,    18,    19,    20,    21,    22,    23,    24
 };
 
 #if YYDEBUG
@@ -437,25 +439,28 @@ static const yytype_uint8 yytranslate[] =
 static const yytype_uint8 yyprhs[] =
 {
        0,     0,     3,     4,     7,    10,    13,    16,    17,    20,
-      23,    26,    27,    28,    34,    35,    43,    48
+      23,    26,    29,    30,    31,    37,    38,    46,    51,    56,
+      60
 };
 
 /* YYRHS -- A `-1'-separated list of the rules' RHS.  */
 static const yytype_int8 yyrhs[] =
 {
-      24,     0,    -1,    -1,    25,    28,    -1,    26,    30,    -1,
-      26,    28,    -1,    26,    33,    -1,    -1,    27,    30,    -1,
-      27,    28,    -1,    27,    32,    -1,    -1,    -1,     3,    12,
-      29,    26,     9,    -1,    -1,     4,     7,    22,     6,    31,
-      27,     9,    -1,     8,    22,    10,    22,    -1,     5,    12,
-      10,    12,    -1
+      26,     0,    -1,    -1,    27,    30,    -1,    28,    32,    -1,
+      28,    30,    -1,    28,    35,    -1,    -1,    29,    32,    -1,
+      29,    30,    -1,    29,    34,    -1,    29,    36,    -1,    -1,
+      -1,     3,    12,    31,    28,     9,    -1,    -1,     4,     7,
+      22,     6,    33,    29,     9,    -1,     8,    22,    10,    22,
+      -1,     5,    12,    10,    12,    -1,    23,    22,    22,    -1,
+      23,    22,    22,    24,    -1
 };
 
 /* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
 static const yytype_uint8 yyrline[] =
 {
-       0,    34,    34,    34,    36,    36,    36,    36,    38,    38,
-      38,    38,    40,    40,    50,    50,    62,    65
+       0,    35,    35,    35,    37,    37,    37,    37,    39,    39,
+      39,    39,    39,    41,    41,    51,    51,    63,    66,    69,
+      72
 };
 #endif
 
@@ -467,8 +472,9 @@ static const char *const yytname[] =
   "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL",
   "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C",
   "APIC", "APIC_CLUSTER", "PCI_DOMAIN", "IRQ", "DRQ", "IO", "NUMBER",
-  "$accept", "devtree", "$@1", "chipchildren", "devicechildren", "chip",
-  "@2", "device", "@3", "resource", "registers", 0
+  "SUBSYSTEMID", "INHERIT", "$accept", "devtree", "$@1", "chipchildren",
+  "devicechildren", "chip", "@2", "device", "@3", "resource", "registers",
+  "subsystemid", 0
 };
 #endif
 
@@ -479,22 +485,24 @@ static const yytype_uint16 yytoknum[] =
 {
        0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
      265,   266,   267,   268,   269,   270,   271,   272,   273,   274,
-     275,   276,   277
+     275,   276,   277,   278,   279
 };
 # endif
 
 /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
 static const yytype_uint8 yyr1[] =
 {
-       0,    23,    25,    24,    26,    26,    26,    26,    27,    27,
-      27,    27,    29,    28,    31,    30,    32,    33
+       0,    25,    27,    26,    28,    28,    28,    28,    29,    29,
+      29,    29,    29,    31,    30,    33,    32,    34,    35,    36,
+      36
 };
 
 /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
 static const yytype_uint8 yyr2[] =
 {
        0,     2,     0,     2,     2,     2,     2,     0,     2,     2,
-       2,     0,     0,     5,     0,     7,     4,     4
+       2,     2,     0,     0,     5,     0,     7,     4,     4,     3,
+       4
 };
 
 /* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
@@ -502,35 +510,35 @@ static const yytype_uint8 yyr2[] =
    means the default is an error.  */
 static const yytype_uint8 yydefact[] =
 {
-       2,     0,     0,     1,     0,     3,    12,     7,     0,     0,
-       0,    13,     5,     4,     6,     0,     0,     0,     0,    14,
-      17,    11,     0,     0,    15,     9,     8,    10,     0,     0,
-      16
+       2,     0,     0,     1,     0,     3,    13,     7,     0,     0,
+       0,    14,     5,     4,     6,     0,     0,     0,     0,    15,
+      18,    12,     0,     0,    16,     0,     9,     8,    10,    11,
+       0,     0,     0,    19,    17,    20
 };
 
 /* YYDEFGOTO[NTERM-NUM].  */
 static const yytype_int8 yydefgoto[] =
 {
-      -1,     1,     2,     8,    22,     5,     7,    13,    21,    27,
-      14
+      -1,     1,     2,     8,    22,     5,     7,    13,    21,    28,
+      14,    29
 };
 
 /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
    STATE-NUM.  */
-#define YYPACT_NINF -10
+#define YYPACT_NINF -9
 static const yytype_int8 yypact[] =
 {
-     -10,     6,     5,   -10,    -1,   -10,   -10,   -10,    -2,     8,
-       0,   -10,   -10,   -10,   -10,    -9,     7,    10,     9,   -10,
-     -10,   -10,     1,    -4,   -10,   -10,   -10,   -10,    12,    -3,
-     -10
+      -9,     3,     1,    -9,    -2,    -9,    -9,    -9,     4,     5,
+      -1,    -9,    -9,    -9,    -9,    -8,     7,     9,     6,    -9,
+      -9,    -9,    -3,     0,    -9,     2,    -9,    -9,    -9,    -9,
+      11,     8,    10,    -5,    -9,    -9
 };
 
 /* YYPGOTO[NTERM-NUM].  */
 static const yytype_int8 yypgoto[] =
 {
-     -10,   -10,   -10,   -10,   -10,    -8,   -10,     2,   -10,   -10,
-     -10
+      -9,    -9,    -9,    -9,    -9,    -6,    -9,    12,    -9,    -9,
+      -9,    -9
 };
 
 /* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
@@ -540,26 +548,28 @@ static const yytype_int8 yypgoto[] =
 #define YYTABLE_NINF -1
 static const yytype_uint8 yytable[] =
 {
-      12,     4,     9,    10,     4,     9,     3,    11,     4,    23,
-      24,     6,    16,    17,    25,    15,    19,    18,    28,    30,
-       0,    20,    29,     0,    26
+       4,     9,    12,     3,     4,    23,    24,     4,     9,    10,
+       6,    16,    15,    11,    17,    19,    26,    18,    20,    35,
+      25,    32,    30,     0,    31,     0,     0,     0,     0,     0,
+      33,     0,    34,     0,    27
 };
 
 static const yytype_int8 yycheck[] =
 {
-       8,     3,     4,     5,     3,     4,     0,     9,     3,     8,
-       9,    12,    12,    22,    22,     7,     6,    10,    22,    22,
-      -1,    12,    10,    -1,    22
+       3,     4,     8,     0,     3,     8,     9,     3,     4,     5,
+      12,    12,     7,     9,    22,     6,    22,    10,    12,    24,
+      23,    10,    22,    -1,    22,    -1,    -1,    -1,    -1,    -1,
+      22,    -1,    22,    -1,    22
 };
 
 /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
    symbol of state STATE-NUM.  */
 static const yytype_uint8 yystos[] =
 {
-       0,    24,    25,     0,     3,    28,    12,    29,    26,     4,
-       5,     9,    28,    30,    33,     7,    12,    22,    10,     6,
-      12,    31,    27,     8,     9,    28,    30,    32,    22,    10,
-      22
+       0,    26,    27,     0,     3,    30,    12,    31,    28,     4,
+       5,     9,    30,    32,    35,     7,    12,    22,    10,     6,
+      12,    33,    29,     8,     9,    23,    30,    32,    34,    36,
+      22,    22,    10,    22,    22,    24
 };
 
 #define yyerrok		(yyerrstatus = 0)
@@ -1380,7 +1390,7 @@ yyreduce:
     { postprocess_devtree(); ;}
     break;
 
-  case 12:
+  case 13:
 
     {
 	(yyval.device) = new_chip(cur_parent, cur_bus, (yyvsp[(2) - (2)].string));
@@ -1388,7 +1398,7 @@ yyreduce:
 ;}
     break;
 
-  case 13:
+  case 14:
 
     {
 	cur_parent = (yyvsp[(3) - (5)].device)->parent;
@@ -1397,7 +1407,7 @@ yyreduce:
 ;}
     break;
 
-  case 14:
+  case 15:
 
     {
 	(yyval.device) = new_device(cur_parent, cur_bus, (yyvsp[(2) - (4)].number), (yyvsp[(3) - (4)].string), (yyvsp[(4) - (4)].number));
@@ -1406,7 +1416,7 @@ yyreduce:
 ;}
     break;
 
-  case 15:
+  case 16:
 
     {
 	cur_parent = (yyvsp[(5) - (7)].device)->parent;
@@ -1416,16 +1426,26 @@ yyreduce:
 ;}
     break;
 
-  case 16:
+  case 17:
 
     { add_resource(cur_parent, (yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); ;}
     break;
 
-  case 17:
+  case 18:
 
     { add_register(cur_parent, (yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); ;}
     break;
 
+  case 19:
+
+    { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (3)].string), NULL, 16), strtol((yyvsp[(3) - (3)].string), NULL, 16), 0); ;}
+    break;
+
+  case 20:
+
+    { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), strtol((yyvsp[(3) - (4)].string), NULL, 16), 1); ;}
+    break;
+
 
 
       default: break;
diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped
index 8c6b5f6..fc101c2 100644
--- a/util/sconfig/sconfig.tab.h_shipped
+++ b/util/sconfig/sconfig.tab.h_shipped
@@ -58,7 +58,9 @@
      IRQ = 274,
      DRQ = 275,
      IO = 276,
-     NUMBER = 277
+     NUMBER = 277,
+     SUBSYSTEMID = 278,
+     INHERIT = 279
    };
 #endif
 
diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y
index 1c5db2a..f97850f 100755
--- a/util/sconfig/sconfig.y
+++ b/util/sconfig/sconfig.y
@@ -29,13 +29,14 @@ static struct device *cur_parent, *cur_bus;
 	char *string;
 	int number;
 }
-%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER
+
+%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT
 %%
 devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ;
 
 chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ;
 
-devicechildren: devicechildren device | devicechildren chip | devicechildren resource | /* empty */ ;
+devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | /* empty */ ;
 
 chip: CHIP STRING /* == path */ {
 	$<device>$ = new_chip(cur_parent, cur_bus, $<string>2);
@@ -65,4 +66,11 @@ resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */
 registers: REGISTER STRING /* == regname */ EQUALS STRING /* == regval */
 	{ add_register(cur_parent, $<string>2, $<string>4); } ;
 
+subsystemid: SUBSYSTEMID NUMBER NUMBER
+	{ add_pci_subsystem_ids(cur_parent, strtol($<string>2, NULL, 16), strtol($<string>3, NULL, 16), 0); };
+
+subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT
+	{ add_pci_subsystem_ids(cur_parent, strtol($<string>2, NULL, 16), strtol($<string>3, NULL, 16), 1); };
+
+
 %%
-- 
1.7.4.1




From svens at stackframe.org  Tue Mar  1 16:16:59 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue,  1 Mar 2011 16:16:59 +0100
Subject: [coreboot] [PATCH 2/2] Use subsystem id from devicetree.cb instead
	of Kconfig and move all boards to the new config scheme.
In-Reply-To: <1298992619-6601-1-git-send-email-svens@stackframe.org>
References: <1298992619-6601-1-git-send-email-svens@stackframe.org>
Message-ID: <1298992619-6601-3-git-send-email-svens@stackframe.org>

---
 src/Kconfig                                        |    7 ---
 src/devices/pci_device.c                           |   24 +++-------
 src/mainboard/amd/bimini_fam10/Kconfig             |    8 ---
 src/mainboard/amd/bimini_fam10/devicetree.cb       |    1 +
 src/mainboard/amd/dbm690t/Kconfig                  |    8 ---
 src/mainboard/amd/dbm690t/devicetree.cb            |    1 +
 src/mainboard/amd/inagua/Kconfig                   |    8 ---
 src/mainboard/amd/inagua/devicetree.cb             |    1 +
 src/mainboard/amd/mahogany/Kconfig                 |    8 ---
 src/mainboard/amd/mahogany/devicetree.cb           |    1 +
 src/mainboard/amd/mahogany_fam10/Kconfig           |    8 ---
 src/mainboard/amd/mahogany_fam10/devicetree.cb     |    1 +
 src/mainboard/amd/persimmon/Kconfig                |    8 ---
 src/mainboard/amd/persimmon/devicetree.cb          |    1 +
 src/mainboard/amd/pistachio/Kconfig                |    8 ---
 src/mainboard/amd/pistachio/devicetree.cb          |    1 +
 src/mainboard/amd/serengeti_cheetah/Kconfig        |    8 ---
 src/mainboard/amd/serengeti_cheetah/devicetree.cb  |    1 +
 src/mainboard/amd/serengeti_cheetah_fam10/Kconfig  |    8 ---
 .../amd/serengeti_cheetah_fam10/devicetree.cb      |    1 +
 src/mainboard/amd/tilapia_fam10/Kconfig            |    8 ---
 src/mainboard/amd/tilapia_fam10/devicetree.cb      |    1 +
 src/mainboard/arima/hdama/Kconfig                  |    8 ---
 src/mainboard/arima/hdama/devicetree.cb            |    1 +
 src/mainboard/asrock/939a785gmh/Kconfig            |    8 ---
 src/mainboard/asrock/939a785gmh/devicetree.cb      |    1 +
 src/mainboard/asrock/e350m1/Kconfig                |    8 ---
 src/mainboard/asrock/e350m1/devicetree.cb          |    1 +
 src/mainboard/asus/Kconfig                         |    4 --
 src/mainboard/asus/a8n_e/Kconfig                   |    8 ---
 src/mainboard/asus/a8n_e/devicetree.cb             |    1 +
 src/mainboard/asus/a8v-e_deluxe/Kconfig            |    4 --
 src/mainboard/asus/a8v-e_se/Kconfig                |    4 --
 src/mainboard/asus/m2n-e/Kconfig                   |    4 --
 src/mainboard/asus/m2n-e/devicetree.cb             |    1 +
 src/mainboard/asus/m2v-mx_se/Kconfig               |    4 --
 src/mainboard/asus/m2v/Kconfig                     |    4 --
 src/mainboard/asus/m4a78-em/Kconfig                |    8 ---
 src/mainboard/asus/m4a78-em/devicetree.cb          |    1 +
 src/mainboard/asus/m4a785-m/Kconfig                |    8 ---
 src/mainboard/asus/m4a785-m/devicetree.cb          |    1 +
 src/mainboard/broadcom/blast/Kconfig               |    8 ---
 src/mainboard/broadcom/blast/devicetree.cb         |    1 +
 src/mainboard/dell/s1850/Kconfig                   |    8 ---
 src/mainboard/dell/s1850/devicetree.cb             |    1 +
 src/mainboard/gigabyte/ga_2761gxdk/Kconfig         |    8 ---
 src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb   |    1 +
 src/mainboard/gigabyte/m57sli/Kconfig              |    8 ---
 src/mainboard/gigabyte/m57sli/devicetree.cb        |    1 +
 src/mainboard/gigabyte/ma785gmt/Kconfig            |    8 ---
 src/mainboard/gigabyte/ma785gmt/devicetree.cb      |    1 +
 src/mainboard/gigabyte/ma78gm/Kconfig              |    8 ---
 src/mainboard/gigabyte/ma78gm/devicetree.cb        |    1 +
 src/mainboard/hp/dl145_g1/Kconfig                  |    8 ---
 src/mainboard/hp/dl145_g1/devicetree.cb            |    1 +
 src/mainboard/iei/kino-780am2-fam10/Kconfig        |    8 ---
 src/mainboard/intel/Kconfig                        |    4 --
 src/mainboard/intel/d945gclf/Kconfig               |    4 --
 src/mainboard/intel/d945gclf/devicetree.cb         |    1 +
 src/mainboard/intel/jarrell/Kconfig                |    8 ---
 src/mainboard/intel/jarrell/devicetree.cb          |    1 +
 src/mainboard/intel/mtarvon/Kconfig                |    8 ---
 src/mainboard/intel/mtarvon/devicetree.cb          |    1 +
 src/mainboard/intel/truxton/Kconfig                |    8 ---
 src/mainboard/intel/truxton/devicetree.cb          |    1 +
 src/mainboard/intel/xe7501devkit/Kconfig           |    8 ---
 src/mainboard/intel/xe7501devkit/devicetree.cb     |    1 +
 src/mainboard/iwill/dk8_htx/Kconfig                |    8 ---
 src/mainboard/iwill/dk8_htx/devicetree.cb          |    1 +
 src/mainboard/iwill/dk8s2/Kconfig                  |    8 ---
 src/mainboard/iwill/dk8s2/devicetree.cb            |    1 +
 src/mainboard/jetway/pa78vm5/Kconfig               |    8 ---
 src/mainboard/jetway/pa78vm5/devicetree.cb         |    1 +
 src/mainboard/kontron/kt690/Kconfig                |    8 ---
 src/mainboard/kontron/kt690/devicetree.cb          |    1 +
 src/mainboard/lenovo/x60/devicetree.cb             |   49 +++++++++++++++-----
 src/mainboard/msi/Kconfig                          |    4 --
 src/mainboard/msi/ms7135/Kconfig                   |    4 --
 src/mainboard/msi/ms7135/devicetree.cb             |    1 +
 src/mainboard/msi/ms7260/Kconfig                   |    8 ---
 src/mainboard/msi/ms7260/devicetree.cb             |    1 +
 src/mainboard/msi/ms9185/Kconfig                   |    8 ---
 src/mainboard/msi/ms9185/devicetree.cb             |    1 +
 src/mainboard/msi/ms9282/Kconfig                   |    8 ---
 src/mainboard/msi/ms9282/devicetree.cb             |    1 +
 src/mainboard/msi/ms9652_fam10/Kconfig             |    8 ---
 src/mainboard/msi/ms9652_fam10/devicetree.cb       |    1 +
 src/mainboard/newisys/khepri/Kconfig               |    8 ---
 src/mainboard/newisys/khepri/devicetree.cb         |    1 +
 src/mainboard/nvidia/l1_2pvv/Kconfig               |    8 ---
 src/mainboard/nvidia/l1_2pvv/devicetree.cb         |    1 +
 src/mainboard/roda/Kconfig                         |    4 --
 src/mainboard/roda/rk886ex/Kconfig                 |    4 --
 src/mainboard/roda/rk886ex/devicetree.cb           |    1 +
 src/mainboard/sunw/ultra40/Kconfig                 |    8 ---
 src/mainboard/sunw/ultra40/devicetree.cb           |    1 +
 src/mainboard/supermicro/Kconfig                   |    4 --
 src/mainboard/supermicro/h8dme/Kconfig             |    8 ---
 src/mainboard/supermicro/h8dme/devicetree.cb       |    1 +
 src/mainboard/supermicro/h8dmr/Kconfig             |    8 ---
 src/mainboard/supermicro/h8dmr/devicetree.cb       |    1 +
 src/mainboard/supermicro/h8dmr_fam10/Kconfig       |    4 --
 src/mainboard/supermicro/h8dmr_fam10/devicetree.cb |    1 +
 src/mainboard/supermicro/h8qme_fam10/Kconfig       |    4 --
 src/mainboard/supermicro/h8qme_fam10/devicetree.cb |    1 +
 src/mainboard/supermicro/x6dai_g/Kconfig           |    8 ---
 src/mainboard/supermicro/x6dai_g/devicetree.cb     |    1 +
 src/mainboard/supermicro/x6dhe_g/Kconfig           |    8 ---
 src/mainboard/supermicro/x6dhe_g/devicetree.cb     |    1 +
 src/mainboard/supermicro/x6dhe_g2/Kconfig          |    8 ---
 src/mainboard/supermicro/x6dhe_g2/devicetree.cb    |    1 +
 src/mainboard/supermicro/x6dhr_ig/Kconfig          |    8 ---
 src/mainboard/supermicro/x6dhr_ig/devicetree.cb    |    1 +
 src/mainboard/supermicro/x6dhr_ig2/Kconfig         |    8 ---
 src/mainboard/supermicro/x6dhr_ig2/devicetree.cb   |    1 +
 src/mainboard/technexion/tim5690/Kconfig           |    8 ---
 src/mainboard/technexion/tim5690/devicetree.cb     |    1 +
 src/mainboard/technexion/tim8690/Kconfig           |    8 ---
 src/mainboard/technexion/tim8690/devicetree.cb     |    1 +
 src/mainboard/tyan/Kconfig                         |    4 --
 src/mainboard/tyan/s2735/Kconfig                   |    4 --
 src/mainboard/tyan/s2735/devicetree.cb             |    1 +
 src/mainboard/tyan/s2850/Kconfig                   |    4 --
 src/mainboard/tyan/s2850/devicetree.cb             |    1 +
 src/mainboard/tyan/s2875/Kconfig                   |    4 --
 src/mainboard/tyan/s2875/devicetree.cb             |    1 +
 src/mainboard/tyan/s2880/Kconfig                   |    4 --
 src/mainboard/tyan/s2880/devicetree.cb             |    1 +
 src/mainboard/tyan/s2881/Kconfig                   |    4 --
 src/mainboard/tyan/s2881/devicetree.cb             |    1 +
 src/mainboard/tyan/s2882/Kconfig                   |    4 --
 src/mainboard/tyan/s2882/devicetree.cb             |    1 +
 src/mainboard/tyan/s2885/Kconfig                   |    4 --
 src/mainboard/tyan/s2885/devicetree.cb             |    1 +
 src/mainboard/tyan/s2891/Kconfig                   |    4 --
 src/mainboard/tyan/s2891/devicetree.cb             |    1 +
 src/mainboard/tyan/s2892/Kconfig                   |    4 --
 src/mainboard/tyan/s2892/devicetree.cb             |    1 +
 src/mainboard/tyan/s2895/Kconfig                   |    4 --
 src/mainboard/tyan/s2895/devicetree.cb             |    1 +
 src/mainboard/tyan/s2912/Kconfig                   |    4 --
 src/mainboard/tyan/s2912/devicetree.cb             |    1 +
 src/mainboard/tyan/s2912_fam10/Kconfig             |    4 --
 src/mainboard/tyan/s2912_fam10/devicetree.cb       |    1 +
 src/mainboard/tyan/s4880/Kconfig                   |    4 --
 src/mainboard/tyan/s4880/devicetree.cb             |    1 +
 src/mainboard/tyan/s4882/Kconfig                   |    4 --
 src/mainboard/tyan/s4882/devicetree.cb             |    1 +
 src/mainboard/via/Kconfig                          |    4 --
 src/mainboard/via/pc2500e/Kconfig                  |    8 ---
 src/mainboard/via/pc2500e/devicetree.cb            |    1 +
 src/mainboard/wyse/Kconfig                         |    4 --
 src/southbridge/intel/i82801gx/pci.c               |   13 ++---
 153 files changed, 118 insertions(+), 563 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 28915b2..05b4adb 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -137,13 +137,6 @@ config PCI_BUS_SEGN_BITS
 	int
 	default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x0
 config PCI_ROM_RUN
 	bool
 	default n
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index b6a8078..9070fd7 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -586,16 +586,6 @@ void pci_dev_set_resources(struct device *dev)
 	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 }
 
-unsigned __attribute__((weak)) mainboard_pci_subsystem_vendor_id(__attribute__((unused)) struct device *dev)
-{
-		return CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID;
-}
-
-unsigned __attribute__((weak)) mainboard_pci_subsystem_device_id(__attribute__((unused)) struct device *dev)
-{
-		return CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID;
-}
-
 void pci_dev_enable_resources(struct device *dev)
 {
 	const struct pci_operations *ops;
@@ -603,13 +593,13 @@ void pci_dev_enable_resources(struct device *dev)
 
 	/* Set the subsystem vendor and device ID for mainboard devices. */
 	ops = ops_pci(dev);
-	if (dev->on_mainboard && ops && ops->set_subsystem) {
-		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", dev_path(dev),
-		       mainboard_pci_subsystem_vendor_id(dev),
-		       mainboard_pci_subsystem_device_id(dev));
-		ops->set_subsystem(dev,
-				   mainboard_pci_subsystem_vendor_id(dev),
-				   mainboard_pci_subsystem_device_id(dev));
+	if (dev->on_mainboard && ops && ops->set_subsystem &&
+		dev->subsystem_vendor && dev->subsystem_device) {
+		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
+			dev_path(dev), dev->subsystem_vendor,
+			dev->subsystem_device);
+		ops->set_subsystem(dev, dev->subsystem_vendor,
+			dev->subsystem_device);
 	}
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;
diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig
index d39da7b..2118078 100644
--- a/src/mainboard/amd/bimini_fam10/Kconfig
+++ b/src/mainboard/amd/bimini_fam10/Kconfig
@@ -91,14 +91,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb
index 5916c9f..a5bec74 100644
--- a/src/mainboard/amd/bimini_fam10/devicetree.cb
+++ b/src/mainboard/amd/bimini_fam10/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig
index d1e2649..3d3a04c 100644
--- a/src/mainboard/amd/dbm690t/Kconfig
+++ b/src/mainboard/amd/dbm690t/Kconfig
@@ -59,12 +59,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_AMD_DBM690T
diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb
index d13c5da..e1b01b2 100644
--- a/src/mainboard/amd/dbm690t/devicetree.cb
+++ b/src/mainboard/amd/dbm690t/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index 8a2c834..8e4eca9 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -118,14 +118,6 @@ config ACPI_SSDTX_NUM
         int
         default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-        hex
-        default 0x1510
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-        hex
-        default 0x1022
-
 config RAMBASE
         hex
         default 0x200000
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index a0a19ea..acae2ca 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -23,6 +23,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                 end
         end
         device pci_domain 0 on
+                subsystemid 0x1022 0x1510 inherit
                 chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig
index 09adfcb..731002d 100644
--- a/src/mainboard/amd/mahogany/Kconfig
+++ b/src/mainboard/amd/mahogany/Kconfig
@@ -73,12 +73,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
 endif # BOARD_AMD_MAHOGANY
diff --git a/src/mainboard/amd/mahogany/devicetree.cb b/src/mainboard/amd/mahogany/devicetree.cb
index 7965989..d60d5a1 100644
--- a/src/mainboard/amd/mahogany/devicetree.cb
+++ b/src/mainboard/amd/mahogany/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig
index 0f6c6b3..9c2e081 100644
--- a/src/mainboard/amd/mahogany_fam10/Kconfig
+++ b/src/mainboard/amd/mahogany_fam10/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb
index d1f26d1..c51e53e 100644
--- a/src/mainboard/amd/mahogany_fam10/devicetree.cb
+++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index 650e7aa..66c37f2 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -118,14 +118,6 @@ config ACPI_SSDTX_NUM
         int
         default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-        hex
-        default 0x1510
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-        hex
-        default 0x1022
-
 config RAMBASE
         hex
         default 0x200000
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index 48fd741..8ca165b 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -23,6 +23,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                 end
         end
         device pci_domain 0 on
+                subsystemid 0x1022 0x1510 inherit
                 chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig
index b9f37b3..487a599 100644
--- a/src/mainboard/amd/pistachio/Kconfig
+++ b/src/mainboard/amd/pistachio/Kconfig
@@ -71,12 +71,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_AMD_PISTACHIO
diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb
index 76f0fe7..6608fdd 100644
--- a/src/mainboard/amd/pistachio/devicetree.cb
+++ b/src/mainboard/amd/pistachio/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge, K8 HT Configuration
 				chip southbridge/amd/rs690
diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig
index 6a4aea1..f08fd6e 100644
--- a/src/mainboard/amd/serengeti_cheetah/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah/Kconfig
@@ -82,14 +82,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config ACPI_SSDTX_NUM
 	int
 	default 4
diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
index 8ea682f..b819292 100644
--- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb
+++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x2b80 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
index a49e3c9..4c9d2a0 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
@@ -84,14 +84,6 @@ config ACPI_SSDTX_NUM
 	int
 	default 5
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
index 7c36509..bfbb2b3 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x2b80 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig
index 0d85f86..b18115b 100644
--- a/src/mainboard/amd/tilapia_fam10/Kconfig
+++ b/src/mainboard/amd/tilapia_fam10/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb
index 0a26361..aeb582a 100644
--- a/src/mainboard/amd/tilapia_fam10/devicetree.cb
+++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/arima/hdama/Kconfig b/src/mainboard/arima/hdama/Kconfig
index 0019bb4..7f0e40d 100644
--- a/src/mainboard/arima/hdama/Kconfig
+++ b/src/mainboard/arima/hdama/Kconfig
@@ -21,14 +21,6 @@ config MAINBOARD_DIR
 	string
 	default arima/hdama
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x161f
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3016
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0
diff --git a/src/mainboard/arima/hdama/devicetree.cb b/src/mainboard/arima/hdama/devicetree.cb
index c908921..d7252e2 100644
--- a/src/mainboard/arima/hdama/devicetree.cb
+++ b/src/mainboard/arima/hdama/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x161f 0x3016 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig
index e3eb57a..7021655 100644
--- a/src/mainboard/asrock/939a785gmh/Kconfig
+++ b/src/mainboard/asrock/939a785gmh/Kconfig
@@ -74,12 +74,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
 endif # BOARD_ASROCK_939A785GMH
diff --git a/src/mainboard/asrock/939a785gmh/devicetree.cb b/src/mainboard/asrock/939a785gmh/devicetree.cb
index 76f61b0..1dc92a3 100644
--- a/src/mainboard/asrock/939a785gmh/devicetree.cb
+++ b/src/mainboard/asrock/939a785gmh/devicetree.cb
@@ -16,6 +16,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index 06fd4f0..9b73ea3 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -118,14 +118,6 @@ config ACPI_SSDTX_NUM
         int
         default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-        hex
-        default 0x1510
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-        hex
-        default 0x1022
-
 config RAMBASE
         hex
         default 0x200000
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 648db98..9dceae6 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -23,6 +23,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                 end
         end
         device pci_domain 0 on
+                subsystemid 0x1022 0x1510 inherit
                 chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig
index bf8742a..875fd5a 100644
--- a/src/mainboard/asus/Kconfig
+++ b/src/mainboard/asus/Kconfig
@@ -77,8 +77,4 @@ config MAINBOARD_VENDOR
 	string
 	default "ASUS"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # VENDOR_ASUS
diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig
index 6512589..aca9e33 100644
--- a/src/mainboard/asus/a8n_e/Kconfig
+++ b/src/mainboard/asus/a8n_e/Kconfig
@@ -70,12 +70,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 13
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x815a
-
 endif # BOARD_ASUS_A8N_E
diff --git a/src/mainboard/asus/a8n_e/devicetree.cb b/src/mainboard/asus/a8n_e/devicetree.cb
index 1144f0c..86bf3aa 100644
--- a/src/mainboard/asus/a8n_e/devicetree.cb
+++ b/src/mainboard/asus/a8n_e/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
   end
 
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1043 0x815a inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge
diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig
index f9ac563..05408ca 100644
--- a/src/mainboard/asus/a8v-e_deluxe/Kconfig
+++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig
@@ -70,8 +70,4 @@ config HT_CHAIN_UNITID_BASE
 	hex
 	default 0x0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # BOARD_ASUS_A8V_E_DELUXE
diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig
index abf2bd9..4975cfa 100644
--- a/src/mainboard/asus/a8v-e_se/Kconfig
+++ b/src/mainboard/asus/a8v-e_se/Kconfig
@@ -70,8 +70,4 @@ config HT_CHAIN_UNITID_BASE
 	hex
 	default 0x0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # BOARD_ASUS_A8V_E_SE
diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig
index 60b7e15..c23a2df 100644
--- a/src/mainboard/asus/m2n-e/Kconfig
+++ b/src/mainboard/asus/m2n-e/Kconfig
@@ -98,8 +98,4 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x8239
-
 endif # BOARD_ASUS_M2N_E
diff --git a/src/mainboard/asus/m2n-e/devicetree.cb b/src/mainboard/asus/m2n-e/devicetree.cb
index dbadf0e..bf4de25 100644
--- a/src/mainboard/asus/m2n-e/devicetree.cb
+++ b/src/mainboard/asus/m2n-e/devicetree.cb
@@ -25,6 +25,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1043 0x8239 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig
index b6a2fe6..09157ee 100644
--- a/src/mainboard/asus/m2v-mx_se/Kconfig
+++ b/src/mainboard/asus/m2v-mx_se/Kconfig
@@ -89,8 +89,4 @@ config HT_CHAIN_END_UNITID_BASE
 	hex
 	default 0x20
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # BOARD_ASUS_M2V_MX_SE
diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig
index 757bc32..571b940 100644
--- a/src/mainboard/asus/m2v/Kconfig
+++ b/src/mainboard/asus/m2v/Kconfig
@@ -75,10 +75,6 @@ config HT_CHAIN_UNITID_BASE
 	hex
 	default 0x0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 config IRQ_SLOT_COUNT
 	int
 	default 14
diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig
index 18542d3..d036b21 100644
--- a/src/mainboard/asus/m4a78-em/Kconfig
+++ b/src/mainboard/asus/m4a78-em/Kconfig
@@ -77,14 +77,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x83f1
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/asus/m4a78-em/devicetree.cb b/src/mainboard/asus/m4a78-em/devicetree.cb
index 914fde4..c463d71 100644
--- a/src/mainboard/asus/m4a78-em/devicetree.cb
+++ b/src/mainboard/asus/m4a78-em/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1043 0x83f1 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig
index e41fcc2..84cc06c 100644
--- a/src/mainboard/asus/m4a785-m/Kconfig
+++ b/src/mainboard/asus/m4a785-m/Kconfig
@@ -78,14 +78,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x83a2
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb
index 0736b72..2fad39b 100644
--- a/src/mainboard/asus/m4a785-m/devicetree.cb
+++ b/src/mainboard/asus/m4a785-m/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1043 0x83a2
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig
index 63a2975..4bad57d 100644
--- a/src/mainboard/broadcom/blast/Kconfig
+++ b/src/mainboard/broadcom/blast/Kconfig
@@ -70,12 +70,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x161f
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_BROADCOM_BLAST
diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb
index c50ebc7..6779a7a 100644
--- a/src/mainboard/broadcom/blast/devicetree.cb
+++ b/src/mainboard/broadcom/blast/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x161f 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
                               #  devices on link 0
diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig
index 4185dfc..381c9f6 100644
--- a/src/mainboard/dell/s1850/Kconfig
+++ b/src/mainboard/dell/s1850/Kconfig
@@ -26,14 +26,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "PowerEdge 1850"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x5580
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb
index de8c90b..c56fd37 100644
--- a/src/mainboard/dell/s1850/devicetree.cb
+++ b/src/mainboard/dell/s1850/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x5580 inherit
 		chip southbridge/intel/i82801ex # i82801er
 			# USB ports
 			device pci 1d.0 on end
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
index 6571b31..d25db85 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
@@ -78,14 +78,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1039
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1234
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
index 62f9238..e1aac4e 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x1039 0x1234 inherit
 		chip northbridge/amd/amdk8 #mc0
 			device pci 18.0 on
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index e36dccc..7250a9c 100644
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -82,14 +82,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/gigabyte/m57sli/devicetree.cb b/src/mainboard/gigabyte/m57sli/devicetree.cb
index 3bae560..2184de5 100644
--- a/src/mainboard/gigabyte/m57sli/devicetree.cb
+++ b/src/mainboard/gigabyte/m57sli/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
 end
 device pci_domain 0 on				# PCI domain
+  subsystemid 0x1022 0x2b80 inherit
   chip northbridge/amd/amdk8			# Northbridge / RAM controller
     device pci 18.0 on				# Link 0 == LDT 0
       chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig
index 96b456c..fd511a8 100644
--- a/src/mainboard/gigabyte/ma785gmt/Kconfig
+++ b/src/mainboard/gigabyte/ma785gmt/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/gigabyte/ma785gmt/devicetree.cb b/src/mainboard/gigabyte/ma785gmt/devicetree.cb
index dc7bd10..6cc966a 100644
--- a/src/mainboard/gigabyte/ma785gmt/devicetree.cb
+++ b/src/mainboard/gigabyte/ma785gmt/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig
index cf3f6a2..56b819e 100644
--- a/src/mainboard/gigabyte/ma78gm/Kconfig
+++ b/src/mainboard/gigabyte/ma78gm/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb
index 59e1502..38ff642 100644
--- a/src/mainboard/gigabyte/ma78gm/devicetree.cb
+++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x3060 0x1022 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig
index bb4a33d..eb90b07 100644
--- a/src/mainboard/hp/dl145_g1/Kconfig
+++ b/src/mainboard/hp/dl145_g1/Kconfig
@@ -34,14 +34,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "ProLiant DL145 G1"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x7460
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb
index bd37862..3237723 100644
--- a/src/mainboard/hp/dl145_g1/devicetree.cb
+++ b/src/mainboard/hp/dl145_g1/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
     end
   end
   device pci_domain 0 on
+    subsystemid 0x1022 0x7460 inherit
     chip northbridge/amd/amdk8
       device pci 18.0 on end # link 0
       device pci 18.0 on end # link 1
diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig
index e662fe4..8fb1950 100644
--- a/src/mainboard/iei/kino-780am2-fam10/Kconfig
+++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x0000
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x0000
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig
index 612b1c1..ff8d63b 100644
--- a/src/mainboard/intel/Kconfig
+++ b/src/mainboard/intel/Kconfig
@@ -32,8 +32,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Intel"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
 endif # VENDOR_INTEL
diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
index 04643bb..ff8c638 100644
--- a/src/mainboard/intel/d945gclf/Kconfig
+++ b/src/mainboard/intel/d945gclf/Kconfig
@@ -49,10 +49,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "D945GCLF"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x464C
-
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xf0000000
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index c808cdc..a58d99e 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -26,6 +26,7 @@ chip northbridge/intel/i945
         end
 
         device pci_domain 0 on
+                subsystemid 0x8086 0x464c inherit
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
 		device pci 02.0 on end # vga controller
diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig
index 2ac8ea3..494086e 100644
--- a/src/mainboard/intel/jarrell/Kconfig
+++ b/src/mainboard/intel/jarrell/Kconfig
@@ -35,14 +35,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 18
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1079
-
 config DIMM_MAP_LOGICAL
 	hex
 	default 0x0124
diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb
index a187d23..fb32a08 100644
--- a/src/mainboard/intel/jarrell/devicetree.cb
+++ b/src/mainboard/intel/jarrell/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520
 	device pci_domain 0 on
+		subsystemid 0x8086 0x1079 inherit
 		device pci 00.0 on end
 		device pci 00.1 on end
 		device pci 01.0 on end
diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig
index 76dec5e..76477b0 100644
--- a/src/mainboard/intel/mtarvon/Kconfig
+++ b/src/mainboard/intel/mtarvon/Kconfig
@@ -25,14 +25,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 1
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2680
-
 config DCACHE_RAM_BASE
 	hex
 	default 0xffdf8000
diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb
index 8585b54..cd7df2d 100644
--- a/src/mainboard/intel/mtarvon/devicetree.cb
+++ b/src/mainboard/intel/mtarvon/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/i3100
         device pci_domain 0 on
+                subsystemid 0x8086 0x2680 inherit
                 device pci 00.0 on end # IMCH
                 device pci 00.1 on end # IMCH error status
                 device pci 01.0 on end # IMCH EDMA engine
diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig
index 1ba7137..5f7de08 100644
--- a/src/mainboard/intel/truxton/Kconfig
+++ b/src/mainboard/intel/truxton/Kconfig
@@ -27,14 +27,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 1
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2680
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb
index 7563f02..ced9eb9 100644
--- a/src/mainboard/intel/truxton/devicetree.cb
+++ b/src/mainboard/intel/truxton/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/i3100
         device pci_domain 0 on
+	       subsystemid 0x8086 0x2680 inherit
                 device pci 00.0 on end # IMCH
                 device pci 00.1 on end # IMCH error status
                 device pci 01.0 on end # IMCH EDMA engine
diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig
index 35a1cd1..9163423 100644
--- a/src/mainboard/intel/xe7501devkit/Kconfig
+++ b/src/mainboard/intel/xe7501devkit/Kconfig
@@ -37,12 +37,4 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2480
-
 endif # BOARD_INTEL_XE7501DEVKIT
diff --git a/src/mainboard/intel/xe7501devkit/devicetree.cb b/src/mainboard/intel/xe7501devkit/devicetree.cb
index 3275457..e8b9e82 100644
--- a/src/mainboard/intel/xe7501devkit/devicetree.cb
+++ b/src/mainboard/intel/xe7501devkit/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7501
 	device pci_domain 0 on
+		subsystemid 0x8086 0x2480 inheritx
 		device pci 0.0 on end # Chipset host controller
 		device pci 0.1 on end # Host RASUM controller
 		device pci 2.0 on # Hub interface B
diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig
index 414fa45..e58fe4e 100644
--- a/src/mainboard/iwill/dk8_htx/Kconfig
+++ b/src/mainboard/iwill/dk8_htx/Kconfig
@@ -63,14 +63,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config ACPI_SSDTX_NUM
 	int
 	default 5
diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb
index e1cb939..d0cff02 100644
--- a/src/mainboard/iwill/dk8_htx/devicetree.cb
+++ b/src/mainboard/iwill/dk8_htx/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x2b80 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end
 			device pci 18.0 on end
diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig
index d144b7d..78d0637 100644
--- a/src/mainboard/iwill/dk8s2/Kconfig
+++ b/src/mainboard/iwill/dk8s2/Kconfig
@@ -60,12 +60,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 12
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x161f
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3016
-
 endif # BOARD_IWILL_DK8S2
diff --git a/src/mainboard/iwill/dk8s2/devicetree.cb b/src/mainboard/iwill/dk8s2/devicetree.cb
index 8185b5d..5f27f87 100644
--- a/src/mainboard/iwill/dk8s2/devicetree.cb
+++ b/src/mainboard/iwill/dk8s2/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x161f 0x3016 inheritx
 		chip northbridge/amd/amdk8
 			device pci 18.0 on # LDT 0
 				chip southbridge/amd/amd8131
diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig
index 10fab73..62adb53 100644
--- a/src/mainboard/jetway/pa78vm5/Kconfig
+++ b/src/mainboard/jetway/pa78vm5/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/jetway/pa78vm5/devicetree.cb b/src/mainboard/jetway/pa78vm5/devicetree.cb
index 73f6ac2..5ce3a6d 100644
--- a/src/mainboard/jetway/pa78vm5/devicetree.cb
+++ b/src/mainboard/jetway/pa78vm5/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+	       subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig
index 891de59..91d6b67 100644
--- a/src/mainboard/kontron/kt690/Kconfig
+++ b/src/mainboard/kontron/kt690/Kconfig
@@ -28,14 +28,6 @@ config MAINBOARD_DIR
 	string
 	default kontron/kt690
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1488
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6900
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0
diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb
index d509050..e589641 100644
--- a/src/mainboard/kontron/kt690/devicetree.cb
+++ b/src/mainboard/kontron/kt690/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+	       subsystemid 0x1488 0x6900 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 40e16b3..a6664bc 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -29,9 +29,15 @@ chip northbridge/intel/i945
         end
 
         device pci_domain 0 on
-                device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 02.1 on end # display controller
+                device pci 00.0 on # Host bridge
+			subsystemid 0x17aa 0x2017
+		end
+		device pci 02.0 on # VGA controller
+			subsystemid 0x17aa 0x201a
+		end
+		device pci 02.1 on # display controller
+			subsystemid 0x17aa 0x201a
+		end
                 chip southbridge/intel/i82801gx
 			register "pirqa_routing" = "0x0b"
 			register "pirqb_routing" = "0x0b"
@@ -54,15 +60,28 @@ chip northbridge/intel/i945
 
 			register "gpe0_en" = "0x11000006"
 
-			device pci 1b.0 on end # Audio Controller
+			device pci 1b.0 on # Audio Cnotroller
+				subsystemid 0x17aa 0x2010
+			end
 			device pci 1c.0 on end # Ethernet
 			device pci 1c.1 on end # Atheros WLAN
-			device pci 1d.0 on end # USB UHCI
-			device pci 1d.1 on end # USB UHCI
-			device pci 1d.2 on end # USB UHCI
-			device pci 1d.3 on end # USB UHCI
-			device pci 1d.7 on end # USB2 EHCI
+			device pci 1d.0 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.1 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.2 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.3 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.7 on # USB2 EHCI
+				subsystemid 0x17aa 0x200b
+			end
 			device pci 1f.0 on # PCI-LPC bridge
+				subsystemid 0x17aa 0x2009
 				chip ec/lenovo/pmh7
 					device pnp ff.1 on # dummy
 					end
@@ -120,9 +139,15 @@ chip northbridge/intel/i945
 					end
 				end
 			end
-			device pci 1f.1 off end # IDE
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
+			device pci 1f.1 off # IDE
+				subsystemid 0x17aa 0x200c
+			end
+                        device pci 1f.2 on # SATA
+				subsystemid 0x17aa 0x200d
+			end
+                        device pci 1f.3 on # SMBUS
+				subsystemid 0x17aa 0x200f
+			end
 		end
 		chip southbridge/ricoh/rl5c476
 		end
diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig
index c2f1595..3d0de4a 100644
--- a/src/mainboard/msi/Kconfig
+++ b/src/mainboard/msi/Kconfig
@@ -56,8 +56,4 @@ config MAINBOARD_VENDOR
 	string
 	default "MSI"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
 endif # VENDOR_MSI
diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig
index d8581f7..0611be2 100644
--- a/src/mainboard/msi/ms7135/Kconfig
+++ b/src/mainboard/msi/ms7135/Kconfig
@@ -34,10 +34,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "MS-7135"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x7135
-
 config MAX_CPUS
 	int
 	default 2
diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb
index 14c6bad..54e5d5e 100644
--- a/src/mainboard/msi/ms7135/devicetree.cb
+++ b/src/mainboard/msi/ms7135/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
   end
 
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x7135 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge
diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig
index aec6af5..be425ec 100644
--- a/src/mainboard/msi/ms7260/Kconfig
+++ b/src/mainboard/msi/ms7260/Kconfig
@@ -80,14 +80,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x7260
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/msi/ms7260/devicetree.cb b/src/mainboard/msi/ms7260/devicetree.cb
index 552224d..47d5381 100644
--- a/src/mainboard/msi/ms7260/devicetree.cb
+++ b/src/mainboard/msi/ms7260/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x7260 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig
index 5e28353..1464acd 100644
--- a/src/mainboard/msi/ms9185/Kconfig
+++ b/src/mainboard/msi/ms9185/Kconfig
@@ -71,12 +71,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 endif # BOARD_MSI_MS9185
diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb
index fc566e2..4051c10 100644
--- a/src/mainboard/msi/ms9185/devicetree.cb
+++ b/src/mainboard/msi/ms9185/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
        device pci_domain 0 on
+       	      subsystemid 0x1022 0x2b80 inherit
                chip northbridge/amd/amdk8
                        device pci 18.0 on end
                        device pci 18.0 on end
diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig
index f2ea65a..3ccc3f9 100644
--- a/src/mainboard/msi/ms9282/Kconfig
+++ b/src/mainboard/msi/ms9282/Kconfig
@@ -72,14 +72,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x9282
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb
index 74ea183..b52e7ed 100644
--- a/src/mainboard/msi/ms9282/devicetree.cb
+++ b/src/mainboard/msi/ms9282/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x9282 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
index d8025d7..948d320 100644
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -87,14 +87,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "MS-9652"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x9652
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb
index c3e4e4f..0e9a3ff 100644
--- a/src/mainboard/msi/ms9652_fam10/devicetree.cb
+++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb
@@ -28,6 +28,7 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x9652 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on			# Link 0
         chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig
index d11d6ea..fc4c223 100644
--- a/src/mainboard/newisys/khepri/Kconfig
+++ b/src/mainboard/newisys/khepri/Kconfig
@@ -69,12 +69,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 9
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x17c2
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x10
-
 endif # BOARD_NEWISYS_KHEPRI
diff --git a/src/mainboard/newisys/khepri/devicetree.cb b/src/mainboard/newisys/khepri/devicetree.cb
index a56a010..97d506a 100644
--- a/src/mainboard/newisys/khepri/devicetree.cb
+++ b/src/mainboard/newisys/khepri/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdk8/root_complex
 	end
 
 	device pci_domain 0 on
+	       subsystemid 0x17c2 0x0010 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end # LDT 0
 			device pci 18.0 on     # LDT 1
diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index 80f5e34..bfec323 100644
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -84,14 +84,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/nvidia/l1_2pvv/devicetree.cb b/src/mainboard/nvidia/l1_2pvv/devicetree.cb
index 1340cb3..9a80710 100644
--- a/src/mainboard/nvidia/l1_2pvv/devicetree.cb
+++ b/src/mainboard/nvidia/l1_2pvv/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1022 0x2b80 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/roda/Kconfig b/src/mainboard/roda/Kconfig
index d2f1e95..ba4b6ec 100644
--- a/src/mainboard/roda/Kconfig
+++ b/src/mainboard/roda/Kconfig
@@ -14,8 +14,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Roda"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x4352
-
 endif # VENDOR_RODA
diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index 647511a..340ee98 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -46,10 +46,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6886
-
 config MAXIMUM_SUPPORTED_FREQUENCY
 	int
 	default 400
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index a713331..7439462 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -28,6 +28,7 @@ chip northbridge/intel/i945
         end
 
         device pci_domain 0 on
+	       subsystemid 0x4352 0x0686 inherit
                 device pci 00.0 on end # host bridge
 		# auto detection:
 		#device pci 01.0 off end # i945 PCIe root port
diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig
index 3b8544b..81a6608 100644
--- a/src/mainboard/sunw/ultra40/Kconfig
+++ b/src/mainboard/sunw/ultra40/Kconfig
@@ -75,12 +75,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x108e
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x40
-
 endif # BOARD_SUNW_ULTRA40
diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb
index 059724e..829a7d4 100644
--- a/src/mainboard/sunw/ultra40/devicetree.cb
+++ b/src/mainboard/sunw/ultra40/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+   subsystemid 0x108e 0x40 inheritx
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on			# Link 0 == LDT 0
diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig
index 5ac7dda..8e5694c 100644
--- a/src/mainboard/supermicro/Kconfig
+++ b/src/mainboard/supermicro/Kconfig
@@ -38,8 +38,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Supermicro"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
 endif # VENDOR_SUPERMICRO
diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig
index 0259b4a..ce49a47 100644
--- a/src/mainboard/supermicro/h8dme/Kconfig
+++ b/src/mainboard/supermicro/h8dme/Kconfig
@@ -81,12 +81,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 endif # BOARD_SUPERMICRO_H8DME
diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb
index df40dc3..73a43e8 100644
--- a/src/mainboard/supermicro/h8dme/devicetree.cb
+++ b/src/mainboard/supermicro/h8dme/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig
index 81517be..5527319 100644
--- a/src/mainboard/supermicro/h8dmr/Kconfig
+++ b/src/mainboard/supermicro/h8dmr/Kconfig
@@ -80,12 +80,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 endif # BOARD_SUPERMICRO_H8DMR
diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb
index 1dfd32a..6c96ac0 100644
--- a/src/mainboard/supermicro/h8dmr/devicetree.cb
+++ b/src/mainboard/supermicro/h8dmr/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig
index 4b31bf3..195bc5c 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig
@@ -100,8 +100,4 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 endif # BOARD_SUPERMICRO_H8DMR_FAM10
diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
index da82b17..6c4443f 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig
index bd0f550..1d4f8e7 100644
--- a/src/mainboard/supermicro/h8qme_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig
@@ -99,10 +99,6 @@ config SERIAL_CPU_INIT
 	bool
 	default y
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 config STACK_SIZE
 	hex
 	default 0x10000
diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
index 990afa4..56ba7b5 100644
--- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/supermicro/x6dai_g/Kconfig b/src/mainboard/supermicro/x6dai_g/Kconfig
index 8b1cf5a..bac1008 100644
--- a/src/mainboard/supermicro/x6dai_g/Kconfig
+++ b/src/mainboard/supermicro/x6dai_g/Kconfig
@@ -23,14 +23,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "X6DAi-G"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6780
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/supermicro/x6dai_g/devicetree.cb b/src/mainboard/supermicro/x6dai_g/devicetree.cb
index c8ce779..e6201a8 100644
--- a/src/mainboard/supermicro/x6dai_g/devicetree.cb
+++ b/src/mainboard/supermicro/x6dai_g/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7525 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x6780 inherit
 		chip southbridge/intel/esb6300  # esb6300
 			register "pirq_a_d" = "0x0b0a0a05"
 			register "pirq_e_h" = "0x0a0b0c80"
diff --git a/src/mainboard/supermicro/x6dhe_g/Kconfig b/src/mainboard/supermicro/x6dhe_g/Kconfig
index 8771d9e..e8466be 100644
--- a/src/mainboard/supermicro/x6dhe_g/Kconfig
+++ b/src/mainboard/supermicro/x6dhe_g/Kconfig
@@ -25,14 +25,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "X6DHE-G"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6080
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/supermicro/x6dhe_g/devicetree.cb b/src/mainboard/supermicro/x6dhe_g/devicetree.cb
index 6dd6b17..08c0751 100644
--- a/src/mainboard/supermicro/x6dhe_g/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhe_g/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/intel/e7520  # MCH
 		device pnp 00.3 off end
 	end
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x6080 inherit
 		chip southbridge/intel/esb6300	# ESB6300
 			register "pirq_a_d" = "0x0b070a05"
 			register "pirq_e_h" = "0x0a808080"
diff --git a/src/mainboard/supermicro/x6dhe_g2/Kconfig b/src/mainboard/supermicro/x6dhe_g2/Kconfig
index 96549d6..e9d4041 100644
--- a/src/mainboard/supermicro/x6dhe_g2/Kconfig
+++ b/src/mainboard/supermicro/x6dhe_g2/Kconfig
@@ -26,14 +26,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "X6DHE-G2"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6080
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
index 04110b0..ecfe0a0 100644
--- a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/intel/e7520  # MCH
 		device pnp 00.3 off end
 	end
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x6080 inherit
 		chip southbridge/intel/i82801ex	# ICH5R
 			register "pirq_a_d" = "0x0b070a05"
 			register "pirq_e_h" = "0x0a808080"
diff --git a/src/mainboard/supermicro/x6dhr_ig/Kconfig b/src/mainboard/supermicro/x6dhr_ig/Kconfig
index d1163d7..a146e77 100644
--- a/src/mainboard/supermicro/x6dhr_ig/Kconfig
+++ b/src/mainboard/supermicro/x6dhr_ig/Kconfig
@@ -25,14 +25,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "X6DHR-iG"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x5580
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
index df778ed..6ada3b1 100644
--- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x5580 inherit
 		chip southbridge/intel/i82801ex # i82801er
 			# USB ports
 			device pci 1d.0 on end
diff --git a/src/mainboard/supermicro/x6dhr_ig2/Kconfig b/src/mainboard/supermicro/x6dhr_ig2/Kconfig
index 494b0ed..6196e2a 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/Kconfig
+++ b/src/mainboard/supermicro/x6dhr_ig2/Kconfig
@@ -25,14 +25,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "X6DHR-iG2"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x5580
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
index 77c9e9d..3d9b644 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x5580 inherit
 		chip southbridge/intel/i82801ex # i82801er
 			# USB ports
 			device pci 1d.0 on end
diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig
index d855df1..21cfa7b 100644
--- a/src/mainboard/technexion/tim5690/Kconfig
+++ b/src/mainboard/technexion/tim5690/Kconfig
@@ -60,14 +60,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 config STACK_SIZE
 	hex
 	default 0x2000
diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb
index c129a2d..970d0e2 100644
--- a/src/mainboard/technexion/tim5690/devicetree.cb
+++ b/src/mainboard/technexion/tim5690/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+	       subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig
index b9f34ad..5af6ace 100644
--- a/src/mainboard/technexion/tim8690/Kconfig
+++ b/src/mainboard/technexion/tim8690/Kconfig
@@ -59,12 +59,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_TECHNEXION_TIM8690
diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb
index 55a2e05..6981dbc 100644
--- a/src/mainboard/technexion/tim8690/devicetree.cb
+++ b/src/mainboard/technexion/tim8690/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+	       subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
diff --git a/src/mainboard/tyan/Kconfig b/src/mainboard/tyan/Kconfig
index 6af48a2..01e4f35 100644
--- a/src/mainboard/tyan/Kconfig
+++ b/src/mainboard/tyan/Kconfig
@@ -74,8 +74,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Tyan"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x10f1
-
 endif # VENDOR_TYAN
diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig
index e1f475b..4aafa3c 100644
--- a/src/mainboard/tyan/s2735/Kconfig
+++ b/src/mainboard/tyan/s2735/Kconfig
@@ -45,8 +45,4 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2735
-
 endif # BOARD_TYAN_S2735
diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb
index b519a4a..542a013 100644
--- a/src/mainboard/tyan/s2735/devicetree.cb
+++ b/src/mainboard/tyan/s2735/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7501
         device pci_domain 0 on
+	       subsystemid 0x10f1 0x2735 inherit
 		device pci 0.0 on end
         	device pci 0.1 on end
         	device pci 2.0 on
diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig
index ab5897a..c555951 100644
--- a/src/mainboard/tyan/s2850/Kconfig
+++ b/src/mainboard/tyan/s2850/Kconfig
@@ -23,10 +23,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2850"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2850
-
 config MAX_CPUS
 	int
 	default 2
diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb
index 6a9a420..0ec3d6e 100644
--- a/src/mainboard/tyan/s2850/devicetree.cb
+++ b/src/mainboard/tyan/s2850/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x2850 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on # LDT0
 				#  devices on link 2, link 2 == LDT 2
diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig
index 89a1177..56c3723 100644
--- a/src/mainboard/tyan/s2875/Kconfig
+++ b/src/mainboard/tyan/s2875/Kconfig
@@ -25,10 +25,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2875"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2875
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb
index d3c2582..c9f0dd2 100644
--- a/src/mainboard/tyan/s2875/devicetree.cb
+++ b/src/mainboard/tyan/s2875/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x2875 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig
index a98ec06..87ec6ca 100644
--- a/src/mainboard/tyan/s2880/Kconfig
+++ b/src/mainboard/tyan/s2880/Kconfig
@@ -33,10 +33,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2880"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2880
-
 config MAX_CPUS
 	int
 	default 2
diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb
index ba43b27..735b4e6 100644
--- a/src/mainboard/tyan/s2880/devicetree.cb
+++ b/src/mainboard/tyan/s2880/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x2880 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig
index 81a349d..fd5fca8 100644
--- a/src/mainboard/tyan/s2881/Kconfig
+++ b/src/mainboard/tyan/s2881/Kconfig
@@ -35,10 +35,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2881"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2881
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2881/devicetree.cb b/src/mainboard/tyan/s2881/devicetree.cb
index 2422459..7e836ff 100644
--- a/src/mainboard/tyan/s2881/devicetree.cb
+++ b/src/mainboard/tyan/s2881/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
     end
   end
   device pci_domain 0 on
+    subsystemid 0x10f1 0x2881 inherit
     chip northbridge/amd/amdk8
       device pci 18.0 on end # link 0
       device pci 18.0 on end # link 1
diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig
index 00e813a..c6711b3 100644
--- a/src/mainboard/tyan/s2882/Kconfig
+++ b/src/mainboard/tyan/s2882/Kconfig
@@ -34,10 +34,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2882"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2882
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb
index b8f2160..bbc4a59 100644
--- a/src/mainboard/tyan/s2882/devicetree.cb
+++ b/src/mainboard/tyan/s2882/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdk8/root_complex
         end
 
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x2882 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig
index 03a5952..f4a6f49 100644
--- a/src/mainboard/tyan/s2885/Kconfig
+++ b/src/mainboard/tyan/s2885/Kconfig
@@ -35,10 +35,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2885"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2885
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb
index 0eb1b9e..7e45a8c 100644
--- a/src/mainboard/tyan/s2885/devicetree.cb
+++ b/src/mainboard/tyan/s2885/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x2885 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on # LDT0
 				chip southbridge/amd/amd8151
diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig
index 31e99b6..2848380 100644
--- a/src/mainboard/tyan/s2891/Kconfig
+++ b/src/mainboard/tyan/s2891/Kconfig
@@ -36,10 +36,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2891"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2891
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2891/devicetree.cb b/src/mainboard/tyan/s2891/devicetree.cb
index 73034b1..d793640 100644
--- a/src/mainboard/tyan/s2891/devicetree.cb
+++ b/src/mainboard/tyan/s2891/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2891 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge
diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig
index df3430b..88703f3 100644
--- a/src/mainboard/tyan/s2892/Kconfig
+++ b/src/mainboard/tyan/s2892/Kconfig
@@ -35,10 +35,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2892"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2892
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2892/devicetree.cb b/src/mainboard/tyan/s2892/devicetree.cb
index b84c041..3b999ca 100644
--- a/src/mainboard/tyan/s2892/devicetree.cb
+++ b/src/mainboard/tyan/s2892/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2892 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge
diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig
index 0f8482b..f35ea82 100644
--- a/src/mainboard/tyan/s2895/Kconfig
+++ b/src/mainboard/tyan/s2895/Kconfig
@@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2895"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2895
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2895/devicetree.cb b/src/mainboard/tyan/s2895/devicetree.cb
index 7841a0e..7d7abc3 100644
--- a/src/mainboard/tyan/s2895/devicetree.cb
+++ b/src/mainboard/tyan/s2895/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2895 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge
diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig
index 466cb4a..811e9a7 100644
--- a/src/mainboard/tyan/s2912/Kconfig
+++ b/src/mainboard/tyan/s2912/Kconfig
@@ -79,10 +79,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2912
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/tyan/s2912/devicetree.cb b/src/mainboard/tyan/s2912/devicetree.cb
index 11c6a73..0ce4a48 100644
--- a/src/mainboard/tyan/s2912/devicetree.cb
+++ b/src/mainboard/tyan/s2912/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2912 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index 58cdb9c..d7d5114 100644
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -80,10 +80,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2912
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb
index 8373ffc..43bdeb6 100644
--- a/src/mainboard/tyan/s2912_fam10/devicetree.cb
+++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2912 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig
index 5147b97..0b425b9 100644
--- a/src/mainboard/tyan/s4880/Kconfig
+++ b/src/mainboard/tyan/s4880/Kconfig
@@ -65,8 +65,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 22
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x4880
-
 endif # BOARD_TYAN_S4880
diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb
index cb34235..4f21cf3 100644
--- a/src/mainboard/tyan/s4880/devicetree.cb
+++ b/src/mainboard/tyan/s4880/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdk8/root_complex
         end
 
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x4880 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end # LDT0
 			device pci 18.0 on end # LDT1
diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig
index b0d8897..3aa1690 100644
--- a/src/mainboard/tyan/s4882/Kconfig
+++ b/src/mainboard/tyan/s4882/Kconfig
@@ -65,8 +65,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 22
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x4882
-
 endif # BOARD_TYAN_S4882
diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb
index d4a7017..9476c8f 100644
--- a/src/mainboard/tyan/s4882/devicetree.cb
+++ b/src/mainboard/tyan/s4882/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x4882 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end # LDT0
 			device pci 18.0 on #  northbridge
diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig
index f272247..6980548 100644
--- a/src/mainboard/via/Kconfig
+++ b/src/mainboard/via/Kconfig
@@ -32,8 +32,4 @@ config MAINBOARD_VENDOR
 	string
 	default "VIA"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1019
-
 endif # VENDOR_VIA
diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig
index 3244ea9..70aa8d7 100644
--- a/src/mainboard/via/pc2500e/Kconfig
+++ b/src/mainboard/via/pc2500e/Kconfig
@@ -26,14 +26,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 10
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1019
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0xaa51
-
 config VGA_BIOS_FILE
 	string
 	default "M14CRT.ROM"
diff --git a/src/mainboard/via/pc2500e/devicetree.cb b/src/mainboard/via/pc2500e/devicetree.cb
index a891ef1..05ce877 100644
--- a/src/mainboard/via/pc2500e/devicetree.cb
+++ b/src/mainboard/via/pc2500e/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/via/cn700			# Northbridge
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1019 0xaa51 inherit
     device pci 0.0 on end			# AGP Bridge
     device pci 0.1 on end			# Error Reporting
     device pci 0.2 on end			# Host Bus Control
diff --git a/src/mainboard/wyse/Kconfig b/src/mainboard/wyse/Kconfig
index 2607d6c..e4a89d9 100644
--- a/src/mainboard/wyse/Kconfig
+++ b/src/mainboard/wyse/Kconfig
@@ -32,8 +32,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Wyse"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x102d
-
 endif # VENDOR_WYSE
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index a8e8988..a433b5b 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -70,14 +70,13 @@ static void ich_pci_dev_enable_resources(struct device *dev)
 
 	/* Set the subsystem vendor and device id for mainboard devices */
 	ops = ops_pci(dev);
-	if (dev->on_mainboard && ops && ops->set_subsystem) {
+	if (dev->on_mainboard && ops && ops->set_subsystem &&
+	    dev->subsystem_vendor && dev->subsystem_device) {
 		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
-			dev_path(dev),
-			mainboard_pci_subsystem_vendor_id(dev),
-			mainboard_pci_subsystem_device_id(dev));
-		ops->set_subsystem(dev,
-			mainboard_pci_subsystem_vendor_id(dev),
-			mainboard_pci_subsystem_device_id(dev));
+		       dev_path(dev), dev->subsystem_vendor,
+		       dev->subsystem_device);
+		ops->set_subsystem(dev, dev->subsystem_vendor,
+				   dev->subsystem_device);
 	}
 
 	command = pci_read_config16(dev, PCI_COMMAND);
-- 
1.7.4.1




From svn at coreboot.org  Tue Mar  1 16:18:26 2011
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Mar 2011 15:18:26 -0000
Subject: [coreboot]  #175: Gift Baskets
Message-ID: <063.f8e231f3d63fc36f91b0b817f3e8eb55@coreboot.org>

#175: Gift Baskets
------------------------------------+----------------------------------
    Reporter:  ronnie.liloonline@?  |         Owner:  stepan@?
        Type:  defect               |        Status:  new
    Priority:  major                |     Milestone:
   Component:  coreboot             |      Keywords:  gift baskets
Dependencies:                       |  Patch Status:  there is no patch
------------------------------------+----------------------------------
 == Gift Baskets - How To Make Your Own Valentine's Day Gift Baskets ==

 [[Image(http://s6.thisnext.com/media/largest_dimension/B3679D57.jpg)]]

 When you wanted to make such '''[http://www.giftbasketsplus.com/ gift
 baskets]''' in making things that can be better for them having such ways
 to have its ways that will make those people whom you wanted to give such
 '''baskets''' in a certain period of time. There are things that will make
 those people have such '''shopping baskets''' makings such ways to satisfy
 their needs in life living in this world. For such situations that a
 certain individual can have the things that will be best for them to think
 about such ways to have its best ways in life living.

 [[Image(http://www.withourbest.com/wp-content/uploads/2010/11/Corporate-
 Gift-Basket.png)]]

 Making things that is best for those people having the things that can be
 better for them having such '''[http://trac.cps-cms.org/ticket/2343 gift
 baskets]''' in a certain period of time. For the things that can be better
 for them in making such ways to have such ways that will make them have a
 '''gift basket''' that will make them have the things they may need in
 life.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/175>
coreboot <http://www.coreboot.org/>


From svens at stackframe.org  Tue Mar  1 17:28:28 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue,  1 Mar 2011 17:28:28 +0100
Subject: [coreboot] [PATCH v2] new subsystemid option for scnfig
Message-ID: <1298996910-9031-1-git-send-email-svens@stackframe.org>

Hi List,

i fixed a few boards which missed the proper Kconfig/sconfig conversion.
Thanks to Peter Stuge for pointing that out. Also fix a few white space errors.




From svens at stackframe.org  Tue Mar  1 17:28:29 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue,  1 Mar 2011 17:28:29 +0100
Subject: [coreboot] [PATCH 1/2] Add subsystemid option to sconfig
In-Reply-To: <1298996910-9031-1-git-send-email-svens@stackframe.org>
References: <1298996910-9031-1-git-send-email-svens@stackframe.org>
Message-ID: <1298996910-9031-2-git-send-email-svens@stackframe.org>

Allow user to add 'subsystemid <vendor> <device> [inherit]' to devicetree.cb for
PCI and PCI domain devices.

Example:

	device pci 00.0 on
	       subsystemid dead beef
	end

If the user wants to have this ID inherited to all subdevices/functions,
he can add 'inherit', like in the following example:

	device pci 00.0 on
	       subsystemid dead beef inherit
	end

If the user don't want to inherit a Subsystem for a single device, he can
specify 'subsystemid 0 0' on this particular device.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/include/device/device.h        |    2 +
 util/sconfig/main.c                |   46 +++++++++++++
 util/sconfig/sconfig.h             |    4 +
 util/sconfig/sconfig.l             |    2 +
 util/sconfig/sconfig.tab.c_shipped |  124 +++++++++++++++++++++---------------
 util/sconfig/sconfig.tab.h_shipped |    4 +-
 util/sconfig/sconfig.y             |   12 +++-
 7 files changed, 139 insertions(+), 55 deletions(-)

diff --git a/src/include/device/device.h b/src/include/device/device.h
index 7dbbb4f..f6bbe9a 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -64,6 +64,8 @@ struct device {
 	struct device_path path;
 	unsigned 	vendor;
 	unsigned 	device;
+	unsigned subsystem_vendor;
+	unsigned subsystem_device;
 	unsigned int	class;		/* 3 bytes: (base, sub, prog-if) */
 	unsigned int	hdr_type;	/* PCI header type */
 	unsigned int    enabled : 1;	/* set if we should enable the device */
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index a3994fb..727fcce 100755
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -59,6 +59,8 @@ static struct device *new_dev(struct device *parent, struct device *bus) {
 	dev->id = ++devcount;
 	dev->parent = parent;
 	dev->bus = bus;
+	dev->subsystem_vendor = -1;
+	dev->subsystem_device = -1;
 	head->next = dev;
 	head = dev;
 	return dev;
@@ -279,6 +281,18 @@ void add_register(struct device *dev, char *name, char *val) {
 	}
 }
 
+void add_pci_subsystem_ids(struct device *dev, int vendor, int device, int inherit)
+{
+	if (dev->bustype != PCI && dev->bustype != PCI_DOMAIN) {
+		printf("ERROR: 'subsystem' only allowed for PCI devices\n");
+		exit(1);
+	}
+
+	dev->subsystem_vendor = vendor;
+	dev->subsystem_device = device;
+	dev->inherit_subsystem = inherit;
+}
+
 static void pass0(FILE *fil, struct device *ptr) {
 	if (ptr->type == device && ptr->id == 0)
 		fprintf(fil, "struct bus %s_links[];\n", ptr->name);
@@ -303,6 +317,12 @@ static void pass1(FILE *fil, struct device *ptr) {
 		fprintf(fil, "},\n");
 		fprintf(fil, "\t.enabled = %d,\n", ptr->enabled);
 		fprintf(fil, "\t.on_mainboard = 1,\n");
+		if (ptr->subsystem_vendor > 0)
+			fprintf(fil, "\t.subsystem_vendor = 0x%04x,\n", ptr->subsystem_vendor);
+
+		if (ptr->subsystem_device > 0)
+			fprintf(fil, "\t.subsystem_device = 0x%04x,\n", ptr->subsystem_device);
+
 		if (ptr->rescnt > 0) {
 			fprintf(fil, "\t.resource_list = &%s_res[0],\n", ptr->name);
 		}
@@ -392,6 +412,29 @@ static void walk_device_tree(FILE *fil, struct device *ptr, void (*func)(FILE *,
 	} while (ptr);
 }
 
+static void inherit_subsystem_ids(FILE *file, struct device *dev)
+{
+	struct device *p;
+	int i =0;
+
+	if (dev->subsystem_vendor != -1 && dev->subsystem_device != -1) {
+		/* user already gave us a subsystem vendor/device */
+		return;
+	}
+
+	for(p = dev; p && p != p->parent; (p = p->parent), i++) {
+
+		if (p->bustype != PCI && p->bustype != PCI_DOMAIN)
+			continue;
+
+		if (p->inherit_subsystem) {
+			dev->subsystem_vendor = p->subsystem_vendor;
+			dev->subsystem_device = p->subsystem_device;
+			break;
+		}
+	}
+}
+
 int main(int argc, char** argv) {
 	if (argc != 3) {
 		printf("usage: sconfig vendor/mainboard outputdir\n");
@@ -444,6 +487,9 @@ int main(int argc, char** argv) {
 		h = h->next;
 		fprintf(staticc, "#include \"%s/chip.h\"\n", h->name);
 	}
+
+	walk_device_tree(staticc, &root, inherit_subsystem_ids, NULL);
+
 	fprintf(staticc, "\n/* pass 0 */\n");
 	walk_device_tree(staticc, &root, pass0, NULL);
 	fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device *last_dev = &%s;\n", lastdev->name);
diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h
index 8fbae6a..d893c05 100755
--- a/util/sconfig/sconfig.h
+++ b/util/sconfig/sconfig.h
@@ -52,6 +52,9 @@ struct device {
 	int link;
 	int rescnt;
 	int chiph_exists;
+	int subsystem_vendor;
+	int subsystem_device;
+	int inherit_subsystem;
 	char *ops;
 	char *name;
 	char *name_underscore;
@@ -90,3 +93,4 @@ struct device *new_device(struct device *parent, struct device *busdev, const in
 void alias_siblings(struct device *d);
 void add_resource(struct device *dev, int type, int index, int base);
 void add_register(struct device *dev, char *name, char *val);
+void add_pci_subsystem_ids(struct device *dev, int vendor, int device, int inherit);
diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l
index 3d1593a..50c315b 100755
--- a/util/sconfig/sconfig.l
+++ b/util/sconfig/sconfig.l
@@ -42,6 +42,8 @@ pci_domain	{yylval.number=PCI_DOMAIN; return(BUS);}
 irq		{yylval.number=IRQ; return(RESOURCE);}
 drq		{yylval.number=DRQ; return(RESOURCE);}
 io		{yylval.number=IO; return(RESOURCE);}
+inherit		{return(INHERIT);}
+subsystemid	{return(SUBSYSTEMID);}
 end		{return(END);}
 =		{return(EQUALS);}
 0x[0-9a-fA-F.]+	{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped
index 4c78b62..dbefe06 100644
--- a/util/sconfig/sconfig.tab.c_shipped
+++ b/util/sconfig/sconfig.tab.c_shipped
@@ -139,7 +139,9 @@ static struct device *cur_parent, *cur_bus;
      IRQ = 274,
      DRQ = 275,
      IO = 276,
-     NUMBER = 277
+     NUMBER = 277,
+     SUBSYSTEMID = 278,
+     INHERIT = 279
    };
 #endif
 
@@ -380,20 +382,20 @@ union yyalloc
 /* YYFINAL -- State number of the termination state.  */
 #define YYFINAL  3
 /* YYLAST -- Last index in YYTABLE.  */
-#define YYLAST   24
+#define YYLAST   34
 
 /* YYNTOKENS -- Number of terminals.  */
-#define YYNTOKENS  23
+#define YYNTOKENS  25
 /* YYNNTS -- Number of nonterminals.  */
-#define YYNNTS  11
+#define YYNNTS  12
 /* YYNRULES -- Number of rules.  */
-#define YYNRULES  17
+#define YYNRULES  20
 /* YYNRULES -- Number of states.  */
-#define YYNSTATES  31
+#define YYNSTATES  36
 
 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
 #define YYUNDEFTOK  2
-#define YYMAXUTOK   277
+#define YYMAXUTOK   279
 
 #define YYTRANSLATE(YYX)						\
   ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
@@ -428,7 +430,7 @@ static const yytype_uint8 yytranslate[] =
        2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
        2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
        5,     6,     7,     8,     9,    10,    11,    12,    13,    14,
-      15,    16,    17,    18,    19,    20,    21,    22
+      15,    16,    17,    18,    19,    20,    21,    22,    23,    24
 };
 
 #if YYDEBUG
@@ -437,25 +439,28 @@ static const yytype_uint8 yytranslate[] =
 static const yytype_uint8 yyprhs[] =
 {
        0,     0,     3,     4,     7,    10,    13,    16,    17,    20,
-      23,    26,    27,    28,    34,    35,    43,    48
+      23,    26,    29,    30,    31,    37,    38,    46,    51,    56,
+      60
 };
 
 /* YYRHS -- A `-1'-separated list of the rules' RHS.  */
 static const yytype_int8 yyrhs[] =
 {
-      24,     0,    -1,    -1,    25,    28,    -1,    26,    30,    -1,
-      26,    28,    -1,    26,    33,    -1,    -1,    27,    30,    -1,
-      27,    28,    -1,    27,    32,    -1,    -1,    -1,     3,    12,
-      29,    26,     9,    -1,    -1,     4,     7,    22,     6,    31,
-      27,     9,    -1,     8,    22,    10,    22,    -1,     5,    12,
-      10,    12,    -1
+      26,     0,    -1,    -1,    27,    30,    -1,    28,    32,    -1,
+      28,    30,    -1,    28,    35,    -1,    -1,    29,    32,    -1,
+      29,    30,    -1,    29,    34,    -1,    29,    36,    -1,    -1,
+      -1,     3,    12,    31,    28,     9,    -1,    -1,     4,     7,
+      22,     6,    33,    29,     9,    -1,     8,    22,    10,    22,
+      -1,     5,    12,    10,    12,    -1,    23,    22,    22,    -1,
+      23,    22,    22,    24,    -1
 };
 
 /* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
 static const yytype_uint8 yyrline[] =
 {
-       0,    34,    34,    34,    36,    36,    36,    36,    38,    38,
-      38,    38,    40,    40,    50,    50,    62,    65
+       0,    35,    35,    35,    37,    37,    37,    37,    39,    39,
+      39,    39,    39,    41,    41,    51,    51,    63,    66,    69,
+      72
 };
 #endif
 
@@ -467,8 +472,9 @@ static const char *const yytname[] =
   "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL",
   "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C",
   "APIC", "APIC_CLUSTER", "PCI_DOMAIN", "IRQ", "DRQ", "IO", "NUMBER",
-  "$accept", "devtree", "$@1", "chipchildren", "devicechildren", "chip",
-  "@2", "device", "@3", "resource", "registers", 0
+  "SUBSYSTEMID", "INHERIT", "$accept", "devtree", "$@1", "chipchildren",
+  "devicechildren", "chip", "@2", "device", "@3", "resource", "registers",
+  "subsystemid", 0
 };
 #endif
 
@@ -479,22 +485,24 @@ static const yytype_uint16 yytoknum[] =
 {
        0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
      265,   266,   267,   268,   269,   270,   271,   272,   273,   274,
-     275,   276,   277
+     275,   276,   277,   278,   279
 };
 # endif
 
 /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
 static const yytype_uint8 yyr1[] =
 {
-       0,    23,    25,    24,    26,    26,    26,    26,    27,    27,
-      27,    27,    29,    28,    31,    30,    32,    33
+       0,    25,    27,    26,    28,    28,    28,    28,    29,    29,
+      29,    29,    29,    31,    30,    33,    32,    34,    35,    36,
+      36
 };
 
 /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
 static const yytype_uint8 yyr2[] =
 {
        0,     2,     0,     2,     2,     2,     2,     0,     2,     2,
-       2,     0,     0,     5,     0,     7,     4,     4
+       2,     2,     0,     0,     5,     0,     7,     4,     4,     3,
+       4
 };
 
 /* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
@@ -502,35 +510,35 @@ static const yytype_uint8 yyr2[] =
    means the default is an error.  */
 static const yytype_uint8 yydefact[] =
 {
-       2,     0,     0,     1,     0,     3,    12,     7,     0,     0,
-       0,    13,     5,     4,     6,     0,     0,     0,     0,    14,
-      17,    11,     0,     0,    15,     9,     8,    10,     0,     0,
-      16
+       2,     0,     0,     1,     0,     3,    13,     7,     0,     0,
+       0,    14,     5,     4,     6,     0,     0,     0,     0,    15,
+      18,    12,     0,     0,    16,     0,     9,     8,    10,    11,
+       0,     0,     0,    19,    17,    20
 };
 
 /* YYDEFGOTO[NTERM-NUM].  */
 static const yytype_int8 yydefgoto[] =
 {
-      -1,     1,     2,     8,    22,     5,     7,    13,    21,    27,
-      14
+      -1,     1,     2,     8,    22,     5,     7,    13,    21,    28,
+      14,    29
 };
 
 /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
    STATE-NUM.  */
-#define YYPACT_NINF -10
+#define YYPACT_NINF -9
 static const yytype_int8 yypact[] =
 {
-     -10,     6,     5,   -10,    -1,   -10,   -10,   -10,    -2,     8,
-       0,   -10,   -10,   -10,   -10,    -9,     7,    10,     9,   -10,
-     -10,   -10,     1,    -4,   -10,   -10,   -10,   -10,    12,    -3,
-     -10
+      -9,     3,     1,    -9,    -2,    -9,    -9,    -9,     4,     5,
+      -1,    -9,    -9,    -9,    -9,    -8,     7,     9,     6,    -9,
+      -9,    -9,    -3,     0,    -9,     2,    -9,    -9,    -9,    -9,
+      11,     8,    10,    -5,    -9,    -9
 };
 
 /* YYPGOTO[NTERM-NUM].  */
 static const yytype_int8 yypgoto[] =
 {
-     -10,   -10,   -10,   -10,   -10,    -8,   -10,     2,   -10,   -10,
-     -10
+      -9,    -9,    -9,    -9,    -9,    -6,    -9,    12,    -9,    -9,
+      -9,    -9
 };
 
 /* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
@@ -540,26 +548,28 @@ static const yytype_int8 yypgoto[] =
 #define YYTABLE_NINF -1
 static const yytype_uint8 yytable[] =
 {
-      12,     4,     9,    10,     4,     9,     3,    11,     4,    23,
-      24,     6,    16,    17,    25,    15,    19,    18,    28,    30,
-       0,    20,    29,     0,    26
+       4,     9,    12,     3,     4,    23,    24,     4,     9,    10,
+       6,    16,    15,    11,    17,    19,    26,    18,    20,    35,
+      25,    32,    30,     0,    31,     0,     0,     0,     0,     0,
+      33,     0,    34,     0,    27
 };
 
 static const yytype_int8 yycheck[] =
 {
-       8,     3,     4,     5,     3,     4,     0,     9,     3,     8,
-       9,    12,    12,    22,    22,     7,     6,    10,    22,    22,
-      -1,    12,    10,    -1,    22
+       3,     4,     8,     0,     3,     8,     9,     3,     4,     5,
+      12,    12,     7,     9,    22,     6,    22,    10,    12,    24,
+      23,    10,    22,    -1,    22,    -1,    -1,    -1,    -1,    -1,
+      22,    -1,    22,    -1,    22
 };
 
 /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
    symbol of state STATE-NUM.  */
 static const yytype_uint8 yystos[] =
 {
-       0,    24,    25,     0,     3,    28,    12,    29,    26,     4,
-       5,     9,    28,    30,    33,     7,    12,    22,    10,     6,
-      12,    31,    27,     8,     9,    28,    30,    32,    22,    10,
-      22
+       0,    26,    27,     0,     3,    30,    12,    31,    28,     4,
+       5,     9,    30,    32,    35,     7,    12,    22,    10,     6,
+      12,    33,    29,     8,     9,    23,    30,    32,    34,    36,
+      22,    22,    10,    22,    22,    24
 };
 
 #define yyerrok		(yyerrstatus = 0)
@@ -1380,7 +1390,7 @@ yyreduce:
     { postprocess_devtree(); ;}
     break;
 
-  case 12:
+  case 13:
 
     {
 	(yyval.device) = new_chip(cur_parent, cur_bus, (yyvsp[(2) - (2)].string));
@@ -1388,7 +1398,7 @@ yyreduce:
 ;}
     break;
 
-  case 13:
+  case 14:
 
     {
 	cur_parent = (yyvsp[(3) - (5)].device)->parent;
@@ -1397,7 +1407,7 @@ yyreduce:
 ;}
     break;
 
-  case 14:
+  case 15:
 
     {
 	(yyval.device) = new_device(cur_parent, cur_bus, (yyvsp[(2) - (4)].number), (yyvsp[(3) - (4)].string), (yyvsp[(4) - (4)].number));
@@ -1406,7 +1416,7 @@ yyreduce:
 ;}
     break;
 
-  case 15:
+  case 16:
 
     {
 	cur_parent = (yyvsp[(5) - (7)].device)->parent;
@@ -1416,16 +1426,26 @@ yyreduce:
 ;}
     break;
 
-  case 16:
+  case 17:
 
     { add_resource(cur_parent, (yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); ;}
     break;
 
-  case 17:
+  case 18:
 
     { add_register(cur_parent, (yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); ;}
     break;
 
+  case 19:
+
+    { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (3)].string), NULL, 16), strtol((yyvsp[(3) - (3)].string), NULL, 16), 0); ;}
+    break;
+
+  case 20:
+
+    { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), strtol((yyvsp[(3) - (4)].string), NULL, 16), 1); ;}
+    break;
+
 
 
       default: break;
diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped
index 8c6b5f6..fc101c2 100644
--- a/util/sconfig/sconfig.tab.h_shipped
+++ b/util/sconfig/sconfig.tab.h_shipped
@@ -58,7 +58,9 @@
      IRQ = 274,
      DRQ = 275,
      IO = 276,
-     NUMBER = 277
+     NUMBER = 277,
+     SUBSYSTEMID = 278,
+     INHERIT = 279
    };
 #endif
 
diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y
index 1c5db2a..f97850f 100755
--- a/util/sconfig/sconfig.y
+++ b/util/sconfig/sconfig.y
@@ -29,13 +29,14 @@ static struct device *cur_parent, *cur_bus;
 	char *string;
 	int number;
 }
-%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER
+
+%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT
 %%
 devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ;
 
 chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ;
 
-devicechildren: devicechildren device | devicechildren chip | devicechildren resource | /* empty */ ;
+devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | /* empty */ ;
 
 chip: CHIP STRING /* == path */ {
 	$<device>$ = new_chip(cur_parent, cur_bus, $<string>2);
@@ -65,4 +66,11 @@ resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */
 registers: REGISTER STRING /* == regname */ EQUALS STRING /* == regval */
 	{ add_register(cur_parent, $<string>2, $<string>4); } ;
 
+subsystemid: SUBSYSTEMID NUMBER NUMBER
+	{ add_pci_subsystem_ids(cur_parent, strtol($<string>2, NULL, 16), strtol($<string>3, NULL, 16), 0); };
+
+subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT
+	{ add_pci_subsystem_ids(cur_parent, strtol($<string>2, NULL, 16), strtol($<string>3, NULL, 16), 1); };
+
+
 %%
-- 
1.7.4.1




From svens at stackframe.org  Tue Mar  1 17:28:30 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue,  1 Mar 2011 17:28:30 +0100
Subject: [coreboot] [PATCH 2/2] Use subsystem id from devicetree.cb instead
	of Kconfig and move all boards to the new config scheme.
In-Reply-To: <1298996910-9031-1-git-send-email-svens@stackframe.org>
References: <1298996910-9031-1-git-send-email-svens@stackframe.org>
Message-ID: <1298996910-9031-3-git-send-email-svens@stackframe.org>

---
 src/Kconfig                                        |    7 ---
 src/devices/pci_device.c                           |   21 ++------
 src/mainboard/amd/bimini_fam10/Kconfig             |    8 ---
 src/mainboard/amd/bimini_fam10/devicetree.cb       |    1 +
 src/mainboard/amd/dbm690t/Kconfig                  |    8 ---
 src/mainboard/amd/dbm690t/devicetree.cb            |    1 +
 src/mainboard/amd/inagua/Kconfig                   |    8 ---
 src/mainboard/amd/inagua/devicetree.cb             |    1 +
 src/mainboard/amd/mahogany/Kconfig                 |    8 ---
 src/mainboard/amd/mahogany/devicetree.cb           |    1 +
 src/mainboard/amd/mahogany_fam10/Kconfig           |    8 ---
 src/mainboard/amd/mahogany_fam10/devicetree.cb     |    1 +
 src/mainboard/amd/persimmon/Kconfig                |    8 ---
 src/mainboard/amd/persimmon/devicetree.cb          |    1 +
 src/mainboard/amd/pistachio/Kconfig                |    8 ---
 src/mainboard/amd/pistachio/devicetree.cb          |    1 +
 src/mainboard/amd/serengeti_cheetah/Kconfig        |    8 ---
 src/mainboard/amd/serengeti_cheetah/devicetree.cb  |    1 +
 src/mainboard/amd/serengeti_cheetah_fam10/Kconfig  |    8 ---
 .../amd/serengeti_cheetah_fam10/devicetree.cb      |    1 +
 src/mainboard/amd/tilapia_fam10/Kconfig            |    8 ---
 src/mainboard/amd/tilapia_fam10/devicetree.cb      |    1 +
 src/mainboard/arima/hdama/Kconfig                  |    8 ---
 src/mainboard/arima/hdama/devicetree.cb            |    1 +
 src/mainboard/asrock/939a785gmh/Kconfig            |    8 ---
 src/mainboard/asrock/939a785gmh/devicetree.cb      |    1 +
 src/mainboard/asrock/e350m1/Kconfig                |    8 ---
 src/mainboard/asrock/e350m1/devicetree.cb          |    1 +
 src/mainboard/asus/Kconfig                         |    4 --
 src/mainboard/asus/a8n_e/Kconfig                   |    8 ---
 src/mainboard/asus/a8n_e/devicetree.cb             |    1 +
 src/mainboard/asus/a8v-e_deluxe/Kconfig            |    4 --
 src/mainboard/asus/a8v-e_deluxe/devicetree.cb      |    1 +
 src/mainboard/asus/a8v-e_se/Kconfig                |    4 --
 src/mainboard/asus/a8v-e_se/devicetree.cb          |    1 +
 src/mainboard/asus/m2n-e/Kconfig                   |    4 --
 src/mainboard/asus/m2n-e/devicetree.cb             |    1 +
 src/mainboard/asus/m2v-mx_se/Kconfig               |    4 --
 src/mainboard/asus/m2v-mx_se/devicetree.cb         |    1 +
 src/mainboard/asus/m2v/Kconfig                     |    4 --
 src/mainboard/asus/m2v/devicetree.cb               |    1 +
 src/mainboard/asus/m4a78-em/Kconfig                |    8 ---
 src/mainboard/asus/m4a78-em/devicetree.cb          |    1 +
 src/mainboard/asus/m4a785-m/Kconfig                |    8 ---
 src/mainboard/asus/m4a785-m/devicetree.cb          |    1 +
 src/mainboard/broadcom/blast/Kconfig               |    8 ---
 src/mainboard/broadcom/blast/devicetree.cb         |    1 +
 src/mainboard/dell/s1850/Kconfig                   |    8 ---
 src/mainboard/dell/s1850/devicetree.cb             |    1 +
 src/mainboard/gigabyte/ga_2761gxdk/Kconfig         |    8 ---
 src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb   |    1 +
 src/mainboard/gigabyte/m57sli/Kconfig              |    8 ---
 src/mainboard/gigabyte/m57sli/devicetree.cb        |    1 +
 src/mainboard/gigabyte/ma785gmt/Kconfig            |    8 ---
 src/mainboard/gigabyte/ma785gmt/devicetree.cb      |    1 +
 src/mainboard/gigabyte/ma78gm/Kconfig              |    8 ---
 src/mainboard/gigabyte/ma78gm/devicetree.cb        |    1 +
 src/mainboard/hp/dl145_g1/Kconfig                  |    8 ---
 src/mainboard/hp/dl145_g1/devicetree.cb            |    1 +
 src/mainboard/iei/kino-780am2-fam10/Kconfig        |    8 ---
 src/mainboard/intel/Kconfig                        |    4 --
 src/mainboard/intel/d945gclf/Kconfig               |    4 --
 src/mainboard/intel/d945gclf/devicetree.cb         |    1 +
 src/mainboard/intel/jarrell/Kconfig                |    8 ---
 src/mainboard/intel/jarrell/devicetree.cb          |    1 +
 src/mainboard/intel/mtarvon/Kconfig                |    8 ---
 src/mainboard/intel/mtarvon/devicetree.cb          |    1 +
 src/mainboard/intel/truxton/Kconfig                |    8 ---
 src/mainboard/intel/truxton/devicetree.cb          |    1 +
 src/mainboard/intel/xe7501devkit/Kconfig           |    8 ---
 src/mainboard/intel/xe7501devkit/devicetree.cb     |    1 +
 src/mainboard/iwill/dk8_htx/Kconfig                |    8 ---
 src/mainboard/iwill/dk8_htx/devicetree.cb          |    1 +
 src/mainboard/iwill/dk8s2/Kconfig                  |    8 ---
 src/mainboard/iwill/dk8s2/devicetree.cb            |    1 +
 src/mainboard/jetway/pa78vm5/Kconfig               |    8 ---
 src/mainboard/jetway/pa78vm5/devicetree.cb         |    1 +
 src/mainboard/kontron/kt690/Kconfig                |    8 ---
 src/mainboard/kontron/kt690/devicetree.cb          |    1 +
 src/mainboard/lenovo/x60/devicetree.cb             |   50 +++++++++++++++-----
 src/mainboard/msi/Kconfig                          |    4 --
 src/mainboard/msi/ms7135/Kconfig                   |    4 --
 src/mainboard/msi/ms7135/devicetree.cb             |    1 +
 src/mainboard/msi/ms7260/Kconfig                   |    8 ---
 src/mainboard/msi/ms7260/devicetree.cb             |    1 +
 src/mainboard/msi/ms9185/Kconfig                   |    8 ---
 src/mainboard/msi/ms9185/devicetree.cb             |    1 +
 src/mainboard/msi/ms9282/Kconfig                   |    8 ---
 src/mainboard/msi/ms9282/devicetree.cb             |    1 +
 src/mainboard/msi/ms9652_fam10/Kconfig             |    8 ---
 src/mainboard/msi/ms9652_fam10/devicetree.cb       |    1 +
 src/mainboard/newisys/khepri/Kconfig               |    8 ---
 src/mainboard/newisys/khepri/devicetree.cb         |    1 +
 src/mainboard/nvidia/l1_2pvv/Kconfig               |    8 ---
 src/mainboard/nvidia/l1_2pvv/devicetree.cb         |    1 +
 src/mainboard/roda/Kconfig                         |    4 --
 src/mainboard/roda/rk886ex/Kconfig                 |    4 --
 src/mainboard/roda/rk886ex/devicetree.cb           |    1 +
 src/mainboard/sunw/ultra40/Kconfig                 |    8 ---
 src/mainboard/sunw/ultra40/devicetree.cb           |    1 +
 src/mainboard/supermicro/Kconfig                   |    4 --
 src/mainboard/supermicro/h8dme/Kconfig             |    8 ---
 src/mainboard/supermicro/h8dme/devicetree.cb       |    1 +
 src/mainboard/supermicro/h8dmr/Kconfig             |    8 ---
 src/mainboard/supermicro/h8dmr/devicetree.cb       |    1 +
 src/mainboard/supermicro/h8dmr_fam10/Kconfig       |    4 --
 src/mainboard/supermicro/h8dmr_fam10/devicetree.cb |    1 +
 src/mainboard/supermicro/h8qme_fam10/Kconfig       |    4 --
 src/mainboard/supermicro/h8qme_fam10/devicetree.cb |    1 +
 src/mainboard/supermicro/x6dai_g/Kconfig           |    8 ---
 src/mainboard/supermicro/x6dai_g/devicetree.cb     |    1 +
 src/mainboard/supermicro/x6dhe_g/Kconfig           |    8 ---
 src/mainboard/supermicro/x6dhe_g/devicetree.cb     |    1 +
 src/mainboard/supermicro/x6dhe_g2/Kconfig          |    8 ---
 src/mainboard/supermicro/x6dhe_g2/devicetree.cb    |    1 +
 src/mainboard/supermicro/x6dhr_ig/Kconfig          |    8 ---
 src/mainboard/supermicro/x6dhr_ig/devicetree.cb    |    1 +
 src/mainboard/supermicro/x6dhr_ig2/Kconfig         |    8 ---
 src/mainboard/supermicro/x6dhr_ig2/devicetree.cb   |    1 +
 src/mainboard/technexion/tim5690/Kconfig           |    8 ---
 src/mainboard/technexion/tim5690/devicetree.cb     |    1 +
 src/mainboard/technexion/tim8690/Kconfig           |    8 ---
 src/mainboard/technexion/tim8690/devicetree.cb     |    1 +
 src/mainboard/tyan/Kconfig                         |    4 --
 src/mainboard/tyan/s2735/Kconfig                   |    4 --
 src/mainboard/tyan/s2735/devicetree.cb             |    1 +
 src/mainboard/tyan/s2850/Kconfig                   |    4 --
 src/mainboard/tyan/s2850/devicetree.cb             |    1 +
 src/mainboard/tyan/s2875/Kconfig                   |    4 --
 src/mainboard/tyan/s2875/devicetree.cb             |    1 +
 src/mainboard/tyan/s2880/Kconfig                   |    4 --
 src/mainboard/tyan/s2880/devicetree.cb             |    1 +
 src/mainboard/tyan/s2881/Kconfig                   |    4 --
 src/mainboard/tyan/s2881/devicetree.cb             |    1 +
 src/mainboard/tyan/s2882/Kconfig                   |    4 --
 src/mainboard/tyan/s2882/devicetree.cb             |    1 +
 src/mainboard/tyan/s2885/Kconfig                   |    4 --
 src/mainboard/tyan/s2885/devicetree.cb             |    1 +
 src/mainboard/tyan/s2891/Kconfig                   |    4 --
 src/mainboard/tyan/s2891/devicetree.cb             |    1 +
 src/mainboard/tyan/s2892/Kconfig                   |    4 --
 src/mainboard/tyan/s2892/devicetree.cb             |    1 +
 src/mainboard/tyan/s2895/Kconfig                   |    4 --
 src/mainboard/tyan/s2895/devicetree.cb             |    1 +
 src/mainboard/tyan/s2912/Kconfig                   |    4 --
 src/mainboard/tyan/s2912/devicetree.cb             |    1 +
 src/mainboard/tyan/s2912_fam10/Kconfig             |    4 --
 src/mainboard/tyan/s2912_fam10/devicetree.cb       |    1 +
 src/mainboard/tyan/s4880/Kconfig                   |    4 --
 src/mainboard/tyan/s4880/devicetree.cb             |    1 +
 src/mainboard/tyan/s4882/Kconfig                   |    4 --
 src/mainboard/tyan/s4882/devicetree.cb             |    1 +
 src/mainboard/via/Kconfig                          |    4 --
 src/mainboard/via/pc2500e/Kconfig                  |    8 ---
 src/mainboard/via/pc2500e/devicetree.cb            |    1 +
 src/mainboard/wyse/Kconfig                         |    4 --
 src/mainboard/wyse/s50/devicetree.cb               |    1 +
 src/southbridge/intel/i82801gx/pci.c               |   10 ++--
 158 files changed, 120 insertions(+), 561 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 28915b2..05b4adb 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -137,13 +137,6 @@ config PCI_BUS_SEGN_BITS
 	int
 	default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x0
 config PCI_ROM_RUN
 	bool
 	default n
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index b6a8078..fe4c579 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -586,16 +586,6 @@ void pci_dev_set_resources(struct device *dev)
 	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 }
 
-unsigned __attribute__((weak)) mainboard_pci_subsystem_vendor_id(__attribute__((unused)) struct device *dev)
-{
-		return CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID;
-}
-
-unsigned __attribute__((weak)) mainboard_pci_subsystem_device_id(__attribute__((unused)) struct device *dev)
-{
-		return CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID;
-}
-
 void pci_dev_enable_resources(struct device *dev)
 {
 	const struct pci_operations *ops;
@@ -604,12 +594,11 @@ void pci_dev_enable_resources(struct device *dev)
 	/* Set the subsystem vendor and device ID for mainboard devices. */
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
-		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", dev_path(dev),
-		       mainboard_pci_subsystem_vendor_id(dev),
-		       mainboard_pci_subsystem_device_id(dev));
-		ops->set_subsystem(dev,
-				   mainboard_pci_subsystem_vendor_id(dev),
-				   mainboard_pci_subsystem_device_id(dev));
+		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
+			dev_path(dev), dev->subsystem_vendor,
+			dev->subsystem_device);
+		ops->set_subsystem(dev, dev->subsystem_vendor,
+			dev->subsystem_device);
 	}
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;
diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig
index d39da7b..2118078 100644
--- a/src/mainboard/amd/bimini_fam10/Kconfig
+++ b/src/mainboard/amd/bimini_fam10/Kconfig
@@ -91,14 +91,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb
index 5916c9f..a5bec74 100644
--- a/src/mainboard/amd/bimini_fam10/devicetree.cb
+++ b/src/mainboard/amd/bimini_fam10/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig
index d1e2649..3d3a04c 100644
--- a/src/mainboard/amd/dbm690t/Kconfig
+++ b/src/mainboard/amd/dbm690t/Kconfig
@@ -59,12 +59,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_AMD_DBM690T
diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb
index d13c5da..e1b01b2 100644
--- a/src/mainboard/amd/dbm690t/devicetree.cb
+++ b/src/mainboard/amd/dbm690t/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index 8a2c834..8e4eca9 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -118,14 +118,6 @@ config ACPI_SSDTX_NUM
         int
         default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-        hex
-        default 0x1510
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-        hex
-        default 0x1022
-
 config RAMBASE
         hex
         default 0x200000
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index a0a19ea..acae2ca 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -23,6 +23,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                 end
         end
         device pci_domain 0 on
+                subsystemid 0x1022 0x1510 inherit
                 chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig
index 09adfcb..731002d 100644
--- a/src/mainboard/amd/mahogany/Kconfig
+++ b/src/mainboard/amd/mahogany/Kconfig
@@ -73,12 +73,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
 endif # BOARD_AMD_MAHOGANY
diff --git a/src/mainboard/amd/mahogany/devicetree.cb b/src/mainboard/amd/mahogany/devicetree.cb
index 7965989..d60d5a1 100644
--- a/src/mainboard/amd/mahogany/devicetree.cb
+++ b/src/mainboard/amd/mahogany/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig
index 0f6c6b3..9c2e081 100644
--- a/src/mainboard/amd/mahogany_fam10/Kconfig
+++ b/src/mainboard/amd/mahogany_fam10/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb
index d1f26d1..c51e53e 100644
--- a/src/mainboard/amd/mahogany_fam10/devicetree.cb
+++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index 650e7aa..66c37f2 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -118,14 +118,6 @@ config ACPI_SSDTX_NUM
         int
         default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-        hex
-        default 0x1510
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-        hex
-        default 0x1022
-
 config RAMBASE
         hex
         default 0x200000
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index 48fd741..8ca165b 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -23,6 +23,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                 end
         end
         device pci_domain 0 on
+                subsystemid 0x1022 0x1510 inherit
                 chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig
index b9f37b3..487a599 100644
--- a/src/mainboard/amd/pistachio/Kconfig
+++ b/src/mainboard/amd/pistachio/Kconfig
@@ -71,12 +71,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_AMD_PISTACHIO
diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb
index 76f0fe7..6608fdd 100644
--- a/src/mainboard/amd/pistachio/devicetree.cb
+++ b/src/mainboard/amd/pistachio/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge, K8 HT Configuration
 				chip southbridge/amd/rs690
diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig
index 6a4aea1..f08fd6e 100644
--- a/src/mainboard/amd/serengeti_cheetah/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah/Kconfig
@@ -82,14 +82,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config ACPI_SSDTX_NUM
 	int
 	default 4
diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
index 8ea682f..b819292 100644
--- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb
+++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x2b80 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
index a49e3c9..4c9d2a0 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
@@ -84,14 +84,6 @@ config ACPI_SSDTX_NUM
 	int
 	default 5
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
index 7c36509..bfbb2b3 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x2b80 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig
index 0d85f86..b18115b 100644
--- a/src/mainboard/amd/tilapia_fam10/Kconfig
+++ b/src/mainboard/amd/tilapia_fam10/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb
index 0a26361..aeb582a 100644
--- a/src/mainboard/amd/tilapia_fam10/devicetree.cb
+++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/arima/hdama/Kconfig b/src/mainboard/arima/hdama/Kconfig
index 0019bb4..7f0e40d 100644
--- a/src/mainboard/arima/hdama/Kconfig
+++ b/src/mainboard/arima/hdama/Kconfig
@@ -21,14 +21,6 @@ config MAINBOARD_DIR
 	string
 	default arima/hdama
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x161f
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3016
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0
diff --git a/src/mainboard/arima/hdama/devicetree.cb b/src/mainboard/arima/hdama/devicetree.cb
index c908921..d7252e2 100644
--- a/src/mainboard/arima/hdama/devicetree.cb
+++ b/src/mainboard/arima/hdama/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x161f 0x3016 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig
index e3eb57a..7021655 100644
--- a/src/mainboard/asrock/939a785gmh/Kconfig
+++ b/src/mainboard/asrock/939a785gmh/Kconfig
@@ -74,12 +74,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
 endif # BOARD_ASROCK_939A785GMH
diff --git a/src/mainboard/asrock/939a785gmh/devicetree.cb b/src/mainboard/asrock/939a785gmh/devicetree.cb
index 76f61b0..1dc92a3 100644
--- a/src/mainboard/asrock/939a785gmh/devicetree.cb
+++ b/src/mainboard/asrock/939a785gmh/devicetree.cb
@@ -16,6 +16,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index 06fd4f0..9b73ea3 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -118,14 +118,6 @@ config ACPI_SSDTX_NUM
         int
         default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-        hex
-        default 0x1510
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-        hex
-        default 0x1022
-
 config RAMBASE
         hex
         default 0x200000
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 648db98..9dceae6 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -23,6 +23,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                 end
         end
         device pci_domain 0 on
+                subsystemid 0x1022 0x1510 inherit
                 chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig
index bf8742a..875fd5a 100644
--- a/src/mainboard/asus/Kconfig
+++ b/src/mainboard/asus/Kconfig
@@ -77,8 +77,4 @@ config MAINBOARD_VENDOR
 	string
 	default "ASUS"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # VENDOR_ASUS
diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig
index 6512589..aca9e33 100644
--- a/src/mainboard/asus/a8n_e/Kconfig
+++ b/src/mainboard/asus/a8n_e/Kconfig
@@ -70,12 +70,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 13
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x815a
-
 endif # BOARD_ASUS_A8N_E
diff --git a/src/mainboard/asus/a8n_e/devicetree.cb b/src/mainboard/asus/a8n_e/devicetree.cb
index 1144f0c..86bf3aa 100644
--- a/src/mainboard/asus/a8n_e/devicetree.cb
+++ b/src/mainboard/asus/a8n_e/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
   end
 
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1043 0x815a inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge
diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig
index f9ac563..05408ca 100644
--- a/src/mainboard/asus/a8v-e_deluxe/Kconfig
+++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig
@@ -70,8 +70,4 @@ config HT_CHAIN_UNITID_BASE
 	hex
 	default 0x0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # BOARD_ASUS_A8V_E_DELUXE
diff --git a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb b/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
index cd80392..31df8fa 100644
--- a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
+++ b/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 1043 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig
index abf2bd9..4975cfa 100644
--- a/src/mainboard/asus/a8v-e_se/Kconfig
+++ b/src/mainboard/asus/a8v-e_se/Kconfig
@@ -70,8 +70,4 @@ config HT_CHAIN_UNITID_BASE
 	hex
 	default 0x0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # BOARD_ASUS_A8V_E_SE
diff --git a/src/mainboard/asus/a8v-e_se/devicetree.cb b/src/mainboard/asus/a8v-e_se/devicetree.cb
index cd80392..3da93fe 100644
--- a/src/mainboard/asus/a8v-e_se/devicetree.cb
+++ b/src/mainboard/asus/a8v-e_se/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1043 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig
index 60b7e15..c23a2df 100644
--- a/src/mainboard/asus/m2n-e/Kconfig
+++ b/src/mainboard/asus/m2n-e/Kconfig
@@ -98,8 +98,4 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x8239
-
 endif # BOARD_ASUS_M2N_E
diff --git a/src/mainboard/asus/m2n-e/devicetree.cb b/src/mainboard/asus/m2n-e/devicetree.cb
index dbadf0e..bf4de25 100644
--- a/src/mainboard/asus/m2n-e/devicetree.cb
+++ b/src/mainboard/asus/m2n-e/devicetree.cb
@@ -25,6 +25,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1043 0x8239 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig
index b6a2fe6..09157ee 100644
--- a/src/mainboard/asus/m2v-mx_se/Kconfig
+++ b/src/mainboard/asus/m2v-mx_se/Kconfig
@@ -89,8 +89,4 @@ config HT_CHAIN_END_UNITID_BASE
 	hex
 	default 0x20
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # BOARD_ASUS_M2V_MX_SE
diff --git a/src/mainboard/asus/m2v-mx_se/devicetree.cb b/src/mainboard/asus/m2v-mx_se/devicetree.cb
index 93a3a87..7e4c6d1 100644
--- a/src/mainboard/asus/m2v-mx_se/devicetree.cb
+++ b/src/mainboard/asus/m2v-mx_se/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1043 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig
index 757bc32..571b940 100644
--- a/src/mainboard/asus/m2v/Kconfig
+++ b/src/mainboard/asus/m2v/Kconfig
@@ -75,10 +75,6 @@ config HT_CHAIN_UNITID_BASE
 	hex
 	default 0x0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 config IRQ_SLOT_COUNT
 	int
 	default 14
diff --git a/src/mainboard/asus/m2v/devicetree.cb b/src/mainboard/asus/m2v/devicetree.cb
index a08defb..2ace9db 100644
--- a/src/mainboard/asus/m2v/devicetree.cb
+++ b/src/mainboard/asus/m2v/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+  subsystemid 0x143 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig
index 18542d3..d036b21 100644
--- a/src/mainboard/asus/m4a78-em/Kconfig
+++ b/src/mainboard/asus/m4a78-em/Kconfig
@@ -77,14 +77,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x83f1
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/asus/m4a78-em/devicetree.cb b/src/mainboard/asus/m4a78-em/devicetree.cb
index 914fde4..c463d71 100644
--- a/src/mainboard/asus/m4a78-em/devicetree.cb
+++ b/src/mainboard/asus/m4a78-em/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1043 0x83f1 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig
index e41fcc2..84cc06c 100644
--- a/src/mainboard/asus/m4a785-m/Kconfig
+++ b/src/mainboard/asus/m4a785-m/Kconfig
@@ -78,14 +78,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x83a2
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb
index 0736b72..e8764b1 100644
--- a/src/mainboard/asus/m4a785-m/devicetree.cb
+++ b/src/mainboard/asus/m4a785-m/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1043 0x83a2 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig
index 63a2975..4bad57d 100644
--- a/src/mainboard/broadcom/blast/Kconfig
+++ b/src/mainboard/broadcom/blast/Kconfig
@@ -70,12 +70,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x161f
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_BROADCOM_BLAST
diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb
index c50ebc7..6779a7a 100644
--- a/src/mainboard/broadcom/blast/devicetree.cb
+++ b/src/mainboard/broadcom/blast/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x161f 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
                               #  devices on link 0
diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig
index 4185dfc..381c9f6 100644
--- a/src/mainboard/dell/s1850/Kconfig
+++ b/src/mainboard/dell/s1850/Kconfig
@@ -26,14 +26,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "PowerEdge 1850"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x5580
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb
index de8c90b..c56fd37 100644
--- a/src/mainboard/dell/s1850/devicetree.cb
+++ b/src/mainboard/dell/s1850/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x5580 inherit
 		chip southbridge/intel/i82801ex # i82801er
 			# USB ports
 			device pci 1d.0 on end
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
index 6571b31..d25db85 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
@@ -78,14 +78,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1039
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1234
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
index 62f9238..e1aac4e 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x1039 0x1234 inherit
 		chip northbridge/amd/amdk8 #mc0
 			device pci 18.0 on
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index e36dccc..7250a9c 100644
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -82,14 +82,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/gigabyte/m57sli/devicetree.cb b/src/mainboard/gigabyte/m57sli/devicetree.cb
index 3bae560..2184de5 100644
--- a/src/mainboard/gigabyte/m57sli/devicetree.cb
+++ b/src/mainboard/gigabyte/m57sli/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
 end
 device pci_domain 0 on				# PCI domain
+  subsystemid 0x1022 0x2b80 inherit
   chip northbridge/amd/amdk8			# Northbridge / RAM controller
     device pci 18.0 on				# Link 0 == LDT 0
       chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig
index 96b456c..fd511a8 100644
--- a/src/mainboard/gigabyte/ma785gmt/Kconfig
+++ b/src/mainboard/gigabyte/ma785gmt/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/gigabyte/ma785gmt/devicetree.cb b/src/mainboard/gigabyte/ma785gmt/devicetree.cb
index dc7bd10..6cc966a 100644
--- a/src/mainboard/gigabyte/ma785gmt/devicetree.cb
+++ b/src/mainboard/gigabyte/ma785gmt/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig
index cf3f6a2..56b819e 100644
--- a/src/mainboard/gigabyte/ma78gm/Kconfig
+++ b/src/mainboard/gigabyte/ma78gm/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb
index 59e1502..38ff642 100644
--- a/src/mainboard/gigabyte/ma78gm/devicetree.cb
+++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x3060 0x1022 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig
index bb4a33d..eb90b07 100644
--- a/src/mainboard/hp/dl145_g1/Kconfig
+++ b/src/mainboard/hp/dl145_g1/Kconfig
@@ -34,14 +34,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "ProLiant DL145 G1"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x7460
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb
index bd37862..3237723 100644
--- a/src/mainboard/hp/dl145_g1/devicetree.cb
+++ b/src/mainboard/hp/dl145_g1/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
     end
   end
   device pci_domain 0 on
+    subsystemid 0x1022 0x7460 inherit
     chip northbridge/amd/amdk8
       device pci 18.0 on end # link 0
       device pci 18.0 on end # link 1
diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig
index e662fe4..8fb1950 100644
--- a/src/mainboard/iei/kino-780am2-fam10/Kconfig
+++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x0000
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x0000
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig
index 612b1c1..ff8d63b 100644
--- a/src/mainboard/intel/Kconfig
+++ b/src/mainboard/intel/Kconfig
@@ -32,8 +32,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Intel"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
 endif # VENDOR_INTEL
diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
index 04643bb..ff8c638 100644
--- a/src/mainboard/intel/d945gclf/Kconfig
+++ b/src/mainboard/intel/d945gclf/Kconfig
@@ -49,10 +49,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "D945GCLF"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x464C
-
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xf0000000
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index c808cdc..a58d99e 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -26,6 +26,7 @@ chip northbridge/intel/i945
         end
 
         device pci_domain 0 on
+                subsystemid 0x8086 0x464c inherit
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
 		device pci 02.0 on end # vga controller
diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig
index 2ac8ea3..494086e 100644
--- a/src/mainboard/intel/jarrell/Kconfig
+++ b/src/mainboard/intel/jarrell/Kconfig
@@ -35,14 +35,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 18
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1079
-
 config DIMM_MAP_LOGICAL
 	hex
 	default 0x0124
diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb
index a187d23..fb32a08 100644
--- a/src/mainboard/intel/jarrell/devicetree.cb
+++ b/src/mainboard/intel/jarrell/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520
 	device pci_domain 0 on
+		subsystemid 0x8086 0x1079 inherit
 		device pci 00.0 on end
 		device pci 00.1 on end
 		device pci 01.0 on end
diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig
index 76dec5e..76477b0 100644
--- a/src/mainboard/intel/mtarvon/Kconfig
+++ b/src/mainboard/intel/mtarvon/Kconfig
@@ -25,14 +25,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 1
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2680
-
 config DCACHE_RAM_BASE
 	hex
 	default 0xffdf8000
diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb
index 8585b54..cd7df2d 100644
--- a/src/mainboard/intel/mtarvon/devicetree.cb
+++ b/src/mainboard/intel/mtarvon/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/i3100
         device pci_domain 0 on
+                subsystemid 0x8086 0x2680 inherit
                 device pci 00.0 on end # IMCH
                 device pci 00.1 on end # IMCH error status
                 device pci 01.0 on end # IMCH EDMA engine
diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig
index 1ba7137..5f7de08 100644
--- a/src/mainboard/intel/truxton/Kconfig
+++ b/src/mainboard/intel/truxton/Kconfig
@@ -27,14 +27,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 1
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2680
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb
index 7563f02..ced9eb9 100644
--- a/src/mainboard/intel/truxton/devicetree.cb
+++ b/src/mainboard/intel/truxton/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/i3100
         device pci_domain 0 on
+	       subsystemid 0x8086 0x2680 inherit
                 device pci 00.0 on end # IMCH
                 device pci 00.1 on end # IMCH error status
                 device pci 01.0 on end # IMCH EDMA engine
diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig
index 35a1cd1..9163423 100644
--- a/src/mainboard/intel/xe7501devkit/Kconfig
+++ b/src/mainboard/intel/xe7501devkit/Kconfig
@@ -37,12 +37,4 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2480
-
 endif # BOARD_INTEL_XE7501DEVKIT
diff --git a/src/mainboard/intel/xe7501devkit/devicetree.cb b/src/mainboard/intel/xe7501devkit/devicetree.cb
index 3275457..e8b9e82 100644
--- a/src/mainboard/intel/xe7501devkit/devicetree.cb
+++ b/src/mainboard/intel/xe7501devkit/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7501
 	device pci_domain 0 on
+		subsystemid 0x8086 0x2480 inheritx
 		device pci 0.0 on end # Chipset host controller
 		device pci 0.1 on end # Host RASUM controller
 		device pci 2.0 on # Hub interface B
diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig
index 414fa45..e58fe4e 100644
--- a/src/mainboard/iwill/dk8_htx/Kconfig
+++ b/src/mainboard/iwill/dk8_htx/Kconfig
@@ -63,14 +63,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config ACPI_SSDTX_NUM
 	int
 	default 5
diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb
index e1cb939..d0cff02 100644
--- a/src/mainboard/iwill/dk8_htx/devicetree.cb
+++ b/src/mainboard/iwill/dk8_htx/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x2b80 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end
 			device pci 18.0 on end
diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig
index d144b7d..78d0637 100644
--- a/src/mainboard/iwill/dk8s2/Kconfig
+++ b/src/mainboard/iwill/dk8s2/Kconfig
@@ -60,12 +60,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 12
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x161f
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3016
-
 endif # BOARD_IWILL_DK8S2
diff --git a/src/mainboard/iwill/dk8s2/devicetree.cb b/src/mainboard/iwill/dk8s2/devicetree.cb
index 8185b5d..5f27f87 100644
--- a/src/mainboard/iwill/dk8s2/devicetree.cb
+++ b/src/mainboard/iwill/dk8s2/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x161f 0x3016 inheritx
 		chip northbridge/amd/amdk8
 			device pci 18.0 on # LDT 0
 				chip southbridge/amd/amd8131
diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig
index 10fab73..62adb53 100644
--- a/src/mainboard/jetway/pa78vm5/Kconfig
+++ b/src/mainboard/jetway/pa78vm5/Kconfig
@@ -79,14 +79,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/jetway/pa78vm5/devicetree.cb b/src/mainboard/jetway/pa78vm5/devicetree.cb
index 73f6ac2..5ce3a6d 100644
--- a/src/mainboard/jetway/pa78vm5/devicetree.cb
+++ b/src/mainboard/jetway/pa78vm5/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end
 	device pci_domain 0 on
+	       subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig
index 891de59..91d6b67 100644
--- a/src/mainboard/kontron/kt690/Kconfig
+++ b/src/mainboard/kontron/kt690/Kconfig
@@ -28,14 +28,6 @@ config MAINBOARD_DIR
 	string
 	default kontron/kt690
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1488
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6900
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0
diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb
index d509050..e589641 100644
--- a/src/mainboard/kontron/kt690/devicetree.cb
+++ b/src/mainboard/kontron/kt690/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+	       subsystemid 0x1488 0x6900 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 40e16b3..f766e89 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -29,9 +29,16 @@ chip northbridge/intel/i945
         end
 
         device pci_domain 0 on
-                device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 02.1 on end # display controller
+		subsystemid 1337 0 inherit
+                device pci 00.0 on # Host bridge
+			subsystemid 0x17aa 0x2017
+		end
+		device pci 02.0 on # VGA controller
+			subsystemid 0x17aa 0x201a
+		end
+		device pci 02.1 on # display controller
+			subsystemid 0x17aa 0x201a
+		end
                 chip southbridge/intel/i82801gx
 			register "pirqa_routing" = "0x0b"
 			register "pirqb_routing" = "0x0b"
@@ -54,15 +61,28 @@ chip northbridge/intel/i945
 
 			register "gpe0_en" = "0x11000006"
 
-			device pci 1b.0 on end # Audio Controller
+			device pci 1b.0 on # Audio Cnotroller
+				subsystemid 0x17aa 0x2010
+			end
 			device pci 1c.0 on end # Ethernet
 			device pci 1c.1 on end # Atheros WLAN
-			device pci 1d.0 on end # USB UHCI
-			device pci 1d.1 on end # USB UHCI
-			device pci 1d.2 on end # USB UHCI
-			device pci 1d.3 on end # USB UHCI
-			device pci 1d.7 on end # USB2 EHCI
+			device pci 1d.0 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.1 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.2 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.3 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.7 on # USB2 EHCI
+				subsystemid 0x17aa 0x200b
+			end
 			device pci 1f.0 on # PCI-LPC bridge
+				subsystemid 0x17aa 0x2009
 				chip ec/lenovo/pmh7
 					device pnp ff.1 on # dummy
 					end
@@ -120,9 +140,15 @@ chip northbridge/intel/i945
 					end
 				end
 			end
-			device pci 1f.1 off end # IDE
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
+			device pci 1f.1 off # IDE
+				subsystemid 0x17aa 0x200c
+			end
+                        device pci 1f.2 on # SATA
+				subsystemid 0x17aa 0x200d
+			end
+                        device pci 1f.3 on # SMBUS
+				subsystemid 0x17aa 0x200f
+			end
 		end
 		chip southbridge/ricoh/rl5c476
 		end
diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig
index c2f1595..3d0de4a 100644
--- a/src/mainboard/msi/Kconfig
+++ b/src/mainboard/msi/Kconfig
@@ -56,8 +56,4 @@ config MAINBOARD_VENDOR
 	string
 	default "MSI"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
 endif # VENDOR_MSI
diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig
index d8581f7..0611be2 100644
--- a/src/mainboard/msi/ms7135/Kconfig
+++ b/src/mainboard/msi/ms7135/Kconfig
@@ -34,10 +34,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "MS-7135"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x7135
-
 config MAX_CPUS
 	int
 	default 2
diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb
index 14c6bad..54e5d5e 100644
--- a/src/mainboard/msi/ms7135/devicetree.cb
+++ b/src/mainboard/msi/ms7135/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
   end
 
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x7135 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge
diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig
index aec6af5..be425ec 100644
--- a/src/mainboard/msi/ms7260/Kconfig
+++ b/src/mainboard/msi/ms7260/Kconfig
@@ -80,14 +80,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x7260
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/msi/ms7260/devicetree.cb b/src/mainboard/msi/ms7260/devicetree.cb
index 552224d..47d5381 100644
--- a/src/mainboard/msi/ms7260/devicetree.cb
+++ b/src/mainboard/msi/ms7260/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x7260 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig
index 5e28353..1464acd 100644
--- a/src/mainboard/msi/ms9185/Kconfig
+++ b/src/mainboard/msi/ms9185/Kconfig
@@ -71,12 +71,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 endif # BOARD_MSI_MS9185
diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb
index fc566e2..4051c10 100644
--- a/src/mainboard/msi/ms9185/devicetree.cb
+++ b/src/mainboard/msi/ms9185/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
        device pci_domain 0 on
+       	      subsystemid 0x1022 0x2b80 inherit
                chip northbridge/amd/amdk8
                        device pci 18.0 on end
                        device pci 18.0 on end
diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig
index f2ea65a..3ccc3f9 100644
--- a/src/mainboard/msi/ms9282/Kconfig
+++ b/src/mainboard/msi/ms9282/Kconfig
@@ -72,14 +72,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x9282
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb
index 74ea183..b52e7ed 100644
--- a/src/mainboard/msi/ms9282/devicetree.cb
+++ b/src/mainboard/msi/ms9282/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x9282 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
index d8025d7..948d320 100644
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -87,14 +87,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "MS-9652"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x9652
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb
index c3e4e4f..0e9a3ff 100644
--- a/src/mainboard/msi/ms9652_fam10/devicetree.cb
+++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb
@@ -28,6 +28,7 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x9652 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on			# Link 0
         chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig
index d11d6ea..fc4c223 100644
--- a/src/mainboard/newisys/khepri/Kconfig
+++ b/src/mainboard/newisys/khepri/Kconfig
@@ -69,12 +69,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 9
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x17c2
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x10
-
 endif # BOARD_NEWISYS_KHEPRI
diff --git a/src/mainboard/newisys/khepri/devicetree.cb b/src/mainboard/newisys/khepri/devicetree.cb
index a56a010..97d506a 100644
--- a/src/mainboard/newisys/khepri/devicetree.cb
+++ b/src/mainboard/newisys/khepri/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdk8/root_complex
 	end
 
 	device pci_domain 0 on
+	       subsystemid 0x17c2 0x0010 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end # LDT 0
 			device pci 18.0 on     # LDT 1
diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index 80f5e34..bfec323 100644
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -84,14 +84,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/nvidia/l1_2pvv/devicetree.cb b/src/mainboard/nvidia/l1_2pvv/devicetree.cb
index 1340cb3..9a80710 100644
--- a/src/mainboard/nvidia/l1_2pvv/devicetree.cb
+++ b/src/mainboard/nvidia/l1_2pvv/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1022 0x2b80 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge
diff --git a/src/mainboard/roda/Kconfig b/src/mainboard/roda/Kconfig
index d2f1e95..ba4b6ec 100644
--- a/src/mainboard/roda/Kconfig
+++ b/src/mainboard/roda/Kconfig
@@ -14,8 +14,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Roda"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x4352
-
 endif # VENDOR_RODA
diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index 647511a..340ee98 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -46,10 +46,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6886
-
 config MAXIMUM_SUPPORTED_FREQUENCY
 	int
 	default 400
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index a713331..7439462 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -28,6 +28,7 @@ chip northbridge/intel/i945
         end
 
         device pci_domain 0 on
+	       subsystemid 0x4352 0x0686 inherit
                 device pci 00.0 on end # host bridge
 		# auto detection:
 		#device pci 01.0 off end # i945 PCIe root port
diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig
index 3b8544b..81a6608 100644
--- a/src/mainboard/sunw/ultra40/Kconfig
+++ b/src/mainboard/sunw/ultra40/Kconfig
@@ -75,12 +75,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x108e
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x40
-
 endif # BOARD_SUNW_ULTRA40
diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb
index 059724e..829a7d4 100644
--- a/src/mainboard/sunw/ultra40/devicetree.cb
+++ b/src/mainboard/sunw/ultra40/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+   subsystemid 0x108e 0x40 inheritx
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on			# Link 0 == LDT 0
diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig
index 5ac7dda..8e5694c 100644
--- a/src/mainboard/supermicro/Kconfig
+++ b/src/mainboard/supermicro/Kconfig
@@ -38,8 +38,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Supermicro"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
 endif # VENDOR_SUPERMICRO
diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig
index 0259b4a..ce49a47 100644
--- a/src/mainboard/supermicro/h8dme/Kconfig
+++ b/src/mainboard/supermicro/h8dme/Kconfig
@@ -81,12 +81,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 endif # BOARD_SUPERMICRO_H8DME
diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb
index df40dc3..73a43e8 100644
--- a/src/mainboard/supermicro/h8dme/devicetree.cb
+++ b/src/mainboard/supermicro/h8dme/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig
index 81517be..5527319 100644
--- a/src/mainboard/supermicro/h8dmr/Kconfig
+++ b/src/mainboard/supermicro/h8dmr/Kconfig
@@ -80,12 +80,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 endif # BOARD_SUPERMICRO_H8DMR
diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb
index 1dfd32a..6c96ac0 100644
--- a/src/mainboard/supermicro/h8dmr/devicetree.cb
+++ b/src/mainboard/supermicro/h8dmr/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig
index 4b31bf3..195bc5c 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig
@@ -100,8 +100,4 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 endif # BOARD_SUPERMICRO_H8DMR_FAM10
diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
index da82b17..6c4443f 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig
index bd0f550..1d4f8e7 100644
--- a/src/mainboard/supermicro/h8qme_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig
@@ -99,10 +99,6 @@ config SERIAL_CPU_INIT
 	bool
 	default y
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 config STACK_SIZE
 	hex
 	default 0x10000
diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
index 990afa4..56ba7b5 100644
--- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/supermicro/x6dai_g/Kconfig b/src/mainboard/supermicro/x6dai_g/Kconfig
index 8b1cf5a..bac1008 100644
--- a/src/mainboard/supermicro/x6dai_g/Kconfig
+++ b/src/mainboard/supermicro/x6dai_g/Kconfig
@@ -23,14 +23,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "X6DAi-G"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6780
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/supermicro/x6dai_g/devicetree.cb b/src/mainboard/supermicro/x6dai_g/devicetree.cb
index c8ce779..e6201a8 100644
--- a/src/mainboard/supermicro/x6dai_g/devicetree.cb
+++ b/src/mainboard/supermicro/x6dai_g/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7525 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x6780 inherit
 		chip southbridge/intel/esb6300  # esb6300
 			register "pirq_a_d" = "0x0b0a0a05"
 			register "pirq_e_h" = "0x0a0b0c80"
diff --git a/src/mainboard/supermicro/x6dhe_g/Kconfig b/src/mainboard/supermicro/x6dhe_g/Kconfig
index 8771d9e..e8466be 100644
--- a/src/mainboard/supermicro/x6dhe_g/Kconfig
+++ b/src/mainboard/supermicro/x6dhe_g/Kconfig
@@ -25,14 +25,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "X6DHE-G"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6080
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/supermicro/x6dhe_g/devicetree.cb b/src/mainboard/supermicro/x6dhe_g/devicetree.cb
index 6dd6b17..08c0751 100644
--- a/src/mainboard/supermicro/x6dhe_g/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhe_g/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/intel/e7520  # MCH
 		device pnp 00.3 off end
 	end
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x6080 inherit
 		chip southbridge/intel/esb6300	# ESB6300
 			register "pirq_a_d" = "0x0b070a05"
 			register "pirq_e_h" = "0x0a808080"
diff --git a/src/mainboard/supermicro/x6dhe_g2/Kconfig b/src/mainboard/supermicro/x6dhe_g2/Kconfig
index 96549d6..e9d4041 100644
--- a/src/mainboard/supermicro/x6dhe_g2/Kconfig
+++ b/src/mainboard/supermicro/x6dhe_g2/Kconfig
@@ -26,14 +26,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "X6DHE-G2"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6080
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
index 04110b0..ecfe0a0 100644
--- a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/intel/e7520  # MCH
 		device pnp 00.3 off end
 	end
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x6080 inherit
 		chip southbridge/intel/i82801ex	# ICH5R
 			register "pirq_a_d" = "0x0b070a05"
 			register "pirq_e_h" = "0x0a808080"
diff --git a/src/mainboard/supermicro/x6dhr_ig/Kconfig b/src/mainboard/supermicro/x6dhr_ig/Kconfig
index d1163d7..a146e77 100644
--- a/src/mainboard/supermicro/x6dhr_ig/Kconfig
+++ b/src/mainboard/supermicro/x6dhr_ig/Kconfig
@@ -25,14 +25,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "X6DHR-iG"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x5580
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
index df778ed..6ada3b1 100644
--- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x5580 inherit
 		chip southbridge/intel/i82801ex # i82801er
 			# USB ports
 			device pci 1d.0 on end
diff --git a/src/mainboard/supermicro/x6dhr_ig2/Kconfig b/src/mainboard/supermicro/x6dhr_ig2/Kconfig
index 494b0ed..6196e2a 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/Kconfig
+++ b/src/mainboard/supermicro/x6dhr_ig2/Kconfig
@@ -25,14 +25,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "X6DHR-iG2"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x5580
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
index 77c9e9d..3d9b644 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x5580 inherit
 		chip southbridge/intel/i82801ex # i82801er
 			# USB ports
 			device pci 1d.0 on end
diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig
index d855df1..21cfa7b 100644
--- a/src/mainboard/technexion/tim5690/Kconfig
+++ b/src/mainboard/technexion/tim5690/Kconfig
@@ -60,14 +60,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 config STACK_SIZE
 	hex
 	default 0x2000
diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb
index c129a2d..970d0e2 100644
--- a/src/mainboard/technexion/tim5690/devicetree.cb
+++ b/src/mainboard/technexion/tim5690/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+	       subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig
index b9f34ad..5af6ace 100644
--- a/src/mainboard/technexion/tim8690/Kconfig
+++ b/src/mainboard/technexion/tim8690/Kconfig
@@ -59,12 +59,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_TECHNEXION_TIM8690
diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb
index 55a2e05..6981dbc 100644
--- a/src/mainboard/technexion/tim8690/devicetree.cb
+++ b/src/mainboard/technexion/tim8690/devicetree.cb
@@ -15,6 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
+	       subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
diff --git a/src/mainboard/tyan/Kconfig b/src/mainboard/tyan/Kconfig
index 6af48a2..01e4f35 100644
--- a/src/mainboard/tyan/Kconfig
+++ b/src/mainboard/tyan/Kconfig
@@ -74,8 +74,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Tyan"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x10f1
-
 endif # VENDOR_TYAN
diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig
index e1f475b..4aafa3c 100644
--- a/src/mainboard/tyan/s2735/Kconfig
+++ b/src/mainboard/tyan/s2735/Kconfig
@@ -45,8 +45,4 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2735
-
 endif # BOARD_TYAN_S2735
diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb
index b519a4a..542a013 100644
--- a/src/mainboard/tyan/s2735/devicetree.cb
+++ b/src/mainboard/tyan/s2735/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7501
         device pci_domain 0 on
+	       subsystemid 0x10f1 0x2735 inherit
 		device pci 0.0 on end
         	device pci 0.1 on end
         	device pci 2.0 on
diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig
index ab5897a..c555951 100644
--- a/src/mainboard/tyan/s2850/Kconfig
+++ b/src/mainboard/tyan/s2850/Kconfig
@@ -23,10 +23,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2850"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2850
-
 config MAX_CPUS
 	int
 	default 2
diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb
index 6a9a420..0ec3d6e 100644
--- a/src/mainboard/tyan/s2850/devicetree.cb
+++ b/src/mainboard/tyan/s2850/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x2850 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on # LDT0
 				#  devices on link 2, link 2 == LDT 2
diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig
index 89a1177..56c3723 100644
--- a/src/mainboard/tyan/s2875/Kconfig
+++ b/src/mainboard/tyan/s2875/Kconfig
@@ -25,10 +25,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2875"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2875
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb
index d3c2582..c9f0dd2 100644
--- a/src/mainboard/tyan/s2875/devicetree.cb
+++ b/src/mainboard/tyan/s2875/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x2875 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig
index a98ec06..87ec6ca 100644
--- a/src/mainboard/tyan/s2880/Kconfig
+++ b/src/mainboard/tyan/s2880/Kconfig
@@ -33,10 +33,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2880"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2880
-
 config MAX_CPUS
 	int
 	default 2
diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb
index ba43b27..735b4e6 100644
--- a/src/mainboard/tyan/s2880/devicetree.cb
+++ b/src/mainboard/tyan/s2880/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x2880 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig
index 81a349d..fd5fca8 100644
--- a/src/mainboard/tyan/s2881/Kconfig
+++ b/src/mainboard/tyan/s2881/Kconfig
@@ -35,10 +35,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2881"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2881
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2881/devicetree.cb b/src/mainboard/tyan/s2881/devicetree.cb
index 2422459..7e836ff 100644
--- a/src/mainboard/tyan/s2881/devicetree.cb
+++ b/src/mainboard/tyan/s2881/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
     end
   end
   device pci_domain 0 on
+    subsystemid 0x10f1 0x2881 inherit
     chip northbridge/amd/amdk8
       device pci 18.0 on end # link 0
       device pci 18.0 on end # link 1
diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig
index 00e813a..c6711b3 100644
--- a/src/mainboard/tyan/s2882/Kconfig
+++ b/src/mainboard/tyan/s2882/Kconfig
@@ -34,10 +34,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2882"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2882
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb
index b8f2160..bbc4a59 100644
--- a/src/mainboard/tyan/s2882/devicetree.cb
+++ b/src/mainboard/tyan/s2882/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdk8/root_complex
         end
 
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x2882 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0
diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig
index 03a5952..f4a6f49 100644
--- a/src/mainboard/tyan/s2885/Kconfig
+++ b/src/mainboard/tyan/s2885/Kconfig
@@ -35,10 +35,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2885"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2885
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb
index 0eb1b9e..7e45a8c 100644
--- a/src/mainboard/tyan/s2885/devicetree.cb
+++ b/src/mainboard/tyan/s2885/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x2885 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on # LDT0
 				chip southbridge/amd/amd8151
diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig
index 31e99b6..2848380 100644
--- a/src/mainboard/tyan/s2891/Kconfig
+++ b/src/mainboard/tyan/s2891/Kconfig
@@ -36,10 +36,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2891"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2891
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2891/devicetree.cb b/src/mainboard/tyan/s2891/devicetree.cb
index 73034b1..d793640 100644
--- a/src/mainboard/tyan/s2891/devicetree.cb
+++ b/src/mainboard/tyan/s2891/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2891 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge
diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig
index df3430b..88703f3 100644
--- a/src/mainboard/tyan/s2892/Kconfig
+++ b/src/mainboard/tyan/s2892/Kconfig
@@ -35,10 +35,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2892"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2892
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2892/devicetree.cb b/src/mainboard/tyan/s2892/devicetree.cb
index b84c041..3b999ca 100644
--- a/src/mainboard/tyan/s2892/devicetree.cb
+++ b/src/mainboard/tyan/s2892/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2892 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge
diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig
index 0f8482b..f35ea82 100644
--- a/src/mainboard/tyan/s2895/Kconfig
+++ b/src/mainboard/tyan/s2895/Kconfig
@@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "S2895"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2895
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/tyan/s2895/devicetree.cb b/src/mainboard/tyan/s2895/devicetree.cb
index 7841a0e..7d7abc3 100644
--- a/src/mainboard/tyan/s2895/devicetree.cb
+++ b/src/mainboard/tyan/s2895/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2895 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge
diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig
index 466cb4a..811e9a7 100644
--- a/src/mainboard/tyan/s2912/Kconfig
+++ b/src/mainboard/tyan/s2912/Kconfig
@@ -79,10 +79,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2912
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/tyan/s2912/devicetree.cb b/src/mainboard/tyan/s2912/devicetree.cb
index 11c6a73..0ce4a48 100644
--- a/src/mainboard/tyan/s2912/devicetree.cb
+++ b/src/mainboard/tyan/s2912/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2912 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index 58cdb9c..d7d5114 100644
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -80,10 +80,6 @@ config SERIAL_CPU_INIT
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2912
-
 config IRQ_SLOT_COUNT
 	int
 	default 11
diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb
index 8373ffc..43bdeb6 100644
--- a/src/mainboard/tyan/s2912_fam10/devicetree.cb
+++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2912 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end
diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig
index 5147b97..0b425b9 100644
--- a/src/mainboard/tyan/s4880/Kconfig
+++ b/src/mainboard/tyan/s4880/Kconfig
@@ -65,8 +65,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 22
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x4880
-
 endif # BOARD_TYAN_S4880
diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb
index cb34235..4f21cf3 100644
--- a/src/mainboard/tyan/s4880/devicetree.cb
+++ b/src/mainboard/tyan/s4880/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/amd/amdk8/root_complex
         end
 
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x4880 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end # LDT0
 			device pci 18.0 on end # LDT1
diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig
index b0d8897..3aa1690 100644
--- a/src/mainboard/tyan/s4882/Kconfig
+++ b/src/mainboard/tyan/s4882/Kconfig
@@ -65,8 +65,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 22
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x4882
-
 endif # BOARD_TYAN_S4882
diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb
index d4a7017..9476c8f 100644
--- a/src/mainboard/tyan/s4882/devicetree.cb
+++ b/src/mainboard/tyan/s4882/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/amd/amdk8/root_complex
                 end
         end
 	device pci_domain 0 on
+	       subsystemid 0x10f1 0x4882 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end # LDT0
 			device pci 18.0 on #  northbridge
diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig
index f272247..6980548 100644
--- a/src/mainboard/via/Kconfig
+++ b/src/mainboard/via/Kconfig
@@ -32,8 +32,4 @@ config MAINBOARD_VENDOR
 	string
 	default "VIA"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1019
-
 endif # VENDOR_VIA
diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig
index 3244ea9..70aa8d7 100644
--- a/src/mainboard/via/pc2500e/Kconfig
+++ b/src/mainboard/via/pc2500e/Kconfig
@@ -26,14 +26,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 10
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1019
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0xaa51
-
 config VGA_BIOS_FILE
 	string
 	default "M14CRT.ROM"
diff --git a/src/mainboard/via/pc2500e/devicetree.cb b/src/mainboard/via/pc2500e/devicetree.cb
index a891ef1..05ce877 100644
--- a/src/mainboard/via/pc2500e/devicetree.cb
+++ b/src/mainboard/via/pc2500e/devicetree.cb
@@ -1,5 +1,6 @@
 chip northbridge/via/cn700			# Northbridge
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1019 0xaa51 inherit
     device pci 0.0 on end			# AGP Bridge
     device pci 0.1 on end			# Error Reporting
     device pci 0.2 on end			# Host Bus Control
diff --git a/src/mainboard/wyse/Kconfig b/src/mainboard/wyse/Kconfig
index 2607d6c..e4a89d9 100644
--- a/src/mainboard/wyse/Kconfig
+++ b/src/mainboard/wyse/Kconfig
@@ -32,8 +32,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Wyse"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x102d
-
 endif # VENDOR_WYSE
diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb
index b88bc46..504a5de 100644
--- a/src/mainboard/wyse/s50/devicetree.cb
+++ b/src/mainboard/wyse/s50/devicetree.cb
@@ -28,6 +28,7 @@ chip northbridge/amd/gx2
 		end
 	end
   	device pci_domain 0 on 
+		subsystemid 102d 0 inherit
     		device pci 1.0 on end
 		device pci 1.1 on end
       		chip southbridge/amd/cs5536
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index a8e8988..cfb23e6 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -72,12 +72,10 @@ static void ich_pci_dev_enable_resources(struct device *dev)
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
 		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
-			dev_path(dev),
-			mainboard_pci_subsystem_vendor_id(dev),
-			mainboard_pci_subsystem_device_id(dev));
-		ops->set_subsystem(dev,
-			mainboard_pci_subsystem_vendor_id(dev),
-			mainboard_pci_subsystem_device_id(dev));
+		       dev_path(dev), dev->subsystem_vendor,
+		       dev->subsystem_device);
+		ops->set_subsystem(dev, dev->subsystem_vendor,
+				   dev->subsystem_device);
 	}
 
 	command = pci_read_config16(dev, PCI_COMMAND);
-- 
1.7.4.1




From buurin at gmail.com  Tue Mar  1 17:30:46 2011
From: buurin at gmail.com (Keith Hui)
Date: Tue, 1 Mar 2011 11:30:46 -0500
Subject: [coreboot] how to deal with large romstage size?
In-Reply-To: <AANLkTi=apQevBJ1zU-600RPtVogY_m38ZP8B+UedPooH@mail.gmail.com>
References: <AANLkTi=apQevBJ1zU-600RPtVogY_m38ZP8B+UedPooH@mail.gmail.com>
Message-ID: <AANLkTikfNYEKmuR3K15BidV+9mmsJzz-47aAm1f6QiHZ@mail.gmail.com>

> Hi all,
>
> After I add some memory initialisize code, the romstage is over 64K byte,and tne code can't run properly.
> Then what should I do when romstage is over 64K byte? Is romstage's size limits to 64KB?
>
> Thanks a lot!
> 2011-03-01
>

It is not a direct limitation on romstage's size, but a result of most
chipsets mapping only the top 64KB of flash to the memory space. Most
chipsets require some programming to have the entire flash rom appear
in memory. Your code didn't run properly because not all of it has
been mapped to memory space and get effectively cut.

But my romstage for Intel 440BX is only about 11KB. What chipset are
you dealing with?

Also, look at implementing TINY_BOOTBLOCK which leaves a tiny stub,
well within the 64KB limit, which does nothing but enable enough
hardware (southbridge to be exact) to make the entire rom visible,
then locates and executes the real romstage which is now just another
stage in CBFS. Again, all 440BX/PIIX4 boards implement this and can be
a reference.

Hope this help.
Keith



From peter at stuge.se  Tue Mar  1 18:20:02 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 1 Mar 2011 18:20:02 +0100
Subject: [coreboot] how to deal with large romstage size?
In-Reply-To: <AANLkTikfNYEKmuR3K15BidV+9mmsJzz-47aAm1f6QiHZ@mail.gmail.com>
References: <AANLkTi=apQevBJ1zU-600RPtVogY_m38ZP8B+UedPooH@mail.gmail.com>
	<AANLkTikfNYEKmuR3K15BidV+9mmsJzz-47aAm1f6QiHZ@mail.gmail.com>
Message-ID: <20110301172002.13895.qmail@stuge.se>

Keith Hui wrote:
> Also, look at implementing TINY_BOOTBLOCK which leaves a tiny stub,
> well within the 64KB limit, which does nothing but enable enough
> hardware (southbridge to be exact) to make the entire rom visible,
> then locates and executes the real romstage which is now just another
> stage in CBFS.

Yes, this method should always be used when implementing support for
new components in coreboot.


//Peter



From svn at coreboot.org  Tue Mar  1 20:21:55 2011
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Mar 2011 19:21:55 -0000
Subject: [coreboot] #176: Life Insurance - How To Buy Life Insurance Policies
Message-ID: <045.ef8f7ea4df59624bd0fd392d3e0942e1@coreboot.org>

#176: Life Insurance - How To Buy Life Insurance Policies
-------------------------------------+-------------------------------------
    Reporter:  anonymous             |         Owner:
        Type:  enhancement           |  c-d.hailfinger.devel.2006@?
    Priority:  major                 |        Status:  new
   Component:  flashrom (please use  |     Milestone:  flashrom v1.1
  trac on flashrom.org)              |      Keywords:  life insurance
Dependencies:                        |  Patch Status:  patch needs review
-------------------------------------+-------------------------------------
 [[Image(http://www.johnkatsouris.co.uk/images/family_park.jpg)]]

 Buying such services like '''[http://www.lifeinsurance.net.au/ life
 insurance]''' in making things better for those people to have its best
 ways that will be better for them during this days. It can make things
 better for those people to have its best ways to satisfy their needs in
 life living in this world. This '''insurances''' people can have the
 things they need in life living in this world. Having such services that
 will make things better for them having the best services that will make
 them have a '''Life Insurance''' in making things better for them during
 this days.

 [[Image(http://www.townofajax.com/AssetFactory.aspx?did=3403)]]

 It can make things better for those people having such
 '''[http://www.lifeinsurance.net.au/ life insurance]''' in a certain
 period of time. It is best for those people to have such ways that can be
 better for those people on having the things that will make them have such
 '''Living Insurance''' in a certain period of time that will make those
 people have its best ways in living.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/176>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Tue Mar  1 20:23:33 2011
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Mar 2011 19:23:33 -0000
Subject: [coreboot] #177: Life Insurance - How To Buy Life Insurance Policies
Message-ID: <045.3916e58f8f26dff0bd7f3a0ab26555b8@coreboot.org>

#177: Life Insurance - How To Buy Life Insurance Policies
-------------------------------------+-------------------------------------
    Reporter:  anonymous             |         Owner:
        Type:  enhancement           |  c-d.hailfinger.devel.2006@?
    Priority:  major                 |        Status:  new
   Component:  flashrom (please use  |     Milestone:  flashrom v1.1
  trac on flashrom.org)              |      Keywords:  life insurance
Dependencies:                        |  Patch Status:  patch needs review
-------------------------------------+-------------------------------------
 [[Image(http://www.johnkatsouris.co.uk/images/family_park.jpg)]]

 Buying such services like '''[http://www.lifeinsurance.net.au/ life
 insurance]''' in making things better for those people to have its best
 ways that will be better for them during this days. It can make things
 better for those people to have its best ways to satisfy their needs in
 life living in this world. This '''insurances''' people can have the
 things they need in life living in this world. Having such services that
 will make things better for them having the best services that will make
 them have a '''Life Insurance''' in making things better for them during
 this days.

 [[Image(http://image26.webshots.com/26/5/78/34/368457834uKnpBR_fs.jpg)]]

 It can make things better for those people having such
 '''[http://www.lifeinsurance.net.au/ life insurance]''' in a certain
 period of time. It is best for those people to have such ways that can be
 better for those people on having the things that will make them have such
 '''Living Insurance''' in a certain period of time that will make those
 people have its best ways in living.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/177>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Tue Mar  1 20:24:35 2011
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Mar 2011 19:24:35 -0000
Subject: [coreboot] #178: Life Insurance - How To Buy Life Insurance Policies
Message-ID: <045.bc210f8e81ae23679af903f14ee706f6@coreboot.org>

#178: Life Insurance - How To Buy Life Insurance Policies
-------------------------------------+-------------------------------------
    Reporter:  anonymous             |         Owner:
        Type:  enhancement           |  c-d.hailfinger.devel.2006@?
    Priority:  major                 |        Status:  new
   Component:  flashrom (please use  |     Milestone:  flashrom v1.1
  trac on flashrom.org)              |      Keywords:  life insurance
Dependencies:                        |  Patch Status:  patch needs review
-------------------------------------+-------------------------------------
 [[Image(http://www.johnkatsouris.co.uk/images/family_park.jpg)]]

 Buying such services like '''[http://www.lifeinsurance.net.au/ life
 insurance]''' in making things better for those people to have its best
 ways that will be better for them during this days. It can make things
 better for those people to have its best ways to satisfy their needs in
 life living in this world. This '''insurances''' people can have the
 things they need in life living in this world. Having such services that
 will make things better for them having the best services that will make
 them have a '''Life Insurance''' in making things better for them during
 this days.

 [[Image(http://onlinearnings.com/wp-content/uploads/2009/07/happy-life-
 insurance.jpg)]]

 It can make things better for those people having such
 '''[http://www.lifeinsurance.net.au/ life insurance]''' in a certain
 period of time. It is best for those people to have such ways that can be
 better for those people on having the things that will make them have such
 '''Living Insurance''' in a certain period of time that will make those
 people have its best ways in living.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/178>
coreboot <http://www.coreboot.org/>


From peter at stuge.se  Tue Mar  1 20:46:51 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 1 Mar 2011 20:46:51 +0100
Subject: [coreboot] [PATCH 1/2] Add subsystemid option to sconfig
In-Reply-To: <1298996910-9031-2-git-send-email-svens@stackframe.org>
References: <1298996910-9031-1-git-send-email-svens@stackframe.org>
	<1298996910-9031-2-git-send-email-svens@stackframe.org>
Message-ID: <20110301194651.4370.qmail@stuge.se>

Sven Schnelle wrote:
> Allow user to add 'subsystemid <vendor> <device> [inherit]' to devicetree.cb for
> PCI and PCI domain devices.
> 
> Example:
> 
> 	device pci 00.0 on
> 	       subsystemid dead beef
> 	end
> 
> If the user wants to have this ID inherited to all subdevices/functions,
> he can add 'inherit', like in the following example:
> 
> 	device pci 00.0 on
> 	       subsystemid dead beef inherit
> 	end
> 
> If the user don't want to inherit a Subsystem for a single device, he can
> specify 'subsystemid 0 0' on this particular device.
> 
> Signed-off-by: Sven Schnelle <svens at stackframe.org>

Acked-by: Peter Stuge <peter at stuge.se>



From peter at stuge.se  Tue Mar  1 20:47:19 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 1 Mar 2011 20:47:19 +0100
Subject: [coreboot] [PATCH 2/2] Use subsystem id from
	devicetree.cb	instead of Kconfig and move all boards to the
	new config scheme.
In-Reply-To: <1298996910-9031-3-git-send-email-svens@stackframe.org>
References: <1298996910-9031-1-git-send-email-svens@stackframe.org>
	<1298996910-9031-3-git-send-email-svens@stackframe.org>
Message-ID: <20110301194719.4470.qmail@stuge.se>

Sven Schnelle wrote:
>  158 files changed, 120 insertions(+), 561 deletions(-)

Signed-off-by and commit message is missing. But:

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Tue Mar  1 20:58:15 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 20:58:15 +0100
Subject: [coreboot] [commit] r6420 - in trunk: src/include/device
	util/sconfig
Message-ID: <E1PuVi3-0002zh-ND@ra.coresystems.de>

Author: svens
Date: Tue Mar  1 20:58:15 2011
New Revision: 6420
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6420

Log:
Add subsystemid option to sconfig

Allow user to add 'subsystemid <vendor> <device> [inherit]' to devicetree.cb for
PCI and PCI domain devices.

Example:

	device pci 00.0 on
	       subsystemid dead beef
	end

If the user wants to have this ID inherited to all subdevices/functions,
he can add 'inherit', like in the following example:

	device pci 00.0 on
	       subsystemid dead beef inherit
	end

If the user don't want to inherit a Subsystem for a single device, he can
specify 'subsystemid 0 0' on this particular device.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/include/device/device.h
   trunk/util/sconfig/main.c
   trunk/util/sconfig/sconfig.h
   trunk/util/sconfig/sconfig.l
   trunk/util/sconfig/sconfig.tab.c_shipped
   trunk/util/sconfig/sconfig.tab.h_shipped
   trunk/util/sconfig/sconfig.y

Modified: trunk/src/include/device/device.h
==============================================================================
--- trunk/src/include/device/device.h	Tue Mar  1 09:09:22 2011	(r6419)
+++ trunk/src/include/device/device.h	Tue Mar  1 20:58:15 2011	(r6420)
@@ -64,6 +64,8 @@
 	struct device_path path;
 	unsigned 	vendor;
 	unsigned 	device;
+	u16 subsystem_vendor;
+	u16  subsystem_device;
 	unsigned int	class;		/* 3 bytes: (base, sub, prog-if) */
 	unsigned int	hdr_type;	/* PCI header type */
 	unsigned int    enabled : 1;	/* set if we should enable the device */

Modified: trunk/util/sconfig/main.c
==============================================================================
--- trunk/util/sconfig/main.c	Tue Mar  1 09:09:22 2011	(r6419)
+++ trunk/util/sconfig/main.c	Tue Mar  1 20:58:15 2011	(r6420)
@@ -59,6 +59,8 @@
 	dev->id = ++devcount;
 	dev->parent = parent;
 	dev->bus = bus;
+	dev->subsystem_vendor = -1;
+	dev->subsystem_device = -1;
 	head->next = dev;
 	head = dev;
 	return dev;
@@ -279,6 +281,18 @@
 	}
 }
 
+void add_pci_subsystem_ids(struct device *dev, int vendor, int device, int inherit)
+{
+	if (dev->bustype != PCI && dev->bustype != PCI_DOMAIN) {
+		printf("ERROR: 'subsystem' only allowed for PCI devices\n");
+		exit(1);
+	}
+
+	dev->subsystem_vendor = vendor;
+	dev->subsystem_device = device;
+	dev->inherit_subsystem = inherit;
+}
+
 static void pass0(FILE *fil, struct device *ptr) {
 	if (ptr->type == device && ptr->id == 0)
 		fprintf(fil, "struct bus %s_links[];\n", ptr->name);
@@ -303,6 +317,12 @@
 		fprintf(fil, "},\n");
 		fprintf(fil, "\t.enabled = %d,\n", ptr->enabled);
 		fprintf(fil, "\t.on_mainboard = 1,\n");
+		if (ptr->subsystem_vendor > 0)
+			fprintf(fil, "\t.subsystem_vendor = 0x%04x,\n", ptr->subsystem_vendor);
+
+		if (ptr->subsystem_device > 0)
+			fprintf(fil, "\t.subsystem_device = 0x%04x,\n", ptr->subsystem_device);
+
 		if (ptr->rescnt > 0) {
 			fprintf(fil, "\t.resource_list = &%s_res[0],\n", ptr->name);
 		}
@@ -392,6 +412,29 @@
 	} while (ptr);
 }
 
+static void inherit_subsystem_ids(FILE *file, struct device *dev)
+{
+	struct device *p;
+	int i =0;
+
+	if (dev->subsystem_vendor != -1 && dev->subsystem_device != -1) {
+		/* user already gave us a subsystem vendor/device */
+		return;
+	}
+
+	for(p = dev; p && p != p->parent; (p = p->parent), i++) {
+
+		if (p->bustype != PCI && p->bustype != PCI_DOMAIN)
+			continue;
+
+		if (p->inherit_subsystem) {
+			dev->subsystem_vendor = p->subsystem_vendor;
+			dev->subsystem_device = p->subsystem_device;
+			break;
+		}
+	}
+}
+
 int main(int argc, char** argv) {
 	if (argc != 3) {
 		printf("usage: sconfig vendor/mainboard outputdir\n");
@@ -444,6 +487,9 @@
 		h = h->next;
 		fprintf(staticc, "#include \"%s/chip.h\"\n", h->name);
 	}
+
+	walk_device_tree(staticc, &root, inherit_subsystem_ids, NULL);
+
 	fprintf(staticc, "\n/* pass 0 */\n");
 	walk_device_tree(staticc, &root, pass0, NULL);
 	fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device *last_dev = &%s;\n", lastdev->name);

Modified: trunk/util/sconfig/sconfig.h
==============================================================================
--- trunk/util/sconfig/sconfig.h	Tue Mar  1 09:09:22 2011	(r6419)
+++ trunk/util/sconfig/sconfig.h	Tue Mar  1 20:58:15 2011	(r6420)
@@ -52,6 +52,9 @@
 	int link;
 	int rescnt;
 	int chiph_exists;
+	int subsystem_vendor;
+	int subsystem_device;
+	int inherit_subsystem;
 	char *ops;
 	char *name;
 	char *name_underscore;
@@ -90,3 +93,4 @@
 void alias_siblings(struct device *d);
 void add_resource(struct device *dev, int type, int index, int base);
 void add_register(struct device *dev, char *name, char *val);
+void add_pci_subsystem_ids(struct device *dev, int vendor, int device, int inherit);

Modified: trunk/util/sconfig/sconfig.l
==============================================================================
--- trunk/util/sconfig/sconfig.l	Tue Mar  1 09:09:22 2011	(r6419)
+++ trunk/util/sconfig/sconfig.l	Tue Mar  1 20:58:15 2011	(r6420)
@@ -42,6 +42,8 @@
 irq		{yylval.number=IRQ; return(RESOURCE);}
 drq		{yylval.number=DRQ; return(RESOURCE);}
 io		{yylval.number=IO; return(RESOURCE);}
+inherit		{return(INHERIT);}
+subsystemid	{return(SUBSYSTEMID);}
 end		{return(END);}
 =		{return(EQUALS);}
 0x[0-9a-fA-F.]+	{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}

Modified: trunk/util/sconfig/sconfig.tab.c_shipped
==============================================================================
--- trunk/util/sconfig/sconfig.tab.c_shipped	Tue Mar  1 09:09:22 2011	(r6419)
+++ trunk/util/sconfig/sconfig.tab.c_shipped	Tue Mar  1 20:58:15 2011	(r6420)
@@ -139,7 +139,9 @@
      IRQ = 274,
      DRQ = 275,
      IO = 276,
-     NUMBER = 277
+     NUMBER = 277,
+     SUBSYSTEMID = 278,
+     INHERIT = 279
    };
 #endif
 
@@ -380,20 +382,20 @@
 /* YYFINAL -- State number of the termination state.  */
 #define YYFINAL  3
 /* YYLAST -- Last index in YYTABLE.  */
-#define YYLAST   24
+#define YYLAST   34
 
 /* YYNTOKENS -- Number of terminals.  */
-#define YYNTOKENS  23
+#define YYNTOKENS  25
 /* YYNNTS -- Number of nonterminals.  */
-#define YYNNTS  11
+#define YYNNTS  12
 /* YYNRULES -- Number of rules.  */
-#define YYNRULES  17
+#define YYNRULES  20
 /* YYNRULES -- Number of states.  */
-#define YYNSTATES  31
+#define YYNSTATES  36
 
 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
 #define YYUNDEFTOK  2
-#define YYMAXUTOK   277
+#define YYMAXUTOK   279
 
 #define YYTRANSLATE(YYX)						\
   ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
@@ -428,7 +430,7 @@
        2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
        2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
        5,     6,     7,     8,     9,    10,    11,    12,    13,    14,
-      15,    16,    17,    18,    19,    20,    21,    22
+      15,    16,    17,    18,    19,    20,    21,    22,    23,    24
 };
 
 #if YYDEBUG
@@ -437,25 +439,28 @@
 static const yytype_uint8 yyprhs[] =
 {
        0,     0,     3,     4,     7,    10,    13,    16,    17,    20,
-      23,    26,    27,    28,    34,    35,    43,    48
+      23,    26,    29,    30,    31,    37,    38,    46,    51,    56,
+      60
 };
 
 /* YYRHS -- A `-1'-separated list of the rules' RHS.  */
 static const yytype_int8 yyrhs[] =
 {
-      24,     0,    -1,    -1,    25,    28,    -1,    26,    30,    -1,
-      26,    28,    -1,    26,    33,    -1,    -1,    27,    30,    -1,
-      27,    28,    -1,    27,    32,    -1,    -1,    -1,     3,    12,
-      29,    26,     9,    -1,    -1,     4,     7,    22,     6,    31,
-      27,     9,    -1,     8,    22,    10,    22,    -1,     5,    12,
-      10,    12,    -1
+      26,     0,    -1,    -1,    27,    30,    -1,    28,    32,    -1,
+      28,    30,    -1,    28,    35,    -1,    -1,    29,    32,    -1,
+      29,    30,    -1,    29,    34,    -1,    29,    36,    -1,    -1,
+      -1,     3,    12,    31,    28,     9,    -1,    -1,     4,     7,
+      22,     6,    33,    29,     9,    -1,     8,    22,    10,    22,
+      -1,     5,    12,    10,    12,    -1,    23,    22,    22,    -1,
+      23,    22,    22,    24,    -1
 };
 
 /* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
 static const yytype_uint8 yyrline[] =
 {
-       0,    34,    34,    34,    36,    36,    36,    36,    38,    38,
-      38,    38,    40,    40,    50,    50,    62,    65
+       0,    35,    35,    35,    37,    37,    37,    37,    39,    39,
+      39,    39,    39,    41,    41,    51,    51,    63,    66,    69,
+      72
 };
 #endif
 
@@ -467,8 +472,9 @@
   "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL",
   "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C",
   "APIC", "APIC_CLUSTER", "PCI_DOMAIN", "IRQ", "DRQ", "IO", "NUMBER",
-  "$accept", "devtree", "$@1", "chipchildren", "devicechildren", "chip",
-  "@2", "device", "@3", "resource", "registers", 0
+  "SUBSYSTEMID", "INHERIT", "$accept", "devtree", "$@1", "chipchildren",
+  "devicechildren", "chip", "@2", "device", "@3", "resource", "registers",
+  "subsystemid", 0
 };
 #endif
 
@@ -479,22 +485,24 @@
 {
        0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
      265,   266,   267,   268,   269,   270,   271,   272,   273,   274,
-     275,   276,   277
+     275,   276,   277,   278,   279
 };
 # endif
 
 /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
 static const yytype_uint8 yyr1[] =
 {
-       0,    23,    25,    24,    26,    26,    26,    26,    27,    27,
-      27,    27,    29,    28,    31,    30,    32,    33
+       0,    25,    27,    26,    28,    28,    28,    28,    29,    29,
+      29,    29,    29,    31,    30,    33,    32,    34,    35,    36,
+      36
 };
 
 /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
 static const yytype_uint8 yyr2[] =
 {
        0,     2,     0,     2,     2,     2,     2,     0,     2,     2,
-       2,     0,     0,     5,     0,     7,     4,     4
+       2,     2,     0,     0,     5,     0,     7,     4,     4,     3,
+       4
 };
 
 /* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
@@ -502,35 +510,35 @@
    means the default is an error.  */
 static const yytype_uint8 yydefact[] =
 {
-       2,     0,     0,     1,     0,     3,    12,     7,     0,     0,
-       0,    13,     5,     4,     6,     0,     0,     0,     0,    14,
-      17,    11,     0,     0,    15,     9,     8,    10,     0,     0,
-      16
+       2,     0,     0,     1,     0,     3,    13,     7,     0,     0,
+       0,    14,     5,     4,     6,     0,     0,     0,     0,    15,
+      18,    12,     0,     0,    16,     0,     9,     8,    10,    11,
+       0,     0,     0,    19,    17,    20
 };
 
 /* YYDEFGOTO[NTERM-NUM].  */
 static const yytype_int8 yydefgoto[] =
 {
-      -1,     1,     2,     8,    22,     5,     7,    13,    21,    27,
-      14
+      -1,     1,     2,     8,    22,     5,     7,    13,    21,    28,
+      14,    29
 };
 
 /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
    STATE-NUM.  */
-#define YYPACT_NINF -10
+#define YYPACT_NINF -9
 static const yytype_int8 yypact[] =
 {
-     -10,     6,     5,   -10,    -1,   -10,   -10,   -10,    -2,     8,
-       0,   -10,   -10,   -10,   -10,    -9,     7,    10,     9,   -10,
-     -10,   -10,     1,    -4,   -10,   -10,   -10,   -10,    12,    -3,
-     -10
+      -9,     3,     1,    -9,    -2,    -9,    -9,    -9,     4,     5,
+      -1,    -9,    -9,    -9,    -9,    -8,     7,     9,     6,    -9,
+      -9,    -9,    -3,     0,    -9,     2,    -9,    -9,    -9,    -9,
+      11,     8,    10,    -5,    -9,    -9
 };
 
 /* YYPGOTO[NTERM-NUM].  */
 static const yytype_int8 yypgoto[] =
 {
-     -10,   -10,   -10,   -10,   -10,    -8,   -10,     2,   -10,   -10,
-     -10
+      -9,    -9,    -9,    -9,    -9,    -6,    -9,    12,    -9,    -9,
+      -9,    -9
 };
 
 /* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
@@ -540,26 +548,28 @@
 #define YYTABLE_NINF -1
 static const yytype_uint8 yytable[] =
 {
-      12,     4,     9,    10,     4,     9,     3,    11,     4,    23,
-      24,     6,    16,    17,    25,    15,    19,    18,    28,    30,
-       0,    20,    29,     0,    26
+       4,     9,    12,     3,     4,    23,    24,     4,     9,    10,
+       6,    16,    15,    11,    17,    19,    26,    18,    20,    35,
+      25,    32,    30,     0,    31,     0,     0,     0,     0,     0,
+      33,     0,    34,     0,    27
 };
 
 static const yytype_int8 yycheck[] =
 {
-       8,     3,     4,     5,     3,     4,     0,     9,     3,     8,
-       9,    12,    12,    22,    22,     7,     6,    10,    22,    22,
-      -1,    12,    10,    -1,    22
+       3,     4,     8,     0,     3,     8,     9,     3,     4,     5,
+      12,    12,     7,     9,    22,     6,    22,    10,    12,    24,
+      23,    10,    22,    -1,    22,    -1,    -1,    -1,    -1,    -1,
+      22,    -1,    22,    -1,    22
 };
 
 /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
    symbol of state STATE-NUM.  */
 static const yytype_uint8 yystos[] =
 {
-       0,    24,    25,     0,     3,    28,    12,    29,    26,     4,
-       5,     9,    28,    30,    33,     7,    12,    22,    10,     6,
-      12,    31,    27,     8,     9,    28,    30,    32,    22,    10,
-      22
+       0,    26,    27,     0,     3,    30,    12,    31,    28,     4,
+       5,     9,    30,    32,    35,     7,    12,    22,    10,     6,
+      12,    33,    29,     8,     9,    23,    30,    32,    34,    36,
+      22,    22,    10,    22,    22,    24
 };
 
 #define yyerrok		(yyerrstatus = 0)
@@ -1380,7 +1390,7 @@
     { postprocess_devtree(); ;}
     break;
 
-  case 12:
+  case 13:
 
     {
 	(yyval.device) = new_chip(cur_parent, cur_bus, (yyvsp[(2) - (2)].string));
@@ -1388,7 +1398,7 @@
 ;}
     break;
 
-  case 13:
+  case 14:
 
     {
 	cur_parent = (yyvsp[(3) - (5)].device)->parent;
@@ -1397,7 +1407,7 @@
 ;}
     break;
 
-  case 14:
+  case 15:
 
     {
 	(yyval.device) = new_device(cur_parent, cur_bus, (yyvsp[(2) - (4)].number), (yyvsp[(3) - (4)].string), (yyvsp[(4) - (4)].number));
@@ -1406,7 +1416,7 @@
 ;}
     break;
 
-  case 15:
+  case 16:
 
     {
 	cur_parent = (yyvsp[(5) - (7)].device)->parent;
@@ -1416,16 +1426,26 @@
 ;}
     break;
 
-  case 16:
+  case 17:
 
     { add_resource(cur_parent, (yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); ;}
     break;
 
-  case 17:
+  case 18:
 
     { add_register(cur_parent, (yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); ;}
     break;
 
+  case 19:
+
+    { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (3)].string), NULL, 16), strtol((yyvsp[(3) - (3)].string), NULL, 16), 0); ;}
+    break;
+
+  case 20:
+
+    { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), strtol((yyvsp[(3) - (4)].string), NULL, 16), 1); ;}
+    break;
+
 
 
       default: break;

Modified: trunk/util/sconfig/sconfig.tab.h_shipped
==============================================================================
--- trunk/util/sconfig/sconfig.tab.h_shipped	Tue Mar  1 09:09:22 2011	(r6419)
+++ trunk/util/sconfig/sconfig.tab.h_shipped	Tue Mar  1 20:58:15 2011	(r6420)
@@ -58,7 +58,9 @@
      IRQ = 274,
      DRQ = 275,
      IO = 276,
-     NUMBER = 277
+     NUMBER = 277,
+     SUBSYSTEMID = 278,
+     INHERIT = 279
    };
 #endif
 

Modified: trunk/util/sconfig/sconfig.y
==============================================================================
--- trunk/util/sconfig/sconfig.y	Tue Mar  1 09:09:22 2011	(r6419)
+++ trunk/util/sconfig/sconfig.y	Tue Mar  1 20:58:15 2011	(r6420)
@@ -29,13 +29,14 @@
 	char *string;
 	int number;
 }
-%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER
+
+%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT
 %%
 devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ;
 
 chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ;
 
-devicechildren: devicechildren device | devicechildren chip | devicechildren resource | /* empty */ ;
+devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | /* empty */ ;
 
 chip: CHIP STRING /* == path */ {
 	$<device>$ = new_chip(cur_parent, cur_bus, $<string>2);
@@ -65,4 +66,11 @@
 registers: REGISTER STRING /* == regname */ EQUALS STRING /* == regval */
 	{ add_register(cur_parent, $<string>2, $<string>4); } ;
 
+subsystemid: SUBSYSTEMID NUMBER NUMBER
+	{ add_pci_subsystem_ids(cur_parent, strtol($<string>2, NULL, 16), strtol($<string>3, NULL, 16), 0); };
+
+subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT
+	{ add_pci_subsystem_ids(cur_parent, strtol($<string>2, NULL, 16), strtol($<string>3, NULL, 16), 1); };
+
+
 %%



From svn at coreboot.org  Tue Mar  1 20:58:49 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 20:58:49 +0100
Subject: [coreboot] [commit] r6421 - in trunk/src: . devices
	mainboard/amd/bimini_fam10 mainboard/amd/dbm690t
	mainboard/amd/inagua mainboard/amd/mahogany
	mainboard/amd/mahogany_fam10 mainboard/amd/persimmon mainboard/...
Message-ID: <E1PuVib-0003PP-3p@ra.coresystems.de>

Author: svens
Date: Tue Mar  1 20:58:47 2011
New Revision: 6421
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6421

Log:
Use subsystem id from devicetree.cb instead of Kconfig and move
all boards to the new config scheme.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/Kconfig
   trunk/src/devices/pci_device.c
   trunk/src/mainboard/amd/bimini_fam10/Kconfig
   trunk/src/mainboard/amd/bimini_fam10/devicetree.cb
   trunk/src/mainboard/amd/dbm690t/Kconfig
   trunk/src/mainboard/amd/dbm690t/devicetree.cb
   trunk/src/mainboard/amd/inagua/Kconfig
   trunk/src/mainboard/amd/inagua/devicetree.cb
   trunk/src/mainboard/amd/mahogany/Kconfig
   trunk/src/mainboard/amd/mahogany/devicetree.cb
   trunk/src/mainboard/amd/mahogany_fam10/Kconfig
   trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb
   trunk/src/mainboard/amd/persimmon/Kconfig
   trunk/src/mainboard/amd/persimmon/devicetree.cb
   trunk/src/mainboard/amd/pistachio/Kconfig
   trunk/src/mainboard/amd/pistachio/devicetree.cb
   trunk/src/mainboard/amd/serengeti_cheetah/Kconfig
   trunk/src/mainboard/amd/serengeti_cheetah/devicetree.cb
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
   trunk/src/mainboard/amd/tilapia_fam10/Kconfig
   trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb
   trunk/src/mainboard/arima/hdama/Kconfig
   trunk/src/mainboard/arima/hdama/devicetree.cb
   trunk/src/mainboard/asrock/939a785gmh/Kconfig
   trunk/src/mainboard/asrock/939a785gmh/devicetree.cb
   trunk/src/mainboard/asrock/e350m1/Kconfig
   trunk/src/mainboard/asrock/e350m1/devicetree.cb
   trunk/src/mainboard/asus/Kconfig
   trunk/src/mainboard/asus/a8n_e/Kconfig
   trunk/src/mainboard/asus/a8n_e/devicetree.cb
   trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig
   trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
   trunk/src/mainboard/asus/a8v-e_se/Kconfig
   trunk/src/mainboard/asus/a8v-e_se/devicetree.cb
   trunk/src/mainboard/asus/m2n-e/Kconfig
   trunk/src/mainboard/asus/m2n-e/devicetree.cb
   trunk/src/mainboard/asus/m2v-mx_se/Kconfig
   trunk/src/mainboard/asus/m2v-mx_se/devicetree.cb
   trunk/src/mainboard/asus/m2v/Kconfig
   trunk/src/mainboard/asus/m2v/devicetree.cb
   trunk/src/mainboard/asus/m4a78-em/Kconfig
   trunk/src/mainboard/asus/m4a78-em/devicetree.cb
   trunk/src/mainboard/asus/m4a785-m/Kconfig
   trunk/src/mainboard/asus/m4a785-m/devicetree.cb
   trunk/src/mainboard/broadcom/blast/Kconfig
   trunk/src/mainboard/broadcom/blast/devicetree.cb
   trunk/src/mainboard/dell/s1850/Kconfig
   trunk/src/mainboard/dell/s1850/devicetree.cb
   trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
   trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
   trunk/src/mainboard/gigabyte/m57sli/Kconfig
   trunk/src/mainboard/gigabyte/m57sli/devicetree.cb
   trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
   trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb
   trunk/src/mainboard/gigabyte/ma78gm/Kconfig
   trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb
   trunk/src/mainboard/hp/dl145_g1/Kconfig
   trunk/src/mainboard/hp/dl145_g1/devicetree.cb
   trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig
   trunk/src/mainboard/intel/Kconfig
   trunk/src/mainboard/intel/d945gclf/Kconfig
   trunk/src/mainboard/intel/d945gclf/devicetree.cb
   trunk/src/mainboard/intel/jarrell/Kconfig
   trunk/src/mainboard/intel/jarrell/devicetree.cb
   trunk/src/mainboard/intel/mtarvon/Kconfig
   trunk/src/mainboard/intel/mtarvon/devicetree.cb
   trunk/src/mainboard/intel/truxton/Kconfig
   trunk/src/mainboard/intel/truxton/devicetree.cb
   trunk/src/mainboard/intel/xe7501devkit/Kconfig
   trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
   trunk/src/mainboard/iwill/dk8_htx/Kconfig
   trunk/src/mainboard/iwill/dk8_htx/devicetree.cb
   trunk/src/mainboard/iwill/dk8s2/Kconfig
   trunk/src/mainboard/iwill/dk8s2/devicetree.cb
   trunk/src/mainboard/jetway/pa78vm5/Kconfig
   trunk/src/mainboard/jetway/pa78vm5/devicetree.cb
   trunk/src/mainboard/kontron/kt690/Kconfig
   trunk/src/mainboard/kontron/kt690/devicetree.cb
   trunk/src/mainboard/lenovo/x60/devicetree.cb
   trunk/src/mainboard/msi/Kconfig
   trunk/src/mainboard/msi/ms7135/Kconfig
   trunk/src/mainboard/msi/ms7135/devicetree.cb
   trunk/src/mainboard/msi/ms7260/Kconfig
   trunk/src/mainboard/msi/ms7260/devicetree.cb
   trunk/src/mainboard/msi/ms9185/Kconfig
   trunk/src/mainboard/msi/ms9185/devicetree.cb
   trunk/src/mainboard/msi/ms9282/Kconfig
   trunk/src/mainboard/msi/ms9282/devicetree.cb
   trunk/src/mainboard/msi/ms9652_fam10/Kconfig
   trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb
   trunk/src/mainboard/newisys/khepri/Kconfig
   trunk/src/mainboard/newisys/khepri/devicetree.cb
   trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
   trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb
   trunk/src/mainboard/roda/Kconfig
   trunk/src/mainboard/roda/rk886ex/Kconfig
   trunk/src/mainboard/roda/rk886ex/devicetree.cb
   trunk/src/mainboard/sunw/ultra40/Kconfig
   trunk/src/mainboard/sunw/ultra40/devicetree.cb
   trunk/src/mainboard/supermicro/Kconfig
   trunk/src/mainboard/supermicro/h8dme/Kconfig
   trunk/src/mainboard/supermicro/h8dme/devicetree.cb
   trunk/src/mainboard/supermicro/h8dmr/Kconfig
   trunk/src/mainboard/supermicro/h8dmr/devicetree.cb
   trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
   trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
   trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig
   trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
   trunk/src/mainboard/supermicro/x6dai_g/Kconfig
   trunk/src/mainboard/supermicro/x6dai_g/devicetree.cb
   trunk/src/mainboard/supermicro/x6dhe_g/Kconfig
   trunk/src/mainboard/supermicro/x6dhe_g/devicetree.cb
   trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig
   trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
   trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig
   trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
   trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig
   trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
   trunk/src/mainboard/technexion/tim5690/Kconfig
   trunk/src/mainboard/technexion/tim5690/devicetree.cb
   trunk/src/mainboard/technexion/tim8690/Kconfig
   trunk/src/mainboard/technexion/tim8690/devicetree.cb
   trunk/src/mainboard/tyan/Kconfig
   trunk/src/mainboard/tyan/s2735/Kconfig
   trunk/src/mainboard/tyan/s2735/devicetree.cb
   trunk/src/mainboard/tyan/s2850/Kconfig
   trunk/src/mainboard/tyan/s2850/devicetree.cb
   trunk/src/mainboard/tyan/s2875/Kconfig
   trunk/src/mainboard/tyan/s2875/devicetree.cb
   trunk/src/mainboard/tyan/s2880/Kconfig
   trunk/src/mainboard/tyan/s2880/devicetree.cb
   trunk/src/mainboard/tyan/s2881/Kconfig
   trunk/src/mainboard/tyan/s2881/devicetree.cb
   trunk/src/mainboard/tyan/s2882/Kconfig
   trunk/src/mainboard/tyan/s2882/devicetree.cb
   trunk/src/mainboard/tyan/s2885/Kconfig
   trunk/src/mainboard/tyan/s2885/devicetree.cb
   trunk/src/mainboard/tyan/s2891/Kconfig
   trunk/src/mainboard/tyan/s2891/devicetree.cb
   trunk/src/mainboard/tyan/s2892/Kconfig
   trunk/src/mainboard/tyan/s2892/devicetree.cb
   trunk/src/mainboard/tyan/s2895/Kconfig
   trunk/src/mainboard/tyan/s2895/devicetree.cb
   trunk/src/mainboard/tyan/s2912/Kconfig
   trunk/src/mainboard/tyan/s2912/devicetree.cb
   trunk/src/mainboard/tyan/s2912_fam10/Kconfig
   trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb
   trunk/src/mainboard/tyan/s4880/Kconfig
   trunk/src/mainboard/tyan/s4880/devicetree.cb
   trunk/src/mainboard/tyan/s4882/Kconfig
   trunk/src/mainboard/tyan/s4882/devicetree.cb
   trunk/src/mainboard/via/Kconfig
   trunk/src/mainboard/via/pc2500e/Kconfig
   trunk/src/mainboard/via/pc2500e/devicetree.cb
   trunk/src/mainboard/wyse/Kconfig
   trunk/src/mainboard/wyse/s50/devicetree.cb
   trunk/src/southbridge/intel/i82801gx/pci.c

Modified: trunk/src/Kconfig
==============================================================================
--- trunk/src/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -137,13 +137,6 @@
 	int
 	default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x0
 config PCI_ROM_RUN
 	bool
 	default n

Modified: trunk/src/devices/pci_device.c
==============================================================================
--- trunk/src/devices/pci_device.c	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/devices/pci_device.c	Tue Mar  1 20:58:47 2011	(r6421)
@@ -586,16 +586,6 @@
 	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 }
 
-unsigned __attribute__((weak)) mainboard_pci_subsystem_vendor_id(__attribute__((unused)) struct device *dev)
-{
-		return CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID;
-}
-
-unsigned __attribute__((weak)) mainboard_pci_subsystem_device_id(__attribute__((unused)) struct device *dev)
-{
-		return CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID;
-}
-
 void pci_dev_enable_resources(struct device *dev)
 {
 	const struct pci_operations *ops;
@@ -604,12 +594,11 @@
 	/* Set the subsystem vendor and device ID for mainboard devices. */
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
-		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", dev_path(dev),
-		       mainboard_pci_subsystem_vendor_id(dev),
-		       mainboard_pci_subsystem_device_id(dev));
-		ops->set_subsystem(dev,
-				   mainboard_pci_subsystem_vendor_id(dev),
-				   mainboard_pci_subsystem_device_id(dev));
+		printk(BIOS_DEBUG, "%s subsystem <- %04x/%04x\n",
+			dev_path(dev), dev->subsystem_vendor,
+			dev->subsystem_device);
+		ops->set_subsystem(dev, dev->subsystem_vendor,
+			dev->subsystem_device);
 	}
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;

Modified: trunk/src/mainboard/amd/bimini_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/bimini_fam10/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/bimini_fam10/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -91,14 +91,6 @@
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/amd/bimini_fam10/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/bimini_fam10/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/bimini_fam10/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/amd/dbm690t/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/dbm690t/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -59,12 +59,4 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_AMD_DBM690T

Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/dbm690t/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -15,6 +15,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690

Modified: trunk/src/mainboard/amd/inagua/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/inagua/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/inagua/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -118,14 +118,6 @@
         int
         default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-        hex
-        default 0x1510
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-        hex
-        default 0x1022
-
 config RAMBASE
         hex
         default 0x200000

Modified: trunk/src/mainboard/amd/inagua/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/inagua/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/inagua/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -23,6 +23,7 @@
                 end
         end
         device pci_domain 0 on
+                subsystemid 0x1022 0x1510 inherit
                 chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex

Modified: trunk/src/mainboard/amd/mahogany/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/mahogany/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/mahogany/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -73,12 +73,4 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
 endif # BOARD_AMD_MAHOGANY

Modified: trunk/src/mainboard/amd/mahogany/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/mahogany/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/mahogany/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -15,6 +15,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -79,14 +79,6 @@
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/amd/persimmon/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/persimmon/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/persimmon/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -118,14 +118,6 @@
         int
         default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-        hex
-        default 0x1510
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-        hex
-        default 0x1022
-
 config RAMBASE
         hex
         default 0x200000

Modified: trunk/src/mainboard/amd/persimmon/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/persimmon/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/persimmon/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -23,6 +23,7 @@
                 end
         end
         device pci_domain 0 on
+                subsystemid 0x1022 0x1510 inherit
                 chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex

Modified: trunk/src/mainboard/amd/pistachio/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/pistachio/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/pistachio/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -71,12 +71,4 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_AMD_PISTACHIO

Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/pistachio/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/pistachio/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -15,6 +15,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge, K8 HT Configuration
 				chip southbridge/amd/rs690

Modified: trunk/src/mainboard/amd/serengeti_cheetah/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/serengeti_cheetah/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -82,14 +82,6 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config ACPI_SSDTX_NUM
 	int
 	default 4

Modified: trunk/src/mainboard/amd/serengeti_cheetah/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/serengeti_cheetah/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x2b80 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -84,14 +84,6 @@
 	int
 	default 5
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x2b80 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/amd/tilapia_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/tilapia_fam10/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -79,14 +79,6 @@
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/arima/hdama/Kconfig
==============================================================================
--- trunk/src/mainboard/arima/hdama/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/arima/hdama/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -21,14 +21,6 @@
 	string
 	default arima/hdama
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x161f
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3016
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0

Modified: trunk/src/mainboard/arima/hdama/devicetree.cb
==============================================================================
--- trunk/src/mainboard/arima/hdama/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/arima/hdama/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x161f 0x3016 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asrock/939a785gmh/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -74,12 +74,4 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
 endif # BOARD_ASROCK_939A785GMH

Modified: trunk/src/mainboard/asrock/939a785gmh/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asrock/939a785gmh/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -16,6 +16,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/asrock/e350m1/Kconfig
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asrock/e350m1/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -118,14 +118,6 @@
         int
         default 0
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-        hex
-        default 0x1510
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-        hex
-        default 0x1022
-
 config RAMBASE
         hex
         default 0x200000

Modified: trunk/src/mainboard/asrock/e350m1/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asrock/e350m1/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asrock/e350m1/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -23,6 +23,7 @@
                 end
         end
         device pci_domain 0 on
+                subsystemid 0x1022 0x1510 inherit
                 chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex

Modified: trunk/src/mainboard/asus/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -77,8 +77,4 @@
 	string
 	default "ASUS"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # VENDOR_ASUS

Modified: trunk/src/mainboard/asus/a8n_e/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/a8n_e/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -70,12 +70,4 @@
 	int
 	default 13
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x815a
-
 endif # BOARD_ASUS_A8N_E

Modified: trunk/src/mainboard/asus/a8n_e/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/a8n_e/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
   end
 
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1043 0x815a inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge

Modified: trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -70,8 +70,4 @@
 	hex
 	default 0x0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # BOARD_ASUS_A8V_E_DELUXE

Modified: trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 1043 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/a8v-e_se/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -70,8 +70,4 @@
 	hex
 	default 0x0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # BOARD_ASUS_A8V_E_SE

Modified: trunk/src/mainboard/asus/a8v-e_se/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/a8v-e_se/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1043 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/asus/m2n-e/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m2n-e/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/m2n-e/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -98,8 +98,4 @@
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x8239
-
 endif # BOARD_ASUS_M2N_E

Modified: trunk/src/mainboard/asus/m2n-e/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/m2n-e/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/m2n-e/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -25,6 +25,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1043 0x8239 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge

Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -89,8 +89,4 @@
 	hex
 	default 0x20
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 endif # BOARD_ASUS_M2V_MX_SE

Modified: trunk/src/mainboard/asus/m2v-mx_se/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/m2v-mx_se/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1043 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/asus/m2v/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m2v/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/m2v/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -75,10 +75,6 @@
 	hex
 	default 0x0
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 config IRQ_SLOT_COUNT
 	int
 	default 14

Modified: trunk/src/mainboard/asus/m2v/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/m2v/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/m2v/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x143 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/asus/m4a78-em/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m4a78-em/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/m4a78-em/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -77,14 +77,6 @@
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x83f1
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/asus/m4a78-em/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/m4a78-em/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/m4a78-em/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1043 0x83f1 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/asus/m4a785-m/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/m4a785-m/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -78,14 +78,6 @@
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x83a2
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1043
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/asus/m4a785-m/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/asus/m4a785-m/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1043 0x83a2 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/broadcom/blast/Kconfig
==============================================================================
--- trunk/src/mainboard/broadcom/blast/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/broadcom/blast/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -70,12 +70,4 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x161f
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_BROADCOM_BLAST

Modified: trunk/src/mainboard/broadcom/blast/devicetree.cb
==============================================================================
--- trunk/src/mainboard/broadcom/blast/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/broadcom/blast/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x161f 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
                               #  devices on link 0

Modified: trunk/src/mainboard/dell/s1850/Kconfig
==============================================================================
--- trunk/src/mainboard/dell/s1850/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/dell/s1850/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -26,14 +26,6 @@
 	string
 	default "PowerEdge 1850"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x5580
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/dell/s1850/devicetree.cb
==============================================================================
--- trunk/src/mainboard/dell/s1850/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/dell/s1850/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x5580 inherit
 		chip southbridge/intel/i82801ex # i82801er
 			# USB ports
 			device pci 1d.0 on end

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -78,14 +78,6 @@
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1039
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1234
-
 config IRQ_SLOT_COUNT
 	int
 	default 11

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x1039 0x1234 inherit
 		chip northbridge/amd/amdk8 #mc0
 			device pci 18.0 on
 				#  devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/gigabyte/m57sli/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -82,14 +82,6 @@
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config IRQ_SLOT_COUNT
 	int
 	default 11

Modified: trunk/src/mainboard/gigabyte/m57sli/devicetree.cb
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/gigabyte/m57sli/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
 end
 device pci_domain 0 on				# PCI domain
+  subsystemid 0x1022 0x2b80 inherit
   chip northbridge/amd/amdk8			# Northbridge / RAM controller
     device pci 18.0 on				# Link 0 == LDT 0
       chip southbridge/nvidia/mcp55		# Southbridge

Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -79,14 +79,6 @@
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -79,14 +79,6 @@
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x3060 0x1022 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/hp/dl145_g1/Kconfig
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/hp/dl145_g1/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -34,14 +34,6 @@
 	string
 	default "ProLiant DL145 G1"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x7460
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/hp/dl145_g1/devicetree.cb
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/hp/dl145_g1/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on
+    subsystemid 0x1022 0x7460 inherit
     chip northbridge/amd/amdk8
       device pci 18.0 on end # link 0
       device pci 18.0 on end # link 1

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -79,14 +79,6 @@
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x0000
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x0000
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/intel/Kconfig
==============================================================================
--- trunk/src/mainboard/intel/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -32,8 +32,4 @@
 	string
 	default "Intel"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
 endif # VENDOR_INTEL

Modified: trunk/src/mainboard/intel/d945gclf/Kconfig
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/d945gclf/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -49,10 +49,6 @@
 	string
 	default "D945GCLF"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x464C
-
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xf0000000

Modified: trunk/src/mainboard/intel/d945gclf/devicetree.cb
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/d945gclf/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -26,6 +26,7 @@
         end
 
         device pci_domain 0 on
+                subsystemid 0x8086 0x464c inherit
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
 		device pci 02.0 on end # vga controller

Modified: trunk/src/mainboard/intel/jarrell/Kconfig
==============================================================================
--- trunk/src/mainboard/intel/jarrell/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/jarrell/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -35,14 +35,6 @@
 	int
 	default 18
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1079
-
 config DIMM_MAP_LOGICAL
 	hex
 	default 0x0124

Modified: trunk/src/mainboard/intel/jarrell/devicetree.cb
==============================================================================
--- trunk/src/mainboard/intel/jarrell/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/jarrell/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520
 	device pci_domain 0 on
+		subsystemid 0x8086 0x1079 inherit
 		device pci 00.0 on end
 		device pci 00.1 on end
 		device pci 01.0 on end

Modified: trunk/src/mainboard/intel/mtarvon/Kconfig
==============================================================================
--- trunk/src/mainboard/intel/mtarvon/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/mtarvon/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -25,14 +25,6 @@
 	int
 	default 1
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2680
-
 config DCACHE_RAM_BASE
 	hex
 	default 0xffdf8000

Modified: trunk/src/mainboard/intel/mtarvon/devicetree.cb
==============================================================================
--- trunk/src/mainboard/intel/mtarvon/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/mtarvon/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -1,5 +1,6 @@
 chip northbridge/intel/i3100
         device pci_domain 0 on
+                subsystemid 0x8086 0x2680 inherit
                 device pci 00.0 on end # IMCH
                 device pci 00.1 on end # IMCH error status
                 device pci 01.0 on end # IMCH EDMA engine

Modified: trunk/src/mainboard/intel/truxton/Kconfig
==============================================================================
--- trunk/src/mainboard/intel/truxton/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/truxton/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -27,14 +27,6 @@
 	int
 	default 1
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2680
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/intel/truxton/devicetree.cb
==============================================================================
--- trunk/src/mainboard/intel/truxton/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/truxton/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -1,5 +1,6 @@
 chip northbridge/intel/i3100
         device pci_domain 0 on
+                subsystemid 0x8086 0x2680 inherit
                 device pci 00.0 on end # IMCH
                 device pci 00.1 on end # IMCH error status
                 device pci 01.0 on end # IMCH EDMA engine

Modified: trunk/src/mainboard/intel/xe7501devkit/Kconfig
==============================================================================
--- trunk/src/mainboard/intel/xe7501devkit/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/xe7501devkit/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -37,12 +37,4 @@
 	int
 	default 2
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x8086
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2480
-
 endif # BOARD_INTEL_XE7501DEVKIT

Modified: trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
==============================================================================
--- trunk/src/mainboard/intel/xe7501devkit/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/intel/xe7501devkit/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7501
 	device pci_domain 0 on
+		subsystemid 0x8086 0x2480 inherit
 		device pci 0.0 on end # Chipset host controller
 		device pci 0.1 on end # Host RASUM controller
 		device pci 2.0 on # Hub interface B

Modified: trunk/src/mainboard/iwill/dk8_htx/Kconfig
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/iwill/dk8_htx/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -63,14 +63,6 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config ACPI_SSDTX_NUM
 	int
 	default 5

Modified: trunk/src/mainboard/iwill/dk8_htx/devicetree.cb
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/iwill/dk8_htx/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x2b80 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end
 			device pci 18.0 on end

Modified: trunk/src/mainboard/iwill/dk8s2/Kconfig
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/iwill/dk8s2/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -60,12 +60,4 @@
 	int
 	default 12
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x161f
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3016
-
 endif # BOARD_IWILL_DK8S2

Modified: trunk/src/mainboard/iwill/dk8s2/devicetree.cb
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/iwill/dk8s2/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x161f 0x3016 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on # LDT 0
 				chip southbridge/amd/amd8131

Modified: trunk/src/mainboard/jetway/pa78vm5/Kconfig
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/jetway/pa78vm5/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -79,14 +79,6 @@
 	hex
 	default 0xc0000
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3060
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/jetway/pa78vm5/devicetree.cb
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/jetway/pa78vm5/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/kontron/kt690/Kconfig
==============================================================================
--- trunk/src/mainboard/kontron/kt690/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/kontron/kt690/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -28,14 +28,6 @@
 	string
 	default kontron/kt690
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1488
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6900
-
 config APIC_ID_OFFSET
 	hex
 	default 0x0

Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb
==============================================================================
--- trunk/src/mainboard/kontron/kt690/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/kontron/kt690/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -15,6 +15,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1488 0x6900 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690

Modified: trunk/src/mainboard/lenovo/x60/devicetree.cb
==============================================================================
--- trunk/src/mainboard/lenovo/x60/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/lenovo/x60/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -22,17 +22,23 @@
 
 chip northbridge/intel/i945
 
-        device lapic_cluster 0 on
-                chip cpu/intel/socket_mFCPGA478
-                        device lapic 0 on end
-                end
-        end
-
-        device pci_domain 0 on
-                device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 02.1 on end # display controller
-                chip southbridge/intel/i82801gx
+	device lapic_cluster 0 on
+		chip cpu/intel/socket_mFCPGA478
+			device lapic 0 on end
+		end
+	end
+
+	device pci_domain 0 on
+		device pci 00.0 on # Host bridge
+			subsystemid 0x17aa 0x2017
+		end
+		device pci 02.0 on # VGA controller
+			subsystemid 0x17aa 0x201a
+		end
+		device pci 02.1 on # display controller
+			subsystemid 0x17aa 0x201a
+		end
+		chip southbridge/intel/i82801gx
 			register "pirqa_routing" = "0x0b"
 			register "pirqb_routing" = "0x0b"
 			register "pirqc_routing" = "0x0b"
@@ -46,23 +52,36 @@
 			#  0 No effect (default)
 			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
 			#  2 SCI (if corresponding GPIO_EN bit is also set)
-                        register "gpi13_routing" = "2"
-                        register "gpi12_routing" = "2"
-                        register "gpi8_routing" = "2"
+			register "gpi13_routing" = "2"
+			register "gpi12_routing" = "2"
+			register "gpi8_routing" = "2"
 
-                        register "sata_ahci" = "0x0"
+			register "sata_ahci" = "0x0"
 
 			register "gpe0_en" = "0x11000006"
 
-			device pci 1b.0 on end # Audio Controller
+			device pci 1b.0 on # Audio Cnotroller
+				subsystemid 0x17aa 0x2010
+			end
 			device pci 1c.0 on end # Ethernet
 			device pci 1c.1 on end # Atheros WLAN
-			device pci 1d.0 on end # USB UHCI
-			device pci 1d.1 on end # USB UHCI
-			device pci 1d.2 on end # USB UHCI
-			device pci 1d.3 on end # USB UHCI
-			device pci 1d.7 on end # USB2 EHCI
+			device pci 1d.0 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.1 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.2 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.3 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.7 on # USB2 EHCI
+				subsystemid 0x17aa 0x200b
+			end
 			device pci 1f.0 on # PCI-LPC bridge
+				subsystemid 0x17aa 0x2009
 				chip ec/lenovo/pmh7
 					device pnp ff.1 on # dummy
 					end
@@ -120,9 +139,15 @@
 					end
 				end
 			end
-			device pci 1f.1 off end # IDE
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
+			device pci 1f.1 off # IDE
+				subsystemid 0x17aa 0x200c
+			end
+			device pci 1f.2 on # SATA
+				subsystemid 0x17aa 0x200d
+			end
+			device pci 1f.3 on # SMBUS
+				subsystemid 0x17aa 0x200f
+			end
 		end
 		chip southbridge/ricoh/rl5c476
 		end

Modified: trunk/src/mainboard/msi/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -56,8 +56,4 @@
 	string
 	default "MSI"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
 endif # VENDOR_MSI

Modified: trunk/src/mainboard/msi/ms7135/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7135/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/ms7135/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -34,10 +34,6 @@
 	string
 	default "MS-7135"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x7135
-
 config MAX_CPUS
 	int
 	default 2

Modified: trunk/src/mainboard/msi/ms7135/devicetree.cb
==============================================================================
--- trunk/src/mainboard/msi/ms7135/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/ms7135/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
   end
 
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x7135 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge

Modified: trunk/src/mainboard/msi/ms7260/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7260/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/ms7260/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -80,14 +80,6 @@
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x7260
-
 config IRQ_SLOT_COUNT
 	int
 	default 11

Modified: trunk/src/mainboard/msi/ms7260/devicetree.cb
==============================================================================
--- trunk/src/mainboard/msi/ms7260/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/ms7260/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x7260 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge

Modified: trunk/src/mainboard/msi/ms9185/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9185/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/ms9185/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -71,12 +71,4 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 endif # BOARD_MSI_MS9185

Modified: trunk/src/mainboard/msi/ms9185/devicetree.cb
==============================================================================
--- trunk/src/mainboard/msi/ms9185/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/ms9185/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
                 end
         end
        device pci_domain 0 on
+               subsystemid 0x1022 0x2b80 inherit
                chip northbridge/amd/amdk8
                        device pci 18.0 on end
                        device pci 18.0 on end

Modified: trunk/src/mainboard/msi/ms9282/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9282/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/ms9282/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -72,14 +72,6 @@
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x9282
-
 config IRQ_SLOT_COUNT
 	int
 	default 11

Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb
==============================================================================
--- trunk/src/mainboard/msi/ms9282/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/ms9282/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x9282 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge

Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -87,14 +87,6 @@
 	string
 	default "MS-9652"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1462
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x9652
-
 config RAMBASE
 	hex
 	default 0x200000

Modified: trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -28,6 +28,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1462 0x9652 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on			# Link 0
         chip southbridge/nvidia/mcp55		# Southbridge

Modified: trunk/src/mainboard/newisys/khepri/Kconfig
==============================================================================
--- trunk/src/mainboard/newisys/khepri/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/newisys/khepri/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -69,12 +69,4 @@
 	int
 	default 9
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x17c2
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x10
-
 endif # BOARD_NEWISYS_KHEPRI

Modified: trunk/src/mainboard/newisys/khepri/devicetree.cb
==============================================================================
--- trunk/src/mainboard/newisys/khepri/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/newisys/khepri/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
 	end
 
 	device pci_domain 0 on
+		subsystemid 0x17c2 0x0010 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end # LDT 0
 			device pci 18.0 on     # LDT 1

Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -84,14 +84,6 @@
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2b80
-
 config IRQ_SLOT_COUNT
 	int
 	default 11

Modified: trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1022 0x2b80 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/mcp55		# Southbridge

Modified: trunk/src/mainboard/roda/Kconfig
==============================================================================
--- trunk/src/mainboard/roda/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/roda/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -14,8 +14,4 @@
 	string
 	default "Roda"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x4352
-
 endif # VENDOR_RODA

Modified: trunk/src/mainboard/roda/rk886ex/Kconfig
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/roda/rk886ex/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -46,10 +46,6 @@
 	int
 	default 2
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6886
-
 config MAXIMUM_SUPPORTED_FREQUENCY
 	int
 	default 400

Modified: trunk/src/mainboard/roda/rk886ex/devicetree.cb
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/roda/rk886ex/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -28,6 +28,7 @@
         end
 
         device pci_domain 0 on
+                subsystemid 0x4352 0x0686 inherit
                 device pci 00.0 on end # host bridge
 		# auto detection:
 		#device pci 01.0 off end # i945 PCIe root port

Modified: trunk/src/mainboard/sunw/ultra40/Kconfig
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/sunw/ultra40/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -75,12 +75,4 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x108e
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x40
-
 endif # BOARD_SUNW_ULTRA40

Modified: trunk/src/mainboard/sunw/ultra40/devicetree.cb
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/sunw/ultra40/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x108e 0x0040 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on			# Link 0 == LDT 0

Modified: trunk/src/mainboard/supermicro/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -38,8 +38,4 @@
 	string
 	default "Supermicro"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
 endif # VENDOR_SUPERMICRO

Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/h8dme/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -81,12 +81,4 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 endif # BOARD_SUPERMICRO_H8DME

Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end

Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/h8dmr/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -80,12 +80,4 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 endif # BOARD_SUPERMICRO_H8DMR

Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -100,8 +100,4 @@
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 endif # BOARD_SUPERMICRO_H8DMR_FAM10

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -99,10 +99,6 @@
 	bool
 	default y
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x1511
-
 config STACK_SIZE
 	hex
 	default 0x10000

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x15d9 0x1511 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end

Modified: trunk/src/mainboard/supermicro/x6dai_g/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/x6dai_g/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -23,14 +23,6 @@
 	string
 	default "X6DAi-G"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6780
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/supermicro/x6dai_g/devicetree.cb
==============================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/x6dai_g/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7525 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x6780 inherit
 		chip southbridge/intel/esb6300  # esb6300
 			register "pirq_a_d" = "0x0b0a0a05"
 			register "pirq_e_h" = "0x0a0b0c80"

Modified: trunk/src/mainboard/supermicro/x6dhe_g/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/x6dhe_g/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -25,14 +25,6 @@
 	string
 	default "X6DHE-G"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6080
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/supermicro/x6dhe_g/devicetree.cb
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/x6dhe_g/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
 		device pnp 00.3 off end
 	end
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x6080 inherit
 		chip southbridge/intel/esb6300	# ESB6300
 			register "pirq_a_d" = "0x0b070a05"
 			register "pirq_e_h" = "0x0a808080"

Modified: trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -26,14 +26,6 @@
 	string
 	default "X6DHE-G2"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x6080
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
 		device pnp 00.3 off end
 	end
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x6080 inherit
 		chip southbridge/intel/i82801ex	# ICH5R
 			register "pirq_a_d" = "0x0b070a05"
 			register "pirq_e_h" = "0x0a808080"

Modified: trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -25,14 +25,6 @@
 	string
 	default "X6DHR-iG"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x5580
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x5580 inherit
 		chip southbridge/intel/i82801ex # i82801er
 			# USB ports
 			device pci 1d.0 on end

Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -25,14 +25,6 @@
 	string
 	default "X6DHR-iG2"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x15d9
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x5580
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on
+		subsystemid 0x15d9 0x5580 inherit
 		chip southbridge/intel/i82801ex # i82801er
 			# USB ports
 			device pci 1d.0 on end

Modified: trunk/src/mainboard/technexion/tim5690/Kconfig
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/technexion/tim5690/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -60,14 +60,6 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 config STACK_SIZE
 	hex
 	default 0x2000

Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/technexion/tim5690/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -15,6 +15,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690

Modified: trunk/src/mainboard/technexion/tim8690/Kconfig
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/technexion/tim8690/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -59,12 +59,4 @@
 	int
 	default 11
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1022
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x3050
-
 endif # BOARD_TECHNEXION_TIM8690

Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/technexion/tim8690/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -15,6 +15,7 @@
 		end
 	end
 	device pci_domain 0 on
+		subsystemid 0x1022 0x3050 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690

Modified: trunk/src/mainboard/tyan/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -74,8 +74,4 @@
 	string
 	default "Tyan"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x10f1
-
 endif # VENDOR_TYAN

Modified: trunk/src/mainboard/tyan/s2735/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2735/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2735/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -45,8 +45,4 @@
 	int
 	default 2
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2735
-
 endif # BOARD_TYAN_S2735

Modified: trunk/src/mainboard/tyan/s2735/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2735/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2735/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -1,5 +1,6 @@
 chip northbridge/intel/e7501
         device pci_domain 0 on
+		subsystemid 0x10f1 0x2735 inherit
 		device pci 0.0 on end
         	device pci 0.1 on end
         	device pci 2.0 on

Modified: trunk/src/mainboard/tyan/s2850/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2850/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2850/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -23,10 +23,6 @@
 	string
 	default "S2850"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2850
-
 config MAX_CPUS
 	int
 	default 2

Modified: trunk/src/mainboard/tyan/s2850/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2850/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2850/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x10f1 0x2850 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on # LDT0
 				#  devices on link 2, link 2 == LDT 2

Modified: trunk/src/mainboard/tyan/s2875/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2875/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2875/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -25,10 +25,6 @@
 	string
 	default "S2875"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2875
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/tyan/s2875/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2875/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2875/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x10f1 0x2875 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/tyan/s2880/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2880/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2880/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -33,10 +33,6 @@
 	string
 	default "S2880"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2880
-
 config MAX_CPUS
 	int
 	default 2

Modified: trunk/src/mainboard/tyan/s2880/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2880/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2880/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x10f1 0x2880 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/tyan/s2881/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2881/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2881/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -35,10 +35,6 @@
 	string
 	default "S2881"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2881
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/tyan/s2881/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2881/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2881/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on
+    subsystemid 0x10f1 0x2881 inherit
     chip northbridge/amd/amdk8
       device pci 18.0 on end # link 0
       device pci 18.0 on end # link 1

Modified: trunk/src/mainboard/tyan/s2882/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2882/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2882/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -34,10 +34,6 @@
 	string
 	default "S2882"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2882
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/tyan/s2882/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2882/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2882/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
         end
 
 	device pci_domain 0 on
+		subsystemid 0x10f1 0x2882 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge
 				#  devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/tyan/s2885/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2885/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2885/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -35,10 +35,6 @@
 	string
 	default "S2885"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2885
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/tyan/s2885/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2885/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2885/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x10f1 0x2885 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on # LDT0
 				chip southbridge/amd/amd8151

Modified: trunk/src/mainboard/tyan/s2891/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2891/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2891/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -36,10 +36,6 @@
 	string
 	default "S2891"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2891
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/tyan/s2891/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2891/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2891/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2891 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge

Modified: trunk/src/mainboard/tyan/s2892/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2892/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2892/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -35,10 +35,6 @@
 	string
 	default "S2892"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2892
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/tyan/s2892/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2892/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2892/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2892 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge

Modified: trunk/src/mainboard/tyan/s2895/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2895/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2895/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -40,10 +40,6 @@
 	string
 	default "S2895"
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2895
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/src/mainboard/tyan/s2895/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2895/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2895/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2895 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on			# Link 0 == LDT 0
         chip southbridge/nvidia/ck804		# Southbridge

Modified: trunk/src/mainboard/tyan/s2912/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2912/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -79,10 +79,6 @@
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2912
-
 config IRQ_SLOT_COUNT
 	int
 	default 11

Modified: trunk/src/mainboard/tyan/s2912/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2912/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2912/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2912 inherit
     chip northbridge/amd/amdk8			# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end

Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -80,10 +80,6 @@
 	bool
 	default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x2912
-
 config IRQ_SLOT_COUNT
 	int
 	default 11

Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x10f1 0x2912 inherit
     chip northbridge/amd/amdfam10		# Northbridge / RAM controller
       device pci 18.0 on end
       device pci 18.0 on end

Modified: trunk/src/mainboard/tyan/s4880/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s4880/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s4880/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -65,8 +65,4 @@
 	int
 	default 22
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x4880
-
 endif # BOARD_TYAN_S4880

Modified: trunk/src/mainboard/tyan/s4880/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s4880/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s4880/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -6,6 +6,7 @@
         end
 
 	device pci_domain 0 on
+		subsystemid 0x10f1 0x4880 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end # LDT0
 			device pci 18.0 on end # LDT1

Modified: trunk/src/mainboard/tyan/s4882/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s4882/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s4882/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -65,8 +65,4 @@
 	int
 	default 22
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0x4882
-
 endif # BOARD_TYAN_S4882

Modified: trunk/src/mainboard/tyan/s4882/devicetree.cb
==============================================================================
--- trunk/src/mainboard/tyan/s4882/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/tyan/s4882/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -5,6 +5,7 @@
                 end
         end
 	device pci_domain 0 on
+		subsystemid 0x10f1 0x4882 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end # LDT0
 			device pci 18.0 on #  northbridge

Modified: trunk/src/mainboard/via/Kconfig
==============================================================================
--- trunk/src/mainboard/via/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/via/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -32,8 +32,4 @@
 	string
 	default "VIA"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1019
-
 endif # VENDOR_VIA

Modified: trunk/src/mainboard/via/pc2500e/Kconfig
==============================================================================
--- trunk/src/mainboard/via/pc2500e/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/via/pc2500e/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -26,14 +26,6 @@
 	int
 	default 10
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x1019
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	hex
-	default 0xaa51
-
 config VGA_BIOS_FILE
 	string
 	default "M14CRT.ROM"

Modified: trunk/src/mainboard/via/pc2500e/devicetree.cb
==============================================================================
--- trunk/src/mainboard/via/pc2500e/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/via/pc2500e/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -1,5 +1,6 @@
 chip northbridge/via/cn700			# Northbridge
   device pci_domain 0 on			# PCI domain
+    subsystemid 0x1019 0xaa51 inherit
     device pci 0.0 on end			# AGP Bridge
     device pci 0.1 on end			# Error Reporting
     device pci 0.2 on end			# Host Bus Control

Modified: trunk/src/mainboard/wyse/Kconfig
==============================================================================
--- trunk/src/mainboard/wyse/Kconfig	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/wyse/Kconfig	Tue Mar  1 20:58:47 2011	(r6421)
@@ -32,8 +32,4 @@
 	string
 	default "Wyse"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	hex
-	default 0x102d
-
 endif # VENDOR_WYSE

Modified: trunk/src/mainboard/wyse/s50/devicetree.cb
==============================================================================
--- trunk/src/mainboard/wyse/s50/devicetree.cb	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/mainboard/wyse/s50/devicetree.cb	Tue Mar  1 20:58:47 2011	(r6421)
@@ -28,6 +28,7 @@
 		end
 	end
   	device pci_domain 0 on 
+		subsystemid 102d 0 inherit
     		device pci 1.0 on end
 		device pci 1.1 on end
       		chip southbridge/amd/cs5536

Modified: trunk/src/southbridge/intel/i82801gx/pci.c
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/pci.c	Tue Mar  1 20:58:15 2011	(r6420)
+++ trunk/src/southbridge/intel/i82801gx/pci.c	Tue Mar  1 20:58:47 2011	(r6421)
@@ -71,13 +71,11 @@
 	/* Set the subsystem vendor and device id for mainboard devices */
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
-		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
-			dev_path(dev),
-			mainboard_pci_subsystem_vendor_id(dev),
-			mainboard_pci_subsystem_device_id(dev));
-		ops->set_subsystem(dev,
-			mainboard_pci_subsystem_vendor_id(dev),
-			mainboard_pci_subsystem_device_id(dev));
+		printk(BIOS_DEBUG, "%s subsystem <- %04x/%04x\n",
+		       dev_path(dev), dev->subsystem_vendor,
+		       dev->subsystem_device);
+		ops->set_subsystem(dev, dev->subsystem_vendor,
+				   dev->subsystem_device);
 	}
 
 	command = pci_read_config16(dev, PCI_COMMAND);



From svens at stackframe.org  Tue Mar  1 21:02:23 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Mar 2011 21:02:23 +0100
Subject: [coreboot] [PATCH 1/2] Add subsystemid option to sconfig
In-Reply-To: <20110301194651.4370.qmail@stuge.se> (Peter Stuge's message of
	"Tue\, 1 Mar 2011 20\:46\:51 +0100")
References: <1298996910-9031-1-git-send-email-svens@stackframe.org>
	<1298996910-9031-2-git-send-email-svens@stackframe.org>
	<20110301194651.4370.qmail@stuge.se>
Message-ID: <87sjv638z4.fsf@begreifnix.stackframe.org>

Peter Stuge <peter at stuge.se> writes:

> Sven Schnelle wrote:
>> Allow user to add 'subsystemid <vendor> <device> [inherit]' to devicetree.cb for
>> PCI and PCI domain devices.
>> 
>> Example:
>> 
>> 	device pci 00.0 on
>> 	       subsystemid dead beef
>> 	end
>> 
>> If the user wants to have this ID inherited to all subdevices/functions,
>> he can add 'inherit', like in the following example:
>> 
>> 	device pci 00.0 on
>> 	       subsystemid dead beef inherit
>> 	end
>> 
>> If the user don't want to inherit a Subsystem for a single device, he can
>> specify 'subsystemid 0 0' on this particular device.
>> 
>> Signed-off-by: Sven Schnelle <svens at stackframe.org>
>
> Acked-by: Peter Stuge <peter at stuge.se>

r6420, thanks.

~sven



From svens at stackframe.org  Tue Mar  1 21:02:39 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Mar 2011 21:02:39 +0100
Subject: [coreboot] [PATCH 2/2] Use subsystem id from
	devicetree.cb	instead of Kconfig and move all boards to the
	new config scheme.
In-Reply-To: <20110301194719.4470.qmail@stuge.se> (Peter Stuge's message of
	"Tue\, 1 Mar 2011 20\:47\:19 +0100")
References: <1298996910-9031-1-git-send-email-svens@stackframe.org>
	<1298996910-9031-3-git-send-email-svens@stackframe.org>
	<20110301194719.4470.qmail@stuge.se>
Message-ID: <87mxle38yo.fsf@begreifnix.stackframe.org>

Peter Stuge <peter at stuge.se> writes:

> Sven Schnelle wrote:
>>  158 files changed, 120 insertions(+), 561 deletions(-)
>
> Signed-off-by and commit message is missing. But:
>
> Acked-by: Peter Stuge <peter at stuge.se>

r6421, thanks.

~sven



From svn at coreboot.org  Tue Mar  1 21:53:25 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 21:53:25 +0100
Subject: [coreboot] build service results for r6421
Message-ID: <E1PuWZR-0003D6-Pf@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "svens" checked in revision 6421 to
the coreboot repository. This caused the following 
changes:

Change Log:
Use subsystem id from devicetree.cb instead of Kconfig and move
all boards to the new config scheme.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>

Build Log:
Compilation of amd:bimini_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=bimini_fam10&vendor=amd&num=2
Compilation of amd:dbm690t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=dbm690t&vendor=amd&num=2
Compilation of amd:inagua has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=inagua&vendor=amd&num=2
Compilation of amd:mahogany has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=mahogany&vendor=amd&num=2
Compilation of amd:mahogany_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=mahogany_fam10&vendor=amd&num=2
Compilation of amd:persimmon has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=persimmon&vendor=amd&num=2
Compilation of amd:pistachio has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=pistachio&vendor=amd&num=2
Compilation of amd:serengeti_cheetah has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=serengeti_cheetah&vendor=amd&num=2
Compilation of amd:serengeti_cheetah_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=serengeti_cheetah_fam10&vendor=amd&num=2
Compilation of amd:tilapia_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=tilapia_fam10&vendor=amd&num=2
Compilation of arima:hdama has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=hdama&vendor=arima&num=2
Compilation of asrock:939a785gmh has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=939a785gmh&vendor=asrock&num=2
Compilation of asrock:e350m1 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=e350m1&vendor=asrock&num=2
Compilation of asus:a8n_e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=a8n_e&vendor=asus&num=2
Compilation of asus:a8v-e_deluxe has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=a8v-e_deluxe&vendor=asus&num=2
Compilation of asus:a8v-e_se has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=a8v-e_se&vendor=asus&num=2
Compilation of asus:m2n-e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=m2n-e&vendor=asus&num=2
Compilation of asus:m2v has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=m2v&vendor=asus&num=2
Compilation of asus:m2v-mx_se has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=m2v-mx_se&vendor=asus&num=2
Compilation of asus:m4a78-em has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=m4a78-em&vendor=asus&num=2
Compilation of asus:m4a785-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=m4a785-m&vendor=asus&num=2
Compilation of broadcom:blast has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=blast&vendor=broadcom&num=2
Compilation of dell:s1850 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s1850&vendor=dell&num=2
Compilation of gigabyte:ga_2761gxdk has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=ga_2761gxdk&vendor=gigabyte&num=2
Compilation of gigabyte:m57sli has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=m57sli&vendor=gigabyte&num=2
Compilation of gigabyte:ma785gmt has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=ma785gmt&vendor=gigabyte&num=2
Compilation of gigabyte:ma78gm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=ma78gm&vendor=gigabyte&num=2
Compilation of hp:dl145_g1 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=dl145_g1&vendor=hp&num=2
Compilation of intel:d945gclf has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=d945gclf&vendor=intel&num=2
Compilation of intel:jarrell has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=jarrell&vendor=intel&num=2
Compilation of intel:mtarvon has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=mtarvon&vendor=intel&num=2
Compilation of intel:truxton has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=truxton&vendor=intel&num=2
Compilation of intel:xe7501devkit has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=xe7501devkit&vendor=intel&num=2
Compilation of iwill:dk8_htx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=dk8_htx&vendor=iwill&num=2
Compilation of iwill:dk8s2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=dk8s2&vendor=iwill&num=2
Compilation of jetway:pa78vm5 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=pa78vm5&vendor=jetway&num=2
Compilation of kontron:kt690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=kt690&vendor=kontron&num=2
Compilation of lenovo:x60 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=x60&vendor=lenovo&num=2
Compilation of msi:ms7135 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=ms7135&vendor=msi&num=2
Compilation of msi:ms7260 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=ms7260&vendor=msi&num=2
Compilation of msi:ms9185 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=ms9185&vendor=msi&num=2
Compilation of msi:ms9282 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=ms9282&vendor=msi&num=2
Compilation of msi:ms9652_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=ms9652_fam10&vendor=msi&num=2
Compilation of newisys:khepri has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=khepri&vendor=newisys&num=2
Compilation of nvidia:l1_2pvv has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=l1_2pvv&vendor=nvidia&num=2
Compilation of roda:rk886ex has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=rk886ex&vendor=roda&num=2
Compilation of sunw:ultra40 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=ultra40&vendor=sunw&num=2
Compilation of supermicro:h8dme has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=h8dme&vendor=supermicro&num=2
Compilation of supermicro:h8dmr has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=h8dmr&vendor=supermicro&num=2
Compilation of supermicro:h8dmr_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=h8dmr_fam10&vendor=supermicro&num=2
Compilation of supermicro:h8qme_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=h8qme_fam10&vendor=supermicro&num=2
Compilation of supermicro:x6dai_g has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=x6dai_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=x6dhe_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=x6dhe_g2&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=x6dhr_ig&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=x6dhr_ig2&vendor=supermicro&num=2
Compilation of technexion:tim5690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=tim5690&vendor=technexion&num=2
Compilation of technexion:tim8690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=tim8690&vendor=technexion&num=2
Compilation of tyan:s2735 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2735&vendor=tyan&num=2
Compilation of tyan:s2850 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2850&vendor=tyan&num=2
Compilation of tyan:s2875 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2875&vendor=tyan&num=2
Compilation of tyan:s2880 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2880&vendor=tyan&num=2
Compilation of tyan:s2881 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2881&vendor=tyan&num=2
Compilation of tyan:s2882 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2882&vendor=tyan&num=2
Compilation of tyan:s2885 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2885&vendor=tyan&num=2
Compilation of tyan:s2891 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2891&vendor=tyan&num=2
Compilation of tyan:s2892 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2892&vendor=tyan&num=2
Compilation of tyan:s2895 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2895&vendor=tyan&num=2
Compilation of tyan:s2912 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2912&vendor=tyan&num=2
Compilation of tyan:s2912_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s2912_fam10&vendor=tyan&num=2
Compilation of tyan:s4880 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s4880&vendor=tyan&num=2
Compilation of tyan:s4882 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s4882&vendor=tyan&num=2
Compilation of via:pc2500e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=pc2500e&vendor=via&num=2
Compilation of wyse:s50 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6421&device=s50&vendor=wyse&num=2


If something broke during this checkin please be a pain 
in svens's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From stefan.reinauer at coreboot.org  Tue Mar  1 22:09:13 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 1 Mar 2011 22:09:13 +0100
Subject: [coreboot] [PATCH] outb(* 0x80) to post_code()
In-Reply-To: <4D6858EB.8050107@gmail.com>
References: <4D67BE45.70300@gmail.com> <4D67EB68.2090609@gmail.com>
	<20110225211058.GH9338@coreboot.org>
	<4D6820FE.7020108@georgi-clan.de>
	<20110225214549.GA18842@coreboot.org>
	<4D682536.7080300@georgi-clan.de>
	<20110225215939.GA28964@coreboot.org> <4D682C8B.5090707@gmail.com>
	<20110226005841.GA23938@coreboot.org> <4D6858EB.8050107@gmail.com>
Message-ID: <20110301210913.GA28067@coreboot.org>

* Alex G. <mr.nuke.me at gmail.com> [110226 02:35]:
> Index: src/include/console/post_codes.h
> ===================================================================
> --- src/include/console/post_codes.h	(revision 0)
> +++ src/include/console/post_codes.h	(revision 0)
> @@ -0,0 +1,350 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me at gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 3 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + * 
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */

Due to the GPLv2 only nature of many source code files, we can not allow
GPLv3 or even GPLv3 or later code to be committed to the repository.
Please make this GPLv2 if possible.

Stefan




From stefan.reinauer at coreboot.org  Tue Mar  1 22:14:40 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 1 Mar 2011 22:14:40 +0100
Subject: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
In-Reply-To: <20110216134309.6588.qmail@stuge.se>
References: <4D553502.50904@gmail.com>
 <20110216134309.6588.qmail@stuge.se>
Message-ID: <20110301211440.GB28067@coreboot.org>

* Peter Stuge <peter at stuge.se> [110216 14:43]:
> Alex G. wrote:
> > Extended K8T890 driver to include the K8T800 and K8M800 northbridges.
> > The K8T800 is almost identical to the K8T800Pro, also added to this
> > patch. The K8T800_OLD is also defined, which is an older  version of 
> > the K8T800, but which has no driver and early HT code yet.
> > Also extended the K8M890 VGA driver to work for the K8M800 (not tested).
> > According to the datasheet, the K8T890 and K8T800 are similar enough
> > to be able to use the same initialization code. At least for the
> > K8T800, this is sufficient to have a working HT link with the CPU, and
> > to initialise the V-Link to the southbridge.
> > 
> > Signed-off-by Alexandru Gagniuc <mr.nuke.me at gmail.com>
> 
> Acked-by: Peter Stuge <peter at stuge.se>
> 
> r6367
 
Sorry, we have to back this out again since the license of some of the
files are not compatible with the coreboot license. 
Unfortunately at this point we can not allow GPLv3 code in the
repository, as the resulting image will be GPLv2.

Can you please back this out, Peter? (Or Alexandru, send a license
update if licensing your files under GPLv2 is ok for you)

Stefan




From stefan.reinauer at coreboot.org  Tue Mar  1 22:40:10 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 1 Mar 2011 22:40:10 +0100
Subject: [coreboot] [commit] r6420 - in trunk: src/include/device
 util/sconfig
In-Reply-To: <E1PuVi3-0002zh-ND@ra.coresystems.de>
References: <E1PuVi3-0002zh-ND@ra.coresystems.de>
Message-ID: <20110301214010.GA9658@coreboot.org>

* repository service <svn at coreboot.org> [110301 20:58]:
> Author: svens
> Date: Tue Mar  1 20:58:15 2011
> New Revision: 6420
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6420
> 
> Modified: trunk/src/include/device/device.h
> ==============================================================================
> --- trunk/src/include/device/device.h	Tue Mar  1 09:09:22 2011	(r6419)
> +++ trunk/src/include/device/device.h	Tue Mar  1 20:58:15 2011	(r6420)
> @@ -64,6 +64,8 @@
>  	struct device_path path;
>  	unsigned 	vendor;
>  	unsigned 	device;
> +	u16 subsystem_vendor;
> +	u16  subsystem_device;

is that difference in white space on purpose?

Stefan



From svn at coreboot.org  Tue Mar  1 22:43:57 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 22:43:57 +0100
Subject: [coreboot] [commit] r6422 - trunk/util/sconfig
Message-ID: <E1PuXML-0006Pg-QS@ra.coresystems.de>

Author: svens
Date: Tue Mar  1 22:43:57 2011
New Revision: 6422
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6422

Log:
Add lex output

lex.yy.c_shipped wasn't committed in r6420, which breaks the build
if you don't have the expert option checked that rebuilds those files.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Sven Schnelle <svens at stackframe.org>

Modified:
   trunk/util/sconfig/lex.yy.c_shipped

Modified: trunk/util/sconfig/lex.yy.c_shipped
==============================================================================
--- trunk/util/sconfig/lex.yy.c_shipped	Tue Mar  1 20:58:47 2011	(r6421)
+++ trunk/util/sconfig/lex.yy.c_shipped	Tue Mar  1 22:43:57 2011	(r6422)
@@ -1,5 +1,5 @@
 
-#line 3 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
+#line 3 "/home/svens/coreboot/coreboot-svn/util/sconfig/lex.yy.c_shipped"
 
 #define  YY_INT_ALIGNED short int
 
@@ -368,8 +368,8 @@
 	*yy_cp = '\0'; \
 	(yy_c_buf_p) = yy_cp;
 
-#define YY_NUM_RULES 25
-#define YY_END_OF_BUFFER 26
+#define YY_NUM_RULES 27
+#define YY_END_OF_BUFFER 28
 /* This struct is not used in this scanner,
    but its presence is necessary. */
 struct yy_trans_info
@@ -377,17 +377,20 @@
 	flex_int32_t yy_verify;
 	flex_int32_t yy_nxt;
 	};
-static yyconst flex_int16_t yy_accept[87] =
+static yyconst flex_int16_t yy_accept[104] =
     {   0,
-        0,    0,   26,   24,    1,    3,   24,   24,   24,   21,
-       21,   19,   22,   22,   22,   22,   24,   24,   24,   24,
-       24,   24,    1,    3,   24,    0,   24,    0,    2,   21,
-       22,   24,   24,   22,   24,   24,   24,   17,   24,   24,
-       24,    7,   24,   24,   24,   23,   23,   20,   24,   24,
-       16,   18,   11,   15,   24,    8,    9,   10,   24,    4,
-       24,   24,   24,   24,   24,   12,   24,   24,    5,   24,
-       24,   24,   24,   24,   24,   24,   24,    6,   24,   24,
-       24,   14,   24,   24,   13,    0
+        0,    0,   28,   26,    1,    3,   26,   26,   26,   23,
+       23,   21,   24,   24,   24,   24,   26,   26,   26,   26,
+       26,   26,   26,    1,    3,   26,    0,   26,    0,    2,
+       23,   24,   26,   26,   24,   26,   26,   26,   26,   17,
+       26,   26,   26,    7,   26,   26,   26,   26,   25,   25,
+       22,   26,   26,   16,   20,   11,   26,   15,   26,    8,
+        9,   10,   26,   26,    4,   26,   26,   26,   26,   26,
+       26,   26,   26,   12,   26,   26,   26,    5,   26,   26,
+       26,   26,   26,   18,   26,   26,   26,   26,   26,   26,
+        6,   26,   26,   26,   26,   26,   14,   26,   26,   19,
+
+       26,   13,    0
     } ;
 
 static yyconst flex_int32_t yy_ec[256] =
@@ -401,11 +404,11 @@
        10,    1,    1,    1,   11,   11,   11,   11,   11,   11,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,   12,    1,   13,   11,   14,   15,
+        1,    1,    1,    1,   12,    1,   13,   14,   15,   16,
 
-       16,   17,   18,   19,   20,    1,    1,   21,   22,   23,
-       24,   25,   26,   27,   28,   29,   30,   31,    1,   32,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+       17,   18,   19,   20,   21,    1,    1,   22,   23,   24,
+       25,   26,   27,   28,   29,   30,   31,   32,    1,   33,
+       34,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
@@ -422,88 +425,96 @@
         1,    1,    1,    1,    1
     } ;
 
-static yyconst flex_int32_t yy_meta[33] =
+static yyconst flex_int32_t yy_meta[35] =
     {   0,
         1,    2,    2,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1
+        1,    1,    1,    1
     } ;
 
-static yyconst flex_int16_t yy_base[92] =
+static yyconst flex_int16_t yy_base[109] =
     {   0,
-        0,    0,  144,    0,  141,  145,  139,   31,   35,   32,
-      109,    0,   43,   46,   59,   49,   35,  127,   46,   47,
-      123,    0,  136,  145,   71,  132,   75,  133,  145,    0,
-       72,   80,  115,   75,  108,  118,  118,    0,  105,  105,
-      112,    0,  108,  102,  108,    0,  145,    0,  100,  104,
-        0,    0,    0,    0,  103,    0,  110,    0,  101,    0,
-      106,  105,  103,   89,  100,  103,   81,   75,    0,   89,
-       80,   85,   79,   86,   71,   62,   70,    0,   57,   48,
-       35,    0,   44,   15,    0,  145,   34,  106,  108,  110,
-      112
+        0,    0,  164,    0,  161,  165,  159,   33,   37,   34,
+      128,    0,   46,   49,   53,   56,   50,  147,   48,   22,
+      142,  127,    0,  155,  165,   74,  151,   65,  152,  165,
+        0,   75,   78,  133,   90,  126,  136,  136,  130,    0,
+      122,  122,  129,    0,  125,  119,  125,  129,    0,  165,
+        0,  116,  120,    0,    0,    0,  123,    0,  118,    0,
+      126,    0,  116,  107,    0,  120,  106,  118,  116,  102,
+       87,  103,   98,  106,   92,   86,   86,    0,   84,   98,
+       89,   94,   80,    0,   87,   95,   79,   89,   74,   83,
+        0,   80,   73,   77,   79,   60,    0,   72,   56,    0,
 
+       43,    0,  165,   43,  122,  124,  126,  128
     } ;
 
-static yyconst flex_int16_t yy_def[92] =
+static yyconst flex_int16_t yy_def[109] =
     {   0,
-       86,    1,   86,   87,   86,   86,   87,   88,   89,   87,
-       10,   87,   10,   10,   10,   10,   87,   87,   87,   87,
-       87,   87,   86,   86,   88,   90,   89,   91,   86,   10,
-       10,   10,   87,   10,   87,   87,   87,   87,   87,   87,
-       87,   87,   87,   87,   87,   87,   86,   32,   87,   87,
-       87,   87,   87,   87,   87,   87,   87,   87,   87,   87,
-       87,   87,   87,   87,   87,   87,   87,   87,   87,   87,
-       87,   87,   87,   87,   87,   87,   87,   87,   87,   87,
-       87,   87,   87,   87,   87,    0,   86,   86,   86,   86,
-       86
+      103,    1,  103,  104,  103,  103,  104,  105,  106,  104,
+       10,  104,   10,   10,   10,   10,  104,  104,  104,  104,
+      104,  104,  104,  103,  103,  105,  107,  106,  108,  103,
+       10,   10,   10,  104,   10,  104,  104,  104,  104,  104,
+      104,  104,  104,  104,  104,  104,  104,  104,  104,  103,
+       33,  104,  104,  104,  104,  104,  104,  104,  104,  104,
+      104,  104,  104,  104,  104,  104,  104,  104,  104,  104,
+      104,  104,  104,  104,  104,  104,  104,  104,  104,  104,
+      104,  104,  104,  104,  104,  104,  104,  104,  104,  104,
+      104,  104,  104,  104,  104,  104,  104,  104,  104,  104,
 
+      104,  104,    0,  103,  103,  103,  103,  103
     } ;
 
-static yyconst flex_int16_t yy_nxt[178] =
+static yyconst flex_int16_t yy_nxt[200] =
     {   0,
         4,    5,    6,    7,    8,    9,   10,   11,   10,   12,
-       13,    4,   13,   14,   15,   16,   13,    4,    4,   17,
-       18,    4,    4,   19,   20,    4,   21,    4,    4,    4,
-        4,    4,   26,   26,   22,   22,   28,   29,   30,   30,
-       30,   85,   31,   37,   31,   31,   31,   31,   31,   31,
-       31,   31,   31,   31,   31,   31,   31,   31,   38,   84,
-       43,   39,   41,   83,   33,   31,   31,   31,   42,   44,
-       82,   36,   26,   26,   34,   46,   28,   29,   31,   31,
-       31,   31,   31,   31,   81,   35,   48,   48,   48,   80,
-       48,   79,   48,   48,   48,   48,   48,   78,   77,   76,
-
-       75,   74,   73,   72,   71,   50,   25,   25,   27,   27,
-       26,   26,   28,   28,   70,   69,   68,   67,   66,   65,
-       64,   63,   62,   61,   60,   59,   58,   57,   56,   55,
-       54,   53,   52,   51,   49,   29,   47,   23,   45,   40,
-       32,   24,   23,   86,    3,   86,   86,   86,   86,   86,
-       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,
-       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,
-       86,   86,   86,   86,   86,   86,   86
+       13,    4,   13,   13,   14,   15,   16,   13,    4,    4,
+       17,   18,    4,    4,   19,   20,    4,   21,   22,    4,
+        4,    4,    4,    4,   27,   27,   45,   23,   29,   30,
+       31,   31,   31,   23,   32,   46,   32,   32,   32,   32,
+       32,   32,   32,   32,   32,   32,   32,   32,   38,   32,
+       32,   32,   32,   32,   32,   43,   29,   30,   34,   35,
+      102,   44,  101,   39,   40,   27,   27,   41,   49,   37,
+       36,   32,   32,   32,   51,   51,   51,  100,   51,   99,
+       51,   51,   51,   51,   51,   51,   32,   32,   32,   98,
+
+       97,   96,   95,   94,   93,   92,   91,   90,   89,   88,
+       87,   86,   85,   84,   83,   82,   81,   80,   79,   78,
+       77,   53,   26,   26,   28,   28,   27,   27,   29,   29,
+       76,   75,   74,   73,   72,   71,   70,   69,   68,   67,
+       66,   65,   64,   63,   62,   61,   60,   59,   58,   57,
+       56,   55,   54,   52,   30,   50,   24,   48,   47,   42,
+       33,   25,   24,  103,    3,  103,  103,  103,  103,  103,
+      103,  103,  103,  103,  103,  103,  103,  103,  103,  103,
+      103,  103,  103,  103,  103,  103,  103,  103,  103,  103,
+      103,  103,  103,  103,  103,  103,  103,  103,  103
+
     } ;
 
-static yyconst flex_int16_t yy_chk[178] =
+static yyconst flex_int16_t yy_chk[200] =
     {   0,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    8,    8,   87,    8,    9,    9,   10,   10,
-       10,   84,   10,   17,   10,   10,   10,   10,   10,   13,
-       13,   13,   14,   14,   14,   16,   16,   16,   17,   83,
-       20,   17,   19,   81,   14,   15,   15,   15,   19,   20,
-       80,   16,   25,   25,   15,   25,   27,   27,   31,   31,
-       31,   34,   34,   34,   79,   15,   32,   32,   32,   77,
-       32,   76,   32,   32,   32,   32,   32,   75,   74,   73,
-
-       72,   71,   70,   68,   67,   34,   88,   88,   89,   89,
-       90,   90,   91,   91,   66,   65,   64,   63,   62,   61,
-       59,   57,   55,   50,   49,   45,   44,   43,   41,   40,
-       39,   37,   36,   35,   33,   28,   26,   23,   21,   18,
-       11,    7,    5,    3,   86,   86,   86,   86,   86,   86,
-       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,
-       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,
-       86,   86,   86,   86,   86,   86,   86
+        1,    1,    1,    1,    8,    8,   20,    8,    9,    9,
+       10,   10,   10,  104,   10,   20,   10,   10,   10,   10,
+       10,   10,   13,   13,   13,   14,   14,   14,   17,   15,
+       15,   15,   16,   16,   16,   19,   28,   28,   14,   15,
+      101,   19,   99,   17,   17,   26,   26,   17,   26,   16,
+       15,   32,   32,   32,   33,   33,   33,   98,   33,   96,
+       33,   33,   33,   33,   33,   33,   35,   35,   35,   95,
+
+       94,   93,   92,   90,   89,   88,   87,   86,   85,   83,
+       82,   81,   80,   79,   77,   76,   75,   74,   73,   72,
+       71,   35,  105,  105,  106,  106,  107,  107,  108,  108,
+       70,   69,   68,   67,   66,   64,   63,   61,   59,   57,
+       53,   52,   48,   47,   46,   45,   43,   42,   41,   39,
+       38,   37,   36,   34,   29,   27,   24,   22,   21,   18,
+       11,    7,    5,    3,  103,  103,  103,  103,  103,  103,
+      103,  103,  103,  103,  103,  103,  103,  103,  103,  103,
+      103,  103,  103,  103,  103,  103,  103,  103,  103,  103,
+      103,  103,  103,  103,  103,  103,  103,  103,  103
+
     } ;
 
 static yy_state_type yy_last_accepting_state;
@@ -780,13 +791,13 @@
 			while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
 				{
 				yy_current_state = (int) yy_def[yy_current_state];
-				if ( yy_current_state >= 87 )
+				if ( yy_current_state >= 104 )
 					yy_c = yy_meta[(unsigned int) yy_c];
 				}
 			yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
 			++yy_cp;
 			}
-		while ( yy_base[yy_current_state] != 145 );
+		while ( yy_base[yy_current_state] != 165 );
 
 yy_find_action:
 		yy_act = yy_accept[yy_current_state];
@@ -882,34 +893,42 @@
 	YY_BREAK
 case 18:
 YY_RULE_SETUP
-{return(END);}
+{return(INHERIT);}
 	YY_BREAK
 case 19:
 YY_RULE_SETUP
-{return(EQUALS);}
+{return(SUBSYSTEMID);}
 	YY_BREAK
 case 20:
 YY_RULE_SETUP
-{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
+{return(END);}
 	YY_BREAK
 case 21:
 YY_RULE_SETUP
-{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
+{return(EQUALS);}
 	YY_BREAK
 case 22:
 YY_RULE_SETUP
 {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
 	YY_BREAK
 case 23:
-/* rule 23 can match eol */
 YY_RULE_SETUP
-{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);}
+{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
 	YY_BREAK
 case 24:
 YY_RULE_SETUP
-{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);}
+{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
 	YY_BREAK
 case 25:
+/* rule 25 can match eol */
+YY_RULE_SETUP
+{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);}
+	YY_BREAK
+case 26:
+YY_RULE_SETUP
+{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);}
+	YY_BREAK
+case 27:
 YY_RULE_SETUP
 ECHO;
 	YY_BREAK
@@ -1204,7 +1223,7 @@
 		while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
 			{
 			yy_current_state = (int) yy_def[yy_current_state];
-			if ( yy_current_state >= 87 )
+			if ( yy_current_state >= 104 )
 				yy_c = yy_meta[(unsigned int) yy_c];
 			}
 		yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
@@ -1232,11 +1251,11 @@
 	while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
 		{
 		yy_current_state = (int) yy_def[yy_current_state];
-		if ( yy_current_state >= 87 )
+		if ( yy_current_state >= 104 )
 			yy_c = yy_meta[(unsigned int) yy_c];
 		}
 	yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-	yy_is_jam = (yy_current_state == 86);
+	yy_is_jam = (yy_current_state == 103);
 
 	return yy_is_jam ? 0 : yy_current_state;
 }



From svn at coreboot.org  Tue Mar  1 22:51:29 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 22:51:29 +0100
Subject: [coreboot] [commit] r6423 - trunk/src/include/device
Message-ID: <E1PuXTd-0000pe-Ug@ra.coresystems.de>

Author: svens
Date: Tue Mar  1 22:51:29 2011
New Revision: 6423
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6423

Log:
Fix a simple whitespace error in src/include/device/device.h

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Sven Schnelle <svens at stackframe.org>
Reported-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/src/include/device/device.h

Modified: trunk/src/include/device/device.h
==============================================================================
--- trunk/src/include/device/device.h	Tue Mar  1 22:43:57 2011	(r6422)
+++ trunk/src/include/device/device.h	Tue Mar  1 22:51:29 2011	(r6423)
@@ -64,8 +64,8 @@
 	struct device_path path;
 	unsigned 	vendor;
 	unsigned 	device;
-	u16 subsystem_vendor;
-	u16  subsystem_device;
+	u16		subsystem_vendor;
+	u16		subsystem_device;
 	unsigned int	class;		/* 3 bytes: (base, sub, prog-if) */
 	unsigned int	hdr_type;	/* PCI header type */
 	unsigned int    enabled : 1;	/* set if we should enable the device */



From svens at stackframe.org  Tue Mar  1 22:52:11 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Mar 2011 22:52:11 +0100
Subject: [coreboot] [commit] r6420 - in trunk: src/include/device
	util/sconfig
In-Reply-To: <20110301214010.GA9658@coreboot.org> (Stefan Reinauer's message
	of "Tue, 1 Mar 2011 22:40:10 +0100")
References: <E1PuVi3-0002zh-ND@ra.coresystems.de>
	<20110301214010.GA9658@coreboot.org>
Message-ID: <86zkpezeyc.fsf@stackframe.org>

Stefan Reinauer <stefan.reinauer at coreboot.org> writes:

> * repository service <svn at coreboot.org> [110301 20:58]:
>> Author: svens
>> Date: Tue Mar  1 20:58:15 2011
>> New Revision: 6420
>> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6420
>> 
>> Modified: trunk/src/include/device/device.h
>> ==============================================================================
>> --- trunk/src/include/device/device.h	Tue Mar  1 09:09:22 2011	(r6419)
>> +++ trunk/src/include/device/device.h	Tue Mar  1 20:58:15 2011	(r6420)
>> @@ -64,6 +64,8 @@
>>  	struct device_path path;
>>  	unsigned 	vendor;
>>  	unsigned 	device;
>> +	u16 subsystem_vendor;
>> +	u16  subsystem_device;
>
> is that difference in white space on purpose?

No, fixed in r6423.

Thanks,

Sven.



From sylvain.hitier at gmail.com  Tue Mar  1 22:18:49 2011
From: sylvain.hitier at gmail.com (Sylvain 'ythier' Hitier)
Date: Tue, 1 Mar 2011 22:18:49 +0100
Subject: [coreboot] [PATCH] r6420-remove-unused-var.patch
Message-ID: <20110301211849.GA15194@begonia>

(Please keep me in CC, I'm not subscribed to the list)

After reading r6420.

Index: util/sconfig/main.c
===================================================================
--- util/sconfig/main.c	(revision 6421)
+++ util/sconfig/main.c	(working copy)
@@ -415,14 +415,13 @@
 static void inherit_subsystem_ids(FILE *file, struct device *dev)
 {
 	struct device *p;
-	int i =0;
 
 	if (dev->subsystem_vendor != -1 && dev->subsystem_device != -1) {
 		/* user already gave us a subsystem vendor/device */
 		return;
 	}
 
-	for(p = dev; p && p != p->parent; (p = p->parent), i++) {
+	for(p = dev; p && p != p->parent; p = p->parent) {
 
 		if (p->bustype != PCI && p->bustype != PCI_DOMAIN)
 			continue;

Regards,
Sylvain "ythier" Hitier

-- 
Free hugs for Free Software Fellows!
Living in a Debian package => http://en.wikipedia.org/wiki/Apt,_Vaucluse



From sylvain.hitier at gmail.com  Tue Mar  1 22:20:36 2011
From: sylvain.hitier at gmail.com (Sylvain 'ythier' Hitier)
Date: Tue, 1 Mar 2011 22:20:36 +0100
Subject: [coreboot] [PATCH] r6421-correct-ids.patch
Message-ID: <20110301212036.GB15194@begonia>

(Please keep me in CC, I'm not subscribed to the list)

After reading r6421.

Index: src/mainboard/asus/m2v/devicetree.cb
===================================================================
--- src/mainboard/asus/m2v/devicetree.cb	(revision 6421)
+++ src/mainboard/asus/m2v/devicetree.cb	(working copy)
@@ -5,7 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
-    subsystemid 0x143 0 inherit
+    subsystemid 0x1043 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0
Index: src/mainboard/gigabyte/ma78gm/devicetree.cb
===================================================================
--- src/mainboard/gigabyte/ma78gm/devicetree.cb	(revision 6421)
+++ src/mainboard/gigabyte/ma78gm/devicetree.cb	(working copy)
@@ -6,7 +6,7 @@
 		end
 	end
 	device pci_domain 0 on
-		subsystemid 0x3060 0x1022 inherit
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
Index: src/mainboard/roda/rk886ex/devicetree.cb
===================================================================
--- src/mainboard/roda/rk886ex/devicetree.cb	(revision 6421)
+++ src/mainboard/roda/rk886ex/devicetree.cb	(working copy)
@@ -28,7 +28,7 @@
         end
 
         device pci_domain 0 on
-                subsystemid 0x4352 0x0686 inherit
+                subsystemid 0x4352 0x6886 inherit
                 device pci 00.0 on end # host bridge
 		# auto detection:
 		#device pci 01.0 off end # i945 PCIe root port

Regards,
Sylvain "ythier" Hitier

-- 
Free hugs for Free Software Fellows!
Living in a Debian package => http://en.wikipedia.org/wiki/Apt,_Vaucluse



From sylvain.hitier at gmail.com  Tue Mar  1 22:46:19 2011
From: sylvain.hitier at gmail.com (Sylvain 'ythier' Hitier)
Date: Tue, 1 Mar 2011 22:46:19 +0100
Subject: [coreboot] [PATCH] r6420-remove-unused-var.patch
In-Reply-To: <20110301211849.GA15194@begonia>
References: <20110301211849.GA15194@begonia>
Message-ID: <20110301214619.GC15194@begonia>

(Please keep me in CC, I'm not subscribed to the list)

After reading r6420.

Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier at gmail.com>

Index: util/sconfig/main.c
===================================================================
--- util/sconfig/main.c	(revision 6421)
+++ util/sconfig/main.c	(working copy)
@@ -415,14 +415,13 @@
 static void inherit_subsystem_ids(FILE *file, struct device *dev)
 {
 	struct device *p;
-	int i =0;
 
 	if (dev->subsystem_vendor != -1 && dev->subsystem_device != -1) {
 		/* user already gave us a subsystem vendor/device */
 		return;
 	}
 
-	for(p = dev; p && p != p->parent; (p = p->parent), i++) {
+	for(p = dev; p && p != p->parent; p = p->parent) {
 
 		if (p->bustype != PCI && p->bustype != PCI_DOMAIN)
 			continue;

Regards,
Sylvain "ythier" Hitier

-- 
Free hugs for Free Software Fellows!
Living in a Debian package => http://en.wikipedia.org/wiki/Apt,_Vaucluse



From sylvain.hitier at gmail.com  Tue Mar  1 22:47:33 2011
From: sylvain.hitier at gmail.com (Sylvain 'ythier' Hitier)
Date: Tue, 1 Mar 2011 22:47:33 +0100
Subject: [coreboot] [PATCH] r6421-correct-ids.patch
In-Reply-To: <20110301212036.GB15194@begonia>
References: <20110301212036.GB15194@begonia>
Message-ID: <20110301214733.GD15194@begonia>

(Please keep me in CC, I'm not subscribed to the list)

After reading r6421.

Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier at gmail.com>

Index: src/mainboard/asus/m2v/devicetree.cb
===================================================================
--- src/mainboard/asus/m2v/devicetree.cb	(revision 6421)
+++ src/mainboard/asus/m2v/devicetree.cb	(working copy)
@@ -5,7 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
-    subsystemid 0x143 0 inherit
+    subsystemid 0x1043 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0
Index: src/mainboard/gigabyte/ma78gm/devicetree.cb
===================================================================
--- src/mainboard/gigabyte/ma78gm/devicetree.cb	(revision 6421)
+++ src/mainboard/gigabyte/ma78gm/devicetree.cb	(working copy)
@@ -6,7 +6,7 @@
 		end
 	end
 	device pci_domain 0 on
-		subsystemid 0x3060 0x1022 inherit
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
Index: src/mainboard/roda/rk886ex/devicetree.cb
===================================================================
--- src/mainboard/roda/rk886ex/devicetree.cb	(revision 6421)
+++ src/mainboard/roda/rk886ex/devicetree.cb	(working copy)
@@ -28,7 +28,7 @@
         end
 
         device pci_domain 0 on
-                subsystemid 0x4352 0x0686 inherit
+                subsystemid 0x4352 0x6886 inherit
                 device pci 00.0 on end # host bridge
 		# auto detection:
 		#device pci 01.0 off end # i945 PCIe root port

Regards,
Sylvain "ythier" Hitier

-- 
Free hugs for Free Software Fellows!
Living in a Debian package => http://en.wikipedia.org/wiki/Apt,_Vaucluse



From svn at coreboot.org  Tue Mar  1 22:57:11 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 22:57:11 +0100
Subject: [coreboot] [commit] r6424 - trunk/util/sconfig
Message-ID: <E1PuXZ9-0001VO-M2@ra.coresystems.de>

Author: svens
Date: Tue Mar  1 22:57:11 2011
New Revision: 6424
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6424

Log:
[SCONFIG] remove unused variable in inherit_subsystem_ids()

i is a leftover from debugging, no longer needed. So just remove it.

Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier at gmail.com>
Acked-by: Sven Schnelle <svens at stackframe.org>

Modified:
   trunk/util/sconfig/main.c

Modified: trunk/util/sconfig/main.c
==============================================================================
--- trunk/util/sconfig/main.c	Tue Mar  1 22:51:29 2011	(r6423)
+++ trunk/util/sconfig/main.c	Tue Mar  1 22:57:11 2011	(r6424)
@@ -415,14 +415,13 @@
 static void inherit_subsystem_ids(FILE *file, struct device *dev)
 {
 	struct device *p;
-	int i =0;
 
 	if (dev->subsystem_vendor != -1 && dev->subsystem_device != -1) {
 		/* user already gave us a subsystem vendor/device */
 		return;
 	}
 
-	for(p = dev; p && p != p->parent; (p = p->parent), i++) {
+	for(p = dev; p && p != p->parent; p = p->parent) {
 
 		if (p->bustype != PCI && p->bustype != PCI_DOMAIN)
 			continue;



From svens at stackframe.org  Tue Mar  1 22:57:52 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Mar 2011 22:57:52 +0100
Subject: [coreboot] [PATCH] r6420-remove-unused-var.patch
In-Reply-To: <20110301214619.GC15194@begonia> (Sylvain Hitier's message of
	"Tue, 1 Mar 2011 22:46:19 +0100")
References: <20110301211849.GA15194@begonia> <20110301214619.GC15194@begonia>
Message-ID: <86r5aqzeov.fsf@stackframe.org>

Sylvain 'ythier' Hitier <sylvain.hitier at gmail.com> writes:

> (Please keep me in CC, I'm not subscribed to the list)
>
> After reading r6420.
>
> Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier at gmail.com>
>
> Index: util/sconfig/main.c
> ===================================================================
> --- util/sconfig/main.c	(revision 6421)
> +++ util/sconfig/main.c	(working copy)
> @@ -415,14 +415,13 @@
>  static void inherit_subsystem_ids(FILE *file, struct device *dev)
>  {
>  	struct device *p;
> -	int i =0;
>  
>  	if (dev->subsystem_vendor != -1 && dev->subsystem_device != -1) {
>  		/* user already gave us a subsystem vendor/device */
>  		return;
>  	}
>  
> -	for(p = dev; p && p != p->parent; (p = p->parent), i++) {
> +	for(p = dev; p && p != p->parent; p = p->parent) {
>  
>  		if (p->bustype != PCI && p->bustype != PCI_DOMAIN)
>  			continue;
>
> Regards,
> Sylvain "ythier" Hitier

r6424.

Thanks,

Sven.



From svn at coreboot.org  Tue Mar  1 23:02:38 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 23:02:38 +0100
Subject: [coreboot] [commit] r6425 - in trunk/src/mainboard: asus/m2v
	gigabyte/ma78gm roda/rk886ex
Message-ID: <E1PuXeQ-0001Et-If@ra.coresystems.de>

Author: svens
Date: Tue Mar  1 23:02:37 2011
New Revision: 6425
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6425

Log:
Fix some subsystemid statements in r6421

Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier at gmail.com>
Acked-by: Sven Schnelle <svens at stackframe.org>

Modified:
   trunk/src/mainboard/asus/m2v/devicetree.cb
   trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb
   trunk/src/mainboard/roda/rk886ex/devicetree.cb

Modified: trunk/src/mainboard/asus/m2v/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/m2v/devicetree.cb	Tue Mar  1 22:57:11 2011	(r6424)
+++ trunk/src/mainboard/asus/m2v/devicetree.cb	Tue Mar  1 23:02:37 2011	(r6425)
@@ -5,7 +5,7 @@
     end
   end
   device pci_domain 0 on			# PCI domain
-    subsystemid 0x143 0 inherit
+    subsystemid 0x1043 0 inherit
     chip northbridge/amd/amdk8			# mc0
       device pci 18.0 on			# Northbridge
         # Devices on link 0, link 0 == LDT 0

Modified: trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb	Tue Mar  1 22:57:11 2011	(r6424)
+++ trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb	Tue Mar  1 23:02:37 2011	(r6425)
@@ -6,7 +6,7 @@
 		end
 	end
 	device pci_domain 0 on
-		subsystemid 0x3060 0x1022 inherit
+		subsystemid 0x1022 0x3060 inherit
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780

Modified: trunk/src/mainboard/roda/rk886ex/devicetree.cb
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/devicetree.cb	Tue Mar  1 22:57:11 2011	(r6424)
+++ trunk/src/mainboard/roda/rk886ex/devicetree.cb	Tue Mar  1 23:02:37 2011	(r6425)
@@ -28,7 +28,7 @@
         end
 
         device pci_domain 0 on
-                subsystemid 0x4352 0x0686 inherit
+                subsystemid 0x4352 0x6886 inherit
                 device pci 00.0 on end # host bridge
 		# auto detection:
 		#device pci 01.0 off end # i945 PCIe root port



From svens at stackframe.org  Tue Mar  1 23:03:49 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 01 Mar 2011 23:03:49 +0100
Subject: [coreboot] [PATCH] r6421-correct-ids.patch
In-Reply-To: <20110301214733.GD15194@begonia> (Sylvain Hitier's message of
	"Tue, 1 Mar 2011 22:47:33 +0100")
References: <20110301212036.GB15194@begonia> <20110301214733.GD15194@begonia>
Message-ID: <86lj0yzeey.fsf@stackframe.org>

Sylvain 'ythier' Hitier <sylvain.hitier at gmail.com> writes:

> (Please keep me in CC, I'm not subscribed to the list)
>
> After reading r6421.
>
> Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier at gmail.com>
>
> Index: src/mainboard/asus/m2v/devicetree.cb
> ===================================================================
> --- src/mainboard/asus/m2v/devicetree.cb	(revision 6421)
> +++ src/mainboard/asus/m2v/devicetree.cb	(working copy)
> @@ -5,7 +5,7 @@
>      end
>    end
>    device pci_domain 0 on			# PCI domain
> -    subsystemid 0x143 0 inherit
> +    subsystemid 0x1043 0 inherit
>      chip northbridge/amd/amdk8			# mc0
>        device pci 18.0 on			# Northbridge
>          # Devices on link 0, link 0 == LDT 0
> Index: src/mainboard/gigabyte/ma78gm/devicetree.cb
> ===================================================================
> --- src/mainboard/gigabyte/ma78gm/devicetree.cb	(revision 6421)
> +++ src/mainboard/gigabyte/ma78gm/devicetree.cb	(working copy)
> @@ -6,7 +6,7 @@
>  		end
>  	end
>  	device pci_domain 0 on
> -		subsystemid 0x3060 0x1022 inherit
> +		subsystemid 0x1022 0x3060 inherit
>  		chip northbridge/amd/amdfam10
>  			device pci 18.0 on #  northbridge
>  				chip southbridge/amd/rs780
> Index: src/mainboard/roda/rk886ex/devicetree.cb
> ===================================================================
> --- src/mainboard/roda/rk886ex/devicetree.cb	(revision 6421)
> +++ src/mainboard/roda/rk886ex/devicetree.cb	(working copy)
> @@ -28,7 +28,7 @@
>          end
>  
>          device pci_domain 0 on
> -                subsystemid 0x4352 0x0686 inherit
> +                subsystemid 0x4352 0x6886 inherit
>                  device pci 00.0 on end # host bridge
>  		# auto detection:
>  		#device pci 01.0 off end # i945 PCIe root port
>
> Regards,
> Sylvain "ythier" Hitier
>
> -- 
> Free hugs for Free Software Fellows!
> Living in a Debian package => http://en.wikipedia.org/wiki/Apt,_Vaucluse

r6425.

Thanks,

Sven.



From svn at coreboot.org  Tue Mar  1 23:13:36 2011
From: svn at coreboot.org (repository service)
Date: Tue, 01 Mar 2011 23:13:36 +0100
Subject: [coreboot] build service results for r6422
Message-ID: <E1PuXp2-0001vc-V2@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "svens" checked in revision 6422 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add lex output

lex.yy.c_shipped wasn't committed in r6420, which breaks the build
if you don't have the expert option checked that rebuilds those files.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Sven Schnelle <svens at stackframe.org>



Build Log:
Compilation of amd:bimini_fam10 has been fixed
Compilation of amd:dbm690t has been fixed
Compilation of amd:inagua has been fixed
Compilation of amd:mahogany has been fixed
Compilation of amd:mahogany_fam10 has been fixed
Compilation of amd:persimmon has been fixed
Compilation of amd:pistachio has been fixed
Compilation of amd:serengeti_cheetah has been fixed
Compilation of amd:serengeti_cheetah_fam10 has been fixed
Compilation of amd:tilapia_fam10 has been fixed
Compilation of arima:hdama has been fixed
Compilation of asrock:939a785gmh has been fixed
Compilation of asrock:e350m1 has been fixed
Compilation of asus:a8n_e has been fixed
Compilation of asus:a8v-e_deluxe has been fixed
Compilation of asus:a8v-e_se has been fixed
Compilation of asus:m2n-e has been fixed
Compilation of asus:m2v has been fixed
Compilation of asus:m2v-mx_se has been fixed
Compilation of asus:m4a78-em has been fixed
Compilation of asus:m4a785-m has been fixed
Compilation of broadcom:blast has been fixed
Compilation of dell:s1850 has been fixed
Compilation of gigabyte:ga_2761gxdk has been fixed
Compilation of gigabyte:m57sli has been fixed
Compilation of gigabyte:ma785gmt has been fixed
Compilation of gigabyte:ma78gm has been fixed
Compilation of hp:dl145_g1 has been fixed
Compilation of intel:d945gclf has been fixed
Compilation of intel:jarrell has been fixed
Compilation of intel:mtarvon has been fixed
Compilation of intel:truxton has been fixed
Compilation of intel:xe7501devkit has been fixed
Compilation of iwill:dk8_htx has been fixed
Compilation of iwill:dk8s2 has been fixed
Compilation of jetway:pa78vm5 has been fixed
Compilation of kontron:kt690 has been fixed
Compilation of lenovo:x60 has been fixed
Compilation of msi:ms7135 has been fixed
Compilation of msi:ms7260 has been fixed
Compilation of msi:ms9185 has been fixed
Compilation of msi:ms9282 has been fixed
Compilation of msi:ms9652_fam10 has been fixed
Compilation of newisys:khepri has been fixed
Compilation of nvidia:l1_2pvv has been fixed
Compilation of roda:rk886ex has been fixed
Compilation of sunw:ultra40 has been fixed
Compilation of supermicro:h8dme has been fixed
Compilation of supermicro:h8dmr has been fixed
Compilation of supermicro:h8dmr_fam10 has been fixed
Compilation of supermicro:h8qme_fam10 has been fixed
Compilation of supermicro:x6dai_g has been fixed
Compilation of supermicro:x6dhe_g has been fixed
Compilation of supermicro:x6dhe_g2 has been fixed
Compilation of supermicro:x6dhr_ig has been fixed
Compilation of supermicro:x6dhr_ig2 has been fixed
Compilation of technexion:tim5690 has been fixed
Compilation of technexion:tim8690 has been fixed
Compilation of tyan:s2735 has been fixed
Compilation of tyan:s2850 has been fixed
Compilation of tyan:s2875 has been fixed
Compilation of tyan:s2880 has been fixed
Compilation of tyan:s2881 has been fixed
Compilation of tyan:s2882 has been fixed
Compilation of tyan:s2885 has been fixed
Compilation of tyan:s2891 has been fixed
Compilation of tyan:s2892 has been fixed
Compilation of tyan:s2895 has been fixed
Compilation of tyan:s2912 has been fixed
Compilation of tyan:s2912_fam10 has been fixed
Compilation of tyan:s4880 has been fixed
Compilation of tyan:s4882 has been fixed
Compilation of via:pc2500e has been fixed
Compilation of wyse:s50 has been fixed


If something broke during this checkin please be a pain 
in svens's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From joe at settoplinux.org  Wed Mar  2 00:39:05 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 01 Mar 2011 18:39:05 -0500
Subject: [coreboot] #178: Life Insurance - How To Buy Life Insurance
	Policies
In-Reply-To: <045.bc210f8e81ae23679af903f14ee706f6@coreboot.org>
References: <045.bc210f8e81ae23679af903f14ee706f6@coreboot.org>
Message-ID: <4D6D8399.7090706@settoplinux.org>

On 03/01/2011 02:24 PM, coreboot wrote:
> #178: Life Insurance - How To Buy Life Insurance Policies
> -------------------------------------+-------------------------------------
>      Reporter:  anonymous             |         Owner:
>          Type:  enhancement           |  c-d.hailfinger.devel.2006@?
>      Priority:  major                 |        Status:  new
>     Component:  flashrom (please use  |     Milestone:  flashrom v1.1
>    trac on flashrom.org)              |      Keywords:  life insurance
> Dependencies:                        |  Patch Status:  patch needs review
> -------------------------------------+-------------------------------------
>   [[Image(http://www.johnkatsouris.co.uk/images/family_park.jpg)]]
>
>   Buying such services like '''[http://www.lifeinsurance.net.au/ life
>   insurance]''' in making things better for those people to have its best
>   ways that will be better for them during this days. It can make things
>   better for those people to have its best ways to satisfy their needs in
>   life living in this world. This '''insurances''' people can have the
>   things they need in life living in this world. Having such services that
>   will make things better for them having the best services that will make
>   them have a '''Life Insurance''' in making things better for them during
>   this days.
>
>   [[Image(http://onlinearnings.com/wp-content/uploads/2009/07/happy-life-
>   insurance.jpg)]]
>
>   It can make things better for those people having such
>   '''[http://www.lifeinsurance.net.au/ life insurance]''' in a certain
>   period of time. It is best for those people to have such ways that can be
>   better for those people on having the things that will make them have such
>   '''Living Insurance''' in a certain period of time that will make those
>   people have its best ways in living.
>
coreboot is selling life insurance now?
Is this in case of electro static discharge?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From joe at settoplinux.org  Wed Mar  2 00:40:25 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 01 Mar 2011 18:40:25 -0500
Subject: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
In-Reply-To: <20110301211440.GB28067@coreboot.org>
References: <4D553502.50904@gmail.com> <20110216134309.6588.qmail@stuge.se>
	<20110301211440.GB28067@coreboot.org>
Message-ID: <4D6D83E9.4080400@settoplinux.org>

On 03/01/2011 04:14 PM, Stefan Reinauer wrote:
> * Peter Stuge<peter at stuge.se>  [110216 14:43]:
>> Alex G. wrote:
>>> Extended K8T890 driver to include the K8T800 and K8M800 northbridges.
>>> The K8T800 is almost identical to the K8T800Pro, also added to this
>>> patch. The K8T800_OLD is also defined, which is an older  version of
>>> the K8T800, but which has no driver and early HT code yet.
>>> Also extended the K8M890 VGA driver to work for the K8M800 (not tested).
>>> According to the datasheet, the K8T890 and K8T800 are similar enough
>>> to be able to use the same initialization code. At least for the
>>> K8T800, this is sufficient to have a working HT link with the CPU, and
>>> to initialise the V-Link to the southbridge.
>>>
>>> Signed-off-by Alexandru Gagniuc<mr.nuke.me at gmail.com>
>>
>> Acked-by: Peter Stuge<peter at stuge.se>
>>
>> r6367
>
> Sorry, we have to back this out again since the license of some of the
> files are not compatible with the coreboot license.
> Unfortunately at this point we can not allow GPLv3 code in the
> repository, as the resulting image will be GPLv2.
>
> Can you please back this out, Peter? (Or Alexandru, send a license
> update if licensing your files under GPLv2 is ok for you)
>
> Stefan
>
>
Wow! That is a big no, no.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From c-d.hailfinger.devel.2006 at gmx.net  Wed Mar  2 01:05:38 2011
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 02 Mar 2011 01:05:38 +0100
Subject: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
In-Reply-To: <4D6D83E9.4080400@settoplinux.org>
References: <4D553502.50904@gmail.com>
	<20110216134309.6588.qmail@stuge.se>	<20110301211440.GB28067@coreboot.org>
	<4D6D83E9.4080400@settoplinux.org>
Message-ID: <4D6D89D2.9070304@gmx.net>

Auf 02.03.2011 00:40, Joseph Smith schrieb:
> On 03/01/2011 04:14 PM, Stefan Reinauer wrote:
>> * Peter Stuge<peter at stuge.se>  [110216 14:43]:
>>> Alex G. wrote:
>>>> Extended K8T890 driver to include the K8T800 and K8M800 northbridges.
>>>> The K8T800 is almost identical to the K8T800Pro, also added to this
>>>> patch. The K8T800_OLD is also defined, which is an older  version of
>>>> the K8T800, but which has no driver and early HT code yet.
>>>> Also extended the K8M890 VGA driver to work for the K8M800 (not
>>>> tested).
>>>> According to the datasheet, the K8T890 and K8T800 are similar enough
>>>> to be able to use the same initialization code. At least for the
>>>> K8T800, this is sufficient to have a working HT link with the CPU, and
>>>> to initialise the V-Link to the southbridge.
>>>>
>>>> Signed-off-by Alexandru Gagniuc<mr.nuke.me at gmail.com>
>>>
>>> Acked-by: Peter Stuge<peter at stuge.se>
>>>
>>> r6367
>>
>> Sorry, we have to back this out again since the license of some of the
>> files are not compatible with the coreboot license.
>> Unfortunately at this point we can not allow GPLv3 code in the
>> repository, as the resulting image will be GPLv2.
>>
>> Can you please back this out, Peter? (Or Alexandru, send a license
>> update if licensing your files under GPLv2 is ok for you)
>>
> Wow! That is a big no, no.

Only src/southbridge/via/k8t890/k8x8xx.h is affected. Since it is
essentially just a wrapper of another header file, can we just kill the
indirection and the problem is solved?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stefan.reinauer at coreboot.org  Wed Mar  2 01:08:08 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 2 Mar 2011 01:08:08 +0100
Subject: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
In-Reply-To: <4D6D89D2.9070304@gmx.net>
References: <4D553502.50904@gmail.com> <20110216134309.6588.qmail@stuge.se>
	<20110301211440.GB28067@coreboot.org>
	<4D6D83E9.4080400@settoplinux.org> <4D6D89D2.9070304@gmx.net>
Message-ID: <20110302000808.GA10000@coreboot.org>

* Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [110302 01:05]:
> Auf 02.03.2011 00:40, Joseph Smith schrieb:
> > On 03/01/2011 04:14 PM, Stefan Reinauer wrote:
> >> * Peter Stuge<peter at stuge.se>  [110216 14:43]:
> >>> Alex G. wrote:
> >>>> Extended K8T890 driver to include the K8T800 and K8M800 northbridges.
> >>>> The K8T800 is almost identical to the K8T800Pro, also added to this
> >>>> patch. The K8T800_OLD is also defined, which is an older  version of
> >>>> the K8T800, but which has no driver and early HT code yet.
> >>>> Also extended the K8M890 VGA driver to work for the K8M800 (not
> >>>> tested).
> >>>> According to the datasheet, the K8T890 and K8T800 are similar enough
> >>>> to be able to use the same initialization code. At least for the
> >>>> K8T800, this is sufficient to have a working HT link with the CPU, and
> >>>> to initialise the V-Link to the southbridge.
> >>>>
> >>>> Signed-off-by Alexandru Gagniuc<mr.nuke.me at gmail.com>
> >>>
> >>> Acked-by: Peter Stuge<peter at stuge.se>
> >>>
> >>> r6367
> >>
> >> Sorry, we have to back this out again since the license of some of the
> >> files are not compatible with the coreboot license.
> >> Unfortunately at this point we can not allow GPLv3 code in the
> >> repository, as the resulting image will be GPLv2.
> >>
> >> Can you please back this out, Peter? (Or Alexandru, send a license
> >> update if licensing your files under GPLv2 is ok for you)
> >>
> > Wow! That is a big no, no.
> 
> Only src/southbridge/via/k8t890/k8x8xx.h is affected. Since it is
> essentially just a wrapper of another header file, can we just kill the
> indirection and the problem is solved?

Sure. Patches welcome.




From stefan.reinauer at coreboot.org  Wed Mar  2 01:14:54 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 2 Mar 2011 01:14:54 +0100
Subject: [coreboot] #178: Life Insurance - How To Buy Life Insurance
 Policies
In-Reply-To: <4D6D8399.7090706@settoplinux.org>
References: <045.bc210f8e81ae23679af903f14ee706f6@coreboot.org>
	<4D6D8399.7090706@settoplinux.org>
Message-ID: <20110302001454.GA13829@coreboot.org>

Thanks to Peter Stuge for his hint, we are moderating Trac posts now for
all anonymous posts so this should no longer be an issue.

* Joseph Smith <joe at settoplinux.org> [110302 00:39]:
> On 03/01/2011 02:24 PM, coreboot wrote:
> >#178: Life Insurance - How To Buy Life Insurance Policies
> >-------------------------------------+-------------------------------------
> >     Reporter:  anonymous             |         Owner:
> >         Type:  enhancement           |  c-d.hailfinger.devel.2006@?
> >     Priority:  major                 |        Status:  new
> >    Component:  flashrom (please use  |     Milestone:  flashrom v1.1
> >   trac on flashrom.org)              |      Keywords:  life insurance
> >Dependencies:                        |  Patch Status:  patch needs review
> >-------------------------------------+-------------------------------------
> >  [[Image(http://www.johnkatsouris.co.uk/images/family_park.jpg)]]
> >
> >  Buying such services like '''[http://www.lifeinsurance.net.au/ life
> >  insurance]''' in making things better for those people to have its best
> >  ways that will be better for them during this days. It can make things
> >  better for those people to have its best ways to satisfy their needs in
> >  life living in this world. This '''insurances''' people can have the
> >  things they need in life living in this world. Having such services that
> >  will make things better for them having the best services that will make
> >  them have a '''Life Insurance''' in making things better for them during
> >  this days.
> >
> >  [[Image(http://onlinearnings.com/wp-content/uploads/2009/07/happy-life-
> >  insurance.jpg)]]
> >
> >  It can make things better for those people having such
> >  '''[http://www.lifeinsurance.net.au/ life insurance]''' in a certain
> >  period of time. It is best for those people to have such ways that can be
> >  better for those people on having the things that will make them have such
> >  '''Living Insurance''' in a certain period of time that will make those
> >  people have its best ways in living.
> >
> coreboot is selling life insurance now?
> Is this in case of electro static discharge?
> 
> -- 
> Thanks,
> Joseph Smith
> Set-Top-Linux
> www.settoplinux.org
> 
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot



From stefan.reinauer at coreboot.org  Wed Mar  2 01:17:24 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 2 Mar 2011 01:17:24 +0100
Subject: [coreboot] Tiny bootblock vs Bigbootblock
In-Reply-To: <AANLkTi=_mGkbFrJ2hcxw7dTE2tgyrTAhz8hgQJ49dgps@mail.gmail.com>
References: <AANLkTi=_mGkbFrJ2hcxw7dTE2tgyrTAhz8hgQJ49dgps@mail.gmail.com>
Message-ID: <20110302001724.GB13829@coreboot.org>

* ali hagigat <hagigatali at gmail.com> [110301 09:58]:
> What is the difference between tiny and big boot block?

In big boot block mode, romstage (and thus ram init) is part of the
boot block. In tiny boot block mode, romstage is an extra file in CBFS.

> My second question is that the code of bootblock is copied to romstage
> too. I mean we have a duplicate code in two different components. Is
> that right?

That might be a mistake. Where did you see that?

Stefan
 



From stefan.reinauer at coreboot.org  Wed Mar  2 01:23:26 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 2 Mar 2011 01:23:26 +0100
Subject: [coreboot] Google Summer of Code 2011
In-Reply-To: <34dd433c9e05e4b3bb30ac7c9fff035a@imap.1and1.com>
References: <AANLkTinnR-_y64jtTe+0VORe+6heGE4tKObqb2v=2xYf@mail.gmail.com>
	<34dd433c9e05e4b3bb30ac7c9fff035a@imap.1and1.com>
Message-ID: <20110302002326.GC13829@coreboot.org>

* Joseph Smith <joe at settoplinux.org> [110301 10:08]:
> On Mon, 28 Feb 2011 18:17:34 -0700, Marc Jones <marcj303 at gmail.com> wrote:
> > GSoC mentoring org signup starts this week and is due by March 11. I
> > can take the lead this year, unless someone else would like to do it.
> > 
> > If we are accepted (I expect we will be), Student applications are
> > March 28 - April 8.
> > 
> > Please add your project ideas to the wiki : http://www.coreboot.org/GSoC
> > 
> > Who would like to be a mentor this year?
> > 
> > Marc
> 
> Hmm, even though I am getting old I am going to go back to school in the
> fall 2011 to further my education (and hopefully take some x86 assembly
> courses, cause I know some of you get sick of my assembly questions :-)). 
> Could I be considered a student candidate for GSoC?


You might. Check out

http://www.google-melange.com/document/show/gsoc_program/google/gsoc2011/faqs#who

Stefan



From stefan.reinauer at coreboot.org  Wed Mar  2 01:24:09 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 2 Mar 2011 01:24:09 +0100
Subject: [coreboot] coreboot certified hardware
In-Reply-To: <4D6C91D1.9030409@jenbo.dk>
References: <4CA978ED.8000002@georgi-clan.de>
	<201010041950.25088.phorsyon@gmx.net>
	<20101004192314.7903.qmail@stuge.se>
	<AANLkTimROPLy7jwLcLhNDF0SPNL6R-hw2HS6YPi0zm_B@mail.gmail.com>
	<AANLkTikStpx9167n_eC4FyQovxRu-nZtYujEWW3Kxnh8@mail.gmail.com>
	<4CAAE908.5090708@assembler.cz>
	<AANLkTikKA_veW1YHwB3WmctCFZwZrOGStm6Q5v5PtXTh@mail.gmail.com>
	<20101005162634.30508.qmail@stuge.se>
	<AANLkTik5JdmeNdBWigQiORPVgcEdg4oS+kCX5KFxU4JB@mail.gmail.com>
	<4D6C91D1.9030409@jenbo.dk>
Message-ID: <20110302002409.GD13829@coreboot.org>

* Anders Jenbo <anders at jenbo.dk> [110301 07:27]:
> Wondered if you guys have seen this:
> 
> http://www.h-online.com/open/news/item/Intel-releases-GRUB-based-BIOS-test-suite-1197828.html

Did anyone work on getting this to work on coreboot?

Stefan



From zxy__1127 at 163.com  Wed Mar  2 02:47:12 2011
From: zxy__1127 at 163.com (zxy__1127)
Date: Wed, 2 Mar 2011 09:47:12 +0800
Subject: [coreboot] how to deal with large romstage size?
References: <AANLkTi=apQevBJ1zU-600RPtVogY_m38ZP8B+UedPooH@mail.gmail.com>,
	<AANLkTikfNYEKmuR3K15BidV+9mmsJzz-47aAm1f6QiHZ@mail.gmail.com>
Message-ID: <201103020947121258043@163.com >

???? Keith Hui 
????? 2011-03-02  00:32:50 
???? coreboot at coreboot.org 
??? 
??? Re: [coreboot] how to deal with large romstage size? 
 
> Hi all,
>
> After I add some memory initialisize code, the romstage is over 64K byte,and tne code can't run properly.
> Then what should I do when romstage is over 64K byte? Is romstage's size limits to 64KB?
>
> Thanks a lot!
> 2011-03-01
>

It is not a direct limitation on romstage's size, but a result of most
chipsets mapping only the top 64KB of flash to the memory space. Most
chipsets require some programming to have the entire flash rom appear
in memory. Your code didn't run properly because not all of it has
been mapped to memory space and get effectively cut.

But my romstage for Intel 440BX is only about 11KB. What chipset are
you dealing with?

my chipset is intel arrandal+qm57,it's MRC code is very large(about 110KB after build) :-(

Also, look at implementing TINY_BOOTBLOCK which leaves a tiny stub,
well within the 64KB limit, which does nothing but enable enough
hardware (southbridge to be exact) to make the entire rom visible,
then locates and executes the real romstage which is now just another
stage in CBFS. Again, all 440BX/PIIX4 boards implement this and can be
a reference.

actually, it can run at bootblock,but can not reach "cache_as_ram:".
So I think the code failed at jmp to the romstage in CBFS.

Hope this help.
Keith

-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
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From buurin at gmail.com  Wed Mar  2 05:30:26 2011
From: buurin at gmail.com (Keith Hui)
Date: Tue, 1 Mar 2011 23:30:26 -0500
Subject: [coreboot] ACPI breakage/questions and ramstage code question
Message-ID: <AANLkTiniZ=j66tw=mTKW0ddR2J3DT=XScO3inOFeGK9G@mail.gmail.com>

---
First, Mysterious breakage on experimental i82371eb ACPI stuff

Rudolf, Idwer, and anyone that tried doing ACPI for the ASUS P2B
series of boards:

I'm seeing mysterious compiler breakge after updating my local copy to
r6424. I copied that from P2B to P2B-LS and both break. Make log says:

    CC         southbridge/intel/i82371eb/fadt.driver.o
src/southbridge/intel/i82371eb/fadt.c:35:35: error: expected ?)?
before ?*? token
make: *** [build/southbridge/intel/i82371eb/fadt.driver.o] Error 1

Which points to this in the file:

/**
 * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
 * Reference: ACPIspec40a, 5.2.9, page 118
 */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void * dsdt)
{
        acpi_header_t *header = &(fadt->header);
       	device_t dev;
[ Rest of function goes here]
}

Are any of you guys having the same problem?

I ran abuild on a random target with ACPI and didn't have this
problem. I will try to find out why but hoping that someone will beat
me to an explanation.

---
In code that create ACPI tables like the above, have anyone tried
declaring the constant part of the tables statically, memcpy() it to a
working buffer at runtime, fill in the dynamic parts, then pass it on?
Currently all entries in these ACPI tables are written at runtime,
producing a lot of code that may not be needed.

---
I am finding these getting compiled into my ramstage:

...
    CC         devices/device_util.ramstage.o
    CC         devices/pci_device.ramstage.o
>    CC         devices/pcix_device.ramstage.o
>    CC         devices/pciexp_device.ramstage.o
    CC         devices/agp_device.ramstage.o
>    CC         devices/cardbus_device.ramstage.o
    CC         devices/pnp_device.ramstage.o
    CC         devices/pci_ops.ramstage.o
    CC         devices/smbus_ops.ramstage.o
    CC         devices/pci_rom.ramstage.o
...

Why is code for every bus types getting compiled in anyway? The
compile shown here is for ASUS P2B-LS, which has no PCIX, no PCI
express (board predates this), and no cardbus. Can I attempt to leave
these out and hopefully save some time and bytes?



From buurin at gmail.com  Wed Mar  2 05:44:31 2011
From: buurin at gmail.com (Keith Hui)
Date: Tue, 1 Mar 2011 23:44:31 -0500
Subject: [coreboot] how to deal with large romstage size?
In-Reply-To: <201103020947121258043@163.com>
References: <AANLkTi=apQevBJ1zU-600RPtVogY_m38ZP8B+UedPooH@mail.gmail.com>
	<AANLkTikfNYEKmuR3K15BidV+9mmsJzz-47aAm1f6QiHZ@mail.gmail.com>
	<201103020947121258043@163.com>
Message-ID: <AANLkTinYBZ55gjnCBE-0ttB1rwADruPjnzC5brOsEyqO@mail.gmail.com>

Arrandale and QM57... very nice recent hardware.

You are going to need to 1) make TINY_BOOTBLOCK work, 2) make sure
QM57 can map the entire ROM, 3) make CAR work on Arrandale, IIRC
coreboot still has no support for anything in the Intel Core family of
CPUs.

Good luck.

> ??? Re: [coreboot] how to deal with large romstage size?
>> Hi all,
>>
>> After I add some memory initialisize code, the romstage is over 64K byte,and tne code can't run properly.
>> Then what should I do when romstage is over 64K byte? Is romstage's size limits to 64KB?
>>
>> Thanks a lot!
>> 2011-03-01
>>
>
>> It is not a direct limitation on romstage's size, but a result of most
>> chipsets mapping only the top 64KB of flash to the memory space. Most
>> chipsets require some programming to have the entire flash rom appear
>> in memory. Your code didn't run properly because not all of it has
>> been mapped to memory space and get effectively cut.
>>
>> But my romstage for Intel 440BX is only about 11KB. What chipset are
>> you dealing with?
>
> my chipset is intel arrandal+qm57,it's MRC code is very large(about 110KB
> after build) :-(
>
>> Also, look at implementing TINY_BOOTBLOCK which leaves a tiny stub,
>> well within the 64KB limit, which does nothing but enable enough
>> hardware (southbridge to be exact) to make the entire rom visible,
>> then locates and executes the real romstage which is now just another
>> stage in CBFS. Again, all 440BX/PIIX4 boards implement this and can be
>> a reference.
>
> actually, it can run at bootblock,but can not reach "cache_as_ram:".
> So I think the code failed at jmp to the romstage in CBFS.
>



From peter at stuge.se  Wed Mar  2 05:56:13 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 2 Mar 2011 05:56:13 +0100
Subject: [coreboot] how to deal with large romstage size?
In-Reply-To: <AANLkTinYBZ55gjnCBE-0ttB1rwADruPjnzC5brOsEyqO@mail.gmail.com>
References: <AANLkTi=apQevBJ1zU-600RPtVogY_m38ZP8B+UedPooH@mail.gmail.com>
	<AANLkTikfNYEKmuR3K15BidV+9mmsJzz-47aAm1f6QiHZ@mail.gmail.com>
	<201103020947121258043@163.com>
	<AANLkTinYBZ55gjnCBE-0ttB1rwADruPjnzC5brOsEyqO@mail.gmail.com>
Message-ID: <20110302045613.13499.qmail@stuge.se>

Keith Hui wrote:
> You are going to need to 1) make TINY_BOOTBLOCK work, 2) make sure
> QM57 can map the entire ROM, 3) make CAR work on Arrandale,

This is a good stragey. Serialport is also important. When serialport
is working, SerialICE can reveal many required details.


> IIRC coreboot still has no support for anything in the Intel Core
> family of CPUs.

There is good support for the Core microarchitecture (Core Solo/Duo,
Core2) but nothing for Nehalem.


//Peter



From zxy__1127 at 163.com  Wed Mar  2 06:30:08 2011
From: zxy__1127 at 163.com (zxy__1127)
Date: Wed, 2 Mar 2011 13:30:08 +0800
Subject: [coreboot] how to deal with large romstage size?
References: <AANLkTi=apQevBJ1zU-600RPtVogY_m38ZP8B+UedPooH@mail.gmail.com>,
	<AANLkTikfNYEKmuR3K15BidV+9mmsJzz-47aAm1f6QiHZ@mail.gmail.com>,
	<201103020947121258043@163.com>,
	<AANLkTinYBZ55gjnCBE-0ttB1rwADruPjnzC5brOsEyqO@mail.gmail.com>
Message-ID: <201103021330083287179@163.com >


Arrandale and QM57... very nice recent hardware.

You are going to need to 1) make TINY_BOOTBLOCK work, 2) make sure
QM57 can map the entire ROM, 3) make CAR work on Arrandale, IIRC
coreboot still has no support for anything in the Intel Core family of
CPUs.

Good luck.

1) make TINY_BOOTBLOCK work
in .config file:CONFIG_TINY_BOOTBLOCK=y,is it means TINY_BOOTBLOCK work?
2) make sure QM57 can map the entire ROM
I'll work on it.
3) make CAR work on Arrandale
Sorry, my mistake.
it can run at bootblock,but can not reach "cache_as_ram:". --> It just take place when romstage in CBFS > 64KB.
when romstage in CBFS < 64KB, it runs OK,and serial can print strings.
So CAR work well on Arrandale.

Thanks!
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From c-d.hailfinger.devel.2006 at gmx.net  Wed Mar  2 08:05:11 2011
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 02 Mar 2011 08:05:11 +0100
Subject: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
In-Reply-To: <20110302000808.GA10000@coreboot.org>
References: <4D553502.50904@gmail.com> <20110216134309.6588.qmail@stuge.se>
	<20110301211440.GB28067@coreboot.org>
	<4D6D83E9.4080400@settoplinux.org> <4D6D89D2.9070304@gmx.net>
	<20110302000808.GA10000@coreboot.org>
Message-ID: <4D6DEC27.7020501@gmx.net>

Auf 02.03.2011 01:08, Stefan Reinauer schrieb:
> * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [110302 01:05]:
>   
>> Auf 02.03.2011 00:40, Joseph Smith schrieb:
>>     
>>> On 03/01/2011 04:14 PM, Stefan Reinauer wrote:
>>>       
>>>> * Peter Stuge<peter at stuge.se>  [110216 14:43]:
>>>>         
>>>>> Alex G. wrote:
>>>>>           
>>>>>> Extended K8T890 driver to include the K8T800 and K8M800 northbridges.
>>>>>> The K8T800 is almost identical to the K8T800Pro, also added to this
>>>>>> patch. The K8T800_OLD is also defined, which is an older  version of
>>>>>> the K8T800, but which has no driver and early HT code yet.
>>>>>> Also extended the K8M890 VGA driver to work for the K8M800 (not
>>>>>> tested).
>>>>>> According to the datasheet, the K8T890 and K8T800 are similar enough
>>>>>> to be able to use the same initialization code. At least for the
>>>>>> K8T800, this is sufficient to have a working HT link with the CPU, and
>>>>>> to initialise the V-Link to the southbridge.
>>>>>>
>>>>>> Signed-off-by Alexandru Gagniuc<mr.nuke.me at gmail.com>
>>>>>>             
>>>>> Acked-by: Peter Stuge<peter at stuge.se>
>>>>>
>>>>> r6367
>>>>>           
>>>> Sorry, we have to back this out again since the license of some of the
>>>> files are not compatible with the coreboot license.
>>>> Unfortunately at this point we can not allow GPLv3 code in the
>>>> repository, as the resulting image will be GPLv2.
>>>>
>>>> Can you please back this out, Peter? (Or Alexandru, send a license
>>>> update if licensing your files under GPLv2 is ok for you)
>>>>
>>>>         
>>> Wow! That is a big no, no.
>>>       
>> Only src/southbridge/via/k8t890/k8x8xx.h is affected. Since it is
>> essentially just a wrapper of another header file, can we just kill the
>> indirection and the problem is solved?
>>     
> Sure. Patches welcome.
>   

Remove a pure wrapper header file which had a different license by accident.

Untested, please use "patch -p0 -R" to apply.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


-- 
http://www.hailfinger.org/

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From stefan.reinauer at coreboot.org  Wed Mar  2 08:41:04 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 01 Mar 2011 23:41:04 -0800
Subject: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
In-Reply-To: <4D6DEC27.7020501@gmx.net>
References: <4D553502.50904@gmail.com>
	<20110216134309.6588.qmail@stuge.se>	<20110301211440.GB28067@coreboot.org>	<4D6D83E9.4080400@settoplinux.org>
	<4D6D89D2.9070304@gmx.net>	<20110302000808.GA10000@coreboot.org>
	<4D6DEC27.7020501@gmx.net>
Message-ID: <4D6DF490.1040601@coreboot.org>

On 3/1/11 11:05 PM, Carl-Daniel Hailfinger wrote:
> Auf 02.03.2011 01:08, Stefan Reinauer schrieb:
>> * Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006 at gmx.net>  [110302 01:05]:
>>
>>> Auf 02.03.2011 00:40, Joseph Smith schrieb:
>>>
>>>> On 03/01/2011 04:14 PM, Stefan Reinauer wrote:
>>>>
>>>>> * Peter Stuge<peter at stuge.se>   [110216 14:43]:
>>>>>
>>>>>> Alex G. wrote:
>>>>>>
>>>>>>> Extended K8T890 driver to include the K8T800 and K8M800 northbridges.
>>>>>>> The K8T800 is almost identical to the K8T800Pro, also added to this
>>>>>>> patch. The K8T800_OLD is also defined, which is an older  version of
>>>>>>> the K8T800, but which has no driver and early HT code yet.
>>>>>>> Also extended the K8M890 VGA driver to work for the K8M800 (not
>>>>>>> tested).
>>>>>>> According to the datasheet, the K8T890 and K8T800 are similar enough
>>>>>>> to be able to use the same initialization code. At least for the
>>>>>>> K8T800, this is sufficient to have a working HT link with the CPU, and
>>>>>>> to initialise the V-Link to the southbridge.
>>>>>>>
>>>>>>> Signed-off-by Alexandru Gagniuc<mr.nuke.me at gmail.com>
>>>>>>>
>>>>>> Acked-by: Peter Stuge<peter at stuge.se>
>>>>>>
>>>>>> r6367
>>>>>>
>>>>> Sorry, we have to back this out again since the license of some of the
>>>>> files are not compatible with the coreboot license.
>>>>> Unfortunately at this point we can not allow GPLv3 code in the
>>>>> repository, as the resulting image will be GPLv2.
>>>>>
>>>>> Can you please back this out, Peter? (Or Alexandru, send a license
>>>>> update if licensing your files under GPLv2 is ok for you)
>>>>>
>>>>>
>>>> Wow! That is a big no, no.
>>>>
>>> Only src/southbridge/via/k8t890/k8x8xx.h is affected. Since it is
>>> essentially just a wrapper of another header file, can we just kill the
>>> indirection and the problem is solved?
>>>
>> Sure. Patches welcome.
>>
> Remove a pure wrapper header file which had a different license by accident.
>
> Untested, please use "patch -p0 -R" to apply.
>
> Signed-off-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006 at gmx.net>
>
>
> Acked-by: Stefan Reinauer<stefan.reinauer at coreboot.org>




From stefan.reinauer at coreboot.org  Wed Mar  2 08:43:17 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 01 Mar 2011 23:43:17 -0800
Subject: [coreboot] ACPI breakage/questions and ramstage code question
In-Reply-To: <AANLkTiniZ=j66tw=mTKW0ddR2J3DT=XScO3inOFeGK9G@mail.gmail.com>
References: <AANLkTiniZ=j66tw=mTKW0ddR2J3DT=XScO3inOFeGK9G@mail.gmail.com>
Message-ID: <4D6DF515.6050507@coreboot.org>

On 3/1/11 8:30 PM, Keith Hui wrote:
> ---
> First, Mysterious breakage on experimental i82371eb ACPI stuff
>
> Rudolf, Idwer, and anyone that tried doing ACPI for the ASUS P2B
> series of boards:
>
> I'm seeing mysterious compiler breakge after updating my local copy to
> r6424. I copied that from P2B to P2B-LS and both break. Make log says:
>
>      CC         southbridge/intel/i82371eb/fadt.driver.o
> src/southbridge/intel/i82371eb/fadt.c:35:35: error: expected ?)?
> before ?*? token
> make: *** [build/southbridge/intel/i82371eb/fadt.driver.o] Error 1
>
> Which points to this in the file:
>
> /**
>   * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
>   * Reference: ACPIspec40a, 5.2.9, page 118
>   */
> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void * dsdt)
> {
>          acpi_header_t *header =&(fadt->header);
>         	device_t dev;
> [ Rest of function goes here]
> }
>
> Are any of you guys having the same problem?

No. Which line contains the error?




From stefan.reinauer at coreboot.org  Wed Mar  2 08:49:14 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 01 Mar 2011 23:49:14 -0800
Subject: [coreboot] how to deal with large romstage size?
In-Reply-To: <201103020947121258043@163.com >
References: <AANLkTi=apQevBJ1zU-600RPtVogY_m38ZP8B+UedPooH@mail.gmail.com>,
	<AANLkTikfNYEKmuR3K15BidV+9mmsJzz-47aAm1f6QiHZ@mail.gmail.com>
	<201103020947121258043@163.com >
Message-ID: <4D6DF67A.5070907@coreboot.org>

On 3/1/11 5:47 PM, zxy__1127 wrote:
> *? ???* Keith Hui
> *? ????* 2011-03-02 00:32:50
> *? ???* coreboot at coreboot.org
> *? ??*
> *? ??* Re: [coreboot] how to deal with large romstage size?
> > Hi all,
> >
> > After I add some memory initialisize code, the romstage is over 64K
> byte,and tne code can't run properly.
> > Then what should I do when romstage is over 64K byte? Is romstage's
> size limits to 64KB?
> >
> > Thanks a lot!
> > 2011-03-01
> >
> It is not a direct limitation on romstage's size, but a result of most
> chipsets mapping only the top 64KB of flash to the memory space. Most
> chipsets require some programming to have the entire flash rom appear
> in memory. Your code didn't run properly because not all of it has
> been mapped to memory space and get effectively cut.
> But my romstage for Intel 440BX is only about 11KB. What chipset are
> you dealing with?
> my chipset is intel arrandal+qm57,it's MRC code is very large(about
> 110KB after build) :-(
> Also, look at implementing TINY_BOOTBLOCK which leaves a tiny stub,
> well within the 64KB limit, which does nothing but enable enough
> hardware (southbridge to be exact) to make the entire rom visible,
> then locates and executes the real romstage which is now just another
> stage in CBFS. Again, all 440BX/PIIX4 boards implement this and can be
> a reference.
> *actually, it can run at bootblock,but can not reach "cache_as_ram:".*
>

I think you need to make the complete flash visible in a southbridge
bootblock.c

It would help if you could publish your current code so we can do better
than asking the crystal ball for answers ;)

Stefan

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From anders at jenbo.dk  Wed Mar  2 08:54:12 2011
From: anders at jenbo.dk (Anders Jenbo)
Date: Wed, 02 Mar 2011 08:54:12 +0100
Subject: [coreboot]  via apollo pro 133 code (for mue)
Message-ID: <4D6DF7A4.7080202@jenbo.dk>

Hi here is the code i did for the via apollo pro 133(a), i also included 
the code for the board that i was working on so you have some sample 
code to work with.
I was working on the SMB code when i last left it so it isn't able to 
detect the ram yet, but the serial output works so you have some thing 
to debug with.

-Anders
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From zxy__1127 at 163.com  Wed Mar  2 09:26:26 2011
From: zxy__1127 at 163.com (zxy__1127)
Date: Wed, 2 Mar 2011 16:26:26 +0800
Subject: [coreboot] how to deal with large romstage size?
References: <AANLkTi=apQevBJ1zU-600RPtVogY_m38ZP8B+UedPooH@mail.gmail.com>,
	<AANLkTikfNYEKmuR3K15BidV+9mmsJzz-47aAm1f6QiHZ@mail.gmail.com>,
	<201103020947121258043@163.com, >, <4D6DF67A.5070907@coreboot.org>
Message-ID: <201103021626233438401@163.com >

Hi,

I think you need to make the complete flash visible in a southbridge bootblock.c

It would help if you could publish your current code so we can do better than asking the crystal ball for answers ;)

it's based on D945gclf, but MRC is under NDA, :-(

Thanks!
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From mr.nuke.me at gmail.com  Wed Mar  2 09:54:05 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Mar 2011 10:54:05 +0200
Subject: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
In-Reply-To: <20110301211440.GB28067@coreboot.org>
References: <4D553502.50904@gmail.com> <20110216134309.6588.qmail@stuge.se>
	<20110301211440.GB28067@coreboot.org>
Message-ID: <4D6E05AD.40709@gmail.com>

On 03/01/2011 11:14 PM, Stefan Reinauer wrote:
> * Peter Stuge <peter at stuge.se> [110216 14:43]:
>> Alex G. wrote:
>>> Extended K8T890 driver to include the K8T800 and K8M800 northbridges.
>>> The K8T800 is almost identical to the K8T800Pro, also added to this
>>> patch. The K8T800_OLD is also defined, which is an older  version of 
>>> the K8T800, but which has no driver and early HT code yet.
>>> Also extended the K8M890 VGA driver to work for the K8M800 (not tested).
>>> According to the datasheet, the K8T890 and K8T800 are similar enough
>>> to be able to use the same initialization code. At least for the
>>> K8T800, this is sufficient to have a working HT link with the CPU, and
>>> to initialise the V-Link to the southbridge.
>>>
>>> Signed-off-by Alexandru Gagniuc <mr.nuke.me at gmail.com>
>>
>> Acked-by: Peter Stuge <peter at stuge.se>
>>
>> r6367
>  
> Sorry, we have to back this out again since the license of some of the
> files are not compatible with the coreboot license. 
> Unfortunately at this point we can not allow GPLv3 code in the
> repository, as the resulting image will be GPLv2.
> 
> Can you please back this out, Peter? (Or Alexandru, send a license
> update if licensing your files under GPLv2 is ok for you)
> 
You may change the license to GPLv2+.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>



From mr.nuke.me at gmail.com  Wed Mar  2 09:55:01 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Mar 2011 10:55:01 +0200
Subject: [coreboot] [PATCH] outb(* 0x80) to post_code()
In-Reply-To: <20110301210913.GA28067@coreboot.org>
References: <4D67BE45.70300@gmail.com>
	<4D67EB68.2090609@gmail.com>	<20110225211058.GH9338@coreboot.org>	<4D6820FE.7020108@georgi-clan.de>	<20110225214549.GA18842@coreboot.org>	<4D682536.7080300@georgi-clan.de>	<20110225215939.GA28964@coreboot.org>
	<4D682C8B.5090707@gmail.com>	<20110226005841.GA23938@coreboot.org>
	<4D6858EB.8050107@gmail.com> <20110301210913.GA28067@coreboot.org>
Message-ID: <4D6E05E5.6090306@gmail.com>

On 03/01/2011 11:09 PM, Stefan Reinauer wrote:
> * Alex G. <mr.nuke.me at gmail.com> [110226 02:35]:
>> Index: src/include/console/post_codes.h
>> ===================================================================
>> --- src/include/console/post_codes.h	(revision 0)
>> +++ src/include/console/post_codes.h	(revision 0)
>> @@ -0,0 +1,350 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me at gmail.com>
>> + *
>> + * This program is free software: you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 3 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + * 
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>> + */
> 
> Due to the GPLv2 only nature of many source code files, we can not allow
> GPLv3 or even GPLv3 or later code to be committed to the repository.
> Please make this GPLv2 if possible.
> 
You may, if you wish, change the license to GPLv2+.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>





From mr.nuke.me at gmail.com  Wed Mar  2 10:08:15 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Mar 2011 11:08:15 +0200
Subject: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
In-Reply-To: <20110302000808.GA10000@coreboot.org>
References: <4D553502.50904@gmail.com> <20110216134309.6588.qmail@stuge.se>
	<20110301211440.GB28067@coreboot.org>
	<4D6D83E9.4080400@settoplinux.org> <4D6D89D2.9070304@gmx.net>
	<20110302000808.GA10000@coreboot.org>
Message-ID: <4D6E08FF.1090305@gmail.com>

On 03/02/2011 02:08 AM, Stefan Reinauer wrote:
> * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [110302 01:05]:
>> Auf 02.03.2011 00:40, Joseph Smith schrieb:
>>> On 03/01/2011 04:14 PM, Stefan Reinauer wrote:
>>>> * Peter Stuge<peter at stuge.se>  [110216 14:43]:
>>>>> Alex G. wrote:
>>>>>> Extended K8T890 driver to include the K8T800 and K8M800 northbridges.
>>>>>> The K8T800 is almost identical to the K8T800Pro, also added to this
>>>>>> patch. The K8T800_OLD is also defined, which is an older  version of
>>>>>> the K8T800, but which has no driver and early HT code yet.
>>>>>> Also extended the K8M890 VGA driver to work for the K8M800 (not
>>>>>> tested).
>>>>>> According to the datasheet, the K8T890 and K8T800 are similar enough
>>>>>> to be able to use the same initialization code. At least for the
>>>>>> K8T800, this is sufficient to have a working HT link with the CPU, and
>>>>>> to initialise the V-Link to the southbridge.
>>>>>>
>>>>>> Signed-off-by Alexandru Gagniuc<mr.nuke.me at gmail.com>
>>>>>
>>>>> Acked-by: Peter Stuge<peter at stuge.se>
>>>>>
>>>>> r6367
>>>>
>>>> Sorry, we have to back this out again since the license of some of the
>>>> files are not compatible with the coreboot license.
>>>> Unfortunately at this point we can not allow GPLv3 code in the
>>>> repository, as the resulting image will be GPLv2.
>>>>
>>>> Can you please back this out, Peter? (Or Alexandru, send a license
>>>> update if licensing your files under GPLv2 is ok for you)
>>>>
>>> Wow! That is a big no, no.
>>
>> Only src/southbridge/via/k8t890/k8x8xx.h is affected. Since it is
>> essentially just a wrapper of another header file, can we just kill the
>> indirection and the problem is solved?
> 
> Sure. Patches welcome.
> 
Actually, if I messed it up, I find it fair that I fix it. Sorry I
couldn't get to it earlier.

Alex
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From mr.nuke.me at gmail.com  Wed Mar  2 10:10:05 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Mar 2011 11:10:05 +0200
Subject: [coreboot] [PATCH] outb(* 0x80) to post_code()
In-Reply-To: <4D6E05E5.6090306@gmail.com>
References: <4D67BE45.70300@gmail.com>
	<4D67EB68.2090609@gmail.com>	<20110225211058.GH9338@coreboot.org>	<4D6820FE.7020108@georgi-clan.de>	<20110225214549.GA18842@coreboot.org>	<4D682536.7080300@georgi-clan.de>	<20110225215939.GA28964@coreboot.org>
	<4D682C8B.5090707@gmail.com>	<20110226005841.GA23938@coreboot.org>
	<4D6858EB.8050107@gmail.com> <20110301210913.GA28067@coreboot.org>
	<4D6E05E5.6090306@gmail.com>
Message-ID: <4D6E096D.8060704@gmail.com>

On 03/02/2011 10:55 AM, Alex G. wrote:
> On 03/01/2011 11:09 PM, Stefan Reinauer wrote:
>> Due to the GPLv2 only nature of many source code files, we can not allow
>> GPLv3 or even GPLv3 or later code to be committed to the repository.
>> Please make this GPLv2 if possible.
>>
> You may, if you wish, change the license to GPLv2+.
> 
Nevermind that. I'll resubmit the patch. I mess it, I fix it :)

Alex





From hagigatali at gmail.com  Wed Mar  2 11:53:05 2011
From: hagigatali at gmail.com (ali hagigat)
Date: Wed, 2 Mar 2011 14:23:05 +0330
Subject: [coreboot] Tiny bootblock vs Bigbootblock
In-Reply-To: <20110302001724.GB13829@coreboot.org>
References: <AANLkTi=_mGkbFrJ2hcxw7dTE2tgyrTAhz8hgQJ49dgps@mail.gmail.com>
	<20110302001724.GB13829@coreboot.org>
Message-ID: <AANLkTin-6F71Q3tZZQv5e4n0UQOeqWgddv0HKmZp6qjK@mail.gmail.com>

I think i made a mistake. In big boot block, bootblock code is written
once for coreboot.pre and the same is for tiny boot block. My source
of confusion was the inclusion of the bootblock code in crt0.
Regards

On Wed, Mar 2, 2011 at 3:47 AM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * ali hagigat <hagigatali at gmail.com> [110301 09:58]:
>> What is the difference between tiny and big boot block?
>
> In big boot block mode, romstage (and thus ram init) is part of the
> boot block. In tiny boot block mode, romstage is an extra file in CBFS.
>
>> My second question is that the code of bootblock is copied to romstage
>> too. I mean we have a duplicate code in two different components. Is
>> that right?
>
> That might be a mistake. Where did you see that?
>
> Stefan
>
>



From svens at stackframe.org  Wed Mar  2 15:50:06 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Wed,  2 Mar 2011 15:50:06 +0100
Subject: [coreboot] [PATCH] add PC87384 SuperIO
Message-ID: <1299077406-24752-1-git-send-email-svens@stackframe.org>

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/superio/nsc/Kconfig              |    2 +
 src/superio/nsc/Makefile.inc         |    1 +
 src/superio/nsc/pc87384/Makefile.inc |   22 +++++++++
 src/superio/nsc/pc87384/chip.h       |   31 +++++++++++++
 src/superio/nsc/pc87384/pc87384.h    |   28 ++++++++++++
 src/superio/nsc/pc87384/superio.c    |   80 ++++++++++++++++++++++++++++++++++
 6 files changed, 164 insertions(+), 0 deletions(-)
 create mode 100644 src/superio/nsc/pc87384/Makefile.inc
 create mode 100644 src/superio/nsc/pc87384/chip.h
 create mode 100644 src/superio/nsc/pc87384/pc87384.h
 create mode 100644 src/superio/nsc/pc87384/superio.c

diff --git a/src/superio/nsc/Kconfig b/src/superio/nsc/Kconfig
index 3a98d83..0d97bc4 100644
--- a/src/superio/nsc/Kconfig
+++ b/src/superio/nsc/Kconfig
@@ -30,6 +30,8 @@ config SUPERIO_NSC_PC87366
 	bool
 config SUPERIO_NSC_PC87382
 	bool
+config SUPERIO_NSC_PC87384
+	bool
 config SUPERIO_NSC_PC87392
 	bool
 config SUPERIO_NSC_PC87417
diff --git a/src/superio/nsc/Makefile.inc b/src/superio/nsc/Makefile.inc
index 08f28df..c11170e 100644
--- a/src/superio/nsc/Makefile.inc
+++ b/src/superio/nsc/Makefile.inc
@@ -23,6 +23,7 @@ subdirs-y += pc87351
 subdirs-y += pc87360
 subdirs-y += pc87366
 subdirs-y += pc87382
+subdirs-y += pc87384
 subdirs-y += pc87392
 subdirs-y += pc87417
 subdirs-y += pc87427
diff --git a/src/superio/nsc/pc87384/Makefile.inc b/src/superio/nsc/pc87384/Makefile.inc
new file mode 100644
index 0000000..b577489
--- /dev/null
+++ b/src/superio/nsc/pc87384/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_NSC_PC87384) += superio.c
+
diff --git a/src/superio/nsc/pc87384/chip.h b/src/superio/nsc/pc87384/chip.h
new file mode 100644
index 0000000..4eaa92f
--- /dev/null
+++ b/src/superio/nsc/pc87384/chip.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_NSC_PC87384_CHIP_H
+#define SUPERIO_NSC_PC87384_CHIP_H
+
+#include <uart8250.h>
+extern struct chip_operations superio_nsc_pc87384_ops;
+
+struct superio_nsc_pc87384_config {
+	struct uart8250 com1, com2;
+};
+
+#endif
diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h
new file mode 100644
index 0000000..fe573b7
--- /dev/null
+++ b/src/superio/nsc/pc87384/pc87384.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_NSC_PC87384_H
+#define SUPERIO_NSC_PC87384_H
+
+#define PC87384_PP   0x01
+#define PC87384_SP2  0x02
+#define PC87384_SP1  0x03
+#define PC87384_GPIO 0x07
+#endif
diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c
new file mode 100644
index 0000000..5bd318f
--- /dev/null
+++ b/src/superio/nsc/pc87384/superio.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "pc87384.h"
+
+static void init(device_t dev)
+{
+	struct superio_nsc_pc87384_config *conf = dev->chip_info;
+	struct resource *res0;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.pnp.device) {
+	case PC87384_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case PC87384_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+
+	case PC87384_GPIO:
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, PC87384_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0} },
+	{ &ops, PC87384_SP1,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } },
+	{ &ops, PC87384_SP2,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } },
+	{ &ops, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nsc_pc87384_ops = {
+	CHIP_NAME("NSC PC87384 Super I/O")
+	.enable_dev = enable_dev,
+};
-- 
1.7.4.1




From buurin at gmail.com  Wed Mar  2 16:28:50 2011
From: buurin at gmail.com (Keith Hui)
Date: Wed, 2 Mar 2011 10:28:50 -0500
Subject: [coreboot] how to deal with large romstage size?
Message-ID: <AANLkTi=F9okJdwOU6UwnUssjH0p669VVKHxhpGdCKwi5@mail.gmail.com>

>> Hi,
>>
>> I think you need to make the complete flash visible in a southbridge bootblock.c
>>
>> It would help if you could publish your current code so we can do better than asking the crystal ball for answers ;)
>>
> it's based on D945gclf, but MRC is under NDA, :-(
>
> Thanks!

It's the Memory Reference Code, for those who don't know.

You probably can place a banner to be sent via serial port where MRC
is about to come into play ie. raminit is about to start, and replace
the MRC in the review copy you post up here with some code to generate
110k of dead beefs. :-D When we try it and the banner shows, that
would be a good sign.

AMD wins a point in supporting open source, again. -_-



From andy at vrea.uho.edu.cu  Wed Mar  2 18:03:20 2011
From: andy at vrea.uho.edu.cu (Andy)
Date: Wed, 2 Mar 2011 12:03:20 -0500
Subject: [coreboot] Hello
Message-ID: <E23E60F3944549B0BB0715647EAF8980@superpc>

How to use the coreboot-5917 software??
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From mr.nuke.me at gmail.com  Wed Mar  2 20:05:14 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Mar 2011 21:05:14 +0200
Subject: [coreboot] [PATCH] outb(* 0x80) to post_code()
In-Reply-To: <4D6E096D.8060704@gmail.com>
References: <4D67BE45.70300@gmail.com>
	<4D67EB68.2090609@gmail.com>	<20110225211058.GH9338@coreboot.org>	<4D6820FE.7020108@georgi-clan.de>	<20110225214549.GA18842@coreboot.org>	<4D682536.7080300@georgi-clan.de>	<20110225215939.GA28964@coreboot.org>
	<4D682C8B.5090707@gmail.com>	<20110226005841.GA23938@coreboot.org>
	<4D6858EB.8050107@gmail.com> <20110301210913.GA28067@coreboot.org>
	<4D6E05E5.6090306@gmail.com> <4D6E096D.8060704@gmail.com>
Message-ID: <4D6E94EA.9070100@gmail.com>

Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
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From bj.rn at co-assembler.net  Wed Mar  2 20:08:39 2011
From: bj.rn at co-assembler.net (=?iso-8859-1?b?Qmr2cm4=?= Busse)
Date: Wed, 02 Mar 2011 20:08:39 +0100
Subject: [coreboot] via apollo pro 133 code (for mue)
In-Reply-To: <4D6DF7A4.7080202@jenbo.dk>
References: <4D6DF7A4.7080202@jenbo.dk>
Message-ID: <20110302200839.10056l0dzfjhabhz@mail.baerlin.eu>

Quoting Anders Jenbo <anders at jenbo.dk>:

> Hi here is the code i did for the via apollo pro 133(a), i also  
> included the code for the board that i was working on so you have  
> some sample code to work with.
> I was working on the SMB code when i last left it so it isn't able  
> to detect the ram yet, but the serial output works so you have some  
> thing to debug with.
>
> -Anders
>

Hi Anders,

thanks a lot! I am glad there is serial output already. Looking  
forward to some adventure.
Will report back as soon as there is some progress.

Regards,
  Bj?rn



----------------------------------------------------------------
This message was sent using IMP, the Internet Messaging Program.




From svn at coreboot.org  Wed Mar  2 20:56:28 2011
From: svn at coreboot.org (repository service)
Date: Wed, 02 Mar 2011 20:56:28 +0100
Subject: [coreboot] [commit] r6426 - trunk/src/southbridge/via/k8t890
Message-ID: <E1Pus9s-0007VC-Cd@ra.coresystems.de>

Author: stuge
Date: Wed Mar  2 20:56:28 2011
New Revision: 6426
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6426

Log:
Fixes licensing of src/southbridge/via/k8t890/k8x8xx.h to GPLv2+ from GPLv3.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/southbridge/via/k8t890/k8x8xx.h

Modified: trunk/src/southbridge/via/k8t890/k8x8xx.h
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8x8xx.h	Tue Mar  1 23:02:37 2011	(r6425)
+++ trunk/src/southbridge/via/k8t890/k8x8xx.h	Wed Mar  2 20:56:28 2011	(r6426)
@@ -5,7 +5,7 @@
  *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
@@ -14,7 +14,8 @@
  * GNU General Public License for more details.
  * 
  * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
 #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H



From peter at stuge.se  Wed Mar  2 20:56:45 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 2 Mar 2011 20:56:45 +0100
Subject: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
In-Reply-To: <4D6E08FF.1090305@gmail.com>
References: <4D553502.50904@gmail.com> <20110216134309.6588.qmail@stuge.se>
	<20110301211440.GB28067@coreboot.org>
	<4D6D83E9.4080400@settoplinux.org> <4D6D89D2.9070304@gmx.net>
	<20110302000808.GA10000@coreboot.org> <4D6E08FF.1090305@gmail.com>
Message-ID: <20110302195645.13427.qmail@stuge.se>

Alex G. wrote:
> > Sure. Patches welcome.
> 
> Actually, if I messed it up, I find it fair that I fix it.

Not only is it the only fair way, it's also the simplest way. I'm
sorry people were so trigger happy with this.


> Sorry I couldn't get to it earlier.

No problem.


> Fixes licensing of src/src/southbridge/via/k8t890/k8x8xx.h to GPLv2+ from GPLv3.
> 
> Signed-off-by: Alexandru Gagniuc <mr.nuke.megmail.com>

Acked-by: Peter Stuge <peter at stuge.se>

r6426



From mr.nuke.me at gmail.com  Wed Mar  2 21:23:32 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Mar 2011 22:23:32 +0200
Subject: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard
In-Reply-To: <4D66673D.1030004@gmail.com>
References: <4D5C5664.8040601@gmail.com> <4D66673D.1030004@gmail.com>
Message-ID: <4D6EA744.6030308@gmail.com>

On 02/24/2011 04:12 PM, Alex G. wrote:
> Ping!
> 
Ping6 ?

Alex
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From njacobs8 at hetnet.nl  Wed Mar  2 21:13:33 2011
From: njacobs8 at hetnet.nl (Nils)
Date: Wed, 2 Mar 2011 21:13:33 +0100
Subject: [coreboot] [commit] r6418 - trunk/src/northbridge/amd/lx
Message-ID: <201103022113.33984.njacobs8@hetnet.nl>

Hi Patrick,

>Author: oxygene
>Date: Tue Mar  1 08:30:14 2011
>New Revision: 6418
>URL: https://tracker.coreboot.org/trac/coreboot/changeset/6418
>
>Log:
>Mark non-returning function as noreturn to help some compiler versions
>
>Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
>Acked-by: Patrick Georgi <patrick.georgi at secunet.com>
>
>Modified:
>   trunk/src/northbridge/amd/lx/raminit.c
>
>Modified: trunk/src/northbridge/amd/lx/raminit.c
>==============================================================================
>--- trunk/src/northbridge/amd/lx/raminit.c      Tue Mar  1 08:26:00 2011        
>(r6417)
>+++ trunk/src/northbridge/amd/lx/raminit.c      Tue Mar  1 08:30:14 2011        
>(r6418)
>@@ -32,7 +32,7 @@
>        printk(BIOS_DEBUG, " * %s\n", s);
> }
> 
>-static void hcf(void)
>+static void __attribute__((noreturn)) hcf(void)
> {
>        print_emerg("DIE\n");
>        /* this guarantees we flush the UART fifos (if any) and also

Should this change also be applied for the almost same function in Geode GX2?

Thanks,Nils.



From mr.nuke.me at gmail.com  Wed Mar  2 21:38:08 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 02 Mar 2011 22:38:08 +0200
Subject: [coreboot] [PATCH] Proposal for dealing with superio
	*.c	includes
In-Reply-To: <4D6A3F6C.4040305@gmail.com>
References: <4D68EF61.6080309@gmail.com> <20110226211656.5093.qmail@stuge.se>
	<4D69734C.5040700@gmail.com> <4D6A3F6C.4040305@gmail.com>
Message-ID: <4D6EAAB0.2070608@gmail.com>

Option C with GPLv2+ licensing.

Alex
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From patrick at georgi-clan.de  Wed Mar  2 21:48:59 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 02 Mar 2011 21:48:59 +0100
Subject: [coreboot] [commit] r6418 - trunk/src/northbridge/amd/lx
In-Reply-To: <201103022113.33984.njacobs8@hetnet.nl>
References: <201103022113.33984.njacobs8@hetnet.nl>
Message-ID: <4D6EAD3B.6030001@georgi-clan.de>

Am 02.03.2011 21:13, schrieb Nils:
>> -static void hcf(void)
>> +static void __attribute__((noreturn)) hcf(void)
> Should this change also be applied for the almost same function in Geode GX2?
As long as it doesn't return, yes.


Patrick



From joe at settoplinux.org  Wed Mar  2 22:20:21 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 02 Mar 2011 16:20:21 -0500
Subject: [coreboot] Hello
In-Reply-To: <E23E60F3944549B0BB0715647EAF8980@superpc>
References: <E23E60F3944549B0BB0715647EAF8980@superpc>
Message-ID: <4D6EB495.5050405@settoplinux.org>

On 03/02/2011 12:03 PM, Andy wrote:
> How to use the coreboot-5917 software??
>
$ svn co svn://coreboot.org/coreboot/trunk coreboot -r 5917

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From buurin at gmail.com  Wed Mar  2 22:33:16 2011
From: buurin at gmail.com (Keith Hui)
Date: Wed, 2 Mar 2011 16:33:16 -0500
Subject: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this
In-Reply-To: <AANLkTi=ChqsYw_XoAczknZ0EUuoOGAtojH94t5-jy8Ew@mail.gmail.com>
References: <AANLkTikumlUzP5ybFivRRbIl015dm1douWyp2Fp6ezRQ@mail.gmail.com>
	<AANLkTi=HR1rw08bWQBJ3+Jmn+iEcdoa+EdM9CBG1_rm5@mail.gmail.com>
	<AANLkTik+kysDgBtXjBtKbjS=LKc+M2FSp3ASnNHS3qAR@mail.gmail.com>
	<20110114084736.GC4518@localhost2.local>
	<AANLkTi=ChqsYw_XoAczknZ0EUuoOGAtojH94t5-jy8Ew@mail.gmail.com>
Message-ID: <AANLkTikkZsatbku6EFrZhFGMbtwryUz0a-Nzt1-JwpJr@mail.gmail.com>

ping3?

On Mon, Jan 31, 2011 at 12:53 PM, Keith Hui <buurin at gmail.com> wrote:
> On Fri, Jan 14, 2011 at 3:47 AM, Roger <rogerx.oss at gmail.com> wrote:
>> On Tue, Jan 11, 2011 at 11:17:17PM -0500, Keith Hui wrote:
>>>Hi all,
>>>
>>>Here is the new L2 cache patch. Sign-off in the patch itself. Still
>>>very juicy and tasty at 25k. :D
>>>
>>>Also done is including cpu/intel/model_68x again in slot_1. Otherwise
>>>it will die with a Coppermine P3 installed.
>>>
>>>My boot log on P2B-LS and a Katmai 600MHz attached.
>>>
>>>I have optimized it some more, and added more information and
>>>meaningful constants as I cross checked the code with Intel's
>>>documentation. Some debugging messages are different too. Give this a
>>>good workout.
>>
>> Acked-by: Roger Zauner <rogerx.oss at gmail.com>
>>
>> Wondering if people are still waiting for acked-by. ... acked it, code compiles
>> for my "Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host
>> bridge", but have Coppermine CPU's so the code is ignored.
>
> Also wondering the status of this.
>



From peter at stuge.se  Wed Mar  2 22:38:11 2011
From: peter at stuge.se (Peter Stuge)
Date: Wed, 2 Mar 2011 22:38:11 +0100
Subject: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard
In-Reply-To: <4D6EA744.6030308@gmail.com>
References: <4D5C5664.8040601@gmail.com> <4D66673D.1030004@gmail.com>
	<4D6EA744.6030308@gmail.com>
Message-ID: <20110302213811.27526.qmail@stuge.se>

Alex G. wrote:
> Add support for ASUS K8X-X SE motherboard.
..
> Linux cannot complete booting.

Also not with acpi=off so that it uses the mptable?

Basically the code isn't ready yet.

Maybe we should have a CONFIG_EXPERIMENTAL ?


//Peter



From joe at settoplinux.org  Wed Mar  2 22:41:01 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 02 Mar 2011 16:41:01 -0500
Subject: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard
In-Reply-To: <20110302213811.27526.qmail@stuge.se>
References: <4D5C5664.8040601@gmail.com>
	<4D66673D.1030004@gmail.com>	<4D6EA744.6030308@gmail.com>
	<20110302213811.27526.qmail@stuge.se>
Message-ID: <4D6EB96D.40508@settoplinux.org>

On 03/02/2011 04:38 PM, Peter Stuge wrote:
> Alex G. wrote:
>> Add support for ASUS K8X-X SE motherboard.
> ..
>> Linux cannot complete booting.
>
> Also not with acpi=off so that it uses the mptable?
>
> Basically the code isn't ready yet.
>
> Maybe we should have a CONFIG_EXPERIMENTAL ?
>
>
> //Peter
>
Alex why don't you leave acpi out for now, Linux doesn't need it to 
boot. I would concentrate on your IRQ routing issue.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From mr.nuke.me at gmail.com  Wed Mar  2 23:03:05 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 03 Mar 2011 00:03:05 +0200
Subject: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard
In-Reply-To: <4D6EB96D.40508@settoplinux.org>
References: <4D5C5664.8040601@gmail.com>	<4D66673D.1030004@gmail.com>	<4D6EA744.6030308@gmail.com>	<20110302213811.27526.qmail@stuge.se>
	<4D6EB96D.40508@settoplinux.org>
Message-ID: <4D6EBE99.6050106@gmail.com>

On 03/02/2011 11:41 PM, Joseph Smith wrote:
> On 03/02/2011 04:38 PM, Peter Stuge wrote:
>> Alex G. wrote:
>>> Add support for ASUS K8X-X SE motherboard.
>> ..
>>> Linux cannot complete booting.
>>
>> Also not with acpi=off so that it uses the mptable?
>>
Yes. It fails to work with acpi, mptable, and pirq table. That means [no
option], "acpi=off", and "acpi=off noapic" respectively.

>> Basically the code isn't ready yet.
>>
I explained the issue in more detail in my first email qith this patch,
that I had sent a while back.

>> Maybe we should have a CONFIG_EXPERIMENTAL ?
>>
Alright, but don't mind my asking, how exactly do we do this?

> Alex why don't you leave acpi out for now, Linux doesn't need it to
> boot. I would concentrate on your IRQ routing issue.
> 
I haven't even touched the ACPI in over month. I'm testing with
"acpi=off". The problem doesn't seem to be IRQ routing, as in routing,
but the IOAPIC refusing to work the way it should work. I've explained
this in more detail in my initial posting.

I'm waiting for the friend who owns this board to pick it up any day
now, so I doubt I will be able to finish it. I've been spinning in
circles for a very long time now. If I can't get it ready, I'd like the
next person who tries to port this board to already have my work as a
starting point.

Alex



From flashrom at mkarcher.dialup.fu-berlin.de  Wed Mar  2 23:30:21 2011
From: flashrom at mkarcher.dialup.fu-berlin.de (Michael Karcher)
Date: Wed, 02 Mar 2011 23:30:21 +0100
Subject: [coreboot] Add NSC PC87364 support to superiotool
Message-ID: <1299105021.4793.56.camel@localhost>

Hello jankeso,

in the process of writing a board enable procedure for your mainboard I
stumbled upon the fact that the chip used to control the write enable
line is most likely your Super I/O chip, which is a NSC PC87364.
superiotool currently does not support dumping that chip, so I can not
verify that indeed the GPIO port of the Super I/O chip is accessed (at
address 0x80C). I attached a patch to dump the contents of that chip to
this mail. Please apply that patch to current superiotool CVS sources
(to be obtained from svn://coreboot.org/repos/trunk/util/superiotool)
and attach the output to a reply to this mail or upload to
paste.flashrom.org.

This mail has been cc'ed to the coreboot list for getting this patch
included into superiotool. If something is wrong with that patch, please
Cc: me, as I am not subscribed to the coreboot list. Thanks.

Regards,
  Michael Karcher
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From buurin at gmail.com  Thu Mar  3 00:01:28 2011
From: buurin at gmail.com (Keith Hui)
Date: Wed, 2 Mar 2011 18:01:28 -0500
Subject: [coreboot] [PATCH] Proposal for dealing with superio *.c
	includes
Message-ID: <AANLkTi=-wMh8V+T9VxqFV7LfX7MPkfQAGA++GjQe+Dt+@mail.gmail.com>

> Option C with GPLv2+ licensing.

A few quick things:

SUPERIO_FINTEK_F81865F_HAS_EARLY_SERIAL seems long-winded for a name.

I prefer to define CONFIG_SUPERIO_HAS_EARLY_SERIAL (or even just
CONFIG_HAS_EARLY_SERIAL) within the superio Kconfig and not in
mainboard Kconfig. This I think would be a per-superio setting. While
we're at it, have we seen a board with 2+ superios?

Having said that though, isn't early serial support sort of mandatory anyway?

Secretly I'm hoping that some of my ideas end up in here. :-)

Cheers
Keith



From mr.nuke.me at gmail.com  Thu Mar  3 00:06:39 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 03 Mar 2011 01:06:39 +0200
Subject: [coreboot] [PATCH] Proposal for dealing with superio *.c
	includes
In-Reply-To: <AANLkTi=-wMh8V+T9VxqFV7LfX7MPkfQAGA++GjQe+Dt+@mail.gmail.com>
References: <AANLkTi=-wMh8V+T9VxqFV7LfX7MPkfQAGA++GjQe+Dt+@mail.gmail.com>
Message-ID: <4D6ECD7F.2070207@gmail.com>

On 03/03/2011 01:01 AM, Keith Hui wrote:
>> Option C with GPLv2+ licensing.
> 
> A few quick things:
> 
> SUPERIO_FINTEK_F81865F_HAS_EARLY_SERIAL seems long-winded for a name.
> 
> I prefer to define CONFIG_SUPERIO_HAS_EARLY_SERIAL (or even just
> CONFIG_HAS_EARLY_SERIAL) within the superio Kconfig and not in
> mainboard Kconfig. This I think would be a per-superio setting. While
> we're at it, have we seen a board with 2+ superios?
> 
The idea was that, if a board has more than one superio, we would have
to select which of those carries the early serial. Let's say board
PETER40S has two superios: an KEITH875H and an ALEX666G. Both have early
serial capability, but you have to specify which of those will be used
for serial purpose.

So you have:
	select SUPERIO_KEITH875H
	select SUPERIO_ALEX666G
	select SUPERIO_ALEX666G_HAS_EARLY_SERIAL

> Having said that though, isn't early serial support sort of mandatory anyway?
> 
The point is not to specify if a superio has early serial. It is to
specify which of the different superio's early serial will get compiled
in, and used.

Alex



From joe at settoplinux.org  Thu Mar  3 01:15:44 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 02 Mar 2011 19:15:44 -0500
Subject: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard
In-Reply-To: <4D6EBE99.6050106@gmail.com>
References: <4D5C5664.8040601@gmail.com>	<4D66673D.1030004@gmail.com>	<4D6EA744.6030308@gmail.com>	<20110302213811.27526.qmail@stuge.se>	<4D6EB96D.40508@settoplinux.org>
	<4D6EBE99.6050106@gmail.com>
Message-ID: <4D6EDDB0.3000003@settoplinux.org>

On 03/02/2011 05:03 PM, Alex G. wrote:
> On 03/02/2011 11:41 PM, Joseph Smith wrote:
>> On 03/02/2011 04:38 PM, Peter Stuge wrote:
>>> Alex G. wrote:
>>>> Add support for ASUS K8X-X SE motherboard.
>>> ..
>>>> Linux cannot complete booting.
>>>
>>> Also not with acpi=off so that it uses the mptable?
>>>
> Yes. It fails to work with acpi, mptable, and pirq table. That means [no
> option], "acpi=off", and "acpi=off noapic" respectively.
>
>>> Basically the code isn't ready yet.
>>>
> I explained the issue in more detail in my first email qith this patch,
> that I had sent a while back.
>
>>> Maybe we should have a CONFIG_EXPERIMENTAL ?
>>>
> Alright, but don't mind my asking, how exactly do we do this?
>
>> Alex why don't you leave acpi out for now, Linux doesn't need it to
>> boot. I would concentrate on your IRQ routing issue.
>>
> I haven't even touched the ACPI in over month. I'm testing with
> "acpi=off". The problem doesn't seem to be IRQ routing, as in routing,
> but the IOAPIC refusing to work the way it should work. I've explained
> this in more detail in my initial posting.
>
> I'm waiting for the friend who owns this board to pick it up any day
> now, so I doubt I will be able to finish it. I've been spinning in
> circles for a very long time now. If I can't get it ready, I'd like the
> next person who tries to port this board to already have my work as a
> starting point.
>
Alex have you tried adding irqpoll to your command line? It may give you 
some clues?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From peter at stuge.se  Thu Mar  3 03:58:45 2011
From: peter at stuge.se (Peter Stuge)
Date: Thu, 3 Mar 2011 03:58:45 +0100
Subject: [coreboot] [PATCH] add PC87384 SuperIO
In-Reply-To: <1299077406-24752-1-git-send-email-svens@stackframe.org>
References: <1299077406-24752-1-git-send-email-svens@stackframe.org>
Message-ID: <20110303025845.4356.qmail@stuge.se>

Sven Schnelle wrote:
> Signed-off-by: Sven Schnelle <svens at stackframe.org>

Acked-by: Peter Stuge <peter at stuge.se>



From Patrick.Georgi at secunet.com  Thu Mar  3 08:35:52 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Thu, 3 Mar 2011 08:35:52 +0100
Subject: [coreboot] [PATCH] Proposal for dealing with superio *.c
	includes
In-Reply-To: <4D6ECD7F.2070207@gmail.com>
References: <AANLkTi=-wMh8V+T9VxqFV7LfX7MPkfQAGA++GjQe+Dt+@mail.gmail.com>
	<4D6ECD7F.2070207@gmail.com>
Message-ID: <1299137752.2446.4.camel@linux-0a8x.site>

Am Donnerstag, den 03.03.2011, 01:06 +0200 schrieb Alex G.:
> So you have:
> 	select SUPERIO_KEITH875H
> 	select SUPERIO_ALEX666G
> 	select SUPERIO_ALEX666G_HAS_EARLY_SERIAL
> 
> > Having said that though, isn't early serial support sort of mandatory anyway?
> > 
> The point is not to specify if a superio has early serial. It is to
> specify which of the different superio's early serial will get compiled
> in, and used.
The chipset components in Kconfig could be derived from the
devicetree.cb (statically, on config time or before) - this would
simplify board config a bit by reducing duplication.

Early serial could be managed with a new keyword there
("chip superio/foo/bar early")

Thoughts?

Patrick
-- 
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
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From patrick at georgi-clan.de  Thu Mar  3 08:41:15 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 03 Mar 2011 08:41:15 +0100
Subject: [coreboot] =?utf-8?q?how_to_deal_with_large_romstage_size=3F?=
In-Reply-To: <201103021626233438401@163.com >
References: <AANLkTi=apQevBJ1zU-600RPtVogY_m38ZP8B+UedPooH@mail.gmail.com>, 
	<AANLkTikfNYEKmuR3K15BidV+9mmsJzz-47aAm1f6QiHZ@mail.gmail.com>, 
	<201103020947121258043@163.com, >, 
	<4D6DF67A.5070907@coreboot.org> <201103021626233438401@163.com >
Message-ID: <5af2f8b8a978a7a71f841a502ed8307c@localhost>


On Wed, 2 Mar 2011 16:26:26 +0800, "zxy__1127" <zxy__1127 at 163.com > wrote:
> it's based on D945gclf, but MRC is under NDA, :-(
Just to prevent any surprises: coreboot is licensed under the terms of the
GPL (version 2).
It won't be easy to develop a product that is distributable under both the
terms of the GPL and the MRC's licensing terms.


Patrick



From svn at coreboot.org  Thu Mar  3 09:29:04 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Mar 2011 09:29:04 +0100
Subject: [coreboot] [commit] r6427 - in trunk/src/superio/nsc: . pc87384
Message-ID: <E1Pv3uC-0003ym-CQ@ra.coresystems.de>

Author: svens
Date: Thu Mar  3 09:29:03 2011
New Revision: 6427
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6427

Log:
add PC87384 SuperIO

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>

Added:
   trunk/src/superio/nsc/pc87384/
   trunk/src/superio/nsc/pc87384/Makefile.inc
      - copied, changed from r6425, trunk/src/superio/nsc/Makefile.inc
   trunk/src/superio/nsc/pc87384/chip.h
   trunk/src/superio/nsc/pc87384/pc87384.h
   trunk/src/superio/nsc/pc87384/superio.c
Modified:
   trunk/src/superio/nsc/Kconfig
   trunk/src/superio/nsc/Makefile.inc

Modified: trunk/src/superio/nsc/Kconfig
==============================================================================
--- trunk/src/superio/nsc/Kconfig	Wed Mar  2 20:56:28 2011	(r6426)
+++ trunk/src/superio/nsc/Kconfig	Thu Mar  3 09:29:03 2011	(r6427)
@@ -30,6 +30,8 @@
 	bool
 config SUPERIO_NSC_PC87382
 	bool
+config SUPERIO_NSC_PC87384
+	bool
 config SUPERIO_NSC_PC87392
 	bool
 config SUPERIO_NSC_PC87417

Modified: trunk/src/superio/nsc/Makefile.inc
==============================================================================
--- trunk/src/superio/nsc/Makefile.inc	Wed Mar  2 20:56:28 2011	(r6426)
+++ trunk/src/superio/nsc/Makefile.inc	Thu Mar  3 09:29:03 2011	(r6427)
@@ -23,6 +23,7 @@
 subdirs-y += pc87360
 subdirs-y += pc87366
 subdirs-y += pc87382
+subdirs-y += pc87384
 subdirs-y += pc87392
 subdirs-y += pc87417
 subdirs-y += pc87427

Copied and modified: trunk/src/superio/nsc/pc87384/Makefile.inc (from r6425, trunk/src/superio/nsc/Makefile.inc)
==============================================================================
--- trunk/src/superio/nsc/Makefile.inc	Tue Mar  1 23:02:37 2011	(r6425, copy source)
+++ trunk/src/superio/nsc/pc87384/Makefile.inc	Thu Mar  3 09:29:03 2011	(r6427)
@@ -1,11 +1,12 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
 ##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,14 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-subdirs-y += pc8374
-subdirs-y += pc87309
-subdirs-y += pc87351
-subdirs-y += pc87360
-subdirs-y += pc87366
-subdirs-y += pc87382
-subdirs-y += pc87392
-subdirs-y += pc87417
-subdirs-y += pc87427
-subdirs-y += pc97307
-subdirs-y += pc97317
+ramstage-$(CONFIG_SUPERIO_NSC_PC87384) += superio.c
+

Added: trunk/src/superio/nsc/pc87384/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87384/chip.h	Thu Mar  3 09:29:03 2011	(r6427)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_NSC_PC87384_CHIP_H
+#define SUPERIO_NSC_PC87384_CHIP_H
+
+#include <uart8250.h>
+extern struct chip_operations superio_nsc_pc87384_ops;
+
+struct superio_nsc_pc87384_config {
+	struct uart8250 com1, com2;
+};
+
+#endif

Added: trunk/src/superio/nsc/pc87384/pc87384.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87384/pc87384.h	Thu Mar  3 09:29:03 2011	(r6427)
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_NSC_PC87384_H
+#define SUPERIO_NSC_PC87384_H
+
+#define PC87384_PP   0x01
+#define PC87384_SP2  0x02
+#define PC87384_SP1  0x03
+#define PC87384_GPIO 0x07
+#endif

Added: trunk/src/superio/nsc/pc87384/superio.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/superio/nsc/pc87384/superio.c	Thu Mar  3 09:29:03 2011	(r6427)
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "pc87384.h"
+
+static void init(device_t dev)
+{
+	struct superio_nsc_pc87384_config *conf = dev->chip_info;
+	struct resource *res0;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.pnp.device) {
+	case PC87384_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case PC87384_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+
+	case PC87384_GPIO:
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, PC87384_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0} },
+	{ &ops, PC87384_SP1,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } },
+	{ &ops, PC87384_SP2,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } },
+	{ &ops, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nsc_pc87384_ops = {
+	CHIP_NAME("NSC PC87384 Super I/O")
+	.enable_dev = enable_dev,
+};



From svens at stackframe.org  Thu Mar  3 09:32:47 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Thu, 03 Mar 2011 09:32:47 +0100
Subject: [coreboot] [PATCH] add PC87384 SuperIO
In-Reply-To: <20110303025845.4356.qmail@stuge.se> (Peter Stuge's message of
	"Thu\, 3 Mar 2011 03\:58\:45 +0100")
References: <1299077406-24752-1-git-send-email-svens@stackframe.org>
	<20110303025845.4356.qmail@stuge.se>
Message-ID: <87ipw061u8.fsf@begreifnix.stackframe.org>

Peter Stuge <peter at stuge.se> writes:

> Sven Schnelle wrote:
>> Signed-off-by: Sven Schnelle <svens at stackframe.org>
>
> Acked-by: Peter Stuge <peter at stuge.se>

r6427.

Thanks,

Sven.



From svens at stackframe.org  Thu Mar  3 09:37:33 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Thu, 03 Mar 2011 09:37:33 +0100
Subject: [coreboot] [PATCH] Proposal for dealing with superio *.c
	includes
In-Reply-To: <AANLkTi=-wMh8V+T9VxqFV7LfX7MPkfQAGA++GjQe+Dt+@mail.gmail.com>
	(Keith Hui's message of "Wed\, 2 Mar 2011 18\:01\:28 -0500")
References: <AANLkTi=-wMh8V+T9VxqFV7LfX7MPkfQAGA++GjQe+Dt+@mail.gmail.com>
Message-ID: <87ei6o61ma.fsf@begreifnix.stackframe.org>

Hi Keith,

Keith Hui <buurin at gmail.com> writes:

>> Option C with GPLv2+ licensing.
>
> A few quick things:
>
> SUPERIO_FINTEK_F81865F_HAS_EARLY_SERIAL seems long-winded for a name.
>
> I prefer to define CONFIG_SUPERIO_HAS_EARLY_SERIAL (or even just
> CONFIG_HAS_EARLY_SERIAL) within the superio Kconfig and not in
> mainboard Kconfig. This I think would be a per-superio setting. While
> we're at it, have we seen a board with 2+ superios?

Depends on what the definition of 'one Board' is. :) One example of
having more than one superio is the Lenovo X60/T60 - both have one
superio in the Laptop, and one in the Docking station. You can't
use the serial Port in the Laptop for an early console without
soldering, but that's one practically example of having more
than one superio.

I would prefer to add such settings to devicetree.cb - Kconfig isn't the
right right place for it IMHO, and isn't flexible enough.

Sven.



From mr.nuke.me at gmail.com  Thu Mar  3 09:40:38 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 03 Mar 2011 10:40:38 +0200
Subject: [coreboot] [PATCH] Proposal for dealing with superio *.c
	includes
In-Reply-To: <1299137752.2446.4.camel@linux-0a8x.site>
References: <AANLkTi=-wMh8V+T9VxqFV7LfX7MPkfQAGA++GjQe+Dt+@mail.gmail.com>
	<4D6ECD7F.2070207@gmail.com>
	<1299137752.2446.4.camel@linux-0a8x.site>
Message-ID: <4D6F5406.3090407@gmail.com>

On 03/03/2011 09:35 AM, Georgi, Patrick wrote:
> The chipset components in Kconfig could be derived from the
> devicetree.cb (statically, on config time or before) - this would
> simplify board config a bit by reducing duplication.
> 
> Early serial could be managed with a new keyword there
> ("chip superio/foo/bar early")
> 
> Thoughts?
I like the idea. It's long term, and cleaner.

            chip superio/foo/bar		# Super I/O
              device pnp 2e.1 on		# Com1
                io 0x60 = 0x3f8
                irq 0x70 = 4
                serial_console
              end

So not only would we specify that the superio hosts the serial console,
but also at which address that is, eliminating the need for
#define SERIAL_DEV PNP_DEV(0x2e, FOOBAR_SP1)
in romstage.c

+1

Alex



From sh4r4d at gmail.com  Thu Mar  3 10:44:06 2011
From: sh4r4d at gmail.com (sh4r4d at gmail.com)
Date: Thu, 03 Mar 2011 15:14:06 +0530
Subject: [coreboot] Help for motherboard
References: <86pqqouuco.fsf@personal.machine.of.sharard.com>
	<4D5FD0F9.10407@gmail.com>
	<86hbc0ufkg.fsf@personal.machine.of.sharard.com>
	<4D6004A4.9050409@gmail.com>
Message-ID: <ryld3m8o7x5.fsf@personal.machine.of.sharard.com>

On Sat, Feb 19 2011, Alex G. wrote:

> On 02/19/2011 06:58 PM, sh4r4d at gmail.com wrote:
>> 
>> I wanted general purpose regular desktop for programming, internet,
>> GNU/Linux with common servers dovecote, tomcat, apache etc
>> 
> Probably a socket AM2+ board will be best for you if you want to run
> coreboot.
>
> The Gigabyte GA-MA785GMT-UD2H is the only AM3 board supported. Someone
> recently had a problem getting it to run, but at worst, it needs a bit
> of tweaking. It has a COM port header, so we can use that to debug if
> something may not be working. It doesn't include the adapter for the com
> port, but that should be cheap to get.
>
> http://www.coreboot.org/GIGABYTE_GA-MA785GMT-UD2H
>
> The board has 4 hardware versions, so you may encounter issues depending
> on which version you get. I'd definitely suggest AM3 versus the older
> AM2/AM2+.
>
> You can also pick your favorite board and port it (which we'd all love :p ).
>

I have inquired here in shop they have told me newer 
board in
      GIGABYTE_GA-MA785GMT-US2H
than
      GIGABYTE_GA-MA785GMT-UD2H

(change in one letter `D' to `S')      

So I wanted to know if I have to purchase `GIGABYTE_GA-MA785GMT-US2H'
as `GIGABYTE_GA-MA785GMT-UD2H' is not available, Could it be easy
to get coreboot in it as `GIGABYTE_GA-MA785GMT-UD2H' have been already
supported, might be it is a newer version of `GIGABYTE_GA-MA785GMT-UD2H'?

Thanks Alex, Scott and Coreboot for detailed answers.

-- 
Regards,
-sharad




From nrubinstein at proformatique.com  Thu Mar  3 12:20:43 2011
From: nrubinstein at proformatique.com (=?utf-8?Q?No=C3=A9_Rubinstein?=)
Date: Thu, 3 Mar 2011 12:20:43 +0100 (CET)
Subject: [coreboot] Working on support for the Tolapai
In-Reply-To: <ryld3m8o7x5.fsf@personal.machine.of.sharard.com>
Message-ID: <1165634880.59164.1299151243082.JavaMail.root@Paperboy>

Hi,

I'm currently working on improving the support in Coreboot for the Intel Truxton, which is an EVB for Intel EP80579 (codename Tolapai). I'm trying to make it more agnostic with regards to which RAM modules can be used. Right now, it supports only some ECC modules.

I was able to get the board running with a Hynix HYMP564P72BP8-Y5 module, but I got into strange behaviour, as I only got the boot to work after adding two print statements in the RAM init (!). When trying to make modifications to support other boards, I got into similarly seemingly undeterministic failures: that is Coreboot failing during or little before the raminit, at random points (including during the execution of print statements). I'm not currently aware of where the problem comes from; I suppose it might be a compiler problem, or a cache problem, or something else entirely. Any idea about this problem? I don't understand the coreboot build process very well yet; is this part compiled with GCC?

It might not be related, but I have been able to get to the end of the before-ram code by adding the following to enable_smbus in src/southbridge/intel/i3100/early_smbus.c:
        // Taken from the i82801ex code
        /* clear any lingering errors, so the transaction will run */
        outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);

With the info I have at disposition, I will probably be able to get a better support for the RAM init part. As it has been based on DDR1 init code and is used for DDR2, I think it is a good idea to rewrite it or to replace it with something derived from the i945 raminit code. Any thought on the matter?

Thanks,
--
No? Rubinstein
Proformatique (groupe Avencall) - XiVO IPBX OpenHardware
10 bis, rue Lucien VOILIN - 92800 Puteaux
T?l. : +33 (0)1 41 38 99 60 ext 123
Fax. : +33 (0)1 41 38 99 70



From buurin at gmail.com  Thu Mar  3 15:49:09 2011
From: buurin at gmail.com (Keith Hui)
Date: Thu, 3 Mar 2011 09:49:09 -0500
Subject: [coreboot] [PATCH] Proposal for dealing with superio *.c
	includes
In-Reply-To: <4D6F5406.3090407@gmail.com>
References: <AANLkTi=-wMh8V+T9VxqFV7LfX7MPkfQAGA++GjQe+Dt+@mail.gmail.com>
	<4D6ECD7F.2070207@gmail.com>
	<1299137752.2446.4.camel@linux-0a8x.site>
	<4D6F5406.3090407@gmail.com>
Message-ID: <AANLkTinaPjyroLyQ7BbyxodX1AXjbVmYeGG79KyKU9gc@mail.gmail.com>

I like this solution too. Just that it requires hacking sconfig, and
I'm not even close to qualified to actually do it. :)

And this requires sconfig to produce some other output for romstage as
well. The hardware tree it produces is currently only used during
ramstage.

While we're on sconfig, devicetree, superio and romstage, can we add a
facility where I can declare some known, fixed initialization
sequences that needs to be programmed into certain devices?

Suppose my new board requires 0x00 to be written into pnp device 2e.5,
registers 0xf0-0xf5. Can we make it so that it will accept this
declaration, and do it during romstage?

If I need to do it now, I'll need to hijack either of io and drq for
it and can only do it when pnp is initialized in ramstage.

            chip superio/foo/bar                # Super I/O
              device pnp 2e.5 on                # PME
                reg 0xf0 = 0x00
                reg 0xf1 = 0x00
                reg 0xf2 = 0x00
                reg 0xf3 = 0x00
                reg 0xf4 = 0x00
                reg 0xf5 = 0x00
              end

Thanks

On Thu, Mar 3, 2011 at 3:40 AM, Alex G. <mr.nuke.me at gmail.com> wrote:
> On 03/03/2011 09:35 AM, Georgi, Patrick wrote:
>> The chipset components in Kconfig could be derived from the
>> devicetree.cb (statically, on config time or before) - this would
>> simplify board config a bit by reducing duplication.
>>
>> Early serial could be managed with a new keyword there
>> ("chip superio/foo/bar early")
>>
>> Thoughts?
> I like the idea. It's long term, and cleaner.
>
> ? ? ? ? ? ?chip superio/foo/bar ? ? ? ? ? ? ? ?# Super I/O
> ? ? ? ? ? ? ?device pnp 2e.1 on ? ? ? ? ? ? ? ?# Com1
> ? ? ? ? ? ? ? ?io 0x60 = 0x3f8
> ? ? ? ? ? ? ? ?irq 0x70 = 4
> ? ? ? ? ? ? ? ?serial_console
> ? ? ? ? ? ? ?end
>
> So not only would we specify that the superio hosts the serial console,
> but also at which address that is, eliminating the need for
> #define SERIAL_DEV PNP_DEV(0x2e, FOOBAR_SP1)
> in romstage.c
>
> +1
>
> Alex
>



From mr.nuke.me at gmail.com  Thu Mar  3 16:08:55 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 03 Mar 2011 17:08:55 +0200
Subject: [coreboot] [PATCH] Proposal for dealing with superio *.c
	includes
In-Reply-To: <AANLkTinaPjyroLyQ7BbyxodX1AXjbVmYeGG79KyKU9gc@mail.gmail.com>
References: <AANLkTi=-wMh8V+T9VxqFV7LfX7MPkfQAGA++GjQe+Dt+@mail.gmail.com>	<4D6ECD7F.2070207@gmail.com>	<1299137752.2446.4.camel@linux-0a8x.site>	<4D6F5406.3090407@gmail.com>
	<AANLkTinaPjyroLyQ7BbyxodX1AXjbVmYeGG79KyKU9gc@mail.gmail.com>
Message-ID: <4D6FAF07.1060208@gmail.com>

On 03/03/2011 04:49 PM, Keith Hui wrote:
> I like this solution too. Just that it requires hacking sconfig, and
> I'm not even close to qualified to actually do it. :)
> 
> And this requires sconfig to produce some other output for romstage as
> well. The hardware tree it produces is currently only used during
> ramstage.
> 
> While we're on sconfig, devicetree, superio and romstage, can we add a
> facility where I can declare some known, fixed initialization
> sequences that needs to be programmed into certain devices?
> 
And have the same sequence in every devicetree.cb that uses that device?
That's code duplication, which is exactly what we are trying to avoid.
Imagine if we find a problem with a superio used in 30 boards. Instead
of changing one file, we have 30 devicetree.cb .

> Suppose my new board requires 0x00 to be written into pnp device 2e.5,
> registers 0xf0-0xf5. Can we make it so that it will accept this
> declaration, and do it during romstage?
> 
On second thought, it might be a good idea if and only if your board
requires a _different_ sequence, and anything in devicetree.cb would
override the default one.

> If I need to do it now, I'll need to hijack either of io and drq for
> it and can only do it when pnp is initialized in ramstage.
> 
>             chip superio/foo/bar                # Super I/O
>               device pnp 2e.5 on                # PME
>                 reg 0xf0 = 0x00
>                 reg 0xf1 = 0x00
>                 reg 0xf2 = 0x00
>                 reg 0xf3 = 0x00
>                 reg 0xf4 = 0x00
>                 reg 0xf5 = 0x00
>               end
> 
I'm not seeing any generic "reg" infrastructure. It doesn't look that
hard to extend though.

However, devicetree.cb _seems_ to deal exclusively with ramstage. Not
too sure how we can extend that to romstage.

Alex



From svn at coreboot.org  Thu Mar  3 16:36:08 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Mar 2011 16:36:08 +0100
Subject: [coreboot] [commit] r6428 - trunk/src/mainboard/msi/ms7135
Message-ID: <E1PvAZU-0005cc-TP@ra.coresystems.de>

Author: jakllsch
Date: Thu Mar  3 16:36:08 2011
New Revision: 6428
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6428

Log:
Configure PCIe lanes on ms7135 as original BIOS does.

Signed-off-by: <jakllsch at kollasch.net>
Acked-by: <jakllsch at kollasch.net>

Modified:
   trunk/src/mainboard/msi/ms7135/Kconfig

Modified: trunk/src/mainboard/msi/ms7135/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7135/Kconfig	Thu Mar  3 09:29:03 2011	(r6427)
+++ trunk/src/mainboard/msi/ms7135/Kconfig	Thu Mar  3 16:36:08 2011	(r6428)
@@ -58,4 +58,8 @@
 	int
 	default 13
 
+config CK804_PCI_E_X
+	int
+	default 0
+
 endif # BOARD_MSI_MS7135



From nrubinstein at proformatique.com  Thu Mar  3 16:46:58 2011
From: nrubinstein at proformatique.com (=?utf-8?Q?No=C3=A9_Rubinstein?=)
Date: Thu, 3 Mar 2011 16:46:58 +0100 (CET)
Subject: [coreboot] Working on support for the Tolapai
In-Reply-To: <1165634880.59164.1299151243082.JavaMail.root@Paperboy>
Message-ID: <72146176.59513.1299167218025.JavaMail.root@Paperboy>

> When trying to make modifications to support other boards,
> I got into similarly seemingly undeterministic failures
This was to be read "When trying to make modification to
support other *RAM modules*".

After further testing, I can confirm that the random failure
problem has *not* been fixed by my SMBus init change.

I still get random failures (i.e. no more serial output, POST
code 80) during the RAM init, and the behaviour changes when
adding or removing print statements.

The Truxton romstage is build with romcc. Is it very likely
that this is a bug with romcc? As it looks like support for
non-CAR might be dropped in the future, I might port the Truxton
romstage to gcc. Any directions/how-to on the matter?
I am not sure what exactly needs to be done, and how much time
it would take.

--
No? Rubinstein
Proformatique (groupe Avencall) - XiVO IPBX OpenHardware
10 bis, rue Lucien VOILIN - 92800 Puteaux
T?l. : +33 (0)1 41 38 99 60 ext 123
Fax. : +33 (0)1 41 38 99 70

----- Mail original -----
De: "No? Rubinstein" <nrubinstein at proformatique.com>
?: coreboot at coreboot.org
Envoy?: Jeudi 3 Mars 2011 12:20:43
Objet: [coreboot] Working on support for the Tolapai

Hi,

I'm currently working on improving the support in Coreboot for the Intel Truxton, which is an EVB for Intel EP80579 (codename Tolapai). I'm trying to make it more agnostic with regards to which RAM modules can be used. Right now, it supports only some ECC modules.

I was able to get the board running with a Hynix HYMP564P72BP8-Y5 module, but I got into strange behaviour, as I only got the boot to work after adding two print statements in the RAM init (!). When trying to make modifications to support other boards, I got into similarly seemingly undeterministic failures: that is Coreboot failing during or little before the raminit, at random points (including during the execution of print statements). I'm not currently aware of where the problem comes from; I suppose it might be a compiler problem, or a cache problem, or something else entirely. Any idea about this problem? I don't understand the coreboot build process very well yet; is this part compiled with GCC?

It might not be related, but I have been able to get to the end of the before-ram code by adding the following to enable_smbus in src/southbridge/intel/i3100/early_smbus.c:
        // Taken from the i82801ex code
        /* clear any lingering errors, so the transaction will run */
        outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);

With the info I have at disposition, I will probably be able to get a better support for the RAM init part. As it has been based on DDR1 init code and is used for DDR2, I think it is a good idea to rewrite it or to replace it with something derived from the i945 raminit code. Any thought on the matter?

Thanks,
--
No? Rubinstein
Proformatique (groupe Avencall) - XiVO IPBX OpenHardware
10 bis, rue Lucien VOILIN - 92800 Puteaux
T?l. : +33 (0)1 41 38 99 60 ext 123
Fax. : +33 (0)1 41 38 99 70

-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot



From jakllsch at kollasch.net  Thu Mar  3 17:10:14 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Thu, 3 Mar 2011 16:10:14 +0000
Subject: [coreboot] [patch] improve ck804 HPET resource handling
Message-ID: <20110303161014.GA9626@tarantulon.kollasch.net>

Improve ck804 IOAPIC and HPET resource handling.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
-----
-------------- next part --------------
Index: src/southbridge/nvidia/ck804/lpc.c
===================================================================
--- src/southbridge/nvidia/ck804/lpc.c	(revision 6427)
+++ src/southbridge/nvidia/ck804/lpc.c	(working copy)
@@ -104,15 +104,6 @@
 		pci_write_config8(dev, 0x6d, new);
 }
 
-static void enable_hpet(struct device *dev)
-{
-	unsigned long hpet_address;
-
-	pci_write_config32(dev, 0x44, 0xfed00001);
-	hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
-	printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address);
-}
-
 unsigned pm_base = 0;
 
 static void lpc_init(device_t dev)
@@ -130,12 +121,6 @@
 		return;
 #endif
 
-#if 0
-	/* Posted memory write enable */
-	byte = pci_read_config8(dev, 0x46);
-	pci_write_config8(dev, 0x46, byte | (1 << 0));
-#endif
-
 	/* Power after power fail */
 	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
@@ -166,12 +151,6 @@
 	pci_write_config8(dev, 0xe8, byte);
 #endif
 
-	/* Enable Error reporting. */
-	/* Set up sync flood detected. */
-	byte = pci_read_config8(dev, 0x47);
-	byte |= (1 << 1);
-	pci_write_config8(dev, 0x47, byte);
-
 	/* Set up NMI on errors. */
 	byte = inb(0x70);		/* RTC70 */
 	byte_old = byte;
@@ -190,9 +169,6 @@
 	/* Initialize ISA DMA. */
 	isa_dma_init();
 
-	/* Initialize the High Precision Event Timers (HPET). */
-	enable_hpet(dev);
-
 	rom_dummy_write(dev);
 }
 
@@ -205,6 +181,9 @@
 	/* We got one for APIC, or one more for TRAP. */
 	pci_dev_read_resources(dev);
 
+	/* HPET */
+	pci_get_resource(dev, 0x44);
+
 	/* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
 	for (index = 0x60; index <= 0x68; index += 4)	/* We got another 3. */
 		pci_get_resource(dev, index);
@@ -223,12 +202,44 @@
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = IO_APIC_ADDR;
-	res->size = 0x00001000;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	if (dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE) {
+		res = find_resource(dev, 0x14); /* IOAPIC */
+		if (res) {
+			res->base = IO_APIC_ADDR;
+			res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+		}
+
+		res = find_resource(dev, 0x44); /* HPET */
+		if (res) {
+			res->base = 0xfed00000;
+			res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+		}
+	}
 }
 
+static void ck804_lpc_set_resources(device_t dev)
+{
+	struct resource *res;
+
+	pci_dev_set_resources(dev);
+
+	/* APIC */
+	res = find_resource(dev, 0x14);
+	if (res) {
+		pci_write_config32(dev, 0x14, res->base);
+		res->flags |= IORESOURCE_STORED;
+		report_resource_stored(dev, res, "");
+	}
+
+	/* HPET */
+	res = find_resource(dev, 0x44);
+	if (res) {
+		pci_write_config32(dev, 0x44, res->base|1);
+		res->flags |= IORESOURCE_STORED;
+		report_resource_stored(dev, res, "");
+	}
+}
+
 /**
  * Enable resources for children devices.
  *
@@ -299,7 +310,7 @@
 
 static struct device_operations lpc_ops = {
 	.read_resources   = ck804_lpc_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.set_resources    = ck804_lpc_set_resources,
 	.enable_resources = ck804_lpc_enable_resources,
 	.init             = lpc_init,
 	.scan_bus         = scan_static_bus,

From svn at coreboot.org  Thu Mar  3 17:28:40 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Mar 2011 17:28:40 +0100
Subject: [coreboot] build service results for r6428
Message-ID: <E1PvBOK-0001Az-4F@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "jakllsch" checked in revision 6428 to
the coreboot repository. This caused the following 
changes:

Change Log:
Configure PCIe lanes on ms7135 as original BIOS does.

Signed-off-by: <jakllsch at kollasch.net>
Acked-by: <jakllsch at kollasch.net>


Build Log:
Compilation of digitallogic:adl855pc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6428&device=adl855pc&vendor=digitallogic&num=2


If something broke during this checkin please be a pain 
in jakllsch's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Thu Mar  3 20:08:23 2011
From: peter at stuge.se (Peter Stuge)
Date: Thu, 3 Mar 2011 20:08:23 +0100
Subject: [coreboot] [patch] improve ck804 HPET resource handling
In-Reply-To: <20110303161014.GA9626@tarantulon.kollasch.net>
References: <20110303161014.GA9626@tarantulon.kollasch.net>
Message-ID: <20110303190823.6744.qmail@stuge.se>

Jonathan A. Kollasch wrote:
> Improve ck804 IOAPIC and HPET resource handling.
> 
> Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>

Acked-by: Peter Stuge <peter at stuge.se>



From chertovs at gmail.com  Thu Mar  3 20:08:41 2011
From: chertovs at gmail.com (Vitaly Chertovskih)
Date: Thu, 3 Mar 2011 22:08:41 +0300
Subject: [coreboot] Troubles with 17'' WXGA on Roda RK886EX
Message-ID: <AANLkTimm2OJhUz_Ogh682yUZusJB3inkEkePtwoiJ96x@mail.gmail.com>

Hi!

I'm experiencing some troubles with VGA on notebook "Roda RF8". That
notebook's motherboard and other specification is exact to Roda RK886EX,
only the screen is larger (17'' WXGA 1440x900).
On that week I installed coreboot on Roda RK886EX, it starts perfectly. But
when i flashed the same coreboot on notebook RF8 - the screen is lightened,
but remains blank. When i connect external LCD - it(external) works well
with coreboot. So, i think, that the trouble is in initialization of that
internal widescreen LCD.

Roda RK886EX have LCD 15.1? XGA (1024x768) - works perfect.
Roda RF8 - 17'' WXGA 1440x900 - blank (but lightened) screen (other init and
OS booting is perfect with external LCD)

The log file says nothing - when coreboot or seabios calls vga.bin - all is
ok, like on Roda RK886EX.

Please, help me. Where and how i can fix that?

P.S.

I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS image
(I download it from coreboot.org), and including VGA onboard rom, grabbed
from /dev/mem as described in howtos on coreboot.org.

I include my log from COM1.
-------------- next part --------------
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?



coreboot-4.0-r6411- ??? ???  3 23:00:03 MSK 2011 starting...



Mobile Intel(R) 82945GM/GME Express Chipset

(G)MCH capable of up to FSB 800 MHz

(G)MCH capable of up to DDR2-667

Setting up static southbridge registers... GPIOS... done.

Disabling Watchdog reboot... done.

Setting up static northbridge registers... done.

Waiting for MCHBAR to come up...ok

PM1_CNT: 00001c00

SMBus controller enabled.

Setting up RAM controller.

This mainboard supports Dual Channel Operation.

DDR II Channel 0 Socket 0: x8DDS

DDR II Channel 1 Socket 0: N/A

SLP S4# Assertion Width Violation.

Reset required.





coreboot-4.0-r6411- ??? ???  3 23:00:03 MSK 2011 starting...



Mobile Intel(R) 82945GM/GME Express Chipset

(G)MCH capable of up to FSB 800 MHz

(G)MCH capable of up to DDR2-667

Setting up static southbridge registers... GPIOS... done.

Disabling Watchdog reboot... done.

Setting up static northbridge registers... done.

Waiting for MCHBAR to come up...ok

PM1_CNT: 00001c00

SMBus controller enabled.

Setting up RAM controller.

This mainboard supports Dual Channel Operation.

DDR II Channel 0 Socket 0: x8DDS

DDR II Channel 1 Socket 0: N/A

Memory will be driven at 400MHz with CAS=3 clocks

tRAS = 9 cycles

tRP = 3 cycles

tRCD = 3 cycles

Refresh: 7.8us

tWR = 3 cycles

DIMM 0 side 0 = 1024 MB

DIMM 0 side 1 = 1024 MB

tRFC = 26 cycles

Setting Graphics Frequency... 

FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz

Setting Memory Frequency... CLKCFG=0x00010023, ok (unchanged)

Setting mode of operation for memory channels...Single Channel 0 only.

Programming Clock Crossing...MEM=400 FSB=667... ok

Setting RAM size... 

C0DRB = 0x40404020

C1DRB = 0x00000000

TOLUD = 0x0080

Setting row attributes... 

C0DRA = 0x0033

C1DRA = 0x0000

DIMM0 has 8 banks.

one dimm per channel config.. 

Initializing System Memory IO... 

Programming Dual Channel RCOMP

Table Index: 19

Programming DLL Timings... 

Enabling System Memory IO... 

jedec enable sequence: bank 0

jedec enable sequence: bank 1

bankaddr from bank size of rank 0

receive_enable_autoconfig() for channel 0

  find_strobes_low()

    set_receive_enable() medium=0x3, coarse=0x3

    set_receive_enable() medium=0x1, coarse=0x3

    set_receive_enable() medium=0x1, coarse=0x3

  find_strobes_edge()

    set_receive_enable() medium=0x1, coarse=0x3

  add_quarter_clock() mediumcoarse=0d fine=92

    set_receive_enable() medium=0x3, coarse=0x3

  find_preamble()

    set_receive_enable() medium=0x3, coarse=0x2

    set_receive_enable() medium=0x3, coarse=0x1

  add_quarter_clock() mediumcoarse=07 fine=12

  normalize()

    set_receive_enable() medium=0x0, coarse=0x2

RAM initialization finished.

Setting up Egress Port RCRB

Loading port arbitration table ...ok

Wait for VC1 negotiation ...ok

Setting up DMI RCRB

Wait for VC1 negotiation ...done..

Internal graphics: enabled

Waiting for DMI hardware...ok

Enabling PCI Express x16 Link

SLOTSTS: 0000

Disabling PCI Express x16 Link

Wait for link to enter detect state... ok

Setting up Root Complex Topology

Loading image.

Check CBFS header at fffeffe0

magic is 4f524243

Found CBFS header at fffeffe0

Check cmos_layout.bin

CBFS: follow chain: fff00000 + 28 + 54f + align -> fff00580

Check pci8086,27ae.rom

CBFS: follow chain: fff00580 + 38 + 10000 + align -> fff105c0

Check fallback/coreboot_ram

Stage: loading fallback/coreboot_ram @ 0x100000 (409600 bytes), entry @ 0x100000

Stage: done loading.

Jumping to image.

POST: 0x80

POST: 0x39

coreboot-4.0-r6411- ??? ???  3 23:00:03 MSK 2011 booting...

POST: 0x40

Enumerating buses...

Show all devs...Before device enumeration.

Root Device: enabled 1

APIC_CLUSTER: 0: enabled 1

APIC: 00: enabled 1

PCI_DOMAIN: 0000: enabled 1

PCI: 00:00.0: enabled 1

PCI: 00:1b.0: enabled 1

PCI: 00:1c.0: enabled 1

PCI: 00:1c.1: enabled 1

PCI: 00:1c.2: enabled 1

PCI: 00:1d.0: enabled 1

PCI: 00:1d.1: enabled 1

PCI: 00:1d.2: enabled 1

PCI: 00:1d.3: enabled 1

PCI: 00:1d.7: enabled 1

PCI: 00:1e.0: enabled 1

PCI: 00:03.0: enabled 1

PCI: 00:03.1: enabled 1

PCI: 00:03.2: enabled 1

PCI: 00:03.3: enabled 0

PCI: 00:1f.0: enabled 1

PNP: 002e.1: enabled 1

PNP: 002e.2: enabled 1

PNP: 002e.3: enabled 1

PNP: 002e.5: enabled 0

PNP: 00ff.1: enabled 1

PCI: 00:1f.2: enabled 1

PCI: 00:1f.3: enabled 1

Compare with tree...

Root Device: enabled 1

 APIC_CLUSTER: 0: enabled 1

  APIC: 00: enabled 1

 PCI_DOMAIN: 0000: enabled 1

  PCI: 00:00.0: enabled 1

  PCI: 00:1b.0: enabled 1

  PCI: 00:1c.0: enabled 1

  PCI: 00:1c.1: enabled 1

  PCI: 00:1c.2: enabled 1

  PCI: 00:1d.0: enabled 1

  PCI: 00:1d.1: enabled 1

  PCI: 00:1d.2: enabled 1

  PCI: 00:1d.3: enabled 1

  PCI: 00:1d.7: enabled 1

  PCI: 00:1e.0: enabled 1

   PCI: 00:03.0: enabled 1

   PCI: 00:03.1: enabled 1

   PCI: 00:03.2: enabled 1

   PCI: 00:03.3: enabled 0

  PCI: 00:1f.0: enabled 1

   PNP: 002e.1: enabled 1

   PNP: 002e.2: enabled 1

   PNP: 002e.3: enabled 1

   PNP: 002e.5: enabled 0

   PNP: 00ff.1: enabled 1

  PCI: 00:1f.2: enabled 1

  PCI: 00:1f.3: enabled 1

Display I/O: 0x35

scan_static_bus for Root Device

APIC_CLUSTER: 0 enabled

PCI_DOMAIN: 0000 enabled

PCI_DOMAIN: 0000 scanning...

PCI: pci_scan_bus for bus 00

POST: 0x24

PCI: 00:00.0 [8086/27ac] enabled

PCI: 00:02.0 [8086/27ae] enabled

PCI: 00:02.1 [8086/27a6] ops

PCI: 00:02.1 [8086/27a6] enabled

PCI: Static device PCI: 00:1b.0 not found, disabling it.

PCI: 00:1c.0 [8086/27d0] bus ops

PCI: 00:1c.0 [8086/27d0] enabled

PCI: Static device PCI: 00:1c.1 not found, disabling it.

PCI: Static device PCI: 00:1c.2 not found, disabling it.

PCI: 00:1c.3 [8086/27d6] bus ops

PCI: 00:1c.3 [8086/27d6] enabled

PCI: 00:1d.0 [8086/27c8] ops

PCI: 00:1d.0 [8086/27c8] enabled

PCI: 00:1d.1 [8086/27c9] ops

PCI: 00:1d.1 [8086/27c9] enabled

PCI: 00:1d.2 [8086/27ca] ops

PCI: 00:1d.2 [8086/27ca] enabled

PCI: 00:1d.3 [8086/27cb] ops

PCI: 00:1d.3 [8086/27cb] enabled

PCI: 00:1d.7 [8086/27cc] ops

PCI: 00:1d.7 [8086/27cc] enabled

PCI: 00:1e.0 [8086/2448] bus ops

PCI: 00:1e.0 [8086/2448] enabled

PCI: 00:1e.2 [8086/27de] ops

PCI: 00:1e.2 [8086/27de] enabled

PCI: 00:1f.0 [8086/27bd] bus ops

PCI: 00:1f.0 [8086/27bd] enabled

PCI: 00:1f.2 [8086/27c4] ops

PCI: 00:1f.2 [8086/27c4] enabled

PCI: 00:1f.3 [8086/27da] bus ops

PCI: 00:1f.3 [8086/27da] enabled

POST: 0x25

do_pci_scan_bridge for PCI: 00:1c.0

PCI: pci_scan_bus for bus 01

POST: 0x24

PCI: Using configuration type 1

POST: 0x25

PCI: pci_scan_bus returning with max=001

POST: 0x55

do_pci_scan_bridge returns max 1

do_pci_scan_bridge for PCI: 00:1c.3

PCI: pci_scan_bus for bus 02

POST: 0x24

PCI: 02:00.0 [10ec/8168] ops

PCI: 02:00.0 [10ec/8168] enabled

POST: 0x25

PCI: pci_scan_bus returning with max=002

POST: 0x55

do_pci_scan_bridge returns max 2

do_pci_scan_bridge for PCI: 00:1e.0

PCI: pci_scan_bus for bus 03

POST: 0x24

PCI: 03:03.0 [104c/ac8e] bus ops

PCI: 03:03.0 [104c/ac8e] enabled

PCI: 03:03.1 [104c/ac8e] bus ops

PCI: 03:03.1 [104c/ac8e] enabled

PCI: 03:03.2 [104c/802e] ops

PCI: 03:03.2 [104c/802e] enabled

PCI: 03:03.3 [104c/ac8f] disabled

POST: 0x25

do_pci_scan_bridge for PCI: 03:03.0

PCI: pci_scan_bus for bus 04

POST: 0x24

POST: 0x25

PCI: pci_scan_bus returning with max=004

POST: 0x55

do_pci_scan_bridge returns max 4

do_pci_scan_bridge for PCI: 03:03.1

PCI: pci_scan_bus for bus 05

POST: 0x24

POST: 0x25

PCI: pci_scan_bus returning with max=005

POST: 0x55

do_pci_scan_bridge returns max 5

PCI: pci_scan_bus returning with max=005

POST: 0x55

do_pci_scan_bridge returns max 5

scan_static_bus for PCI: 00:1f.0

PNP: 002e.1 enabled

PNP: 002e.2 enabled

PNP: 002e.3 enabled

PNP: 002e.5 disabled

PNP: 00ff.1 enabled

PNP: 00ff.0 enabled

scan_static_bus for PCI: 00:1f.0 done

scan_static_bus for PCI: 00:1f.3

scan_static_bus for PCI: 00:1f.3 done

PCI: pci_scan_bus returning with max=005

POST: 0x55

scan_static_bus for Root Device done

done

POST: 0x66

Setting up VGA for PCI: 00:02.0

Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000

Setting PCI_BRIDGE_CTL_VGA for bridge Root Device

Allocating resources...

Reading resources...

Root Device read_resources bus 0 link: 0

APIC_CLUSTER: 0 read_resources bus 0 link: 0

APIC: 00 missing read_resources

APIC_CLUSTER: 0 read_resources bus 0 link: 0 done

PCI_DOMAIN: 0000 read_resources bus 0 link: 0

PCI: 00:1c.0 read_resources bus 1 link: 0

PCI: 00:1c.0 read_resources bus 1 link: 0 done

PCI: 00:1c.3 read_resources bus 2 link: 0

PCI: 00:1c.3 read_resources bus 2 link: 0 done

PCI: 00:1e.0 read_resources bus 3 link: 0

PCI: 03:03.0 read_resources bus 4 link: 0

PCI: 03:03.0 read_resources bus 4 link: 0 done

PCI: 03:03.1 read_resources bus 5 link: 0

PCI: 03:03.1 read_resources bus 5 link: 0 done

PCI: 00:1e.0 read_resources bus 3 link: 0 done

PCI: 00:1f.0 read_resources bus 0 link: 0

PNP: 00ff.1 missing read_resources

PCI: 00:1f.0 read_resources bus 0 link: 0 done

PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done

Root Device read_resources bus 0 link: 0 done

Done reading resources.

Show resources in subtree (Root Device)...After reading.

 Root Device child on link 0 APIC_CLUSTER: 0

  APIC_CLUSTER: 0 child on link 0 APIC: 00

   APIC: 00

  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0

  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000

  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100

   PCI: 00:00.0

   PCI: 00:02.0

   PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10

   PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14

   PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18

   PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c

   PCI: 00:02.1

   PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10

   PCI: 00:1b.0

   PCI: 00:1c.0

   PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c

   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24

   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20

   PCI: 00:1c.1

   PCI: 00:1c.2

   PCI: 00:1c.3 child on link 0 PCI: 02:00.0

   PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c

   PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24

   PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20

    PCI: 02:00.0

    PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10

    PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18

    PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30

   PCI: 00:1d.0

   PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20

   PCI: 00:1d.1

   PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20

   PCI: 00:1d.2

   PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20

   PCI: 00:1d.3

   PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20

   PCI: 00:1d.7

   PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10

   PCI: 00:1e.0 child on link 0 PCI: 03:03.0

   PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c

   PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24

   PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20

    PCI: 03:03.0

    PCI: 03:03.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10

    PCI: 03:03.0 resource base 0 size 1000 align 2 gran 2 limit ffff flags 100 index 2c

    PCI: 03:03.0 resource base 0 size 1000 align 2 gran 2 limit ffff flags 100 index 34

    PCI: 03:03.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c

    PCI: 03:03.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24

    PCI: 03:03.1

    PCI: 03:03.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10

    PCI: 03:03.1 resource base 0 size 1000 align 2 gran 2 limit ffff flags 100 index 2c

    PCI: 03:03.1 resource base 0 size 1000 align 2 gran 2 limit ffff flags 100 index 34

    PCI: 03:03.1 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c

    PCI: 03:03.1 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24

    PCI: 03:03.2

    PCI: 03:03.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10

    PCI: 03:03.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14

    PCI: 03:03.3

   PCI: 00:1e.2

   PCI: 00:1e.2 resource base 0 size 200 align 9 gran 9 limit ffffffff flags 200 index 18

   PCI: 00:1e.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 1c

   PCI: 00:1f.0 child on link 0 PNP: 002e.1

   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000

   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100

   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3

    PNP: 002e.1

    PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60

    PNP: 002e.1 resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70

    PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74

    PNP: 002e.2

    PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60

    PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70

    PNP: 002e.3

    PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60

    PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70

    PNP: 002e.5

    PNP: 002e.5 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60

    PNP: 002e.5 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62

    PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70

    PNP: 00ff.1

    PNP: 00ff.0

   PCI: 00:1f.2

   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10

   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14

   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18

   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c

   PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20

   PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24

   PCI: 00:1f.3

   PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20

PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff

PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff

PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done

PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff

PCI: 02:00.0 10 *  [0x0 - 0xff] io

PCI: 00:1c.3 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done

PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff

PCI: 03:03.0 2c *  [0x0 - 0xfff] io

PCI: 03:03.0 34 *  [0x1000 - 0x1fff] io

PCI: 03:03.1 2c *  [0x2000 - 0x2fff] io

PCI: 03:03.1 34 *  [0x3000 - 0x3fff] io

PCI: 00:1e.0 compute_resources_io: base: 4000 size: 4000 align: 12 gran: 12 limit: ffff done

PCI: 00:1e.0 1c *  [0x0 - 0x3fff] io

PCI: 00:1c.3 1c *  [0x4000 - 0x4fff] io

PCI: 00:1d.0 20 *  [0x5000 - 0x501f] io

PCI: 00:1d.1 20 *  [0x5020 - 0x503f] io

PCI: 00:1d.2 20 *  [0x5040 - 0x505f] io

PCI: 00:1d.3 20 *  [0x5060 - 0x507f] io

PCI: 00:1f.3 20 *  [0x5080 - 0x509f] io

PCI: 00:1f.2 20 *  [0x50a0 - 0x50af] io

PCI: 00:02.0 14 *  [0x50b0 - 0x50b7] io

PCI: 00:1f.2 10 *  [0x50b8 - 0x50bf] io

PCI: 00:1f.2 18 *  [0x50c0 - 0x50c7] io

PCI: 00:1f.2 14 *  [0x50c8 - 0x50cb] io

PCI: 00:1f.2 1c *  [0x50cc - 0x50cf] io

PCI_DOMAIN: 0000 compute_resources_io: base: 50d0 size: 50d0 align: 12 gran: 0 limit: ffff done

PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff

PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff

PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done

PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff

PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done

PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff

PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done

PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff

PCI: 02:00.0 30 *  [0x0 - 0x1ffff] mem

PCI: 02:00.0 18 *  [0x20000 - 0x20fff] mem

PCI: 00:1c.3 compute_resources_mem: base: 21000 size: 100000 align: 20 gran: 20 limit: ffffffff done

PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff

PCI: 03:03.0 1c *  [0x0 - 0x1ffffff] prefmem

PCI: 03:03.1 1c *  [0x2000000 - 0x3ffffff] prefmem

PCI: 00:1e.0 compute_resources_prefmem: base: 4000000 size: 4000000 align: 20 gran: 20 limit: ffffffff done

PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff

PCI: 03:03.2 14 *  [0x0 - 0x3fff] mem

PCI: 03:03.0 24 *  [0x4000 - 0x2003fff] mem

PCI: 03:03.1 24 *  [0x2004000 - 0x4003fff] mem

PCI: 03:03.0 10 *  [0x4004000 - 0x4004fff] mem

PCI: 03:03.1 10 *  [0x4005000 - 0x4005fff] mem

PCI: 03:03.2 10 *  [0x4006000 - 0x40067ff] mem

PCI: 00:1e.0 compute_resources_mem: base: 4006800 size: 4100000 align: 20 gran: 20 limit: ffffffff done

PCI: 00:02.0 18 *  [0x0 - 0xfffffff] prefmem

PCI: 00:1e.0 20 *  [0x10000000 - 0x140fffff] mem

PCI: 00:1e.0 24 *  [0x14100000 - 0x180fffff] prefmem

PCI: 00:1c.3 20 *  [0x18100000 - 0x181fffff] mem

PCI: 00:02.0 10 *  [0x18200000 - 0x1827ffff] mem

PCI: 00:02.1 10 *  [0x18280000 - 0x182fffff] mem

PCI: 00:02.0 1c *  [0x18300000 - 0x1833ffff] mem

PCI: 00:1d.7 10 *  [0x18340000 - 0x183403ff] mem

PCI: 00:1f.2 24 *  [0x18340400 - 0x183407ff] mem

PCI: 00:1e.2 18 *  [0x18340800 - 0x183409ff] mem

PCI: 00:1e.2 1c *  [0x18340a00 - 0x18340aff] mem

PCI_DOMAIN: 0000 compute_resources_mem: base: 18340b00 size: 18340b00 align: 28 gran: 0 limit: ffffffff done

avoid_fixed_resources: PCI_DOMAIN: 0000

avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff

avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff

constrain_resources: PCI_DOMAIN: 0000

constrain_resources: PCI: 00:00.0

constrain_resources: PCI: 00:02.0

constrain_resources: PCI: 00:02.1

constrain_resources: PCI: 00:1c.0

constrain_resources: PCI: 00:1c.3

constrain_resources: PCI: 02:00.0

constrain_resources: PCI: 00:1d.0

constrain_resources: PCI: 00:1d.1

constrain_resources: PCI: 00:1d.2

constrain_resources: PCI: 00:1d.3

constrain_resources: PCI: 00:1d.7

constrain_resources: PCI: 00:1e.0

constrain_resources: PCI: 03:03.0

constrain_resources: PCI: 03:03.1

constrain_resources: PCI: 03:03.2

constrain_resources: PCI: 00:1e.2

constrain_resources: PCI: 00:1f.0

constrain_resources: PNP: 002e.1

constrain_resources: PNP: 002e.2

constrain_resources: PNP: 002e.3

constrain_resources: PNP: 00ff.1

constrain_resources: PNP: 00ff.0

constrain_resources: PCI: 00:1f.2

constrain_resources: PCI: 00:1f.3

avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff

	lim->base 00001000 lim->limit 0000ffff

avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff

	lim->base 00000000 lim->limit febfffff

Setting resources...

PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:50d0 align:12 gran:0 limit:ffff

Assigned: PCI: 00:1e.0 1c *  [0x1000 - 0x4fff] io

Assigned: PCI: 00:1c.3 1c *  [0x5000 - 0x5fff] io

Assigned: PCI: 00:1d.0 20 *  [0x6000 - 0x601f] io

Assigned: PCI: 00:1d.1 20 *  [0x6020 - 0x603f] io

Assigned: PCI: 00:1d.2 20 *  [0x6040 - 0x605f] io

Assigned: PCI: 00:1d.3 20 *  [0x6060 - 0x607f] io

Assigned: PCI: 00:1f.3 20 *  [0x6080 - 0x609f] io

Assigned: PCI: 00:1f.2 20 *  [0x60a0 - 0x60af] io

Assigned: PCI: 00:02.0 14 *  [0x60b0 - 0x60b7] io

Assigned: PCI: 00:1f.2 10 *  [0x60b8 - 0x60bf] io

Assigned: PCI: 00:1f.2 18 *  [0x60c0 - 0x60c7] io

Assigned: PCI: 00:1f.2 14 *  [0x60c8 - 0x60cb] io

Assigned: PCI: 00:1f.2 1c *  [0x60cc - 0x60cf] io

PCI_DOMAIN: 0000 allocate_resources_io: next_base: 60d0 size: 50d0 align: 12 gran: 0 done

PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff

PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done

PCI: 00:1c.3 allocate_resources_io: base:5000 size:1000 align:12 gran:12 limit:ffff

Assigned: PCI: 02:00.0 10 *  [0x5000 - 0x50ff] io

PCI: 00:1c.3 allocate_resources_io: next_base: 5100 size: 1000 align: 12 gran: 12 done

PCI: 00:1e.0 allocate_resources_io: base:1000 size:4000 align:12 gran:12 limit:ffff

Assigned: PCI: 03:03.0 2c *  [0x1000 - 0x1fff] io

Assigned: PCI: 03:03.0 34 *  [0x2000 - 0x2fff] io

Assigned: PCI: 03:03.1 2c *  [0x3000 - 0x3fff] io

Assigned: PCI: 03:03.1 34 *  [0x4000 - 0x4fff] io

PCI: 00:1e.0 allocate_resources_io: next_base: 5000 size: 4000 align: 12 gran: 12 done

PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:18340b00 align:28 gran:0 limit:febfffff

Assigned: PCI: 00:02.0 18 *  [0xe0000000 - 0xefffffff] prefmem

Assigned: PCI: 00:1e.0 20 *  [0xf0000000 - 0xf40fffff] mem

Assigned: PCI: 00:1e.0 24 *  [0xf4100000 - 0xf80fffff] prefmem

Assigned: PCI: 00:1c.3 20 *  [0xf8100000 - 0xf81fffff] mem

Assigned: PCI: 00:02.0 10 *  [0xf8200000 - 0xf827ffff] mem

Assigned: PCI: 00:02.1 10 *  [0xf8280000 - 0xf82fffff] mem

Assigned: PCI: 00:02.0 1c *  [0xf8300000 - 0xf833ffff] mem

Assigned: PCI: 00:1d.7 10 *  [0xf8340000 - 0xf83403ff] mem

Assigned: PCI: 00:1f.2 24 *  [0xf8340400 - 0xf83407ff] mem

Assigned: PCI: 00:1e.2 18 *  [0xf8340800 - 0xf83409ff] mem

Assigned: PCI: 00:1e.2 1c *  [0xf8340a00 - 0xf8340aff] mem

PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f8340b00 size: 18340b00 align: 28 gran: 0 done

PCI: 00:1c.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff

PCI: 00:1c.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done

PCI: 00:1c.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff

PCI: 00:1c.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done

PCI: 00:1c.3 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff

PCI: 00:1c.3 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done

PCI: 00:1c.3 allocate_resources_mem: base:f8100000 size:100000 align:20 gran:20 limit:febfffff

Assigned: PCI: 02:00.0 30 *  [0xf8100000 - 0xf811ffff] mem

Assigned: PCI: 02:00.0 18 *  [0xf8120000 - 0xf8120fff] mem

PCI: 00:1c.3 allocate_resources_mem: next_base: f8121000 size: 100000 align: 20 gran: 20 done

PCI: 00:1e.0 allocate_resources_prefmem: base:f4100000 size:4000000 align:20 gran:20 limit:febfffff

Assigned: PCI: 03:03.0 1c *  [0xf4100000 - 0xf60fffff] prefmem

Assigned: PCI: 03:03.1 1c *  [0xf6100000 - 0xf80fffff] prefmem

PCI: 00:1e.0 allocate_resources_prefmem: next_base: f8100000 size: 4000000 align: 20 gran: 20 done

PCI: 00:1e.0 allocate_resources_mem: base:f0000000 size:4100000 align:20 gran:20 limit:febfffff

Assigned: PCI: 03:03.2 14 *  [0xf0000000 - 0xf0003fff] mem

Assigned: PCI: 03:03.0 24 *  [0xf0004000 - 0xf2003fff] mem

Assigned: PCI: 03:03.1 24 *  [0xf2004000 - 0xf4003fff] mem

Assigned: PCI: 03:03.0 10 *  [0xf4004000 - 0xf4004fff] mem

Assigned: PCI: 03:03.1 10 *  [0xf4005000 - 0xf4005fff] mem

Assigned: PCI: 03:03.2 10 *  [0xf4006000 - 0xf40067ff] mem

PCI: 00:1e.0 allocate_resources_mem: next_base: f4006800 size: 4100000 align: 20 gran: 20 done

Root Device assign_resources, bus 0 link: 0

pci_tolm: 0xe0000000

Base of stolen memory: 0x7f800000

Top of Low Used DRAM: 0x80000000

IGD decoded, subtracting 8M UMA

Available memory: 2088960K (2040M)

Adding UMA memory area

Adding PCIe config bar

PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0

PCI: 00:02.0 10 <- [0x00f8200000 - 0x00f827ffff] size 0x00080000 gran 0x13 mem

PCI: 00:02.0 14 <- [0x00000060b0 - 0x00000060b7] size 0x00000008 gran 0x03 io

PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem

PCI: 00:02.0 1c <- [0x00f8300000 - 0x00f833ffff] size 0x00040000 gran 0x12 mem

PCI: 00:02.1 10 <- [0x00f8280000 - 0x00f82fffff] size 0x00080000 gran 0x13 mem

PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io

PCI: 00:1c.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 prefmem

PCI: 00:1c.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 mem

PCI: 00:1c.3 1c <- [0x0000005000 - 0x0000005fff] size 0x00001000 gran 0x0c bus 02 io

PCI: 00:1c.3 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem

PCI: 00:1c.3 20 <- [0x00f8100000 - 0x00f81fffff] size 0x00100000 gran 0x14 bus 02 mem

PCI: 00:1c.3 assign_resources, bus 2 link: 0

PCI: 02:00.0 10 <- [0x0000005000 - 0x00000050ff] size 0x00000100 gran 0x08 io

PCI: 02:00.0 18 <- [0x00f8120000 - 0x00f8120fff] size 0x00001000 gran 0x0c mem64

PCI: 02:00.0 30 <- [0x00f8100000 - 0x00f811ffff] size 0x00020000 gran 0x11 romem

PCI: 00:1c.3 assign_resources, bus 2 link: 0

PCI: 00:1d.0 20 <- [0x0000006000 - 0x000000601f] size 0x00000020 gran 0x05 io

PCI: 00:1d.1 20 <- [0x0000006020 - 0x000000603f] size 0x00000020 gran 0x05 io

PCI: 00:1d.2 20 <- [0x0000006040 - 0x000000605f] size 0x00000020 gran 0x05 io

PCI: 00:1d.3 20 <- [0x0000006060 - 0x000000607f] size 0x00000020 gran 0x05 io

PCI: 00:1d.7 10 <- [0x00f8340000 - 0x00f83403ff] size 0x00000400 gran 0x0a mem

PCI: 00:1e.0 1c <- [0x0000001000 - 0x0000004fff] size 0x00004000 gran 0x0c bus 03 io

PCI: 00:1e.0 24 <- [0x00f4100000 - 0x00f80fffff] size 0x04000000 gran 0x14 bus 03 prefmem

PCI: 00:1e.0 20 <- [0x00f0000000 - 0x00f40fffff] size 0x04100000 gran 0x14 bus 03 mem

PCI: 00:1e.0 assign_resources, bus 3 link: 0

PCI: 03:03.0 In set resources 

PCI: 03:03.0 10 <- [0x00f4004000 - 0x00f4004fff] size 0x00001000 gran 0x0c mem

PCI: 03:03.0 2c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x02 io

PCI: 03:03.0 34 <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io

PCI: 03:03.0 1c <- [0x00f4100000 - 0x00f60fffff] size 0x02000000 gran 0x0c prefmem

PCI: 03:03.0 24 <- [0x00f0004000 - 0x00f2003fff] size 0x02000000 gran 0x0c mem

PCI: 03:03.0 done set resources 

PCI: 03:03.1 In set resources 

PCI: 03:03.1 10 <- [0x00f4005000 - 0x00f4005fff] size 0x00001000 gran 0x0c mem

PCI: 03:03.1 2c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io

PCI: 03:03.1 34 <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x02 io

PCI: 03:03.1 1c <- [0x00f6100000 - 0x00f80fffff] size 0x02000000 gran 0x0c prefmem

PCI: 03:03.1 24 <- [0x00f2004000 - 0x00f4003fff] size 0x02000000 gran 0x0c mem

PCI: 03:03.1 done set resources 

PCI: 03:03.2 10 <- [0x00f4006000 - 0x00f40067ff] size 0x00000800 gran 0x0b mem

PCI: 03:03.2 14 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e mem

PCI: 00:1e.0 assign_resources, bus 3 link: 0

PCI: 00:1e.2 18 <- [0x00f8340800 - 0x00f83409ff] size 0x00000200 gran 0x09 mem

PCI: 00:1e.2 1c <- [0x00f8340a00 - 0x00f8340aff] size 0x00000100 gran 0x08 mem

PCI: 00:1f.0 assign_resources, bus 0 link: 0

PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io

PNP: 002e.1 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq

ERROR: PNP: 002e.1 74 not allocated

PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io

PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq

PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io

PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq

PCI: 00:1f.0 assign_resources, bus 0 link: 0

PCI: 00:1f.2 10 <- [0x00000060b8 - 0x00000060bf] size 0x00000008 gran 0x03 io

PCI: 00:1f.2 14 <- [0x00000060c8 - 0x00000060cb] size 0x00000004 gran 0x02 io

PCI: 00:1f.2 18 <- [0x00000060c0 - 0x00000060c7] size 0x00000008 gran 0x03 io

PCI: 00:1f.2 1c <- [0x00000060cc - 0x00000060cf] size 0x00000004 gran 0x02 io

PCI: 00:1f.2 20 <- [0x00000060a0 - 0x00000060af] size 0x00000010 gran 0x04 io

PCI: 00:1f.2 24 <- [0x00f8340400 - 0x00f83407ff] size 0x00000400 gran 0x0a mem

PCI: 00:1f.3 20 <- [0x0000006080 - 0x000000609f] size 0x00000020 gran 0x05 io

PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0

Root Device assign_resources, bus 0 link: 0

Done setting resources.

Show resources in subtree (Root Device)...After assigning values.

 Root Device child on link 0 APIC_CLUSTER: 0

  APIC_CLUSTER: 0 child on link 0 APIC: 00

   APIC: 00

  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0

  PCI_DOMAIN: 0000 resource base 1000 size 50d0 align 12 gran 0 limit ffff flags 40040100 index 10000000

  PCI_DOMAIN: 0000 resource base e0000000 size 18340b00 align 28 gran 0 limit febfffff flags 40040200 index 10000100

  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3

  PCI_DOMAIN: 0000 resource base c0000 size 7f740000 align 0 gran 0 limit 0 flags e0004200 index 4

  PCI_DOMAIN: 0000 resource base 7f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 6

  PCI_DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7

   PCI: 00:00.0

   PCI: 00:02.0

   PCI: 00:02.0 resource base f8200000 size 80000 align 19 gran 19 limit febfffff flags 60000200 index 10

   PCI: 00:02.0 resource base 60b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14

   PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 18

   PCI: 00:02.0 resource base f8300000 size 40000 align 18 gran 18 limit febfffff flags 60000200 index 1c

   PCI: 00:02.1

   PCI: 00:02.1 resource base f8280000 size 80000 align 19 gran 19 limit febfffff flags 60000200 index 10

   PCI: 00:1b.0

   PCI: 00:1c.0

   PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c

   PCI: 00:1c.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24

   PCI: 00:1c.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20

   PCI: 00:1c.1

   PCI: 00:1c.2

   PCI: 00:1c.3 child on link 0 PCI: 02:00.0

   PCI: 00:1c.3 resource base 5000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c

   PCI: 00:1c.3 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24

   PCI: 00:1c.3 resource base f8100000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20

    PCI: 02:00.0

    PCI: 02:00.0 resource base 5000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10

    PCI: 02:00.0 resource base f8120000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 18

    PCI: 02:00.0 resource base f8100000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30

   PCI: 00:1d.0

   PCI: 00:1d.0 resource base 6000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20

   PCI: 00:1d.1

   PCI: 00:1d.1 resource base 6020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20

   PCI: 00:1d.2

   PCI: 00:1d.2 resource base 6040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20

   PCI: 00:1d.3

   PCI: 00:1d.3 resource base 6060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20

   PCI: 00:1d.7

   PCI: 00:1d.7 resource base f8340000 size 400 align 10 gran 10 limit febfffff flags 60000200 index 10

   PCI: 00:1e.0 child on link 0 PCI: 03:03.0

   PCI: 00:1e.0 resource base 1000 size 4000 align 12 gran 12 limit ffff flags 60080102 index 1c

   PCI: 00:1e.0 resource base f4100000 size 4000000 align 20 gran 20 limit febfffff flags 60081202 index 24

   PCI: 00:1e.0 resource base f0000000 size 4100000 align 20 gran 20 limit febfffff flags 60080202 index 20

    PCI: 03:03.0

    PCI: 03:03.0 resource base f4004000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10

    PCI: 03:03.0 resource base 1000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c

    PCI: 03:03.0 resource base 2000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34

    PCI: 03:03.0 resource base f4100000 size 2000000 align 12 gran 12 limit febfffff flags 60001200 index 1c

    PCI: 03:03.0 resource base f0004000 size 2000000 align 12 gran 12 limit febfffff flags 60000200 index 24

    PCI: 03:03.1

    PCI: 03:03.1 resource base f4005000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10

    PCI: 03:03.1 resource base 3000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c

    PCI: 03:03.1 resource base 4000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34

    PCI: 03:03.1 resource base f6100000 size 2000000 align 12 gran 12 limit febfffff flags 60001200 index 1c

    PCI: 03:03.1 resource base f2004000 size 2000000 align 12 gran 12 limit febfffff flags 60000200 index 24

    PCI: 03:03.2

    PCI: 03:03.2 resource base f4006000 size 800 align 11 gran 11 limit febfffff flags 60000200 index 10

    PCI: 03:03.2 resource base f0000000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 14

    PCI: 03:03.3

   PCI: 00:1e.2

   PCI: 00:1e.2 resource base f8340800 size 200 align 9 gran 9 limit febfffff flags 60000200 index 18

   PCI: 00:1e.2 resource base f8340a00 size 100 align 8 gran 8 limit febfffff flags 60000200 index 1c

   PCI: 00:1f.0 child on link 0 PNP: 002e.1

   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000

   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100

   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3

    PNP: 002e.1

    PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60

    PNP: 002e.1 resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70

    PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74

    PNP: 002e.2

    PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60

    PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70

    PNP: 002e.3

    PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60

    PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70

    PNP: 002e.5

    PNP: 002e.5 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60

    PNP: 002e.5 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62

    PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70

    PNP: 00ff.1

    PNP: 00ff.0

   PCI: 00:1f.2

   PCI: 00:1f.2 resource base 60b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10

   PCI: 00:1f.2 resource base 60c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14

   PCI: 00:1f.2 resource base 60c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18

   PCI: 00:1f.2 resource base 60cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c

   PCI: 00:1f.2 resource base 60a0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20

   PCI: 00:1f.2 resource base f8340400 size 400 align 10 gran 10 limit febfffff flags 60000200 index 24

   PCI: 00:1f.3

   PCI: 00:1f.3 resource base 6080 size 20 align 5 gran 5 limit ffff flags 60000100 index 20

Done allocating resources.

POST: 0x88

Enabling resources...

PCI: 00:00.0 subsystem <- 4352/6886

PCI: 00:00.0 cmd <- 06

PCI: 00:02.0 cmd <- 03

PCI: 00:02.1 cmd <- 02

PCI: 00:1c.0 bridge ctrl <- 0003

PCI: 00:1c.0 subsystem <- 4352/6886

PCI: 00:1c.0 cmd <- 100

PCI: 00:1c.3 bridge ctrl <- 0003

PCI: 00:1c.3 cmd <- 07

PCI: 00:1d.0 subsystem <- 4352/6886

PCI: 00:1d.0 cmd <- 01

PCI: 00:1d.1 subsystem <- 4352/6886

PCI: 00:1d.1 cmd <- 01

PCI: 00:1d.2 subsystem <- 4352/6886

PCI: 00:1d.2 cmd <- 01

PCI: 00:1d.3 subsystem <- 4352/6886

PCI: 00:1d.3 cmd <- 01

PCI: 00:1d.7 subsystem <- 4352/6886

PCI: 00:1d.7 cmd <- 102

PCI: 00:1e.0 bridge ctrl <- 0003

PCI: 00:1e.0 subsystem <- 4352/6886

PCI: 00:1e.0 cmd <- 107 (NOT WRITTEN!)

PCI: 00:1e.2 cmd <- 02

PCI: 00:1f.0 subsystem <- 4352/6886

PCI: 00:1f.0 cmd <- 107

PCI: 00:1f.2 subsystem <- 4352/6886

PCI: 00:1f.2 cmd <- 03

PCI: 00:1f.3 subsystem <- 4352/6886

PCI: 00:1f.3 cmd <- 101

PCI: 02:00.0 cmd <- 03

PCI: 03:03.0 bridge ctrl <- 0143

PCI: 03:03.0 cmd <- 03

PCI: 03:03.1 bridge ctrl <- 0143

PCI: 03:03.1 cmd <- 03

PCI: 03:03.2 cmd <- 02

done.

Initializing devices...

Root Device init

APIC_CLUSTER: 0 init

start_eip=0x0000c000, offset=0x00100000, code_size=0x0000005b

Initializing SMM handler... ... pmbase = 0x0500



SMI_STS: PM1 

PM1_STS: PWRBTN TMROF 

GPE0_STS: PME 

ALT_GP_SMI_STS: 

TCO_STS: 

  ... raise SMI#

Initializing CPU #0

CPU: vendor Intel device 6fb

CPU: family 06, model 0f, stepping 0b

POST: 0x60

Enabling cache

microcode_info: sig = 0x000006fb pf=0x00000020 rev = 0x00000000

CPU: Intel(R) Core(TM)2 Duo CPU     T5500  @ 1.66GHz.



Setting fixed MTRRs(0-88) Type: UC

Setting fixed MTRRs(0-16) Type: WB

Setting fixed MTRRs(24-88) Type: WB

DONE fixed MTRRs

call enable_fixed_mtrr()

Setting variable MTRR 0, base:    0MB, range: 1024MB, type WB

ADDRESS_MASK_HIGH=0xf

Setting variable MTRR 1, base: 1024MB, range:  512MB, type WB

ADDRESS_MASK_HIGH=0xf

Setting variable MTRR 2, base: 1536MB, range:  256MB, type WB

ADDRESS_MASK_HIGH=0xf

Setting variable MTRR 3, base: 1792MB, range:  128MB, type WB

ADDRESS_MASK_HIGH=0xf

Setting variable MTRR 4, base: 1920MB, range:   64MB, type WB

ADDRESS_MASK_HIGH=0xf

Setting variable MTRR 5, base: 1984MB, range:   32MB, type WB

ADDRESS_MASK_HIGH=0xf

Running out of variable MTRRs!

Zero-sized MTRR range @0KB

DONE variable MTRRs

Clear out the extra MTRR's

call enable_var_mtrr()

Leave x86_setup_var_mtrrs

POST: 0x6a



MTRR check

Fixed MTRRs   : Enabled

Variable MTRRs: Enabled



POST: 0x93

Setting up local apic... apic_id: 0x00 done.

POST: 0x9b

CPU: 0 2 siblings

CPU: 0 has sibling 1

Asserting INIT.

Waiting for send to finish...

+Deasserting INIT.

Waiting for send to finish...

+#startup loops: 2.

Sending STARTUP #1 to 1.

After apic_write.

Startup point 1.

Waiting for send to finish...

+Sending STARTUP #2 to 1.

After apic_write.

Startup point 1.

Waiting for send to finish...

+After Startup.

CPU #0 initialized

Waiting for 1 CPUS to stop

Initializing CPU #1

CPU: vendor Intel device 6fb

CPU: family 06, model 0f, stepping 0b

POST: 0x60

Enabling cache

microcode_info: sig = 0x000006fb pf=0x00000020 rev = 0x00000000

CPU: Intel(R) Core(TM)2 Duo CPU     T5500  @ 1.66GHz.



Setting fixed MTRRs(0-88) Type: UC

Setting fixed MTRRs(0-16) Type: WB

Setting fixed MTRRs(24-88) Type: WB

DONE fixed MTRRs

call enable_fixed_mtrr()

Setting variable MTRR 0, base:    0MB, range: 1024MB, type WB

ADDRESS_MASK_HIGH=0xf

Setting variable MTRR 1, base: 1024MB, range:  512MB, type WB

ADDRESS_MASK_HIGH=0xf

Setting variable MTRR 2, base: 1536MB, range:  256MB, type WB

ADDRESS_MASK_HIGH=0xf

Setting variable MTRR 3, base: 1792MB, range:  128MB, type WB

ADDRESS_MASK_HIGH=0xf

Setting variable MTRR 4, base: 1920MB, range:   64MB, type WB

ADDRESS_MASK_HIGH=0xf

Setting variable MTRR 5, base: 1984MB, range:   32MB, type WB

ADDRESS_MASK_HIGH=0xf

Running out of variable MTRRs!

Zero-sized MTRR range @0KB

DONE variable MTRRs

Clear out the extra MTRR's

call enable_var_mtrr()

Leave x86_setup_var_mtrrs

POST: 0x6a



MTRR check

Fixed MTRRs   : Enabled

Variable MTRRs: Enabled



POST: 0x93

Setting up local apic... apic_id: 0x01 done.

POST: 0x9b

CPU: 1 2 siblings

CPU #1 initialized

CPU 1 going down...

All AP CPUs stopped

PCI: 00:00.0 init

PCI: 00:02.0 init

Check CBFS header at fffeffe0

magic is 4f524243

Found CBFS header at fffeffe0

Check cmos_layout.bin

CBFS: follow chain: fff00000 + 28 + 54f + align -> fff00580

Check pci8086,27ae.rom

In CBFS, ROM address for PCI: 00:02.0 = fff005b8

PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040

PCI ROM image, vendor ID 8086, device ID 27a2,

ID mismatch: vendor ID 8086, device ID 27a2

PCI: 00:02.1 init

PCI: 00:1c.0 init

Initializing ICH7 PCIe bridge.

PCI: 00:1c.3 init

Initializing ICH7 PCIe bridge.

PCI: 00:1d.0 init

UHCI: Setting up controller.. done.

PCI: 00:1d.1 init

UHCI: Setting up controller.. done.

PCI: 00:1d.2 init

UHCI: Setting up controller.. done.

PCI: 00:1d.3 init

UHCI: Setting up controller.. done.

PCI: 00:1d.7 init

EHCI: Setting up controller.. done.

PCI: 00:1e.0 init

PCI: 00:1e.2 init

Initializing AC'97 Audio.

No primary codec. Disabling AC'97 Audio.

PCI: 00:1f.0 init

i82801gx: lpc_init

Southbridge APIC ID = 2

Dumping IOAPIC registers

  reg 0x0000: 0x02000000

  reg 0x0001: 0x00170020

  reg 0x0002: 0x00170020

Set power on after power failure.

NMI sources disabled.

rtc_failed = 0x0

RTC Init

i8259_configure_irq_trigger: current interrupts are 0x0

i8259_configure_irq_trigger: try to set interrupts 0x200

Disabling ACPI via APMC:

done.

Locking SMM.

PCI: 00:1f.2 init

i82801gx_sata: initializing...

SATA controller in combined mode.

PCI: 00:1f.3 init

Initializing SMBus device:

  Old SMBUS Base Address: 0x6081

  New SMBUS Base Address: 0x0401

PCI: 02:00.0 init

Initializing RTL8168 Gigabit Ethernet

PCI: 03:03.0 init

TI PCI7420/7620 init

PCI: 03:03.1 init

TI PCI7420/7620 init

PCI: 03:03.2 init

TI PCI7420/7620 FireWire init

PNP: 002e.1 init

PNP: 002e.2 init

PNP: 002e.3 init

PNP: 00ff.0 init

Renesas M3885x: Initializing keyboard.

Keyboard init...

m3885: get variable 0c = 88

m3885: set variable 0c = 88

m3885: set procram 80 = c1

m3885: set procram 81 = c0

m3885: set procram 82 = d8

m3885: set procram 83 = db

m3885: set procram 84 = bf

m3885: set procram 85 = 05

m3885: set procram 86 = 76

m3885: set procram 87 = bf

m3885: set procram 88 = bf

m3885: set procram 89 = 80

m3885: set procram 8a = 78

m3885: set procram 8b = bf

m3885: set procram 8c = bf

m3885: set procram 8d = 07

m3885: set procram 8e = 88

m3885: set procram 8f = c2

m3885: set procram 90 = 03

m3885: set procram 91 = 09

m3885: set procram 92 = d9

m3885: set procram 93 = 16

m3885: set procram 94 = bf

m3885: set procram 95 = 06

m3885: set procram 96 = 0e

m3885: set procram 97 = 81

m3885: set procram 98 = bf

m3885: set procram 99 = bf

m3885: set procram 9a = ee

m3885: set procram 9b = bf

m3885: set procram 9c = bf

m3885: set procram 9d = 55

m3885: set procram 9e = 9a

m3885: set procram 9f = 89

m3885: set procram a0 = 1e

m3885: set procram a1 = 15

m3885: set procram a2 = 36

m3885: set procram a3 = da

m3885: set procram a4 = e8

m3885: set procram a5 = bf

m3885: set procram a6 = 0d

m3885: set procram a7 = bf

m3885: set procram a8 = bf

m3885: set procram a9 = bf

m3885: set procram aa = bf

m3885: set procram ab = a3

m3885: set procram ac = bf

m3885: set procram ad = 4e

m3885: set procram ae = 66

m3885: set procram af = 8b

m3885: set procram b0 = 1d

m3885: set procram b1 = 2e

m3885: set procram b2 = e6

m3885: set procram b3 = e7

m3885: set procram b4 = e5

m3885: set procram b5 = 1c

m3885: set procram b6 = 58

m3885: set procram b7 = bf

m3885: set procram b8 = 82

m3885: set procram b9 = bf

m3885: set procram ba = f0

m3885: set procram bb = bf

m3885: set procram bc = bf

m3885: set procram bd = 5b

m3885: set procram be = 5d

m3885: set procram bf = 8c

m3885: set procram c0 = 22

m3885: set procram c1 = 25

m3885: set procram c2 = 2c

m3885: set procram c3 = 35

m3885: set procram c4 = e1

m3885: set procram c5 = 1a

m3885: set procram c6 = 96

m3885: set procram c7 = bf

m3885: set procram c8 = bf

m3885: set procram c9 = bf

m3885: set procram ca = ec

m3885: set procram cb = bf

m3885: set procram cc = bf

m3885: set procram cd = 54

m3885: set procram ce = f1

m3885: set procram cf = 8f

m3885: set procram d0 = 1b

m3885: set procram d1 = 2a

m3885: set procram d2 = 2b

m3885: set procram d3 = 32

m3885: set procram d4 = e9

m3885: set procram d5 = 31

m3885: set procram d6 = 29

m3885: set procram d7 = 61

m3885: set procram d8 = bf

m3885: set procram d9 = bf

m3885: set procram da = 8d

m3885: set procram db = bf

m3885: set procram dc = 86

m3885: set procram dd = c3

m3885: set procram de = 92

m3885: set procram df = 93

m3885: set procram e0 = 21

m3885: set procram e1 = 23

m3885: set procram e2 = 34

m3885: set procram e3 = 33

m3885: set procram e4 = 41

m3885: set procram e5 = e0

m3885: set procram e6 = bf

m3885: set procram e7 = bf

m3885: set procram e8 = bf

m3885: set procram e9 = 85

m3885: set procram ea = eb

m3885: set procram eb = bf

m3885: set procram ec = b6

m3885: set procram ed = bf

m3885: set procram ee = 91

m3885: set procram ef = bf

m3885: set procram f0 = 26

m3885: set procram f1 = 24

m3885: set procram f2 = 2d

m3885: set procram f3 = e3

m3885: set procram f4 = e2

m3885: set procram f5 = e4

m3885: set procram f6 = bf

m3885: set procram f7 = bf

m3885: set procram f8 = 87

m3885: set procram f9 = bf

m3885: set procram fa = ea

m3885: set procram fb = bf

m3885: set procram fc = bf

m3885: set procram fd = 52

m3885: set procram fe = 90

m3885: set procram ff = 8e

m3885: set variable 0c = a8

m3885: get variable 00 = 47

M388x has 71 variables in bank 2.

m3885: get variable 23 = 80

Writing Fn-Table to M388x RAM offset 0x80

m3885: set procram 80 = 04

m3885: set procram 81 = bd

m3885: set procram 82 = 0c

m3885: set procram 83 = be

m3885: set procram 84 = 7e

m3885: set procram 85 = 9a

m3885: set procram 86 = 8a

m3885: set procram 87 = b6

m3885: set procram 88 = 92

m3885: set procram 89 = 8f

m3885: set procram 8a = 93

m3885: set procram 8b = 8e

m3885: set procram 8c = 81

m3885: set procram 8d = 86

m3885: set procram 8e = 82

m3885: set procram 8f = 87

m3885: set procram 90 = 8a

m3885: set procram 91 = 9a

m3885: set procram 92 = 8d

m3885: set procram 93 = 7e

m3885: set procram 94 = 88

m3885: set procram 95 = 84

m3885: set procram 96 = 7e

m3885: set procram 97 = 78

m3885: set procram 98 = 77

m3885: set procram 99 = 07

m3885: set procram 9a = 77

m3885: set procram 9b = 98

m3885: set procram 9c = 89

m3885: set procram 9d = b2

m3885: set procram 9e = 05

m3885: set procram 9f = 9b

m3885: set procram a0 = 78

m3885: set procram a1 = 84

m3885: set procram a2 = 07

m3885: set procram a3 = 88

m3885: set procram a4 = 8a

m3885: set procram a5 = 7e

m3885: set procram a6 = 05

m3885: set procram a7 = a6

m3885: set procram a8 = 06

m3885: set procram a9 = a7

m3885: set procram aa = 04

m3885: set procram ab = a8

m3885: set procram ac = 0c

m3885: set procram ad = a9

m3885: set procram ae = 03

m3885: set procram af = aa

m3885: set procram b0 = 0b

m3885: set procram b1 = c1

m3885: set procram b2 = 83

m3885: set procram b3 = c0

m3885: set procram b4 = 0a

m3885: set procram b5 = ad

m3885: set procram b6 = 01

m3885: set procram b7 = ae

m3885: set procram b8 = 09

m3885: set procram b9 = af

m3885: set procram ba = 78

m3885: set procram bb = b0

m3885: set procram bc = 07

m3885: set procram bd = b1

m3885: set procram be = 1a

m3885: set procram bf = 61

m3885: set procram c0 = 3b

m3885: set procram c1 = 69

m3885: set procram c2 = 42

m3885: set procram c3 = 72

m3885: set procram c4 = 4b

m3885: set procram c5 = 7a

m3885: set procram c6 = 3c

m3885: set procram c7 = 6b

m3885: set procram c8 = 43

m3885: set procram c9 = 73

m3885: set procram ca = 44

m3885: set procram cb = 74

m3885: set procram cc = 3d

m3885: set procram cd = 6c

m3885: set procram ce = 3e

m3885: set procram cf = 75

m3885: set procram d0 = 46

m3885: set procram d1 = 7d

m3885: set procram d2 = 3a

m3885: set procram d3 = 70

m3885: set procram d4 = 49

m3885: set procram d5 = 71

m3885: set procram d6 = 4a

m3885: set procram d7 = 94

m3885: set procram d8 = 4c

m3885: set procram d9 = 79

m3885: set procram da = 4c

m3885: set procram db = 7c

m3885: set procram dc = 45

m3885: set procram dd = 7c

m3885: set procram de = 45

m3885: set procram df = 79

m3885: set procram e0 = 4d

m3885: set procram e1 = 7b

m3885: set procram e2 = 5a

m3885: set procram e3 = 95

m3885: set procram e4 = 4c

m3885: set procram e5 = 7b

m3885: set procram e6 = 45

m3885: set procram e7 = 7b

m3885: set procram e8 = 4d

m3885: set procram e9 = 79

m3885: set procram ea = 4d

m3885: set procram eb = 7c

m3885: set procram ec = 4e

m3885: set procram ed = 7b

m3885: set procram ee = 54

m3885: set procram ef = 95

m3885: set procram f0 = 52

m3885: set procram f1 = 7c

m3885: set procram f2 = 45

m3885: set procram f3 = 94

m3885: set procram f4 = 4a

m3885: set procram f5 = 79

m3885: set procram f6 = b3

m3885: set procram f7 = 95

m3885: set procram f8 = b4

m3885: set procram f9 = 7b

m3885: set procram fa = b5

m3885: set procram fb = 7c

m3885: set procram fc = 00

m3885: set procram fd = 00

m3885: set procram fe = 55

m3885: set procram ff = 79

m3885: set variable 0c = 88

m3885: get variable 00 = 47

M388x has 71 variables in original bank.

m3885: get variable 08 = 20

m3885: set variable 08 = 6c

m3885: get variable 0a = 00

m3885: set variable 0a = 00

m3885: get variable 0c = 88

m3885: set variable 0c = 08

m3885: get variable 11 = 40

m3885: set variable 11 = 06

m3885: get variable 13 = 00

m3885: set variable 13 = 00

m3885: get variable 14 = 00

m3885: set variable 14 = 00

m3885: get variable 15 = 00

m3885: set variable 15 = 3f

m3885: get variable 16 = 00

m3885: set variable 16 = 00

m3885: get variable 17 = 00

m3885: set variable 17 = 00

m3885: get variable 18 = 46

m3885: set variable 18 = 0e

m3885: get variable 19 = 00

m3885: set variable 19 = 9f

m3885: get variable 1a = 00

m3885: set variable 1a = 9f

m3885: get variable 1b = 00

m3885: set variable 1b = 6a

m3885: get variable 1c = 00

m3885: set variable 1c = 9f

m3885: get variable 1d = 00

m3885: set variable 1d = 9f

m3885: get variable 1e = 9f

m3885: set variable 1e = 87

m3885: get variable 1f = 00

m3885: set variable 1f = 9f

m3885: get variable 20 = 29

m3885: set variable 20 = 9f

m3885: get variable 21 = 01

m3885: set variable 21 = 08

m3885: get variable 24 = 02

m3885: set variable 24 = 30

m3885: get variable 2b = 00

m3885: set variable 2b = 00

m3885: get variable 2c = 00

m3885: set variable 2c = 80

m3885: get variable 2d = 00

m3885: set variable 2d = 02

m3885: get variable 2e = 00

m3885: set variable 2e = 00

m3885: get variable 2f = 80

m3885: set variable 2f = 00

m3885: set variable 0c = 98

m3885: set procram ff = c1

m3885: set procram 6d = 81

m3885: set procram 6c = 80

m3885: set procram f2 = 02

m3885: set procram f3 = 5d

m3885: set procram f9 = 0a

m3885: get variable 0c = 98

m3885: set variable 0c = c8

m3885: get procram f8 = ea

m3885: set procram d0 = 9a

m3885: get variable 0c = c8

m3885: set variable 0c = c8

m3885: get procram f8 = ea

m3885: set procram d2 = 9a

m3885: get variable 0c = c8

m3885: set variable 0c = c8

m3885: get procram f8 = ea

m3885: set procram d3 = 8a

m3885: set procram d1 = 88

m3885: set procram d6 = 88

m3885: set procram d7 = 88

m3885: set procram d4 = 98

m3885: set procram d5 = 98

m3885: set procram da = 80

m3885: set procram db = 80

m3885: set procram dd = 80

m3885: set procram de = 80

m3885: set procram df = 80

m3885: set procram d8 = 81

m3885: set procram d9 = 81

m3885: set procram dc = 81

m3885: set variable 0c = d8

m3885: set procram 81 = 9c

m3885: set procram 82 = 01

m3885: set procram 84 = 50

m3885: set procram 85 = 55

m3885: set procram 86 = 81

m3885: set procram 87 = 78

m3885: set procram 89 = 9c

m3885: set procram 8a = 01

m3885: set procram 8c = 4b

m3885: set procram 8d = 50

m3885: set procram 8e = 81

Devices initialized

Show all devs...After init.

Root Device: enabled 1

APIC_CLUSTER: 0: enabled 1

APIC: 00: enabled 1

PCI_DOMAIN: 0000: enabled 1

PCI: 00:00.0: enabled 1

PCI: 00:1b.0: enabled 0

PCI: 00:1c.0: enabled 1

PCI: 00:1c.1: enabled 0

PCI: 00:1c.2: enabled 0

PCI: 00:1d.0: enabled 1

PCI: 00:1d.1: enabled 1

PCI: 00:1d.2: enabled 1

PCI: 00:1d.3: enabled 1

PCI: 00:1d.7: enabled 1

PCI: 00:1e.0: enabled 1

PCI: 03:03.0: enabled 1

PCI: 03:03.1: enabled 1

PCI: 03:03.2: enabled 1

PCI: 03:03.3: enabled 0

PCI: 00:1f.0: enabled 1

PNP: 002e.1: enabled 1

PNP: 002e.2: enabled 1

PNP: 002e.3: enabled 1

PNP: 002e.5: enabled 0

PNP: 00ff.1: enabled 1

PCI: 00:1f.2: enabled 1

PCI: 00:1f.3: enabled 1

PCI: 00:02.0: enabled 1

PCI: 00:02.1: enabled 1

PCI: 00:1c.3: enabled 1

PCI: 00:1e.2: enabled 1

PCI: 02:00.0: enabled 1

PNP: 00ff.0: enabled 1

APIC: 01: enabled 1

POST: 0x89

Initializing CBMEM area to 0x7f6f0000 (1114112 bytes)

Adding CBMEM entry as no. 1

Moving GDT to 7f6f0200...ok

POST: 0x8a

High Tables Base is 7f6f0000.

POST: 0x9a

Copying Interrupt Routing Table to 0x000f0000... done.

Adding CBMEM entry as no. 2

Copying Interrupt Routing Table to 0x7f6f0400... done.

PIRQ table: 320 bytes.

POST: 0x9b

Wrote the mp table end at: 000f0410 - 000f059c

Adding CBMEM entry as no. 3

Wrote the mp table end at: 7f6f1410 - 7f6f159c

MP table: 412 bytes.

POST: 0x9c

Adding CBMEM entry as no. 4

ACPI: Writing ACPI tables at 7f6f2400.

ACPI:    * HPET

ACPI: added table 1/32, length now 40

ACPI:    * MADT

ACPI: added table 2/32, length now 44

ACPI:    * MCFG

ACPI: added table 3/32, length now 48

ACPI:     * FACS

ACPI: Patching up global NVS in DSDT at offset 0x020d -> 0x7f6f5f10

ACPI:     * DSDT @ 7f6f2730 Length 37d9

ACPI:     * FADT

ACPI: added table 4/32, length now 52

ACPI:     * SSDT

Found 1 CPU(s) with 2 core(s) each.

clocks between 996 and 1660 MHz.

adding 3 P-States between busratio 6 and a, incl. P0

clocks between 996 and 1660 MHz.

adding 3 P-States between busratio 6 and a, incl. P0

ACPI: added table 5/32, length now 56

current = 7f6f6300

ACPI:     * DMI (Linux workaround)

ACPI: done.

Laptop handling...

ACPI tables: 16224 bytes.

POST: 0x9d

Adding CBMEM entry as no. 5

Writing high table forward entry at 0x00000500

Wrote coreboot table at: 00000500 - 00000518  checksum a06e

New low_table_end: 0x00000518

Now going to write high coreboot table at 0x7f6fe000

rom_table_end = 0x7f6fe000

Adjust low_table_end from 0x00000518 to 0x00001000 

Adjust rom_table_end from 0x7f6fe000 to 0x7f700000 

Adding high table area

coreboot memory table:

 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES

 1. 0000000000001000-000000000009ffff: RAM

 2. 00000000000c0000-000000007f6effff: RAM

 3. 000000007f6f0000-000000007f7fffff: CONFIGURATION TABLES

 4. 000000007f800000-000000007fffffff: RESERVED

 5. 00000000f0000000-00000000f3ffffff: RESERVED

Wrote coreboot table at: 7f6fe000 - 7f6fe1bc  checksum c4ba

coreboot table: 444 bytes.

POST: 0x9e

Adding CBMEM entry as no. 6

 0. FREE SPACE 7f800000 00000000

 1. GDT        7f6f0200 00000200

 2. IRQ TABLE  7f6f0400 00001000

 3. SMP TABLE  7f6f1400 00001000

 4. ACPI       7f6f2400 0000bc00

 5. COREBOOT   7f6fe000 00002000

 6. ACPI RESUME7f700000 00100000

Check CBFS header at fffeffe0

magic is 4f524243

Found CBFS header at fffeffe0

Check cmos_layout.bin

CBFS: follow chain: fff00000 + 28 + 54f + align -> fff00580

Check pci8086,27ae.rom

CBFS: follow chain: fff00580 + 38 + 10000 + align -> fff105c0

Check fallback/coreboot_ram

CBFS: follow chain: fff105c0 + 38 + 1a33b + align -> fff2a940

Check fallback/payload

Got a payload

Loading segment from rom address 0xfff2a978

  data (compression=0)

  New segment dstaddr 0xec400 memsize 0x13c00 srcaddr 0xfff2a9b0 filesize 0x13c00

  (cleaned up) New segment addr 0xec400 size 0x13c00 offset 0xfff2a9b0 filesize 0x13c00

Loading segment from rom address 0xfff2a994

  Entry Point 0x000fdf82

Loading Segment: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 filesz: 0x0000000000013c00

lb: [0x0000000000100000, 0x0000000000164000)

Post relocation: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 filesz: 0x0000000000013c00

it's not compressed!

[ 0x000ec400, 00100000, 0x00100000) <- fff2a9b0

dest 000ec400, end 00100000, bouncebuffer 7f628000

Loaded segments

ICH7 watchdog disabled

Jumping to boot code at fdf82

POST: 0xfe

entry    = 0x000fdf82

lb_start = 0x00100000

lb_size  = 0x00064000

adjust   = 0x7f58c000

buffer   = 0x7f628000

     elf_boot_notes = 0x0012c2d0

adjusted_boot_notes = 0x7f6b82d0

Start bios (version 0.6.0-20100326_214650-morn.localdomain)

Found mainboard Roda RK886EX

Found CBFS header at 0xfffeffe0

Ram Size=0x7f6f0000 (0x0000000000000000 high)

CPU Mhz=1668

Found 2 cpu(s) max supported 2 cpu(s)

Copying PIR from 0x7f6f0400 to 0x000f7a70

Copying MPTABLE from 0x7f6f1400/7f6f1410 to 0x000f78d0

Copying ACPI RSDP from 0x7f6f2400 to 0x000f78a0

SMBIOS ptr=0x000f7880 table=0x7f6efec0

Scan for VGA option rom

Running option rom at c000:0003

Turning on vga console

Starting SeaBIOS (version 0.6.0-20100326_214650-morn.localdomain)



No support for 64bit EHCI

UHCI init on dev 00:1d.0 (io=6000)

UHCI init on dev 00:1d.1 (io=6020)

UHCI init on dev 00:1d.2 (io=6040)

UHCI init on dev 00:1d.3 (io=6060)

Found 0 lpt ports

Found 2 serial ports

ATA controller 0 at 1f0/3f4/0 (irq 14 dev fa)

ATA controller 1 at 170/374/0 (irq 15 dev fa)

ata0-0: TOSHIBA MK3265GSX ATA-8 Hard-Disk (298 GiBytes)

drive 0x000f7800: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=625142448

ata1-0: Optiarc DVD RW AD-7580A ATAPI-7 CD-Rom/DVD-Rom

PS2 keyboard initialized

Scan for option roms

Press F12 for boot menu.



Returned 61440 bytes of ZoneHigh

e820 map has 6 items:

  0: 0000000000000000 - 000000000009f400 = 1

  1: 000000000009f400 - 00000000000a0000 = 2

  2: 00000000000f0000 - 0000000000100000 = 2

  3: 0000000000100000 - 000000007f6ef000 = 1

  4: 000000007f6ef000 - 0000000080000000 = 2

  5: 00000000f0000000 - 00000000f4000000 = 2

enter handle_19:

  NULL

Booting from Floppy...

Boot failed: could not read the boot disk



enter handle_18:

  NULL

Booting from CD-Rom...

Device reports MEDIUM NOT PRESENT

atapi_is_ready returned -1

Boot failed: Could not read from CDROM (code 0003)

enter handle_18:

  NULL

Booting from Hard Disk...

Booting from 0000:7c00


From svn at coreboot.org  Thu Mar  3 21:52:50 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Mar 2011 21:52:50 +0100
Subject: [coreboot] [commit] r6429 - trunk/src/southbridge/nvidia/ck804
Message-ID: <E1PvFVy-0003s8-UP@ra.coresystems.de>

Author: jakllsch
Date: Thu Mar  3 21:52:50 2011
New Revision: 6429
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6429

Log:
Improve ck804 IOAPIC and HPET resource handling.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/southbridge/nvidia/ck804/lpc.c

Modified: trunk/src/southbridge/nvidia/ck804/lpc.c
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/lpc.c	Thu Mar  3 16:36:08 2011	(r6428)
+++ trunk/src/southbridge/nvidia/ck804/lpc.c	Thu Mar  3 21:52:50 2011	(r6429)
@@ -104,15 +104,6 @@
 		pci_write_config8(dev, 0x6d, new);
 }
 
-static void enable_hpet(struct device *dev)
-{
-	unsigned long hpet_address;
-
-	pci_write_config32(dev, 0x44, 0xfed00001);
-	hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
-	printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address);
-}
-
 unsigned pm_base = 0;
 
 static void lpc_init(device_t dev)
@@ -130,12 +121,6 @@
 		return;
 #endif
 
-#if 0
-	/* Posted memory write enable */
-	byte = pci_read_config8(dev, 0x46);
-	pci_write_config8(dev, 0x46, byte | (1 << 0));
-#endif
-
 	/* Power after power fail */
 	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
@@ -166,12 +151,6 @@
 	pci_write_config8(dev, 0xe8, byte);
 #endif
 
-	/* Enable Error reporting. */
-	/* Set up sync flood detected. */
-	byte = pci_read_config8(dev, 0x47);
-	byte |= (1 << 1);
-	pci_write_config8(dev, 0x47, byte);
-
 	/* Set up NMI on errors. */
 	byte = inb(0x70);		/* RTC70 */
 	byte_old = byte;
@@ -190,9 +169,6 @@
 	/* Initialize ISA DMA. */
 	isa_dma_init();
 
-	/* Initialize the High Precision Event Timers (HPET). */
-	enable_hpet(dev);
-
 	rom_dummy_write(dev);
 }
 
@@ -205,6 +181,9 @@
 	/* We got one for APIC, or one more for TRAP. */
 	pci_dev_read_resources(dev);
 
+	/* HPET */
+	pci_get_resource(dev, 0x44);
+
 	/* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
 	for (index = 0x60; index <= 0x68; index += 4)	/* We got another 3. */
 		pci_get_resource(dev, index);
@@ -223,10 +202,42 @@
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = IO_APIC_ADDR;
-	res->size = 0x00001000;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	if (dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE) {
+		res = find_resource(dev, 0x14); /* IOAPIC */
+		if (res) {
+			res->base = IO_APIC_ADDR;
+			res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+		}
+
+		res = find_resource(dev, 0x44); /* HPET */
+		if (res) {
+			res->base = 0xfed00000;
+			res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+		}
+	}
+}
+
+static void ck804_lpc_set_resources(device_t dev)
+{
+	struct resource *res;
+
+	pci_dev_set_resources(dev);
+
+	/* APIC */
+	res = find_resource(dev, 0x14);
+	if (res) {
+		pci_write_config32(dev, 0x14, res->base);
+		res->flags |= IORESOURCE_STORED;
+		report_resource_stored(dev, res, "");
+	}
+
+	/* HPET */
+	res = find_resource(dev, 0x44);
+	if (res) {
+		pci_write_config32(dev, 0x44, res->base|1);
+		res->flags |= IORESOURCE_STORED;
+		report_resource_stored(dev, res, "");
+	}
 }
 
 /**
@@ -299,7 +310,7 @@
 
 static struct device_operations lpc_ops = {
 	.read_resources   = ck804_lpc_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.set_resources    = ck804_lpc_set_resources,
 	.enable_resources = ck804_lpc_enable_resources,
 	.init             = lpc_init,
 	.scan_bus         = scan_static_bus,



From svn at coreboot.org  Thu Mar  3 22:20:33 2011
From: svn at coreboot.org (repository service)
Date: Thu, 03 Mar 2011 22:20:33 +0100
Subject: [coreboot] build service results for r6429
Message-ID: <E1PvFwn-0005lt-2w@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "jakllsch" checked in revision 6429 to
the coreboot repository. This caused the following 
changes:

Change Log:
Improve ck804 IOAPIC and HPET resource handling.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Compilation of digitallogic:adl855pc has been fixed


If something broke during this checkin please be a pain 
in jakllsch's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From jakllsch at kollasch.net  Thu Mar  3 23:13:56 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Thu, 3 Mar 2011 22:13:56 +0000
Subject: [coreboot] [patch] correct off-by-one in pre-rev-F model F powernow
	code
Message-ID: <20110303221356.GA16103@tarantulon.kollasch.net>

Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.
With this change the last P-state entry of the last CPU in the table
is successfully conveyed into the SSDT.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
----
-------------- next part --------------
Index: src/cpu/amd/model_fxx/powernow_acpi.c
===================================================================
--- src/cpu/amd/model_fxx/powernow_acpi.c	(revision 6429)
+++ src/cpu/amd/model_fxx/powernow_acpi.c	(working copy)
@@ -622,7 +622,7 @@
 		Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage);
 		Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100;
 		Pstate_num++;
-	} while ((Pstate_num < MAXP) && (data->pstates[Pstate_num].freqMhz != 0));
+	} while ((Pstate_num < MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0));
 
 	for (i=0;i<Pstate_num;i++)
 		printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i,

From peter at stuge.se  Thu Mar  3 23:19:28 2011
From: peter at stuge.se (Peter Stuge)
Date: Thu, 3 Mar 2011 23:19:28 +0100
Subject: [coreboot] [patch] correct off-by-one in pre-rev-F model
	F	powernow code
In-Reply-To: <20110303221356.GA16103@tarantulon.kollasch.net>
References: <20110303221356.GA16103@tarantulon.kollasch.net>
Message-ID: <20110303221929.12619.qmail@stuge.se>

Jonathan A. Kollasch wrote:
> Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.
> With this change the last P-state entry of the last CPU in the table
> is successfully conveyed into the SSDT.
> 
> Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Fri Mar  4 00:09:44 2011
From: svn at coreboot.org (repository service)
Date: Fri, 04 Mar 2011 00:09:44 +0100
Subject: [coreboot] [commit] r6430 - trunk/src/cpu/amd/model_fxx
Message-ID: <E1PvHeS-0007cW-35@ra.coresystems.de>

Author: jakllsch
Date: Fri Mar  4 00:09:43 2011
New Revision: 6430
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6430

Log:
Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.
With this change the last P-state entry of the last CPU in the table
is successfully conveyed into the SSDT.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/cpu/amd/model_fxx/powernow_acpi.c

Modified: trunk/src/cpu/amd/model_fxx/powernow_acpi.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/powernow_acpi.c	Thu Mar  3 21:52:50 2011	(r6429)
+++ trunk/src/cpu/amd/model_fxx/powernow_acpi.c	Fri Mar  4 00:09:43 2011	(r6430)
@@ -622,7 +622,7 @@
 		Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage);
 		Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100;
 		Pstate_num++;
-	} while ((Pstate_num < MAXP) && (data->pstates[Pstate_num].freqMhz != 0));
+	} while ((Pstate_num < MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0));
 
 	for (i=0;i<Pstate_num;i++)
 		printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i,



From jankeso at gmail.com  Thu Mar  3 19:03:46 2011
From: jankeso at gmail.com (=?UTF-8?Q?Micha=C5=82_Janke?=)
Date: Thu, 3 Mar 2011 19:03:46 +0100
Subject: [coreboot] Add NSC PC87364 support to superiotool
In-Reply-To: <1299105021.4793.56.camel@localhost>
References: <1299105021.4793.56.camel@localhost>
Message-ID: <AANLkTikrUOwmN4NwZkwerYDGzKS2X0iTFmgLZHmQc-JM@mail.gmail.com>

Hi Michael,

seems to me that the GPIO is accessed as you predicted. I attach the
output of superiorool -deV.

Regards,
Michal

2011/3/2 Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>:
> Hello jankeso,
>
> in the process of writing a board enable procedure for your mainboard I
> stumbled upon the fact that the chip used to control the write enable
> line is most likely your Super I/O chip, which is a NSC PC87364.
> superiotool currently does not support dumping that chip, so I can not
> verify that indeed the GPIO port of the Super I/O chip is accessed (at
> address 0x80C). I attached a patch to dump the contents of that chip to
> this mail. Please apply that patch to current superiotool CVS sources
> (to be obtained from svn://coreboot.org/repos/trunk/util/superiotool)
> and attach the output to a reply to this mail or upload to
> paste.flashrom.org.
>
> This mail has been cc'ed to the coreboot list for getting this patch
> included into superiotool. If something is wrong with that patch, please
> Cc: me, as I am not subscribed to the coreboot list. Thanks.
>
> Regards,
> ?Michael Karcher
>
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From stefan.reinauer at coreboot.org  Fri Mar  4 04:47:42 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Fri, 4 Mar 2011 04:47:42 +0100
Subject: [coreboot] Troubles with 17'' WXGA on Roda RK886EX
In-Reply-To: <AANLkTimm2OJhUz_Ogh682yUZusJB3inkEkePtwoiJ96x@mail.gmail.com>
References: <AANLkTimm2OJhUz_Ogh682yUZusJB3inkEkePtwoiJ96x@mail.gmail.com>
Message-ID: <20110304034742.GA26988@coreboot.org>

* Vitaly Chertovskih <chertovs at gmail.com> [110303 20:08]:
> Hi!
>  
> I'm experiencing some troubles with VGA on notebook "Roda RF8". That notebook's
> motherboard and other specification is exact to Roda RK886EX, only the screen
> is larger (17'' WXGA 1440x900).
> On that week I installed coreboot on Roda RK886EX, it starts perfectly. But
> when i flashed the same coreboot on notebook RF8 - the screen is lightened, but
> remains blank. When i connect external LCD - it(external) works well with
> coreboot. So, i think, that the trouble is in initialization of that internal
> widescreen LCD.
> 
> Roda RK886EX have LCD 15.1  XGA (1024x768) - works perfect.
> Roda RF8 - 17'' WXGA 1440x900 - blank (but lightened) screen (other init and OS
> booting is perfect with external LCD)
> 
> The log file says nothing - when coreboot or seabios calls vga.bin - all is ok,
> like on Roda RK886EX.
> 
> Please, help me. Where and how i can fix that?
> 
> P.S.
> 
> I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS image (I
> download it from coreboot.org), and including VGA onboard rom, grabbed from /
> dev/mem as described in howtos on coreboot.org.
> 
> I include my log from COM1.

Hi Vitaly,

it looks like your option rom does not match the graphics device

PCI: 00:02.0 [8086/27ae]

Your option rom seems to be for 8086/27a2 ...

Please also increase the log level of SeaBIOS.

Stefan






From stefan.reinauer at coreboot.org  Fri Mar  4 04:49:25 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Fri, 4 Mar 2011 04:49:25 +0100
Subject: [coreboot] Add NSC PC87364 support to superiotool
In-Reply-To: <1299105021.4793.56.camel@localhost>
References: <1299105021.4793.56.camel@localhost>
Message-ID: <20110304034925.GA29179@coreboot.org>

* Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de> [110302 23:30]:
> Hello jankeso,
> 
> in the process of writing a board enable procedure for your mainboard I
> stumbled upon the fact that the chip used to control the write enable
> line is most likely your Super I/O chip, which is a NSC PC87364.
> superiotool currently does not support dumping that chip, so I can not
> verify that indeed the GPIO port of the Super I/O chip is accessed (at
> address 0x80C). I attached a patch to dump the contents of that chip to
> this mail. Please apply that patch to current superiotool CVS sources
> (to be obtained from svn://coreboot.org/repos/trunk/util/superiotool)
> and attach the output to a reply to this mail or upload to
> paste.flashrom.org.
> 
> This mail has been cc'ed to the coreboot list for getting this patch
> included into superiotool. If something is wrong with that patch, please
> Cc: me, as I am not subscribed to the coreboot list. Thanks.
> 
> Regards,
>   Michael Karcher

> Add National Semiconductors PC87364.
> 
> Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>





From bari at onelabs.com  Fri Mar  4 05:10:10 2011
From: bari at onelabs.com (bari)
Date: Thu, 03 Mar 2011 22:10:10 -0600
Subject: [coreboot] Help for motherboard
In-Reply-To: <ryld3m8o7x5.fsf@personal.machine.of.sharard.com>
References: <86pqqouuco.fsf@personal.machine.of.sharard.com>	<4D5FD0F9.10407@gmail.com>	<86hbc0ufkg.fsf@personal.machine.of.sharard.com>	<4D6004A4.9050409@gmail.com>
	<ryld3m8o7x5.fsf@personal.machine.of.sharard.com>
Message-ID: <4D706622.8080400@onelabs.com>

sh4r4d at gmail.com wrote:

> So I wanted to know if I have to purchase `GIGABYTE_GA-MA785GMT-US2H'
> as `GIGABYTE_GA-MA785GMT-UD2H' is not available, Could it be easy
> to get coreboot in it as `GIGABYTE_GA-MA785GMT-UD2H' have been already
> supported, might be it is a newer version of `GIGABYTE_GA-MA785GMT-UD2H'?

Either board works with coreboot with minor tweaking. Compare the 
chipset, memory type and super IO on boards. If coreboot supports the 
devices then most of the work is already done. Gigabyte boards usually 
have the dual BIOS device circuit that make flash programming a bit more 
complicated. You might have to check if Flashrom ever was patched to 
support it.

-Bari



From zxy__1127 at 163.com  Fri Mar  4 06:46:15 2011
From: zxy__1127 at 163.com (zxy__1127)
Date: Fri, 4 Mar 2011 13:46:15 +0800
Subject: [coreboot] Troubles with 17'' WXGA on Roda RK886EX
References: <AANLkTimm2OJhUz_Ogh682yUZusJB3inkEkePtwoiJ96x@mail.gmail.com>,
	<20110304034742.GA26988@coreboot.org>
Message-ID: <201103041346155462338@163.com >

Hi 

I think it's a issue about lvds setting in VGA rom.
You can get the vbios from Intel's web site, and you need to modify it to fit your screen.
8086/27ae 8086/27a2 just different ID,because your have let the VGA rom run, so it doesn't matter  :-)  


thanks!
2011-03-04 



zxy__1127 



 
* Vitaly Chertovskih  <chertovs at gmail.com > [110303 20:08]:
> Hi!
>  
> I'm experiencing some troubles with VGA on notebook "Roda RF8". That notebook's
> motherboard and other specification is exact to Roda RK886EX, only the screen
> is larger (17'' WXGA 1440x900).
> On that week I installed coreboot on Roda RK886EX, it starts perfectly. But
> when i flashed the same coreboot on notebook RF8 - the screen is lightened, but
> remains blank. When i connect external LCD - it(external) works well with
> coreboot. So, i think, that the trouble is in initialization of that internal
> widescreen LCD.
> 
> Roda RK886EX have LCD 15.1  XGA (1024x768) - works perfect.
> Roda RF8 - 17'' WXGA 1440x900 - blank (but lightened) screen (other init and OS
> booting is perfect with external LCD)
> 
> The log file says nothing - when coreboot or seabios calls vga.bin - all is ok,
> like on Roda RK886EX.
> 
> Please, help me. Where and how i can fix that?
> 
> P.S.
> 
> I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS image (I
> download it from coreboot.org), and including VGA onboard rom, grabbed from /
> dev/mem as described in howtos on coreboot.org.
> 
> I include my log from COM1.

Hi Vitaly,

it looks like your option rom does not match the graphics device

PCI: 00:02.0 [8086/27ae]

Your option rom seems to be for 8086/27a2 ...

Please also increase the log level of SeaBIOS.

Stefan




-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
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From stefan.reinauer at coreboot.org  Fri Mar  4 07:05:57 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Thu, 03 Mar 2011 22:05:57 -0800
Subject: [coreboot] Troubles with 17'' WXGA on Roda RK886EX
In-Reply-To: <201103041346155462338@163.com >
References: <AANLkTimm2OJhUz_Ogh682yUZusJB3inkEkePtwoiJ96x@mail.gmail.com>,
	<20110304034742.GA26988@coreboot.org>
	<201103041346155462338@163.com >
Message-ID: <4D708145.6060109@coreboot.org>

On 3/3/11 9:46 PM, zxy__1127 wrote:
> Hi
> I think it's a issue about lvds setting in VGA rom.
> You can get the vbios from Intel's web site, and you need to modify it
> to fit your screen.
> 8086/27ae 8086/27a2 just different ID,because your have let the VGA
> rom run, so it doesn't matter :-)

It should be easier to grab the vbios from the existing BIOS. According
to the logs that were attached, at least coreboot did not run the vbios
at all.

Stefan


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From zxy__1127 at 163.com  Fri Mar  4 07:49:50 2011
From: zxy__1127 at 163.com (zxy__1127)
Date: Fri, 4 Mar 2011 14:49:50 +0800
Subject: [coreboot] Troubles with 17'' WXGA on Roda RK886EX
References: <AANLkTimm2OJhUz_Ogh682yUZusJB3inkEkePtwoiJ96x@mail.gmail.com>,
	<20110304034742.GA26988@coreboot.org>,
	<201103041346155462338@163.com, >, <4D708145.6060109@coreboot.org>
Message-ID: <201103041449504370312@163.com >

Then need to let it run correctlly first.
3 steps:
1)  CONFIG_VGA_BIOS_ID="8086,27ae"
2)  modify VGA rom in hex, offset 46h =0xae
3?ignor the checksun error in payload(seabios....).

may be there are  better ways,let me know :-)

Thanks!
2011-03-04 



zxy__1127 
 
On 3/3/11 9:46 PM, zxy__1127 wrote: 
Hi 

I think it's a issue about lvds setting in VGA rom.
You can get the vbios from Intel's web site, and you need to modify it to fit your screen.
8086/27ae 8086/27a2 just different ID,because your have let the VGA rom run, so it doesn't matter  :-) 


It should be easier to grab the vbios from the existing BIOS. According to the logs that were attached, at least coreboot did not run the vbios at all.

Stefan
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From Patrick.Georgi at secunet.com  Fri Mar  4 08:15:17 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Fri, 4 Mar 2011 08:15:17 +0100
Subject: [coreboot] [PATCH] Move cmos.default handling to bootblock
In-Reply-To: <1298028503.3970.100.camel@linux-0a8x.site>
References: <1296566674.6489.78.camel@linux-0a8x.site>
	<20110218025515.26931.qmail@stuge.se>
	<1298012947.3970.1.camel@linux-0a8x.site>
	<20110218111538.17715.qmail@stuge.se>
	<1298028503.3970.100.camel@linux-0a8x.site>
Message-ID: <1299222917.16762.1.camel@linux-0a8x.site>

Am Freitag, den 18.02.2011, 12:28 +0100 schrieb Georgi, Patrick:
> Am Freitag, den 18.02.2011, 12:15 +0100 schrieb Peter Stuge:
> > > HAVE_CMOS_DEFAULT. Without this, cmos.default isn't put into CBFS
> > > (by default), and without that file, no write happens.
> > But it's a mainboard knob, not a user knob, right?
> We don't deliver cmos.default files, so this is a user setting at this
> time.
> This might change, and then we should reevaluate how we handle CMOS.
> But USE_OPTION_TABLE should disable it _all_ anyway.
> 
> So you already have:
> - no CMOS at all
> - CMOS support, but no cmos.default
> - CMOS support with cmos.default

> > * Strict mode (requires NVRAM to always be correct, or will fail to
> >   boot. maybe also other extra checks in the code)
> "Fail to boot"? I wonder about its use.
Ping again?
What's missing except for new features (eg. more fine-grained control
that allows users to build images that won't boot in certain
circumstances)?


Patrick

-- 
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
>  
> Patrick Georgi
> Fachbereich SINA-Entwicklung
> Gesch?ftsbereich Hochsicherheit
> secunet Security Networks AG
> Mergenthalerallee 77
> 65760 Eschborn, Germany
> Telefon +49 201 54 54-3610
> Telefax +49 201 54 54-1325
> Patrick.Georgi at secunet.com 
> www.secunet.com 
> 
> Sitz: Kronprinzenstra?e 30, 45128 Essen
> Amtsgericht Essen HRB 13615
> Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
> Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
>   
> Diese E-Mail kann vertrauliche Informationen enthalten. Falls Sie diese
> E-Mail irrt?mlich erhalten haben, informieren Sie bitte unverz?glich
> den Absender und l?schen Sie diese E-Mail von jedem Rechner, auch von
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From stefan.reinauer at coreboot.org  Fri Mar  4 09:32:33 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Fri, 04 Mar 2011 00:32:33 -0800
Subject: [coreboot] [PATCH] Move cmos.default handling to bootblock
In-Reply-To: <1296566674.6489.78.camel@linux-0a8x.site>
References: <1296566674.6489.78.camel@linux-0a8x.site>
Message-ID: <4D70A3A1.5050402@coreboot.org>

On 2/1/11 2:50 AM, Patrick Georgi wrote:
> The cmos.default code wasn't actually used so far, due to an oversight
> when forward-porting this feature from an old branch.
>
> - Extend walkcbfs' use by factoring out the stage handling into C code.
> - New sanitize_cmos() function that looks if CMOS data is invalid and
>    cmos.default exists and if so overwrites CMOS with cmos.default data.
> - Use sanitize_cmos() in both bootblock implementations.
> - Drop the need to reboot after writing CMOS: CMOS wasn't used so far,
>    so we can go on without a reboot.
> - Remove the restriction that cmos.default only works on CAR boards.
> - Always build in cmos.default support on boards that USE_OPTION_TABLE.
>
> Signed-off-by: Patrick Georgi<patrick.georgi at secunet.com>
>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

with some optional comments below

> index 895a185..a808cec 100644
> --- a/src/arch/x86/include/bootblock_common.h
> +++ b/src/arch/x86/include/bootblock_common.h
> @@ -17,17 +17,45 @@ static void bootblock_northbridge_init(void) { }
>   static void bootblock_southbridge_init(void) { }
>   #endif
>
> -static unsigned long findstage(char* target)
> +static void *walkcbfs(char *target)
>   {
> -	unsigned long entry;
> +	void *entry;
>   	asm volatile (
>   		"mov $1f, %%esp\n\t"
> -		"jmp walkcbfs\n\t"
> +		"jmp walkcbfs_asm\n\t"
maybe just call it _walkcbfs ?
> +/* just enough to support findstage. copied because the original version doesn't easily pass through romcc */
> +struct cbfs_stage {
> +	unsigned long compression;
> +	unsigned long entry; // this is really 64bit, but properly endianized
Would it make sense to add an unsigned long entry_high after this, in 
this case? Or use a union or uint64_t for entry?

> +#if CONFIG_USE_OPTION_TABLE
> +#include<pc80/mc146818rtc.h>
Since you start using cmos in the bootblock, you might have to consider 
enabling RCBA and the upper 128 bytes of CMOS in some Intel 
southbridges' bootblock.c

> +static void sanitize_cmos(void)
> +{
> +	if (cmos_error() || !cmos_chksum_valid()) {
Is this reliably working on hardware? I remember cmos_error being flaky 
on ICH7 early on at some point.

> diff --git a/src/pc80/mc146818rtc_early.c b/src/pc80/mc146818rtc_early.c
> index 920deda..d09d6b9 100644
> --- a/src/pc80/mc146818rtc_early.c
> +++ b/src/pc80/mc146818rtc_early.c
> @@ -11,15 +11,6 @@
>   #error "CONFIG_MAX_REBOOT_CNT too high"
>   #endif
>
> -#if CONFIG_USE_CMOS_RECOVERY
> -#include<cbfs.h>
> -#include<console/loglevel.h>
> -
> -int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
> -#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
> -#define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg)
> -#endif
> -
>   static int cmos_error(void)
>   {
>   	unsigned char reg_d;
> @@ -63,25 +54,6 @@ static inline int do_normal_boot(void)
>   	unsigned char byte;
>
>   	if (cmos_error() || !cmos_chksum_valid()) {
> -#if CONFIG_USE_CMOS_RECOVERY
> -		char *cmos_default = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT);
> -		if (cmos_default) {
> -			int i;
> -			printk_warning("WARNING - CMOS CORRUPTED. RESTORING DEFAULTS.\n");
> -			/* First 14 bytes are reserved for
> -			   RTC and ignored by nvramtool, too.
> -			   Only 128 bytes: 128+ requires cmos configuration and
> -			   contains only suspend-to-ram data, which isn't part
> -			   of the recovery procedure. */
> -			for (i = 14; i<  128; i++) {
> -				cmos_write(cmos_default[i], i);
> -			}
> -			/* Now reboot to run with default cmos. */
> -			outb(0x06, 0xcf9);
> -			for (;;) asm("hlt"); /* Wait for reset! */
> -		}
> -#endif
> -
How does cmos recovery behave on non-CAR systems if this is removed? It 
would be nice to if we could make sure it works everywhere



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From chertovs at gmail.com  Fri Mar  4 10:25:57 2011
From: chertovs at gmail.com (Vitaly Chertovskih)
Date: Fri, 4 Mar 2011 12:25:57 +0300
Subject: [coreboot] Troubles with 17'' WXGA on Roda RK886EX
In-Reply-To: <201103041449504370312@163.com>
References: <AANLkTimm2OJhUz_Ogh682yUZusJB3inkEkePtwoiJ96x@mail.gmail.com>
	<20110304034742.GA26988@coreboot.org>
	<4D708145.6060109@coreboot.org> <201103041449504370312@163.com>
Message-ID: <AANLkTimV=U=nF+K8ffU81-q=y8k1gJCKCdVPy0bN1t3G@mail.gmail.com>

Hi!

I've grabbed the right one vga bios with 0xae.Ignoring the seabios checksum,
it starts normally. Now, coreboot copies it into mem and i can see intel
vgabios boot logo, but it appears only on the external LCD. The problem
remains the same. Internal LCD is blank, but highlightened. On the 15'' Roda
RK8 - all is good. On my 17'' RF8 - blank screen. What shall i do?

Please, help.

Here is some log.

Coreboot init VGA:
****
CBFS: follow chain: fff00000 + 28 + 54f + align -> fff00580
Check pci8086,27ae.rom
In CBFS, ROM address for PCI: 00:02.0 = fff005b8
PCI expansion ROM, signature 0xaa55, INIT size 0xea00, data ptr 0x0040
PCI ROM image, vendor ID 8086, device ID 27ae,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from fff005b8 to 0xc0000, 0xea00 bytes
Real mode stub @00000600: 606 bytes
Calling Option ROM...
DISPLAY=3
... Option ROM returned.

******

Seabios :

*****

Scan for VGA option rom
Running option rom at c000:0003
unimplemented handle_155fXX:40:
   a=10005f40  b=00000011  c=00000055  d=00000000 ds=0000 es=c000 ss=0000
  si=0008c2b0 di=00000080 bp=00006efc sp=00006e6a cs=c000 ip=4bd4  f=0046
unimplemented handle_155fXX:40:
   a=00005f35  b=0000078f  c=00000002  d=000000c0 ds=c000 es=c000 ss=0000
  si=00071423 di=00000080 bp=00006efc sp=00006ed6 cs=c000 ip=4bd4  f=0046
Turning on vga text mode console

*******
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From jakllsch at kollasch.net  Fri Mar  4 15:55:37 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Fri, 4 Mar 2011 14:55:37 +0000
Subject: [coreboot] [patch] P-states for selected socket 754 processors
Message-ID: <20110304145537.GB18832@tarantulon.kollasch.net>

Add P-states for select Socket 754 processors.

States for AMA3000BEX5AR, SDA3100AIO3BX, and SDA3400AIO3BX
are from AMD document 30430 3.51.  States for ADA3200AIO4BX
derived from SSDT of a MS-7135.  States for TMDML34BKX5LD derived
from legacy PowerNow! table of a MS-7135, and therefore lack accurate
TDP information.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
-----
-------------- next part --------------
Index: src/cpu/amd/model_fxx/powernow_acpi.c
===================================================================
--- src/cpu/amd/model_fxx/powernow_acpi.c	(revision 6430)
+++ src/cpu/amd/model_fxx/powernow_acpi.c	(working copy)
@@ -563,6 +563,21 @@
 	  {1800, 1200, 748}, {1000, 1100, 466}}},
 	{3000, 0x4, 0x10ff0, 0xa, 0xa, 670,
 	 {{1000, 1100, 210}}},
+	/* AMA3000BEX5AR */
+	{3000, 0x4, 0xf4a, 0xa, 0x0, 815,
+	 {{1600, 1400, 570}, {800, 1100, 190}}},
+	/* TMDML34BKX5LD, needs real TDP info */
+	{34, 0xa, 0x20f42, 0xa, 0x0, 350,
+	 {{1600, 1400, 340}, {800, 1000, 330}}},
+	/* SDA3100AIO3BX */
+	{3100, 0x26, 0x20fc2, 0xa, 0xa, 590,
+	 {{1000, 1100, 217}}},
+	/* SDA3400AIO3BX */
+	{3400, 0x26, 0x20fc2, 0xc, 0xc, 590,
+	 {{1800, 1350, 496}, {1000, 1100, 207}}},
+	/* ADA3200AIO4BX */
+	{3200, 0x4, 0x20fc2, 0xe, 0xe, 670,
+	 {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}},
 };
 
 static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)

From marcj303 at gmail.com  Fri Mar  4 17:37:11 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 4 Mar 2011 09:37:11 -0700
Subject: [coreboot] [patch] P-states for selected socket 754 processors
In-Reply-To: <20110304145537.GB18832@tarantulon.kollasch.net>
References: <20110304145537.GB18832@tarantulon.kollasch.net>
Message-ID: <AANLkTineqBxUDH=T3jWDznjbxzhvD7yVEqW7YsETwfdc@mail.gmail.com>

On Fri, Mar 4, 2011 at 7:55 AM, Jonathan A. Kollasch
<jakllsch at kollasch.net> wrote:
> Add P-states for select Socket 754 processors.
>
> States for AMA3000BEX5AR, SDA3100AIO3BX, and SDA3400AIO3BX
> are from AMD document 30430 3.51. ?States for ADA3200AIO4BX
> derived from SSDT of a MS-7135. ?States for TMDML34BKX5LD derived
> from legacy PowerNow! table of a MS-7135, and therefore lack accurate
> TDP information.
>
> Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>

Acked-by: Marc Jones <marcj303 at gmail.com>

-- 
http://se-eng.com



From svn at coreboot.org  Fri Mar  4 18:09:21 2011
From: svn at coreboot.org (repository service)
Date: Fri, 04 Mar 2011 18:09:21 +0100
Subject: [coreboot] [commit] r6431 - trunk/src/mainboard/amd/bimini_fam10
Message-ID: <E1PvYVF-00027m-M8@ra.coresystems.de>

Author: oxygene
Date: Fri Mar  4 18:09:21 2011
New Revision: 6431
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6431

Log:
Redo r6099 after copy&pasted code reintroduced DIMMx #defines

Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Patrick Georgi <patrick at georgi-clan.de>

Modified:
   trunk/src/mainboard/amd/bimini_fam10/romstage.c

Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/bimini_fam10/romstage.c	Fri Mar  4 00:09:43 2011	(r6430)
+++ trunk/src/mainboard/amd/bimini_fam10/romstage.c	Fri Mar  4 18:09:21 2011	(r6431)
@@ -49,6 +49,7 @@
 #include "southbridge/amd/rs780/early_setup.c"
 #include "southbridge/amd/sb800/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
+#include <spd.h>
 
 static void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -77,11 +78,6 @@
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);



From svn at coreboot.org  Fri Mar  4 21:01:15 2011
From: svn at coreboot.org (repository service)
Date: Fri, 04 Mar 2011 21:01:15 +0100
Subject: [coreboot] [commit] r6432 - trunk/src/cpu/amd/model_fxx
Message-ID: <E1PvbBb-0007bd-UU@ra.coresystems.de>

Author: jakllsch
Date: Fri Mar  4 21:01:15 2011
New Revision: 6432
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6432

Log:
Add P-states for select Socket 754 processors.

States for AMA3000BEX5AR, SDA3100AIO3BX, and SDA3400AIO3BX
are from AMD document 30430 3.51.  States for ADA3200AIO4BX
derived from SSDT of a MS-7135.  States for TMDML34BKX5LD derived
from legacy PowerNow! table of a MS-7135, and therefore lack accurate
TDP information.

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/cpu/amd/model_fxx/powernow_acpi.c

Modified: trunk/src/cpu/amd/model_fxx/powernow_acpi.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/powernow_acpi.c	Fri Mar  4 18:09:21 2011	(r6431)
+++ trunk/src/cpu/amd/model_fxx/powernow_acpi.c	Fri Mar  4 21:01:15 2011	(r6432)
@@ -563,6 +563,21 @@
 	  {1800, 1200, 748}, {1000, 1100, 466}}},
 	{3000, 0x4, 0x10ff0, 0xa, 0xa, 670,
 	 {{1000, 1100, 210}}},
+	/* AMA3000BEX5AR */
+	{3000, 0x4, 0xf4a, 0xa, 0x0, 815,
+	 {{1600, 1400, 570}, {800, 1100, 190}}},
+	/* TMDML34BKX5LD, needs real TDP info */
+	{34, 0xa, 0x20f42, 0xa, 0x0, 350,
+	 {{1600, 1400, 340}, {800, 1000, 330}}},
+	/* SDA3100AIO3BX */
+	{3100, 0x26, 0x20fc2, 0xa, 0xa, 590,
+	 {{1000, 1100, 217}}},
+	/* SDA3400AIO3BX */
+	{3400, 0x26, 0x20fc2, 0xc, 0xc, 590,
+	 {{1800, 1350, 496}, {1000, 1100, 207}}},
+	/* ADA3200AIO4BX */
+	{3200, 0x4, 0x20fc2, 0xe, 0xe, 670,
+	 {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}},
 };
 
 static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)



From patrick at georgi-clan.de  Fri Mar  4 21:07:30 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 04 Mar 2011 21:07:30 +0100
Subject: [coreboot] [PATCH] Move cmos.default handling to bootblock
In-Reply-To: <4D70A3A1.5050402@coreboot.org>
References: <1296566674.6489.78.camel@linux-0a8x.site>
	<4D70A3A1.5050402@coreboot.org>
Message-ID: <4D714682.9080705@georgi-clan.de>

Am 04.03.2011 09:32, schrieb Stefan Reinauer:
>> index 895a185..a808cec 100644
>> --- a/src/arch/x86/include/bootblock_common.h
>> +++ b/src/arch/x86/include/bootblock_common.h
>> @@ -17,17 +17,45 @@ static void bootblock_northbridge_init(void) { }
>>  static void bootblock_southbridge_init(void) { }
>>  #endif
>>  
>> -static unsigned long findstage(char* target)
>> +static void *walkcbfs(char *target)
>>  {
>> -	unsigned long entry;
>> +	void *entry;
>>  	asm volatile (
>>  		"mov $1f, %%esp\n\t"
>> -		"jmp walkcbfs\n\t"
>> +		"jmp walkcbfs_asm\n\t"
> maybe just call it _walkcbfs ?
I thought about it, but I wanted to avoid confusion in case some
compiler uses _ prefixes (in which case that would be __walkcbfs).

>> +/* just enough to support findstage. copied because the original version doesn't easily pass through romcc */
>> +struct cbfs_stage {
>> +	unsigned long compression;
>> +	unsigned long entry; // this is really 64bit, but properly endianized
> Would it make sense to add an unsigned long entry_high after this, in
> this case? Or use a union or uint64_t for entry?
unsigned long entry_high; is better (romcc and all that)

>> +#if CONFIG_USE_OPTION_TABLE
>> +#include <pc80/mc146818rtc.h>
> Since you start using cmos in the bootblock, you might have to consider
> enabling RCBA and the upper 128 bytes of CMOS in some Intel
> southbridges' bootblock.c
The recovery code explicitely covers the first 128 bytes only - so far
the upper 128 bytes are used for suspend-to-ram data only, so this isn't
urgent yet.

RCBA, yes.. I'll take a look, but I think it worked when I tested it.

>> +static void sanitize_cmos(void)
>> +{
>> +	if (cmos_error() || !cmos_chksum_valid()) {
> Is this reliably working on hardware? I remember cmos_error being flaky
> on ICH7 early on at some point.
And I vaguely remember that we managed to stabilize this by tweaking
registers.

> How does cmos recovery behave on non-CAR systems if this is removed? It
> would be nice to if we could make sure it works everywhere
The only caller of this function is bootblock_normal - so by default,
this code wasn't used at all.

The patch works on qemu, which is a "non-CAR" system, right?



Patrick



From brandonrd7 at gmail.com  Sat Mar  5 01:17:35 2011
From: brandonrd7 at gmail.com (Brandon Dowdy)
Date: Sat, 5 Mar 2011 00:17:35 +0000
Subject: [coreboot] Here are the specs of my laptop:
Message-ID: <AANLkTikXQzpgvrX1p6J8XcXgjkEaBf28btFqrjKp1pO=@mail.gmail.com>

Name: Toshiba A135-S4437
CPU: Intel Core Duo
Northbridge: Intel 945GM
Southbridge: Intel ICH7-M
EC: ENE KB910QF*
Super I/O: I don't know
Flash Chip: SST SST39VF080**
Flash Chip Size: 1MB
Flash Chip Supported: Yes
Flash Chip Type: Parallel***






* This is from a schematic I looked at online.

** This flash chip is Parallel although the southbridge supports only FWH.
This might be a flashrom bug or it might be that my laptop uses a special
mechanism.
*** That is explained on the Supported Hardware page of the flashrom wiki.
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From c-d.hailfinger.devel.2006 at gmx.net  Fri Mar  4 20:22:53 2011
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Mar 2011 20:22:53 +0100
Subject: [coreboot] [flashrom]  Add NSC PC87364 support to superiotool
In-Reply-To: <20110304034925.GA29179@coreboot.org>
References: <1299105021.4793.56.camel@localhost>
	<20110304034925.GA29179@coreboot.org>
Message-ID: <4D713C0D.5030701@gmx.net>

Auf 04.03.2011 04:49, Stefan Reinauer schrieb:
> * Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de> [110302 23:30]:
>   
>> Add National Semiconductors PC87364.
>>
>> Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
>>     
> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
>   

Michael, AFAIK the flashrom and coreboot repositories have the same user
rights, so in theory you should be able to commit.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From mr.nuke.me at gmail.com  Sun Mar  6 00:56:21 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Sun, 06 Mar 2011 01:56:21 +0200
Subject: [coreboot] Issue mainboard asus a8n-e
In-Reply-To: <4D6C20D3.30204@swissonline.ch>
References: <4D6C20D3.30204@swissonline.ch>
Message-ID: <4D72CDA5.5090702@gmail.com>

On 03/01/2011 12:25 AM, ors wrote:
> Author: raby71
> Date: Mon Feb 28 22:00 2011
> last Revision: 6380
> 
> hi all
> 
> I try to work my board (asus a8n-e) with coreboot. I compiled coreboot
> with a debian 5.07 installation.
Try building coreboot with crossgcc. just cd into util/crossgcc/ and
build crossgcc. The coreboot build system should automatically use it if
it's built.


> flashrom, the system starts, also the monitor until to boot-promt (or
> payload terminal) but is not possible to type anything with keyboard
> (usb or ps/2) to monitor,
Sounds like an IRQ issue to me.

> simply: i'm not able to take further actions.
> I compiled coreboot with payloads filo grub2 and seabios, but i have in
> all my tries the same effect.
>
Select the Seabios stable option in make menuconfig. It should at the
very least build seabios with console output, so we can see what seabios
has to say. (remember, with crossgcc).

> !! Resource didn't fit !!
>   aligned base 400 size 100 limit 200
>   4ff needs to be <= 200 (limit)
>   PCI: 00:01.0 68 *  [0x800 - 0x8ff] io
Someone wiser (than me), please have a look at this error. I have no
idea why it happens, or what the implications are.

> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
> amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0
> link 0x0
> 
> FATAL: stdin closed
> picocom v1.4
Output got truncated here. Please make sure output is not truncated, and
we also get the SeaBIOS part.

Alex



From mr.nuke.me at gmail.com  Sun Mar  6 01:35:10 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Sun, 06 Mar 2011 02:35:10 +0200
Subject: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard
In-Reply-To: <4D6EDDB0.3000003@settoplinux.org>
References: <4D5C5664.8040601@gmail.com>	<4D66673D.1030004@gmail.com>	<4D6EA744.6030308@gmail.com>	<20110302213811.27526.qmail@stuge.se>	<4D6EB96D.40508@settoplinux.org>
	<4D6EBE99.6050106@gmail.com> <4D6EDDB0.3000003@settoplinux.org>
Message-ID: <4D72D6BE.7000403@gmail.com>

On 03/03/2011 02:15 AM, Joseph Smith wrote:
> Alex have you tried adding irqpoll to your command line? It may give you
> some clues?
> 
Just did: http://pastebin.com/6n2AV3DU

I'm looking over the output to see if there's anything useful.

Alex




From buurin at gmail.com  Sun Mar  6 02:43:46 2011
From: buurin at gmail.com (Keith Hui)
Date: Sat, 5 Mar 2011 20:43:46 -0500
Subject: [coreboot] AGP video card reset again showing only half the RAM.
	Why?
Message-ID: <AANLkTi=wqgZL6+370mB=4S-kDrqp3HWrW1Ee-N0t_thd@mail.gmail.com>

Tonight I observed that on my P2B-LS board, my nvidia geforce fx5200
AGP card with 128MB ram, after the first initialization run showing
128MB RAM, reset again showing only 64MB RAM. Is this as simple as a
AGP graphics aperture problem? Or is it something more?



From hagigatali at gmail.com  Sun Mar  6 09:58:08 2011
From: hagigatali at gmail.com (ali hagigat)
Date: Sun, 6 Mar 2011 12:28:08 +0330
Subject: [coreboot] a question about ASUS, MEW-AM
Message-ID: <AANLkTik=C4V_5vYXG7knWF9Hm2qinkPTzr-DhzESb-sR@mail.gmail.com>

Where the graphics card is initialized in the source code? Is it using
Internal graphics card or external? I found some vga routines in pc80
and console folders.



From flashrom at mkarcher.dialup.fu-berlin.de  Sun Mar  6 00:53:03 2011
From: flashrom at mkarcher.dialup.fu-berlin.de (Michael Karcher)
Date: Sun, 06 Mar 2011 00:53:03 +0100
Subject: [coreboot] [flashrom]  Add NSC PC87364 support to superiotool
In-Reply-To: <4D713C0D.5030701@gmx.net>
References: <1299105021.4793.56.camel@localhost>
	<20110304034925.GA29179@coreboot.org>  <4D713C0D.5030701@gmx.net>
Message-ID: <1299369183.5453.5.camel@localhost>

Hello coreboot developers,

> >> Add National Semiconductors PC87364.
> >> Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
> > Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
> Michael, AFAIK the flashrom and coreboot repositories have the same user
> rights, so in theory you should be able to commit.

how would you like me to proceed? Technically I most likely have commit
rights to that repo, but I never felt as coreboot developer and don't
read the coreboot mailing list. Should I nevertheless commit myself or
should I have some coreboot guy commit that patch?

Regards,
  Michael Karcher




From mr.nuke.me at gmail.com  Sun Mar  6 15:01:15 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Sun, 06 Mar 2011 16:01:15 +0200
Subject: [coreboot] [flashrom]  Add NSC PC87364 support to superiotool
In-Reply-To: <1299369183.5453.5.camel@localhost>
References: <1299105021.4793.56.camel@localhost>	<20110304034925.GA29179@coreboot.org>
	<4D713C0D.5030701@gmx.net> <1299369183.5453.5.camel@localhost>
Message-ID: <4D7393AB.8030505@gmail.com>

On 03/06/2011 01:53 AM, Michael Karcher wrote:
> Hello coreboot developers,
> 
>>>> Add National Semiconductors PC87364.
>>>> Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
>>> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
>> Michael, AFAIK the flashrom and coreboot repositories have the same user
>> rights, so in theory you should be able to commit.
> 
> how would you like me to proceed? Technically I most likely have commit
> rights to that repo, but I never felt as coreboot developer and don't
> read the coreboot mailing list. Should I nevertheless commit myself or
> should I have some coreboot guy commit that patch?
> 
It was acked by Stefan. I think you can confidently commit.

Alex



From paulepanter at users.sourceforge.net  Sun Mar  6 15:35:23 2011
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sun, 06 Mar 2011 15:35:23 +0100
Subject: [coreboot] [flashrom]  Add NSC PC87364 support to superiotool
In-Reply-To: <4D7393AB.8030505@gmail.com>
References: <1299105021.4793.56.camel@localhost>
	<20110304034925.GA29179@coreboot.org> <4D713C0D.5030701@gmx.net>
	<1299369183.5453.5.camel@localhost>  <4D7393AB.8030505@gmail.com>
Message-ID: <1299422123.28285.2.camel@mattotaupa>

Dear Michael,


I am adding you back to CC.

Am Sonntag, den 06.03.2011, 16:01 +0200 schrieb Alex G.:
> On 03/06/2011 01:53 AM, Michael Karcher wrote:

> >>>> Add National Semiconductors PC87364.
> >>>> Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
> >>> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
> >> Michael, AFAIK the flashrom and coreboot repositories have the same user
> >> rights, so in theory you should be able to commit.
> > 
> > how would you like me to proceed? Technically I most likely have commit
> > rights to that repo, but I never felt as coreboot developer and don't
> > read the coreboot mailing list. Should I nevertheless commit myself or
> > should I have some coreboot guy commit that patch?

> It was acked by Stefan. I think you can confidently commit.

I would also say that you can commit.

And Michael, why not become a coreboot developer and port your
motherboard. You would be warmly welcomed. ;-)


Thanks,

Paul
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From vidwer at gmail.com  Sun Mar  6 17:53:35 2011
From: vidwer at gmail.com (Idwer Vollering)
Date: Sun, 6 Mar 2011 17:53:35 +0100
Subject: [coreboot] ACPI breakage/questions and ramstage code question
In-Reply-To: <AANLkTiniZ=j66tw=mTKW0ddR2J3DT=XScO3inOFeGK9G@mail.gmail.com>
References: <AANLkTiniZ=j66tw=mTKW0ddR2J3DT=XScO3inOFeGK9G@mail.gmail.com>
Message-ID: <AANLkTinDFbW0+ecOkFHHHA_eQEs-qXjRYmVPnZXGtZZE@mail.gmail.com>

2011/3/2 Keith Hui <buurin at gmail.com>

> ---
> First, Mysterious breakage on experimental i82371eb ACPI stuff
>
> Rudolf, Idwer, and anyone that tried doing ACPI for the ASUS P2B
> series of boards:
>
> I'm seeing mysterious compiler breakge after updating my local copy to
> r6424. I copied that from P2B to P2B-LS and both break.


This breakage happens after "make distclean" too ? Backup your .config
first.
Do you have any local changes ?


> Make log says:
>
>    CC         southbridge/intel/i82371eb/fadt.driver.o
> src/southbridge/intel/i82371eb/fadt.c:35:35: error: expected ?)?
> before ?*? token
> make: *** [build/southbridge/intel/i82371eb/fadt.driver.o] Error 1
>
> Which points to this in the file:
>
> /**
>  * Create the Fixed ACPI Description Tables (FADT) for any board with this
> SB.
>  * Reference: ACPIspec40a, 5.2.9, page 118
>  */
> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void * dsdt)
>

That should be *fadt, *facs and *dsdt:
http://tracker.coreboot.org/trac/coreboot/browser/trunk/src/southbridge/intel/i82371eb/fadt.c#L35


> {
>        acpi_header_t *header = &(fadt->header);
>        device_t dev;
> [ Rest of function goes here]
> }
>
> Are any of you guys having the same problem?
>

No, not with archlinux' 'native' gcc and not with crossgcc (and not with
abuild, abuild uses crossgcc too).
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From svens at stackframe.org  Sun Mar  6 18:46:52 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sun,  6 Mar 2011 17:46:52 +0000
Subject: [coreboot] [PATCH] X60: add thermal zone 0
Message-ID: <1299433612-7431-1-git-send-email-svens@stackframe.org>

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/x60/acpi/ec.asl      |    4 +++-
 src/mainboard/lenovo/x60/acpi/thermal.asl |   26 ++++++++++++++++++++++++++
 2 files changed, 29 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl
index 775fa58..f18b665 100644
--- a/src/mainboard/lenovo/x60/acpi/ec.asl
+++ b/src/mainboard/lenovo/x60/acpi/ec.asl
@@ -36,7 +36,9 @@ Device(EC)
 				LEDS, 8,	/* LED state */
 		Offset (0x3B),
 				    , 1,
-				KBLT, 1,         /* Keyboard Light */
+				KBLT, 1,        /* Keyboard Light */
+		Offset (0x78),
+				TMP0, 8,	/* Thermal Zone 0 temperature */
 		Offset (0x81),
 				PAGE, 8		/* Information Page Selector */
         }
diff --git a/src/mainboard/lenovo/x60/acpi/thermal.asl b/src/mainboard/lenovo/x60/acpi/thermal.asl
index e69de29..b7256ce 100644
--- a/src/mainboard/lenovo/x60/acpi/thermal.asl
+++ b/src/mainboard/lenovo/x60/acpi/thermal.asl
@@ -0,0 +1,26 @@
+Scope(\_TZ)
+{
+	Method(C2K, 1, NotSerialized)
+	{
+		Multiply(Arg0, 10, Local0)
+		Add (Local0, 2732, Local0)
+		if (LLessEqual(Local0, 2732)) {
+		        Return (3000)
+		}
+
+		if (LGreater(Local0, 4012)) {
+		        Return (3000)
+		}
+		Return (Local0)
+	}
+
+	ThermalZone(THM0)
+	{
+		Method(_CRT, 0, NotSerialized) {
+			Return (C2K(127))
+		}
+		Method(_TMP) {
+			Return (C2K(\_SB.PCI0.LPCB.EC.TMP0))
+		}
+	}
+}
-- 
1.7.4.1




From svn at coreboot.org  Sun Mar  6 18:58:32 2011
From: svn at coreboot.org (repository service)
Date: Sun, 06 Mar 2011 18:58:32 +0100
Subject: [coreboot] [commit] r6433 - trunk/util/superiotool
Message-ID: <E1PwIDw-0007Hy-1d@ra.coresystems.de>

Author: hailfinger
Date: Sun Mar  6 18:58:31 2011
New Revision: 6433
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6433

Log:
Add support for the NSC PC87364 Super I/O.

superiotool -deV output:
http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html

Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/util/superiotool/nsc.c

Modified: trunk/util/superiotool/nsc.c
==============================================================================
--- trunk/util/superiotool/nsc.c	Fri Mar  4 21:01:15 2011	(r6432)
+++ trunk/util/superiotool/nsc.c	Sun Mar  6 18:58:31 2011	(r6433)
@@ -242,6 +242,48 @@
 			{0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,EOT}},
 		{EOT}}},
 	{0xe4, "PC87364", {
+		{NOLDN, NULL,
+			{0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x2a,
+			 0x2b,0x2c,0x2d,0x2e,EOT},
+			{0xe4,0x11,0x00,0x03,0x00,0x00,0x00,NANA,0x00,MISC,
+			 0x00,0x00,NANA,RSVD,EOT}},
+		{0x0, "Floppy",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT},
+			{0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}},
+		{0x1, "Parallel port",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,EOT}},
+		{0x2, "COM2",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}},
+		{0x3, "COM1",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}},
+		{0x4, "System wake-up control (SWC)",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}},
+		{0x5, "Mouse",
+			{0x30,0x70,0x71,0x74,0x75,EOT},
+			{0x00,0x0c,0x02,0x04,0x04,EOT}},
+		{0x6, "Keyboard",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0,
+			 EOT},
+			{0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,0x40,
+			 EOT}},
+		{0x7, "GPIO",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2,
+			 EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x00,0x00,
+			 EOT}},
+		{0x8, "ACCESS.bus (ACB)",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,EOT}},
+		{0x9, "Fan speed control and monitor (FSCM)",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x00,EOT}},
+		{0xa, "Watchdog timer",
+			{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+			{0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x02,EOT}},
 		{EOT}}},
 	{0xe5, "PC87365", {	/* SRID[7..0] == chip revision */
 		{EOT}}},



From c-d.hailfinger.devel.2006 at gmx.net  Sun Mar  6 19:01:46 2011
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 06 Mar 2011 19:01:46 +0100
Subject: [coreboot] [flashrom]  Add NSC PC87364 support to superiotool
In-Reply-To: <4D713C0D.5030701@gmx.net>
References: <1299105021.4793.56.camel@localhost>	<20110304034925.GA29179@coreboot.org>
	<4D713C0D.5030701@gmx.net>
Message-ID: <4D73CC0A.8020709@gmx.net>

Auf 04.03.2011 20:22, Carl-Daniel Hailfinger schrieb:
> Auf 04.03.2011 04:49, Stefan Reinauer schrieb:
>   
>> * Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de> [110302 23:30]:
>>   
>>     
>>> Add National Semiconductors PC87364.
>>>
>>> Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
>>>     
>>>       
>> Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
>>   
>>     
> Michael, AFAIK the flashrom and coreboot repositories have the same user
> rights, so in theory you should be able to commit.
>   

Sorry about the confusion.

Thanks for your patch!
Committed to the coreboot repo in revision 6433.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svens at stackframe.org  Sun Mar  6 19:36:50 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sun,  6 Mar 2011 18:36:50 +0000
Subject: [coreboot] [PATCH] X60: add thermal zone 1
Message-ID: <1299436610-6030-1-git-send-email-svens@stackframe.org>

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/x60/acpi/thermal.asl |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/lenovo/x60/acpi/thermal.asl b/src/mainboard/lenovo/x60/acpi/thermal.asl
index b7256ce..35b6f14 100644
--- a/src/mainboard/lenovo/x60/acpi/thermal.asl
+++ b/src/mainboard/lenovo/x60/acpi/thermal.asl
@@ -23,4 +23,19 @@ Scope(\_TZ)
 			Return (C2K(\_SB.PCI0.LPCB.EC.TMP0))
 		}
 	}
+
+	ThermalZone(THM1)
+	{
+		Method(_CRT, 0, NotSerialized) {
+			Return (C2K(99))
+		}
+
+		Method(_PSV, 0, NotSerialized) {
+			Return (C2K(94))
+		}
+
+		Method(_TMP) {
+			Return (C2K(\_SB.PCI0.LPCB.EC.TMP1))
+		}
+	}
 }
-- 
1.7.4.1




From peter at stuge.se  Sun Mar  6 20:46:54 2011
From: peter at stuge.se (Peter Stuge)
Date: Sun, 6 Mar 2011 20:46:54 +0100
Subject: [coreboot] a question about ASUS, MEW-AM
In-Reply-To: <AANLkTik=C4V_5vYXG7knWF9Hm2qinkPTzr-DhzESb-sR@mail.gmail.com>
References: <AANLkTik=C4V_5vYXG7knWF9Hm2qinkPTzr-DhzESb-sR@mail.gmail.com>
Message-ID: <20110306194654.25389.qmail@stuge.se>

ali hagigat wrote:
> Where the graphics card is initialized in the source code? Is it using
> Internal graphics card or external? I found some vga routines in pc80
> and console folders.

There is most likely no code in coreboot to initialize the graphics
on this board, and you will be forced to let SeaBIOS initialize the
VGA option ROM which you can extract from factory BIOS or a running
system, all per instructions on web page.


//Peter



From stefan.reinauer at coreboot.org  Sun Mar  6 21:29:24 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sun, 06 Mar 2011 12:29:24 -0800
Subject: [coreboot] [PATCH] X60: add thermal zone 1
In-Reply-To: <1299436610-6030-1-git-send-email-svens@stackframe.org>
References: <1299436610-6030-1-git-send-email-svens@stackframe.org>
Message-ID: <4D73EEA4.5030505@coreboot.org>

> Signed-off-by: Sven Schnelle<svens at stackframe.org>
>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>



From donnie2008 at breakthru.com  Sun Mar  6 07:23:14 2011
From: donnie2008 at breakthru.com (donnie hylton)
Date: Sat, 5 Mar 2011 22:23:14 -0800
Subject: [coreboot] email to flashrom
Message-ID: <20110306062314.9367E2778EF@ii16-16.friendfinderinc.com>

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From donnie2008 at breakthru.com  Sun Mar  6 07:09:13 2011
From: donnie2008 at breakthru.com (donnie hylton)
Date: Sat, 5 Mar 2011 22:09:13 -0800
Subject: [coreboot] hardware specs and bios info
Message-ID: <20110306060913.D60062778DB@ii16-16.friendfinderinc.com>

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From donnie2008 at breakthru.com  Sun Mar  6 15:29:16 2011
From: donnie2008 at breakthru.com (donnie hylton)
Date: Sun, 6 Mar 2011 06:29:16 -0800
Subject: [coreboot] not sure
Message-ID: <20110306142916.D952E2778DC@ii16-16.friendfinderinc.com>

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From peter at stuge.se  Sun Mar  6 23:41:49 2011
From: peter at stuge.se (Peter Stuge)
Date: Sun, 6 Mar 2011 23:41:49 +0100
Subject: [coreboot] [PATCH] X60: add thermal zone 1
In-Reply-To: <1299436610-6030-1-git-send-email-svens@stackframe.org>
References: <1299436610-6030-1-git-send-email-svens@stackframe.org>
Message-ID: <20110306224149.19394.qmail@stuge.se>

Sven Schnelle wrote:
> Signed-off-by: Sven Schnelle <svens at stackframe.org>

Acked-by: Peter Stuge <peter at stuge.se>



From mr.nuke.me at gmail.com  Mon Mar  7 07:37:20 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Mon, 07 Mar 2011 08:37:20 +0200
Subject: [coreboot] hardware specs and bios info
In-Reply-To: <20110306060913.D60062778DB@ii16-16.friendfinderinc.com>
References: <20110306060913.D60062778DB@ii16-16.friendfinderinc.com>
Message-ID: <4D747D20.90206@gmail.com>

On 03/06/2011 08:09 AM, donnie hylton wrote:
> i only have a 32 bit edition of windows installed
iigh!
> and i know nothing
> about programming
You don't need to know how too program the space shuttle to type a few
lines (hehe, even copy paste) into the terminal.
> so i am not able to use the linux tools listed. 
You are unwilling. If you want us to look at the information, you should
have the courtesy to provide us with what we ask, not make us lose our
time trying to figure out that we don't have that info. There is a good
reason we ask for _that_ information and not anything else.
Incidentally I looked over what your provided, and there is nothing of
use in it.

> so i
> have sent the hardware specs in the attachments that i created using
> some programs for windows i found. my laptop is a toshiba l35 s2151. in
> the hardware specs and the bios info the number of total memory slots
> says 4 even though there are only 2. i have taken the laptop apart more
> than once and have only seen 2 ram slots. here is a link to the
> processor.
> http://ark.intel.com/Product.aspx?id=27149&processor=420&spec-codes=SL8VZ
> in the hardware spec attachment that i sent it says that the package
> socket is 479 mPGA but on the intel webpage under Ordering / sSpecs /
> Steppings the processor is listed as Intel? Celeron? M Processor 420 (1M
> Cache, 1.60 GHz, 533 MHz FSB) uFCPGA, Tray
> and having a socket type of PPGA478. that is 3 different listings
> PPGA478,479 mPGA,uFCPGA from 2 different sources intel and speccy a
> program from piriform.
Nice. But the specs are useless

That being said, get a large cup of strong coffee, a good pack of
cigarettes (or Pringles if you don't smoke), and run the tools that we
ask you to (No, I did not say liveUSB, I have everyone on the list to
vouch for me I didn't say it).

Alex



From svn at coreboot.org  Mon Mar  7 10:00:51 2011
From: svn at coreboot.org (repository service)
Date: Mon, 07 Mar 2011 10:00:51 +0100
Subject: [coreboot] [commit] r6434 - trunk/src/mainboard/lenovo/x60/acpi
Message-ID: <E1PwWJ9-0000lE-5u@ra.coresystems.de>

Author: svens
Date: Mon Mar  7 10:00:50 2011
New Revision: 6434
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6434

Log:
X60: add thermal zone 0

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/lenovo/x60/acpi/ec.asl
   trunk/src/mainboard/lenovo/x60/acpi/thermal.asl

Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/acpi/ec.asl	Sun Mar  6 18:58:31 2011	(r6433)
+++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl	Mon Mar  7 10:00:50 2011	(r6434)
@@ -36,7 +36,9 @@
 				LEDS, 8,	/* LED state */
 		Offset (0x3B),
 				    , 1,
-				KBLT, 1,         /* Keyboard Light */
+				KBLT, 1,        /* Keyboard Light */
+		Offset (0x78),
+				TMP0, 8,	/* Thermal Zone 0 temperature */
 		Offset (0x81),
 				PAGE, 8		/* Information Page Selector */
         }

Modified: trunk/src/mainboard/lenovo/x60/acpi/thermal.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/acpi/thermal.asl	Sun Mar  6 18:58:31 2011	(r6433)
+++ trunk/src/mainboard/lenovo/x60/acpi/thermal.asl	Mon Mar  7 10:00:50 2011	(r6434)
@@ -0,0 +1,26 @@
+Scope(\_TZ)
+{
+	Method(C2K, 1, NotSerialized)
+	{
+		Multiply(Arg0, 10, Local0)
+		Add (Local0, 2732, Local0)
+		if (LLessEqual(Local0, 2732)) {
+		        Return (3000)
+		}
+
+		if (LGreater(Local0, 4012)) {
+		        Return (3000)
+		}
+		Return (Local0)
+	}
+
+	ThermalZone(THM0)
+	{
+		Method(_CRT, 0, NotSerialized) {
+			Return (C2K(127))
+		}
+		Method(_TMP) {
+			Return (C2K(\_SB.PCI0.LPCB.EC.TMP0))
+		}
+	}
+}



From svn at coreboot.org  Mon Mar  7 10:09:51 2011
From: svn at coreboot.org (repository service)
Date: Mon, 07 Mar 2011 10:09:51 +0100
Subject: [coreboot] [commit] r6435 - trunk/src/mainboard/lenovo/x60/acpi
Message-ID: <E1PwWRr-0006ba-HF@ra.coresystems.de>

Author: svens
Date: Mon Mar  7 10:09:51 2011
New Revision: 6435
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6435

Log:
X60: add thermal zone 1

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/lenovo/x60/acpi/ec.asl
   trunk/src/mainboard/lenovo/x60/acpi/thermal.asl

Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/acpi/ec.asl	Mon Mar  7 10:00:50 2011	(r6434)
+++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl	Mon Mar  7 10:09:51 2011	(r6435)
@@ -39,6 +39,7 @@
 				KBLT, 1,        /* Keyboard Light */
 		Offset (0x78),
 				TMP0, 8,	/* Thermal Zone 0 temperature */
+				TMP1, 8,	/* Thermal Zone 1 temperature */
 		Offset (0x81),
 				PAGE, 8		/* Information Page Selector */
         }

Modified: trunk/src/mainboard/lenovo/x60/acpi/thermal.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/acpi/thermal.asl	Mon Mar  7 10:00:50 2011	(r6434)
+++ trunk/src/mainboard/lenovo/x60/acpi/thermal.asl	Mon Mar  7 10:09:51 2011	(r6435)
@@ -23,4 +23,19 @@
 			Return (C2K(\_SB.PCI0.LPCB.EC.TMP0))
 		}
 	}
+
+	ThermalZone(THM1)
+	{
+		Method(_CRT, 0, NotSerialized) {
+			Return (C2K(99))
+		}
+
+		Method(_PSV, 0, NotSerialized) {
+			Return (C2K(94))
+		}
+
+		Method(_TMP) {
+			Return (C2K(\_SB.PCI0.LPCB.EC.TMP1))
+		}
+	}
 }



From mr.nuke.me at gmail.com  Mon Mar  7 11:19:28 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Mon, 07 Mar 2011 12:19:28 +0200
Subject: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard
In-Reply-To: <4D72D6BE.7000403@gmail.com>
References: <4D5C5664.8040601@gmail.com>	<4D66673D.1030004@gmail.com>	<4D6EA744.6030308@gmail.com>	<20110302213811.27526.qmail@stuge.se>	<4D6EB96D.40508@settoplinux.org>
	<4D6EBE99.6050106@gmail.com> <4D6EDDB0.3000003@settoplinux.org>
	<4D72D6BE.7000403@gmail.com>
Message-ID: <4D74B130.4050700@gmail.com>

This is my last submission of this patch. I've made the board depend on
CONFIG_EXPERT, and added a help menu describing it does not work. I
leave the mptable because I have invested significant effort into making
sure it is correct. I leave the APCI table because I have invested
effort into getting the _PRT to be correct.

There is a comment in a linux source file:
"Some [firmware] writers are clueless".
I feel like one of those firmware writers, be it because I wasn't able
to find the information I need, or I have and am not able to understand it.

I have gotten tired of spinning in circles with this board, and am thus
abandoning it. I make this last submission on a use it or lose it basis.

/me out

Alex
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From mathias.krause at secunet.com  Mon Mar  7 15:33:22 2011
From: mathias.krause at secunet.com (Mathias Krause)
Date: Mon, 07 Mar 2011 15:33:22 +0100
Subject: [coreboot] [PATCH] nvramtool: fixed working with files only on a
 non-coreboot system
Message-ID: <4D74ECB2.6050700@secunet.com>

nvramtool tried to get the CMOS layout from the coreboot option table
even when told to take a layout file. This patch fixes that case by
slightly changing the order of evaluating the specific options. Now
almost all combinations are valid (CMOS content from NVRAM/CBFS/file
with CMOS layout from CBFS/option table/layout file).

Additionally I fixed some white space issues (spaces to tabs) and throw
in some newlines to aid readability of the code.

Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
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From svn at coreboot.org  Mon Mar  7 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 07 Mar 2011 16:00:02 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1Pwbuk-0004ll-81@ra.coresystems.de>

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From seppk at arcor.de  Mon Mar  7 19:11:21 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Mon, 07 Mar 2011 19:11:21 +0100
Subject: [coreboot] option_table.h missing
Message-ID: <4D751FC9.3010002@arcor.de>

Hi,
I got the following build time failure with revision 6435:

     HOSTCC     cbfstool/cbfstool.o
     HOSTCXX    cbfstool/cbfstool (link)
     CC         lib/uart8250.romstage.o
src/lib/uart8250.c:25:26: error: option_table.h: Datei oder Verzeichnis 
nicht gefunden
src/lib/uart8250.c: In function 'uart_init':
src/lib/uart8250.c:112: error: 'CMOS_VSTART_baud_rate' undeclared (first 
use in this function)
src/lib/uart8250.c:112: error: (Each undeclared identifier is reported 
only once
src/lib/uart8250.c:112: error: for each function it appears in.)
src/lib/uart8250.c:112: error: 'CMOS_VLEN_baud_rate' undeclared (first 
use in this function)
make: *** [build/lib/uart8250.romstage.o] Fehler 1

Can anyone tell me what's wrong ?

Thanks.

Josef



From stefan.reinauer at coreboot.org  Mon Mar  7 20:18:57 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Mon, 7 Mar 2011 20:18:57 +0100
Subject: [coreboot] AGP video card reset again showing only half the
 RAM. Why?
In-Reply-To: <AANLkTi=wqgZL6+370mB=4S-kDrqp3HWrW1Ee-N0t_thd@mail.gmail.com>
References: <AANLkTi=wqgZL6+370mB=4S-kDrqp3HWrW1Ee-N0t_thd@mail.gmail.com>
Message-ID: <20110307191856.GA8786@coreboot.org>

* Keith Hui <buurin at gmail.com> [110306 02:43]:
> Tonight I observed that on my P2B-LS board, my nvidia geforce fx5200
> AGP card with 128MB ram, after the first initialization run showing
> 128MB RAM, reset again showing only 64MB RAM. Is this as simple as a
> AGP graphics aperture problem? Or is it something more?
 
You might want to assert a reset on the AGP bridge on reboot. See
romstage.c of the Kontron 986lcd-m for more information.




From marcj303 at gmail.com  Tue Mar  8 00:25:07 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 7 Mar 2011 16:25:07 -0700
Subject: [coreboot] Google Summer of Code 2011
In-Reply-To: <AANLkTinnR-_y64jtTe+0VORe+6heGE4tKObqb2v=2xYf@mail.gmail.com>
References: <AANLkTinnR-_y64jtTe+0VORe+6heGE4tKObqb2v=2xYf@mail.gmail.com>
Message-ID: <AANLkTingHGyJOFKNQdxH5pF=1iMk0gY_Cnb6X75FJCzg@mail.gmail.com>

On Mon, Feb 28, 2011 at 6:17 PM, Marc Jones <marcj303 at gmail.com> wrote:
> GSoC mentoring org signup starts this week and is due by March 11. I
> can take the lead this year, unless someone else would like to do it.
>
> If we are accepted (I expect we will be), Student applications are
> March 28 - April 8.
>
> Please add your project ideas to the wiki : http://www.coreboot.org/GSoC
>
> Who would like to be a mentor this year?


Hi All,

I am getting ready to fill out the GSoC application and I need an
backup admin in order to submit the application. If you plan on being
a mentor and don't mind being the backup admin, please send me your
GSoC link_id.

Thanks,
Marc



-- 
http://se-eng.com



From c-d.hailfinger.devel.2006 at gmx.net  Tue Mar  8 02:19:09 2011
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 08 Mar 2011 02:19:09 +0100
Subject: [coreboot] Google Summer of Code 2011
In-Reply-To: <AANLkTingHGyJOFKNQdxH5pF=1iMk0gY_Cnb6X75FJCzg@mail.gmail.com>
References: <AANLkTinnR-_y64jtTe+0VORe+6heGE4tKObqb2v=2xYf@mail.gmail.com>
	<AANLkTingHGyJOFKNQdxH5pF=1iMk0gY_Cnb6X75FJCzg@mail.gmail.com>
Message-ID: <4D75840D.7080800@gmx.net>

Hi Marc,

can we have one coordinated coreboot+flashrom application?

Auf 08.03.2011 00:25, Marc Jones schrieb:
> On Mon, Feb 28, 2011 at 6:17 PM, Marc Jones <marcj303 at gmail.com> wrote:
>   
>> GSoC mentoring org signup starts this week and is due by March 11. I
>> can take the lead this year, unless someone else would like to do it.
>>
>> Who would like to be a mentor this year?
>>     
> I am getting ready to fill out the GSoC application and I need an
> backup admin in order to submit the application. If you plan on being
> a mentor and don't mind being the backup admin, please send me your
> GSoC link_id.
>   

I could act as backup admin, but I have to clarify this with my employer
first.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From marcj303 at gmail.com  Tue Mar  8 02:34:20 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 7 Mar 2011 18:34:20 -0700
Subject: [coreboot] Google Summer of Code 2011
In-Reply-To: <4D75840D.7080800@gmx.net>
References: <AANLkTinnR-_y64jtTe+0VORe+6heGE4tKObqb2v=2xYf@mail.gmail.com>
	<AANLkTingHGyJOFKNQdxH5pF=1iMk0gY_Cnb6X75FJCzg@mail.gmail.com>
	<4D75840D.7080800@gmx.net>
Message-ID: <AANLkTik3wqx=n8WtxBEhJANd+HnC1hquM9SgafkO6WPQ@mail.gmail.com>

On Mon, Mar 7, 2011 at 6:19 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi Marc,
>
> can we have one coordinated coreboot+flashrom application?

Yes, I think that anything under the coreboot umbrella, like flashrom,
serialice, other tools and payloads should be considered for coreboot
GSoC.

>
> Auf 08.03.2011 00:25, Marc Jones schrieb:
>> On Mon, Feb 28, 2011 at 6:17 PM, Marc Jones <marcj303 at gmail.com> wrote:
>>
>>> GSoC mentoring org signup starts this week and is due by March 11. I
>>> can take the lead this year, unless someone else would like to do it.
>>>
>>> Who would like to be a mentor this year?
>>>
>> I am getting ready to fill out the GSoC application and I need an
>> backup admin in order to submit the application. If you plan on being
>> a mentor and don't mind being the backup admin, please send me your
>> GSoC link_id.
>>
>
> I could act as backup admin, but I have to clarify this with my employer
> first.

That would be great. Please let me know in the next day or so.

Marc

-- 
http://se-eng.com



From svn at coreboot.org  Tue Mar  8 08:50:43 2011
From: svn at coreboot.org (repository service)
Date: Tue, 08 Mar 2011 08:50:43 +0100
Subject: [coreboot] [commit] r6436 - in trunk/src: arch/x86 arch/x86/include
	arch/x86/init arch/x86/lib pc80
Message-ID: <E1Pwrgp-0005Ju-Ia@ra.coresystems.de>

Author: oxygene
Date: Tue Mar  8 08:50:43 2011
New Revision: 6436
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6436

Log:
Move cmos.default handling to bootblock

The cmos.default code wasn't actually used so far, due to an oversight
when forward-porting this feature from an old branch.

- Extend walkcbfs' use by factoring out the stage handling into C code.
- New sanitize_cmos() function that looks if CMOS data is invalid and
  cmos.default exists and if so overwrites CMOS with cmos.default data.
- Use sanitize_cmos() in both bootblock implementations.
- Drop the need to reboot after writing CMOS: CMOS wasn't used so far,
  so we can go on without a reboot.
- Remove the restriction that cmos.default only works on CAR boards.
- Always build in cmos.default support on boards that
  USE_OPTION_TABLE.

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/src/arch/x86/Kconfig
   trunk/src/arch/x86/Makefile.bootblock.inc
   trunk/src/arch/x86/include/bootblock_common.h
   trunk/src/arch/x86/init/bootblock_normal.c
   trunk/src/arch/x86/init/bootblock_simple.c
   trunk/src/arch/x86/lib/walkcbfs.S
   trunk/src/pc80/mc146818rtc_early.c

Modified: trunk/src/arch/x86/Kconfig
==============================================================================
--- trunk/src/arch/x86/Kconfig	Mon Mar  7 10:09:51 2011	(r6435)
+++ trunk/src/arch/x86/Kconfig	Tue Mar  8 08:50:43 2011	(r6436)
@@ -91,14 +91,8 @@
 config BOOTBLOCK_NORTHBRIDGE_INIT
 	string
 
-config USE_CMOS_RECOVERY
-	bool
-	default n if ROMCC
-	default y
-
 config HAVE_CMOS_DEFAULT
 	def_bool n
-	depends on USE_CMOS_RECOVERY
 
 config CMOS_DEFAULT_FILE
 	string

Modified: trunk/src/arch/x86/Makefile.bootblock.inc
==============================================================================
--- trunk/src/arch/x86/Makefile.bootblock.inc	Mon Mar  7 10:09:51 2011	(r6435)
+++ trunk/src/arch/x86/Makefile.bootblock.inc	Tue Mar  8 08:50:43 2011	(r6436)
@@ -57,7 +57,7 @@
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -MMD -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@
 
-$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc
+$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
 	$(CC) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \
 		$< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d

Modified: trunk/src/arch/x86/include/bootblock_common.h
==============================================================================
--- trunk/src/arch/x86/include/bootblock_common.h	Mon Mar  7 10:09:51 2011	(r6435)
+++ trunk/src/arch/x86/include/bootblock_common.h	Tue Mar  8 08:50:43 2011	(r6436)
@@ -17,17 +17,45 @@
 static void bootblock_southbridge_init(void) { }
 #endif
 
-static unsigned long findstage(char* target)
+static void *walkcbfs(char *target)
 {
-	unsigned long entry;
+	void *entry;
 	asm volatile (
 		"mov $1f, %%esp\n\t"
-		"jmp walkcbfs\n\t"
+		"jmp walkcbfs_asm\n\t"
 		"1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp");
 	return entry;
 }
 
+/* just enough to support findstage. copied because the original version doesn't easily pass through romcc */
+struct cbfs_stage {
+	unsigned long compression;
+	unsigned long entry; // this is really 64bit, but properly endianized
+};
+
+static unsigned long findstage(char* target)
+{
+	return ((struct cbfs_stage*)walkcbfs(target))->entry;
+}
+
 static void call(unsigned long addr, unsigned long bist)
 {
 	asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist));
 }
+
+#if CONFIG_USE_OPTION_TABLE
+#include <pc80/mc146818rtc.h>
+
+static void sanitize_cmos(void)
+{
+	if (cmos_error() || !cmos_chksum_valid()) {
+		unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default");
+		if (cmos_default) {
+			int i;
+			for (i = 14; i < 128; i++) {
+				cmos_write(cmos_default[i], i);
+			}
+		}
+	}
+}
+#endif

Modified: trunk/src/arch/x86/init/bootblock_normal.c
==============================================================================
--- trunk/src/arch/x86/init/bootblock_normal.c	Mon Mar  7 10:09:51 2011	(r6435)
+++ trunk/src/arch/x86/init/bootblock_normal.c	Tue Mar  8 08:50:43 2011	(r6436)
@@ -8,6 +8,10 @@
 		bootblock_southbridge_init();
 	}
 
+#if CONFIG_USE_OPTION_TABLE
+	sanitize_cmos();
+#endif
+
 	unsigned long entry;
 	if (do_normal_boot())
 		entry = findstage("normal/romstage");

Modified: trunk/src/arch/x86/init/bootblock_simple.c
==============================================================================
--- trunk/src/arch/x86/init/bootblock_simple.c	Mon Mar  7 10:09:51 2011	(r6435)
+++ trunk/src/arch/x86/init/bootblock_simple.c	Tue Mar  8 08:50:43 2011	(r6436)
@@ -6,6 +6,11 @@
 		bootblock_northbridge_init();
 		bootblock_southbridge_init();
 	}
+
+#if CONFIG_USE_OPTION_TABLE
+	sanitize_cmos();
+#endif
+
 	const char* target1 = "fallback/romstage";
 	unsigned long entry;
 	entry = findstage(target1);

Modified: trunk/src/arch/x86/lib/walkcbfs.S
==============================================================================
--- trunk/src/arch/x86/lib/walkcbfs.S	Mon Mar  7 10:09:51 2011	(r6435)
+++ trunk/src/arch/x86/lib/walkcbfs.S	Tue Mar  8 08:50:43 2011	(r6436)
@@ -15,19 +15,13 @@
 
 #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4)
 
-#define CBFS_STAGE_COMPRESSION 0
-#define CBFS_STAGE_ENTRY (CBFS_STAGE_COMPRESSION + 4)
-#define CBFS_STAGE_LOAD (CBFS_STAGE_ENTRY + 8)
-#define CBFS_STAGE_LEN (CBFS_STAGE_LOAD + 8)
-#define CBFS_STAGE_MEMLEN (CBFS_STAGE_LEN + 4)
-
 /*
   input %esi: filename
   input %esp: return address (not pointer to return address!)
   output %eax: entry point
   clobbers %ebx, %ecx, %edi
 */
-walkcbfs:
+walkcbfs_asm:
 	cld
 
 	mov CBFS_HEADER_PTR, %eax
@@ -67,8 +61,6 @@
 	mov CBFS_FILE_OFFSET(%ebx), %eax
 	bswap %eax
 	add %ebx, %eax
-	add $CBFS_STAGE_ENTRY, %eax /* eax = ((cbfs_stage* (cbfs_file* ebx)->offset)->entry) */
-	mov 0(%eax), %eax
 	jmp *%esp
 
 tryharder:

Modified: trunk/src/pc80/mc146818rtc_early.c
==============================================================================
--- trunk/src/pc80/mc146818rtc_early.c	Mon Mar  7 10:09:51 2011	(r6435)
+++ trunk/src/pc80/mc146818rtc_early.c	Tue Mar  8 08:50:43 2011	(r6436)
@@ -11,15 +11,6 @@
 #error "CONFIG_MAX_REBOOT_CNT too high"
 #endif
 
-#if CONFIG_USE_CMOS_RECOVERY
-#include <cbfs.h>
-#include <console/loglevel.h>
-
-int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
-#define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg)
-#endif
-
 static int cmos_error(void)
 {
 	unsigned char reg_d;
@@ -63,25 +54,6 @@
 	unsigned char byte;
 
 	if (cmos_error() || !cmos_chksum_valid()) {
-#if CONFIG_USE_CMOS_RECOVERY
-		char *cmos_default = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT);
-		if (cmos_default) {
-			int i;
-			printk_warning("WARNING - CMOS CORRUPTED. RESTORING DEFAULTS.\n");
-			/* First 14 bytes are reserved for
-			   RTC and ignored by nvramtool, too.
-			   Only 128 bytes: 128+ requires cmos configuration and
-			   contains only suspend-to-ram data, which isn't part
-			   of the recovery procedure. */
-			for (i = 14; i < 128; i++) {
-				cmos_write(cmos_default[i], i);
-			}
-			/* Now reboot to run with default cmos. */
-			outb(0x06, 0xcf9);
-			for (;;) asm("hlt"); /* Wait for reset! */
-		}
-#endif
-
 		/* There are no impossible values, no checksums so just
 		 * trust whatever value we have in the the cmos,
 		 * but clear the fallback bit.



From Patrick.Georgi at secunet.com  Tue Mar  8 10:50:07 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Tue, 8 Mar 2011 10:50:07 +0100
Subject: [coreboot] [PATCH]Fix option_table.h issues
Message-ID: <1299577807.2459.13.camel@linux-0a8x.site>

Hi,

attached patch makes option_table.h a dependency for all
romstage/ramstage files built from C, forcing the build system to create
option_table.h earlier in the build.

This should fix the build issues that were seen by Jonathan, Josef, and
others.

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

-- 
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
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From cinap_lenrek at gmx.de  Tue Mar  8 10:28:13 2011
From: cinap_lenrek at gmx.de (cinap_lenrek at gmx.de)
Date: Tue, 8 Mar 2011 10:28:13 +0100
Subject: [coreboot] self modifying code in intel vga bios?
Message-ID: <2126bccccf316bb3c7cb18611ac9e112@gmx.de>

Fish- has catched this on a Intel(r)915GM/910ML/915MS Graphics Controller
with realemu:

bad mem write c0c11
bad memory access
1d17b0 4a008800 00000002 00000000 0000a002 00009000 00005108 ac007bda 00007bc0 0000 0000 0000 c000 csZoPdI 61ed c6 MOV CS:[c11], $01

question to the coreboot guys:

did you ever see the bios writing in the rom area? 

i found this quote on: http://www.coreboot.org/VGA_support

"Even if your VGA BIOS uses self-modifying code you get a correct image"

i know that the rom area is usualy cached in ram but to catch mistakes
i disallow writing to the rom area...  fish will make full traces
later this day...  it could be just a screwup on my side...
just curious :)

--
cinap




From Patrick.Georgi at secunet.com  Tue Mar  8 11:01:57 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Tue, 8 Mar 2011 11:01:57 +0100
Subject: [coreboot] self modifying code in intel vga bios?
In-Reply-To: <2126bccccf316bb3c7cb18611ac9e112@gmx.de>
References: <2126bccccf316bb3c7cb18611ac9e112@gmx.de>
Message-ID: <1299578517.2459.16.camel@linux-0a8x.site>

Am Dienstag, den 08.03.2011, 10:28 +0100 schrieb cinap_lenrek at gmx.de:
> i know that the rom area is usualy cached in ram but to catch mistakes
> i disallow writing to the rom area...  fish will make full traces
> later this day...  it could be just a screwup on my side...
> just curious :)
I saw Intel VGABIOSes write to that area, and it was required for proper
operation of the device later. See r6251 of coreboot where I changed
YABEL's behaviour to account for that.


Regards,
Patrick
-- 
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
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From Patrick.Georgi at secunet.com  Tue Mar  8 11:05:57 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Tue, 8 Mar 2011 11:05:57 +0100
Subject: [coreboot] [PATCH]More flexibility for coreboot version string
Message-ID: <1299578757.2459.18.camel@linux-0a8x.site>

Hi,

attached patch improves flexibility on coreboot version strings in the
final binary. See attachment for details.
-- 
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
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From svn at coreboot.org  Tue Mar  8 13:58:16 2011
From: svn at coreboot.org (repository service)
Date: Tue, 08 Mar 2011 13:58:16 +0100
Subject: [coreboot] [commit] r6437 - trunk/util/nvramtool/cli
Message-ID: <E1PwwUS-0000U1-Gl@ra.coresystems.de>

Author: oxygene
Date: Tue Mar  8 13:58:16 2011
New Revision: 6437
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6437

Log:
nvramtool: Change precedence order for data sources

nvramtool couldn't handle certain combinations of sources for CMOS
layout and CMOS data. This change allows for nearly all combinations.

Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/util/nvramtool/cli/nvramtool.c

Modified: trunk/util/nvramtool/cli/nvramtool.c
==============================================================================
--- trunk/util/nvramtool/cli/nvramtool.c	Tue Mar  8 08:50:43 2011	(r6436)
+++ trunk/util/nvramtool/cli/nvramtool.c	Tue Mar  8 13:58:16 2011	(r6437)
@@ -102,13 +102,9 @@
 
 	parse_nvramtool_args(argc, argv);
 
-	if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_LAYOUT_FILE].found) {
-		set_layout_filename(nvramtool_op_modifiers
-				    [NVRAMTOOL_MOD_USE_CMOS_LAYOUT_FILE].param);
-		fn = get_layout_from_file;
-	} else if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_OPT_TABLE].found) {
-		fn = get_layout_from_cmos_table;
-	} else if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CBFS_FILE].found) {
+	/* If we should operate on a CBFS file default to reading the layout
+	 * and CMOS contents from it. */
+	if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CBFS_FILE].found) {
 		open_cbfs(nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CBFS_FILE].param);
 		if (!nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].found) {
 			cmos_default = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT, NULL);
@@ -117,36 +113,55 @@
 				exit(1);
 			}
 		}
+		fn = get_layout_from_cbfs_file;
 	}
+
+	/* If the user wants to use a specific layout file or explicitly use
+	 * the coreboot option table allow him to override previous settings. */
+	if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_LAYOUT_FILE].found) {
+		set_layout_filename(nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_LAYOUT_FILE].param);
+		fn = get_layout_from_file;
+	} else if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_OPT_TABLE].found) {
+		fn = get_layout_from_cmos_table;
+	}
+
+	/* Allow the user to use a file for the CMOS contents, possibly
+	 * overriding a previously opened "cmos.default" file from the CBFS. */
 	if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].found) {
-		int fd;
 		struct stat fd_stat;
-	       	if ((fd = open(nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param, O_RDWR | O_CREAT, 0666)) < 0) {
+		int fd;
+
+		if ((fd = open(nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param, O_RDWR | O_CREAT, 0666)) < 0) {
 			fprintf(stderr, "Couldn't open '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param);
 			exit(1);
 		}
+
 		if (fstat(fd, &fd_stat) == -1) {
 			fprintf(stderr, "Couldn't stat '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param);
 			exit(1);
 		}
+		
 		if (fd_stat.st_size < 128) {
 			lseek(fd, 127, SEEK_SET);
 			write(fd, "\0", 1);
 			fsync(fd);
 		}
+		
 		cmos_default = mmap(NULL, 128, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
 		if (cmos_default == MAP_FAILED) {
 			fprintf(stderr, "Couldn't map '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param);
 			exit(1);
 		}
 	}
+
+	/* Switch to memory based CMOS access. */
 	if (cmos_default) {
 		select_hal(HAL_MEMORY, cmos_default);
-		fn = get_layout_from_cbfs_file;
 	}
 
 	register_cmos_layout_get_fn(fn);
-	op_fns[nvramtool_op.op] ();
+	op_fns[nvramtool_op.op]();
+
 	return 0;
 }
 



From Patrick.Georgi at secunet.com  Tue Mar  8 14:01:21 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Tue, 8 Mar 2011 14:01:21 +0100
Subject: [coreboot] [PATCH] nvramtool: fixed working with files only on
	a non-coreboot system
In-Reply-To: <4D74ECB2.6050700@secunet.com>
References: <4D74ECB2.6050700@secunet.com>
Message-ID: <1299589281.2459.19.camel@linux-0a8x.site>

Am Montag, den 07.03.2011, 15:33 +0100 schrieb Mathias Krause:
> Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

and committed as r6437


Thanks,
Patrick
-- 
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

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From svens at stackframe.org  Tue Mar  8 16:53:48 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 08 Mar 2011 16:53:48 +0100
Subject: [coreboot] RFC: Make ec/acpi ports configurable
Message-ID: <87vczt4nhv.fsf@begreifnix.stackframe.org>

Hi List,

the Lenovo Embedded Controller contains 2 register pairs for ACPI:
the default 0x62/0x66 pair, and a 0x1600/0x1604 pair, which is intended
to be used by SMM code.

While the current code works with the 0x62/0x66 pair (which is fine
because there are no SMM users right now), we might switch to
0x1600/0x1604 for later versions where the SMM code actually uses
the EC.

So i thought about using the sconfig 'register' keyword for specifying
the Register pair. If it is not given in devicetree.cb, the default
ACPI addresses will be used.

I've attached a short patch as an example to this mail (i have not tried
if it works - it is just for discussion).

One question is if we should use global static variables for the
register addresses, or pass struct ec_acpi_config * to all functions?

And we may think about renaming the 'register' keyword to something like
'config', as this describes better what it does.

Regards,

Sven.

>From 9a3d656d19849bf842b0f2e1e3a86ee6b0d5a77a Mon Sep 17 00:00:00 2001
From: Sven Schnelle <svens at stackframe.org>
Date: Tue, 8 Mar 2011 16:43:28 +0100
Subject: [PATCH] ec/acpi: make ACPI register pair configurable
To: coreboot at coreboot.org
Cc: svens at stackframe.org,
    svens at stackframe.org

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/ec/acpi/chip.h                     |   31 +++++++++++++++++++++++++++++++
 src/ec/acpi/ec.c                       |   30 +++++++++++++++++++++++-------
 src/mainboard/lenovo/x60/devicetree.cb |    2 ++
 3 files changed, 56 insertions(+), 7 deletions(-)
 create mode 100644 src/ec/acpi/chip.h

diff --git a/src/ec/acpi/chip.h b/src/ec/acpi/chip.h
new file mode 100644
index 0000000..b0d1121
--- /dev/null
+++ b/src/ec/acpi/chip.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef EC_ACPI_CHIP_H
+#define EC_ACPI_CHIP_H
+
+extern struct chip_operations ec_acpi_ops;
+
+struct ec_acpi_config {
+	int cmd_reg;
+	int data_reg;
+};
+
+#endif
diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
index 7a01b7e..80d5056 100644
--- a/src/ec/acpi/ec.c
+++ b/src/ec/acpi/ec.c
@@ -24,13 +24,17 @@
 #include <arch/io.h>
 #include <delay.h>
 #include "ec.h"
+#include "chip.h"
+
+static int ec_cmd_reg = EC_SC;
+static int ec_data_reg = EC_DATA;
 
 int send_ec_command(u8 command)
 {
 	int timeout;
 
 	timeout = 0x7ff;
-	while ((inb(EC_SC) & EC_IBF) && --timeout) {
+	while ((inb(ec_cmd_reg) & EC_IBF) && --timeout) {
 		udelay(10);
 		if ((timeout & 0xff) == 0)
 			printk(BIOS_SPEW, ".");
@@ -41,7 +45,7 @@ int send_ec_command(u8 command)
 		// return -1;
 	}
 
-	outb(command, EC_SC);
+	outb(command, ec_cmd_reg);
 	return 0;
 }
 
@@ -50,7 +54,7 @@ int send_ec_data(u8 data)
 	int timeout;
 
 	timeout = 0x7ff;
-	while ((inb(EC_SC) & EC_IBF) && --timeout) { // wait for IBF = 0
+	while ((inb(ec_cmd_reg) & EC_IBF) && --timeout) { // wait for IBF = 0
 		udelay(10);
 		if ((timeout & 0xff) == 0)
 			printk(BIOS_SPEW, ".");
@@ -61,14 +65,14 @@ int send_ec_data(u8 data)
 		// return -1;
 	}
 
-	outb(data, EC_DATA);
+	outb(data, ec_data_reg);
 
 	return 0;
 }
 
 int send_ec_data_nowait(u8 data)
 {
-	outb(data, EC_DATA);
+	outb(data, ec_data_reg);
 
 	return 0;
 }
@@ -80,7 +84,7 @@ u8 recv_ec_data(void)
 
 	timeout = 0x7fff;
 	while (--timeout) { // Wait for OBF = 1
-		if (inb(EC_SC) & EC_OBF) {
+		if (inb(ec_cmd_reg) & EC_OBF) {
 			break;
 		}
 		udelay(10);
@@ -92,7 +96,7 @@ u8 recv_ec_data(void)
 		// return -1;
 	}
 
-	data = inb(EC_DATA);
+	data = inb(ec_data_reg);
 	printk(BIOS_DEBUG, "recv_ec_data: 0x%02x\n", data);
 
 	return data;
@@ -113,6 +117,18 @@ int ec_write(u8 addr, u8 data)
 	return send_ec_data(data);
 }
 
+static void ec_acpi_init(device_t dev)
+{
+	struct ec_acpi_config *cfg = dev->chip_info;
+
+	if (cfg->cmd_reg)
+		ec_cmd_reg = cfg->cmd_reg;
+
+	if (cfg->data_reg)
+		ec_data_reg = cfg->data_reg;
+}
+
 struct chip_operations ec_acpi_ops = {
 	CHIP_NAME("ACPI Embedded Controller")
+	.enable_dev = ec_acpi_init
 };
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 2817255..eaad967 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -87,6 +87,8 @@ chip northbridge/intel/i945
 					end
 				end
 				chip ec/acpi
+					register "cmd_reg" = "0x1604"
+					register "data_reg" = "0x1600"
 					device pnp ff.2 on # dummy
 						io 0x60 = 0x62
 						io 0x62 = 0x66
-- 
1.7.4.1




From joe at settoplinux.org  Tue Mar  8 17:08:12 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 08 Mar 2011 11:08:12 -0500
Subject: [coreboot] =?utf-8?q?self_modifying_code_in_intel_vga_bios=3F?=
In-Reply-To: <1299578517.2459.16.camel@linux-0a8x.site>
References: <2126bccccf316bb3c7cb18611ac9e112@gmx.de>
	<1299578517.2459.16.camel@linux-0a8x.site>
Message-ID: <541aaa48d4c7d970d83580b1c60ab5fa@imap.1and1.com>

O.T. - Is there i915 development going on?

On Tue, 8 Mar 2011 11:01:57 +0100, "Georgi, Patrick"
<Patrick.Georgi at secunet.com> wrote:
> Am Dienstag, den 08.03.2011, 10:28 +0100 schrieb cinap_lenrek at gmx.de:
>> i know that the rom area is usualy cached in ram but to catch mistakes
>> i disallow writing to the rom area...  fish will make full traces
>> later this day...  it could be just a screwup on my side...
>> just curious :)
> I saw Intel VGABIOSes write to that area, and it was required for proper
> operation of the device later. See r6251 of coreboot where I changed
> YABEL's behaviour to account for that.
> 
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From mathias.krause at secunet.com  Tue Mar  8 19:48:34 2011
From: mathias.krause at secunet.com (Mathias Krause)
Date: Tue, 08 Mar 2011 19:48:34 +0100
Subject: [coreboot] [PATCH] nvramtool: Fix CMOS layout initialization using
	option table
Message-ID: <4D767A02.1020902@secunet.com>

Move get_layout_from_cmos_table() to accessors/layout-bin.c so
process_layout() will do its check against the right cmos_table.

This bug was introduced with r6314.
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From jakllsch at kollasch.net  Tue Mar  8 20:44:20 2011
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Tue, 8 Mar 2011 19:44:20 +0000
Subject: [coreboot] [PATCH]Fix option_table.h issues
In-Reply-To: <1299577807.2459.13.camel@linux-0a8x.site>
References: <1299577807.2459.13.camel@linux-0a8x.site>
Message-ID: <20110308194420.GE8881@tarantulon.kollasch.net>

On Tue, Mar 08, 2011 at 10:50:07AM +0100, Georgi, Patrick wrote:
> Hi,
> 
> attached patch makes option_table.h a dependency for all
> romstage/ramstage files built from C, forcing the build system to create
> option_table.h earlier in the build.
> 
> This should fix the build issues that were seen by Jonathan, Josef, and
> others.
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>



From svn at coreboot.org  Tue Mar  8 21:49:19 2011
From: svn at coreboot.org (repository service)
Date: Tue, 08 Mar 2011 21:49:19 +0100
Subject: [coreboot] [commit] r6438 - in trunk: . src/pc80
Message-ID: <E1Px3qJ-0005l9-5E@ra.coresystems.de>

Author: oxygene
Date: Tue Mar  8 21:49:18 2011
New Revision: 6438
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6438

Log:
Add option_table.h as dependency for all C based object files if option tables are used.

This is to make sure that the file exists when it is needed. While this isn't the case for every C source file, it doesn't hurt either to create the file a bit sooner than strictly necessary.

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>

Modified:
   trunk/Makefile
   trunk/Makefile.inc
   trunk/src/pc80/Makefile.inc

Modified: trunk/Makefile
==============================================================================
--- trunk/Makefile	Tue Mar  8 13:58:16 2011	(r6437)
+++ trunk/Makefile	Tue Mar  8 21:49:18 2011	(r6438)
@@ -207,9 +207,10 @@
 # $1 obj class
 # $2 source suffix (c, S)
 # $3 additional compiler flags
+# $4 additional dependencies
 ifn$(EMPTY)def $(1)-objs_$(2)_template
 de$(EMPTY)fine $(1)-objs_$(2)_template
-$(obj)/$$(1).$(1).o: src/$$(1).$(2) $(obj)/config.h
+$(obj)/$$(1).$(1).o: src/$$(1).$(2) $(obj)/config.h $(4)
 	@printf "    CC         $$$$(subst $$$$(obj)/,,$$$$(@))\n"
 	$(CC) $(3) -MMD $$$$(CFLAGS) -c -o $$$$@ $$$$<
 en$(EMPTY)def
@@ -219,7 +220,7 @@
 filetypes-of-class=$(subst .,,$(sort $(suffix $($(1)-srcs))))
 $(foreach class,$(classes), \
 	$(foreach type,$(call filetypes-of-class,$(class)), \
-		$(eval $(call create_cc_template,$(class),$(type),$($(class)-$(type)-ccopts)))))
+		$(eval $(call create_cc_template,$(class),$(type),$($(class)-$(type)-ccopts),$($(class)-$(type)-deps)))))
 
 foreach-src=$(foreach file,$($(1)-srcs),$(eval $(call $(1)-objs_$(subst .,,$(suffix $(file)))_template,$(subst src/,,$(basename $(file))))))
 $(eval $(foreach class,$(classes),$(call foreach-src,$(class))))

Modified: trunk/Makefile.inc
==============================================================================
--- trunk/Makefile.inc	Tue Mar  8 13:58:16 2011	(r6437)
+++ trunk/Makefile.inc	Tue Mar  8 21:49:18 2011	(r6438)
@@ -54,6 +54,9 @@
 romstage-S-ccopts:=-DASSEMBLY -D__PRE_RAM__
 driver-S-ccopts:=-DASSEMBLY
 
+ramstage-c-deps:=$$(OPTION_TABLE_H)
+romstage-c-deps:=$$(OPTION_TABLE_H)
+
 #######################################################################
 # Add handler to compile ACPI's ASL
 define ramstage-objs_asl_template
@@ -174,7 +177,7 @@
 	@printf "    HOSTCC     $(subst $(objutil)/,,$(@))\n"
 	$(HOSTCC) -MMD -I$(subst $(objutil)/,util/,$(dir $<)) -I$(dir $<) $(HOSTCFLAGS) -c -o $@ $<
 
-$(obj)/%.ramstage.o: $(obj)/%.c $(obj)/config.h
+$(obj)/%.ramstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -MMD $(CFLAGS) -c -o $@ $<
 

Modified: trunk/src/pc80/Makefile.inc
==============================================================================
--- trunk/src/pc80/Makefile.inc	Tue Mar  8 13:58:16 2011	(r6437)
+++ trunk/src/pc80/Makefile.inc	Tue Mar  8 21:49:18 2011	(r6438)
@@ -7,9 +7,6 @@
 romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c
 subdirs-y += vga
 
-$(obj)/pc80/mc146818rtc.ramstage.o : $(OPTION_TABLE_H)
-$(obj)/pc80/mc146818rtc_early.romstage.o : $(OPTION_TABLE_H)
-
 cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default
 cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE)
 cmos.default-type = 0xaa



From patrick at georgi-clan.de  Tue Mar  8 21:50:15 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 08 Mar 2011 21:50:15 +0100
Subject: [coreboot] [PATCH]Fix option_table.h issues
In-Reply-To: <20110308194420.GE8881@tarantulon.kollasch.net>
References: <1299577807.2459.13.camel@linux-0a8x.site>
	<20110308194420.GE8881@tarantulon.kollasch.net>
Message-ID: <4D769687.9040304@georgi-clan.de>

Am 08.03.2011 20:44, schrieb Jonathan A. Kollasch:
>> This should fix the build issues that were seen by Jonathan, Josef, and
>> others.
>> Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
> Acked-by: Jonathan Kollasch <jakllsch at kollasch.net>
Thanks, r6438


Patrick



From svn at coreboot.org  Wed Mar  9 00:01:46 2011
From: svn at coreboot.org (repository service)
Date: Wed, 09 Mar 2011 00:01:46 +0100
Subject: [coreboot] [commit] r6439 - in trunk/src:
	mainboard/amd/bimini_fam10 mainboard/amd/mahogany_fam10
	mainboard/amd/serengeti_cheetah_fam10
	mainboard/amd/tilapia_fam10 mainboard/asus/m4a78-em
	mainboard/asus/m4a78...
Message-ID: <E1Px5uU-0007g2-Qw@ra.coresystems.de>

Author: sduplichan
Date: Wed Mar  9 00:01:46 2011
New Revision: 6439
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6439

Log:
Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF.

The patch makes these changes:

1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15
   romstage.c files where it is used (AMD family 10h projects).
2) Add a prototype to amdfam10.h.
3) Modify the swap list and test in real hardware for mahogany_fam10 and
   kino family 10h and confirm HT3 operation for the SB link.

Abuild tested.

Signed-off-by: Scott Duplichan <sc... at notabs.org>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/src/mainboard/amd/bimini_fam10/romstage.c
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
   trunk/src/mainboard/amd/tilapia_fam10/romstage.c
   trunk/src/mainboard/asus/m4a78-em/romstage.c
   trunk/src/mainboard/asus/m4a785-m/romstage.c
   trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
   trunk/src/mainboard/gigabyte/ma78gm/romstage.c
   trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
   trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
   trunk/src/mainboard/jetway/pa78vm5/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
   trunk/src/mainboard/tyan/s2912_fam10/romstage.c
   trunk/src/northbridge/amd/amdfam10/amdfam10.h
   trunk/src/northbridge/amd/amdht/ht_wrapper.c

Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/bimini_fam10/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/amd/bimini_fam10/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -237,3 +237,34 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+
+	return 0;
+}

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -232,3 +232,34 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+
+	return 0;
+}

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -337,3 +337,37 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -231,3 +231,37 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/asus/m4a78-em/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a78-em/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/asus/m4a78-em/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -232,3 +232,37 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -232,3 +232,37 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -228,3 +228,37 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -230,3 +230,37 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -222,3 +222,37 @@
 
 	post_cache_as_ram();
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -233,3 +233,34 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+
+	return 0;
+}

Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -238,3 +238,37 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -253,3 +253,37 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -246,3 +246,37 @@
 	post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
 	post_code(0x42);     // Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -295,3 +295,37 @@
  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
  post_code(0x42);  // Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -250,3 +250,37 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}

Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/amdfam10.h	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/northbridge/amd/amdfam10/amdfam10.h	Wed Mar  9 00:01:46 2011	(r6439)
@@ -1199,4 +1199,7 @@
 u8 get_sbbusn(u8 sblk);
 #endif
 
+#include "northbridge/amd/amdht/porting.h"
+BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List);
+
 #endif /* AMDFAM10_H */

Modified: trunk/src/northbridge/amd/amdht/ht_wrapper.c
==============================================================================
--- trunk/src/northbridge/amd/amdht/ht_wrapper.c	Tue Mar  8 21:49:18 2011	(r6438)
+++ trunk/src/northbridge/amd/amdht/ht_wrapper.c	Wed Mar  9 00:01:46 2011	(r6439)
@@ -97,42 +97,6 @@
 
 }
 
-
-/**
- * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
- * Description:
- *	This routine is called every time a non-coherent chain is processed.
- *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
- *	swap list. The first part of the list controls the BUID assignment and the
- *	second part of the list provides the device to device linking.  Device orientation
- *	can be detected automatically, or explicitly.  See documentation for more details.
- *
- *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- *	based on each device's unit count.
- *
- * Parameters:
- *	@param[in]  u8  node    = The node on which this chain is located
- *	@param[in]  u8  link    = The link on the host for this chain
- *	@param[out] u8** list   = supply a pointer to a list
- *	@param[out] BOOL result = true to use a manual list
- *				  false to initialize the link automatically
- */
-static BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
-{
-	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
-	/* If the BUID was adjusted in early_ht we need to do the manual override */
-	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
-		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
-		if ((node == 0) && (link == 0)) {	/* BSP SB link */
-			*List = swaplist;
-			return 1;
-		}
-	}
-
-	return 0;
-}
-
-
 /**
  * void getAmdTopolist(u8 ***p)
  *



From scott at notabs.org  Wed Mar  9 00:06:06 2011
From: scott at notabs.org (Scott Duplichan)
Date: Tue, 8 Mar 2011 17:06:06 -0600
Subject: [coreboot] 870 attempt
In-Reply-To: <20110224213405.GF8049@coreboot.org>
References: <20110224021337.GA5415@tarantulon.kollasch.net><20110224142320.GB5415@tarantulon.kollasch.net><AANLkTikQMJeqFZ7N_11rjB84dLbWNMcGuXkBfmJuHT3A@mail.gmail.com><3EE5664A5AE8429B8BF30C9AEA8F989C@m3a78>
	<20110224213405.GF8049@coreboot.org>
Message-ID: <5BD345685AA14EA18171660A2BB5A46D@m3a78>

]> Also remember that the family 10h swap list problem still exists.
]> There are some old patches and discussion that might be useful.
]> Here is an example:
]> 
]> http://www.mail-archive.com/coreboot at coreboot.org/msg27356.html
]
] Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Thanks Stefen, rev 6439.
Thanks,
Scott




From mathias.krause at secunet.com  Wed Mar  9 11:45:48 2011
From: mathias.krause at secunet.com (Mathias Krause)
Date: Wed, 09 Mar 2011 11:45:48 +0100
Subject: [coreboot] [PATCH] nvramtool: Fix CMOS layout initialization
 using	option table
In-Reply-To: <4D767A02.1020902@secunet.com>
References: <4D767A02.1020902@secunet.com>
Message-ID: <4D775A5C.8050006@secunet.com>

On 08.03.2011 19:48, Mathias Krause wrote:
> Move get_layout_from_cmos_table() to accessors/layout-bin.c so
> process_layout() will do its check against the right cmos_table.
> 
> This bug was introduced with r6314.
> 

Forgot the most important part! Of course:

Signed-off-by: Mathias Krause <mathias.krause at secunet.com>



From seppk at arcor.de  Wed Mar  9 14:34:51 2011
From: seppk at arcor.de (Josef Kellermann)
Date: Wed, 09 Mar 2011 14:34:51 +0100
Subject: [coreboot] correct 'power_on_after_fail' setting
Message-ID: <4D7781FB.6030200@arcor.de>

Hi,
bit 0 of pm reg#74 have to be set turn on system after power resumes.
See '42661_sb600_rrg_nda_3.02.pdf' for detail.

Signed-off-by: Josef Kellermann <seppk at arcor.de> <mailto://seppk at arcor.de>
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From mr.nuke.me at gmail.com  Wed Mar  9 21:03:49 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 09 Mar 2011 22:03:49 +0200
Subject: [coreboot] [The 604 CAR crusades][Master Yoda style] Preludium
Message-ID: <4D77DD25.20604@gmail.com>

Hi everyone,

The Tyan S2735 a Socket 604 (Intel) board it is which CAR it uses I
found. "Why care I should?" yourself you ask. Because eight boards which
socket 604 use, ROMCC they are.

dell/s1850
intel/jarrell
intel/xe7501devkit
supermicro/x6dai_g
supermicro/x6dhe_g
supermicro/x6dhe_g2
supermicro/x6dhr_ig
supermicro/x6dhr_ig2

This a bug to be considered is. Any 604 board as CAR work it should this
means. Move them all to CAR we should.

Alex




From mr.nuke.me at gmail.com  Wed Mar  9 21:44:49 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 09 Mar 2011 22:44:49 +0200
Subject: [coreboot] [PATCH] [1/4] [The 604 CAR crusades] Episode I - The
	Superio Menace
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D77E6C1.8080004@gmail.com>

See patch.
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From mr.nuke.me at gmail.com  Wed Mar  9 21:59:50 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 09 Mar 2011 22:59:50 +0200
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D77EA46.7010000@gmail.com>

While the previous two patches were innocently trivial and abuild
tested, this one _will_ break the build for several Socket 604 boards.
We want the build to be broken until we can port those to CAR.

See patch for verbosity.
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From mr.nuke.me at gmail.com  Wed Mar  9 21:55:42 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 09 Mar 2011 22:55:42 +0200
Subject: [coreboot] [PATCH][2/4][The 604 CAR crusades] Episode II - The
	Northbridge Wars
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D77E94E.3000002@gmail.com>

See patch.
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From stefan.reinauer at coreboot.org  Wed Mar  9 22:19:40 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 9 Mar 2011 22:19:40 +0100
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <4D77EA46.7010000@gmail.com>
References: <4D77DD25.20604@gmail.com>
 <4D77EA46.7010000@gmail.com>
Message-ID: <20110309211940.GA6991@coreboot.org>

* Alex G. <mr.nuke.me at gmail.com> [110309 21:59]:
> While the previous two patches were innocently trivial and abuild
> tested, this one _will_ break the build for several Socket 604 boards.
> We want the build to be broken until we can port those to CAR.

Please provide a patch that does that. Actually we don't want the build
to be broken. ;-)

> See patch for verbosity.

> The Tyan s2735 is a Socket 604 board that uses CAR.

Did you verify that all CPUs that can be plugged into a Socket 604 can
actually do CAR?





From mr.nuke.me at gmail.com  Wed Mar  9 22:19:23 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 09 Mar 2011 23:19:23 +0200
Subject: [coreboot] [PATCH] [4/4] [The 604 CAR crusades] Episode IV - A new
	board
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D77EEDB.9020005@gmail.com>

See patch.
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From mr.nuke.me at gmail.com  Wed Mar  9 22:23:36 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Wed, 09 Mar 2011 23:23:36 +0200
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <20110309211940.GA6991@coreboot.org>
References: <4D77DD25.20604@gmail.com> <4D77EA46.7010000@gmail.com>
	<20110309211940.GA6991@coreboot.org>
Message-ID: <4D77EFD8.7060008@gmail.com>

On 03/09/2011 11:19 PM, Stefan Reinauer wrote:
> * Alex G. <mr.nuke.me at gmail.com> [110309 21:59]:
>> While the previous two patches were innocently trivial and abuild
>> tested, this one _will_ break the build for several Socket 604 boards.
>> We want the build to be broken until we can port those to CAR.
> 
> Please provide a patch that does that. Actually we don't want the build
> to be broken. ;-)
> 
See Episode IV.
I can only do so much at once. There are nine boards in this situation.
I can't do all of them at once, so please be patient. More patches will
be coming in the following days/week/two weeks (depending on how busy I am).

>> The Tyan s2735 is a Socket 604 board that uses CAR.
> 
> Did you verify that all CPUs that can be plugged into a Socket 604 can
> actually do CAR?
> 
Pentium, P2, and P3 can all do CAR. The 604 Xeons, which are based on P4
can most definitely do CAR.

Alex




From mr.nuke.me at gmail.com  Wed Mar  9 23:05:49 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 10 Mar 2011 00:05:49 +0200
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <4D77EFD8.7060008@gmail.com>
References: <4D77DD25.20604@gmail.com> <4D77EA46.7010000@gmail.com>
	<20110309211940.GA6991@coreboot.org> <4D77EFD8.7060008@gmail.com>
Message-ID: <4D77F9BD.4030403@gmail.com>

On 03/09/2011 11:23 PM, Alex G. wrote:
> On 03/09/2011 11:19 PM, Stefan Reinauer wrote:
>>
>> Did you verify that all CPUs that can be plugged into a Socket 604 can
>> actually do CAR?
>>
> Pentium, P2, and P3 can all do CAR. The 604 Xeons, which are based on P4
> can most definitely do CAR.
>
To that 603 Xeons as well add.

Master Yoda



From mr.nuke.me at gmail.com  Wed Mar  9 23:48:39 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 10 Mar 2011 00:48:39 +0200
Subject: [coreboot] [PATCH] [The 604 CAR crusades] Episode V - Mr. Nuke
	strikes back
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D7803C7.3070901@gmail.com>

See patch
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From mr.nuke.me at gmail.com  Thu Mar 10 00:28:25 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 10 Mar 2011 01:28:25 +0200
Subject: [coreboot] [PATCH] [The 604 CAR crusades] Episode VI - Return of
	the Patcher
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D780D19.4010306@gmail.com>

I hope you don't mind my submitting two patches in one email. I'm
running out of titles to inspire myself from.

Alex
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From mr.nuke.me at gmail.com  Thu Mar 10 01:26:10 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 10 Mar 2011 02:26:10 +0200
Subject: [coreboot] [PATCH] [The 604 CAR crusades] Cyborg Bear
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D781AA2.6070703@gmail.com>

Two more boards, right here, right now.
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From joe at settoplinux.org  Thu Mar 10 01:30:20 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 09 Mar 2011 19:30:20 -0500
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <20110309211940.GA6991@coreboot.org>
References: <4D77DD25.20604@gmail.com> <4D77EA46.7010000@gmail.com>
	<20110309211940.GA6991@coreboot.org>
Message-ID: <4D781B9C.8020405@settoplinux.org>

On 03/09/2011 04:19 PM, Stefan Reinauer wrote:
> * Alex G.<mr.nuke.me at gmail.com>  [110309 21:59]:
>> While the previous two patches were innocently trivial and abuild
>> tested, this one _will_ break the build for several Socket 604 boards.
>> We want the build to be broken until we can port those to CAR.
>
> Please provide a patch that does that. Actually we don't want the build
> to be broken. ;-)
>
>> See patch for verbosity.
>
>> The Tyan s2735 is a Socket 604 board that uses CAR.
>
> Did you verify that all CPUs that can be plugged into a Socket 604 can
> actually do CAR?
>
>
>
Yes I am a little confused. Alex did you actually test CAR on a Socket 
604 board? Or is this all just abuilded?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From mr.nuke.me at gmail.com  Thu Mar 10 01:42:35 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 10 Mar 2011 02:42:35 +0200
Subject: [coreboot] [PATCH] [The 604 CAR crusades] Lord of the drinks - The
	two patches
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D781E7B.5080206@gmail.com>

Two patches yet again.
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From mr.nuke.me at gmail.com  Thu Mar 10 01:59:43 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 10 Mar 2011 02:59:43 +0200
Subject: [coreboot] [PATCH] [The 604 CAR crusades] Lord of the Drinks - The
 Fellowship of the Jarrell
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D78227F.7080906@gmail.com>

Only one this time.
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From mr.nuke.me at gmail.com  Thu Mar 10 02:04:44 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 10 Mar 2011 03:04:44 +0200
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <4D781B9C.8020405@settoplinux.org>
References: <4D77DD25.20604@gmail.com> <4D77EA46.7010000@gmail.com>
	<20110309211940.GA6991@coreboot.org>
	<4D781B9C.8020405@settoplinux.org>
Message-ID: <4D7823AC.4050309@gmail.com>

On 03/10/2011 02:30 AM, Joseph Smith wrote:
> Yes I am a little confused. Alex did you actually test CAR on a Socket
> 604 board? Or is this all just abuilded?
> 
I researched the matter, found that those CPUs support it, and I even
found that a board already implemented CAR for 604 CPUs. Please the
Preludium read if the chance yet got you not you have. No I do not have
a 604 board, and did not test this on a 604 board.

Alex



From mr.nuke.me at gmail.com  Thu Mar 10 02:30:17 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 10 Mar 2011 03:30:17 +0200
Subject: [coreboot] [PATCH] [The 604 CAR crusades] Lord of the Drinks -
 Return of the Dell
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D7829A9.50401@gmail.com>

Last two, I promise.
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From joe at settoplinux.org  Thu Mar 10 02:43:08 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 09 Mar 2011 20:43:08 -0500
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <4D7823AC.4050309@gmail.com>
References: <4D77DD25.20604@gmail.com>
	<4D77EA46.7010000@gmail.com>	<20110309211940.GA6991@coreboot.org>	<4D781B9C.8020405@settoplinux.org>
	<4D7823AC.4050309@gmail.com>
Message-ID: <4D782CAC.80101@settoplinux.org>

On 03/09/2011 08:04 PM, Alex G. wrote:
> On 03/10/2011 02:30 AM, Joseph Smith wrote:
>> Yes I am a little confused. Alex did you actually test CAR on a Socket
>> 604 board? Or is this all just abuilded?
>>
> I researched the matter, found that those CPUs support it, and I even
> found that a board already implemented CAR for 604 CPUs. Please the
> Preludium read if the chance yet got you not you have. No I do not have
> a 604 board, and did not test this on a 604 board.
>
Sorry to say Alex, unless someone can with the hardware (at least one 
board can confirm) I will have to sit this one out. I know from 
developing CAR for both i830 and i810 that things can got wrong very 
easily, and if they do you will not even get serial output....
Sorry.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From mr.nuke.me at gmail.com  Thu Mar 10 02:45:16 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Thu, 10 Mar 2011 03:45:16 +0200
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <4D782CAC.80101@settoplinux.org>
References: <4D77DD25.20604@gmail.com>
	<4D77EA46.7010000@gmail.com>	<20110309211940.GA6991@coreboot.org>	<4D781B9C.8020405@settoplinux.org>
	<4D7823AC.4050309@gmail.com> <4D782CAC.80101@settoplinux.org>
Message-ID: <4D782D2C.6090800@gmail.com>

On 03/10/2011 03:43 AM, Joseph Smith wrote:
> Sorry to say Alex, unless someone can with the hardware (at least one
> board can confirm) I will have to sit this one out. I know from
> developing CAR for both i830 and i810 that things can got wrong very
> easily, and if they do you will not even get serial output....
> Sorry.
> 
Sorry to say that someone with the Tyan board I mentioned has already
tested, otherwise it would not have been committed as CAR in the tree,
and I would not have wasted this monumental amount of time converting
the rest.

Tyan S2735 is the board you're looking for. If this is not enough for
you, then please shoot me. :)

Alex



From anup.kadam at gmail.com  Thu Mar 10 06:42:29 2011
From: anup.kadam at gmail.com (Anup Rao)
Date: Thu, 10 Mar 2011 11:12:29 +0530
Subject: [coreboot] Support fot UMC UM8670 Super IO
Message-ID: <AANLkTimo7MpVSdL34_bhUcGdPX9egC08pruyKstxrXK5@mail.gmail.com>

Hi Everyone,

I want to install Coreboot on an old Cyrix 6x86 machine. It comes
equipped with a M558 motherboard.
The AMI BIOS string ID is  51-0830-001437-00111111-071595-UT801X-001_10_UTRON-F
Further details can be found on this webpage:
http://motherboards.mbarron.net/models/pcchips/m558.htm

The Super IO chip on it is a UMC UM8670. The Superiotool currently
does not detect/dump this chip (exactly as mentioned on the supported
HW page).
Also, It is currently not listed on the supported chipsets page for
Coreboot. I am unable to find any further information on the web for
this chip.
I am hoping that this chip is in someway a clone or identical to other
SuperIO chips.

Can anyone confirm if it is supported by Coreboot? If not can anyone
point me to a location where information on this chip could be
available ?

Regards,
Anup



From peter at stuge.se  Thu Mar 10 07:38:40 2011
From: peter at stuge.se (Peter Stuge)
Date: Thu, 10 Mar 2011 07:38:40 +0100
Subject: [coreboot] [PATCH] nvramtool: Fix CMOS layout
	initialization	using option table
In-Reply-To: <4D775A5C.8050006@secunet.com>
References: <4D767A02.1020902@secunet.com> <4D775A5C.8050006@secunet.com>
Message-ID: <20110310063840.15162.qmail@stuge.se>

Mathias Krause wrote:
> On 08.03.2011 19:48, Mathias Krause wrote:
> > Move get_layout_from_cmos_table() to accessors/layout-bin.c so
> > process_layout() will do its check against the right cmos_table.
> > 
> > This bug was introduced with r6314.
> > 
> 
> Forgot the most important part! Of course:
> 
> Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Thu Mar 10 08:52:02 2011
From: svn at coreboot.org (repository service)
Date: Thu, 10 Mar 2011 08:52:02 +0100
Subject: [coreboot] [commit] r6440 - in trunk/util/nvramtool: . accessors
Message-ID: <E1PxafC-00059H-Ru@ra.coresystems.de>

Author: oxygene
Date: Thu Mar 10 08:52:02 2011
New Revision: 6440
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6440

Log:
nvramtool: Move code so it has access to the right data structures

Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/util/nvramtool/accessors/layout-bin.c
   trunk/util/nvramtool/lbtable.c
   trunk/util/nvramtool/lbtable.h

Modified: trunk/util/nvramtool/accessors/layout-bin.c
==============================================================================
--- trunk/util/nvramtool/accessors/layout-bin.c	Wed Mar  9 00:01:46 2011	(r6439)
+++ trunk/util/nvramtool/accessors/layout-bin.c	Thu Mar 10 08:52:02 2011	(r6440)
@@ -84,6 +84,20 @@
 }
 
 /****************************************************************************
+ * get_layout_from_cmos_table
+ *
+ * Find the CMOS table which is stored within the coreboot table and set the
+ * global variable cmos_table to point to it.
+ ****************************************************************************/
+void get_layout_from_cmos_table(void)
+{
+	get_lbtable();
+	cmos_table = (const struct cmos_option_table *)
+	    find_lbrec(LB_TAG_CMOS_OPTION_TABLE);
+	process_layout();
+}
+
+/****************************************************************************
  * process_cmos_table
  *
  * Extract layout information from the CMOS option table and store it in our

Modified: trunk/util/nvramtool/lbtable.c
==============================================================================
--- trunk/util/nvramtool/lbtable.c	Wed Mar  9 00:01:46 2011	(r6439)
+++ trunk/util/nvramtool/lbtable.c	Thu Mar 10 08:52:02 2011	(r6440)
@@ -63,7 +63,6 @@
 					    unsigned long end,
 					    int *bad_header_count,
 					    int *bad_table_count);
-static const struct lb_record *find_lbrec(uint32_t tag);
 static const char *lbrec_tag_to_str(uint32_t tag);
 static void memory_print_fn(const struct lb_record *rec);
 static void mainboard_print_fn(const struct lb_record *rec);
@@ -215,11 +214,6 @@
 /* Pointer to coreboot table. */
 static const struct lb_header *lbtable = NULL;
 
-/* The CMOS option table is located within the coreboot table.  It tells us
- * where the CMOS parameters are located in the nonvolatile RAM.
- */
-static const struct cmos_option_table *cmos_table = NULL;
-
 static const hexdump_format_t format =
     { 12, 4, "            ", " | ", " ", " | ", '.' };
 
@@ -303,21 +297,6 @@
 }
 
 /****************************************************************************
- * get_layout_from_cmos_table
- *
- * Find the CMOS table which is stored within the coreboot table and set the
- * global variable cmos_table to point to it.
- ****************************************************************************/
-void get_layout_from_cmos_table(void)
-{
-
-	get_lbtable();
-	cmos_table = (const struct cmos_option_table *)
-	    find_lbrec(LB_TAG_CMOS_OPTION_TABLE);
-	process_layout();
-}
-
-/****************************************************************************
  * dump_lbtable
  *
  * Do a low-level dump of the coreboot table.
@@ -538,7 +517,7 @@
  * Find the record in the coreboot table that matches 'tag'.  Return pointer
  * to record on success or NULL if record not found.
  ****************************************************************************/
-static const struct lb_record *find_lbrec(uint32_t tag)
+const struct lb_record *find_lbrec(uint32_t tag)
 {
 	const char *p;
 	uint32_t bytes_processed;

Modified: trunk/util/nvramtool/lbtable.h
==============================================================================
--- trunk/util/nvramtool/lbtable.h	Wed Mar  9 00:01:46 2011	(r6439)
+++ trunk/util/nvramtool/lbtable.h	Thu Mar 10 08:52:02 2011	(r6440)
@@ -39,6 +39,7 @@
 void dump_lbtable(void);
 void list_lbtable_choices(void);
 void list_lbtable_item(const char item[]);
+const struct lb_record *find_lbrec(uint32_t tag);
 
 void process_layout(void);
 #endif				/* LBTABLE_H */



From joe at settoplinux.org  Thu Mar 10 09:38:41 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 10 Mar 2011 03:38:41 -0500
Subject: [coreboot] Support fot UMC UM8670 Super IO
In-Reply-To: <AANLkTimo7MpVSdL34_bhUcGdPX9egC08pruyKstxrXK5@mail.gmail.com>
References: <AANLkTimo7MpVSdL34_bhUcGdPX9egC08pruyKstxrXK5@mail.gmail.com>
Message-ID: <ec77a43b86200ecc574bd1541aa6c599@imap.1and1.com>



On Thu, 10 Mar 2011 11:12:29 +0530, Anup Rao <anup.kadam at gmail.com> wrote:
> Hi Everyone,
> 
> I want to install Coreboot on an old Cyrix 6x86 machine. It comes
> equipped with a M558 motherboard.
> The AMI BIOS string ID is 
> 51-0830-001437-00111111-071595-UT801X-001_10_UTRON-F
> Further details can be found on this webpage:
> http://motherboards.mbarron.net/models/pcchips/m558.htm
> 
> The Super IO chip on it is a UMC UM8670. The Superiotool currently
> does not detect/dump this chip (exactly as mentioned on the supported
> HW page).
> Also, It is currently not listed on the supported chipsets page for
> Coreboot. I am unable to find any further information on the web for
> this chip.
> I am hoping that this chip is in someway a clone or identical to other
> SuperIO chips.
> 
> Can anyone confirm if it is supported by Coreboot? If not can anyone
> point me to a location where information on this chip could be
> available ?
> 
Good luck to you, no part of that board is currently supported by coreboot
it is simply way too old. Also good luck trying to find any datasheets for
something that old.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From anish.mailing.list at gmail.com  Thu Mar 10 18:58:42 2011
From: anish.mailing.list at gmail.com (Anish Patel)
Date: Thu, 10 Mar 2011 12:58:42 -0500
Subject: [coreboot] Coreboot for AMD Fusion family 14h: ASRock E350M1
In-Reply-To: <EEE8936604F64C53BBF4825727C6C554@m3a78>
References: <20110224073140.8943.qmail@stuge.se><2CC455A98CF84BB5AD9067CC4205143C@m3a78>	<20110224173841.30173.qmail@stuge.se>
	<EEE8936604F64C53BBF4825727C6C554@m3a78>
Message-ID: <4D791152.5010405@gmail.com>

On 02/24/11 13:48, Scott Duplichan wrote:
> Peter wrote:
>
> ]Scott Duplichan wrote:
> ]>  ]>  A video option rom needs to be added to support the built-in uma
> ]>  ]>  graphics.
> ]>  ]
> ]>  ]Does the default filename match what was extracted from factory EFI?
> ]>
> ]>  I do not know of a way to recover the original filename of the
> ]>  extracted video BIOS. After booting the factory BIOS, I saved
> ]>  physical memory range C0000-CFFFF to a file with a made up name.
>
> ]Ahh! And that worked? It doesn't always. The original filename would
> ]be discovered by using bios_extract or another similar tool on the
> ]factory firmware image. That also doesn't work always, but it's worth
> ]a try.
>
> I tried AMIBCP.exe. That is the only tool I have for AMI Aptio UEFI BIOS.
> It displays lots of strings, but no filenames. Wonderful UEFI uses GUIDs
> internally for option rom tracking.
>
>
this EFI bios is using the CSM module so it can use the traditional vBIOS.
are there any plans to support this new GOP model they (the EFI guys) 
are trying to push?
> ]>  >  +++ src/mainboard/asrock/e350m1/dsdt.asl	(working copy)
> ]>  >  @@ -23,7 +23,7 @@
> ]>  >   	"DSDT",                 /* Signature */
> ]>  >   	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
> ]>  >   	"AMD   ",               /* OEMID */
> ]>  >  -	"PERSIMMO",	     /* TABLE ID */
> ]>  >  +	"E350M1  ",	     /* TABLE ID */
> ]>
> ]>  ]Also change AMD?
> ]>  Thanks for pointing this out, I changed it.
> ]>  In the revised patch, I also changed it in mptable.c
> ]
> ]Nice catch!
>
>
> ]>  +++ src/mainboard/asrock/e350m1/mainboard.c	(working copy)
> ]..
> ]>  @@ -110,6 +110,6 @@
> ]>   	return 0;
> ]>   }
> ]>   struct chip_operations mainboard_ops = {
> ]>  -	CHIP_NAME("AMD PERSIMMON Mainboard")
> ]>  -	.enable_dev = persimmon_enable,
> ]>  +    CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
> ]>  +	.enable_dev = e350m1_enable,
> ]
> ]Some whitespace on the CHIP_NAME line seems off. After that and if
> ]you find something out about the VGA BIOS filename it's
>
> Oops, got it.
>
> Acked-by: Peter Stuge<peter at stuge.se>
>
>
>




From scott at notabs.org  Thu Mar 10 19:36:39 2011
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 10 Mar 2011 12:36:39 -0600
Subject: [coreboot] Coreboot for AMD Fusion family 14h: ASRock E350M1
In-Reply-To: <4D791152.5010405@gmail.com>
References: <20110224073140.8943.qmail@stuge.se><2CC455A98CF84BB5AD9067CC4205143C@m3a78>	<20110224173841.30173.qmail@stuge.se>
	<EEE8936604F64C53BBF4825727C6C554@m3a78>
	<4D791152.5010405@gmail.com>
Message-ID: <791C3B2490B643D6BDE823471907517E@m3a78>

Anish Patel wrote:

]this EFI bios is using the CSM module so it can use the traditional vBIOS.
]are there any plans to support this new GOP model they (the EFI guys) 
]are trying to push?

I like the idea of replacing a 16-bit binary module with 32-bit
source code. But I think the use of EFI GOP is still quite limited.
All of the UEFI BIOS I have seen from AMI, Insyde, and Phoenix still
use CSM to execute the old legacy 16-bit video option rom. The only
EFI BIOS I know of that executes video code natively is Apple. Native
video code execution probably contributes to Apple's fast boot time.
The problem for us is getting the needed source code from the video
manufacturer.

Thanks,
Scott






From nrubinstein at proformatique.com  Thu Mar 10 20:03:24 2011
From: nrubinstein at proformatique.com (=?utf-8?Q?No=C3=A9_Rubinstein?=)
Date: Thu, 10 Mar 2011 20:03:24 +0100 (CET)
Subject: [coreboot] Trying to port Intel Truxton to CAR
In-Reply-To: <459498655.65530.1299783522884.JavaMail.root@Paperboy>
Message-ID: <252648561.65536.1299783804432.JavaMail.root@Paperboy>

NOT TO MERGE 
Signed-off-by: No? Rubinstein <nrubinstein at proformatique.com>

I'm trying to port Intel Truxton to CAR. So far, serial output works and Coreboot fails during SPD dump. If I remove the SPD dump, serial output doesn't work anymore (??).

I have been told on the chan to post my current progress here. The patch is not meant to be used as-is, and contains a lot of unrelated code, as I was explicitly requested to leave things as they are.

-- 
No? Rubinstein 
Proformatique (groupe Avencall) - XiVO IPBX OpenHardware 
10 bis, rue Lucien VOILIN - 92800 Puteaux 
T?l. : +33 (0)1 41 38 99 60 ext 123 
Fax. : +33 (0)1 41 38 99 70 

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From messageforpeter at gmail.com  Thu Mar 10 20:16:18 2011
From: messageforpeter at gmail.com (Peter James)
Date: Thu, 10 Mar 2011 14:16:18 -0500
Subject: [coreboot] Intel 855GM status?
Message-ID: <AANLkTik58TYr5dqYdGi-19ir9sYWxWy7QeWmXWhMtO5p@mail.gmail.com>

Just wondering if any further progress has been made to the intel 82855
chipset which as far as I can tell is in a WIP status.  Has anyone been able
to get this working successfully?  I see someone is working on a similar
chipset 854gme.  I own an Acer tm 291lci which has this chipset and would be
willing to test..

Many thanks in advance,


Peter
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From vidwer at gmail.com  Thu Mar 10 21:37:41 2011
From: vidwer at gmail.com (Idwer Vollering)
Date: Thu, 10 Mar 2011 21:37:41 +0100
Subject: [coreboot] Intel 855GM status?
In-Reply-To: <AANLkTik58TYr5dqYdGi-19ir9sYWxWy7QeWmXWhMtO5p@mail.gmail.com>
References: <AANLkTik58TYr5dqYdGi-19ir9sYWxWy7QeWmXWhMtO5p@mail.gmail.com>
Message-ID: <AANLkTingRrAbyKUfmhWbea2FP4GN9NzNqEoQPd_gGPkb@mail.gmail.com>

2011/3/10 Peter James <messageforpeter at gmail.com>

> Just wondering if any further progress has been made to the intel 82855
> chipset which as far as I can tell is in a WIP status.  Has anyone been able
> to get this working successfully?
>

Apparently not/not really. What board images have you tried to boot:
digitallogic/adl855pc, lanner/em8510 ?
Also, this quote applies: "Your board is not in the list?  (
http://www.coreboot.org/Supported_Motherboards) It will not be unless you do
the port."

  I see someone is working on a similar chipset 854gme.  I own an Acer tm
> 291lci which has this chipset and would be willing to test..
>
> Many thanks in advance,
>
>
> Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From anish.mailing.list at gmail.com  Thu Mar 10 23:08:48 2011
From: anish.mailing.list at gmail.com (Anish Patel)
Date: Thu, 10 Mar 2011 17:08:48 -0500
Subject: [coreboot] Coreboot for AMD Fusion family 14h: ASRock E350M1
In-Reply-To: <791C3B2490B643D6BDE823471907517E@m3a78>
References: <20110224073140.8943.qmail@stuge.se><2CC455A98CF84BB5AD9067CC4205143C@m3a78>	<20110224173841.30173.qmail@stuge.se>
	<EEE8936604F64C53BBF4825727C6C554@m3a78>
	<4D791152.5010405@gmail.com>
	<791C3B2490B643D6BDE823471907517E@m3a78>
Message-ID: <4D794BF0.4070502@gmail.com>

On 03/10/11 13:36, Scott Duplichan wrote:
> Anish Patel wrote:
>
> ]this EFI bios is using the CSM module so it can use the traditional vBIOS.
> ]are there any plans to support this new GOP model they (the EFI guys)
> ]are trying to push?
>
> I like the idea of replacing a 16-bit binary module with 32-bit
> source code. But I think the use of EFI GOP is still quite limited.
> All of the UEFI BIOS I have seen from AMI, Insyde, and Phoenix still
> use CSM to execute the old legacy 16-bit video option rom. The only
> EFI BIOS I know of that executes video code natively is Apple. Native
> video code execution probably contributes to Apple's fast boot time.
> The problem for us is getting the needed source code from the video
> manufacturer.
>
> Thanks,
> Scott
>
>
>
>
Well Intel lets you get to their GOP module with IMGD/EMGD for certain 
products.  They also have this EPOG thingy for their BLDK thing they 
just built.
which apparently is also going to be released for their other procs too.




From zxy__1127 at 163.com  Fri Mar 11 01:55:14 2011
From: zxy__1127 at 163.com (zxy__1127)
Date: Fri, 11 Mar 2011 08:55:14 +0800
Subject: [coreboot] Trying to port Intel Truxton to CAR
References: <252648561.65536.1299783804432.JavaMail.root@Paperboy>
Message-ID: <201103110855140629379@163.com >

hi

check smbus DEVID. 

Thanks!
2011-03-11 



zxy__1127 



???? No?_Rubinstein 
????? 2011-03-11  03:03:50 
???? coreboot at coreboot.org 
??? 
??? [coreboot] Trying to port Intel Truxton to CAR 
 
NOT TO MERGE 
Signed-off-by: No? Rubinstein  <nrubinstein at proformatique.com >

I'm trying to port Intel Truxton to CAR. So far, serial output works and Coreboot fails during SPD dump. If I remove the SPD dump, serial output doesn't work anymore (??).

I have been told on the chan to post my current progress here. The patch is not meant to be used as-is, and contains a lot of unrelated code, as I was explicitly requested to leave things as they are.

-- 
No? Rubinstein 
Proformatique (groupe Avencall) - XiVO IPBX OpenHardware 
10 bis, rue Lucien VOILIN - 92800 Puteaux 
T?l. : +33 (0)1 41 38 99 60 ext 123 
Fax. : +33 (0)1 41 38 99 70 
-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
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From joe at settoplinux.org  Fri Mar 11 01:58:31 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 10 Mar 2011 19:58:31 -0500
Subject: [coreboot] Trying to port Intel Truxton to CAR
In-Reply-To: <201103110855140629379@163.com >
References: <252648561.65536.1299783804432.JavaMail.root@Paperboy>
	<201103110855140629379@163.com >
Message-ID: <4D7973B7.6020206@settoplinux.org>

On 03/10/2011 07:55 PM, zxy__1127 wrote:
> hi
> check smbus DEVID.

Would be early smbus at that point.

> Thanks!
> 2011-03-11
> ------------------------------------------------------------------------
> zxy__1127
> ------------------------------------------------------------------------
> *????* No?_Rubinstein
> *?????* 2011-03-11 03:03:50
> *????* coreboot at coreboot.org
> *???*
> *???* [coreboot] Trying to port Intel Truxton to CAR
> NOT TO MERGE
> Signed-off-by: No? Rubinstein <nrubinstein at proformatique.com >
> I'm trying to port Intel Truxton to CAR. So far, serial output works and 
> Coreboot fails during SPD dump. If I remove the SPD dump, serial output 
> doesn't work anymore (??).
> I have been told on the chan to post my current progress here. The patch 
> is not meant to be used as-is, and contains a lot of unrelated code, as 
> I was explicitly requested to leave things as they are.
> -- 
> No? Rubinstein
> Proformatique (groupe Avencall) - XiVO IPBX OpenHardware
> 10 bis, rue Lucien VOILIN - 92800 Puteaux
> T?l. : +33 (0)1 41 38 99 60 ext 123
> Fax. : +33 (0)1 41 38 99 70
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 

Could also be something is funky with your memory controller not
initializing correctly, this would cause bad SPD reads.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From the.mighty.alien.dwarf at gmail.com  Thu Mar 10 02:31:16 2011
From: the.mighty.alien.dwarf at gmail.com (the.mighty.alien.dwarf)
Date: Thu, 10 Mar 2011 03:31:16 +0200
Subject: [coreboot] [The 604 CAR crusades][Master Yoda style] Postludium
In-Reply-To: <4D77DD25.20604@gmail.com>
References: <4D77DD25.20604@gmail.com>
Message-ID: <4D7829E4.5020505@gmail.com>

These patches to commit you want.

Master Yoda



From jktu17 at gmail.com  Fri Mar 11 11:19:17 2011
From: jktu17 at gmail.com (Oleg Gvozdev)
Date: Fri, 11 Mar 2011 13:19:17 +0300
Subject: [coreboot] Support for Core i3 and better
Message-ID: <AANLkTikOhRm+XaOeDMDMkp1SSXU-CruZFmPChaVFM8xC@mail.gmail.com>

Hello
Could you, please, advise what motherboard I should use with coreboot to
support Core i3, i5 or i7 CPU ?
And if any of these CPUs is not supported for now, where they will be
supported?

As an alternative: do you support Core 2 Duo and with what motheboard ?

Thanks
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From mr.nuke.me at gmail.com  Fri Mar 11 11:53:50 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Fri, 11 Mar 2011 12:53:50 +0200
Subject: [coreboot] Support for Core i3 and better
In-Reply-To: <AANLkTikOhRm+XaOeDMDMkp1SSXU-CruZFmPChaVFM8xC@mail.gmail.com>
References: <AANLkTikOhRm+XaOeDMDMkp1SSXU-CruZFmPChaVFM8xC@mail.gmail.com>
Message-ID: <4D79FF3E.7080506@gmail.com>

On 03/11/2011 12:19 PM, Oleg Gvozdev wrote:
> Hello
> Could you, please, advise what motherboard I should use with coreboot to
> support Core i3, i5 or i7 CPU ?
Yes.

> And if any of these CPUs is not supported for now, where they will be
> supported?
In their momma's gusset.

> As an alternative: do you support Core 2 Duo and with what motheboard ?
>
A little word of advice. Coming and asking us about what hardware to buy
from a vendor that is more evil and uncooperative than Satan, is not
going to bring you happy respondents. We're getting tired of having to
tell people that Intel does not provide the documentation needed to
support their hardware.

So, suck it up, and look at AMD's offering instead.

Alex



From prakash at punnoor.de  Fri Mar 11 11:28:54 2011
From: prakash at punnoor.de (Prakash Punnoor)
Date: Fri, 11 Mar 2011 11:28:54 +0100
Subject: [coreboot] [PATCH] Dump some more registers for Winbond W83627DHG
Message-ID: <201103111128.59960.prakash@punnoor.de>

Hi,

I noticed some registers of Winbond W83627DHG, which the datasheet mentions, 
were not dumped by superiotool. This patch adds those registers to the dump.

Signed-off-by: Prakash Punnoor <prakash at punnoor.de>
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From joe at settoplinux.org  Fri Mar 11 12:41:32 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 11 Mar 2011 06:41:32 -0500
Subject: [coreboot] Support for Core i3 and better
In-Reply-To: <4D79FF3E.7080506@gmail.com>
References: <AANLkTikOhRm+XaOeDMDMkp1SSXU-CruZFmPChaVFM8xC@mail.gmail.com>
	<4D79FF3E.7080506@gmail.com>
Message-ID: <e9c91d577890a958f81937822299c6c1@imap.1and1.com>



On Fri, 11 Mar 2011 12:53:50 +0200, "Alex G." <mr.nuke.me at gmail.com> wrote:
> On 03/11/2011 12:19 PM, Oleg Gvozdev wrote:
>> Hello
>> Could you, please, advise what motherboard I should use with coreboot to
>> support Core i3, i5 or i7 CPU ?
> Yes.
> 
>> And if any of these CPUs is not supported for now, where they will be
>> supported?
> In their momma's gusset.
> 
>> As an alternative: do you support Core 2 Duo and with what motheboard ?
>>
> A little word of advice. Coming and asking us about what hardware to buy
> from a vendor that is more evil and uncooperative than Satan, is not
> going to bring you happy respondents. We're getting tired of having to
> tell people that Intel does not provide the documentation needed to
> support their hardware.
> 
> So, suck it up, and look at AMD's offering instead.
> 
Wow! 

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From jktu17 at gmail.com  Fri Mar 11 12:50:32 2011
From: jktu17 at gmail.com (Oleg Gvozdev)
Date: Fri, 11 Mar 2011 14:50:32 +0300
Subject: [coreboot] Support for Core i3 and better
In-Reply-To: <4D79FF3E.7080506@gmail.com>
References: <AANLkTikOhRm+XaOeDMDMkp1SSXU-CruZFmPChaVFM8xC@mail.gmail.com>
	<4D79FF3E.7080506@gmail.com>
Message-ID: <AANLkTikEKsAiA_a_wegkPU1O6fqLYUv9rvUO0ERASmpF@mail.gmail.com>

2011/3/11 Alex G. <mr.nuke.me at gmail.com>

> On 03/11/2011 12:19 PM, Oleg Gvozdev wrote:
> > Hello
> > Could you, please, advise what motherboard I should use with coreboot to
> > support Core i3, i5 or i7 CPU ?
> Yes.
>
> > And if any of these CPUs is not supported for now, where they will be
> > supported?
> In their momma's gusset.
>
> > As an alternative: do you support Core 2 Duo and with what motheboard ?
> >
> A little word of advice. Coming and asking us about what hardware to buy
> from a vendor that is more evil and uncooperative than Satan, is not
> going to bring you happy respondents. We're getting tired of having to
> tell people that Intel does not provide the documentation needed to
> support their hardware.
>
> So, suck it up, and look at AMD's offering instead.
>
> Alex
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


Thanks,

I look now at Gygabyte GA-MA785GMT-UD2H and AM3 socket.


And my final questions are the next:

1. Does Coreboot work with Phenom II  Thuban CPU ? I want 6-core CPU of
Phenom2

2. If it does not, what do you suggest from quadcores Phenom2 AM3 or AM+..
(i wrote your sentence about Satan,but i dont want to spend money on
unworking system)

I just need as much powerfull CPU as it can be to use with Coreboot.
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From joe at settoplinux.org  Fri Mar 11 14:42:17 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 11 Mar 2011 08:42:17 -0500
Subject: [coreboot] Support for Core i3 and better
In-Reply-To: <AANLkTikEKsAiA_a_wegkPU1O6fqLYUv9rvUO0ERASmpF@mail.gmail.com>
References: <AANLkTikOhRm+XaOeDMDMkp1SSXU-CruZFmPChaVFM8xC@mail.gmail.com>
	<4D79FF3E.7080506@gmail.com>
	<AANLkTikEKsAiA_a_wegkPU1O6fqLYUv9rvUO0ERASmpF@mail.gmail.com>
Message-ID: <234ed6e8a7f497dd0d0582f189525e65@imap.1and1.com>



On Fri, 11 Mar 2011 14:50:32 +0300, Oleg Gvozdev <jktu17 at gmail.com> wrote:
> 2011/3/11 Alex G. <mr.nuke.me at gmail.com>
> 
>> On 03/11/2011 12:19 PM, Oleg Gvozdev wrote:
>> > Hello
>> > Could you, please, advise what motherboard I should use with coreboot
> to
>> > support Core i3, i5 or i7 CPU ?
>> Yes.
>>
>> > And if any of these CPUs is not supported for now, where they will be
>> > supported?
>> In their momma's gusset.
>>
>> > As an alternative: do you support Core 2 Duo and with what motheboard
?
>> >
>> A little word of advice. Coming and asking us about what hardware to buy
>> from a vendor that is more evil and uncooperative than Satan, is not
>> going to bring you happy respondents. We're getting tired of having to
>> tell people that Intel does not provide the documentation needed to
>> support their hardware.
>>
>> So, suck it up, and look at AMD's offering instead.
>>
>> Alex
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
> 
> 
> Thanks,
> 
> I look now at Gygabyte GA-MA785GMT-UD2H and AM3 socket.
> 
> 
> And my final questions are the next:
> 
> 1. Does Coreboot work with Phenom II  Thuban CPU ? I want 6-core CPU of
> Phenom2
> 
> 2. If it does not, what do you suggest from quadcores Phenom2 AM3 or
AM+..
> (i wrote your sentence about Satan,but i dont want to spend money on
> unworking system)
> 
> I just need as much powerfull CPU as it can be to use with Coreboot.

Did you look here?
http://www.coreboot.org/Supported_Motherboards

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From mr.nuke.me at gmail.com  Fri Mar 11 16:49:50 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Fri, 11 Mar 2011 17:49:50 +0200
Subject: [coreboot] Support for Core i3 and better
In-Reply-To: <AANLkTikEKsAiA_a_wegkPU1O6fqLYUv9rvUO0ERASmpF@mail.gmail.com>
References: <AANLkTikOhRm+XaOeDMDMkp1SSXU-CruZFmPChaVFM8xC@mail.gmail.com>	<4D79FF3E.7080506@gmail.com>
	<AANLkTikEKsAiA_a_wegkPU1O6fqLYUv9rvUO0ERASmpF@mail.gmail.com>
Message-ID: <4D7A449E.7090507@gmail.com>

On 03/11/2011 01:50 PM, Oleg Gvozdev wrote:
> I look now at Gygabyte GA-MA785GMT-UD2H and AM3 socket.
> 
And this is the board I would have suggested. It's the only officially
suppported board with AM3 and DDR3.
http://www.coreboot.org/GIGABYTE_GA-MA785GMT-UD2H

The problem with this board is that it comes in several "versions".
We've had people having difficulties getting other versions to run, but
most of the hard work is done. With a bit of patience at worst, you
should be able to get it running.

You could theoretically get any AM3 board and port it; this will be
extra work, however.

> 1. Does Coreboot work with Phenom II  Thuban CPU ? I want 6-core CPU of
> Phenom2
> 
It's supported.

> 2. If it does not, what do you suggest from quadcores Phenom2 AM3 or
> AM+.. (i wrote your sentence about Satan,but i dont want to spend money
> on unworking system)
> 
AM3 six-core is porbably the best bet for anyone wanting to run coreboot
on a modern system.

> I just need as much powerfull CPU as it can be to use with Coreboot.
> 
Well, there is Socket G34, which is mostly the same silicon as the
Phenom II, and it comes in 8 or 12-core variants (and 1, 2 or 4 sockets
-- up to 48 cores total) _*_BUT_*_ this will need serious work to get
running.  Even with AMD's excellent cooperation, this is no easy task.
Such a job will turn you into a coreboot developer. ;)

Alex




From peter at stuge.se  Fri Mar 11 23:21:46 2011
From: peter at stuge.se (Peter Stuge)
Date: Fri, 11 Mar 2011 23:21:46 +0100
Subject: [coreboot] Coreboot for AMD Fusion family 14h: ASRock E350M1
In-Reply-To: <4D794BF0.4070502@gmail.com>
References: <20110224173841.30173.qmail@stuge.se>
	<EEE8936604F64C53BBF4825727C6C554@m3a78>
	<4D791152.5010405@gmail.com>
	<791C3B2490B643D6BDE823471907517E@m3a78>
	<4D794BF0.4070502@gmail.com>
Message-ID: <20110311222146.30638.qmail@stuge.se>

Anish Patel wrote:
>> ]are there any plans to support this new GOP model they (the EFI
>> ]guys) are trying to push?
>>
>> I like the idea of replacing a 16-bit binary module with 32-bit
>> source code.
..
> Well Intel lets you get to their GOP module with IMGD/EMGD for
> certain products.  They also have this EPOG thingy for their BLDK
> thing they just built.

Great. Please send a patch that you have made sure is legal.


> which apparently is also going to be released for their other
> procs too.

Great. Please send patches for those too!


//Peter



From svens at stackframe.org  Sat Mar 12 01:18:06 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sat, 12 Mar 2011 00:18:06 +0000
Subject: [coreboot] [PATCH 2/3] ec/acpi: make ACPI register pair configurable
In-Reply-To: <1299889087-3174-1-git-send-email-svens@stackframe.org>
References: <1299889087-3174-1-git-send-email-svens@stackframe.org>
Message-ID: <1299889087-3174-2-git-send-email-svens@stackframe.org>

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/ec/acpi/ec.c |   23 ++++++++++++++++-------
 src/ec/acpi/ec.h |    1 +
 2 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
index e353260..1d4ffb8 100644
--- a/src/ec/acpi/ec.c
+++ b/src/ec/acpi/ec.c
@@ -25,12 +25,15 @@
 #include <delay.h>
 #include "ec.h"
 
+static int ec_cmd_reg = EC_SC;
+static int ec_data_reg = EC_DATA;
+
 int send_ec_command(u8 command)
 {
 	int timeout;
 
 	timeout = 0x7ff;
-	while ((inb(EC_SC) & EC_IBF) && --timeout) {
+	while ((inb(ec_cmd_reg) & EC_IBF) && --timeout) {
 		udelay(10);
 		if ((timeout & 0xff) == 0)
 			printk(BIOS_SPEW, ".");
@@ -41,7 +44,7 @@ int send_ec_command(u8 command)
 		// return -1;
 	}
 
-	outb(command, EC_SC);
+	outb(command, ec_cmd_reg);
 	return 0;
 }
 
@@ -50,7 +53,7 @@ int send_ec_data(u8 data)
 	int timeout;
 
 	timeout = 0x7ff;
-	while ((inb(EC_SC) & EC_IBF) && --timeout) { // wait for IBF = 0
+	while ((inb(ec_cmd_reg) & EC_IBF) && --timeout) { // wait for IBF = 0
 		udelay(10);
 		if ((timeout & 0xff) == 0)
 			printk(BIOS_SPEW, ".");
@@ -61,14 +64,14 @@ int send_ec_data(u8 data)
 		// return -1;
 	}
 
-	outb(data, EC_DATA);
+	outb(data, ec_data_reg);
 
 	return 0;
 }
 
 int send_ec_data_nowait(u8 data)
 {
-	outb(data, EC_DATA);
+	outb(data, ec_data_reg);
 
 	return 0;
 }
@@ -80,7 +83,7 @@ u8 recv_ec_data(void)
 
 	timeout = 0x7fff;
 	while (--timeout) { // Wait for OBF = 1
-		if (inb(EC_SC) & EC_OBF) {
+		if (inb(ec_cmd_reg) & EC_OBF) {
 			break;
 		}
 		udelay(10);
@@ -92,7 +95,7 @@ u8 recv_ec_data(void)
 		// return -1;
 	}
 
-	data = inb(EC_DATA);
+	data = inb(ec_data_reg);
 	printk(BIOS_DEBUG, "recv_ec_data: 0x%02x\n", data);
 
 	return data;
@@ -123,6 +126,12 @@ void ec_clr_bit(u8 addr, u8 bit)
 	ec_write(addr, ec_read(addr) &  ~(1 << bit));
 }
 
+void ec_set_ports(u16 cmd_reg, u16 data_reg)
+{
+	ec_cmd_reg = cmd_reg;
+	ec_data_reg = data_reg;
+}
+
 struct chip_operations ec_acpi_ops = {
 	CHIP_NAME("ACPI Embedded Controller")
 };
diff --git a/src/ec/acpi/ec.h b/src/ec/acpi/ec.h
index cabbfea..b5a1197 100644
--- a/src/ec/acpi/ec.h
+++ b/src/ec/acpi/ec.h
@@ -46,6 +46,7 @@ u8 ec_read(u8 addr);
 int ec_write(u8 addr, u8 data);
 void ec_set_bit(u8 addr, u8 bit);
 void ec_clr_bit(u8 addr, u8 bit);
+void ec_set_ports(u16 cmd_reg, u16 data_reg);
 
 #endif
 
-- 
1.7.4.1




From svens at stackframe.org  Sat Mar 12 01:18:07 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sat, 12 Mar 2011 00:18:07 +0000
Subject: [coreboot] [PATCH 3/3] X60: use I/O 0x1600/0x1604 for ACPI accesses
In-Reply-To: <1299889087-3174-1-git-send-email-svens@stackframe.org>
References: <1299889087-3174-1-git-send-email-svens@stackframe.org>
Message-ID: <1299889087-3174-3-git-send-email-svens@stackframe.org>

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/x60/mainboard.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
index b8e6a49..79e4a83 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -50,6 +50,11 @@ static void wlan_enable(void)
 
 static void mainboard_enable(device_t dev)
 {
+	/* Enable 1600/1604 register pair */
+	ec_set_bit(0x00, 0x05);
+	/* switch to just enabled registers for ACPI */
+	ec_set_ports(0x1604, 0x1600);
+
 	backlight_enable();
 	trackpoint_enable();
 	/* FIXME: this should be ACPI's task
-- 
1.7.4.1




From svens at stackframe.org  Sat Mar 12 01:18:05 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sat, 12 Mar 2011 00:18:05 +0000
Subject: [coreboot] [PATCH 1/3] ACPI EC: add ec_set_bit() / ec_clr_bit()
Message-ID: <1299889087-3174-1-git-send-email-svens@stackframe.org>

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/ec/acpi/ec.c |   10 ++++++++++
 src/ec/acpi/ec.h |    2 ++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
index 7a01b7e..e353260 100644
--- a/src/ec/acpi/ec.c
+++ b/src/ec/acpi/ec.c
@@ -113,6 +113,16 @@ int ec_write(u8 addr, u8 data)
 	return send_ec_data(data);
 }
 
+void ec_set_bit(u8 addr, u8 bit)
+{
+	ec_write(addr, ec_read(addr) | (1 << bit));
+}
+
+void ec_clr_bit(u8 addr, u8 bit)
+{
+	ec_write(addr, ec_read(addr) &  ~(1 << bit));
+}
+
 struct chip_operations ec_acpi_ops = {
 	CHIP_NAME("ACPI Embedded Controller")
 };
diff --git a/src/ec/acpi/ec.h b/src/ec/acpi/ec.h
index 77ee637..cabbfea 100644
--- a/src/ec/acpi/ec.h
+++ b/src/ec/acpi/ec.h
@@ -44,6 +44,8 @@ int send_ec_data_nowait(u8 data);
 u8 recv_ec_data(void);
 u8 ec_read(u8 addr);
 int ec_write(u8 addr, u8 data);
+void ec_set_bit(u8 addr, u8 bit);
+void ec_clr_bit(u8 addr, u8 bit);
 
 #endif
 
-- 
1.7.4.1




From stefan.reinauer at coreboot.org  Sat Mar 12 00:19:41 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 12 Mar 2011 00:19:41 +0100
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <4D782D2C.6090800@gmail.com>
References: <4D77DD25.20604@gmail.com> <4D77EA46.7010000@gmail.com>
	<20110309211940.GA6991@coreboot.org>
	<4D781B9C.8020405@settoplinux.org> <4D7823AC.4050309@gmail.com>
	<4D782CAC.80101@settoplinux.org> <4D782D2C.6090800@gmail.com>
Message-ID: <20110311231940.GA2211@coreboot.org>

* Alex G. <mr.nuke.me at gmail.com> [110310 02:45]:
> On 03/10/2011 03:43 AM, Joseph Smith wrote:
> > Sorry to say Alex, unless someone can with the hardware (at least one
> > board can confirm) I will have to sit this one out. I know from
> > developing CAR for both i830 and i810 that things can got wrong very
> > easily, and if they do you will not even get serial output....
> > Sorry.
> > 
> Sorry to say that someone with the Tyan board I mentioned has already
> tested, otherwise it would not have been committed as CAR in the tree,
> and I would not have wasted this monumental amount of time converting
> the rest.
> 
> Tyan S2735 is the board you're looking for. If this is not enough for
> you, then please shoot me. :)
> 
> Alex

The S2735 is a dual Xeon server board. While I am pretty sure that this
one worked nicely at some point, I don't think that this suggests that
we should enable the same CAR code on all other socket 604 boards
without testing.

Stefan

 



From mr.nuke.me at gmail.com  Sat Mar 12 00:32:20 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Sat, 12 Mar 2011 01:32:20 +0200
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <20110311231940.GA2211@coreboot.org>
References: <4D77DD25.20604@gmail.com> <4D77EA46.7010000@gmail.com>
	<20110309211940.GA6991@coreboot.org>
	<4D781B9C.8020405@settoplinux.org> <4D7823AC.4050309@gmail.com>
	<4D782CAC.80101@settoplinux.org> <4D782D2C.6090800@gmail.com>
	<20110311231940.GA2211@coreboot.org>
Message-ID: <4D7AB104.6070901@gmail.com>

On 03/12/2011 01:19 AM, Stefan Reinauer wrote:
> The S2735 is a dual Xeon server board. While I am pretty sure that this
> one worked nicely at some point, I don't think that this suggests that
> we should enable the same CAR code on all other socket 604 boards
> without testing.
>
Umh, the same CAR code is used for all supported Intel CPUs. I don't
know why you guys are so skeptical on this. It's code that's been proven
to work on numerous CPUs, including the socket that this patch is
referring to.

Alex



From stefan.reinauer at coreboot.org  Sat Mar 12 00:40:49 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 12 Mar 2011 00:40:49 +0100
Subject: [coreboot] [PATCH 3/3] X60: use I/O 0x1600/0x1604 for ACPI
 accesses
In-Reply-To: <1299889087-3174-3-git-send-email-svens@stackframe.org>
References: <1299889087-3174-1-git-send-email-svens@stackframe.org>
	<1299889087-3174-3-git-send-email-svens@stackframe.org>
Message-ID: <20110311234049.GA14109@coreboot.org>

* Sven Schnelle <svens at stackframe.org> [110312 01:18]:
> Signed-off-by: Sven Schnelle <svens at stackframe.org>
> ---
>  src/mainboard/lenovo/x60/mainboard.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
> index b8e6a49..79e4a83 100644
> --- a/src/mainboard/lenovo/x60/mainboard.c
> +++ b/src/mainboard/lenovo/x60/mainboard.c
> @@ -50,6 +50,11 @@ static void wlan_enable(void)
>  
>  static void mainboard_enable(device_t dev)
>  {
> +	/* Enable 1600/1604 register pair */
> +	ec_set_bit(0x00, 0x05);
> +	/* switch to just enabled registers for ACPI */
> +	ec_set_ports(0x1604, 0x1600);
> +

I think you only need to use the high ports in SMM code to avoid race
conditions.

Stefan



From stefan.reinauer at coreboot.org  Sat Mar 12 00:41:40 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 12 Mar 2011 00:41:40 +0100
Subject: [coreboot] [PATCH 3/3] X60: use I/O 0x1600/0x1604 for ACPI
 accesses
In-Reply-To: <1299889087-3174-3-git-send-email-svens@stackframe.org>
References: <1299889087-3174-1-git-send-email-svens@stackframe.org>
	<1299889087-3174-3-git-send-email-svens@stackframe.org>
Message-ID: <20110311234140.GB14109@coreboot.org>

* Sven Schnelle <svens at stackframe.org> [110312 01:18]:
> Signed-off-by: Sven Schnelle <svens at stackframe.org>
> ---
>  src/mainboard/lenovo/x60/mainboard.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
> index b8e6a49..79e4a83 100644
> --- a/src/mainboard/lenovo/x60/mainboard.c
> +++ b/src/mainboard/lenovo/x60/mainboard.c
> @@ -50,6 +50,11 @@ static void wlan_enable(void)
>  
>  static void mainboard_enable(device_t dev)
>  {
> +	/* Enable 1600/1604 register pair */
> +	ec_set_bit(0x00, 0x05);
> +	/* switch to just enabled registers for ACPI */

I think the comment is misleading. ACPI has nothing to do with this.

> +	ec_set_ports(0x1604, 0x1600);
> +




From stefan.reinauer at coreboot.org  Sat Mar 12 00:42:49 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 12 Mar 2011 00:42:49 +0100
Subject: [coreboot] [PATCH 2/3] ec/acpi: make ACPI register pair
 configurable
In-Reply-To: <1299889087-3174-2-git-send-email-svens@stackframe.org>
References: <1299889087-3174-1-git-send-email-svens@stackframe.org>
	<1299889087-3174-2-git-send-email-svens@stackframe.org>
Message-ID: <20110311234249.GA16059@coreboot.org>

* Sven Schnelle <svens at stackframe.org> [110312 01:18]:
> Signed-off-by: Sven Schnelle <svens at stackframe.org>
> ---
>  src/ec/acpi/ec.c |   23 ++++++++++++++++-------
>  src/ec/acpi/ec.h |    1 +
>  2 files changed, 17 insertions(+), 7 deletions(-)

I wonder if you want two sets of access functions, like on the Getac
P470 instead of changing the base address on the fly.






From stefan.reinauer at coreboot.org  Sat Mar 12 02:02:08 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 12 Mar 2011 02:02:08 +0100
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <4D7AB104.6070901@gmail.com>
References: <4D77DD25.20604@gmail.com> <4D77EA46.7010000@gmail.com>
	<20110309211940.GA6991@coreboot.org>
	<4D781B9C.8020405@settoplinux.org> <4D7823AC.4050309@gmail.com>
	<4D782CAC.80101@settoplinux.org> <4D782D2C.6090800@gmail.com>
	<20110311231940.GA2211@coreboot.org> <4D7AB104.6070901@gmail.com>
Message-ID: <20110312010208.GA9775@coreboot.org>

* Alex G. <mr.nuke.me at gmail.com> [110312 00:32]:
> Umh, the same CAR code is used for all supported Intel CPUs. 

No, it's not. It just happens to live in a directory that seems to imply
this. There are quire a number of Intel CPUs that don't work with that
code (Intel Core/Core 2 and Atom being some of the ones that are
supported by special code). In fact, I think the code in cpu/intel/car
only supports a very small number of Intel CPUs.

Stefan



From mr.nuke.me at gmail.com  Sat Mar 12 02:38:17 2011
From: mr.nuke.me at gmail.com (Alex G.)
Date: Sat, 12 Mar 2011 03:38:17 +0200
Subject: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III -
 Revenge of the Abuild
In-Reply-To: <20110312010208.GA9775@coreboot.org>
References: <4D77DD25.20604@gmail.com> <4D77EA46.7010000@gmail.com>
	<20110309211940.GA6991@coreboot.org>
	<4D781B9C.8020405@settoplinux.org> <4D7823AC.4050309@gmail.com>
	<4D782CAC.80101@settoplinux.org> <4D782D2C.6090800@gmail.com>
	<20110311231940.GA2211@coreboot.org> <4D7AB104.6070901@gmail.com>
	<20110312010208.GA9775@coreboot.org>
Message-ID: <4D7ACE89.300@gmail.com>

On 03/12/2011 03:02 AM, Stefan Reinauer wrote:
> * Alex G. <mr.nuke.me at gmail.com> [110312 00:32]:
>> Umh, the same CAR code is used for all supported Intel CPUs. 
> 
> No, it's not. It just happens to live in a directory that seems to imply
> this. There are quire a number of Intel CPUs that don't work with that
> code (Intel Core/Core 2 and Atom being some of the ones that are
> supported by special code). In fact, I think the code in cpu/intel/car
> only supports a very small number of Intel CPUs.

You'sa point is well seen; however, your previous arguments about
thrashing these patches are not. As far as debating those arguments, I'm
just too tired to pointlessly try to get people to do something useful. :(

Alex




From dhendrix at google.com  Sat Mar 12 03:29:37 2011
From: dhendrix at google.com (David Hendricks)
Date: Fri, 11 Mar 2011 18:29:37 -0800
Subject: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13
Message-ID: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>

Hey everyone,
Stefan and I are going to be @ Google in Mountain View hacking on Coreboot
this weekend, so we figured this would be a good time to host another users
group meeting for those interested. This time we'll be hacking on our shiny
new AMD Persimmons (Fam 14h / Fusion) dev boards which I have been assured
by AMD are non-confidential so anyone curious can come in and poke at 'em.
Or you can swing by Fry's before coming and pick up a generic E350 board,
like the one Scott Duplichan recently ported:
http://www.coreboot.org/pipermail/coreboot/2011-February/063737.html

When: Sunday Mar. 13, noon to 8pm
Where: 1950 Charleston Rd. in Mountain View [
Link<http://maps.google.com/maps?q=1950+charleston+rd+mountain+view+ca&ie=UTF8&hq=&hnear=1950+Charleston+Rd,+Mountain+View,+Santa+Clara,+California+94043&gl=us&t=h&z=16>
],
Alamitos conference room (1st floor, adjacent to lobby)
Contact #: 408-512-3445

(last meeting's participants bcc'd since this is pretty short notice)

-- 
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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From tsylla at alum.mit.edu  Sat Mar 12 04:23:11 2011
From: tsylla at alum.mit.edu (Tom Sylla)
Date: Fri, 11 Mar 2011 19:23:11 -0800
Subject: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13
In-Reply-To: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>
References: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>
Message-ID: <AANLkTi=ZgiwbxK6Kz9mYOKdha7KBDwuXD+bZMOjyAHxi@mail.gmail.com>

Central Computers has a couple in stock also, the GA-E350N-USB3 (dual
BIOS pain) and I believe the E35M1-M Pro (microATX)

On Fri, Mar 11, 2011 at 6:29 PM, David Hendricks <dhendrix at google.com> wrote:
> Hey everyone,
> Stefan and I are going to be @ Google in Mountain View hacking on Coreboot
> this weekend, so we figured this would be a good time to host another users
> group meeting for those interested. This time we'll be hacking on our shiny
> new AMD Persimmons (Fam 14h / Fusion) dev boards which I have been assured
> by AMD are non-confidential so anyone curious can come in and poke at 'em.
> Or you can swing by Fry's before coming and pick up a generic E350 board,
> like the one Scott Duplichan recently
> ported:?http://www.coreboot.org/pipermail/coreboot/2011-February/063737.html
> When:?Sunday Mar. 13, noon to 8pm
> Where: 1950 Charleston Rd. in Mountain View [?Link?], Alamitos conference
> room (1st floor, adjacent to lobby)
> Contact #: 408-512-3445
> (last meeting's participants bcc'd since this is pretty short notice)
> --
> David Hendricks (dhendrix)
> Systems Software Engineer, Google Inc.
>



From gregg.drwho8 at gmail.com  Sat Mar 12 05:14:08 2011
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Fri, 11 Mar 2011 23:14:08 -0500
Subject: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13
In-Reply-To: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>
References: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>
Message-ID: <AANLkTinkKo8eGoU5U0CS2JD+PAQKE-3bu-R5O7Xyx_+o@mail.gmail.com>

On Fri, Mar 11, 2011 at 9:29 PM, David Hendricks <dhendrix at google.com> wrote:
> Hey everyone,
> Stefan and I are going to be @ Google in Mountain View hacking on Coreboot
> this weekend, so we figured this would be a good time to host another users
> group meeting for those interested. This time we'll be hacking on our shiny
> new AMD Persimmons (Fam 14h / Fusion) dev boards which I have been assured
> by AMD are non-confidential so anyone curious can come in and poke at 'em.
> Or you can swing by Fry's before coming and pick up a generic E350 board,
> like the one Scott Duplichan recently
> ported:?http://www.coreboot.org/pipermail/coreboot/2011-February/063737.html
> When:?Sunday Mar. 13, noon to 8pm
> Where: 1950 Charleston Rd. in Mountain View [?Link?], Alamitos conference
> room (1st floor, adjacent to lobby)
> Contact #: 408-512-3445
> (last meeting's participants bcc'd since this is pretty short notice)
> --
> David Hendricks (dhendrix)
> Systems Software Engineer, Google Inc.
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Hello!
I imagine it would not practical to throw a Coreboot based event here
in NYC? I've been to the Google NYC Offices before, and it looks, well
good to me.

Although off list I can relate some issues I can't make public.....
-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature fought the Time Wars, time and again."



From svens at stackframe.org  Sat Mar 12 09:16:45 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sat, 12 Mar 2011 09:16:45 +0100
Subject: [coreboot] [PATCH 3/3] X60: use I/O 0x1600/0x1604 for ACPI
	accesses
In-Reply-To: <20110311234049.GA14109@coreboot.org> (Stefan Reinauer's message
	of "Sat\, 12 Mar 2011 00\:40\:49 +0100")
References: <1299889087-3174-1-git-send-email-svens@stackframe.org>
	<1299889087-3174-3-git-send-email-svens@stackframe.org>
	<20110311234049.GA14109@coreboot.org>
Message-ID: <87d3lweosy.fsf@begreifnix.stackframe.org>

Stefan Reinauer <stefan.reinauer at coreboot.org> writes:

> * Sven Schnelle <svens at stackframe.org> [110312 01:18]:
>> Signed-off-by: Sven Schnelle <svens at stackframe.org>
>> ---
>>  src/mainboard/lenovo/x60/mainboard.c |    5 +++++
>>  1 files changed, 5 insertions(+), 0 deletions(-)
>> 
>> diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
>> index b8e6a49..79e4a83 100644
>> --- a/src/mainboard/lenovo/x60/mainboard.c
>> +++ b/src/mainboard/lenovo/x60/mainboard.c
>> @@ -50,6 +50,11 @@ static void wlan_enable(void)
>>  
>>  static void mainboard_enable(device_t dev)
>>  {
>> +	/* Enable 1600/1604 register pair */
>> +	ec_set_bit(0x00, 0x05);
>> +	/* switch to just enabled registers for ACPI */
>> +	ec_set_ports(0x1604, 0x1600);
>> +
>
> I think you only need to use the high ports in SMM code to avoid race
> conditions.

Yes. But the original BIOS switches to those ports at the same time, and
i want to do it the same way. Makes comparing bus cycles easier, and has
no disadvantages IMHO.



From svens at stackframe.org  Sat Mar 12 09:20:35 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sat, 12 Mar 2011 09:20:35 +0100
Subject: [coreboot] [PATCH 3/3] X60: use I/O 0x1600/0x1604 for ACPI
	accesses
In-Reply-To: <20110311234140.GB14109@coreboot.org> (Stefan Reinauer's message
	of "Sat\, 12 Mar 2011 00\:41\:40 +0100")
References: <1299889087-3174-1-git-send-email-svens@stackframe.org>
	<1299889087-3174-3-git-send-email-svens@stackframe.org>
	<20110311234140.GB14109@coreboot.org>
Message-ID: <877hc4eomk.fsf@begreifnix.stackframe.org>

Stefan Reinauer <stefan.reinauer at coreboot.org> writes:

> * Sven Schnelle <svens at stackframe.org> [110312 01:18]:
>> Signed-off-by: Sven Schnelle <svens at stackframe.org>
>> ---
>>  src/mainboard/lenovo/x60/mainboard.c |    5 +++++
>>  1 files changed, 5 insertions(+), 0 deletions(-)
>> 
>> diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
>> index b8e6a49..79e4a83 100644
>> --- a/src/mainboard/lenovo/x60/mainboard.c
>> +++ b/src/mainboard/lenovo/x60/mainboard.c
>> @@ -50,6 +50,11 @@ static void wlan_enable(void)
>>  
>>  static void mainboard_enable(device_t dev)
>>  {
>> +	/* Enable 1600/1604 register pair */
>> +	ec_set_bit(0x00, 0x05);
>> +	/* switch to just enabled registers for ACPI */
>
> I think the comment is misleading. ACPI has nothing to do with this.

You're right. This is obviously wrong. Those are the EC registers, not
ACPI ;)

Sven.



From svens at stackframe.org  Sat Mar 12 09:23:55 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Sat, 12 Mar 2011 09:23:55 +0100
Subject: [coreboot] [PATCH 2/3] ec/acpi: make ACPI register pair
	configurable
In-Reply-To: <20110311234249.GA16059@coreboot.org> (Stefan Reinauer's message
	of "Sat\, 12 Mar 2011 00\:42\:49 +0100")
References: <1299889087-3174-1-git-send-email-svens@stackframe.org>
	<1299889087-3174-2-git-send-email-svens@stackframe.org>
	<20110311234249.GA16059@coreboot.org>
Message-ID: <8739mseoh0.fsf@begreifnix.stackframe.org>

Stefan Reinauer <stefan.reinauer at coreboot.org> writes:

> * Sven Schnelle <svens at stackframe.org> [110312 01:18]:
>> Signed-off-by: Sven Schnelle <svens at stackframe.org>
>> ---
>>  src/ec/acpi/ec.c |   23 ++++++++++++++++-------
>>  src/ec/acpi/ec.h |    1 +
>>  2 files changed, 17 insertions(+), 7 deletions(-)
>
> I wonder if you want two sets of access functions, like on the Getac
> P470 instead of changing the base address on the fly.

I like the Adress configuration more. Accessing the 0x1600/0x1604
register pair works the same way as the 0x62/0x66 pair, so i dont
like to copy all the accessor function just because the base address
changed. And the performance impact of looking up the addresses instead
of having it as a literal in the outb asembler instruction is probably
negligible.

Sven.



From xdrudis at tinet.cat  Sat Mar 12 10:53:44 2011
From: xdrudis at tinet.cat (xdrudis)
Date: Sat, 12 Mar 2011 10:53:44 +0100
Subject: [coreboot] Support for Core i3 and better
In-Reply-To: <4D7A449E.7090507@gmail.com>
References: <AANLkTikOhRm+XaOeDMDMkp1SSXU-CruZFmPChaVFM8xC@mail.gmail.com>
	<4D79FF3E.7080506@gmail.com>
	<AANLkTikEKsAiA_a_wegkPU1O6fqLYUv9rvUO0ERASmpF@mail.gmail.com>
	<4D7A449E.7090507@gmail.com>
Message-ID: <20110312095344.GA3800@ideafix.casa.ct>

On Fri, Mar 11, 2011 at 05:49:50PM +0200, Alex G. wrote:
> > 1. Does Coreboot work with Phenom II  Thuban CPU ? I want 6-core CPU of
> > Phenom2
> > 
> It's supported.
>

I didn't know this had been tested. It's a little difficult for me to
keep track of all mail in the list.

http://www.coreboot.org/Supported_Chipsets_and_Devices

says [only?] FAM10 revisions B0-B3 are supported.

My Phenom II X4 910e is rev RB_C3 and still doesn't boot (although I
no longer think it's the CPU but the southbridge, I can't confirm
either until I can boot).

According to 
http://en.wikipedia.org/wiki/List_of_AMD_Phenom_microprocessors#Phenom_series
all Phenom II X6 would be revision E0 (one could look at more authoritative 
sources, maybe)

In theory many revisions should work.  In practice there are some
constants in src/northbridge/amd/amdmct/amddefs.h which allocate one
bit in a 32 bit value for each revision. Then these are used to build
masks to test whether to apply workarounds for CPU errata or
particular initializations (like in
src/cpu/amd/model_10xxx/defaults.h).  Some revisions (beyond HY_D0, I
think), don't fit in these 32 bits.  I suspect those revisions may not
work, but maybe these revisions might work because they
just don't need workarounds, etc. I even sent some patches that would 
only make sense for revision E and they were committed, but I couldn't 
test them (I sent them precisely because I thought no revision E CPU 
had been used with coreboot, so I couldn't break anything that worked before, 
just hopefully add a small part to support future work).

It might be good to collect a list of tested CPU revisions and maybe 
any issues found or any tests performed, if the supported chipsets 
page is out of date for FAM10. 

I'm sorry I can't contribute to this list though, until my board boots. 

P.S. Whether E0 works or not, there's good documentation for it, so it 
is fixable. 



From peter at stuge.se  Sat Mar 12 14:14:56 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 12 Mar 2011 14:14:56 +0100
Subject: [coreboot] Support for Core i3 and better
In-Reply-To: <AANLkTikEKsAiA_a_wegkPU1O6fqLYUv9rvUO0ERASmpF@mail.gmail.com>
References: <AANLkTikOhRm+XaOeDMDMkp1SSXU-CruZFmPChaVFM8xC@mail.gmail.com>
	<4D79FF3E.7080506@gmail.com>
	<AANLkTikEKsAiA_a_wegkPU1O6fqLYUv9rvUO0ERASmpF@mail.gmail.com>
Message-ID: <20110312131456.20943.qmail@stuge.se>

Oleg Gvozdev wrote:
> i dont want to spend money on unworking system
> 
> I just need as much powerfull CPU as it can be to use with
> Coreboot.

If you are willing to spend a bit of time with the source code, and
you have programming experience and knowledge of CPUs then I think
you'll be successful. As was pointed out, I'm not sure the higher
end multicore CPUs have been tested on recent boards, however.

You would help the project and your fellow CPU power needing person
by testing with coreboot and worst case spending some time to get
things to work.

In general, if what you need is to pay for something that you do not
want to touch, then open source is the wrong answer.

If you are looking for a service provider that can create a solution
then there are a few of those within the coreboot community as well.
Explain a bit more about your requirements and one of them could get
in touch, if this is what you seek.


//Peter



From echelon at free.fr  Sat Mar 12 17:47:08 2011
From: echelon at free.fr (Florentin Demetrescu)
Date: Sat, 12 Mar 2011 17:47:08 +0100
Subject: [coreboot] Coreboot Hackathon
In-Reply-To: <20110118100932.5638.qmail@stuge.se>
References: <AANLkTikSyLgtxR4sD+n9iZm3rahuWrqT0--E0kGNGJuM@mail.gmail.com>
	<4D356263.50907@assembler.cz> <20110118100932.5638.qmail@stuge.se>
Message-ID: <1299948428.4d7ba38caa0aa@webmail.free.fr>

Hello,

Are you people (from Europe and .. abroad) still interested for a coreboot
hackathon in april/may in Prague?
Today there are only 4 answers for the doodle poll started by Rudolph.
By the way, Rudolph, do you think it is still possible for you to organise this
event in Prague anytime soon or not? Do you need some help eventually?
In general, for my part, I'm very interested for this kind of event, but
unfortunately I don't have right now the time/resources to travel to America so
doing it in Europe will be a good thing this time for me.. :-/

Best regards,
 Florentin

Quoting Peter Stuge <peter at stuge.se>:

> Rudolf Marek wrote:
> > Well for all those Europeans which might feel bit sad that
> > California is "far far way" I have a following proposal.
> >
> > Lets meet in Prague for a weekend in April/May.
>
> These are really awesome initiatives! I wish I could come to both,
> but I guess it'll be Prague for me.
>
> In any case, we also have a good opportunity to meet up during
> FOSDEM, and I hope that a lot of people will be there.
>
> Last year we did the devroom and that pretty much kept everyone
> occupied full time. This year it is "only" an expo stand and a talk,
> but I think there will still not be a lot of time for hacking - so
> the hackathons are a wonderful idea.
>
>
> > Prague is not so distant:
> >
> > Prague - Dresden - 153km
> > Prague - Wien - 334km
> > Prague - Nurnberg - 291km
>
> I might come by car from Berlin, and could of course pick up some
> passengers along the way.
>
>
> > I created some doodle (which contains just fridays from the intended
> > weekends).
> >
> > http://doodle.com/2n4h3gcugwvs6c9k
>
> Note that LinuxTag has moved into May (11-14) so we should plan a
> date around that somehow cleverly. I think the first two weekends
> in May are out, but question is if we want to do hackathon before
> or after LinuxTag.
>
> At LinuxTag there are usually more people interested in using
> coreboot than developing, but there are exceptions, and it would be
> great to invite those who are interested to the hackathon.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>





From r.marek at assembler.cz  Sat Mar 12 18:35:02 2011
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 12 Mar 2011 18:35:02 +0100
Subject: [coreboot] Coreboot Hackathon
In-Reply-To: <1299948428.4d7ba38caa0aa@webmail.free.fr>
References: <AANLkTikSyLgtxR4sD+n9iZm3rahuWrqT0--E0kGNGJuM@mail.gmail.com>	<4D356263.50907@assembler.cz>
	<20110118100932.5638.qmail@stuge.se>
	<1299948428.4d7ba38caa0aa@webmail.free.fr>
Message-ID: <4D7BAEC6.3090506@assembler.cz>

Hi,

Yes I think it looks like the may 27,28,29 date fits for us all.

The doodle is here:

http://doodle.com/2n4h3gcugwvs6c9k

I think I can still do that. Current plan is to use a computer lab at university 
with preinstalled coreboot related toolchains etc.

As for the accommodation i think I can reserve some dormitory style.

Preliminary Plan

Friday evening, social "pub" style event (beer or Kofola drought ;)
Saturday - hackaton from 9-21 afterwards some Prague night walk
Sunday - hackaton + departure.

As very preliminary I try to get some google money for google developers to get 
them to Prague even from US.

Thanks,
Rudolf






From echelon at free.fr  Sat Mar 12 20:06:21 2011
From: echelon at free.fr (Florentin Demetrescu)
Date: Sat, 12 Mar 2011 20:06:21 +0100
Subject: [coreboot] Coreboot Hackathon
In-Reply-To: <4D7BAEC6.3090506@assembler.cz>
References: <AANLkTikSyLgtxR4sD+n9iZm3rahuWrqT0--E0kGNGJuM@mail.gmail.com>
	<4D356263.50907@assembler.cz> <20110118100932.5638.qmail@stuge.se>
	<1299948428.4d7ba38caa0aa@webmail.free.fr>
	<4D7BAEC6.3090506@assembler.cz>
Message-ID: <1299956781.4d7bc42dd569a@webmail.free.fr>

Great!
Count me in!..
It would be nice if many coreboot "historical gurus" ( ;-) ) do the travel to
make the event even more interesting..
Anyway thank you Rudolf for your efforts!
 Florentin

Quoting Rudolf Marek <r.marek at assembler.cz>:

> Hi,
>
> Yes I think it looks like the may 27,28,29 date fits for us all.
>
> The doodle is here:
>
> http://doodle.com/2n4h3gcugwvs6c9k
>
> I think I can still do that. Current plan is to use a computer lab at
> university
> with preinstalled coreboot related toolchains etc.
>
> As for the accommodation i think I can reserve some dormitory style.
>
> Preliminary Plan
>
> Friday evening, social "pub" style event (beer or Kofola drought ;)
> Saturday - hackaton from 9-21 afterwards some Prague night walk
> Sunday - hackaton + departure.
>
> As very preliminary I try to get some google money for google developers to
> get
> them to Prague even from US.
>
> Thanks,
> Rudolf
>
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>





From stefan.reinauer at coreboot.org  Sat Mar 12 21:32:52 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 12 Mar 2011 12:32:52 -0800
Subject: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13
In-Reply-To: <AANLkTinkKo8eGoU5U0CS2JD+PAQKE-3bu-R5O7Xyx_+o@mail.gmail.com>
References: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>
	<AANLkTinkKo8eGoU5U0CS2JD+PAQKE-3bu-R5O7Xyx_+o@mail.gmail.com>
Message-ID: <4D7BD874.8020609@coreboot.org>

On 3/11/11 8:14 PM, Gregg Levine wrote:
> Hello!
> I imagine it would not practical to throw a Coreboot based event here
> in NYC? I've been to the Google NYC Offices before, and it looks, well
> good to me.
>
> Although off list I can relate some issues I can't make public.....

I don't know of any NYC Googlers involved in coreboot. However, don't 
let that discourage you!

If you find some fellow coreboot folks around NYC, you should go ahead 
and organize a meeting. If you can't find a conference room to use, any 
cafe will usually do fine. They might look weird at you when you bring 
too much hardware, but we've never had any (real) trouble with that 
approach when trying this in Brussels, Denver or Hamburg. :-)


Stefan



From ward at gnu.org  Sat Mar 12 21:50:37 2011
From: ward at gnu.org (Ward Vandewege)
Date: Sat, 12 Mar 2011 15:50:37 -0500
Subject: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13
In-Reply-To: <4D7BD874.8020609@coreboot.org>
References: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>
	<AANLkTinkKo8eGoU5U0CS2JD+PAQKE-3bu-R5O7Xyx_+o@mail.gmail.com>
	<4D7BD874.8020609@coreboot.org>
Message-ID: <20110312205037.GA21351@countzero.vandewege.net>

On Sat, Mar 12, 2011 at 12:32:52PM -0800, Stefan Reinauer wrote:
> If you find some fellow coreboot folks around NYC, you should go
> ahead and organize a meeting. If you can't find a conference room to
> use, any cafe will usually do fine. They might look weird at you
> when you bring too much hardware, but we've never had any (real)
> trouble with that approach when trying this in Brussels, Denver or
> Hamburg. :-)

Well, in Hamburg they were a bit upset about this after about three
consecutive evenings of hacking in the hotel lobby. Ah, well.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From joe at settoplinux.org  Sat Mar 12 22:09:19 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 12 Mar 2011 16:09:19 -0500
Subject: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13
In-Reply-To: <AANLkTinkKo8eGoU5U0CS2JD+PAQKE-3bu-R5O7Xyx_+o@mail.gmail.com>
References: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>
	<AANLkTinkKo8eGoU5U0CS2JD+PAQKE-3bu-R5O7Xyx_+o@mail.gmail.com>
Message-ID: <02e79d7d-d57b-4051-9564-ced7744b1e3f@email.android.com>

Hello I am in the new england area so NYC is not to far for me :-)
-- 
Sent from my Android phone with K-9 Mail. Please excuse my brevity.

Gregg Levine <gregg.drwho8 at gmail.com> wrote:

On Fri, Mar 11, 2011 at 9:29 PM, David Hendricks <dhendrix at google.com> wrote: > Hey everyone, > Stefan and I are going to be @ Google in Mountain View hacking on Coreboot > this weekend, so we figured this would be a good time to host another users > group meeting for those interested. This time we'll be hacking on our shiny > new AMD Persimmons (Fam 14h / Fusion) dev boards which I have been assured > by AMD are non-confidential so anyone curious can come in and poke at 'em. > Or you can swing by Fry's before coming and pick up a generic E350 board, > like the one Scott Duplichan recently > ported: http://www.coreboot.org/pipermail/coreboot/2011-February/063737.html > When: Sunday Mar. 13, noon to 8pm > Where: 1950 Charleston Rd. in Mountain View [ Link ], Alamitos conference > room (1st floor, adjacent to lobby) > Contact #: 408-512-3445 > (last meeting's participants bcc'd since this is pretty short notice) > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Hello! I imagine it would not practical to throw a Coreboot based event here in NYC? I've been to the Google NYC Offices before, and it looks, well good to me. Although off list I can relate some issues I can't make public..... ----- Gregg C Levine gregg.drwho8 at gmail.com "This signature fought the Time Wars, time and again." -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot 

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From peter at stuge.se  Sat Mar 12 22:34:52 2011
From: peter at stuge.se (Peter Stuge)
Date: Sat, 12 Mar 2011 22:34:52 +0100
Subject: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13
In-Reply-To: <20110312205037.GA21351@countzero.vandewege.net>
References: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>
	<AANLkTinkKo8eGoU5U0CS2JD+PAQKE-3bu-R5O7Xyx_+o@mail.gmail.com>
	<4D7BD874.8020609@coreboot.org>
	<20110312205037.GA21351@countzero.vandewege.net>
Message-ID: <20110312213452.28450.qmail@stuge.se>

Ward Vandewege wrote:
> Well, in Hamburg they were a bit upset about this after about three
> consecutive evenings of hacking in the hotel lobby. Ah, well.

I think because they wanted to rent out their conference room. Use a
place without conference room, but just the lobby. :)


//Peter



From anish.mailing.list at gmail.com  Sat Mar 12 23:07:16 2011
From: anish.mailing.list at gmail.com (Anish Patel)
Date: Sat, 12 Mar 2011 17:07:16 -0500
Subject: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13
In-Reply-To: <02e79d7d-d57b-4051-9564-ced7744b1e3f@email.android.com>
References: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>	<AANLkTinkKo8eGoU5U0CS2JD+PAQKE-3bu-R5O7Xyx_+o@mail.gmail.com>
	<02e79d7d-d57b-4051-9564-ced7744b1e3f@email.android.com>
Message-ID: <4D7BEE94.8030004@gmail.com>

how many other new englanders are there on CB?
maybe portland or boston can do one

On 03/12/11 16:09, Joseph Smith wrote:
> Hello I am in the new england area so NYC is not to far for me :-)
> -- 
> Sent from my Android phone with K-9 Mail. Please excuse my brevity.
>
> Gregg Levine <gregg.drwho8 at gmail.com> wrote:
>
>     On Fri, Mar 11, 2011 at 9:29 PM, David Hendricks
>     <dhendrix at google.com> wrote:
>     > Hey everyone,
>     > Stefan and I are going to be @ Google in Mountain View hacking
>     on Coreboot
>     > this weekend, so we figured this would be a good time to host
>     another users
>     > group meeting for those interested. This time we'll be hacking
>     on our shiny
>     > new AMD Persimmons (Fam 14h / Fusion) dev boards which I have
>     been assured
>     > by AMD are non-confidential so anyone curious can come in and
>     poke at 'em.
>     > Or you can swing by Fry's before coming and pick up a generic
>     E350 board,
>     > like the one Scott Duplichan recently
>     > ported:
>     http://www.coreboot.org/pipermail/coreboot/2011-February/063737.html
>     > When: Sunday Mar. 13, noon to 8pm
>     > Where: 1950 Charleston Rd. in Mountain View [ Link ], Alamitos
>     conference
>     > room (1st floor, adjacent to lobby)
>     > Contact #: 408-512-3445
>     > (last meeting's participants bcc'd since this is pretty short
>     notice)
>     > --
>     > David Hendricks (dhendrix)
>     > Systems Software Engineer, Google Inc.
>     >
>     > --
>     > coreboot mailing list: coreboot at coreboot.org
>     > http://www.coreboot.org/mailman/listinfo/coreboot
>     >
>
>     Hello!
>     I imagine it would not practical to throw a Coreboot based event
>     here in NYC? I've been to the Google NYC Offices before, and it
>     looks, well good to me.
>
>     Although off list I can relate some issues I can't make public.....
>     -----
>     Gregg C Levine gregg.drwho8 at gmail.com
>     "This signature fought the Time Wars, time and again."
>
>     -- 
>     coreboot mailing list: coreboot at coreboot.org
>     http://www.coreboot.org/mailman/listinfo/coreboot
>

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From corey.osgood at gmail.com  Sun Mar 13 01:35:12 2011
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 12 Mar 2011 19:35:12 -0500
Subject: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13
In-Reply-To: <4D7BEE94.8030004@gmail.com>
References: <AANLkTik=DeFjxN0XBjYbvkYSZd7OFDrA9q6HSGtQVGiL@mail.gmail.com>
	<AANLkTinkKo8eGoU5U0CS2JD+PAQKE-3bu-R5O7Xyx_+o@mail.gmail.com>
	<02e79d7d-d57b-4051-9564-ced7744b1e3f@email.android.com>
	<4D7BEE94.8030004@gmail.com>
Message-ID: <AANLkTinpjkd3KYyVLVGVH9q6B1jRMskrW1NQDjfEXxyS@mail.gmail.com>

I'm from the Bangor, ME area. I don't do coreboot hacking much
anymore, but I might show up if the date and location worked.

-Corey

On Sat, Mar 12, 2011 at 5:07 PM, Anish Patel
<anish.mailing.list at gmail.com> wrote:
> how many other new englanders are there on CB?
> maybe portland or boston can do one
>
> On 03/12/11 16:09, Joseph Smith wrote:
>
> Hello I am in the new england area so NYC is not to far for me :-)
> --
> Sent from my Android phone with K-9 Mail. Please excuse my brevity.
>
> Gregg Levine <gregg.drwho8 at gmail.com> wrote:
>>
>> On Fri, Mar 11, 2011 at 9:29 PM, David Hendricks <dhendrix at google.com>
>> wrote:
>> > Hey everyone,
>> > Stefan and I are going to be @ Google in Mountain View hacking on
>> > Coreboot
>> > this weekend, so we figured this would be a good time to host another
>> > users
>> > group meeting for those interested. This time we'll be hacking on our
>> > shiny
>> > new AMD Persimmons (Fam 14h / Fusion) dev boards which I have been
>> > assured
>> > by AMD are non-confidential so anyone curious can come in and poke at
>> > 'em.
>> > Or you can swing by Fry's before coming and pick up a generic E350
>> > board,
>> > like the one Scott Duplichan recently
>> >
>> > ported:?http://www.coreboot.org/pipermail/coreboot/2011-February/063737.html
>> > When:?Sunday Mar. 13, noon to 8pm
>> > Where: 1950 Charleston Rd. in Mountain View [?Link?], Alamitos
>> > conference
>> > room (1st floor, adjacent to lobby)
>> > Contact #: 408-512-3445
>> > (last meeting's participants bcc'd since this is pretty short notice)
>> > --
>> > David Hendricks (dhendrix)
>> > Systems Software Engineer, Google Inc.
>> >
>> > --
>> > coreboot mailing list: coreboot at coreboot.org
>> > http://www.coreboot.org/mailman/listinfo/coreboot
>> >
>>
>> Hello!
>> I imagine it would not practical to throw a Coreboot based event here in
>> NYC? I've been to the Google NYC Offices before, and it looks, well good to
>> me.
>>
>> Although off list I can relate some issues I can't make public.....
>> -----
>> Gregg C Levine gregg.drwho8 at gmail.com
>> "This signature fought the Time Wars, time and again."
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From scott at notabs.org  Sun Mar 13 04:47:56 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sat, 12 Mar 2011 21:47:56 -0600
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
Message-ID: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>

Hello,

I am trying to overcome problems building seabios/tools/kconfig from
the windows/mingw environment. Here are the failures:

1) Link step for tools/kconfig/conf fails to find regcomp/regexec/regfree.
   In the mingw environment these functions are available in libregex, 
   but libregex is not included in the standard library search. I have
   not found a way to add '-lregex' to the link command line:
   $(Q)$(HOSTCC) $(HOSTLDFLAGS) -o $@ $(addprefix $(obj)/,$($(@F)-objs)) $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
   HOSTLDFLAGS occurs too early in the file list for this use.
		
2) Link step for tools/kconfig/conf fails to find function uname().
   I can come up with a library to provide this function but need
   help passing it to the linker, same as with item 1.

3) Function mkdir() takes only one argument in the mingw environment,
   yet takes 2 arguments otherwise. I have not found a good way to 
   overcome this difference.

Thanks,
Scott

		
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From peter at stuge.se  Sun Mar 13 05:39:27 2011
From: peter at stuge.se (Peter Stuge)
Date: Sun, 13 Mar 2011 05:39:27 +0100
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
Message-ID: <20110313043927.18783.qmail@stuge.se>

Scott Duplichan wrote:
> I have not found a way to add '-lregex' to the link command line:
> $(Q)$(HOSTCC) $(HOSTLDFLAGS) -o $@ $(addprefix $(obj)/,$($(@F)-objs)) $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
> HOSTLDFLAGS occurs too early in the file list for this use.

I'd say the above command line is incorrect. HOSTLDFLAGS should come
right before HOST_LOADLIBES.


> 3) Function mkdir() takes only one argument in the mingw environment,
>    yet takes 2 arguments otherwise. I have not found a good way to 
>    overcome this difference.

#ifdef WIN32
	mkdir(path);
#else
	mkdir(path, mask);
#endif


//Peter



From patrick at georgi-clan.de  Sun Mar 13 08:20:52 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 13 Mar 2011 08:20:52 +0100
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
Message-ID: <4D7C7054.5000007@georgi-clan.de>

Am 13.03.2011 04:47, schrieb Scott Duplichan:
> Hello,
> 
> I am trying to overcome problems buildingseabios/tools/kconfigfrom
> 
> the windows/mingw environment.Hereare the failures:
> 
> 1)Link step fortools/kconfig/conffails to findregcomp/regexec/regfree.
> 
>   In the mingw environment these functions are available in libregex,
> 
>   but libregexis notincluded inthe standard library search. I have
> 
>   not found away to add'-lregex'to the link command line:
The main issue is that libregex isn't available reliably on mingw.
On coreboot, I simply added a libregex implementation to the tree and
added it to the build.


In general, maybe just copy over coreboot's kconfig and look for the
changes (there are some you'd have to revert)?


Patrick



From scott at notabs.org  Sun Mar 13 19:37:16 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 13 Mar 2011 13:37:16 -0500
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <20110313043927.18783.qmail@stuge.se>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
	<20110313043927.18783.qmail@stuge.se>
Message-ID: <928AB2AAF3094345B1E6060DC61C305C@m3a78>

Peter Stuge wrote:

]Scott Duplichan wrote:
]> I have not found a way to add '-lregex' to the link command line:
]> $(Q)$(HOSTCC) $(HOSTLDFLAGS) -o $@ $(addprefix $(obj)/,$($(@F)-objs)) $(HOST_LOADLIBES) ]$(HOSTLOADLIBES_$(@F))
]> HOSTLDFLAGS occurs too early in the file list for this use.
]
]I'd say the above command line is incorrect. HOSTLDFLAGS should come
]right before HOST_LOADLIBES.

I suppose so, at least for the use of adding libraries.

]> 3) Function mkdir() takes only one argument in the mingw environment,
]>    yet takes 2 arguments otherwise. I have not found a good way to 
]>    overcome this difference.
]
]#ifdef WIN32
]	mkdir(path);
]#else
]	mkdir(path, mask);
]#endif

This method works. I will repost this message on the seabios list
if no mingw change/fix can be found to get this build working.

]
]//Peter


Thanks,
Scott




From scott at notabs.org  Sun Mar 13 20:25:20 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 13 Mar 2011 14:25:20 -0500
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <4D7C7054.5000007@georgi-clan.de>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
	<4D7C7054.5000007@georgi-clan.de>
Message-ID: <DC4A41558EDE411CAE78DB6E3A618FEF@m3a78>

Patrick Georgi wrote:

]Am 13.03.2011 04:47, schrieb Scott Duplichan:
]> Hello,
]> 
]> I am trying to overcome problems buildingseabios/tools/kconfigfrom
]> the windows/mingw environment.Hereare the failures:
]> 1)Link step fortools/kconfig/conffails to findregcomp/regexec/regfree.
]>   In the mingw environment these functions are available in libregex,
]>   but libregexis notincluded inthe standard library search. I have
]>   not found away to add'-lregex'to the link command line:

]The main issue is that libregex isn't available reliably on mingw.
]On coreboot, I simply added a libregex implementation to the tree and
]added it to the build.

I thought about this method too. I could just add the needed objects
to a library that is already included in the default search.

]In general, maybe just copy over coreboot's kconfig and look for the
]changes (there are some you'd have to revert)?

This is essentially what I am doing now. To run abuild, I change
the default payload from seabios to none. I am hoping to find a
solution that works with no modification to the coreboot trunk
at all.

]Patrick

Here is another problem with using mingw to build coreboot. 
Building projects that include the new AMD reference code
(ASRock E350, AMD Persimmon, AMD Inagua) fail with the message,
"Couldn't commit memory for cygwin heap",
http://gitorious.org/msys/msys/blobs/MSYS-1_0_14/src/winsup/cygwin/cygheap.cc#line175
Restarting the build works around the problem. I found cygheap.cc
uses a very simple malloc/free scheme where the memory originates
from Windows function VirtualAlloc, yet is never returned by calling
VirtualFree. In addition, VirtualAlloc allocates one 4096 byte page
minimum, which is wasting a lot for allocations of only a few bytes.
For now, I just expanded CYGHEAPSIZE a bit. A better fix may be 
needed in the future.

Thanks,
Scott




From patrick at georgi-clan.de  Sun Mar 13 21:13:22 2011
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 13 Mar 2011 21:13:22 +0100
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <DC4A41558EDE411CAE78DB6E3A618FEF@m3a78>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
	<4D7C7054.5000007@georgi-clan.de>
	<DC4A41558EDE411CAE78DB6E3A618FEF@m3a78>
Message-ID: <4D7D2562.5050600@georgi-clan.de>

Am 13.03.2011 20:25, schrieb Scott Duplichan:
> ]In general, maybe just copy over coreboot's kconfig and look for the
> ]changes (there are some you'd have to revert)?
> 
> This is essentially what I am doing now. To run abuild, I change
> the default payload from seabios to none. I am hoping to find a
> solution that works with no modification to the coreboot trunk
> at all.
I was thinking about changing seabios' kconfig the same way we changed
coreboot's kconfig.
No changes to coreboot necessary.

> Here is another problem with using mingw to build coreboot. 
> Building projects that include the new AMD reference code
> (ASRock E350, AMD Persimmon, AMD Inagua) fail with the message,
> "Couldn't commit memory for cygwin heap",
> http://gitorious.org/msys/msys/blobs/MSYS-1_0_14/src/winsup/cygwin/cygheap.cc#line175
> Restarting the build works around the problem. I found cygheap.cc
> uses a very simple malloc/free scheme where the memory originates
> from Windows function VirtualAlloc, yet is never returned by calling
> VirtualFree. In addition, VirtualAlloc allocates one 4096 byte page
> minimum, which is wasting a lot for allocations of only a few bytes.
> For now, I just expanded CYGHEAPSIZE a bit. A better fix may be 
> needed in the future.
I'm not quite sure - are you using mingw or cygwin?


Patrick



From scott at notabs.org  Sun Mar 13 21:30:41 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 13 Mar 2011 15:30:41 -0500
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <4D7D2562.5050600@georgi-clan.de>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
	<4D7C7054.5000007@georgi-clan.de>
	<DC4A41558EDE411CAE78DB6E3A618FEF@m3a78>
	<4D7D2562.5050600@georgi-clan.de>
Message-ID: <A85E1A3E63BD4754BA750537E2A87CA0@m3a78>

Patrick Georgi wrote:

] I'm not quite sure - are you using mingw or cygwin?
] Patrick

I am using mingw. For my OS (Windows Server 2003 x64), cygwin
has a severe performance problem. Build time is at least 4
times that of mingw. Building is really painful when I use
cygwin.

The cygwin version of cygheap.cc seems more refined than the
mingw version of that file, though the cygwin version also
lacks a call to VirtualFree.

Thanks,
Scott




From joe at settoplinux.org  Sun Mar 13 23:45:24 2011
From: joe at settoplinux.org (Joseph Smith)
Date: Sun, 13 Mar 2011 18:45:24 -0400
Subject: [coreboot] Microcode CPU writeup
In-Reply-To: <4D6B4BBA.6080509@assembler.cz>
References: <4D6B4BBA.6080509@assembler.cz>
Message-ID: <4D7D4904.2030301@settoplinux.org>

On 02/28/2011 02:16 AM, Rudolf Marek wrote:
> Hi all,
>
> Would someone be interrested if I write something about microcoded CPUs
> controllers? Like the classic uCode ROM + ALU + Regs + IO unit?
>
> Thanks,
> Rudolf
>
>
>
Yeah sure :-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From stefan.reinauer at coreboot.org  Sun Mar 13 23:48:01 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sun, 13 Mar 2011 23:48:01 +0100
Subject: [coreboot] [PATCH 2/3] ec/acpi: make ACPI register pair
 configurable
In-Reply-To: <8739mseoh0.fsf@begreifnix.stackframe.org>
References: <1299889087-3174-1-git-send-email-svens@stackframe.org>
	<1299889087-3174-2-git-send-email-svens@stackframe.org>
	<20110311234249.GA16059@coreboot.org>
	<8739mseoh0.fsf@begreifnix.stackframe.org>
Message-ID: <20110313224801.GA20727@coreboot.org>

* Sven Schnelle <svens at stackframe.org> [110312 09:23]:
> Stefan Reinauer <stefan.reinauer at coreboot.org> writes:
> 
> > * Sven Schnelle <svens at stackframe.org> [110312 01:18]:
> >> Signed-off-by: Sven Schnelle <svens at stackframe.org>
> >> ---
> >>  src/ec/acpi/ec.c |   23 ++++++++++++++++-------
> >>  src/ec/acpi/ec.h |    1 +
> >>  2 files changed, 17 insertions(+), 7 deletions(-)

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>




From kevin at koconnor.net  Sun Mar 13 23:52:53 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sun, 13 Mar 2011 18:52:53 -0400
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
Message-ID: <20110313225253.GA4004@morn.localdomain>

On Sat, Mar 12, 2011 at 09:47:56PM -0600, Scott Duplichan wrote:
> Hello,
> 
> I am trying to overcome problems building seabios/tools/kconfig from
> the windows/mingw environment. Here are the failures:
> 
> 1) Link step for tools/kconfig/conf fails to find regcomp/regexec/regfree.
>    In the mingw environment these functions are available in libregex, 
>    but libregex is not included in the standard library search. I have
>    not found a way to add '-lregex' to the link command line:
>    $(Q)$(HOSTCC) $(HOSTLDFLAGS) -o $@ $(addprefix $(obj)/,$($(@F)-objs)) $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
>    HOSTLDFLAGS occurs too early in the file list for this use.

Can you add it to HOST_LOADLIBES?

> 2) Link step for tools/kconfig/conf fails to find function uname().
>    I can come up with a library to provide this function but need
>    help passing it to the linker, same as with item 1.
> 
> 3) Function mkdir() takes only one argument in the mingw environment,
>    yet takes 2 arguments otherwise. I have not found a good way to 
>    overcome this difference.

What about making a file "mingw_fixups.h" and changing the HOSTCFLAGS
to add "-include mingw_fixups.h".  The header can then do something
like:

#define uname(arg1) memset(arg1, 0, sizeof(*arg1))
#define mkdir(arg1,arg2) mkdir(arg1)

-Kevin



From stefan.reinauer at coreboot.org  Sun Mar 13 23:59:03 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sun, 13 Mar 2011 23:59:03 +0100
Subject: [coreboot] [PATCH 3/3] X60: use I/O 0x1600/0x1604 for ACPI
 accesses
In-Reply-To: <87d3lweosy.fsf@begreifnix.stackframe.org>
References: <1299889087-3174-1-git-send-email-svens@stackframe.org>
	<1299889087-3174-3-git-send-email-svens@stackframe.org>
	<20110311234049.GA14109@coreboot.org>
	<87d3lweosy.fsf@begreifnix.stackframe.org>
Message-ID: <20110313225903.GB20727@coreboot.org>

* Sven Schnelle <svens at stackframe.org> [110312 09:16]:
> Stefan Reinauer <stefan.reinauer at coreboot.org> writes:
> 
> > * Sven Schnelle <svens at stackframe.org> [110312 01:18]:
> >> Signed-off-by: Sven Schnelle <svens at stackframe.org>
> >> ---
> >>  src/mainboard/lenovo/x60/mainboard.c |    5 +++++
> >>  1 files changed, 5 insertions(+), 0 deletions(-)
> >> 
> >> diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
> >> index b8e6a49..79e4a83 100644
> >> --- a/src/mainboard/lenovo/x60/mainboard.c
> >> +++ b/src/mainboard/lenovo/x60/mainboard.c
> >> @@ -50,6 +50,11 @@ static void wlan_enable(void)
> >>  
> >>  static void mainboard_enable(device_t dev)
> >>  {
> >> +	/* Enable 1600/1604 register pair */
> >> +	ec_set_bit(0x00, 0x05);
> >> +	/* switch to just enabled registers for ACPI */
> >> +	ec_set_ports(0x1604, 0x1600);
> >> +
> >
> > I think you only need to use the high ports in SMM code to avoid race
> > conditions.
> 
> Yes. But the original BIOS switches to those ports at the same time, and
> i want to do it the same way. Makes comparing bus cycles easier, and has
> no disadvantages IMHO.

It does have a disadvantage if there is an SMI that accesses the EC
while you access the EC in your code, too.

Also be sure to explicitly re-set the right address in SMM mode,
otherwise SMM will still use the original registers as SMM uses an extra
copy of the EC access code.

Last but not least, make sure that 0x1600 is blocked from use of the
resource allocator for anything else.





From svn at coreboot.org  Mon Mar 14 03:21:55 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 03:21:55 +0100
Subject: [coreboot] [DirectHW] [commit] r1 - branches tags trunk
	trunk/macosx trunk/macosx/DirectHW
	trunk/macosx/DirectHW/DirectHW.pmdoc
	trunk/macosx/DirectHW/DirectHW.xcodeproj
	trunk/macosx/DirectHW/build trunk/macos...
Message-ID: <E1PyxPv-0002ri-Sp@ra.coresystems.de>

Author: stepan
Date: Mon Mar 14 03:21:55 2011
New Revision: 1
URL: https://tracker.coreboot.org/trac/directhw/changeset/1

Log:
Latest DirectHW version in public repository svn://coreboot.org/directhw
See http://www.coreboot.org/DirectHW for more information.

Added:
   branches/
   tags/
   trunk/
   trunk/macosx/
   trunk/macosx/DirectHW/
   trunk/macosx/DirectHW/Copying.rtf
   trunk/macosx/DirectHW/DirectHW-Framework-Info.plist
   trunk/macosx/DirectHW/DirectHW-Info.plist
   trunk/macosx/DirectHW/DirectHW-i386-only.diff
   trunk/macosx/DirectHW/DirectHW.c
   trunk/macosx/DirectHW/DirectHW.cpp
   trunk/macosx/DirectHW/DirectHW.h
   trunk/macosx/DirectHW/DirectHW.hpp
   trunk/macosx/DirectHW/DirectHW.pmdoc/
   trunk/macosx/DirectHW/DirectHW.pmdoc/01directhw-contents.xml
   trunk/macosx/DirectHW/DirectHW.pmdoc/01directhw.xml
   trunk/macosx/DirectHW/DirectHW.pmdoc/index.xml
   trunk/macosx/DirectHW/DirectHW.xcodeproj/
   trunk/macosx/DirectHW/DirectHW.xcodeproj/project.pbxproj
   trunk/macosx/DirectHW/Makefile
   trunk/macosx/DirectHW/ReadMe.rtf
   trunk/macosx/DirectHW/Welcome.rtf
   trunk/macosx/DirectHW/background.png   (contents, props changed)
   trunk/macosx/DirectHW/build/
   trunk/macosx/DirectHW/installer.png   (contents, props changed)
   trunk/macosx/Makefile
   trunk/macosx/create-dmg/
   trunk/macosx/create-dmg/create-dmg   (contents, props changed)
   trunk/macosx/create-dmg/sample   (contents, props changed)
   trunk/macosx/create-dmg/support/
   trunk/macosx/create-dmg/support/AdiumApplescriptRunner   (contents, props changed)
   trunk/macosx/create-dmg/support/template.applescript
   trunk/macosx/patches/
   trunk/macosx/patches/dmidecode-2.9.diff
   trunk/macosx/patches/flashrom-r1280.diff
   trunk/macosx/patches/inteltool-r6440.diff
   trunk/macosx/patches/msrtool-r6440.diff
   trunk/macosx/patches/nvramtool-r6440.diff
   trunk/macosx/patches/pciutils-3.1.7.diff
   trunk/macosx/patches/superiotool-r6440.diff
   trunk/windows/
   trunk/windows/README

Added: trunk/macosx/DirectHW/Copying.rtf
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/Copying.rtf	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,13 @@
+{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320
+{\fonttbl\f0\fnil\fcharset0 Monaco;}
+{\colortbl;\red255\green255\blue255;}
+\paperw11900\paperh16840\margl1440\margr1440\vieww12980\viewh15380\viewkind0
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+
+\f0\fs20 \cf0 DirectHW is Copyright \'a9 2008-2010 coresystems GmbH <{\field{\*\fldinst{HYPERLINK "mailto:info at coresystems.de"}}{\fldrslt info at coresystems.de}}>\
+\
+Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.\
+\
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\
+\
+Visit {\field{\*\fldinst{HYPERLINK "http://www.coresystems.de/"}}{\fldrslt http://www.coresystems.de/}} for more information.}
\ No newline at end of file

Added: trunk/macosx/DirectHW/DirectHW-Framework-Info.plist
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW-Framework-Info.plist	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
+<plist version="1.0">
+<dict>
+	<key>CFBundleDevelopmentRegion</key>
+	<string>English</string>
+	<key>CFBundleExecutable</key>
+	<string>${EXECUTABLE_NAME}</string>
+	<key>CFBundleIdentifier</key>
+	<string>com.coresystems.DirectHW</string>
+	<key>CFBundleInfoDictionaryVersion</key>
+	<string>6.0</string>
+	<key>CFBundlePackageType</key>
+	<string>FMWK</string>
+	<key>CFBundleSignature</key>
+	<string>????</string>
+	<key>CFBundleVersion</key>
+	<string>1.3</string>
+</dict>
+</plist>

Added: trunk/macosx/DirectHW/DirectHW-Info.plist
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW-Info.plist	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
+<plist version="1.0">
+<dict>
+	<key>CFBundleDevelopmentRegion</key>
+	<string>English</string>
+	<key>CFBundleExecutable</key>
+	<string>DirectHW</string>
+	<key>CFBundleIdentifier</key>
+	<string>com.coresystems.driver.DirectHW</string>
+	<key>CFBundleInfoDictionaryVersion</key>
+	<string>6.0</string>
+	<key>CFBundleName</key>
+	<string>DirectHW</string>
+	<key>CFBundlePackageType</key>
+	<string>KEXT</string>
+	<key>CFBundleSignature</key>
+	<string>????</string>
+	<key>CFBundleVersion</key>
+	<string>1.3</string>
+	<key>IOKitPersonalities</key>
+	<dict>
+		<key>DirectHWUserClient</key>
+		<dict>
+			<key>CFBundleIdentifier</key>
+			<string>com.coresystems.driver.DirectHW</string>
+			<key>IOClass</key>
+			<string>DirectHWService</string>
+			<key>IOMatchCategory</key>
+			<string>DirectHWService</string>
+			<key>IOProviderClass</key>
+			<string>IOResources</string>
+			<key>IOResourceMatch</key>
+			<string>IOKit</string>
+			<key>IOUserClientClass</key>
+			<string>DirectHWUserClient</string>
+		</dict>
+	</dict>
+	<key>OSBundleLibraries</key>
+	<dict>
+		<key>com.apple.kpi.mach</key>
+		<string>8.0.0</string>
+		<key>com.apple.kpi.iokit</key>
+		<string>8.0</string>
+		<key>com.apple.kpi.libkern</key>
+		<string>8.0</string>
+		<key>com.apple.kpi.unsupported</key>
+		<string>8.0</string>
+	</dict>
+</dict>
+</plist>

Added: trunk/macosx/DirectHW/DirectHW-i386-only.diff
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW-i386-only.diff	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,20 @@
+Index: DirectHW.xcodeproj/project.pbxproj
+===================================================================
+--- DirectHW.xcodeproj/project.pbxproj	(revision 110)
++++ DirectHW.xcodeproj/project.pbxproj	(working copy)
+@@ -202,7 +202,6 @@
+ 			isa = XCBuildConfiguration;
+ 			buildSettings = {
+ 				ARCHS = (
+-					x86_64,
+ 					i386,
+ 				);
+ 				COPY_PHASE_STRIP = NO;
+@@ -228,7 +227,6 @@
+ 			isa = XCBuildConfiguration;
+ 			buildSettings = {
+ 				ARCHS = (
+-					x86_64,
+ 					i386,
+ 				);
+ 				COPY_PHASE_STRIP = YES;

Added: trunk/macosx/DirectHW/DirectHW.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW.c	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,388 @@
+/*
+ * DirectHW.c - userspace part for DirectHW
+ *
+ * Copyright ? 2008-2010 coresystems GmbH <info at coresystems.de>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <AvailabilityMacros.h>
+#include <IOKit/IOKitLib.h>
+#include <ApplicationServices/ApplicationServices.h>
+#include <CoreFoundation/CoreFoundation.h>
+#include <unistd.h>
+#include <errno.h>
+#include "DirectHW.h"
+
+#ifndef MAP_FAILED
+#define MAP_FAILED	((void *)-1)
+#endif
+
+/* define WANT_OLD_API for support of OSX 10.4 and earlier */
+#undef WANT_OLD_API
+
+/* define DEBUG to print Framework debugging information */
+#undef DEBUG
+
+#define     err_get_system(err) (((err)>>26)&0x3f)
+#define     err_get_sub(err)    (((err)>>14)&0xfff)
+#define     err_get_code(err)   ((err)&0x3fff)
+
+enum {
+	kReadIO,
+	kWriteIO,
+	kPrepareMap,
+	kReadMSR,
+	kWriteMSR,
+	kNumberOfMethods
+};
+
+typedef struct {
+	UInt32 offset;
+	UInt32 width;
+	UInt32 data;
+} iomem_t;
+
+typedef struct {
+	UInt64 addr;
+	UInt64 size;
+} map_t;
+
+typedef struct {
+	UInt32 core;
+	UInt32 index;
+	UInt32 hi;
+	UInt32 lo;
+} msrcmd_t;
+
+static io_connect_t connect = -1;
+static io_service_t iokit_uc;
+
+static int darwin_init(void)
+{
+	kern_return_t err;
+
+	/* Note the actual security happens in the kernel module.
+	 * This check is just candy to be able to get nicer output
+	 */
+	if (getuid() != 0) {
+		/* Fun's reserved for root */
+		errno = EPERM;
+		return -1;
+	}
+
+	/* Get the DirectHW driver service */
+	iokit_uc = IOServiceGetMatchingService(kIOMasterPortDefault,
+					IOServiceMatching("DirectHWService"));
+
+	if (!iokit_uc) {
+		printf("DirectHW.kext not loaded.\n");
+		errno = ENOSYS;
+		return -1;
+	}
+
+	/* Create an instance */
+	err = IOServiceOpen(iokit_uc, mach_task_self(), 0, &connect);
+
+	/* Should not go further if error with service open */
+	if (err != KERN_SUCCESS) {
+		printf("Could not create DirectHW instance.\n");
+		errno = ENOSYS;
+		return -1;
+	}
+
+	return 0;
+}
+
+static void darwin_cleanup(void)
+{
+	IOServiceClose(connect);
+}
+
+static int darwin_ioread(int pos, unsigned char * buf, int len)
+{
+
+	kern_return_t err;
+	size_t dataInLen = sizeof(iomem_t);
+	size_t dataOutLen = sizeof(iomem_t);
+	iomem_t in;
+	iomem_t out;
+	UInt32 tmpdata;
+
+	in.width = len;
+	in.offset = pos;
+
+	if (len > 4)
+		return 1;
+
+#if !defined(__LP64__) && defined(WANT_OLD_API)
+	/* Check if OSX 10.5 API is available */
+	if (IOConnectCallStructMethod != NULL) {
+#endif
+		err = IOConnectCallStructMethod(connect, kReadIO, &in, dataInLen, &out, &dataOutLen);
+#if !defined(__LP64__) && defined(WANT_OLD_API)
+	} else {
+		/* Use old API */
+		err = IOConnectMethodStructureIStructureO(connect, kReadIO, dataInLen, &dataOutLen, &in, &out);
+	}
+#endif
+
+	if (err != KERN_SUCCESS)
+		return 1;
+
+	tmpdata = out.data;
+
+	switch (len) {
+	case 1:
+		memcpy(buf, &tmpdata, 1);
+		break;
+	case 2:
+		memcpy(buf, &tmpdata, 2);
+		break;
+	case 4:
+		memcpy(buf, &tmpdata, 4);
+		break;
+	}
+
+	return 0;
+}
+
+static int darwin_iowrite(int pos, unsigned char * buf, int len)
+{
+	kern_return_t err;
+	size_t dataInLen = sizeof(iomem_t);
+	size_t dataOutLen = sizeof(iomem_t);
+	iomem_t in;
+	iomem_t out;
+
+	in.width = len;
+	in.offset = pos;
+	memcpy(&in.data, buf, len);
+
+	if (len > 4)
+		return 1;
+
+#if !defined(__LP64__) && defined(WANT_OLD_API)
+	/* Check if OSX 10.5 API is available */
+	if (IOConnectCallStructMethod != NULL) {
+#endif
+		err = IOConnectCallStructMethod(connect, kWriteIO, &in, dataInLen, &out, &dataOutLen);
+#if !defined(__LP64__) && defined(WANT_OLD_API)
+	} else {
+		/* Use old API */
+		err = IOConnectMethodStructureIStructureO(connect, kWriteIO, dataInLen, &dataOutLen, &in, &out);
+	}
+#endif
+
+	if (err != KERN_SUCCESS)
+		return 1;
+
+	return 0;
+}
+
+
+/* Compatibility interface */
+
+unsigned char inb(unsigned short addr)
+{
+	unsigned char ret;
+	darwin_ioread(addr, &ret, 1);
+	return ret;
+}
+
+unsigned short inw(unsigned short addr)
+{
+	unsigned short ret;
+	darwin_ioread(addr, (unsigned char *)&ret, 2);
+	return ret;
+}
+
+unsigned int inl(unsigned short addr)
+{
+	unsigned int ret;
+	darwin_ioread(addr, (unsigned char *)&ret, 4);
+	return ret;
+}
+
+void outb(unsigned char val, unsigned short addr)
+{
+	darwin_iowrite(addr, &val, 1);
+}
+
+void outw(unsigned short val, unsigned short addr)
+{
+	darwin_iowrite(addr, (unsigned char *)&val, 2);
+}
+
+void outl(unsigned int val, unsigned short addr)
+{
+	darwin_iowrite(addr, (unsigned char *)&val, 4);
+}
+
+int iopl(int level __attribute__((unused)))
+{
+	atexit(darwin_cleanup);
+	return darwin_init();
+}
+
+void *map_physical(uint64_t phys_addr, size_t len)
+{
+	kern_return_t err;
+#if __LP64__
+	mach_vm_address_t addr;
+	mach_vm_size_t size;
+#else
+        vm_address_t addr;
+        vm_size_t size;
+#endif
+	size_t dataInLen = sizeof(map_t);
+	size_t dataOutLen = sizeof(map_t);
+	map_t in, out;
+
+	in.addr = phys_addr;
+	in.size = len;
+
+#ifdef DEBUG
+	printf("map_phys: phys %08lx, %08x\n", phys_addr, len);
+#endif
+
+#if !defined(__LP64__) && defined(WANT_OLD_API)
+	/* Check if OSX 10.5 API is available */
+	if (IOConnectCallStructMethod != NULL) {
+#endif
+		err = IOConnectCallStructMethod(connect, kPrepareMap, &in, dataInLen, &out, &dataOutLen);
+#if !defined(__LP64__) && defined(WANT_OLD_API)
+	} else {
+		/* Use old API */
+		err = IOConnectMethodStructureIStructureO(connect, kPrepareMap, dataInLen, &dataOutLen, &in, &out);
+	}
+#endif
+
+	if (err != KERN_SUCCESS) {
+		printf("\nError(kPrepareMap): system 0x%x subsystem 0x%x code 0x%x ",
+				err_get_system(err), err_get_sub(err), err_get_code(err));
+
+		printf("physical 0x%08lx[0x%x]\n", phys_addr, (unsigned int)len);
+
+		switch (err_get_code(err)) {
+		case 0x2c2: printf("Invalid argument.\n"); errno = EINVAL; break;
+		case 0x2cd: printf("Device not open.\n"); errno = ENOENT; break;
+		}
+
+		return MAP_FAILED;
+	}
+
+        err = IOConnectMapMemory(connect, 0, mach_task_self(),
+			&addr, &size, kIOMapAnywhere | kIOMapInhibitCache);
+
+	/* Now this is odd; The above connect seems to be unfinished at the
+	 * time the function returns. So wait a little bit, or the calling
+	 * program will just segfault. Bummer. Who knows a better solution?
+	 */
+	usleep(1000);
+
+	if (err != KERN_SUCCESS) {
+		printf("\nError(IOConnectMapMemory): system 0x%x subsystem 0x%x code 0x%x ",
+				err_get_system(err), err_get_sub(err), err_get_code(err));
+
+		printf("physical 0x%08lx[0x%x]\n", phys_addr, (unsigned int)len);
+
+		switch (err_get_code(err)) {
+		case 0x2c2: printf("Invalid argument.\n"); errno = EINVAL; break;
+		case 0x2cd: printf("Device not open.\n"); errno = ENOENT; break;
+		}
+
+		return MAP_FAILED;
+	}
+
+#ifdef DEBUG
+	printf("map_phys: virt %08x, %08x\n", addr, size);
+#endif
+
+        return (void *)addr;
+}
+
+void unmap_physical(void *virt_addr __attribute__((unused)), size_t len __attribute__((unused)))
+{
+	// Nut'n Honey
+}
+
+static int current_logical_cpu = 0;
+
+msr_t rdmsr(int addr)
+{
+	kern_return_t err;
+	size_t dataInLen = sizeof(msrcmd_t);
+	size_t dataOutLen = sizeof(msrcmd_t);
+	msrcmd_t in, out;
+	msr_t ret = { INVALID_MSR_HI, INVALID_MSR_LO };
+
+	in.core = current_logical_cpu;
+	in.index = addr;
+
+#if !defined(__LP64__) && defined(WANT_OLD_API)
+	/* Check if OSX 10.5 API is available */
+	if (IOConnectCallStructMethod != NULL) {
+#endif
+		err = IOConnectCallStructMethod(connect, kReadMSR, &in, dataInLen, &out, &dataOutLen);
+#if !defined(__LP64__) && defined(WANT_OLD_API)
+	} else {
+		/* Use old API */
+		err = IOConnectMethodStructureIStructureO(connect, kReadMSR, dataInLen, &dataOutLen, &in, &out);
+	}
+#endif
+
+	if (err != KERN_SUCCESS)
+		return ret;
+
+	ret.lo = out.lo;
+	ret.hi = out.hi;
+
+	return ret;
+}
+
+int wrmsr(int addr, msr_t msr)
+{
+	kern_return_t err;
+	size_t dataInLen = sizeof(msrcmd_t);
+	size_t dataOutLen = sizeof(msrcmd_t);
+	msrcmd_t in, out;
+
+	in.core = current_logical_cpu;
+	in.index = addr;
+	in.lo = msr.lo;
+	in.hi = msr.hi;
+
+#if !defined(__LP64__) && defined(WANT_OLD_API)
+	/* Check if OSX 10.5 API is available */
+	if (IOConnectCallStructMethod != NULL) {
+#endif
+		err = IOConnectCallStructMethod(connect, kWriteMSR, &in, dataInLen, &out, &dataOutLen);
+#if !defined(__LP64__) && defined(WANT_OLD_API)
+	} else {
+		/* Use old API */
+		err = IOConnectMethodStructureIStructureO(connect, kWriteMSR, dataInLen, &dataOutLen, &in, &out);
+	}
+#endif
+
+	if (err != KERN_SUCCESS)
+		return 1;
+
+	return 0;
+}
+
+int logical_cpu_select(int cpu)
+{
+	current_logical_cpu = cpu;
+}
+

Added: trunk/macosx/DirectHW/DirectHW.cpp
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW.cpp	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,395 @@
+/* DirectHW - Kernel extension to pass through IO commands to user space
+ *
+ * Copyright ? 2008-2010 coresystems GmbH <info at coresystems.de>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <IOKit/IOLib.h>
+#include <IOKit/IOService.h>
+#include <IOKit/IOUserClient.h>
+#include <IOKit/IOKitKeys.h>
+#include <IOKit/IOMemoryDescriptor.h>
+#include <architecture/i386/pio.h>
+
+#include "DirectHW.hpp"
+
+#undef DEBUG_KEXT
+//#define DEBUG_KEXT
+
+#define super IOService
+
+OSDefineMetaClassAndStructors(DirectHWService, IOService)
+
+bool DirectHWService::start(IOService * provider)
+{
+        IOLog("DirectHW: Driver v%s (compiled on %s) loaded. "
+		"Visit http://www.coresystems.de/ for more information.\n",
+			DIRECTHW_VERSION, __DATE__);
+
+	if (super::start(provider)) {
+		registerService();
+		return true;
+	}
+
+	return false;
+}
+
+#undef super
+#define super IOUserClient
+
+OSDefineMetaClassAndStructors(DirectHWUserClient, IOUserClient)
+
+const IOExternalMethod DirectHWUserClient::fMethods[kNumberOfMethods] = {
+	{0, (IOMethod) & DirectHWUserClient::ReadIO, kIOUCStructIStructO, sizeof(iomem_t), sizeof(iomem_t)},
+	{0, (IOMethod) & DirectHWUserClient::WriteIO, kIOUCStructIStructO, sizeof(iomem_t), sizeof(iomem_t)},
+	{0, (IOMethod) & DirectHWUserClient::PrepareMap, kIOUCStructIStructO, sizeof(map_t), sizeof(map_t)},
+	{0, (IOMethod) & DirectHWUserClient::ReadMSR, kIOUCStructIStructO, sizeof(msrcmd_t), sizeof(msrcmd_t)},
+	{0, (IOMethod) & DirectHWUserClient::WriteMSR, kIOUCStructIStructO, sizeof(msrcmd_t), sizeof(msrcmd_t)}
+};
+
+bool DirectHWUserClient::initWithTask(task_t task, void *securityID, UInt32 type)
+{
+	bool ret;
+
+	ret = super::initWithTask(task, securityID, type);
+
+#ifdef DEBUG_KEXT
+	IOLog("DirectHW: initWithTask(%p, %p, %08lx)\n", (void *)task, securityID, type);
+#endif
+        if (!ret) {
+		IOLog("DirectHW: initWithTask failed.\n");
+		return false;
+	}
+
+	fTask = task;
+
+	return true;
+}
+
+IOExternalMethod *DirectHWUserClient::getTargetAndMethodForIndex(IOService ** target, UInt32 index)
+{
+	if (index < (UInt32) kNumberOfMethods) {
+		if (fMethods[index].object == (IOService *) 0)
+			*target = this;
+
+		return (IOExternalMethod *) & fMethods[index];
+	} else {
+		*target = NULL;
+		return NULL;
+	}
+}
+
+bool DirectHWUserClient::start(IOService * provider)
+{
+	bool success;
+
+#ifdef DEBUG_KEXT
+	IOLog("DirectHW: Starting DirectHWUserClient\n");
+#endif
+
+	fProvider = OSDynamicCast(DirectHWService, provider);
+	success = (fProvider != NULL);
+
+	if (kIOReturnSuccess != clientHasPrivilege(current_task(),kIOClientPrivilegeAdministrator)) {
+		IOLog("DirectHW: Need to be administrator.\n");
+		success = false;
+	}
+
+	if (success) {
+		success = super::start(provider);
+#ifdef DEBUG_KEXT
+		IOLog("DirectHW: Client successfully started.\n");
+#endif
+	} else {
+		IOLog("DirectHW: Could not start client.\n");
+	}
+	return success;
+}
+
+void DirectHWUserClient::stop(IOService *provider)
+{
+#ifdef DEBUG_KEXT
+	IOLog("DirectHW: Stopping client.\n");
+#endif
+	super::stop(provider);
+}
+
+IOReturn DirectHWUserClient::clientClose(void)
+{
+	bool success = terminate();
+	if (!success) {
+		IOLog("DirectHW: Client NOT successfully closed.\n");
+	} else {
+#ifdef DEBUG_KEXT
+		IOLog("DirectHW: Client successfully closed.\n");
+#endif
+	}
+
+	return kIOReturnSuccess;
+}
+
+IOReturn
+DirectHWUserClient::ReadIO(iomem_t * inStruct, iomem_t * outStruct,
+				IOByteCount inStructSize,
+				IOByteCount * outStructSize)
+{
+
+	if (fProvider == NULL || isInactive()) {
+		return kIOReturnNotAttached;
+	}
+	 
+	switch (inStruct->width) {
+	case 1:
+		outStruct->data = inb(inStruct->offset);
+		break;
+	case 2:
+		outStruct->data = inw(inStruct->offset);
+		break;
+	case 4:
+		outStruct->data = inl(inStruct->offset);
+		break;
+	default:
+		IOLog("DirectHW: Invalid read attempt %d bytes at IO address %x\n",
+		      (int)inStruct->width, (unsigned int)inStruct->offset);
+		break;
+	}
+
+#ifdef DEBUG_KEXT
+	IOLog("DirectHW: Read %d bytes at IO address %x (result=%x)\n",
+		      inStruct->width, inStruct->offset, outStruct->data);
+#endif
+
+
+	*outStructSize = sizeof(iomem_t);
+
+	return kIOReturnSuccess;
+}
+
+
+IOReturn
+DirectHWUserClient::WriteIO(iomem_t * inStruct, iomem_t * outStruct,
+				 IOByteCount inStructSize,
+				 IOByteCount * outStructSize)
+{
+	if (fProvider == NULL || isInactive()) {
+		return kIOReturnNotAttached;
+	} 
+	
+#ifdef DEBUG_KEXT
+	IOLog("DirectHW: Write %d bytes at IO address %x (value=%x)\n",
+		      inStruct->width, inStruct->offset, inStruct->data);
+#endif
+	
+	switch (inStruct->width) {
+	case 1:
+		outb(inStruct->offset, inStruct->data);
+		break;
+	case 2:
+		outw(inStruct->offset, inStruct->data);
+		break;
+	case 4:
+		outl(inStruct->offset, inStruct->data);
+		break;
+	default:
+		IOLog("DirectHW: Invalid write attempt %d bytes at IO address %x\n",
+		      (int)inStruct->width, (unsigned int)inStruct->offset);
+	}
+
+	*outStructSize = sizeof(iomem_t);
+
+	return kIOReturnSuccess;
+}
+
+
+IOReturn
+DirectHWUserClient::PrepareMap(map_t * inStruct, map_t * outStruct,
+				IOByteCount inStructSize,
+				IOByteCount * outStructSize)
+{
+	if (fProvider == NULL || isInactive()) {
+		return kIOReturnNotAttached;
+	} 
+
+	if(LastMapAddr || LastMapSize)
+		return kIOReturnNotOpen;
+
+	LastMapAddr = inStruct->addr;
+	LastMapSize = inStruct->size;
+
+#ifdef DEBUG_KEXT
+	IOLog("DirectHW: PrepareMap 0x%08x[0x%x]\n", LastMapAddr, LastMapSize);
+#endif
+
+	*outStructSize = sizeof(map_t);
+
+	return kIOReturnSuccess;
+}
+
+inline void
+DirectHWUserClient::cpuid(uint32_t op1, uint32_t op2, uint32_t *data)
+{
+	asm("cpuid"
+		: "=a" (data[0]),
+		"=b" (data[1]),
+		"=c" (data[2]),
+		"=d" (data[3])
+		: "a"(op1), "c"(op2));
+}
+
+void
+DirectHWUserClient::MSRHelperFunction(void *data)
+{
+	MSRHelper * MSRData = (MSRHelper *)data;
+	msrcmd_t * inStruct = MSRData->in;
+	msrcmd_t * outStruct = MSRData->out;
+
+	outStruct->core = -1;
+	outStruct->lo = INVALID_MSR_LO;
+	outStruct->hi = INVALID_MSR_HI;
+
+	uint32_t cpuiddata[4];
+
+	cpuid(1, 0, cpuiddata);
+	bool have_ht = ((cpuiddata[3] & (1 << 28)) != 0);
+	uint32_t core_id = cpuiddata[1] >> 24;
+
+	cpuid(11, 0, cpuiddata);
+	uint32_t smt_mask = ~((-1) << (cpuiddata[0] &0x1f));
+
+	// TODO: What we want is this:
+	// if (inStruct->core != cpu_to_core(cpu_number()))
+	//	return;
+
+	if ((core_id & smt_mask) != core_id)
+		return; // It's a HT thread
+
+	if (inStruct->core != cpu_number())
+		return;
+
+	IOLog("DirectHW: ReadMSRHelper %d %d %x \n", inStruct->core,
+		cpu_number(), smt_mask);
+
+	if (MSRData->Read) {
+		asm volatile (
+			"rdmsr"
+			: "=a" (outStruct->lo), "=d" (outStruct->hi)
+			: "c" (inStruct->index)
+		);
+	} else {
+		asm volatile (
+			"wrmsr"
+			: /* No outputs */
+			: "c" (inStruct->index), "a" (inStruct->lo), "d" (inStruct->hi)
+		);
+	}
+
+	outStruct->index = inStruct->index;
+	outStruct->core = inStruct->core;
+}
+
+IOReturn
+DirectHWUserClient::ReadMSR(msrcmd_t * inStruct, msrcmd_t * outStruct,
+				IOByteCount inStructSize,
+				IOByteCount * outStructSize)
+{
+	if (fProvider == NULL || isInactive()) {
+		return kIOReturnNotAttached;
+	} 
+
+	MSRHelper MSRData = { inStruct, outStruct, true };
+	mp_rendezvous(NULL, (void (*)(void *))MSRHelperFunction, NULL,
+			(void *)&MSRData);
+
+	*outStructSize = sizeof(msrcmd_t);
+
+	if (outStruct->core != inStruct->core)
+		return kIOReturnIOError;
+
+	IOLog("DirectHW: ReadMSR(0x%08x) = 0x%08x:0x%08x\n",
+			(unsigned int)inStruct->index,
+			(unsigned int)outStruct->hi,
+			(unsigned int)outStruct->lo);
+
+	return kIOReturnSuccess;
+}
+
+IOReturn
+DirectHWUserClient::WriteMSR(msrcmd_t * inStruct, msrcmd_t * outStruct,
+				IOByteCount inStructSize,
+				IOByteCount * outStructSize)
+{
+	if (fProvider == NULL || isInactive()) {
+		return kIOReturnNotAttached;
+	} 
+
+	IOLog("DirectHW: WriteMSR(0x%08x) = 0x%08x:0x%08x\n",
+			(unsigned int)inStruct->index,
+			(unsigned int)inStruct->hi,
+			(unsigned int)inStruct->lo);
+
+	MSRHelper MSRData = { inStruct, outStruct, false };
+	mp_rendezvous(NULL, (void (*)(void *))MSRHelperFunction, NULL,
+			(void *)&MSRData);
+
+	*outStructSize = sizeof(msrcmd_t);
+
+	if (outStruct->core != inStruct->core)
+		return kIOReturnIOError;
+
+	return kIOReturnSuccess;
+}
+
+IOReturn DirectHWUserClient::clientMemoryForType(UInt32 type, UInt32 *flags, IOMemoryDescriptor **memory)
+{
+	IOMemoryDescriptor *newmemory;
+
+#ifdef DEBUG_KEXT
+	IOLog("DirectHW: clientMemoryForType(%x, %p, %p)\n", type, flags, memory);
+#endif
+	if (type != 0) {
+		IOLog("DirectHW: Unknown mapping type %x.\n", (unsigned int)type);
+		return kIOReturnUnsupported;
+	}
+
+	if ((LastMapAddr == 0) && (LastMapSize == 0)) {
+		IOLog("DirectHW: No PrepareMap called.\n");
+		return kIOReturnNotAttached;
+	}
+
+#ifdef DEBUG_KEXT
+	IOLog("DirectHW: Mapping physical 0x%08x[0x%x]\n",
+			LastMapAddr, LastMapSize);
+#endif
+
+	newmemory = IOMemoryDescriptor::withPhysicalAddress(LastMapAddr, LastMapSize, kIODirectionIn);
+	
+	/* Reset mapping to zero */
+	LastMapAddr = 0;
+	LastMapSize = 0;
+
+	if (newmemory == 0) {
+		IOLog("DirectHW: Could not map memory!\n");
+		return kIOReturnNotOpen;
+	}
+
+	newmemory->retain();
+	*memory = newmemory;
+
+#ifdef DEBUG_KEXT
+	IOLog("DirectHW: Mapping succeeded.\n");
+#endif
+
+	return kIOReturnSuccess;
+}
+

Added: trunk/macosx/DirectHW/DirectHW.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW.h	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,45 @@
+/*
+ * DirectHW.h - userspace part for DirectHW
+ *
+ * Copyright ? 2008-2010 coresystems GmbH <info at coresystems.de>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __DIRECTHW_H
+#define __DIRECTHW_H
+
+#include <stdint.h>
+
+int iopl(int unused);
+
+unsigned char inb(unsigned short addr);
+unsigned short inw(unsigned short addr);
+unsigned int inl(unsigned short addr);
+
+void outb(unsigned char val, unsigned short addr);
+void outw(unsigned short val, unsigned short addr);
+void outl(unsigned int val, unsigned short addr);
+
+void *map_physical(uint64_t phys_addr, size_t len);
+void unmap_physical(void *virt_addr, size_t len);
+
+typedef struct { uint32_t hi, lo; } msr_t;
+msr_t rdmsr(int addr);
+int wrmsr(int addr, msr_t msr);
+int logical_cpu_select(int cpu);
+
+#define INVALID_MSR_LO 0x63744857
+#define INVALID_MSR_HI 0x44697265
+
+#endif

Added: trunk/macosx/DirectHW/DirectHW.hpp
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW.hpp	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,127 @@
+/* DirectHW - Kernel extension to pass through IO commands to user space
+ *
+ * Copyright ? 2008-2010 coresystems GmbH <info at coresystems.de>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define DIRECTHW_VERSION "1.3"
+#define DIRECTHW_VERNUM 0x00100300
+
+/* */
+
+class DirectHWService:public IOService {
+	OSDeclareDefaultStructors(DirectHWService)
+
+      public:
+	virtual bool start(IOService * provider);
+
+};
+
+
+/* */
+
+class DirectHWService;
+
+class DirectHWUserClient:public IOUserClient {
+	OSDeclareDefaultStructors(DirectHWUserClient)
+
+	enum {
+		kReadIO,
+		kWriteIO,
+		kPrepareMap,
+		kReadMSR,
+		kWriteMSR,
+		kNumberOfMethods
+	};
+
+	typedef struct {
+		UInt32 offset;
+		UInt32 width;
+		UInt32 data;
+	} iomem_t;
+
+	typedef struct {
+		UInt64 addr;
+		UInt64 size;
+	} map_t;
+
+	typedef struct {
+		UInt32 core;
+		UInt32 index;
+		UInt32 hi;
+		UInt32 lo;
+	} msrcmd_t;
+
+      public:
+	virtual bool initWithTask(task_t task, void *securityID, UInt32 type);
+
+	virtual bool start(IOService * provider);
+	virtual void stop(IOService * provider);
+
+	virtual IOReturn clientMemoryForType(UInt32 type, UInt32 *flags, IOMemoryDescriptor **memory);
+
+	virtual IOReturn clientClose(void);
+
+      protected:
+	DirectHWService * fProvider;
+
+	static const IOExternalMethod fMethods[kNumberOfMethods];
+
+	virtual IOExternalMethod * getTargetAndMethodForIndex(IOService ** target, UInt32 index);
+
+	virtual IOReturn ReadIO(iomem_t * inStruct, iomem_t * outStruct,
+				 IOByteCount inStructSize,
+				 IOByteCount * outStructSize);
+
+	virtual IOReturn WriteIO(iomem_t * inStruct, iomem_t * outStruct,
+				  IOByteCount inStructSize,
+				  IOByteCount * outStructSize);
+
+	virtual IOReturn PrepareMap(map_t * inStruct, map_t * outStruct,
+				  IOByteCount inStructSize,
+				  IOByteCount * outStructSize);
+
+	virtual IOReturn ReadMSR(msrcmd_t * inStruct, msrcmd_t * outStruct,
+				  IOByteCount inStructSize,
+				  IOByteCount * outStructSize);
+
+	virtual IOReturn WriteMSR(msrcmd_t * inStruct, msrcmd_t * outStruct,
+				  IOByteCount inStructSize,
+				  IOByteCount * outStructSize);
+
+      private:
+	task_t fTask;
+	UInt64 LastMapAddr, LastMapSize;
+
+	static void MSRHelperFunction(void *data);
+	typedef struct { msrcmd_t *in, *out; bool Read; } MSRHelper;
+	static inline void cpuid(uint32_t op1, uint32_t op2, uint32_t *data);
+};
+
+extern "C" {
+
+/* from sys/osfmk/i386/mp.c */
+
+extern void mp_rendezvous(
+	void (*setup_func)(void *),
+	void (*action_func)(void *),
+	void (*teardown_func)(void *),
+	void *arg);
+
+extern int cpu_number(void);
+
+}
+
+#define INVALID_MSR_LO 0x63744857
+#define INVALID_MSR_HI 0x44697265

Added: trunk/macosx/DirectHW/DirectHW.pmdoc/01directhw-contents.xml
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW.pmdoc/01directhw-contents.xml	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,85 @@
+<pkg-contents spec="1.12">
+    <f n="DirectHW" o="root" g="wheel" p="16877" x="true" pt="build/DirectHW" m="true" t="file">
+        <f n="System" o="root" g="wheel" p="16877">
+            <f n="Library" o="root" g="wheel" p="16877">
+                <f n="Extensions" o="root" g="wheel" p="16877">
+                    <f n="DirectHW.kext" o="root" g="wheel" p="16877">
+                        <f n="Contents" o="root" g="wheel" p="16877">
+                            <f n="Info.plist" o="root" g="wheel" p="33188">
+                                <mod>mode</mod>
+                            </f>
+                            <f n="MacOS" o="root" g="wheel" p="16877">
+                                <f n="DirectHW" o="root" g="wheel" p="33188">
+                                    <mod>mode</mod>
+                                </f>
+                                <mod>mode</mod>
+                            </f>
+                            <mod>mode</mod>
+                        </f>
+                        <mod>mode</mod>
+                    </f>
+                </f>
+                <f n="Frameworks" o="root" g="wheel" p="16877">
+                    <f n="DirectHW.framework" o="root" g="wheel" p="16877">
+                        <f n="DirectHW" o="root" g="wheel" p="33261">
+                            <mod>mode</mod>
+                        </f>
+                        <f n="Headers" o="root" g="wheel" p="16877">
+                            <f n="DirectHW.h" o="root" g="wheel" p="33188">
+                                <mod>mode</mod>
+                            </f>
+                            <mod>mode</mod>
+                        </f>
+                        <f n="Resources" o="root" g="wheel" p="16877">
+                            <f n="Info.plist" o="root" g="wheel" p="33188">
+                                <mod>mode</mod>
+                            </f>
+                            <mod>mode</mod>
+                        </f>
+                        <f n="Versions" o="root" g="wheel" p="16877">
+                            <f n="A" o="root" g="wheel" p="16877">
+                                <f n="DirectHW" o="root" g="wheel" p="33261">
+                                    <mod>mode</mod>
+                                </f>
+                                <f n="Headers" o="root" g="wheel" p="16877">
+                                    <f n="DirectHW.h" o="root" g="wheel" p="33188">
+                                        <mod>mode</mod>
+                                    </f>
+                                    <mod>mode</mod>
+                                </f>
+                                <f n="Resources" o="root" g="wheel" p="16877">
+                                    <f n="Info.plist" o="root" g="wheel" p="33188">
+                                        <mod>mode</mod>
+                                    </f>
+                                    <mod>mode</mod>
+                                </f>
+                                <mod>mode</mod>
+                            </f>
+                            <f n="Current" o="root" g="wheel" p="16877">
+                                <f n="DirectHW" o="root" g="wheel" p="33261">
+                                    <mod>mode</mod>
+                                </f>
+                                <f n="Headers" o="root" g="wheel" p="16877">
+                                    <f n="DirectHW.h" o="root" g="wheel" p="33188">
+                                        <mod>mode</mod>
+                                    </f>
+                                    <mod>mode</mod>
+                                </f>
+                                <f n="Resources" o="root" g="wheel" p="16877">
+                                    <f n="Info.plist" o="root" g="wheel" p="33188">
+                                        <mod>mode</mod>
+                                    </f>
+                                    <mod>mode</mod>
+                                </f>
+                                <mod>mode</mod>
+                            </f>
+                            <mod>mode</mod>
+                        </f>
+                        <mod>mode</mod>
+                    </f>
+                </f>
+            </f>
+        </f>
+        <mod>group</mod>
+    </f>
+</pkg-contents>

Added: trunk/macosx/DirectHW/DirectHW.pmdoc/01directhw.xml
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW.pmdoc/01directhw.xml	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,29 @@
+<pkgref spec="1.12" uuid="9EEC00E4-527A-400E-A366-6F0D0ABB0D19">
+    <config>
+        <identifier>com.coresystems.directhw.DirectHW.pkg</identifier>
+        <version>1.0</version>
+        <description></description>
+        <post-install type="none"/>
+        <requireAuthorization/>
+        <installFrom relative="true" mod="true">build/DirectHW</installFrom>
+        <installTo>/</installTo>
+        <flags>
+            <followSymbolicLinks/>
+        </flags>
+        <packageStore type="internal"></packageStore>
+        <mod>installFrom.isRelativeType</mod>
+        <mod>installFrom.path</mod>
+        <mod>parent</mod>
+        <mod>installTo</mod>
+    </config>
+    <contents>
+        <file-list>01directhw-contents.xml</file-list>
+        <component id="com.coresystems.driver.DirectHW" path="build/DirectHW/System/Library/Extensions/DirectHW.kext" version="1.0"/>
+        <component id="com.coresystems.DirectHW" path="build/DirectHW/System/Library/Frameworks/DirectHW.framework" version="1.0"/>
+        <filter>/CVS$</filter>
+        <filter>/\.svn$</filter>
+        <filter>/\.cvsignore$</filter>
+        <filter>/\.cvspass$</filter>
+        <filter>/\.DS_Store$</filter>
+    </contents>
+</pkgref>

Added: trunk/macosx/DirectHW/DirectHW.pmdoc/index.xml
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW.pmdoc/index.xml	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,58 @@
+<pkmkdoc spec="1.12">
+    <properties>
+        <title>DirectHW</title>
+        <build>DirectHW.pkg</build>
+        <organization>com.coresystems</organization>
+        <userSees ui="easy"/>
+        <min-target os="3"/>
+        <domain system="true"/>
+    </properties>
+    <distribution>
+        <versions min-spec="1.000000"/>
+        <scripts>
+	    function CheckHardwareCompatibility() {
+                if (system.sysctl('hw.machine') == 'i386') {
+                    return true;
+                }
+            
+                if (system.sysctl('hw.machine') == 'x86_64') {
+                    return true;
+                }
+            
+                return false;
+            }
+        </scripts>
+    </distribution>
+    <contents>
+        <choice title="DirectHW" id="choice2" starts_selected="true" starts_enabled="true" starts_hidden="false">
+            <pkgref id="com.coresystems.directhw.DirectHW.pkg"/>
+        </choice>
+    </contents>
+    <resources bg-scale="none" bg-align="bottomleft">
+        <locale lang="en">
+            <resource relative="true" mod="true" type="background">installer.png</resource>
+            <resource relative="true" mod="true" type="license">Copying.rtf</resource>
+            <resource relative="true" mod="true" type="welcome">Welcome.rtf</resource>
+        </locale>
+    </resources>
+    <requirements>
+        <requirement id="java" operator="eq" value="true">
+            <argument>CheckHardwareCompatibility()</argument>
+            <message-title>Unsupported Architecture</message-title>
+            <message>DirectHW is only supported on Intel? based Apple systems.</message>
+        </requirement>
+    </requirements>
+    <flags/>
+    <postinstall>
+        <action id="com.apple.packagemaker.actions.loadkext">
+            <value>com.coresystems.driver.DirectHW</value>
+	    <type>component</type>
+        </action>
+    </postinstall>
+    <item type="file">01directhw.xml</item>
+    <mod>properties.title</mod>
+    <mod>postinstallActions.actions</mod>
+    <mod>description</mod>
+    <mod>properties.anywhereDomain</mod>
+    <mod>properties.systemDomain</mod>
+</pkmkdoc>

Added: trunk/macosx/DirectHW/DirectHW.xcodeproj/project.pbxproj
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/DirectHW.xcodeproj/project.pbxproj	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,336 @@
+// !$*UTF8*$!
+{
+	archiveVersion = 1;
+	classes = {
+	};
+	objectVersion = 44;
+	objects = {
+
+/* Begin PBXBuildFile section */
+		5D9932DD0D0F97EF00760F43 /* DirectHW.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 5D9932B30D0F95DD00760F43 /* DirectHW.cpp */; };
+		FDC4F2BC0E923E0C0006B2A5 /* DirectHW.h in Headers */ = {isa = PBXBuildFile; fileRef = FD12A6710E9235DB004BBD7B /* DirectHW.h */; settings = {ATTRIBUTES = (Public, ); }; };
+		FDC4F2BD0E923E100006B2A5 /* DirectHW.c in Sources */ = {isa = PBXBuildFile; fileRef = FD12A6700E9235DB004BBD7B /* DirectHW.c */; };
+		FDC4F2BF0E923E2B0006B2A5 /* IOKit.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = FDC4F2BE0E923E2B0006B2A5 /* IOKit.framework */; };
+/* End PBXBuildFile section */
+
+/* Begin PBXFileReference section */
+		5D9932B30D0F95DD00760F43 /* DirectHW.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = DirectHW.cpp; sourceTree = "<group>"; };
+		5D9932B40D0F95DD00760F43 /* DirectHW.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = DirectHW.hpp; sourceTree = "<group>"; };
+		5D9932D60D0F97D000760F43 /* DirectHW.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = DirectHW.kext; sourceTree = BUILT_PRODUCTS_DIR; };
+		5D9932D70D0F97D000760F43 /* DirectHW-Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = "DirectHW-Info.plist"; sourceTree = "<group>"; };
+		FD12A6700E9235DB004BBD7B /* DirectHW.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = DirectHW.c; sourceTree = "<group>"; };
+		FD12A6710E9235DB004BBD7B /* DirectHW.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = DirectHW.h; sourceTree = "<group>"; };
+		FDC4F1CB0E923CB30006B2A5 /* DirectHW-Framework-Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = "DirectHW-Framework-Info.plist"; sourceTree = "<group>"; };
+		FDC4F2B50E923DF00006B2A5 /* DirectHW.framework */ = {isa = PBXFileReference; explicitFileType = wrapper.framework; includeInIndex = 0; path = DirectHW.framework; sourceTree = BUILT_PRODUCTS_DIR; };
+		FDC4F2BE0E923E2B0006B2A5 /* IOKit.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = IOKit.framework; path = /System/Library/Frameworks/IOKit.framework; sourceTree = "<absolute>"; };
+/* End PBXFileReference section */
+
+/* Begin PBXFrameworksBuildPhase section */
+		5D9932D40D0F97D000760F43 /* Frameworks */ = {
+			isa = PBXFrameworksBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+		FDC4F2B30E923DF00006B2A5 /* Frameworks */ = {
+			isa = PBXFrameworksBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+				FDC4F2BF0E923E2B0006B2A5 /* IOKit.framework in Frameworks */,
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+/* End PBXFrameworksBuildPhase section */
+
+/* Begin PBXGroup section */
+		5D9932890D0F94EE00760F43 = {
+			isa = PBXGroup;
+			children = (
+				FDC4F2BE0E923E2B0006B2A5 /* IOKit.framework */,
+				5D9932940D0F94F500760F43 /* Source */,
+				5D99329C0D0F952400760F43 /* Products */,
+				5D9932D70D0F97D000760F43 /* DirectHW-Info.plist */,
+				FDC4F1CB0E923CB30006B2A5 /* DirectHW-Framework-Info.plist */,
+			);
+			sourceTree = "<group>";
+		};
+		5D9932940D0F94F500760F43 /* Source */ = {
+			isa = PBXGroup;
+			children = (
+				FD12A6700E9235DB004BBD7B /* DirectHW.c */,
+				FD12A6710E9235DB004BBD7B /* DirectHW.h */,
+				5D9932B30D0F95DD00760F43 /* DirectHW.cpp */,
+				5D9932B40D0F95DD00760F43 /* DirectHW.hpp */,
+			);
+			name = Source;
+			sourceTree = "<group>";
+		};
+		5D99329C0D0F952400760F43 /* Products */ = {
+			isa = PBXGroup;
+			children = (
+				5D9932D60D0F97D000760F43 /* DirectHW.kext */,
+				FDC4F2B50E923DF00006B2A5 /* DirectHW.framework */,
+			);
+			name = Products;
+			sourceTree = "<group>";
+		};
+/* End PBXGroup section */
+
+/* Begin PBXHeadersBuildPhase section */
+		FDC4F2B00E923DF00006B2A5 /* Headers */ = {
+			isa = PBXHeadersBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+				FDC4F2BC0E923E0C0006B2A5 /* DirectHW.h in Headers */,
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+/* End PBXHeadersBuildPhase section */
+
+/* Begin PBXNativeTarget section */
+		5D9932D50D0F97D000760F43 /* KEXT */ = {
+			isa = PBXNativeTarget;
+			buildConfigurationList = 5D9932DB0D0F97D100760F43 /* Build configuration list for PBXNativeTarget "KEXT" */;
+			buildPhases = (
+				5D9932D20D0F97D000760F43 /* Sources */,
+				5D9932D30D0F97D000760F43 /* Resources */,
+				5D9932D40D0F97D000760F43 /* Frameworks */,
+			);
+			buildRules = (
+			);
+			dependencies = (
+			);
+			name = KEXT;
+			productName = DirectHW;
+			productReference = 5D9932D60D0F97D000760F43 /* DirectHW.kext */;
+			productType = "com.apple.product-type.kernel-extension.iokit";
+		};
+		FDC4F2B40E923DF00006B2A5 /* DirectHW */ = {
+			isa = PBXNativeTarget;
+			buildConfigurationList = FDC4F2C00E923E2B0006B2A5 /* Build configuration list for PBXNativeTarget "DirectHW" */;
+			buildPhases = (
+				FDC4F2B00E923DF00006B2A5 /* Headers */,
+				FDC4F2B10E923DF00006B2A5 /* Resources */,
+				FDC4F2B20E923DF00006B2A5 /* Sources */,
+				FDC4F2B30E923DF00006B2A5 /* Frameworks */,
+			);
+			buildRules = (
+			);
+			dependencies = (
+			);
+			name = DirectHW;
+			productName = DirectHW;
+			productReference = FDC4F2B50E923DF00006B2A5 /* DirectHW.framework */;
+			productType = "com.apple.product-type.framework";
+		};
+/* End PBXNativeTarget section */
+
+/* Begin PBXProject section */
+		5D99328B0D0F94EE00760F43 /* Project object */ = {
+			isa = PBXProject;
+			buildConfigurationList = 5D99328E0D0F94EE00760F43 /* Build configuration list for PBXProject "DirectHW" */;
+			compatibilityVersion = "Xcode 3.0";
+			hasScannedForEncodings = 0;
+			mainGroup = 5D9932890D0F94EE00760F43;
+			productRefGroup = 5D99329C0D0F952400760F43 /* Products */;
+			projectDirPath = "";
+			projectRoot = "";
+			targets = (
+				5D9932D50D0F97D000760F43 /* KEXT */,
+				FDC4F2B40E923DF00006B2A5 /* DirectHW */,
+			);
+		};
+/* End PBXProject section */
+
+/* Begin PBXResourcesBuildPhase section */
+		5D9932D30D0F97D000760F43 /* Resources */ = {
+			isa = PBXResourcesBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+		FDC4F2B10E923DF00006B2A5 /* Resources */ = {
+			isa = PBXResourcesBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+/* End PBXResourcesBuildPhase section */
+
+/* Begin PBXSourcesBuildPhase section */
+		5D9932D20D0F97D000760F43 /* Sources */ = {
+			isa = PBXSourcesBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+				5D9932DD0D0F97EF00760F43 /* DirectHW.cpp in Sources */,
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+		FDC4F2B20E923DF00006B2A5 /* Sources */ = {
+			isa = PBXSourcesBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+				FDC4F2BD0E923E100006B2A5 /* DirectHW.c in Sources */,
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+/* End PBXSourcesBuildPhase section */
+
+/* Begin XCBuildConfiguration section */
+		5D99328C0D0F94EE00760F43 /* Debug */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				COPY_PHASE_STRIP = YES;
+				MACOSX_DEPLOYMENT_TARGET = 10.4;
+				STRIPFLAGS = "-no_uuid";
+			};
+			name = Debug;
+		};
+		5D99328D0D0F94EE00760F43 /* Release */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				COPY_PHASE_STRIP = YES;
+				MACOSX_DEPLOYMENT_TARGET = 10.4;
+				STRIPFLAGS = "-no_uuid";
+			};
+			name = Release;
+		};
+		5D9932D90D0F97D100760F43 /* Debug */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				ARCHS = (
+					x86_64,
+					i386,
+				);
+				COPY_PHASE_STRIP = NO;
+				GCC_DYNAMIC_NO_PIC = NO;
+				GCC_ENABLE_FIX_AND_CONTINUE = NO;
+				GCC_MODEL_TUNING = G5;
+				GCC_OPTIMIZATION_LEVEL = 0;
+				INFOPLIST_FILE = "DirectHW-Info.plist";
+				INSTALL_GROUP = wheel;
+				INSTALL_OWNER = root;
+				INSTALL_PATH = "$(SYSTEM_LIBRARY_DIR)/Extensions";
+				MODULE_NAME = com.coresystems.driver.DirectHW;
+				MODULE_VERSION = 1.0;
+				PREBINDING = NO;
+				PRODUCT_NAME = DirectHW;
+				VALID_ARCHS = "i386 x86_64";
+				WRAPPER_EXTENSION = kext;
+				ZERO_LINK = NO;
+			};
+			name = Debug;
+		};
+		5D9932DA0D0F97D100760F43 /* Release */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				ARCHS = (
+					x86_64,
+					i386,
+				);
+				COPY_PHASE_STRIP = YES;
+				DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym";
+				GCC_ENABLE_FIX_AND_CONTINUE = NO;
+				GCC_MODEL_TUNING = G5;
+				INFOPLIST_FILE = "DirectHW-Info.plist";
+				INSTALL_GROUP = wheel;
+				INSTALL_OWNER = root;
+				INSTALL_PATH = "$(SYSTEM_LIBRARY_DIR)/Extensions";
+				MODULE_NAME = com.coresystems.driver.DirectHW;
+				MODULE_VERSION = 1.0;
+				PREBINDING = NO;
+				PRODUCT_NAME = DirectHW;
+				VALID_ARCHS = "i386 x86_64";
+				WRAPPER_EXTENSION = kext;
+				ZERO_LINK = NO;
+			};
+			name = Release;
+		};
+		FDC4F2B60E923DF00006B2A5 /* Debug */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				ARCHS = (
+					x86_64,
+					i386,
+				);
+				COPY_PHASE_STRIP = NO;
+				DYLIB_COMPATIBILITY_VERSION = 1;
+				DYLIB_CURRENT_VERSION = 1;
+				FRAMEWORK_VERSION = A;
+				GCC_DYNAMIC_NO_PIC = NO;
+				GCC_ENABLE_FIX_AND_CONTINUE = YES;
+				GCC_MODEL_TUNING = G5;
+				GCC_OPTIMIZATION_LEVEL = 0;
+				GCC_PRECOMPILE_PREFIX_HEADER = YES;
+				INFOPLIST_FILE = "DirectHW-Framework-Info.plist";
+				INSTALL_PATH = "$(SYSTEM_LIBRARY_DIR)/Frameworks";
+				OTHER_LDFLAGS = "";
+				PREBINDING = NO;
+				PRODUCT_NAME = DirectHW;
+				VALID_ARCHS = "i386 x86_64";
+				ZERO_LINK = YES;
+			};
+			name = Debug;
+		};
+		FDC4F2B70E923DF00006B2A5 /* Release */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				ARCHS = (
+					x86_64,
+					i386,
+				);
+				COPY_PHASE_STRIP = NO;
+				DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym";
+				DYLIB_COMPATIBILITY_VERSION = 1;
+				DYLIB_CURRENT_VERSION = 1;
+				FRAMEWORK_VERSION = A;
+				GCC_ENABLE_FIX_AND_CONTINUE = NO;
+				GCC_MODEL_TUNING = G5;
+				GCC_PRECOMPILE_PREFIX_HEADER = YES;
+				INFOPLIST_FILE = "DirectHW-Framework-Info.plist";
+				INSTALL_PATH = "$(SYSTEM_LIBRARY_DIR)/Frameworks";
+				OTHER_LDFLAGS = "";
+				PREBINDING = NO;
+				PRODUCT_NAME = DirectHW;
+				VALID_ARCHS = "i386 x86_64";
+				ZERO_LINK = NO;
+			};
+			name = Release;
+		};
+/* End XCBuildConfiguration section */
+
+/* Begin XCConfigurationList section */
+		5D99328E0D0F94EE00760F43 /* Build configuration list for PBXProject "DirectHW" */ = {
+			isa = XCConfigurationList;
+			buildConfigurations = (
+				5D99328C0D0F94EE00760F43 /* Debug */,
+				5D99328D0D0F94EE00760F43 /* Release */,
+			);
+			defaultConfigurationIsVisible = 0;
+			defaultConfigurationName = Release;
+		};
+		5D9932DB0D0F97D100760F43 /* Build configuration list for PBXNativeTarget "KEXT" */ = {
+			isa = XCConfigurationList;
+			buildConfigurations = (
+				5D9932D90D0F97D100760F43 /* Debug */,
+				5D9932DA0D0F97D100760F43 /* Release */,
+			);
+			defaultConfigurationIsVisible = 0;
+			defaultConfigurationName = Release;
+		};
+		FDC4F2C00E923E2B0006B2A5 /* Build configuration list for PBXNativeTarget "DirectHW" */ = {
+			isa = XCConfigurationList;
+			buildConfigurations = (
+				FDC4F2B60E923DF00006B2A5 /* Debug */,
+				FDC4F2B70E923DF00006B2A5 /* Release */,
+			);
+			defaultConfigurationIsVisible = 0;
+			defaultConfigurationName = Release;
+		};
+/* End XCConfigurationList section */
+	};
+	rootObject = 5D99328B0D0F94EE00760F43 /* Project object */;
+}

Added: trunk/macosx/DirectHW/Makefile
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/Makefile	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,68 @@
+#
+# DirectHW - Kernel extension to pass through IO commands to user space
+#
+# Copyright ? 2008-2010 coresystems GmbH <info at coresystems.de>
+#
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+#
+
+all: dmg
+
+prepare:
+	if [ ! -r .patched ]; then \
+		test `uname -r  | cut -f1 -d\.` -lt 10 && \
+			patch -p0 < DirectHW-i386-only.diff || echo "Not patching."; \
+	fi
+	touch .patched
+
+build: prepare
+	xcodebuild -alltargets
+
+install: build
+	sudo xcodebuild -alltargets DSTROOT=`pwd`/build/DirectHW install
+
+package: install
+	/Developer/usr/bin/packagemaker -v --doc DirectHW.pmdoc \
+		--id com.coresystems.DirectHW --out build/DirectHW.pkg
+
+dmg: package
+	rm -rf DirectHW.dmg
+	rm -rf out
+	mkdir out
+	cp -r build/DirectHW.pkg out/Install\ DirectHW.pkg
+	cp -r ReadMe.rtf out/Read\ Me.rtf
+	/Developer/Tools/SetFile -a E out/Install\ DirectHW.pkg
+	/Developer/Tools/SetFile -a E out/Read\ Me.rtf
+	../create-dmg/create-dmg --window-size 447 337 \
+		--background background.png --icon-size 80 \
+		--volname "Install DirectHW" \
+		--icon "Install DirectHW.pkg" 142 64 \
+		--icon "Read Me.rtf" 310 64 \
+		DirectHW.dmg out
+
+load: install
+	cd build/DirectHW/System/Library/Extensions; sudo kextunload -v DirectHW.kext; sudo kextload -v DirectHW.kext
+
+installer: package
+	rm -rf ~/Desktop/DirectHW.pkg
+	cp -r build/DirectHW.pkg ~/Desktop
+
+clean:
+	sudo rm -rf build/Release build/DirectHW.build build/DirectHW build/DirectHW.pkg
+	rm -rf out
+
+distclean:
+	rm DirectHW.dmg
+
+.PHONY: prepare build install package dmg load copy clean distclean
+

Added: trunk/macosx/DirectHW/ReadMe.rtf
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/ReadMe.rtf	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,116 @@
+{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320
+{\fonttbl\f0\fswiss\fcharset0 ArialMT;\f1\fnil\fcharset0 Monaco;}
+{\colortbl;\red255\green255\blue255;}
+\paperw11900\paperh16840\margl1440\margr1440\vieww10800\viewh9120\viewkind0
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+
+\f0\b\fs24 \cf0 Welcome to DirectHW by coresystems GmbH\
+
+\b0 \
+
+\b ABOUT\
+
+\b0 \
+DirectHW is a software compatibility layer for Mac OS X. It provides a kernel driver and framework that emulates the most commonly used hardware access functions on x86 machines, such as:\
+\
+	\'95	iopl\
+	\'95	inb, inw, inl, outb, outw, outl\
+	\'95	rdmsr, wrmsr\
+	\'95	mmap() of physical address space\
+\
+This package was originally intended to get the coreboot\'ae utilities running on Mac OS X. But you're encouraged to use it for many more opportunities.\
+\
+Visit {\field{\*\fldinst{HYPERLINK "http://www.coresystems.de/"}}{\fldrslt http://www.coresystems.de/}} for more information.\
+\
+\
+
+\b LICENSE\
+
+\b0 \
+DirectHW is Copyright \'a9 2008-2010 coresystems GmbH <{\field{\*\fldinst{HYPERLINK "mailto:info at coresystems.de"}}{\fldrslt info at coresystems.de}}>\
+\
+Permission to use, copy, modify, and/or distribute this software for any\
+purpose with or without fee is hereby granted, provided that the above\
+copyright notice and this permission notice appear in all copies.\
+\
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\
+\
+coreboot\'ae is a registered trademark of coresystems GmbH\
+\
+
+\b CHANGELOG\
+
+\b0 \
+
+\itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrt\brdrnil \trbrdrl\brdrnil \trbrdrr\brdrnil 
+\clvertalc \clshdrawnil \clwWidth1460\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx2880
+\clvertalc \clshdrawnil \clwWidth560\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx5760
+\clvertalc \clshdrawnil \clwWidth8120\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx8640
+\pard\intbl\itap1\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+\cf0 2010/10/20\
+\cell 
+\pard\intbl\itap1\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+\cf0 v1.3\
+\cell 
+\pard\intbl\itap1\tx220\tx720\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\li720\fi-720\ql\qnatural\pardirnatural
+\cf0 - Implement SMP capable MSR handling\
+- Fix 32bit/64bit user space/kernel space\cell \row
+
+\itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil 
+\clvertalc \clshdrawnil \clwWidth1460\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx2880
+\clvertalc \clshdrawnil \clwWidth560\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx5760
+\clvertalc \clshdrawnil \clwWidth8120\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx8640
+\pard\intbl\itap1\tx220\tx720\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\li720\fi-720\ql\qnatural\pardirnatural
+\cf0 2010/10/18\
+\
+\cell 
+\pard\intbl\itap1\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+\cf0 v1.2\
+\
+\cell 
+\pard\intbl\itap1\tx220\tx720\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\li720\fi-720\ql\qnatural\pardirnatural
+\cf0 - Rename to DirectHW\
+- Fix memory mapping return values\
+- Security fix, kept now checks for admin priviledges\cell \row
+
+\itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil 
+\clvertalc \clshdrawnil \clwWidth1460\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx2880
+\clvertalc \clshdrawnil \clwWidth560\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx5760
+\clvertalc \clshdrawnil \clwWidth8120\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx8640
+\pard\intbl\itap1\tx220\tx720\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\li720\fi-720\ql\qnatural\pardirnatural
+\cf0 2009/08/30\cell 
+\pard\intbl\itap1\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+\cf0 v1.1\cell 
+\pard\intbl\itap1\tx220\tx720\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\li720\fi-720\ql\qnatural\pardirnatural
+\cf0 - Update for 64bit Mac OS X 10.6 (Snow Leopard)\cell \row
+
+\itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrt\brdrnil \trbrdrr\brdrnil 
+\clvertalc \clshdrawnil \clwWidth1460\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx2880
+\clvertalc \clshdrawnil \clwWidth560\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx5760
+\clvertalc \clshdrawnil \clwWidth8120\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf1 \clbrdrl\brdrs\brdrw20\brdrcf1 \clbrdrb\brdrs\brdrw20\brdrcf1 \clbrdrr\brdrs\brdrw20\brdrcf1 \clpadl100 \clpadr100 \gaph\cellx8640
+\pard\intbl\itap1\tx220\tx720\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\li720\fi-720\ql\qnatural\pardirnatural
+\cf0 2008/11/16\cell 
+\pard\intbl\itap1\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+\cf0 v1.0\cell 
+\pard\intbl\itap1\tx220\tx720\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\li720\fi-720\ql\qnatural\pardirnatural
+\cf0 - Initial version\cell \lastrow\row
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+\cf0 \
+\
+
+\b CONTACT\
+
+\b0 \
+Please contact us at <{\field{\*\fldinst{HYPERLINK "mailto:info at coresystems.de"}}{\fldrslt info at coresystems.de}}>.\
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+
+\f1\fs20 \cf0 \
+\
+\
+}
\ No newline at end of file

Added: trunk/macosx/DirectHW/Welcome.rtf
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/DirectHW/Welcome.rtf	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,33 @@
+{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320
+{\fonttbl\f0\fnil\fcharset0 LucidaGrande;}
+{\colortbl;\red255\green255\blue255;\red128\green128\blue128;\red100\green100\blue100;}
+{\*\listtable{\list\listtemplateid1\listhybrid{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace360\levelindent0{\*\levelmarker \{disc\}}{\leveltext\leveltemplateid1\'01\uc0\u8226 ;}{\levelnumbers;}\fi-360\li720\lin720 }{\listname ;}\listid1}}
+{\*\listoverridetable{\listoverride\listid1\listoverridecount0\ls1}}
+\paperw11900\paperh16840\margl1440\margr1440\vieww9000\viewh8400\viewkind0
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+
+\f0\b\fs26 \cf2 Welcome to DirectHW by coresystems GmbH\
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\sl120\slmult1\ql\qnatural\pardirnatural
+
+\b0 \cf2 \
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+\cf2 DirectHW is a software compatibility layer for Mac OS X. It provides a kernel driver and framework that emulates the most commonly used hardware access functions on x86 machines, such as:\
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\sl120\slmult1\ql\qnatural\pardirnatural
+\cf2 \
+\pard\tx220\tx720\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\li720\fi-720\ql\qnatural\pardirnatural
+\ls1\ilvl0\cf2 {\listtext	\'95	}iopl\
+{\listtext	\'95	}inb, inw, inl, outb, outw, outl\
+{\listtext	\'95	}rdmsr, wrmsr\
+{\listtext	\'95	}mmap() of physical address space\
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\sl120\slmult1\ql\qnatural\pardirnatural
+\cf2 \
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+\cf2 This package was originally intended to get the coreboot\'ae utilities running on Mac OS X. But you're encouraged to use it for many more opportunities.\
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\sl120\slmult1\ql\qnatural\pardirnatural
+\cf2 \
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+\cf2 Visit {\field{\*\fldinst{HYPERLINK "http://www.coresystems.de/"}}{\fldrslt \cf3 http://www.coresystems.de/}} for more information.\
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\sl120\slmult1\ql\qnatural\pardirnatural
+\cf2 \
+\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
+\cf2 You will now be guided through the steps necessary to install this software.}
\ No newline at end of file

Added: trunk/macosx/DirectHW/background.png
==============================================================================
Binary file. No diff available.

Added: trunk/macosx/DirectHW/installer.png
==============================================================================
Binary file. No diff available.

Added: trunk/macosx/Makefile
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/Makefile	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,47 @@
+all:
+	@echo "make directhw	-	builds DirectHW dmg."
+	@echo "make pciutils	-	builds pciutils dmg."
+	#@echo "make tools	-	builds coreboot utilities dmg."
+	@echo "make clean	-	clean up."
+
+PCIUTILS=pciutils-3.1.7
+
+directhw:
+	$(MAKE) -C DirectHW
+
+pciutils:
+	rm -rf $(PCIUTILS)
+	wget ftp://ftp.kernel.org/pub/software/utils/pciutils/$(PCIUTILS).tar.bz2
+	tar xvjf $(PCIUTILS).tar.bz2
+	patch -p0 < patches/$(PCIUTILS).diff
+	cd $(PCIUTILS); \
+	make OPT="-O2 -arch i386 -arch x86_64" LDFLAGS="-arch i386 -arch x86_64" IDSDIR=/usr/share; \
+	make install DESTDIR=$(shell pwd)/$(PCIUTILS)/root PREFIX=/usr ; \
+	make install-lib DESTDIR=$(shell pwd)/$(PCIUTILS)/root PREFIX=/usr ; \
+	/Developer/usr/bin/packagemaker -v --doc $(shell pwd)/$(PCIUTILS)/osx/pciutils.pmdoc --id com.pciutils --out pciutils.pkg
+	rm -rf $(PCIUTILS).dmg
+	rm -rf out
+	mkdir out
+	cp -r $(PCIUTILS)/pciutils.pkg out/Install\ PCI\ Utilities.pkg
+	cp -r $(PCIUTILS)/osx/Welcome.rtf out/Read\ Me.rtf
+	/Developer/Tools/SetFile -a E out/Install\ PCI\ Utilities.pkg
+	/Developer/Tools/SetFile -a E out/Read\ Me.rtf
+	./create-dmg/create-dmg --window-size 447 337 --background \
+	DirectHW/background.png --icon-size 80 \
+	--volname "Install PCI Utilities" \
+	--icon "Install PCI Utilities.pkg" 142 64 \
+	--icon "Read Me.rtf" 310 64 $(PCIUTILS).dmg out
+
+#tools: 
+#	$(MAKE) -C tools
+
+#patches:
+#	$(MAKE) -C upstream
+
+clean:
+	#cd $(PCIUTILS); make clean; rm -rf pciutils.pkg; rm -rf root
+	#cd tools; make clean
+	cd DirectHW; make clean
+
+.PHONY: all directhw pciutils tools patches clean
+

Added: trunk/macosx/create-dmg/create-dmg
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/create-dmg/create-dmg	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,169 @@
+#! /bin/bash
+
+# Create a read-only disk image of the contents of a folder
+#
+# Usage: make-diskimage <image_file>
+#                       <src_folder>
+#                       <volume_name>
+#                       <applescript>
+#                       <artpath>
+#                       <eula_resource_file>
+
+set -e;
+
+function pure_version() {
+  echo '1.0.0.2'
+}
+
+function version() {
+  echo "create-dmg $(pure_version)"
+}
+
+function usage() {
+  version
+  echo "Creates a fancy DMG file."
+  echo "Usage:  $(basename $0) options... image.dmg source_folder"
+  echo "All contents of source_folder will be copied into the disk image."
+  echo "Options:"
+  echo "  --volname name"
+  echo "      set volume name (displayed in the Finder sidebar and window title)"
+  echo "  --background pic.png"
+  echo "      set folder background image (provide png, gif, jpg)"
+  echo "  --window-pos x y"
+  echo "      set position the folder window"
+  echo "  --window-size width height"
+  echo "      set size of the folder window"
+  echo "  --icon-size icon_size"
+  echo "      set window icons size (up to 128)"
+  echo "  --icon file_name x y"
+  echo "      set position of the file's icon"
+  echo "  --custom-icon file_name custom_icon_or_sample_file x y"
+  echo "      set position and custom icon"
+  echo "  --version         show tool version number"
+  echo "  -h, --help        display this help"
+  exit 0
+}
+
+WINX=10
+WINY=60
+WINW=600
+WINH=400
+ICON_SIZE=128
+
+while test "${1:0:1}" = "-"; do
+  case $1 in
+    --volname)
+      VOLUME_NAME="$2"
+      shift; shift;;
+    --background)
+      BACKGROUND_FILE="$2"
+      BACKGROUND_FILE_NAME="$(basename $BACKGROUND_FILE)"
+      BACKGROUND_CLAUSE="set background picture of opts to file \".background:$BACKGROUND_FILE_NAME\""
+      shift; shift;;
+    --icon-size)
+      ICON_SIZE="$2"
+      shift; shift;;
+    --window-pos)
+      WINX=$2; WINY=$3
+      shift; shift; shift;;
+    --window-size)
+      WINW=$2; WINH=$3
+      shift; shift; shift;;
+    --icon)
+      POSITION_CLAUSE="${POSITION_CLAUSE}set position of item \"$2\" to {$3, $4}
+"
+      echo $POSITION_CLAUSE
+      shift; shift; shift; shift;;
+    --custom-icon)
+      shift; shift; shift; shift; shift;;
+    -h | --help)
+      usage;;
+    --version)
+      version; exit 0;;
+    --pure-version)
+      pure_version; exit 0;;
+    -*)
+      echo "Unknown option $1. Run with --help for help."
+      exit 1;;
+  esac
+done
+
+test -z "$2" && {
+  echo "Not enough arguments. Invoke with --help for help."
+  exit 1
+}
+
+DMG_PATH="$1"
+DMG_DIRNAME="$(dirname "$DMG_PATH")"
+DMG_DIR="$(cd $DMG_DIRNAME > /dev/null; pwd)"
+DMG_NAME="$(basename "$DMG_PATH")"
+DMG_TEMP_NAME="$DMG_DIR/rw.${DMG_NAME}"
+SRC_FOLDER="$(cd "$2" > /dev/null; pwd)"
+test -z "$VOLUME_NAME" && VOLUME_NAME="$(basename "$DMG_PATH" .dmg)"
+
+AUX_PATH="$(cd "$(dirname $0)"; pwd)/support"
+
+test -d "$AUX_PATH" || {
+  echo "Cannot find support directory: $AUX_PATH"
+  exit 1
+}
+
+# Create the image
+echo "Creating disk image..."
+test -f "${DMG_TEMP_NAME}" && rm -f "${DMG_TEMP_NAME}"
+hdiutil create -srcfolder "$SRC_FOLDER" -volname "${VOLUME_NAME}" -fs HFS+ -fsargs "-c c=64,a=16,e=16" -format UDRW -size 300m "${DMG_TEMP_NAME}"
+
+# mount it
+echo "Mounting disk image..."
+MOUNT_DIR="/Volumes/${VOLUME_NAME}"
+echo "Mount directory: $MOUNT_DIR"
+DEV_NAME=$(hdiutil attach -readwrite -noverify -noautoopen "${DMG_TEMP_NAME}" | egrep '^/dev/' | sed 1q | awk '{print $1}')
+echo "Device name:     $DEV_NAME"
+
+#cp RightDS_Store "/Volumes/${VOLUME_NAME}/.DS_Store"
+
+if ! test -z "$BACKGROUND_FILE"; then
+  echo "Copying background file..."
+  test -d "$MOUNT_DIR/.background" || mkdir "$MOUNT_DIR/.background"
+  cp "$BACKGROUND_FILE" "$MOUNT_DIR/.background/$BACKGROUND_FILE_NAME"
+fi
+
+# run applescript
+APPLESCRIPT=$(mktemp -t createdmg)
+cat "$AUX_PATH/template.applescript" | sed -e "s/WINX/$WINX/g" -e "s/WINY/$WINY/g" -e "s/WINW/$WINW/g" -e "s/WINH/$WINH/g" -e "s/BACKGROUND_CLAUSE/$BACKGROUND_CLAUSE/g" -e "s/ICON_SIZE/$ICON_SIZE/g" | perl -pe  "s/POSITION_CLAUSE/$POSITION_CLAUSE/g" >"$APPLESCRIPT"
+
+echo "Running Applescript: ./AdiumApplescriptRunner \"${APPLESCRIPT}\" process_disk_image \"${VOLUME_NAME}\""
+"$AUX_PATH/AdiumApplescriptRunner" "${APPLESCRIPT}" process_disk_image "${VOLUME_NAME}" || true
+echo "Done running the applescript..."
+sleep 4
+
+# make sure it's not world writeable
+echo "Fixing permissions..."
+chmod -Rf go-w "${MOUNT_DIR}" || true
+echo "Done fixing permissions."
+
+# make the top window open itself on mount:
+if [ -x /usr/local/bin/openUp ]; then
+    echo "Applying openUp..."
+    /usr/local/bin/openUp "${MOUNT_DIR}"
+fi
+
+# unmount
+echo "Unmounting disk image..."
+hdiutil detach "${DEV_NAME}"
+
+# compress image
+echo "Compressing disk image..."
+hdiutil convert "${DMG_TEMP_NAME}" -format UDZO -imagekey zlib-level=9 -o "${DMG_DIR}/${DMG_NAME}"
+rm -f "${DMG_TEMP_NAME}"
+
+# adding EULA resources
+if [ ! -z "${EULA_RSRC}" -a "${EULA_RSRC}" != "-null-" ]; then
+        echo "adding EULA resources"
+        hdiutil unflatten "${DMG_DIR}/${DMG_NAME}"
+        /Developer/Tools/ResMerger -a "${EULA_RSRC}" -o "${DMG_DIR}/${DMG_NAME}"
+        hdiutil flatten "${DMG_DIR}/${DMG_NAME}"
+fi
+
+echo "Disk image done"
+exit 0

Added: trunk/macosx/create-dmg/sample
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/create-dmg/sample	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,3 @@
+#! /bin/bash
+test -f test2.dmg && rm test2.dmg
+./create-dmg --window-size 500 300 --background ~/Projects/eclipse-osx-repackager/build/background.gif --icon-size 96 --volname "Hyper Foo" --icon "Applications" 380 205 --icon "Eclipse OS X Repackager" 110 205 test2.dmg /Users/andreyvit/Projects/eclipse-osx-repackager/temp/Eclipse\ OS\ X\ Repackager\ r10/

Added: trunk/macosx/create-dmg/support/AdiumApplescriptRunner
==============================================================================
Binary file. No diff available.

Added: trunk/macosx/create-dmg/support/template.applescript
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/create-dmg/support/template.applescript	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,105 @@
+on run -- for testing in script editor
+	process_disk_image("Adium X 1.0b20", "/Users/evands/adium-1.0/Release/Artwork")
+end run
+
+on process_disk_image(volumeName)
+	tell application "Finder"
+		tell disk (volumeName as string)
+			open
+			
+			set theXOrigin to WINX
+			set theYOrigin to WINY
+			set theWidth to WINW
+			set theHeight to WINH
+			
+			set theBottomRightX to (theXOrigin + theWidth)
+			set theBottomRightY to (theYOrigin + theHeight)
+			set dsStore to "\"" & "/Volumes/" & volumeName & "/" & ".DS_STORE\""
+			--			do shell script "rm " & dsStore
+			
+			tell container window
+				set current view to icon view
+				set toolbar visible to false
+				set statusbar visible to false
+				set the bounds to {theXOrigin, theYOrigin, theBottomRightX, theBottomRightY}
+				set statusbar visible to false
+			end tell
+			
+			set opts to the icon view options of container window
+			tell opts
+				set icon size to ICON_SIZE
+				set arrangement to not arranged
+			end tell
+			-- set background picture of opts to file ".background:background.png"
+			BACKGROUND_CLAUSE
+			
+			-- Positioning
+			POSITION_CLAUSE
+			-- set position of item "Adium.app" to {196, 273}
+			
+			-- Custom icons
+			-- my copyIconOfTo(artPath & "/ApplicationsIcon", "/Volumes/" & volumeName & "/Applications")
+			
+			-- Label colors
+			-- set label index of item "Adium.app" to 6
+			-- set label index of item "License.txt" to 7
+			-- set label index of item "Changes.txt" to 7
+			-- set label index of item "Applications" to 4
+			
+			update without registering applications
+			-- Force saving of the size
+      delay 1
+      
+			tell container window
+				set statusbar visible to false
+				set the bounds to {theXOrigin, theYOrigin, theBottomRightX - 10, theBottomRightY - 10}
+			end tell
+			
+			update without registering applications
+		end tell
+		
+    delay 1
+		
+		tell disk (volumeName as string)
+			tell container window
+				set statusbar visible to false
+				set the bounds to {theXOrigin, theYOrigin, theBottomRightX, theBottomRightY}
+			end tell
+			
+			update without registering applications
+	  end tell
+		
+		--give the finder some time to write the .DS_Store file
+    delay 3
+    
+		set waitTime to 0
+		set ejectMe to false
+		repeat while ejectMe is false
+			delay 1
+			set waitTime to waitTime + 1
+			
+			if (do shell script "[ -f " & dsStore & " ]; echo $?") = "0" then set ejectMe to true
+		end repeat
+		log "waited " & waitTime & " seconds for .DS_STORE to be created."
+	end tell
+end process_disk_image
+
+on copyIconOfTo(aFileOrFolderWithIcon, aFileOrFolder)
+	tell application "Finder" to set f to POSIX file aFileOrFolderWithIcon as alias
+	-- grab the file's icon
+	my CopyOrPaste(f, "c")
+	-- now the icon is in the clipboard
+	tell application "Finder" to set c to POSIX file aFileOrFolder as alias
+	my CopyOrPaste(result, "v")
+end copyIconOfTo
+
+on CopyOrPaste(i, cv)
+	tell application "Finder"
+		activate
+		open information window of i
+	end tell
+	tell application "System Events" to tell process "Finder" to tell window 1
+		keystroke tab -- select icon button
+		keystroke (cv & "w") using command down (* (copy or paste) + close window *)
+	end tell -- window 1 then process Finder then System Events
+end CopyOrPaste
\ No newline at end of file

Added: trunk/macosx/patches/dmidecode-2.9.diff
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/patches/dmidecode-2.9.diff	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,206 @@
+Index: dmidecode-2.9/config.h
+===================================================================
+--- dmidecode-2.9/config.h	(revision 122)
++++ dmidecode-2.9/config.h	(working copy)
+@@ -9,8 +9,12 @@
+ #ifdef __BEOS__
+ #define DEFAULT_MEM_DEV "/dev/misc/mem"
+ #else
++#ifdef __APPLE__
++#define DEFAULT_MEM_DEV "DirectHW"
++#else
+ #define DEFAULT_MEM_DEV "/dev/mem"
+ #endif
++#endif
+ 
+ /* Use mmap or not */
+ #ifndef __BEOS__
+Index: dmidecode-2.9/util.c
+===================================================================
+--- dmidecode-2.9/util.c	(revision 122)
++++ dmidecode-2.9/util.c	(working copy)
+@@ -47,6 +47,10 @@
+ #include "types.h"
+ #include "util.h"
+ 
++#ifdef __APPLE__
++#include <DirectHW/DirectHW.h>
++#endif
++
+ #ifndef USE_MMAP
+ static int myread(int fd, u8 *buf, size_t count, const char *prefix)
+ {
+@@ -97,6 +101,7 @@
+ void *mem_chunk(size_t base, size_t len, const char *devmem)
+ {
+ 	void *p;
++#ifndef __APPLE__
+ 	int fd;
+ #ifdef USE_MMAP
+ 	size_t mmoffset;
+@@ -160,6 +165,22 @@
+ 	
+ 	if(close(fd)==-1)
+ 		perror(devmem);
+-	
++#else
++	void *v;
++	iopl(3);
++	if((v=map_physical(base, len))==NULL)
++	{
++		perror("map_physical");
++		return NULL;
++	}
++
++	if((p=malloc(len))==NULL)
++	{
++		perror("malloc");
++		return NULL;
++	}
++	memcpy(p, v, len);
++	unmap_physical(v, len);
++#endif
+ 	return p;
+ }
+Index: dmidecode-2.9/Makefile
+===================================================================
+--- dmidecode-2.9/Makefile	(revision 122)
++++ dmidecode-2.9/Makefile	(working copy)
+@@ -21,6 +21,11 @@
+ # Pass linker flags here
+ LDFLAGS =
+ 
++OS_ARCH = $(shell uname)
++ifeq ($(OS_ARCH), Darwin)
++LDFLAGS += -framework IOKit -framework DirectHW
++endif
++
+ DESTDIR =
+ prefix  = /usr/local
+ sbindir = $(prefix)/sbin
+Index: dmidecode-2.9/biosdecode.c
+===================================================================
+--- dmidecode-2.9/biosdecode.c	(revision 122)
++++ dmidecode-2.9/biosdecode.c	(working copy)
+@@ -557,9 +557,15 @@
+ static int parse_command_line(int argc, char * const argv[])
+ {
+ 	int option;
++#ifndef __APPLE__
+ 	const char *optstring = "d:hV";
++#else
++	const char *optstring = "hV";
++#endif
+ 	struct option longopts[]={
++#ifndef __APPLE__
+ 		{ "dev-mem", required_argument, NULL, 'd' },
++#endif
+ 		{ "help", no_argument, NULL, 'h' },
+ 		{ "version", no_argument, NULL, 'V' },
+ 		{ 0, 0, 0, 0 }
+@@ -568,9 +574,11 @@
+ 	while((option=getopt_long(argc, argv, optstring, longopts, NULL))!=-1)
+ 		switch(option)
+ 		{
++#ifndef __APPLE__
+ 			case 'd':
+ 				opt.devmem=optarg;
+ 				break;
++#endif
+ 			case 'h':
+ 				opt.flags|=FLAG_HELP;
+ 				break;
+@@ -589,7 +597,9 @@
+ 	static const char *help=
+ 		"Usage: biosdecode [OPTIONS]\n"
+ 		"Options are:\n"
++#ifndef __APPLE__
+ 		" -d, --dev-mem FILE     Read memory from device FILE (default: " DEFAULT_MEM_DEV ")\n"
++#endif
+ 		" -h, --help             Display this help text and exit\n"
+ 		" -V, --version          Display the version and exit\n";
+ 	
+Index: dmidecode-2.9/vpdopt.c
+===================================================================
+--- dmidecode-2.9/vpdopt.c	(revision 122)
++++ dmidecode-2.9/vpdopt.c	(working copy)
+@@ -92,9 +92,15 @@
+ int parse_command_line(int argc, char * const argv[])
+ {
+ 	int option;
++#ifndef __APPLE__
+ 	const char *optstring = "d:hs:uV";
++#else
++	const char *optstring = "hs:uV";
++#endif
+ 	struct option longopts[]={
++#ifndef __APPLE__
+ 		{ "dev-mem", required_argument, NULL, 'd' },
++#endif
+ 		{ "help", no_argument, NULL, 'h' },
+ 		{ "string", required_argument, NULL, 's' },
+ 		{ "dump", no_argument, NULL, 'u' },
+@@ -105,9 +111,11 @@
+ 	while((option=getopt_long(argc, argv, optstring, longopts, NULL))!=-1)
+ 		switch(option)
+ 		{
++#ifndef __APPLE__
+ 			case 'd':
+ 				opt.devmem=optarg;
+ 				break;
++#endif
+ 			case 'h':
+ 				opt.flags|=FLAG_HELP;
+ 				break;
+@@ -147,7 +155,9 @@
+ 	static const char *help=
+ 		"Usage: vpddecode [OPTIONS]\n"
+ 		"Options are:\n"
++#ifndef __APPLE__
+ 		" -d, --dev-mem FILE     Read memory from device FILE (default: " DEFAULT_MEM_DEV ")\n"
++#endif
+ 		" -h, --help             Display this help text and exit\n"
+ 		" -s, --string KEYWORD   Only display the value of the given VPD string\n"
+ 		" -u, --dump             Do not decode the VPD records\n"
+Index: dmidecode-2.9/ownership.c
+===================================================================
+--- dmidecode-2.9/ownership.c	(revision 122)
++++ dmidecode-2.9/ownership.c	(working copy)
+@@ -112,9 +112,15 @@
+ static int parse_command_line(int argc, char * const argv[])
+ {
+ 	int option;
++#ifndef __APPLE__
+ 	const char *optstring = "d:hV";
++#else
++	const char *optstring = "hV";
++#endif
+ 	struct option longopts[]={
++#ifndef __APPLE__
+ 		{ "dev-mem", required_argument, NULL, 'd' },
++#endif
+ 		{ "help", no_argument, NULL, 'h' },
+ 		{ "version", no_argument, NULL, 'V' },
+ 		{ 0, 0, 0, 0 }
+@@ -123,9 +129,11 @@
+ 	while((option=getopt_long(argc, argv, optstring, longopts, NULL))!=-1)
+ 		switch(option)
+ 		{
++#ifndef __APPLE__
+ 			case 'd':
+ 				opt.devmem=optarg;
+ 				break;
++#endif
+ 			case 'h':
+ 				opt.flags|=FLAG_HELP;
+ 				break;
+@@ -144,7 +152,9 @@
+ 	static const char *help=
+ 		"Usage: ownership [OPTIONS]\n"
+ 		"Options are:\n"
++#ifndef __APPLE__
+ 		" -d, --dev-mem FILE     Read memory from device FILE (default: " DEFAULT_MEM_DEV ")\n"
++#endif
+ 		" -h, --help             Display this help text and exit\n"
+ 		" -V, --version          Display the version and exit\n";
+ 	

Added: trunk/macosx/patches/flashrom-r1280.diff
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/patches/flashrom-r1280.diff	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,41 @@
+Index: flashrom-r1280/hwaccess.h
+===================================================================
+--- flashrom-r1280/hwaccess.h
++++ flashrom-r1280/hwaccess.h
+@@ -194,7 +194,7 @@
+ #else
+ #if defined(__DARWIN__)
+     /* Header is part of the DirectHW library. */
+-    #include <DirectIO/darwinio.h>
++    #include <DirectHW/DirectHW.h>
+     #define off64_t off_t
+     #define lseek64 lseek
+ #endif
+Index: flashrom-r1280/Makefile
+===================================================================
+--- flashrom-r1280/Makefile
++++ flashrom-r1280/Makefile
+@@ -44,8 +44,8 @@
+ endif
+ ifeq ($(OS_ARCH), Darwin)
+ CPPFLAGS += -I/opt/local/include -I/usr/local/include
+-# DirectIO framework can be found in the DirectHW library.
+-LDFLAGS += -framework IOKit -framework DirectIO -L/opt/local/lib -L/usr/local/lib
++# DirectHW framework can be found in the DirectHW library.
++LDFLAGS += -framework IOKit -framework DirectHW -L/opt/local/lib -L/usr/local/lib
+ endif
+ ifeq ($(OS_ARCH), FreeBSD)
+ CPPFLAGS += -I/usr/local/include
+Index: flashrom-r1280/physmap.c
+===================================================================
+--- flashrom-r1280/physmap.c
++++ flashrom-r1280/physmap.c
+@@ -134,7 +134,7 @@
+ }
+ #elif defined(__DARWIN__)
+ 
+-#define MEM_DEV "DirectIO"
++#define MEM_DEV "DirectHW"
+ 
+ static void *sys_physmap(unsigned long phys_addr, size_t len)
+ {

Added: trunk/macosx/patches/inteltool-r6440.diff
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/patches/inteltool-r6440.diff	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,48 @@
+Index: inteltool-r6440/inteltool.h
+===================================================================
+--- inteltool-r6440/inteltool.h
++++ inteltool-r6440/inteltool.h
+@@ -26,7 +26,7 @@
+ #if (defined(__MACH__) && defined(__APPLE__))
+ /* DirectHW is available here: http://www.coresystems.de/en/directhw */
+ #define __DARWIN__
+-#include <DirectIO/darwinio.h>
++#include <DirectHW/DirectHW.h>
+ #endif
+ #include <pci/pci.h>
+ 
+@@ -111,7 +111,7 @@
+ #endif
+ typedef struct { uint16_t addr; int size; char *name; } io_register_t;
+ 
+-void *map_physical(unsigned long phys_addr, size_t len);
++void *map_physical(uint64_t phys_addr, size_t len);
+ void unmap_physical(void *virt_addr, size_t len);
+ 
+ unsigned int cpuid(unsigned int op);
+Index: inteltool-r6440/inteltool.c
+===================================================================
+--- inteltool-r6440/inteltool.c
++++ inteltool-r6440/inteltool.c
+@@ -85,7 +85,7 @@
+ #ifndef __DARWIN__
+ static int fd_mem;
+ 
+-void *map_physical(unsigned long phys_addr, size_t len)
++void *map_physical(uint64_t phys_addr, size_t len)
+ {
+ 	void *virt_addr;
+ 
+Index: inteltool-r6440/Makefile
+===================================================================
+--- inteltool-r6440/Makefile
++++ inteltool-r6440/Makefile
+@@ -31,7 +31,7 @@
+ 
+ OS_ARCH	= $(shell uname)
+ ifeq ($(OS_ARCH), Darwin)
+-LDFLAGS = -framework DirectIO -lpci -lz
++LDFLAGS = -framework DirectHW -lpci -lz
+ endif
+ ifeq ($(OS_ARCH), FreeBSD)
+ CFLAGS += -I/usr/local/include

Added: trunk/macosx/patches/msrtool-r6440.diff
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/patches/msrtool-r6440.diff	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,57 @@
+Index: msrtool-r6440/msrtool.c
+===================================================================
+--- msrtool-r6440/msrtool.c
++++ msrtool-r6440/msrtool.c
+@@ -49,7 +49,7 @@
+ 
+ static struct sysdef allsystems[] = {
+ 	{ "linux", "Linux with /dev/cpu/*/msr", linux_probe, linux_open, linux_close, linux_rdmsr },
+-	{ "darwin", "OS X with DirectIO", darwin_probe, darwin_open, darwin_close, darwin_rdmsr },
++	{ "darwin", "Mac OS X with DirectHW", darwin_probe, darwin_open, darwin_close, darwin_rdmsr },
+ 	{ "freebsd", "FreeBSD with /dev/cpuctl*", freebsd_probe, freebsd_open, freebsd_close, freebsd_rdmsr },
+ 	{ SYSTEM_EOT }
+ };
+Index: msrtool-r6440/configure
+===================================================================
+--- msrtool-r6440/configure
++++ msrtool-r6440/configure
+@@ -155,7 +155,7 @@
+ 	rm -f .config.c
+ 	exit 1
+ }
+-LDFLAGS=`trylink "libpci (from pciutils)" "${pc_LDFLAGS}" "-lpci -lz" "-L/usr/local/lib -lpci -lz" "-framework DirectIO -lpci -lz"` || {
++LDFLAGS=`trylink "libpci (from pciutils)" "${pc_LDFLAGS}" "-lpci -lz" "-L/usr/local/lib -lpci -lz" "-framework DirectHW -lpci -lz"` || {
+ 	rm -f .config.c .config.o
+ 	exit 1
+ }
+Index: msrtool-r6440/msrtool.h
+===================================================================
+--- msrtool-r6440/msrtool.h
++++ msrtool-r6440/msrtool.h
+@@ -24,9 +24,9 @@
+ #include <stdio.h>
+ #include <stdint.h>
+ #if (defined(__MACH__) && defined(__APPLE__))
+-/* DirectIO is available here: http://www.coresystems.de/en/directio */
++/* DirectHW is available here: http://www.coreboot.org/DirectHW */
+ #define __DARWIN__
+-#include <DirectIO/darwinio.h>
++#include <DirectHW/DirectHW.h>
+ #endif
+ #if defined(__FreeBSD__)
+ #include <sys/ioctl.h>
+Index: msrtool-r6440/darwin.c
+===================================================================
+--- msrtool-r6440/darwin.c
++++ msrtool-r6440/darwin.c
+@@ -26,8 +26,8 @@
+ 
+ #include "msrtool.h"
+ 
+-/* This Darwin support requires DirectIO, which is available at
+- * http://www.coresystems.de/en/directio
++/* This Darwin support requires DirectHW, which is available at
++ * http://www.coreboot.org/DirectHW
+  */
+ 
+ int darwin_probe(const struct sysdef *system)

Added: trunk/macosx/patches/nvramtool-r6440.diff
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/patches/nvramtool-r6440.diff	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,26 @@
+Index: nvramtool-r6440/accessors/cmos-hw-unix.c
+===================================================================
+--- nvramtool-r6440/accessors/cmos-hw-unix.c
++++ nvramtool-r6440/accessors/cmos-hw-unix.c
+@@ -15,7 +15,7 @@
+ #include <sys/io.h>
+ #endif
+ #if (defined(__MACH__) && defined(__APPLE__))
+-#include <DirectIO/darwinio.h>
++#include <DirectHW/DirectHW.h>
+ #endif
+ #if defined(__NetBSD__)
+ #if defined(__i386__) || defined(__x86_64__) 
+Index: nvramtool-r6440/Makefile
+===================================================================
+--- nvramtool-r6440/Makefile
++++ nvramtool-r6440/Makefile
+@@ -37,7 +37,7 @@
+ 
+ OS_ARCH        = $(shell uname)
+ ifeq ($(OS_ARCH), Darwin)
+-LDFLAGS = -framework DirectIO
++LDFLAGS = -framework DirectHW
+ endif
+ ifeq ($(OS_ARCH), NetBSD)
+ LDFLAGS = -l$(shell uname -p)

Added: trunk/macosx/patches/pciutils-3.1.7.diff
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/patches/pciutils-3.1.7.diff	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,189 @@
+Index: pciutils-3.1.7/osx/Welcome.rtf
+===================================================================
+--- pciutils-3.1.7/osx/Welcome.rtf
++++ pciutils-3.1.7/osx/Welcome.rtf
+@@ -0,0 +1,20 @@
++{\rtf1\ansi\ansicpg1252\cocoartf949\cocoasubrtf540
++{\fonttbl\f0\fnil\fcharset0 LucidaGrande;}
++{\colortbl;\red255\green255\blue255;\red128\green128\blue128;}
++\paperw11900\paperh16840\margl1440\margr1440\vieww9000\viewh8400\viewkind0
++\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
++
++\f0\b\fs26 \cf2 Welcome to PCI Utilities\
++\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\sl120\slmult1\ql\qnatural\pardirnatural
++
++\b0 \cf2 \
++\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural
++\cf2 This package contains the PCI Utilities, version 3.1.7.\
++\
++Copyright (c) 1997--2010 Martin Mares <mj at ucw.cz>\
++\
++The PCI Utilities package contains a library for portable access to PCI bus configuration registers and several utilities based on this library.\
++\
++You also might want to look at the pciutils web page containing release notes and other news: http://mj.ucw.cz/pciutils.shtml .\
++\
++You will now be guided through the steps necessary to install this software.}
+Index: pciutils-3.1.7/osx/pciutils.pmdoc/01root.xml
+===================================================================
+--- pciutils-3.1.7/osx/pciutils.pmdoc/01root.xml
++++ pciutils-3.1.7/osx/pciutils.pmdoc/01root.xml
+@@ -0,0 +1,24 @@
++<pkgref spec="1.12" uuid="94522C23-7BEF-4761-8AA3-4FE2E2784DB7">
++    <config>
++        <identifier>com.pciutils.pciutils.pkg</identifier>
++	<version>1</version>
++	<description></description>
++	<post-install type="none"/>
++        <requireAuthorization/>
++        <installFrom relative="true" mod="true">../root/</installFrom>
++        <flags>
++            <followSymbolicLinks/>
++        </flags>
++        <packageStore type="internal"></packageStore>
++	<mod>parent</mod>
++	<mod>installFrom.path</mod>
++	<mod>identifier</mod>
++    </config>
++    <contents>
++	<filter>/CVS$</filter>
++	<filter>/\.svn$</filter>
++	<filter>/\.cvsignore$</filter>
++	<filter>/\.cvspass$</filter>
++	<filter>/\.DS_Store$</filter>
++    </contents>
++</pkgref>
+Index: pciutils-3.1.7/osx/pciutils.pmdoc/index.xml
+===================================================================
+--- pciutils-3.1.7/osx/pciutils.pmdoc/index.xml
++++ pciutils-3.1.7/osx/pciutils.pmdoc/index.xml
+@@ -0,0 +1,53 @@
++<pkmkdoc spec="1.12">
++    <properties>
++        <title>PCI Utilities</title>
++	<build>pciutils.pkg</build>
++	<organization>com.pciutils</organization>
++	<userSees ui="easy"/>
++        <min-target os="2"/>
++        <domain system="true"/>
++    </properties>
++    <distribution>
++        <versions min-spec="1.000000"/><scripts>
++            function CheckHardwareCompatibility() {
++            if (system.sysctl('hw.machine') == 'i386') {
++            return true;
++            }
++            
++            if (system.sysctl('hw.machine') == 'x86_64') {
++            return true;
++            }
++            
++            return false;
++            }
++        </scripts>
++    </distribution>
++    <description>The PCI Utilities package contains a library for portable access to PCI bus configuration registers and several utilities based on this library.
++    </description>
++    <contents>
++        <choice title="PCI Utilities" id="choice0" starts_selected="true" starts_enabled="true" starts_hidden="false">
++            <pkgref id="com.pciutils.pciutils.pkg"/>
++        </choice>
++    </contents>
++    <resources bg-scale="none" bg-align="bottomleft">
++        <locale lang="en">
++	    <resource relative="true" mod="true" type="license">../COPYING</resource>
++	    <resource relative="true" mod="true" type="welcome">Welcome.rtf</resource>
++        </locale>
++    </resources>
++    <requirements>
++        <requirement id="java" operator="eq" value="true">
++            <argument>CheckHardwareCompatibility()</argument>
++	    <message-title>Unsupported Architecture</message-title>
++	    <message>PCI utilities are only supported on Intel? based Apple systems.</message>
++        </requirement>
++    </requirements>
++    <flags/>
++    <item type="file">01root.xml</item>
++    <mod>properties.userDomain</mod>
++    <mod>properties.systemDomain</mod>
++    <mod>properties.anywhereDomain</mod>
++    <mod>properties.title</mod>
++    <mod>description</mod>
++    <mod>postinstallActions.actions</mod>
++</pkmkdoc>
+Index: pciutils-3.1.7/lib/i386-io-darwin.h
+===================================================================
+--- pciutils-3.1.7/lib/i386-io-darwin.h
++++ pciutils-3.1.7/lib/i386-io-darwin.h
+@@ -0,0 +1,30 @@
++/*
++ * Copyright (C) 2008-2010 coresystems GmbH
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
++ */
++
++#include <DirectHW/DirectHW.h>
++
++static int intel_setup_io(struct pci_access *a __attribute__((unused)))
++{
++	return !iopl(0);
++}
++
++static int intel_cleanup_io(struct pci_access *a __attribute__((unused)))
++{
++	return 1;
++}
++
+Index: pciutils-3.1.7/lib/configure
+===================================================================
+--- pciutils-3.1.7/lib/configure
++++ pciutils-3.1.7/lib/configure
+@@ -8,9 +8,9 @@
+ echo_n() {
+ 	if [ -n "$BASH" ]
+ 	then
+-		echo -n "$*"
++		/bin/echo -n "$*"
+ 	else
+-		echo "$*\c"
++		/bin/echo "$*\c"
+ 	fi
+ }
+ 
+@@ -124,6 +124,12 @@
+ 		echo >>$c '#define PCI_HAVE_PM_INTEL_CONF'
+ 		echo >>$m 'WITH_LIBS+=-lioperm'
+ 		;;
++	darwin)
++		echo_n " i386-ports"
++		echo >>$c '#define PCI_HAVE_PM_INTEL_CONF'
++		echo >>$c '#define PCI_HAVE_64BIT_ADDRESS'
++		echo >>$m 'WITH_LIBS+=-framework DirectHW'
++		;;
+         *)
+ 		echo " Unfortunately, your OS is not supported by the PCI Library"
+ 		exit 1
+Index: pciutils-3.1.7/lib/i386-ports.c
+===================================================================
+--- pciutils-3.1.7/lib/i386-ports.c
++++ pciutils-3.1.7/lib/i386-ports.c
+@@ -22,6 +22,8 @@
+ #include "i386-io-windows.h"
+ #elif defined(PCI_OS_CYGWIN)
+ #include "i386-io-cygwin.h"
++#elif defined(PCI_OS_DARWIN)
++#include "i386-io-darwin.h"
+ #else
+ #error Do not know how to access I/O ports on this OS.
+ #endif

Added: trunk/macosx/patches/superiotool-r6440.diff
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/patches/superiotool-r6440.diff	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1,28 @@
+Index: superiotool-r6440/superiotool.h
+===================================================================
+--- superiotool-r6440/superiotool.h
++++ superiotool-r6440/superiotool.h
+@@ -33,8 +33,8 @@
+ #include <sys/io.h>
+ #endif
+ #if (defined(__MACH__) && defined(__APPLE__))
+-/* DirectIO is available here: http://www.coresystems.de/en/directio */
+-#include <DirectIO/darwinio.h>
++/* DirectHW is available here: http://www.coreboot.org/DirectHW */
++#include <DirectHW/DirectHW.h>
+ #endif
+ 
+ #ifdef PCI_SUPPORT
+Index: superiotool-r6440/Makefile
+===================================================================
+--- superiotool-r6440/Makefile
++++ superiotool-r6440/Makefile
+@@ -37,7 +37,7 @@
+ 
+ OS_ARCH = $(shell uname)
+ ifeq ($(OS_ARCH), Darwin)
+-LIBS = -framework IOKit -framework DirectIO -lpci -lz
++LIBS = -framework IOKit -framework DirectHW -lpci -lz
+ endif
+ ifeq ($(OS_ARCH), FreeBSD)
+ CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \

Added: trunk/windows/README
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/windows/README	Mon Mar 14 03:21:55 2011	(r1)
@@ -0,0 +1 @@
+work in progress



From svn at coreboot.org  Mon Mar 14 03:41:04 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 03:41:04 +0100
Subject: [coreboot] [DirectHW] [commit] r2 - trunk/macosx/patches
Message-ID: <E1PyxiS-0004q2-BU@ra.coresystems.de>

Author: stepan
Date: Mon Mar 14 03:41:03 2011
New Revision: 2
URL: https://tracker.coreboot.org/trac/directhw/changeset/2

Log:
new upstream patch for dmidecode 2.11

Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Added:
   trunk/macosx/patches/dmidecode-2.11.diff
Deleted:
   trunk/macosx/patches/dmidecode-2.9.diff

Added: trunk/macosx/patches/dmidecode-2.11.diff
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/macosx/patches/dmidecode-2.11.diff	Mon Mar 14 03:41:03 2011	(r2)
@@ -0,0 +1,207 @@
+Index: dmidecode-2.11/biosdecode.c
+===================================================================
+--- dmidecode-2.11/biosdecode.c
++++ dmidecode-2.11/biosdecode.c
+@@ -560,9 +560,15 @@
+ static int parse_command_line(int argc, char * const argv[])
+ {
+ 	int option;
++#ifndef __APPLE__
+ 	const char *optstring = "d:hV";
++#else
++	const char *optstring = "hV";
++#endif
+ 	struct option longopts[] = {
++#ifndef __APPLE__
+ 		{ "dev-mem", required_argument, NULL, 'd' },
++#endif
+ 		{ "help", no_argument, NULL, 'h' },
+ 		{ "version", no_argument, NULL, 'V' },
+ 		{ 0, 0, 0, 0 }
+@@ -571,9 +577,11 @@
+ 	while ((option = getopt_long(argc, argv, optstring, longopts, NULL)) != -1)
+ 		switch (option)
+ 		{
++#ifndef __APPLE__
+ 			case 'd':
+ 				opt.devmem = optarg;
+ 				break;
++#endif
+ 			case 'h':
+ 				opt.flags |= FLAG_HELP;
+ 				break;
+@@ -592,7 +600,9 @@
+ 	static const char *help =
+ 		"Usage: biosdecode [OPTIONS]\n"
+ 		"Options are:\n"
++#ifndef __APPLE__
+ 		" -d, --dev-mem FILE     Read memory from device FILE (default: " DEFAULT_MEM_DEV ")\n"
++#endif
+ 		" -h, --help             Display this help text and exit\n"
+ 		" -V, --version          Display the version and exit\n";
+ 
+Index: dmidecode-2.11/config.h
+===================================================================
+--- dmidecode-2.11/config.h
++++ dmidecode-2.11/config.h
+@@ -12,9 +12,13 @@
+ #ifdef __sun
+ #define DEFAULT_MEM_DEV "/dev/xsvc"
+ #else
++#ifdef __APPLE__
++#define DEFAULT_MEM_DEV "DirectHW"
++#else
+ #define DEFAULT_MEM_DEV "/dev/mem"
+ #endif
+ #endif
++#endif
+ 
+ /* Use mmap or not */
+ #ifndef __BEOS__
+Index: dmidecode-2.11/vpdopt.c
+===================================================================
+--- dmidecode-2.11/vpdopt.c
++++ dmidecode-2.11/vpdopt.c
+@@ -92,9 +92,15 @@
+ int parse_command_line(int argc, char * const argv[])
+ {
+ 	int option;
++#ifndef __APPLE__
+ 	const char *optstring = "d:hs:uV";
++#else
++	const char *optstring = "hs:uV";
++#endif
+ 	struct option longopts[] = {
++#ifndef __APPLE__
+ 		{ "dev-mem", required_argument, NULL, 'd' },
++#endif
+ 		{ "help", no_argument, NULL, 'h' },
+ 		{ "string", required_argument, NULL, 's' },
+ 		{ "dump", no_argument, NULL, 'u' },
+@@ -105,9 +111,11 @@
+ 	while ((option = getopt_long(argc, argv, optstring, longopts, NULL)) != -1)
+ 		switch (option)
+ 		{
++#ifndef __APPLE__
+ 			case 'd':
+ 				opt.devmem = optarg;
+ 				break;
++#endif
+ 			case 'h':
+ 				opt.flags |= FLAG_HELP;
+ 				break;
+@@ -147,7 +155,9 @@
+ 	static const char *help =
+ 		"Usage: vpddecode [OPTIONS]\n"
+ 		"Options are:\n"
++#ifndef __APPLE__
+ 		" -d, --dev-mem FILE     Read memory from device FILE (default: " DEFAULT_MEM_DEV ")\n"
++#endif
+ 		" -h, --help             Display this help text and exit\n"
+ 		" -s, --string KEYWORD   Only display the value of the given VPD string\n"
+ 		" -u, --dump             Do not decode the VPD records\n"
+Index: dmidecode-2.11/util.c
+===================================================================
+--- dmidecode-2.11/util.c
++++ dmidecode-2.11/util.c
+@@ -47,6 +47,10 @@
+ #include "types.h"
+ #include "util.h"
+ 
++#ifdef __APPLE__
++#include <DirectHW/DirectHW.h>
++#endif
++
+ static int myread(int fd, u8 *buf, size_t count, const char *prefix)
+ {
+ 	ssize_t r = 1;
+@@ -95,6 +99,7 @@
+ void *mem_chunk(size_t base, size_t len, const char *devmem)
+ {
+ 	void *p;
++#ifndef __APPLE__
+ 	int fd;
+ #ifdef USE_MMAP
+ 	size_t mmoffset;
+@@ -158,7 +163,23 @@
+ out:
+ 	if (close(fd) == -1)
+ 		perror(devmem);
++#else
++	void *v;
++	iopl(3);
++	if((v=map_physical(base, len))==NULL)
++	{
++		perror("map_physical");
++		return NULL;
++	}
+ 
++	if((p=malloc(len))==NULL)
++	{
++		perror("malloc");
++		return NULL;
++	}
++	memcpy(p, v, len);
++	unmap_physical(v, len);
++#endif
+ 	return p;
+ }
+ 
+Index: dmidecode-2.11/ownership.c
+===================================================================
+--- dmidecode-2.11/ownership.c
++++ dmidecode-2.11/ownership.c
+@@ -114,9 +114,15 @@
+ static int parse_command_line(int argc, char * const argv[])
+ {
+ 	int option;
++#ifndef __APPLE__
+ 	const char *optstring = "d:hV";
++#else
++	const char *optstring = "hV";
++#endif
+ 	struct option longopts[] = {
++#ifndef __APPLE__
+ 		{ "dev-mem", required_argument, NULL, 'd' },
++#endif
+ 		{ "help", no_argument, NULL, 'h' },
+ 		{ "version", no_argument, NULL, 'V' },
+ 		{ 0, 0, 0, 0 }
+@@ -125,9 +131,11 @@
+ 	while ((option = getopt_long(argc, argv, optstring, longopts, NULL)) != -1)
+ 		switch (option)
+ 		{
++#ifndef __APPLE__
+ 			case 'd':
+ 				opt.devmem = optarg;
+ 				break;
++#endif
+ 			case 'h':
+ 				opt.flags |= FLAG_HELP;
+ 				break;
+@@ -146,7 +154,9 @@
+ 	static const char *help =
+ 		"Usage: ownership [OPTIONS]\n"
+ 		"Options are:\n"
++#ifndef __APPLE__
+ 		" -d, --dev-mem FILE     Read memory from device FILE (default: " DEFAULT_MEM_DEV ")\n"
++#endif
+ 		" -h, --help             Display this help text and exit\n"
+ 		" -V, --version          Display the version and exit\n";
+ 
+Index: dmidecode-2.11/Makefile
+===================================================================
+--- dmidecode-2.11/Makefile
++++ dmidecode-2.11/Makefile
+@@ -25,6 +25,11 @@
+ # Pass linker flags here
+ LDFLAGS =
+ 
++OS_ARCH = $(shell uname)
++ifeq ($(OS_ARCH), Darwin)
++LDFLAGS += -framework IOKit -framework DirectHW
++endif
++
+ DESTDIR =
+ prefix  = /usr/local
+ sbindir = $(prefix)/sbin



From svn at coreboot.org  Mon Mar 14 03:46:17 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 03:46:17 +0100
Subject: [coreboot] [DirectHW] [commit] r3 - trunk/macosx/patches
Message-ID: <E1PyxnV-0005lk-E5@ra.coresystems.de>

Author: stepan
Date: Mon Mar 14 03:46:17 2011
New Revision: 3
URL: https://tracker.coreboot.org/trac/directhw/changeset/3

Log:
Add proper Signed-off-by and patch descriptions 

Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/macosx/patches/dmidecode-2.11.diff
   trunk/macosx/patches/flashrom-r1280.diff
   trunk/macosx/patches/inteltool-r6440.diff
   trunk/macosx/patches/msrtool-r6440.diff
   trunk/macosx/patches/nvramtool-r6440.diff
   trunk/macosx/patches/pciutils-3.1.7.diff
   trunk/macosx/patches/superiotool-r6440.diff

Modified: trunk/macosx/patches/dmidecode-2.11.diff
==============================================================================
--- trunk/macosx/patches/dmidecode-2.11.diff	Mon Mar 14 03:41:03 2011	(r2)
+++ trunk/macosx/patches/dmidecode-2.11.diff	Mon Mar 14 03:46:17 2011	(r3)
@@ -1,3 +1,8 @@
+Port dmidecode package to Mac OS X using DirectHW:
+http://www.coreboot.org/DirectHW
+
+Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
+
 Index: dmidecode-2.11/biosdecode.c
 ===================================================================
 --- dmidecode-2.11/biosdecode.c

Modified: trunk/macosx/patches/flashrom-r1280.diff
==============================================================================
--- trunk/macosx/patches/flashrom-r1280.diff	Mon Mar 14 03:41:03 2011	(r2)
+++ trunk/macosx/patches/flashrom-r1280.diff	Mon Mar 14 03:46:17 2011	(r3)
@@ -1,3 +1,8 @@
+Update port of flashrom package to Mac OS X using DirectHW:
+http://www.coreboot.org/DirectHW
+
+Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
+
 Index: flashrom-r1280/hwaccess.h
 ===================================================================
 --- flashrom-r1280/hwaccess.h

Modified: trunk/macosx/patches/inteltool-r6440.diff
==============================================================================
--- trunk/macosx/patches/inteltool-r6440.diff	Mon Mar 14 03:41:03 2011	(r2)
+++ trunk/macosx/patches/inteltool-r6440.diff	Mon Mar 14 03:46:17 2011	(r3)
@@ -1,3 +1,8 @@
+Update port of inteltool to Mac OS X using DirectHW:
+http://www.coreboot.org/DirectHW
+
+Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
+
 Index: inteltool-r6440/inteltool.h
 ===================================================================
 --- inteltool-r6440/inteltool.h

Modified: trunk/macosx/patches/msrtool-r6440.diff
==============================================================================
--- trunk/macosx/patches/msrtool-r6440.diff	Mon Mar 14 03:41:03 2011	(r2)
+++ trunk/macosx/patches/msrtool-r6440.diff	Mon Mar 14 03:46:17 2011	(r3)
@@ -1,3 +1,8 @@
+Update port of msrtool to Mac OS X using DirectHW:
+http://www.coreboot.org/DirectHW
+
+Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
+
 Index: msrtool-r6440/msrtool.c
 ===================================================================
 --- msrtool-r6440/msrtool.c

Modified: trunk/macosx/patches/nvramtool-r6440.diff
==============================================================================
--- trunk/macosx/patches/nvramtool-r6440.diff	Mon Mar 14 03:41:03 2011	(r2)
+++ trunk/macosx/patches/nvramtool-r6440.diff	Mon Mar 14 03:46:17 2011	(r3)
@@ -1,3 +1,8 @@
+Update port of nvramtool to Mac OS X using DirectHW:
+http://www.coreboot.org/DirectHW
+
+Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
+
 Index: nvramtool-r6440/accessors/cmos-hw-unix.c
 ===================================================================
 --- nvramtool-r6440/accessors/cmos-hw-unix.c

Modified: trunk/macosx/patches/pciutils-3.1.7.diff
==============================================================================
--- trunk/macosx/patches/pciutils-3.1.7.diff	Mon Mar 14 03:41:03 2011	(r2)
+++ trunk/macosx/patches/pciutils-3.1.7.diff	Mon Mar 14 03:46:17 2011	(r3)
@@ -1,3 +1,8 @@
+Port pciutils to Mac OS X using DirectHW:
+http://www.coreboot.org/DirectHW
+
+Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
+
 Index: pciutils-3.1.7/osx/Welcome.rtf
 ===================================================================
 --- pciutils-3.1.7/osx/Welcome.rtf

Modified: trunk/macosx/patches/superiotool-r6440.diff
==============================================================================
--- trunk/macosx/patches/superiotool-r6440.diff	Mon Mar 14 03:41:03 2011	(r2)
+++ trunk/macosx/patches/superiotool-r6440.diff	Mon Mar 14 03:46:17 2011	(r3)
@@ -1,3 +1,8 @@
+Update port of superiotool to Mac OS X using DirectHW:
+http://www.coreboot.org/DirectHW
+
+Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
+
 Index: superiotool-r6440/superiotool.h
 ===================================================================
 --- superiotool-r6440/superiotool.h



From scott at notabs.org  Mon Mar 14 03:55:55 2011
From: scott at notabs.org (Scott Duplichan)
Date: Sun, 13 Mar 2011 21:55:55 -0500
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <20110313225253.GA4004@morn.localdomain>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
	<20110313225253.GA4004@morn.localdomain>
Message-ID: <F51E1EF25C924524B8D7931169545360@m3a78>

Kevin O'Connor wrote:

]On Sat, Mar 12, 2011 at 09:47:56PM -0600, Scott Duplichan wrote:
]> Hello,
]> 
]> I am trying to overcome problems building seabios/tools/kconfig from
]> the windows/mingw environment. Here are the failures:
]> 
]> 1) Link step for tools/kconfig/conf fails to find regcomp/regexec/regfree.
]>    In the mingw environment these functions are available in libregex, 
]>    but libregex is not included in the standard library search. I have
]>    not found a way to add '-lregex' to the link command line:
]>    $(Q)$(HOSTCC) $(HOSTLDFLAGS) -o $@ $(addprefix $(obj)/,$($(@F)-objs)) $(HOST_LOADLIBES) ]$(HOSTLOADLIBES_$(@F))
]>    HOSTLDFLAGS occurs too early in the file list for this use.
]
]Can you add it to HOST_LOADLIBES?

When added to HOST_LOADLIBES before starting the build, the value
is cleared by coreboot/util/kconfig/makefile line 103,

100: # Use recursively expanded variables so we do not call gcc unless
101: # we really need to do so. (Do not call gcc as part of make mrproper)
102: HOST_EXTRACFLAGS = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags)
103: HOST_LOADLIBES   = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC))


]> 2) Link step for tools/kconfig/conf fails to find function uname().
]>    I can come up with a library to provide this function but need
]>    help passing it to the linker, same as with item 1.
]> 
]> 3) Function mkdir() takes only one argument in the mingw environment,
]>    yet takes 2 arguments otherwise. I have not found a good way to 
]>    overcome this difference.
]
]What about making a file "mingw_fixups.h" and changing the HOSTCFLAGS
]to add "-include mingw_fixups.h".  The header can then do something
]like:
]
]#define uname(arg1) memset(arg1, 0, sizeof(*arg1))
]#define mkdir(arg1,arg2) mkdir(arg1)

This idea is workable. I Used:
#define _SYS_UTSNAME_H
struct utsname{char release[20];};
#define uname(arg1) memset(arg1, 0, sizeof(*arg1))
#define mkdir(arg1,...) mkdir(arg1)

The '#define _SYS_UTSNAME_H' blocks utsname.h inclusion. This is needed
to prevent a conflict between the macro definition and the function
prototype. A minimal utsname struct definition must be added back. The
mkdir macro is changed to variadic type to prevent a compile fail.

I bypassed the libregex problem for the moment and ran with the above
change to see what other problems remain. A seabios/tools/kconfig/confdata.c
call to rename(newname, dirname) fails. It appears the destination file must
not exist for the win32 version of this function to succeed. Here is how the
how the problem was overcome for coreboot:
http://tracker.coreboot.org/trac/coreboot/changeset/4952
When I add the UNLINK_IF_NECESSARY part of this change, the rename succeeds.
Could seabios adopt this change? For simplicity, the neighboring definition
#define mkdir(x,y) mkdir(x) could be considered too.

Thanks,
Scott

]
]-Kevin




From kevin at koconnor.net  Mon Mar 14 04:30:49 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sun, 13 Mar 2011 23:30:49 -0400
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <F51E1EF25C924524B8D7931169545360@m3a78>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
	<20110313225253.GA4004@morn.localdomain>
	<F51E1EF25C924524B8D7931169545360@m3a78>
Message-ID: <20110314033049.GA14722@morn.localdomain>

On Sun, Mar 13, 2011 at 09:55:55PM -0500, Scott Duplichan wrote:
> Kevin O'Connor wrote:
> ]What about making a file "mingw_fixups.h" and changing the HOSTCFLAGS
> ]to add "-include mingw_fixups.h".  The header can then do something
> ]like:
> ]
> ]#define uname(arg1) memset(arg1, 0, sizeof(*arg1))
> ]#define mkdir(arg1,arg2) mkdir(arg1)
> I bypassed the libregex problem for the moment and ran with the above
> change to see what other problems remain. A seabios/tools/kconfig/confdata.c
> call to rename(newname, dirname) fails. It appears the destination file must
> not exist for the win32 version of this function to succeed.

Can you fix this up using the same "mingw_fixups.h" trick?  That is,
something like:

static inline void myrename() { ...}

#define rename(...) myrename(...)

If you're having a conflict with a system header, you should be able
to include the header in mingw_fixups prior to the #define.

>Here is how the
> how the problem was overcome for coreboot:
> http://tracker.coreboot.org/trac/coreboot/changeset/4952
> When I add the UNLINK_IF_NECESSARY part of this change, the rename succeeds.
> Could seabios adopt this change?

It's possible, but I'd prefer to keep the source code close to the
Linux version - it makes merges later on easier.

-Kevin



From svn at coreboot.org  Mon Mar 14 09:18:17 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 09:18:17 +0100
Subject: [coreboot] [commit] r6441 - trunk/src/ec/acpi
Message-ID: <E1Pz2yn-0007zK-OW@ra.coresystems.de>

Author: svens
Date: Mon Mar 14 09:18:17 2011
New Revision: 6441
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6441

Log:
ACPI EC: add ec_set_bit() / ec_clr_bit()

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Sven Schnelle <svens at stackframe.org>

Modified:
   trunk/src/ec/acpi/ec.c
   trunk/src/ec/acpi/ec.h

Modified: trunk/src/ec/acpi/ec.c
==============================================================================
--- trunk/src/ec/acpi/ec.c	Thu Mar 10 08:52:02 2011	(r6440)
+++ trunk/src/ec/acpi/ec.c	Mon Mar 14 09:18:17 2011	(r6441)
@@ -113,6 +113,16 @@
 	return send_ec_data(data);
 }
 
+void ec_set_bit(u8 addr, u8 bit)
+{
+	ec_write(addr, ec_read(addr) | (1 << bit));
+}
+
+void ec_clr_bit(u8 addr, u8 bit)
+{
+	ec_write(addr, ec_read(addr) &  ~(1 << bit));
+}
+
 struct chip_operations ec_acpi_ops = {
 	CHIP_NAME("ACPI Embedded Controller")
 };

Modified: trunk/src/ec/acpi/ec.h
==============================================================================
--- trunk/src/ec/acpi/ec.h	Thu Mar 10 08:52:02 2011	(r6440)
+++ trunk/src/ec/acpi/ec.h	Mon Mar 14 09:18:17 2011	(r6441)
@@ -44,6 +44,8 @@
 u8 recv_ec_data(void);
 u8 ec_read(u8 addr);
 int ec_write(u8 addr, u8 data);
+void ec_set_bit(u8 addr, u8 bit);
+void ec_clr_bit(u8 addr, u8 bit);
 
 #endif
 



From svn at coreboot.org  Mon Mar 14 09:18:30 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 09:18:30 +0100
Subject: [coreboot] [commit] r6442 - trunk/src/ec/acpi
Message-ID: <E1Pz2z0-00082c-Vk@ra.coresystems.de>

Author: svens
Date: Mon Mar 14 09:18:27 2011
New Revision: 6442
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6442

Log:
ec/acpi: make ACPI register pair configurable

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/src/ec/acpi/ec.c
   trunk/src/ec/acpi/ec.h

Modified: trunk/src/ec/acpi/ec.c
==============================================================================
--- trunk/src/ec/acpi/ec.c	Mon Mar 14 09:18:17 2011	(r6441)
+++ trunk/src/ec/acpi/ec.c	Mon Mar 14 09:18:27 2011	(r6442)
@@ -25,12 +25,15 @@
 #include <delay.h>
 #include "ec.h"
 
+static int ec_cmd_reg = EC_SC;
+static int ec_data_reg = EC_DATA;
+
 int send_ec_command(u8 command)
 {
 	int timeout;
 
 	timeout = 0x7ff;
-	while ((inb(EC_SC) & EC_IBF) && --timeout) {
+	while ((inb(ec_cmd_reg) & EC_IBF) && --timeout) {
 		udelay(10);
 		if ((timeout & 0xff) == 0)
 			printk(BIOS_SPEW, ".");
@@ -41,7 +44,7 @@
 		// return -1;
 	}
 
-	outb(command, EC_SC);
+	outb(command, ec_cmd_reg);
 	return 0;
 }
 
@@ -50,7 +53,7 @@
 	int timeout;
 
 	timeout = 0x7ff;
-	while ((inb(EC_SC) & EC_IBF) && --timeout) { // wait for IBF = 0
+	while ((inb(ec_cmd_reg) & EC_IBF) && --timeout) { // wait for IBF = 0
 		udelay(10);
 		if ((timeout & 0xff) == 0)
 			printk(BIOS_SPEW, ".");
@@ -61,14 +64,14 @@
 		// return -1;
 	}
 
-	outb(data, EC_DATA);
+	outb(data, ec_data_reg);
 
 	return 0;
 }
 
 int send_ec_data_nowait(u8 data)
 {
-	outb(data, EC_DATA);
+	outb(data, ec_data_reg);
 
 	return 0;
 }
@@ -80,7 +83,7 @@
 
 	timeout = 0x7fff;
 	while (--timeout) { // Wait for OBF = 1
-		if (inb(EC_SC) & EC_OBF) {
+		if (inb(ec_cmd_reg) & EC_OBF) {
 			break;
 		}
 		udelay(10);
@@ -92,7 +95,7 @@
 		// return -1;
 	}
 
-	data = inb(EC_DATA);
+	data = inb(ec_data_reg);
 	printk(BIOS_DEBUG, "recv_ec_data: 0x%02x\n", data);
 
 	return data;
@@ -123,6 +126,12 @@
 	ec_write(addr, ec_read(addr) &  ~(1 << bit));
 }
 
+void ec_set_ports(u16 cmd_reg, u16 data_reg)
+{
+	ec_cmd_reg = cmd_reg;
+	ec_data_reg = data_reg;
+}
+
 struct chip_operations ec_acpi_ops = {
 	CHIP_NAME("ACPI Embedded Controller")
 };

Modified: trunk/src/ec/acpi/ec.h
==============================================================================
--- trunk/src/ec/acpi/ec.h	Mon Mar 14 09:18:17 2011	(r6441)
+++ trunk/src/ec/acpi/ec.h	Mon Mar 14 09:18:27 2011	(r6442)
@@ -46,6 +46,7 @@
 int ec_write(u8 addr, u8 data);
 void ec_set_bit(u8 addr, u8 bit);
 void ec_clr_bit(u8 addr, u8 bit);
+void ec_set_ports(u16 cmd_reg, u16 data_reg);
 
 #endif
 



From stefan.reinauer at coreboot.org  Mon Mar 14 04:49:17 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sun, 13 Mar 2011 20:49:17 -0700
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <20110314033049.GA14722@morn.localdomain>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>	<20110313225253.GA4004@morn.localdomain>	<F51E1EF25C924524B8D7931169545360@m3a78>
	<20110314033049.GA14722@morn.localdomain>
Message-ID: <4D7D903D.7030305@coreboot.org>

On 3/13/11 8:30 PM, Kevin O'Connor wrote:
>> Here is how the
>> how the problem was overcome for coreboot:
>> http://tracker.coreboot.org/trac/coreboot/changeset/4952
>> When I add the UNLINK_IF_NECESSARY part of this change, the rename succeeds.
>> Could seabios adopt this change?
> It's possible, but I'd prefer to keep the source code close to the
> Linux version - it makes merges later on easier.

Then maybe we should send our patches upstream?



From svn at coreboot.org  Mon Mar 14 10:08:28 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 10:08:28 +0100
Subject: [coreboot] [commit] r6443 - trunk/util/msrtool
Message-ID: <E1Pz3lM-0000DI-8Y@ra.coresystems.de>

Author: stuge
Date: Mon Mar 14 10:08:27 2011
New Revision: 6443
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6443

Log:
msrtool: Update to use DirectHW on Mac OS X

http://www.coreboot.org/DirectHW

Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/util/msrtool/configure
   trunk/util/msrtool/darwin.c
   trunk/util/msrtool/msrtool.c
   trunk/util/msrtool/msrtool.h

Modified: trunk/util/msrtool/configure
==============================================================================
--- trunk/util/msrtool/configure	Mon Mar 14 09:18:27 2011	(r6442)
+++ trunk/util/msrtool/configure	Mon Mar 14 10:08:27 2011	(r6443)
@@ -155,7 +155,7 @@
 	rm -f .config.c
 	exit 1
 }
-LDFLAGS=`trylink "libpci (from pciutils)" "${pc_LDFLAGS}" "-lpci -lz" "-L/usr/local/lib -lpci -lz" "-framework DirectIO -lpci -lz"` || {
+LDFLAGS=`trylink "libpci (from pciutils)" "${pc_LDFLAGS}" "-lpci -lz" "-L/usr/local/lib -lpci -lz" "-framework DirectHW -lpci -lz"` || {
 	rm -f .config.c .config.o
 	exit 1
 }

Modified: trunk/util/msrtool/darwin.c
==============================================================================
--- trunk/util/msrtool/darwin.c	Mon Mar 14 09:18:27 2011	(r6442)
+++ trunk/util/msrtool/darwin.c	Mon Mar 14 10:08:27 2011	(r6443)
@@ -26,8 +26,8 @@
 
 #include "msrtool.h"
 
-/* This Darwin support requires DirectIO, which is available at
- * http://www.coresystems.de/en/directio
+/* This Darwin support requires DirectHW, which is available at
+ * http://www.coreboot.org/DirectHW
  */
 
 int darwin_probe(const struct sysdef *system)

Modified: trunk/util/msrtool/msrtool.c
==============================================================================
--- trunk/util/msrtool/msrtool.c	Mon Mar 14 09:18:27 2011	(r6442)
+++ trunk/util/msrtool/msrtool.c	Mon Mar 14 10:08:27 2011	(r6443)
@@ -49,7 +49,7 @@
 
 static struct sysdef allsystems[] = {
 	{ "linux", "Linux with /dev/cpu/*/msr", linux_probe, linux_open, linux_close, linux_rdmsr },
-	{ "darwin", "OS X with DirectIO", darwin_probe, darwin_open, darwin_close, darwin_rdmsr },
+	{ "darwin", "Mac OS X with DirectHW", darwin_probe, darwin_open, darwin_close, darwin_rdmsr },
 	{ "freebsd", "FreeBSD with /dev/cpuctl*", freebsd_probe, freebsd_open, freebsd_close, freebsd_rdmsr },
 	{ SYSTEM_EOT }
 };

Modified: trunk/util/msrtool/msrtool.h
==============================================================================
--- trunk/util/msrtool/msrtool.h	Mon Mar 14 09:18:27 2011	(r6442)
+++ trunk/util/msrtool/msrtool.h	Mon Mar 14 10:08:27 2011	(r6443)
@@ -24,9 +24,9 @@
 #include <stdio.h>
 #include <stdint.h>
 #if (defined(__MACH__) && defined(__APPLE__))
-/* DirectIO is available here: http://www.coresystems.de/en/directio */
+/* DirectHW is available here: http://www.coreboot.org/DirectHW */
 #define __DARWIN__
-#include <DirectIO/darwinio.h>
+#include <DirectHW/DirectHW.h>
 #endif
 #if defined(__FreeBSD__)
 #include <sys/ioctl.h>



From peter at stuge.se  Mon Mar 14 10:11:43 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 14 Mar 2011 10:11:43 +0100
Subject: [coreboot] [DirectHW] [commit] r1 - branches tags
	trunk	trunk/macosx
	trunk/macosx/DirectHW	trunk/macosx/DirectHW/DirectHW.pmdoc	trunk/macosx/DirectHW/DirectHW.xcodeproj	trunk/macosx/DirectHW/build
	trunk/macos...
In-Reply-To: <E1PyxPv-0002ri-Sp@ra.coresystems.de>
References: <E1PyxPv-0002ri-Sp@ra.coresystems.de>
Message-ID: <20110314091143.25268.qmail@stuge.se>

repository service wrote:
> Added:
>    trunk/macosx/patches/msrtool-r6440.diff

svn rm:ed this but could not commit to DirectHW. Patch has been
applied upstream.


//Peter



From kevin at koconnor.net  Mon Mar 14 13:42:01 2011
From: kevin at koconnor.net (Kevin O'Connor)
Date: Mon, 14 Mar 2011 08:42:01 -0400
Subject: [coreboot] mingw build problem with seabios/tools/kconfig
In-Reply-To: <4D7D903D.7030305@coreboot.org>
References: <6DFE68E6176942FE9D8CA94893DF9BC9@m3a78>
	<20110313225253.GA4004@morn.localdomain>
	<F51E1EF25C924524B8D7931169545360@m3a78>
	<20110314033049.GA14722@morn.localdomain>
	<4D7D903D.7030305@coreboot.org>
Message-ID: <20110314124201.GA32618@morn.localdomain>

On Sun, Mar 13, 2011 at 08:49:17PM -0700, Stefan Reinauer wrote:
> On 3/13/11 8:30 PM, Kevin O'Connor wrote:
> >>Here is how the
> >>how the problem was overcome for coreboot:
> >>http://tracker.coreboot.org/trac/coreboot/changeset/4952
> >>When I add the UNLINK_IF_NECESSARY part of this change, the rename succeeds.
> >>Could seabios adopt this change?
> >It's possible, but I'd prefer to keep the source code close to the
> >Linux version - it makes merges later on easier.
> 
> Then maybe we should send our patches upstream?

Yes - getting the patches into the Linux kbuild source would be best.

-Kevin



From svens at stackframe.org  Mon Mar 14 13:47:18 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Mon, 14 Mar 2011 13:47:18 +0100
Subject: [coreboot] [PATCH] X60: Add _PRW/_PSW methods to LID/SLPB objects
Message-ID: <1300106838-23881-1-git-send-email-svens@stackframe.org>

This patch adds the required methods for enabling/disabling
the LID and SLPB objects as wake source. On Thinkpads, the
Fn key can (and is by the Vendor BIOS) programmed as Wake source,
so let's do it the same way.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/x60/acpi/lid.asl         |   21 +++++++++++++++++++--
 src/mainboard/lenovo/x60/acpi/sleepbutton.asl |   24 ++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/lenovo/x60/acpi/lid.asl b/src/mainboard/lenovo/x60/acpi/lid.asl
index 2c92ee6..2dfa8d1 100644
--- a/src/mainboard/lenovo/x60/acpi/lid.asl
+++ b/src/mainboard/lenovo/x60/acpi/lid.asl
@@ -21,9 +21,12 @@
 
 Field(ERAM, ByteAcc, NoLock, Preserve)
 {
+                Offset (0x32),
+			    , 2,
+			WKLD, 1,
 		Offset (0x46),
-				, 2,
-			LIDS	, 1
+			    , 2,
+			LIDS, 1
 }
 
 Device(LID)
@@ -34,4 +37,18 @@ Device(LID)
 	{
 		return (LIDS)
 	}
+
+	Method(_PRW, 0, NotSerialized)
+	{
+		Return (Package() { 0x18, 0x03 })
+	}
+
+	Method(_PSW, 1, NotSerialized)
+	{
+		if (Arg0) {
+			Store(1, WKLD)
+		} else {
+			Store(0, WKLD)
+		}
+	}
 }
diff --git a/src/mainboard/lenovo/x60/acpi/sleepbutton.asl b/src/mainboard/lenovo/x60/acpi/sleepbutton.asl
index c339158..09e88aa 100644
--- a/src/mainboard/lenovo/x60/acpi/sleepbutton.asl
+++ b/src/mainboard/lenovo/x60/acpi/sleepbutton.asl
@@ -19,7 +19,31 @@
  * MA 02110-1301 USA
  */
 
+Field(ERAM, ByteAcc, NoLock, Preserve)
+{
+		Offset (0x32),
+			    , 4,
+			WKFN, 1,
+		Offset(0x83),
+			FNKY, 8
+}
+
 Device(SLPB)
 {
         Name (_HID, EisaId ("PNP0C0E"))
+	Method(_PRW, 0, NotSerialized)
+	{
+		Return (Package() { 0x18, 0x03 })
+	}
+
+	Method(_PSW, 1, NotSerialized)
+	{
+		if (Arg0) {
+			Store(6, FNKY) /* Fn key acts as wake button */
+			Store(1, WKFN)
+		} else {
+			Store(0, FNKY) /* Fn key normal operation */
+			Store(0, WKFN)
+		}
+	}
 }
-- 
1.7.4.1




From peter at stuge.se  Mon Mar 14 14:34:13 2011
From: peter at stuge.se (Peter Stuge)
Date: Mon, 14 Mar 2011 14:34:13 +0100
Subject: [coreboot] [PATCH] X60: Add _PRW/_PSW methods to
	LID/SLPB	objects
In-Reply-To: <1300106838-23881-1-git-send-email-svens@stackframe.org>
References: <1300106838-23881-1-git-send-email-svens@stackframe.org>
Message-ID: <20110314133413.6604.qmail@stuge.se>

Sven Schnelle wrote:
> This patch adds the required methods for enabling/disabling
> the LID and SLPB objects as wake source. On Thinkpads, the
> Fn key can (and is by the Vendor BIOS) programmed as Wake source,
> so let's do it the same way.
> 
> Signed-off-by: Sven Schnelle <svens at stackframe.org>

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Mon Mar 14 14:42:09 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 14:42:09 +0100
Subject: [coreboot] [commit] r6444 - in trunk/src/mainboard/lenovo/x60: .
	acpi
Message-ID: <E1Pz82D-0003w7-4A@ra.coresystems.de>

Author: svens
Date: Mon Mar 14 14:42:08 2011
New Revision: 6444
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6444

Log:
X60: Add _PRW/_PSW methods to LID/SLPB objects

This patch adds the required methods for enabling/disabling
the LID and SLPB objects as wake source. On Thinkpads, the
Fn key can (and is by the Vendor BIOS) programmed as Wake source,
so let's do it the same way.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>

Added:
   trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl
Modified:
   trunk/src/mainboard/lenovo/x60/acpi/lid.asl
   trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl
   trunk/src/mainboard/lenovo/x60/dsdt.asl

Modified: trunk/src/mainboard/lenovo/x60/acpi/lid.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/acpi/lid.asl	Mon Mar 14 10:08:27 2011	(r6443)
+++ trunk/src/mainboard/lenovo/x60/acpi/lid.asl	Mon Mar 14 14:42:08 2011	(r6444)
@@ -21,9 +21,12 @@
 
 Field(ERAM, ByteAcc, NoLock, Preserve)
 {
+                Offset (0x32),
+			    , 2,
+			WKLD, 1,
 		Offset (0x46),
-				, 2,
-			LIDS	, 1
+			    , 2,
+			LIDS, 1
 }
 
 Device(LID)
@@ -34,4 +37,18 @@
 	{
 		return (LIDS)
 	}
+
+	Method(_PRW, 0, NotSerialized)
+	{
+		Return (Package() { 0x18, 0x03 })
+	}
+
+	Method(_PSW, 1, NotSerialized)
+	{
+		if (Arg0) {
+			Store(1, WKLD)
+		} else {
+			Store(0, WKLD)
+		}
+	}
 }

Modified: trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl	Mon Mar 14 10:08:27 2011	(r6443)
+++ trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl	Mon Mar 14 14:42:08 2011	(r6444)
@@ -19,7 +19,31 @@
  * MA 02110-1301 USA
  */
 
+Field(ERAM, ByteAcc, NoLock, Preserve)
+{
+		Offset (0x32),
+			    , 4,
+			WKFN, 1,
+		Offset(0x83),
+			FNKY, 8
+}
+
 Device(SLPB)
 {
         Name (_HID, EisaId ("PNP0C0E"))
+	Method(_PRW, 0, NotSerialized)
+	{
+		Return (Package() { 0x18, 0x03 })
+	}
+
+	Method(_PSW, 1, NotSerialized)
+	{
+		if (Arg0) {
+			Store(6, FNKY) /* Fn key acts as wake button */
+			Store(1, WKFN)
+		} else {
+			Store(0, FNKY) /* Fn key normal operation */
+			Store(0, WKFN)
+		}
+	}
 }

Added: trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl	Mon Mar 14 14:42:08 2011	(r6444)
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+Scope (\_SI)
+{
+	Method(_SST, 1, NotSerialized)
+	{
+		If (LEqual (Arg0, 0)) {
+			/* Indicator off */
+
+			/* power LED off */
+			\_SB.PCI0.LPC.EC.LED(0x00)
+			/* suspend LED off */
+			\_SB.PCI0.LPC.EC.LED(0x07)
+		}
+
+		If (LEqual (Arg0, 1)) {
+			/* working state */
+
+			/* power LED on */
+			\_SB.PCI0.LPC.EC.LED(0x80)
+			/* suspend LED off */
+			\_SB.PCI0.LPC.EC.LED(0x07)
+		}
+
+		If (LEqual (Arg0, 2)) {
+			/* waking state */
+
+			/* power LED om */
+			\_SB.PCI0.LPC.EC.LED(0x80)
+			/* suspend LED blinking */
+			\_SB.PCI0.LPC.EC.LED(0xc7)
+		}
+
+		If (LEqual (Arg0, 3)) {
+			/* sleep state */
+
+			/* power LED off */
+			\_SB.PCI0.LPC.EC.LED(0x00)
+			/* suspend LED on */
+			\_SB.PCI0.LPC.EC.LED(0x87)
+		}
+		
+		
+		
+	}
+}

Modified: trunk/src/mainboard/lenovo/x60/dsdt.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/dsdt.asl	Mon Mar 14 10:08:27 2011	(r6443)
+++ trunk/src/mainboard/lenovo/x60/dsdt.asl	Mon Mar 14 14:42:08 2011	(r6444)
@@ -42,7 +42,8 @@
 
 	// Thermal Zone
 	#include "acpi/thermal.asl"
-
+	// System status indicators
+	#include "acpi/systemstatus.asl
 	Scope (\_SB) {
 		Device (PCI0)
 		{



From svn at coreboot.org  Mon Mar 14 15:10:55 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 15:10:55 +0100
Subject: [coreboot] build service results for r6444
Message-ID: <E1Pz8U3-0006DB-U5@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "svens" checked in revision 6444 to
the coreboot repository. This caused the following 
changes:

Change Log:
X60: Add _PRW/_PSW methods to LID/SLPB objects

This patch adds the required methods for enabling/disabling
the LID and SLPB objects as wake source. On Thinkpads, the
Fn key can (and is by the Vendor BIOS) programmed as Wake source,
so let's do it the same way.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>

Build Log:
Compilation of lenovo:x60 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6444&device=x60&vendor=lenovo&num=2


If something broke during this checkin please be a pain 
in svens's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Mon Mar 14 15:26:42 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 15:26:42 +0100
Subject: [coreboot] [commit] r6445 - trunk/src/mainboard/lenovo/x60
Message-ID: <E1Pz8jK-0008CQ-At@ra.coresystems.de>

Author: svens
Date: Mon Mar 14 15:26:41 2011
New Revision: 6445
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6445

Log:
X60: fix typo in dsdt.asl

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Sven Schnelle <svens at stackframe.org>

Modified:
   trunk/src/mainboard/lenovo/x60/dsdt.asl

Modified: trunk/src/mainboard/lenovo/x60/dsdt.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/dsdt.asl	Mon Mar 14 14:42:08 2011	(r6444)
+++ trunk/src/mainboard/lenovo/x60/dsdt.asl	Mon Mar 14 15:26:41 2011	(r6445)
@@ -43,7 +43,7 @@
 	// Thermal Zone
 	#include "acpi/thermal.asl"
 	// System status indicators
-	#include "acpi/systemstatus.asl
+	#include "acpi/systemstatus.asl"
 	Scope (\_SB) {
 		Device (PCI0)
 		{



From svn at coreboot.org  Mon Mar 14 15:55:48 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 15:55:48 +0100
Subject: [coreboot] build service results for r6445
Message-ID: <E1Pz9BU-0002ZJ-1z@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "svens" checked in revision 6445 to
the coreboot repository. This caused the following 
changes:

Change Log:
X60: fix typo in dsdt.asl

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Sven Schnelle <svens at stackframe.org>

Build Log:
Compilation of lenovo:x60 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6445&device=x60&vendor=lenovo&num=2


If something broke during this checkin please be a pain 
in svens's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Mon Mar 14 16:00:02 2011
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 14 Mar 2011 16:00:02 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1Pz9Fa-0003Lm-8N@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20110314/0b55f569/attachment.html>

From svn at coreboot.org  Mon Mar 14 16:23:45 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 16:23:45 +0100
Subject: [coreboot] [commit] r6446 - trunk/src/mainboard/lenovo/x60/acpi
Message-ID: <E1Pz9cX-0007os-CX@ra.coresystems.de>

Author: svens
Date: Mon Mar 14 16:23:44 2011
New Revision: 6446
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6446

Log:
X60: LPC bus is LPCB, not LPC

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Sven Schnelle <svens at stackframe.org>

Modified:
   trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl

Modified: trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl	Mon Mar 14 15:26:41 2011	(r6445)
+++ trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl	Mon Mar 14 16:23:44 2011	(r6446)
@@ -28,36 +28,36 @@
 			/* Indicator off */
 
 			/* power LED off */
-			\_SB.PCI0.LPC.EC.LED(0x00)
+			\_SB.PCI0.LPCB.EC.LED(0x00)
 			/* suspend LED off */
-			\_SB.PCI0.LPC.EC.LED(0x07)
+			\_SB.PCI0.LPCB.EC.LED(0x07)
 		}
 
 		If (LEqual (Arg0, 1)) {
 			/* working state */
 
 			/* power LED on */
-			\_SB.PCI0.LPC.EC.LED(0x80)
+			\_SB.PCI0.LPCB.EC.LED(0x80)
 			/* suspend LED off */
-			\_SB.PCI0.LPC.EC.LED(0x07)
+			\_SB.PCI0.LPCB.EC.LED(0x07)
 		}
 
 		If (LEqual (Arg0, 2)) {
 			/* waking state */
 
 			/* power LED om */
-			\_SB.PCI0.LPC.EC.LED(0x80)
+			\_SB.PCI0.LPCB.EC.LED(0x80)
 			/* suspend LED blinking */
-			\_SB.PCI0.LPC.EC.LED(0xc7)
+			\_SB.PCI0.LPCB.EC.LED(0xc7)
 		}
 
 		If (LEqual (Arg0, 3)) {
 			/* sleep state */
 
 			/* power LED off */
-			\_SB.PCI0.LPC.EC.LED(0x00)
+			\_SB.PCI0.LPCB.EC.LED(0x00)
 			/* suspend LED on */
-			\_SB.PCI0.LPC.EC.LED(0x87)
+			\_SB.PCI0.LPCB.EC.LED(0x87)
 		}
 		
 		



From svn at coreboot.org  Mon Mar 14 17:15:00 2011
From: svn at coreboot.org (repository service)
Date: Mon, 14 Mar 2011 17:15:00 +0100
Subject: [coreboot] build service results for r6446
Message-ID: <E1PzAQ8-0008Ms-Vs@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "svens" checked in revision 6446 to
the coreboot repository. This caused the following 
changes:

Change Log:
X60: LPC bus is LPCB, not LPC

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Sven Schnelle <svens at stackframe.org>

Build Log:
Compilation of lenovo:x60 has been fixed


If something broke during this checkin please be a pain 
in svens's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From anish.mailing.list at gmail.com  Mon Mar 14 20:42:25 2011
From: anish.mailing.list at gmail.com (Anish Patel)
Date: Mon, 14 Mar 2011 15:42:25 -0400
Subject: [coreboot] intel atom + us15
In-Reply-To: <4D7E6A28.3040002@gmail.com>
References: <4D7E6A28.3040002@gmail.com>
Message-ID: <4D7E6FA1.2080700@gmail.com>

On 03/14/11 15:19, Anish Patel wrote:
> Hi All,
>     I am trying to get coreboot running on my PC/104+ atom  board.  I 
> think i have everything pretty much good to go, except for one problem.
> When i try to build, it says it can't find my cmc.bin file, which i 
> have extracted from the factory bios and placed in many different 
> locations inside the coreboot build tree.  As well as tell coreboot 
> the location of the cmc.bin file, yet everytime i build i get this error.
>
>
>     GEN        bootblock/ldscript.ld
>     LINK       bootblock.elf
>     OBJCOPY    coreboot.bootblock
> make: *** No rule to make target `"cmc.bin"', needed by 
> `build/coreboot.pre1'.  Stop.
>
>
> any hints on where to place this file would be greatly appreciared.  
> as a note, i have made a oprom directory in the coreboot root.  this 
> place hold my vgabios.bin which the coreboot build system find an 
> links properly.
>
>
> thanks
> anish
>
i have found the problem
reverting back the the Makefile.inc from r6199 for the sch fixed the 
problem.

thanks
anish




From anish.mailing.list at gmail.com  Mon Mar 14 20:19:04 2011
From: anish.mailing.list at gmail.com (Anish Patel)
Date: Mon, 14 Mar 2011 15:19:04 -0400
Subject: [coreboot] intel atom + us15
Message-ID: <4D7E6A28.3040002@gmail.com>

Hi All,
     I am trying to get coreboot running on my PC/104+ atom  board.  I 
think i have everything pretty much good to go, except for one problem.
When i try to build, it says it can't find my cmc.bin file, which i have 
extracted from the factory bios and placed in many different locations 
inside the coreboot build tree.  As well as tell coreboot the location 
of the cmc.bin file, yet everytime i build i get this error.


     GEN        bootblock/ldscript.ld
     LINK       bootblock.elf
     OBJCOPY    coreboot.bootblock
make: *** No rule to make target `"cmc.bin"', needed by 
`build/coreboot.pre1'.  Stop.


any hints on where to place this file would be greatly appreciared.  as 
a note, i have made a oprom directory in the coreboot root.  this place 
hold my vgabios.bin which the coreboot build system find an links properly.


thanks
anish




From svens at stackframe.org  Tue Mar 15 09:41:12 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 15 Mar 2011 09:41:12 +0100
Subject: [coreboot] [PATCH 2/2] X60: Clear EC events when wake GPE is
	triggered
In-Reply-To: <1300178472-7948-1-git-send-email-svens@stackframe.org>
References: <1300178472-7948-1-git-send-email-svens@stackframe.org>
Message-ID: <1300178472-7948-2-git-send-email-svens@stackframe.org>

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/x60/acpi/ec.asl  |    2 ++
 src/mainboard/lenovo/x60/acpi/gpe.asl |    8 ++++++++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl
index ec5c6ab..7e2b94d 100644
--- a/src/mainboard/lenovo/x60/acpi/ec.asl
+++ b/src/mainboard/lenovo/x60/acpi/ec.asl
@@ -37,6 +37,8 @@ Device(EC)
 		Offset (0x3B),
 				    , 1,
 				KBLT, 1,        /* Keyboard Light */
+		Offset (0x4e),
+		               WAKE, 16,
 		Offset (0x78),
 				TMP0, 8,	/* Thermal Zone 0 temperature */
 				TMP1, 8,	/* Thermal Zone 1 temperature */
diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl
index e69de29..1c5d1bd 100644
--- a/src/mainboard/lenovo/x60/acpi/gpe.asl
+++ b/src/mainboard/lenovo/x60/acpi/gpe.asl
@@ -0,0 +1,8 @@
+Scope (\_GPE)
+{
+	Method(_L18, 0, NotSerialized)
+	{
+		/* Read EC register to clear wake status */
+		Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
+	}
+}
-- 
1.7.4.1




From svens at stackframe.org  Tue Mar 15 09:41:11 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 15 Mar 2011 09:41:11 +0100
Subject: [coreboot] [PATCH 1/2] ACPI EC: add ec_query function
Message-ID: <1300178472-7948-1-git-send-email-svens@stackframe.org>

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/ec/acpi/ec.c |    6 ++++++
 src/ec/acpi/ec.h |    1 +
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
index 1d4ffb8..2680aa3 100644
--- a/src/ec/acpi/ec.c
+++ b/src/ec/acpi/ec.c
@@ -116,6 +116,12 @@ int ec_write(u8 addr, u8 data)
 	return send_ec_data(data);
 }
 
+u8 ec_query(void)
+{
+	send_ec_command(0x84);
+	return recv_ec_data();
+}
+
 void ec_set_bit(u8 addr, u8 bit)
 {
 	ec_write(addr, ec_read(addr) | (1 << bit));
diff --git a/src/ec/acpi/ec.h b/src/ec/acpi/ec.h
index b5a1197..8fc88d2 100644
--- a/src/ec/acpi/ec.h
+++ b/src/ec/acpi/ec.h
@@ -42,6 +42,7 @@ int send_ec_command(u8 command);
 int send_ec_data(u8 data);
 int send_ec_data_nowait(u8 data);
 u8 recv_ec_data(void);
+u8 ec_query(void);
 u8 ec_read(u8 addr);
 int ec_write(u8 addr, u8 data);
 void ec_set_bit(u8 addr, u8 bit);
-- 
1.7.4.1




From peter at stuge.se  Tue Mar 15 10:42:26 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 15 Mar 2011 10:42:26 +0100
Subject: [coreboot] [PATCH 1/2] ACPI EC: add ec_query function
In-Reply-To: <1300178472-7948-1-git-send-email-svens@stackframe.org>
References: <1300178472-7948-1-git-send-email-svens@stackframe.org>
Message-ID: <20110315094227.26880.qmail@stuge.se>

Sven Schnelle wrote:
> Signed-off-by: Sven Schnelle <svens at stackframe.org>

Acked-by: Peter Stuge <peter at stuge.se>



From peter at stuge.se  Tue Mar 15 10:42:29 2011
From: peter at stuge.se (Peter Stuge)
Date: Tue, 15 Mar 2011 10:42:29 +0100
Subject: [coreboot] [PATCH 2/2] X60: Clear EC events when wake GPE
	is	triggered
In-Reply-To: <1300178472-7948-2-git-send-email-svens@stackframe.org>
References: <1300178472-7948-1-git-send-email-svens@stackframe.org>
	<1300178472-7948-2-git-send-email-svens@stackframe.org>
Message-ID: <20110315094229.26910.qmail@stuge.se>

Sven Schnelle wrote:
> Signed-off-by: Sven Schnelle <svens at stackframe.org>

Acked-by: Peter Stuge <peter at stuge.se>



From Patrick.Georgi at secunet.com  Tue Mar 15 10:47:04 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Tue, 15 Mar 2011 10:47:04 +0100
Subject: [coreboot] [PATCH]More flexibility for coreboot version string
In-Reply-To: <1299578757.2459.18.camel@linux-0a8x.site>
References: <1299578757.2459.18.camel@linux-0a8x.site>
Message-ID: <1300182425.2420.1.camel@linux-0a8x.site>

Am Dienstag, den 08.03.2011, 11:05 +0100 schrieb Georgi, Patrick:
> attached patch improves flexibility on coreboot version strings in the
> final binary. See attachment for details.
ping? (http://patchwork.coreboot.org/patch/2754/)
-- 
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
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From svn at coreboot.org  Tue Mar 15 10:52:08 2011
From: svn at coreboot.org (repository service)
Date: Tue, 15 Mar 2011 10:52:08 +0100
Subject: [coreboot] [commit] r6447 - trunk/src/ec/acpi
Message-ID: <E1PzQvA-0006wo-6U@ra.coresystems.de>

Author: svens
Date: Tue Mar 15 10:52:07 2011
New Revision: 6447
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6447

Log:
ACPI EC: add ec_query function

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/ec/acpi/ec.c
   trunk/src/ec/acpi/ec.h

Modified: trunk/src/ec/acpi/ec.c
==============================================================================
--- trunk/src/ec/acpi/ec.c	Mon Mar 14 16:23:44 2011	(r6446)
+++ trunk/src/ec/acpi/ec.c	Tue Mar 15 10:52:07 2011	(r6447)
@@ -116,6 +116,12 @@
 	return send_ec_data(data);
 }
 
+u8 ec_query(void)
+{
+	send_ec_command(0x84);
+	return recv_ec_data();
+}
+
 void ec_set_bit(u8 addr, u8 bit)
 {
 	ec_write(addr, ec_read(addr) | (1 << bit));

Modified: trunk/src/ec/acpi/ec.h
==============================================================================
--- trunk/src/ec/acpi/ec.h	Mon Mar 14 16:23:44 2011	(r6446)
+++ trunk/src/ec/acpi/ec.h	Tue Mar 15 10:52:07 2011	(r6447)
@@ -42,6 +42,7 @@
 int send_ec_data(u8 data);
 int send_ec_data_nowait(u8 data);
 u8 recv_ec_data(void);
+u8 ec_query(void);
 u8 ec_read(u8 addr);
 int ec_write(u8 addr, u8 data);
 void ec_set_bit(u8 addr, u8 bit);



From svn at coreboot.org  Tue Mar 15 10:52:17 2011
From: svn at coreboot.org (repository service)
Date: Tue, 15 Mar 2011 10:52:17 +0100
Subject: [coreboot] [commit] r6448 - trunk/src/mainboard/lenovo/x60/acpi
Message-ID: <E1PzQvJ-00070X-Vv@ra.coresystems.de>

Author: svens
Date: Tue Mar 15 10:52:17 2011
New Revision: 6448
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6448

Log:
X60: Clear EC events when wake GPE is triggered

Signed-off-by: Sven Schnelle <svens at stackframe.org>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/mainboard/lenovo/x60/acpi/ec.asl
   trunk/src/mainboard/lenovo/x60/acpi/gpe.asl

Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/acpi/ec.asl	Tue Mar 15 10:52:07 2011	(r6447)
+++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl	Tue Mar 15 10:52:17 2011	(r6448)
@@ -37,6 +37,8 @@
 		Offset (0x3B),
 				    , 1,
 				KBLT, 1,        /* Keyboard Light */
+		Offset (0x4e),
+		               WAKE, 16,
 		Offset (0x78),
 				TMP0, 8,	/* Thermal Zone 0 temperature */
 				TMP1, 8,	/* Thermal Zone 1 temperature */

Modified: trunk/src/mainboard/lenovo/x60/acpi/gpe.asl
==============================================================================
--- trunk/src/mainboard/lenovo/x60/acpi/gpe.asl	Tue Mar 15 10:52:07 2011	(r6447)
+++ trunk/src/mainboard/lenovo/x60/acpi/gpe.asl	Tue Mar 15 10:52:17 2011	(r6448)
@@ -0,0 +1,8 @@
+Scope (\_GPE)
+{
+	Method(_L18, 0, NotSerialized)
+	{
+		/* Read EC register to clear wake status */
+		Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
+	}
+}



From svens at stackframe.org  Tue Mar 15 15:30:10 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 15 Mar 2011 15:30:10 +0100
Subject: [coreboot] [PATCH] X60: remove beep call from _Q26/_Q27
Message-ID: <1300199410-6701-1-git-send-email-svens@stackframe.org>

no need to trigger sound, the EC takes care of generating the annoying
AC state beep if enabled in the sound mask.

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/x60/acpi/ec.asl |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl
index 7e2b94d..c805e5a 100644
--- a/src/mainboard/lenovo/x60/acpi/ec.asl
+++ b/src/mainboard/lenovo/x60/acpi/ec.asl
@@ -87,14 +87,12 @@ Device(EC)
 	Method(_Q26, 0, NotSerialized)
 	{
 		Notify (AC, 0x80)
-		Beep(6)
 	}
 
 	/* AC status change: not present */
 	Method(_Q27, 0, NotSerialized)
 	{
 		Notify (AC, 0x80)
-		Beep(6)
 	}
 
 
-- 
1.7.4.1




From svens at stackframe.org  Tue Mar 15 22:25:50 2011
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 15 Mar 2011 22:25:50 +0100
Subject: [coreboot] [PATCH] X60: Add notifications for LID objects
Message-ID: <1300224350-2969-1-git-send-email-svens@stackframe.org>

Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/x60/acpi/ec.asl |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl
index 7e2b94d..2318817 100644
--- a/src/mainboard/lenovo/x60/acpi/ec.asl
+++ b/src/mainboard/lenovo/x60/acpi/ec.asl
@@ -97,6 +97,16 @@ Device(EC)
 		Beep(6)
 	}
 
+	Method(_Q2A, 0, NotSerialized)
+	{
+		Notify(\_SB.PCI0.LPCB.EC.LID, 0x80)
+	}
+
+	Method(_Q2B, 0, NotSerialized)
+	{
+		Notify(\_SB.PCI0.LPCB.EC.LID, 0x80)
+	}
+
 
 #include "ac.asl"
 #include "battery.asl"
-- 
1.7.4.1




From stefan.reinauer at coreboot.org  Tue Mar 15 23:01:49 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 15 Mar 2011 23:01:49 +0100
Subject: [coreboot] intel atom + us15
In-Reply-To: <4D7E6FA1.2080700@gmail.com>
References: <4D7E6A28.3040002@gmail.com>
 <4D7E6FA1.2080700@gmail.com>
Message-ID: <20110315220148.GA631@coreboot.org>

* Anish Patel <anish.mailing.list at gmail.com> [110314 20:42]:
> On 03/14/11 15:19, Anish Patel wrote:
> >Hi All,
> >    I am trying to get coreboot running on my PC/104+ atom  board.
> >I think i have everything pretty much good to go, except for one
> >problem.
> >When i try to build, it says it can't find my cmc.bin file, which
> >i have extracted from the factory bios and placed in many
> >different locations inside the coreboot build tree.  As well as
> >tell coreboot the location of the cmc.bin file, yet everytime i
> >build i get this error.
> >
> >
> >    GEN        bootblock/ldscript.ld
> >    LINK       bootblock.elf
> >    OBJCOPY    coreboot.bootblock
> >make: *** No rule to make target `"cmc.bin"', needed by
> >`build/coreboot.pre1'.  Stop.
> >
> >
> >any hints on where to place this file would be greatly
> >appreciared.  as a note, i have made a oprom directory in the
> >coreboot root.  this place hold my vgabios.bin which the coreboot
> >build system find an links properly.
> >
> >
> >thanks
> >anish
> >
> i have found the problem
> reverting back the the Makefile.inc from r6199 for the sch fixed the
> problem.

Which Makefile.inc. Can you please send a patch?
 



From stefan.reinauer at coreboot.org  Tue Mar 15 23:04:36 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Tue, 15 Mar 2011 23:04:36 +0100
Subject: [coreboot] [DirectHW] [commit] r1 - branches tags trunk
 trunk/macosx trunk/macosx/DirectHW	trunk/macosx/DirectHW/DirectHW.pmdoc
 trunk/macosx/DirectHW/DirectHW.xcodeproj	trunk/macosx/DirectHW/build
 trunk/macos...
In-Reply-To: <20110314091143.25268.qmail@stuge.se>
References: <E1PyxPv-0002ri-Sp@ra.coresystems.de>
	<20110314091143.25268.qmail@stuge.se>
Message-ID: <20110315220436.GA22181@coreboot.org>

* Peter Stuge <peter at stuge.se> [110314 10:11]:
> repository service wrote:
> > Added:
> >    trunk/macosx/patches/msrtool-r6440.diff
> 
> svn rm:ed this but could not commit to DirectHW. Patch has been
> applied upstream.

Commit permissions added. 




From andrey at zonov.org  Sun Mar 13 16:05:13 2011
From: andrey at zonov.org (Andrey Zonov)
Date: Sun, 13 Mar 2011 18:05:13 +0300
Subject: [coreboot] Does nvramtool have snapshots or releases tarballs?
Message-ID: <4D7CDD29.5020005@zonov.org>

Hi,

I'm making FreeBSD port of nvramtool and I don't want to download full 
coreboot snapshot to build only nvramtool. Where can I find snapshots of 
nvramtool only? If you don't separate that things, don't you mind if I 
will make snapshots by myself and put it on my website (and freebsd.org 
maybe)?

Thanks.

-- 
Andrey Zonov




From stefan.reinauer at coreboot.org  Wed Mar 16 05:50:09 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 16 Mar 2011 05:50:09 +0100
Subject: [coreboot] [PATCH]More flexibility for coreboot version string
In-Reply-To: <1299578757.2459.18.camel@linux-0a8x.site>
References: <1299578757.2459.18.camel@linux-0a8x.site>
Message-ID: <20110316045009.GA25100@coreboot.org>

* Georgi, Patrick <Patrick.Georgi at secunet.com> [110308 11:05]:
> Hi,
> 
> attached patch improves flexibility on coreboot version strings in the
> final binary. See attachment for details.
> -- 
> Patrick Georgi
> SINA-Development - High Security
> secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
> Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 
> 
> Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
> Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
> Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

> commit 5d8fbe10ad1fb834874148a3e6adb01515362e35
> Author: Patrick Georgi <Patrick.Georgi at secunet.com>
> Date:   Tue Mar 8 10:56:34 2011 +0100
> 
>     More complete control over KERNELVERSION variable
>     
>     Allow using revision information (from svn or git) even if the version
>     number is changed on the command line
>     (eg. make KERNELVERSION='11.03$(REV)') or dropping it entirely if having
>     that information in the coreboot binary is not desired.
>     
>     Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>




From stefan.reinauer at coreboot.org  Wed Mar 16 05:56:00 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 16 Mar 2011 05:56:00 +0100
Subject: [coreboot] Does nvramtool have snapshots or releases tarballs?
In-Reply-To: <4D7CDD29.5020005@zonov.org>
References: <4D7CDD29.5020005@zonov.org>
Message-ID: <20110316045600.GA26599@coreboot.org>

* Andrey Zonov <andrey at zonov.org> [110313 16:05]:
> Hi,
> 
> I'm making FreeBSD port of nvramtool and I don't want to download
> full coreboot snapshot to build only nvramtool. Where can I find
> snapshots of nvramtool only? If you don't separate that things,
> don't you mind if I will make snapshots by myself and put it on my
> website (and freebsd.org maybe)?
> 
> Thanks.

You can download specific releases of subtrees through trac:
http://tracker.coreboot.org/trac/coreboot/changeset/6448/trunk/util/nvramtool?old_path=%2F&old=6448&format=zip

Some snapshots are kept here:
http://qa.coreboot.org/snapshots/

Other than that there are no separate archives for sub projects.

If this helps you, feel free to host them on your website. But a
complete coreboot tree bzipped is only 4.5MB, so it's not incredibly
big.

Stefan




From Zheng.Bao at amd.com  Wed Mar 16 09:38:09 2011
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Wed, 16 Mar 2011 16:38:09 +0800
Subject: [coreboot] What is needed in dsdt to enable S4(Besides \_S4)
Message-ID: <DD1CC71B621B004FA76856E5129D6B1704B26872@sbjgexmb1.amd.com>

I have \_S4 in my dsdt.asl.  But the dmesg only reports:

ACPI: (supports S0 S1 S2 S3 S5)

 

And cat /sys/power/state only says:

Standby mem

 

So what else is needed?

 

Thanks.

 

Zheng

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From ranma+coreboot at tdiedrich.de  Wed Mar 16 17:49:07 2011
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 16 Mar 2011 17:49:07 +0100
Subject: [coreboot] What is needed in dsdt to enable S4(Besides \_S4)
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1704B26872@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B1704B26872@sbjgexmb1.amd.com>
Message-ID: <20110316164906.GG29032@yumi.tdiedrich.de>

Bao, Zheng wrote:
> I have \_S4 in my dsdt.asl.  But the dmesg only reports:
> 
> ACPI: (supports S0 S1 S2 S3 S5)
> 
>  
> 
> And cat /sys/power/state only says:
> 
> Standby mem

S4 is not used for suspend to disk in Linux AFAIK.
You just need to compile in suspend to disk support and specify a
resume partition on the kernel command line (Usually your swap
partition).

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From stefan.reinauer at coreboot.org  Wed Mar 16 19:21:24 2011
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 16 Mar 2011 19:21:24 +0100
Subject: [coreboot] What is needed in dsdt to enable S4(Besides \_S4)
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1704B26872@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B1704B26872@sbjgexmb1.amd.com>
Message-ID: <20110316182124.GA24856@coreboot.org>

* Bao, Zheng <Zheng.Bao at amd.com> [110316 09:38]:
> I have \_S4 in my dsdt.asl.  But the dmesg only reports:
> 
> ACPI: (supports S0 S1 S2 S3 S5)
 

> So what else is needed?
 
I think you also need to add S4BIOS_REQ in the FADT and implement an SMM
handler to handle it.

You don't need that for software suspend to disk though

Stefan




From kh.nirschl at googlemail.com  Wed Mar 16 20:44:06 2011
From: kh.nirschl at googlemail.com (Karl-Heinz Nirschl)
Date: Wed, 16 Mar 2011 20:44:06 +0100
Subject: [coreboot] intel atom + us15
In-Reply-To: <20110315220148.GA631@coreboot.org>
References: <4D7E6A28.3040002@gmail.com> <4D7E6FA1.2080700@gmail.com>
	<20110315220148.GA631@coreboot.org>
Message-ID: <AANLkTik6U6SfEdoARSk2QNDULoO52YGjRqUOj-fJYZ2N@mail.gmail.com>

Hi,
i think the following patch should do the trick:


---
Index: src/southbridge/intel/sch/Makefile.inc
===================================================================
--- src/southbridge/intel/sch/Makefile.inc	(Revision 6439)
+++ src/southbridge/intel/sch/Makefile.inc	(Arbeitskopie)
@@ -37,6 +37,6 @@

 # We don't ship that, but booting without it is bound to fail
 cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin
-cmc.bin-file := $(CONFIG_CMC_FILE)
+cmc.bin-file := $(call strip_quotes,$(CONFIG_CMC_FILE))
 cmc.bin-type := 0xaa
 cmc.bin-position := 0xfffd0000
---


best regards,




2011/3/15 Stefan Reinauer <stefan.reinauer at coreboot.org>:
> * Anish Patel <anish.mailing.list at gmail.com> [110314 20:42]:
>> On 03/14/11 15:19, Anish Patel wrote:
>> >Hi All,
>> > ? ?I am trying to get coreboot running on my PC/104+ atom ?board.
>> >I think i have everything pretty much good to go, except for one
>> >problem.
>> >When i try to build, it says it can't find my cmc.bin file, which
>> >i have extracted from the factory bios and placed in many
>> >different locations inside the coreboot build tree. ?As well as
>> >tell coreboot the location of the cmc.bin file, yet everytime i
>> >build i get this error.
>> >
>> >
>> > ? ?GEN ? ? ? ?bootblock/ldscript.ld
>> > ? ?LINK ? ? ? bootblock.elf
>> > ? ?OBJCOPY ? ?coreboot.bootblock
>> >make: *** No rule to make target `"cmc.bin"', needed by
>> >`build/coreboot.pre1'. ?Stop.
>> >
>> >
>> >any hints on where to place this file would be greatly
>> >appreciared. ?as a note, i have made a oprom directory in the
>> >coreboot root. ?this place hold my vgabios.bin which the coreboot
>> >build system find an links properly.
>> >
>> >
>> >thanks
>> >anish
>> >
>> i have found the problem
>> reverting back the the Makefile.inc from r6199 for the sch fixed the
>> problem.
>
> Which Makefile.inc. Can you please send a patch?
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From njacobs8 at hetnet.nl  Wed Mar 16 22:46:29 2011
From: njacobs8 at hetnet.nl (Nils)
Date: Wed, 16 Mar 2011 22:46:29 +0100
Subject: [coreboot] JCALG1 archive
Message-ID: <201103162246.29268.njacobs8@hetnet.nl>

Hello All,
I have a rom image witch contains an JCALG1 archive.
I would like to know what it contains , does anyone know of a ready to use 
tool that can extract an JCALG1 archive?

Thanks, Nils.



From mr.mylanman at gmail.com  Wed Mar 16 23:27:34 2011
From: mr.mylanman at gmail.com (Mylan Connolly)
Date: Wed, 16 Mar 2011 18:27:34 -0400
Subject: [coreboot] Checking compatibility - Biostar TA890GXE
Message-ID: <AANLkTinf+Zq34Are=_f86hmVsW-3a86=+c-ifRYQ3i-D@mail.gmail.com>

Hello all;

I was mailing to see about the future possibility about CoreBoot working on
my motherboard.

My PC is a custom-built machine with the following hardware:

CPU:    AMD Phenom II X6 1055T
MB:    Biostar T-Power TA890GXE
RAM:    4GB DDR3
Video:    nVidia GTX260 (I also have an nVidia GTX460, but the GTX260 seems
to play with Nouveau better)
HD:    2TB Hitachi, 640GB Western Digital

[mylan at arch-desktop ~]$ lspci -tvnn
-[0000:00]-+-00.0  Advanced Micro Devices [AMD] RS880 Host Bridge
[1022:9601]
           +-02.0-[01]----00.0  nVidia Corporation GT200 [GeForce GTX 260]
[10de:05e2]
           +-05.0-[04]--+-00.0  VIA Technologies, Inc. VT6315 Series
Firewire Controller [1106:3403]
           |            \-00.1  VIA Technologies, Inc. VT6415 PATA IDE Host
Controller [1106:0415]
           +-06.0-[02]----00.0  Realtek Semiconductor Co., Ltd.
RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168]
           +-11.0  ATI Technologies Inc SB700/SB800 SATA Controller [IDE
mode] [1002:4390]
           +-12.0  ATI Technologies Inc SB700/SB800 USB OHCI0 Controller
[1002:4397]
           +-12.2  ATI Technologies Inc SB700/SB800 USB EHCI Controller
[1002:4396]
           +-13.0  ATI Technologies Inc SB700/SB800 USB OHCI0 Controller
[1002:4397]
           +-13.2  ATI Technologies Inc SB700/SB800 USB EHCI Controller
[1002:4396]
           +-14.0  ATI Technologies Inc SBx00 SMBus Controller [1002:4385]
           +-14.1  ATI Technologies Inc SB700/SB800 IDE Controller
[1002:439c]
           +-14.2  ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383]
           +-14.3  ATI Technologies Inc SB700/SB800 LPC host controller
[1002:439d]
           +-14.4-[03]--
           +-14.5  ATI Technologies Inc SB700/SB800 USB OHCI2 Controller
[1002:4399]
           +-16.0  ATI Technologies Inc SB700/SB800 USB OHCI0 Controller
[1002:4397]
           +-16.2  ATI Technologies Inc SB700/SB800 USB EHCI Controller
[1002:4396]
           +-18.0  Advanced Micro Devices [AMD] Family 10h Processor
HyperTransport Configuration [1022:1200]
           +-18.1  Advanced Micro Devices [AMD] Family 10h Processor Address
Map [1022:1201]
           +-18.2  Advanced Micro Devices [AMD] Family 10h Processor DRAM
Controller [1022:1202]
           +-18.3  Advanced Micro Devices [AMD] Family 10h Processor
Miscellaneous Control [1022:1203]
           \-18.4  Advanced Micro Devices [AMD] Family 10h Processor Link
Control [1022:1204]

[mylan at arch-desktop ~]$ sudo superiotool -dV
Password:
superiotool r6433
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x2e...
Found ITE IT8721F (id=0x8721, rev=0x1) at 0x2e
No dump available for this Super I/O
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x164e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e...
  Failed. Returned data: sid=0xff, id=0x00, rev=0x00
Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e...
  Failed. Returned data: sid=0xff, id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for VIA Super I/O at 0x3f0...
  PCI device 1106:0686 not found.

[mylan at arch-desktop ~]$ sudo flashrom -V
flashrom v0.9.3-r1205 on Linux 2.6.37-ARCH (x86_64), built with libpci
3.1.7, GCC 4.5.2 20110127 (prerelease), little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 1 usecs, 851M loops per
second, 10 myus = 9 us, 100 myus = 91 us, 1000 myus = 912 us, 10000 myus =
9139 us, 4 myus = 4 us, OK.
Initializing internal programmer
No coreboot table found.
sh: dmidecode: command not found
dmidecode execution unsucessfull - continuing without DMI info
Found ITE Super I/O, ID 0x8721.
Found chipset "AMD SB700/SB710/SB750", enabling flash write... chipset PCI
ID is 1002:439d, SPI base address is at 0xfec10000
AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0
PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1
SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=7,
SpiBridgeDisable=1, DropOneClkOnRd=0
NormSpeed is 33 MHz
GPIO11 used for SPI_DO
GPIO12 used for SPI_DI
GPIO31 used for SPI_HOLD
GPIO32 used for SPI_CS
GPIO47 used for SPI_CLK
SB700 IMC is not active.
ROM strap override is not active
OK.
This chipset supports the following protocols: LPC,FWH,SPI.
Super I/O ID 0x8721 is not on the list of flash capable controllers.
Probing for AMD Am29F010A/B, 128 KB: skipped.
Probing for AMD Am29F002(N)BB, 256 KB: skipped.
Probing for AMD Am29F002(N)BT, 256 KB: skipped.
Probing for AMD Am29F016D, 2048 KB: skipped.
Probing for AMD Am29F040B, 512 KB: skipped.
Probing for AMD Am29F080B, 1024 KB: skipped.
Probing for AMD Am29LV040B, 512 KB: skipped.
Probing for AMD Am29LV081B, 1024 KB: skipped.
Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for AMIC A29002B, 256 KB: skipped.
Probing for AMIC A29002T, 256 KB: skipped.
Probing for AMIC A29040B, 512 KB: skipped.
Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x03, id2 0x52,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT29C512, 64 KB: skipped.
Probing for Atmel AT29C010A, 128 KB: skipped.
Probing for Atmel AT29C020, 256 KB: skipped.
Probing for Atmel AT29C040A, 512 KB: skipped.
Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Atmel AT49BV512, 64 KB: skipped.
Probing for Atmel AT49F020, 256 KB: skipped.
Probing for Atmel AT49F002(N), 256 KB: skipped.
Probing for Atmel AT49F002(N)T, 256 KB: skipped.
Probing for Bright BM29F040, 512 KB: skipped.
Probing for EMST F49B002UA, 256 KB: skipped.
Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014
Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014
Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Eon EN29F010, 128 KB: skipped.
Probing for Eon EN29F002(A)(N)B, 256 KB: skipped.
Probing for Eon EN29F002(A)(N)T, 256 KB: skipped.
Probing for Fujitsu MBM29F004BC, 512 KB: skipped.
Probing for Fujitsu MBM29F004TC, 512 KB: skipped.
Probing for Fujitsu MBM29F400BC, 512 KB: skipped.
Probing for Fujitsu MBM29F400TC, 512 KB: skipped.
Probing for Hyundai HY29F002T, 256 KB: skipped.
Probing for Hyundai HY29F002B, 256 KB: skipped.
Probing for Hyundai HY29F040A, 512 KB: skipped.
Probing for Intel 28F001BN/BX-B, 128 KB: skipped.
Probing for Intel 28F001BN/BX-T, 128 KB: skipped.
Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped.
Probing for Intel 28F008S3/S5/SC, 512 KB: skipped.
Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped.
Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped.
Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped.
Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped.
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x03, id2 0x52, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Macronix MX29F001B, 128 KB: skipped.
Probing for Macronix MX29F001T, 128 KB: skipped.
Probing for Macronix MX29F002B, 256 KB: skipped.
Probing for Macronix MX29F002T, 256 KB: skipped.
Probing for Macronix MX29F040, 512 KB: skipped.
Probing for Macronix MX29LV040, 512 KB: skipped.
Probing for MoselVitelic V29C51000B, 64 KB: skipped.
Probing for MoselVitelic V29C51000T, 64 KB: skipped.
Probing for MoselVitelic V29C51400B, 512 KB: skipped.
Probing for MoselVitelic V29C51400T, 512 KB: skipped.
Probing for MoselVitelic V29LC51000, 64 KB: skipped.
Probing for MoselVitelic V29LC51001, 128 KB: skipped.
Probing for MoselVitelic V29LC51002, 256 KB: skipped.
Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for PMC Pm29F002T, 256 KB: skipped.
Probing for PMC Pm29F002B, 256 KB: skipped.
Probing for PMC Pm39LV010, 128 KB: skipped.
Probing for PMC Pm39LV020, 256 KB: skipped.
Probing for PMC Pm39LV040, 512 KB: skipped.
Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x26, id2 0x7e,
id1 is normal flash content, id2 is normal flash content
Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x03, id2 0x52,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13
Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13
Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13
Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for SST SST28SF040A, 512 KB: skipped.
Probing for SST SST29EE010, 128 KB: skipped.
Probing for SST SST29LE010, 128 KB: skipped.
Probing for SST SST29EE020A, 256 KB: skipped.
Probing for SST SST29LE020, 256 KB: skipped.
Probing for SST SST39SF512, 64 KB: skipped.
Probing for SST SST39SF010A, 128 KB: skipped.
Probing for SST SST39SF020A, 256 KB: skipped.
Probing for SST SST39SF040, 512 KB: skipped.
Probing for SST SST39VF512, 64 KB: skipped.
Probing for SST SST39VF010, 128 KB: skipped.
Probing for SST SST39VF020, 256 KB: skipped.
Probing for SST SST39VF040, 512 KB: skipped.
Probing for SST SST39VF080, 1024 KB: skipped.
Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0x26, id2
0x7e, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x51, id2
0x4d, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x03, id2
0x52, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x03, id2 0x52, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x26, id2 0x7e,
id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x26, id2 0x7e,
id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x03, id2 0x52,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x03, id2 0x52,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014
Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID.
Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID.
Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014
Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014
Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID.
Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014
Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014
Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014
Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014
Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for ST M29F002B, 256 KB: skipped.
Probing for ST M29F002T/NT, 256 KB: skipped.
Probing for ST M29F040B, 512 KB: skipped.
Probing for ST M29F400BB, 512 KB: skipped.
Probing for ST M29F400BT, 512 KB: skipped.
Probing for ST M29W010B, 128 KB: skipped.
Probing for ST M29W040B, 512 KB: skipped.
Probing for ST M29W512B, 64 KB: skipped.
Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x03, id2 0x52, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x03, id2 0x52, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x26, id2 0x7e, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x03, id2 0x52, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped.
Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped.
Probing for TI TMS29F002RB, 256 KB: skipped.
Probing for TI TMS29F002RT, 256 KB: skipped.
Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Chip status register is 00
Found chip "Winbond W25Q80" (1024 KB, SPI) at physical address 0xfff00000.
Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2
0x4014
Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped.
Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped.
Probing for Winbond W29C040/P, 512 KB: skipped.
Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped.
Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x03, id2
0x52, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W39V040(F)B, 512 KB: probe_jedec_common: id1 0x03, id2
0x52, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W39V040(F)C, 512 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec_common: id1 0x03, id2
0x52, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x03, id2
0x52, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W49F002U/N, 256 KB: skipped.
Probing for Winbond W49F020, 256 KB: skipped.
Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x26, id2
0x7e, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0x26, id2
0x7e, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe
timing information, using default 10mS/40uS. probe_jedec_common: id1 0x03,
id2 0x52, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xef, id2 0x4014
Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xef, id2 0x4014
Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xef, id2 0x4014
Probing for Macronix unknown Macronix SPI chip, 0 KB:
probe_spi_rdid_generic: id1 0xef, id2 0x4014
Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xef, id2 0x4014
Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xef, id2 0x4014
Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef,
id2 0x4014
Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1
0xef, id2 0x4014
Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic:
id1 0xef, id2 0x4014
Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xef,
id2 0x13
No operations were specified

Biostar TA890GXE Version 5.2
http://www.biostar.com.tw/app/en/mb/content.php?S_ID=475

I am running Arch Linux, I'm not sure what other information is needed, but
please let me know if this could be working at some point on this board, I'd
really love to ditch the proprietary BIOS if possible, although if not then
that is certainly understandable!  Thanks for the hard work, it looks like
an incredible project!

Mylan
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From svn at coreboot.org  Thu Mar 17 08:47:49 2011
From: svn at coreboot.org (repository service)
Date: Thu, 17 Mar 2011 08:47:49 +0100
Subject: [coreboot] [commit] r6449 - trunk
Message-ID: <E1Q07vx-0001UE-Gr@ra.coresystems.de>

Author: oxygene
Date: Thu Mar 17 08:47:49 2011
New Revision: 6449
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6449

Log:
More complete control over KERNELVERSION variable

Allow using revision information (from svn or git) even if the version
number is changed on the command line (eg. make KERNELVERSION='11.03$(REV)')
or dropping it entirely if having that information in the coreboot binary is
not desired.

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/Makefile.inc

Modified: trunk/Makefile.inc
==============================================================================
--- trunk/Makefile.inc	Tue Mar 15 10:52:17 2011	(r6448)
+++ trunk/Makefile.inc	Thu Mar 17 08:47:49 2011	(r6449)
@@ -19,7 +19,8 @@
 
 #######################################################################
 # misleadingly named, this is the coreboot version
-export KERNELVERSION      := 4.0
+REV=-r$(shell if [ -d $(top)/.svn -a -f "`which svnversion`" ]; then svnversion $(top); else if [ -d $(top)/.git -a -f "`which git`" ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)
+export KERNELVERSION      := 4.0$(REV)
 
 #######################################################################
 # Basic component discovery
@@ -123,7 +124,7 @@
 	printf "/* build system definitions (autogenerated) */\n" > $(obj)/build.ht
 	printf "#ifndef __BUILD_H\n" >> $(obj)/build.ht
 	printf "#define __BUILD_H\n\n" >> $(obj)/build.ht
-	printf "#define COREBOOT_VERSION \"$(KERNELVERSION)-r$(shell if [ -d $(top)/.svn -a -f "`which svnversion`" ]; then svnversion $(top); else if [ -d $(top)/.git -a -f "`which git`" ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)\"\n" >> $(obj)/build.ht
+	printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht
 	printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht
 	printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht
 	printf "\n" >> $(obj)/build.ht



From svn at coreboot.org  Thu Mar 17 13:20:05 2011
From: svn at coreboot.org (repository service)
Date: Thu, 17 Mar 2011 13:20:05 +0100
Subject: [coreboot] [commit] r6450 - trunk/payloads/libpayload/libc
Message-ID: <E1Q0CBR-0001ou-GC@ra.coresystems.de>

Author: oxygene
Date: Thu Mar 17 13:20:04 2011
New Revision: 6450
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6450

Log:
libpayload: fix string-to-numeric functions for base > 10

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/payloads/libpayload/libc/string.c

Modified: trunk/payloads/libpayload/libc/string.c
==============================================================================
--- trunk/payloads/libpayload/libc/string.c	Thu Mar 17 08:47:49 2011	(r6449)
+++ trunk/payloads/libpayload/libc/string.c	Thu Mar 17 13:20:04 2011	(r6450)
@@ -407,7 +407,7 @@
         if (ch >= '0' && ch <= '9')
                 return ch - '0';
         else
-                return tolower(ch) - 'a';
+                return 10 + tolower(ch) - 'a';
 }
 
 /**



From svn at coreboot.org  Thu Mar 17 13:34:16 2011
From: svn at coreboot.org (repository service)
Date: Thu, 17 Mar 2011 13:34:16 +0100
Subject: [coreboot] [commit] r6451 - trunk/src/southbridge/amd/sb600
Message-ID: <E1Q0CPA-0007Wg-Og@ra.coresystems.de>

Author: oxygene
Date: Thu Mar 17 13:34:15 2011
New Revision: 6451
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6451

Log:
Fix power_on_after_fail handling on AMD SB600

Bit 0 of pm reg#74 have to be set turn on system after power resumes.
See '42661_sb600_rrg_nda_3.02.pdf' (or '46155_sb600_rrg_pub_3.03.pdf')
for details, look for 'PwrFailShadow'.

[Patrick: I didn't include the get_options reorganization as get_option
doesn't overwrite "on" if power_on_after_fail isn't found in CMOS.
Style changes were also left out.]

Signed-off-by: Josef Kellermann <seppk at arcor.de>
Acked-by: Patrick Georgi <patrick.georgi at secunet.com>

Modified:
   trunk/src/southbridge/amd/sb600/sm.c

Modified: trunk/src/southbridge/amd/sb600/sm.c
==============================================================================
--- trunk/src/southbridge/amd/sb600/sm.c	Thu Mar 17 13:20:04 2011	(r6450)
+++ trunk/src/southbridge/amd/sb600/sm.c	Thu Mar 17 13:34:15 2011	(r6451)
@@ -94,7 +94,7 @@
 	byte = pm_ioread(0x74);
 	byte &= ~0x03;
 	if (on) {
-		byte |= 2;
+		byte |= 1 << 0;
 	}
 	byte |= 1 << 2;
 	pm_iowrite(0x74, byte);



From Patrick.Georgi at secunet.com  Thu Mar 17 14:08:34 2011
From: Patrick.Georgi at secunet.com (Georgi, Patrick)
Date: Thu, 17 Mar 2011 14:08:34 +0100
Subject: [coreboot] [PATCH]Filo: rework device string parser
Message-ID: <1300367314.2421.11.camel@linux-0a8x.site>

Hi,

attached patches rework the device string parser in FILO so it should be
easier to understand, and adds some more ways to specify
devices/partitions. Specifically:

2-refactor-dev-parsing.diff:
- copy_path_to_filo_bootline() erases the target location instead
  of expecting the callers to do so
- callers of copy_path_to_filo_bootline() don't erase the target
  variables themselves.

This fixes an issue where the function is called without the variable
being erased. I couldn't think of any plausible scenario in which the
old behaviour is desirable.


3-rewrite-drive-specification-parser.diff:
- copy_path_to_filo_bootline is rewritten for clarity.
- copy_path_to_filo_bootline now supports @address syntax in grub-style
  device names.
- use strtoul instead of a custom number parser (theoretically allows
  for >99 disks/partitions, but I guess we'll never have to work with
  that)

The old implementation of the function was a mess of hidden state
dragged around in incidental configuration in variables. The current
code flow should be easier to follow.

4-handle-partition-only-changes.diff:
- Allow new syntax "(,N)" (grub-style) or "N:" (filo/linux-style) which
  simply switches to a different partition on the current device.

Use case: one partition with filo.lst, another with kernels, filo.lst
references the kernel as "5:/boot/kernel" and it works no matter the
drive name.

Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

-- 
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com 

Sitz: Kronprinzenstra?e 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

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From anish.mailing.list at gmail.com  Thu Mar 17 19:36:35 2011
From: anish.mailing.list at gmail.com (Anish Patel)
Date: Thu, 17 Mar 2011 14:36:35 -0400
Subject: [coreboot] intel atom + us15
In-Reply-To: <AANLkTik6U6SfEdoARSk2QNDULoO52YGjRqUOj-fJYZ2N@mail.gmail.com>
References: <4D7E6A28.3040002@gmail.com>	<4D7E6FA1.2080700@gmail.com>	<20110315220148.GA631@coreboot.org>
	<AANLkTik6U6SfEdoARSk2QNDULoO52YGjRqUOj-fJYZ2N@mail.gmail.com>
Message-ID: <4D8254B3.80500@gmail.com>

This solves the problem, thanks Karl!


Anish

On 03/16/11 15:44, Karl-Heinz Nirschl wrote:
> Hi,
> i think the following patch should do the trick:
>
>
> ---
> Index: src/southbridge/intel/sch/Makefile.inc
> ===================================================================
> --- src/southbridge/intel/sch/Makefile.inc	(Revision 6439)
> +++ src/southbridge/intel/sch/Makefile.inc	(Arbeitskopie)
> @@ -37,6 +37,6 @@
>
>   # We don't ship that, but booting without it is bound to fail
>   cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin
> -cmc.bin-file := $(CONFIG_CMC_FILE)
> +cmc.bin-file := $(call strip_quotes,$(CONFIG_CMC_FILE))
>   cmc.bin-type := 0xaa
>   cmc.bin-position := 0xfffd0000
> ---
>
>
> best regards,
>
>
>
>
> 2011/3/15 Stefan Reinauer<stefan.reinauer at coreboot.org>:
>> * Anish Patel<anish.mailing.list at gmail.com>  [110314 20:42]:
>>> On 03/14/11 15:19, Anish Patel wrote:
>>>> Hi All,
>>>>     I am trying to get coreboot running on my PC/104+ atom  board.
>>>> I think i have everything pretty much good to go, except for one
>>>> problem.
>>>> When i try to build, it says it can't find my cmc.bin file, which
>>>> i have extracted from the factory bios and placed in many
>>>> different locations inside the coreboot build tree.  As well as
>>>> tell coreboot the location of the cmc.bin file, yet everytime i
>>>> build i get this error.
>>>>
>>>>
>>>>     GEN        bootblock/ldscript.ld
>>>>     LINK       bootblock.elf
>>>>     OBJCOPY    coreboot.bootblock
>>>> make: *** No rule to make target `"cmc.bin"', needed by
>>>> `build/coreboot.pre1'.  Stop.
>>>>
>>>>
>>>> any hints on where to place this file would be greatly
>>>> appreciared.  as a note, i have made a oprom directory in the
>>>> coreboot root.  this place hold my vgabios.bin which the coreboot
>>>> build system find an links properly.
>>>>
>>>>
>>>> thanks
>>>> anish
>>>>
>>> i have found the problem
>>> reverting back the the Makefile.inc from r6199 for the sch fixed the
>>> problem.
>> Which Makefile.inc. Can you please send a patch?
>>
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>




From marcj303 at gmail.com  Thu Mar 17 23:20:24 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 17 Mar 2011 16:20:24 -0600
Subject: [coreboot] A patch to perform some AMD Agesa cleanup
In-Reply-To: <276EC11373289744A112A8FE6675506701A3C9F822@SAUSEXMBP01.amd.com>
References: <276EC11373289744A112A8FE6675506701A3C9F822@SAUSEXMBP01.amd.com>
Message-ID: <AANLkTinOjV2UyMYxDagzc6neSbxgwf-KfDKpfKSQzKWm@mail.gmail.com>

On Thu, Mar 17, 2011 at 3:21 PM, Vibrans, Frank <Frank.Vibrans at amd.com> wrote:
> This patch performs some cleanup and file shrinkage of the AMD Agesa code.
>
>
>
> Signed-off-by Frank Vibrans <frank.vibrans at amd.com>
>

Acked-by: Marc Jones <marcj303 at gmail.com>

r6452



-- 
http://se-eng.com



From svn at coreboot.org  Thu Mar 17 23:46:14 2011
From: svn at coreboot.org (repository service)
Date: Thu, 17 Mar 2011 23:46:14 +0100
Subject: [coreboot] build service results for r6452
Message-ID: <E1Q0LxO-0007HS-Va@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "mjones" checked in revision 6452 to
the coreboot repository. This caused the following 
changes:

Change Log:
Perform cleanup and file shrinkage of the AMD AGESA code.

Signed-off-by: Frank.Vibrans <frank.vibrans at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Build Log:
Compilation of amd:inagua has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6452&device=inagua&vendor=amd&num=2
Compilation of amd:persimmon has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6452&device=persimmon&vendor=amd&num=2
Compilation of asrock:e350m1 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6452&device=e350m1&vendor=asrock&num=2


If something broke during this checkin please be a pain 
in mjones's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Fri Mar 18 00:14:24 2011
From: svn at coreboot.org (repository service)
Date: Fri, 18 Mar 2011 00:14:24 +0100
Subject: [coreboot] [commit] r6453 - in trunk/src:
	cpu/amd/agesa_wrapper/family14 vendorcode/amd/agesa/Include
Message-ID: <E1Q0MOe-0001Ns-Lp@ra.coresystems.de>

Author: mjones
Date: Fri Mar 18 00:14:24 2011
New Revision: 6453
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6453

Log:
Fix breaking the build after removing files in tthe previous checkin. 

Signed-off-by: Marc Jones <marcj303 at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/cpu/amd/agesa_wrapper/family14/Makefile.inc
   trunk/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h
   trunk/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h

Modified: trunk/src/cpu/amd/agesa_wrapper/family14/Makefile.inc
==============================================================================
--- trunk/src/cpu/amd/agesa_wrapper/family14/Makefile.inc	Thu Mar 17 23:19:45 2011	(r6452)
+++ trunk/src/cpu/amd/agesa_wrapper/family14/Makefile.inc	Fri Mar 18 00:14:24 2011	(r6453)
@@ -66,9 +66,6 @@
 agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c
 agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
 agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
-agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B_Unenc.c
-agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A_Unenc.c
-agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000025_Unenc.c
 agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c
 agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
 agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c

Modified: trunk/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h	Thu Mar 17 23:19:45 2011	(r6452)
+++ trunk/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h	Fri Mar 18 00:14:24 2011	(r6453)
@@ -324,11 +324,8 @@
 
     #if GET_PATCHES == TRUE
       #define F14_ON_UCODE_0B
-      #define F14_ON_UCODE_0B_UNENC
       #define F14_ON_UCODE_1A
-      #define F14_ON_UCODE_1A_UNENC
       #define F14_ON_UCODE_25
-      #define F14_ON_UCODE_25_UNENC
 
       // If a patch is required for recovery mode to function properly, add a
       // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
@@ -338,35 +335,20 @@
           #undef F14_ON_UCODE_0B
           #define F14_ON_UCODE_0B &CpuF14MicrocodePatch0500000B,
 
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B_Unenc;
-          #undef F14_ON_UCODE_0B_UNENC
-          #define F14_ON_UCODE_0B_UNENC &CpuF14MicrocodePatch0500000B_Unenc,
-
           extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A;
           #undef F14_ON_UCODE_1A
           #define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A,
-
-          extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A_Unenc;
-          #undef F14_ON_UCODE_1A_UNENC
-          #define F14_ON_UCODE_1A_UNENC &CpuF14MicrocodePatch0500001A_Unenc,
         #endif
         extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025;
         #undef F14_ON_UCODE_25
         #define F14_ON_UCODE_25 &CpuF14MicrocodePatch05000025,
-
-        extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025_Unenc;
-        #undef F14_ON_UCODE_25_UNENC
-        #define F14_ON_UCODE_25_UNENC &CpuF14MicrocodePatch05000025_Unenc,
       #endif
 
       CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[] =
       {
         F14_ON_UCODE_0B
-        F14_ON_UCODE_0B_UNENC
         F14_ON_UCODE_1A
-        F14_ON_UCODE_1A_UNENC
         F14_ON_UCODE_25
-        F14_ON_UCODE_25_UNENC
         NULL
       };
 

Modified: trunk/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h
==============================================================================
--- trunk/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h	Thu Mar 17 23:19:45 2011	(r6452)
+++ trunk/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h	Fri Mar 18 00:14:24 2011	(r6453)
@@ -388,24 +388,18 @@
 
     #if GET_PATCHES == TRUE
       #define F15_OR_UCODE_09
-      #define F15_OR_UCODE_09_UNENC
 
       #if AGESA_ENTRY_INIT_EARLY == TRUE
         #if OPTION_EARLY_SAMPLES == TRUE
           extern  CONST MICROCODE_PATCHES_4K ROMDATA CpuF15OrMicrocodePatch06000009;
           #undef F15_OR_UCODE_09
           #define F15_OR_UCODE_09 &CpuF15OrMicrocodePatch06000009,
-
-          extern  CONST MICROCODE_PATCHES_4K ROMDATA CpuF15OrMicrocodePatch06000009_Unenc;
-          #undef F15_OR_UCODE_09_UNENC
-          #define F15_OR_UCODE_09_UNENC &CpuF15OrMicrocodePatch06000009_Unenc,
         #endif
       #endif
 
       CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15OrMicroCodePatchArray[] =
       {
         F15_OR_UCODE_09
-        F15_OR_UCODE_09_UNENC
         NULL
       };
 



From svn at coreboot.org  Fri Mar 18 00:42:52 2011
From: svn at coreboot.org (repository service)
Date: Fri, 18 Mar 2011 00:42:52 +0100
Subject: [coreboot] build service results for r6453
Message-ID: <E1Q0MqC-0003tu-DG@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "mjones" checked in revision 6453 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix breaking the build after removing files in tthe previous checkin.

Signed-off-by: Marc Jones <marcj303 at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Build Log:
Compilation of amd:inagua has been fixed
Compilation of amd:persimmon has been fixed
Compilation of asrock:e350m1 has been fixed


If something broke during this checkin please be a pain 
in mjones's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From marcj303 at gmail.com  Fri Mar 18 21:05:09 2011
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 18 Mar 2011 14:05:09 -0600
Subject: [coreboot] coreboot GSoC 2011
Message-ID: <AANLkTimCFOYts42aY51J4t-mUoTbqOYMG==k+pWHM9mr@mail.gmail.com>

I'm happy to announce that coreboot has been accepted to participate
in GSoC 2011. Please forward this information to all prospective GSoC
student participants. Note, the coreboot project acts as an umbrella
for coreboot related projects like flashrom and other payloads.

   http://www.google-melange.com/gsoc/org/show/google/gsoc2011/coreboot



Prospective students and mentors should visit the coreboot wiki for
complete information.

   http://www.coreboot.org/GSoC



Please feel free to update the wiki or email the coreboot list if you
have additional project ideas or other comments.


Regards,

Marc

-- 
http://se-eng.com



From svn at coreboot.org  Fri Mar 18 23:08:39 2011
From: svn at coreboot.org (repository service)
Date: Fri, 18 Mar 2011 23:08:39 +0100
Subject: [coreboot] [commit] r6454 - in trunk/util: inteltool nvramtool
	nvramtool/accessors superiotool
Message-ID: <E1Q0hqZ-0001oP-NV@ra.coresystems.de>

Author: stepan
Date: Fri Mar 18 23:08:39 2011
New Revision: 6454
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6454

Log:
DirectHW fixes for coreboot utilities

See http://www.coreboot.org/DirectHW for more information

Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Modified:
   trunk/util/inteltool/Makefile
   trunk/util/inteltool/inteltool.c
   trunk/util/inteltool/inteltool.h
   trunk/util/nvramtool/Makefile
   trunk/util/nvramtool/accessors/cmos-hw-unix.c
   trunk/util/superiotool/Makefile
   trunk/util/superiotool/superiotool.h

Modified: trunk/util/inteltool/Makefile
==============================================================================
--- trunk/util/inteltool/Makefile	Fri Mar 18 00:14:24 2011	(r6453)
+++ trunk/util/inteltool/Makefile	Fri Mar 18 23:08:39 2011	(r6454)
@@ -31,7 +31,7 @@
 
 OS_ARCH	= $(shell uname)
 ifeq ($(OS_ARCH), Darwin)
-LDFLAGS = -framework DirectIO -lpci -lz
+LDFLAGS = -framework DirectHW -lpci -lz
 endif
 ifeq ($(OS_ARCH), FreeBSD)
 CFLAGS += -I/usr/local/include

Modified: trunk/util/inteltool/inteltool.c
==============================================================================
--- trunk/util/inteltool/inteltool.c	Fri Mar 18 00:14:24 2011	(r6453)
+++ trunk/util/inteltool/inteltool.c	Fri Mar 18 23:08:39 2011	(r6454)
@@ -85,7 +85,7 @@
 #ifndef __DARWIN__
 static int fd_mem;
 
-void *map_physical(unsigned long phys_addr, size_t len)
+void *map_physical(uint64_t phys_addr, size_t len)
 {
 	void *virt_addr;
 

Modified: trunk/util/inteltool/inteltool.h
===============================