[coreboot] how to deal with large romstage size?
buurin at gmail.com
Wed Mar 2 16:28:50 CET 2011
>> I think you need to make the complete flash visible in a southbridge bootblock.c
>> It would help if you could publish your current code so we can do better than asking the crystal ball for answers ;)
> it's based on D945gclf, but MRC is under NDA, :-(
It's the Memory Reference Code, for those who don't know.
You probably can place a banner to be sent via serial port where MRC
is about to come into play ie. raminit is about to start, and replace
the MRC in the review copy you post up here with some code to generate
110k of dead beefs. :-D When we try it and the banner shows, that
would be a good sign.
AMD wins a point in supporting open source, again. -_-
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